.gitignore: exclude logo generated file

Correct the rule in .gitignore to skip u_boot_logo.bmp.S artifact which
is generated for any board with CONFIG_VIDEO_LOGO enabled.

Also, correct the stale u_boot_logo name in CLEAN_FILES in top-level
Makefile.

Signed-off-by: Denis Mukhin <dmukhin@ford.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

.gitignore

@@ -80,7 +80,7 @@ fit-dtb.blob*
 /*imx8mimage*
 /*imx8mcst*
 /*rcar4-sa0*
-/drivers/video/u_boot_logo.S
+/drivers/video/u_boot_logo.bmp.S
 /test/fdt_overlay/test-fdt-overlay-stacked.dtbo.S
 /test/fdt_overlay/test-fdt-overlay.dtbo.S
 capsule_esl_file

.gitlab-ci-sage-lab.yml

@@ -153,20 +153,13 @@ Raspberry Pi 4 (rpi_arm64):
     LABGRID_EXPORTER: "sage-exporter-rpi4-1"
     LG_PLACE: "rpi4-1"
     TEST_PY_BD: "rpi_arm64"
-    OVERRIDE: "-a UNIT_TEST -a ~CMD_EFIDEBUG -a CMD_BOOTMENU -a CMD_LOG -a ~CMD_BOOTEFI_SELFTEST -a CMD_TFTPPUT -a FIT -a FIT_SIGNATURE -a FIT_BEST_MATCH -a SYS_BOOTM_LEN=0x4000000 -a BOOTSTAGE -a BOOTSTAGE_STASH -a CMD_BOOTSTAGE -a BOOTSTAGE_STASH_ADDR=0x02400000"
-
-Raspberry Pi 4 (rpi_arm64, lwIP):
-  <<: *sage_lab_dfn
-  needs: [ "Raspberry Pi 4 (rpi_arm64)" ]
-  variables:
-    LABGRID_EXPORTER: "sage-exporter-rpi4-1"
-    LG_PLACE: "rpi4-1"
-    TEST_PY_BD: "rpi_arm64"
-    OVERRIDE: "-a UNIT_TEST -a ~CMD_EFIDEBUG -a CMD_BOOTMENU -a CMD_LOG -a ~CMD_BOOTEFI_SELFTEST -a FIT -a FIT_SIGNATURE -a FIT_BEST_MATCH -a SYS_BOOTM_LEN=0x4000000 -a BOOTSTAGE -a BOOTSTAGE_STASH -a CMD_BOOTSTAGE -a BOOTSTAGE_STASH_ADDR=0x02400000 -a NET_LWIP"
+    # DHCP is not being run first, needs to be investigated.
+    TEST_PY_TEST_SPEC: "not test_efi_helloworld_net_http"
+    OVERRIDE: "-a UNIT_TEST -a ~CMD_EFIDEBUG -a CMD_BOOTMENU -a CMD_LOG -a ~CMD_BOOTEFI_SELFTEST -a FIT -a FIT_SIGNATURE -a FIT_BEST_MATCH -a SYS_BOOTM_LEN=0x4000000 -a BOOTSTAGE -a BOOTSTAGE_STASH -a CMD_BOOTSTAGE -a BOOTSTAGE_STASH_ADDR=0x02400000"
 
 Raspberry Pi 4 (rpi_4_32b):
   <<: *sage_lab_dfn
-  needs: [ "Raspberry Pi 4 (rpi_arm64, lwIP)" ]
+  needs: [ "Raspberry Pi 4 (rpi_arm64)" ]
   variables:
     LABGRID_EXPORTER: "sage-exporter-rpi4-1"
     LG_PLACE: "rpi4-1"
@@ -197,20 +190,13 @@ Raspberry Pi 3 (rpi_arm64):
     LABGRID_EXPORTER: "sage-exporter-rpi3-1"
     LG_PLACE: "rpi3-1"
     TEST_PY_BD: "rpi_arm64"
-    OVERRIDE: "-a UNIT_TEST -a ~CMD_EFIDEBUG -a CMD_BOOTMENU -a CMD_LOG -a ~CMD_BOOTEFI_SELFTEST -a CMD_TFTPPUT -a FIT -a FIT_SIGNATURE -a FIT_BEST_MATCH -a SYS_BOOTM_LEN=0x4000000 -a BOOTSTAGE -a BOOTSTAGE_STASH -a CMD_BOOTSTAGE -a BOOTSTAGE_STASH_ADDR=0x02400000"
-
-Raspberry Pi 3 (rpi_arm64, lwIP):
-  <<: *sage_lab_dfn
-  needs: [ "Raspberry Pi 3 (rpi_arm64)" ]
-  variables:
-    LABGRID_EXPORTER: "sage-exporter-rpi3-1"
-    LG_PLACE: "rpi3-1"
-    TEST_PY_BD: "rpi_arm64"
-    OVERRIDE: "-a UNIT_TEST -a ~CMD_EFIDEBUG -a CMD_BOOTMENU -a CMD_LOG -a ~CMD_BOOTEFI_SELFTEST -a FIT -a FIT_SIGNATURE -a FIT_BEST_MATCH -a SYS_BOOTM_LEN=0x4000000 -a BOOTSTAGE -a BOOTSTAGE_STASH -a CMD_BOOTSTAGE -a BOOTSTAGE_STASH_ADDR=0x02400000 -a NET_LWIP"
+    # DHCP is not being run first, needs to be investigated.
+    TEST_PY_TEST_SPEC: "not test_efi_helloworld_net_http"
+    OVERRIDE: "-a UNIT_TEST -a ~CMD_EFIDEBUG -a CMD_BOOTMENU -a CMD_LOG -a ~CMD_BOOTEFI_SELFTEST -a FIT -a FIT_SIGNATURE -a FIT_BEST_MATCH -a SYS_BOOTM_LEN=0x4000000 -a BOOTSTAGE -a BOOTSTAGE_STASH -a CMD_BOOTSTAGE -a BOOTSTAGE_STASH_ADDR=0x02400000"
 
 Raspberry Pi 3 (rpi_3_32b):
   <<: *sage_lab_dfn
-  needs: [ "Raspberry Pi 3 (rpi_arm64, lwIP)" ]
+  needs: [ "Raspberry Pi 3 (rpi_arm64)" ]
   variables:
     LABGRID_EXPORTER: "sage-exporter-rpi3-1"
     LG_PLACE: "rpi3-1"

MAINTAINERS

@@ -317,13 +317,26 @@ M:	Fabio Estevam <festevam@gmail.com>
 R:	NXP i.MX U-Boot Team <uboot-imx@nxp.com>
 S:	Maintained
 T:	git https://source.denx.de/u-boot/custodians/u-boot-imx.git
-N:	imx
-N:	mxc
-N:	nxp
-N:	vf610
+F:	arch/Kconfig.nxp
 F:	arch/arm/cpu/arm1136/mx*/
 F:	arch/arm/cpu/arm926ejs/mx*/
+F:	arch/arm/cpu/armv7/vf610/
+F:	arch/arm/dts/*imx*
+F:	arch/arm/mach-imx/
+F:	arch/arm/include/asm/arch-imx*/
 F:	arch/arm/include/asm/arch-mx*/
+F:	arch/arm/include/asm/arch-vf610/
+F:	arch/arm/include/asm/mach-imx/
+F:	board/nxp/*mx*/
+F:	board/nxp/common/
+F:	common/spl/spl_imx_container.c
+F:	doc/board/nxp/
+F:	doc/imx/
+F:	drivers/mailbox/imx-mailbox.c
+F:	drivers/remoteproc/imx*
+F:	drivers/serial/serial_mxc.c
+F:	drivers/spi/nxp_xspi.c
+F:	include/imx_container.h
 
 ARM HISILICON
 M:	Peter Griffin <peter.griffin@linaro.org>

Makefile

@@ -920,7 +920,7 @@ endif
 ifdef CONFIG_CC_OPTIMIZE_FOR_SIZE
 KBUILD_CFLAGS	+= -Os
 else ifdef CONFIG_CC_OPTIMIZE_FOR_DEBUG
--KBUILD_CFLAGS  += -Og
+KBUILD_CFLAGS  += -Og
 # Avoid false positives -Wmaybe-uninitialized
 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78394
 KBUILD_CFLAGS  += -Wno-maybe-uninitialized
@@ -2544,7 +2544,7 @@ CLEAN_FILES  += $(MODVERDIR) \
 			$(filter-out include, $(shell ls -1 $d 2>/dev/null))))
 
 CLEAN_FILES += include/autoconf.mk* include/bmp_logo.h include/bmp_logo_data.h \
-	       include/config.h include/generated/env.* drivers/video/u_boot_logo.S \
+	       include/config.h include/generated/env.* drivers/video/u_boot_logo.bmp.S \
 	       tools/version.h u-boot* MLO* SPL System.map fit-dtb.blob* \
 	       u-boot-ivt.img.log u-boot-dtb.imx.log SPL.log u-boot.imx.log \
 	       lpc32xx-* bl31.c bl31.elf bl31_*.bin image.map tispl.bin* \

README

@@ -707,7 +707,7 @@ The following options need to be configured:
 		The same can be accomplished in a more flexible way
 		for any variable by configuring the type of access
 		to allow for those variables in the ".flags" variable
-		or by setting CONFIG_ENV_FLAGS_LIST_STATIC.
+		or define CFG_ENV_FLAGS_LIST_STATIC.
 
 - Protected RAM:
 		CFG_PRAM
@@ -941,6 +941,173 @@ typically in board_init_f() and board_init_r().
 - CONFIG_BOARD_EARLY_INIT_R: Call board_early_init_r()
 - CONFIG_BOARD_LATE_INIT: Call board_late_init()
 
+Configuration Settings:
+-----------------------
+
+- CONFIG_SYS_LONGHELP: Defined when you want long help messages included;
+		undefine this when you're short of memory.
+
+- CFG_SYS_HELP_CMD_WIDTH: Defined when you want to override the default
+		width of the commands listed in the 'help' command output.
+
+- CONFIG_SYS_PROMPT:	This is what U-Boot prints on the console to
+		prompt for user input.
+
+- CFG_SYS_BAUDRATE_TABLE:
+		List of legal baudrate settings for this board.
+
+- CFG_SYS_MEM_RESERVE_SECURE
+		Only implemented for ARMv8 for now.
+		If defined, the size of CFG_SYS_MEM_RESERVE_SECURE memory
+		is substracted from total RAM and won't be reported to OS.
+		This memory can be used as secure memory. A variable
+		gd->arch.secure_ram is used to track the location. In systems
+		the RAM base is not zero, or RAM is divided into banks,
+		this variable needs to be recalcuated to get the address.
+
+- CFG_SYS_SDRAM_BASE:
+		Physical start address of SDRAM. _Must_ be 0 here.
+
+- CFG_SYS_FLASH_BASE:
+		Physical start address of Flash memory.
+
+- CONFIG_SYS_MALLOC_LEN:
+		Size of DRAM reserved for malloc() use.
+
+- CFG_SYS_BOOTMAPSZ:
+		Maximum size of memory mapped by the startup code of
+		the Linux kernel; all data that must be processed by
+		the Linux kernel (bd_info, boot arguments, FDT blob if
+		used) must be put below this limit, unless "bootm_low"
+		environment variable is defined and non-zero. In such case
+		all data for the Linux kernel must be between "bootm_low"
+		and "bootm_low" + CFG_SYS_BOOTMAPSZ.	 The environment
+		variable "bootm_mapsize" will override the value of
+		CFG_SYS_BOOTMAPSZ.  If CFG_SYS_BOOTMAPSZ is undefined,
+		then the value in "bootm_size" will be used instead.
+
+- CONFIG_SYS_BOOT_GET_CMDLINE:
+		Enables allocating and saving kernel cmdline in space between
+		"bootm_low" and "bootm_low" + BOOTMAPSZ.
+
+- CONFIG_SYS_BOOT_GET_KBD:
+		Enables allocating and saving a kernel copy of the bd_info in
+		space between "bootm_low" and "bootm_low" + BOOTMAPSZ.
+
+- CONFIG_SYS_FLASH_PROTECTION
+		If defined, hardware flash sectors protection is used
+		instead of U-Boot software protection.
+
+- CONFIG_SYS_FLASH_CFI:
+		Define if the flash driver uses extra elements in the
+		common flash structure for storing flash geometry.
+
+- CONFIG_FLASH_CFI_DRIVER
+		This option also enables the building of the cfi_flash driver
+		in the drivers directory
+
+- CONFIG_FLASH_CFI_MTD
+		This option enables the building of the cfi_mtd driver
+		in the drivers directory. The driver exports CFI flash
+		to the MTD layer.
+
+- CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+		Use buffered writes to flash.
+
+- CONFIG_ENV_FLAGS_LIST_DEFAULT
+- CFG_ENV_FLAGS_LIST_STATIC
+	Enable validation of the values given to environment variables when
+	calling env set.  Variables can be restricted to only decimal,
+	hexadecimal, or boolean.  If CONFIG_CMD_NET is also defined,
+	the variables can also be restricted to IP address or MAC address.
+
+	The format of the list is:
+		type_attribute = [s|d|x|b|i|m]
+		access_attribute = [a|r|o|c]
+		attributes = type_attribute[access_attribute]
+		entry = variable_name[:attributes]
+		list = entry[,list]
+
+	The type attributes are:
+		s - String (default)
+		d - Decimal
+		x - Hexadecimal
+		b - Boolean ([1yYtT|0nNfF])
+		i - IP address
+		m - MAC address
+
+	The access attributes are:
+		a - Any (default)
+		r - Read-only
+		o - Write-once
+		c - Change-default
+
+	- CONFIG_ENV_FLAGS_LIST_DEFAULT
+		Define this to a list (string) to define the ".flags"
+		environment variable in the default or embedded environment.
+
+	- CFG_ENV_FLAGS_LIST_STATIC
+		Define this to a list (string) to define validation that
+		should be done if an entry is not found in the ".flags"
+		environment variable.  To override a setting in the static
+		list, simply add an entry for the same variable name to the
+		".flags" variable.
+
+	If CONFIG_REGEX is defined, the variable_name above is evaluated as a
+	regular expression. This allows multiple variables to define the same
+	flags without explicitly listing them for each variable.
+
+The following definitions that deal with the placement and management
+of environment data (variable area); in general, we support the
+following configurations:
+
+BE CAREFUL! The first access to the environment happens quite early
+in U-Boot initialization (when we try to get the setting of for the
+console baudrate). You *MUST* have mapped your NVRAM area then, or
+U-Boot will hang.
+
+Please note that even with NVRAM we still use a copy of the
+environment in RAM: we could work on NVRAM directly, but we want to
+keep settings there always unmodified except somebody uses "saveenv"
+to save the current settings.
+
+BE CAREFUL! For some special cases, the local device can not use
+"saveenv" command. For example, the local device will get the
+environment stored in a remote NOR flash by SRIO or PCIE link,
+but it can not erase, write this NOR flash by SRIO or PCIE interface.
+
+- CONFIG_NAND_ENV_DST
+
+	Defines address in RAM to which the nand_spl code should copy the
+	environment. If redundant environment is used, it will be copied to
+	CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE.
+
+Please note that the environment is read-only until the monitor
+has been relocated to RAM and a RAM copy of the environment has been
+created; also, when using EEPROM you will have to use env_get_f()
+until then to read environment variables.
+
+The environment is protected by a CRC32 checksum. Before the monitor
+is relocated into RAM, as a result of a bad CRC you will be working
+with the compiled-in default environment - *silently*!!! [This is
+necessary, because the first environment variable we need is the
+"baudrate" setting for the console - if we have a bad CRC, we don't
+have any device yet where we could complain.]
+
+Note: once the monitor has been relocated, then it will complain if
+the default environment is used; a new CRC is computed as soon as you
+use the "saveenv" command to store a valid environment.
+
+- CONFIG_DISPLAY_BOARDINFO
+		Display information about the board that U-Boot is running on
+		when U-Boot starts up. The board function checkboard() is called
+		to do this.
+
+- CONFIG_DISPLAY_BOARDINFO_LATE
+		Similar to the previous option, but display this information
+		later, once stdio is running and output goes to the LCD, if
+		present.
+
 Low Level (hardware related) configuration options:
 ---------------------------------------------------
 

arch/arm/cpu/u-boot.lds

@@ -96,7 +96,7 @@ SECTIONS
 	{
 		KEEP(*(.__secure_stack_start))
 
-		/* Skip addresses for stack */
+		/* Skip addreses for stack */
 		. = . + CONFIG_ARMV7_PSCI_NR_CPUS * ARM_PSCI_STACK_SIZE;
 
 		/* Align end of stack section to page boundary */

arch/arm/dts/Makefile

@@ -872,6 +872,8 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
 	imx8mm-mx8menlo.dtb \
 	imx8mm-phg.dtb \
 	imx8mq-cm.dtb \
+	imx8mq-mnt-reform2.dtb \
+	imx8mq-phanbell.dtb \
 	imx8mp-data-modul-edm-sbc.dtb \
 	imx8mp-dhcom-som-overlay-rev100.dtbo \
 	imx8mp-dhcom-som-overlay-eth1xfast.dtbo \
@@ -881,7 +883,10 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
 	imx8mp-dhcom-pdk3-overlay-rev100.dtbo \
 	imx8mp-dhcom-picoitx.dtb \
 	imx8mp-icore-mx8mp-edimm2.2.dtb \
-	imx8mp-msc-sm2s.dtb
+	imx8mp-msc-sm2s.dtb \
+	imx8mq-pico-pi.dtb \
+	imx8mq-kontron-pitx-imx8m.dtb \
+	imx8mq-librem5-r4.dtb
 
 dtb-$(CONFIG_ARCH_IMX9) += \
 	imx93-11x11-frdm.dtb \
@@ -894,6 +899,9 @@ dtb-$(CONFIG_RZA1) += \
 	r7s72100-genmai.dtb \
 	r7s72100-gr-peach.dtb
 
+dtb-$(CONFIG_RCAR_GEN3) += \
+	r8a779md-geist.dtb
+
 dtb-$(CONFIG_RCAR_GEN5) += \
 	r8a78000-ironhide-cm33.dtb
 

arch/arm/dts/imx8mm-beacon-baseboard.dtsi

@@ -0,0 +1,437 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2020 Compass Electronics Group, LLC
+ */
+
+#include <dt-bindings/phy/phy-imx8-pcie.h>
+
+/ {
+	leds {
+		compatible = "gpio-leds";
+
+		led0 {
+			label = "gen_led0";
+			gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+
+		led1 {
+			label = "gen_led1";
+			gpios = <&pca6416_1 5 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+
+		led2 {
+			label = "gen_led2";
+			gpios = <&pca6416_1 6 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+
+		led3 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_led3>;
+			label = "heartbeat";
+			gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "heartbeat";
+		};
+	};
+
+	pcie0_refclk: pcie0-refclk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <100000000>;
+	};
+
+	pcie0_refclk_gated:  pcie0-refclk-gated {
+		compatible = "gpio-gate-clock";
+		clocks = <&pcie0_refclk>;
+		#clock-cells = <0>;
+		enable-gpios = <&pca6416_1 2 GPIO_ACTIVE_LOW>;
+	};
+
+	reg_audio: regulator-audio {
+		compatible = "regulator-fixed";
+		regulator-name = "3v3_aud";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&pca6416_1 11 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	reg_usbotg1: regulator-usbotg1 {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_reg_usb_otg1>;
+		regulator-name = "usb_otg_vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	reg_camera: regulator-camera {
+		compatible = "regulator-fixed";
+		regulator-name = "mipi_pwr";
+		regulator-min-microvolt = <2800000>;
+		regulator-max-microvolt = <2800000>;
+		gpio = <&pca6416_1 0 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		startup-delay-us = <100000>;
+	};
+
+	reg_pcie0: regulator-pcie {
+		compatible = "regulator-fixed";
+		regulator-name = "pci_pwr_en";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		enable-active-high;
+		gpio = <&pca6416_1 1 GPIO_ACTIVE_HIGH>;
+		startup-delay-us = <100000>;
+	};
+
+	reg_usdhc2_vmmc: regulator-usdhc2 {
+		compatible = "regulator-fixed";
+		regulator-name = "VSD_3V3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	sound {
+		compatible = "fsl,imx-audio-wm8962";
+		model = "wm8962-audio";
+		audio-cpu = <&sai3>;
+		audio-codec = <&wm8962>;
+		audio-routing =
+			"Headphone Jack", "HPOUTL",
+			"Headphone Jack", "HPOUTR",
+			"Ext Spk", "SPKOUTL",
+			"Ext Spk", "SPKOUTR",
+			"AMIC", "MICBIAS",
+			"IN3R", "AMIC";
+	};
+};
+
+&csi {
+	status = "okay";
+};
+
+&ecspi2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_espi2>;
+	cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
+	status = "okay";
+
+	eeprom@0 {
+		compatible = "microchip,at25160bn", "atmel,at25";
+		reg = <0>;
+		spi-max-frequency = <5000000>;
+		spi-cpha;
+		spi-cpol;
+		pagesize = <32>;
+		size = <2048>;
+		address-width = <16>;
+	};
+};
+
+&i2c2 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	status = "okay";
+
+	camera@3c {
+		compatible = "ovti,ov5640";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_ov5640>;
+		reg = <0x3c>;
+		clocks = <&clk IMX8MM_CLK_CLKO1>;
+		clock-names = "xclk";
+		assigned-clocks = <&clk IMX8MM_CLK_CLKO1>;
+		assigned-clock-parents = <&clk IMX8MM_CLK_24M>;
+		assigned-clock-rates = <24000000>;
+		AVDD-supply = <&reg_camera>;  /* 2.8v */
+		powerdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+		reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
+
+		port {
+			/* MIPI CSI-2 bus endpoint */
+			ov5640_to_mipi_csi2: endpoint {
+				remote-endpoint = <&imx8mm_mipi_csi_in>;
+				clock-lanes = <0>;
+				data-lanes = <1 2>;
+			};
+		};
+	};
+};
+
+&i2c4 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c4>;
+	status = "okay";
+
+	wm8962: audio-codec@1a {
+		compatible = "wlf,wm8962";
+		reg = <0x1a>;
+		clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
+		DCVDD-supply = <&reg_audio>;
+		DBVDD-supply = <&reg_audio>;
+		AVDD-supply = <&reg_audio>;
+		CPVDD-supply = <&reg_audio>;
+		MICVDD-supply = <&reg_audio>;
+		PLLVDD-supply = <&reg_audio>;
+		SPKVDD1-supply = <&reg_audio>;
+		SPKVDD2-supply = <&reg_audio>;
+		gpio-cfg = <
+			0x0000 /* 0:Default */
+			0x0000 /* 1:Default */
+			0x0000 /* 2:FN_DMICCLK */
+			0x0000 /* 3:Default */
+			0x0000 /* 4:FN_DMICCDAT */
+			0x0000 /* 5:Default */
+		>;
+	};
+
+	pca6416_0: gpio@20 {
+		compatible = "nxp,pcal6416";
+		reg = <0x20>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_pcal6414>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-parent = <&gpio4>;
+		interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	pca6416_1: gpio@21 {
+		compatible = "nxp,pcal6416";
+		reg = <0x21>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-parent = <&gpio4>;
+		interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
+	};
+};
+
+&mipi_csi {
+	status = "okay";
+	ports {
+		port@0 {
+			imx8mm_mipi_csi_in: endpoint {
+				remote-endpoint = <&ov5640_to_mipi_csi2>;
+				data-lanes = <1 2>;
+			};
+		};
+	};
+};
+
+&pcie_phy {
+	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
+	fsl,tx-deemph-gen1 = <0x2d>;
+	fsl,tx-deemph-gen2 = <0xf>;
+	fsl,clkreq-unsupported;
+	clocks = <&pcie0_refclk_gated>;
+	clock-names = "ref";
+	status = "okay";
+};
+
+&pcie0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pcie0>;
+	reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
+	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
+		 <&pcie0_refclk_gated>;
+	clock-names = "pcie", "pcie_aux", "pcie_bus";
+	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
+			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
+	assigned-clock-rates = <10000000>, <250000000>;
+	assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
+				 <&clk IMX8MM_SYS_PLL2_250M>;
+	vpcie-supply = <&reg_pcie0>;
+	status = "okay";
+};
+
+&sai3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_sai3>;
+	assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
+	assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
+	assigned-clock-rates = <24576000>;
+	fsl,sai-mclk-direction-output;
+	status = "okay";
+};
+
+&snvs_pwrkey {
+	status = "okay";
+};
+
+&uart2 { /* console */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart2>;
+	status = "okay";
+};
+
+&uart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart3>;
+	assigned-clocks = <&clk IMX8MM_CLK_UART3>;
+	assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
+	uart-has-rtscts;
+	status = "okay";
+};
+
+&usbotg1 {
+	vbus-supply = <&reg_usbotg1>;
+	disable-over-current;
+	dr_mode = "otg";
+	status = "okay";
+};
+
+&usbotg2 {
+	pinctrl-names = "default";
+	disable-over-current;
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usbphynop2 {
+	reset-gpios = <&pca6416_1 7 GPIO_ACTIVE_HIGH>;
+};
+
+&usdhc2 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
+	bus-width = <4>;
+	vmmc-supply = <&reg_usdhc2_vmmc>;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl_espi2: espi2grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK		0x82
+			MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI		0x82
+			MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO		0x82
+			MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9		0x41
+		>;
+	};
+
+	pinctrl_i2c2: i2c2grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL		0x400001c3
+			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA		0x400001c3
+		>;
+	};
+
+	pinctrl_i2c4: i2c4grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL		0x400001c3
+			MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA		0x400001c3
+		>;
+	};
+
+	pinctrl_led3: led3grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28	0x41
+		>;
+	};
+
+	pinctrl_ov5640: ov5640grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7		0x19
+			MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6		0x19
+			MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1	0x59
+		>;
+	};
+
+	pinctrl_pcal6414: pcal6414-gpiogrp {
+		fsl,pins = <
+			MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27		0x19
+		>;
+	};
+
+	pinctrl_reg_usb_otg1: usbotg1grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29     0x19
+		>;
+	};
+
+	pinctrl_pcie0: pcie0grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21       0x41
+		>;
+	};
+
+	pinctrl_sai3: sai3grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC     0xd6
+			MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK      0xd6
+			MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK        0xd6
+			MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0     0xd6
+			MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0	0xd6
+		>;
+	};
+
+	pinctrl_uart2: uart2grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140
+			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140
+		>;
+	};
+
+	pinctrl_uart3: uart3grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX	0x40
+			MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX	0x40
+			MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B	0x40
+			MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B	0x40
+		>;
+	};
+
+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+		fsl,pins = <
+			MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B	0x41
+			MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
+		>;
+	};
+
+	pinctrl_usdhc2: usdhc2grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK	0x190
+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD	0x1d0
+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0
+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0
+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0
+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0
+			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
+		>;
+	};
+
+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+		fsl,pins = <
+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK	0x194
+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD	0x1d4
+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4
+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4
+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4
+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4
+			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
+		>;
+	};
+
+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+		fsl,pins = <
+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK	0x196
+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD	0x1d6
+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6
+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6
+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6
+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6
+			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
+		>;
+	};
+};

arch/arm/dts/imx8mn-beacon-baseboard.dtsi

@@ -0,0 +1,309 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2020 Compass Electronics Group, LLC
+ */
+
+/ {
+	leds {
+		compatible = "gpio-leds";
+
+		led-0 {
+			label = "gen_led0";
+			gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+
+		led-1 {
+			label = "gen_led1";
+			gpios = <&pca6416_1 5 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+
+		led-2 {
+			label = "gen_led2";
+			gpios = <&pca6416_1 6 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+
+		led-3 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_led3>;
+			label = "heartbeat";
+			gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "heartbeat";
+		};
+	};
+
+	reg_audio: regulator-audio {
+		compatible = "regulator-fixed";
+		regulator-name = "3v3_aud";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&pca6416_1 11 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	reg_usdhc2_vmmc: regulator-usdhc2 {
+		compatible = "regulator-fixed";
+		regulator-name = "vsd_3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	reg_usb_otg_vbus: regulator-usb {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_reg_usb_otg>;
+		regulator-name = "usb_otg_vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	sound {
+		compatible = "fsl,imx-audio-wm8962";
+		model = "wm8962-audio";
+		audio-cpu = <&sai3>;
+		audio-codec = <&wm8962>;
+		audio-routing =
+			"Headphone Jack", "HPOUTL",
+			"Headphone Jack", "HPOUTR",
+			"Ext Spk", "SPKOUTL",
+			"Ext Spk", "SPKOUTR",
+			"AMIC", "MICBIAS",
+			"IN3R", "AMIC";
+	};
+};
+
+&ecspi2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_espi2>;
+	cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
+	status = "okay";
+
+	eeprom@0 {
+		compatible = "microchip,at25160bn", "atmel,at25";
+		reg = <0>;
+		spi-max-frequency = <5000000>;
+		spi-cpha;
+		spi-cpol;
+		pagesize = <32>;
+		size = <2048>;
+		address-width = <16>;
+	};
+};
+
+&i2c4 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c4>;
+	status = "okay";
+
+	pca6416_0: gpio@20 {
+		compatible = "nxp,pcal6416";
+		reg = <0x20>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_pcal6414>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-parent = <&gpio4>;
+		interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	pca6416_1: gpio@21 {
+		compatible = "nxp,pcal6416";
+		reg = <0x21>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-parent = <&gpio4>;
+		interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	wm8962: audio-codec@1a {
+		compatible = "wlf,wm8962";
+		reg = <0x1a>;
+		clocks = <&clk IMX8MN_CLK_SAI3_ROOT>;
+		DCVDD-supply = <&reg_audio>;
+		DBVDD-supply = <&reg_audio>;
+		AVDD-supply = <&reg_audio>;
+		CPVDD-supply = <&reg_audio>;
+		MICVDD-supply = <&reg_audio>;
+		PLLVDD-supply = <&reg_audio>;
+		SPKVDD1-supply = <&reg_audio>;
+		SPKVDD2-supply = <&reg_audio>;
+		gpio-cfg = <
+			0x0000 /* 0:Default */
+			0x0000 /* 1:Default */
+			0x0000 /* 2:FN_DMICCLK */
+			0x0000 /* 3:Default */
+			0x0000 /* 4:FN_DMICCDAT */
+			0x0000 /* 5:Default */
+		>;
+	};
+};
+
+&easrc {
+	fsl,asrc-rate = <48000>;
+	status = "okay";
+};
+
+&sai3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_sai3>;
+	assigned-clocks = <&clk IMX8MN_CLK_SAI3>;
+	assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
+	assigned-clock-rates = <24576000>;
+	fsl,sai-mclk-direction-output;
+	status = "okay";
+};
+
+&snvs_pwrkey {
+	status = "okay";
+};
+
+&uart2 { /* console */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart2>;
+	status = "okay";
+};
+
+&uart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart3>;
+	assigned-clocks = <&clk IMX8MN_CLK_UART3>;
+	assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
+	uart-has-rtscts;
+	status = "okay";
+};
+
+&usbotg1 {
+	vbus-supply = <&reg_usb_otg_vbus>;
+	disable-over-current;
+	dr_mode = "otg";
+	status = "okay";
+};
+
+&usdhc2 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
+	bus-width = <4>;
+	vmmc-supply = <&reg_usdhc2_vmmc>;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl_espi2: espi2grp {
+		fsl,pins = <
+			MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK		0x82
+			MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI		0x82
+			MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO		0x82
+			MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9		0x41
+		>;
+	};
+
+	pinctrl_i2c2: i2c2grp {
+		fsl,pins = <
+			MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL		0x400001c3
+			MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA		0x400001c3
+		>;
+	};
+
+	pinctrl_i2c4: i2c4grp {
+		fsl,pins = <
+			MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL		0x400001c3
+			MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA		0x400001c3
+		>;
+	};
+
+	pinctrl_led3: led3grp {
+		fsl,pins = <
+			MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28	0x41
+		>;
+	};
+
+	pinctrl_pcal6414: pcal6414-gpiogrp {
+		fsl,pins = <
+			MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27		0x19
+		>;
+	};
+
+	pinctrl_reg_usb_otg: reg-otggrp {
+		fsl,pins = <
+			MX8MN_IOMUXC_SAI3_RXC_GPIO4_IO29     0x19
+		>;
+	};
+
+	pinctrl_sai3: sai3grp {
+		fsl,pins = <
+			MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC     0xd6
+			MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK      0xd6
+			MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK        0xd6
+			MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0     0xd6
+			MX8MN_IOMUXC_SAI3_RXD_SAI3_RX_DATA0	0xd6
+		>;
+	};
+
+	pinctrl_uart2: uart2grp {
+		fsl,pins = <
+			MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140
+			MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140
+		>;
+	};
+
+	pinctrl_uart3: uart3grp {
+		fsl,pins = <
+			MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX	0x40
+			MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX	0x40
+			MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B	0x40
+			MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B	0x40
+		>;
+	};
+
+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+		fsl,pins = <
+			MX8MN_IOMUXC_SD2_CD_B_USDHC2_CD_B	0x41
+			MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
+		>;
+	};
+
+	pinctrl_usdhc2: usdhc2grp {
+		fsl,pins = <
+			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK	0x190
+			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD	0x1d0
+			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0
+			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0
+			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0
+			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0
+			MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
+		>;
+	};
+
+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+		fsl,pins = <
+			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK	0x194
+			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD	0x1d4
+			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4
+			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4
+			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4
+			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4
+			MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
+		>;
+	};
+
+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+		fsl,pins = <
+			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK	0x196
+			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD	0x1d6
+			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6
+			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6
+			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6
+			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6
+			MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
+		>;
+	};
+};

arch/arm/dts/imx8mn-evk.dtsi

@@ -0,0 +1,533 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019 NXP
+ */
+
+#include <dt-bindings/usb/pd.h>
+#include "imx8mn.dtsi"
+
+/ {
+	chosen {
+		stdout-path = &uart2;
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_gpio_led>;
+
+		status {
+			label = "yellow:status";
+			gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+	};
+
+	memory@40000000 {
+		device_type = "memory";
+		reg = <0x0 0x40000000 0 0x80000000>;
+	};
+
+	reg_usdhc2_vmmc: regulator-usdhc2 {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
+		regulator-name = "VSD_3V3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	ir-receiver {
+		compatible = "gpio-ir-receiver";
+		gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_ir>;
+		linux,autosuspend-period = <125>;
+	};
+
+	audio_codec_bt_sco: audio-codec-bt-sco {
+		compatible = "linux,bt-sco";
+		#sound-dai-cells = <1>;
+	};
+
+	wm8524: audio-codec {
+		#sound-dai-cells = <0>;
+		compatible = "wlf,wm8524";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_gpio_wlf>;
+		wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
+		clocks = <&clk IMX8MN_CLK_SAI3_ROOT>;
+		clock-names = "mclk";
+	};
+
+	sound-bt-sco {
+		compatible = "simple-audio-card";
+		simple-audio-card,name = "bt-sco-audio";
+		simple-audio-card,format = "dsp_a";
+		simple-audio-card,bitclock-inversion;
+		simple-audio-card,frame-master = <&btcpu>;
+		simple-audio-card,bitclock-master = <&btcpu>;
+
+		btcpu: simple-audio-card,cpu {
+			sound-dai = <&sai2>;
+			dai-tdm-slot-num = <2>;
+			dai-tdm-slot-width = <16>;
+		};
+
+		simple-audio-card,codec {
+			sound-dai = <&audio_codec_bt_sco 1>;
+		};
+	};
+
+	sound-wm8524 {
+		compatible = "fsl,imx-audio-wm8524";
+		model = "wm8524-audio";
+		audio-cpu = <&sai3>;
+		audio-codec = <&wm8524>;
+		audio-asrc = <&easrc>;
+		audio-routing =
+			"Line Out Jack", "LINEVOUTL",
+			"Line Out Jack", "LINEVOUTR";
+	};
+
+	sound-spdif {
+		compatible = "fsl,imx-audio-spdif";
+		model = "imx-spdif";
+		spdif-controller = <&spdif1>;
+		spdif-out;
+		spdif-in;
+	};
+};
+
+&easrc {
+	fsl,asrc-rate = <48000>;
+	status = "okay";
+};
+
+&fec1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec1>;
+	phy-mode = "rgmii-id";
+	phy-handle = <&ethphy0>;
+	fsl,magic-packet;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy@0 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <0>;
+			reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
+			reset-assert-us = <10000>;
+			qca,disable-smarteee;
+			vddio-supply = <&vddio>;
+
+			vddio: vddio-regulator {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+			};
+		};
+	};
+};
+
+&flexspi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexspi>;
+	status = "okay";
+
+	flash0: flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		spi-max-frequency = <166000000>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
+	};
+};
+
+&i2c1 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	status = "okay";
+};
+
+&i2c2 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	status = "okay";
+
+	ptn5110: tcpc@50 {
+		compatible = "nxp,ptn5110";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_typec1>;
+		reg = <0x50>;
+		interrupt-parent = <&gpio2>;
+		interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+		status = "okay";
+
+		port {
+			typec1_dr_sw: endpoint {
+				remote-endpoint = <&usb1_drd_sw>;
+			};
+		};
+
+		typec1_con: connector {
+			compatible = "usb-c-connector";
+			label = "USB-C";
+			power-role = "dual";
+			data-role = "dual";
+			try-power-role = "sink";
+			source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+			sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
+				     PDO_VAR(5000, 20000, 3000)>;
+			op-sink-microwatt = <15000000>;
+			self-powered;
+		};
+	};
+};
+
+&i2c3 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c3>;
+	status = "okay";
+
+	pca6416: gpio@20 {
+		compatible = "ti,tca6416";
+		reg = <0x20>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+};
+
+&sai2 {
+	#sound-dai-cells = <0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_sai2>;
+	assigned-clocks = <&clk IMX8MN_CLK_SAI2>;
+	assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
+	assigned-clock-rates = <24576000>;
+	status = "okay";
+};
+
+&sai3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_sai3>;
+	assigned-clocks = <&clk IMX8MN_CLK_SAI3>;
+	assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
+	assigned-clock-rates = <24576000>;
+	fsl,sai-mclk-direction-output;
+	status = "okay";
+};
+
+&snvs_pwrkey {
+	status = "okay";
+};
+
+&spdif1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_spdif1>;
+	assigned-clocks = <&clk IMX8MN_CLK_SPDIF1>;
+	assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
+	assigned-clock-rates = <24576000>;
+	status = "okay";
+};
+
+&uart2 { /* console */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart2>;
+	status = "okay";
+};
+
+&uart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart3>;
+	assigned-clocks = <&clk IMX8MN_CLK_UART3>;
+	assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
+	uart-has-rtscts;
+	status = "okay";
+};
+
+&usbotg1 {
+	dr_mode = "otg";
+	hnp-disable;
+	srp-disable;
+	adp-disable;
+	usb-role-switch;
+	disable-over-current;
+	samsung,picophy-pre-emp-curr-control = <3>;
+	samsung,picophy-dc-vol-level-adjust = <7>;
+	status = "okay";
+
+	port {
+		usb1_drd_sw: endpoint {
+			remote-endpoint = <&typec1_dr_sw>;
+		};
+	};
+};
+
+&usdhc2 {
+	assigned-clocks = <&clk IMX8MN_CLK_USDHC2>;
+	assigned-clock-rates = <200000000>;
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+	cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
+	bus-width = <4>;
+	vmmc-supply = <&reg_usdhc2_vmmc>;
+	status = "okay";
+};
+
+&usdhc3 {
+	assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
+	assigned-clock-rates = <400000000>;
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc3>;
+	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+
+&wdog1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wdog>;
+	fsl,ext-reset-output;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl_fec1: fec1grp {
+		fsl,pins = <
+			MX8MN_IOMUXC_ENET_MDC_ENET1_MDC		0x3
+			MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO	0x3
+			MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3	0x1f
+			MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2	0x1f
+			MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1	0x1f
+			MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0	0x1f
+			MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3	0x91
+			MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2	0x91
+			MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1	0x91
+			MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0	0x91
+			MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC	0x1f
+			MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC	0x91
+			MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
+			MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
+			MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22	0x19
+		>;
+	};
+
+	pinctrl_flexspi: flexspigrp {
+		fsl,pins = <
+			MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK               0x1c2
+			MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B            0x82
+			MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0           0x82
+			MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1           0x82
+			MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2           0x82
+			MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3           0x82
+		>;
+	};
+
+	pinctrl_gpio_led: gpioledgrp {
+		fsl,pins = <
+			MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16	0x19
+		>;
+	};
+
+	pinctrl_gpio_wlf: gpiowlfgrp {
+		fsl,pins = <
+			MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21	0xd6
+		>;
+	};
+
+	pinctrl_ir: irgrp {
+		fsl,pins = <
+			MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13              0x4f
+		>;
+	};
+
+	pinctrl_i2c1: i2c1grp {
+		fsl,pins = <
+			MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL		0x400001c3
+			MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA		0x400001c3
+		>;
+	};
+
+	pinctrl_i2c2: i2c2grp {
+		fsl,pins = <
+			MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL		0x400001c3
+			MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA		0x400001c3
+		>;
+	};
+
+	pinctrl_i2c3: i2c3grp {
+		fsl,pins = <
+			MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL		0x400001c3
+			MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA		0x400001c3
+		>;
+	};
+
+	pinctrl_pmic: pmicirqgrp {
+		fsl,pins = <
+			MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x141
+		>;
+	};
+
+	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
+		fsl,pins = <
+			MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
+		>;
+	};
+
+	pinctrl_sai2: sai2grp {
+		fsl,pins = <
+			MX8MN_IOMUXC_SAI2_TXC_SAI2_TX_BCLK      0xd6
+			MX8MN_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC     0xd6
+			MX8MN_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0    0xd6
+			MX8MN_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0    0xd6
+		>;
+	};
+
+	pinctrl_sai3: sai3grp {
+		fsl,pins = <
+			MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC     0xd6
+			MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK      0xd6
+			MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK        0xd6
+			MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0     0xd6
+		>;
+	};
+
+	pinctrl_spdif1: spdif1grp {
+		fsl,pins = <
+			MX8MN_IOMUXC_SPDIF_TX_SPDIF1_OUT	0xd6
+			MX8MN_IOMUXC_SPDIF_RX_SPDIF1_IN		0xd6
+		>;
+	};
+
+	pinctrl_typec1: typec1grp {
+		fsl,pins = <
+			MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11	0x159
+		>;
+	};
+
+	pinctrl_uart2: uart2grp {
+		fsl,pins = <
+			MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140
+			MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140
+		>;
+	};
+
+	pinctrl_uart3: uart3grp {
+		fsl,pins = <
+			MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX		0x140
+			MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX		0x140
+			MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B	0x140
+			MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B	0x140
+		>;
+	};
+
+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+		fsl,pins = <
+			MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15	0x1c4
+		>;
+	};
+
+	pinctrl_usdhc2: usdhc2grp {
+		fsl,pins = <
+			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x190
+			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0
+			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0
+			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0
+			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0
+			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0
+			MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
+		>;
+	};
+
+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+		fsl,pins = <
+			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x194
+			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4
+			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4
+			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4
+			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4
+			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4
+			MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
+		>;
+	};
+
+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+		fsl,pins = <
+			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x196
+			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6
+			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6
+			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6
+			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6
+			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6
+			MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
+		>;
+	};
+
+	pinctrl_usdhc3: usdhc3grp {
+		fsl,pins = <
+			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK		0x40000190
+			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d0
+			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d0
+			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d0
+			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d0
+			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d0
+			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d0
+			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d0
+			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d0
+			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d0
+			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x190
+		>;
+	};
+
+	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
+		fsl,pins = <
+			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK		0x40000194
+			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d4
+			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d4
+			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d4
+			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d4
+			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d4
+			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d4
+			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d4
+			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d4
+			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d4
+			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x194
+		>;
+	};
+
+	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
+		fsl,pins = <
+			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK		0x40000196
+			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d6
+			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d6
+			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d6
+			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d6
+			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d6
+			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d6
+			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d6
+			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d6
+			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d6
+			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x196
+		>;
+	};
+
+	pinctrl_wdog: wdoggrp {
+		fsl,pins = <
+			MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B		0x166
+		>;
+	};
+};

arch/arm/dts/imx8mq-kontron-pitx-imx8m.dts

@@ -0,0 +1,613 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree File for the Kontron pitx-imx8m board.
+ *
+ * Copyright (C) 2021 Heiko Thiery <heiko.thiery@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "imx8mq.dtsi"
+#include <dt-bindings/net/ti-dp83867.h>
+
+/ {
+	model = "Kontron pITX-imx8m";
+	compatible = "kontron,pitx-imx8m", "fsl,imx8mq";
+
+	aliases {
+		i2c0 = &i2c1;
+		i2c1 = &i2c2;
+		i2c2 = &i2c3;
+		mmc0 = &usdhc1;
+		mmc1 = &usdhc2;
+		serial0 = &uart1;
+		serial1 = &uart2;
+		serial2 = &uart3;
+		spi0 = &qspi0;
+		spi1 = &ecspi2;
+	};
+
+	chosen {
+		stdout-path = "serial2:115200n8";
+	};
+
+	pcie0_refclk: pcie0-clock {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <100000000>;
+	};
+
+	pcie1_refclk: pcie1-clock {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <100000000>;
+	};
+
+	reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_reg_usdhc2>;
+		regulator-name = "V_3V3_SD";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+		off-on-delay-us = <20000>;
+		enable-active-high;
+	};
+};
+
+&ecspi2 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>;
+	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
+	status = "okay";
+
+	tpm@0 {
+		compatible = "infineon,slb9670";
+		reg = <0>;
+		spi-max-frequency = <43000000>;
+	};
+};
+
+&fec1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec1>;
+	phy-mode = "rgmii-id";
+	phy-handle = <&ethphy0>;
+	fsl,magic-packet;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy@0 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <0>;
+			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
+			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
+			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+			reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
+			reset-assert-us = <10>;
+			reset-deassert-us = <280>;
+		};
+	};
+};
+
+&i2c1 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	status = "okay";
+
+	pmic@8 {
+		compatible = "fsl,pfuze100";
+		fsl,pfuze-support-disable-sw;
+		reg = <0x8>;
+
+		regulators {
+			sw1a_reg: sw1ab {
+				regulator-name = "V_0V9_GPU";
+				regulator-min-microvolt = <825000>;
+				regulator-max-microvolt = <1100000>;
+			};
+
+			sw1c_reg: sw1c {
+				regulator-name = "V_0V9_VPU";
+				regulator-min-microvolt = <825000>;
+				regulator-max-microvolt = <1100000>;
+			};
+
+			sw2_reg: sw2 {
+				regulator-name = "V_1V1_NVCC_DRAM";
+				regulator-min-microvolt = <1100000>;
+				regulator-max-microvolt = <1100000>;
+				regulator-always-on;
+			};
+
+			sw3a_reg: sw3ab {
+				regulator-name = "V_1V0_DRAM";
+				regulator-min-microvolt = <825000>;
+				regulator-max-microvolt = <1100000>;
+				regulator-always-on;
+			};
+
+			sw4_reg: sw4 {
+				regulator-name = "V_1V8_S0";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+			};
+
+			swbst_reg: swbst {
+				regulator-name = "NC";
+				regulator-min-microvolt = <5000000>;
+				regulator-max-microvolt = <5150000>;
+			};
+
+			snvs_reg: vsnvs {
+				regulator-name = "V_0V9_SNVS";
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-always-on;
+			};
+
+			vref_reg: vrefddr {
+				regulator-name = "V_0V55_VREF_DDR";
+				regulator-always-on;
+			};
+
+			vgen1_reg: vgen1 {
+				regulator-name = "V_1V5_CSI";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+			};
+
+			vgen2_reg: vgen2 {
+				regulator-name = "V_0V9_PHY";
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <975000>;
+				regulator-always-on;
+			};
+
+			vgen3_reg: vgen3 {
+				regulator-name = "V_1V8_PHY";
+				regulator-min-microvolt = <1675000>;
+				regulator-max-microvolt = <1975000>;
+				regulator-always-on;
+			};
+
+			vgen4_reg: vgen4 {
+				regulator-name = "V_1V8_VDDA";
+				regulator-min-microvolt = <1625000>;
+				regulator-max-microvolt = <1875000>;
+				regulator-always-on;
+			};
+
+			vgen5_reg: vgen5 {
+				regulator-name = "V_3V3_PHY";
+				regulator-min-microvolt = <3075000>;
+				regulator-max-microvolt = <3625000>;
+				regulator-always-on;
+			};
+
+			vgen6_reg: vgen6 {
+				regulator-name = "V_2V8_CAM";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+		};
+	};
+
+	fan-controller@1b {
+		compatible = "maxim,max6650";
+		reg = <0x1b>;
+		maxim,fan-microvolt = <5000000>;
+	};
+
+	rtc@32 {
+		compatible = "microcrystal,rv8803";
+		reg = <0x32>;
+	};
+
+	sensor@4b {
+		compatible = "national,lm75b";
+		reg = <0x4b>;
+	};
+
+	eeprom@51 {
+		compatible = "atmel,24c32";
+		reg = <0x51>;
+		pagesize = <32>;
+	};
+};
+
+&i2c2 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	status = "okay";
+};
+
+&i2c3 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c3>;
+	status = "okay";
+};
+
+/* M.2 B-key slot */
+&pcie0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pcie0>;
+	reset-gpio = <&gpio1 9 GPIO_ACTIVE_LOW>;
+	clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
+		 <&clk IMX8MQ_CLK_PCIE1_AUX>,
+		 <&clk IMX8MQ_CLK_PCIE1_PHY>,
+		 <&pcie0_refclk>;
+	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
+	status = "okay";
+};
+
+/* Intel Ethernet Controller I210/I211 */
+&pcie1 {
+	clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
+		 <&clk IMX8MQ_CLK_PCIE2_AUX>,
+		 <&clk IMX8MQ_CLK_PCIE2_PHY>,
+		 <&pcie1_refclk>;
+	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
+	fsl,max-link-speed = <1>;
+	status = "okay";
+};
+
+&pgc_gpu {
+	power-supply = <&sw1a_reg>;
+};
+
+&pgc_vpu {
+	power-supply = <&sw1c_reg>;
+};
+
+&qspi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_qspi>;
+	status = "okay";
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0>;
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <4>;
+		m25p,fast-read;
+		spi-max-frequency = <50000000>;
+	};
+};
+
+&snvs_pwrkey {
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	assigned-clocks = <&clk IMX8MQ_CLK_UART1>;
+	assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
+	status = "okay";
+};
+
+&uart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart2>;
+	assigned-clocks = <&clk IMX8MQ_CLK_UART2>;
+	assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
+	status = "okay";
+};
+
+&uart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart3>;
+	uart-has-rtscts;
+	assigned-clocks = <&clk IMX8MQ_CLK_UART3>;
+	assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
+	status = "okay";
+};
+
+&usb3_phy0 {
+	status = "okay";
+};
+
+&usb3_phy1 {
+	status = "okay";
+};
+
+&usb_dwc3_0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usb0>;
+	dr_mode = "otg";
+	hnp-disable;
+	srp-disable;
+	adp-disable;
+	maximum-speed = "high-speed";
+	status = "okay";
+};
+
+&usb_dwc3_1 {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usdhc1 {
+	assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
+	assigned-clock-rates = <400000000>;
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+	vqmmc-supply = <&sw4_reg>;
+	bus-width = <8>;
+	non-removable;
+	no-sd;
+	no-sdio;
+	status = "okay";
+};
+
+&usdhc2 {
+	assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
+	assigned-clock-rates = <200000000>;
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+	bus-width = <4>;
+	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+	wp-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
+	vmmc-supply = <&reg_usdhc2_vmmc>;
+	status = "okay";
+};
+
+&wdog1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wdog>;
+	fsl,ext-reset-output;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog>;
+
+	pinctrl_hog: hoggrp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2		0x19 /* TPM Reset */
+			MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4		0x19 /* USB2 Hub Reset */
+		>;
+	};
+
+	pinctrl_gpio: gpiogrp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5			0x19 /* GPIO0 */
+			MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15		0x19 /* GPIO1 */
+			MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17		0x19 /* GPIO2 */
+			MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18		0x19 /* GPIO3 */
+			MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16		0x19 /* GPIO4 */
+			MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10		0x19 /* GPIO5 */
+			MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11		0x19 /* GPIO6 */
+			MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12		0x19 /* GPIO7 */
+		>;
+	};
+
+	pinctrl_pcie0: pcie0grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x16 /* PCIE_PERST */
+			MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29		0x16 /* W_DISABLE */
+		>;
+	};
+
+	pinctrl_reg_usdhc2: regusdhc2gpiogrp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19		0x41
+		>;
+	};
+
+	pinctrl_fec1: fec1grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC			0x3
+			MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO		0x23
+			MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
+			MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
+			MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
+			MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
+			MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
+			MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
+			MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
+			MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
+			MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
+			MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
+			MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
+			MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
+			MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11		0x16
+			MX8MQ_IOMUXC_GPIO1_IO15_GPIO1_IO15		0x16
+		>;
+	};
+
+	pinctrl_i2c1: i2c1grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL			0x4000007f
+			MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA			0x4000007f
+		>;
+	};
+
+	pinctrl_i2c2: i2c2grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL			0x4000007f
+			MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA			0x4000007f
+		>;
+	};
+
+	pinctrl_i2c3: i2c3grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL			0x4000007f
+			MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA			0x4000007f
+		>;
+	};
+
+	pinctrl_qspi: qspigrp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK		0x82
+			MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B		0x82
+			MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0		0x82
+			MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1		0x82
+			MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2		0x82
+			MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3		0x82
+		>;
+	};
+
+	pinctrl_ecspi2: ecspi2grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI		0x19
+			MX8MQ_IOMUXC_ECSPI2_MISO_ECSPI2_MISO		0x19
+			MX8MQ_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK		0x19
+		>;
+	};
+
+	pinctrl_ecspi2_cs: ecspi2csgrp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_ECSPI2_SS0_GPIO5_IO13		0x19
+		>;
+	};
+
+	pinctrl_uart1: uart1grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX		0x49
+			MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX		0x49
+		>;
+	};
+
+	pinctrl_uart2: uart2grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX		0x49
+			MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX		0x49
+		>;
+	};
+
+	pinctrl_uart3: uart3grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX		0x49
+			MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX		0x49
+			MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B		0x49
+			MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B	0x49
+		>;
+	};
+
+	pinctrl_usdhc1: usdhc1grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x83
+			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc3
+			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc3
+			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc3
+			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc3
+			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc3
+			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc3
+			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc3
+			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc3
+			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc3
+			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x83
+			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
+		>;
+	};
+
+	pinctrl_usdhc1_100mhz: usdhc1-100grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x8d
+			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xcd
+			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xcd
+			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xcd
+			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xcd
+			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xcd
+			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xcd
+			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xcd
+			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xcd
+			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xcd
+			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x8d
+			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
+		>;
+	};
+
+	pinctrl_usdhc1_200mhz: usdhc1-200grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x9f
+			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xdf
+			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xdf
+			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xdf
+			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xdf
+			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xdf
+			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xdf
+			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xdf
+			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xdf
+			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xdf
+			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x9f
+			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
+		>;
+	};
+
+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12		0x41
+			MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20			0x19
+		>;
+	};
+
+	pinctrl_usdhc2: usdhc2grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x83
+			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc3
+			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc3
+			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc3
+			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc3
+			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc3
+			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
+		>;
+	};
+
+	pinctrl_usdhc2_100mhz: usdhc2-100grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x8d
+			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xcd
+			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xcd
+			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xcd
+			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xcd
+			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xcd
+			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
+		>;
+	};
+
+	pinctrl_usdhc2_200mhz: usdhc2-200grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x9f
+			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xdf
+			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xdf
+			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xdf
+			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xdf
+			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xdf
+			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
+		>;
+	};
+
+	pinctrl_usb0: usb0grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_GPIO1_IO12_USB1_OTG_PWR		0x19
+			MX8MQ_IOMUXC_GPIO1_IO13_USB1_OTG_OC		0x19
+		>;
+	};
+
+	pinctrl_wdog: wdoggrp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B		0xc6
+		>;
+	};
+};

arch/arm/dts/imx8mq-librem5-r3.dtsi

@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2021 Purism SPC <kernel@puri.sm>
+
+/dts-v1/;
+
+/*
+ * This file describes hardware that is shared among r3 ("Dogwood") and
+ * later revisions of the Librem 5 so it has to be included in dts there.
+ */
+
+#include "imx8mq-librem5.dtsi"
+
+/ {
+	model = "Purism Librem 5r3";
+	compatible = "purism,librem5r3", "purism,librem5", "fsl,imx8mq";
+};
+
+&accel_gyro {
+	mount-matrix =  "1",  "0",  "0",
+			"0",  "1",  "0",
+			"0",  "0", "-1";
+};
+
+&bq25895 {
+	ti,battery-regulation-voltage = <4200000>; /* uV */
+	ti,charge-current = <1500000>; /* uA */
+	ti,termination-current = <144000>;  /* uA */
+};
+
+&camera_front {
+	pinctrl-0 = <&pinctrl_csi1>, <&pinctrl_r3_camera_pwr>;
+	shutdown-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>;
+};
+
+&iomuxc {
+	pinctrl_r3_camera_pwr: r3camerapwrgrp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_SPDIF_RX_GPIO5_IO4		0x83
+		>;
+	};
+};
+
+&proximity {
+	proximity-near-level = <25>;
+};

arch/arm/dts/imx8mq-librem5-r4.dts

@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2021 Purism SPC <kernel@puri.sm>
+
+/dts-v1/;
+
+#include "imx8mq-librem5-r3.dtsi"
+
+/ {
+	model = "Purism Librem 5r4";
+	compatible = "purism,librem5r4", "purism,librem5", "fsl,imx8mq";
+};
+
+&bat {
+	maxim,rsns-microohm = <1667>;
+};
+
+&led_backlight {
+	led-max-microamp = <25000>;
+};
+
+&lcd_panel {
+	compatible = "ys,ys57pss36bh5gq";
+};
+
+&proximity {
+	proximity-near-level = <10>;
+};

arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi

@@ -9,7 +9,3 @@
 &uart1 { /* console */
 	bootph-pre-ram;
 };
-
-&{/panel} {
-	compatible = "innolux,n125hce-gn1", "simple-panel";
-};

arch/arm/dts/imx8mq-mnt-reform2.dts

@@ -0,0 +1,354 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/*
+ * Copyright 2019-2021 MNT Research GmbH
+ * Copyright 2021 Lucas Stach <dev@lynxeye.de>
+ */
+
+/dts-v1/;
+
+#include "imx8mq-nitrogen-som.dtsi"
+
+/ {
+	model = "MNT Reform 2";
+	compatible = "mntre,reform2", "boundary,imx8mq-nitrogen8m-som", "fsl,imx8mq";
+	chassis-type = "laptop";
+
+	backlight: backlight {
+		compatible = "pwm-backlight";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_backlight>;
+		pwms = <&pwm2 0 10000 0>;
+		power-supply = <&reg_main_usb>;
+		enable-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+		brightness-levels = <0 32 64 128 160 200 255>;
+		default-brightness-level = <6>;
+	};
+
+	panel {
+		compatible = "innolux,n125hce-gn1", "simple-panel";
+		power-supply = <&reg_main_3v3>;
+		backlight = <&backlight>;
+		no-hpd;
+
+		port {
+			panel_in: endpoint {
+				remote-endpoint = <&edp_bridge_out>;
+			};
+		};
+	};
+
+	pcie1_refclk: clock-pcie1-refclk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <100000000>;
+	};
+
+	reg_main_5v: regulator-main-5v {
+		compatible = "regulator-fixed";
+		regulator-name = "5V";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	reg_main_3v3: regulator-main-3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "3V3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	reg_main_usb: regulator-main-usb {
+		compatible = "regulator-fixed";
+		regulator-name = "USB_PWR";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&reg_main_5v>;
+	};
+
+	reg_main_1v8: regulator-main-1v8 {
+		compatible = "regulator-fixed";
+		regulator-name = "1V8";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&reg_main_3v3>;
+	};
+
+	reg_main_1v2: regulator-main-1v2 {
+		compatible = "regulator-fixed";
+		regulator-name = "1V2";
+		regulator-min-microvolt = <1200000>;
+		regulator-max-microvolt = <1200000>;
+		vin-supply = <&reg_main_5v>;
+	};
+
+	sound {
+		compatible = "fsl,imx-audio-wm8960";
+		audio-cpu = <&sai2>;
+		audio-codec = <&wm8960>;
+		audio-routing =
+			"Headphone Jack", "HP_L",
+			"Headphone Jack", "HP_R",
+			"Ext Spk", "SPK_LP",
+			"Ext Spk", "SPK_LN",
+			"Ext Spk", "SPK_RP",
+			"Ext Spk", "SPK_RN",
+			"LINPUT1", "Mic Jack",
+			"Mic Jack", "MICB",
+			"LINPUT2", "Line In Jack",
+			"RINPUT2", "Line In Jack";
+		model = "wm8960-audio";
+	};
+};
+
+&dphy {
+	assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
+	assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>;
+	assigned-clock-rates = <25000000>;
+	status = "okay";
+};
+
+&fec1 {
+	status = "okay";
+};
+
+&i2c3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c3>;
+	status = "okay";
+
+	wm8960: codec@1a {
+		compatible = "wlf,wm8960";
+		reg = <0x1a>;
+		clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
+		clock-names = "mclk";
+		#sound-dai-cells = <0>;
+	};
+
+	rtc@68 {
+		compatible = "nxp,pcf8523";
+		reg = <0x68>;
+	};
+};
+
+&i2c4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c4>;
+	clock-frequency = <400000>;
+	status = "okay";
+
+	edp_bridge: bridge@2c {
+		compatible = "ti,sn65dsi86";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_edp_bridge>;
+		reg = <0x2c>;
+		enable-gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
+		vccio-supply = <&reg_main_1v8>;
+		vpll-supply = <&reg_main_1v8>;
+		vcca-supply = <&reg_main_1v2>;
+		vcc-supply = <&reg_main_1v2>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+
+				edp_bridge_in: endpoint {
+					remote-endpoint = <&mipi_dsi_out>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+
+				edp_bridge_out: endpoint {
+					remote-endpoint = <&panel_in>;
+				};
+			};
+		};
+	};
+};
+
+&lcdif {
+	assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>;
+	assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>;
+	/delete-property/assigned-clock-rates;
+	status = "okay";
+};
+
+&mipi_dsi {
+	status = "okay";
+
+	ports {
+		port@1 {
+			reg = <1>;
+
+			mipi_dsi_out: endpoint {
+				remote-endpoint = <&edp_bridge_in>;
+			};
+		};
+	};
+};
+
+&pcie1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pcie1>;
+	reset-gpio = <&gpio3 23 GPIO_ACTIVE_LOW>;
+	clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
+		 <&clk IMX8MQ_CLK_PCIE2_AUX>,
+		 <&clk IMX8MQ_CLK_PCIE2_PHY>,
+		 <&pcie1_refclk>;
+	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
+	status = "okay";
+};
+
+&pwm2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm2>;
+	status = "okay";
+};
+
+&reg_1p8v {
+	vin-supply = <&reg_main_5v>;
+};
+
+&reg_snvs {
+	vin-supply = <&reg_main_5v>;
+};
+
+&reg_arm_dram {
+	vin-supply = <&reg_main_5v>;
+};
+
+&reg_dram_1p1v {
+	vin-supply = <&reg_main_5v>;
+};
+
+&reg_soc_gpu_vpu {
+	vin-supply = <&reg_main_5v>;
+};
+
+&sai2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_sai2>;
+	assigned-clocks = <&clk IMX8MQ_CLK_SAI2>;
+	assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
+	assigned-clock-rates = <25000000>;
+	fsl,sai-mclk-direction-output;
+	fsl,sai-asynchronous;
+	status = "okay";
+};
+
+&snvs_rtc {
+	status = "disabled";
+};
+
+&uart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart2>;
+	status = "okay";
+};
+
+&usb3_phy0 {
+	vbus-supply = <&reg_main_usb>;
+	status = "okay";
+};
+
+&usb3_phy1 {
+	vbus-supply = <&reg_main_usb>;
+	status = "okay";
+};
+
+&usb_dwc3_0 {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usb_dwc3_1 {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usdhc2 {
+	assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
+	assigned-clock-rates = <200000000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc2>;
+	vqmmc-supply = <&reg_main_3v3>;
+	vmmc-supply = <&reg_main_3v3>;
+	bus-width = <4>;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl_backlight: backlightgrp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10		0x3
+		>;
+	};
+
+	pinctrl_edp_bridge: edpbridgegrp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20		0x1
+		>;
+	};
+
+	pinctrl_i2c3: i2c3grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL			0x40000022
+			MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA			0x40000022
+		>;
+	};
+
+	pinctrl_i2c4: i2c4grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL			0x40000022
+			MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA			0x40000022
+		>;
+	};
+
+	pinctrl_pcie1: pcie1grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23		0x16
+		>;
+	};
+
+	pinctrl_pwm2: pwm2grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_SPDIF_RX_PWM2_OUT			0x3
+		>;
+	};
+
+	pinctrl_sai2: sai2grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0		0xd6
+			MX8MQ_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC		0xd6
+			MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK		0xd6
+			MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC		0xd6
+			MX8MQ_IOMUXC_SAI2_RXC_SAI2_RX_BCLK		0xd6
+			MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK		0xd6
+			MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0		0xd6
+		>;
+	};
+
+	pinctrl_uart2: uart2grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX		0x45
+			MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX		0x45
+		>;
+	};
+
+	pinctrl_usdhc2: usdhc2grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_SD2_CD_B_USDHC2_CD_B		0x0
+			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x83
+			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc3
+			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc3
+			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc3
+			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc3
+			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc3
+		>;
+	};
+};

arch/arm/dts/imx8mq-nitrogen-som.dtsi

@@ -0,0 +1,278 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2018 Boundary Devices
+ * Copyright 2021 Lucas Stach <dev@lynxeye.de>
+ */
+
+#include "imx8mq.dtsi"
+
+/ {
+	model = "Boundary Devices i.MX8MQ Nitrogen8M";
+	compatible = "boundary,imx8mq-nitrogen8m-som", "fsl,imx8mq";
+
+	chosen {
+		stdout-path = &uart1;
+	};
+
+	reg_1p8v: regulator-fixed-1v8 {
+		compatible = "regulator-fixed";
+		regulator-name = "1P8V";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+	};
+
+	reg_snvs: regulator-fixed-snvs {
+		compatible = "regulator-fixed";
+		regulator-name = "VDD_SNVS";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+};
+
+&{/opp-table/opp-800000000} {
+	opp-microvolt = <1000000>;
+};
+
+&{/opp-table/opp-1000000000} {
+	opp-microvolt = <1000000>;
+};
+
+&A53_0 {
+	cpu-supply = <&reg_arm_dram>;
+};
+
+&A53_1 {
+	cpu-supply = <&reg_arm_dram>;
+};
+
+&A53_2 {
+	cpu-supply = <&reg_arm_dram>;
+};
+
+&A53_3 {
+	cpu-supply = <&reg_arm_dram>;
+};
+
+&fec1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec1>;
+	phy-mode = "rgmii-id";
+	phy-handle = <&ethphy0>;
+	fsl,magic-packet;
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy@4 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <4>;
+			interrupt-parent = <&gpio1>;
+			interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+			reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
+			reset-assert-us = <10000>;
+			reset-deassert-us = <300>;
+		};
+	};
+};
+
+&i2c1 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	status = "okay";
+
+	i2c-mux@70 {
+		compatible = "nxp,pca9546";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_i2c1_pca9546>;
+		reg = <0x70>;
+		reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		i2c1a: i2c@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			reg_arm_dram: regulator@60 {
+				compatible = "fcs,fan53555";
+				reg = <0x60>;
+				regulator-name = "VDD_ARM_DRAM_1V";
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <1000000>;
+				regulator-always-on;
+			};
+		};
+
+		i2c1b: i2c@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			reg_dram_1p1v: regulator@60 {
+				compatible = "fcs,fan53555";
+				reg = <0x60>;
+				regulator-name = "NVCC_DRAM_1P1V";
+				regulator-min-microvolt = <1100000>;
+				regulator-max-microvolt = <1100000>;
+				regulator-always-on;
+			};
+		};
+
+		i2c1c: i2c@2 {
+			reg = <2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			reg_soc_gpu_vpu: regulator@60 {
+				compatible = "fcs,fan53555";
+				reg = <0x60>;
+				regulator-name = "VDD_SOC_GPU_VPU";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-always-on;
+			};
+		};
+
+		i2c1d: i2c@3 {
+			reg = <3>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+	};
+};
+
+&pgc_gpu {
+	power-supply = <&reg_soc_gpu_vpu>;
+};
+
+&pgc_vpu {
+	power-supply = <&reg_soc_gpu_vpu>;
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	status = "okay";
+};
+
+&usdhc1 {
+	assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
+	assigned-clock-rates = <400000000>;
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+	vqmmc-supply = <&reg_1p8v>;
+	vmmc-supply = <&reg_snvs>;
+	bus-width = <8>;
+	non-removable;
+	no-mmc-hs400;
+	no-sdio;
+	no-sd;
+	status = "okay";
+};
+
+&wdog1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wdog>;
+	fsl,ext-reset-output;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl_fec1: fec1grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC			0x3
+			MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO		0x23
+			MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
+			MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
+			MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
+			MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
+			MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
+			MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
+			MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
+			MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0xd1
+			MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
+			MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
+			MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
+			MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0xd1
+			MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x1
+			MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11		0x41
+		>;
+	};
+
+	pinctrl_i2c1: i2c1grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL			0x40000022
+			MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA			0x40000022
+		>;
+	};
+
+	pinctrl_i2c1_pca9546: i2c1-pca9546grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8		0x49
+		>;
+	};
+
+	pinctrl_uart1: uart1grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX		0x45
+			MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX		0x45
+		>;
+	};
+
+	pinctrl_usdhc1: usdhc1grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x83
+			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc3
+			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc3
+			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc3
+			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc3
+			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc3
+			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc3
+			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc3
+			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc3
+			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc3
+			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
+		>;
+	};
+
+	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x8d
+			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xcd
+			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xcd
+			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xcd
+			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xcd
+			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xcd
+			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xcd
+			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xcd
+			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xcd
+			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xcd
+		>;
+	};
+
+	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x9f
+			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xdf
+			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xdf
+			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xdf
+			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xdf
+			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xdf
+			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xdf
+			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xdf
+			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xdf
+			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xdf
+		>;
+	};
+
+	pinctrl_wdog: wdoggrp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B		0xc6
+		>;
+	};
+};

arch/arm/dts/imx8mq-phanbell.dts

@@ -0,0 +1,481 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2017-2019 NXP
+ */
+
+/dts-v1/;
+
+#include "imx8mq.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+	model = "Google i.MX8MQ Phanbell";
+	compatible = "google,imx8mq-phanbell", "fsl,imx8mq";
+
+	chosen {
+		stdout-path = &uart1;
+	};
+
+	memory@40000000 {
+		device_type = "memory";
+		reg = <0x00000000 0x40000000 0 0x40000000>;
+	};
+
+	pmic_osc: clock-pmic {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <32768>;
+		clock-output-names = "pmic_osc";
+	};
+
+	reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
+		compatible = "regulator-fixed";
+		regulator-name = "VSD_3V3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	fan: gpio-fan {
+		compatible = "gpio-fan";
+		gpio-fan,speed-map = <0 0 8600 1>;
+		gpios = <&gpio3 5 GPIO_ACTIVE_HIGH>;
+		#cooling-cells = <2>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_gpio_fan>;
+		status = "okay";
+	};
+};
+
+&A53_0 {
+	cpu-supply = <&buck2>;
+};
+
+&A53_1 {
+	cpu-supply = <&buck2>;
+};
+
+&A53_2 {
+	cpu-supply = <&buck2>;
+};
+
+&A53_3 {
+	cpu-supply = <&buck2>;
+};
+
+&cpu_thermal {
+	trips {
+		cpu_alert0: trip0 {
+			temperature = <75000>;
+			hysteresis = <2000>;
+			type = "passive";
+		};
+
+		cpu_alert1: trip1 {
+			temperature = <80000>;
+			hysteresis = <2000>;
+			type = "passive";
+		};
+
+		cpu_crit0: trip3 {
+			temperature = <90000>;
+			hysteresis = <2000>;
+			type = "critical";
+		};
+
+		fan_toggle0: trip4 {
+			temperature = <65000>;
+			hysteresis = <10000>;
+			type = "active";
+		};
+	};
+
+	cooling-maps {
+		map0 {
+			trip = <&cpu_alert0>;
+			cooling-device =
+			<&A53_0 0 1>; /* Exclude highest OPP */
+		};
+
+		map1 {
+			trip = <&cpu_alert1>;
+			cooling-device =
+			<&A53_0 0 2>; /* Exclude two highest OPPs */
+		};
+
+		map4 {
+			trip = <&fan_toggle0>;
+			cooling-device = <&fan 0 1>;
+		};
+	};
+};
+
+&i2c1 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	status = "okay";
+
+	pmic: pmic@4b {
+		compatible = "rohm,bd71837";
+		reg = <0x4b>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_pmic>;
+		#clock-cells = <0>;
+		clocks = <&pmic_osc>;
+		clock-output-names = "pmic_clk";
+		interrupt-parent = <&gpio1>;
+		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+
+		regulators {
+			buck1: BUCK1 {
+				regulator-name = "buck1";
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1300000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <1250>;
+				rohm,dvs-run-voltage = <900000>;
+				rohm,dvs-idle-voltage = <900000>;
+				rohm,dvs-suspend-voltage = <800000>;
+			};
+
+			buck2: BUCK2 {
+				regulator-name = "buck2";
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <1000000>;
+				regulator-boot-on;
+				regulator-always-on;
+				rohm,dvs-run-voltage = <1000000>;
+				rohm,dvs-idle-voltage = <900000>;
+			};
+
+			buck3: BUCK3 {
+				regulator-name = "buck3";
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1300000>;
+				regulator-boot-on;
+				rohm,dvs-run-voltage = <900000>;
+			};
+
+			buck4: BUCK4 {
+				regulator-name = "buck4";
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1300000>;
+				regulator-boot-on;
+				regulator-always-on;
+				rohm,dvs-run-voltage = <900000>;
+			};
+
+			buck5: BUCK5 {
+				regulator-name = "buck5";
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck6: BUCK6 {
+				regulator-name = "buck6";
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck7: BUCK7 {
+				regulator-name = "buck7";
+				regulator-min-microvolt = <1605000>;
+				regulator-max-microvolt = <1995000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck8: BUCK8 {
+				regulator-name = "buck8";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1400000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo1: LDO1 {
+				regulator-name = "ldo1";
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo2: LDO2 {
+				regulator-name = "ldo2";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo3: LDO3 {
+				regulator-name = "ldo3";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo4: LDO4 {
+				regulator-name = "ldo4";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo5: LDO5 {
+				regulator-name = "ldo5";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo6: LDO6 {
+				regulator-name = "ldo6";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo7: LDO7 {
+				regulator-name = "ldo7";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+		};
+	};
+};
+
+&fec1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec1>;
+	phy-mode = "rgmii-id";
+	phy-handle = <&ethphy0>;
+	fsl,magic-packet;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		ethphy0: ethernet-phy@0 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <0>;
+			reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
+			reset-assert-us = <10000>;
+			reset-deassert-us = <50000>;
+		};
+	};
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	status = "okay";
+};
+
+&usdhc1 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+
+&usdhc2 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+	bus-width = <4>;
+	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+	vmmc-supply = <&reg_usdhc2_vmmc>;
+	status = "okay";
+};
+
+&usb3_phy0 {
+	status = "okay";
+};
+
+&usb_dwc3_0 {
+	dr_mode = "otg";
+	status = "okay";
+};
+
+&usb3_phy1 {
+	status = "okay";
+};
+
+&usb_dwc3_1 {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&wdog1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wdog>;
+	fsl,ext-reset-output;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl_fec1: fec1grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC			0x3
+			MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO		0x23
+			MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
+			MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
+			MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
+			MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
+			MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
+			MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
+			MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
+			MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
+			MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
+			MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
+			MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
+			MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
+			MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x19
+		>;
+	};
+
+	pinctrl_gpio_fan: gpiofangrp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5			0x16
+		>;
+	};
+
+	pinctrl_i2c1: i2c1grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL			0x4000007f
+			MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA			0x4000007f
+		>;
+	};
+
+	pinctrl_pmic: pmicirqgrp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x41
+		>;
+	};
+
+	pinctrl_uart1: uart1grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX		0x49
+			MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX		0x49
+		>;
+	};
+
+	pinctrl_usdhc1: usdhc1grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x83
+			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc3
+			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc3
+			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc3
+			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc3
+			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc3
+			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc3
+			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc3
+			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc3
+			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc3
+			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x83
+			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
+		>;
+	};
+
+	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x85
+			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc5
+			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc5
+			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc5
+			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc5
+			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc5
+			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc5
+			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc5
+			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc5
+			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc5
+			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x85
+			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
+		>;
+	};
+
+	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x87
+			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc7
+			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc7
+			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc7
+			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc7
+			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc7
+			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc7
+			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc7
+			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc7
+			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc7
+			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x87
+			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
+		>;
+	};
+
+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12	0x41
+			MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
+		>;
+	};
+
+	pinctrl_usdhc2: usdhc2grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x83
+			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc3
+			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc3
+			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc3
+			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc3
+			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc3
+			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
+		>;
+	};
+
+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x85
+			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc5
+			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc5
+			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc5
+			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc5
+			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc5
+			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
+		>;
+	};
+
+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x87
+			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc7
+			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc7
+			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc7
+			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc7
+			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc7
+			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
+		>;
+	};
+
+	pinctrl_wdog: wdoggrp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
+		>;
+	};
+};

arch/arm/dts/imx8mq-pico-pi.dts

@@ -0,0 +1,418 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 Wandboard, Org.
+ * Copyright 2017 NXP
+ *
+ * Author: Richard Hu <hakahu@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "imx8mq.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+	model = "TechNexion PICO-PI-8M";
+	compatible = "technexion,pico-pi-imx8m", "fsl,imx8mq";
+
+	chosen {
+		stdout-path = &uart1;
+	};
+
+	pmic_osc: clock-pmic {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <32768>;
+		clock-output-names = "pmic_osc";
+	};
+
+	reg_usb_otg_vbus: regulator-usb-otg-vbus {
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_otg_vbus>;
+		compatible = "regulator-fixed";
+		regulator-name = "usb_otg_vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&gpio3 14 GPIO_ACTIVE_LOW>;
+	};
+};
+
+&fec1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec1 &pinctrl_enet_3v3>;
+	phy-mode = "rgmii-id";
+	phy-handle = <&ethphy0>;
+	fsl,magic-packet;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy@1 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <1>;
+		};
+	};
+};
+
+&i2c1 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	status = "okay";
+
+	pmic: pmic@4b {
+		reg = <0x4b>;
+		compatible = "rohm,bd71837";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_pmic>;
+		clocks = <&pmic_osc>;
+		clock-names = "osc";
+		clock-output-names = "pmic_clk";
+		interrupt-parent = <&gpio1>;
+		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+		interrupt-names = "irq";
+
+		regulators {
+			buck1: BUCK1 {
+				regulator-name = "buck1";
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1300000>;
+				regulator-boot-on;
+				regulator-ramp-delay = <1250>;
+				rohm,dvs-run-voltage = <900000>;
+				rohm,dvs-idle-voltage = <850000>;
+				rohm,dvs-suspend-voltage = <800000>;
+			};
+
+			buck2: BUCK2 {
+				regulator-name = "buck2";
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1300000>;
+				regulator-boot-on;
+				regulator-ramp-delay = <1250>;
+				rohm,dvs-run-voltage = <1000000>;
+				rohm,dvs-idle-voltage = <900000>;
+			};
+
+			buck3: BUCK3 {
+				regulator-name = "buck3";
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1300000>;
+				regulator-boot-on;
+				rohm,dvs-run-voltage = <1000000>;
+			};
+
+			buck4: BUCK4 {
+				regulator-name = "buck4";
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1300000>;
+				regulator-boot-on;
+				rohm,dvs-run-voltage = <1000000>;
+			};
+
+			buck5: BUCK5 {
+				regulator-name = "buck5";
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-boot-on;
+			};
+
+			buck6: BUCK6 {
+				regulator-name = "buck6";
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+			};
+
+			buck7: BUCK7 {
+				regulator-name = "buck7";
+				regulator-min-microvolt = <1605000>;
+				regulator-max-microvolt = <1995000>;
+				regulator-boot-on;
+			};
+
+			buck8: BUCK8 {
+				regulator-name = "buck8";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1400000>;
+				regulator-boot-on;
+			};
+
+			ldo1: LDO1 {
+				regulator-name = "ldo1";
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo2: LDO2 {
+				regulator-name = "ldo2";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo3: LDO3 {
+				regulator-name = "ldo3";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+			};
+
+			ldo4: LDO4 {
+				regulator-name = "ldo4";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-boot-on;
+			};
+
+			ldo5: LDO5 {
+				regulator-name = "ldo5";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+			};
+
+			ldo6: LDO6 {
+				regulator-name = "ldo6";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-boot-on;
+			};
+
+			ldo7: LDO7 {
+				regulator-name = "ldo7";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+			};
+		};
+	};
+};
+
+&i2c2 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	status = "okay";
+};
+
+&uart1 { /* console */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	status = "okay";
+};
+
+&usdhc1 {
+	assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
+	assigned-clock-rates = <400000000>;
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+
+&usdhc2 {
+	assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
+	assigned-clock-rates = <200000000>;
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+	bus-width = <4>;
+	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
+&usb3_phy0 {
+	status = "okay";
+};
+
+&usb3_phy1 {
+	status = "okay";
+};
+
+&usb_dwc3_1 {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&wdog1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wdog>;
+	fsl,ext-reset-output;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl_enet_3v3: enet3v3grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0	0x19
+		>;
+	};
+
+	pinctrl_fec1: fec1grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC		0x3
+			MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO	0x23
+			MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3	0x1f
+			MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2	0x1f
+			MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1	0x1f
+			MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0	0x1f
+			MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3	0x91
+			MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2	0x91
+			MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1	0x91
+			MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0	0x91
+			MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC	0x1f
+			MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC	0x91
+			MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
+			MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
+			MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9	0x19
+		>;
+	};
+
+	pinctrl_i2c1: i2c1grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL			0x4000007f
+			MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA			0x4000007f
+		>;
+	};
+
+	pinctrl_i2c2: i2c2grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL			0x4000007f
+			MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA			0x4000007f
+		>;
+	};
+
+	pinctrl_otg_vbus: otgvbusgrp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14		0x19   /* USB OTG VBUS Enable */
+		>;
+	};
+
+	pinctrl_pmic: pmicirqgrp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x41
+		>;
+	};
+
+	pinctrl_uart1: uart1grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX		0x49
+			MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX		0x49
+		>;
+	};
+
+	pinctrl_uart2: uart2grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX		0x49
+			MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX		0x49
+			MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B		0x49
+			MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B		0x49
+		>;
+	};
+
+	pinctrl_usdhc1: usdhc1grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x83
+			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc3
+			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc3
+			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc3
+			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc3
+			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc3
+			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc3
+			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc3
+			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc3
+			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc3
+			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x83
+		>;
+	};
+
+	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x85
+			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc5
+			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc5
+			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc5
+			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc5
+			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc5
+			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc5
+			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc5
+			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc5
+			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc5
+			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x85
+		>;
+	};
+
+	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x87
+			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc7
+			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc7
+			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc7
+			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc7
+			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc7
+			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc7
+			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc7
+			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc7
+			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc7
+			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x87
+		>;
+	};
+
+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12	0x41
+		>;
+	};
+
+	pinctrl_usdhc2: usdhc2grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x83
+			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc3
+			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc3
+			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc3
+			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc3
+			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc3
+			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
+		>;
+	};
+
+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x85
+			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc5
+			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc5
+			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc5
+			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc5
+			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc5
+			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
+		>;
+	};
+
+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x87
+			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc7
+			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc7
+			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc7
+			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc7
+			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc7
+			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
+		>;
+	};
+
+	pinctrl_wdog: wdoggrp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
+		>;
+	};
+};

arch/arm/dts/imx95-toradex-smarc-dev-u-boot.dtsi

@@ -10,6 +10,7 @@
 };
 
 &gpio1 {
+	reg = <0 0x47400000 0 0x1000>, <0 0x47400040 0 0x40>;
 	bootph-pre-ram;
 };
 

arch/arm/dts/imx95-verdin-wifi-dev-u-boot.dtsi

@@ -26,6 +26,7 @@
 };
 
 &gpio1 {
+	reg = <0 0x47400000 0 0x1000>, <0 0x47400000 0 0x40>;
 	bootph-pre-ram;
 
 	ctrl-sleep-moci-hog {

arch/arm/dts/k3-am625-phycore-som-binman.dtsi

@@ -9,11 +9,6 @@
 #include "k3-binman.dtsi"
 
 #ifdef CONFIG_TARGET_PHYCORE_AM62X_R5
-
-&rcfg_yaml_tifs {
-	config = "tifs-rm-cfg.yaml";
-};
-
 &binman {
 	tiboot3-am62x-hs-phycore-som.bin {
 		filename = "tiboot3-am62x-hs-phycore-som.bin";

arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi

@@ -7,10 +7,6 @@
 
 #ifdef CONFIG_TARGET_VERDIN_AM62_R5
 
-&rcfg_yaml_tifs {
-	config = "tifs-rm-cfg.yaml";
-};
-
 &binman {
 	tiboot3-am62x-hs-verdin.bin {
 		filename = "tiboot3-am62x-hs-verdin.bin";

arch/arm/dts/k3-am62p5-verdin-wifi-dev-binman.dtsi

@@ -7,10 +7,6 @@
 
 #if IS_ENABLED(CONFIG_TARGET_VERDIN_AM62P_R5)
 
-&rcfg_yaml_tifs {
-	config = "tifs-rm-cfg.yaml";
-};
-
 &binman {
 	tiboot3-am62px-hs-fs-verdin.bin {
 		filename = "tiboot3-am62px-hs-fs-verdin.bin";

arch/arm/dts/lemans-evk-u-boot.dtsi

@@ -1,19 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-/*
- * Copyright (c) 2026, Qualcomm Innovation Center, Inc. All rights reserved.
- */
-
-/ {
-	/* Will be removed when bootloader updates later */
-	memory@80000000 {
-		device_type = "memory";
-		reg = <0x0 0x80000000 0x0 0x3ee00000>,
-		      <0x0 0xc0000000 0x0 0x0fd00000>,
-		      <0xD 0x00000000 0x2 0x54100000>,
-		      <0xA 0x80000000 0x1 0x80000000>,
-		      <0x9 0x00000000 0x1 0x80000000>,
-		      <0x1 0x00000000 0x3 0x00000000>,
-		      <0x0 0xd0000000 0x0 0x01900000>,
-		      <0x0 0xd3500000 0x0 0x2cb00000>;
-	};
-};

arch/arm/dts/r8a779md-geist-u-boot.dtsi

@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source extras for U-Boot for the Geist board with r8a779md
+ *
+ * Copyright (C) 2025-2026 Renesas Electronics Corp.
+ */
+
+/ {
+	aliases {
+		spi0 = &rpc;
+	};
+};
+
+&pfc {
+	qspi0_pins: qspi0 {
+		groups = "qspi0_ctrl", "qspi0_data4";
+		function = "qspi0";
+	};
+};
+
+/*
+ * SPI access works only if TFA is built with RCAR_RPC_HYPERFLASH_LOCKED=0
+ * and SPD=none , otherwise the RPC access is blocked either by TFA in case
+ * the former is set to 1, or by OPTEE-OS in case SPD=opteed .
+ */
+&rpc {
+	pinctrl-0 = <&qspi0_pins>;
+	pinctrl-names = "default";
+
+	#address-cells = <1>;
+	#size-cells = <0>;
+	spi-max-frequency = <40000000>;
+	status = "okay";
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <40000000>;
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <1>;
+	};
+};
+
+&sdhi0 {
+	sd-uhs-sdr12;
+	sd-uhs-sdr25;
+	sd-uhs-sdr104;
+	max-frequency = <208000000>;
+};
+
+&sdhi2 {
+	mmc-ddr-1_8v;
+	mmc-hs200-1_8v;
+	max-frequency = <200000000>;
+};
+
+&vcc_sdhi0 {
+	u-boot,off-on-delay-us = <20000>;
+};

arch/arm/dts/r8a779md-geist.dts

@@ -0,0 +1,717 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the Geist board with R-Car M3Le
+ *
+ * Copyright (C) 2025-2026 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include "r8a779md.dtsi"
+
+/ {
+	model = "Renesas Geist board based on r8a779md";
+	compatible = "renesas,geist", "renesas,r8a779md", "renesas,r8a77965";
+
+	aliases {
+		serial0 = &scif2;
+		serial1 = &hscif1;
+		ethernet0 = &avb;
+		mmc0 = &sdhi2;
+		mmc1 = &sdhi0;
+	};
+
+	chosen {
+		bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
+		stdout-path = "serial0:115200n8";
+	};
+
+	audio_clkout: audio-clkout {
+		/*
+		 * This is same as <&rcar_sound 0>
+		 * but needed to avoid cs2500/rcar_sound probe dead-lock
+		 */
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <12288000>;
+	};
+
+	backlight: backlight {
+		compatible = "pwm-backlight";
+		pwms = <&pwm1 0 50000>;
+
+		brightness-levels = <256 128 64 16 8 4 0>;
+		default-brightness-level = <6>;
+
+		power-supply = <&reg_12v>;
+		enable-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
+	};
+
+	cvbs-in {
+		compatible = "composite-video-connector";
+		label = "CVBS IN";
+
+		port {
+			cvbs_con: endpoint {
+				remote-endpoint = <&adv7482_ain7>;
+			};
+		};
+	};
+
+	hdmi-in {
+		compatible = "hdmi-connector";
+		label = "HDMI IN";
+		type = "a";
+
+		port {
+			hdmi_in_con: endpoint {
+				remote-endpoint = <&adv7482_hdmi>;
+			};
+		};
+	};
+
+	keys {
+		compatible = "gpio-keys";
+
+		pinctrl-0 = <&keys_pins>;
+		pinctrl-names = "default";
+
+		key-1 {
+			gpios = <&gpio5 17 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_1>;
+			label = "SW4-1";
+			wakeup-source;
+			debounce-interval = <20>;
+		};
+
+		key-2 {
+			gpios = <&gpio5 20 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_2>;
+			label = "SW4-2";
+			wakeup-source;
+			debounce-interval = <20>;
+		};
+
+		key-3 {
+			gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_3>;
+			label = "SW4-3";
+			wakeup-source;
+			debounce-interval = <20>;
+		};
+
+		key-4 {
+			gpios = <&gpio5 23 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_4>;
+			label = "SW4-4";
+			wakeup-source;
+			debounce-interval = <20>;
+		};
+
+		key-a {
+			gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_A>;
+			label = "TSW0";
+			wakeup-source;
+			debounce-interval = <20>;
+		};
+
+		key-b {
+			gpios = <&gpio6 12 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_B>;
+			label = "TSW1";
+			wakeup-source;
+			debounce-interval = <20>;
+		};
+
+		key-c {
+			gpios = <&gpio6 13 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_C>;
+			label = "TSW2";
+			wakeup-source;
+			debounce-interval = <20>;
+		};
+	};
+
+	memory@48000000 {
+		device_type = "memory";
+		/* first 128MB is reserved for secure area. */
+		reg = <0x0 0x48000000 0x0 0x78000000>;
+	};
+
+	memory@480000000 {
+		device_type = "memory";
+		reg = <0x4 0x80000000 0x0 0x80000000>;
+	};
+
+	reg_1p8v: regulator-1p8v {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-1.8V";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	reg_3p3v: regulator-3p3v {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-3.3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	reg_12v: regulator-12v {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-12V";
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	vbus0_usb2: regulator-vbus0-usb2 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "USB20_VBUS0";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+
+		gpio = <&gpio6 16 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	vcc_sdhi0: regulator-vcc-sdhi0 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "SDHI0 Vcc";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	vccq_sdhi0: regulator-vccq-sdhi0 {
+		compatible = "regulator-gpio";
+
+		regulator-name = "SDHI0 VccQ";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
+		gpios-states = <1>;
+		states = <3300000 1>, <1800000 0>;
+	};
+
+	sound_card: sound {
+		compatible = "audio-graph-card";
+
+		label = "rcar-sound";
+		dais = <&rsnd_port0>; /* AK4619 Audio Codec */
+	};
+
+	x12_clk: x12-clock {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <24576000>;
+	};
+
+	/* External DU dot clocks */
+	x21_clk: x21-clock {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <33000000>;
+	};
+
+	x22_clk: x22-clock {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <33000000>;
+	};
+
+	x23_clk: x23-clock {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <25000000>;
+	};
+
+	x3013_clk: x3013-clock {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <25000000>;
+	};
+};
+
+&audio_clk_a {
+	clock-frequency = <22579200>;
+};
+
+&avb {
+	pinctrl-0 = <&avb_pins>;
+	pinctrl-names = "default";
+	phy-handle = <&phy0>;
+	tx-internal-delay-ps = <2000>;
+	status = "okay";
+
+	phy0: ethernet-phy@0 {
+		compatible = "ethernet-phy-id0022.1622";
+		rxc-skew-ps = <1500>;
+		reg = <0>;
+		interrupts-extended = <&gpio2 11 IRQ_TYPE_LEVEL_LOW>;
+		reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
+		reset-assert-us = <10000>;
+		reset-deassert-us = <300>;
+	};
+};
+
+&csi40 {
+	status = "okay";
+
+	ports {
+		port@0 {
+			csi40_in: endpoint {
+				clock-lanes = <0>;
+				data-lanes = <1 2 3 4>;
+				remote-endpoint = <&adv7482_txa>;
+			};
+		};
+	};
+};
+
+&ehci0 {
+	dr_mode = "otg";
+	status = "okay";
+};
+
+&extalr_clk {
+	clock-frequency = <32768>;
+};
+
+&extal_clk {
+	clock-frequency = <16666666>;
+};
+
+&hscif1 {
+	pinctrl-0 = <&hscif1_pins>;
+	pinctrl-names = "default";
+
+	uart-has-rtscts;
+	/* Please only enable hscif1 or scif1 */
+	status = "okay";
+};
+
+&hsusb {
+	dr_mode = "otg";
+	status = "okay";
+};
+
+&i2c2 {
+	pinctrl-0 = <&i2c2_pins>;
+	pinctrl-names = "default";
+	clock-frequency = <100000>;
+	status = "okay";
+
+	ak4619: codec@10 {
+		compatible = "asahi-kasei,ak4619";
+		reg = <0x10>;
+		clocks = <&rcar_sound 3>;
+		clock-names = "mclk";
+		#sound-dai-cells = <0>;
+
+		port {
+			ak4619_endpoint: endpoint {
+				remote-endpoint = <&rsnd_endpoint0>;
+			};
+		};
+	};
+
+	/* Pin-to-pin, register map, and control compatible with CS2000 and CS2200 */
+	cs2500: clock-controller@4f {
+		#clock-cells = <0>;
+		compatible = "cirrus,cs2500", "cirrus,cs2000-cp";
+		reg = <0x4f>;
+		clocks = <&audio_clkout>, <&x12_clk>;
+		clock-names = "clk_in", "ref_clk";
+
+		assigned-clocks = <&cs2500>;
+		assigned-clock-rates = <24576000>; /* 1/1 divide */
+	};
+};
+
+&i2c4 {
+	clock-frequency = <400000>;
+	status = "okay";
+
+	versaclock3: clock-controller@68 {
+		compatible = "renesas,5p35023";
+		reg = <0x68>;
+		#clock-cells = <1>;
+		clocks = <&x3013_clk>;
+		assigned-clocks = <&versaclock3 4>, <&versaclock3 5>;
+		assigned-clock-rates = <100000000>, <100000000>;
+	};
+
+	versaclock5: clock-controller@6a {
+		compatible = "idt,5p49v5923";
+		reg = <0x6a>;
+		#clock-cells = <1>;
+		clocks = <&x23_clk>;
+		clock-names = "xin";
+	};
+
+	video-receiver@70 {
+		compatible = "adi,adv7482";
+		reg = <0x70 0x71 0x72 0x73 0x74 0x75
+		       0x60 0x61 0x62 0x63 0x64 0x65>;
+		reg-names = "main", "dpll", "cp", "hdmi", "edid", "repeater",
+			    "infoframe", "cbus", "cec", "sdp", "txa", "txb" ;
+
+		interrupts-extended = <&gpio6 30 IRQ_TYPE_LEVEL_LOW>,
+				      <&gpio6 31 IRQ_TYPE_LEVEL_LOW>;
+		interrupt-names = "intrq1", "intrq2";
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@7 {
+				reg = <7>;
+
+				adv7482_ain7: endpoint {
+					remote-endpoint = <&cvbs_con>;
+				};
+			};
+
+			port@8 {
+				reg = <8>;
+
+				adv7482_hdmi: endpoint {
+					remote-endpoint = <&hdmi_in_con>;
+				};
+			};
+
+			port@a {
+				reg = <10>;
+
+				adv7482_txa: endpoint {
+					clock-lanes = <0>;
+					data-lanes = <1 2 3 4>;
+					remote-endpoint = <&csi40_in>;
+				};
+			};
+		};
+	};
+
+	csa_vdd: adc@7c {
+		compatible = "maxim,max9611";
+		reg = <0x7c>;
+
+		shunt-resistor-micro-ohms = <5000>;
+	};
+
+	csa_dvfs: adc@7f {
+		compatible = "maxim,max9611";
+		reg = <0x7f>;
+
+		shunt-resistor-micro-ohms = <5000>;
+	};
+};
+
+&i2c_dvfs {
+	status = "okay";
+
+	clock-frequency = <400000>;
+
+	eeprom@50 {
+		compatible = "rohm,br24t01", "atmel,24c01";
+		reg = <0x50>;
+		pagesize = <8>;
+	};
+};
+
+&ohci0 {
+	dr_mode = "otg";
+	status = "okay";
+};
+
+&pcie_bus_clk {
+	clock-frequency = <100000000>;
+	status = "disabled";
+};
+
+&pciec0 {
+	clocks = <&cpg CPG_MOD 319>, <&versaclock3 4>;
+	status = "okay";
+};
+
+&pfc {
+	pinctrl-0 = <&scif_clk_pins>;
+	pinctrl-names = "default";
+
+	avb_pins: avb {
+		mux {
+			groups = "avb_link", "avb_mdio", "avb_mii";
+			function = "avb";
+		};
+
+		pins_mdio {
+			groups = "avb_mdio";
+			drive-strength = <24>;
+		};
+
+		pins_mii_tx {
+			pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0",
+			       "PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3";
+			drive-strength = <12>;
+		};
+	};
+
+	hscif1_pins: hscif1 {
+		groups = "hscif1_data_a", "hscif1_ctrl_a";
+		function = "hscif1";
+	};
+
+	i2c2_pins: i2c2 {
+		groups = "i2c2_a";
+		function = "i2c2";
+	};
+
+	irq0_pins: irq0 {
+		groups = "intc_ex_irq0";
+		function = "intc_ex";
+	};
+
+	keys_pins: keys {
+		pins = "GP_5_17", "GP_5_20", "GP_5_22";
+		bias-pull-up;
+	};
+
+	pwm1_pins: pwm1 {
+		groups = "pwm1_a";
+		function = "pwm1";
+	};
+
+	scif1_pins: scif1 {
+		groups = "scif1_data_a", "scif1_ctrl";
+		function = "scif1";
+	};
+
+	scif2_pins: scif2 {
+		groups = "scif2_data_a";
+		function = "scif2";
+	};
+
+	scif_clk_pins: scif_clk {
+		groups = "scif_clk_a";
+		function = "scif_clk";
+	};
+
+	sdhi0_pins: sd0 {
+		groups = "sdhi0_data4", "sdhi0_ctrl";
+		function = "sdhi0";
+		power-source = <3300>;
+	};
+
+	sdhi0_pins_uhs: sd0_uhs {
+		groups = "sdhi0_data4", "sdhi0_ctrl";
+		function = "sdhi0";
+		power-source = <1800>;
+	};
+
+	sdhi2_pins: sd2 {
+		groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
+		function = "sdhi2";
+		power-source = <1800>;
+	};
+
+	sound_pins: sound {
+		groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a";
+		function = "ssi";
+	};
+
+	sound_clk_pins: sound_clk {
+		groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clk_c_a",
+			 "audio_clkout_a", "audio_clkout3_a";
+		function = "audio_clk";
+	};
+
+	usb0_pins: usb0 {
+		groups = "usb0";
+		function = "usb0";
+	};
+};
+
+&pwm1 {
+	pinctrl-0 = <&pwm1_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&rcar_sound {
+	pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
+	pinctrl-names = "default";
+
+	/* Single DAI */
+	#sound-dai-cells = <0>;
+
+	/* audio_clkout0/1/2/3 */
+	#clock-cells = <1>;
+	clock-frequency = <12288000 11289600>;
+
+	status = "okay";
+
+	/* update <audio_clk_b> to <cs2500> */
+	clocks = <&cpg CPG_MOD 1005>,
+		 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
+		 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
+		 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
+		 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
+		 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
+		 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
+		 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
+		 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
+		 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
+		 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
+		 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
+		 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
+		 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
+		 <&audio_clk_a>, <&cs2500>,
+		 <&audio_clk_c>,
+		 <&cpg CPG_MOD 922>;
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		rsnd_port0: port@0 {
+			reg = <0>;
+
+			rsnd_endpoint0: endpoint {
+				remote-endpoint = <&ak4619_endpoint>;
+				dai-format = "left_j";
+				bitclock-master = <&rsnd_endpoint0>;
+				frame-master = <&rsnd_endpoint0>;
+				playback = <&ssi0>, <&src0>, <&dvc0>;
+				capture = <&ssi1>, <&src1>, <&dvc1>;
+			};
+		};
+	};
+};
+
+&rwdt {
+	timeout-sec = <60>;
+	status = "okay";
+};
+
+&scif1 {
+	pinctrl-0 = <&scif1_pins>;
+	pinctrl-names = "default";
+
+	uart-has-rtscts;
+	/* Please only enable hscif1 or scif1 */
+	/* status = "okay"; */
+};
+
+&scif2 {
+	pinctrl-0 = <&scif2_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&scif_clk {
+	clock-frequency = <14745600>;
+};
+
+&sdhi0 {
+	pinctrl-0 = <&sdhi0_pins>;
+	pinctrl-1 = <&sdhi0_pins_uhs>;
+	pinctrl-names = "default", "state_uhs";
+
+	vmmc-supply = <&vcc_sdhi0>;
+	vqmmc-supply = <&vccq_sdhi0>;
+	cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
+	wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
+	bus-width = <4>;
+	sd-uhs-sdr50;
+	sd-uhs-sdr104;
+	status = "okay";
+};
+
+&sdhi2 {
+	/* used for on-board 8bit eMMC */
+	pinctrl-0 = <&sdhi2_pins>;
+	pinctrl-1 = <&sdhi2_pins>;
+	pinctrl-names = "default", "state_uhs";
+
+	vmmc-supply = <&reg_3p3v>;
+	vqmmc-supply = <&reg_1p8v>;
+	bus-width = <8>;
+	mmc-hs200-1_8v;
+	no-sd;
+	no-sdio;
+	non-removable;
+	fixed-emmc-driver-type = <1>;
+	full-pwr-cycle-in-suspend;
+	status = "okay";
+};
+
+&ssi1 {
+	shared-pin;
+};
+
+&usb_extal_clk {
+	clock-frequency = <50000000>;
+};
+
+&usb2_phy0 {
+	pinctrl-0 = <&usb0_pins>;
+	pinctrl-names = "default";
+
+	vbus-supply = <&vbus0_usb2>;
+	status = "okay";
+};
+
+&vin0 {
+	status = "okay";
+};
+
+&vin1 {
+	status = "okay";
+};
+
+&vin2 {
+	status = "okay";
+};
+
+&vin3 {
+	status = "okay";
+};
+
+&vin4 {
+	status = "okay";
+};
+
+&vin5 {
+	status = "okay";
+};
+
+&vin6 {
+	status = "okay";
+};
+
+&vin7 {
+	status = "okay";
+};
+
+&vspb {
+	status = "okay";
+};
+
+&vspi0 {
+	status = "okay";
+};

arch/arm/dts/r8a779md.dtsi

@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the R-Car M3Le (R8A779MD) SoC
+ *
+ * Copyright (C) 2025-2026 Renesas Electronics Corp.
+ */
+
+#include "r8a77965.dtsi"
+
+/ {
+	compatible = "renesas,r8a779md", "renesas,r8a77965";
+};
+
+/delete-node/ &csi20;
+/delete-node/ &drif00;
+/delete-node/ &drif01;
+/delete-node/ &drif10;
+/delete-node/ &drif11;
+/delete-node/ &drif20;
+/delete-node/ &drif21;
+/delete-node/ &drif30;
+/delete-node/ &drif31;
+/delete-node/ &du;
+/delete-node/ &ehci1;
+/delete-node/ &hdmi0;
+/delete-node/ &lvds0;
+/delete-node/ &mlp;
+/delete-node/ &ohci1;
+/delete-node/ &pciec1;
+/delete-node/ &sata;
+/delete-node/ &usb2_phy1;
+/delete-node/ &usb3_peri0;
+/delete-node/ &usb3_phy0;
+/delete-node/ &vin0csi20;
+/delete-node/ &vin1csi20;
+/delete-node/ &vin2csi20;
+/delete-node/ &vin3csi20;
+/delete-node/ &vin4csi20;
+/delete-node/ &vin5csi20;
+/delete-node/ &vin6csi20;
+/delete-node/ &vin7csi20;
+/delete-node/ &xhci0;
+
+&sdhi0 {
+	compatible = "renesas,sdhi-r8a779md", "renesas,rcar-gen3-sdhi";
+};
+
+&sdhi1 {
+	compatible = "renesas,sdhi-r8a779md", "renesas,rcar-gen3-sdhi";
+};
+
+&sdhi2 {
+	compatible = "renesas,sdhi-r8a779md", "renesas,rcar-gen3-sdhi";
+};
+
+&sdhi3 {
+	compatible = "renesas,sdhi-r8a779md", "renesas,rcar-gen3-sdhi";
+	no-mmc;
+};

arch/arm/dts/stm32mp15-scmi-u-boot.dtsi

@@ -21,6 +21,13 @@
 		pinctrl1 = &pinctrl_z;
 	};
 
+	arm_wdt: watchdog {
+		compatible = "arm,smc-wdt";
+		arm,smc-id = <0xbc000000>;
+		timeout-sec = <32>;
+		status = "okay";
+	};
+
 	binman: binman {
 		multiple-images;
 	};
@@ -103,7 +110,7 @@
 };
 
 &iwdg2 {
-	bootph-all;
+	status = "disabled";
 };
 
 /* pre-reloc probe = reserve video frame buffer in video_reserve() */

arch/arm/include/asm/arch-imx9/ddr.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Copyright 2022-2026 NXP
+ * Copyright 2022 NXP
  */
 
 #ifndef __ASM_ARCH_IMX8M_DDR_H
@@ -100,52 +100,6 @@ struct dram_timing_info {
 
 extern struct dram_timing_info dram_timing;
 
-/* Quick Boot related */
-#define DDRPHY_QB_CSR_SIZE	5168
-#define DDRPHY_QB_ACSM_SIZE	(4 * 1024)
-#define DDRPHY_QB_MSB_SIZE	0x200
-#define DDRPHY_QB_PSTATES	0
-#define DDRPHY_QB_PST_SIZE	(DDRPHY_QB_PSTATES * 4 * 1024)
-
-/**
- * This structure needs to be aligned with the one in OEI.
- */
-struct ddrphy_qb_state {
-	u32 crc;		  /* Used for ensuring integrity in DRAM */
-#define MAC_LENGTH		8 /* 256 bits, 32-bit aligned */
-	u32 mac[MAC_LENGTH];	  /* For 95A0/1 use mac[0] to keep CRC32 value */
-	u8 trained_vrefca_a0;
-	u8 trained_vrefca_a1;
-	u8 trained_vrefca_b0;
-	u8 trained_vrefca_b1;
-	u8 trained_vrefdq_a0;
-	u8 trained_vrefdq_a1;
-	u8 trained_vrefdq_b0;
-	u8 trained_vrefdq_b1;
-	u8 trained_vrefdqu_a0;
-	u8 trained_vrefdqu_a1;
-	u8 trained_vrefdqu_b0;
-	u8 trained_vrefdqu_b1;
-	u8 trained_dramdfe_a0;
-	u8 trained_dramdfe_a1;
-	u8 trained_dramdfe_b0;
-	u8 trained_dramdfe_b1;
-	u8 trained_dramdca_a0;
-	u8 trained_dramdca_a1;
-	u8 trained_dramdca_b0;
-	u8 trained_dramdca_b1;
-	u16 qb_pll_upll_prog0;
-	u16 qb_pll_upll_prog1;
-	u16 qb_pll_upll_prog2;
-	u16 qb_pll_upll_prog3;
-	u16 qb_pll_ctrl1;
-	u16 qb_pll_ctrl4;
-	u16 qb_pll_ctrl5;
-	u16 csr[DDRPHY_QB_CSR_SIZE];
-	u16 acsm[DDRPHY_QB_ACSM_SIZE];
-	u16 pst[DDRPHY_QB_PST_SIZE];
-};
-
 void ddr_load_train_firmware(enum fw_type type);
 int ddr_init(struct dram_timing_info *timing_info);
 int ddr_cfg_phy(struct dram_timing_info *timing_info);

arch/arm/include/asm/arch-imx9/sys_proto.h

@@ -23,10 +23,6 @@ int low_drive_freq_update(void *blob);
 enum imx9_soc_voltage_mode soc_target_voltage_mode(void);
 int get_reset_reason(bool sys, bool lm);
 
-int scmi_get_boot_device_offset(unsigned long *img_off);
-int scmi_get_boot_stage(u8 *stage);
-u8 scmi_get_imgset_sel(void);
-
 #define is_voltage_mode(mode) (soc_target_voltage_mode() == (mode))
 
 #endif

arch/arm/include/asm/mach-imx/ahab.h

@@ -8,7 +8,7 @@
 
 #include <imx_container.h>
 
-void *ahab_auth_cntr_hdr(struct container_hdr *container, u16 length);
+int ahab_auth_cntr_hdr(struct container_hdr *container, u16 length);
 int ahab_auth_release(void);
 int ahab_verify_cntr_image(struct boot_img_t *img, int image_index);
 

arch/arm/include/asm/mach-imx/qb.h

@@ -1,15 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2026 NXP
- */
-
-#ifndef __IMX_QB_H__
-#define __IMX_QB_H__
-
-#include <stdbool.h>
-
-bool imx_qb_check(void);
-int imx_qb(const char *ifname, const char *dev, bool save);
-void spl_imx_qb_save(void);
-
-#endif

arch/arm/mach-imx/Kconfig

@@ -71,38 +71,10 @@ config CSF_SIZE
 	  Define the maximum size for Command Sequence File (CSF) binary
 	  this information is used to define the image boot data.
 
-config IMX_QB
-	bool "Support Quickboot flow for Synopsis DDR PHY on iMX platforms"
-	default y
-	depends on IMX94 || IMX95 || IMX952
-	help
-	  Enable the logic for saving DDR training data from volatile
-	  memory to non-volatile storage. OEI uses the saved data to
-	  run Quickboot flow and skip re-training the DDR PHY.
-
-config SPL_IMX_QB
-	bool "Run qb save during SPL"
-	depends on SPL && IMX_QB
-	help
-	  Automatically save DDR training data (Quickboot data)
-	  to current boot device when needed (when OEI runs Training
-	  flow and saves qb data to volatile memory).
-
-config CMD_IMX_QB
-	bool "Support the 'qb' command"
-	default y
-	depends on IMX_QB
-	help
-	  Enable qb command to write/erase DDR quick boot training
-	  data to/from a chosen boot device. Using 'qb save/erase'
-	  without arguments implies using the current boot device's
-	  first bootable partition (e.g. boot0 for eMMC). For use in
-	  uuu scripts, the boot device must be specified explicitly.
-
 config CMD_BMODE
 	bool "Support the 'bmode' command"
 	default y
-	depends on IMX95 || ARCH_IMX8M || ARCH_MX7 || ARCH_MX6 || ARCH_MX5
+	depends on ARCH_IMX8M || ARCH_MX7 || ARCH_MX6 || ARCH_MX5
 	help
 	  This enables the 'bmode' (bootmode) command for forcing
 	  a boot from specific media.

arch/arm/mach-imx/Makefile

@@ -80,7 +80,6 @@ endif
 ifneq ($(CONFIG_XPL_BUILD),y)
 obj-$(CONFIG_CMD_BMODE) += cmd_bmode.o
 obj-$(CONFIG_CMD_HDMIDETECT) += cmd_hdmidet.o
-obj-$(CONFIG_CMD_IMX_QB) += cmd_qb.o
 obj-$(CONFIG_CMD_DEKBLOB) += cmd_dek.o
 obj-$(CONFIG_CMD_NANDBCB) += cmd_nandbcb.o
 endif

arch/arm/mach-imx/cmd_qb.c

@@ -1,102 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/**
- * Copyright 2024-2026 NXP
- */
-#include <command.h>
-#include <spl.h>
-#include <stdlib.h>
-
-#include <asm/mach-imx/boot_mode.h>
-#include <asm/mach-imx/sys_proto.h>
-#include <asm/mach-imx/qb.h>
-
-static void parse_qb_args(int argc, char * const argv[],
-			  const char **ifname, const char **dev)
-{
-	/* qb save/erase -> use boot device */
-	if (argc < 2) {
-		*ifname = "auto";
-		return;
-	}
-
-	*ifname = argv[1];
-
-	if (argc == 3)
-		*dev = argv[2];
-}
-
-static int do_qb(struct cmd_tbl *cmdtp, int flag, int argc,
-		 char * const argv[], bool save)
-{
-	const char *ifname, *dev;
-
-	parse_qb_args(argc, argv, &ifname, &dev);
-
-	if (imx_qb(ifname, dev, save))
-		return CMD_RET_FAILURE;
-
-	return CMD_RET_SUCCESS;
-}
-
-static int do_qb_check(struct cmd_tbl *cmdtp, int flag,
-		       int argc, char * const argv[])
-{
-	return imx_qb_check() ? CMD_RET_SUCCESS : CMD_RET_FAILURE;
-}
-
-static int do_qb_save(struct cmd_tbl *cmdtp, int flag,
-		      int argc, char * const argv[])
-{
-	return do_qb(cmdtp, flag, argc, argv, true);
-}
-
-static int do_qb_erase(struct cmd_tbl *cmdtp, int flag,
-		       int argc, char * const argv[])
-{
-	return do_qb(cmdtp, flag, argc, argv, false);
-}
-
-static struct cmd_tbl cmd_qb[] = {
-	U_BOOT_CMD_MKENT(check, 1, 1, do_qb_check, "", ""),
-	U_BOOT_CMD_MKENT(save,  3, 1, do_qb_save,  "", ""),
-	U_BOOT_CMD_MKENT(erase, 3, 1, do_qb_erase, "", ""),
-};
-
-static int do_qbops(struct cmd_tbl *cmdtp, int flag, int argc,
-		    char *const argv[])
-{
-	struct cmd_tbl *cp;
-
-	cp = find_cmd_tbl(argv[1], cmd_qb, ARRAY_SIZE(cmd_qb));
-
-	/* Drop the qb command */
-	argc--;
-	argv++;
-
-	if (!cp) {
-		printf("qb: %s: command not found\n", argv[0] ? argv[0] : " ");
-		return CMD_RET_USAGE;
-	}
-
-	if (argc > cp->maxargs) {
-		printf("qb %s: too many arguments: %d > %d\n", cp->name,
-		       argc - 1, cp->maxargs - 1);
-		return CMD_RET_USAGE;
-	}
-
-	if (flag == CMD_FLAG_REPEAT && !cmd_is_repeatable(cp)) {
-		printf("qb %s: repeat flag set but command is not repeatable\n",
-		       cp->name);
-		return CMD_RET_SUCCESS;
-	}
-
-	return cp->cmd(cmdtp, flag, argc, argv);
-}
-
-U_BOOT_CMD(
-	qb, 4, 1, do_qbops,
-	"DDR Quick Boot sub system",
-	"check - check if quick boot data is stored in mem by training flow\n"
-	"qb save [interface] [dev]  - save quick boot data in NVM => trigger quick boot flow\n"
-	"qb erase [interface] [dev] - erase quick boot data from NVM => trigger training flow\n"
-);

arch/arm/mach-imx/ele_ahab.c

@@ -255,7 +255,7 @@ static void display_ahab_auth_ind(u32 event)
 	printf("%s\n", ele_ind_str[get_idx(ele_ind, resp_ind, ARRAY_SIZE(ele_ind))]);
 }
 
-void *ahab_auth_cntr_hdr(struct container_hdr *container, u16 length)
+int ahab_auth_cntr_hdr(struct container_hdr *container, u16 length)
 {
 	int err;
 	u32 resp;
@@ -271,10 +271,9 @@ void *ahab_auth_cntr_hdr(struct container_hdr *container, u16 length)
 		printf("Authenticate container hdr failed, return %d, resp 0x%x\n",
 		       err, resp);
 		display_ahab_auth_ind(resp);
-		return NULL;
 	}
 
-	return (void *)IMG_CONTAINER_BASE; /* Return authenticated container header */
+	return err;
 }
 
 int ahab_auth_release(void)
@@ -328,6 +327,7 @@ int authenticate_os_container(ulong addr)
 {
 	struct container_hdr *phdr;
 	int i, ret = 0;
+	int err;
 	u16 length;
 	struct boot_img_t *img;
 	unsigned long s, e;
@@ -357,8 +357,8 @@ int authenticate_os_container(ulong addr)
 
 	debug("container length %u\n", length);
 
-	phdr = ahab_auth_cntr_hdr(phdr, length);
-	if (!phdr) {
+	err = ahab_auth_cntr_hdr(phdr, length);
+	if (err) {
 		ret = -EIO;
 		goto exit;
 	}
@@ -367,7 +367,7 @@ int authenticate_os_container(ulong addr)
 
 	/* Copy images to dest address */
 	for (i = 0; i < phdr->num_images; i++) {
-		img = (struct boot_img_t *)((ulong)phdr +
+		img = (struct boot_img_t *)(addr +
 					    sizeof(struct container_hdr) +
 					    i * sizeof(struct boot_img_t));
 

arch/arm/mach-imx/image-container.c

@@ -240,14 +240,6 @@ static unsigned long get_boot_device_offset(void *dev, int dev_type)
 		return offset;
 	}
 
-#if IS_ENABLED(CONFIG_ARCH_IMX9) && IS_ENABLED(CONFIG_SCMI_FIRMWARE)
-	int ret;
-	ret = scmi_get_boot_device_offset(&offset);
-	if (!ret)
-		return offset;
-	/* fall back to boot from primary set if get rom passover failed */
-#endif
-
 	sec_boot = check_secondary_cnt_set(&sec_set_off);
 	if (sec_boot)
 		printf("Secondary set selected\n");
@@ -374,17 +366,10 @@ int spl_mmc_emmc_boot_partition(struct mmc *mmc)
 
 	part = EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config);
 	if (part == EMMC_BOOT_PART_BOOT1 || part == EMMC_BOOT_PART_BOOT2) {
-		bool sec_boot = false;
-#if IS_ENABLED(CONFIG_ARCH_IMX9) && IS_ENABLED(CONFIG_SCMI_FIRMWARE)
-		u8 stage;
-		int ret;
-		ret = scmi_get_boot_stage(&stage);
-		if (!ret)
-			sec_boot = (stage == 0x9);
-#else
 		unsigned long sec_set_off = 0;
+		bool sec_boot = false;
+
 		sec_boot = check_secondary_cnt_set(&sec_set_off);
-#endif
 		if (sec_boot)
 			part = (part == EMMC_BOOT_PART_BOOT1) ? EMMC_HWPART_BOOT2 : EMMC_HWPART_BOOT1;
 	} else if (part == EMMC_BOOT_PART_USER) {

arch/arm/mach-imx/imx8/ahab.c

@@ -28,7 +28,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define AHAB_HASH_TYPE_MASK	0x00000700
 #define AHAB_HASH_TYPE_SHA256	0
 
-void *ahab_auth_cntr_hdr(struct container_hdr *container, u16 length)
+int ahab_auth_cntr_hdr(struct container_hdr *container, u16 length)
 {
 	int err;
 
@@ -37,12 +37,10 @@ void *ahab_auth_cntr_hdr(struct container_hdr *container, u16 length)
 
 	err = sc_seco_authenticate(-1, SC_SECO_AUTH_CONTAINER,
 				   SECO_LOCAL_SEC_SEC_SECURE_RAM_BASE);
-	if (err) {
+	if (err)
 		printf("Authenticate container hdr failed, return %d\n", err);
-		return NULL;
-	}
 
-	return (void *)SEC_SECURE_RAM_BASE; /* Return authenticated container header */
+	return err;
 }
 
 int ahab_auth_release(void)
@@ -128,7 +126,7 @@ int authenticate_os_container(ulong addr)
 {
 	struct container_hdr *phdr;
 	int i, ret = 0;
-	__maybe_unused int err;
+	int err;
 	u16 length;
 	struct boot_img_t *img;
 	unsigned long s, e;
@@ -161,15 +159,15 @@ int authenticate_os_container(ulong addr)
 
 	debug("container length %u\n", length);
 
-	phdr = ahab_auth_cntr_hdr(phdr, length);
-	if (!phdr) {
+	err = ahab_auth_cntr_hdr(phdr, length);
+	if (err) {
 		ret = -EIO;
 		goto exit;
 	}
 
 	/* Copy images to dest address */
 	for (i = 0; i < phdr->num_images; i++) {
-		img = (struct boot_img_t *)((ulong)phdr +
+		img = (struct boot_img_t *)(addr +
 					    sizeof(struct container_hdr) +
 					    i * sizeof(struct boot_img_t));
 

arch/arm/mach-imx/imx8m/Kconfig

@@ -79,13 +79,11 @@ config TARGET_IMX8MQ_PHANBELL
 	bool "imx8mq_phanbell"
 	select IMX8MQ
 	select IMX8M_LPDDR4
-	imply OF_UPSTREAM
 
 config TARGET_IMX8MQ_REFORM2
 	bool "imx8mq_reform2"
 	select IMX8MQ
 	select IMX8M_LPDDR4
-	imply OF_UPSTREAM
 
 config TARGET_IMX8MM_DATA_MODUL_EDM_SBC
 	bool "Data Modul eDM SBC i.MX8M Mini"
@@ -310,7 +308,6 @@ config TARGET_PICO_IMX8MQ
 	bool "Support Technexion Pico iMX8MQ"
 	select IMX8MQ
 	select IMX8M_LPDDR4
-	imply OF_UPSTREAM
 
 config TARGET_IMX8MN_VAR_SOM
 	bool "Variscite imx8mn_var_som"
@@ -327,7 +324,6 @@ config TARGET_KONTRON_PITX_IMX8M
 	bool "Support Kontron pITX-imx8m"
 	select IMX8MQ
 	select IMX8M_LPDDR4
-	imply OF_UPSTREAM
 
 config TARGET_TORADEX_SMARC_IMX8MP
 	bool "Support Toradex SMARC iMX8M Plus module"
@@ -430,7 +426,6 @@ config TARGET_LIBREM5
 	select IMX8MQ
 	select SUPPORT_SPL
 	select IMX8M_LPDDR4
-	imply OF_UPSTREAM
 
 endchoice
 

arch/arm/mach-imx/imx9/Makefile

@@ -1,6 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
-# Copyright 2022,2026 NXP
+# Copyright 2022 NXP
 
 obj-y += lowlevel_init.o
 
@@ -12,6 +12,4 @@ endif
 
 ifneq ($(CONFIG_SPL_BUILD),y)
 obj-y += imx_bootaux.o
-endif
-
-obj-$(CONFIG_$(PHASE_)IMX_QB) += qb.o
+endif

arch/arm/mach-imx/imx9/clock.c

@@ -478,7 +478,6 @@ u32 get_clk_src_rate(enum ccm_clk_src source)
 	switch (source) {
 	case ARM_PLL_CLK:
 		ctrl = readl(&ana_regs->arm_pll.ctrl.reg);
-		break;
 	case AUDIO_PLL_CLK:
 		ctrl = readl(&ana_regs->audio_pll.ctrl.reg);
 		break;

arch/arm/mach-imx/imx9/qb.c

@@ -1,403 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/**
- * Copyright 2024-2026 NXP
- */
-#include <dm/device-internal.h>
-#include <dm/uclass.h>
-#include <errno.h>
-#include <imx_container.h>
-#include <linux/bitfield.h>
-#include <mmc.h>
-#include <spi_flash.h>
-#include <spl.h>
-#include <stdlib.h>
-#include <u-boot/crc.h>
-
-#include <asm/arch/ddr.h>
-#include <asm/mach-imx/boot_mode.h>
-#include <asm/mach-imx/sys_proto.h>
-
-#define QB_STATE_LOAD_SIZE    SZ_64K
-
-#define BLK_DEV		0
-#define SPI_DEV		1
-
-#define IMG_FLAGS_IMG_TYPE_MASK   0xF
-#define IMG_FLAGS_IMG_TYPE(x)     FIELD_GET(IMG_FLAGS_IMG_TYPE_MASK, (x))
-
-#define IMG_TYPE_DDR_TDATA_DUMMY  0xD   /* dummy DDR training data image */
-
-static const struct {
-	const char *ifname;
-	const char *dev;
-} imx_boot_devs[] = {
-	[BOOT_DEVICE_MMC1] = { "mmc", "0" },
-	[BOOT_DEVICE_MMC2] = { "mmc", "1" },
-	[BOOT_DEVICE_SPI]  = { "spi", "" },
-};
-
-static int imx_qb_get_board_boot_device(void)
-{
-	switch (get_boot_device()) {
-	case SD1_BOOT:
-	case MMC1_BOOT:
-		return BOOT_DEVICE_MMC1;
-	case SD2_BOOT:
-	case MMC2_BOOT:
-		return BOOT_DEVICE_MMC2;
-	case USB_BOOT:
-		return BOOT_DEVICE_BOARD;
-	case QSPI_BOOT:
-		return BOOT_DEVICE_SPI;
-	default:
-		return BOOT_DEVICE_NONE;
-	}
-}
-
-static int imx_qb_get_boot_dev_str(const char **ifname, const char **dev)
-{
-	int boot_dev;
-
-	if (IS_ENABLED(CONFIG_XPL_BUILD))
-		boot_dev = spl_boot_device();
-	else
-		boot_dev = imx_qb_get_board_boot_device();
-
-	if (boot_dev == BOOT_DEVICE_NONE || boot_dev == BOOT_DEVICE_BOARD)
-		return -EINVAL;
-
-	*ifname = imx_boot_devs[boot_dev].ifname;
-	*dev = imx_boot_devs[boot_dev].dev;
-
-	return 0;
-}
-
-bool imx_qb_check(void)
-{
-	struct ddrphy_qb_state *qb_state;
-	u32 size, crc;
-
-	/**
-	 * Ensure CRC is not empty, the reason is that
-	 * the data is invalidated after first save run
-	 * or after it is overwritten.
-	 */
-	qb_state = (struct ddrphy_qb_state *)CONFIG_QB_SAVED_STATE_BASE;
-	size = sizeof(struct ddrphy_qb_state) - sizeof(qb_state->crc);
-	crc = crc32(0, (u8 *)qb_state->mac, size);
-
-	if (!qb_state->crc || crc != qb_state->crc)
-		return false;
-
-	return true;
-}
-
-static int imx_qb_get_blk_boot_part(const char * const ifname,
-				    const char * const dev,
-				    struct blk_desc **bdesc)
-{
-	struct udevice *udev;
-	struct disk_partition info;
-	struct mmc *mmc;
-	int part;
-	int ret;
-
-	if (!IS_ENABLED(CONFIG_XPL_BUILD))
-		return blk_get_device_part_str(ifname, dev, bdesc, &info, 1);
-
-	/**
-	 * SPL does not have access to part_get_info,
-	 * so get the partition manually. Currently only
-	 * supporting MMC devices.
-	 */
-	ret = blk_get_device_by_str(ifname, dev, bdesc);
-
-	if (ret < 0)
-		return -ENODEV;
-
-	if ((*bdesc)->uclass_id != UCLASS_MMC)
-		return -EOPNOTSUPP;
-
-	udev = dev_get_parent((*bdesc)->bdev);
-	mmc = mmc_get_mmc_dev(udev);
-
-	if (IS_SD(mmc) || mmc->part_config == MMCPART_NOAVAILABLE)
-		return 0;
-
-	part = EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config);
-
-	if (part == EMMC_BOOT_PART_BOOT1 || part == EMMC_BOOT_PART_BOOT2)
-		return part;
-
-	return 0;
-}
-
-static ulong imx_qb_get_boot_device_offset(void *dev, int dev_type)
-{
-	struct blk_desc *bdesc;
-
-	switch (dev_type) {
-	case BLK_DEV:
-		bdesc = dev;
-
-		/* eMMC boot partition */
-		if (bdesc->hwpart)
-			return CONTAINER_HDR_EMMC_OFFSET;
-
-		return CONTAINER_HDR_MMCSD_OFFSET;
-	case SPI_DEV:
-		return CONTAINER_HDR_QSPI_OFFSET;
-	default:
-		return -EOPNOTSUPP;
-	}
-}
-
-static int imx_qb_parse_container(void *addr, u64 *qb_data_off)
-{
-	struct container_hdr *phdr;
-	struct boot_img_t *img_entry;
-	u32 img_type, img_end;
-	int i;
-
-	phdr = addr;
-	if (phdr->tag != 0x87 || (phdr->version != 0x0 && phdr->version != 0x2))
-		return -EINVAL;
-
-	img_entry = addr + sizeof(struct container_hdr);
-	for (i = 0; i < phdr->num_images; i++) {
-		img_type = IMG_FLAGS_IMG_TYPE(img_entry->hab_flags);
-		if (img_type == IMG_TYPE_DDR_TDATA_DUMMY && img_entry->size == 0) {
-			/* Image entry pointing to DDR Training Data */
-			*qb_data_off = img_entry->offset;
-			return 0;
-		}
-
-		img_end = img_entry->offset + img_entry->size;
-		if (i + 1 < phdr->num_images) {
-			img_entry++;
-			if (img_end + QB_STATE_LOAD_SIZE == img_entry->offset) {
-				/* hole detected */
-				*qb_data_off = img_end;
-				return 0;
-			}
-		}
-	}
-
-	return -EINVAL;
-}
-
-static int imx_qb_get_dev_qbdata_offset(void *dev, int dev_type, ulong offset,
-					u64 *qbdata_offset)
-{
-	struct blk_desc *bdesc;
-	u8 *buf;
-	ulong count;
-	int ret;
-
-	buf = malloc(CONTAINER_HDR_ALIGNMENT);
-	if (!buf)
-		return -ENOMEM;
-
-	switch (dev_type) {
-	case BLK_DEV:
-		bdesc = dev;
-
-		count = blk_dread(bdesc,
-				  offset / bdesc->blksz,
-				  CONTAINER_HDR_ALIGNMENT / bdesc->blksz,
-				  buf);
-		if (count == 0) {
-			printf("Read container image from MMC/SD failed\n");
-			ret = -EIO;
-			goto imx_qb_get_dev_qbdata_offset_exit;
-		}
-		break;
-	case SPI_DEV:
-		if (!CONFIG_IS_ENABLED(SPI)) {
-			ret = -EOPNOTSUPP;
-			goto imx_qb_get_dev_qbdata_offset_exit;
-		}
-
-		ret = spi_flash_read_dm(dev, offset,
-					CONTAINER_HDR_ALIGNMENT, buf);
-		if (ret) {
-			printf("Read container header from SPI failed\n");
-			ret = -EIO;
-			goto imx_qb_get_dev_qbdata_offset_exit;
-		}
-		break;
-	default:
-		printf("Support for device %d not enabled\n", dev_type);
-		ret = -EOPNOTSUPP;
-		goto imx_qb_get_dev_qbdata_offset_exit;
-	}
-
-	ret = imx_qb_parse_container(buf, qbdata_offset);
-
-imx_qb_get_dev_qbdata_offset_exit:
-	free(buf);
-
-	return ret;
-}
-
-static int imx_qb_get_qbdata_offset(void *dev, int dev_type,
-				    u64 *qbdata_offset)
-{
-	u64 cont_offset;
-	int ret, i;
-
-	cont_offset = imx_qb_get_boot_device_offset(dev, dev_type);
-
-	for (i = 0; i < 3; i++) {
-		ret = imx_qb_get_dev_qbdata_offset(dev, dev_type, cont_offset,
-						   qbdata_offset);
-		if (ret == 0) {
-			(*qbdata_offset) += cont_offset;
-			break;
-		}
-
-		cont_offset += CONTAINER_HDR_ALIGNMENT;
-	}
-
-	return ret;
-}
-
-static int imx_qb_blk(const char * const ifname,
-		      const char * const dev, bool save)
-{
-	struct blk_desc *bdesc;
-	u64 offset;
-	u64 load_size;
-	int part, orig_part;
-	int ret;
-
-	part = imx_qb_get_blk_boot_part(ifname, dev, &bdesc);
-
-	if (part < 0) {
-		printf("Failed to find %s %s\n", ifname, dev);
-		return -ENODEV;
-	}
-
-	orig_part = bdesc->hwpart;
-
-	ret = blk_dselect_hwpart(bdesc, part);
-	if (ret && ret != -EMEDIUMTYPE) {
-		printf("Failed to select hwpart, ret %d\n", ret);
-		return ret;
-	}
-
-	ret = imx_qb_get_qbdata_offset(bdesc, BLK_DEV, &offset);
-	if (ret) {
-		printf("get_qbdata_offset failed, ret = %d\n", ret);
-		return ret;
-	}
-
-	offset /= bdesc->blksz;
-	load_size = QB_STATE_LOAD_SIZE / bdesc->blksz;
-
-	if (save) {
-		/* QB data is stored in DDR -> can use it as buf */
-		ret = blk_dwrite(bdesc, offset, load_size,
-				 (const void *)CONFIG_QB_SAVED_STATE_BASE);
-	} else {
-		/* erase */
-		ret = blk_derase(bdesc, offset, load_size);
-	}
-
-	if (!ret) {
-		printf("Failed to write to block device\n");
-		return -EIO;
-	}
-
-	/* Return to original partition */
-	ret = blk_dselect_hwpart(bdesc, orig_part);
-	if (ret && ret != -EMEDIUMTYPE) {
-		printf("Failed to select hwpart, ret %d\n", ret);
-		return ret;
-	}
-
-	return 0;
-}
-
-static int imx_qb_spi(bool save)
-{
-	struct udevice *flash;
-	u64 offset;
-	int ret;
-
-	if (!CONFIG_IS_ENABLED(SPI)) {
-		printf("SPI not enabled\n");
-		return -EOPNOTSUPP;
-	}
-
-	ret = uclass_first_device_err(UCLASS_SPI_FLASH, &flash);
-	if (ret) {
-		printf("SPI flash not found.\n");
-		return -ENODEV;
-	}
-
-	ret = imx_qb_get_qbdata_offset(flash, SPI_DEV, &offset);
-	if (ret) {
-		printf("get_qbdata_offset failed, ret = %d\n", ret);
-		return ret;
-	}
-
-	ret = spi_flash_erase_dm(flash, offset, QB_STATE_LOAD_SIZE);
-
-	if (ret)
-		return ret;
-
-	if (!save)
-		return 0;
-
-	/* QB data is stored in DDR -> can use it as buf */
-	ret = spi_flash_write_dm(flash, offset,
-				 QB_STATE_LOAD_SIZE,
-				 (const void *)CONFIG_QB_SAVED_STATE_BASE);
-
-	return ret;
-}
-
-int imx_qb(const char *ifname, const char *dev, bool save)
-{
-	int ret;
-
-	ret = 0;
-
-	/* Try to use boot device  */
-	if (!strcmp(ifname, "auto"))
-		ret = imx_qb_get_boot_dev_str(&ifname, &dev);
-
-	if (ret)
-		return ret;
-
-	if (save && !imx_qb_check())
-		return -EINVAL;
-
-	if (!strcmp(ifname, "spi"))
-		ret = imx_qb_spi(save);
-	else
-		ret = imx_qb_blk(ifname, dev, save);
-
-	if (ret)
-		return ret;
-
-	if (!save)
-		return 0;
-
-	/**
-	 * invalidate qb_state mem so that at next boot
-	 * the check function will fail and save won't happen
-	 */
-	memset((void *)CONFIG_QB_SAVED_STATE_BASE, 0,
-	       sizeof(struct ddrphy_qb_state));
-
-	return 0;
-}
-
-void spl_imx_qb_save(void)
-{
-	/* Save QB data on current boot device */
-	if (imx_qb("auto", "", true))
-		printf("QB save failed\n");
-}

arch/arm/mach-imx/imx9/scmi/soc.c

@@ -310,13 +310,6 @@ static struct mm_region imx9_mem_map[] = {
 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 			 PTE_BLOCK_NON_SHARE |
 			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
-	}, {
-		/* QB data */
-		.virt = CONFIG_QB_SAVED_STATE_BASE,
-		.phys = CONFIG_QB_SAVED_STATE_BASE,
-		.size = 0x200000UL,	/* 2M */
-		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-			 PTE_BLOCK_OUTER_SHARE
 	}, {
 		/* empty entry to split table entry 5 if needed when TEEs are used */
 		0,
@@ -752,46 +745,6 @@ void build_info(void)
 	puts("\n");
 }
 
-int scmi_get_boot_device_offset(unsigned long *img_off)
-{
-	int ret;
-	rom_passover_t rom_data = {0};
-
-	ret = scmi_get_rom_data(&rom_data);
-	if (!ret)
-		*img_off = rom_data.img_ofs;
-
-	return 0;
-}
-
-int scmi_get_boot_stage(u8 *stage)
-{
-	int ret;
-	rom_passover_t rom_data = {0};
-
-	ret = scmi_get_rom_data(&rom_data);
-	if (!ret)
-		*stage = rom_data.boot_stage;
-
-	return ret;
-}
-
-u8 scmi_get_imgset_sel(void)
-{
-	rom_passover_t rdata = { 0 };
-	int ret = scmi_get_rom_data(&rdata);
-
-	if (!ret)
-		return rdata.img_set_sel;
-
-	return 0;
-}
-
-int boot_mode_getprisec(void)
-{
-	return !!scmi_get_imgset_sel();
-}
-
 int arch_misc_init(void)
 {
 	build_info();

arch/arm/mach-imx/imx9/soc.c

@@ -198,15 +198,26 @@ static u32 get_cpu_variant_type(u32 type)
 	bool npu_disable = !!(val & BIT(13));
 	bool core1_disable = !!(val & BIT(15));
 	u32 pack_9x9_fused = BIT(4) | BIT(5) | BIT(17) | BIT(19) | BIT(24);
-	u32 speed = (val & GENMASK(11, 6)) >> 6;
+	u32 nxp_recog = (val & GENMASK(23, 16)) >> 16;
 
 	/* For iMX91 */
 	if (type == MXC_CPU_IMX91) {
-		if ((val2 & pack_9x9_fused) == pack_9x9_fused)
+		switch (nxp_recog) {
+		case 0x9:
+		case 0xA:
 			type = MXC_CPU_IMX9111;
-
-		if (speed == 0xf) /* 800Mhz arm */
-			type += 1;
+			break;
+		case 0xD:
+		case 0xE:
+			type = MXC_CPU_IMX9121;
+			break;
+		case 0xF:
+		case 0x10:
+			type = MXC_CPU_IMX9101;
+			break;
+		default:
+			break;	/* 9131 as default */
+		}
 
 		return type;
 	}

arch/arm/mach-imx/mx6/module_fuse.c

@@ -12,54 +12,6 @@
 
 static struct fuse_entry_desc mx6_fuse_descs[] = {
 #if defined(CONFIG_MX6ULL)
-	{MODULE_TSC, "/soc/bus@2000000/touchscreen@2040000", 0x430, 22},
-	{MODULE_TSC, "/soc/bus@2000000/tsc@2040000", 0x430, 22},
-	{MODULE_ADC2, "/soc/bus@2100000/adc@219c000", 0x430, 23},
-	{MODULE_EPDC, "/soc/bus@2200000/epdc@228c000", 0x430, 24},
-	{MODULE_ESAI, "/soc/bus@2000000/spba-bus@2000000/esai@2024000", 0x430, 25},
-	{MODULE_FLEXCAN1, "/soc/bus@2000000/can@2090000", 0x430, 26},
-	{MODULE_FLEXCAN2, "/soc/bus@2000000/can@2094000", 0x430, 27},
-	{MODULE_SPDIF, "/soc/bus@2000000/spba-bus@2000000/spdif@2004000", 0x440, 2},
-	{MODULE_EIM, "/soc/bus@2100000/memory-controller@21b8000", 0x440, 3},
-	{MODULE_EIM, "/soc/bus@2100000/weim@21b8000", 0x440, 3},
-	{MODULE_SD1, "/soc/bus@2100000/mmc@2190000", 0x440, 4},
-	{MODULE_SD1, "/soc/bus@2100000/usdhc@2190000", 0x440, 4},
-	{MODULE_SD2, "/soc/bus@2100000/mmc@2194000", 0x440, 5},
-	{MODULE_SD2, "/soc/bus@2100000/usdhc@2194000", 0x440, 5},
-	{MODULE_QSPI1, "/soc/bus@2100000/spi@21e0000", 0x440, 6},
-	{MODULE_QSPI1, "/soc/bus@2100000/qspi@21e0000", 0x440, 6},
-	{MODULE_GPMI, "/soc/nand-controller@1806000", 0x440, 7},
-	{MODULE_APBHDMA, "/soc/dma-controller@1804000", 0x440, 7},
-	{MODULE_APBHDMA, "/soc/dma-apbh@1804000", 0x440, 7},
-	{MODULE_LCDIF, "/soc/bus@2100000/lcdif@21c8000", 0x440, 8},
-	{MODULE_PXP, "/soc/bus@2100000/pxp@21cc000", 0x440, 9},
-	{MODULE_CSI, "/soc/bus@2100000/csi@21c4000", 0x440, 10},
-	{MODULE_ADC1, "/soc/bus@2100000/adc@2198000", 0x440, 11},
-	{MODULE_ENET1, "/soc/bus@2100000/ethernet@2188000", 0x440, 12},
-	{MODULE_ENET2, "/soc/bus@2000000/ethernet@20b4000", 0x440, 13},
-	{MODULE_DCP, "/soc/bus@2200000/dcp@2280000", 0x440, 14},
-	{MODULE_USB_OTG2, "/soc/bus@2100000/usb@2184200", 0x440, 15},
-	{MODULE_SAI2, "/soc/bus@2000000/spba-bus@2000000/sai@202c000", 0x440, 24},
-	{MODULE_SAI3, "/soc/bus@2000000/spba-bus@2000000/sai@2030000", 0x440, 24},
-	{MODULE_DCP_CRYPTO, "/soc/bus@2200000/dcp@2280000", 0x440, 25},
-	{MODULE_UART5, "/soc/bus@2100000/serial@21f4000", 0x440, 26},
-	{MODULE_UART6, "/soc/bus@2100000/serial@21fc000", 0x440, 26},
-	{MODULE_UART7, "/soc/bus@2000000/spba-bus@2000000/serial@2018000", 0x440, 26},
-	{MODULE_UART8, "/soc/bus@2200000/serial@2288000", 0x440, 26},
-	{MODULE_PWM5, "/soc/bus@2000000/pwm@20f0000", 0x440, 27},
-	{MODULE_PWM6, "/soc/bus@2000000/pwm@20f4000", 0x440, 27},
-	{MODULE_PWM7, "/soc/bus@2000000/pwm@20f8000", 0x440, 27},
-	{MODULE_PWM8, "/soc/bus@2000000/pwm@20fc000", 0x440, 27},
-	{MODULE_ECSPI3, "/soc/bus@2000000/spba-bus@2000000/spi@2010000", 0x440, 28},
-	{MODULE_ECSPI3, "/soc/bus@2000000/spba-bus@2000000/ecspi@2010000", 0x440, 28},
-	{MODULE_ECSPI4, "/soc/bus@2000000/spba-bus@2000000/spi@2014000", 0x440, 28},
-	{MODULE_ECSPI4, "/soc/bus@2000000/spba-bus@2000000/ecspi@2014000", 0x440, 28},
-	{MODULE_I2C3, "/soc/bus@2100000/i2c@21a8000", 0x440, 29},
-	{MODULE_I2C4, "/soc/bus@2100000/i2c@21f8000", 0x440, 29},
-	{MODULE_GPT2, "/soc/bus@2000000/timer@20e8000", 0x440, 30},
-	{MODULE_GPT2, "/soc/bus@2000000/gpt@20e8000", 0x440, 30},
-	{MODULE_EPIT2, "/soc/bus@2000000/epit@20d4000", 0x440, 31},
-
 	{MODULE_TSC, "/soc/aips-bus@2000000/tsc@2040000", 0x430, 22},
 	{MODULE_ADC2, "/soc/aips-bus@2100000/adc@219c000", 0x430, 23},
 	{MODULE_EPDC, "/soc/aips-bus@2200000/epdc@228c000", 0x430, 24},
@@ -138,55 +90,6 @@ static struct fuse_entry_desc mx6_fuse_descs[] = {
 	{MODULE_GPT2, "/soc/aips-bus@02000000/gpt@020e8000", 0x440, 30},
 	{MODULE_EPIT2, "/soc/aips-bus@02000000/epit@020d4000", 0x440, 31},
 #elif defined(CONFIG_MX6UL)
-	{MODULE_TSC, "/soc/bus@2000000/touchscreen@2040000", 0x430, 22},
-	{MODULE_TSC, "/soc/bus@2000000/tsc@2040000", 0x430, 22},
-	{MODULE_ADC2, "/soc/bus@2100000/adc@219c000", 0x430, 23},
-	{MODULE_SIM1, "/soc/bus@2100000/sim@218c000", 0x430, 24},
-	{MODULE_SIM2, "/soc/bus@2100000/sim@21b4000", 0x430, 25},
-	{MODULE_FLEXCAN1, "/soc/bus@2000000/can@2090000", 0x430, 26},
-	{MODULE_FLEXCAN2, "/soc/bus@2000000/can@2094000", 0x430, 27},
-	{MODULE_SPDIF, "/soc/bus@2000000/spba-bus@2000000/spdif@2004000", 0x440, 2},
-	{MODULE_EIM, "/soc/bus@2100000/memory-controller@21b8000", 0x440, 3},
-	{MODULE_EIM, "/soc/bus@2100000/weim@21b8000", 0x440, 3},
-	{MODULE_SD1, "/soc/bus@2100000/mmc@2190000", 0x440, 4},
-	{MODULE_SD1, "/soc/bus@2100000/usdhc@2190000", 0x440, 4},
-	{MODULE_SD2, "/soc/bus@2100000/mmc@2194000", 0x440, 5},
-	{MODULE_SD2, "/soc/bus@2100000/usdhc@2194000", 0x440, 5},
-	{MODULE_QSPI1, "/soc/bus@2100000/spi@21e0000", 0x440, 6},
-	{MODULE_QSPI1, "/soc/bus@2100000/qspi@21e0000", 0x440, 6},
-	{MODULE_GPMI, "/soc/nand-controller@1806000", 0x440, 7},
-	{MODULE_APBHDMA, "/soc/dma-controller@1804000", 0x440, 7},
-	{MODULE_APBHDMA, "/soc/dma-apbh@1804000", 0x440, 7},
-	{MODULE_LCDIF, "/soc/bus@2100000/lcdif@21c8000", 0x440, 8},
-	{MODULE_PXP, "/soc/bus@2100000/pxp@21cc000", 0x440, 9},
-	{MODULE_CSI, "/soc/bus@2100000/csi@21c4000", 0x440, 10},
-	{MODULE_ADC1, "/soc/bus@2100000/adc@2198000", 0x440, 11},
-	{MODULE_ENET1, "/soc/bus@2100000/ethernet@2188000", 0x440, 12},
-	{MODULE_ENET2, "/soc/bus@2000000/ethernet@20b4000", 0x440, 13},
-	{MODULE_CAAM, "/soc/bus@2100000/crypto@2140000", 0x440, 14},
-	{MODULE_CAAM, "/soc/bus@2100000/caam@2140000", 0x440, 14},
-	{MODULE_USB_OTG2, "/soc/bus@2100000/usb@2184200", 0x440, 15},
-	{MODULE_SAI2, "/soc/bus@2000000/spba-bus@2000000/sai@202c000", 0x440, 24},
-	{MODULE_SAI3, "/soc/bus@2000000/spba-bus@2000000/sai@2030000", 0x440, 24},
-	{MODULE_BEE, "/soc/bus@2000000/bee@2044000", 0x440, 25},
-	{MODULE_UART5, "/soc/bus@2100000/serial@21f4000", 0x440, 26},
-	{MODULE_UART6, "/soc/bus@2100000/serial@21fc000", 0x440, 26},
-	{MODULE_UART7, "/soc/bus@2000000/spba-bus@2000000/serial@2018000", 0x440, 26},
-	{MODULE_UART8, "/soc/bus@2000000/spba-bus@2000000/serial@2024000", 0x440, 26},
-	{MODULE_PWM5, "/soc/bus@2000000/pwm@20f0000", 0x440, 27},
-	{MODULE_PWM6, "/soc/bus@2000000/pwm@20f4000", 0x440, 27},
-	{MODULE_PWM7, "/soc/bus@2000000/pwm@20f8000", 0x440, 27},
-	{MODULE_PWM8, "/soc/bus@2000000/pwm@20fc000", 0x440, 27},
-	{MODULE_ECSPI3, "/soc/bus@2000000/spba-bus@2000000/spi@2010000", 0x440, 28},
-	{MODULE_ECSPI3, "/soc/bus@2000000/spba-bus@2000000/ecspi@2010000", 0x440, 28},
-	{MODULE_ECSPI4, "/soc/bus@2000000/spba-bus@2000000/spi@2014000", 0x440, 28},
-	{MODULE_ECSPI4, "/soc/bus@2000000/spba-bus@2000000/ecspi@2014000", 0x440, 28},
-	{MODULE_I2C3, "/soc/bus@2100000/i2c@21a8000", 0x440, 29},
-	{MODULE_I2C4, "/soc/bus@2100000/i2c@21f8000", 0x440, 29},
-	{MODULE_GPT2, "/soc/bus@2000000/timer@20e8000", 0x440, 30},
-	{MODULE_GPT2, "/soc/bus@2000000/gpt@20e8000", 0x440, 30},
-	{MODULE_EPIT2, "/soc/bus@2000000/epit@20d4000", 0x440, 31},
-
 	{MODULE_TSC, "/soc/aips-bus@2000000/tsc@2040000", 0x430, 22},
 	{MODULE_ADC2, "/soc/aips-bus@2100000/adc@219c000", 0x430, 23},
 	{MODULE_SIM1, "/soc/aips-bus@2100000/sim@218c000", 0x430, 24},

arch/arm/mach-imx/priblob.c

@@ -10,7 +10,6 @@
  * to decrypt an encrypted boot image.
  */
 
-#include <config.h>
 #include <asm/io.h>
 #include <command.h>
 #include <fsl_sec.h>

arch/arm/mach-omap2/am33xx/board.c

@@ -266,15 +266,9 @@ int arch_misc_init(void)
 	struct udevice *dev;
 	int ret;
 
-	/*
-	 * The MUSB wrapper driver is bound as a MISC device, so probe here
-	 * to register the musb device early.
-	 */
-	if (IS_ENABLED(CONFIG_USB_MUSB_TI)) {
-		ret = uclass_first_device_err(UCLASS_MISC, &dev);
-		if (ret)
-			return ret;
-	}
+	ret = uclass_first_device_err(UCLASS_MISC, &dev);
+	if (ret)
+		return ret;
 
 #if defined(CONFIG_DM_ETH) && defined(CONFIG_USB_ETHER)
 	usb_ether_init();

arch/arm/mach-renesas/Kconfig.rcar3

@@ -164,12 +164,20 @@ config TARGET_ULCB
 	help
 	  Support for Renesas R-Car Gen3 ULCB platform
 
+config TARGET_GEIST
+	bool "Geist board"
+	imply R8A77965
+	imply SYS_MALLOC_F
+	help
+	  Support for Renesas R-Car Gen3 Geist platform
+
 endchoice
 
 source "board/renesas/condor/Kconfig"
 source "board/renesas/draak/Kconfig"
 source "board/renesas/eagle/Kconfig"
 source "board/renesas/ebisu/Kconfig"
+source "board/renesas/geist/Kconfig"
 source "board/renesas/salvator-x/Kconfig"
 source "board/renesas/ulcb/Kconfig"
 source "board/renesas/v3hsk/Kconfig"

arch/arm/mach-renesas/cpu_info.c

@@ -114,6 +114,8 @@ int arch_misc_init(void)
 
 int print_cpuinfo(void)
 {
+	const uintptr_t pfc_base = 0xe6060000;
+	void __iomem *rcar_m3nm3l_ident = (void __iomem *)pfc_base + 0x800;
 	int i = renesas_cpuinfo_idx();
 
 	if (renesas_cpuinfo[i].cpu_type == RENESAS_CPU_TYPE_R8A7796 &&
@@ -123,6 +125,17 @@ int print_cpuinfo(void)
 		return 0;
 	}
 
+	/*
+	 * M3Le PRR ID is the same as M3N , but PFC register 0x800 reads 0
+	 * on M3N and 1 on M3Le. Use this to discern M3Le from M3N .
+	 */
+	if (renesas_cpuinfo[i].cpu_type == RENESAS_CPU_TYPE_R8A77965 &&
+	    readl(rcar_m3nm3l_ident) == 1) {
+		printf("CPU:   Renesas Electronics R8A779MD rev %d.%d\n",
+		       renesas_get_cpu_rev_integer(), renesas_get_cpu_rev_fraction());
+		return 0;
+	}
+
 	printf("CPU:   Renesas Electronics %s rev %d.%d\n",
 		get_cpu_name(i), renesas_get_cpu_rev_integer(),
 		renesas_get_cpu_rev_fraction());

arch/arm/mach-stm32mp/include/mach/sys_proto.h

@@ -61,20 +61,20 @@
 /* ID for STM32MP25x = Device Part Number (RPN) (bit31:0) */
 #define CPU_STM32MP257Cxx	0x00002000
 #define CPU_STM32MP255Cxx	0x00082000
-#define CPU_STM32MP253Cxx	0x000B2004
-#define CPU_STM32MP251Cxx	0x000B3065
+#define CPU_STM32MP253Cxx	0x000B300C
+#define CPU_STM32MP251Cxx	0x000B306D
 #define CPU_STM32MP257Axx	0x40002E00
 #define CPU_STM32MP255Axx	0x40082E00
-#define CPU_STM32MP253Axx	0x400B2E04
-#define CPU_STM32MP251Axx	0x400B3E65
+#define CPU_STM32MP253Axx	0x400B3E0C
+#define CPU_STM32MP251Axx	0x400B3E6D
 #define CPU_STM32MP257Fxx	0x80002000
 #define CPU_STM32MP255Fxx	0x80082000
-#define CPU_STM32MP253Fxx	0x800B2004
-#define CPU_STM32MP251Fxx	0x800B3065
+#define CPU_STM32MP253Fxx	0x800B300C
+#define CPU_STM32MP251Fxx	0x800B306D
 #define CPU_STM32MP257Dxx	0xC0002E00
 #define CPU_STM32MP255Dxx	0xC0082E00
-#define CPU_STM32MP253Dxx	0xC00B2E04
-#define CPU_STM32MP251Dxx	0xC00B3E65
+#define CPU_STM32MP253Dxx	0xC00B3E0C
+#define CPU_STM32MP251Dxx	0xC00B3E6D
 
 /* return CPU_STMP32MP...Xxx constants */
 u32 get_cpu_type(void);

arch/m68k/Kconfig

@@ -196,14 +196,12 @@ config TARGET_STMARK2
         select M54418
 
 config TARGET_QEMU_M68K
-	bool "Support QEMU m68k virt"
-	select M68040
-	select BOARD_EARLY_INIT_R
-	select VIRTIO_MMIO
-	imply CMD_DM
-	help
-	  This target supports the QEMU m68k virtual machine (-M virt).
-	  It simulates a Motorola 68040 CPU with Goldfish peripherals.
+    bool "Support QEMU m68k virt"
+    select M68040
+    imply CMD_DM
+    help
+      This target supports the QEMU m68k virtual machine (-M virt).
+      It simulates a Motorola 68040 CPU with Goldfish peripherals.
 
 endchoice
 

arch/m68k/include/asm/io.h

@@ -23,27 +23,18 @@
 #define __raw_writew(w,addr) ((*(volatile u16 *) (addr)) = (w))
 #define __raw_writel(l,addr) ((*(volatile u32 *) (addr)) = (l))
 
-#define readb(addr)	in_8((volatile u8 *)(addr))
-#define writeb(b, addr)	out_8((volatile u8 *)(addr), (b))
-#ifdef CONFIG_M680x0
-/*
- * For classic m68k these work the same way as Linux:
- * Read a little endian value, swap to the CPU endian.
- */
-#define readw(addr)	in_le16((volatile u16 *)(addr))
-#define readl(addr)	in_le32((volatile u32 *)(addr))
-#define writew(b, addr)	out_le16((volatile u16 *)(addr), (b))
-#define writel(b, addr)	out_le32((volatile u32 *)(addr), (b))
+#define readb(addr)		in_8((volatile u8 *)(addr))
+#define writeb(b,addr)		out_8((volatile u8 *)(addr), (b))
+#if !defined(__BIG_ENDIAN)
+#define readw(addr)		(*(volatile u16 *) (addr))
+#define readl(addr)		(*(volatile u32 *) (addr))
+#define writew(b,addr)		((*(volatile u16 *) (addr)) = (b))
+#define writel(b,addr)		((*(volatile u32 *) (addr)) = (b))
 #else
-/*
- * For coldfire these read a big endian value and use it
- * as-is. This means that for little endian devices on the
- * bus like PCI device these won't work as expected currently.
- */
-#define readw(addr)	in_be16((volatile u16 *)(addr))
-#define readl(addr)	in_be32((volatile u32 *)(addr))
-#define writew(b, addr)	out_be16((volatile u16 *)(addr), (b))
-#define writel(b, addr)	out_be32((volatile u32 *)(addr), (b))
+#define readw(addr)		in_be16((volatile u16 *)(addr))
+#define readl(addr)		in_be32((volatile u32 *)(addr))
+#define writew(b,addr)		out_be16((volatile u16 *)(addr),(b))
+#define writel(b,addr)		out_be32((volatile u32 *)(addr),(b))
 #endif
 
 /*

arch/x86/cpu/apollolake/cpu_spl.c

@@ -6,7 +6,7 @@
  */
 
 #include <dm.h>
-#include <cros_ec.h>
+#include <ec_commands.h>
 #include <init.h>
 #include <log.h>
 #include <spi_flash.h>

board/boundary/nitrogen6x/nitrogen6x.c

@@ -909,10 +909,8 @@ static const struct boot_mode board_boot_modes[] = {
 
 int misc_init_r(void)
 {
-#if defined(CONFIG_VIDEO_IPUV3)
 	gpio_request(RGB_BACKLIGHT_GP, "lvds backlight");
 	gpio_request(LVDS_BACKLIGHT_GP, "lvds backlight");
-#endif
 	gpio_request(GP_USB_OTG_PWR, "usbotg power");
 	gpio_request(IMX_GPIO_NR(7, 12), "usbh1 hub reset");
 	gpio_request(IMX_GPIO_NR(2, 2), "back");

board/compulab/cm_fx6/cm_fx6.c

@@ -778,7 +778,7 @@ static int sata_imx_remove(struct udevice *dev)
 	return 0;
 }
 
-static const struct ahci_ops sata_imx_ops = {
+struct ahci_ops sata_imx_ops = {
 	.port_status = dwc_ahsata_port_status,
 	.reset	= dwc_ahsata_bus_reset,
 	.scan	= dwc_ahsata_scan,

board/emulation/qemu-m68k/qemu-m68k.c

@@ -14,14 +14,9 @@
 #include <asm/bootinfo.h>
 #include <asm/global_data.h>
 #include <asm/io.h>
-#include <dm.h>
-#include <dm/device-internal.h>
-#include <dm/lists.h>
 #include <dm/platdata.h>
-#include <dm/root.h>
 #include <linux/errno.h>
 #include <linux/sizes.h>
-#include <virtio_mmio.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -30,38 +25,6 @@ static struct goldfish_rtc_plat rtc_plat;
 static struct goldfish_timer_plat timer_plat;
 static struct qemu_virt_ctrl_plat reset_plat;
 
-#define VIRTIO_MMIO_NUM	128
-#define VIRTIO_MMIO_SZ	0x200
-
-static struct virtio_mmio_plat virtio_mmio_plat[VIRTIO_MMIO_NUM];
-static char virtio_mmio_names[VIRTIO_MMIO_NUM][11];
-static phys_addr_t virtio_mmio_base;
-
-static int create_virtio_mmios(void)
-{
-	struct driver *drv;
-	int i, ret;
-
-	if (!virtio_mmio_base)
-		return -ENODEV;
-
-	drv = lists_driver_lookup_name("virtio-mmio");
-	if (!drv)
-		return -ENOENT;
-
-	for (i = 0; i < VIRTIO_MMIO_NUM; i++) {
-		virtio_mmio_plat[i].base = virtio_mmio_base + (VIRTIO_MMIO_SZ * i);
-		sprintf(virtio_mmio_names[i], "virtio-%d", i);
-
-		ret = device_bind(dm_root(), drv, virtio_mmio_names[i],
-				  &virtio_mmio_plat[i], ofnode_null(), NULL);
-		if (ret)
-			return ret;
-	}
-
-	return 0;
-}
-
 /*
  * Theoretical limit derivation:
  * Max Bootinfo Size (Standard Page) = 4096 bytes
@@ -102,9 +65,6 @@ static void parse_bootinfo(void)
 		case BI_VIRT_CTRL_BASE:
 			reset_plat.reg = base;
 			break;
-		case BI_VIRT_VIRTIO_BASE:
-			virtio_mmio_base = base;
-			break;
 		case BI_MEMCHUNK:
 			gd->ram_size = record->data[1];
 			break;
@@ -120,11 +80,6 @@ int board_early_init_f(void)
 	return 0;
 }
 
-int board_early_init_r(void)
-{
-	return create_virtio_mmios();
-}
-
 int checkboard(void)
 {
 	puts("Board: QEMU m68k virt\n");

board/kontron/pitx_imx8m/MAINTAINERS

@@ -1,6 +1,7 @@
 Kontron pITX-imx8m Board
 M:	Heiko Thiery <heiko.thiery@gmail.com>
 S:	Maintained
+F:	arch/arm/dts/imx8mq-kontron-pitx-imx8m*
 F:	board/kontron/pitx_imx8m/*
 F:	include/configs/kontron_pitx_imx8m.h
 F:	configs/kontron_pitx_imx8m_defconfig

board/nxp/imx8mp_evk/spl.c

@@ -65,7 +65,7 @@ int power_init_board(void)
 	 * Enable DVS control through PMIC_STBY_REQ and
 	 * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H)
 	 */
-	if (IS_ENABLED(CONFIG_IMX8M_VDD_SOC_850MV))
+	if (CONFIG_IS_ENABLED(IMX8M_VDD_SOC_850MV))
 		pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14);
 	else
 		pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C);

board/nxp/imx94_evk/spl.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2025-2026 NXP
+ * Copyright 2025 NXP
  */
 
 #include <hang.h>
@@ -14,7 +14,6 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/mach-imx/boot_mode.h>
 #include <asm/mach-imx/ele_api.h>
-#include <asm/mach-imx/qb.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -45,9 +44,6 @@ void spl_board_init(void)
 	ret = ele_start_rng();
 	if (ret)
 		printf("Fail to start RNG: %d\n", ret);
-
-	if (IS_ENABLED(CONFIG_SPL_IMX_QB))
-		spl_imx_qb_save();
 }
 
 static void xspi_nor_reset(void)

board/nxp/imx952_evk/spl.c

@@ -8,7 +8,6 @@
 #include <asm/gpio.h>
 #include <asm/mach-imx/boot_mode.h>
 #include <asm/mach-imx/ele_api.h>
-#include <asm/mach-imx/qb.h>
 #include <asm/sections.h>
 #include <hang.h>
 #include <init.h>
@@ -45,9 +44,6 @@ void spl_board_init(void)
 	ret = ele_start_rng();
 	if (ret)
 		printf("Fail to start RNG: %d\n", ret);
-
-	if (IS_ENABLED(CONFIG_SPL_IMX_QB))
-		spl_imx_qb_save();
 }
 
 static void xspi_nor_reset(void)

board/nxp/imx95_evk/spl.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2025-2026 NXP
+ * Copyright 2025 NXP
  */
 
 #include <hang.h>
@@ -13,7 +13,6 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/mach-imx/boot_mode.h>
 #include <asm/mach-imx/ele_api.h>
-#include <asm/mach-imx/qb.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -42,9 +41,6 @@ void spl_board_init(void)
 	ret = ele_start_rng();
 	if (ret)
 		printf("Fail to start RNG: %d\n", ret);
-
-	if (IS_ENABLED(CONFIG_SPL_IMX_QB))
-		spl_imx_qb_save();
 }
 
 void board_init_f(ulong dummy)

board/phytec/phycore_am62x/tifs-rm-cfg.yaml

@@ -1,867 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-# Copyright (C) 2022-2026 Texas Instruments Incorporated - https://www.ti.com/
-#
-# Resource management configuration for AM62X
-#
-
----
-
-tifs-rm-cfg:
-    rm_boardcfg:
-        rev:
-            boardcfg_abi_maj: 0x0
-            boardcfg_abi_min: 0x1
-        host_cfg:
-            subhdr:
-                magic: 0x4C41
-                size: 356
-            host_cfg_entries:
-                -  # 1
-                    host_id: 12
-                    allowed_atype: 0x2A
-                    allowed_qos: 0xAAAA
-                    allowed_orderid: 0xAAAAAAAA
-                    allowed_priority: 0xAAAA
-                    allowed_sched_priority: 0xAA
-                -  # 2
-                    host_id: 30
-                    allowed_atype: 0x2A
-                    allowed_qos: 0xAAAA
-                    allowed_orderid: 0xAAAAAAAA
-                    allowed_priority: 0xAAAA
-                    allowed_sched_priority: 0xAA
-                -  # 3
-                    host_id: 36
-                    allowed_atype: 0x2A
-                    allowed_qos: 0xAAAA
-                    allowed_orderid: 0xAAAAAAAA
-                    allowed_priority: 0xAAAA
-                    allowed_sched_priority: 0xAA
-                -  # 4
-                    host_id: 0
-                    allowed_atype: 0
-                    allowed_qos: 0
-                    allowed_orderid: 0
-                    allowed_priority: 0
-                    allowed_sched_priority: 0
-                -  # 5
-                    host_id: 0
-                    allowed_atype: 0
-                    allowed_qos: 0
-                    allowed_orderid: 0
-                    allowed_priority: 0
-                    allowed_sched_priority: 0
-                -  # 6
-                    host_id: 0
-                    allowed_atype: 0
-                    allowed_qos: 0
-                    allowed_orderid: 0
-                    allowed_priority: 0
-                    allowed_sched_priority: 0
-                -  # 7
-                    host_id: 0
-                    allowed_atype: 0
-                    allowed_qos: 0
-                    allowed_orderid: 0
-                    allowed_priority: 0
-                    allowed_sched_priority: 0
-                -  # 8
-                    host_id: 0
-                    allowed_atype: 0
-                    allowed_qos: 0
-                    allowed_orderid: 0
-                    allowed_priority: 0
-                    allowed_sched_priority: 0
-                -  # 9
-                    host_id: 0
-                    allowed_atype: 0
-                    allowed_qos: 0
-                    allowed_orderid: 0
-                    allowed_priority: 0
-                    allowed_sched_priority: 0
-                -  # 10
-                    host_id: 0
-                    allowed_atype: 0
-                    allowed_qos: 0
-                    allowed_orderid: 0
-                    allowed_priority: 0
-                    allowed_sched_priority: 0
-                -  # 11
-                    host_id: 0
-                    allowed_atype: 0
-                    allowed_qos: 0
-                    allowed_orderid: 0
-                    allowed_priority: 0
-                    allowed_sched_priority: 0
-                -  # 12
-                    host_id: 0
-                    allowed_atype: 0
-                    allowed_qos: 0
-                    allowed_orderid: 0
-                    allowed_priority: 0
-                    allowed_sched_priority: 0
-                -  # 13
-                    host_id: 0
-                    allowed_atype: 0
-                    allowed_qos: 0
-                    allowed_orderid: 0
-                    allowed_priority: 0
-                    allowed_sched_priority: 0
-                -  # 14
-                    host_id: 0
-                    allowed_atype: 0
-                    allowed_qos: 0
-                    allowed_orderid: 0
-                    allowed_priority: 0
-                    allowed_sched_priority: 0
-                -  # 15
-                    host_id: 0
-                    allowed_atype: 0
-                    allowed_qos: 0
-                    allowed_orderid: 0
-                    allowed_priority: 0
-                    allowed_sched_priority: 0
-                -  # 16
-                    host_id: 0
-                    allowed_atype: 0
-                    allowed_qos: 0
-                    allowed_orderid: 0
-                    allowed_priority: 0
-                    allowed_sched_priority: 0
-                -  # 17
-                    host_id: 0
-                    allowed_atype: 0
-                    allowed_qos: 0
-                    allowed_orderid: 0
-                    allowed_priority: 0
-                    allowed_sched_priority: 0
-                -  # 18
-                    host_id: 0
-                    allowed_atype: 0
-                    allowed_qos: 0
-                    allowed_orderid: 0
-                    allowed_priority: 0
-                    allowed_sched_priority: 0
-                -  # 19
-                    host_id: 0
-                    allowed_atype: 0
-                    allowed_qos: 0
-                    allowed_orderid: 0
-                    allowed_priority: 0
-                    allowed_sched_priority: 0
-                -  # 20
-                    host_id: 0
-                    allowed_atype: 0
-                    allowed_qos: 0
-                    allowed_orderid: 0
-                    allowed_priority: 0
-                    allowed_sched_priority: 0
-                -  # 21
-                    host_id: 0
-                    allowed_atype: 0
-                    allowed_qos: 0
-                    allowed_orderid: 0
-                    allowed_priority: 0
-                    allowed_sched_priority: 0
-                -  # 22
-                    host_id: 0
-                    allowed_atype: 0
-                    allowed_qos: 0
-                    allowed_orderid: 0
-                    allowed_priority: 0
-                    allowed_sched_priority: 0
-                -  # 23
-                    host_id: 0
-                    allowed_atype: 0
-                    allowed_qos: 0
-                    allowed_orderid: 0
-                    allowed_priority: 0
-                    allowed_sched_priority: 0
-                -  # 24
-                    host_id: 0
-                    allowed_atype: 0
-                    allowed_qos: 0
-                    allowed_orderid: 0
-                    allowed_priority: 0
-                    allowed_sched_priority: 0
-                -  # 25
-                    host_id: 0
-                    allowed_atype: 0
-                    allowed_qos: 0
-                    allowed_orderid: 0
-                    allowed_priority: 0
-                    allowed_sched_priority: 0
-                -  # 26
-                    host_id: 0
-                    allowed_atype: 0
-                    allowed_qos: 0
-                    allowed_orderid: 0
-                    allowed_priority: 0
-                    allowed_sched_priority: 0
-                -  # 27
-                    host_id: 0
-                    allowed_atype: 0
-                    allowed_qos: 0
-                    allowed_orderid: 0
-                    allowed_priority: 0
-                    allowed_sched_priority: 0
-                -  # 28
-                    host_id: 0
-                    allowed_atype: 0
-                    allowed_qos: 0
-                    allowed_orderid: 0
-                    allowed_priority: 0
-                    allowed_sched_priority: 0
-                -  # 29
-                    host_id: 0
-                    allowed_atype: 0
-                    allowed_qos: 0
-                    allowed_orderid: 0
-                    allowed_priority: 0
-                    allowed_sched_priority: 0
-                -  # 30
-                    host_id: 0
-                    allowed_atype: 0
-                    allowed_qos: 0
-                    allowed_orderid: 0
-                    allowed_priority: 0
-                    allowed_sched_priority: 0
-                -  # 31
-                    host_id: 0
-                    allowed_atype: 0
-                    allowed_qos: 0
-                    allowed_orderid: 0
-                    allowed_priority: 0
-                    allowed_sched_priority: 0
-                -  # 32
-                    host_id: 0
-                    allowed_atype: 0
-                    allowed_qos: 0
-                    allowed_orderid: 0
-                    allowed_priority: 0
-                    allowed_sched_priority: 0
-        resasg:
-            subhdr:
-                magic: 0x7B25
-                size: 8
-            resasg_entries_size: 824
-            reserved: 0
-    resasg_entries:
-        -
-            start_resource: 0
-            num_resource: 18
-            type: 1677
-            host_id: 12
-            reserved: 0
-        -
-            start_resource: 18
-            num_resource: 6
-            type: 1677
-            host_id: 35
-            reserved: 0
-        -
-            start_resource: 18
-            num_resource: 6
-            type: 1677
-            host_id: 36
-            reserved: 0
-        -
-            start_resource: 24
-            num_resource: 2
-            type: 1677
-            host_id: 30
-            reserved: 0
-        -
-            start_resource: 26
-            num_resource: 6
-            type: 1677
-            host_id: 128
-            reserved: 0
-        -
-            start_resource: 54
-            num_resource: 18
-            type: 1678
-            host_id: 12
-            reserved: 0
-        -
-            start_resource: 72
-            num_resource: 6
-            type: 1678
-            host_id: 35
-            reserved: 0
-        -
-            start_resource: 72
-            num_resource: 6
-            type: 1678
-            host_id: 36
-            reserved: 0
-        -
-            start_resource: 78
-            num_resource: 2
-            type: 1678
-            host_id: 30
-            reserved: 0
-        -
-            start_resource: 80
-            num_resource: 2
-            type: 1678
-            host_id: 128
-            reserved: 0
-        -
-            start_resource: 32
-            num_resource: 12
-            type: 1679
-            host_id: 12
-            reserved: 0
-        -
-            start_resource: 44
-            num_resource: 6
-            type: 1679
-            host_id: 35
-            reserved: 0
-        -
-            start_resource: 44
-            num_resource: 6
-            type: 1679
-            host_id: 36
-            reserved: 0
-        -
-            start_resource: 50
-            num_resource: 2
-            type: 1679
-            host_id: 30
-            reserved: 0
-        -
-            start_resource: 52
-            num_resource: 2
-            type: 1679
-            host_id: 128
-            reserved: 0
-        -
-            start_resource: 0
-            num_resource: 18
-            type: 1696
-            host_id: 12
-            reserved: 0
-        -
-            start_resource: 18
-            num_resource: 6
-            type: 1696
-            host_id: 35
-            reserved: 0
-        -
-            start_resource: 18
-            num_resource: 6
-            type: 1696
-            host_id: 36
-            reserved: 0
-        -
-            start_resource: 24
-            num_resource: 2
-            type: 1696
-            host_id: 30
-            reserved: 0
-        -
-            start_resource: 26
-            num_resource: 6
-            type: 1696
-            host_id: 128
-            reserved: 0
-        -
-            start_resource: 0
-            num_resource: 18
-            type: 1697
-            host_id: 12
-            reserved: 0
-        -
-            start_resource: 18
-            num_resource: 6
-            type: 1697
-            host_id: 35
-            reserved: 0
-        -
-            start_resource: 18
-            num_resource: 6
-            type: 1697
-            host_id: 36
-            reserved: 0
-        -
-            start_resource: 24
-            num_resource: 2
-            type: 1697
-            host_id: 30
-            reserved: 0
-        -
-            start_resource: 26
-            num_resource: 2
-            type: 1697
-            host_id: 128
-            reserved: 0
-        -
-            start_resource: 0
-            num_resource: 12
-            type: 1698
-            host_id: 12
-            reserved: 0
-        -
-            start_resource: 12
-            num_resource: 6
-            type: 1698
-            host_id: 35
-            reserved: 0
-        -
-            start_resource: 12
-            num_resource: 6
-            type: 1698
-            host_id: 36
-            reserved: 0
-        -
-            start_resource: 18
-            num_resource: 2
-            type: 1698
-            host_id: 30
-            reserved: 0
-        -
-            start_resource: 20
-            num_resource: 2
-            type: 1698
-            host_id: 128
-            reserved: 0
-        -
-            start_resource: 5
-            num_resource: 35
-            type: 1802
-            host_id: 12
-            reserved: 0
-        -
-            start_resource: 44
-            num_resource: 35
-            type: 1802
-            host_id: 35
-            reserved: 0
-        -
-            start_resource: 44
-            num_resource: 35
-            type: 1802
-            host_id: 36
-            reserved: 0
-        -
-            start_resource: 168
-            num_resource: 7
-            type: 1802
-            host_id: 30
-            reserved: 0
-        -
-            start_resource: 0
-            num_resource: 1024
-            type: 1807
-            host_id: 128
-            reserved: 0
-        -
-            start_resource: 4096
-            num_resource: 29
-            type: 1808
-            host_id: 128
-            reserved: 0
-        -
-            start_resource: 4608
-            num_resource: 99
-            type: 1809
-            host_id: 128
-            reserved: 0
-        -
-            start_resource: 5120
-            num_resource: 24
-            type: 1810
-            host_id: 128
-            reserved: 0
-        -
-            start_resource: 5632
-            num_resource: 51
-            type: 1811
-            host_id: 128
-            reserved: 0
-        -
-            start_resource: 6144
-            num_resource: 51
-            type: 1812
-            host_id: 128
-            reserved: 0
-        -
-            start_resource: 6656
-            num_resource: 51
-            type: 1813
-            host_id: 128
-            reserved: 0
-        -
-            start_resource: 8192
-            num_resource: 32
-            type: 1814
-            host_id: 128
-            reserved: 0
-        -
-            start_resource: 8704
-            num_resource: 32
-            type: 1815
-            host_id: 128
-            reserved: 0
-        -
-            start_resource: 9216
-            num_resource: 32
-            type: 1816
-            host_id: 128
-            reserved: 0
-        -
-            start_resource: 9728
-            num_resource: 22
-            type: 1817
-            host_id: 128
-            reserved: 0
-        -
-            start_resource: 10240
-            num_resource: 22
-            type: 1818
-            host_id: 128
-            reserved: 0
-        -
-            start_resource: 10752
-            num_resource: 22
-            type: 1819
-            host_id: 128
-            reserved: 0
-        -
-            start_resource: 11264
-            num_resource: 28
-            type: 1820
-            host_id: 128
-            reserved: 0
-        -
-            start_resource: 11776
-            num_resource: 28
-            type: 1821
-            host_id: 128
-            reserved: 0
-        -
-            start_resource: 12288
-            num_resource: 28
-            type: 1822
-            host_id: 128
-            reserved: 0
-        -
-            start_resource: 0
-            num_resource: 10
-            type: 1936
-            host_id: 12
-            reserved: 0
-        -
-            start_resource: 10
-            num_resource: 3
-            type: 1936
-            host_id: 35
-            reserved: 0
-        -
-            start_resource: 10
-            num_resource: 3
-            type: 1936
-            host_id: 36
-            reserved: 0
-        -
-            start_resource: 13
-            num_resource: 3
-            type: 1936
-            host_id: 30
-            reserved: 0
-        -
-            start_resource: 16
-            num_resource: 3
-            type: 1936
-            host_id: 128
-            reserved: 0
-        -
-            start_resource: 19
-            num_resource: 64
-            type: 1937
-            host_id: 12
-            reserved: 0
-        -
-            start_resource: 19
-            num_resource: 64
-            type: 1937
-            host_id: 36
-            reserved: 0
-        -
-            start_resource: 83
-            num_resource: 8
-            type: 1938
-            host_id: 12
-            reserved: 0
-        -
-            start_resource: 91
-            num_resource: 8
-            type: 1939
-            host_id: 12
-            reserved: 0
-        -
-            start_resource: 99
-            num_resource: 10
-            type: 1942
-            host_id: 12
-            reserved: 0
-        -
-            start_resource: 109
-            num_resource: 3
-            type: 1942
-            host_id: 35
-            reserved: 0
-        -
-            start_resource: 109
-            num_resource: 3
-            type: 1942
-            host_id: 36
-            reserved: 0
-        -
-            start_resource: 112
-            num_resource: 3
-            type: 1942
-            host_id: 30
-            reserved: 0
-        -
-            start_resource: 115
-            num_resource: 3
-            type: 1942
-            host_id: 128
-            reserved: 0
-        -
-            start_resource: 118
-            num_resource: 16
-            type: 1943
-            host_id: 12
-            reserved: 0
-        -
-            start_resource: 118
-            num_resource: 16
-            type: 1943
-            host_id: 36
-            reserved: 0
-        -
-            start_resource: 134
-            num_resource: 8
-            type: 1944
-            host_id: 12
-            reserved: 0
-        -
-            start_resource: 134
-            num_resource: 8
-            type: 1945
-            host_id: 12
-            reserved: 0
-        -
-            start_resource: 142
-            num_resource: 8
-            type: 1946
-            host_id: 12
-            reserved: 0
-        -
-            start_resource: 142
-            num_resource: 8
-            type: 1947
-            host_id: 12
-            reserved: 0
-        -
-            start_resource: 0
-            num_resource: 10
-            type: 1955
-            host_id: 12
-            reserved: 0
-        -
-            start_resource: 10
-            num_resource: 3
-            type: 1955
-            host_id: 35
-            reserved: 0
-        -
-            start_resource: 10
-            num_resource: 3
-            type: 1955
-            host_id: 36
-            reserved: 0
-        -
-            start_resource: 13
-            num_resource: 3
-            type: 1955
-            host_id: 30
-            reserved: 0
-        -
-            start_resource: 16
-            num_resource: 3
-            type: 1955
-            host_id: 128
-            reserved: 0
-        -
-            start_resource: 19
-            num_resource: 8
-            type: 1956
-            host_id: 12
-            reserved: 0
-        -
-            start_resource: 19
-            num_resource: 8
-            type: 1956
-            host_id: 36
-            reserved: 0
-        -
-            start_resource: 27
-            num_resource: 1
-            type: 1957
-            host_id: 12
-            reserved: 0
-        -
-            start_resource: 28
-            num_resource: 1
-            type: 1958
-            host_id: 12
-            reserved: 0
-        -
-            start_resource: 0
-            num_resource: 10
-            type: 1961
-            host_id: 12
-            reserved: 0
-        -
-            start_resource: 10
-            num_resource: 3
-            type: 1961
-            host_id: 35
-            reserved: 0
-        -
-            start_resource: 10
-            num_resource: 3
-            type: 1961
-            host_id: 36
-            reserved: 0
-        -
-            start_resource: 13
-            num_resource: 3
-            type: 1961
-            host_id: 30
-            reserved: 0
-        -
-            start_resource: 16
-            num_resource: 3
-            type: 1961
-            host_id: 128
-            reserved: 0
-        -
-            start_resource: 0
-            num_resource: 10
-            type: 1962
-            host_id: 12
-            reserved: 0
-        -
-            start_resource: 10
-            num_resource: 3
-            type: 1962
-            host_id: 35
-            reserved: 0
-        -
-            start_resource: 10
-            num_resource: 3
-            type: 1962
-            host_id: 36
-            reserved: 0
-        -
-            start_resource: 13
-            num_resource: 3
-            type: 1962
-            host_id: 30
-            reserved: 0
-        -
-            start_resource: 16
-            num_resource: 3
-            type: 1962
-            host_id: 128
-            reserved: 0
-        -
-            start_resource: 19
-            num_resource: 1
-            type: 1963
-            host_id: 12
-            reserved: 0
-        -
-            start_resource: 19
-            num_resource: 1
-            type: 1963
-            host_id: 36
-            reserved: 0
-        -
-            start_resource: 19
-            num_resource: 16
-            type: 1964
-            host_id: 12
-            reserved: 0
-        -
-            start_resource: 19
-            num_resource: 16
-            type: 1964
-            host_id: 36
-            reserved: 0
-        -
-            start_resource: 20
-            num_resource: 1
-            type: 1965
-            host_id: 12
-            reserved: 0
-        -
-            start_resource: 35
-            num_resource: 8
-            type: 1966
-            host_id: 12
-            reserved: 0
-        -
-            start_resource: 21
-            num_resource: 1
-            type: 1967
-            host_id: 12
-            reserved: 0
-        -
-            start_resource: 35
-            num_resource: 8
-            type: 1968
-            host_id: 12
-            reserved: 0
-        -
-            start_resource: 22
-            num_resource: 1
-            type: 1969
-            host_id: 12
-            reserved: 0
-        -
-            start_resource: 43
-            num_resource: 8
-            type: 1970
-            host_id: 12
-            reserved: 0
-        -
-            start_resource: 23
-            num_resource: 1
-            type: 1971
-            host_id: 12
-            reserved: 0
-        -
-            start_resource: 43
-            num_resource: 8
-            type: 1972
-            host_id: 12
-            reserved: 0
-        -
-            start_resource: 0
-            num_resource: 1
-            type: 2112
-            host_id: 128
-            reserved: 0
-        -
-            start_resource: 2
-            num_resource: 2
-            type: 2122
-            host_id: 12
-            reserved: 0

board/phytec/phycore_am68x/rm-cfg.yaml

@@ -1,5 +1,5 @@
 # SPDX-License-Identifier: GPL-2.0+
-# Copyright (C) 2022-2026 Texas Instruments Incorporated - https://www.ti.com/
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
 #
 # Resource management configuration for J721S2
 #
@@ -429,24 +429,24 @@ rm-cfg:
             reserved: 0
         -
             start_resource: 10
-            num_resource: 98
+            num_resource: 100
             type: 14528
             host_id: 12
             reserved: 0
         -
-            start_resource: 108
+            start_resource: 110
             num_resource: 32
             type: 14528
             host_id: 13
             reserved: 0
         -
-            start_resource: 140
+            start_resource: 142
             num_resource: 21
             type: 14528
             host_id: 21
             reserved: 0
         -
-            start_resource: 161
+            start_resource: 163
             num_resource: 21
             type: 14528
             host_id: 23
@@ -1431,7 +1431,7 @@ rm-cfg:
             reserved: 0
         -
             start_resource: 236
-            num_resource: 18
+            num_resource: 20
             type: 16970
             host_id: 128
             reserved: 0
@@ -1497,7 +1497,7 @@ rm-cfg:
             reserved: 0
         -
             start_resource: 3426
-            num_resource: 1180
+            num_resource: 1182
             type: 16973
             host_id: 128
             reserved: 0

board/purism/librem5/MAINTAINERS

@@ -2,6 +2,7 @@ PURISM LIBREM5 PHONE
 M:	Angus Ainslie <angus@akkea.ca>
 R:	kernel@puri.sm
 S:	Supported
+F:	arch/arm/dts/imx8mq-librem5*
 F:	board/purism/librem5/
 F:	configs/librem5_defconfig
 F:	include/configs/librem5.h

board/qualcomm/qcom-phone.env

@@ -40,7 +40,6 @@ bootmenu_6=Dump clocks=clk dump; pause
 bootmenu_7=Dump environment=printenv; pause
 bootmenu_8=Board info=bdinfo; pause
 bootmenu_9=Dump bootargs=fdt print /chosen bootargs; pause
-bootmenu_10=Power off=poweroff
 
 # Allow holding the volume down button while U-Boot loads to enter
 # the boot menu

board/renesas/geist/Kconfig

@@ -0,0 +1,15 @@
+if TARGET_GEIST
+
+config SYS_SOC
+	default "renesas"
+
+config SYS_BOARD
+	default "geist"
+
+config SYS_VENDOR
+	default "renesas"
+
+config SYS_CONFIG_NAME
+	default "geist"
+
+endif

board/renesas/geist/Makefile

@@ -0,0 +1,9 @@
+#
+# Copyright (C) 2025-2026 Renesas Electronics Corporation
+#
+# SPDX-License-Identifier: GPL-2.0-only
+#
+
+ifndef CONFIG_XPL_BUILD
+obj-y	+= geist.o
+endif

board/renesas/geist/geist.c

@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * This file is Geist board support.
+ *
+ * Copyright (C) 2025-2026 Renesas Electronics Corporation
+ */
+
+#include <asm/io.h>
+#include <asm/arch/rcar-mstp.h>
+#include <asm/arch/renesas.h>
+#include <init.h>
+
+#define HSUSB_MSTP704		BIT(4)	/* HSUSB */
+
+/* HSUSB block registers */
+#define HSUSB_REG_LPSTS			0xE6590102
+#define HSUSB_REG_LPSTS_SUSPM_NORMAL	BIT(14)
+#define HSUSB_REG_UGCTRL2		0xE6590184
+#define HSUSB_REG_UGCTRL2_USB0SEL	0x30
+#define HSUSB_REG_UGCTRL2_USB0SEL_EHCI	0x10
+
+int board_init(void)
+{
+	/* USB1 pull-up */
+	setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);
+
+	/* Configure the HSUSB block */
+	mstp_clrbits_le32(SMSTPCR7, SMSTPCR7, HSUSB_MSTP704);
+	/* Choice USB0SEL */
+	clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL,
+			HSUSB_REG_UGCTRL2_USB0SEL_EHCI);
+	/* low power status */
+	setbits_le16(HSUSB_REG_LPSTS, HSUSB_REG_LPSTS_SUSPM_NORMAL);
+
+	return 0;
+}

board/st/common/Makefile

@@ -9,6 +9,7 @@ obj-$(CONFIG_PMIC_STPMIC1) += stpmic1.o
 ifeq ($(CONFIG_ARCH_STM32MP),y)
 obj-$(CONFIG_SET_DFU_ALT_INFO) += stm32mp_dfu.o
 obj-$(CONFIG_$(PHASE_)DFU_VIRT) += stm32mp_dfu_virt.o
+obj-$(CONFIG_FWU_MULTI_BANK_UPDATE) += stm32mp_fwu.o
 endif
 
 obj-$(CONFIG_TYPEC_STUSB160X) += stusb160x.o

board/st/common/stm32mp_fwu.c

@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright (C) 2026 Amarula Solutions, Dario Binacchi <dario.binacchi@amarulasolutions.com>
+ */
+
+#include <fwu.h>
+#include <part_efi.h>
+#include <asm/io.h>
+/**
+ * fwu_plat_get_bootidx() - Get the value of the boot index
+ * @boot_idx: Boot index value
+ *
+ * Get the value of the bank(partition) from which the platform
+ * has booted. This value is passed to U-Boot from the earlier
+ * stage bootloader which loads and boots all the relevant
+ * firmware images
+ *
+ */
+void fwu_plat_get_bootidx(uint *boot_idx)
+{
+	*boot_idx = (readl(TAMP_FWU_BOOT_INFO_REG) >>
+		    TAMP_FWU_BOOT_IDX_OFFSET) & TAMP_FWU_BOOT_IDX_MASK;
+}
+
+int fwu_platform_hook(struct udevice *dev, struct fwu_data *data)
+{
+	uint boot_idx;
+	efi_guid_t boot_uuid, root_uuid;
+	const efi_guid_t boot_type_guid = PARTITION_XBOOTLDR;
+	const efi_guid_t root_type_guid =
+		PARTITION_LINUX_FILE_SYSTEM_DATA_GUID;
+	char uuidbuf[UUID_STR_LEN + 1];
+	int retb, retr;
+
+	fwu_plat_get_bootidx(&boot_idx);
+
+	retb = fwu_mdata_get_image_guid(&boot_uuid, &boot_type_guid, boot_idx);
+	retr = fwu_mdata_get_image_guid(&root_uuid, &root_type_guid, boot_idx);
+
+	if (!retb && !retr) {
+		uuid_bin_to_str(boot_uuid.b, uuidbuf, UUID_STR_FORMAT_GUID);
+		env_set("boot_partuuid", uuidbuf);
+
+		uuid_bin_to_str(root_uuid.b, uuidbuf, UUID_STR_FORMAT_GUID);
+		env_set("root_partuuid", uuidbuf);
+	} else if (!retb && retr) {
+		log_warning("%s: found boot GUID but missing root GUID (%d)\n",
+			    __func__, retr);
+	} else if (!retr && retb) {
+		log_warning("%s: found root GUID but missing boot GUID (%d)\n",
+			    __func__, retb);
+	}
+
+	return 0;
+}

board/st/stm32mp1/stm32mp1.c

@@ -837,24 +837,3 @@ static void board_copro_image_process(ulong fw_image, size_t fw_size)
 }
 
 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_COPRO, board_copro_image_process);
-
-#if defined(CONFIG_FWU_MULTI_BANK_UPDATE)
-
-#include <fwu.h>
-
-/**
- * fwu_plat_get_bootidx() - Get the value of the boot index
- * @boot_idx: Boot index value
- *
- * Get the value of the bank(partition) from which the platform
- * has booted. This value is passed to U-Boot from the earlier
- * stage bootloader which loads and boots all the relevant
- * firmware images
- *
- */
-void fwu_plat_get_bootidx(uint *boot_idx)
-{
-	*boot_idx = (readl(TAMP_FWU_BOOT_INFO_REG) >>
-		    TAMP_FWU_BOOT_IDX_OFFSET) & TAMP_FWU_BOOT_IDX_MASK;
-}
-#endif /* CONFIG_FWU_MULTI_BANK_UPDATE */

board/st/stm32mp2/stm32mp2.c

@@ -188,56 +188,3 @@ void board_quiesce_devices(void)
 {
 	led_boot_off();
 }
-
-#if defined(CONFIG_FWU_MULTI_BANK_UPDATE)
-
-#include <fwu.h>
-
-/**
- * fwu_plat_get_bootidx() - Get the value of the boot index
- * @boot_idx: Boot index value
- *
- * Get the value of the bank(partition) from which the platform
- * has booted. This value is passed to U-Boot from the earlier
- * stage bootloader which loads and boots all the relevant
- * firmware images
- *
- */
-void fwu_plat_get_bootidx(uint *boot_idx)
-{
-	*boot_idx = (readl(TAMP_FWU_BOOT_INFO_REG) >>
-		    TAMP_FWU_BOOT_IDX_OFFSET) & TAMP_FWU_BOOT_IDX_MASK;
-}
-
-int fwu_platform_hook(struct udevice *dev, struct fwu_data *data)
-{
-	uint boot_idx;
-	efi_guid_t boot_uuid, root_uuid;
-	const efi_guid_t boot_type_guid = PARTITION_XBOOTLDR;
-	const efi_guid_t root_type_guid =
-		PARTITION_LINUX_FILE_SYSTEM_DATA_GUID;
-	char uuidbuf[UUID_STR_LEN + 1];
-	int retb, retr;
-
-	fwu_plat_get_bootidx(&boot_idx);
-
-	retb = fwu_mdata_get_image_guid(&boot_uuid, &boot_type_guid, boot_idx);
-	retr = fwu_mdata_get_image_guid(&root_uuid, &root_type_guid, boot_idx);
-
-	if (!retb && !retr) {
-		uuid_bin_to_str(boot_uuid.b, uuidbuf, UUID_STR_FORMAT_GUID);
-		env_set("boot_partuuid", uuidbuf);
-
-		uuid_bin_to_str(root_uuid.b, uuidbuf, UUID_STR_FORMAT_GUID);
-		env_set("root_partuuid", uuidbuf);
-	} else if (!retb && retr) {
-		log_warning("%s: found boot GUID but missing root GUID (%d)\n",
-			    __func__, retr);
-	} else if (!retr && retb) {
-		log_warning("%s: found root GUID but missing boot GUID (%d)\n",
-			    __func__, retb);
-	}
-
-	return 0;
-}
-#endif /* CONFIG_FWU_MULTI_BANK_UPDATE */

board/ti/am335x/board.c

@@ -28,7 +28,6 @@
 #include <asm/arch/mmc_host_def.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/mem.h>
-#include <asm/arch/mux.h>
 #include <asm/global_data.h>
 #include <asm/io.h>
 #include <asm/emif.h>
@@ -73,12 +72,6 @@ static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
 #define GPIO0_IRQSTATUSRAW	(AM33XX_GPIO0_BASE + 0x024)
 #define GPIO1_IRQSTATUSRAW	(AM33XX_GPIO1_BASE + 0x024)
 
-static __maybe_unused struct module_pin_mux rmii1_mdio_pin_mux[] = {
-	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},	/* MDIO_CLK */
-	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
-	{-1},
-};
-
 /*
  * Read header information from EEPROM into global structure.
  */
@@ -786,9 +779,6 @@ int board_init(void)
 			hang();
 		}
 
-		if (!eth0_is_mii)
-			configure_module_pin_mux(rmii1_mdio_pin_mux);
-
 		prueth_is_mii = eth0_is_mii;
 
 		/* disable rising edge IRQs */

board/ti/am335x/mux.c

@@ -190,6 +190,8 @@ static struct module_pin_mux mii1_pin_mux[] = {
 };
 
 static struct module_pin_mux rmii1_pin_mux[] = {
+	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},	/* MDIO_CLK */
+	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
 	{OFFSET(mii1_crs), MODE(1) | RXACTIVE},		/* MII1_CRS */
 	{OFFSET(mii1_rxerr), MODE(1) | RXACTIVE},	/* MII1_RXERR */
 	{OFFSET(mii1_txen), MODE(1)},			/* MII1_TXEN */

board/ti/am62x/am6254atl.env

@@ -27,6 +27,10 @@ splashimage=0x82180000
 splashpos=m,m
 splashsource=sf
 
+dfu_alt_info_ram=
+	tispl.bin ram 0x82000000 0x200000;
+	u-boot.img ram 0x82f80000 0x400000
+
 #if CONFIG_BOOTMETH_ANDROID
 #include <env/ti/android.env>
 adtb_idx=0

board/ti/j722s/sec-cfg.yaml

@@ -16,9 +16,9 @@ sec-cfg:
             size: 164
         proc_acl_entries:
             -
-                processor_id: 0x1
-                proc_access_master: 0x23
-                proc_access_secondary: [0xC, 0, 0]
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
             -
                 processor_id: 0
                 proc_access_master: 0

board/toradex/aquila-am69/rm-cfg.yaml

@@ -1,5 +1,5 @@
 # SPDX-License-Identifier: GPL-2.0+
-# Copyright (C) 2022-2026 Texas Instruments Incorporated - https://www.ti.com/
+# Copyright (C) 2022-2025 Texas Instruments Incorporated - https://www.ti.com/
 #
 # Resource management configuration for J784S4
 #
@@ -453,36 +453,36 @@ rm-cfg:
             reserved: 0
         -
             start_resource: 16
-            num_resource: 78
+            num_resource: 80
             type: 18112
             host_id: 12
             reserved: 0
         -
-            start_resource: 94
+            start_resource: 96
             num_resource: 14
             type: 18112
             host_id: 13
             reserved: 0
         -
-            start_resource: 108
+            start_resource: 110
             num_resource: 21
             type: 18112
             host_id: 21
             reserved: 0
         -
-            start_resource: 129
+            start_resource: 131
             num_resource: 21
             type: 18112
             host_id: 23
             reserved: 0
         -
-            start_resource: 150
+            start_resource: 152
             num_resource: 12
             type: 18112
             host_id: 25
             reserved: 0
         -
-            start_resource: 162
+            start_resource: 164
             num_resource: 12
             type: 18112
             host_id: 27
@@ -1719,72 +1719,72 @@ rm-cfg:
             reserved: 0
         -
             start_resource: 56
-            num_resource: 54
+            num_resource: 56
             type: 20554
             host_id: 12
             reserved: 0
         -
-            start_resource: 110
+            start_resource: 112
             num_resource: 24
             type: 20554
             host_id: 13
             reserved: 0
         -
-            start_resource: 134
+            start_resource: 136
             num_resource: 12
             type: 20554
             host_id: 21
             reserved: 0
         -
-            start_resource: 146
+            start_resource: 148
             num_resource: 12
             type: 20554
             host_id: 23
             reserved: 0
         -
-            start_resource: 158
+            start_resource: 160
             num_resource: 10
             type: 20554
             host_id: 25
             reserved: 0
         -
-            start_resource: 168
+            start_resource: 170
             num_resource: 10
             type: 20554
             host_id: 27
             reserved: 0
         -
-            start_resource: 178
+            start_resource: 180
             num_resource: 28
             type: 20554
             host_id: 35
             reserved: 0
         -
-            start_resource: 206
+            start_resource: 208
             num_resource: 8
             type: 20554
             host_id: 37
             reserved: 0
         -
-            start_resource: 214
+            start_resource: 216
             num_resource: 12
             type: 20554
             host_id: 40
             reserved: 0
         -
-            start_resource: 226
+            start_resource: 228
             num_resource: 8
             type: 20554
             host_id: 42
             reserved: 0
         -
-            start_resource: 234
+            start_resource: 236
             num_resource: 10
             type: 20554
             host_id: 45
             reserved: 0
         -
-            start_resource: 244
+            start_resource: 246
             num_resource: 10
             type: 20554
             host_id: 47
@@ -1875,7 +1875,7 @@ rm-cfg:
             reserved: 0
         -
             start_resource: 4472
-            num_resource: 134
+            num_resource: 136
             type: 20557
             host_id: 128
             reserved: 0

board/toradex/aquila-am69/tifs-rm-cfg.yaml

@@ -1,5 +1,5 @@
 # SPDX-License-Identifier: GPL-2.0+
-# Copyright (C) 2022-2026 Texas Instruments Incorporated - https://www.ti.com/
+# Copyright (C) 2022-2025 Texas Instruments Incorporated - https://www.ti.com/
 #
 # Resource management configuration for J784S4
 #
@@ -1455,72 +1455,72 @@ tifs-rm-cfg:
             reserved: 0
         -
             start_resource: 56
-            num_resource: 54
+            num_resource: 56
             type: 20554
             host_id: 12
             reserved: 0
         -
-            start_resource: 110
+            start_resource: 112
             num_resource: 24
             type: 20554
             host_id: 13
             reserved: 0
         -
-            start_resource: 134
+            start_resource: 136
             num_resource: 12
             type: 20554
             host_id: 21
             reserved: 0
         -
-            start_resource: 146
+            start_resource: 148
             num_resource: 12
             type: 20554
             host_id: 23
             reserved: 0
         -
-            start_resource: 158
+            start_resource: 160
             num_resource: 10
             type: 20554
             host_id: 25
             reserved: 0
         -
-            start_resource: 168
+            start_resource: 170
             num_resource: 10
             type: 20554
             host_id: 27
             reserved: 0
         -
-            start_resource: 178
+            start_resource: 180
             num_resource: 28
             type: 20554
             host_id: 35
             reserved: 0
         -
-            start_resource: 206
+            start_resource: 208
             num_resource: 8
             type: 20554
             host_id: 37
             reserved: 0
         -
-            start_resource: 214
+            start_resource: 216
             num_resource: 12
             type: 20554
             host_id: 40
             reserved: 0
         -
-            start_resource: 226
+            start_resource: 228
             num_resource: 8
             type: 20554
             host_id: 42
             reserved: 0
         -
-            start_resource: 234
+            start_resource: 236
             num_resource: 10
             type: 20554
             host_id: 45
             reserved: 0
         -
-            start_resource: 244
+            start_resource: 246
             num_resource: 10
             type: 20554
             host_id: 47

board/toradex/verdin-am62/tifs-rm-cfg.yaml

@@ -1,867 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-# Copyright (C) 2022-2026 Texas Instruments Incorporated - https://www.ti.com/
-#
-# Resource management configuration for AM62X
-#
-
----
-
-tifs-rm-cfg:
-    rm_boardcfg:
-        rev:
-            boardcfg_abi_maj: 0x0
-            boardcfg_abi_min: 0x1
-        host_cfg:
-            subhdr:
-                magic: 0x4C41
-                size: 356
-            host_cfg_entries:
-                -  # 1
-                    host_id: 12
-                    allowed_atype: 0x2A
-                    allowed_qos: 0xAAAA
-                    allowed_orderid: 0xAAAAAAAA
-                    allowed_priority: 0xAAAA
-                    allowed_sched_priority: 0xAA
-                -  # 2
-                    host_id: 30
-                    allowed_atype: 0x2A
-                    allowed_qos: 0xAAAA
-                    allowed_orderid: 0xAAAAAAAA
-                    allowed_priority: 0xAAAA
-                    allowed_sched_priority: 0xAA
-                -  # 3
-                    host_id: 36
-                    allowed_atype: 0x2A
-                    allowed_qos: 0xAAAA
-                    allowed_orderid: 0xAAAAAAAA
-                    allowed_priority: 0xAAAA
-                    allowed_sched_priority: 0xAA
-                -  # 4
-                    host_id: 0
-                    allowed_atype: 0
-                    allowed_qos: 0
-                    allowed_orderid: 0
-                    allowed_priority: 0
-                    allowed_sched_priority: 0
-                -  # 5
-                    host_id: 0
-                    allowed_atype: 0
-                    allowed_qos: 0
-                    allowed_orderid: 0
-                    allowed_priority: 0
-                    allowed_sched_priority: 0
-                -  # 6
-                    host_id: 0
-                    allowed_atype: 0
-                    allowed_qos: 0
-                    allowed_orderid: 0
-                    allowed_priority: 0
-                    allowed_sched_priority: 0
-                -  # 7
-                    host_id: 0
-                    allowed_atype: 0
-                    allowed_qos: 0
-                    allowed_orderid: 0
-                    allowed_priority: 0
-                    allowed_sched_priority: 0
-                -  # 8
-                    host_id: 0
-                    allowed_atype: 0
-                    allowed_qos: 0
-                    allowed_orderid: 0
-                    allowed_priority: 0
-                    allowed_sched_priority: 0
-                -  # 9
-                    host_id: 0
-                    allowed_atype: 0
-                    allowed_qos: 0
-                    allowed_orderid: 0
-                    allowed_priority: 0
-                    allowed_sched_priority: 0
-                -  # 10
-                    host_id: 0
-                    allowed_atype: 0
-                    allowed_qos: 0
-                    allowed_orderid: 0
-                    allowed_priority: 0
-                    allowed_sched_priority: 0
-                -  # 11
-                    host_id: 0
-                    allowed_atype: 0
-                    allowed_qos: 0
-                    allowed_orderid: 0
-                    allowed_priority: 0
-                    allowed_sched_priority: 0
-                -  # 12
-                    host_id: 0
-                    allowed_atype: 0
-                    allowed_qos: 0
-                    allowed_orderid: 0
-                    allowed_priority: 0
-                    allowed_sched_priority: 0
-                -  # 13
-                    host_id: 0
-                    allowed_atype: 0
-                    allowed_qos: 0
-                    allowed_orderid: 0
-                    allowed_priority: 0
-                    allowed_sched_priority: 0
-                -  # 14
-                    host_id: 0
-                    allowed_atype: 0
-                    allowed_qos: 0
-                    allowed_orderid: 0
-                    allowed_priority: 0
-                    allowed_sched_priority: 0
-                -  # 15
-                    host_id: 0
-                    allowed_atype: 0
-                    allowed_qos: 0
-                    allowed_orderid: 0
-                    allowed_priority: 0
-                    allowed_sched_priority: 0
-                -  # 16
-                    host_id: 0
-                    allowed_atype: 0
-                    allowed_qos: 0
-                    allowed_orderid: 0
-                    allowed_priority: 0
-                    allowed_sched_priority: 0
-                -  # 17
-                    host_id: 0
-                    allowed_atype: 0
-                    allowed_qos: 0
-                    allowed_orderid: 0
-                    allowed_priority: 0
-                    allowed_sched_priority: 0
-                -  # 18
-                    host_id: 0
-                    allowed_atype: 0
-                    allowed_qos: 0
-                    allowed_orderid: 0
-                    allowed_priority: 0
-                    allowed_sched_priority: 0
-                -  # 19
-                    host_id: 0
-                    allowed_atype: 0
-                    allowed_qos: 0
-                    allowed_orderid: 0
-                    allowed_priority: 0
-                    allowed_sched_priority: 0
-                -  # 20
-                    host_id: 0
-                    allowed_atype: 0
-                    allowed_qos: 0
-                    allowed_orderid: 0
-                    allowed_priority: 0
-                    allowed_sched_priority: 0
-                -  # 21
-                    host_id: 0
-                    allowed_atype: 0
-                    allowed_qos: 0
-                    allowed_orderid: 0
-                    allowed_priority: 0
-                    allowed_sched_priority: 0
-                -  # 22
-                    host_id: 0
-                    allowed_atype: 0
-                    allowed_qos: 0
-                    allowed_orderid: 0
-                    allowed_priority: 0
-                    allowed_sched_priority: 0
-                -  # 23
-                    host_id: 0
-                    allowed_atype: 0
-                    allowed_qos: 0
-                    allowed_orderid: 0
-                    allowed_priority: 0
-                    allowed_sched_priority: 0
-                -  # 24
-                    host_id: 0
-                    allowed_atype: 0
-                    allowed_qos: 0
-                    allowed_orderid: 0
-                    allowed_priority: 0
-                    allowed_sched_priority: 0
-                -  # 25
-                    host_id: 0
-                    allowed_atype: 0
-                    allowed_qos: 0
-                    allowed_orderid: 0
-                    allowed_priority: 0
-                    allowed_sched_priority: 0
-                -  # 26
-                    host_id: 0
-                    allowed_atype: 0
-                    allowed_qos: 0
-                    allowed_orderid: 0
-                    allowed_priority: 0
-                    allowed_sched_priority: 0
-                -  # 27
-                    host_id: 0
-                    allowed_atype: 0
-                    allowed_qos: 0
-                    allowed_orderid: 0
-                    allowed_priority: 0
-                    allowed_sched_priority: 0
-                -  # 28
-                    host_id: 0
-                    allowed_atype: 0
-                    allowed_qos: 0
-                    allowed_orderid: 0
-                    allowed_priority: 0
-                    allowed_sched_priority: 0
-                -  # 29
-                    host_id: 0
-                    allowed_atype: 0
-                    allowed_qos: 0
-                    allowed_orderid: 0
-                    allowed_priority: 0
-                    allowed_sched_priority: 0
-                -  # 30
-                    host_id: 0
-                    allowed_atype: 0
-                    allowed_qos: 0
-                    allowed_orderid: 0
-                    allowed_priority: 0
-                    allowed_sched_priority: 0
-                -  # 31
-                    host_id: 0
-                    allowed_atype: 0
-                    allowed_qos: 0
-                    allowed_orderid: 0
-                    allowed_priority: 0
-                    allowed_sched_priority: 0
-                -  # 32
-                    host_id: 0
-                    allowed_atype: 0
-                    allowed_qos: 0
-                    allowed_orderid: 0
-                    allowed_priority: 0
-                    allowed_sched_priority: 0
-        resasg:
-            subhdr:
-                magic: 0x7B25
-                size: 8
-            resasg_entries_size: 824
-            reserved: 0
-    resasg_entries:
-        -
-            start_resource: 0
-            num_resource: 18
-            type: 1677
-            host_id: 12
-            reserved: 0
-        -
-            start_resource: 18
-            num_resource: 6
-            type: 1677
-            host_id: 35
-            reserved: 0
-        -
-            start_resource: 18
-            num_resource: 6
-            type: 1677
-            host_id: 36
-            reserved: 0
-        -
-            start_resource: 24
-            num_resource: 2
-            type: 1677
-            host_id: 30
-            reserved: 0
-        -
-            start_resource: 26
-            num_resource: 6
-            type: 1677
-            host_id: 128
-            reserved: 0
-        -
-            start_resource: 54
-            num_resource: 18
-            type: 1678
-            host_id: 12
-            reserved: 0
-        -
-            start_resource: 72
-            num_resource: 6
-            type: 1678
-            host_id: 35
-            reserved: 0
-        -
-            start_resource: 72
-            num_resource: 6
-            type: 1678
-            host_id: 36
-            reserved: 0
-        -
-            start_resource: 78
-            num_resource: 2
-            type: 1678
-            host_id: 30
-            reserved: 0
-        -
-            start_resource: 80
-            num_resource: 2
-            type: 1678
-            host_id: 128
-            reserved: 0
-        -
-            start_resource: 32
-            num_resource: 12
-            type: 1679
-            host_id: 12
-            reserved: 0
-        -
-            start_resource: 44
-            num_resource: 6
-            type: 1679
-            host_id: 35
-            reserved: 0
-        -
-            start_resource: 44
-            num_resource: 6
-            type: 1679
-            host_id: 36
-            reserved: 0
-        -
-            start_resource: 50
-            num_resource: 2
-            type: 1679
-            host_id: 30
-            reserved: 0
-        -
-            start_resource: 52
-            num_resource: 2
-            type: 1679
-            host_id: 128
-            reserved: 0
-        -
-            start_resource: 0
-            num_resource: 18
-            type: 1696
-            host_id: 12
-            reserved: 0
-        -
-            start_resource: 18
-            num_resource: 6
-            type: 1696
-            host_id: 35
-            reserved: 0
-        -
-            start_resource: 18
-            num_resource: 6
-            type: 1696
-            host_id: 36
-            reserved: 0
-        -
-            start_resource: 24
-            num_resource: 2
-            type: 1696
-            host_id: 30
-            reserved: 0
-        -
-            start_resource: 26
-            num_resource: 6
-            type: 1696
-            host_id: 128
-            reserved: 0
-        -
-            start_resource: 0
-            num_resource: 18
-            type: 1697
-            host_id: 12
-            reserved: 0
-        -
-            start_resource: 18
-            num_resource: 6
-            type: 1697
-            host_id: 35
-            reserved: 0
-        -
-            start_resource: 18
-            num_resource: 6
-            type: 1697
-            host_id: 36
-            reserved: 0
-        -
-            start_resource: 24
-            num_resource: 2
-            type: 1697
-            host_id: 30
-            reserved: 0
-        -
-            start_resource: 26
-            num_resource: 2
-            type: 1697
-            host_id: 128
-            reserved: 0
-        -
-            start_resource: 0
-            num_resource: 12
-            type: 1698
-            host_id: 12
-            reserved: 0
-        -
-            start_resource: 12
-            num_resource: 6
-            type: 1698
-            host_id: 35
-            reserved: 0
-        -
-            start_resource: 12
-            num_resource: 6
-            type: 1698
-            host_id: 36
-            reserved: 0
-        -
-            start_resource: 18
-            num_resource: 2
-            type: 1698
-            host_id: 30
-            reserved: 0
-        -
-            start_resource: 20
-            num_resource: 2
-            type: 1698
-            host_id: 128
-            reserved: 0
-        -
-            start_resource: 5
-            num_resource: 35
-            type: 1802
-            host_id: 12
-            reserved: 0
-        -
-            start_resource: 44
-            num_resource: 35
-            type: 1802
-            host_id: 35
-            reserved: 0
-        -
-            start_resource: 44
-            num_resource: 35
-            type: 1802
-            host_id: 36
-            reserved: 0
-        -
-            start_resource: 168
-            num_resource: 7
-            type: 1802
-            host_id: 30
-            reserved: 0
-        -
-            start_resource: 0
-            num_resource: 1024
-            type: 1807
-            host_id: 128
-            reserved: 0
-        -
-            start_resource: 4096
-            num_resource: 29
-            type: 1808
-            host_id: 128
-            reserved: 0
-        -
-            start_resource: 4608
-            num_resource: 99
-            type: 1809
-            host_id: 128
-            reserved: 0
-        -
-            start_resource: 5120
-            num_resource: 24
-            type: 1810
-            host_id: 128
-            reserved: 0
-        -
-            start_resource: 5632
-            num_resource: 51
-            type: 1811
-            host_id: 128
-            reserved: 0
-        -
-            start_resource: 6144
-            num_resource: 51
-            type: 1812
-            host_id: 128
-            reserved: 0
-        -
-            start_resource: 6656
-            num_resource: 51
-            type: 1813
-            host_id: 128
-            reserved: 0
-        -
-            start_resource: 8192
-            num_resource: 32
-            type: 1814
-            host_id: 128
-            reserved: 0
-        -
-            start_resource: 8704
-            num_resource: 32
-            type: 1815
-            host_id: 128
-            reserved: 0
-        -
-            start_resource: 9216
-            num_resource: 32
-            type: 1816
-            host_id: 128
-            reserved: 0
-        -
-            start_resource: 9728
-            num_resource: 22
-            type: 1817
-            host_id: 128
-            reserved: 0
-        -
-            start_resource: 10240
-            num_resource: 22
-            type: 1818
-            host_id: 128
-            reserved: 0
-        -
-            start_resource: 10752
-            num_resource: 22
-            type: 1819
-            host_id: 128
-            reserved: 0
-        -
-            start_resource: 11264
-            num_resource: 28
-            type: 1820
-            host_id: 128
-            reserved: 0
-        -
-            start_resource: 11776
-            num_resource: 28
-            type: 1821
-            host_id: 128
-            reserved: 0
-        -
-            start_resource: 12288
-            num_resource: 28
-            type: 1822
-            host_id: 128
-            reserved: 0
-        -
-            start_resource: 0
-            num_resource: 10
-            type: 1936
-            host_id: 12
-            reserved: 0
-        -
-            start_resource: 10
-            num_resource: 3
-            type: 1936
-            host_id: 35
-            reserved: 0
-        -
-            start_resource: 10
-            num_resource: 3
-            type: 1936
-            host_id: 36
-            reserved: 0
-        -
-            start_resource: 13
-            num_resource: 3
-            type: 1936
-            host_id: 30
-            reserved: 0
-        -
-            start_resource: 16
-            num_resource: 3
-            type: 1936
-            host_id: 128
-            reserved: 0
-        -
-            start_resource: 19
-            num_resource: 64
-            type: 1937
-            host_id: 12
-            reserved: 0
-        -
-            start_resource: 19
-            num_resource: 64
-            type: 1937
-            host_id: 36
-            reserved: 0
-        -
-            start_resource: 83
-            num_resource: 8
-            type: 1938
-            host_id: 12
-            reserved: 0
-        -
-            start_resource: 91
-            num_resource: 8
-            type: 1939
-            host_id: 12
-            reserved: 0
-        -
-            start_resource: 99
-            num_resource: 10
-            type: 1942
-            host_id: 12
-            reserved: 0
-        -
-            start_resource: 109
-            num_resource: 3
-            type: 1942
-            host_id: 35
-            reserved: 0
-        -
-            start_resource: 109
-            num_resource: 3
-            type: 1942
-            host_id: 36
-            reserved: 0
-        -
-            start_resource: 112
-            num_resource: 3
-            type: 1942
-            host_id: 30
-            reserved: 0
-        -
-            start_resource: 115
-            num_resource: 3
-            type: 1942
-            host_id: 128
-            reserved: 0
-        -
-            start_resource: 118
-            num_resource: 16
-            type: 1943
-            host_id: 12
-            reserved: 0
-        -
-            start_resource: 118
-            num_resource: 16
-            type: 1943
-            host_id: 36
-            reserved: 0
-        -
-            start_resource: 134
-            num_resource: 8
-            type: 1944
-            host_id: 12
-            reserved: 0
-        -
-            start_resource: 134
-            num_resource: 8
-            type: 1945
-            host_id: 12
-            reserved: 0
-        -
-            start_resource: 142
-            num_resource: 8
-            type: 1946
-            host_id: 12
-            reserved: 0
-        -
-            start_resource: 142
-            num_resource: 8
-            type: 1947
-            host_id: 12
-            reserved: 0
-        -
-            start_resource: 0
-            num_resource: 10
-            type: 1955
-            host_id: 12
-            reserved: 0
-        -
-            start_resource: 10
-            num_resource: 3
-            type: 1955
-            host_id: 35
-            reserved: 0
-        -
-            start_resource: 10
-            num_resource: 3
-            type: 1955
-            host_id: 36
-            reserved: 0
-        -
-            start_resource: 13
-            num_resource: 3
-            type: 1955
-            host_id: 30
-            reserved: 0
-        -
-            start_resource: 16
-            num_resource: 3
-            type: 1955
-            host_id: 128
-            reserved: 0
-        -
-            start_resource: 19
-            num_resource: 8
-            type: 1956
-            host_id: 12
-            reserved: 0
-        -
-            start_resource: 19
-            num_resource: 8
-            type: 1956
-            host_id: 36
-            reserved: 0
-        -
-            start_resource: 27
-            num_resource: 1
-            type: 1957
-            host_id: 12
-            reserved: 0
-        -
-            start_resource: 28
-            num_resource: 1
-            type: 1958
-            host_id: 12
-            reserved: 0
-        -
-            start_resource: 0
-            num_resource: 10
-            type: 1961
-            host_id: 12
-            reserved: 0
-        -
-            start_resource: 10
-            num_resource: 3
-            type: 1961
-            host_id: 35
-            reserved: 0
-        -
-            start_resource: 10
-            num_resource: 3
-            type: 1961
-            host_id: 36
-            reserved: 0
-        -
-            start_resource: 13
-            num_resource: 3
-            type: 1961
-            host_id: 30
-            reserved: 0
-        -
-            start_resource: 16
-            num_resource: 3
-            type: 1961
-            host_id: 128
-            reserved: 0
-        -
-            start_resource: 0
-            num_resource: 10
-            type: 1962
-            host_id: 12
-            reserved: 0
-        -
-            start_resource: 10
-            num_resource: 3
-            type: 1962
-            host_id: 35
-            reserved: 0
-        -
-            start_resource: 10
-            num_resource: 3
-            type: 1962
-            host_id: 36
-            reserved: 0
-        -
-            start_resource: 13
-            num_resource: 3
-            type: 1962
-            host_id: 30
-            reserved: 0
-        -
-            start_resource: 16
-            num_resource: 3
-            type: 1962
-            host_id: 128
-            reserved: 0
-        -
-            start_resource: 19
-            num_resource: 1
-            type: 1963
-            host_id: 12
-            reserved: 0
-        -
-            start_resource: 19
-            num_resource: 1
-            type: 1963
-            host_id: 36
-            reserved: 0
-        -
-            start_resource: 19
-            num_resource: 16
-            type: 1964
-            host_id: 12
-            reserved: 0
-        -
-            start_resource: 19
-            num_resource: 16
-            type: 1964
-            host_id: 36
-            reserved: 0
-        -
-            start_resource: 20
-            num_resource: 1
-            type: 1965
-            host_id: 12
-            reserved: 0
-        -
-            start_resource: 35
-            num_resource: 8
-            type: 1966
-            host_id: 12
-            reserved: 0
-        -
-            start_resource: 21
-            num_resource: 1
-            type: 1967
-            host_id: 12
-            reserved: 0
-        -
-            start_resource: 35
-            num_resource: 8
-            type: 1968
-            host_id: 12
-            reserved: 0
-        -
-            start_resource: 22
-            num_resource: 1
-            type: 1969
-            host_id: 12
-            reserved: 0
-        -
-            start_resource: 43
-            num_resource: 8
-            type: 1970
-            host_id: 12
-            reserved: 0
-        -
-            start_resource: 23
-            num_resource: 1
-            type: 1971
-            host_id: 12
-            reserved: 0
-        -
-            start_resource: 43
-            num_resource: 8
-            type: 1972
-            host_id: 12
-            reserved: 0
-        -
-            start_resource: 0
-            num_resource: 1
-            type: 2112
-            host_id: 128
-            reserved: 0
-        -
-            start_resource: 2
-            num_resource: 2
-            type: 2122
-            host_id: 12
-            reserved: 0

boot/Kconfig

@@ -142,26 +142,6 @@ config FIT_CIPHER
 	  Enable the feature of data ciphering/unciphering in the tool mkimage
 	  and in the u-boot support of the FIT image.
 
-config FIT_VERITY
-	bool "dm-verity boot parameter generation from FIT metadata"
-	depends on FIT && OF_LIBFDT
-	help
-	  When a FIT configuration contains loadable sub-images of type
-	  IH_TYPE_FILESYSTEM with a dm-verity subnode, this option enables
-	  building the dm-mod.create= and dm-mod.waitfor= kernel
-	  command-line parameters from the verity metadata
-	  (data-block-size, hash-block-size, num-data-blocks,
-	  hash-start-block, algorithm, digest, salt) stored in the FIT.
-
-	  The generated parameters reference /dev/fitN block devices that
-	  Linux's uImage.FIT block driver assigns to loadable sub-images.
-
-	  During FIT parsing (BOOTM_STATE_FINDOTHER), verity cmdline
-	  fragments are stored in struct bootm_headers and automatically
-	  appended to the bootargs environment variable during
-	  BOOTM_STATE_OS_PREP.  This works from both the bootm command
-	  and BOOTSTD bootmeths.
-
 config FIT_VERBOSE
 	bool "Show verbose messages when FIT images fail"
 	help

boot/bootdev-uclass.c

@@ -566,18 +566,13 @@ int bootdev_get_bootflow(struct udevice *dev, struct bootflow_iter *iter,
 {
 	const struct bootdev_ops *ops = bootdev_get_ops(dev);
 
+	log_debug("->get_bootflow %s,%x=%p\n", dev->name, iter->part,
+		  ops->get_bootflow);
 	bootflow_init(bflow, dev, iter->method);
+	if (!ops->get_bootflow)
+		return default_get_bootflow(dev, iter, bflow);
 
-	if (ops && ops->get_bootflow) {
-		log_debug("->get_bootflow %s,%x=%p\n", dev->name, iter->part,
-			  ops->get_bootflow);
-
-		return ops->get_bootflow(dev, iter, bflow);
-	}
-
-	log_debug("->get_bootflow %s,%x is unset\n", dev->name, iter->part);
-
-	return default_get_bootflow(dev, iter, bflow);
+	return ops->get_bootflow(dev, iter, bflow);
 }
 
 int bootdev_next_label(struct bootflow_iter *iter, struct udevice **devp,

boot/bootm.c

@@ -243,13 +243,6 @@ static int boot_get_kernel(const char *addr_fit, struct bootm_headers *images,
 
 static int bootm_start(void)
 {
-	/*
-	 * Free dm-verity allocations from a prior boot attempt before
-	 * zeroing the structure. The pointers are guaranteed to be valid
-	 * or NULL: .bss is zero-initialised, and memset() below zeroes
-	 * them again after every boot.
-	 */
-	fit_verity_free(&images);
 	memset((void *)&images, 0, sizeof(images));
 	images.verify = env_get_yesno("verify");
 
@@ -1078,12 +1071,6 @@ int bootm_run_states(struct bootm_info *bmi, int states)
 		/* For Linux OS do all substitutions at console processing */
 		if (images->os.os == IH_OS_LINUX)
 			flags = BOOTM_CL_ALL;
-		ret = fit_verity_apply_bootargs(images);
-		if (ret) {
-			printf("dm-verity bootargs failed (err=%d)\n", ret);
-			ret = CMD_RET_FAILURE;
-			goto err;
-		}
 		ret = bootm_process_cmdline_env(flags);
 		if (ret) {
 			printf("Cmdline setup failed (err=%d)\n", ret);

boot/cedit.c

@@ -500,8 +500,6 @@ static int h_read_settings(struct scene_obj *obj, void *vpriv)
 		tline = (struct scene_obj_textline *)obj;
 
 		val = ofnode_read_prop(node, obj->name, &len);
-		if (!val)
-			return log_msg_ret("tline", -ENOENT);
 		if (len >= tline->max_chars)
 			return log_msg_ret("str", -ENOSPC);
 		strcpy(abuf_data(&tline->buf), val);

boot/image-board.c

@@ -810,11 +810,6 @@ int boot_get_loadable(struct bootm_headers *images)
 
 			fit_loadable_process(img_type, img_data, img_len);
 		}
-
-		fit_img_result = fit_verity_build_cmdline(buf, conf_noffset,
-							  images);
-		if (fit_img_result < 0)
-			return fit_img_result;
 		break;
 	default:
 		printf("The given image format is not supported (corrupt?)\n");

boot/image-fit.c

@@ -21,11 +21,8 @@
 extern void *aligned_alloc(size_t alignment, size_t size);
 #else
 #include <linux/compiler.h>
-#include <linux/log2.h>
 #include <linux/sizes.h>
-#include <env.h>
 #include <errno.h>
-#include <hexdump.h>
 #include <log.h>
 #include <mapmem.h>
 #include <asm/io.h>
@@ -159,10 +156,18 @@ static void fit_get_debug(const void *fit, int noffset,
 int fit_get_subimage_count(const void *fit, int images_noffset)
 {
 	int noffset;
+	int ndepth;
 	int count = 0;
 
-	fdt_for_each_subnode(noffset, fit, images_noffset)
-		count++;
+	/* Process its subnodes, print out component images details */
+	for (ndepth = 0, count = 0,
+		noffset = fdt_next_node(fit, images_noffset, &ndepth);
+	     (noffset >= 0) && (ndepth > 0);
+	     noffset = fdt_next_node(fit, noffset, &ndepth)) {
+		if (ndepth == 1) {
+			count++;
+		}
+	}
 
 	return count;
 }
@@ -238,39 +243,6 @@ static void fit_image_print_data(const void *fit, int noffset, const char *p,
 	}
 }
 
-static __maybe_unused void fit_image_print_dm_verity(const void *fit,
-						     int noffset,
-						     const char *p)
-{
-#if defined(USE_HOSTCC) || CONFIG_IS_ENABLED(FIT_VERITY)
-	const char *algo;
-	const uint8_t *bin;
-	int len, i;
-
-	algo = fdt_getprop(fit, noffset, FIT_VERITY_ALGO_PROP, NULL);
-	if (algo)
-		printf("%s  Verity algo:  %s\n", p, algo);
-
-	bin = fdt_getprop(fit, noffset, FIT_VERITY_DIGEST_PROP,
-			  &len);
-	if (bin && len > 0) {
-		printf("%s  Verity hash:  ", p);
-		for (i = 0; i < len; i++)
-			printf("%02x", bin[i]);
-		printf("\n");
-	}
-
-	bin = fdt_getprop(fit, noffset, FIT_VERITY_SALT_PROP,
-			  &len);
-	if (bin && len > 0) {
-		printf("%s  Verity salt:  ", p);
-		for (i = 0; i < len; i++)
-			printf("%02x", bin[i]);
-		printf("\n");
-	}
-#endif
-}
-
 /**
  * fit_image_print_verification_data() - prints out the hash/signature details
  * @fit: pointer to the FIT format image header
@@ -299,11 +271,6 @@ static void fit_image_print_verification_data(const void *fit, int noffset,
 				strlen(FIT_SIG_NODENAME))) {
 		fit_image_print_data(fit, noffset, p, "Sign");
 	}
-#if defined(USE_HOSTCC) || CONFIG_IS_ENABLED(FIT_VERITY)
-	else if (!strcmp(name, FIT_VERITY_NODENAME)) {
-		fit_image_print_dm_verity(fit, noffset, p);
-	}
-#endif
 }
 
 /**
@@ -324,7 +291,7 @@ static void fit_conf_print(const void *fit, int noffset, const char *p)
 	const char *uname;
 	int ret;
 	int fdt_index, loadables_index;
-	int sub_noffset;
+	int ndepth;
 
 	/* Mandatory properties */
 	ret = fit_get_desc(fit, noffset, &desc);
@@ -390,8 +357,14 @@ static void fit_conf_print(const void *fit, int noffset, const char *p)
 	}
 
 	/* Process all hash subnodes of the component configuration node */
-	fdt_for_each_subnode(sub_noffset, fit, noffset)
-		fit_image_print_verification_data(fit, sub_noffset, p);
+	for (ndepth = 0, noffset = fdt_next_node(fit, noffset, &ndepth);
+	     (noffset >= 0) && (ndepth > 0);
+	     noffset = fdt_next_node(fit, noffset, &ndepth)) {
+		if (ndepth == 1) {
+			/* Direct child node of the component configuration node */
+			fit_image_print_verification_data(fit, noffset, p);
+		}
+	}
 }
 
 /**
@@ -413,7 +386,8 @@ void fit_print_contents(const void *fit)
 	int images_noffset;
 	int confs_noffset;
 	int noffset;
-	int count;
+	int ndepth;
+	int count = 0;
 	int ret;
 	const char *p;
 	time_t timestamp;
@@ -450,12 +424,20 @@ void fit_print_contents(const void *fit)
 	}
 
 	/* Process its subnodes, print out component images details */
-	count = 0;
-	fdt_for_each_subnode(noffset, fit, images_noffset) {
-		printf("%s Image %u (%s)\n", p, count++,
-		       fit_get_name(fit, noffset, NULL));
+	for (ndepth = 0, count = 0,
+		noffset = fdt_next_node(fit, images_noffset, &ndepth);
+	     (noffset >= 0) && (ndepth > 0);
+	     noffset = fdt_next_node(fit, noffset, &ndepth)) {
+		if (ndepth == 1) {
+			/*
+			 * Direct child node of the images parent node,
+			 * i.e. component image node.
+			 */
+			printf("%s Image %u (%s)\n", p, count++,
+			       fit_get_name(fit, noffset, NULL));
 
-		fit_image_print(fit, noffset, p);
+			fit_image_print(fit, noffset, p);
+		}
 	}
 
 	/* Find configurations parent node offset */
@@ -467,17 +449,25 @@ void fit_print_contents(const void *fit)
 	}
 
 	/* get default configuration unit name from default property */
-	uname = (char *)fdt_getprop(fit, confs_noffset, FIT_DEFAULT_PROP, NULL);
+	uname = (char *)fdt_getprop(fit, noffset, FIT_DEFAULT_PROP, NULL);
 	if (uname)
 		printf("%s Default Configuration: '%s'\n", p, uname);
 
 	/* Process its subnodes, print out configurations details */
-	count = 0;
-	fdt_for_each_subnode(noffset, fit, confs_noffset) {
-		printf("%s Configuration %u (%s)\n", p, count++,
-		       fit_get_name(fit, noffset, NULL));
+	for (ndepth = 0, count = 0,
+		noffset = fdt_next_node(fit, confs_noffset, &ndepth);
+	     (noffset >= 0) && (ndepth > 0);
+	     noffset = fdt_next_node(fit, noffset, &ndepth)) {
+		if (ndepth == 1) {
+			/*
+			 * Direct child node of the configurations parent node,
+			 * i.e. configuration node.
+			 */
+			printf("%s Configuration %u (%s)\n", p, count++,
+			       fit_get_name(fit, noffset, NULL));
 
-		fit_conf_print(fit, noffset, p);
+			fit_conf_print(fit, noffset, p);
+		}
 	}
 }
 
@@ -504,6 +494,7 @@ void fit_image_print(const void *fit, int image_noffset, const char *p)
 	ulong load, entry;
 	const void *data;
 	int noffset;
+	int ndepth;
 	int ret;
 
 	if (!CONFIG_IS_ENABLED(FIT_PRINT))
@@ -593,8 +584,14 @@ void fit_image_print(const void *fit, int image_noffset, const char *p)
 	}
 
 	/* Process all hash subnodes of the component image node */
-	fdt_for_each_subnode(noffset, fit, image_noffset)
-		fit_image_print_verification_data(fit, noffset, p);
+	for (ndepth = 0, noffset = fdt_next_node(fit, image_noffset, &ndepth);
+	     (noffset >= 0) && (ndepth > 0);
+	     noffset = fdt_next_node(fit, noffset, &ndepth)) {
+		if (ndepth == 1) {
+			/* Direct child node of the component image node */
+			fit_image_print_verification_data(fit, noffset, p);
+		}
+	}
 }
 
 /**
@@ -1480,6 +1477,7 @@ int fit_all_image_verify(const void *fit)
 {
 	int images_noffset;
 	int noffset;
+	int ndepth;
 	int count;
 
 	/* Find images parent node offset */
@@ -1493,15 +1491,23 @@ int fit_all_image_verify(const void *fit)
 	/* Process all image subnodes, check hashes for each */
 	printf("## Checking hash(es) for FIT Image at %08lx ...\n",
 	       (ulong)fit);
-	count = 0;
-	fdt_for_each_subnode(noffset, fit, images_noffset) {
-		printf("   Hash(es) for Image %u (%s): ", count,
-		       fit_get_name(fit, noffset, NULL));
-		count++;
+	for (ndepth = 0, count = 0,
+	     noffset = fdt_next_node(fit, images_noffset, &ndepth);
+			(noffset >= 0) && (ndepth > 0);
+			noffset = fdt_next_node(fit, noffset, &ndepth)) {
+		if (ndepth == 1) {
+			/*
+			 * Direct child node of the images parent node,
+			 * i.e. component image node.
+			 */
+			printf("   Hash(es) for Image %u (%s): ", count,
+			       fit_get_name(fit, noffset, NULL));
+			count++;
 
-		if (!fit_image_verify(fit, noffset))
-			return 0;
-		printf("\n");
+			if (!fit_image_verify(fit, noffset))
+				return 0;
+			printf("\n");
+		}
 	}
 	return 1;
 }
@@ -1728,6 +1734,7 @@ int fit_check_format(const void *fit, ulong size)
 
 int fit_conf_find_compat(const void *fit, const void *fdt)
 {
+	int ndepth = 0;
 	int noffset, confs_noffset, images_noffset;
 	const void *fdt_compat;
 	int fdt_compat_len;
@@ -1750,7 +1757,9 @@ int fit_conf_find_compat(const void *fit, const void *fdt)
 	/*
 	 * Loop over the configurations in the FIT image.
 	 */
-	fdt_for_each_subnode(noffset, fit, confs_noffset) {
+	for (noffset = fdt_next_node(fit, confs_noffset, &ndepth);
+			(noffset >= 0) && (ndepth > 0);
+			noffset = fdt_next_node(fit, noffset, &ndepth)) {
 		const void *fdt;
 		const char *kfdt_name;
 		int kfdt_noffset, compat_noffset;
@@ -1759,6 +1768,9 @@ int fit_conf_find_compat(const void *fit, const void *fdt)
 		size_t sz;
 		int i;
 
+		if (ndepth > 1)
+			continue;
+
 		/* If there's a compat property in the config node, use that. */
 		if (fdt_getprop(fit, noffset, FIT_COMPAT_PROP, NULL)) {
 			fdt = fit;		  /* search in FIT image */
@@ -2630,299 +2642,3 @@ out:
 	return fdt_noffset;
 }
 #endif
-
-#if !defined(USE_HOSTCC) && CONFIG_IS_ENABLED(FIT_VERITY)
-
-static const char *const verity_opt_props[] = {
-	FIT_VERITY_OPT_RESTART,
-	FIT_VERITY_OPT_PANIC,
-	FIT_VERITY_OPT_RERR,
-	FIT_VERITY_OPT_PERR,
-	FIT_VERITY_OPT_ONCE,
-};
-
-/**
- * fit_verity_build_target() - build one dm-verity target specification
- * @fit:	pointer to the FIT blob
- * @img_noffset:	image node offset containing the dm-verity subnode
- * @loadable_idx:	index of this loadable (for /dev/fitN)
- * @uname:	unit name of the image
- * @separator:	true if a ";" prefix is needed (not the first target)
- * @buf:	output buffer, or NULL to measure only
- * @bufsize:	size of @buf (ignored when @buf is NULL)
- *
- * Parses all dm-verity properties from the image's ``dm-verity`` child
- * node and writes (or measures) a dm target specification string of the
- * form used by the ``dm-mod.create`` kernel parameter.
- *
- * Return: number of characters that would be written (excluding '\0'),
- *	    or -ve errno on error (e.g. missing mandatory property)
- */
-static int fit_verity_build_target(const void *fit, int img_noffset,
-				   int loadable_idx, const char *uname,
-				   bool separator, char *buf, int bufsize)
-{
-	const char *algorithm;
-	const u8 *digest_raw, *salt_raw;
-	const fdt32_t *val;
-	char *digest_hex = NULL, *salt_hex = NULL, *opt_buf = NULL;
-	int verity_node;
-	unsigned int data_block_size, hash_block_size;
-	int num_data_blocks, hash_start_block;
-	u64 data_sectors;
-	int digest_len, salt_len;
-	int opt_count, opt_off, opt_buf_size;
-	int len;
-	int i;
-
-	verity_node = fdt_subnode_offset(fit, img_noffset, FIT_VERITY_NODENAME);
-	if (verity_node < 0)
-		return -ENOENT;
-
-	/* Mandatory u32 properties */
-	val = fdt_getprop(fit, verity_node, FIT_VERITY_DBS_PROP, NULL);
-	if (!val)
-		return -EINVAL;
-	data_block_size = fdt32_to_cpu(*val);
-
-	val = fdt_getprop(fit, verity_node, FIT_VERITY_HBS_PROP, NULL);
-	if (!val)
-		return -EINVAL;
-	hash_block_size = fdt32_to_cpu(*val);
-
-	val = fdt_getprop(fit, verity_node, FIT_VERITY_NBLK_PROP, NULL);
-	if (!val)
-		return -EINVAL;
-	num_data_blocks = fdt32_to_cpu(*val);
-
-	val = fdt_getprop(fit, verity_node, FIT_VERITY_HBLK_PROP, NULL);
-	if (!val)
-		return -EINVAL;
-	hash_start_block = fdt32_to_cpu(*val);
-
-	if (data_block_size < 512U || !is_power_of_2(data_block_size) ||
-	    hash_block_size < 512U || !is_power_of_2(hash_block_size) ||
-	    !num_data_blocks)
-		return -EINVAL;
-
-	/* Mandatory string */
-	algorithm = fdt_getprop(fit, verity_node, FIT_VERITY_ALGO_PROP, NULL);
-	if (!algorithm)
-		return -EINVAL;
-
-	/* Mandatory byte arrays */
-	digest_raw = fdt_getprop(fit, verity_node, FIT_VERITY_DIGEST_PROP,
-				 &digest_len);
-	if (!digest_raw || digest_len <= 0)
-		return -EINVAL;
-
-	salt_raw = fdt_getprop(fit, verity_node, FIT_VERITY_SALT_PROP,
-			       &salt_len);
-	if (!salt_raw || salt_len <= 0)
-		return -EINVAL;
-
-	/* Hex-encode digest and salt into dynamically sized buffers */
-	digest_hex = malloc(digest_len * 2 + 1);
-	salt_hex = malloc(salt_len * 2 + 1);
-	if (!digest_hex || !salt_hex) {
-		len = -ENOMEM;
-		goto out;
-	}
-	*bin2hex(digest_hex, digest_raw, digest_len) = '\0';
-	*bin2hex(salt_hex, salt_raw, salt_len) = '\0';
-
-	data_sectors = (u64)num_data_blocks * ((u64)data_block_size / 512);
-
-	/* Compute space needed for optional boolean properties */
-	opt_buf_size = 1; /* NUL terminator */
-	for (i = 0; i < ARRAY_SIZE(verity_opt_props); i++)
-		opt_buf_size += strlen(verity_opt_props[i]) + 1;
-	opt_buf = malloc(opt_buf_size);
-	if (!opt_buf) {
-		len = -ENOMEM;
-		goto out;
-	}
-
-	/* Collect optional boolean properties */
-	opt_count = 0;
-	opt_off = 0;
-	opt_buf[0] = '\0';
-	for (i = 0; i < ARRAY_SIZE(verity_opt_props); i++) {
-		if (fdt_getprop(fit, verity_node,
-				verity_opt_props[i], NULL)) {
-			const char *s = verity_opt_props[i];
-			int slen = strlen(s);
-
-			if (opt_off)
-				opt_buf[opt_off++] = ' ';
-			/* Copy with hyphen-to-underscore conversion */
-			while (slen-- > 0) {
-				opt_buf[opt_off++] =
-					(*s == '-') ? '_' : *s;
-				s++;
-			}
-			opt_buf[opt_off] = '\0';
-			opt_count++;
-		}
-	}
-
-	/* Emit (or measure) the target spec */
-	len = snprintf(buf, buf ? bufsize : 0,
-		       "%s%s,,, ro,0 %llu verity 1 /dev/fit%d /dev/fit%d %u %u %d %d %s %s %s",
-		       separator ? ";" : "", uname,
-		       (unsigned long long)data_sectors, loadable_idx, loadable_idx,
-		       data_block_size, hash_block_size,
-		       num_data_blocks, hash_start_block,
-		       algorithm, digest_hex, salt_hex);
-	if (opt_count) {
-		int extra = snprintf(buf ? buf + len : NULL,
-				     buf ? bufsize - len : 0,
-				     " %d %s", opt_count, opt_buf);
-		len += extra;
-	}
-
-out:
-	free(digest_hex);
-	free(salt_hex);
-	free(opt_buf);
-	return len;
-}
-
-int fit_verity_build_cmdline(const void *fit, int conf_noffset,
-			     struct bootm_headers *images)
-{
-	int images_noffset;
-	int dm_create_len = 0, dm_waitfor_len = 0;
-	char *dm_create = NULL, *dm_waitfor = NULL;
-	const char *uname;
-	int loadable_idx;
-	int found = 0;
-	int ret = 0;
-
-	images_noffset = fdt_path_offset(fit, FIT_IMAGES_PATH);
-	if (images_noffset < 0)
-		return 0;
-
-	for (loadable_idx = 0;
-	     (uname = fdt_stringlist_get(fit, conf_noffset,
-					 FIT_LOADABLE_PROP,
-					 loadable_idx, NULL));
-	     loadable_idx++) {
-		int img_noffset, need;
-		u8 img_type;
-		char *tmp;
-
-		img_noffset = fdt_subnode_offset(fit, images_noffset, uname);
-		if (img_noffset < 0)
-			continue;
-
-		if (fit_image_get_type(fit, img_noffset, &img_type) ||
-		    img_type != IH_TYPE_FILESYSTEM)
-			continue;
-
-		/* Measure first, then allocate and write */
-		need = fit_verity_build_target(fit, img_noffset,
-					       loadable_idx, uname,
-					       found > 0, NULL, 0);
-		if (need == -ENOENT)
-			continue;	/* no dm-verity subnode -- fine */
-		if (need < 0) {
-			log_err("FIT: broken dm-verity metadata in '%s'\n",
-				uname);
-			ret = need;
-			goto err;
-		}
-
-		tmp = realloc(dm_create, dm_create_len + need + 1);
-		if (!tmp) {
-			ret = -ENOMEM;
-			goto err;
-		}
-		dm_create = tmp;
-		fit_verity_build_target(fit, img_noffset, loadable_idx,
-					uname, found > 0,
-					dm_create + dm_create_len,
-					need + 1);
-		dm_create_len += need;
-
-		/* Grow dm_waitfor buffer */
-		need = snprintf(NULL, 0, "%s/dev/fit%d",
-				dm_waitfor_len ? "," : "",
-				loadable_idx);
-		tmp = realloc(dm_waitfor, dm_waitfor_len + need + 1);
-		if (!tmp) {
-			ret = -ENOMEM;
-			goto err;
-		}
-		dm_waitfor = tmp;
-		sprintf(dm_waitfor + dm_waitfor_len, "%s/dev/fit%d",
-			dm_waitfor_len ? "," : "",
-			loadable_idx);
-		dm_waitfor_len += need;
-
-		found++;
-	}
-
-	if (found) {
-		/* Transfer ownership to the bootm_headers */
-		images->dm_mod_create = dm_create;
-		images->dm_mod_waitfor = dm_waitfor;
-	} else {
-		free(dm_create);
-		free(dm_waitfor);
-	}
-
-	return 0;
-
-err:
-	free(dm_create);
-	free(dm_waitfor);
-	return ret;
-}
-
-/**
- * fmt used by both the measurement and the actual write of bootargs.
- * Shared to guarantee they stay in sync.
- */
-#define VERITY_BOOTARGS_FMT	"%s%sdm-mod.create=\"%s\" dm-mod.waitfor=\"%s\""
-
-int fit_verity_apply_bootargs(const struct bootm_headers *images)
-{
-	const char *existing;
-	char *newargs;
-	int len;
-
-	if (!images->dm_mod_create)
-		return 0;
-
-	existing = env_get("bootargs");
-	if (!existing)
-		existing = "";
-
-	/* Measure */
-	len = snprintf(NULL, 0, VERITY_BOOTARGS_FMT,
-		       existing, existing[0] ? " " : "",
-		       images->dm_mod_create, images->dm_mod_waitfor);
-
-	newargs = malloc(len + 1);
-	if (!newargs)
-		return -ENOMEM;
-
-	snprintf(newargs, len + 1, VERITY_BOOTARGS_FMT,
-		 existing, existing[0] ? " " : "",
-		 images->dm_mod_create, images->dm_mod_waitfor);
-
-	env_set("bootargs", newargs);
-	free(newargs);
-
-	return 0;
-}
-
-void fit_verity_free(struct bootm_headers *images)
-{
-	free(images->dm_mod_create);
-	free(images->dm_mod_waitfor);
-	images->dm_mod_create = NULL;
-	images->dm_mod_waitfor = NULL;
-}
-#endif /* FIT_VERITY */

cmd/Kconfig

@@ -1871,8 +1871,8 @@ config CMD_PVBLOCK
 
 config CMD_VIRTIO
 	bool "virtio"
-	depends on VIRTIO_BLK
-	default y if VIRTIO_BLK
+	depends on VIRTIO
+	default y if VIRTIO
 	help
 	  VirtIO block device support
 

cmd/cros_ec.c

@@ -13,7 +13,7 @@
 #include <dm/device-internal.h>
 #include <dm/uclass-internal.h>
 
-/* Note: depends on enum ec_image */
+/* Note: depends on enum ec_current_image */
 static const char * const ec_current_image_name[] = {"unknown", "RO", "RW"};
 
 /**
@@ -312,7 +312,7 @@ static int do_cros_ec(struct cmd_tbl *cmdtp, int flag, int argc,
 		if (ret)
 			printf("Error: %d\n", ret);
 	} else if (0 == strcmp("curimage", cmd)) {
-		enum ec_image image;
+		enum ec_current_image image;
 
 		if (cros_ec_read_current_image(dev, &image)) {
 			debug("%s: Could not read KBC image\n", __func__);

cmd/ufetch.c

@@ -157,37 +157,26 @@ static int do_ufetch(struct cmd_tbl *cmdtp, int flag, int argc,
 				printf(" (%d baud)", gd->baudrate);
 			putc('\n');
 			break;
-		case FEATURES: {
-			const char *sep = "";
-
+		case FEATURES:
 			printf("Features:" RESET " ");
-			if (IS_ENABLED(CONFIG_NET)) {
-				printf("%sNet", sep);
-				sep = ", ";
-			}
-			if (IS_ENABLED(CONFIG_EFI_LOADER)) {
-				printf("%sEFI", sep);
-				sep = ", ";
-			}
-			if (IS_ENABLED(CONFIG_CMD_CAT)) {
-				printf("%scat :3", sep);
-				sep = ", ";
-			}
+			if (IS_ENABLED(CONFIG_NET_LEGACY))
+				printf("Net");
+			if (IS_ENABLED(CONFIG_EFI_LOADER))
+				printf(", EFI");
+			if (IS_ENABLED(CONFIG_CMD_CAT))
+				printf(", cat :3");
 #ifdef CONFIG_ARM64
 			switch (current_el()) {
 			case 2:
-				printf("%sVMs", sep);
-				sep = ", ";
+				printf(", VMs");
 				break;
 			case 3:
-				printf("%sfull control!", sep);
-				sep = ", ";
+				printf(", full control!");
 				break;
 			}
 #endif
 			printf("\n");
 			break;
-		}
 		case RELOCATION:
 			if (gd->flags & GD_FLG_SKIP_RELOC)
 				printf("Relocated:" RESET " no\n");

common/bloblist.c

@@ -448,7 +448,6 @@ int bloblist_new(ulong addr, uint size, uint flags, uint align_log2)
 	hdr->align_log2 = align_log2 ? align_log2 : BLOBLIST_BLOB_ALIGN_LOG2;
 	hdr->chksum = 0;
 	gd->bloblist = hdr;
-	gd->flags |= GD_FLG_BLOBLIST_READY;
 
 	return 0;
 }
@@ -476,7 +475,6 @@ int bloblist_check(ulong addr, uint size)
 		return log_msg_ret("Bad checksum", -EIO);
 	}
 	gd->bloblist = hdr;
-	gd->flags |= GD_FLG_BLOBLIST_READY;
 
 	return 0;
 }
@@ -578,88 +576,90 @@ int __weak xferlist_from_boot_arg(ulong __always_unused *addr)
 	return -ENOENT;
 }
 
-bool bloblist_exists(void)
+int bloblist_init(void)
 {
-	int ret;
-	ulong addr = 0;
+	bool fixed = IS_ENABLED(CONFIG_BLOBLIST_FIXED);
+	int ret = 0;
+	ulong addr = 0, size;
 
 	/* Check if a valid transfer list passed in */
-	if (!xferlist_from_boot_arg(&addr))
-		goto found;
+	if (!xferlist_from_boot_arg(&addr)) {
+		size = bloblist_get_total_size();
+	} else {
+		/*
+		 * If U-Boot is not in the first phase, an existing bloblist must
+		 * be at a fixed address.
+		 */
+		bool from_addr = fixed && !xpl_is_first_phase();
 
-	/*
-	 * If Firmware Handoff is mandatory but no transfer list is
-	 * observed, report it as an error.
-	 */
-	if (IS_ENABLED(CONFIG_BLOBLIST_PASSAGE_MANDATORY))
-		return false;
+		/*
+		 * If Firmware Handoff is mandatory but no transfer list is
+		 * observed, report it as an error.
+		 */
+		if (IS_ENABLED(CONFIG_BLOBLIST_PASSAGE_MANDATORY))
+			return -ENOENT;
 
-	/*
-	 * We have checked for a valid transfer list being passed. At this
-	 * point, if we do not have a fixed address for the bloblist, we cannot
-	 * be provided with one.
-	 */
-	if (xpl_is_first_phase() || !IS_ENABLED(CONFIG_BLOBLIST_FIXED))
-		return false;
+		ret = -ENOENT;
 
-	/*
-	 * Check for a valid list as the configured address.
-	 */
-	addr = IF_ENABLED_INT(CONFIG_BLOBLIST_FIXED,
-			      CONFIG_BLOBLIST_ADDR);
-	ret = bloblist_check(addr, CONFIG_BLOBLIST_SIZE);
-	if (!ret)
-		goto found;
+		if (xpl_prev_phase() == PHASE_TPL &&
+		    !IS_ENABLED(CONFIG_TPL_BLOBLIST))
+			from_addr = false;
+		if (fixed)
+			addr = IF_ENABLED_INT(CONFIG_BLOBLIST_FIXED,
+					      CONFIG_BLOBLIST_ADDR);
+		size = CONFIG_BLOBLIST_SIZE;
 
-	log_debug("Bloblist at %lx not found (err=%d)\n", addr, ret);
-	return false;
+		if (from_addr)
+			ret = bloblist_check(addr, size);
+
+		if (ret)
+			log_warning("Bloblist at %lx not found (err=%d)\n",
+				    addr, ret);
+		else
+			/* Get the real size */
+			size = gd->bloblist->total_size;
+	}
+
+	if (ret) {
+		/*
+		 * If we don't have a bloblist from a fixed address, or the one
+		 * in the fixed address is not valid. we must allocate the
+		 * memory for it now.
+		 */
+		if (CONFIG_IS_ENABLED(BLOBLIST_ALLOC)) {
+			void *ptr = memalign(BLOBLIST_ALIGN, size);
+
+			if (!ptr)
+				return log_msg_ret("alloc", -ENOMEM);
+			addr = map_to_sysmem(ptr);
+		} else if (!fixed) {
+			return log_msg_ret("BLOBLIST_FIXED is not enabled",
+					   ret);
+		}
+		log_debug("Creating new bloblist size %lx at %lx\n", size,
+			  addr);
+		ret = bloblist_new(addr, size, 0, 0);
+	} else {
+		log_debug("Found existing bloblist size %lx at %lx\n", size,
+			  addr);
+	}
+
+	if (ret)
+		return log_msg_ret("ini", ret);
+	gd->flags |= GD_FLG_BLOBLIST_READY;
 
-found:
 #ifdef DEBUG
 	bloblist_show_stats();
 	bloblist_show_list();
 #endif
-	return true;
+
+	return 0;
 }
 
-int bloblist_init(void)
+int bloblist_maybe_init(void)
 {
-	int ret;
-	ulong addr = 0, size = CONFIG_BLOBLIST_SIZE;
-
-	if (gd->flags & GD_FLG_BLOBLIST_READY) {
-		log_debug("Found existing bloblist size %x at %p\n",
-			  gd->bloblist->total_size, gd->bloblist);
-		return 0;
-	}
-
-	/*
-	 * If Firmware Handoff is mandatory but no transfer list has been
-	 * observed by fdtdec_setup, report it as an error.
-	 */
-	if (IS_ENABLED(CONFIG_BLOBLIST_PASSAGE_MANDATORY))
-		return -ENOENT;
-
-	/*
-	 * If we don't have an existing bloblist, we either need
-	 * to allocate one now, or initialize the fixed address
-	 * space as a bloblist.
-	 */
-	if (CONFIG_IS_ENABLED(BLOBLIST_ALLOC)) {
-		void *ptr = memalign(BLOBLIST_ALIGN, size);
-
-		if (!ptr)
-			return log_msg_ret("alloc", -ENOMEM);
-		addr = map_to_sysmem(ptr);
-	} else
-		addr = IF_ENABLED_INT(CONFIG_BLOBLIST_FIXED,
-				      CONFIG_BLOBLIST_ADDR);
-
-	log_debug("Creating new bloblist size %lx at %lx\n", size,
-		  addr);
-	ret = bloblist_new(addr, size, 0, 0);
-	if (ret)
-		return log_msg_ret("ini", ret);
+	if (CONFIG_IS_ENABLED(BLOBLIST) && !(gd->flags & GD_FLG_BLOBLIST_READY))
+		return bloblist_init();
 
 	return 0;
 }
@@ -687,9 +687,7 @@ int bloblist_check_reg_conv(ulong rfdt, ulong rzero, ulong rsig, ulong xlist)
 		return ret;
 
 	if (rfdt != (ulong)bloblist_find(BLOBLISTT_CONTROL_FDT, 0)) {
-		/* Remove this bloblist from gd */
-		gd->bloblist = NULL;
-		gd->flags &= ~GD_FLG_BLOBLIST_READY;
+		gd->bloblist = NULL;  /* Reset the gd bloblist pointer */
 		return -EIO;
 	}
 

common/board_f.c

@@ -894,9 +894,7 @@ static void initcall_run_f(void)
 	INITCALL(log_init);
 	INITCALL(initf_bootstage); /* uses its own timer, so does not need DM */
 	INITCALL(event_init);
-#if CONFIG_IS_ENABLED(BLOBLIST)
-	INITCALL(bloblist_init);
-#endif
+	INITCALL(bloblist_maybe_init);
 	INITCALL(setup_spl_handoff);
 #if CONFIG_IS_ENABLED(CONSOLE_RECORD_INIT_F)
 	INITCALL(console_record_init);

common/cli.c

@@ -138,9 +138,11 @@ int run_command_list(const char *cmd, int len, int flag)
 #endif
 	}
 	if (need_buff) {
-		buff = memdup_nul(cmd, len);
+		buff = malloc(len + 1);
 		if (!buff)
 			return 1;
+		memcpy(buff, cmd, len);
+		buff[len] = '\0';
 	}
 #ifdef CONFIG_HUSH_PARSER
 	if (use_hush_old()) {

common/command.c

@@ -367,15 +367,11 @@ int cmd_auto_complete(const char *const prompt, char *buf, int *np, int *colp)
 	int i, j, k, len, seplen, argc;
 	int cnt;
 	char last_char;
-	const char *ps_prompt;
-
-	if (IS_ENABLED(CONFIG_CMDLINE_PS_SUPPORT)) {
-		ps_prompt = env_get("PS1");
-
-		if (!ps_prompt)
-			ps_prompt = CONFIG_SYS_PROMPT;
-	} else
-		ps_prompt = CONFIG_SYS_PROMPT;
+#ifdef CONFIG_CMDLINE_PS_SUPPORT
+	const char *ps_prompt = env_get("PS1");
+#else
+	const char *ps_prompt = CONFIG_SYS_PROMPT;
+#endif
 
 	if (strcmp(prompt, ps_prompt) != 0)
 		return 0;	/* not in normal console */

common/spl/Kconfig

@@ -220,7 +220,7 @@ source "common/spl/Kconfig.nxp"
 
 config HANDOFF
 	bool "Pass hand-off information from SPL to U-Boot proper"
-	depends on BLOBLIST_FIXED
+	depends on BLOBLIST
 	help
 	  It is useful to be able to pass information from SPL to U-Boot
 	  proper to preserve state that is known in SPL and is needed in U-Boot.

common/spl/spl_imx_container.c

@@ -88,7 +88,6 @@ static int read_auth_container(struct spl_image_info *spl_image,
 			       struct spl_load_info *info, ulong offset)
 {
 	struct container_hdr *container = NULL;
-	struct container_hdr *authhdr;
 	u16 length;
 	int i, size, ret = 0;
 
@@ -141,19 +140,15 @@ static int read_auth_container(struct spl_image_info *spl_image,
 		}
 	}
 
-	authhdr = container;
-
 #ifdef CONFIG_AHAB_BOOT
-	authhdr = ahab_auth_cntr_hdr(authhdr, length);
-	if (!authhdr) {
-		ret = -EINVAL;
+	ret = ahab_auth_cntr_hdr(container, length);
+	if (ret)
 		goto end_auth;
-	}
 #endif
 
-	for (i = 0; i < authhdr->num_images; i++) {
+	for (i = 0; i < container->num_images; i++) {
 		struct boot_img_t *image = read_auth_image(spl_image, info,
-							   authhdr, i,
+							   container, i,
 							   offset);
 
 		if (!image) {

common/splash_source.c

@@ -159,12 +159,12 @@ static int splash_select_fs_dev(struct splash_location *location)
 			res = -ENODEV;
 		break;
 	default:
-		printf("Error: %s: unsupported location storage.\n", __func__);
+		printf("Error: unsupported location storage.\n");
 		return -ENODEV;
 	}
 
 	if (res)
-		printf("Error: %s: could not access storage.\n", __func__);
+		printf("Error: could not access storage.\n");
 
 	return res;
 }
@@ -284,8 +284,7 @@ static int splash_load_fs(struct splash_location *location, ulong bmp_load_addr)
 
 	res = fs_size(splash_file, &bmp_size);
 	if (res) {
-		printf("Error: %s: cannot determine file size (%d)\n",
-		       __func__, res);
+		printf("Error (%d): cannot determine file size\n", res);
 		goto out;
 	}
 

common/stdio.c

@@ -217,11 +217,27 @@ struct stdio_dev *stdio_get_by_name(const char *name)
 	return NULL;
 }
 
+struct stdio_dev *stdio_clone(struct stdio_dev *dev)
+{
+	struct stdio_dev *_dev;
+
+	if (!dev)
+		return NULL;
+
+	_dev = calloc(1, sizeof(struct stdio_dev));
+	if (!_dev)
+		return NULL;
+
+	memcpy(_dev, dev, sizeof(struct stdio_dev));
+
+	return _dev;
+}
+
 int stdio_register_dev(struct stdio_dev *dev, struct stdio_dev **devp)
 {
 	struct stdio_dev *_dev;
 
-	_dev = memdup(dev, sizeof(*dev));
+	_dev = stdio_clone(dev);
 	if (!_dev)
 		return -ENODEV;
 	list_add_tail(&_dev->list, &devs.list);

configs/am62x_a53_splashscreen.config

@@ -1,16 +0,0 @@
-CONFIG_FDT_SIMPLEFB=y
-CONFIG_VIDEO=y
-CONFIG_SYS_WHITE_ON_BLACK=y
-CONFIG_SPL_VIDEO_TIDSS=y
-CONFIG_BMP_24BPP=y
-CONFIG_BMP_32BPP=y
-CONFIG_SPL_VIDEO=y
-CONFIG_SPL_SPLASH_SCREEN=y
-CONFIG_SPL_SYS_WHITE_ON_BLACK=y
-CONFIG_SPL_SPLASH_SCREEN_ALIGN=y
-CONFIG_SPL_SPLASH_SOURCE=y
-CONFIG_SPL_BMP=y
-CONFIG_SPL_VIDEO_BMP_GZIP=y
-CONFIG_SPL_BMP_24BPP=y
-CONFIG_SPL_BMP_32BPP=y
-CONFIG_SPL_HIDE_LOGO_VERSION=y