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1090 Commits

Author SHA1 Message Date
Wolfgang Denk
ca6e1c136d Prepare v2010.03
Signed-off-by: Wolfgang Denk <wd@denx.de>
2010-03-31 23:54:39 +02:00
Heiko Schocher
8e64d6efd8 net, doc: How to setup MAC address correctly
As this seems unclear, document how the flow of setting up
the MAC address is correct.

Signed-off-by: Heiko Schocher <hs@denx.de>

Text changed slightly, adding input from Mike Frysinger.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2010-03-31 15:13:32 +02:00
Heiko Schocher
b78b48c6a0 net, fec_mxc: only setup the device enetaddr with eeprom value
Only fill the device enetaddr with the contents of the eeprom,
do not program it in MAC address registers

Signed-off-by: Heiko Schocher <hs@denx.de>
Acked-by: Ben Warren <biggerbadderben@gmail.com>
2010-03-31 15:13:31 +02:00
Felix Radensky
d5a64237d5 doc: Fix ramdisk examples in doc/uImage.FIT/multi.its
The ramdisk sections in doc/uImage.FIT/multi.its lack
load address and entry point properties. Using examples
from this file will result in unbootable image, u-boot
will issue the following error messages:

Can't get ramdisk subimage load address!
Ramdisk image is corrupt or invalid

This patch adds missing properties to ramdisk sections.

Signed-off-by: Felix Radensky <felix@embedded-sol.com>
2010-03-31 15:13:31 +02:00
Heiko Schocher
2d2018f3db jffs2, suen3: Fix compiler warning
$ ./MAKEALL suen3
jffs2_1pass.c: In function 'get_fl_mem':
jffs2_1pass.c:399: warning: unused variable 'id'
jffs2_1pass.c: In function 'get_node_mem':
jffs2_1pass.c:423: warning: unused variable 'id'

Signed-off-by: Heiko Schocher <hs@denx.de>
Tested-by: Tom <Tom.Rix@windriver.com>
2010-03-31 15:13:31 +02:00
Wolfgang Denk
f3dfbb6816 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2010-03-30 22:22:47 +02:00
Wolfgang Denk
7d3ef4fa20 Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx 2010-03-30 22:21:24 +02:00
Timur Tabi
9ff32d8ccf mpc86xx: set the DDR BATs after calculating true DDR size
After determining how much DDR is actually in the system, set DBAT0 and
IBAT0 accordingly.  This ensures that the CPU won't attempt to access
(via speculation) addresses outside of actual memory.

On 86xx systems, DBAT0 and IBAT0 (the BATs for DDR) are initialized to 2GB
and kept that way.  If the system has less than 2GB of memory (typical for
an MPC8610 HPCD), the CPU may attempt to access this memory during
speculation.  The zlib code is notorious for generating such memory reads,
and indeed on the MPC8610, uncompressing the Linux kernel causes a machine
check (without this patch).

Currently we are limited to power of two sized DDR since we only use a
single bat.  If a non-power of two size is used that is less than
CONFIG_MAX_MEM_MAPPED u-boot will crash.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-03-30 10:50:22 -05:00
Kumar Gala
33f57bd553 85xx: Fix enabling of L1 cache parity on secondary cores
Use the same code between primary and secondary cores to init the
L1 cache.  We were not enabling cache parity on the secondary cores.

Also, reworked the L1 cache init code to match the e500mc L2 init code
that first invalidates the cache and locks.  Than enables the cache and
makes sure its enabled before continuing.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-03-30 10:48:30 -05:00
Stefan Roese
1a332da61d ppc4xx: Fix problem with I2C bus >= 1 initialization
This patch fixes a problem introduced with patch eb5eb2b0
[ppc4xx: Cleanup PPC4xx I2C infrastructure]. We need to assign the I2C
base address to the "i2c" pointer inside of the controller loop.
Otherwise controller 0 is initialized multiple times instead of
initializing each I2C controller sequentially.

Tested on Katmai.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>
2010-03-30 13:05:05 +02:00
Heiko Schocher
24de2f4be0 bootm, linux: fix booting Multi-File Image with "kernel+ramdisk+fdt"
Booting a "Multi-File Image" including a linux kernel, ramdisk and
fdt, generated with

mkimage -A ppc \
    -O linux \
    -T multi \
    -C gzip \
    -a 00000000 \
    -e 00000000 \
    -n "kernel-2.6+initrd+dtb" \
    -d "vmlinux.bin.gz:ramdisk_image.gz:board.dtb" \
    multi.bin

actually fails, because ramdisk start and end addresses
didn;t get initialized. This patch fixes this issue.

Tested on the KUP4K board.

Signed-off-by: Heiko Schocher <hs@denx.de>
2010-03-29 14:31:42 +02:00
Wolfgang Denk
2883cc2d48 Prepare 2010.03-rc3
Update CHANGELOG

Signed-off-by: Wolfgang Denk <wd@denx.de>
2010-03-28 00:25:14 +01:00
Wolfgang Denk
060f28532b cmd_usb.c: print debug messages only when DEBUG is defined
Signed-off-by: Wolfgang Denk <wd@denx.de>
2010-03-28 00:19:45 +01:00
Wolfgang Denk
a574cff121 ml300: remove support for broken, orphaned board
The ml300 board has a number of issues, but nobody cares about this
long-orphaned board any more.  Remove it.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Acked-by: Michal Simek <monstr@monstr.eu>
2010-03-28 00:18:58 +01:00
Wolfgang Denk
cc3074c322 Merge branch 'master' of /home/wd/git/u-boot/custodians 2010-03-28 00:15:20 +01:00
Wolfgang Denk
04387d24a1 mkimage: fix Segmentation Fault when run without "-n name" option
The restructuring of the mkimage command in commit 89a4d6b1 ("tools:
mkimage: split code into core, default and FIT image specific")
introduced a bug that caused mkimage to segfault when run without
"-n name" option.  Initialize the imagename entry to prevent that.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2010-03-28 00:13:54 +01:00
Wolfgang Denk
4284f36a3e Merge branch 'master' of git://git.denx.de/u-boot-cfi-flash 2010-03-28 00:11:16 +01:00
Renato Andreola
c40c94a3d2 cfi_flash: precision and underflow problem in tout calculation
With old configuration it could happen tout=0 if CONFIG_SYS_HZ<1000.

Signed-off-by: Renato Andreola <renato.andreola@imagos.it>
Signed-off-by: Alessandro Rubini <rubini@gnudd.com>
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Stefan Roese <sr@denx.de>
2010-03-25 09:44:58 +01:00
Rupjyoti Sarmah
c550afada5 ppc4xx fix unstable 440EPx bootstrap options
440EPx fixed bootstrap options A, B, D, and E sets PLL FWDVA to a value = 1.
This results in the PLLOUTB being greater than the CPU clock frequency
resulting unstable 440EPx operation resulting in various software hang
conditions.

This patch reprograms the FWDVA satisfying the requirement of setting FWDVB
to a value greater than 1 while using one of the four deafult bootstrap options.

Signed-off-by: Rupjyoti Sarmah <rsarmah@amcc.com>
Acked-by : Victor Gallardo <vgallardo@appliedmicro.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2010-03-24 14:27:01 +01:00
Wolfgang Denk
7027d5622d Merge branch 'master' of git://git.denx.de/u-boot-video 2010-03-24 14:11:53 +01:00
Matthias Fuchs
fb508b8b39 at91: Get rid of some warnings when building for otc570
The soft-i2c code for AT91 defines I2C_SOFT_DECLARATIONS
for direct access by dereferencing a pio pointer.
The OTC570 platform uses the AT91 gpio API so it does not
need the pio variable.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
2010-03-24 13:06:24 +01:00
Alessandro Rubini
acb1386893 lcd: make 16bpp work
Support for 16bpp was supposed to be in the code but was not working.
This makes it work and has been tested in the nhk8815 board.

Signed-off-by: Alessandro Rubini <rubini@unipv.it>
Acked-by: Andrea Gallo <andrea.gallo@stericsson.com>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
2010-03-24 11:23:15 +01:00
Wolfgang Denk
152dda3d94 Prepare v2010.03-rc2
Update CHANGELOG

Signed-off-by: Wolfgang Denk <wd@denx.de>
2010-03-22 23:25:00 +01:00
Matthias Kaehlcke
d650da2dd4 ep93xx timer: Fix resolution of get_ticks()
ep93xx timer: Make get_ticks() return a value in CONFIG_SYS_HZ resolution,
as announced by get_tbclk()

Signed-off-by: Matthias Kaehlcke <matthias@kaehlcke.net>
2010-03-22 11:58:28 -05:00
Matthias Kaehlcke
7e67fb5bf2 ep93xx timer: Fix possible overflow in usecs_to_ticks()
ep93xx timer: Use 64-bit values in usecs_to_ticks() in order to avoid
overflows in intermediate values

Signed-off-by: Matthias Kaehlcke <matthias@kaehlcke.net>
2010-03-22 11:58:28 -05:00
Asen Dimov
daa989b472 correct a syntax typo in at91_matrix.h
Signed-off-by: Asen Dimov <dimov@ronetix.at>
2010-03-21 22:22:53 +01:00
Jeff Angielski
322ff395c9 env: fix endian ordering in crc table
The crc table was being built as little endian for big endian
targets.  This would cause fw_printenv to always fail with
"Warning: Bad CRC, using default environment" messages.

Signed-off-by: Jeff Angielski <jeff@theptrgroup.com>
Acked-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
2010-03-21 22:22:53 +01:00
Anatolij Gustschin
51c2ac9bb5 mpc5121: cpu/mpc512x/diu.c: fix warnings
Fix warnings while compiling with CONFIG_VIDEO enabled:

diu.c: In function 'video_hw_init':
diu.c:158: warning: 'return' with no value, in function returning non-void
diu.c:162: warning: format '%ld' expects type 'long int', but argument 6 has type 'int'
diu.c:162: warning: format '%ld' expects type 'long int', but argument 7 has type 'int'

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2010-03-21 22:22:53 +01:00
Anatolij Gustschin
a74908161a console.c: fix problem with splashimage
If a board uses cfb_console driver and splash image
and also defines CONFIG_SILENT_CONSOLE, the user is
locked out even if "silent" is not set. It is not
possible to get any output, neither on vga console
device nor on serial console after redirecting the
output to the serial console, since the GD_FLG_SILENT
flag remains set.

Fix the problem by redirecting the output from frame
buffer to serial console if splashimage is used.
Only suppress the output if "silent" environment
variable was set and don't set the GD_FLG_SILENT
flag arbitrarily.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2010-03-21 22:22:53 +01:00
Thomas Weber
5647f78d04 mod change 755 => 644 for multiple files
I executed 'find . -name "*.[chS]" -perm 755 -exec chmod 644 {} \;'

Signed-off-by: Thomas Weber <swirl@gmx.li>
Add some more: neither Makefile nor config.mk need execute permissions.
Signed-off-by: Wolfgang Denk <wd@denx.de>
2010-03-21 22:22:53 +01:00
Stefano Babic
99c006a320 mxcmmc: fix warnings due to access 32 bit registers with 16 bit accessors
Some registers of the mxcmmc driver were accessed using
16 bit accessor functions, because only the LSB is
significant. This is not needed and generates
warnings.

Signed-off-by: Stefano Babic <sbabic@denx.de>
2010-03-21 22:22:52 +01:00
Wolfgang Denk
c96f86eefc TFTP: allow for adjustable retransmission timout
So far, TFTP negotiated a fixed retransmission timeout of 5 seconds.
In some cases (busy networks, slow TFTP servers) this caused very
slow transfers. A new environment variable "tftptimeout" allows to
set this timeout. Lowering this value may make downloads succeed
faster in networks with high packet loss rates or with unreliable
TFTP servers.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Ben Warren <biggerbadderben@gmail.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2010-03-21 22:22:44 +01:00
Wolfgang Denk
252b404d95 Fix PCI_BASE_ADDRESS_5 handling in pci_hose_config_device()
Signed-off-by: FUJITA Kazutoshi <fujita@soum.co.jp>
Signed-off-by: <wd@denx.de>
Acked-by: Stefan Roese <sr@denx.de>
2010-03-21 17:58:07 +01:00
Frans Meulenbroeks
9d90a93d36 cmd_mmc remove \n
This patch removes the \n after the help message for mmcinfo.
This resulted in an empty line being displayed after the mmcinfo line
when the help command was given.

Signed-off-by: Frans Meulenbroeks <fransmeulenbroeks@gmail.com>
2010-03-21 16:44:04 +01:00
Renato Andreola
67c7189dd3 nios2: Added support to YANU UART
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
2010-03-16 16:01:29 -04:00
Thomas Chou
1e67fb32fb nios2: use generic unaligned.h
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
2010-03-16 12:12:48 -04:00
Wolfgang Denk
f1fdc42e5e Merge branch 'master' of git://git.denx.de/u-boot-video 2010-03-14 00:58:30 +01:00
Mike Frysinger
05022629a2 asm-blackfin/unaligned.h: add for zlib code
The new zlib code wants asm/unaligned.h, so have the Blackfin version pull
in the asm-generic/unaligned.h.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-03-14 00:11:16 +01:00
Mike Frysinger
3adc1fda38 asm-generic/unaligned.h: dynamic default unaligned accesses
This is based on the asm-arm/unaligned.h, but made generic so all arches
that cannot do unaligned accesses can utilize it.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-03-14 00:10:09 +01:00
Matthias Weisser
be129aa718 video: Fix console display when splashscreen is used
If a splashscreen is used the console scrolling used the
scroll size as needed when a logo was displayed. This
patch sets the scroll size to the whole screen if
a splashscreen is shown.

Signed-off-by: Matthias Weisser <matthias.weisser@graf-syteco.de>
2010-03-13 16:42:25 +01:00
Wolfgang Denk
93910edb59 Prepare v2010.03-rc1
Coding style cleanup, update CHANGELOG.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2010-03-12 23:06:04 +01:00
Wolfgang Denk
4e72fb15c9 standalone eepro100_eeprom: fix build error
Building examples/standalone/eepro100_eeprom triggers this error:

In file included from include/common.h:629,
                 from eepro100_eeprom.c:24:
include/net.h: In function 'NetReadIP':
include/net.h:430: warning: implicit declaration of function 'memcpy'
eepro100_eeprom.c: At top level:
eepro100_eeprom.c:81: error: conflicting types for 'memcpy'
include/net.h:430: error: previous implicit declaration of 'memcpy' was here

Fix this.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2010-03-12 22:56:50 +01:00
Wolfgang Denk
1bb1809558 Update .gitignore's: add some generated files
Signed-off-by: Wolfgang Denk <wd@denx.de>
2010-03-12 22:10:31 +01:00
Detlev Zundel
9c9cbe78dc mpc82xx: Remove SL8245 board and the now orpahned sk98lin network driver.
This code has compile problems and the company does not even exist any
more.  So we take the liberty to drop support for it.

Signed-off-by: Detlev Zundel <dzu@denx.de>
CC: Wolfgang Denk <wd@denx.de>
CC: Ben Warren <biggerbadderben@gmail.com>
2010-03-12 09:49:23 +01:00
Kumar Gala
ca02f6f8dc 85xx: Drop FIT support to allow u-boot image to fit in 512k
The 36-bit build exceeds the 512k size we have.  Removing FIT type image
support allows us to fit and we dont really use it.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-03-12 00:26:32 +01:00
Michael Zaidman
5f8419597f Cosmetic change - indentation correction.
Signed-off-by: Michael Zaidman <michael.zaidman@gmail.com>
2010-03-12 00:19:11 +01:00
Anatolij Gustschin
a693447cea cmd_mtdparts.c: prevent printbuffer overflows
The length of configured MTDPARTS_DEFAULT string
could be greater than console printbuffer size.
Replace printf() by puts() to avoid potential buffer
overflows.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2010-03-12 00:18:08 +01:00
Frans Meulenbroeks
3920bbedcf Fix MPC8536DS documentation
This patch corrects small mistake in the register list in
doc/README.mpc8536ds. These registers are 32 bits and this one starts
at ....c not ....e

When using the ...c address I can boot from sd, when using the ...e
address I cannot.

Signed-off-by: Frans Meulenbroeks <fransmeulenbroeks@gmail.com>
Acked-by: Hu Mingkai <B21284@freescale.com>
2010-03-12 00:15:55 +01:00
Heiko Schocher
ab68f4dd19 doc: add README for CONFIG_HWCONFIG option
Signed-off-by: Heiko Schocher <hs@denx.de>
2010-03-12 00:09:25 +01:00
Heiko Schocher
7026ead0d3 TQM8xx: enable device tree support on all TQM8xx based boards.
Also enable support for CONFIG_HWCONFIG because we use this for
configuring if this hardware has a FEC or not.

syntax:

hwconfig=fec:on   if hardware has an fec
hwconfig=fec:off  if hardware has no fec

Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Wolfgang Denk <wd@denx.de>
2010-03-12 00:06:07 +01:00
Heiko Schocher
6ed3b9d44c TQM8xx: add device tree support for TQM8xx based boards.
Also use hwconfig to configure whether the board has a FEC or not.
We then can adjust the DTS to tell Linux if there is a FEC present.

syntax:

hwconfig=fec:on   if hardware has a  FEC
hwconfig=fec:off  if hardware has no FEC

Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Wolfgang Denk <wd@denx.de>
2010-03-12 00:04:52 +01:00
Wolfgang Denk
143cd21fe2 Move CONFIG_UPDATE_TFTP code after CONFIG_PREBOOT
The auto-update feature (CONFIG_UPDATE_TFTP) requires that the env
variable serverip be set for the TFTP access. If DHCP is to be used
to get the serverip env variable, this doesn't work as DHCP happens
after the auto-update attempt has run. A solution is to run DHCP in
PREBOOT, but even this is too late.

To solve this, we move update_tftp() below the PREBOOT stuff.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2010-03-11 23:56:03 +01:00
Mike Frysinger
1b691bb0c2 mkimage: dont force entry point with xip
Some people boot images with the entry point in the middle of the blob
(like Linux with the head code in discardable .init.text), and there is no
no real requirement that the entry point be right after the mkimage header
when doing XIP, so let people specify whatever they want.  If they do need
an entry right after the header, then they still can do that with normal
-e behavior.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-03-11 23:50:06 +01:00
Richard Retanubun
4b99327a41 PPC: Record U-Boot's relocated address in RAM and show in bdinfo.
This patch uses gd->relocaddr variable to store uboot's relocated
address in RAM and shows it in bdinfo command.

This patch moves CONFIG_AMIGAONEG3SE style copying of the address
in board_init_f to just before relocation is actually done.

Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com>
Tested-by: Detlev Zundel <dzu@denx.de>
2010-03-11 23:49:16 +01:00
Wolfgang Denk
8c4444ff5e Fix memory leak in mmc_read()
There is be a path through mmc_read in drivers/mmc/mmc.c where
malloc'd memory is not freed before exiting mmc_read: it occurs if
mmc_set_blocklen() returns a non-zero value.

Reported-by: Quentin Armitage <Quentin@Armitage.org.uk>
Signed-off-by: Wolfgang Denk <wd@denx.de>
2010-03-11 23:35:43 +01:00
Daniel Gorsulowski
6258b04e9a AT91: Update otc570 board to new SoC access
* convert otc570 board to use c stucture SoC access
* change gpio access to at91_gpio syntax

Signed-off-by: Daniel Gorsulowski <Daniel.Gorsulowski@esd.eu>
2010-03-07 12:36:37 -06:00
Jens Scharsig
7cedb29872 updates the at91 main_clock calculation
* updates the conditional main_clock calculation (if AT91_MAIN_CLOCK defined) to c structure SoC access
 * add need register flags

Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de>
2010-03-07 12:36:36 -06:00
Prafulla Wadaskar
637833c2d6 arm: kirkwood: suen3: fixed build warning
This patch fixes following build warning

Invalid Kwbimage command Type - valid names are: BOOT_FROM, NAND_ECC_MODE, NAND_PAGE_SIZE, SATA_PIO_MODE, DDR_INIT_DELAY, DATA, , spi, nand, sata, pex, uart

Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
2010-03-07 12:36:36 -06:00
Stefano Babic
e4d3449201 MX51: removed warnings for the mx51evk
The patch removes warnings at compile time and provides
some cleanup code:
- Removed comment on NAND (not yet supported) from lowlevel_init.S
- Removed NFMS bit definition from imx-regs.h
  The bit is only related to MX.25/35 and can lead to confusion
- Moved is_soc_rev() to soc specific code (removed from mx51evk.c)

Signed-off-by: Stefano Babic <sbabic@denx.de>
2010-03-07 12:36:36 -06:00
Vipin Kumar
9d69e33d8d SPEAr : Supporting new mach ids for spear310 and spear320
Supporting new machine ids for SoCs spear310 and spear320

include/asm-arm/mach-types.h has to be updated before applying
this patch for build to work

Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
2010-03-07 12:36:36 -06:00
Heiko Schocher
cc0b53c8d5 arm, suen3: fix compile error, if doing not a local build
Signed-off-by: Heiko Schocher <hs@denx.de>
2010-03-07 12:36:36 -06:00
Heiko Schocher
67fa8c25f5 arm: add support for the suen3 board from keymile
Add support for the ARM part of the mgcoge2, named suen3.
This board is based on the Marvell Kirkwood (88F6281) SoC.
As there come more board variants, common config options
are collected in include/configs/km_arm.h. Also, this board
use common code for all keymile boards, which is stored in
board/keymile/common/common.c

Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Heiko Schocher <hs@denx.de>
2010-03-07 12:36:36 -06:00
John Rigby
6895d4510a Add support for KARO TX25 board
This is an i.MX25 base board with only NAND
so it uses nand_spl to boot.

Signed-off-by: John Rigby <jcrigby@gmail.com>

Tune configuration, add support for (redundant) environment in NAND.
Signed-off-by: Wolfgang Denk <wd@denx.de>

Acked-by: Wolfgang Denk <wd@denx.de>
CC: Fred Fan <fanyefeng@gmail.com>
CC: Tom <Tom.Rix@windriver.com>
2010-03-07 12:36:36 -06:00
John Rigby
740d6ae5b9 fec_mxc: add MX25 support
Use RMII for MX25
Add code to init gasket that enables RMII

Signed-off-by: John Rigby <jcrigby@gmail.com>
CC: Ben Warren <biggerbadderben@gmail.com>
2010-03-07 12:36:36 -06:00
John Rigby
cb17b92de0 fec_mxc: cleanup and factor out MX27 dependencies
general cleanup
move clock init to cpu_eth_init in cpu/arm926ejs/mx27/generic.c
make MX27 specific phy init conditional on CONFIG_MX27
replace call to imx_get_ahbclk with one to imx_get_fecclk
and define imx_get_fecclk in include/asm-arm/arch-mx27/clock.h

Signed-off-by: John Rigby <jcrigby@gmail.com>
CC: Ben Warren <biggerbadderben@gmail.com>
CC: Fred Fan <fanyefeng@gmail.com>
CC: Tom <Tom.Rix@windriver.com>
2010-03-07 12:36:36 -06:00
John Rigby
552ff8f1d9 Add support for Freescale MX25 SOC
ARM926EJS core with MX31 peripherals.

Signed-off-by: John Rigby <jcrigby@gmail.com>
Earlier Version Signed-off-by: Wolfgang Denk <wd@denx.de>
CC: Fred Fan <fanyefeng@gmail.com>
CC: Tom <Tom.Rix@windriver.com>
2010-03-07 12:36:36 -06:00
John Rigby
e911c983f4 mxc_serial replace platform specific clock
remove ifdef'd clock selection code from
serial_mxc.c and replace with call to imx_get_uartclk

Add definitions for imx_get_uartclk to imx31 and imx27
include files.

This makes it easier to add new imx platforms.

Signed-off-by: John Rigby <jcrigby@gmail.com>
2010-03-07 12:36:36 -06:00
Stefano Babic
c5fb70c911 Add initial support for Freescale mx51evk board
The patch adds initial support for the Freescale mx51evk board.
Network (FEC) and SD controller (fsl_esdhc) are supported.

Signed-off-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Fred Fan <fanyefeng@gmail.com>
2010-03-07 12:36:36 -06:00
Stefano Babic
c67bee1460 fsl_esdhc: add support for mx51 processor
The esdhc controller in the mx51 processor is quite
the same as the one in some powerpc processors
(MPC83xx, MPC85xx). This patches adapts the driver
to support the arm mx51.

Signed-off-by: Stefano Babic <sbabic@denx.de>
2010-03-07 12:36:36 -06:00
Stefano Babic
69df00f9d9 ARM: add accessors functions
Some Freescale's processors of different architecture
have the same peripheral (eSDHC controller in PowerPC
and i.MX51). This patch adds accessors for
the internal registers of the SOCs, as already
implemented in the PowerPC architecture.

Signed-off-by: Stefano Babic <sbabic@denx.de>
2010-03-07 12:36:36 -06:00
Stefano Babic
11fdade294 MMC: add weak function to detect MMC/SD card
Most controllers can check if there is a card in the slot.
However, they require pins that could be not available because
required by other functions and the detection of a card must
be performed in another way. This patch adds a weak function
that a board can implement to add its internal custom way
to check the presence of a MMC/SD card.

Signed-off-by: Stefano Babic <sbabic@denx.de>
2010-03-07 12:36:36 -06:00
Stefano Babic
250de12bc2 mmc: check correctness of the voltage mask in ocr
Most cards do not answer if some reserved bits
in the ocr are set. However, some controllers
can set bit 7 (reserved for low voltages), but
how to manage low voltages SD card is not yet
specified.

Signed-off-by: Stefano Babic <sbabic@denx.de>
2010-03-07 12:36:36 -06:00
Stefano Babic
71d64c0e4f serial_mxc: add support for MX51 processor
The patch adds support for the Freescale mx51 processor.

Signed-off-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Fred Fan <fanyefeng@gmail.com>
2010-03-07 12:36:35 -06:00
Stefano Babic
67adcee0e0 MX51: Add pin and multiplexer definitions.
The patch add header files to support the pin multiplexer
of the the Freescale i.MX51 processor.

Signed-off-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Fred Fan <fanyefeng@gmail.com>
2010-03-07 12:36:35 -06:00
Stefano Babic
fb87a1ed92 MX51: Add register definitions
The patch add header files to support the Freescale i.MX51
processor, setting definitions for internal registers.

Signed-off-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Fred Fan <fanyefeng@gmail.com>
2010-03-07 12:36:35 -06:00
Stefano Babic
64fdf452a8 MX51: Add initial support for the Freescale MX51
The patch add initial support for the Freescale i.MX51 processor
(family arm cortex_a8).

Signed-off-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Fred Fan <fanyefeng@gmail.com>
2010-03-07 12:36:35 -06:00
Matthias Kaehlcke
18ba012b9b edb93xx: Fix SDRAM initialization
edb93xx: Fix SDRAM initialization by issuing a precharge all command before
forcing the precharge and select mode register update mode before programming
the mode registers. Write to the SDRAM banks in order to force a precharge,
reading causes the edb93xx boards to hang

Signed-off-by: Matthias Kaehlcke <matthias@kaehlcke.net>
2010-03-07 12:36:35 -06:00
Anders Darander
cade7d9577 Add bootcount to AT91
Use AT91_GPBR 3 as a bootcount register.
The bootmagic and the bootcount shares AT91_GPBR 3.

Signed-off-by: Anders Darander <ad@datarespons.se>
2010-03-07 12:36:35 -06:00
Tom Rix
5f35348409 ARM Update mach-types
Fetched from http://www.arm.linux.org.uk/developer/machines/download.php
And built with

repo http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm
commit aea187c46f7d03ce985e55eb1398d0776a15b928

Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
2010-03-07 12:36:35 -06:00
Matthias Kaehlcke
c7ad13a242 ep93xx: Refactoring of timer code
ep93xx: Refactoring of the timer code, including the following changes

 * use a free running timer instead of a periodical one
 * use unsigned long long for total number of ticks
 * hold the timer state in a structure instead of separate variables
 * increment the timer counter instead of decrementing it
 * remove unused function udelay_masked()
 * remove unused function set_timer()

Signed-off-by: Matthias Kaehlcke <matthias@kaehlcke.net>
2010-03-07 12:36:35 -06:00
Matthias Kaehlcke
d9f505e3cd ep93xx: Fix calculation of sys ticks in clk_to_systicks()
ep93xx: Use unsigned long long for calculation of sys ticks in clk_to_systicks()
for proper handling of large intermediate values

Signed-off-by: Matthias Kaehlcke <matthias@kaehlcke.net>
2010-03-07 12:36:35 -06:00
Siarhei Siamashka
041d42e789 OMAP3: workaround for ARM Cortex-A8 erratum 725233
725233: PLD instructions executed with PLD data forwarding
enabled can result in a processor deadlock

This deadlock can happen when NEON load instructions are used together
with cache preload instructions (PLD). The problematic conditions
can be triggered in-the-wild by NEON optimized functions from pixman
library (http://cgit.freedesktop.org/pixman), which perform dynamic
adjustment of prefetch distance.

The workaround disables PLD data forwarding by setting PLD_FWD bit
in L2 Cache Auxiliary Control Register as recommended in ARM Cortex-A8
errata list.

The deadlock can only happen on r1pX revisions of Cortex-A8 (used in
OMAP34xx/OMAP35xx). Performance impact of the workaround is practically
non-existant.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2010-03-07 12:36:35 -06:00
Achim Ehrlich
7c966a8bdf ARM change name of defines for AT91 arm926ejs
Configuration defines should be preceeded with CONFIG_SYS_. Renamed
some at91 specific defines to conform to this naming convention:

AT91_CPU_NAME to CONFIG_SYS_AT91_CPU_NAME
AT91_MAIN_CLOCK to CONFIG_SYS_AT91_MAIN_CLOCK

Signed-off-by: Achim Ehrlich <aehrlich@taskit.de>
2010-03-07 12:36:35 -06:00
Ladislav Michl
5c97a1de19 VoiceBlue: fix linker errors
linking eeprom with libgeneric.a is not really needed and causes following
error:
../../lib_generic/libgeneric.a(string.o): In function `strcmp':
/home/ladis/src/u-boot-ti/lib_generic/string.c:152: multiple definition of `strcmp'
../../examples/standalone/libstubs.a(stubs.o):include/_exports.h:24: first defined here
make[1]: *** [eeprom.srec] Error 1

Fix undefined reference to memset generated by some versions of gcc
to zero out initialized structure on the stack:
eeprom.o: In function `eeprom':
board/voiceblue/eeprom.c:152: undefined reference to `memset'
make[1]: *** [eeprom] Error 1

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2010-03-07 12:36:35 -06:00
Ladislav Michl
a32c1e0ecd VoiceBlue: limit line lenght to 80 characters
Reindent configuration header to limit line lenght to 80 characters by
removing obvious and sometimes misleading comments.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2010-03-07 12:36:35 -06:00
Ladislav Michl
779b534385 netstar.h: do not exceed 80 columns
Limit line length to 80 characters mostly by removing obvious and sometimes
misleading comments. Fix indentation, too.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2010-03-07 12:36:35 -06:00
Sandeep Paulraj
3fca29294a DaVinci: Adding entry to MAKEALL for DM365 EVM
The patch adds an entry for the DM365 EVM to MAKEALL

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2010-03-07 12:36:35 -06:00
Nick Thompson
37cffdad06 da830evm: Add support for TI EMAC
Adds support for ethernet networking on the da830evm platform.

This platform uses an SoC EMAC interface and a 3 port ethernet
switch as a PHY with an RMII interface. The PHY also has a i2c
interface for configuring the switch functions.

Signed-off-by: Nick Thompson <nick.thompson@ge.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2010-03-07 12:36:35 -06:00
Ladislav Michl
d8775d03f3 NetStar: make mtdparts default ready for recent kernels
Recent kernels are using generic NAND and NOR drivers. Change
default mtdparts to reflect it.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2010-03-07 12:36:34 -06:00
Ladislav Michl
de9a1e0d08 NetStar: fix default environment
Correct switching partitions after upgrade and make it more readable.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2010-03-07 12:36:34 -06:00
Ladislav Michl
3a67566c1d NetStar: eeprom - fix linker error
linking eeprom with libgeneric.a is not really needed and causes following
error:
../../lib_generic/libgeneric.a(string.o): In function `strcmp':
lib_generic/string.c:152: multiple definition of `strcmp'
../../examples/standalone/libstubs.a(stubs.o):include/_exports.h:24: first defined here
Remove eeprom linker script as well and generate entry point object
(to start application by jumping on its beginning) on the fly.
Out-of-tree build tested as well.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2010-03-07 12:36:34 -06:00
Ladislav Michl
308d463eaf NetStar: eeprom - be less verbose
Use shorter yet descriptive messages, replace printf() with
puts() where appropriate. This saves few bytes.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2010-03-07 12:36:34 -06:00
Ladislav Michl
b29ff62772 NetStar: eeprom - undefined reference to `memset'
Defining partially initialized struct eth_device on stack means
gcc has to zero out it, and some gcc versions optimize this with
an implicit call to memset. Move definition to data section
to avoid that (it has also nice side effect that we need not
to pass it to helper functions anymore)

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2010-03-07 12:36:34 -06:00
Wolfgang Denk
ef8d008730 Merge branch 'master' of git://git.denx.de/u-boot-cfi-flash 2010-03-04 21:30:01 +01:00
Wolfgang Denk
b003bf79e3 Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx 2010-03-04 21:28:46 +01:00
Wolfgang Denk
96dd0a4cbf Merge branch 'next' of git://git.denx.de/u-boot-coldfire 2010-03-04 21:24:44 +01:00
Wolfgang Denk
a43af0f223 Merge branch 'master' of git://git.denx.de/u-boot-sh 2010-03-04 21:11:55 +01:00
Wolfgang Denk
fafe2a9e23 Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx 2010-03-04 21:09:02 +01:00
Wolfgang Wegner
8f9a221045 ] fix monitor protection for CONFIG_MONITOR_IS_IN_RAM
For platforms with flash below ram addresses, the current check to
activate monitor protection is wrong/insufficient. This patch fixes
CONFIG_MONITOR_IS_IN_RAM for these systems by adding a check for
this configuration.

Signed-off-by: Wolfgang Wegner <w.wegner@astro-kom.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2010-03-04 10:07:12 +01:00
Wolfgang Wegner
c7de810c79 allow MCF532x to use CONFIG_MONITOR_IS_IN_RAM
CONFIG_MONITOR_IS_IN_RAM is broken for MCF532x. This patch fixes this
 by conditionally
- removing the vector table at the beginning of code
- not overwriting the vector base register
- removing the code to re-set the PLL, which effectively disables
  SDRAM access

Signed-off-by: Wolfgang Wegner <w.wegner@astro-kom.de>
2010-03-04 01:46:53 -06:00
Richard Retanubun
bb907ab51f MCF5271-only: Added a weak board_reset function to allow custom reset
This patch adds a board_reset function to allow boards to specify
their own custom reset sequence (e.g. resetting by timing out watchdog).
Tested only on MCF5271, can be expanded if needed.

Based on Mike Frysinger's suggestion on:
http://article.gmane.org/gmane.comp.boot-loaders.u-boot/70304

Signed-off-by: Richard Retanubun <RichardRetanubun at RuggedCom.com>
2010-03-04 01:46:49 -06:00
Wolfgang Wegner
992d712950 MCF532x: make icache_enable use CONFIG_SYS_SDRAM_SIZE
in cpu/mcf532x/start.S, the function icache_enable enables the cache for
a fixed 32MB region starting at the SDRAM start address; this patch
changes the function to cover the region defined by CONFIG_SYS_SDRAM_SIZE

Signed-off-by: Wolfgang Wegner <w.wegner at astro-kom.de>
2010-03-04 01:46:21 -06:00
Wolfgang Wegner
870bf3ee60 add include/asm-m68k/unaligned.h
lib_generic/zlib.c needs include/asm/unaligned.h since commit
cd514aeb99, which broke compilation for
Coldfire/M68K. This patch adds the missing header for these
architectures.

Signed-off-by: Wolfgang Wegner <w.wegner at astro-kom.de>
2010-03-04 01:45:38 -06:00
Nobuhiro Iwamatsu
da5e083590 sh: Add asm/unaligned.h and asm/unaligned-sh4a.h from Linux kernel
zlib.c demands asm/unaligned.h. But, SH does not have these.
This commit add asm/unaligned.h and asm/unaligned-sh4a.h from Linux
kernel and modifyf for u-boot.

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2010-03-03 12:21:14 +09:00
Kim Phillips
fe389da6ae mpc83xx: fix out-of-tree mpc8315 nand build
commit 2e95004deb "mpc83xx: Add NAND boot support
for MPC8315E-RDB boards" symlinked nand_spl/board/freescale/mpc8315erdb to
mpc8313erdb in order to not duplicate code.

Since the main makefile builds nand_spl/board/$(BOARDDIR) (which makes sense),
and the board Makefile and linker script are the only two necessary files
to enable out-of-tree building, and other boards have duplicated nand makefiles
(e.g. 8536ds & 8569mds), it only seems prudent to copy these two files in the
name of the 8315 too.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Cc: Anton Vorontsov <avorontsov@ru.mvista.com>
Cc: Wolfgang Denk <wd@denx.de>
2010-03-02 11:24:40 -06:00
Kim Phillips
4e7e12dfa1 mpc83xx: vme8349: fix incorrect BR0_PRELIM port size comment
commit 98d92d8c9f "sbc8349: fix incorrect
comment" missed this one.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2010-03-02 11:24:35 -06:00
Eugene O'Brien
87800f7241 ppc4xx: Corrected EBC register bit definitions
Corrected the bit field positions of the external master priority low
and the external master priority high values in the EBC configuration
register. These bit field positions differ between PPC405 and PPC440
processors

Signed-off-by: Eugene O'Brien <eugene.obrien@advantechamt.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2010-03-02 14:12:52 +01:00
Frans Meulenbroeks
f3651764e5 cmd_itest.c: fix pointer dereferencing
fix pointer dereferencing
if the size is .b and .w an 8 or 16 bit access is done.

Signed-off-by: Frans Meulenbroeks <fransmeulenbroeks@gmail.com>
Acked-by: Detlev Zundel <dzu@denx.de>
2010-02-24 00:09:45 +01:00
Kim Phillips
0ad22703f0 tools: fix imximage warning
Fix build warning:

Configuring for MPC837XEMDS board...
imximage.c: In function `imximage_parse_cfg_file':
imximage.c:146: warning: passing argument 2 of `getline' from incompatible pointer type
/usr/include/bits/stdio.h:116: note: expected `size_t *' but argument is of type `uint32_t *'

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2010-02-24 00:06:18 +01:00
Stefano Babic
5b28e913f4 mkimage: SEGFAULT with imximage on 64 bit systems
Running mkimage to generate an imximage produces a SEGFAULT
on 64 bit machines due to pointer arithmetic limited to 32 bit.

Signed-off-by: Stefano Babic <sbabic@denx.de>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
2010-02-24 00:04:03 +01:00
Kim Phillips
ecd1a09b81 mpc83xx: remove hardcoded network addresses from config files
and avoid e.g., two identical boards from causing random networking
conflicts when hooked up to the same network.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2010-02-22 16:48:06 -06:00
Michael Zaidman
4c006dd150 Bug: do_reset issued via netconsole does not reset mpc83xx cpu.
The do_reset routine in the cpu/mpc83xx/cpu.c file does not reset
the mpc83xx cpu when issued via netconsole.

Moving the console output "resetting the board." to the beginning of
the routine before disabling interrupts solved the problem.

Signed-off-by: Michael Zaidman <michael.zaidman@gmail.com>
Acked-by: Detlev Zundel <dzu@denx.de>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2010-02-18 18:25:09 -06:00
Jens Scharsig
77e7273c40 new board (eb_cpux9k2)
* new board (eb_cpux9k2)
 * support for EB+CPUx9K2 board by BuS Elektronik GmbH & Co. KG
 * select via make eb_cpux9k2_config
 * this also demonstrates, how to use boards with AT91RM9200 cpu
   in at91 arch tree

Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de>
2010-02-12 12:36:04 -06:00
Jens Scharsig
6799a80f76 new at91_emac network driver (NET_MULTI api)
* add's at91_emac (AT91RM9200) network driver (NET_MULTI api)
 * enable driver with CONFIG_DRIVER_AT91EMAC
 * generic PHY initialization
 * modify AT91RM9200 boards to use NET_MULTI driver
 * the drivers has been tested with LXT971 Phy and DM9161 Phy at MII and RMII
   interface

Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de>
2010-02-12 12:36:04 -06:00
Jens Scharsig
98250e8e17 prepare joining at91rm9200 into at91
* prepare joining at91 and at91rm9200
 * add modified copy of soc files to cpu/arm920t/at91 to make
   possible to compile at91rm9200 boards in at91 tree instead
   of at91rm9200
 * add header files with c structure defs for AT91 MC, ST and TC
 * the new cpu files are using at91 c structure soc access
 * please read README.soc-at91 for details

Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de>
2010-02-12 12:31:55 -06:00
Jens Scharsig
1b34f00c28 update at91sam9263ek board to new SoC access
* convert at91sam9263ek board to use c stucture SoC access
 * change gpio access to at91_gpio syntax

Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de>
2010-02-12 12:31:55 -06:00
Jens Scharsig
0cf0b93161 convert common files to new SoC access
* add's a warning to all files, which need update to new SoC access
 * convert common files in cpu/../at91 and a lot of drivers to use
   c stucture SoC access

Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de>
2010-02-12 12:31:55 -06:00
Jens Scharsig
7f9e8633ac convert all at91 files to use at91_gpio driver syntax
* convert all files cpu/../at91 to use at91_gpio driver syntax
 * change AT91_PINP([A-F])(\d+) to AT91_PIO_PORT\1, \2
   this makes all 160 AT91_PINPxxx defines obsolete
 * AT91_PINPxxx defines and gpio.h can be remove, if all boards converted to new SoC access

Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de>
2010-02-12 12:31:54 -06:00
Jens Scharsig
ea8fbba731 add a new AT91 GPIO driver
* add a real AT91 GPIO driver instead of header inline code
* resolve the mixing of port and pins
* change board config files to use new driver
* add macros to gpio to realize backward compatibility

Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de>
2010-02-12 12:31:54 -06:00
Jens Scharsig
5d8e359c38 add c structures for SoC access
* add's c structures for SoC access to pheriperials head files

Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de>
2010-02-12 12:31:54 -06:00
Jens Scharsig
425de62d40 add new CONFIG_AT91_LEGACY
* add's the new temporary CONFIG_AT91_LEGACY to all board configs
 This will need for backward compatiblity, while change the SoC access
 to c structures. If CONFIG_AT91_LEGACY is defined, the deprecated
 SoC is used.

Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de>
2010-02-12 12:31:54 -06:00
Nick Thompson
3a4e43921d DA830 EVM: Enable NAND support on Spectrum Digital EVM
The EVM UI extender card has a NAND device. This change will enable
saveenv to work with NAND and Linux to be booted using:

	mtdparts default
	nboot kernel
	bootm

Signed-off-by: Nick Thompson <nick.thompson@ge.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2010-02-12 12:31:54 -06:00
Nick Thompson
6228e6389e Davinci: Add EMIF-A macros for setting chip select parameters
The patch adds EMIF-A macros for setting chip select parameters

Signed-off-by: Nick Thompson <nick.thompson@ge.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2010-02-12 12:31:54 -06:00
Sanjeev Premi
b74064a0e2 OMAP3: Avoid re-write to PRM_CLKSRC_CTRL
In function get_osc_clk_speed(), do not change/ update
the divider for SYS_CLK as it can has cascading effect
on the other derived clocks.

Sudden change in divider value can lead to inconsistent
behavior in the system - often leading to crashes.

The problem was found when working with OMAP3EVM using
DM3730 processor card.

The patch has been tested with OMAP3530 on OMAP3EVM as
well

Signed-off-by: Sanjeev Premi <premi@ti.com>
Signed-off-by: Hiremath Vaibhav <hvaibhav@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2010-02-12 12:31:54 -06:00
Magnus Lilja
eff536befd SPI: Fix 32 bit transfers in mxc_spi.c
Commit f9b6a1575d,  "i.MX31: fix SPI
driver for shorter than 32 bit" broke 32 bit transfers. This patch
makes single 32 bit transfer work again.

Transfer lengths that are known not to work will abort and print
an error message.

Tested on i.MX31 Litekit and i.MX31 PDK using 32 bit transfers to
the MC13783/ATLAS chip (using the 'date' command).

Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
2010-02-12 12:31:54 -06:00
Alessandro Rubini
39a9142203 edb93xx: enable the uart in devicecfg register
printf goes to uart1, but it will block forever waiting for
busy to go off unless the uart is enabled first.

Signed-off-by: Alessandro Rubini <rubini@gnudd.com>
2010-02-12 12:31:54 -06:00
Alessandro Rubini
822bd70db4 edb93xx: change calculation un early_udelay.h
Previous code compiled with gcc-4.2.2 makes a call to
__aeabi_uidiv to divide by 20. As a side effect it was
not inline any more, and so sdram_cfg used the stack
as well, but this is early code that has no stack yet.
The patch explicitly removes the division, so no stack is used.

The calculation of the counter calls a division by 20

Signed-off-by: Alessandro Rubini <rubini@gnudd.com>
2010-02-12 12:31:54 -06:00
Alessandro Rubini
c50a0f5039 EP93xx: fix syscon_regs definition
The structure was missing a reserved entry (not listed in the manual,
actually), so the last registers had a wrong offset. This prevented
all swlocked registers to be modified as swlock is last in the structure.

Signed-off-by: Alessandro Rubini <rubini@gnudd.com>
2010-02-12 12:31:54 -06:00
Matthias Kaehlcke
fcfb632bd1 ARM: Add support for EP93xx SoCs
Add support for the Cirrus EP93xx platform

Signed-off-by: Matthias Kaehlcke <matthias@kaehlcke.net>
Acked-by: Tom <Tom.Rix@windriver.com>
2010-02-12 12:31:54 -06:00
Matthias Kaehlcke
cf3c142ee4 Add support for EDB93xx boards
Added support for the following EDB93xx boards:

EDB9301
EDB9302
EDB9302A
EDB9307
EDB9307A
EDB93012
EDB9315
EDB9315A

Signed-off-by: Matthias Kaehlcke <matthias@kaehlcke.net>
2010-02-12 12:31:54 -06:00
Ladislav Michl
d798e27b14 NetStar: Remove debug junk leaked into eeprom utility
This patch removes debug junk leaked into eeprom utility.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2010-02-12 12:31:54 -06:00
Ladislav Michl
89e94d81ed NetStar: make crcit utility more readable
This patch makes the crcit utility more readable

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2010-02-12 12:31:54 -06:00
Ladislav Michl
3843e7dc93 NetStar: Disable CONFIG_CMD_JFFS2
This patch removes "CONFIG_CMD_JFFS" from the board config

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2010-02-12 12:31:54 -06:00
Tom Rix
632e1d9014 OMAP3 Move declaration of gpmc_cfg.
Every omap3 board config file declared the global variable gpmc_cfg.
This changes moves the declaration to a better location in the
arch dependent header file cpu.h.

Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2010-02-12 12:31:53 -06:00
Scott Ellis
093d6018cf Overo GPMC registers
Use appropriate GPMC timings for the LAN9221 controller on the
Gumstix Overo expansion boards not the values in arch-omap3/mem.h
which are for a different ethernet controller.

Signed-off-by: Scott Ellis <scott@jumpnowtek.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2010-02-12 12:31:53 -06:00
Nick Thompson
63a47dfd07 da830evm: Use table driven pin mux configuration
Tidyup the pin muxer configuration using the Davinci table driven
pinmux configuration function and data tables.

Signed-off-by: Nick Thompson <nick.thompson@ge.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2010-02-12 12:31:53 -06:00
Sekhar Nori
8ed5885693 TI DaVinci: Driver for the davinci SPI controller
This adds a driver for the SPI controller found on davinci
based SoCs from Texas Instruments.

Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2010-02-12 12:31:53 -06:00
Daniel Gorsulowski
44d8025622 at91: Add esd gmbh OTC570 board support
This patch adds support for esd gmbh OTC570 board.
The OTC570 is based on an Atmel AT91SAM9263 SoC.

Signed-off-by: Daniel Gorsulowski <Daniel.Gorsulowski@esd.eu>
2010-02-12 12:31:53 -06:00
Wolfgang Denk
0b692dcb19 Merge branch 'master' of git://git.denx.de/u-boot-net 2010-02-08 22:09:24 +01:00
Mike Frysinger
e39bf1e2a9 kgdb: cpu/mpc* cpu/74xx: include kgdb.h when needed
Commit cbb0cab1d9 broke some platforms which used kgdb code but
didn't actually include kgdb.h.  So include kgdb.h in all the relevant
traps code.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-02-08 22:05:42 +01:00
Stefan Roese
ab5a0dcb9c net: Use 0.5 sec timeout in miiphy_reset() instead of counting loop
This patch fixes a problem I've notived on a buggy PPC4xx system. This
system has problems with the PHY MDIO communication and seemed to be
stuck/crashed in miiphy_reset(). But degugging revealed, that the CPU
didn't crash, but "only" hung in this counting loop for about 2 minutes.

This patch now uses a real timeout of 0.5 seconds (as mentioned in the
comment in miiphy_reset).

Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2010-02-06 22:52:21 -08:00
Stefano Babic
4294b2485b fec_mxc: add support for MX51 processor
The patch add support for the Freescale mx51 processor
to the FEC ethernet driver.

Signed-off-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2010-02-06 22:52:18 -08:00
Siddarth Gore
e66b19ce6d NET: kirkwood-egiga smi access fix
Although the datasheet mentions seperate smi registers for each
port, using Port 1 smi register to access ethernet phys does not
work. Hence only Port 0 smi register should be used to access all
devices connected to the smi bus. This behavior is consistant with
the mv643xx driver in the linux kernel.

Signed-off-by: Siddarth Gore <gores@marvell.com>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2010-02-06 22:52:14 -08:00
Ladislav Michl
a1b322a983 ns16550: kick watchdog while waiting for a character
ns16550 busyloops waiting for incoming byte causing watchdog to reboot
while waiting for a key press. A call to WATCHDOG_RESET in NS16550_getc
loop fixes it.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
2010-02-03 22:46:58 +01:00
Remy Bohmer
84d36b3018 USB: usb_control_msg wait for driver ISR to set status.
This patch changes usb_control_msg back to the state prior to commit
4886720844.

The USB driver ISR routine may update the status.

Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
2010-02-03 22:06:59 +01:00
Prathap Srinivas
6e20e64f5c musb: Add host support for DM365 EVM
Add support for musb host on DM365 EVM.

Signed-off-by: Prathap Srinivas <msprathap@ti.com>
2010-02-03 22:06:59 +01:00
Cliff Cai
ec2aadb408 usb: musb: fix Blackfin DMA register padding
The conversion from offsets to C structs lost a little padding in the DMA
register map.  Accessing endpoints other than ep0 with DMA would fail as
the addresses wouldn't be adjusted correctly.

Signed-off-by: Cliff Cai <cliff.cai@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-02-03 22:06:59 +01:00
Wolfgang Denk
111d6c6ad1 Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx 2010-02-03 20:22:10 +01:00
Wolfgang Denk
08254a1a97 Merge branch 'master' of git://git.denx.de/u-boot-cfi-flash 2010-02-03 20:15:46 +01:00
Wolfgang Denk
05c2f4fe29 Merge branch 'master' of git://git.denx.de/u-boot-net 2010-02-03 20:10:20 +01:00
Wolfgang Denk
5c1a1a3069 Merge branch 'master' of git://git.denx.de/u-boot-nand-flash 2010-02-03 20:05:27 +01:00
Wolfgang Denk
0ae016f1ff Merge branch 'master' of git://git.denx.de/u-boot-video 2010-02-03 20:03:46 +01:00
Wolfgang Denk
d0750bc9e5 EXBITGEN: drop support for unmaintained board
The EXBITGEN board has not been maintained for a long time; it has
build problems, but no hardware is available any more for testing.

Drop support for this board.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Acked-by: Stefan Roese <sr@denx.de>
2010-02-03 20:01:16 +01:00
Wolfgang Denk
9461a939ca mpc5xxx/cpu_init.c: fix warning: unused variable 'cdm'
Signed-off-by: Wolfgang Denk <wd@denx.de>
Acked-by: Detlev Zundel <dzu@denx.de>
2010-02-03 20:01:05 +01:00
Wolfgang Denk
13d8bfe26c mpc5xxx/cpu_init.c: fix warning: unused variable 'gpt0'
Signed-off-by: Wolfgang Denk <wd@denx.de>
Acked-by: Detlev Zundel <dzu@denx.de>
2010-02-03 20:00:14 +01:00
Matthias Fuchs
4710cee1b5 ppc4xx: Remove unused feature from AR405 board
This patch fixes building for AR405 boards by remove an unused feature.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Signed-off-by: Stefan Roese <sr@denx.de>
2010-02-03 09:17:56 +01:00
Matthias Fuchs
976c21ad8e ppc4xx: Fix building for PLU405 boards
The init_coupler() function from board/esd/plu405/plu405.c
got lost somehow! This patch readds it.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Signed-off-by: Stefan Roese <sr@denx.de>
2010-02-03 09:17:44 +01:00
Matthias Fuchs
59c1db6dab ppc4xx: Fix building of PMC440 board
Remove some unused features and default environment variable
to shrink the PMC440 u-boot.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Signed-off-by: Stefan Roese <sr@denx.de>
2010-02-03 09:17:40 +01:00
Stefan Roese
6f6c26e430 ppc4xx: Fix compilation error on ML2 board
Recently this compilation error occurs:

Configuring for ML2 board...
traps.c: In function 'MachineCheckException':
traps.c:159: error: 'debugger_exception_handler' undeclared (first use
	in this function)
traps.c:159: error: (Each undeclared identifier is reported only once
traps.c:159: error: for each function it appears in.)

This patch now fixes it by including kgdb.h

Signed-off-by: Stefan Roese <sr@denx.de>
2010-02-03 09:17:00 +01:00
Ladislav Michl
f3dec798d9 CFI: fix eraseregions numblocks
eraseregions numblocks was sometimes one less than actual, possibly producing
erase regions with zero blocks. As MTD code touches eraseregions only if
numeraseregions is greater that zero, allocate eraseregions only for non
uniform erase size flash.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Signed-off-by: Stefan Roese <sr@denx.de>
2010-02-02 08:22:00 +01:00
Jens Scharsig
c041e9d212 new at91_emac network driver (NET_MULTI api)
* add's at91_emac (AT91RM9200) network driver (NET_MULTI api)
* enable driver with CONFIG_DRIVER_AT91EMAC
* generic PHY initialization
* modify AT91RM9200 boards to use NET_MULTI driver
* the drivers has been tested with LXT971 Phy and DM9161 Phy at
  MII and RMII interface

Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2010-01-31 22:37:12 -08:00
Matthias Kaehlcke
594d57d0cc Add EP93xx ethernet driver
Added ethernet driver for EP93xx SoCs

Signed-off-by: Matthias Kaehlcke <matthias@kaehlcke.net>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2010-01-31 22:37:12 -08:00
Heiko Schocher
582c55a027 83xx, uec: split enet_interface in two variables
There's no sensible reason to unite speed and interface type into
one variable.  So split this variable enet_interface into two
vars: enet_interface_type, which hold the interface type and speed.

Also: add the possibility for switching between 10 and 100 MBit
interfaces on the fly, when running in FAST_ETH mode.

Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2010-01-31 22:37:12 -08:00
Nick Thompson
d7e354374c TI: DaVinci: Updating EMAC driver for DM365, DM646x and DA8XX
The EMAC IP on DM365, DM646x and DA830 is slightly different
from that on DM644x. This change updates the DaVinci EMAC driver
so that EMAC becomes operational on SOCs with EMAC v2.

Signed-off-by: Nick Thompson <nick.thompson@ge.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2010-01-31 22:37:12 -08:00
Semih Hazar
0f751d6ef3 macb: Fix mii_phy_read and mii_phy_write functions
Enabling CONFIG_CMD_MII in AVR32 boards was not possible due to
compile errors.

This patch fixes miiphy_read and miiphy_write functions and
registers them properly.

Signed-off-by: Semih Hazar <semih.hazar@indefia.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2010-01-31 22:37:12 -08:00
Peter Tyser
5f6b144221 tsec: Add TSEC_FIBER flag
The TSEC_FIBER flag should be set when a PHY is operating with an
external fiber interface.  Currently it is only used to notify a user
that the PHY is operating in fiber mode.

A short description was also added to the other TSEC flag defines so
that it is clear how they differ from one another.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2010-01-31 22:34:34 -08:00
Peter Tyser
8abb8dcc8d tsec: Add support for using the BCM5482 PHY in fiber mode
The BCM5482 PHY supports both copper and fiber as an ethernet medium.
By enabling its copper/fiber mode auto-detection feature it can
dynamically determine if it should be configured for copper or fiber.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2010-01-31 22:34:34 -08:00
Peter Tyser
c6dbdfda53 tsec: General cleanup
- Cleanup formatting of phy_info structures

- Fix lines > 80 chars

- Fix some random indentation inconsistencies

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2010-01-31 22:34:34 -08:00
Peter Tyser
e1957ef02c tsec: Make functions/data static when possible
This is generally good practice and saves ~150 bytes.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2010-01-31 22:34:34 -08:00
Peter Tyser
27165b5c32 tsec: Clean up Broadcom PHY status parsing
- Remove unnecessary printing "Enet starting in <speed>/<duplex>"
    This same information is already printed during normal ethernet
    operation in the form "Speed: 1000, full duplex".

- Add a check for link before determining link speed and duplex
    If there is no link, speed/duplex don't matter.  This also removes
    the annoying and unneeded "Auto-neg error, defaulting to 10BT/HD"
    message that occurs when no link is detected.

- Whitespace and line > 80 characters cleanup

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2010-01-31 22:34:34 -08:00
Peter Tyser
46e91674fb tsec: Force TBI PHY to 1000Mbps full duplex in SGMII mode
In SGMII mode the link between a processor's internal TBI PHY and an
external PHY should always be 1000Mbps, full duplex.  Also, the SGMII
interface between an internal TBI PHY and external PHY does not
support in-band auto-negotation.

Previously, when configured for SGMII mode a TBI PHY would attempt to
restart auto-negotation during initializtion.  This auto-negotation
between a TBI PHY and external PHY would fail and result in unusable
ethernet operation.

Forcing the TBI PHY and and external PHY to link at 1000Mbps full duplex
in SGMII mode resolves this issue of auto-negotation failing.

Note that 10Mbps and 100Mbps operation is still possible on the external
side of the external PHY even when SGMII is operating at 1000Mbps.
The SGMII interface still operates at 1000Mbps, but each byte of data
is repeated 100 or 10 times for 10/100Mbps and the external PHY handles
converting this data stream into proper 10/100Mbps signalling.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2010-01-31 22:34:34 -08:00
Seunghyeon Rhee
76771e595a NET: Fix MAC addr handling for smc911x
This patch turns off MAC address mismatch warning when
optional eeprom programmed with MAC address is not available.
In that case, smc911x's MAC address register has its default
value ff:ff:ff:ff:ff:ff and it's not a valid address. This
makes eth_initialize() show the warning which has no
meaningful information while environment variable ethaddr
overrides the address read from the register. If there's no
eeprom and the value of MAC address register is not valid
after initialization, dev->enetaddr had better not be updated
and maintain its initial value 00:00:00:00:00:00, which I
think is what eth_initialize() expects. This is not a bug fix.
Even without this patch, the driver works fine. It's just for
enhancing the way of displaying messages.

Signed-off-by: Seunghyeon Rhee <seunghyeon@lpmtec.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2010-01-31 22:34:33 -08:00
Matthias Kaehlcke
07c966066b cs8900_initialize() cleanup
cs8900_initialize(): remove unecessary calls to free() and fix memory leak

Signed-off-by: Matthias Kaehlcke <matthias@kaehlcke.net>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2010-01-31 22:34:33 -08:00
Mike Frysinger
c4168af3ba smc91111_eeprom: fix linking error
Building for a bf533-stamp ends up with this error:
smc91111_eeprom.o: In function `smc91111_eeprom':
examples/standalone/smc91111_eeprom.c:58: undefined reference to `memset'
make[2]: *** [smc91111_eeprom] Error 1

The new eth_struct definition means gcc has to zero out the structure on
the stack, and some gcc versions optimize this with an implicit call to
memset.  So tweak the structure style to avoid that gcc feature.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2010-01-31 22:34:33 -08:00
Wolfgang Denk
5f566f4547 cmd_ximg.c: fix error: 'i' undeclared
Fix compile error:

	cmd_ximg.c: In function 'do_imgextract':
	cmd_ximg.c:234: error: 'i' undeclared (first use in this function)
	cmd_ximg.c:234: error: (Each undeclared identifier is reported only once
	cmd_ximg.c:234: error: for each function it appears in.)

Signed-off-by: Wolfgang Denk <wd@denx.de>
2010-01-31 21:51:43 +01:00
Anatolij Gustschin
a6e42ed097 lcd: remove CONFIG_ATMEL_LCD ifdefs from lcd_setfgcolor
Not all boards defining LCD_COLOR16 are able to set
lcd_color_fg/lcd_color_bg correctly. The issue seems to
be caused by CONFIG_ATMEL_LCD ifdefs in lcd_setfgcolor()
and lcd_setbgcolor(). Actually, the color values passed
to these functions are already correct, we don't need
to fix them. So remove ifdefs here.

Reported-by: Alessandro Rubini <rubini@unipv.it>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
2010-01-27 21:23:30 +01:00
Alessandro Rubini
d841978ea6 include/nomadik.h: add physical address for cldc
Signed-off-by: Alessandro Rubini <rubini@unipv.it>
Acked-by: Andrea Gallo <andrea.gallo@stericsson.com>
2010-01-27 21:23:23 +01:00
Alessandro Rubini
3e446cbdf3 video: add amba-clcd prime-cell
This adds support for the CLCD logic cell. It accepts precompiled
register values for specific configuration through a board-supplied
data structure.  It is used by the Nomadik nhk8815, added by a later
patch in this series.

Signed-off-by: Alessandro Rubini <rubini@unipv.it>
Acked-by: Andrea Gallo <andrea.gallo@stericsson.com>
2010-01-27 21:23:14 +01:00
John Rigby
b081c2e9b9 Nand mxc_nand add v1.1 controller support
Add support for version 1.1 of the nfc nand flash
controller which is on the i.mx25 soc.

Signed-off-by: John Rigby <jcrigby@gmail.com>
CC: Scott Wood <scottwood@freescale.com>
2010-01-27 14:22:41 -06:00
John Rigby
f3bb63a304 Add MX25 support to nand_spl fsl nfc driver
MX25 has a different version of the fsl_nfc
flash controller known as version 1.1.

Add support to the nand_spl fsl_nfc driver

Versioning differs from mainline mxc kernel driver
no consensus yet on if the naming here and in
Redboot or the kernel is "correct".

Signed-off-by: John Rigby <jcrigby@gmail.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>
CC: Scott Wood <scottwood@freescale.com>
2010-01-27 14:22:41 -06:00
John Rigby
ef22b50370 arm926ejs: add nand_spl boot support
Add CONFIG_PRELOADER/CONFIG_NAND_SPL support for nand booting
to arm926ejs/start.S

This is derived from CONFIG_PRELOADER support in arm1136/start.S

Signed-off-by: John Rigby <jcrigby@gmail.com>
CC: Scott Wood <scottwood@freescale.com>
2010-01-27 14:22:41 -06:00
Wolfgang Denk
15b86c3d6c env_nand.c: print error message and fail gracefully
env_nand.c would crash silently if a malloc() for the environment
buffers failed; make it print an error message and fail gracefully,
i. e. use the default environment then.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Acked-by: John Rigby <jcrigby@gmail.com>
2010-01-27 14:22:41 -06:00
Liu Yu
674ef7bd02 Nand boot: Add nand boot support for MPC8569mds board
This patch add nand boot support for MPC8569mds board.

Signed-off-by: Liu Yu <yu.liu@freescale.com>
2010-01-27 14:22:40 -06:00
Wolfgang Denk
9b208ece0a Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2010-01-27 20:19:08 +01:00
Kumar Gala
249d4dec69 Fix compiler warning in imximage.c due to getline prototype
imximage.c: In function 'imximage_parse_cfg_file':
imximage.c:142: warning: implicit declaration of function 'getline'

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-27 20:10:01 +01:00
Kumar Gala
a9c3ac78d8 85xx: Add support for 'cpu disable' command
Support disabling of a core via user command 'cpu disable'.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-26 23:17:50 -06:00
Kumar Gala
c894852b7a 86xx: Add support for 'cpu disable' command
Support disabling of a core via user command 'cpu disable'.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-26 23:17:50 -06:00
Kumar Gala
4194b3668a Add support to disable cpu's in multicore processors
Add a disable sub-command to the cpu command that allows for disabling
cores in multicore processors.  This can be useful for systems that are
using multicore chips but aren't utilizing all the cores as a way to
reduce power and possibly improve performance.

Also updated an added missing copyright.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-26 23:17:49 -06:00
Wolfgang Denk
797312a15e Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx 2010-01-26 22:32:38 +01:00
Wolfgang Denk
0a42c3a433 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2010-01-26 22:29:51 +01:00
Heiko Schocher
8b1760ed9a 83xx, kmeter1: fix compile error
- delete double MTDIDS_DEFAULT and MTDPARTS_DEFAULT
  defines in board config file.
- add mising CONFIG_KM_UBI_PARTITION_NAME define

Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2010-01-26 13:50:34 -06:00
Wolfgang Wegner
5912d36507 add ability to handle compressed images to imxtract
imxtract currently can not handle compressed images. This patch adds
handling for bzip2 and zip compression. In both cases, a destination
address has to be specified for extraction.

Signed-off-by: Wolfgang Wegner <w.wegner@astro-kom.de>
2010-01-26 19:36:07 +01:00
Joakim Tjernlund
a16e9a5b5f ppc: remove -ffixed-r14 gcc option.
This is no loger needed, free up r14 for general usage.

Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
2010-01-26 19:30:16 +01:00
Joakim Tjernlund
e6bee80814 ppc: Update README about the new GOT ptr.
r14 is no longer used as non volatile GOT ptr. Instead
the volatile r12 is used so be sure to do GET_GOT in
asm code when you need to access global data.

Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
2010-01-26 19:30:15 +01:00
Joakim Tjernlund
0f8aa15917 ppc: Use r12 instead of r14 as GOT pointer.
r14 is not supposed to be clobbered by functions. Switch
to r12 and call GET_GOT when needed. This will allow u-boot
to loose the -ffixed-r14 gcc option.

Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
2010-01-26 19:30:13 +01:00
Joakim Tjernlund
fc4e188789 ppc: Loose GOT access in IRQ
Using the GOT in IRQ handlers requires r14 to be -ffixed-r14.
Avoid this by relocatate transfer_to_handler too.
This will allow to free up r14 later on.

Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
2010-01-26 19:30:12 +01:00
Vivek Mahajan
66e821ebe9 85xx/p1_p2_rdb: enable hwconfig
Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-25 22:14:40 -06:00
Liu Yu
46df64f22c qe: fixup the snum for MPC8569 Rev2.0
Since 1.0 and 2.0 use different snum table,
we fixup the snum value according to SPRN_SVR.

Signed-off-by: Liu Yu <yu.liu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-25 22:14:39 -06:00
Dave Liu
0fd2fa6cce Fix the local bus divider mapping
The real clock divider is 4 times of the bits LCRR[CLKDIV],
according the latest RevF RM.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-25 22:14:39 -06:00
Liu Yu
c95d541e4b ppc/85xx: Add ATM config for MPC8569MDS
Signed-off-by: Liu Yu <yu.liu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-25 22:14:35 -06:00
Liu Yu
d918038269 ppc/85xx: Add PIB/ATM support for MPC8569mds
Signed-off-by: Liu Yu <yu.liu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-25 22:13:26 -06:00
Li Yang
1118cdbfeb fsl_esdhc: fix wrong clock mask
Fix typo in SYSCTL_CLOCK_MASK, which caused residual in high bits of SDCLKFS.

Signed-off-by: Jin Qing <B24347@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-25 22:13:26 -06:00
Kumar Gala
693416fe01 Revert "ppc/p4080: Fix reporting of PME & FM clock frequencies"
This reverts commit bc20f9a952.

The original code was correct.  I clearly need glasses or a brown
paper bag.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-25 22:13:25 -06:00
James Yang
93cedc7164 ppc/p4080: Fix mask width of RCW fields MEM_PLL_RAT, SYS_PLL_RAT
The masks for MEM_PLL_RAT and SYS_PLL_RAT should have been 5-bits
instead of 4.

Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-25 22:13:25 -06:00
Mike Frysinger
2903ad33a7 jffs2: fix hangs/crashs when not using CONFIG_JFFS2_PART_SIZE
Commit b5b004ad8a caused the sector_size to
be calculated incorrectly when the part size was not hardcoded.  This is
because the new code relied on part->size but tried to do the calculation
before it was initialized properly, and it did not take into consideration
the magic SIZE_REMAINING define.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-26 00:07:50 +01:00
Mike Frysinger
64b1502133 getline: split out for darwin systems
At least on OS X 10.5 and older, getline does not exist.  So split out the
function from the mingw code so that we can pull it in for Darwin systems.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-26 00:07:13 +01:00
Mike Frysinger
e852d36a1e tools: give explicit libfdt paths
The current libfdt object rules hard depend implicitly on the .depend file
being correct.  If it isn't, then it is unable to properly compile the
objects.  Give it a full path like all the other implicit rules here so it
will always work in face of .depend issues.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-26 00:05:42 +01:00
Mike Frysinger
44431cabbb gzip/zlib: make features optional
If you really want to slim down U-Boot and you would rather use a higher
compression scheme (like LZMA), it'd be nice to disable gzip/zlib since
these code bases take up a significant amount of space.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-26 00:04:57 +01:00
Stefano Babic
8edcde5e4e mkimage: Add Freescale imx Boot Image support (imximage)
This patch adds support for "imximage" (MX Boot Image)
to the mkimage utility. The imximage is used on the Freescales's
MX.25, MX.35 and MX.51 processors.

Further details under doc/README.imximage.

This patch was tested on a Freescale mx51evk board.

Signed-off-by: Stefano Babic <sbabic@denx.de>
2010-01-25 23:58:29 +01:00
Detlev Zundel
a21fb981d5 mpc5xxx: Support CPU internal watchdog.
Signed-off-by: Detlev Zundel <dzu@denx.de>
2010-01-25 23:57:39 +01:00
Detlev Zundel
82826d5422 mpc512x: Add display of reset status register
Content of the RSR is put into gd early so we can output it together
with the CPU info.  The clearing of gd in board_init_f is redundant for
this architecture as it is done in cpu_init_f so we remove it.

Signed-off-by: Detlev Zundel <dzu@denx.de>
2010-01-24 15:29:29 +01:00
Wolfgang Denk
a84b655fab Merge branch 'master-sync' of git://git.denx.de/u-boot-arm 2010-01-23 17:42:03 +01:00
Daniel Gorsulowski
a3f3897bfd at91: Enable slow master clock on meesc board
Normally the processor clock has a divisor of 2.
In some cases this this needs to be set to 4.
Check the user has set environment mdiv to 4 to change the divisor.

Signed-off-by: Daniel Gorsulowski <Daniel.Gorsulowski@esd.eu>
2010-01-23 08:15:50 -06:00
Vipin KUMAR
7da6923604 SPEAr : Support added for SPEAr320 board
SPEAr320 SoC support contains basic spear320 support along with the
usage of following drivers
- serial driver(UART)
- i2c driver
- smi driver
- nand driver(FSMC)
- usbd driver
- emi driver(cfi support)

Signed-off-by: Vipin <vipin.kumar@st.com>
2010-01-23 08:15:50 -06:00
Vipin KUMAR
080cfee714 SPEAr : Support added for SPEAr310 board
SPEAr310 SoC support contains basic spear310 support along with the
usage of following drivers
- serial driver(UART)
- i2c driver
- smi driver
- nand driver(FSMC)
- usbd driver
- emi driver(cfi support)

Signed-off-by: Vipin <vipin.kumar@st.com>
2010-01-23 08:15:50 -06:00
Vipin KUMAR
4bfacad4e7 SPEAr : emi controller initialization for CFI driver support
SPEAr310 and SPEAr320 SoCs contain an EMI controller to interface
Paraller NOR flashes. This patch adds the support for this IP

The standard CFI driver is used to interface with NOR flashes

Signed-off-by: Vipin <vipin.kumar@st.com>
2010-01-23 08:15:50 -06:00
Vipin KUMAR
7e074158ce SPEAr : Support added for SPEAr300 board
SPEAr300 SoC support contains basic spear300 support along with the
usage of following drivers
- serial driver(UART)
- i2c driver
- smi driver
- nand driver(FSMC)
- usbd driver

Signed-off-by: Vipin <vipin.kumar@st.com>
2010-01-23 08:15:50 -06:00
Vipin KUMAR
f92994f0f7 SPEAr : Support for HW mac id read/write from i2c mem
This patch adds the  support to read and write mac id from i2c
memory.
For reading:
	if (env contains ethaddr)
		pick env ethaddr
	else
		pick ethaddr from i2c memory
For writing:
	chip_config ethaddr XX:XX:XX:XX:XX:XX writes the mac id
	in i2c memory

Signed-off-by: Vipin <vipin.kumar@st.com>
2010-01-23 08:15:49 -06:00
Vipin KUMAR
566c9c16fe SPEAr : Support added for SPEAr600 board
SPEAr600 SoC support contains basic spear600 support along with the
usage of following drivers
- serial driver(UART)
- i2c driver
- smi driver
- nand driver(FSMC)
- usbd driver

Signed-off-by: Vipin <vipin.kumar@st.com>
2010-01-23 08:15:49 -06:00
Vipin KUMAR
62db1c0d79 SPEAr : usbd driver support for SPEAr SoCs
SPEAr SoCs contain a synopsys usb device controller.
USB Device IP can work in 2 modes
- DMA mode
- Slave mode

The driver adds support only for slave mode operation of usb
device IP. This driver is used along with standard USBTTY
driver to obtain a tty interface over USB on the host

Signed-off-by: Vipin <vipin.kumar@st.com>
2010-01-23 08:15:49 -06:00
Vipin KUMAR
165fa406ad SPEAr : nand driver support for SPEAr SoCs
SPEAr SoCs contain an FSMC controller which can be used to interface
with a range of memories eg. NAND, SRAM, NOR.
Currently, this driver supports interfacing FSMC with NAND memories

Signed-off-by: Vipin <vipin.kumar@st.com>
2010-01-23 08:15:49 -06:00
Vipin KUMAR
a6e34f76c5 SPEAr : smi driver support for SPEAr SoCs
SPEAr SoCs contain a serial memory interface controller. This
controller is used to interface with spi based memories.
This patch adds the driver for this IP.

Signed-off-by: Vipin <vipin.kumar@st.com>
2010-01-23 08:15:49 -06:00
Vipin KUMAR
2403f8f417 SPEAr : i2c driver support added for SPEAr SoCs
SPEAr SoCs contain a synopsys i2c controller.
This patch adds the driver for this IP.

Signed-off-by: Vipin <vipin.kumar@st.com>
2010-01-23 08:15:49 -06:00
Vipin KUMAR
81c0ebf623 SPEAr : Adding basic SPEAr architecture support.
SPEAr Architecture support added. It contains the support for
following SPEAr blocks
- Timer
- System controller
- Misc registers

Signed-off-by: Vipin <vipin.kumar@st.com>
2010-01-23 08:15:49 -06:00
Vipin KUMAR
6fffcdf8c8 SPEAr : Adding README.spear in doc
README.spear contains information about SPEAr architecture and
build options etc

Signed-off-by: Vipin <vipin.kumar@st.com>
2010-01-23 08:15:49 -06:00
Tom Rix
e4c43c20b8 ARM Update mach-types
Fetched from http://www.arm.linux.org.uk/developer/machines/download.php
And built with

repo http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm
commit 2045124ffd1a5e46d157349016a2c50f19c8c91d

Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
2010-01-23 08:15:49 -06:00
Prafulla Wadaskar
bfb6d510e9 Kirkwood: Makefile cleanup- fixed ordering (cosmetic change)
As per coding guidlines, it is good to maintain proper ordering
in the makefiles.
This was missed during initial coding, corrected here.

This was discovered during orion5x code review
Thanks to Albert Aribaud for this.

Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
2010-01-23 08:15:48 -06:00
Prafulla Wadaskar
beca04dd24 Kirkwood: Upgated licencing for files imported from linux source to GPLv2 or later
These are few files directly imported from Linux kernel source.
Those are not modifyed at all ar per strategy.
These files contains source with GPLv2 only
whereas u-boot expects GPLv2 or latter

These files are updated for the same from prior permission from original writes

Acked-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
2010-01-23 08:15:48 -06:00
Minkyu Kang
d8e5f55475 s5pc1xx: update cache routines
Because of v7_flush_dcache_all is moved to omap3/cache.S
and s5pc110 needs cache routines, update s5pc1xx cache routines.

l2_cache_enable and l2_caceh_disable are moved from cache.c to cache.S
and invalidate_dcache is modified for SoC specific.

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2010-01-23 08:15:48 -06:00
Seunghyeon Rhee
17ef9104ae samsung: fix DMC1_MEM_CFG for s3c64xx
The MSB of DMC1_MEM_CFG can be set to '1' for separate CKE control
for S3C6400. In the configuration of SMDK6400, however, two 16-bit
mDDR (SAMSUNG K4X51163) chips are used in parallel to form 32-bit
memory bus and there is no need to control CKE for each chip
separately. AFAIK, CKE1 is not at all connected. Only CKE0 is
used. Futhermore, it should be '0' always for S3C6410. When tested
with a board which has a S3C6410 and the same memory configuration,
a side effect is observed that u-boot command "reset" doesn't work
leading to system hang. Leaving the bit clear is safe in most cases.

Signed-off-by: Seunghyeon Rhee <seunghyeon@lpmtec.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2010-01-23 08:15:48 -06:00
Stefan Roese
9998b1366e ppc4xx: Kilauea: Add CPLD version detection and EBC reconfiguration
A newer CPLD version on the 405EX evaluation board requires a different
EBC controller setup for the CPLD register access. This patch adds a CPLD
version detection for Kilauea and code to reconfigure the EBC controller
(chip select 2) for the old CPLD if no new version is found.

Additionally the CPLD version is printed upon bootup:

Board: Kilauea - AMCC PPC405EX Evaluation Board (CPLD rev. 0)

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Wolfgang Denk <wd@denx.de>
Cc: Zhang Bao Quan <bqzhang@udtech.com.cn>
2010-01-23 09:27:28 +01:00
Felix Radensky
97c9f29008 ppc4xx: Fix sending type 1 PCI transactions
The list of 4xx SoCs that should send type 1 PCI transactions
is not defined correctly. As a result PCI-PCI bridges and devices
behind them are not identified. The following 4xx variants should
send type 1 transactions: 440GX, 440GP, 440SP, 440SPE, 460EX and 460GT.

Signed-off-by: Felix Radensky <felix@embedded-sol.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2010-01-23 09:27:18 +01:00
Detlev Zundel
57ae8a5cce mpc512x: Use in/out accessors for all registers
This is not only a cosmetic change as it fixes the real bug of board
reset not working with the ELDK 4.2 toolchain.

Signed-off-by: Detlev Zundel <dzu@denx.de>
2010-01-21 23:00:45 +01:00
Mike Frysinger
c7c0d542a1 tools: allow people to compile w/out configuring
It's useful to be able to build up the host tools without having to select
a board first.  Pretty much all tools in there are config-independent
anyways.

Also add a shortcut "tools-all" to quickly build all host tools that are
actually config-independent to allow for simple test builds.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-21 23:00:08 +01:00
Mike Frysinger
c5a028f085 ubsha1: drop unnecessary includes/prototypes
This code doesn't use any config.h defines, and the sha1.h header already
declares a sha1_csum prototype.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-21 22:59:29 +01:00
Mike Frysinger
5daa1c18b6 image.h: avoid command.h for host tools
The u-boot command structures don't get used with host systems, so don't
bother including it when building host code.  This avoids an implicit need
on config.h in the process.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-21 22:58:49 +01:00
Matthias Weisser
34be106517 Removing Atmel from ARM926EJ-S Systems
Signed-off-by: Matthias Weisser <weisserm@arcor.de>
2010-01-21 22:52:06 +01:00
Wolfgang Denk
6409b13d65 Merge branch 'master' of /home/wd/git/u-boot/custodians 2010-01-21 22:27:59 +01:00
Wolfgang Denk
4ac63017c3 Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx 2010-01-21 22:27:54 +01:00
Mike Frysinger
a16028da63 lmb: only force on arches that use it
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-21 22:26:00 +01:00
Mike Frysinger
dac4d7e884 sha1: add dedicated config option
The sha1 code is currently compiled for everyone, but in reality, it's
only used by the FIT code.  So make it optional just like MD5.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-21 22:21:22 +01:00
Wolfgang Denk
7114596a7d Merge branch 'master' of git://git.denx.de/u-boot-mips 2010-01-21 22:03:28 +01:00
Wolfgang Denk
d98acd729f Merge branch 'master' of git://git.denx.de/u-boot-nand-flash 2010-01-21 22:02:21 +01:00
Wolfgang Denk
0d131ad9be Merge branch 'master' of git://git.denx.de/u-boot-blackfin 2010-01-21 21:54:37 +01:00
Felix Radensky
33c8c66423 ppc4xx: Allow setting a single SPD EEPROM address for DDR2 DIMMs
On platforms where SPD EEPROM and another EEPROM have adjacent
I2C addresses SPD_EEPROM_ADDRESS should be defined as a single
element array, otherwise DDR2 setup code would fail with the
following error:

ERROR: Unknown DIMM detected in slot 1

However, fixing SPD_EEPROM_ADDRESS would result in another
error:

ERROR: DIMM's DDR1 and DDR2 type can not be mixed.

This happens because initdram() routine does not explicitly
initialize dimm_populated array. This patch fixes the problem.

Signed-off-by: Felix Radensky <felix@embedded-sol.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2010-01-21 08:18:37 +01:00
Felix Radensky
d98964aaac ppc4xx: Fix reporting of bootstrap options G and F on 460EX/GT
Bootstrap options G and F are reported incorrectly (G instead
of F and vice versa). This patch fixes this.

Signed-off-by: Felix Radensky <felix@embedded-sol.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2010-01-21 08:18:30 +01:00
Shinya Kuribayashi
19c2929997 MIPS: qemu_mips: Import asm/unaligned.h from the Linux kernel
with a few adjustments for U-Boot.  This fixes the following build error:

make -C lib_generic/
zlib.c:31:27: error: asm/unaligned.h: No such file or directory
zlib.c: In function 'inflate_fast':
zlib.c:641: warning: implicit declaration of function 'get_unaligned'
make[1]: *** [zlib.o] Error 1
make[1]: Leaving directory `/home/skuribay/git/u-boot.git/lib_generic'
make: *** [lib_generic/libgeneric.a] Error 2

Reported-by: Himanshu Chauhan <himanshu@symmetricore.com>
Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
2010-01-20 21:13:40 +09:00
Magnus Lilja
38a8b3eafb MX31: Activate NAND environment on i.MX31 PDK board.
Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
2010-01-19 17:08:13 -06:00
Magnus Lilja
c4832dffff MXC: Add large page oob layout for i.MX31 NAND controller.
Import the large page oob layout from Linux mxc_nand.c driver.

The CONFIG_SYS_NAND_LARGEPAGE option is used to activate
the large page oob layout. Run time detection is not supported
as this moment.

This has been tested on the i.MX31 PDK board with a large
page NAND device.

Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
2010-01-19 17:08:13 -06:00
Magnus Lilja
f6a9748e32 mxc_nand: Update driver to work with i.MX31.
Tested on i.MX31 Litekit.

Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
2010-01-19 17:08:13 -06:00
Magnus Lilja
c816dcb118 MX31: Add struct definition for clock control module in i.MX31.
Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
2010-01-19 17:08:12 -06:00
Michal Simek
50ef25ef24 microblaze: zlib needs asm/unaligned.h
Microblaze has own hw unaligned handler if is available.
Use big endian version.

Signed-off-by: Michal Simek <monstr@monstr.eu>
2010-01-19 23:22:22 +01:00
Michal Simek
5b8b83bce6 microblaze: Remove getenv_IPaddr prototype
Commit 6a45e38495
should remove reference from Microblaze too.

Signed-off-by: Michal Simek <monstr@monstr.eu>
2010-01-19 23:21:57 +01:00
Alessandro Rubini
b9e6957ca1 MAINTAINERS: fix nhk8815 board name
Signed-off-by: Alessandro Rubini <rubini@unipv.it>
2010-01-19 00:32:53 +01:00
Ben Warren
b40e2320c4 Fix breakage in SMC EEPROM standalone applications
Commit 6a45e38495 (Make getenv_IPaddr() global)
inadvertently added ' #include "net.h" ' to the standalone programs, creating
duplicate definitions of 'struct eth_device'.  This patch removes the local
definitions and removes other code that breaks due to the change in definition.

Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Acked-by: Mike Frysinger <vapier@gentoo.org>
2010-01-19 00:05:53 +01:00
Daniel Hobi
2a9987935e Makefile: fix parallel build
During parallel build, the top Makefile spawns multiple sub-makes for
targets in cpu/$(CPU) and $(dir $(LDSCRIPT)). If the .depend files are
not present in these directories, the sub-makes may end up generating
these files simultaneously which leads to corrupted content.

A typical error message is:

.depend:39: *** multiple target patterns.  Stop.

This patch serializes the creation of .depend in cpu/$(CPU) and
$(dir $(LDSCRIPT)) by adding these directories to the depend target
in the top Makefile.

Other directories in $(LIBS) are not affected since they contain only
one Make target and thus only one sub-make is spawned per directory.

Signed-off-by: Daniel Hobi <daniel.hobi@schmid-telecom.ch>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-18 22:25:16 +01:00
Robin Getz
f19fd87e93 Blackfin: add support for kgdb
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-17 20:36:09 -05:00
Robin Getz
3869453f65 asm-generic/signal.h: import from linux
We need signal.h for Blackfin/KGDB, so import the asm-generic/signal.h
for people to leverage.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-17 20:36:05 -05:00
Heiko Schocher
88ffb2665c CRAMFS: support cramfs in RAM
cramfsls and cramfsload are added to the command list.
A cramfs placed at 'cramfs_addr' can the be listed with 'cramfsls' and files
can be loaded with 'cramfsload'. 'cramfs_addr' is an environment variable
specifying the address the cramfs is located.
This works for powerpc and for ARM.

Use CONFIG_CMD_CRAMFS.

Signed-off-by: Andreas Huber <andreas.huber@keymile.com>
Signed-off-by: Heiko Schocher <hs@denx.de>
2010-01-18 00:44:13 +01:00
Heiko Schocher
4897ee33c9 powerpc: keymile boards updates
- malloc size 4 MB for all keymile boards
- use generic FDT code for fixing up the DTS
- enable unit-led at startup for keymile boards
- remove some dts updates for keymile boards
- ppc_83xx, kmeter1: take FE/GbE PHYs out of reset
- ppc_83xx, kmeter1: change from Intel Strata to Spansion 64MB flash
  changed from Intel Strata to Spansion 64MB flash and changed flash layout.
+---------+----------+-----------------------+-----------------------------+
| name    | size     | range                 | description                 |
+---------+----------+-----------------------+-----------------------------+
| u-boot  |   768 KB | 0xf0000000-0xf00bffff | for u-boot                  |
| env     |   128 KB | 0xf00c0000-0xf00dffff | for environment             |
| envred  |   128 KB | 0xf00e0000-0xf00fffff | for environment (redundant) |
| ubi0    | 64512 KB | 0xf0100000-0xf3ffffff | ubi0 for ubi volumes        |
+---------+----------+-----------------------+-----------------------------+

Signed-off-by: Heiko Schocher <hs@denx.de>
2010-01-18 00:43:54 +01:00
Heiko Schocher
1567b596d9 env, eeprom: add redundant environment support
Add redundant environment support for environment lying on a EEPROM.

Tested on uppcoming suen3 support

Signed-off-by: Andreas Huber <andreas.huber@keymile.com>
2010-01-18 00:43:16 +01:00
Heiko Schocher
548738b4d4 cmd_eeprom: I2C updates
- CONFIG_ENV_EEPROM_IS_ON_I2C
  define this, if you have I2C and SPI activated, and your
  EEPROM, which holds the environment, is on the I2C bus.

- CONFIG_I2C_ENV_EEPROM_BUS
  if you have an Environment on an EEPROM reached over
  I2C muxes, you can now define, how to reach this
  EEPROM.

Signed-off-by: Heiko Schocher <hs@denx.de>
2010-01-18 00:42:37 +01:00
Matthias Kaehlcke
b63815e313 move definition of macros likely and unlikely to compiler.h
the macros likely and unlikely were defined in include/linux/mtd/compat.h,
but used in code not related to MTD. moved the macro definitions to compiler.h

Signed-off-by: Matthias Kaehlcke <matthias@kaehlcke.net>
2010-01-18 00:28:27 +01:00
Detlev Zundel
c3d7eec6d8 cmd_bootm.c: Change interpretation of standalone image parameters.
Current code uses the second argument to bootm for standalone images to
override the load address specified in the image instead of passing all
parameters as is to the application.  This behaviour is not documented
and not in line with how the go command works for standalone applications,
so we simply drop it.

Signed-off-by: Detlev Zundel <dzu@denx.de>
2010-01-18 00:26:36 +01:00
Detlev Zundel
8b828a8f44 cmd_bootm.c: Do not load a ramdisk when not booting a kernel.
In case we boot an image marked as 'standalone' and 'linux', the current
code erroneously tried to load a ramdisk.

Signed-off-by: Detlev Zundel <dzu@denx.de>
2010-01-18 00:26:34 +01:00
Robin Getz
16035bcd8c kgdb: update mem2hex/hex2mem funcs
Convert the funcs to do the conversion inline so that we can do the copy
all at once with memcpy.  This let's us push out an weird arch-specific
issue with accessing different regions of memory to the memcpy function
like the MMRs on Blackfin systems, and it should be a bit faster.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-18 00:24:21 +01:00
Mike Frysinger
cbb0cab1d9 kgdb: drop duplicate debugger_exception_handler
The debugger_exception_handler definition is the same for everyone, so use
the common one now.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-18 00:23:33 +01:00
Robin Getz
0c909551f8 kgdb: add default generic stubs
The default kgdb functions can be implemented with common U-Boot functions,
so rather than force everyone to copy & paste these things, create a set of
weak stubs.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-18 00:23:00 +01:00
Mike Frysinger
fa2744de65 netconsole: mark local funcs with static
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-18 00:21:49 +01:00
Michael Hennerich
7293e0577f easylogo: add support for 16-bit RGB565
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-18 00:21:05 +01:00
Detlev Zundel
0f597bc2a8 mpc5xxx/cpu_init.c: Convert to IO accessors.
Signed-off-by: Detlev Zundel <dzu@denx.de>
2010-01-18 00:19:57 +01:00
Detlev Zundel
18e8989062 mpc5xxx.h: Add structure definition for XLB arbiter block.
Signed-off-by: Detlev Zundel <dzu@denx.de>
2010-01-18 00:19:27 +01:00
Mike Frysinger
10c32ff59f config_defaults.h: new header for common u-boot config defaults
There are a bunch of features in U-Boot that we want to enable by default,
and it's best if we centralize them in one place rather than updating all
the board files out there.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-18 00:04:42 +01:00
Wolfgang Denk
3e3989619f Merge branch 'master' of git://git.denx.de/u-boot-blackfin 2010-01-17 23:08:42 +01:00
Peter Tyser
64917ca389 PCIe, USB: Replace 'end point' references with 'endpoint'
When referring to PCIe and USB 'endpoint' is the standard naming
convention.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: Remy Bohmer <linux@bohmer.net>
2010-01-17 23:06:44 +01:00
Dirk Behme
6a45e38495 Make getenv_IPaddr() global
There are boards out there that do not have network support in
U-Boot (CONFIG_CMD_NET not set), but they do so in Linux. This
makes it desirable to be able to port network configuration (like
the IP address) to the Linux kernel.

We should not make the passing of the IP configuration to Linux
dependent on U-Boot features / settings.

For this, make getenv_IPaddr() global. This fixes build error

u-boot/lib_xxx/board.c:360: undefined reference to `getenv_IPaddr'

on various architectures.

Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
Acked-by: Ben Warren <biggerbadderben@gmail.com>
2010-01-17 20:14:47 +01:00
Mike Frysinger
846a6391e4 Blackfin: drop .eh_frame from linker script
Nothing in U-Boot uses runtime C++ exceptions/unwinding, so there is no
need to list this section.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-17 09:17:27 -05:00
Mike Frysinger
ed912d4d65 Blackfin: use sort funcs in the linker script
This is just Blackfin catching up with every one else.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-17 09:17:27 -05:00
Harald Krapfenbauer
2aeda2d054 Blackfin: tcm-bf518: new board port
Signed-off-by: Harald Krapfenbauer <Harald.Krapfenbauer@bluetechnix.at>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-17 09:17:27 -05:00
Mike Frysinger
c46a0ebf82 Blackfin: enable JFFS summary support for ADI boards
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-17 09:17:27 -05:00
Mike Frysinger
912da8d606 Blackfin: bf518f-ezbrd: increase monitor length
The addition of KGDB overflowed the current linker section.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-17 09:17:27 -05:00
Robin Getz
03642aeee0 Blackfin: handle anomaly 05000257
Need to reload the loop counters to keep from corrupting hardware loops.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-17 09:17:27 -05:00
Robin Getz
b6db283440 Blackfin: keep hwtrace on CPLB miss
Crashes rarely happen in the CPLB miss handler compared to the rest of
U-Boot code, so disable hardware tracing when processing misses.  This
way a crash due to other functions will be shown properly.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-17 09:17:27 -05:00
Robin Getz
0097870e3d Blackfin: add a netconsole helper
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-17 09:17:27 -05:00
Michael Hennerich
10eafa10be Blackfin: add support for BF527-EZKIT v2.1
The new board revision has a different LCD.

Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-17 09:17:27 -05:00
Cliff Cai
9442c4a133 Blackfin: bf527-ezkit/bf548-ezkit: add musb board specific initialization
Signed-off-by: Cliff Cai <cliff.cai@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-17 09:17:27 -05:00
Cliff Cai
581d92eefc Blackfin: bfin_spi: round up clock divider
If the requested clock cannot be exactly obtained, round it up so that we
err on the side of slightly slower rather than slightly faster.

Signed-off-by: Cliff Cai <cliff.cai@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-17 09:17:27 -05:00
Mike Frysinger
a52ad4f994 Blackfin: pull io funcs from linux
Some common code uses more of the io.h funcs than we currently provide, so
pull in all of the ones from the linux kernel.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-17 09:17:27 -05:00
Mike Frysinger
5eefe7e995 Blackfin: section off the CF/IDE io.h hacks
These need to be rethought, but until that happens, isolate the hack so
that we can extend the common code without breaking things.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-17 09:17:27 -05:00
Mike Frysinger
3b062da326 Blackfin: drop unused funcs from io.h
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-17 09:17:27 -05:00
Mike Frysinger
5f79644d26 Blackfin: bf533-stamp: split and cleanup CF/IDE code
Give the CF/IDE code its own file to keep things cleanly separated.  While
we're here, clean up the code to use common functions.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-17 09:17:27 -05:00
Cliff Cai
e54c820991 Blackfin: convert bfin_sdh to generic mmc
Signed-off-by: Cliff Cai <cliff.cai@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-17 09:17:27 -05:00
Cliff Cai
17ebd5bf33 Blackfin: bfin_spi: let boards control idle value
Some SPI devices like to see high idle values rather than low.

Signed-off-by: Cliff Cai <cliff.cai@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-17 09:17:27 -05:00
Mike Frysinger
ea693f22d8 Blackfin: asm/string.h: drop useless includes
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-17 09:17:27 -05:00
Mike Frysinger
f948158f72 Blackfin: use new bfin read/write mmr helper funcs
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-17 09:17:27 -05:00
Mike Frysinger
313e8aacc1 Blackfin: move watchdog config check to Makefile
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-17 09:17:26 -05:00
Mike Frysinger
dc6bc645e0 Blackfin: fix L1 Instruction sizes on BF52x/BF54x
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-17 09:17:26 -05:00
Mike Frysinger
b7659ef2e7 Blackfin: bf527-ezkit: auto-select NAND settings
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-17 09:17:26 -05:00
Mike Frysinger
7527feef06 Blackfin: support boards with no external memory
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-17 09:17:26 -05:00
Mike Frysinger
dbda2c65e5 Blackfin: re-architect initcode
The single initcode function was growing unwieldy, so split it up the
distinct steps into their own function.  This should making digesting the
result much easier on people.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-17 09:17:26 -05:00
Mike Frysinger
f5402d4c27 Blackfin: global_data.h: make pull in needed headers
We need the definition of bd_t in this header, so pull in asm/u-boot.h.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-17 09:17:26 -05:00
Mike Frysinger
fa45bd498a Blackfin: kill off useless initdram() usage
While the initdram() function makes sense on some arches, it doesn't for
Blackfin systems as it's always implemented the same way.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-17 09:17:26 -05:00
Mike Frysinger
b1e2c5519a Blackfin: move section length calculation to linker script
The length of the sections is fixed at link time, so let the linker do the
calculation rather than doing it ourselves at runtime.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-17 09:17:26 -05:00
Valentin Yakovenkov
446707c90f Blackfin: bf561-acvilon: new board port
Signed-off-by: Valentin Yakovenkov <yakovenkov@niistt.ru>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-17 09:17:26 -05:00
Mike Frysinger
16ada4f66f Blackfin: ADI settings: enable silent console support
Very little additional code overhead, and only works when the user sets an
env var ahead of time, so default to on makes sense.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-17 09:17:26 -05:00
Mike Frysinger
ac41c7a0e7 Blackfin: bf537-stamp: rename SPI/MMC define
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-17 09:17:26 -05:00
Harald Krapfenbauer
fd04a05b89 Blackfin: update tiny board settings (voltage/default env)
The tinyboards like to run at a little lower voltage than the default, and
they prefer to boot over the network.  For the latter, extend the common
code a little to make this easier.

Also fix the cm-bf527 env sector size while we're in here to reflect the
flash that is actually in use.

Signed-off-by: Harald Krapfenbauer <Harald.Krapfenbauer@bluetechnix.at>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-17 09:17:26 -05:00
Mike Frysinger
76d82187c6 Blackfin: tweak embedded LDR env config option
Use the common config option for extracting the environment for embedding
into LDR files and clarify the LDR-specific option.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-17 09:17:26 -05:00
Wolfgang Denk
2740544881 malloc: return NULL if not initialized yet
When malloc() was called before it was properly initialized
(as would happen if when used before relocation to RAM) it returned
random, non-NULL values, which called all kinds of difficult to debug
subsequent errors.

Make sure to return NULL when initialization was not done yet.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2010-01-15 13:26:20 +01:00
Wolfgang Denk
f098337152 JFFS2: drop support for LZARI compression mode
Support for LZARI compression mode was added based on a MTD CVS
snapshot of March 13, 2005. However, fs/jffs2/compr_lzari.c contains
contradictory licensing terms: the original copyright clause says "All
rights reserved. Permission granted for non-commercial use.", but
later reference to the file 'LICENCE' in the jffs2 directory was added
which says GPL v2 or later.

As no boards ever used LZARI compression, and this file is also not
present in recent MTD code, we resolve this conflict by removing the
conflicting file and references to it.

Also copy the referenced but missing file 'LICENCE' from the current
MTD source tree.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2010-01-15 11:16:47 +01:00
Wolfgang Denk
2ff6922280 Merge branch 'master' of git://git.denx.de/u-boot-arm 2010-01-12 23:47:03 +01:00
Wolfgang Denk
f8b365ceb6 Merge branch 'master' of git://git.denx.de/u-boot-nand-flash 2010-01-12 23:42:32 +01:00
Wolfgang Denk
c76b64666e Merge branch 'master' of git://git.denx.de/u-boot-usb 2010-01-12 23:39:08 +01:00
Wolfgang Denk
02c631e6ee Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx 2010-01-12 23:30:40 +01:00
Bryan Wu
321790f61b usb: musb: add virtual root hub control support
For MUSB devices that do not support multipoint (hubs), we have to emulate
a root hub so that we can support core operations like resetting ports.

Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Cliff Cai <cliff.cai@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-12 20:11:27 +01:00
Chris Zhang
559e2c87e4 Adds EHCI definitions to sequoia board configuration file.
Adds required definitions for EHCI support in sequoia configuration file.
But still keeps the OHCI as default driver.

Signed-off-by: Chris Zhang <chris@seamicro.com>
2010-01-09 10:27:21 +01:00
Chris Zhang
5f82887fee Add ppc440epx USB ehci support.
Currently ppc440epx uses OHCI for USB full-speed support. This change adds
support for EHCI.

Signed-off-by: Chris Zhang <chris@seamicro.com>
2010-01-09 10:27:15 +01:00
Chris Zhang
b416191a14 Fix EHCI port reset.
In USB ehci driver, the port reset is not terminated. EHCI spec says "A host
 controller must terminate the reset and stabilize the state of the port within
 2 milliseconds". Without termination, a port stays at reset state. This is
 observed on ppc4xx(sequoia) boards.

Signed-off-by: Chris Zhang <chris@seamicro.com>
2010-01-09 10:25:43 +01:00
Sanjeev Premi
b301be0599 omap3: fix compile warning
This patch fixes this warning during compile:

omap3.c: In function 'musb_platform_init':
omap3.c:126: warning: label 'end' defined but not used

Problem reported by: Dirk Behme[dirk.behme@googlemail.com]

Signed-off-by: Sanjeev Premi <premi@ti.com>
2010-01-09 10:25:09 +01:00
Bryan Wu
e608f221c1 usb: musb: add support for Blackfin MUSB
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Cliff Cai <cliff.cai@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Remy Bohmer <linux@bohmer.net>
2010-01-09 10:25:09 +01:00
Bryan Wu
bc72a919e0 usb: musb: change rxcsr register from write to read/modify/write
The RX Control/Status register has bits that we want to preserve, so don't
just write out a single bit.  Preserve the others bits in the process.

The original code posted to the u-boot list had this behavior, but looks
like it was lost somewhere along the way to merging.

Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Cliff Cai <cliff.cai@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Remy Bohmer <linux@bohmer.net>
2010-01-09 10:25:09 +01:00
Bryan Wu
8868fd443b usb: musb: make multipoint optional
The multipoint handling under MUSB is optional, and some parts (like the
Blackfin processor) do not implement support for it.

Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Cliff Cai <cliff.cai@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Remy Bohmer <linux@bohmer.net>
2010-01-09 10:25:08 +01:00
Bryan Wu
df402ba381 usb: musb: make fifo support configurable
The dynamic FIFO handling under MUSB is optional, and some parts (like
the Blackfin processor) do not implement support for it.

Due to this, the FIFO reading/writing steps need special handling, so
mark the common versions weak so drivers can override.

Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Cliff Cai <cliff.cai@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Remy Bohmer <linux@bohmer.net>
2010-01-09 10:25:08 +01:00
Mike Frysinger
dc2cd05c91 usb: musb: make sure the register layout is packed
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Remy Bohmer <linux@bohmer.net>
2010-01-09 10:25:08 +01:00
Ajay Kumar Gupta
7b4292883b DA830: Add usb config
Adding USB configuration. Default is set for USB MSC host.

Signed-off-by: Ajay Kumar Gupta <ajay.gupta@ti.com>
Signed-off-by: Swaminathan S <swami.iyer@ti.com>
2010-01-09 10:25:07 +01:00
Ajay Kumar Gupta
7359273d94 DA8xx: Add MUSB host support
Tested USB host functionality on DA830 EVM.

Signed-off-by: Ajay Kumar Gupta <ajay.gupta@ti.com>
Signed-off-by: Swaminathan S <swami.iyer@ti.com>
2010-01-09 10:25:07 +01:00
Ajay Kumar Gupta
0b232310b2 DA8xx: Add GPIO register definitions
Added DA8xx GPIO base addresses in gpio_defs.h and pointers
to different BANKs which can be used to program GPIOs.

Signed-off-by: Ajay Kumar Gupta <ajay.gupta@ti.com>
Signed-off-by: Swaminathan S <swami.iyer@ti.com>
2010-01-09 10:25:07 +01:00
Ajay Kumar Gupta
82a821f89b DA830: Add pinmux for USB0_DRVVBUS
USB0_DRVVBUS pinmux configuration is required for USB functinality
in uboot.

Signed-off-by: Ajay Kumar Gupta <ajay.gupta@ti.com>
Signed-off-by: Swaminathan S <swami.iyer@ti.com>
2010-01-09 10:25:06 +01:00
Heiko Schocher
a3f5da1bee mpc83xx: add support configure bus parking
Add support to configure bus parking mode and master in bus arbitration
configuration (ACR). Add this for the kmeter1 port:

Configure bus arbiter with recommended values from Freescale
to improve bus latency/throughput for application with
intensive QuiccEngine activity.

Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2010-01-07 18:39:42 -06:00
Reinhard Arlt
a0daa2e06f mpc83xx: vme8349: Fix power up reset sequence for tsi148
Remove PCI reset, if there is a monarch PMC module.

Signed-off-by: Reinhard Arlt <reinhard.arlt@esd.eu>
Signed-off-by: Stefan Roese <sr@denx.de>

convert clrbits_be32 + setbits_be32 to clrsetbits_be32, use out_be32 to set gcr.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2010-01-07 18:36:30 -06:00
Reinhard Arlt
1dee9be683 mpc83xx: Add support for MPC8349 esd caddy2
The caddy2 is a variant of the already supported vme8349. So we just
add the differences to this board port. To better support those two
boards we switched from fixed SDRAM configuration to usage of
spd_sdram(). This is done by providing a board specific SPD EEPROM
routine with different values for both boards.

Signed-off-by: Reinhard Arlt <reinhard.arlt@esd.eu>
Signed-off-by: Stefan Roese <sr@denx.de>

changed to use mkconfig -t option instead, plus misc codingstyle fixes.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2010-01-07 18:34:31 -06:00
Stefan Roese
7693640acd mpc83xx: spd_sdram.c: Disable memory controller before initializing
The memory controller could already be enabled, when spd_sdram() is
called. This could be the case for example, when the SDRAM is initialized
by the JTAG debugger.

The "sync" after the register access via the accessor function is
still needed, because the macro uses the sync before the real write
is done. So until not all accesses are converted to using accessor
functions, this sync still needs to be made "manually" here.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Reinhard Arlt <reinhard.arlt@esd.eu>
Acked-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2010-01-07 18:34:30 -06:00
Anton Vorontsov
2e95004deb mpc83xx: Add NAND boot support for MPC8315E-RDB boards
The core support for NAND booting is there already, so this patch
is pretty straightforward.

There is one trick though: top level Makefile expects nand_spl to
be in nand_spl/board/$(BOARDDIR), but we can fully reuse the code
from mpc8313erdb boards, and so to not duplicate the code we just
symlink nand_spl/board/freescale/mpc8315erdb to mpc8313erdb.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>

o silence make during ln echo
o update documentation
o and avoid:

$ ./MAKEALL MPC8315ERDB_NAND
Configuring for MPC8315ERDB board...
sdram.o: In function `fixed_sdram':
/home/r1aaha/git/u-boot/nand_spl/board/freescale/mpc8313erdb/sdram.c:72: undefined reference to `udelay'

by renaming udelay -> __udelay in the spirit of commit
3eb90bad65 "Generic udelay() with watchdog
support".

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2010-01-07 18:33:52 -06:00
Sanjeev Premi
b821cead7d onenand: Fix compile errors due to FlexOneNAND
This patch fixes the compile error while trying to
compile for omap3evm.

env_onenand.c: In function 'env_relocate_spec':
env_onenand.c:70: error: 'CONFIG_ENV_ADDR_FLEX' undeclared
 (first use in this function)
env_onenand.c:70: error: (Each undeclared identifier is re
ported only once
env_onenand.c:70: error: for each function it appears in.)
env_onenand.c: In function 'saveenv':
env_onenand.c:106: error: 'CONFIG_ENV_ADDR_FLEX' undeclare
d (first use in this function)
env_onenand.c:107: error: 'CONFIG_ENV_SIZE_FLEX' undeclare
d (first use in this function)

Signed-off-by: Sanjeev Premi <premi@ti.com>
Acked-by: Tom Rix <Tom.Rix@windriver.com>
2010-01-06 16:28:00 -06:00
Nick Thompson
20da6f4d93 Davinci: davinci_nand.c performance enhancments
Introduces various optimisations that approximately triple the
read data rate from NAND when run on da830evm.

Most of these optimisations depend on the endianess of the machine
and most of them are very similar to optimisations already present
in the Linux Kernel.

Signed-off-by: Nick Thompson <nick.thompson@ge.com>
2010-01-06 16:11:16 -06:00
Tom Rix
06f95959bc ARM Update mach-types
Fetched from http://www.arm.linux.org.uk/developer/machines/download.php
And built with

repo http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm
commit c9f937e4a3f4ebf9924ec21d80632e5eb61d949c

Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
2010-01-06 09:36:24 -06:00
Becky Bruce
8b0ab30494 ppc/p4080: Add Corenet Platform Cache (CPC) registers
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-05 13:52:00 -06:00
Dave Liu
3e731aaba3 fsl-ddr: setup ODT_RD_CFG & ODT_WR_CFG when we interleave
In chip-select interleaving case, we also need set the ODT_RD_CFG
and ODT_WR_CFG in cs1_config register.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-05 13:50:07 -06:00
Dave Liu
1aa3d08a02 fsl-ddr: add override for the Rtt_Wr
Different boards may require different settings of Dynamic ODT (Rtt_Wr).
We provide a means to allow the board specific code to provide its own
value of Rtt_Wr.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-05 13:49:27 -06:00
Dave Liu
bdc9f7b5ea fsl-ddr: add the override for write leveling
add the override for write leveling sampling and
start time according to specific board.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-05 13:49:10 -06:00
Dave Liu
0a71c92c7e fsl-ddr: Fix power-down timing settings
1. TIMING_CFG_0[ACT_PD_EXIT] was set to 6 clocks, but
   It should be set to tXP parameter, tXP=max(3CK, 7.5ns)
2. TIMING_CFG_0[PRE_PD_EXIT] was set to 6 clocks, but
   It should be set to tXP (if MR0[A12]=1) else to tXPDLL parameter
   We are setting the mode register MR0[A12]='1'

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-05 13:49:10 -06:00
Anton Vorontsov
c4ca10f1db mpc85xx: Add 4-bits eSDHC support for MPC8569E-MDS boards
Thanks to "Errata to MPC8569E PowerQUICC III Integrated Host Processor
Family Reference Manual, Rev. 0" document, which describes all eSDHC
pins, we can add 4-bits eSDHC support for MPC8569E-MDS boards.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-05 13:49:10 -06:00
Kumar Gala
bc20f9a952 ppc/p4080: Fix reporting of PME & FM clock frequencies
We incorrectly had the sense of PME_CLK_SEL, FM1_CLK_SEL, FM2_CLK_SEL
backwards so we report the wrong frequency.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-05 13:49:10 -06:00
Li Yang
de3cbd78c9 fsl_law: add SRIO2 target id and law_size_bits() macro
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-05 13:49:09 -06:00
Kumar Gala
abc76eb6a6 ppc/85xx: Map boot page guarded for MP boot
We already map the page cache-inhibited.  There is no reason we
shouldn't also be marking it guarded to prevent speculative accesses.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-05 13:49:09 -06:00
Kumar Gala
effe4973f2 ppc: Added macro to test for specific SVR revision
Various SoC errata are specific to a given revision of silicon. This
patch gives us a simple macro to use when doing such tests.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-05 13:49:09 -06:00
Dave Liu
f5ecc6e027 p4080: add readback to bootpage translation window
We need to add the readback to bootpage translation LAW
to make it effect.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-05 13:49:09 -06:00
Kumar Gala
5fb6ea3ad3 ppc/85xx: Make flash TLB entry determined at runtime on FSL boards
Rather than hard coding which TLB entry the FLASH is mapped with we can
use find_tlb_idx to determine the entry.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-05 13:49:08 -06:00
Kumar Gala
783852e467 ppc/85xx: Remove CONFIG_SYS_DDR_TLB_START
Now that we dynamically determine TLB CAM entries to use we dont need
CONFIG_SYS_DDR_TLB_START anymore.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-05 13:49:08 -06:00
Kumar Gala
355f4f85e9 ppc/85xx: Make SPD DDR TLB setup code use dynamic entry allocation
Now that we track which TLB CAM entries are used we can allocate
entries on the fly.  Change the SPD DDR TLB setup code to assume
we use at most 8 TLBs (or the number free, which ever is fewer).

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-05 13:49:08 -06:00
Kumar Gala
94e9411b9d ppc/85xx: Add tracking of TLB CAM usage
We need to track which TLB CAM entries are used to allow us to
"dynamically" allocate entries later in the code.  For example the SPD
DDR code today hard codes which TLB entries it uses.  We can now make
that pick entries that are free.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-05 13:49:08 -06:00
Kumar Gala
ee53650dad ppc/8xxx: Remove is_fsl_pci_agent
All users of is_fsl_pci_agent have been converted to fsl_is_pci_agent
that uses the standard PCI programming model to determine host vs
agent/end-point.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-05 13:49:07 -06:00
Kumar Gala
7cb8f79b44 ppc/85xx: Move to using fsl_setup_hose on TQM 85xx
We can use fsl_setup_hose to determine if we are a agent/end-point or
a host.  Rather than using some SoC specific register we can just look
at the PCI cfg space of the host controller to determine this.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-05 13:49:07 -06:00
Kumar Gala
9263e829f0 ppc/85xx: Move to using fsl_setup_hose on P2020 DS
We can use fsl_setup_hose to determine if we are a agent/end-point or
a host.  Rather than using some SoC specific register we can just look
at the PCI cfg space of the host controller to determine this.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-05 13:49:07 -06:00
Kumar Gala
1e21ba8f6d ppc/85xx: Move to using fsl_setup_hose on P1/P2 RDB
We can use fsl_setup_hose to determine if we are a agent/end-point or
a host.  Rather than using some SoC specific register we can just look
at the PCI cfg space of the host controller to determine this.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-05 13:49:07 -06:00
Kumar Gala
42c01b9d1f ppc/85xx: Move to using fsl_setup_hose on MPC8572 DS
We can use fsl_setup_hose to determine if we are a agent/end-point or
a host.  Rather than using some SoC specific register we can just look
at the PCI cfg space of the host controller to determine this.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-05 13:49:06 -06:00
Kumar Gala
5e3d7050cf ppc/86xx: Clean up MPC8610 HPCD PCI setup code
Use new fsl_pci_init_port() that reduces amount of duplicated code in the
board ports, use IO accessors and clean up printing of status info.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-05 13:49:06 -06:00
Kumar Gala
7b626880b4 ppc/85xx: Clean up MPC8548 CDS PCI setup code
Use new fsl_pci_init_port() that reduces amount of duplicated code in the
board ports, use IO accessors and clean up printing of status info.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-05 13:49:06 -06:00
Kumar Gala
feadd5d53b ppc/85xx: Clean up ATUM8548 PCI setup code
Use new fsl_pci_init_port() that reduces amount of duplicated code in the
board ports, use IO accessors and clean up printing of status info.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-05 13:49:06 -06:00
Kumar Gala
4681457e2a ppc/85xx: Clean up MPC8568 MDS PCI setup code
Use new fsl_pci_init_port() that reduces amount of duplicated code in the
board ports, use IO accessors and clean up printing of status info.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-05 13:49:05 -06:00
Kumar Gala
c847e98b14 ppc/85xx: Clean up MPC8569 MDS PCI setup code
Use new fsl_pci_init_port() that reduces amount of duplicated code in the
board ports, use IO accessors and clean up printing of status info.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-05 13:49:05 -06:00
Kumar Gala
645d5a7838 ppc/85xx: Clean up MPC8544 DS PCI setup code
Use new fsl_pci_init_port() that reduces amount of duplicated code in the
board ports, use IO accessors and clean up printing of status info.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-05 13:49:05 -06:00
Mingkai Hu
8a414c4258 ppc/85xx: Clean up MPC8536 DS PCI setup code
Use new fsl_pci_init_port() that reduces amount of duplicated code in the
board ports, use IO accessors and clean up printing of status info.

Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-05 13:49:05 -06:00
Kumar Gala
3ad89c4ecb NET: Base support for etsec2.0
1. Modified the tsec_mdio structure to include the new regs
2. Modified the MDIO_BASE_ADDR so that it will handle both
older version and new version of etsec.

Signed-off-by: Sandeep Gopalpet <sandeep.kumar@freescale.com>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-05 13:49:04 -06:00
Sandeep Gopalpet
b9e186fc31 NET: Move MDIO regs out of TSEC Space
Moved the mdio regs out of the tsec structure,and
provided different offsets for tsec base and mdio
base so that provision for etsec2.0 can be provided.

This patch helps in providing the support for etsec2.0
In etsec2.0, the MDIO register space and the etsec reg
space are different.

Also, moved the TSEC_BASE_ADDR and MDIO_BASE_ADDR definitons into
platform specific files.

Signed-off-by: Sandeep Gopalpet <sandeep.kumar@freescale.com>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-05 13:49:04 -06:00
Kumar Gala
bcad21fda1 85xx: Add support to set DPAA (data path) devices clock frequencies
Set clock-frequency for Frame Manager 0/1 and Patter Match Engine on p4080.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-05 13:49:04 -06:00
Kumar Gala
178e39e199 ppc/8xxx: Don't use pci_cfg on FSL_CORENET platforms
The FSL_CORENET platforms use a completely different means to determine
which PCIe port is enabled as well as if its a host or agent/end-point.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-05 13:49:03 -06:00
Kumar Gala
11588b5dc4 ppc/p4080: Added p4080 SERDES registers & USB offset
Added immap definition for SERDES registers on p4080, the USB offset
(since it was missing) and a GPL header.

Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-05 13:49:03 -06:00
Kumar Gala
82fd1f8da9 85xx: Add support for e500mc cache stashing
The e500mc core supports the ability to stash into the L1 or L2 cache,
however we need to uniquely identify the caches with an id.

We use the following equation to set the various stash-ids:

32 + coreID*2 + 0(L1) or 1(L2)

The 0 (for L1) or 1 (for L2) matches the CT field used be various cache
control instructions.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-05 13:49:02 -06:00
Nick Thompson
26be2c53d6 Davinci: NAND enable ECC even when not in NAND boot mode
Davinci: NAND enable ECC even when not in NAND boot mode

On Davinci platforms, the default NAND device is enabled (for ECC)
in low level boot code when NAND boot mode is used. If booting in
another mode, NAND ECC is not enabled. The driver should make
sure ECC is enabled regardless of boot mode if NAND is configured
in U-Boot.

Signed-off-by: Nick Thompson <nick.thompson@ge.com>
2010-01-04 08:48:17 -06:00
Nick Thompson
97f4eb8cfb Davinci: Configurable NAND chip selects
Davinci: Configurable NAND chip selects

Add a CONFIG_SYS_NAND_CS setting to all davinci configs and
use it to setup the NAND controller in the davinci_nand
mtd driver.

Signed-off-by: Nick Thompson <nick.thompson@gefanuc.com>
2010-01-04 08:48:17 -06:00
Nick Thompson
90110e0eab Davinci: Table driven pinmux configuration
Davinci: Table driven pinmux configuration

Add code to allow pinmux_config tables to be grouped and configured
as a single resource. This removes multiple calls to the pinmux
configuration code from board_init and allows pinmuxes to be
individually configured and added by data manipulation only.

All related #ifdefs can the be removed from board_init code and
since the compiler optimises away statics, #ifdefs can be reduced in
the data definitions as well.

Signed-off-by: Nick Thompson <nick.thompson@gefanuc.com>
2010-01-04 08:48:16 -06:00
Robert P. J. Day
1270ec13d4 Remove superfluous uses of V_PROMPT macro.
A number of config files define the V_PROMPT macro for the
command-line prompt, only to immediately use that macro to define
CONFIG_SYS_PROMPT, making V_PROMPT entirely superfluous.

Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
2010-01-04 08:48:16 -06:00
Grazvydas Ignotas
8b432bebc2 pandora: don't enable VAUX3, VDAC and VPLL2 regulators
These regulators are not needed to start the kernel and only
cause "incomplete constraints" warnings from kernel, so don't
turn them on to save power.

Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
2010-01-04 08:48:16 -06:00
Grazvydas Ignotas
ead39d7aa3 TWL4030: make LEDs selectable for twl4030_led_init()
Not all boards have both LEDs hooked, so enabling both on
boards with single LED will just waste power. Make it
possible to choose LEDs by adding argument to
twl4030_led_init().

Using this turn on only LEDB for pandora, leave both LEDs
on for all other boards, as it was before this patch.

Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
2010-01-04 08:48:15 -06:00
Wolfgang Denk
6ca9da4d42 Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx 2010-01-03 21:07:04 +01:00
Stefan Roese
be34fef7fd ppc4xx: alpr: Remove some not needed commands to make image fit again
The latest changes increased the size of the alpr image a bit more.
Now it doesn't fit into the 256k reserved for it. This patch now removes
the commands "ping" and "diag" which are not needed in the production
systems.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Pieter Voorthuijsen <pieter.voorthuijsen@prodrive.nl>
2009-12-22 05:53:00 +01:00
Heiko Schocher
072e754b6b i2c, ppc4xx: fix compiling KAREF and METROBOX boards.
commit eb5eb2b0f7

ppc4xx: Cleanup PPC4xx I2C infrastructure

This patch cleans up the PPC4xx I2C intrastructure:

- Use C struct to describe the I2C registers instead of defines
- Coding style cleanup (braces, whitespace, comments, line length)
- Extract common code from i2c_read() and i2c_write()
- Remove unneeded IIC defines from ppc405.h & ppc440.h

breaks comiling for the KAREF and METROBOX boards.

This patch fixes this issue.

Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2009-12-22 05:52:48 +01:00
Wolfgang Wegner
87d93a1ba2 move prototypes for gunzip() and zunzip() to common.h
Prototype for gunzip/zunzip was only in lib_generic/gunzip.c and thus
repeated in every file using it. This patch moves the prototypes to
common.h and removes all prototypes distributed anywhere else.

Signed-off-by: Wolfgang Wegner <w.wegner@astro-kom.de>
2009-12-21 21:39:59 +01:00
Wolfgang Denk
f7767c7541 Merge branch 'master' of git://git.denx.de/u-boot-usb 2009-12-21 21:01:56 +01:00
Mahavir Jain
127e10842b usb: write command for RAW partition.
This patch implements write support to usb device with raw partition.
It will be useful for filesystem write support to usb device from
u-boot in future.

Tested with writing kernel image to raw usb disk & booting with usb
read command into ram.

[Note:  run usb part to get info about start sector & number of
sectors on a partition for usb write operation.]

Signed-off-by: Mahavir Jain <mjain@marvell.com>
2009-12-20 12:53:00 +01:00
Ajay Kumar Gupta
73c8640e93 omap3evm: musb: add USB config
Added USB host and device config for host (MSC, Keyboard) and
device (ACM) functionalities.

Signed-off-by: Ajay Kumar Gupta <ajay.gupta@ti.com>
2009-12-20 12:53:00 +01:00
Tom Rix
ae4caf2fb5 OMAP3 USB Initialize twl4030 only if required
OMAP3EVM uses ISP1504 phy and so twl4030 related init is not required.

Submitted-by: Ajay Kumar Gupta <ajay.gupta@ti.com>
Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
2009-12-20 12:51:51 +01:00
Tom Rix
2ec1abea43 OMAP3 zoom2 Use usbtty if the debug board is not connected.
The preferred serial output comes from the debug board.
When the debug board is disconnected, fall back on using
usbtty from the usb connector on the Zoom2 board.

This shows up as /dev/ttyACM0 in a linux host.

Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
2009-12-20 12:51:51 +01:00
Tom Rix
6299487ef5 USBTTY make some function declarations easier to use.
Zoom2 needs to use these declarations and the include directory is a
better place from them than in the middle of the driver directory.
It did not make sense to create a new file for just a couple of
lines so they were appended to the serial.h

Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
2009-12-20 12:51:51 +01:00
Tom Rix
25374bfbf3 OMAP3 beagle Add usbtty configuration
The primary console of beagle is the serial header.

A secondary console is to use the usbtty.  The user can set this
manually by doing

setenv stdout usbtty; setenv stdin usbtty; setenv stderr usbtty
saveenv

usbtty will be usable by accessing the /dev/ttyACM0 on a linux host.

Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
2009-12-20 12:51:51 +01:00
Tom Rix
05be5a60e9 OMAP3 zoom1 Add usbtty configuration
The primary console of zoom1 is the serial out from the jumpers
accessed by removing the back panel.

A secondary console is to use the usbtty.  The user can set this
manually by doing

setenv stdout usbtty; setenv stdin usbtty; setenv stderr usbtty
saveenv

usbtty will be usable by accessing the /dev/ttyACM0 on a linux host.

Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
2009-12-20 12:50:53 +01:00
Tom Rix
f298e4b6dd OMAP3 Add usb device support
This change adds the usb device support for musb.

Omap3 platform support added at the same level as davinci.

The interface for usbtty to use the musb device support was added.

Verified on omap3 beagle, zoom1 and zoom2.

Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
2009-12-20 12:47:37 +01:00
Tom Rix
bffbb2a86d TWL4030 Add usb PHY support
The twl4030 provides a PHY device for connecting a link device,
like musb, to physical connection.

This change adds the twl4030 usb registers and functions for
initializing the PHY as required by omap3.

Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
2009-12-20 12:47:37 +01:00
Tom Rix
988365a204 USB add macros for debugging usb device setup.
When developing usb device features, it is useful to print out
common usb structures.

Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
2009-12-20 12:47:37 +01:00
Tom Rix
8f8bd565f3 USB Consolidate descriptor definitions
The header files usb.h and usbdescriptors.h have the same nameed
structure definitions for

usb_config_descriptor
usb_interface_descriptor
usb_endpoint_descriptor
usb_device_descriptor
usb_string_descriptor

These are out right duplicates in usb.h

usb_device_descriptor
usb_string_descriptor

This one has extra unused elements

usb_endpoint_descriptor

	unsigned char	bRefresh
	unsigned char	bSynchAddress;

These in usb.h have extra elements at the end of the usb 2.0
specified descriptor and are used.

usb_config_descriptor
usb_interface_descriptor

The change is to consolidate the definition of the descriptors
to usbdescriptors.h.  The dublicates in usb.h are removed.
The extra element structure will have their name shorted by
removing the '_descriptor' suffix.

So

usb_config_descriptor -> usb_config
usb_interface_descriptor -> usb_interface

For these, the common descriptor elements are accessed now
by an element 'desc'.

As an example

-	if (iface->bInterfaceClass != USB_CLASS_HUB)
+	if (iface->desc.bInterfaceClass != USB_CLASS_HUB)

This has been compile tested on MAKEALL arm, ppc and mips.

Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
2009-12-20 12:47:37 +01:00
Wolfgang Denk
b6535daefd Merge branch 'next' of git://git.denx.de/u-boot-net 2009-12-17 22:59:27 +01:00
Li Yang
e5e4e705ce Update Makefile for tag generating
Get tag directories from the $(__LIB) and also generate tag for .S files.

Signed-off-by: Li Yang <leoli@freescale.com>
2009-12-17 22:57:54 +01:00
Kumar Gala
d02ffbf8d7 drivers/bios_emulator: Fix compile error in .depend not being generated
make -C drivers/bios_emulator/
make[2]: Entering directory
`drivers/bios_emulator'
In file included from atibios.c:49:
biosemui.h:47:21: error: biosemu.h: No such file or directory
...
x86emu/decode.c:40:28: error: x86emu/x86emui.h: No such file or directory
...

Due to lack of proper CPPFLAGS being passed to .depend generation rule

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-12-17 22:24:36 +01:00
Wolfgang Denk
bb3bcfa242 Merge branch 'next' of ../next 2009-12-15 23:38:34 +01:00
Wolfgang Denk
a200a7c04d Update CHANGELOG; prepare Prepare v2009.11
Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-12-15 23:20:54 +01:00
Peter Tyser
f9476902b7 mpc85xx, mpc86xx: Fix gd->cpu pointer after relocation
The gd->cpu pointer is set to an address located in flash when the
probecpu() function is called while U-Boot is executing from flash.
This pointer needs to be updated to point to an address in RAM after
relocation has occurred otherwise Linux may not be able to boot due to
"fdt board" crashing if flash has been erased or changed.

This bug was introduced in commit
a0e2066f39.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Reported-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Tested-by: Kumar Gala <galak@kernel.crashing.org>
Tested on MPC8527DS.
Tested by: Ed Swarthout <Ed.Swarthout@freescale.com>
2009-12-15 22:45:51 +01:00
Ben Warren
1ab70f6fff Net: Clean up LAN91C96 Support
A previous Commit converted the LAN91C96 Ethernet driver to using the
CONFIG_NET_MULTI API, but did not include full board support.  This patch
finishes the job.

Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-12-14 16:42:03 -08:00
Peter Tyser
3363a34b9e MVBLUE: Remove CONFIG_CMD_IRQ
Neither the MVBLUE nor its underlying architecture implement the
do_irqinfo() function which is required when CONFIG_CMD_IRQ is defined.
This change fixes the following MVBLUE compiler error:

-> ./MAKEALL MVBLUE
Configuring for MVBLUE board...
common/libcommon.a(cmd_irq.o):(.u_boot_cmd+0x24): undefined reference to `do_irqinfo'
make: *** [u-boot] Error 1

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Acked-by: Andre Schwarz <andre.schwarz@matrix-vision.de>
2009-12-14 21:31:17 +01:00
Detlev Zundel
18e8ad60ee imx27lite: Reenable MTD support on NOR flash.
The support for this was silently dropped by a configuration
split during the merge of the imx27lite board support in commit
864aa034f3 (cmd_mtdparts: Move to common
handling of FLASH devices via MTD layer).

Signed-off-by: Detlev Zundel <dzu@denx.de>
2009-12-14 21:30:11 +01:00
Thomas Weber
076cd24cb4 net: dm9000x: fix debug output
commit 60f61e6d76 breaks compile with gcc by introducing __func__
instead of constant string "func" in the macro call but missed to change the macro.

Signed-off-by: Thomas Weber <weber@corscience.de>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-12-13 21:57:01 -08:00
John Ogness
c179a2896e fec_mxc: incomplete error handling
fec_init() will only allocate fec->base_ptr if it is non-NULL. But
the cleanup routine on error will free the pointer without setting
it to NULL. This means that a later call to fec_init() would result
in using an invalid pointer.

Signed-off-by: John Ogness <john.ogness@linutronix.de>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-12-13 21:55:15 -08:00
Reinhard Arlt
2ab4a4d095 net: e1000: Add support for the Intel 82546GB controller
This chip is equipped for example on the esd PMC-ETH2-GB board. So let's
add it to the list of supported chips to the e1000 driver.

Signed-off-by: Reinhard Arlt <reinhard.arlt@esd.eu>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-12-13 21:52:30 -08:00
Remy Bohmer
aafda38fb2 Add error codes/handling for TFTP-server
Signed-off-by: Remy Bohmer <linux@bohmer.net>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-12-13 21:31:26 -08:00
Nishanth Menon
ac6b362a25 LAN91C96: Enable NET_MULTI LAN driver
This modification is NOT tested on any of the
platforms modified as I dont have them. please
help by testing+building+fixing

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-12-13 21:31:26 -08:00
Nishanth Menon
a1725999b8 TI OMAP3: SDP3430 FIX NET_MULTI Warning
Enable the NET MULTI option and remove build warning

Tested: SDP3430

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-12-13 21:31:26 -08:00
Nishanth Menon
b7ad4109da NET: LAN91C96 CONFIG_NET_MULTIify
Make the lan91c96 driver capable of CONFIG_NET_MULTI
to be clean for the new arch, add a a lil detect function
Most of the formatting change was done to keep checkpatch
silent, but a few functions and #if 0ed code which
does not make sense for NET_MULTI have been removed

Now, use the lan91c96_initialize() function to init the driver

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-12-13 21:31:26 -08:00
Mike Frysinger
6ac59c5518 net: pull CONFIG checks out of source and into makefile
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-12-13 21:31:26 -08:00
Stefan Roese
f4cfe42758 nand: Fix access to last block in NAND devices
Currently, the last block of NAND devices can't be accessed. This patch
fixes this issue by correcting the boundary checking (off-by-one error).

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Wolfgang Denk <wd@denx.de>
2009-12-11 13:11:57 -06:00
Peter Korsgaard
3b887ca8ce mpc83xx: boot time regression, move LCRR setup back to cpu_init_f
Commit c7190f02 (retain POR values of non-configured ACR, SPCR, SCCR,
and LCRR bitfields) moved the LCRR assignment to after relocation
to RAM because of the potential problem with changing the local bus
clock while executing from flash.

This change unfortunately adversely affects the boot time, as running
all code up to cpu_init_r can cause significant slowdown.

E.G. on a 8347 board a bootup time increase of ~600ms has been observed:

   0.020 CPU:   e300c1, MPC8347_PBGA_EA, Rev: 3.0 at 400 MHz, CSB: 266.667 MHz
   0.168 RS:    232
   0.172 I2C:   ready
   0.176 DRAM:  64 MB
   1.236 FLASH: 32 MB

Versus:

   0.016 CPU:   e300c1, MPC8347_PBGA_EA, Rev: 3.0 at 400 MHz, CSB: 266.667 MHz
   0.092 RS:    232
   0.092 I2C:   ready
   0.096 DRAM:  64 MB
   0.644 FLASH: 32 MB

So far no boards have needed the late LCRR setup, so simply revert it
for now - If it is needed at a later time, those boards can either do
their own final LCRR setup in board code (E.G. in board_early_init_r),
or we can introduce a CONFIG_SYS_LCRR_LATE config option to only do
the setup in cpu_init_r.

Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-12-09 11:40:52 -06:00
Heiko Schocher
4b142febff common: delete CONFIG_SYS_64BIT_VSPRINTF and CONFIG_SYS_64BIT_STRTOUL
There is more and more usage of printing 64bit values,
so enable this feature generally, and delete the
CONFIG_SYS_64BIT_VSPRINTF and CONFIG_SYS_64BIT_STRTOUL
defines.

Signed-off-by: Heiko Schocher <hs@denx.de>
2009-12-08 22:14:07 +01:00
Heiko Schocher
00b6d927ba 5xxx, fdt: move fdt_fixup_memory() to cpu.c file
u-boot updates, before starting Linux, the memory node in the
DTS. As this is a "standard" feature, move this functionality
to the cpu.c file for mpc5xxx and mpc512x processors.

Signed-off-by: Heiko Schocher <hs@denx.de>
2009-12-08 22:13:02 +01:00
Michal Simek
386118a896 microblaze: Correct ffs regression for Microblaze
We are using generic implementation of ffs. This should
be part of Simon's commit 0413cfecea

Here is warning message which this patch removes.

In file included from /tmp/u-boot-microblaze/include/common.h:38,
                 from cmd_mtdparts.c:87:
/tmp/u-boot-microblaze/include/linux/bitops.h:123:1: warning: "ffs" redefined
In file included from /tmp/u-boot-microblaze/include/linux/bitops.h:110,
                 from /tmp/u-boot-microblaze/include/common.h:38,
                 from cmd_mtdparts.c:87:
/tmp/u-boot-microblaze/include/asm/bitops.h:269:1:
warning: this is the location of the previous definition

Signed-off-by: Michal Simek <monstr@monstr.eu>
2009-12-08 09:19:01 +01:00
Graeme Smecher
8fe7b29f98 microblaze: Stop stack clobbering in microblaze-generic.
A typo caused the stack and malloc regions to overlap, which prevented
mem_malloc_init() from returning. This commit makes the memory layout match
the example described in include/configs/microblaze-generic.h

Signed-off-by: Graeme Smecher <graeme.smecher@mail.mcgill.ca>
Signed-off-by: Michal Simek <monstr@monstr.eu>
2009-12-08 08:51:42 +01:00
Wolfgang Denk
35e3717772 Merge branch 'master' of ../work into next 2009-12-07 23:42:33 +01:00
Wolfgang Denk
0fc52948bd Update CHANGELOG, prepare -rc2
Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-12-07 23:14:13 +01:00
Peter Tyser
f2352877cb MAKEALL: Fix return value
Previously MAKEALL would always return a value of 0, even if 1 or more
boards did not compile.  This change causes MAKEALL to return 0 if all
boards were able to build, otherwise 1.

This change also requires changing the script interpreter from sh to
bash to support bash's PIPESTATUS variable.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2009-12-07 23:06:42 +01:00
Peter Tyser
fbc1c8f6f6 tools/mkimage: Remove duplicate line of code
Recent commits 1a99de2cb4 and
6a590c5f5f both fixed the same bug in the
same manner.  Unfortunately git was "smart" enough to merge both changes
which resulted in some duplicate code.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>

Reordered code and comment a bit.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-12-07 23:01:42 +01:00
Heiko Schocher
df002fa6b9 i2c: fix dangling comment in do_i2c_mw()
commit bd3784df94 deleted some unused
code in do_i2c_mw(), but missed to also remove the respective
commment. This patch fixes this.

Signed-off-by: Heiko Schocher <hs@denx.de>
2009-12-07 22:58:46 +01:00
Heiko Schocher
7cb5fc15f2 mpc52xx, manroland: add some commands
add the following commands for the manroland boards:

CONFIG_CMDLINE_EDITING
CONFIG_COMMAND_HISTORY
CONFIG_AUTO_COMPLETE

Signed-off-by: Heiko Schocher <hs@denx.de>
2009-12-07 22:50:41 +01:00
Wolfgang Denk
206c00f26f Merge branch 'master' into next
Conflicts:
	lib_generic/zlib.c

Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-12-07 22:47:17 +01:00
Stefan Roese
39ff7d5f4c POST: Remove duplicated post_hotkey_pressed() functions
This patch introduces a weak default function for post_hotkey_pressed(),
returning 0, for boards without hotkey support. The long-running tests
won't be started on those boards. This default function was implemented
in many board directories. By implementing this weak default we can
remove all those duplicate versions.

Boards with hotkey support, can override this weak default function
by defining one in their board specific code.

Signed-off-by: Stefan Roese <sr@denx.de>
2009-12-07 22:44:31 +01:00
Heiko Schocher
f8450829f9 52xx, manroland: add fdt_fixup_memory() in ft_board_setup()
To update the real memory size in the memory node on the
uc101 and mucmc52 boards call fdt_fixup_memory() in
ft_board_setup().

Signed-off-by: Heiko Schocher <hs@denx.de>
2009-12-07 22:39:38 +01:00
Daniel Hobi
0ec81db202 Fix computation in nand_util.c:get_len_incl_bad
Depending on offset, flash size and the number of bad blocks,
get_len_incl_bad may return a too small value which may lead to:

1) If there are no bad blocks, nand_{read,write}_skip_bad chooses the
bad block aware read/write code. This may hurt performance, but does
not have any adverse effects.

2) If there are bad blocks, the nand_{read,write}_skip_bad may choose
the bad block unaware read/write code (if len_incl_bad == *length)
which leads to corrupted data.

Signed-off-by: Daniel Hobi <daniel.hobi@schmid-telecom.ch>
2009-12-07 22:38:16 +01:00
Evan Samanas
aabb8cb081 nfs: NfsTimeout() updates
- NfsTimeout() does not correctly update the NFS timeout value which
  results in NfsTimeout() only being called once in certain situations.
  This can result in the 'nfs' command hanging indefinetly.  For
  example, the command:

    nfs 192.168.0.1:/home/user/file

  will not exit until ctrl-c is pressed if 192.168.0.1 does not have an
  NFS server running.

  This issue is resolved by reinitializting the NFS timeout value inside
  NfsTimeout() when a timeout occurs.

- Make the 'nfs' command print the 'T' character when a timeout occurs.
  Previously there was no indication that timeouts were occuring.

- Mimic the 'tftpboot' command and when a download fails print "Retry
  count exceeded; starting again", and restart the download taking the
  'netretry' environment variable into account.

Signed-off-by: Evan Samanas <esamanas@xes-inc.com>
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>

Tested on TQM8xxL.

Tested by: Wolfgang Denk <wd@denx.de>

Tested on MPC8527DS.

Tested by: Ed Swarthout <Ed.Swarthout@freescale.com>
2009-12-07 22:35:47 +01:00
Peter Tyser
224c90d106 bootm: Fix help message's sub-command ordering
The help message for the 'bootm' command listed the 'cmdline' and 'bdt'
sub-commands in the wrong order which resulted in the error below when
following the 'help' command's instructions:

  "Trying to execute a command out of order"

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2009-12-07 22:12:49 +01:00
Robert P. J. Day
a93c92cdda help: Correct syntax of nandecc help output.
"nandecc" help output should not reproduce the command name, nor have
a trailing newline.

Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
2009-12-07 22:06:51 +01:00
Mike Rapoport
c2fff331a3 smc911x: update SMC911X related configuration description
Since commit 736fead8fd "Convert SMC911X
Ethernet driver to CONFIG_NET_MULTI API" SMC911X configration options
are called CONFIG_SMC911X rather than CONFIG_DRIVER_SMC911X. Update
README to reflect that change.

Signed-off-by: Mike Rapoport <mike@compulab.co.il>
2009-12-07 22:05:43 +01:00
Mike Rapoport
45b6b65c6b smc911x: fix typo in smc911x_handle_mac_address name
Signed-off-by: Mike Rapoport <mike@compulab.co.il>
2009-12-07 22:04:02 +01:00
Ed Swarthout
f64ef9bb99 fix nfs symlink name corruption
An off by one error may cause nfs readlink lookup fail if
nfs_path_buff has non-zero data from a previous use.

Loading: *** ERROR: File lookup fail

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
2009-12-07 21:50:19 +01:00
Wolfgang Denk
e8fac25e83 at91sam9261ek.c: fix minor coding style issue.
Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-12-07 21:50:19 +01:00
Wolfgang Denk
4713010adf trab: fix warning: implicit declaration of function 'disable_vfd'
Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-12-07 21:50:18 +01:00
Wolfgang Denk
a9f99ab44b zlib.c: avoid build conflicts for cradle board
Commit dce3d79710 updated the zlib code to v0.95; this caused
conflicts when building for the "cradle" board, because the (pretty
generic) preprocessor variable "OFF" was used in multiple files.
Make sure to avoid further conflicts by #undef'ing it in zlib.c
before redefining it.

Signed-off-by: Wolfgang Denk <wd@denx.de>
cc: Giuseppe Condorelli <giuseppe.condorelli@st.com>
cc: Angelo Castello <angelo.castello@st.com>
cc: Alessandro Rubini <rubini-list@gnudd.com>
2009-12-07 21:50:18 +01:00
Wolfgang Denk
8cbf4e4f17 Fix out-of-tree building of "apollon" board.
Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-12-06 00:27:06 +01:00
Wolfgang Denk
2a49bf3149 Merge branch 'master' into next
Conflicts:
	board/esd/plu405/plu405.c
	drivers/rtc/ftrtc010.c

Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-12-05 02:11:59 +01:00
Mike Frysinger
f68ab43de6 lzma: ignore unset filesizes
The Linux kernel build system changed how it compresses things with LZMA
such that the header no longer contains the filesize (it is instead set to
all F's).  So if we get a LZMA image that has -1 for the 64bit field,
let's just assume that the decompressed size is unknown and continue on.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-12-05 01:49:52 +01:00
Detlev Zundel
cccfc2ab77 README: Rearrange paragraphs to regain linear arrangement.
Two later additions to the Configuration Option section unfortunately
split the description of Show boot progress and the list of its call outs.

Signed-off-by: Detlev Zundel <dzu@denx.de>
2009-12-05 01:47:45 +01:00
Joakim Tjernlund
cd514aeb99 zlib: Optimize decompression
This patch optimizes the direct copy procedure.
Uses get_unaligned() but only in one place.
The copy loop just above this one can also use this
optimization, but I havn't done so as I have not tested if it
is a win there too.
On my MPC8321 this is about 17% faster on my JFFS2 root FS
than the original. No speed test has been performed in u-boot.

Size increase on ppc: 484 bytes

Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Acked-by: Peter Korsgaard <jacmet@sunsite.dk>
2009-12-05 01:32:32 +01:00
Peter Korsgaard
20dde48bca add lzop decompression support
Add lzop decompression support to the existing lzo bitstream handling
(think gzip versus zlib), and support it for uImage decompression if
CONFIG_LZO is enabled.

Lzop doesn't compress as good as gzip (~10% worse), but decompression
is very fast (~0.7s faster here on a slow ppc). The lzop decompression
code is based on Albin Tonnerre's recent ARM Linux lzo support patch.

Cc: albin.tonnerre@free-electrons.com
Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
2009-12-05 01:30:23 +01:00
Peter Tyser
c81296c16f tools/mkimage: Print FIT image contents after creation
Previously, there was no indication to the user that a FIT image was
successfully created after executing mkimage.  For example:

  $ mkimage -f uImage.its uImage.itb
  DTC: dts->dtb  on file "uImage.its"

Adding some additional output after creating a FIT image lets the user
know exactly what is contained in their image, eg:

  $ mkimage -f uImage.its uImage.itb
  DTC: dts->dtb  on file "uImage.its"
  FIT description: Linux kernel 2.6.32-rc7-00201-g7550d6f-dirty
  Created:         Tue Nov 24 15:43:01 2009
   Image 0 (kernel@1)
    Description:  Linux Kernel 2.6.32-rc7-00201-g7550d6f-dirty
    Type:         Kernel Image
    Compression:  gzip compressed
    Data Size:    2707311 Bytes = 2643.86 kB = 2.58 MB
    Architecture: PowerPC
    OS:           Linux
    Load Address: 0x00000000
    Entry Point:  0x00000000
    Hash algo:    crc32
    Hash value:   efe0798b
    Hash algo:    sha1
    Hash value:   ecafba8c95684f2c8fec67e33c41ec88df1534d7
   Image 1 (fdt@1)
    Description:  Flattened Device Tree blob
    Type:         Flat Device Tree
    Compression:  uncompressed
    Data Size:    12288 Bytes = 12.00 kB = 0.01 MB
    Architecture: PowerPC
    Hash algo:    crc32
    Hash value:   a5cab676
    Hash algo:    sha1
    Hash value:   168722b13e305283cfd6603dfe8248cc329adea6
   Default Configuration: 'config@1'
   Configuration 0 (config@1)
    Description:  Default Linux kernel
    Kernel:       kernel@1
    FDT:          fdt@1

This brings the behavior of creating a FIT image in line with creating a
standard uImage, which also prints out the uImage contents after
creation.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2009-12-05 01:13:51 +01:00
Peter Tyser
8e1c89663c tools/fit_image.c: Remove unused fit_set_header()
The FIT fit_set_header() function was copied from the standard uImage's
image_set_header() function during mkimage reorganization.  However, the
fit_set_header() function is not used since FIT images use a standard
device tree blob header.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2009-12-05 01:12:45 +01:00
Peter Tyser
1a99de2cb4 tools/mkimage: Assume FDT image type for FIT images
When building a Flattened Image Tree (FIT) the image type needs to be
"flat_dt".  Commit 89a4d6b12f introduced a
regression which caused the user to need to specify the "-T flat_dt"
parameter on the command line when building a FIT image.  The "-T
flat_dt" parameter should not be needed and is at odds with the current
FIT image documentation.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2009-12-05 01:12:39 +01:00
Ingo van Lil
3eb90bad65 Generic udelay() with watchdog support
According to the PPC reference implementation the udelay() function is
responsible for resetting the watchdog timer as frequently as needed.
Most other architectures do not meet that requirement, so long-running
operations might result in a watchdog reset.

This patch adds a generic udelay() function which takes care of
resetting the watchdog before calling an architecture-specific
__udelay().

Signed-off-by: Ingo van Lil <inguin@gmx.de>
2009-12-05 01:08:53 +01:00
Graeme Russ
1c409bc710 i386: Final Relocation
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2009-12-05 01:05:39 +01:00
Graeme Russ
cabe579480 i386: Move references to link script exports
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2009-12-05 01:05:07 +01:00
Graeme Russ
0fc1b49ecb i386: Remove inline asm symbols from .dynsym
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2009-12-05 01:04:44 +01:00
Graeme Russ
564a9984bd i386: Rearrange Interupt Handling
In preperation for full relocation

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2009-12-05 01:04:18 +01:00
Graeme Russ
27f13075a6 i386: Fix race condition when using SC520 timers
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2009-12-05 01:02:58 +01:00
Graeme Russ
141a62cc12 i386: Fix global label in inline asm compile error
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2009-12-05 01:02:46 +01:00
Graeme Russ
4ee4e413ba i386: Reorder source objects in lib_i386 Makefile
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2009-12-05 01:02:30 +01:00
Graeme Russ
aea14421c5 i386: Fix link collisions resulting from gcc4.4.1 upgrade
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2009-12-05 01:02:19 +01:00
Graeme Russ
b4feeb4e8a i386: Fix malloc initialization
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2009-12-05 01:02:10 +01:00
Graeme Russ
c74bfce0fb i386: Fix dlmalloc compile warning
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2009-12-05 01:01:49 +01:00
Michael Brandt
270737acca EXT2FS: fix inode size for ext2fs rev#0
extfs.c assumes that there is always a valid inode_size field in the
superblock. But this is not true for ext2fs rev 0. Such ext2fs images
are for instance generated by genext2fs. Symptoms on ARM machines are
messages like: "raise: Signal # 8 caught"; on PowerPC "ext2ls" will
print nothing.
This fix checks for rev 0 and uses then 128 bytes as inode size.

Signed-off-by: Michael Brandt <Michael.Brandt@emsyso.de>
Tested on: TQM5200S
Tested-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-12-05 00:46:10 +01:00
Robert P. J. Day
bcb324d68f Remove superfluous preprocessor tests from some cmd_*.c files.
A small number of common/cmd_*.c files contain preprocessor tests that
are apparently superfluous since those same tests are used in the
Makefile to control the compilation of those files.  Those tests are
clearly redundant as long as they surround the entirety of the source
in those files.

Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
2009-12-02 23:46:45 +01:00
Joakim Tjernlund
3ee8c12071 crc32: Impl. linux optimized crc32()
Ported over the more efficient linux crc32() function.
A quick comparsion on ppc:
After changing the old crc32 to do 4 bytes in the
inner loop to be able to compare with new version one can note:
- old inner loop has 61 insn, new has 19 insn.
- new crc32 does one 32 bit load of data to crc while
  the old does four 8 bits loads.
- size is bit bigger for the new crc32:
  1392(old) 1416(new) of text. The is because the new version
  shares code with crc32_no_comp() instead of duplicating code.
- about 33% faster on ppc:
  New > crc 0 0xfffffff -> 39 secs
  Old > crc 0 0xfffffff -> 60 secs

Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
2009-12-02 23:42:40 +01:00
Robert P. J. Day
ad53226156 README: Update the list of directories.
Bring the directory listing more into line with current content.

Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
2009-12-02 23:37:14 +01:00
Pratap Chandu
bd3784df94 Removes dead code in the file common/cmd_i2c.c
There is some dead code enclosed by #if 0 .... #endif in the file
common/cmd_i2c.c
This patch removes the dead code.

Signed-off-by: Pratap Chandu <pratap.rrke@gmail.com>
2009-12-02 23:35:24 +01:00
Mike Frysinger
64a480601a smc91111_eeprom: drop CONFIG stub protection
Since the Makefile now controls the compilation of this, there is no need
for CONFIG checking nor the stub function.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-12-02 23:33:01 +01:00
Magnus Lilja
f3a7bddc06 RTC: Fix return code in MC13783 RTC driver.
Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
2009-12-02 23:29:18 +01:00
Magnus Lilja
d52e3e0176 cmd_date: Fix spelling in error message.
Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
2009-12-02 23:28:10 +01:00
Peter Tyser
c253122395 Move do_irqinfo() to common/cmd_irq.c
cmd_irq.c is a much better home and it is already conditionally
compiled based on CONFIG_CMD_IRQ.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2009-12-02 23:23:20 +01:00
Peter Tyser
a5dd4dc64f cmd_license: Remove unneeded #ifdef CONFIG_CMD_LICENSE
cmd_license is already conditionally compiled at the Makefile-level.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2009-12-02 23:22:26 +01:00
Peter Tyser
06015146a1 m41t11: Remove unused functions
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2009-12-02 23:21:02 +01:00
Peter Tyser
9ef78511cd circbuf: Move to lib_generic and conditionally compile
circbuf could be used as a generic library and is only currently
needed when CONFIG_USB_TTY is defined.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2009-12-02 23:19:32 +01:00
Sanjeev Premi
604f7ce55a Fix build failure in examples/standalone
Some versions of 'make' do not handle trailing white-spaces
properly. Trailing spaces in ELF causes a 'fake' source to
be added to the variable COBJS; leading to build failure
(listed below). The problem was found with GNU Make 3.80.

Using text-function 'strip' as a workaround for the problem.

make[1]: Entering directory `/home/sanjeev/u-boot/examples/standalone'
arm-none-linux-gnueabi-gcc -g  -Os   -fno-common -ffixed-r8 -msoft-float
-D__KERNEL__ -DTEXT_BASE=0x80e80000 -I/home/sanjeev/u-boot/include
-fno-builtin -ffreestanding -nostdinc -isystem /opt/codesourcery/2009q1-
203/bin/../lib/gcc/arm-none-linux-gnueabi/4.3.3/include -pipe  -DCONFIG_
ARM -D__ARM__ -marm  -mabi=aapcs-linux -mno-thumb-interwork -march=armv5
-Wall -Wstrict-prototypes -fno-stack-protector -g  -Os   -fno-common -ff
ixed-r8 -msoft-float   -D__KERNEL__ -DTEXT_BASE=0x80e80000 -I/home/sanje
ev/u-boot/include -fno-builtin -ffreestanding -nostdinc -isystem /opt/co
desourcery/2009q1-203/bin/../lib/gcc/arm-none-linux-gnueabi/4.3.3/includ
e -pipe  -DCONFIG_ARM -D__ARM__ -marm  -mabi=aapcs-linux -mno-thumb-inte
rwork -march=armv5 -I.. -Bstatic -T u-boot.lds  -Ttext 0x80e80000 -o .c
arm-none-linux-gnueabi-gcc: no input files
make[1]: *** [.c] Error 1
make[1]: Leaving directory `/home/sanjeev/u-boot/examples/standalone'
make: *** [examples/standalone] Error 2
premi #

Signed-off-by: Sanjeev Premi <premi@ti.com>

Fixed typo (s/ElF/ELF/).
Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-12-02 23:17:26 +01:00
Scott Wood
d984fed068 makefiles: fixes for building build tools
Currently, some of the tools instead set CC to be HOSTCC in order to re-use
some pattern rules -- but this fails when the user overrides CC on the make
command line.  Also, the HOSTCFLAGS in tools/Makefile are currently not
being used because config.mk overwrites them.

This patch adds static pattern rules for files that have been requested to
be built with the native compiler using $(HOSTSRCS) and $(HOSTOBJS), and
converts the tools to use them.

It restores easylogo to using the host compiler, which was broken by commit
38d299c2db (if this was an intentional change,
please let me know -- but it seems to be a build tool).

It restores -pedantic and the special flags for darwin and cygwin that were
requested in tools/makefile (but keeps the flags added by config.mk) --
hopefully someone can test this on those platforms.  It no longer
conditionalizes -pedantic on not being darwin; it wasn't clear that that was
intentional, and unless there's a real problem it's just inviting people to
contribute non-pedantic patches to those files (I'm not a fan of -pedantic
personally, but if it's on for one platform it should be on for all).

HOST_LDFLAGS is renamed HOSTLDFLAGS for consistency with the previous
HOST_CFLAGS to HOSTCFLAGS rename.  A new HOSTCFLAGS_NOPED is made available
for those files which currently cannot be built with -pedantic, and replaces
the old FIT_CFLAGS.

imls now uses the cross compiler properly, rather than by trying to
reconstruct CC using the typoed $(CROSS_COMPILER).

envcrc.c is now dependency-processed unconditionally -- previously it would
be built without being on (HOST)SRCS if CONFIG_ENV_IS_EMBEDDED was not
selected.

Signed-off-by: Scott Wood <scottwood@freescale.com>
2009-12-02 22:58:46 +01:00
Becky Bruce
af860962b5 85xx: Remove unused CONFIG_ASSUME_AMD_FLASH from config files
A bunch of the 85xx boards have this cruft in them - it's not used
anywhere.  Delete it.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
2009-12-02 22:57:16 +01:00
Mike Frysinger
bf44f3f327 exports: rewrite jump table init
The current jump table init fails to initialize a bunch of exported
symbols (forceenv/do_reset/etc...).  Rather than fix just these few
missing pieces, rewrite the code to utilize the existing list of
exported symbols -- _exports.h.  Since every exported symbol has to
be listed in this header, it makes sense to use it so that we only
ever have one list that needs to be updated and things can't fall
out of sync again.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-12-02 22:53:51 +01:00
Wolfgang Denk
deec1fbd4f MAINTAINERS: update responsible for MPC85xx/86xx
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Kumar Gala <galak@kernel.crashing.org>
Cc: Becky Bruce <beckyb@kernel.crashing.org>
2009-12-02 22:27:26 +01:00
Wolfgang Denk
57bf140ac6 Merge branch 'next-sync' of git://git.denx.de/u-boot-arm into next 2009-12-01 12:10:51 +01:00
Wolfgang Denk
21c76b56a4 Merge branch 'master' of git://git.denx.de/u-boot-nios 2009-12-01 10:15:22 +01:00
Tom Rix
71636fa7c3 ARM Update mach-types
Fetched from http://www.arm.linux.org.uk/developer/machines/download.php
And built with

repo http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm
commit 3fcca9ac6cbce35b3e81e247d375534117d5f4cd

Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
2009-11-29 17:56:36 -06:00
Vaibhav Hiremath
7c15121f40 omap3_mmc: Encapsulate twl4030 under option CONFIG_TWL4030_POWER
Fixes the build/compilation error if we try to re-use the omap3_mmc code
without TWL4030_POWER.

Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
2009-11-27 16:26:18 -06:00
Sandeep Paulraj
6406d6daea TI DaVinci: Adding a README for the DaVinci series of SOC's
Adding an initial README for the DaVinci series of SOC's

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2009-11-27 16:26:18 -06:00
Jean-Christophe PLAGNIOL-VILLARD
990f569c4f avr32/hsdramc: Move conditional compilation to Makefile
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj <at> jcrosoft.com>
Cc: Haavard Skinnemoen <haavard.skinnemoen <at> atmel.com>
2009-11-27 16:26:17 -06:00
Sandeep Paulraj
3f12f5217e NAND: Add config option for imx27lite
We will get compilation warnings without
"CONFIG_SYS_64BIT_VSPRINTF" being defined
in the board config.

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2009-11-27 16:26:17 -06:00
Po-Yu Chuang
43a5f0df2f arm: A320: Add support for Faraday A320 evaluation board
This patch adds support for A320 evaluation board from Faraday. This board
uses FA526 processor by default and has 512kB and 32MB NOR flash, 64M RAM.
FA526 is an ARMv4 processor and uses the ARM920T source in this patch.

Signed-off-by: Po-Yu Chuang <ratbert@faraday-tech.com>
2009-11-27 16:26:17 -06:00
Po-Yu Chuang
39ba774f9b arm: A320: driver for FTRTC010 real time clock
This patch adds an FTRTC010 driver for Faraday A320 evaluation board.

Signed-off-by: Po-Yu Chuang <ratbert@faraday-tech.com>
2009-11-27 16:26:17 -06:00
Sandeep Paulraj
c1ee63cee8 TI DaVinci DM646x: Enable NAND on DM6467 EVM
This patch enables NAND on the DM6467 EVM

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2009-11-27 16:26:17 -06:00
Nishanth Menon
d414aae552 OMAP3: Fix SDRC init
Defaults are for Infineon DDR timings.
Since none of the supported boards currently do
XIP boot, these seem to be faulty. fix the values
as per the calculations(ACTIMA,B), conf
the sdrc power with pwdnen and wakeupproc bits

Signed-off-by: Nishanth Menon <nm@ti.com>
2009-11-27 16:26:17 -06:00
Nishanth Menon
30563a04bf OMAP3:SDRC: introduce DDR types
Micron DDR timings based on:
http://www.sakoman.net/cgi-bin/gitweb.cgi?p=x-load-omap3.git;a=blob;f=include/asm/arch-omap3/mem.h;h=e6fbfe3947f5d0d85fea776e30821d4017316d86;hb=HEAD

Introduce Micron DDR timings and provide
CONFIG_OMAP3_INFINEON_DDR and CONFIG_OMAP3_MICRON_DDR config
options to allow for platform files to setup their timings as
per the type of DDR selected

Reported-by: Steve Sakoman in http://www.nabble.com/forum/Permalink.jtp?root=25779518&post=25959734&page=y

Signed-off-by: Nishanth Menon <nm@ti.com>
2009-11-27 16:26:16 -06:00
Nishanth Menon
169a4c804d OMAP3:SDRC: Cleanup references to SDP
Remove SDP referenced unused defines

Signed-off-by: Nishanth Menon <nm@ti.com>
2009-11-27 16:26:16 -06:00
Sekhar Nori
2819e1365b TI DA8xx: Integrate DA830 EVM support into U-Boot
Integrate DA830 EVM support into U-Boot.

Provides initial support for TI OMAP-L137/DA830 SoC devices on a Spectrum
Digital EVM board. See http://www.spectrumdigital.com/

Signed-off-by: Nick Thompson <nick.thompson@gefanuc.com>
2009-11-27 16:26:16 -06:00
Sekhar Nori
bdc9c6c7f7 TI DA8xx: Add new directory for da830evm board
Add new directory for da830evm board

Provides initial support for TI OMAP-L137/DA830 SoC devices on a Spectrum
Digital EVM board. See http://www.spectrumdigital.com/

Provides:
Initial boot and configuration.
Support for i2c.
UART support (console).

Signed-off-by: Nick Thompson <nick.thompson@gefanuc.com>
2009-11-27 16:26:15 -06:00
Sekhar Nori
91172baf46 TI DA8xx: Add DA8xx cpu functions
Provides initial support for TI OMAP-L1x/DA8xx SoC devices.
See http://www.ti.com

Provides:
Low level initialisation.
System clock API.
Timer control.

Signed-off-by: Nick Thompson <nick.thompson@gefanuc.com>
2009-11-27 16:26:14 -06:00
Nick Thompson
bbed056e55 Add TI DA8xx support: DA8xx includes
Provides initial support for TI OMAP-L1x/DA8xx SoC devices.
See http://www.ti.com

The DA8xx devices are similar to DaVinci devices but have a differing
memory map and updated peripheral versions.

Signed-off-by: Nick Thompson <nick.thompson@gefanuc.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2009-11-27 16:26:14 -06:00
Nick Thompson
ca8480d444 TI Davinci: add a pin multiplexer configuration API
Creates a method allowing pin settings to be logically grouped into data
structure arrays and provides an API to configure the pinmux settings to
enable the relevant pin functions.

Signed-off-by: Nick Thompson <nick.thompson@gefanuc.com>
2009-11-27 16:26:14 -06:00
Nick Thompson
9868a36dfb TI Davinci timer.c: Remove volatiles and memory mapped structures
Remove volatiles and memory mapped structure accesses and replace with
readl and writel macro usage.

Signed-off-by: Nick Thompson <nick.thompson@gefanuc.com>
2009-11-27 16:26:14 -06:00
Grazvydas Ignotas
c90b32739a OMAP3: pandora: fix booting without serial attached
When the board is booted without serial cable attached (which
is how most of them will be used) UART RX is left floating and
sometimes picks noise, which interrupts countdown and enters
U-Boot prompt instead of booting the kernel.

Fix this by setting up internal pullup on UART RX pin. This
does not prevent serial from working as the internal pullup
is weak.

Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
2009-11-27 16:26:14 -06:00
kevin.morfitt@fearnside-systems.co.uk
ac67804fbb Add a unified s3c24x0 header file
This patch adds a unified s3c24x0 cpu header file that selects the header
file for the specific s3c24x0 cpu from the SOC and CPU configs defined in
board config file. This removes the current chain of s3c24-type #ifdef's
from the s3c24x0 code.

Signed-off-by: Kevin Morfitt <kevin.morfitt@fearnside-systems.co.uk>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2009-11-27 16:26:13 -06:00
Seunghyeon Rhee
a59a23d68a S3C6400/SMDK6400: fix stack_setup in start.S
Fix stack_setup to place the stack on the correct address in DRAM
accroding to U-Boot standard and remove conditional compilation by
CONFIG_MEMORY_UPPER_CODE macro that is not necessry. This macro
was introduced and used only by this board for some unclear reason.

The definition of this macro is also removed because it's not
referenced elsewhere.

Signed-off-by: Seunghyeon Rhee <seunghyeon@lpmtec.com>
Tested-by: Minkyu Kang <mk7.kang@samsung.com>
2009-11-27 16:26:13 -06:00
Minkyu Kang
9400322609 s5pc1xx: serial: fix the error check logic
Because of Frame error, Parity error and Overrun error are occured only receive
operation, need to masking when error checking.

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2009-11-27 16:26:13 -06:00
kevin.morfitt@fearnside-systems.co.uk
9ebfdc2022 Clean-up of s3c24x0 header files
Cleans up the s3c24x0 header files:

s4c24x0.h: removes the use of 'volatile' from the S3C24X0_REG8,
S3C24X0_REG16 and S3C24X0_REG32 register typedef's. Registers are always
accessed using the IO accessor functions which cast the register address
as 'volatile' anyway so it isn't required here.

s3c2400.h and s3c2410.h: insert a blank line between the static inline
functions

Signed-off-by: Kevin Morfitt <kevin.morfitt@fearnside-systems.co.uk>
2009-11-27 16:26:13 -06:00
Minkyu Kang
47e801bec3 s3c64xx: move s3c64xx header files to asm-arm/arch-s3c64xx
This patch moves the s3c64xx header files from include/
to include/asm-arm/arch-s3c64xx

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2009-11-27 16:26:13 -06:00
kevin.morfitt@fearnside-systems.co.uk
492fb1fdbc Move s3c24x0 header files to asm-arm/arch-s3c24x0/
This patch moves the s3c24x0 header files from include/ to
include/asm-arm/arch-s3c24x0/.

checkpatch.pl showed 2 errors and 3 warnings. The 2 errors were both due
to a non-UTF8 character in David M?ller's name:

ERROR: Invalid UTF-8, patch and commit message should be encoded in UTF-8
#489: FILE: include/asm-arm/arch-s3c24x0/s3c2410.h:3:
+ * David M?ller ELSOFT AG Switzerland. d.mueller@elsoft.ch

As David's name correctly contains a non-UTF8 character I haven't fixed
these errors.

The 3 warnings were all because of the use of 'volatile' in s3c24x0.h:

WARNING: Use of volatile is usually wrong: see Documentation/volatile-considered-harmful.txt
#673: FILE: include/asm-arm/arch-s3c24x0/s3c24x0.h:35:
+typedef volatile u8	S3C24X0_REG8;
+typedef volatile u16	S3C24X0_REG16;
+typedef volatile u32	S3C24X0_REG32;

I'll fix these errors in another patch.

Tested by running MAKEALL for ARM8 targets and ensuring there were no new
errors or warnings.

Signed-off-by: Kevin Morfitt <kevin.morfitt@fearnside-systems.co.uk>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2009-11-27 16:26:12 -06:00
Tom Rix
2d251ccaa9 ARM Update mach-types
Fetched from http://www.arm.linux.org.uk/developer/machines/download.php
And built with

repo http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm
commit 156171c71a0dc4bce12b4408bb1591f8fe32dc1a

Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
2009-11-27 16:26:12 -06:00
Mark Asselstine
c88ed4cb2e sheevaplug: correct SDRAM address control register
value

The SheevaPlug DevKit is shipped with 4x8 by 1Gb DDR devices in
two banks for a total of 512MB of RAM. Based on this configuration
the existing values for SDRAM address control register are incorrect
and result in random kernel oops as memory is incorrectly accessed
(while for example extracting a large tarball such as a rootfs).
Based on the hardware configuration along with the supporting
documentation from Marvell these are the correct values, as
well this change mimics values previously used in Marvell's own
u-boot git tree for the SheevaPlug.

Other variants of the hardware such as the PogoPlug and TonidoPlug
may have different memory configurations but to properly support
those additional board directories should be maintained or a better
system to support other kwb*.cfg is needed.

Tested on SheevaPlug DevKit.

Signed-off-by: Mark Asselstine <mark.asselstine@windriver.com>
2009-11-27 16:26:12 -06:00
Sandeep Paulraj
9829cabbaa Fix for Void function returning value in sbc35-a9g20
Void function was returning 0 in the m41t94 rtc driver.
This makes it similar to m41t62 rtc driver.

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2009-11-27 16:26:11 -06:00
Tom Rix
d5e2d625c7 ARM Update mach-types.h
From http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm

Commit id 0996391139f43d032335b5360db11da62a2cbb39

Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
2009-11-27 16:26:10 -06:00
Matthias Fuchs
34ddbd171b ppc4xx: Remove autoupdate feature from PLU405 board
The autoupdate feature is not used on PLU405 boards.
So remove it.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Signed-off-by: Stefan Roese <sr@denx.de>
2009-11-25 10:57:33 +01:00
Ira W. Snyder
824d82997f Fix example FIT image source files
The example FIT image source files do not compile with the latest dtc and
mkimage. The following error message is produced:

DTC: dts->dtb  on file "kernel.its"
Error: kernel.its 7:0 - 1:0 syntax error
FATAL ERROR: Unable to parse input tree
./mkimage: Can't read kernel.itb.tmp: Invalid argument

The FIT image source files are missing the "/dts-v1/;" directive at the
beginning of the file. Add the directive to the examples.

Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu>
2009-11-24 23:44:16 +01:00
Mike Frysinger
fd66066ee3 img2srec: use standard types
The img2srec code creates a lot of typedefs with common names.  These
easily clash with system headers that include these typedefs (like mingw).

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-11-24 23:43:18 +01:00
Mike Frysinger
8204e06811 tools: gitignore *.exe binaries
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-11-24 23:42:15 +01:00
Peter Tyser
425d3b666e ppc: Move conditional compilation of kgdb.c to Makefile
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2009-11-24 23:41:11 +01:00
Mike Frysinger
e06ab6546b spi_flash.h: pull in linux/types.h for u## types 2009-11-24 23:40:39 +01:00
Mike Frysinger
0008555f4d bootm: mark local boot_os[] table static
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-11-24 23:40:03 +01:00
Nishanth Menon
a8fa379d47 mkconfig: deny messed up ARCH definition
Refuse to setup a platform if the command line ARCH= is not the same
as the one required for the board. This prevents any user with
prehistoric aliases from messing up their builds.

Reported in thread:
http://old.nabble.com/-U-Boot--Build-breaks-on-some-OMAP3-configs-to26132721.html

Inputs from: Mike Frysinger and Wolfgang Denk:
http://lists.denx.de/pipermail/u-boot/2009-November/063642.html

Cc: Wolfgang Denk <wd@denx.de>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Anand Gadiyar <gadiyar@ti.com>
Cc: Dirk Behme <dirk.behme@googlemail.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2009-11-24 23:37:00 +01:00
Wolfgang Denk
5a1b1f36da Merge branch 'master' of git://git.denx.de/u-boot-net 2009-11-24 23:27:06 +01:00
Wolfgang Denk
7c32dc5bed Merge branch 'master-sync' of git://git.denx.de/u-boot-arm 2009-11-24 23:22:50 +01:00
Wolfgang Denk
2f6f67da1b Merge branch 'next' of git://www.denx.de/git/u-boot-ppc4xx into next 2009-11-24 23:13:06 +01:00
Remy Bohmer
67b96e87da Repair the 'netretry=once' option.
'netretry = once' does the same as 'netretry = yes', because it is not stored
when it was tried once.

Signed-off-by: Remy Bohmer <linux@bohmer.net>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-11-24 14:04:11 -08:00
Remy Bohmer
b25e38fc36 Repair build fail in case CONFIG_PPC=n and CONFIG_FIT=y
Signed-off-by: Remy Bohmer <linux@bohmer.net>
2009-11-24 22:40:20 +01:00
Grazvydas Ignotas
01826abc02 OMAP3: pandora: fix booting without serial attached
When the board is booted without serial cable attached (which
is how most of them will be used) UART RX is left floating and
sometimes picks noise, which interrupts countdown and enters
U-Boot prompt instead of booting the kernel.

Fix this by setting up internal pullup on UART RX pin. This
does not prevent serial from working as the internal pullup
is weak.

Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
2009-11-24 09:04:46 -06:00
Remy Bohmer
41dfd8a603 Add support for CS2 dataflash for Atmel-SPI.
The only missing chipselect line support is CS2, and I need it on
CS2...

Signed-off-by: Remy Bohmer <linux@bohmer.net>
2009-11-23 23:43:37 +01:00
Remy Bohmer
faf36c1437 Fix mingw tools build
mkimage does not build due to missing strtok_r() and getline() implementation

Signed-off-by: Remy Bohmer <linux@bohmer.net>
2009-11-23 23:43:35 +01:00
Remy Bohmer
6a590c5f5f Building of FIT images does not work.
The type is not set for generation of the FIT images, resulting
in no images being created without printing or returning an error

Signed-off-by: Remy Bohmer <linux@bohmer.net>
2009-11-23 23:42:48 +01:00
Renato Andreola
0a7691e820 Nios2: do_boom_linux(): kernel gunzip input data integrity problem due to
missing cache flush.

    Added instruction and data caches flush.

Signed-off-by: Scott McNutt <smcnutt@psyent.com>
2009-11-23 16:45:14 -05:00
Scott McNutt
de03825386 Nios2: Fix compiler warnings in lib_nios2/board.c (unused variables)
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
2009-11-23 16:29:40 -05:00
Scott McNutt
57baa379cf Nios2/Nios: Remove unnecessary (residual) linker Nios command scripts from
the standalone examples.

Signed-off-by: Scott McNutt <smcnutt@psyent.com>
2009-11-23 15:54:25 -05:00
Stefan Roese
eb5eb2b0f7 ppc4xx: Cleanup PPC4xx I2C infrastructure
This patch cleans up the PPC4xx I2C intrastructure:

- Use C struct to describe the I2C registers instead of defines
- Coding style cleanup (braces, whitespace, comments, line length)
- Extract common code from i2c_read() and i2c_write()
- Remove unneeded IIC defines from ppc405.h & ppc440.h

Signed-off-by: Stefan Roese <sr@denx.de>
2009-11-23 16:27:02 +01:00
Stefan Roese
b2f618f215 ppc4xx: Remove some testing code from 4xx_pcie.c
This code got included accidentally.

Signed-off-by: Stefan Roese <sr@denx.de>
2009-11-23 16:25:47 +01:00
Daniel Gorsulowski
4e574c4e2d at91: Extended soft_i2c driver for AT91SAM9263 SoC
While hard_i2c support is not available
(see http://lists.denx.de/pipermail/u-boot/2009-March/049751.html),
this patch enables soft_i2c on AT91SAM9263 SoC.

Signed-off-by: Daniel Gorsulowski <Daniel.Gorsulowski@esd.eu>
2009-11-23 09:26:54 +01:00
Peter Tyser
396fd17338 Add 'true' and 'false' commands
These commands are only enabled when the hush shell is enabled and can
be useful in scripts such as:

while true do
    echo "Booting OS...";
    run $bootcmd;
    echo "Booting OS failed";
    sleep 10;
done

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2009-11-23 00:06:13 +01:00
Peter Tyser
4e1ca93b6b cmd_help: General cleanup
Shorten the overly-verbose help message of 'help' and clean up some
redundant ifdefery while we're at it.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2009-11-23 00:06:12 +01:00
Peter Tyser
6b8f5ad10f command.c: Break commands out to appropriate cmd_*.c files
command.c should contain common code related to commands, not
miscellaneous command implementations.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2009-11-23 00:06:11 +01:00
Mike Frysinger
fcffb680e7 sf: fix stmicro offset setup while erasing
Reported-by: Peter Gombos <gombos@protecta.hu>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-11-22 23:56:36 +01:00
Jason McMullan
d394a77950 sf: new driver for Winbond W25X16/32/64 devices
Signed-off-by: Jason McMullan <jason.mcmullan@gmail.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-11-22 23:54:18 +01:00
Marcel Ziswiler
cada315100 mpc8260: move FDT memory node fixup into common CPU code.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@noser.com>
Tested-by: Heiko Schocher <hs@denx.de>
2009-11-22 23:16:28 +01:00
Po-Yu Chuang
f2cea405f8 Add driver for FTRTC010 real time clock
Signed-off-by: Po-Yu Chuang <ratbert@faraday-tech.com>

Edited commit message.
Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-11-22 22:26:35 +01:00
Mark Jackson
c0356a8801 MIMC200: set default fbmem value
This patch adds a default bootargs "fbmem" value to the
CONFIG_BOOTARGS string for the MIMC200 board.

Signed-off-by: Mark Jackson <mpfj@mimc.co.uk>
2009-11-22 22:07:17 +01:00
Wolfgang Denk
db6ab438d6 Merge branch 'next' of git://git.denx.de/u-boot-nand-flash into next 2009-11-21 23:17:57 +01:00
Wolfgang Denk
77b2517519 Merge branch 'next' of git://www.denx.de/git/u-boot-ppc4xx into next 2009-11-21 23:14:58 +01:00
Sandeep Paulraj
10a5a79912 NAND: Add Support for 4K page size in DaVinci NAND driver
This patch adds support for NAND devices with a page size of
4K in the DaVinci NAND driver. The layout matches the layout that TI uses
for 4K page size NAND devices in the kernel NAND driver.

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2009-11-20 13:15:38 -06:00
Matthias Fuchs
14ce02c881 ppc4xx: Remove unused features from PMC440 board support
This patch shrinks the PMC440 u-boot binary (from next branch)
to fit into 384kB again.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Signed-off-by: Stefan Roese <sr@denx.de>
2009-11-19 11:39:43 +01:00
Matthias Fuchs
629ab99b3b ppc4xx: Remove confusing comment
This is not the sequoia board.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Signed-off-by: Stefan Roese <sr@denx.de>
2009-11-19 11:39:36 +01:00
Stefan Roese
79e2d8df37 ppc4xx: alpr: Remove some not needed commands to make image fit again
The latest changes in the u-boot/next branch increased the size of the
alpr image a bit more. Now it doesn't fit into the 256k reserved for it.
This patch now removes the commands "askenv" and "irq" which are not
needed in the production systems.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Pieter Voorthuijsen <pieter.voorthuijsen@prodrive.nl>
2009-11-19 11:35:52 +01:00
Stefan Roese
6c70049bd1 ppc4xx: Consolidate pci_master_init() function
This patch removes the duplicted implementations of the pci_master_init()
function by introducing a weak default function for it. It can be
overridden by a board specific version.

Signed-off-by: Stefan Roese <sr@denx.de>
2009-11-19 11:35:34 +01:00
Stefan Roese
a760b02031 ppc4xx: Consolidate pci_pre_init() function
This patch removes the duplicted implementations of the pci_pre_init()
function by introducing a weak default function for it. This weak default
has a different implementation for some PPC variants. It can be
overridden by a board specific version.

Signed-off-by: Stefan Roese <sr@denx.de>
2009-11-19 11:35:30 +01:00
Stefan Roese
1095493a5d ppc4xx: Consolidate pci_target_init() function
This patch removes the duplicted implementations of the pci_target_init()
function by introducing a weak default function for it. This weak default
has a different implementation for 440EP(x)/GR(x) PPC's. It can be
overridden by a board specific version (e.g. PMC440, korat).

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Matthias Fuchs <matthias.fuchs@esd.eu>
2009-11-19 11:35:08 +01:00
Hui.Tang
5e1ded558b S3C2410 NAND Flash Add Missing Function
This patch add nand_read_buf() for S3C2410 NAND SPL.
In nand_spl/nand_boot.c, nand_boot() will check nand->select_chip,
so nand->select_chip should also be initialized.

Signed-off-by: Hui.Tang <zetalabs@gmail.com>
2009-11-18 14:30:13 -06:00
Sandeep Paulraj
6cd752f927 NAND: Update read_read_subpage API check
This patch updates a check condition in the NAND driver.
The check condition is similat to what is in linux/next.

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2009-11-18 14:26:40 -06:00
Sandeep Paulraj
bb3e9828e7 NAND:Extending the nand_ecclayout structure
NANDs with page size of lesser than and equal to 2K are
reaching EOL. They are bing replaced with NANDs of
page size 4K and above.
To support this we have to extend the eccpos field

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2009-11-18 14:26:39 -06:00
Matthias Fuchs
3ffc0d61ba ppc4xx: Initialize magnetic coupler on VOM405 boards
This patch fixes an ugly behavior of the IL712 magnetic coupler
as used on VOM405. These parts will remember their last state
over a power cycle which might cause unwanted behavior.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Signed-off-by: Stefan Roese <sr@denx.de>
2009-11-17 13:36:35 +01:00
Matthias Fuchs
be0db3e314 ppc4xx: Initialize magnetic couplers in PLU405
This patch fixes an ugly behavior of the IL712 magnetic couplers
as used on PLU405. These parts will remember their last state
over a power cycle which might cause unwanted behavior.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Signed-off-by: Stefan Roese <sr@denx.de>
2009-11-17 13:25:30 +01:00
Matthias Fuchs
067f54c66a Add minimal SJA1000 header for basic CAN mode
This patch is in preparation for the upcoming PLU405 board fix.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Signed-off-by: Stefan Roese <sr@denx.de>
2009-11-17 13:19:58 +01:00
Dirk Behme
1d2e96de56 OMAP2/3: I2C: Add support for second and third bus
Add support to use second and third I2C bus, too.

Bus 0 is still the default, but by calling i2c_set_bus_num(1/2) before doing
I2C accesses, code can switch to bus 1 and 2, too. Don't forget to switch
back afterwards, then.

Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
2009-11-16 07:25:15 +01:00
Wolfgang Denk
06f43286c6 Merge branch 'master' into next 2009-11-15 23:13:40 +01:00
Wolfgang Denk
3c014f1586 Merge branch 'master' of git://git.denx.de/u-boot-net 2009-11-15 22:50:52 +01:00
Wolfgang Denk
7b18e8c90c Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2009-11-15 22:48:02 +01:00
Wolfgang Denk
b55edd97ce Merge branch 'master-sync' of git://git.denx.de/u-boot-arm 2009-11-15 22:27:16 +01:00
Amul Kumar Saha
c758e947aa ENV Variable support for Flex-OneNAND
Define and use CONFIG_ENV_ADDR_FLEX and CONFIG_ENV_SIZE_FLEX
for storing environment variables.

Signed-off-by: Rohit Hagargundgi <h.rohit@samsung.com>
Signed-off-by: Amul Kumar Saha <amul.saha@samsung.com>
2009-11-13 16:56:18 -06:00
Amul Kumar Saha
cacbe91958 Flex-OneNAND driver support
This patch adds support for Flex-OneNAND devices.

Signed-off-by: Rohit Hagargundgi <h.rohit@samsung.com>
Signed-off-by: Amul Kumar Saha <amul.saha@samsung.com>
2009-11-13 16:56:18 -06:00
Mingkai Hu
35209cbcee fsl_elbc_nand: remove the bbt descriptors relocation fixup
The commit 66372fe2 manually relocated the bbt pattern pointer,
which can be removed by using full relocation.

Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
2009-11-13 16:56:18 -06:00
Mingkai Hu
25643d4da2 ppc/85xx: make boot from NAND full relocation to RAM
Take advantage of the latest full relocation commit of PPC platform
for boot from NAND.

Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
2009-11-13 16:56:17 -06:00
David Brownell
7e86661cd7 NAND: fix "raw" reads with ECC syndrome layouts
The syndrome based page read/write routines store ECC, and possibly other
"OOB" data, right after each chunk of ECC'd data.  With ECC chunk size of
512 bytes and a large page (2KiB) NAND, the layout is:

  data-0 OOB-0 data-1 OOB-1 data-2 OOB-2 data-3 OOB-3 OOB-leftover

Where OOBx is (prepad, ECC, postpad).  However, the current "raw" routines
use a traditional layout -- data OOB, disregarding the prepad and postpad
values -- so when they're used with that type of ECC hardware, those calls
mix up the data and OOB.  Which means, in particular, that bad block
tables won't be found on startup, with data corruption and related chaos
ensuing.

The current syndrome-based drivers in mainline all seem to use one chunk
per page; presumably they haven't noticed such bugs.

Fix this, by adding read/write page_raw_syndrome() routines as siblings of
the existing non-raw routines; "raw" just means to bypass the ECC
computations, not change data and OOB layout.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2009-11-13 16:56:17 -06:00
Sandeep Paulraj
5df3c2b62c NAND: Don't walk past end of oobfree[]
When computing oobavail from the list of free areas in the OOB,
don't assume there will always be an unused slot at the end.
This syncs up with the kernel NAND driver.

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2009-11-13 16:56:16 -06:00
Sandeep Paulraj
18b5a4b43a NAND: Update check condition for nand_read_page_hwecc API
The patch updates the check condition for determining
whether the ECC corrections has failed.
This makes it similar to what is in the kernel NAND driver.

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2009-11-13 16:56:16 -06:00
Sandeep Paulraj
e25ee03962 NAND: Updating comments/explanations in the NAND driver
Patch updates the comments and explanations for
the arguments to various functions.

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2009-11-13 16:56:16 -06:00
Sandeep Paulraj
aad4a28b25 NAND: Subpage shift for ecc_steps equal to 16
This was originally part of Thomas Gleixner's patch for
adding support for 4KiB pages.
This is not part of the U-Boot NAND driver so updating the
driver with this to sync up with the kernel NAND driver.

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2009-11-13 16:56:15 -06:00
Sandeep Paulraj
36e0b98ec8 NAND: Remove commented out code
Patch removes already commented out dead code

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2009-11-13 16:56:15 -06:00
Sandeep Paulraj
4f41e7ea1a NAND: Correct the "chip_shift" calculation
This patch updates the "chip_shift" calculation in the
NAND driver. This is being done to sync up the NAND driver with
the kernel NAND driver.

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2009-11-13 16:56:15 -06:00
Sandeep Paulraj
aaa8eec532 NAND: Update to support 64 bit device size
This patch adds support for NANDs greater than 2 GB.
Patch is based on the MTD NAND driver in the kernel.

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2009-11-13 16:56:14 -06:00
Peter Tyser
581d04f14d cmd_nand: Move conditional compilation to Makefile
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2009-11-13 16:56:14 -06:00
Peter Tyser
9574fd63a9 cmd_nand: Remove duplicate include
Also remove vague, unnecessary comment

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2009-11-13 16:56:13 -06:00
Kumar Gala
cdbdbe65f5 ppc/85xx: Fix how we determine the number of CAM entries
We were incorrectly use the max CAM size as the number of entries in
the array for setting up the addrmap.  We should be using the NENTRY
field which is the low 12-bits of TLB1CFG.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-11-13 09:11:01 -06:00
Mike Rapoport
fbd47b6753 smc911x: make smc911x_initialize return correct value
Make smc911x_initialize return -1 on error and number of interfaces
detected otherwise.

Signed-off-by: Mike Rapoport <mike@compulab.co.il>
Acked-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-11-12 21:25:57 -08:00
Mike Frysinger
c44efcf97b smc911x_eeprom: fix building after smc911x overhaul
When the smc911x driver was converted to NET_MULTI, the smc911x eeprom was
missed.  The config option needed updating as well as overhauling of the
rergister read/write functions.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Tested-by: Mike Rapoport <mike.rapoport@gmail.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-11-12 21:25:56 -08:00
Dave Liu
3ad95deb30 fsl-ddr: Fix the chip-select interleaving issue
commit 1542fbdeec
introduced one new bug to chip-select interleaving.

Single DDR controller also can do the chip-select
interleaving if there is dual-rank or qual-rank DIMMs.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-11-12 08:09:49 -06:00
Wolfgang Denk
4f127980e0 Merge branch 'master' of git://git.denx.de/u-boot-net 2009-11-11 23:10:34 +01:00
Wolfgang Denk
a9e9d69dd8 Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx 2009-11-11 22:58:30 +01:00
javier Martin
651ef90fa6 mxc_fec: avoid free() calls to already freed pointers.
Sometimes, inside NetLoop, eth_halt() is called before eth_init() has
been called. This is harmless except for free() calls to pointers
which have not been allocated yet.

This patch initializes those pointers to NULL and allocates them only
the first time. This way we can get rid of free calls in halt callback.

This has been tested in i.MX27 Litekit board and eldk-4.2 toolchains.

Signed-off-by: Javier Martin <javier.martin@vista-silicon.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-11-11 13:27:09 -08:00
javier Martin
e8f1546a88 mxc_fec: fix some erroneous PHY accesses.
This patch fixes erroneous access to the ethernet PHY which broke the driver.
1. Selector field in the auto-negotiation register must be 0x00001 for
using 802.3, not 0x00000 which is reseved.
2. Access to the PHY address specified by CONFIG_FEC_MXC_PHYADDR, not
0x0 fixed address.

This has been tested in i.MX27 Litekit board and eldk-4.2 toolchains.

Now using proper defines for auto-negotiation register.

Signed-off-by: Javier Martin <javier.martin@vista-silicon.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-11-11 13:27:09 -08:00
Ron Lee
f865fcbbb3 ARM Don't inline weak symbols
------------------------------------------------------------------------

GCC 4.4 complains about this now.

Signed-off-by: Ron Lee <ron@debian.org>
2009-11-11 08:41:01 -06:00
Stefan Roese
efe12bcec5 ppc4xx: Katmai: Add chip_config command
This patch removes the Katmai "bootstrap" command and replaces it
with the now common command "chip_config".

Signed-off-by: Stefan Roese <sr@denx.de>
2009-11-10 15:09:37 +01:00
Stefan Roese
cdaed5dc31 ppc4xx: Switch to I2C bus numer 0 for chip_config command
All currently available 4xx derivats have the I2C bootstrap EEPROM
located on I2C bus number 0. This patch now first sets this bus number,
so that the chip_config command also works for board with multiple
I2C busses, like Katmai.

Signed-off-by: Stefan Roese <sr@denx.de>
2009-11-10 15:09:28 +01:00
Matthias Fuchs
985edaccc4 ppc4xx: Add UBI support to PLU405 boards
-add UBI support
-increase malloc'able memory size
-cleanup MONITOR|FLASH_BASE|LEN constants

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Signed-off-by: Stefan Roese <sr@denx.de>
2009-11-10 15:07:03 +01:00
Ben Warren
d14c7ec2b5 Fix SMC91111 regression: lpd7a40x build failures
Both lpd7a400 and lpd7a404 failed to compile because they had
CONFIG_SMC_USE_IOFUNCS defined:

examples/standalone/smc91111_eeprom.c:388: undefined reference to `SMC_outw'

Also removed an orphaned paren in lpd7a404.h

Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-11-09 21:56:18 -08:00
Ben Warren
1031ae960c SMC91111: Clean up SMC_inx macros on xsengine and xaeniax
This patch fixes the following warnings:

Configuring for xaeniax board...
smc91111_eeprom.c: In function 'print_macaddr':
smc91111_eeprom.c:278: warning: suggest parentheses around + or - in operand of &
smc91111_eeprom.c:281: warning: suggest parentheses around + or - in operand of &
...
Configuring for xsengine board...
smc91111_eeprom.c: In function 'print_macaddr':
smc91111_eeprom.c:278: warning: suggest parentheses around + or - inside shift
smc91111_eeprom.c:281: warning: suggest parentheses around + or - inside shift

Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-11-09 21:55:09 -08:00
Wolfgang Denk
0f365273a6 Merge branch 'master-sync' of git://git.denx.de/u-boot-arm 2009-11-09 22:46:32 +01:00
Ben Warren
830c7b6722 Fix CS8900 regression on impa7 board
The following error was seen on impa7 board, due to its use of a 32-bit bus
on CS8900.
cs8900.c:137:37: error: macro "get_reg_init_bus" passed 2 arguments, but takes just 1

This patch gives the macro the correct number of arguments

Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-11-09 11:43:18 -08:00
Mike Frysinger
e5c5d9e083 clarify eth driver halt/recv steps
The dev->halt() func can be called at any time, and the dev->recv() func
does not need to use NetRxPackets[] when calling NetReceive().

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-11-09 10:40:39 -08:00
Hui.Tang
497ab0eec5 Fix cs8900 dev->priv not init issue
Ensure all CS8900 data structures are assigned before accessing device

Signed-off-by: Hui.Tang <zetalabs@gmail.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-11-09 10:39:36 -08:00
Stefan Roese
4fe5193d46 ppc4xx: 44x_spd_ddr2.c: Fix register macro ECCCR -> ECCES (SDRAM_ECCES)
This error only appears when DEBUG is enabled in this driver. That's why
it went unnoticed till now.

Signed-off-by: Stefan Roese <sr@denx.de>
2009-11-09 13:31:38 +01:00
Stefan Roese
916ed9444d ppc4xx: Canyonlands: Change EBC bus config to drive always (no high-z)
This patch fixes a problem only seen very occasionally on Canyonlands.
The NOR flash interface (CFI driver) doesn't work reliably in all cases.
Erasing and/or programming sometimes doesn't work. Sometimes with
an error message, like "flash not erased" when trying to program an
area that should have just been erased. And sometimes without any error
messages. As mentioned above, this problem was only seen rarely and with
some PLL configuration (CPU speed, EBC speed).

Now I spotted this problem a few times, when running my Canyonlands with
the following setup (chip_config):

1000-nor         - NOR  CPU:1000 PLB: 200 OPB: 100 EBC: 100

Changing the EBC configuration to not release the bus into high
impedance state inbetween the transfers (ATC, DTC and CTC bits set to 1
in EBC0_CFG) seems to fix this problem. I haven't seen any failure
anymore with this patch applied.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: David Mitchell <dmitchell@amcc.com>
Cc: Jeff Mann <MannJ@embeddedplanet.com>
2009-11-09 13:30:19 +01:00
Stefan Roese
56f9b39d1f ppc4xx: Fix NAND booting targets after 4xx linker script consolidation
Somehow I missed the NAND booting targets in the 4xx linker script
consolidation patchset. This patch fixes this issue.

Signed-off-by: Stefan Roese <sr@denx.de>
2009-11-09 13:01:19 +01:00
Stefan Roese
9a81c61249 ppc4xx: Remove duplicated is_pci_host() functions
This patch introduces a weak default function for is_pci_host(),
returning 1. This is the default behaviour, since most boards only
implement PCI host functionality. This weak default can be overridden
by a board specific version if needed.

Signed-off-by: Stefan Roese <sr@denx.de>
2009-11-09 11:27:08 +01:00
Stefan Roese
b0b867462c ppc4xx: Consolidate 4xx PCIe board specific configuration
This patch consolidates the PPC4xx board specific PCIe configuration
code. This way the duplicated code is removed. Boards can implement a
special, non standard behaviour (e.g. number of PCIe slots, etc) by
overriding the weak default functions.

Signed-off-by: Stefan Roese <sr@denx.de>
2009-11-09 11:26:57 +01:00
Remy Bohmer
25793f76bf ARM: Use Linux version for unaligned access code
The asm-arm/unaligned.h includes linux/unaligned/access_ok.h
This file is unsafe to be used on ARM, since it does an unaligned memory
accesses which fails on ARM.

Lookin at Linux the basic difference seems to be the header
"include/asm-arm/unaligned.h". The Linux version of "unaligned.h"
does *not* include "access_ok.h" at all. It includes "le_byteshift.h"
and "be_byteshift.h" instead.

Signed-off-by: Remy Bohmer <linux@bohmer.net>
Signed-off-by: Stefan Roese <sr@denx.de>
--
 include/asm-arm/unaligned.h            |    3 -
 include/linux/unaligned/be_byteshift.h |   70 +++++++++++++++++++++++++++++++++
 include/linux/unaligned/le_byteshift.h |   70 +++++++++++++++++++++++++++++++++
 3 files changed, 142 insertions(+), 1 deletion(-)
 create mode 100644 include/linux/unaligned/be_byteshift.h
 create mode 100644 include/linux/unaligned/le_byteshift.h
2009-11-07 15:56:30 -06:00
Kumar Gala
6d6e7c53d5 ppc/85xx: Fix inclusion of 83xx immap in 85xx builds
The nand_boot_fsl_elbc.c is shared between 83xx & 85xx however we should
not be including the immap_83xx.h when building 85xx.  We can just get
this all from common.h

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-11-04 21:39:07 -06:00
Becky Bruce
107b579c75 86xx: Remove redundant code in initdram
The same code exists both inside an #ifdef and outside of it.
Remove the extra code for all the 86xx boards.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-11-04 21:37:12 -06:00
Ed Swarthout
715d8f7608 fsl_pci_init_port end-point initialization is broken
commit 70ed869e broke fsl pcie end-point initialization.
Returning 0 is not correct.  The function must return the first free
bus number for the next controller.

fsl_pci_init() must still be called and a bus allocated even if the
controller is an end-point.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Acked-by: Vivek Mahajan <vivek.mahajan@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-11-04 09:16:30 -06:00
Kumar Gala
01471d538f Revert "ppc/85xx/pci: fsl_pci_init: pcie agent mode support"
This reverts commit 70ed869ea5.

There isn't any need to modify the API for fsl_pci_init_port to pass the
status of host/agent(end-point) status.  We can determine that
internally to fsl_pci_init_port.  Revert the patch that makes the API
change.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-11-04 09:14:59 -06:00
Stefan Roese
2cd95a25cb ppc4xx: Remove board specific linker scripts from most PPC4xx boards
All these linker scripts can be removed since the new common ppc4xx
linker script should be able to handle all of those boards.

Please test and report problems. Thanks.

Signed-off-by: Stefan Roese <sr@denx.de>
2009-11-02 16:29:04 +01:00
Stefan Roese
4649913ea5 ppc4xx: Add common ppc4xx linker script
This linker script can be used by all PPC4xx platforms. It works for
PPC405 and PPC440 platforms. Boards which need a board specific linker
script can override this default linker script in board/*/config.mk.

Signed-off-by: Stefan Roese <sr@denx.de>
2009-11-02 16:29:04 +01:00
Stefan Roese
b1245dd3c6 ppc4xx: Add custom linker script to board/*/config.mk
These boards have special linker scripts right now. We can't use the
common 4xx linker script here. So overrride the linker script (LDSCRIPT)
in board/*/config.mk and choose the board specific version.

Signed-off-by: Stefan Roese <sr@denx.de>
2009-11-02 16:29:04 +01:00
Stefan Roese
ceaa62a6f0 ppc4xx: Fix problems in some ppc4xx board Makefiles
Some 4xx Makefiles didn't add $(SOBJ) to their board library. This was
no till now problem, since those boards included this object (init.o
most of the time) directly from their linker scripts. This patch clean
this up, so that all objects are now collected in the board library. This
is in preparation for the upcoming PPC4xx linker script consolidation.

Signed-off-by: Stefan Roese <sr@denx.de>
2009-11-02 16:29:03 +01:00
Stefan Roese
a0ff1f129a ppc4xx: sc3: Remove unreferenced external declarations from sc3.h
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>
2009-11-02 16:29:03 +01:00
Stefan Roese
7ec1fedda6 mkconfig: Create board directory (CONFIG_BOARDDIR) in include/config.h
This patch extends the mkconfig script to automatically create a define
for the board directory in include/config.h:

#define CONFIG_BOARDDIR board/amcc/canyonlands

This is needed for the upcoming PPC4xx linker script consolidation,
where the PPC440 platforms need to include a board specific file in
the common linker script.

Signed-off-by: Stefan Roese <sr@denx.de>
2009-11-02 16:29:03 +01:00
Dave Liu
ff88229549 ppc/85xx: Fix misc L2 cache enabling bug
We need loop-check the flash clear lock and enable bit for L2 cache.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-10-31 10:59:52 -05:00
Wolfgang Grandegger
cd12f615e4 mpc52xx: add support for the IPEK01 board
This patch adds support for the board IPEK01 based on the MPC5200.
The Futjitsu Lime graphics controller is configured in 16 bpp mode.

Signed-off-by: Wolfgang Grandegger <wg@denx.de>
2009-10-31 16:14:35 +01:00
Wolfgang Denk
d793b6bb1e Merge branch 'next' of git://git.denx.de/u-boot-video into next 2009-10-31 16:13:18 +01:00
Wolfgang Denk
b91b8f74fe Merge branch 'master' of /home/wd/git/u-boot/custodians 2009-10-31 16:03:08 +01:00
Wolfgang Grandegger
229b6dce67 video: mb862xx: add option VIDEO_FB_16BPP_WORD_SWAP for IPEK01
In 16 bpp mode, the new IPEK01 board only requires swapping of D16 words
for D32 accesses due to the diffferent connecting to the GDC bus. This
patch introduces the configuration option VIDEO_FB_16BPP_WORD_SWAP,
which should be set for all board using the mb862xx in 16 bpp mode. For
the IPEK01, VIDEO_FB_16BPP_PIXEL_SWAP should not be set.

Signed-off-by: Wolfgang Grandegger <wg@denx.de>
2009-10-31 12:17:40 +01:00
Anatolij Gustschin
5d16ca8710 video: mb862xx: add option CONFIG_VIDEO_MB862xx_ACCEL for 32bpp mode
The new IPEK01 board can use the 32 bpp mode for the Lime graphics
controller. For this mode, video accelaration does not work. This patch
makes the accelaration configurable via CONFIG_VIDEO_MB862xx_ACCEL,
which is enabled for the lwmon5 and the socrates board for backward
compatibility.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Wolfgang Grandegger <wg@denx.de>
2009-10-31 12:16:29 +01:00
Wolfgang Grandegger
c28d3bbe96 video: mb862xx: improve board-specific Lime configuration
To avoid board-specific code accessing the mb862xx registers directly,
the public function mb862xx_probe() has been introduced. Furthermore,
the "Change of Clock Frequency" and "Set Memory I/F Mode" registers
are now defined by CONFIG_SYS_MB862xx_CCF and CONFIG_SYS_MB862xx__MMR,
respectively. The BSPs for the socrates and lwmon5 boards have been
adapted accordingly.

Signed-off-by: Wolfgang Grandegger <wg@denx.de>
2009-10-31 12:13:28 +01:00
Valentin Yakovenkov
08ea550eef new PCA9564 i2c bridge driver
Signed-off-by: Valentin Yakovenkov <yakovenkov@niistt.ru>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-10-30 15:10:58 +01:00
Mike Frysinger
08a1c6258c Blackfin: TWI/I2C: implement bus speed get/set functions
While we're here, improve the speed calculation a bit to match the HRM.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-10-30 15:10:58 +01:00
Mike Frysinger
3814ea4f00 Blackfin: TWI/I2C: add timeout to transfer
The current transfer code relies on ctrlc() to abort transfers, but this
requires user interactivity.  Naturalize the process with a timeout.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-10-30 15:10:58 +01:00
Nobuhiro Iwamatsu
59434fe243 sh: Update lowlevel_init.S of espt-giga
There was the point that did not use write macro.
Change to write macro.

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2009-10-30 10:20:16 +09:00
Nobuhiro Iwamatsu
f1cae1969d sh: Move some defs to convince 'pcrel too far'
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Takashi Yoshii <yoshii.takashi@gmail.com>
2009-10-30 10:02:00 +09:00
Nobuhiro Iwamatsu
0f9eaf4b32 sh: Remove malloc_bin_reloc from lib_sh, lib_nios2 and lib_nios.
By "arm/microblaze/nios/nios2/sh: Remove relocation fixups"
(commit: 0630535e2d062dd73c1ceca5c6125c86d1127a49", doesn't need
malloc_bin_reloc function. This commit remove this.

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2009-10-30 08:41:15 +09:00
Ben Warren
0775437293 Fix DM9000 MAC address handling
Proper behavior is to pull MAC address from NVRAM in the initialization() an
stuff it in dev->address, then program the device from dev->address in
the init() function.

Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-10-29 10:06:34 -07:00
Wolfgang Denk
98d92d8c9f sbc8349: fix incorrect comment
The comment for the BR0_PRELIM port size initialization incorrectly
stated 32 bit, while it's actually 16 bit. The code is correct.

Reported-by: Guenter Koellner <guenter.koellner@nsn.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-10-28 22:07:56 +01:00
Wolfgang Denk
f2b4bc04d6 Merge branch 'master' of git://git.denx.de/u-boot-cfi-flash 2009-10-28 21:50:09 +01:00
Wolfgang Denk
d187fcaaa2 Merge branch 'master' of git://git.denx.de/u-boot-sparc 2009-10-28 21:48:40 +01:00
Sandeep Paulraj
a38f85e180 Fix Compliation warning for TNY-A9260 and TNY-A9G20
The patch fixes a compilation warning by defining
CONFIG_SYS_64BIT_VSPRINTF in the config file

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2009-10-28 21:47:08 +01:00
Sandeep Paulraj
264e42ee54 Fix Compliation warning for SBC35-A9G20 board
The patch fixes a compilation warning by defining
CONFIG_SYS_64BIT_VSPRINTF in the config file

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2009-10-28 21:47:07 +01:00
Eric Millbrandt
353462f6ff galaxy5200: Add default environment variables
Extend bootdelay to 10 seconds.  Set boot retry time to 120 seconds and use
reset to retry.  Define default bootcommand and bootargs for production.

Signed-off-by: Eric Millbrandt <emillbrandt@dekaresearch.com>
2009-10-28 21:46:21 +01:00
Stefan Roese
fa36ae790e cfi: Add weak default function for flash_cmd_reset()
Currently the CFI driver issues both AMD and Intel reset commands.
This is because the driver doesn't know yet which chips are connected.
This dual reset seems to cause problems with the M29W128G chips as
reported by Richard Retanubun. This patch now introduces a weak default
function for the CFI reset command, still with both resets. This can
be overridden by a board specific version if necessary.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Richard Retanubun <RichardRetanubun@ruggedcom.com>
2009-10-28 11:34:14 +01:00
Wolfgang Denk
4946775c6d Coding Style cleanup; update CHANGELOG, prepare -rc1
Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-10-28 00:49:47 +01:00
Peter Tyser
246c69225c Add 'editenv' command
The editenv command can be used to edit an environment variable.
Editing an environment variable is useful when one wants to tweak an
existing variable, for example fix a typo or change the baudrate in the
'bootargs' environment variable.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2009-10-27 20:58:25 +01:00
Peter Tyser
b0fa8e5063 setenv(): Delete 0-length environment variables
Previously setenv() would only delete an environment variable if it
was passed a NULL string pointer as a value.  It should also delete an
environment variable when it encounters a valid string pointer of
0-length.

This change/fix is generally useful and is necessary for the upcoming
"editenv" command.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2009-10-27 20:58:25 +01:00
Peter Tyser
ecc5500ee4 readline(): Add ability to modify a string buffer
If the 'buf' parameter is a non-0-length string, its contents will be
edited.  Previously, the initial contents of 'buf' were ignored and the
user entered its contents from scratch.

This change is necessary to support the upcoming "editenv" command but
could also be used for future commands which require a user to modify
an existing string.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2009-10-27 20:58:25 +01:00
Peter Tyser
f923943843 cread_line(): Remove unused variables
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2009-10-27 20:58:25 +01:00
Peter Tyser
e491a71e57 Check for NULL prompt in readline_into_buffer()
Previously, passing readline() or readline_into_buffer() a NULL 'prompt'
parameter would result in puts() printing garbage when
CONFIG_CMDLINE_EDITING was enabled.

Note that no board currently triggers this bug.  Enabling
CONFIG_CMDLINE_EDITING on some boards (eg bab7xx) would result in
the bug appearing.  This change is only intended to prevent someone
from running into this issue in the future.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2009-10-27 20:58:25 +01:00
Wolfgang Denk
16d1c10783 drivers/net/phy/miiphybb.c: fix warning: no newline at end of file
Add missing newline.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Luigi Mantellini <luigi.mantellini@idf-hit.com>
Cc: Ben Warren <biggerbadderben@gmail.com>
2009-10-27 20:58:24 +01:00
Wolfgang Denk
98cecb610f Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2009-10-27 20:56:31 +01:00
Wolfgang Denk
a747a7f310 Revert "env: only build env_embedded and envcrc when needed"
Breaks building on many boards, and no really clean fix available yet.

This reverts commit 6dab6add2d.
2009-10-27 20:46:31 +01:00
Anton Vorontsov
3fca803759 mpc85xx: Configure QE USB for MPC8569E-MDS boards
Setup QE pin multiplexing for USB function, configure needed BCSRs
and add some fdt fixups.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-10-27 10:04:17 -05:00
Anton Vorontsov
14809b6c21 mpc85xx: Configure QE UART for MPC8569E-MDS boards
To make QE UART usable by Linux we should setup pin multiplexing
and turn UCC2 Ethernet node into UCC2 QE UART node.

Also, QE UART is mutually exclusive with UART0, so we can't enable
it if eSDHC is in 4-bits mode on pilot boards, or if it's a prototype
board with eSDHC in 1- or 4-bits mode.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-10-27 10:04:11 -05:00
Anton Vorontsov
70d665b1d2 mpc85xx: Setup QE pinmux for SPI Flash on MPC8569E-MDS boards
SPI Flash (M25P40) is connected to the SPI1 bus, we need a few
qe_iop entries to actually enable SPI1 on these boards.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-10-27 09:44:40 -05:00
Anton Vorontsov
65dec3b459 mpc85xx: Setup SRIO memory region LAW for MPC8569E-MDS boards
This patch sets memory window for Serial RapidIO on MPC8569E-MDS
boards.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-10-27 09:44:37 -05:00
Anton Vorontsov
a29155e122 mpc85xx: Add eLBC NAND support for MPC8569E-MDS boards
Simply add some defines, and adjust TLBe setup to include some
space for eLBC NAND.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-10-27 09:44:32 -05:00
Anton Vorontsov
7f52ed5ef1 mpc85xx: Add eSDHC support for MPC8569E-MDS boards
eSDHC is mutually exlusive with UART0 (in 4-bits mode) and I2C2
(in 1-bit mode). When eSDHC is used, we should switch u-boot console to
UART1, and make the proper device-tree fixups.

Because of an erratum in prototype boards it is impossible to use eSDHC
without disabling UART0 (which makes it quite easy to 'brick' the board
by simply issung 'setenv hwconfig esdhc', and not able to interact with
U-Boot anylonger).

So, but default we assume that the board is a prototype, which is a most
safe assumption. There is no way to determine board revision from a
register, so we use hwconfig.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-10-27 09:36:48 -05:00
Peter Tyser
48618126f7 xpedite5370: Enable multi-core support
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-10-27 09:34:58 -05:00
Peter Tyser
5ccd29c367 85xx: MP Boot Page Translation update
This change has 3 goals:
- Have secondary cores be released into spin loops at their 'true'
  address in SDRAM.  Previously, secondary cores were put into spin
  loops in the 0xfffffxxx address range which required that boot page
  translation was always enabled while cores were in their spin loops.

- Allow the TLB window that the primary core uses to access the
  secondary cores boot page to be placed at any address.  Previously, a
  TLB window at 0xfffff000 was always used to access the seconary cores'
  boot page.  This TLB address requirement overlapped with other
  peripherals on some boards (eg XPedite5370).  By default, the boot
  page TLB will still use the 0xfffffxxx address range, but this can be
  overridden on a board-by-board basis by defining a custom
  CONFIG_BPTR_VIRT_ADDR.  Note that the TLB used to map the boot page
  remains in use while U-Boot executes.  Previously it was only
  temporarily used, then restored to its initial value.

- Allow Boot Page Translation to be disabled on bootup.  Previously,
  Boot Page Translation was always left enabled after secondary cores
  were brought out of reset.  This caused the 0xfffffxxx address range
  to somewhat "magically" be translated to an address in SDRAM.  Some
  boards may not want this oddity in their memory map, so defining
  CONFIG_MPC8xxx_DISABLE_BPTR will turn off Boot Page Translation after
  the secondary cores are initialized.

These changes are only applicable to 85xx boards with CONFIG_MP defined.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-10-27 09:34:57 -05:00
Vivek Mahajan
70ed869ea5 ppc/85xx/pci: fsl_pci_init: pcie agent mode support
Originally written by Jason Jin and Mingkai Hu for mpc8536.

When QorIQ based board is configured as a PCIe agent, then unlock/enable
inbound PCI configuration cycles and init a 4K inbound memory window;
so that a PCIe host can access the PCIe agents SDRAM at address 0x0

* Supported in fsl_pci_init_port() after adding pcie_ep as a param
* Revamped copyright in drivers/pci/fsl_pci_init.c
* Mods in 85xx based board specific pci init after this change

Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-10-27 09:33:51 -05:00
Poonam Aggrwal
273a28ad9e 85xx/p1_p2_rdb: Fixing DDR configuration for 800MHz data rate
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-10-27 09:12:36 -05:00
Poonam Aggrwal
924024c396 85xx/p1_p2rdb: Fix crash while configuring 32 bit DDR i/f for P1020RDB.
The data being modified was in NOR flash which caused the crash.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-10-27 09:12:32 -05:00
Sergey Mironov
2c0c58b92d Fix bug in jumptable call stubs for SPARC.
Signed-off-by: Sergey Mironov <ierton@gmail.com>
Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
2009-10-27 14:09:40 +01:00
Anton Vorontsov
3e303f748c fdt_support: Add multi-serial support for stdout fixup
Currently fdt_fixup_stdout() is using hard-coded CONFIG_CONS_INDEX
constant. With multi-serial support, the CONS_INDEX may no longer
represent actual console, so we should try to extract port number
from the current stdio device name instead of always hard-coding the
constant value.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Acked-by: Gerald Van Baren <vanbaren@cideas.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-10-26 21:35:50 -05:00
Leon Woestenberg
da0e5f7ee8 ppc/85xx: Fix crashes due to generation of SPE instruction
U-Boot crashed on the last instruction:

int parse_stream_outer(struct in_str *inp, int flag)
{
effa4784:       94 21 ff 38     stwu    r1,-200(r1)
effa4788:       7c 08 02 a6     mflr    r0
effa478c:       42 9f 00 05     bcl-    20,4*cr7+so,effa4790 <parse_stream_outer+0xc>
effa4790:       7d 80 00 26     mfcr    r12
effa4794:       13 c1 b3 21     evstdd  r30,176(r1)

...which is a  SPE instruction, although -mno-spe was used.

tmp/cross/ppce500v2/bin/powerpc-angstrom-linux-gnuspe-gcc --version
powerpc-angstrom-linux-gnuspe-gcc (GCC) 4.3.3

Seems to be a known issue (since 2008-04?!)

Googled some, turns out this patch/workaround works for me on MPC8536DS.

See http://gcc.gnu.org/ml/gcc-patches/2008-04/msg00311.html for more info

Signed-off-by: Leon Woestenberg <leon@sidebranch.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-10-26 21:35:45 -05:00
Dave Liu
654ea1f318 ppc/85xx: Make L2 support more robust
According the user manual, we need loop-check the L2 enable bit set.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-10-26 21:24:51 -05:00
Kumar Gala
613ad28c3d ppc/85xx: Fix compiler warning in nand_spl/.../p1_p2_rdb/nand_boot.c
nand_boot.c: In function 'board_init_f':
nand_boot.c:44: warning: 'sys_clk' may be used uninitialized in this function

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-10-26 21:21:25 -05:00
Kumar Gala
e8967d96a0 ppc/85xx: Fix building NAND_SPL out of tree
We need to source files to exist in the O=<FOO> nand_spl dir when
we build out of tree.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-10-26 21:19:22 -05:00
Matthias Fuchs
f3ee25859e License cleanup: Fix license header for some esd display configurations
These files were autogenerated by EPSON configuration tools.
This patch replaces the autogenerated file headers by the GPL
license notice.

This change is done with the explicit permission
of Epson Research & Development / IC Software Development.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
2009-10-24 22:54:29 +02:00
Mike Frysinger
4166ee58d3 sf: add GPL-2 license info
Some of the new spi flash files were missing explicit license lines.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
CC: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2009-10-24 22:44:18 +02:00
Kumar Gala
d535a49300 fdt: Fix fdt padding issue for initrd mem_rsv
Its possible that we end up with a device tree that happens to be a
particular size that after we call fdt_resize() we don't have any
space left for the initrd mem_rsv.

Fix this be adding a second mem_rsv into the size calculation.  We
had one to cover the fdt itself and we have the potential of adding
a second for the initrd.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Gerald Van Baren <vanbaren@cideas.com>
2009-10-24 22:39:51 +02:00
Wolfgang Denk
0ac59d0c07 Merge branch 'master' of /home/wd/git/u-boot/custodians 2009-10-24 22:26:42 +02:00
Wolfgang Denk
922754cc82 Merge branch 'master-sync' of git://git.denx.de/u-boot-arm 2009-10-24 22:26:09 +02:00
Wolfgang Denk
09cc0487b8 Merge branch 'master' of /home/wd/git/u-boot/custodians 2009-10-24 22:25:11 +02:00
Wolfgang Denk
4ee6326815 Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx 2009-10-24 22:25:08 +02:00
Wolfgang Denk
a89805f324 Merge branch 'master' of /home/wd/git/u-boot/custodians 2009-10-24 22:19:54 +02:00
Wolfgang Denk
62506ae140 Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx 2009-10-24 22:19:46 +02:00
Wolfgang Denk
25ee856e44 Merge branch 'master' of /home/wd/git/u-boot/custodians 2009-10-24 22:16:22 +02:00
Steve Sakoman
4bc3d2afb3 ARM: OMAP3: Refactors the SM911x driver
Move the test up in the function to not hang on systems without ethernet.

Signed-off-by: Steve Sakoman <sakoman@gmail.com>
Acked-by: Ben Warren <biggerbadderben@gmail.com>
2009-10-24 09:55:25 -05:00
Minkyu Kang
f380737478 s5pc1xx: SMDKC100: fix compile warnings
fix the following compile warnings
warning: dereferencing type-punned pointer will break strict-aliasing rules

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2009-10-24 09:55:25 -05:00
Simon Kagstrom
8003c361de arm926ejs: 8-byte align stack to avoid LDRD/STRD problems
U-boot for Marvell Kirkwood boards no longer work after the EABI changes
introduced in commit f772acf8a5. This
turns out to be caused by a stack alignment issue. The armv5te
instructions ldrd/strd instructions require 8-byte alignment to work
properly (otherwise undefined behavior).

Tested on an OpenRD base board, where both printouts and ubifs stuff now
works.

Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
2009-10-24 09:55:25 -05:00
Tom Rix
e63e5904b4 TI OMAP3 SDP3430: Initial Support
Start of support of
Texas Instruments Software Development Platform(SDP)
for OMAP3430 - SDP3430

Highlights of this platform are:
Flash Memory devices:
	Sibley NOR, Micron 8bit NAND and OneNAND
Connectivity:
	3 UARTs and expanded 4 UART ports + IrDA
	Ethernet, USB
Other peripherals:
	TWL5030 PMIC+Audio+Keypad
	VGA display
Expansion ports:
	Memory devices plugin boards (PISMO)
	Connectivity board for GPS,WLAN etc.
Completely configurable boot sequence and device mapping
etc.

Support default jumpering and:
 - UART1/ttyS0 console(legacy sdp3430 u-boot)
 - UART3/ttyS2 console (matching other boards,
		 and SDP HW docs)
 - Ethernet
 - mmc0
 - NOR boot

Currently the UART1 is enabled by default.  for
compatibility with other OMAP3 u-boot platforms,
enable the #define of CONSOLE_J9.

Conflicts:

	Makefile

Fixed the conflict with smdkc100_config by moving omap_sdp3430_config
to it is alphabetically sorted location above zoom1.

Signed-off-by: David Brownell <david-b@pacbell.net>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
2009-10-24 09:55:25 -05:00
Sandeep Paulraj
a4474ff862 TI DaVinci: Adding Copyright for DM365 EVM
Forgot to add Copyright while submitting the patch.
This patch adds the copyright.

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2009-10-24 09:55:24 -05:00
Sandeep Paulraj
11b0102218 TI DaVinci: Fix DM6467 EVM Compilation Warning
Due to new TI boards being added to U-Boot, the hardware.h
is getting very messy. The warning being fixed is due to
the EMIF addresses being redefined.

The long term solution(after 2009.11) to this is to
have SOC specific header files.

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2009-10-24 09:55:24 -05:00
Sandeep Paulraj
fac1ef4ba6 TI DaVinci: DM355 Leopard: Fix compilation warning
We get a compliation warning when we enable the NAND driver
for DM355 leopard. The waring we get is that we have
an implicit declaration of davinci_nand_init.

It is fixed by including the asm/arch/nand_defs.h header file

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2009-10-24 09:55:24 -05:00
Nishanth Menon
f8a812aa65 TI OMAP3: make gpmc_config as const
gpmc_config should not be a variant as it is board specific
hence make it a const parameter

Fixes issues identified by Dirk:
- build issue for zoom2
- warnings for all other OMAP3 platforms using nand/onenand etc

Signed-off-by: Nishanth Menon <nm@ti.com>
2009-10-24 09:55:24 -05:00
Stefan Roese
cfc2587462 ppc4xx: Sequoia: Add chip_config command
This patch removes the Sequoia "bootstrap" command and replaces it
with the now common command "chip_config".

Please note that the patches with the dynamic PCI sync clock
configuration have to be applied, before this one should go in.
This is because Sequoia has 2 different bootstrap EEPROMs, and
the old bootstrap command configured different values depending
on the detected PCI async clock (33 vs. 66MHz). With the PCI sync
clock patches, this is not necessary anymore. The PCI sync clock
will be configured correctly on-the-fly now.

Signed-off-by: Stefan Roese <sr@denx.de>
2009-10-23 16:05:11 +02:00
Stefan Roese
c85b583970 ppc4xx: Yosemite/Yellowstone: Check and reconfigure the PCI sync clock
This patch now uses the 440EP(x)/GR(x) function to check and dynamically
reconfigure the PCI sync clock.

Signed-off-by: Stefan Roese <sr@denx.de>
2009-10-23 16:05:02 +02:00
Stefan Roese
23c51a2d63 ppc4xx: Sequoia/Rainer: Check and reconfigure the PCI sync clock
This patch now uses the 440EP(x)/GR(x) function to check and dynamically
reconfigure the PCI sync clock.

Signed-off-by: Stefan Roese <sr@denx.de>
2009-10-23 16:04:54 +02:00
Stefan Roese
08c6a26284 ppc4xx: Print PCI synchronous clock frequency upon bootup
Some 4xx variants (e.g. 440EP(x)/GR(x)) have an internal
synchronous PCI clock. Knowledge about the currently configured
value might be helpful. So let's print it out upon bootup.

Signed-off-by: Stefan Roese <sr@denx.de>
2009-10-23 16:04:45 +02:00
Stefan Roese
5e47f9535f ppc4xx: Add function to check and dynamically change PCI sync clock
PPC440EP(x)/PPC440GR(x):
In asynchronous PCI mode, the synchronous PCI clock must meet
certain requirements. The following equation describes the
relationship that must be maintained between the asynchronous PCI
clock and synchronous PCI clock. Select an appropriate PCI:PLB
ratio to maintain the relationship:

AsyncPCIClk - 1MHz <= SyncPCIclock <= (2 * AsyncPCIClk) - 1MHz

This patch now adds a function to check and reconfigure the sync
PCI clock to meet this requirement. This is in preparation for
some AMCC boards (Sequoia/Rainier and Yosemite/Yellowstone) using this
function to not violate the PCI clocking rules.

Signed-off-by: Stefan Roese <sr@denx.de>
2009-10-23 16:04:36 +02:00
Stefan Roese
92b8964bed ppc4xx: Update flash size in reg property of the NOR flash node
Till now only the ranges in the ebc node are updated with the values
currently configured in the PPC4xx EBC controller. With this patch now
the NOR flash size is updated in the device tree blob as well. This is
done by scanning the compatible nodes "cfi-flash" and "jedec-flash"
for the correct chip select number.

This size fixup is enabled for all AMCC eval board right now. Other
4xx boards may want to enable it as well, if this problem with multiple
NOR FLASH sizes exists.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
2009-10-23 15:56:32 +02:00
Stefan Roese
30d45c0d3e fdt: Add fdt_fixup_nor_flash_size() to fixup NOR FLASH size in dtb
This function can be used to update the size in the "reg" property
of the NOR FLASH device nodes. This is necessary for boards with
non-fixed NOR FLASH sizes.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Gerald Van Baren <vanbaren@cideas.com>
Acked-by: Wolfgang Denk <wd@denx.de>
2009-10-23 15:55:23 +02:00
Wolfgang Denk
76706cb86b cpu/ppc4xx/fdt.c: avoid strcpy() to constant string
strcpy() was iused with the target address being a pointer to a
constant string, which potentially is read-only. Use a (writable)
array of characters instead.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2009-10-23 15:50:22 +02:00
Wolfgang Denk
0e1ac98119 cpu/ppc4xx/fdt.c: avoid strcpy() to constant string
strcpy() was iused with the target address being a pointer to a
constant string, which potentially is read-only. Use a (writable)
array of characters instead.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-10-20 23:07:04 +02:00
Daniel Mack
c55096c084 smc911x: add support for LAN9220
Signed-off-by: Daniel Mack <daniel@caiaq.de>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-10-19 10:08:44 -07:00
Mike Frysinger
f67066b6b0 envcrc: check return value of fwrite()
Newer toolchains will often complain about unchecked fwrite():
	envcrc.c:117: warning: ignoring return value of `fwrite, declared
		with attribute warn_unused_result

So check the return value to silence the warnings.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-10-19 10:36:31 +02:00
Wolfgang Denk
efd988ebaa mcc200: fix build error
Fix compile error:
include/configs/mcc200.h:401:6: error: #elif with no expression

Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-10-19 09:18:57 +02:00
Nishanth Menon
4e0539d269 OMAP3: fix warnings when NAND/ONENAND is not used
Fix build warnings by putting specific used variables
under required #ifdefs for removing:
mem.c:227: warning: unused variable 'f_sec'
mem.c:226: warning: unused variable 'f_off'
mem.c:225: warning: unused variable 'size'
mem.c:224: warning: unused variable 'base'
mem.c:222: warning: unused variable 'gpmc_config'

Signed-off-by: Nishanth Menon <nm@ti.com>
2009-10-18 16:52:54 -05:00
Nishanth Menon
73db0c71da OMAP3: export enable_gpmc_cs_config to board files
Export enable_gpmc_cs_config into common header to
prevent warning:

warning: implicit declaration of function 'enable_gpmc_cs_config'

Signed-off-by: Nishanth Menon <nm@ti.com>
2009-10-18 16:52:53 -05:00
Tom Rix
96a27c6dc2 Zoom2 Fix serial gpmc setup
The offset to the chip select is incorrect.

The change 187af954cf,

omap3: embedd gpmc_cs into gpmc config struct

introduced a problem with the serial gpmc setup.

This patch reverts the chip select to its previous value.

The symptoms of this problem are that the Zoom2
currently hangs.

This was run tested on Zoom2.

Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
2009-10-18 16:52:53 -05:00
Sandeep Paulraj
64d945abe8 TI DaVinci Sonata: Add Config option for 64 bit Support
Adding the CONFIG_SYS_64BIT_VSPRINTF fot the DM644x based Sonata
Without this option enabled while performing NAND operations we will get
wrong diagnostic messages.
Example if the MTD NAND driver find a bad block while erasing from
a certain address, it will say bad block skipped at 0x00000000.

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2009-10-18 16:52:53 -05:00
Sandeep Paulraj
54aa603d2c TI DaVinci DVEVM: Add Config option for 64 bit Support
Adding the CONFIG_SYS_64BIT_VSPRINTF in the DVEVM config.
Without this option enabled while performing NAND operations we will get
wrong diagnostic messages.
Example if the MTD NAND driver find a bad block while erasing from
a certain address, it will say bad block skipped at 0x00000000.

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2009-10-18 16:52:53 -05:00
Sandeep Paulraj
b8d0aa0c78 TI DaVinci DM365: Add Config option for 64 bit Support
Adding the CONFIG_SYS_64BIT_VSPRINTF in the DM365 EVM config.
Without this option enabled while performing NAND operations we will get
wrong diagnostic messages.
Example if the MTD NAND driver find a bad block while erasing from
a certain address, it will say bad block skipped at 0x00000000.

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2009-10-18 16:52:53 -05:00
Sandeep Paulraj
86a725b9c8 TI DaVinci DM355: Add Config option for 64 bit Support
Adding the CONFIG_SYS_64BIT_VSPRINTF in the DM355 EVM config.
Without this option enabled while performing NAND operations we will get
wrong diagnostic messages.
Example if the MTD NAND driver find a bad block while erasing from
a certain address, it will say bad block skipped at 0x00000000.

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2009-10-18 16:52:53 -05:00
Sandeep Paulraj
9c44ddccb6 TI: OMAP3: Remove SZ_xx references
This patch removes dependency on the sizes.h header file
and removes all references to SZ_xx.

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2009-10-18 16:52:52 -05:00
Steve Sakoman
13d2cb988f OMAP3: Update Overo and Beagle environment
Update default environment to support new kernel DSS2 subsystem and
simplify rootfs type and location changes.

Signed-off-by: Steve Sakoman <sakoman@gmail.com>
Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
2009-10-18 16:52:52 -05:00
Sandeep Paulraj
c73607c552 TI DaVinci: Maintainer for DM355 and DM365 EVM
Adding entries to the MAINTAINERS directory for the
DM355 and DM365 EVM.

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2009-10-18 16:42:22 -05:00
Sandeep Paulraj
5df65cf56a TI: DaVinci: DM355 Leopard board support
This patch adds support for the leopard board which is
based on the DM355 SOC.

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2009-10-18 16:42:21 -05:00
Sandeep Paulraj
6ab176d709 TI DaVinci DM646x: Adding initial support for DM6467 EVM
This patch adds the initial support for DM6467 EVM.
Other features like NET and NAND support will be added as follow up patches.

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2009-10-18 16:42:21 -05:00
Sandeep Paulraj
d884f64a7b TI DaVinci DM365: Fix Compilation warning for DM365 EVM
This patch fixes a compilation warning while compiling
the DM365 EVM.

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2009-10-18 16:42:21 -05:00
Sandeep Paulraj
6fe5e87be4 TI DaVinci DM355: Fix Compilation warning for DM355 EVM
This patch fixes a compilation warning while compiling
the DM355 EVM.

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2009-10-18 16:42:21 -05:00
Eric Benard
513bbe1b17 AT91 CPUAT91 Fix compiler warning
This change fixes the compiler warning

main.c: In function 'abortboot':
main.c:122: warning: too few arguments for format

Signed-off-by: Eric Benard <eric@eukrea.com>
Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
2009-10-18 16:40:15 -05:00
Eric Benard
b1e81f701d AT91 CPU9260 CPU9G20 Fix compile warnings
This change fixes the compiler warning

nand_util.c:45:2: warning: #warning Please define CONFIG_SYS_64BIT_VSPRINTF
  for correct output!

Signed-off-by: Eric Benard <eric@eukrea.com>
Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
2009-10-18 16:39:01 -05:00
Eric Benard
94d50c527a AT91 CPU9260 Fix machine ID when using a CPU9G20.
Signed-off-by: Eric Benard <eric@eukrea.com>
Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
2009-10-18 16:38:16 -05:00
Alessandro Rubini
8c0a92c8f4 lcd: remove '#if 0' 32-bit scroll, now memcpy does it
Signed-off-by: Alessandro Rubini <rubini@unipv.it>
Acked-by: Andrea Gallo <andrea.gallo@stericsson.com>
2009-10-18 23:10:43 +02:00
Alessandro Rubini
e3ea948d45 lib_generic memset: fill one word at a time if possible
If the destination is aligned, fill ulong values until possible.
Then fill remaining part by byte.

Signed-off-by: Alessandro Rubini <rubini@unipv.it>
Acked-by: Andrea Gallo <andrea.gallo@stericsson.com>
Acked-by: Mike Frysinger <vapier@gentoo.org>
2009-10-18 23:10:40 +02:00
Alessandro Rubini
ecd830b863 lib_generic memcpy: copy one word at a time if possible
If source and destination are aligned, this copies ulong values
until possible, trailing part is copied by byte. Thanks for the details
to Wolfgang Denk, Mike Frysinger, Peter Tyser, Chris Moore.

Signed-off-by: Alessandro Rubini <rubini@unipv.it>
Acked-by: Andrea Gallo <andrea.gallo@stericsson.com>
Acked-by: Mike Frysinger <vapier@gentoo.org>
2009-10-18 23:10:37 +02:00
Alessandro Rubini
9c5586aa19 setenv: do console redirection even if previously unset
If "stdout" is not previously set, doing "setenv stdout lcd" had no
effect, since console redirection only worked if the environment
variable was already set; the second time you run setenv it worked.
Most default environments lack stdin/out/err definitions, so I'm sure
I'm not alone with this problem.

This patch simply moves a block of code out of a conditional, to do
the same work even if the variable was previously unset.

Signed-off-by: Alessandro Rubini <rubini@unipv.it>
Acked-by: Andrea Gallo <andrea.gallo@stericsson.com>
2009-10-18 23:07:03 +02:00
Martha Stan
c9ee39972a mpc512x: fix System Clock Control constants for USB1 & USB2
Signer-off-by: Martha Stan <mmarx@silicontkx.com>
2009-10-18 23:04:05 +02:00
Paul Gortmaker
87b22b7787 mem_mtest: fix error reporting, allow escape with ^C
The basic memtest function tries to watch for ^C after each
pattern pass as an escape mechanism, but if things are horribly
wrong, we'll be stuck in an inner loop flooding the console with
error messages and never check for ^C.  To make matters worse,
if the user waits for all the error messages to complete, we
then incorrectly report the test passed without errors.

Adding a check for ^C after any error is printed will give
the end user an escape mechanism from a console flood without
slowing down the overall test speed on a slow processor.

Also, the more extensive memtest quit after just a single error,
which is inconsistent with the normal memtest, and not useful if
if you are doing dynamic environmental impact testing, such as
heating/cooling etc.

Both tests now track the error count and report it properly
at test completion.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Acked-by: Mike Frysinger <vapier@gentoo.org>
2009-10-18 22:57:06 +02:00
Mike Frysinger
9f4a420663 new default shortcut to config & build a board
The majority of the time that I build things in U-Boot, I want to just
build for the board.  I don't make board config tweaks after selecting the
board.  So add a new pattern rule that allows people to combine two steps
in one go:
	`make foo_config && make` => `make foo`

This shouldn't conflict with any existing make rules as the pattern rule
is used only the rule doesn't already exist.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-10-18 22:56:06 +02:00
Mike Frysinger
6dab6add2d env: only build env_embedded and envcrc when needed
The env code is protected by the ENV_IS_EMBEDDED define, so attempting to
compile the code when this isn't defined is pointless.  Now that the env
headers have unified around CONFIG_ENV_IS_EMBEDDED, convert the build
system to only build the env objects when this is enabled.  And now that
the env code is conditionally compiled, we can drop the source code checks.

For people who want to extract the environment manually, add a new option
CONFIG_BUILD_ENVCRC that only enables the envcrc utility.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-10-18 22:53:18 +02:00
Daniel Mack
78f4ca7976 part_dos: check status flags of partitions
Only read partitions which have 0x00 or 0x80 set in their status field.
All others are invalid.

Signed-off-by: Daniel Mack <daniel@caiaq.de>
2009-10-18 22:50:21 +02:00
Eric Millbrandt
45def0ab9d galaxy5200: change cs1 configuration
Correct the chip select configuration for the nand flash chip select.

Signed-off-by: Eric Millbrandt <emillbrandt@dekaresearch.com>
2009-10-18 22:46:31 +02:00
Niklaus Giger
7936b51165 Cleanup: use constant
Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
2009-10-18 22:41:33 +02:00
Kim Phillips
7120c88810 mpc83xx: mpc8313 - handle erratum IPIC1 (TSEC IRQ number swappage)
mpc8313e erratum IPIC1 swapped TSEC interrupt ID numbers on rev. 1
h/w (see AN3545).  The base device tree in use has rev. 1 ID numbers,
so if on Rev. 2 (and higher) h/w, we fix them up here.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Reviewed-by: Roland Lezuo <roland.lezuo@chello.at>
2009-10-16 17:08:35 -05:00
Anton Vorontsov
91525c6715 mpc85xx: Fix booting on various boards
commit 0e870980a6 ("8xxx: Removed
CONFIG_NUM_CPUS from 85xx/86xx") breaks U-Boot on various boards,
namely the ones that call get_sys_info() from board_early_init_f().

get_sys_info() calls cpu_numcores(), which depends on probecpu()
being called before. But probecpu() is called after board_early_init_f(),
and so cpu_numcores() returns random values, which in turn crashes
get_sys_info().

To fix the issue we place probecpu() before board_early_init_f()
in an initialization sequence.

Booting on the following boards should be revived now:
 mpc8540ads
 mpc8541cds
 mpc8548cds
 mpc8555cds
 mpc8560ads
 mpc8568mds
 mpc8569mds
 and maybe more.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-10-16 10:21:56 -05:00
Paul Gortmaker
26df6aa991 mpc86xx: delete unused MPC86xx_DDR_SDRAM_CLK_CNTL define
This is an orphaned legacy leftover that is just polluting
the config file namespace.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-10-16 10:21:39 -05:00
Dipen Dudhat
fad15096e3 ppc/P1_P2_RDB: On-chip BootROM support
On Chip BootROM support for P1 and P2 series RDB platforms.

This patch is derived from latest On Chip BootROM support on MPC8536DS

Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-10-16 10:21:39 -05:00
Dipen Dudhat
f7780ec977 ppc/P1_P2_RDB: NAND Boot Support
NAND Boot support for P1 and P2 series RDB platforms.

This patch is derived from NAND Boot support on MPC8536DS.

Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-10-16 10:21:39 -05:00
Paul Gortmaker
d11823ca3c mpc8xxx: improve LAW error messages when setting up DDR
When setting up the LAWs for the DDR, if there was an error,
you got the not-so-helpful error text "ERROR" and nothing
else.  Not only is it non-informative, but it is also
pretty frustrating trying to grep for "ERROR" in the source.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-10-16 10:21:39 -05:00
Paul Gortmaker
a9946e3fc7 sbc8641d: fix LAW so board doesn't hang on DDR init
All versions between now and since this commit:

  commit bd76729bcb
  MPC86xx: set CONFIG_MAX_MEM_MAPPED to 2G by default

will fail to allow the SBC8641D to get past DDR init, because the
LAW config was overlapping.  Eventually this board will do SPD
EEPROM config, but for now this gets the board working again.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-10-16 10:21:39 -05:00
Wolfgang Denk
9efe379a0e Merge branch 'master' of git://git.denx.de/u-boot-blackfin 2009-10-15 22:13:37 +02:00
kevin.morfitt@fearnside-systems.co.uk
3d1988ab47 Clean-up of s3c24x0 nand driver
This patch re-formats the arm920t s3c24x0 nand driver in preparation for changes
to add support for the Embest SBC2440-II Board.

The changes are as follows:
- re-indent the code using Lindent
- make sure register layouts are defined using a C struct
- replace the upper-case typedef'ed C struct names with lower case
non-typedef'ed ones
- make sure registers are accessed using the proper accessor functions
- run checkpatch.pl and fix any error reports

It assumes the following patch has been applied first:
- [U-Boot][PATCH-ARM] CONFIG_SYS_HZ fix for ARM902T S3C24X0 Boards, 05/09/2009
 - patches 1/4, 2/4 and 3/4 of this series

Tested on an Embest SBC2440-II Board with local u-boot patches as I don't have
any s3c2400 or s3c2410 boards but need this patch applying before I can submit
patches for the SBC2440-II Board. Also, temporarily modified sbc2410x, smdk2400,
smdk2410 and trab configs to use the mtd nand driver (which isn't used by any
board at the moment), ran MAKEALL for all ARM9 targets and no new warnings or
errors were found.

Signed-off-by: Kevin Morfitt <kevin.morfitt@fearnside-systems.co.uk>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2009-10-13 21:13:57 -05:00
kevin.morfitt@fearnside-systems.co.uk
eb0ae7f549 Clean-up of s3c24x0 drivers excluding nand driver
This patch re-formats the arm920t s3c24x0 driver files, excluding the nand
driver, in preparation for changes to add support for the Embest SBC2440-II Board.

The changes are as follows:
- re-indent the code using Lindent
- make sure register layouts are defined using a C struct
- replace the upper-case typedef'ed C struct names with lower case
  non-typedef'ed ones
- make sure registers are accessed using the proper accessor functions
- run checkpatch.pl and fix any error reports

It assumes the following patch has been applied first:
- [U-Boot][PATCH-ARM] CONFIG_SYS_HZ fix for ARM902T S3C24X0 Boards, 05/09/2009
- patches 1/4 and 2/4 of this series

Tested on an Embest SBC2440-II Board with local u-boot patches as I don't have
any s3c2400 or s3c2410 boards but need this patch applying before I can submit
patches for the SBC2440-II Board. Also, temporarily modified sbc2410x, smdk2400,
smdk2410 and trab configs to use the mtd nand driver (which isn't used by any
board at the moment), ran MAKEALL for all ARM9 targets and no new warnings or
errors were found.

Signed-off-by: Kevin Morfitt <kevin.morfitt@fearnside-systems.co.uk>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2009-10-13 21:13:56 -05:00
kevin.morfitt@fearnside-systems.co.uk
8250d0bae8 Clean-up of s3c24x0 header files
This patch re-formats the arm920t s3c24x0 header files in preparation for
changes to add support for the Embest SBC2440-II Board.

The changes are as follows:
- re-indent the code using Lindent
- make sure register layouts are defined using a C struct
- replace the upper-case typedef'ed C struct names with lower case
non-typedef'ed ones
- make sure registers are accessed using the proper accessor functions
- run checkpatch.pl and fix any error reports

It assumes the following patch has been applied first:
- [U-Boot][PATCH-ARM] CONFIG_SYS_HZ fix for ARM902T S3C24X0 Boards, 05/09/2009
- patch 1/4 of this series

Tested on an Embest SBC2440-II Board with local u-boot patches as I don't have
any s3c2400 or s3c2410 boards but need this patch applying before I can submit
patches for the SBC2440-II Board. Also, temporarily modified sbc2410x, smdk2400,
smdk2410 and trab configs to use the mtd nand driver (which isn't used by any
board at the moment), ran MAKEALL for all ARM9 targets and no new warnings or
errors were found.

Signed-off-by: Kevin Morfitt <kevin.morfitt@fearnside-systems.co.uk>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2009-10-13 21:13:56 -05:00
kevin.morfitt@fearnside-systems.co.uk
d67cce2dda Clean-up of cpu_arm920t and cpu_arm920t_s3c24x0 code
This patch re-formats the code in cpu/arm920t and cpu/arm920t/23c24x0 in
preparation for changes to add support for the Embest SBC2440-II Board.

The changes are as follows:
- re-indent the code using Lindent
- make sure register layouts are defined using a C struct
- replace the upper-case typedef'ed C struct names with lower case
  non-typedef'ed ones
- make sure registers are accessed using the proper accessor functions
- run checkpatch.pl and fix any error reports

It assumes the following patch has been applied first:
- [U-Boot][PATCH-ARM] CONFIG_SYS_HZ fix for ARM902T S3C24X0 Boards, 05/09/2009

Tested on an Embest SBC2440-II Board with local u-boot patches as I don't have
any s3c2400 or s3c2410 boards but need this patch applying before I can submit
patches for the SBC2440-II Board. Also, ran MAKEALL for all ARM9 targets and no
new warnings or errors were found.

Signed-off-by: Kevin Morfitt <kevin.morfitt@fearnside-systems.co.uk>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2009-10-13 21:13:56 -05:00
kevin.morfitt@fearnside-systems.co.uk
cd85662b34 CONFIG_SYS_HZ fix for ARM902T S3C24X0 Boards
This sets CONFIG_SYS_HZ to 1000 for all boards that use the s3c2400 and
s3c2410 cpu's which fixes various problems such as the timeouts in tftp being
too short.

Tested on an Embest SBC2440-II Board with local u-boot patches as I don't
have any s3c2400 or s3c2410 boards but need this patch applying before I can
submit patches for the SBC2440-II Board. Also, ran MAKEALL for all ARM9 targets
and no new warnings or errors were found.

It was originally submitted on 21/06/2009 but didn't get into the 2009.08
release, and Jean-Pierre made one comment on the original patch (see
http://lists.denx.de/pipermail/u-boot/2009-July/055470.html). I've made two
changes to the original patch:
- it's been re-based to the current release
- I've re-named get_timer_raw() to get_ticks() in response to Jean-Pierre's comment

This affects the sbc2410, smdk2400, smdk2410 and trab boards. I've copied it
directly to the maintainers of all except the sbc2410 which doesn't have an
entry in MAINTAINERS.

Signed-off-by: Kevin Morfitt <kmorfitt@aselaptop-1.localdomain>
Tested-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2009-10-13 21:13:55 -05:00
Minkyu Kang
8bc4ee9e82 s5pc1xx: add support SMDKC100 board
Adds new board SMDKC100 that uses s5pc100 SoC

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: HeungJun, Kim <riverful.kim@samsung.com>
2009-10-13 21:13:55 -05:00
Minkyu Kang
dd2c9e6a3b s5pc1xx: support serial driver
This patch includes the serial driver for s5pc1xx.
s5pc1xx uart driver needs own register setting and clock configuration.
So, need to special driver.

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2009-10-13 21:13:55 -05:00
Minkyu Kang
4678d674f0 s5pc1xx: support onenand driver
This patch includes the onenand driver for s5pc100

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
2009-10-13 21:13:55 -05:00
Minkyu Kang
399e5ae0d0 s5pc1xx: support Samsung s5pc1xx SoC
This patch adds support for the Samsung s5pc100 and s5pc110
SoCs. The s5pc1xx SoC is an ARM Cortex A8 processor.

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: HeungJun, Kim <riverful.kim@samsung.com>
2009-10-13 21:13:55 -05:00
Mike Frysinger
d087d19a99 Blackfin: drop MAC display at boot
The default Blackfin boot would display the MAC address for the first NIC,
but this relies on the environment.  The current net multi stack no longer
writes the default hardware settings to the environment, so most of the
time the display shows all zeros.  This can be pretty confusing and really
doesn't add anything useful, so just drop it.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-10-13 22:00:29 -04:00
Mike Frysinger
1f003cf473 Blackfin: reset watchdog in udelay()
All arches apparently should reset the watchdog in their udelay loop as
noted on the mailing list recently:

  > A comment in flash_status_check() suggests that udelay() is
  > expected to reset the watchdog, but I can't find any architecture
  > where it does.

  If this is missing in other architectures, it should be fixed at the
  root cause, i. e. in udelay() or in the respective support routines.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-10-13 21:48:52 -04:00
Mike Frysinger
370ec73455 Blackfin: Remove relocation fixups
Blackfin pieces like commit 0630535e2d.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-10-13 21:48:52 -04:00
Daniel Gorsulowski
a380279b2a at91: Update MEESC board support
This patch implements several updates:
-disable CONFIG_ENV_OVERWRITE
-add new hardware style variants and set the arch numbers appropriate
-pass the serial# and hardware revision to the kernel
-removed unused macros from include/configs/meesc.h
-fixed multiline comment style

Signed-off-by: Daniel Gorsulowski <Daniel.Gorsulowski@esd.eu>
2009-10-13 06:17:38 -05:00
Simon Kagstrom
9df20ce211 arm: Correct build with CONFIG_SYS_HUSH_PARSER set
FLAG_PARSE_SEMICOLON is not defined without hush.h, so include that.

Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
2009-10-13 06:17:38 -05:00
Olof Johansson
df3826262c TI: OMAP3: Overo Tobi ethernet support
Add setup for ethernet on Tobi, allowing kernel/ramdisk to be loaded
over tftp.

This also refactors the smc911x driver to allow for detecting when the
chip is missing. I.e. the detect_chip() function is called earlier and
will abort gracefully when the Chip ID read returns all 1's.

Signed-off-by: Olof Johansson <olof@lixom.net>
Acked-by: Dirk Behme <dirk.behme@googlemail.com>
Acked-by: Ben Warren <biggerbadderben@gmail.com>
2009-10-13 06:17:38 -05:00
Olof Johansson
2a6cc97b91 SMC911X: Add chip auto detection
Refactor the smc911x driver to allow for detecting when the chip is missing.
I.e. the detect_chip() function is called earlier and will abort gracefully
when the Chip ID read returns all 1's.

Signed-off-by: Olof Johansson <olof@lixom.net>
Acked-by: Dirk Behme <dirk.behme@googlemail.com>
Acked-by: Ben Warren <biggerbadderben@gmail.com>
2009-10-13 06:17:37 -05:00
Tom Rix
0297ec7e2a TI OMAP3 Use arm init sequence to initialize i2c
This changes fixes an early i2c error.

It appears that I2C is working because once a read or write
error is detected, the omap24xx_i2c driver calls i2c_init
inside its error handling check.

While it is ok to attempt error handling this way, the boards
must not depend on this side effect to initialize it's i2c.

Instead of explicitly calling i2c_init for every board, use
the generic arm initialization in lib_arm/board.c. By defining
the config variable CONFIG_HARD_I2C, the omap3 i2c initialization
is included in the init_sequence table.

Run tested on Beagle.
Compile tested on the omap3's

Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
Acked-by: Dirk Behme <dirk.behme@googlemail.com>
2009-10-13 06:17:37 -05:00
Sandeep Paulraj
4df30f3bb7 TI: DaVinci DM365: Enabling network Support on DM365 EVM
This patch enables EMAC on the DM365 EVM.

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Acked-by: Tom Rix <Tom.Rix@windriver.com>
2009-10-13 06:17:37 -05:00
Sandeep Paulraj
00e1665a3c TI: DaVinci: GPIO header file and definitions
Some DaVinci SOC's use GPIOs to enable EMAC and DM9000.
This patch adds some definitions for GPIO registers and also adds
structures for GPIO.
A separate header file is being added so that in future we
can have a DaVinci GPIO driver similer to OMAP.

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Acked-by: Tom Rix <Tom.Rix@windriver.com>
2009-10-13 06:17:37 -05:00
Sandeep Paulraj
95ae803afb TI: DaVinci DM646x: Update flag used to represent DM646x SOC's
In the DaVinci specific code, we use both CONFIG_SOC_DM646X and
CONFIG_SOC_DM646x to represent DM646x specific code.
This patch changes occurrences of CONFIG_SOC_DM646x to
CONFIG_SOC_DM646X. This is because for DM644x series of SOCs we use
the flag CONFIG_SOC_DM644X. We want some uniformity.

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Acked-by: Tom Rix <Tom.Rix@windriver.com>
2009-10-13 06:17:37 -05:00
Olof Johansson
fc9165fdb3 OMAP3: Clean up whitespace in mux configs
Switch from space-based indentation to tab-based in mux configs, as pointed
out by WD at:

http://lists.denx.de/pipermail/u-boot/2009-September/061241.html

Nothing but whitespace changes in this patch (diff -w gives no output).

Signed-off-by: Olof Johansson <olof@lixom.net>
2009-10-13 06:17:36 -05:00
Dirk Behme
9de0212bd7 OMAP3 MMC: Fix warning dereferencing type-punned pointer
Fix warning
Dereferencing type-punned pointer will break strict-aliasing rules

Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
CC: Steve Sakoman <sakoman@gmail.com>
Acked-by: Tom Rix <Tom.Rix@windriver.com>
2009-10-13 06:17:36 -05:00
Simon Kagstrom
e92daeb5c2 Support for the OpenRD base board
The implementation is borrowed from the sheevaplug board and the Marvell
1.1.4 code. Unsupported (or untested) is the SD card, PCIe and SATA.

Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
2009-10-13 06:17:36 -05:00
Prafulla Wadaskar
a62e78fc44 Kirkwood: mv88f6281gtw_ge: Add kwbimage build support
This patch adds kwbimage configuration file
(used by mkimage utility)
to support u-boot.kwb target on mv88f6281gtw_ge board.

To create Kirkwood boot image to be flashed on SPI Flash,
additional parameter u-boot.kwb need to be passed during make.

Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
2009-10-13 06:17:36 -05:00
Prafulla Wadaskar
5bc7cbc15b Kirkwood: rd6281a: Add kwbimage build support
This patch adds kwbimage configuration file
(used by mkimage utility)
to support u-boot.kwb target on rd6281a platform.

To create Kirkwood boot image to be flashed on NAND,
additional parameter u-boot.kwb need to be passed during make.

Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
2009-10-13 06:17:36 -05:00
Tom Rix
23b80982a0 Add support for Eukrea CPU9260/CPU9G20 SBC
these boards are built around Atmel's AT91SAM9260/9G20 and have
up to 64MB of NOR flash, up to 128MB of SDRAM, up to 2GB of NAND
and include a 10/100 Ethernet PHY in RMII mode.

Signed-off-by: Eric Benard <eric@eukrea.com>
Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
2009-10-13 06:17:35 -05:00
Tom Rix
d8380c9d35 Add support for Eukrea CPUAT91 SBC
CPUAT91 is built around Atmel's AT91RM9200 and has up to 16MB of NOR
flash, up to 128MB of SDRAM, and includes a Micrel KS8721 PHY in RMII
mode.

Signed-off-by: Eric Benard <eric@eukrea.com>
Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
2009-10-13 06:17:35 -05:00
Sandeep Paulraj
eb95aa15e6 TI: DaVinci DM365: Minor config cleanup
The DM365 config was using the 'CONFIG_CMD_SAVEENV' flag.
This is already included when we include the
config_cmd_default.h header file. So this flag is removed.
Also another flag to enable NAND functions was being
enabled incorrectly.

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2009-10-13 06:17:35 -05:00
Sandeep Paulraj
5d783c1ffd TI DaVinci DM365: Removing header file which does not exist
The DaVinci DM365 EVM board specific code was including a header file
which does not exist. So removing this header file.

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2009-10-13 06:17:35 -05:00
Sandeep Paulraj
409ec37bd8 TI DaVinci: DM355: Config Cleanup and Update
This patch does the following
1) Enables the NAND driver which is now available.
2) Enables the 'CONFIG_MTD_DEVICE' as without this the
compilation will fail
3) We now have a safe place to store environment and defines
an offset where this can be stored. This offset value is such that it is after
the location where U-Boot is flashed using TI flash utilities.
4) Enables Bootdelay
5) Increases malloc() arena size. Manufacturers are coming out with
NAND with large blocks sizes of upto 1 MiB. It has been noticed that
as the block size of the NAND used is increased, if this particular
value is not increased, the NAND driver will output out of memory
errors.

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2009-10-13 06:17:34 -05:00
Sandeep Paulraj
7908c97a10 TI DaVinci: DM646x: Initial Support for DM646x SOC
DM646x is an SOC from TI which has both an ARM and a DSP.
There are multiple variants of the SOC mainly dealing with different
core speeds.
This patch adds the initial framework for the DM646x SOC.

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2009-10-13 06:17:34 -05:00
Sandeep Paulraj
5d0f53624c TI DaVinci: DM6446: Fix Compilation error in NAND mode
The Default mode that is built for the Davinci DVEVM happens
to be the NOR mode.
When we want to build for the NAND mode, we get a compilation
error. This is overcome by defining the CONFIG_MTD_DEVICE
flag in the NAND mode.
The image built for NAND mode was successfully tested on the
DaVinci DM6446 EVM.

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2009-10-13 06:17:33 -05:00
Tom Rix
7a2aa8b681 OMAP3 Move cache routine to cache.S
v7_flush_dcache_all, because it depends on omap ROM code is not
generic.  Rename the function to 'invalidate_dcache' and move it
to the omap cpu directory.

Collect the other omap cache routines l2_cache_enable and
l2_cache_disable with invalide_dcache into cache.S.  This
means removing the old cache.c file that contained l2_cache_enable
and l2_cache_disable.

The conversion from cache.c to cache.S was done most through
disassembling the uboot binary.  The only significant change was
to change the comparision for the return of get_cpu_rev from

   cmp	r0, #0
   beq	earlier_than_label

Which was lost information to

   cmp	r0, #CPU_3XX_ES20
   blt	earlier_than_label

The paths through the enable routine were verified by
adding an infinite loop and seeing the hang.  Then
removing the infinite loop and seeing it continue.

The disable routine is similar enough that it was not
tested with this method.

Run tested by cold booting from nand on beagle and zoom1.
Compile tested on MAKEALL arm.

Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
2009-10-13 06:17:33 -05:00
Sandeep Paulraj
a16df2c111 TI DaVinci: Remove references to SZ_xx
This patch removes the asm/sizes.h header file from being
included in the DaVinci SOC configs.
References to SZ_xx have been replaced by appropriate
bit shifted values.

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Acked-by: Wolfgang Denk <wd@denx.de>
2009-10-13 06:17:33 -05:00
Wolfgang Denk
14abfe361b Merge branch 'master' of /home/wd/git/u-boot/custodians 2009-10-12 23:40:27 +02:00
Ed Swarthout
285870f753 Leave x86emu op code tables in default section
Forcing the tables into got2 caused extra relocation when using -mrelocatable.
This patch requires any board defining CONFIG_BIOSEMU to use -mrelocatable.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Acked-by: Jin Zhengxiong <Jason.Jin@freescale.com>
2009-10-12 23:34:06 +02:00
Luigi 'Comio' Mantellini
be2254423b Update all board to support new bbmiiphy driver (with multibus support)
Signed-off-by: Luigi 'Comio' Mantellini <luigi.mantellini@idf-hit.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-10-10 23:16:55 -07:00
Luigi 'Comio' Mantellini
310cecb8cc Add bb_miiphy_init call before any ethernet bring-up code.
Signed-off-by: Luigi 'Comio' Mantellini <luigi.mantellini@idf-hit.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-10-10 23:16:53 -07:00
Luigi 'Comio' Mantellini
4ba31ab33a Rewrite the miiphybb (Bit-banged MII bus driver) in order to support an arbitrary number of mii buses.
This feature is useful when your board uses different mii buses for different
phys and all (or a part) of these buses are implemented via bit-banging mode.

The driver requires that the following macros should be defined into the board
configuration file:

CONFIG_BITBANGMII       - Enable the miiphybb driver
CONFIG_BITBANGMII_MULTI - Enable the multi bus support

If the CONFIG_BITBANGMII_MULTI is not defined, the board's config file needs
to define at least the following macros:

MII_INIT      - Generic code to enable the MII bus (optional)
MDIO_DECLARE  - Declaration needed to access to the MDIO pin (optional)
MDIO_ACTIVE   - Activate the MDIO pin as out pin
MDIO_TRISTATE - Activate the MDIO pin as input/tristate pin
MDIO_READ     - Read the MDIO pin
MDIO(v)       - Write v on the MDIO pin
MDC_DECLARE   - Declaration needed to access to the MDC pin (optional)
MDC(v)        - Write v on the MDC pin

The previous macros make the driver compatible with the previous version
(that didn't support the multi-bus).

When the CONFIG_BITBANGMII_MULTI is also defined, the board code needs to fill
the bb_miiphy_buses[] array with a record for each required bus and declare
the bb_miiphy_buses_num variable with the number of mii buses.
The record (struct bb_miiphy_bus) has the following fields/callbacks (see
miiphy.h for details):

char name[]            - The symbolic name that must be equal to the MII bus
                         registered name
int (*init)()          - Initialization function called at startup time (just
                         before the Ethernet initialization)
int (*mdio_active)()   - Activate the MDIO pin as output
int (*mdio_tristate)() - Activate the MDIO pin as input/tristate pin
int (*set_mdio)()      - Write the MDIO pin
int (*get_mdio)()      - Read the MDIO pin
int (*set_mdc)()       - Write the MDC pin
int (*delay)()         - Delay function
void *priv             - Private data used by board specific code

The board code will look like:

struct bb_miiphy_bus bb_miiphy_buses[] = {
 { .name = miibus#1, .init = b1_init, .mdio_active = b1_mdio_active, ... },
 { .name = miibus#2, .init = b2_init, .mdio_active = b2_mdio_active, ... },
 ...
int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
                          sizeof(bb_miiphy_buses[0]);

Signed-off-by: Luigi 'Comio' Mantellini <luigi.mantellini@idf-hit.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-10-10 23:16:53 -07:00
Paul Gortmaker
efaf6f1bf6 mpc83xx: cosmetic comment update relating to SPD EEPROM
commit 6d0f6bcf33 did the big
rename of CFG_ macros to CONFIG_SYS macros.  But it missed
a couple of instances within comments.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-10-09 14:09:15 -05:00
Wolfgang Denk
cd77dd109c Merge branch 'reloc' 2009-10-09 00:03:18 +02:00
Joakim Tjernlund
afc3ba0fc4 relocation: Do not relocate NULL pointers.
NULL is an absolute value and should not be relocated.
After this correction code like:
 void weak_fun(void) __attribute__((weak));
 printf("weak_fun:%p\n", weak_fun);
will still print null after relocation.

Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
2009-10-08 09:33:36 +02:00
Peter Tyser
3beb40c247 85xx: Ensure BSS segment isn't linked at address 0
When U-Boot is relocated from flash to RAM pointers are modified
accordingly.  However, pointers initialzed with NULL values should not
be modified so that they maintain their intended NULL value.  If the
BSS segment is linked at address 0 its address will not be
updated as necessary during relocation.

This is a temporary workaround.  The end goal is to add support to
U-Boot to dynamically locate the BSS at an arbitrary address at
runtime.  When the ability to fixup the BSS inteligently is
added, this workaround can be removed and the 85xx link script
can put the BSS at a fixed address at link time.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2009-10-08 00:33:47 +02:00
Detlev Zundel
95c44ec485 tqm5200: Correct comment and code in post_hotkeys_pressed.
This fixes the code and the comment according to the original intent of
doing an intensive memory test when PSC6_3 is pulled low on the STK52xx.
Notably PORT_CONFIG will be overridden with this correct code now,
so beware.

The original code only worked by coincidence depending on the PORT_CONFIG
setting from the header file.  The new code was tested to ensure that the
(undocumented) memory test still works on the STK52x.

Signed-off-by: Detlev Zundel <dzu@denx.de>
CC: Martin Krause <Martin.Krause@tqs.de>

Minor white-space cleanup.
Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-10-08 00:31:23 +02:00
Wolfgang Denk
da01f53404 mpc512x: fix fixed_sdram() init code.
Commit 054197ba and later fixes used an array to initialize some of
the MDDRC parameters; however, the use of an array turned out to be a
bad idea as it was not possible to correlate structure entries to
array indices in readable and reliable way. Now we use a struct
instead, which makes this self-explanatory.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-10-08 00:23:12 +02:00
Niklaus Giger
dbcc357166 ppc4xx: respect 80-chars per line in ppc*.h files
After running checkstyle.pl on the three previous patches I noted that in
the *.h files there were a lot of long lines. This patch solves this problem.

Signed-off-by: Niklaus Giger <niklaus.giger@member.fsf.org>
Signed-off-by: Stefan Roese <sr@denx.de>
2009-10-07 09:15:30 +02:00
Niklaus Giger
78d2a64137 ppc4xx: Rework cmd reginfo
The command "reginfo" got an overhaul for the ppc4xx. It dumps all the
relevant HW configuration registers (address, symbolic name, content).
This allows to easily detect errors in *.h files and changes in the HW
configuration.

Signed-off-by: Niklaus Giger <niklaus.giger@member.fsf.org>
Signed-off-by: Stefan Roese <sr@denx.de>
2009-10-07 09:15:26 +02:00
Niklaus Giger
ddc922ff2c ppc_4xx: Apply new HW register names
Modify all existing *.c files to use the new register names
as seen in the AMCC manuals.

Signed-off-by: Niklaus Giger <niklaus.giger@member.fsf.org>
Signed-off-by: Stefan Roese <sr@denx.de>
2009-10-07 09:15:20 +02:00
Niklaus Giger
f80e61dcfe ppc4xx: Cleanup some HW register names
Here you find all the changes in the include directory for new register names
and adapting other ones to the names used by AMCC in their manuals, e.g.
For 440EPx/GRPPC440EPx/GRX, Revision 1.15 – September 22, 2008
For PPC405GP Embedded Processor, Revision 1.02 – March 22, 2006

Signed-off-by: Niklaus Giger <niklaus.giger@member.fsf.org>
Signed-off-by: Stefan Roese <sr@denx.de>
2009-10-07 09:15:13 +02:00
Stefan Roese
56f14818f6 ppc4xx: Add PPC405EX(r) Rev D support
Unfortunately some Rev D PPC405EX/405EXr PVR's are identical with older
405EX(r) parts. Here a list:

0x12911475 - 405EX Rev D with Security *and* 405EX Rev A/B witout Sec
0x12911473 - 405EX Rev D without Security *and* 405EXr Rev A/B with Sec

Since there are only a few older parts in the field, this patch now
changes the PVR's above to represent the new Rev D versions.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Phong Vo" <pvo@amcc.com>
2009-10-07 09:14:27 +02:00
Stefan Roese
06dfaeef52 ppc4xx: Fix msg "initialization as root-complex failed" upon PCIe scan
This message is printed upon PCIe bus scan, not only upon error, but also
if no PCIe device is detected at all. Since this is not an error, let's
remove this message in this case. We already have the message
"link is not up." if there is no PCIe device present.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Wolfgang Denk <wd@denx.de>
2009-10-07 09:13:46 +02:00
Mike Nuss
54f5f056aa PPC4xx: Denali core: Fix incorrect DDR row bits
The SPD detection code for the Denali memory controller used on some
ppc4xx
processors incorrectly encodes DDR0_42. With certain memory
configurations,
this can cause the bootwrapper to incorrectly calculate the installed
memory
size, because the number of row bits is wrong. This patch fixes that
encoding.

Signed-off-by: Mike Nuss <mike@terascala.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2009-10-07 09:10:11 +02:00
Ben Warren
99dbd4efd6 Add information about return values of xxx_eth_register() in documentation
As discussed on mailing list, <0 indicates failure, >=0 indicates number
of interfaces found.

Also added blurb about private data

Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-10-05 00:02:51 -07:00
Mike Frysinger
1f1e774ec6 document network driver framework
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Acked-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-10-04 23:03:06 -07:00
Prafulla Wadaskar
aba8237257 net: kirkwood_egiga.c: fixed build warning
if link up detection code is disabled through config option, it gives build warning.
This patch fixes the same

Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-10-04 22:55:02 -07:00
Ben Warren
7194ab8095 Convert SMC91111 Ethernet driver to CONFIG_NET_MULTI API
All in-tree boards that use this controller have CONFIG_NET_MULTI
added
Also:
  - changed CONFIG_DRIVER_SMC91111 to CONFIG_SMC91111
  - cleaned up line lengths
  - modified all boards that override weak function in this driver
  - modified all eeprom standalone apps to work with new driver
  - updated blackfin standalone EEPROM app after testing

Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-10-04 22:37:03 -07:00
Prafulla Wadaskar
32e7f239dd net: phy: mv88e61xx.c : fixed build warning
following build warning was observed

mv88e61xx.c: In function ‘mv88e61xx_busychk’:
mv88e61xx.c:208: warning: dereferencing type-punned pointer will break strict-aliasing rules

This patch fixes the same
Patch tested for rd6281a board build

Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-10-04 22:30:46 -07:00
James Clough
c0b46d8ead net: Fix problem with 405EZ ethernet interrupt
On 405EZ the RX-/TX-interrupts are coalesced into one IRQ bit in the
UIC. We need to acknowledge the RX-/TX-interrupts in the
SDR0_ICINTSTAT reg as well.

This problem was introduced with commit
d1631fe1 [ppc4xx: Consolidate PPC4xx UIC defines]

Signed-off-by: James Clough <james@rtetc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-10-04 22:25:20 -07:00
Mike Frysinger
91b469c95f net: add random_port() prototype
The random_port() is meant to be used by other net code, but without a
prototype, we get fun warnings like:
dns.c: In function 'DnsSend':
dns.c:89: warning: implicit declaration of function 'random_port'

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-10-04 22:25:20 -07:00
Wolfgang Denk
311c19ccb5 Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx 2009-10-03 23:40:35 +02:00
Wolfgang Denk
eb4bf4c077 Merge branch 'master' of git://git.denx.de/u-boot-blackfin 2009-10-03 23:38:55 +02:00
Peter Tyser
3469424cb6 ppc: Remove reloc_off field from global_data structure
Now that proper relocation is supported, the reloc_off field is no longer
necessary.

Note that the location of the standalone application jump table pointer
in the global data structure is affected by this change, breaking
execution of standalone applications compiled for previous versions of
U-Boot.

We therefore increment XF_VERSION to 6

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-10-03 10:17:57 +02:00
Peter Tyser
0630535e2d arm/microblaze/nios/nios2/sh: Remove relocation fixups
These architectures don't need relocation fixups, so reduce their
codesize a bit by defining CONFIG_RELOC_FIXUP_WORKS.

Also remove the reloc_off field from their global data structures
as it is no longer needed.

Note that the location of the standalone application jump table pointer
in the global data structure is affected by this change, breaking
execution of standalone applications compiled for previous versions of
U-Boot. We will therefore increment XF_VERSION in the next commit,
which also touches this area.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-10-03 10:17:57 +02:00
Peter Tyser
521af04d85 Conditionally perform common relocation fixups
Add #ifdefs where necessary to not perform relocation fixups.  This
allows boards/architectures which support relocation to trim a decent
chunk of code.

Note that this patch doesn't add #ifdefs to architecture-specific code
which does not support relocation.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2009-10-03 10:17:57 +02:00
Peter Tyser
3cbcfa70b1 p3mx: Remove serial relocation fixups
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2009-10-03 10:17:57 +02:00
Peter Tyser
80f73b92a1 lwmon, lwmon5: Remove sysmon POST relocation fixups
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2009-10-03 10:17:56 +02:00
Peter Tyser
331ab60c4a mpl: Remove memory test relocation fixups
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2009-10-03 10:17:56 +02:00
Peter Tyser
6385b28116 fpga: Remove relocation fixups
PPC boards are the only users of the current FPGA code which is littered
with manual relocation fixups.  Now that proper relocation is supported
for PPC boards, remove FPGA manual relocation.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2009-10-03 10:17:56 +02:00
Peter Tyser
cd1011db80 tsec: Remove PHY command relocation fixups
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2009-10-03 10:17:56 +02:00
Peter Tyser
b5650c5d8c ppc: Remove board-specific command table relocation fixups
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2009-10-03 10:17:56 +02:00
Peter Tyser
e6b05e774d ppc: Remove extable relocation fixups
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2009-10-03 10:17:56 +02:00
Peter Tyser
b32a894011 ppc: Remove pci config table pointer relocation fixups
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2009-10-03 10:17:56 +02:00
Peter Tyser
a0e2066f39 ppc: Remove board.c relocation fixups
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2009-10-03 10:15:45 +02:00
Peter Tyser
2446151974 ppc: Check for compilers that don't support relocation
Certain ppc compilers are known not to generate the .fixup section
properly.  The .fixup section is necessary to create a relocatable
U-Boot image.  A basic check for the existence of the .fixup section
should hopefully catch the majority of broken compilers which don't
support relocation.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2009-10-03 10:15:45 +02:00
Peter Tyser
858290178f ppc: Enable full relocation to RAM
The following changes allow U-Boot to fully relocate from flash to
RAM:
 - Remove linker scripts' .fixup sections from the .text section
 - Add -mrelocatable to PLATFORM_RELFLAGS for all boards
 - Define CONFIG_RELOC_FIXUP_WORKS for all boards

Previously, U-Boot would partially relocate, but statically initialized
pointers needed to be manually relocated.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2009-10-03 10:15:45 +02:00
Matthias Fuchs
3b4bd2d75c ppc4xx: Add SDRAM detection for PMC440 boards
This patch adds support to detect the amount of DDR2 SDRAM
on PMC440 modules. Detection is done by probing through
a list of available and supported hardware configurations
from 1GByte down to 256MB.

The static TLB entry is replaced by dynamically created entries.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Signed-off-by: Stefan Roese <sr@denx.de>
2009-10-02 13:56:07 +02:00
Stefan Roese
fb95169e39 ppc4xx: Merge PPC4xx DDR and DDR2 ECC handling
This patch merges the ECC handling (ECC parity byte writing) into one
file (ecc.c) for all PPC4xx SDRAM controllers except for PPC440EPx/GRx.
This exception is because only those PPC's use the completely different
Denali SDRAM controller core.

Previously we had two routines to generate/write the ECC parity bytes.
With this patch we now only have one core function left.

Tested on Kilauea (no ECC) and Katmai (with and without ECC).

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Felix Radensky <felix@embedded-sol.com>
Cc: Grant Erickson <gerickson@nuovations.com>
Cc: Pieter Voorthuijsen <pv@prodrive.nl>
2009-10-02 13:53:37 +02:00
Felix Radensky
d24bd2517a ppc4xx: Reorganize DDR2 ECC handling
Reorganize DDR2 ECC handling to use common code for
SPD DIMMs and soldered SDRAM. Also, use common code
to display SDRAM info (ECC, CAS latency) for SPD and
soldered SDRAM variants.

Signed-off-by: Felix Radensky <felix@embedded-sol.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2009-10-02 13:53:28 +02:00
Wolfgang Denk
1d96cfe8f5 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2009-09-30 23:39:36 +02:00
Wolfgang Denk
7529b4445b Merge branch 'master' of git://git.denx.de/u-boot-nand-flash 2009-09-30 23:34:36 +02:00
Wolfgang Denk
9e2032aa56 Merge branch 'master' of git://git.denx.de/u-boot-ubi 2009-09-30 23:28:18 +02:00
Wolfgang Denk
9ae7ae6b4d Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx 2009-09-30 23:26:59 +02:00
Wolfgang Denk
7b5ae460c3 Merge branch 'master' of git://git.denx.de/u-boot-i2c 2009-09-30 23:24:10 +02:00
Wolfgang Denk
37d416324b Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx 2009-09-30 23:22:46 +02:00
Wolfgang Denk
d3909d74cc Merge branch 'master' of git://git.denx.de/u-boot-fdt 2009-09-30 23:16:49 +02:00
Mike Frysinger
46a887949e Blackfin: update default console= settings
The Linux kernel has changed the way it numbers serial ports, so update
the default command line to match it.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-09-30 15:15:08 -04:00
Mike Frysinger
4c5f307d58 Blackfin: bf533-ezkit: update env location
The u-boot image has outgrown the current space and overflowed into the
env sector.  So move the env to the next available sector (we've already
allocated the first few sectors anyways for u-boot).

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-09-30 15:15:06 -04:00
Kumar Gala
24b17d8a3c ppc/85xx: get_law_entry isn't used in CONFIG_NAND_SPL
Don't include get_law_entry as part of the NAND_SPL build since the
code isnt used.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-30 08:42:12 -05:00
Mingkai Hu
693a048d8a Add README.mpc8536ds
Add boot from NAND/eSDHC/eSPI description

Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-30 08:42:12 -05:00
Mingkai Hu
e40ac4870c On-chip ROM boot: MPC8536DS support
The MPC8536E is capable of booting from the on-chip ROM - boot from
eSDHC and boot from eSPI. When power on, the porcessor excutes the
ROM code to initialize the eSPI/eSDHC controller, and loads the mian
U-Boot image from the memory device that interfaced to the controller,
such as the SDCard or SPI EEPROM, to the target memory, e.g. SDRAM or
L2SRAM, then boot from it.

The memory device should contain a specific data structure with control
word and config word at the fixed address. The config word direct the
process how to config the memory device, and the control word direct
the processor where to find the image on the memory device, or where
copy the main image to. The user can use any method to store the data
structure to the memory device, only if store it on the assigned address.

The on-chip ROM code will map the whole 4GB address space by setting
entry0 in the TLB1, so the main image need to switch to Address space 1
to disable this mapping and map the address space again.

This patch implements loading the mian U-Boot image into L2SRAM, so
the image can configure the system memory by using SPD EEPROM.

Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-30 08:42:11 -05:00
Mingkai Hu
9a1a0aedbb NAND boot: MPC8536DS support
MPC8536E can support booting from NAND flash which uses the
image u-boot-nand.bin. This image contains two parts: a 4K
NAND loader and a main U-Boot image. The former is appended
to the latter to produce u-boot-nand.bin. The 4K NAND loader
includes the corresponding nand_spl directory, along with the
code twisted by CONFIG_NAND_SPL. The main U-Boot image just
like a general U-Boot image except the parts that included by
CONFIG_SYS_RAMBOOT.

When power on, eLBC will automatically load from bank 0 the
4K NAND loader into the FCM buffer RAM where CPU can execute
the boot code directly. In the first stage, the NAND loader
copies itself to RAM or L2SRAM to free up the FCM buffer RAM,
then loads the main image from NAND flash to RAM or L2SRAM
and boot from it.

This patch implements the NAND loader to load the main image
into L2SRAM, so the main image can configure the RAM by using
SPD EEPROM. In the first stage, the NAND loader copies itself
to the second to last 4K address space, and uses the last 4K
address space as the initial RAM for stack.

Obviously, the size of L2SRAM shouldn't be less than the size
of the image used. If so, the workaround is to generate another
image that includes the code to configure the RAM by SPD and
load it to L2SRAM first, then relocate the main image to RAM
to boot up.

Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-30 08:42:06 -05:00
Mingkai Hu
0735570052 mpc8536: fix board config file line length
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-30 08:29:51 -05:00
Paul Gortmaker
dd9ca98f26 sbc8548: reclaim wasted sector in boot flash
By nature of being based off the MPC8548CDS board, this
board inherited an ENV_SIZE setting of 256k.  But since
it has a smaller flash device (8MB soldered on), it has
a native sector size of 128k, and hence the ENV_SIZE was
causing 2 sectors to be used for the environment.

By removing the unused sector, we can push TEXT_BASE up
closer to the end of address space and reclaim that
sector for any other application.  This also fixes the
mismatch between TEXT_BASE and MONITOR_LEN reported by
Kumar earlier.

Since this board also supports the ability to boot off
the 64MB SODIMM flash, this change is forward looking
with that in mind; i.e. the settings for MONITOR_LEN
and ENV_SIZE will work when the 512k sectors of the
SODIMM flash are used for alternate boot in the future.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-30 08:29:47 -05:00
Kumar Gala
8280912e06 ppc/85xx: Clean up immap_85xx.h
* Converted all white space to tabs
* Converted all types to u8/u16/u32
* Reduce lines to fit in 80 columns
* Renamed MPC85xx_{Q,B}MAN -> FSL_CORENET_{Q,B}MAN

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-28 22:35:58 -05:00
Scott Wood
d44e9c1736 NAND: davinci: Fix warnings when 4-bit ECC not used
I accidentally left v2 of "NAND: DaVinci:Adding 4 BIT ECC support"
applied when I pushed the tree last merge window, and missed these fixes
which were in v3 of that patch.

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2009-09-28 16:33:18 -05:00
Kyungmin Park
ca6189db48 Refactor OneNAND IPL code
Refactoring the OneNAND IPL code

and some minor fixed:
- Remove unnecessary header file
- Fix wrong access at read interrupt
- The recent OneNAND has 4KiB pagesize

Also Board can override OneNAND IPL image

Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
2009-09-28 14:17:56 -05:00
Shinya Kuribayashi
a05e3f9a08 MIPS: VCT: Remove read_spareram reference
The commit ecad289fc6 (OneNAND: Remove
unused read_spareram and add unlock_all as kernel does) forgot to remove
a local reference to read_spareram in board/micronas/vct/ebi_onenand.c,
which causes the following build failure when configured with OneNAND:

ebi_onenand.c: In function 'onenand_board_init':
ebi_onenand.c:196: error: 'struct onenand_chip' has no member named 'read_spareram'
make[1]: *** [ebi_onenand.o] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [board/micronas/vct/libvct.a] Error 2

Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
Acked-by: Stefan Roese <sr@denx.de>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2009-09-28 13:55:06 -05:00
Simon Kagstrom
ef37c6835e ubifs: Correct dereferencing of files-after-symlinks
Files in directories which are symlinked to were not dereferenced
correctly in last commit. E.g., with a symlink

   /boot/lnk -> /boot/real_dir

loading

   /boot/lnk/uImage

will fail. This patch fixes that by simply seeing to it that the target
base directory has a slash after it.

Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
Signed-off-by: Stefan Roese <sr@denx.de>
2009-09-28 16:58:31 +02:00
Stefan Roese
b306db2f1b ppc4xx: Remove mtsdram0() marcos and use common mtsdram() instead
Additionally some whitespace coding style fixes.

Signed-off-by: Stefan Roese <sr@denx.de>
2009-09-28 10:46:05 +02:00
Stefan Roese
95b602bab5 ppc4xx: Convert PPC4xx SDRAM defines from lower case to upper case
The latest PPC4xx register cleanup patch missed some SDRAM defines.
This patch now changes lower case UIC defines to upper case. Also
some names are changed to match the naming in the IBM/AMCC users
manuals (e.g. mem_mcopt1 -> SDRAM0_CFG).

Signed-off-by: Stefan Roese <sr@denx.de>
2009-09-28 10:45:54 +02:00
Stefan Roese
952e7760bf ppc4xx: Convert PPC4xx UIC defines from lower case to upper case
The latest PPC4xx register cleanup patch missed the UIC defines.
This patch now changes lower case UIC defines to upper case.

Signed-off-by: Stefan Roese <sr@denx.de>
2009-09-28 10:45:42 +02:00
Joakim Tjernlund
d1c9e5b379 fsl_i2c: Do not generate STOP after read.
__i2c_read always ends with a STOP condition thereby releasing
the bus. It is cleaner to do the STOP magic in i2c_read(), like
i2c_write() does. This may also help future multimaster systems which
wants to hold on to the bus until all transactions are finished.

Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
2009-09-28 07:35:56 +02:00
Joakim Tjernlund
9940420212 fsl_i2c: Impl. AN2919, rev 5 to calculate FDR/DFSR
The latest AN2919 has changed the way FDR/DFSR should be calculated.
Update the driver according to spec. However, Condition 2
is not accounted for as it is not clear how to do so.

Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Acked-by: Wolfgang Grandegger <wg@grandegger.com>
2009-09-28 07:35:54 +02:00
Joakim Tjernlund
d01ee4db93 fsl_i2c: Add CONFIG_FSL_I2C_CUSTOM_{DFSR/FDR}
Some boards need a higher DFSR value than the spec currently
recommends so give these boards the means to define there own.

For completeness, add CONFIG_FSL_I2C_CUSTOM_FDR too.

Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
2009-09-28 07:35:53 +02:00
Joakim Tjernlund
21f4cbb772 fsl_i2c: Wait for STOP condition to propagate
After issuing a STOP one must wait until the STOP has completed
on the bus before doing something new to the controller.

Also add an extra read of SR as the manual mentions doing that
is a good idea.

Remove surplus write of CR just before a write, isn't required and
could potentially disturb the I2C bus.

Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
2009-09-28 07:35:52 +02:00
Kim Phillips
c7190f028f mpc83xx: retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfields
some LCRR bits are not documented throughout the 83xx family RMs.
New board porters copying similar board configurations might omit
setting e.g., DBYP since it was not documented in their SoC's RM.

Prevent them bricking their board by retaining power on reset values
in bit fields that the board porter doesn't explicitly configure
via CONFIG_SYS_<registername>_<bitfield> assignments in the board
config file.

also move LCRR assignment to cpu_init_r[am] to help ensure no
transactions are being executed via the local bus while CLKDIV is being
modified.

also start to use i/o accessors.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-09-26 21:19:38 -05:00
Paul Gortmaker
00ec0ff549 sbc8349: tidy up Makefile to use new configuration script.
Commit 804d83a5 allows us to move all the configuration
variation tweaks out of the top level Makefile and down
into the board config header.  This takes advantage of
that for the sbc8349 board.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-09-25 18:27:54 -05:00
Anton Vorontsov
da6eea0f48 mpc83xx: mpc8360emds: Add QE USB device tree fixups
With this patch we can change QE USB mode without need to hand-edit
the device tree.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-09-25 18:25:51 -05:00
Anton Vorontsov
89da44ce3f mpc83xx: mpc8360emds: Use RGMII-ID mode, add workarounds for rev. 2.1 CPUs
This patch fixes various ethernet issues with gigabit links handling
in U-Boot. The workarounds originally implemented by Kim Phillips for
Linux kernel.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-09-25 18:25:51 -05:00
Anton Vorontsov
034477bb31 mpc83xx: mpc8360emds: Don't use LBC SDRAM when DDR is available
Since commit 5c2ff323a9 ("mpc8360emds:
rework LBC SDRAM setup"), LBC SDRAM is available for use in Linux.

Though, it appears that QE Ethernet in Gigabit mode can't transmit
large packets when it tries to work with a data in LBC SDRAM (memtest
didn't discover any issues, is LBC SDRAM just too slow?).

With this patch we can still use the board without DDR memory, but
if DDR is available, we don't use LBC SDRAM.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-09-25 18:25:51 -05:00
Anton Vorontsov
d77c779bc2 net: uec: Fix uccf.h and uec.h headers to include headers they depend on
Headers should include headers containing prototypes and defines they
depend on, don't assume that they're included by somebody else.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-09-25 18:25:50 -05:00
Anton Vorontsov
6185f80c31 net: uec_phy: Implement TXID and RXID RGMII modes for Marvell PHYs
This will be needed for MPC8360E-MDS boards with rev. 2.1 CPUs.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-09-25 18:25:41 -05:00
Wolfgang Denk
984f10baac mpc5121ads: fix breakage introduced when reordering elpida_mddrc_config[]
Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-09-25 14:16:00 +02:00
Ken MacLeod
6e748ea004 cmd_fdt.c: fix parse of byte streams and strings
Commit 4abd844d8e extended the fdt command parser to handle property
strings which are split across multiple arguments but it was broken for
byte streams and strings.

Byte stream parsing:

 * Fixes where it would terminate early or go into an endless loop.

 * Fixes a 0x00 being inserted into the data if there is a space after
   '[' or a separate argument.

 * Fixes dereferencing the argument pointer after the last argument.

 * Checks for bad characters.

String parsing:

 * Treat multiple arguments as a string list.  This fixes an issue where
   only the last argument was stored.

Signed-off-by: Ken MacLeod <ken@bitsko.slc.ut.us>
2009-09-24 21:57:30 -04:00
Heiko Schocher
3887c3fbdb mucmc52, uc101: delete ata@3a00 node, if no CF card is detected
U-Boot can detect if an IDE device is present or not.
If not, and this new config option is activated, U-Boot
removes the ATA node from the DTS before booting Linux,
so the Linux IDE driver does not probe the device and
crash. This is needed for buggy hardware (uc101) where
no pull down resistor is connected to the signal IDE5V_DD7.

Signed-off-by: Heiko Schocher <hs@denx.de>
2009-09-25 01:22:13 +02:00
Heiko Schocher
7f625fc6d3 mpc5200, mucmc52, uc101: config cleanup
- As these boards are similiar, collect common config options
  in manroland/common.h and manroland/mpc52xx-common.h
  for mpc5200 specific common options for this manufacturer.
- add OF support
- update default environment

Signed-off-by: Heiko Schocher <hs@denx.de>

Minor edit of commit message.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-09-25 01:19:17 +02:00
Wolfgang Denk
9d142ea8f7 Fix "ppc/85xx: Clean up use of LAWAR defines" breakage
Commit 002741ae86 modified include/asm-ppc/mmu.h such that the LAWAR_
defines were only enabled for the 83xx platform, but they are also
needed on MPC512x system. Enabling these for E300 systems seems thus
more appropriate.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-09-25 01:02:52 +02:00
Martha M Stan
a5aa3998ab Add Elpida Memory Configuration to mpc5121ads Boards
Signed-off-by: Martha M Stan <mmarx@silicontkx.com>

Minor coding style cleanup.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-09-25 00:45:38 +02:00
Martha M Stan
054197ba8e mpc512x: Streamlined fixed_sdram() init sequence.
Signed-off-by: Martha M Stan <mmarx@silicontkx.com>

Minor cleanup:

Re-ordered default_mddrc_config[] to have matching indices.

This allows to use the same index "N" for source and target fields;
before, we had code like this

	out_be32(&im->mddrc.ddr_time_config2, mddrc_config[3]);

which always looked like a copy & paste error because 2 != 3.

Also, use NULL when meaning a null pointer.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-09-25 00:45:30 +02:00
Wolfgang Denk
5e498dfab8 Merge branch 'master' of /home/wd/git/u-boot/custodians 2009-09-24 23:40:25 +02:00
Kumar Gala
39aaca1f66 ppc/p4080: Determine various chip frequencies on CoreNet platforms
The means to determine the core, bus, and DDR frequencies are completely
new on CoreNet style platforms.  Additionally on p4080 we can have
different frequencies for FMAN and PME IP blocks.  We need to keep track
of the FMAN & PME frequencies since they are used for time stamping
capabilities inside each block.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-24 12:05:29 -05:00
Kumar Gala
3c2a67eec8 ppc/p4080: Handle timebase enabling and frequency reporting
On CoreNet style platforms the timebase frequency is the bus frequency
defined by 16 (on PQ3 it is divide by 8).  Also on the CoreNet platforms
the core not longer controls the enabling of the timebase.  We now need
to enable the boot core's timebase via CCSR register writes.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-24 12:05:29 -05:00
Kumar Gala
7e4259bba4 ppc/p4080: Add various p4080 related defines (and p4040)
There are various locations that we have chip specific info:

* Makefile for which ddr code to build
* Added p4080 & p4040 to cpu_type_list and SVR list
* Added number of LAWs for p4080
* Set CONFIG_MAX_CPUS to 8 for p4080

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-24 12:05:28 -05:00
Kumar Gala
39a7e7fd53 ppc/p4080: CoreNet platfrom style secondary core release
The CoreNet platform style of bringing secondary cores out of reset is
a bit different that the PQ3 style.  Mostly the registers that we use
to setup boot translation, enable time bases, and boot release the cores
have moved around.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-24 12:05:28 -05:00
Kumar Gala
a880cf3e0e ppc/p4080: CoreNet platfrom style CCSRBAR setting
On CoreNet based platforms the CCSRBAR address is split between an high &
low register and we no longer shift the address.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2009-09-24 12:05:28 -05:00
Kumar Gala
418ec85843 ppc/p4080: Add support for CoreNet style platform LAWs
On CoreNet based platforms the LAW address is split between an high &
low register and we no longer shift the address.  Also, the target IDs
on CoreNet platforms have been completely re-assigned.

Additionally, added a new find_law() API to which LAW an address hits in.
This is need for the CoreNet style boot release code since it will need
to determine what the target ID should be set to for boot window
translation.

Finally, enamed LAWAR_EN to LAW_EN and moved to header so we can use
it elsewhere.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-24 12:05:28 -05:00
Kumar Gala
01df521217 ppc/p4080: Add p4080 platform immap definitions
The p4080 SoC has a significant amount of commonality with the 85xx/PQ3
platform.  We reuse the 85xx immap and just add new definitions for
local access and global utils.  The global utils is now broken into
global utils, clocking and run control/power management.

The offsets from CCSR for a number of blocks have also changed.  We
introduce the CONFIG_FSL_CORENET define to distinquish the PQ3 style of
platform from the new p4080 platform.  We don't use QoirQ as there are
products (like p2020) that are PQ3 based platforms but have the QoirQ
name.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-24 12:05:27 -05:00
Kumar Gala
25bacf7a2b ppc/85xx: Fix enabling of L2 cache
We need to flash invalidate the locks in addition to the cache
before we enable.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-24 12:05:27 -05:00
Vivek Mahajan
cb0ff65c61 85xx-fdt: Fixed l2-ctlr's compatible prop for QorIQ
The code assumed names where just numbers and always prefixed 'mpc'.
However newer QorIQ don't follow the mpc naming scheme.

Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-24 12:05:27 -05:00
Mingkai Hu
234a89d911 ppc/85xx: add cpu init config file for boot from NAND
When boot from NAND, the NAND flash must be connected to br/or0.
Also init RAM(L2 SRAM or DDR SDRAM) for load the second image to
it.

Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-24 12:05:26 -05:00
Mingkai Hu
266139b88b immap_85xx: add porpllsr's plat ratio definition
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-24 12:05:26 -05:00
Mingkai Hu
098bcbae31 ppc/85xx: add ld script file for boot from NAND
The first stage 4K image uses a seperate ld script file to
generate 4K image. This patch moves it to the cpu/mpc85xx/*
to make it avaliable for 85xx platform.

Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-24 12:05:25 -05:00
Peter Tyser
8439f05cfd mpc8610hpcd: Use common 86xx fdt fixup code
Using the common 86xx fdt fixups removes some board-specific code and
should make the mpc8610hpcd easier to maintain in the long run.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-24 12:05:25 -05:00
Paul Gortmaker
928435d11b sbc85x0: tidy up Makefile to use new configuration script.
Commit 804d83a5 allows us to move all the configuration
variation tweaks out of the top level Makefile and down
into the boards config header.  This takes advantage of
that for the sbc8540/sbc8560 boards.

There were a couple of cheezy comments pointing at incorrect
files, or files that don't exist, so I've cleaned those up too.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-24 12:05:00 -05:00
Paul Gortmaker
2738bc8df6 sbc8548: allow enabling PCI via a make config option
Prior to this commit, to enable PCI, you had to go manually
edit the board config header, and if you had 33MHz PCI, you
had to manually change CONFIG_SYS_NS16550_CLK too, which was
not real user friendly,

This adds the typical PCI and clock speed make targets to the
toplevel Makefile in accordance with what is being done with
other boards (i.e. using the "-t" to mkconfig).

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-24 12:05:00 -05:00
Paul Gortmaker
fdc7eb90b5 sbc8548: update PCI/PCI-e support code
The PCI/PCI-e support for the sbc8548 was based on an earlier
version of what the MPC8548CDS board was using, and in its
current state it won't even compile.  This re-syncs it to match
the latest codebase and makes use of the new shared PCI functions
to reduce board duplication.

It borrows from the MPC8568MDS, in that it pulls the PCI-e I/O
back to 0xe280_0000 (where PCI2 would be on MPC8548CDS), and
similarly it coalesces the PCI and PCI-e mem into one single TLB.

Both PCI-x and PCI-e have been tested with intel e1000 cards
under linux (with an accompanying dts change in place)

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-24 12:05:00 -05:00
Paul Gortmaker
a8b3e90f79 fsl_pci: create a SET_STD_PCI_INFO() helper wrapper
Recycle the recently added PCI-e wrapper used to reduce board
duplication of code by creating a similar version for plain PCI.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-24 12:05:00 -05:00
Paul Gortmaker
11d5a629f8 sbc8548: correct local bus SDRAM size from 64M to 128M
The size of the LB SDRAM on this board is 128MB, spanning CS3
and CS4.  It was previously only being configured for 64MB on
CS3, since that was what the original codebase of the MPC8548CDS
had.  In addition to setting up BR4/OR4, this also adds the TLB
entry for the second half of the SDRAM.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-24 12:05:00 -05:00
Paul Gortmaker
0c7e4d45d9 sbc8548: use I/O accessors
Sweep throught the board specific file and replace the various
register proddings with the equivalent I/O accessors.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-24 12:05:00 -05:00
Paul Gortmaker
fc38eb98ff sbc8548: remove eTSEC3/4 voltage hack
With only eTSEC1 and 2 being brought out to RJ-45 connectors, we
aren't interested in the eTSEC3/4 voltage hack on this board

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-24 12:05:00 -05:00
Paul Gortmaker
9b3ba24f18 sbc8548: enable access to second bank of flash
The sbc8548 has a 64MB SODIMM flash module off of CS6 that
previously wasn't enumerated by u-boot.  There were already
BR6/OR6 settings for it [used by cpu_init_f()] but there
was no TLB entry and it wasn't in the list of flash banks
reported to u-boot.

The location of the 64MB flash is "pulled back" 8MB from
a 64MB boundary, in order to allow address space for the
8MB boot flash that is at the end of 32 bit address space.
This means creating two 4MB TLB entries for the 8MB chunk,
and then expanding the original boot flash entry to 64MB
in order to cover the 8MB boot flash and the remainder
(56MB) of the user flash.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-24 12:05:00 -05:00
Paul Gortmaker
ded58f4153 sbc8548: cosmetic line re-wrap
Fix the extra long lines to be consistent with u-boot coding style.
No functional change here.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
2009-09-24 12:04:59 -05:00
Paul Gortmaker
2c40acd352 sbc8548: get_clock_freq is not valid for this board
The get_clock_freq() comes from freescale/common/cadmus.c and is
only valid for the CDS based 85xx reference platforms.  It would
be nice if we could read the 33 vs. 66MHz status somehow, but in
the meantime, tie it to CONFIG_SYS_CLK_FREQ like all the other
non-CDS boards do.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-24 12:04:59 -05:00
Paul Gortmaker
7b1f1399e8 sbc8548: delete unused MPC8548CDS info carried over from port
There are a couple defines and PCI bridge quirks related to the PCI
backplane of the MPC8548CDS that have no meaning in the context of
the port to the sbc8548 board, so delete them.

Also, the form factor of the sbc8548 is a standalone board with a
single PCI-X and a single PCI-e slot.  That pretty much guarantees
that it will never be a PCI agent itself, so the host/agent and root
complex/end node distinctions have been removed.

Similarly, since there is no physical connector mapping to PCI2, so
all references of PCI2 in the board support files have been removed
as well.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-24 12:04:59 -05:00
Paul Gortmaker
94ca091456 sbc8548: enable use of PCI network cards
Create a board_eth_init to allow a place to hook in
the PCI ethernet init after all the eTSEC are up
and configured.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-24 12:04:59 -05:00
Poonam Aggrwal
82b7725b6d ppc/85xx: 32bit DDR changes for P1020/P1011
The P1020/P1011 SOCs support max 32bit DDR width as opposed to P2020/P2010
where max DDR data width supported is 64bit.

As a next step the DDR data width initialization would be made more dynamic
with more flexibility from the board perspective and user choice.
Going forward we would also remove the hardcodings for platforms with onboard
memories and try to use the FSL SPD code for DDR initialization.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-24 12:04:59 -05:00
Paul Gortmaker
bd42bbb858 sbc8548: replace README with completely new document
The previous README.sbc8548 was pretty much content-free. Replace
it with something that actually gives the end user some relevant
hardware details, and also lists the u-boot configuration choices.

Also in the cosmetic department, fix the bogus line in the Makefile
that was carried over from the SBC8560 Makefile, and the typo in
the sbc8548.c copyright.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-24 12:04:59 -05:00
Kumar Gala
002741ae86 ppc/85xx: Clean up use of LAWAR defines
On 85xx platforms we shouldn't be using any LAWAR_* defines
but using the LAW_* ones provided by fsl-law.h.  Rename any such
uses and limit the LAWAR_ to the 83xx platform as the only user so
we will get compile errors in the future.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-24 12:04:58 -05:00
Kumar Gala
f61dae7c9d ppc/85xx: Clean up mpc8572DS PCI setup code
Use new fsl_pci_init_port() that reduces amount of duplicated code in the
board ports, use IO accessors and clean up printing of status info.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-24 12:04:58 -05:00
Kumar Gala
4958af8735 ppc/85xx: Clean up p2020ds PCI setup code
Use new fsl_pci_init_port() that reduces amount of duplicated code in the
board ports, use IO accessors and clean up printing of status info.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-24 12:04:58 -05:00
Kumar Gala
93a83872c7 ppc/85xx: Clean up p1_p2_rdb PCI setup
General code cleanup to use in/out IO accessors as well as making
the code that prints out info sane between board and generic fsl pci
code.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-24 12:04:58 -05:00
Kumar Gala
62ca21c442 ppc/85xx: Simplify the top makefile for P1_P2_RDB boards
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-24 12:04:58 -05:00
Kumar Gala
a0f9e0e0f0 ppc/85xx: Simplify the top makefile for 36-bit config for P2020DS
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-24 12:04:57 -05:00
Kumar Gala
f9edcc10e6 ppc/85xx: Simplify the top makefile for 36-bit config for MPC8572DS
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-24 12:04:57 -05:00
Mingkai Hu
0e905ac28b ppc/85xx: simplify the top makefile for 36-bit config for mpc8536ds
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-24 12:04:57 -05:00
Kumar Gala
202d94875c ppc/85xx: Fix LCRR_CLKDIV defines
For some reason the CLKDIV field varies between SoC in how it interprets
the bit values.

All 83xx and early (e500v1) PQ3 devices support:
 clk/2: CLKDIV = 2
 clk/4: CLKDIV = 4
 clk/8: CLKDIV = 8

Newer PQ3 (e500v2) and MPC86xx support:
 clk/4: CLKDIV = 2
 clk/8: CLKDIV = 4
 clk/16: CLKDIV = 8

Ensure that the MPC86xx and MPC85xx still get the same behavior and make
the defines reflect their logical view (not the value of the field).

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Peter Tyser <ptyser@xes-inc.com>
2009-09-24 12:04:57 -05:00
Peter Tyser
55f786d8ba MAKEALL: Use POSIX math
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2009-09-24 00:37:43 +02:00
Peter Tyser
40a28f0885 MAKEALL: Add summary information
This change adds some basic summary information to the MAKEALL script.
The summary information includes how many boards were compiled, how many
boards had compile warnings or errors, and which specific boards had
compile warnings or errors.

This information is useful when doing compile testing to quickly
determine which boards are broken.

As a side benefit, no empty $BOARD.ERR files are generated by MAKEALL.
Previously, each board had a corresponding $BOARD.ERR file, even if the
board compiled cleanly.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2009-09-24 00:37:41 +02:00
Eric Millbrandt
71ce9bd7f5 galaxy5200: enable version environment variable
Add version environment variable configuration to the galaxy5200
board header file.

Signed-off-by: Eric Millbrandt <emillbrandt@dekaresearch.com>

Edited commit message.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-09-24 00:23:05 +02:00
Werner Pfister
c569ad6e1e digsy_mtc: Add TCR register value for RTC (DS1339)
Signed-off-by: Werner Pfister <werner.pfister@intercontrol.de>
Signed-off-by: Detlev Zundel <dzu@denx.de>
2009-09-24 00:21:06 +02:00
Werner Pfister
b0078c8792 rtc/ds1337.c: Allow to set TCR register
This is needed to correctly start the charging of an attached capacitor
or battery.

Signed-off-by: Werner Pfister <werner.pfister@intercontrol.de>
Signed-off-by: Detlev Zundel <dzu@denx.de>
2009-09-24 00:20:33 +02:00
Wolfgang Denk
30d7aae7e8 Merge branch 'master' of /home/wd/git/u-boot/custodians 2009-09-24 00:18:15 +02:00
Wolfgang Denk
9a49e0e161 Merge branch 'master' of git://git.denx.de/u-boot-ubi 2009-09-24 00:18:10 +02:00
Wolfgang Denk
1c19863fa2 Merge branch 'master' of /home/wd/git/u-boot/custodians 2009-09-24 00:17:17 +02:00
Simon Kagstrom
9d7952e4c6 ubifs: Add support for looking up directory and relative symlinks
This patch adds support for resolving symlinks to directories as well as
relative symlinks. Symlinks are now always resolved during file lookup,
so the load stage no longer needs to special-case them.

Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
Signed-off-by: Stefan Roese <sr@denx.de>
2009-09-23 15:58:05 +02:00
Rupjyoti Sarmah
fcdb36b85a ppc4xx: Fix PCIE PLL lock on 440SPe Yucca board
u-boot reports a PCIE PLL lock error at boot time on Yucca board, and
left PCIe nonfunctional. This is fixed by making u-boot function
ppc4xx_init_pcie() to wait 300 uS after negating reset before the
first check of the PLL lock.

Signed-off-by: Rupjyoti Sarmah <rsarmah@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2009-09-23 15:46:08 +02:00
Dirk Eibach
91d599044c ppc4xx: Make DDR2 timing for intip more robust
DDR2 timing for intip was on the edge for some of the available chips
for this board. Now it is verfied to work with all of them.

Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2009-09-23 15:46:02 +02:00
Wolfgang Denk
184a3a27f5 board/linkstation/ide.c: Fix compile warning
Fix warning: ide.c:60: warning: dereferencing type-punned pointer will
break strict-aliasing rules

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Guennadi Liakhovetski <lg@denx.de>
2009-09-22 23:53:44 +02:00
Peter Tyser
004eca0c9b ppc: Clean up calling of phy_reset() during init
Remove board-specific #ifdefs for calling phy_reset() during
initializtion

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2009-09-22 23:05:29 +02:00
Peter Tyser
3a8f28d0a6 ppc: Clean up calling of misc_init_r() during init
Remove board-specific #ifdefs for calling misc_init_r() during
initializtion

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Acked-by: Heiko Schocher <hs@denx.de>
2009-09-22 23:04:44 +02:00
Peter Tyser
3202d33169 Remove deprecated 'autoscr' command/variables
The more standard 'source' command provides identical functionality to
the autoscr command.

Environment variable names/values on the MVBC_P, MVBML7, kmeter1,
mgcoge, and km8xx boards are updated to no longer refernce 'autoscr'.

The 'autoscript' and 'autoscript_uname' environment variables are
also removed.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Acked-by: Andre Schwarz <andre.schwarz@matrix-vision.de>
Acked-by: Heiko Schocher <hs@denx.de>
2009-09-22 23:03:24 +02:00
Paul Gibson
d3f4941874 mpc512x. Micron nand flash needs a reset before a read command is issued.
Micron nand flash needs a reset before a read command is issued.
The current mpc5121_nfc driver ignores the reset command.
2009-09-22 22:59:42 +02:00
Marcel Ziswiler
b55ae40249 FDT: remove obsolete OF_CPU and OF_SOC macros.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@noser.com>
Acked-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Acked-by: Heiko Schocher <hs@denx.de>
2009-09-22 22:59:27 +02:00
Wolfgang Denk
3b6a9267f0 board/flagadm/flash.c: fix compile warning
Fix warning: flash.c:531: warning: dereferencing type-punned pointer
will break strict-aliasing rules

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Kri Davsson <kd@flaga.is>
2009-09-18 23:24:48 +02:00
Wolfgang Denk
084f3ddac6 Merge branch 'warning-cleanup' 2009-09-18 23:20:12 +02:00
Wolfgang Denk
3dc5e00454 Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx 2009-09-17 23:28:31 +02:00
Simon Kagstrom
0413cfecea Correct ffs/fls regression for PowerPC etc
Commits

  02f99901ed
  52d61227b6

introduced a regression where platform-specific ffs/fls implementations
were defined away. This patch corrects that by using PLATFORM_xxx
instead of the name itself.

Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Stefan Roese <sr@denx.de>
2009-09-17 22:45:31 +02:00
Stefan Roese
e67af44d01 ppc4xx: Consolidate get_OPB_freq()
All 4xx variants had their own, mostly identical get_OPB_freq()
function. Some variants even only had the OPB frequency calculated
in this routine and not supplied the sys_info.freqOPB variable
correctly (e.g. 405EZ). This resulted in incorrect OPB values passed
via the FDT to Linux.

This patch now removes all those copies and only uses one function
for all 4xx variants (except for IOP480 which doesn't have an OPB).

Signed-off-by: Stefan Roese <sr@denx.de>
2009-09-17 14:08:32 +02:00
Stefan Roese
84a45d33c2 ppc4xx: Enable commands for FDT enabled Linux booting on AMCC Acadia
Acadia still used the "old" arch/ppc bootm commands for booting
Linux images without FDT. This patch now enables these fdt-aware
boot commands for Acadia as well.

Signed-off-by: Stefan Roese <sr@denx.de>
2009-09-17 14:08:26 +02:00
Stefan Roese
95a4a593b5 ppc4xx: Fix 405EZ uart base baud calculation
With this fix, Linux correctly configures the baudrate when booting
with FDT passed from U-Boot to Linux.

Signed-off-by: Stefan Roese <sr@denx.de>
2009-09-17 14:05:52 +02:00
Kumar Gala
15fba3279b ppc/85xx: Disable all async interrupt sources when we boot
We should make sure to clear MSR[ME, CE, DE] when we boot an OS image
since we have changed the exception vectors and the OSes vectors might
not be setup we should avoid async interrupts at all costs.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-15 21:30:09 -05:00
Kumar Gala
9f00409a9d ppc/85xx: Split out cpu_init_early into its own file for NAND_SPL
By pulling out cpu_init_early we can build just it and not all of
cpu_init for NAND_SPL.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-15 21:30:09 -05:00
Kumar Gala
0456dbf347 ppc/85xx: Change cpu_init_early_f so we can use with NAND SPL
Use write_tlb and don't use memset so we can use the same code for
cpu_init_early_f between NAND SPL and not.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-15 21:30:09 -05:00
Mingkai Hu
6e1385d5f8 NAND boot: change NAND loader's relocate SP to CONFIG param
So that we can set the NAND loader's relocate stack pointer
to the value other than the relocate address + 0x10000.

Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-15 21:30:09 -05:00
Mingkai Hu
7da53351d8 ppc/85xx: add boot from NAND/eSDHC/eSPI support
The MPC8536E is capable of booting form NAND/eSDHC/eSPI, this patch
implements these three bootup methods in a unified way - all of these
use the general cpu/mpc85xx/start.S, and load the main image to L2SRAM
which lets us use the SPD to initialize the SDRAM.

For all three bootup methods, the bootup process can be divided into two
stages: the first stage will initialize the corresponding controller,
configure the L2SRAM, then copy the second stage image to L2SRAM and
jump to it. The second stage image is just like the general U-Boot image
to configure all the hardware and boot up to U-Boot command line.

When boot from NAND, the eLBC controller will first load the first stage
image to internal 4K RAM buffer because it's also stored on the NAND
flash. The first stage image, also call 4K NAND loader, will initialize
the L2SRAM, load the second stage image to L2SRAM and jump to it. The 4K
NAND loader's code comes from the corresponding nand_spl directory, along
with the code twisted by CONFIG_NAND_SPL.

When boot from eSDHC/eSPI, there's no such a first stage image because
the CPU ROM code does the same work. It will initialize the L2SRAM
according to the config addr/word pairs on the fixed address and
initialize the eSDHC/eSPI controller, then load the second stage image
to L2SRAM and jump to it.

The macro CONFIG_SYS_RAMBOOT is used to control the code to produce the
second stage image for all different bootup methods. It's set in the
board config file when one of the bootup methods above is selected.

Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-15 21:30:09 -05:00
Kumar Gala
b2eec281a8 ppc/85xx: Move code around to prep for NAND_SPL
If we move some of the functions in tlb.c around we need less
ifdefs.  The first stage loader just needs invalidate_tlb and
init_tlbs.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-15 21:30:09 -05:00
Kumar Gala
206af3527c ppc/85xx: Repack tlb_table to save space
We can pack the initial tlb_table in MAS register format and use
write_tlb to set things up.  This savings can be helpful for NAND
style first stage boot loaders.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-15 21:30:09 -05:00
Kumar Gala
d30f904353 ppc/85xx: Introduce low level write_tlb function
Factor out the code we use to actually write a tlb entry.

set_tlb is a logical view of the TLB while write_tlb is a low level
matching the MAS registers.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-15 21:30:08 -05:00
Roy Zang
0ead6f2ed7 ppc/85xx: Enable usb ehci support for p2020ds board
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-15 21:30:08 -05:00
Kumar Gala
6d8565a1ed ppc/8xxx: Misc DDR related fixes
* Fix setting of ESDMODE (MR1) register - the bit shifting was wrong
* Fix the format string to match size in a debug print

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-15 21:30:08 -05:00
Scott Wood
3e3c9c157b ppc/85xx: Remove some bogus code from external interrupt handler.
Skipping the interrupted instruction will accomplish nothing other
than turning a spurious interrupt into a crash.

External interrupts are not machine checks, so don't count them as such.

Signed-off-by: Scott Wood <scottwood@freescale.com>
2009-09-15 21:30:08 -05:00
Scott Wood
dcc87dd58d ppc/85xx: Ensure that MAS8 is zero when writing TLB entries.
Its reset value is random, and we sometimes read uninitialized TLB
arrays.  Make sure that we don't retain MAS8 from reading such an entry
if the VF bit in MAS8 is set, attempts to use the mapping will trap.

Signed-off-by: Scott Wood <scottwood@freescale.com>
2009-09-15 21:30:08 -05:00
Scott Wood
1b72dbecca ppc/85xx: Don't enable interrupts before we're ready
We cannot handle any exceptions while running in AS1, as the exceptions
will transition back to AS0 without a valid mapping.

Signed-off-by: Scott Wood <scottwood@freescale.com>
2009-09-15 21:30:07 -05:00
Marcel Ziswiler
3ca55bce9c mpc8260: remove Ethernet node fixup to use generic FDT code.
Remove Ethernet node fixup from mgcoge and muas3001 boards and modify its
configs for the common mpc8260 code to use generic Ethernet fixup.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@noser.com>
Tested-by: Heiko Schocher <hs@denx.de>
2009-09-15 23:01:15 +02:00
Mike Frysinger
1c20e4a9fb tools/netconsole: use ncb automatically if available
The standard netcat, while ubiquitous, doesn't handle broadcast udp packets
properly.  The local ncb util does however.  So if ncb can be located in
the standard locations, automatically use that instead.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-09-15 22:55:45 +02:00
Mike Frysinger
770931805d tools/netconsole: make a bit more robust
The netcat utility likes to exit when it receives an empty packet (as it
thinks this means EOF).  This can easily occur when working with command
line editing as this behavior will be triggered when using backspace.  Or
with tabs and command line completion.  So create two netcat processes -
one to only listen (and put it into a loop), and one to do the sending.
Once the user quits the transmitting netcat, the listening one will be
killed automatically.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-09-15 22:54:19 +02:00
Simon Kagstrom
a6e19d69f6 arm: Define test_and_set_bit and test_and_clear bit for ARM
Needed for (e.g.) ubifs support to work.

Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
2009-09-15 22:35:20 +02:00
Simon Kagstrom
52d61227b6 Define ffs/fls for all architectures
UBIFS requires fls(), which is not defined for arm (and some other
architectures) and this patch adds it. The implementation is taken from
Linux and is generic. ffs() is also defined for those that miss it.

Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
2009-09-15 22:34:32 +02:00
Simon Kagstrom
4b15de08fe arm: Make arm bitops endianness-independent
Bring over the bitop implementations from the Linux
include/asm-generic/bitops/non-atomic.h to provide
endianness-independence.

Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
2009-09-15 22:34:04 +02:00
Simon Kagstrom
02f99901ed Move __set/clear_bit from ubifs.h to bitops.h
__set_bit and __clear_bit are defined in ubifs.h as well as in
asm/include/bitops.h for some architectures. This patch moves
the generic implementation to include/linux/bitops.h and uses
that unless it's defined by the architecture.

Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
2009-09-15 22:31:24 +02:00
Mike Frysinger
557555fe0b standalone: convert to kbuild style
Clean up the arch/cpu/board/config checks as well as redundant setting of
srec/bin variables by using the kbuild VAR-$(...) style.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-09-15 22:27:23 +02:00
Wolfgang Denk
804d83a563 mkconfig: split the board make target to multiple config targets
To simplify the top level makefile it useful to be able to parse
the top level makefile target to multiple individual target, then
put them to the config.h, leave the board config file to handle
the different targets.

Note that this method uses the '_'(underline) as the delimiter when
splits the board make target.

Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>

This also reverts commit 511c02f611.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-09-15 22:14:18 +02:00
Wolfgang Denk
041a6a0c2e Merge branch 'master' of git://git.denx.de/u-boot-microblaze 2009-09-15 21:45:50 +02:00
Wolfgang Denk
cae26e2fdd Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx 2009-09-15 21:43:25 +02:00
Wolfgang Denk
ceb2d57c22 kwbimage.c: Fix compile warning when building on 64 bit systems (again)
Commit 51003b89 attempted to fix a build problem on 64 bit systems,
but just turned it into a build problem on 32 bit systems (silly me).

Now do the Right Thing (TM) and use a "%zu" printf format.

Also fix spelling error.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-09-15 21:32:19 +02:00
Wolfgang Denk
6c7bc91fb3 board/amcc/common/flash.c: Fix compile warning
Fix warning: ../common/flash.c:917: warning: dereferencing type-punned
pointer will break strict-aliasing rules

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Stefan Roese <sr@denx.de>
Acked-by: Stefan Roese <sr@denx.de>
2009-09-15 00:29:49 +02:00
Wolfgang Denk
70fb809c56 board/amcc/yucca/flash.c: Fix compile warning
Fix warning: flash.c:919: warning: dereferencing type-punned pointer
will break strict-aliasing rules

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Stefan Roese <sr@denx.de>
Acked-by: Stefan Roese <sr@denx.de>
2009-09-15 00:29:13 +02:00
Wolfgang Denk
030ec52f8c board/amcc/taihu/flash.c: Fix compile warning
Fix warnings:
flash.c: In function 'write_word_1':
flash.c:696: warning: dereferencing type-punned pointer will break strict-aliasing rules
flash.c: In function 'write_word_2':
flash.c:1044: warning: dereferencing type-punned pointer will break strict-aliasing rules

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Stefan Roese <sr@denx.de>
Acked-by: Stefan Roese <sr@denx.de>
2009-09-15 00:28:24 +02:00
Wolfgang Denk
0fd3d902d9 board/etin/debris/phantom.c: Fix compile error
Fix build problem caused by commit e84aba13: "Replace BCD2BIN and
BIN2BCD macros with inline functions"

phantom.c:163: error: redefinition of 'bcd2bin'
/home/wd/git/u-boot/work/include/bcd.h:16: error: previous definition of 'bcd2bin' was here
phantom.c:168: error: redefinition of 'bin2bcd'
/home/wd/git/u-boot/work/include/bcd.h:21: error: previous definition of 'bin2bcd' was here

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Sangmoon Kim <dogoil@etinsys.com>
2009-09-15 00:17:56 +02:00
Wolfgang Denk
5168801f4b board/dave/common/flash.c: fix compile warning
Fix warning: ../common/flash.c:668: warning: dereferencing type-punned
pointer will break strict-aliasing rules

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Andrea Marson <andrea.marson@dave-tech.it>
2009-09-15 00:15:58 +02:00
Wolfgang Denk
97138fc480 board/esd/cpci750/ide.c: fix compile warning
Fix warning: ide.c:54: warning: dereferencing type-punned pointer will
break strict-aliasing rules

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Cc: Stefan Roese <sr@denx.de>
Acked-by: Stefan Roese <sr@denx.de>
2009-09-15 00:13:15 +02:00
Wolfgang Denk
ba73060cf4 board/esd/common/flash.c: Fix compile warning
Fix warning: ../common/flash.c:635: warning: dereferencing type-punned
pointer will break strict-aliasing rules

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Cc: Stefan Roese <sr@denx.de>
Acked-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Acked-by: Stefan Roese <sr@denx.de>
2009-09-15 00:12:31 +02:00
Wolfgang Denk
2d6d9f0848 sk98lin: fix compile warnings
Fix warnings:
skge.c: In function 'BoardInitMem':
skge.c:1389: warning: dereferencing type-punned pointer will break strict-aliasing rules
skge.c:1390: warning: dereferencing type-punned pointer will break strict-aliasing rules
skge.c:1391: warning: dereferencing type-punned pointer will break strict-aliasing rules
skgesirq.c: In function 'SkGePortCheckUpXmac':
skgesirq.c:1301: warning: dereferencing type-punned pointer will break strict-aliasing rules
skgesirq.c:1301: warning: dereferencing type-punned pointer will break strict-aliasing rules
skgesirq.c:1398: warning: dereferencing type-punned pointer will break strict-aliasing rules
skgesirq.c:1398: warning: dereferencing type-punned pointer will break strict-aliasing rules
skrlmt.c: In function 'SkRlmtInit':
skrlmt.c:661: warning: dereferencing type-punned pointer will break strict-aliasing rules
skxmac2.c: In function 'SkMacPromiscMode':
skxmac2.c:753: warning: dereferencing type-punned pointer will break strict-aliasing rules
skxmac2.c:753: warning: dereferencing type-punned pointer will break strict-aliasing rules
skxmac2.c: In function 'SkMacHashing':
skxmac2.c:803: warning: dereferencing type-punned pointer will break strict-aliasing rules
skxmac2.c:803: warning: dereferencing type-punned pointer will break strict-aliasing rules
skxmac2.c: In function 'SkMacFlushTxFifo':
skxmac2.c:1115: warning: dereferencing type-punned pointer will break strict-aliasing rules
skxmac2.c:1115: warning: dereferencing type-punned pointer will break strict-aliasing rules
skxmac2.c: In function 'SkMacFlushRxFifo':
skxmac2.c:1145: warning: dereferencing type-punned pointer will break strict-aliasing rules
skxmac2.c:1145: warning: dereferencing type-punned pointer will break strict-aliasing rules
skxmac2.c: In function 'SkXmInitPauseMd':
skxmac2.c:1987: warning: dereferencing type-punned pointer will break strict-aliasing rules
skxmac2.c:1987: warning: dereferencing type-punned pointer will break strict-aliasing rules
skxmac2.c: In function 'SkXmOverflowStatus':
skxmac2.c:4236: warning: dereferencing type-punned pointer will break strict-aliasing rules
skxmac2.c:4236: warning: dereferencing type-punned pointer will break strict-aliasing rules
skxmac2.c:4242: warning: dereferencing type-punned pointer will break strict-aliasing rules
skxmac2.c:4242: warning: dereferencing type-punned pointer will break strict-aliasing rules

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Ben Warren <biggerbadderben@gmail.com>
2009-09-15 00:11:48 +02:00
Wolfgang Denk
3708e4cdb1 drivers/net/natsemi.c: fix compile warning
Fix warning: natsemi.c:757: warning: dereferencing type-punned pointer
will break strict-aliasing rules

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Ben Warren <biggerbadderben@gmail.com>
2009-09-15 00:11:02 +02:00
Michal Simek
78d19a3987 net: emaclite: Cleanup license to be GPL compatible
Signed-off-by: Stephen Neuendorffer <stephen.neuendorffer@xilinx.com>
Signed-off-by: Michal Simek <monstr@monstr.eu>
2009-09-14 14:40:04 +02:00
Michal Simek
0900bee9ab microblaze: Enable hush parser
With Hush parser is possible to change command line in dtb

Signed-off-by: Michal Simek <monstr@monstr.eu>
2009-09-14 14:40:04 +02:00
Michal Simek
13916abf99 microblaze: Remove AtmarkTechno Suzaku board
Users should use microblaze-generic platform.
This platform is longer not supported.

Signed-off-by: Michal Simek <monstr@monstr.eu>
2009-09-14 14:40:04 +02:00
Michal Simek
3ceba1d45d net: Remove old Xilinx Emac driver
Signed-off-by: Michal Simek <monstr@monstr.eu>
2009-09-14 14:40:03 +02:00
Michal Simek
2fddd44464 microblaze: Short size of global data and fix malloc size
If is full malloc area global, data are rewrite because
there was bad size of malloc area.

Signed-off-by: Michal Simek <monstr@monstr.eu>
2009-09-14 14:40:03 +02:00
Michal Simek
aedb468309 microblaze: Add sbss, scommon and COMMON symbols for clearing
Signed-off-by: Michal Simek <monstr@monstr.eu>
2009-09-14 14:40:03 +02:00
Dirk Eibach
4c1883670a ppc4xx: Rename compactcenter to intip
Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2009-09-11 10:37:47 +02:00
Stefan Roese
d1c3b27525 ppc4xx: Big cleanup of PPC4xx defines
This patch cleans up multiple issues of the 4xx register (mostly
DCR, SDR, CPR, etc) definitions:

- Change lower case defines to upper case (plb4_acr -> PLB4_ACR)
- Change the defines to better match the names from the
  user's manuals (e.g. cprpllc -> CPR0_PLLC)
- Removal of some unused defines

Please test this patch intensive on your PPC4xx platform. Even though
I tried not to break anything and tested successfully on multiple
4xx AMCC platforms, testing on custom platforms is recommended.

Signed-off-by: Stefan Roese <sr@denx.de>
2009-09-11 10:35:58 +02:00
Wolfgang Denk
d8d8724be0 net/bootp.c: fix compile warning
Fix warning: bootp.c:695: warning: dereferencing type-punned pointer
will break strict-aliasing rules

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Ben Warren <biggerbadderben@gmail.com>
2009-09-11 10:10:12 +02:00
Wolfgang Denk
51003b8981 kwbimage.c: Fix compile warning when building on 64 bit systems
Fix this warning when building on 64 bit systems:
tools/kwbimage.c: In function 'kwbimage_checksum32':
tools/kwbimage.c:135: warning: format '%d' expects type 'int',
but argument 4 has type 'long unsigned int'

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
2009-09-11 09:11:03 +02:00
Marcel Ziswiler
e7963772eb muas3001: remove BRG clock node fixup to use common mpc8260 code.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@noser.com>
Acked-by: Heiko Schocher <hs@denx.de>
2009-09-10 23:11:50 +02:00
Marcel Ziswiler
c7c1dbbf71 r7780mp: fix typo in Ethernet chip model number comment.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@noser.com>
2009-09-10 23:11:03 +02:00
Marcel Ziswiler
45f89f340b ep8248: add support for device tree and secondary Ethernet interface.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@noser.com>
2009-09-10 23:08:48 +02:00
Prafulla Wadaskar
aa0c7a86cd mkimage: Add Kirkwood Boot Image support (kwbimage)
This patch adds support for "kwbimage" (Kirkwood Boot Image)
image types to the mkimage code.

For details refer to docs/README.kwbimage

This patch is tested with Sheevaplug board

Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
Acked-by: Ron Lee <ron@debian.org>

Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
2009-09-10 22:58:48 +02:00
Prafulla Wadaskar
7809fbb9aa Kirkwood: Sheevaplug: Add kwimage configuration file
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
2009-09-10 22:58:48 +02:00
Prafulla Wadaskar
b029dddc9a mkimage: Make table_entry code global
- make get_table_entry_id() global
- make get_table_entry_name() global
- move struct table_entry to image.h

Currently this code is used by image.c only.

This patch makes this API global so it can be used by other parts of
code, too.

Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
Acked-by: Ron Lee <ron.debian.org>

Edit comments and commit message.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-09-10 22:58:48 +02:00
Prafulla Wadaskar
f666dea8ab mkimage: Make genimg_print_size() global
Currently it is used by image.c only, but the the function can be
used to support additional mkimage types like for example kwbimage,
so make this function globally visible.

Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>

Edited commit message.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-09-10 22:58:48 +02:00
Prafulla Wadaskar
37b801888c mkimage: Include missing files in build dependency calculations
Include default_image.o and fit_image.o into the build dependency
calculations. This makes sure they get rebuilt if any of the headers
they include are modified

Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
Acked-by: Ron Lee <ron@debian.org>

Edited commit message.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-09-10 22:58:48 +02:00
Wolfgang Denk
3a2003f61e tools/mkimage: fix compiler warnings, use "const"
This fixes some compiler warnings:
tools/default_image.c:141: warning: initialization from incompatible pointer type
tools/fit_image.c:202: warning: initialization from incompatible pointer type
and changes to code to use "const" attributes in a few places where
it's appropriate.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-09-10 22:58:48 +02:00
Prafulla Wadaskar
89a4d6b12f tools: mkimage: split code into core, default and FIT image specific
This is a first step towards reorganizing the mkimage code to make it
easier to add support for additional images types. Current mkimage
code is specific to generating uImage and FIT image files, but the
same framework can be used to generate other image types like
Kirkwood boot images (kwbimage-TBD). For this, the mkimage code gets
reworked:

Here is the brief plan for the same:-
a) Split mkimage code into core and image specific support
b) Implement callback functions for image specific code
c) Move image type specific code to respective C files
       Currently there are two types of file generation/list
       supported (i.e uImage, FIT), the code is abstracted from
       mkimage.c/.h and put in default_image.c and fit_image.c;
       all code in these file is static except init function call
d) mkimage_register API is added to add new image type support
All above is addressed in this patch
e) Add kwbimage type support to this new framework (TBD)
This will be implemented in a following commit.

Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
Edit commit message, fix coding style and typos.
Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-09-10 22:58:48 +02:00
Prafulla Wadaskar
449609f5b1 tools: mkimage: Fixed build warnings
uninitialized retval variable warning fixed
crc32 APIs moved to crc.h (newly added) and build warnings fixed

Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-09-10 22:58:47 +02:00
Prafulla Wadaskar
14821d7dea tools: mkimage: Makefile sorted
The tools/Makefile is sorted for all entries,

Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
2009-09-10 22:58:47 +02:00
Prafulla Wadaskar
f7644c0bf3 tools: mkimage : bugfix returns correct value for list command
List command always return "EXIT_SUCCESS" even in case of
failure by any means.

This patch return 0 if list command is sucessful,
returns negative value reported by check_header functions

Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-09-10 22:58:47 +02:00
Mingkai Hu
511c02f611 mkconfig: pass the board name to board config file
Then we can handle different config targets in the board file, which
simplifies the top level Makefile for boards that have multiple
config targets.

Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
2009-09-10 22:56:55 +02:00
Wolfgang Denk
d640ac58db Remove "atmel_df_pow2" binary with "make clean"
Commit 65f6f07b added support for the atmel_df_pow2 standalone program
but missed to add a rule to remove it to the "clean" make target.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-09-10 22:47:43 +02:00
Stefan Roese
0b34dbbd0b ppc4xx: Fix compilation warning in 4xx miiphy.c
This patch fixes the following compilation warning:

miiphy.c: In function 'emac4xx_miiphy_read':
miiphy.c:353: warning: dereferencing type-punned pointer will break
strict-aliasing rules

Signed-off-by: Stefan Roese <sr@denx.de>
2009-09-10 14:38:17 +02:00
Matthias Fuchs
82379b5564 ppc4xx: Add CONFIG_PCI_4xx_PTM_OVERWRITE to some esd 4xx boards
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Signed-off-by: Stefan Roese <sr@denx.de>
2009-09-10 14:38:17 +02:00
Matthias Fuchs
99bcf14d55 ppc4xx: Allow overwriting pci target registers for all 4xx boards
This patch adds the CONFIG_PCI_4xx_PTM_OVERWRITE option and replaces
the ugly 'if defined(BOARD1) || ... || defined(BOARDn)' construct
in 4xx pci code.

When CONFIG_PCI_4xx_PTM_OVERWRITE is defined the default ptm register
setup can be overwritten through environment variables ptm1la, ptm1ms,
ptm2la and ptm2ms to do application specific pci target BAR configuration.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Signed-off-by: Stefan Roese <sr@denx.de>
2009-09-10 14:38:17 +02:00
Matthias Fuchs
cfab2ae322 ppc4xx: Fix PMC405DE support
This patch fixes PMC405DE support. Patch 85d6bf0b fixed out-of-tree
building for this board but the loadpci object did not get linked
after that.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Signed-off-by: Stefan Roese <sr@denx.de>
2009-09-10 14:38:17 +02:00
Detlev Zundel
c8355b9d9f amcc-common.h: Use filenames from environment variables for update procedure.
Using a separate "u-boot" environment variable allows to easily
specify different filenames for the update procedure.  This is also in
line with many other board configurations defining an "update" script.

Signed-off-by: Detlev Zundel <dzu@denx.de>
Acked-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2009-09-10 14:38:17 +02:00
Kumar Gala
6c97a20d0b ppc/85xx: Introduce RESET_VECTOR_ADDRESS to handle non-standard link address
Some board ports place TEXT_BASE at a location that would cause the
RESET_VECTOR_ADDRESS not to be at 0xfffffffc when we link.  By default
we assume RESET_VECTOR_ADDRESS will be 0xfffffffc if the board doesn't
explicitly set it.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Wolfgang Denk <wd@denx.de>
2009-09-09 21:04:47 -05:00
Kumar Gala
c348322ac7 ppc/85xx: Clean up do_reset
There is no reason to do a run time check for e500 v1 based cores to
determine if we have the GUTs RSTCR facility.  Only the first generation
of PQ3 parts (MPC8540/41/55/60) do not have it.  So checking to see if
we are e500 v2 would miss future parts (like e500mc).

Just change this to be ifdef'd based on CONFIG_MPC85{40,41,55,60}.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-08 13:47:18 -05:00
Poonam Aggrwal
21170c80a8 ppc/85xx/86xx: Bug fix: call to puts in probecpu() moved to checkcpu().
While in probecpu() UART is still not initialized.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-08 09:10:08 -05:00
Poonam Aggrwal
f8027f6b47 ppc/85xx/86xx: Device tree fixup for number of cores
Fixing the number of cores in the device tree based on the actual number of
cores on the system.  With this same device tree image can be used for dual
core and single core members of otherwise exactly same SOC.

For example:
* P2020RDB and P2010RDB
* P1020RDB and P1011RDB
* MPC8641D and MPC8641

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-08 09:10:08 -05:00
Poonam Aggrwal
58442dc01e ppc/85xx,86xx: Handling Unknown SOC version
Incase the system is detected with Unknown SVR, let the system boot
with a default value and a proper message.

Now with dynamic detection of SOC properties from SVR, this is necessary
to prevent a crash.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-08 09:10:08 -05:00
Kumar Gala
3e7b6c1f2d ppc/8xxx: Refactor code to determine if PCI is enabled & agent/host
Refactor the code into a simple bitmask lookup table that determines if
a given PCI controller is enabled and if its in host/root-complex or
agent/end-point mode.

Each processor in the PQ3/MPC86xx family specified different encodings
for the cfg_host_agt[] and cfg_IO_ports[] boot strapping signals.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-08 09:10:07 -05:00
Kumar Gala
5052a771cf ppc/85xx: Cleanup makefile and related optional files
Cleaned up cpu/mpc85xx/Makefile to use CONFIG_* for those obvious cases
we have like PCI, CPM2, QE.  Also reworked it to use one line per file
for everything and sorted in alphabetical order.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-08 09:10:07 -05:00
Timur Tabi
74c5dfd81f fsl: add register read-back to set_law()
After programming a new LAW, we should read-back the LAWAR register so that
we sync the writes.  Otherwise, code that attempts to use the new LAW-mapped
memory might fail right away.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-08 09:10:06 -05:00
Kumar Gala
c725908681 ppc/85xx: Fix bug in setup_mp code
Its possible that we try and copy the boot page code out of flash into a
DDR location that doesn't have a TLB cover it.  For example, if we have
3G of DDR we typically only map the first 2G.  In the cases of 4G+ this
wasn't an issue since the reset page TLB mapping covered the last page
of memory which we wanted to copy to.

We now change the physical address of the reset page TLB to map to the
true physical location of the boot page code, copy and than set the
TLB back to its 1:1 mapping of the reset page.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-08 09:10:06 -05:00
Kumar Gala
c2287af155 ppc/85xx: Add a simple function to search the TLB
Allow us to search the TLB array based on an address.  This is useful
if we want to change an entry but dont know where it happens to be
located.

For example, the boot page mapping we use on MP or the flash TLB that
we change the WIMGE settings for after we've relocated.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-08 09:10:05 -05:00
Kumar Gala
26f4cdba6b 85xx: Add support for setting IVORs to fixed offset defaults
In future Book-E implementations IVORs will most likely go away and be
replaced with fixed offsets.  The IVPR will continue to exist to allow
for relocation of the interrupt vectors.

This code adds support to setup the IVORs as their fixed offset values
per the ISA 2.06 spec when we transition from u-boot to another OS
either via 'bootm' or a cpu release.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-08 09:10:05 -05:00
Dipen Dudhat
da1cd955df ppc/85xx: Fix up eSDHC controller clock frequency in the device tree
Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-08 09:10:04 -05:00
Kumar Gala
2abbd31da6 ppc/8xxx: Remove ddr_pd_cntl register since it doesn't exist
The ddr_pd_cntl isn't defined in any reference manual and thus we wil
remove especially since we set it to 0, which would most likely be its
POR value.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-08 09:10:04 -05:00
Kumar Gala
13d46ab257 ppc/8xxx: relocate cpu pointer in global data
Now that we have a pointer to the cpu struct we need to relocate it once
we get into ram.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-08 09:10:04 -05:00
Anton Vorontsov
9c671e7062 fsl: sys_eeprom: Fix 'may be used uninitialized' warning
The warning is bogus, so silence it by initializing the 'ret' variable.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Acked-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-08 09:10:03 -05:00
Dipen Dudhat
6b9ea08c50 ppc/85xx: Use CONFIG_FSL_ESDHC to enable sdhc clk
Enable eSDHC Clock based on generic CONFIG_FSL_ESDHC define instead of a
platform define.  This will enable all the 85xx platforms to use sdhc_clk
based on CONFIG_FSL_ESDHC.

Signed-off-by: Gao Guanhua <B22826@freescale.com>
Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-08 09:10:02 -05:00
Wolfgang Denk
0052a051f6 Merge branch 'master' of git://git.denx.de/u-boot-i2c 2009-09-07 23:20:04 +02:00
Wolfgang Denk
3ea43ff773 Merge branch 'master' of git://git.denx.de/u-boot-arm 2009-09-07 23:12:46 +02:00
Timur Tabi
92477a631b fsl_i2c: increase I2C timeout values and make them configurable
The value of I2C_TIMEOUT in fsl_i2c.c has several problems.  First, it is
defined as CONFIG_HZ/4, but it is used as a count of microseconds, so it makes
no sense to derive it from a clock rate.  Second, the current value (250) is
too low for some boards, so it needs to be increased.  Third, the timeout
necessary for multiple-master arbitration is larger than the timeout for basic
read/write operations, so we shouldn't have a single constant for both timeouts.
Finally, it would be nice if we could override these values on a per-board
basis.

Signed-off-by: Timur Tabi <timur@freescale.com>
Acked-by: Wolfgang Denk <wd@denx.de>
Tested-by: Peter Tyser <ptyser@xes-inc.com>
Acked-by: Peter Tyser <ptyser@xes-inc.com>
2009-09-06 11:26:05 +02:00
Eric Millbrandt
5da71efa18 Reset i2c slave devices during init on mpc5xxx cpus
Reset any i2c devices that may have been interrupted during a system reset.
Normally this would be accomplished by clocking the line until SCL and SDA
are released and then sending a start condtiion (From an Atmel datasheet).
There is no direct access to the i2c pins so instead create start commands
through the i2c interface.  Send a start command then delay for the SDA Hold
time, repeat this by disabling/enabling the bus a total of 9 times.

Signed-off-by: Eric Millbrandt <emillbrandt@dekaresearch.com>
2009-09-06 11:26:04 +02:00
Sandeep Paulraj
2d4072c06b ARM: DaVinci: Adding Support for DaVinci DM365 EVM
This patch adds support for the DM365 EVM.
It has been tested on a DM365 EVM.

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2009-09-05 13:48:43 +02:00
Sandeep Paulraj
cf463091bc ARM: DaVinci: DaVinci DM365 SOC specific code
This patch adds support for DaVinci DM365 SOC.

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2009-09-05 13:48:07 +02:00
Ilko Iliev
e830b66b35 DM9000 init for pm9261
Signed-off-by: Ilko Iliev <iliev@ronetix.at>
2009-09-05 02:58:42 +02:00
Frederik Kriewitz
c35d7cf071 Add support for the DevKit8000 board
This patch adds support for the DevKit8000 board.

Signed-off-by: Frederik Kriewitz <frederik@kriewitz.eu>
2009-09-05 01:33:14 +02:00
Jean-Christophe PLAGNIOL-VILLARD
127f9ae575 omap3: move the other boards to board/
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2009-09-05 01:33:12 +02:00
Jean-Christophe PLAGNIOL-VILLARD
350f3ac573 arm: move Logicpd's boards to board/logicpd/
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2009-09-05 01:33:11 +02:00
Jean-Christophe PLAGNIOL-VILLARD
0a0e4bad96 omap: move TI's boards to board/ti/
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2009-09-05 01:33:09 +02:00
Wolfgang Denk
9f23ca42b3 ARM: Update mach-types
Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-09-04 23:20:29 +02:00
Mike Frysinger
262ae0a619 push LOAD_ADDR out to arch mk files
Rather than maintain/extend the current ifeq($(ARCH)) mess that exists in
the standalone Makefile, push the setting up of LOAD_ADDR out to the arch
config.mk (and rename to STANDALONE_LOAD_ADDR in the process).  This keeps
the common code clean and lets the arch do whatever crazy crap it wants in
its own area.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-09-04 23:06:34 +02:00
Giuseppe CONDORELLI
7662eb2b9d zlib: fix code when DEBUG is defined
Removed stdio.h inclusion and moved trace macros to use printf avoiding to
write debug informations to standard error.

Signed-off-by: Giuseppe Condorelli <giuseppe.condorelli@st.com>
2009-09-04 23:04:20 +02:00
Scott Wood
cfcbf8c4cf mxc_nand: Remove Freescale's "All Rights Reserved."
Signed-off-by: Scott Wood <scottwood@freescale.com>
2009-09-04 23:03:10 +02:00
Anton Vorontsov
001d615681 mpc83xx/serdes: License cleanup: remove "All Rights Reserved" notice
"All Rights Reserved" conflicts with the GPL.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
2009-09-04 23:02:04 +02:00
Wolfgang Denk
46ff6d4613 License cleanup: remove unintended "All Rights Reserved" notices.
Some files included my old standerd file header which had a "All
Rights Reserved" part. As this has never been my intention, I remove
these lines to make the files compatible with GPL v.2 and later.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-09-04 23:00:56 +02:00
Wolfgang Denk
37daa77f3c cmd_mtdparts.c: fix compiler warning in debug code
Fix warning messages:
cmd_mtdparts.c:1429: warning: format '%08lx' expects type 'long
unsigned int', but argument 6 has type 'u32'
cmd_mtdparts.c:1429: warning: format '%08lx' expects type 'long
unsigned int', but argument 7 has type 'u32'

Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-09-04 22:58:57 +02:00
Anton Vorontsov
d8bc55a6fb Move uninitialized_var() macro from ubi_uboot.h to compiler.h
This is needed so that we could use this macro for non-UBI code.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
2009-09-04 22:16:40 +02:00
Kumar Gala
d72871e138 arm: Remove -fno-strict-aliasing
-fno-strict-aliasing is hidding warnings.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-04 22:15:53 +02:00
Kumar Gala
d6281ff0cc ppc: Remove -fno-strict-aliasing
-fno-strict-aliasing is hidding warnings.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-04 22:15:48 +02:00
Eric Millbrandt
795d246c27 galaxy5200: Add chip select region for an Epson S1D15313
Signed-off-by: Eric Millbrandt <emillbrandt@dekaresearch.com>
2009-09-04 22:12:38 +02:00
Kumar Gala
3dfad40a04 Add ability for arch code to make changes before we boot
Added a arch_preboot_os() function that cpu specific code can implement to
allow for various modifications to the state of the machine right before
we boot.  This can be useful to setup register state to a specific
configuration.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-04 22:11:23 +02:00
Roy Zang
9ea005fb44 Use different PBA value for E1000 PCI and PCIe cards
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Acked-by: Andr Schwarz <andre.schwarz@matrix-vision.de>
2009-09-04 22:03:02 +02:00
Graeme Russ
5b34a296d4 Add PCI support to eNET board
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2009-09-04 21:57:50 +02:00
Graeme Russ
f50b619d9c i386: Moved PCI from #ifdef to conditional compile for sc520 boards
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2009-09-04 21:57:22 +02:00
Graeme Russ
ed7a1b681d i386: Replace [read, write]_mmcr_[byte, word, long] with memory mapped structure
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2009-09-04 21:56:45 +02:00
Graeme Russ
9b32f96b5b Misc sc520 cdp fixups
Now that the PCI, SATA et al compile problems have been resolved, the
cludge that was applied to avoid them can be removed

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2009-09-04 21:55:57 +02:00
Graeme Russ
91ee4e183c Fixup sc520_spunk board
Primary intent is to resolve build errors for this board which has been
neglected for a very long time. I do not have one of these boards, so I
cannot test functionality

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2009-09-04 21:55:17 +02:00
Graeme Russ
8907b8dbc5 Misc ds1722 fixups
This patch is based on a patch submitted by Jean-Christophe PLAGNIOL-VILLARD
on 18th May 2008 as part of a general i386 / sc520 fixup which was never
applied

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2009-09-04 21:54:52 +02:00
Graeme Russ
a92510e7fa Misc ti_pci1410a fixups
Removed do_pinit() - now declared in cmd_pcmcia.c

Added #define CONFIG_CMD_PCMCIA around pcmcia_off() in line with other
PCMCIA drivers

signed/unsigned type fixups

Added semi-colon after default: label as required by newer gcc

The only board that appears to use this driver is the sc520_spunk which
is very old and very likely very broken anyway. I do not have one to test
whether this patch breaks anything functionaly, I have can only check
that it compiles without warning or error

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2009-09-04 21:54:04 +02:00
Graeme Russ
31b9ab33d9 Misc SATA fixups
Cast first parameter to sata_cpy()

In /drivers/block/ata_piix.h, ata_id_has_lba48(), ata_id_has_lba(),
ata_id_has_dma(), ata_id_u32(), ata_id_u64() are all defined in
include/libata.h which is included in ata.h which is included by all files
which include ata_piix.h (only ata_piix.c) so these definitions are
supurflous to (and conlict with) this in libata.h. Interestingly, my
compiler complains about ata_id_u64 already being defined, but not
ata_id_u32

ata_dump_id() is defined in include/libata.h and should not be static
(maybe should even use ata_dump_id() in libata.c

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2009-09-04 21:53:37 +02:00
Graeme Russ
d754902409 i386: Misc PCI fixups
Change PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY (Originally done in
commit ff4e66e93c, regressed by commit 6d7f610b09)

Cast PCI_ROM_ADDRESS_MASK to u32

Wrap probe_pci_video() call inside #ifdef CONFIG_VIDEO

Change call to pci_find_class() to pci_find_devices(). This is based on a
patch submitted on 1st March 2007 (Patch that fixes the compilation errors
for sc520_cdp board) by mushtaq_k

This patch requires that PCI_VIDEO_VENDOR_ID and PCI_VIDEO_DEVICE_ID be
specified in the board config file.  Dummy values have been added for the
SC520 CDP board to enable compilation, but since I do not have one of these,
I do know what the values should be

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2009-09-04 21:52:52 +02:00
Graeme Russ
04ff9ab158 Fix sc520 timer interrupt generation
The current implementation has the timer being started before the interrupt
handler is installed. It the interrupt occurs before the handler is
installed, the timer interrupt is never reset and the timer stops

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2009-09-04 21:51:56 +02:00
Graeme Russ
f3a8d6b29b Fix environment configuration for eNET board
The current configuration of the Environment has the redundant copy of the
environment in the Boot Flash - This was never the intent. The Environment
should instead be in the first two sectors of the first Strata Flash

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2009-09-04 21:51:22 +02:00
Graeme Russ
ea0c37798c i386: Fix regression introduced by commit 8c63d47651
A local variable was deleted that should not have been

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2009-09-04 21:50:18 +02:00
Graeme Russ
cfb3a736ff i386: Change inline asm global symbols to local
gcc 4.3.2 optimiser creates multiple copies of inline asm (who knows why)
Remove use of global names for labels to prevent 'symbol already defined'
errors

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2009-09-04 21:49:48 +02:00
Graeme Russ
a3ab8caee6 i386: Add errno.h
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2009-09-04 21:49:19 +02:00
Peter Tyser
d4e8ada0f6 Consolidate arch-specific mem_malloc_init() implementations
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2009-09-04 21:47:07 +02:00
Peter Tyser
a483a167bc Standardize mem_malloc_init() implementation
This lays the groundwork to allow architectures to share a common
mem_malloc_init().

Note that the x86 implementation was not modified as it did not fit the
mold of all other architectures.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2009-09-04 21:46:32 +02:00
Peter Tyser
5e93bd1c9a Consolidate arch-specific sbrk() implementations
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2009-09-04 21:45:39 +02:00
Mike Frysinger
65f6f07b72 atmel_df_pow2: standalone to convert dataflashes to pow2
Atmel DataFlashes by default operate with pages that are slightly bigger
than normal binary sizes (i.e. many are 1056 byte pages rather than 1024
bytes).  However, they also have a "power of 2" mode where the pages show
up with the normal binary size.  The latter mode is required in order to
boot with a Blackfin processor, so many people wish to convert their
DataFlashes on their development systems to this mode.  This standalone
application does just that.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-09-04 21:31:30 +02:00
Mike Frysinger
cb95c7a935 Blackfin: cm-bf548: fix device->stdio_dev fallout
The recent 52cb4d4fb3 commit which renamed device to stdio_dev missed the
cm-bf548's video board.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-09-02 05:58:39 -04:00
Mike Frysinger
c7bcdde46a Blackfin: enable 64bit printf for nand
Since the NAND code now uses 64bit code, make sure we enable support for
ADI Blackfin boards in printf to avoid the warning:
nand_util.c:45:2: warning: #warning Please define CONFIG_SYS_64BIT_VSPRINTF for correct output!

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-09-02 05:58:39 -04:00
Mike Frysinger
9c46e71af2 Blackfin: use scratch pad for exception stack
If the memory layout pushes the stack out of the default DCPLB coverage,
the exception handler may trigger a double fault by trying to push onto
the uncovered stack.  So handle the exception stack similar to the kernel
by using the top of the scratch pad SRAM.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-09-02 05:58:38 -04:00
Mike Frysinger
69a25ce357 Blackfin: increase default console size
The default console size indirectly applies to length of env vars, so a
smaller length makes it hard to pass longer command lines to kernels.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-09-02 05:58:38 -04:00
Mike Frysinger
f541e1d6d9 Blackfin: fix debug printf modifiers
The display_global_data() function generated warnings with pretty much
every variable.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-09-02 05:58:38 -04:00
Harald Krapfenbauer
4640c2b869 Blackfin: cm-bf537u: new board port
The CM-BF537U is similar to the CM-BF537E module, but enough to need its
own board port.

Signed-off-by: Harald Krapfenbauer <Harald.Krapfenbauer@bluetechnix.at>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-09-02 05:58:37 -04:00
Robin Getz
c4db335c2e Blackfin: change global data register from P5 to P3
Since the Blackfin ABI favors higher scratch registers by default, use the
last scratch register (P3) for global data rather than the first (P5).
This allows the compiler's register allocator to use higher number scratch
P registers, which in turn better matches the Blackfin instruction set,
which reduces the size of U-Boot by more than 1024 bytes...

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-09-02 05:14:02 -04:00
Robin Getz
574b70df03 Blackfin: enable more network commands for ADI dev boards
Add dns and ntp to default networking commands, and ask for more dhcp
options to better configure the network environment.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-09-02 05:14:02 -04:00
Michael Hennerich
aa7b248a05 Blackfin: bf537-stamp: comment CF-Flash Card Support better
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-09-02 05:14:01 -04:00
Robin Getz
69c6d268a2 Blackfin: use +(filesize) to make sure we are only doing what is necessary
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-09-02 04:10:30 -04:00
Albin Tonnerre
2dc851e3b0 Support for the Calao TNY-A9260/TNY-A9G20 boards
The Calao TNY-A9260 and TNY-9G20 are boards manufactured and sold by
Calao Systems <http://www.calao-systems.com>. Their components are very
similar to the AT91SAM9260EK board, so their configuration is based on
the configuration of this board. There are however some differences:
different clocks, no LCD, no ethernet. They also can use SPI EEPROM to
store the environment.

Signed-off-by: Albin Tonnerre <albin.tonnerre@free-electrons.com>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2009-09-01 22:35:58 +02:00
Prafulla Wadaskar
49d2cb4d61 arm: Kirkwood: add SYSRSTn Duration Counter Support
This feature can be used to trigger special command "sysrstcmd" using
reset key long press event and environment variable "sysrstdelay" is set
(useful for reset to factory or manufacturing mode execution)

Kirkwood SoC implements a hardware-based SYSRSTn duration counter.
When SYSRSTn is asserted low, a SYSRSTn duration counter is running.
The counter value is stored in the SYSRSTn Length Counter Register
The counter is based on the 25-MHz reference clock (40ns)
It is a 29-bit counter, yielding a maximum counting duration of
2^29/25 MHz (21.4 seconds). When the counter reach its maximum value,
it remains at this value until counter reset is triggered by setting
bit 31 of KW_REG_SYSRST_CNT

Implementation:
Upon long reset assertion (> ${sysrstdelay} in secs) sysrstcmd will be
executed if pre-defined in environment variables.
This feature will be disabled if "sysrstdelay" variable is unset.

for-ex.
setenv sysrst_cmd "echo starting factory reset;
		   nand erase 0xa0000 0x20000;
		   echo finish ed sysrst command;"
will erase particular nand sector if triggered by this event

Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
2009-09-01 22:34:03 +02:00
Albin Tonnerre
9453967e28 Add support for the Calao SBC35-A9G20 board
The Calao SBC35-A9G20 board is manufactured and sold by Calao Systems
<http://www.calao-systems.com>. It is built around an AT91SAM9G20 ARM SoC
running at 400MHz. It features an Ethernet port, an SPI RTC backed by an onboard
battery , an SD/MMC slot, a CompactFlash slot, 64Mo of SDRAM, 256Mo of NAND
flash, two USB host ports, and an USB device port. More informations can be
found at <http://www.calao-systems.com/articles.php?lng=en&pg=5936>

Signed-off-by: Albin Tonnerre <albin.tonnerre@free-electrons.com>
2009-09-01 22:13:37 +02:00
Ilya Yanok
10bc241dfc imx27lite: add support for imx27lite board from LogicPD
This patch adds support for i.MX27-LITEKIT development board from
LogicPD. This board uses i.MX27 SoC and has 2MB NOR flash, 64MB NAND
flash, FEC ethernet controller integrated into i.MX27.

Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Acked-by: Wolfgang Denk <wd@denx.de>
2009-09-01 22:10:55 +02:00
Albin Tonnerre
50b5fff558 at91sam9260/afeb9260: Fix SPI initialization
Commit 7ebafb7ec1 introduced a mistake in the spi
init function call for those boards. This patch fixes this.

Signed-off-by: Albin Tonnerre <albin.tonnerre@free-electrons.com>
2009-09-01 22:10:10 +02:00
Simon Kagstrom
f3d4f8870e Remove duplicate set_cr
Remove duplicate set_cr

set_cr is defined in both asm-arm/proc-armv/system.h and
include/asm-arm/system.h. This patch removes it (and some duplicate
defines) from the former.

Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
2009-09-01 22:08:46 +02:00
Wolfgang Denk
3aa8b68d80 Merge branch 'next' of ../next 2009-08-31 22:21:47 +02:00
Timur Tabi
2d04db088e fsl: simplify the "mac id" command, improve boot-time informational message
The "mac id" command took a 4-character parameter as the identifier string.
However, for any given board, only one kind of identifier is acceptable, so it
makes no sense to ask the user to type it in.  Instead, if the user enters
"mac id", the identifier (and also the version, if it's NXID) will
automatically be set to the correct value.

Improve the message that is displayed when EEPROM is read during boot.  It now
displays "EEPROM:" and then either an error message or the EEPROM identifier
if successful.

If the identifier in EEPROM is valid, then always reject a bad CRC, even if the
CRC field has not been initialized.

Don't force the MAC address count to MAX_NUM_PORTS or less.  Forcing the value
to be changed resulting in an in-memory copy that does not match what's in
hardware, even though the user did not request that change.

Finally, always update the CRC value in the in-memory copy after any field
is changed, so that the CRC is always correct.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-28 17:12:52 -05:00
Poonam Aggrwal
33f3f34255 85xx: Added PCIe support for P1 P2 RDB
Call fsl_pci_init_port() to initialize all the PCIe ports on the board.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-28 17:12:46 -05:00
Poonam Aggrwal
0d3d68b25a driver/fsl_pci: Add fsl_pci_init_port function to initialize a PCI controller
fsl_pci_init_port can be called from board specific PCI initialization
routines to setup the PCI (or PCIe) controller.  This will reduce code
redundancy in most of the 85xx/86xx FSL board ports that setup PCI.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-28 17:12:43 -05:00
Timur Tabi
05f6f66474 85xx: Improve MPIC initialization
The MPIC initialization code for Freescale e500 CPUs was not using I/O
accessors, and it was not issuing a read-back to the MPIC after setting
mixed mode.  This may be the cause of a spurious interrupt on some systems.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-28 17:12:43 -05:00
Poonam Aggrwal
c17b79fbd0 85xx: Added support for P1011RDB and P2010RDB
P1011 and P2010 are single core variants of P1010 and P2020 respectively.
The board(RDB) will be same.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-28 17:12:42 -05:00
Poonam Aggrwal
a713ba926b 85xx: Added single core members of FSL P1xx/P2xx processors series
P1011 - Single core variant of P1020
P2010 - Single core variant of P2020

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-28 17:12:41 -05:00
Poonam Aggrwal
bf488bc094 85xx: P1020RDB Support Added
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-28 17:12:41 -05:00
Poonam Aggrwal
3b1f243b8d 85xx: Added CONFIG_MAX_CPUS for P1020
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-28 17:12:41 -05:00
Mingkai Hu
76b474e2f5 85xx: Add L2SRAM Register's macro definition
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-28 17:12:41 -05:00
Felix Radensky
158c6724c9 85xx: Fix memory test range on MPC8536DS
With current values of CONFIG_SYS_MEMTEST_START and CONFIG_SYS_MEMTEST_END
memory test hangs if run without arguments. Set them to sane values, so
that all available 512MB of RAM excluding exception vectors at the bottom
and u-boot code and stack at the top can be tested.

Signed-off-by: Felix Radensky <felix@embedded-sol.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-28 17:12:40 -05:00
Kumar Gala
ef41f2a25c 85xx: Removed BEDBUG support on P1_P2_RDB
To match all other 85xx platforms we are removing BEDBUG support.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-28 17:12:40 -05:00
Kumar Gala
b560ab85ed 85xx: Init pci ethernet cards if we enable any on MPC8572DS
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-28 17:12:40 -05:00
Peter Tyser
1bb61b69f7 xes: Use proper IO access functions
Also fix some minor whitespace oddities while we're cleaning up

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-28 17:12:39 -05:00
Kumar Gala
ec79d33b2c 85xx: Move to a common linker script
There are really no differences between all the 85xx linker scripts so
we can just move to a single common one.  Board code is still able to
override the common one if need be.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-28 17:12:39 -05:00
Poonam Aggrwal
87c7661b42 85xx: Added P1020 Processor Support.
P1020 is another member of QorIQ series of processors which falls in ULE
category. It is an e500 based dual core SOC.

Being a scaled down version of P2020 it has following differences:
- 533MHz - 800MHz core frequency.
- 256Kbyte L2 cache
- Ethernet controllers with classification capabilities.
Also the SOC is pin compatible with P2020

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-28 17:12:39 -05:00
Poonam Aggrwal
728ece343e 85xx: Add support for P2020RDB board
The code base adds P1 & P2 RDB platforms support.
The folder and file names can cater to future SOCs of P1/P2 family.
P1 & P2 processors are 85xx platforms, part of Freescale QorIQ series.

Tested following on P2020RDB:
1. eTSECs
2. DDR, NAND, NOR, I2C.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-28 17:12:38 -05:00
Poonam Aggrwal
0e870980a6 8xxx: Removed CONFIG_NUM_CPUS from 85xx/86xx
The number of CPUs are getting detected dynamically by checking the
processor SVR value.  Also removed CONFIG_NUM_CPUS references from all
the platforms with 85xx/86xx processors.

This can help to use the same u-boot image across the platforms.

Also revamped and corrected few Freescale Copyright messages.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-28 17:12:38 -05:00
Poonam Aggrwal
18bacc2027 8xxx: Refactored common cpu specific code for 85xx/86xx into one file.
Removed same code pieces from cpu/mpc85xx/cpu.c and cpu/mpc86xx/cpu.c
and moved to cpu/mpc8xxx/cpu.c(new file)

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-28 17:12:38 -05:00
Alex Dubov
7b18c227b8 stx: create common vendor/board hierarchy for STx boards
Move files belonging to the STx boards into common vendor directory and
update the Makefile to reflect this.

Signed-off-by: Alex Dubov <oakad@yahoo.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-28 17:12:38 -05:00
Peter Tyser
bafdf9aa9d 85xx: Remove unused CONFIG_CLEAR_LAW0 defines
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-28 17:12:37 -05:00
Kumar Gala
73aacc5228 86xx: Remove redudant PLATFORM_CPPFLAGS
For historic reasons we had defined some additional PLATFORM_CPPFLAGS like:

PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx=1
PLATFORM_CPPFLAGS += -DCONFIG_MPC8641=1

However these are all captured in the config.h and thus redudant.  Also
moved common 86xx flags into cpu/mpc86xx/config.mk.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-28 17:12:37 -05:00
Kumar Gala
53efa1f1ac 85xx: Remove redudant PLATFORM_CPPFLAGS
For historic reasons we had defined some additional PLATFORM_CPPFLAGS
like:

PLATFORM_CPPFLAGS += -DCONFIG_E500=1
PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
PLATFORM_CPPFLAGS += -DCONFIG_MPC8548=1

However these are all captured in the config.h and thus redudant.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-28 17:12:37 -05:00
Kumar Gala
337f9fde2e 85xx: Add a 36-bit physical configuration for MPC8536DS
We move all IO addressed (CCSR, localbus, PCI) above the 4G boundary
to allow for larger memory sizes.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Wolfgang Denk <wd@denx.de>

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-28 17:12:36 -05:00
Kumar Gala
ecead84d56 85xx: Cleanup whitespace in mpc8536ds.c
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-28 17:12:36 -05:00
Kumar Gala
ad19e7a5d2 pci/fsl_pci_init: Rework PCI ATMU setup to handle >4G of memory
The old PCI ATMU setup code would just mimic the PCI regions into the
ATMU registers.  For simple memory maps in which all memory, MMIO, etc
space fit into 4G this works ok.  However there are issues with we have
>4G of memory as we know can't access all of memory and we need to
ensure that PCICSRBAR (PEXCSRBAR on PCIe) isn't overlapping with
anything since we can't turn it off.

We first setup outbound windows based on what the board code setup
in the pci regions for MMIO and IO access.  Next we place PCICSRBAR
below the MMIO window.  After which we try to setup the inbound windows
to map as much of memory as possible.

On PCIe based controllers we are able to overmap the ATMU setup since
RX & TX links are separate but report the proper amount of inbound
address space to the region tracking to ensure there is no overlap.

On PCI based controllers we use as many inbound windows as available to
map as much of the memory as possible.

Additionally we changed all the CCSR register access to use proper IO
accessor functions.  Also had to add CONFIG_SYS_CCSRBAR_PHYS to some
86xx platforms that didn't have it defined.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-28 17:12:36 -05:00
Kumar Gala
8295b94400 pci/fsl_pci_init: Use PCIe capability to determine if controller is PCIe
Change the code to use the PCIe capabilities register to determine if we
are a PCIe controller or not.  Additionally cleaned up some white space
and formatting in the file.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-28 17:12:36 -05:00
Kumar Gala
cb151aa2cf pci/fsl_pci_init: Fold fsl_pci_setup_inbound_windows into fsl_pci_init
Every platform that calls fsl_pci_init calls fsl_pci_setup_inbound_windows
before it calls fsl_pci_init.  There isn't any reason to just call it
from fsl_pci_init and simplify things a bit.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-28 17:12:35 -05:00
Kumar Gala
fb3143b35e pci/fsl_pci_init: Fold pci_setup_indirect into fsl_pci_init
Every platform that calls fsl_pci_init calls pci_setup_indirect before
it calls fsl_pci_init.  There isn't any reason to just call it from
fsl_pci_init and simplify things a bit.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-28 17:12:35 -05:00
Wolfgang Denk
5928da0193 Merge branch 'next' of git://git.denx.de/u-boot-nand-flash into next 2009-08-28 00:17:41 +02:00
Sandeep Paulraj
77b351cd0f NAND: DaVinci: V2 Adding 4 BIT ECC support
This patch adds 4 BIT ECC support in the DaVinci NAND
driver. Tested on both the DM355 and DM365.

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2009-08-26 15:37:03 -05:00
Sandeep Paulraj
f83b7f9e8a MTD:NAND: ADD new ECC mode NAND_ECC_HW_OOB_FIRST
This patch adds the new mode NAND_ECC_HW_OOB_FIRST in the nand code to
support 4-bit ECC on TI DaVinci devices with large page (up to 2K) NAND
chips.  This ECC mode is similar to NAND_ECC_HW, with the exception of
read_page API that first reads the OOB area, reads the data in chunks,
feeds the ECC from OOB area to the ECC hw engine and perform any
correction on the data as per the ECC status reported by the engine.

This patch has been accepted by Andrew Morton and can be found at

http://userweb.kernel.org/~akpm/mmotm/broken-out/mtd-nand-add-new-ecc-mode-ecc_hw_oob_first.patch

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Sneha Narnakaje <nsnehaprabha@ti.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2009-08-26 15:37:03 -05:00
Ilya Yanok
36fab997d8 mxc_nand: add nand driver for MX2/MX3
Driver for NFC NAND controller found on Freescale's MX2 and MX3
processors. Ported from Linux. Tested only with i.MX27 but should
works with other MX2 and MX3 processors too.

Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2009-08-26 15:37:03 -05:00
Sandeep Paulraj
a2c65b47ef NAND: ADD page Parameter to all read_page/read_page_raw API's
This patch adds a new "page" parameter to all NAND read_page/read_page_raw
APIs.  The read_page API for the new mode ECC_HW_OOB_FIRST requires the
page information to send the READOOB command and read the OOB area before
the data area.

This patch has been accepted by Andrew Morton and can be found at
http://userweb.kernel.org/~akpm/mmotm/broken-out/mtd-nand-add-page-parameter-to-all-read_page-read_page_raw-apis.patch

WE would like this to become part of the u-boot GIT as well

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Sneha Narnakaje <nsnehaprabha@ti.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2009-08-26 15:37:02 -05:00
Heiko Schocher
de4250929f 83xx, kmeter1: added NAND support
Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2009-08-26 15:37:02 -05:00
Kyungmin Park
ecad289fc6 OneNAND: Remove unused read_spareram
Remove unused read_spareram and add unlock_all as kernel does

Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2009-08-26 15:37:02 -05:00
Matthias Kaehlcke
403ce1f759 KB9202: Add NAND support
Add KB9202 NAND driver

Signed-off-by: Matthias Kaehlcke <matthias@kaehlcke.net>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2009-08-26 15:37:01 -05:00
Kyungmin Park
ce3277a6f2 OneNAND: Remove unused read_spareram
Remove unused read_spareram and add unlock_all as kernel does

Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
2009-08-26 22:06:50 +02:00
Eric Millbrandt
0d042037b3 galaxy5200: Cleanup typo and trailing whitespace
Signed-off-by: Eric Millbrandt <emillbrandt@dekaresearch.com>
2009-08-26 21:33:27 +02:00
Wolfgang Denk
d7f4d14a8b Merge branch 'next' of git://www.denx.de/git/u-boot-coldfire into next 2009-08-26 21:29:32 +02:00
TsiChung Liew
f6a309080b ColdFire: Fix compile warning messages
Change %08lX to %08X in board.c. Remove unused variable
'oscillator' in mcf5227x/cpu_init.c and 'scm2' in
mcf532x/cpu_init.c. Provide argument type cast in
drivers/dma/MCD_dmaApi.c.

Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
2009-08-26 03:44:31 -05:00
TsiChung Liew
88c811b153 ColdFire: Fix missing _IO_BASE which caused compile error
The compile error was caused by a recent patch. Affected platforms -
M5253DEMO.h, M5253EVBE.h, and M54455EVB.h. Adding the _IO_BASE
automatically defined to 0 in asm-m68k/io.h if it isn't set in
platform configuration file.

Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
2009-08-26 03:40:59 -05:00
Niklaus Giger
3a7b2c21fb Support up to 7 banks for ids as specified in JEDEC JEP106Z
see http://www.jedec.org/download/search/jep106Z.pdf
Add some second source legacy flash chips 256x8.

Signed-off-by: Niklaus Giger <niklaus.giger@member.fsf.org>
Signed-off-by: Stefan Roese <sr@denx.de>
2009-08-26 08:58:27 +02:00
Wolfgang Denk
d3870bd2d8 Merge branch 'next' of git://git.denx.de/u-boot-net into next 2009-08-25 23:03:22 +02:00
Wolfgang Denk
68ccfa482b Merge branch 'master' into next 2009-08-25 22:57:10 +02:00
Kim Phillips
0d071cdd78 net: tsec - handle user interrupt while waiting for PHY auto negotiation to complete
if you don't have firmware installed for the PHY to come to life, this
wait can be painful - let's give the option to avoid it if we want.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-08-25 13:35:55 -07:00
Robin Getz
4fccb818e7 Add Transfer Size Option to tftp
Optionally add RFC 2349 "Transfer Size Option", so we can minimize the
time spent sending data over the UART (now print a single line during a
tftp transfer).

 - If turned on (CONFIG_TFTP_TSIZE), U-Boot asks for the size of the file.
 - if receives the file size, a single line (50 chars) are printed.
     one hash mark == 2% of the file downloaded.
 - if it doesn't receive the file size (the server doesn't support RFC
     2349, prints standard hash marks (one mark for each UDP frame).

Signed-off-by: Robin Getz <rgetz@blackfin.uclinux.org>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-08-25 13:35:54 -07:00
Robin Getz
488feef852 Add debug message for Blackfin Ethernet Rx function.
Add a simple print for the Blackfin's Ethernet Rx function,
so we can debug incomming Ethernet functions easier.

Signed-off-by: Robin Getz <rgetz@blackfin.uclinux.org>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-08-25 13:35:54 -07:00
Ben Warren
b1c0eaac11 Convert CS8900 Ethernet driver to CONFIG_NET_MULTI API
All in-tree boards that use this controller have CONFIG_NET_MULTI added
Also:
  - changed CONFIG_DRIVER_CS8900 to CONFIG_CS8900
  - changed CS8900_BASE to CONFIG_CS8900_BASE
  - changed CS8900_BUS?? to CONFIG_CS8900_BUS??
  - cleaned up line lengths
  - modified VCMA9 command function that accesses the device
  - removed MAC address initialization from lib_arm/board.c

Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Tested-by: Wolfgang Denk <wd@denx.de>
Acked-by: Wolfgang Denk <wd@denx.de>
2009-08-25 13:35:54 -07:00
Alessandro Rubini
d47628a6ec arm nomadik: activate defrag choose 4k transfer block size
This chooses 4kB data size for both TFTP and NFS, as an example
about how to use support for IP fragments.

Signed-off-by: Alessandro Rubini <rubini@gnudd.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-08-25 13:35:54 -07:00
Alessandro Rubini
bd931ca61c nfs: accept CONFIG_NFS_READ_SIZE from config file
To take advantage of defragmented packets, the config file
can define CONFIG_NFS_READ_SIZE to override the 1kB default.
No support is there for an environment variable by now.

Signed-off-by: Alessandro Rubini <rubini@gnudd.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-08-25 13:35:54 -07:00
Alessandro Rubini
89ba81d107 tftp: get the tftp block size from config file and from the environment
Increasing the block size is useful if CONFIG_IP_DEFRAG is
used. Howerver, the last fragments in a burst may overflow the
receiving ethernet, so the default is left at 1468, with thre new
CONFIG_TFTP_BLOCKSIZE for config files. Further, "tftpblocksize"
can be set in the environment.

Signed-off-by: Alessandro Rubini <rubini@gnudd.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-08-25 13:35:54 -07:00
Alessandro Rubini
5cfaa4e54d net: defragment IP packets
The defragmenting code is enabled by CONFIG_IP_DEFRAG; the code is
useful for TFTP and NFS transfers.  The user can specify the maximum
defragmented payload as CONFIG_NET_MAXDEFRAG (default 16k).
Since NFS has a bigger per-packet overhead than TFTP, the static
reassembly buffer can hold CONFIG_NET_MAXDEFRAG + the NFS overhead.

The packet buffer is used as an array of "hole" structures, acting as
a double-linked list. Each new fragment can split a hole in two,
reduce a hole or fill a hole. No support is there for a fragment
overlapping two diffrent holes (i.e., thre new fragment is across an
already-received fragment).

Signed-off-by: Alessandro Rubini <rubini@gnudd.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-08-25 13:35:54 -07:00
Eric Millbrandt
307ecb6db0 Add support for USB on PSC3 for the mpc5200
Support USB on PSC3 on the mpc5200.  Before this patch, enabling USB support
would reconfigure PSC4 and PSC5 to USB.  The mpc5200 does not support USB
enabled on both the standard USB port and PSC3.  This patch masks the
appropriate bits when enabling USB.

Signed-off-by: Eric Millbrandt <emillbrandt@dekaresearch.com>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Acked-by: Remy Bohmer <linux@bohmer.net>
2009-08-25 12:57:55 +02:00
Albin Tonnerre
6b8548b0f7 Add driver for the ST M41T94 SPI RTC
This RTC is used in some Calao boards. The driver code is taken from
the linux rtc-m41t94 driver

Signed-off-by: Albin Tonnerre <albin.tonnerre@free-electrons.com>
2009-08-25 12:57:55 +02:00
Albin Tonnerre
885fc78c28 Switch from per-driver to common definition of bin2bcd and bcd2bin
Signed-off-by: Albin Tonnerre <albin.tonnerre@free-electrons.com>
Acked-by: Stefan Roese <sr@denx.de>
2009-08-25 12:57:55 +02:00
Albin Tonnerre
e84aba135e Replace BCD2BIN and BIN2BCD macros with inline functions
In the process, also remove backward-compatiblity macros BIN_TO_BCD and
BCD_TO_BIN and update the sole board using them to use the new bin2bcd
and bcd2bin instead

Signed-off-by: Albin Tonnerre <albin.tonnerre@free-electrons.com>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: Detlev Zundel <dzu@denx.de>
2009-08-25 12:57:55 +02:00
Eric Millbrandt
5b53b29bc2 Add support for the galaxy5200
Add support for the DEKA Research and Development galaxy5200 board

The galaxy5200 is an Freescale mpc5200 based embedded industrial
control board.

Signed-off-by: Eric Millbrandt <emillbrandt@dekaresearch.com>
2009-08-25 12:57:55 +02:00
Mike Frysinger
0a9e4e7721 unify {CONFIG_,}ENV_IS_EMBEDDED
Some boards have fallen out of sync by defining CONFIG_ENV_IS_EMBEDDED
manually.  While it is useful to have this available to the build system,
let's do it automatically rather than forcing people to opt into it.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Albin Tonnerre <albin.tonnerre@free-electrons.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-08-25 12:57:54 +02:00
Robin Getz
02c9aa1d41 Add md5sum and sha1 commands...
Now that we have sha1 and md5 in lib_generic, allow people to use
them on the command line, for checking downloaded files.

Signed-off-by: Robin Getz <rgetz@analog.com>
2009-08-25 12:57:54 +02:00
2130 changed files with 101982 additions and 95643 deletions

13728
CHANGELOG

File diff suppressed because it is too large Load Diff

View File

@@ -17,6 +17,10 @@
# Board CPU #
#########################################################################
Poonam Aggrwal <poonam.aggrwal@freescale.com>
P2020RDB P2020
Greg Allen <gallen@arlut.utexas.edu>
UTX8245 MPC8245
@@ -32,6 +36,7 @@ Reinhard Arlt <reinhard.arlt@esd-electronics.com>
mecp5200 MPC5200
pf5200 MPC5200
caddy2 MPC8349
vme8349 MPC8349
CPCI750 PPC750FX/GX
@@ -113,7 +118,6 @@ Wolfgang Denk <wd@denx.de>
CU824 MPC8240
Sandpoint8240 MPC8240
SL8245 MPC8245
ATC MPC8250
PM825 MPC8250
@@ -129,24 +133,26 @@ Wolfgang Denk <wd@denx.de>
PCIPPC2 MPC750
PCIPPC6 MPC750
EXBITGEN PPC405GP
Jon Diekema <jon.diekema@smiths-aerospace.com>
sbc8260 MPC8260
Dirk Eibach <eibach@gdsys.de>
compactcenter PPC460EX
devconcenter PPC460EX
dlvision PPC405EP
gdppc440etx PPC440EP/GR
intip PPC460EX
neo PPC405EP
Dave Ellis <DGE@sixnetio.com>
SXNI855T MPC8xx
Fred Fan <fanyefeng@gmail.com>
mx51evk i.MX51
Thomas Frieden <ThomasF@hyperion-entertainment.com>
AmigaOneG3SE MPC7xx
@@ -197,6 +203,8 @@ Frank Gottschling <fgottschling@eltec.de>
Wolfgang Grandegger <wg@denx.de>
ipek01 MPC5200
CCM MPC855
PN62 MPC8240
@@ -273,7 +281,7 @@ Nye Liu <nyet@zumanetworks.com>
ZUMA MPC7xx_74xx
Jon Loeliger <jdl@freescale.com>
Kumar Gala <kumar.gala@freescale.com>
MPC8540ADS MPC8540
MPC8560ADS MPC8560
@@ -404,9 +412,9 @@ Heiko Schocher <hs@denx.de>
muas3001 MPC8270
municse MPC5200
sc3 PPC405GP
suen3 ARM926EJS (Kirkwood SoC)
uc101 MPC5200
Peter De Schrijver <p2@mind.be>
ML2 PPC4xx
@@ -521,6 +529,12 @@ Dirk Behme <dirk.behme@gmail.com>
omap3_beagle ARM CORTEX-A8 (OMAP3530 SoC)
Eric Benard <eric@eukrea.com>
cpuat91 ARM920T
cpu9260 ARM926EJS (AT91SAM9260 SoC)
cpu9G20 ARM926EJS (AT91SAM9G20 SoC)
Rishi Bhattacharya <rishi@ti.com>
omap5912osk ARM926EJS
@@ -533,12 +547,17 @@ Rick Bronson <rick@efn.org>
AT91RM9200DK at91rm9200
Po-Yu Chuang <ratbert@faraday-tech.com>
a320evb FA526 (ARM920T-like) (a320 SoC)
George G. Davis <gdavis@mvista.com>
assabet SA1100
gcplus SA1100
Wolfgang Denk <wd@denx.de>
imx27lite i.MX27
qong i.MX31
Thomas Elste <info@elste.org>
@@ -556,6 +575,7 @@ Peter Figuli <peposh@etc.sk>
Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
meesc ARM926EJS (AT91SAM9263 SoC)
otc570 ARM926EJS (AT91SAM9263 SoC)
Sedji Gaouaou<sedji.gaouaou@atmel.com>
at91sam9g10ek ARM926EJS (AT91SAM9G10 SoC)
@@ -580,19 +600,44 @@ Gary Jennejohn <garyj@denx.de>
smdk2400 ARM920T
trab ARM920T
Matthias Kaehlcke <matthias@kaehlcke.net>
edb9301 ARM920T (EP9301)
edb9302 ARM920T (EP9302)
edb9302a ARM920T (EP9302)
edb9307 ARM920T (EP9307)
edb9307a ARM920T (EP9307)
edb9312 ARM920T (EP9312)
edb9315 ARM920T (EP9315)
edb9315a ARM920T (EP9315)
Konstantin Kletschke <kletschke@synertronixx.de>
scb9328 ARM920T
Simon Kagstrom <simon.kagstrom@netinsight.net>
openrd_base ARM926EJS (Kirkwood SoC)
Nishant Kamat <nskamat@ti.com>
omap1610h2 ARM926EJS
Frederik Kriewitz <frederik@kriewitz.eu>
devkit8000 ARM CORTEX-A8 (OMAP3530 SoC)
Sergey Kubushyn <ksi@koi8.net>
DV-EVM ARM926EJS
SONATA ARM926EJS
SCHMOOGIE ARM926EJS
Sandeep Paulraj <s-paulraj@ti.com>
davinci_dm355evm ARM926EJS
davinci_dm355leopard ARM926EJS
davinci_dm365evm ARM926EJS
davinci_dm6467evm ARM926EJS
Prakash Kumar <prakash@embedx.com>
cerf250 xscale
@@ -609,6 +654,7 @@ Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Nishanth Menon <nm@ti.com>
omap3_sdp3430 ARM CORTEX-A8 (OMAP3xx SoC)
omap3_zoom1 ARM CORTEX-A8 (OMAP3xx SoC)
David Müller <d.mueller@elsoft.ch>
@@ -616,6 +662,10 @@ David M
smdk2410 ARM920T
VCMA9 ARM920T
Eric Millbrandt <emillbrandt@dekaresearch.com>
galaxy5200 mpc5200
Rolf Offermanns <rof@sysgo.de>
shannon SA1100
@@ -650,6 +700,10 @@ Tom Rix <Tom.Rix@windriver.com>
omap3_zoom2 ARM CORTEX-A8 (OMAP3xx SoC)
John Rigby <jcrigby@gmail.com>
tx25 i.MX25
Stefan Roese <sr@denx.de>
ixdpg425 xscale
@@ -659,12 +713,16 @@ Stefan Roese <sr@denx.de>
Alessandro Rubini <rubini@unipv.it>
Nomadik Linux Team <STN_WMM_nomadik_linux@list.st.com>
nmdk8815 ARM926EJS (Nomadik 8815 Soc)
nhk8815 ARM926EJS (Nomadik 8815 Soc)
Steve Sakoman <sakoman@gmail.com>
omap3_overo ARM CORTEX-A8 (OMAP3xx SoC)
Jens Scharsig <esw@bus-elektronik.de>
eb_cpux9k2 ARM920T (AT91RM9200 SoC)
Robert Schwebel <r.schwebel@pengutronix.de>
csb226 xscale
@@ -681,6 +739,16 @@ Andrea Scian <andrea.scian@dave-tech.it>
B2 ARM7TDMI (S3C44B0X)
Nick Thompson <nick.thompson@gefanuc.com>
da830evm ARM926EJS (DA830/OMAP-L137)
Albin Tonnerre <albin.tonnerre@free-electrons.com>
sbc35_a9g20 ARM926EJS (AT91SAM9G20 SoC)
tny_a9260 ARM926EJS (AT91SAM9260 SoC)
tny_a9g20 ARM926EJS (AT91SAM9G20 SoC)
Greg Ungerer <greg.ungerer@opengear.com>
cm4008 ks8695p
@@ -706,6 +774,10 @@ Alex Z
lart SA1100
dnp1110 SA1110
Minkyu Kang <mk7.kang@samsung.com>
SMDKC100 ARM CORTEX-A8 (S5PC100 SoC)
-------------------------------------------------------------------------
Unknown / orphaned boards:
@@ -787,10 +859,6 @@ Scott McNutt <smcnutt@psyent.com>
# Board CPU #
#########################################################################
Yasushi Shoji <yashi@atmark-techno.com>
SUZAKU MicroBlaze
Michal Simek <monstr@monstr.eu>
microblaze-generic MicroBlaze
@@ -895,6 +963,7 @@ Blackfin Team <u-boot-devel@blackfin.uclinux.org>
BF518F-EZBRD BF518
BF526-EZBRD BF526
BF527-EZKIT BF527
BF527-EZKIT-V2 BF527
BF533-EZKIT BF533
BF533-STAMP BF533
BF537-PNAV BF537
@@ -909,8 +978,10 @@ Blackfin Team <u-boot-devel@blackfin.uclinux.org>
CM-BF527 BF527
CM-BF533 BF533
CM-BF537E BF537
CM-BF537U BF537
CM-BF548 BF548
CM-BF561 BF561
TCM-BF518 BF518
TCM-BF537 BF537
Martin Strubel <strubel@section5.ch>
@@ -929,6 +1000,11 @@ Blackfin Team <u-boot-devel@blackfin.uclinux.org>
IBF-DSP561 BF561
Valentin Yakovenkov <yakovenkov@niistt.ru>
Anton Shurpin <shurpin.aa@niistt.ru>
BF561-ACVILON BF561
#########################################################################
# End of MAINTAINERS list #
#########################################################################

113
MAKEALL
View File

@@ -1,11 +1,15 @@
#!/bin/sh
#!/bin/bash
# Print statistics when we exit
trap exit 1 2 3 15
trap print_stats 0
# Determine number of CPU cores if no default was set
: ${BUILD_NCPUS:="`getconf _NPROCESSORS_ONLN`"}
if [ "$BUILD_NCPUS" -gt 1 ]
then
JOBS=-j`expr "$BUILD_NCPUS" + 1`
JOBS="-j $((BUILD_NCPUS + 1))"
else
JOBS=""
fi
@@ -31,6 +35,12 @@ fi
LIST=""
# Keep track of the number of builds and errors
ERR_CNT=0
ERR_LIST=""
TOTAL_CNT=0
RC=0
#########################################################################
## MPC5xx Systems
#########################################################################
@@ -50,9 +60,11 @@ LIST_5xxx=" \
digsy_mtc \
EVAL5200 \
fo300 \
galaxy5200 \
icecube_5100 \
icecube_5200 \
inka4x0 \
ipek01 \
lite5200b \
mcc200 \
mecp5200 \
@@ -184,7 +196,6 @@ LIST_4xx=" \
canyonlands \
canyonlands_nand \
CMS700 \
compactcenter \
CPCI2DP \
CPCI405 \
CPCI4052 \
@@ -202,7 +213,6 @@ LIST_4xx=" \
DU440 \
ebony \
ERIC \
EXBITGEN \
fx12mm \
G2000 \
gdppc440etx \
@@ -213,6 +223,7 @@ LIST_4xx=" \
hcu5 \
HH405 \
HUB405 \
intip \
JSE \
KAREF \
katmai \
@@ -227,7 +238,6 @@ LIST_4xx=" \
MIP405 \
MIP405T \
ML2 \
ml300 \
ml507 \
ml507_flash \
neo \
@@ -301,7 +311,6 @@ LIST_824x=" \
Sandpoint8240 \
Sandpoint8245 \
sbc8240 \
SL8245 \
utx8245 \
"
@@ -346,10 +355,12 @@ LIST_8260=" \
#########################################################################
LIST_83xx=" \
caddy2 \
kmeter1 \
MPC8313ERDB_33 \
MPC8313ERDB_NAND_66 \
MPC8315ERDB \
MPC8315ERDB_NAND \
MPC8323ERDB \
MPC832XEMDS \
MPC832XEMDS_ATM \
@@ -377,6 +388,9 @@ LIST_83xx=" \
LIST_85xx=" \
ATUM8548 \
MPC8536DS \
MPC8536DS_NAND \
MPC8536DS_SDCARD \
MPC8536DS_SPIFLASH \
MPC8540ADS \
MPC8540EVAL \
MPC8541CDS \
@@ -386,14 +400,36 @@ LIST_85xx=" \
MPC8560ADS \
MPC8568MDS \
MPC8569MDS \
MPC8569MDS_ATM \
MPC8569MDS_NAND \
MPC8572DS \
MPC8572DS_36BIT \
P2020DS \
P2020DS_36BIT \
P1011RDB \
P1011RDB_NAND \
P1011RDB_SDCARD \
P1011RDB_SPIFLASH \
P1020RDB \
P1020RDB_NAND \
P1020RDB_SDCARD \
P1020RDB_SPIFLASH \
P2010RDB \
P2010RDB_NAND \
P2010RDB_SDCARD \
P2010RDB_SPIFLASH \
P2020RDB \
P2020RDB_NAND \
P2020RDB_SDCARD \
P2020RDB_SPIFLASH \
PM854 \
PM856 \
sbc8540 \
sbc8548 \
sbc8548_PCI_33 \
sbc8548_PCI_66 \
sbc8548_PCI_33_PCIE \
sbc8548_PCI_66_PCIE \
sbc8560 \
socrates \
stxgp3 \
@@ -505,6 +541,7 @@ LIST_ARM7=" \
#########################################################################
LIST_ARM9=" \
a320evb \
ap920t \
ap922_XA10 \
ap926ejs \
@@ -515,6 +552,16 @@ LIST_ARM9=" \
cp926ejs \
cp946es \
cp966 \
da830evm \
edb9301 \
edb9302 \
edb9302a \
edb9307 \
edb9307a \
edb9312 \
edb9315 \
edb9315a \
imx27lite \
lpd7a400 \
mv88f6281gtw_ge \
mx1ads \
@@ -527,12 +574,18 @@ LIST_ARM9=" \
omap1610inn \
omap5912osk \
omap730p2 \
openrd_base \
rd6281a \
sbc2410x \
scb9328 \
sheevaplug \
smdk2400 \
smdk2410 \
spear300 \
spear310 \
spear320 \
spear600 \
suen3 \
trab \
VCMA9 \
versatile \
@@ -544,6 +597,9 @@ LIST_ARM9=" \
davinci_sffsdr \
davinci_sonata \
davinci_dm355evm \
davinci_dm355leopard \
davinci_dm365evm \
davinci_dm6467evm \
"
#########################################################################
@@ -575,12 +631,16 @@ LIST_ARM11=" \
## ARM Cortex-A8 Systems
#########################################################################
LIST_ARM_CORTEX_A8=" \
devkit8000 \
mx51evk \
omap3_beagle \
omap3_overo \
omap3_evm \
omap3_pandora \
omap3_sdp3430 \
omap3_zoom1 \
omap3_zoom2 \
smdkc100 \
"
#########################################################################
@@ -595,18 +655,26 @@ LIST_at91=" \
at91sam9260ek \
at91sam9261ek \
at91sam9263ek \
at91sam9g10ek \
at91sam9g10ek \
at91sam9g20ek \
at91sam9m10g45ek \
at91sam9rlek \
cmc_pu2 \
CPUAT91 \
CPU9260 \
CPU9G20 \
csb637 \
eb_cpux9k2 \
kb9202 \
meesc \
mp2usb \
m501sk \
otc570 \
pm9261 \
pm9263 \
SBC35_A9G20 \
TNY_A9260 \
TNY_A9G20 \
"
#########################################################################
@@ -765,7 +833,6 @@ LIST_nios2=" \
LIST_microblaze=" \
microblaze-generic \
suzaku \
"
#########################################################################
@@ -820,6 +887,7 @@ LIST_blackfin=" \
bf518f-ezbrd \
bf526-ezbrd \
bf527-ezkit \
bf527-ezkit-v2 \
bf533-ezkit \
bf533-stamp \
bf537-minotaur \
@@ -828,14 +896,17 @@ LIST_blackfin=" \
bf537-stamp \
bf538f-ezkit \
bf548-ezkit \
bf561-acvilon \
bf561-ezkit \
blackstamp \
cm-bf527 \
cm-bf533 \
cm-bf537e \
cm-bf537u \
cm-bf548 \
cm-bf561 \
ibf-dsp561 \
tcm-bf518 \
tcm-bf537 \
"
@@ -891,13 +962,39 @@ build_target() {
${MAKE} ${JOBS} all 2>&1 >${LOG_DIR}/$target.MAKELOG \
| tee ${LOG_DIR}/$target.ERR
# Check for 'make' errors
if [ ${PIPESTATUS[0]} -ne 0 ] ; then
RC=1
fi
if [ -s ${LOG_DIR}/$target.ERR ] ; then
ERR_CNT=$((ERR_CNT + 1))
ERR_LIST="${ERR_LIST} $target"
else
rm ${LOG_DIR}/$target.ERR
fi
TOTAL_CNT=$((TOTAL_CNT + 1))
${CROSS_COMPILE}size ${BUILD_DIR}/u-boot \
| tee -a ${LOG_DIR}/$target.MAKELOG
}
#-----------------------------------------------------------------------
print_stats() {
echo ""
echo "--------------------- SUMMARY ----------------------------"
echo "Boards compiled: ${TOTAL_CNT}"
if [ ${ERR_CNT} -gt 0 ] ; then
echo "Boards with warnings or errors: ${ERR_CNT} (${ERR_LIST} )"
fi
echo "----------------------------------------------------------"
exit $RC
}
#-----------------------------------------------------------------------
for arg in $@
do
case "$arg" in

360
Makefile
View File

@@ -21,8 +21,8 @@
# MA 02111-1307 USA
#
VERSION = 2009
PATCHLEVEL = 08
VERSION = 2010
PATCHLEVEL = 03
SUBLEVEL =
EXTRAVERSION =
ifneq "$(SUBLEVEL)" ""
@@ -218,7 +218,6 @@ LIBS += drivers/mtd/ubi/libubi.a
LIBS += drivers/mtd/spi/libspi_flash.a
LIBS += drivers/net/libnet.a
LIBS += drivers/net/phy/libphy.a
LIBS += drivers/net/sk98lin/libsk98lin.a
LIBS += drivers/pci/libpci.a
LIBS += drivers/pcmcia/libpcmcia.a
LIBS += drivers/power/libpower.a
@@ -229,11 +228,11 @@ endif
ifeq ($(CPU),mpc85xx)
LIBS += drivers/qe/qe.a
LIBS += cpu/mpc8xxx/ddr/libddr.a
TAG_SUBDIRS += cpu/mpc8xxx
LIBS += cpu/mpc8xxx/lib8xxx.a
endif
ifeq ($(CPU),mpc86xx)
LIBS += cpu/mpc8xxx/ddr/libddr.a
TAG_SUBDIRS += cpu/mpc8xxx
LIBS += cpu/mpc8xxx/lib8xxx.a
endif
LIBS += drivers/rtc/librtc.a
LIBS += drivers/serial/libserial.a
@@ -241,6 +240,7 @@ LIBS += drivers/twserial/libtws.a
LIBS += drivers/usb/gadget/libusb_gadget.a
LIBS += drivers/usb/host/libusb_host.a
LIBS += drivers/usb/musb/libusb_musb.a
LIBS += drivers/usb/phy/libusb_phy.a
LIBS += drivers/video/libvideo.a
LIBS += drivers/watchdog/libwatchdog.a
LIBS += common/libcommon.a
@@ -283,6 +283,7 @@ endif
ifeq ($(CONFIG_ONENAND_U_BOOT),y)
ONENAND_IPL = onenand_ipl
U_BOOT_ONENAND = $(obj)u-boot-onenand.bin
ONENAND_BIN ?= $(obj)onenand_ipl/onenand-ipl-2k.bin
endif
__OBJS := $(subst $(obj),,$(OBJS))
@@ -306,7 +307,7 @@ $(obj)u-boot.bin: $(obj)u-boot
$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
$(obj)u-boot.ldr: $(obj)u-boot
$(obj)tools/envcrc --binary > $(obj)env-ldr.o
$(CREATE_LDR_ENV)
$(LDR) -T $(CONFIG_BFIN_CPU) -c $@ $< $(LDR_FLAGS)
$(obj)u-boot.ldr.hex: $(obj)u-boot.ldr
@@ -322,6 +323,14 @@ $(obj)u-boot.img: $(obj)u-boot.bin
sed -e 's/"[ ]*$$/ for $(BOARD) board"/') \
-d $< $@
$(obj)u-boot.imx: $(obj)u-boot.bin
$(obj)tools/mkimage -n $(IMX_CONFIG) -T imximage \
-e $(TEXT_BASE) -d $< $@
$(obj)u-boot.kwb: $(obj)u-boot.bin
$(obj)tools/mkimage -n $(KWD_CONFIG) -T kwbimage \
-a $(TEXT_BASE) -e $(TEXT_BASE) -d $< $@
$(obj)u-boot.sha1: $(obj)u-boot.bin
$(obj)tools/ubsha1 $(obj)u-boot.bin
@@ -372,8 +381,7 @@ $(ONENAND_IPL): $(TIMESTAMP_FILE) $(VERSION_FILE) $(obj)include/autoconf.mk
$(MAKE) -C onenand_ipl/board/$(BOARDDIR) all
$(U_BOOT_ONENAND): $(ONENAND_IPL) $(obj)u-boot.bin
cat $(obj)onenand_ipl/onenand-ipl-2k.bin $(obj)u-boot.bin > $(obj)u-boot-onenand.bin
cat $(obj)onenand_ipl/onenand-ipl-4k.bin $(obj)u-boot.bin > $(obj)u-boot-flexonenand.bin
cat $(ONENAND_BIN) $(obj)u-boot.bin > $(obj)u-boot-onenand.bin
$(VERSION_FILE):
@( printf '#define U_BOOT_VERSION "U-Boot %s%s"\n' "$(U_BOOT_VERSION)" \
@@ -393,54 +401,25 @@ updater:
env:
$(MAKE) -C tools/env all MTD_VERSION=${MTD_VERSION} || exit 1
# Explicitly make _depend in subdirs containing multiple targets to prevent
# parallel sub-makes creating .depend files simultaneously.
depend dep: $(TIMESTAMP_FILE) $(VERSION_FILE) $(obj)include/autoconf.mk
for dir in $(SUBDIRS) ; do $(MAKE) -C $$dir _depend ; done
for dir in $(SUBDIRS) cpu/$(CPU) $(dir $(LDSCRIPT)) ; do \
$(MAKE) -C $$dir _depend ; done
TAG_SUBDIRS = $(SUBDIRS)
TAG_SUBDIRS += $(dir $(__LIBS))
TAG_SUBDIRS += include
TAG_SUBDIRS += lib_generic board/$(BOARDDIR)
TAG_SUBDIRS += cpu/$(CPU)
TAG_SUBDIRS += lib_$(ARCH)
TAG_SUBDIRS += fs/cramfs
TAG_SUBDIRS += fs/fat
TAG_SUBDIRS += fs/fdos
TAG_SUBDIRS += fs/jffs2
TAG_SUBDIRS += fs/yaffs2
TAG_SUBDIRS += net
TAG_SUBDIRS += disk
TAG_SUBDIRS += common
TAG_SUBDIRS += drivers/bios_emulator
TAG_SUBDIRS += drivers/block
TAG_SUBDIRS += drivers/gpio
TAG_SUBDIRS += drivers/hwmon
TAG_SUBDIRS += drivers/i2c
TAG_SUBDIRS += drivers/input
TAG_SUBDIRS += drivers/misc
TAG_SUBDIRS += drivers/mmc
TAG_SUBDIRS += drivers/mtd
TAG_SUBDIRS += drivers/mtd/nand
TAG_SUBDIRS += drivers/mtd/onenand
TAG_SUBDIRS += drivers/mtd/spi
TAG_SUBDIRS += drivers/net
TAG_SUBDIRS += drivers/net/sk98lin
TAG_SUBDIRS += drivers/pci
TAG_SUBDIRS += drivers/pcmcia
TAG_SUBDIRS += drivers/qe
TAG_SUBDIRS += drivers/rtc
TAG_SUBDIRS += drivers/serial
TAG_SUBDIRS += drivers/spi
TAG_SUBDIRS += drivers/usb
TAG_SUBDIRS += drivers/video
tags ctags:
ctags -w -o $(obj)ctags `find $(SUBDIRS) $(TAG_SUBDIRS) \
-name '*.[ch]' -print`
ctags -w -o $(obj)ctags `find $(TAG_SUBDIRS) \
-name '*.[chS]' -print`
etags:
etags -a -o $(obj)etags `find $(SUBDIRS) $(TAG_SUBDIRS) \
-name '*.[ch]' -print`
etags -a -o $(obj)etags `find $(TAG_SUBDIRS) \
-name '*.[chS]' -print`
cscope:
find $(SUBDIRS) $(TAG_SUBDIRS) -name '*.[ch]' -print \
> cscope.files
find $(TAG_SUBDIRS) -name '*.[chS]' -print > cscope.files
cscope -b -q -k
SYSTEM_MAP = \
@@ -475,10 +454,15 @@ $(obj)include/autoconf.mk: $(obj)include/config.h
else # !config.mk
all $(obj)u-boot.hex $(obj)u-boot.srec $(obj)u-boot.bin \
$(obj)u-boot.img $(obj)u-boot.dis $(obj)u-boot \
$(SUBDIRS) $(TIMESTAMP_FILE) $(VERSION_FILE) gdbtools updater env depend \
dep tags ctags etags cscope $(obj)System.map:
$(filter-out tools,$(SUBDIRS)) $(TIMESTAMP_FILE) $(VERSION_FILE) gdbtools \
updater env depend dep tags ctags etags cscope $(obj)System.map:
@echo "System not configured - see README" >&2
@ exit 1
tools:
$(MAKE) -C tools
tools-all:
$(MAKE) -C tools HOST_TOOLS_ALL=y
endif # config.mk
.PHONY : CHANGELOG
@@ -495,6 +479,9 @@ unconfig:
$(obj)board/*/config.tmp $(obj)board/*/*/config.tmp \
$(obj)include/autoconf.mk $(obj)include/autoconf.mk.dep
%: %_config
$(MAKE)
#========================================================================
# PowerPC
#========================================================================
@@ -544,6 +531,12 @@ digsy_mtc_RAMBOOT_config: unconfig
}
@$(MKCONFIG) -a digsy_mtc ppc mpc5xxx digsy_mtc
galaxy5200_LOWBOOT_config \
galaxy5200_config: unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_$(@:_config=) 1" >$(obj)include/config.h
@$(MKCONFIG) -a galaxy5200 ppc mpc5xxx galaxy5200
hmi1001_config: unconfig
@$(MKCONFIG) hmi1001 ppc mpc5xxx hmi1001
@@ -591,6 +584,9 @@ jupiter_config: unconfig
inka4x0_config: unconfig
@$(MKCONFIG) inka4x0 ppc mpc5xxx inka4x0
ipek01_config: unconfig
@$(MKCONFIG) -a ipek01 ppc mpc5xxx ipek01
lite5200b_config \
lite5200b_PM_config \
lite5200b_LOWBOOT_config: unconfig
@@ -1142,7 +1138,7 @@ SPD823TS_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc8xx spd8xx
stxxtc_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc8xx stxxtc
@$(MKCONFIG) $(@:_config=) ppc mpc8xx stxxtc stx
svm_sc8xx_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc8xx svm_sc8xx
@@ -1296,14 +1292,6 @@ CATcenter_33_config: unconfig
CMS700_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx cms700 esd
# Compact-Center & DevCon-Center use different U-Boot images
compactcenter_config \
devconcenter_config: unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_$$(echo $(subst ,,$(@:_config=)) | \
tr '[:lower:]' '[:upper:]')" >$(obj)include/config.h
@$(MKCONFIG) -n $@ -a compactcenter ppc ppc4xx compactcenter gdsys
CPCI2DP_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx cpci2dp esd
@@ -1347,9 +1335,6 @@ ebony_config: unconfig
ERIC_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx eric
EXBITGEN_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx exbitgen
fx12mm_flash_config: unconfig
@mkdir -p $(obj)include $(obj)board/xilinx/ppc405-generic
@mkdir -p $(obj)include $(obj)board/avnet/fx12mm
@@ -1388,6 +1373,14 @@ HH405_config: unconfig
HUB405_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx hub405 esd
# Compact-Center(codename intip) & DevCon-Center use different U-Boot images
intip_config \
devconcenter_config: unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_$$(echo $(subst ,,$(@:_config=)) | \
tr '[:lower:]' '[:upper:]')" >$(obj)include/config.h
@$(MKCONFIG) -n $@ -a intip ppc ppc4xx intip gdsys
JSE_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx jse
@@ -1442,9 +1435,6 @@ MIP405T_config: unconfig
ML2_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx ml2
ml300_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx ml300 xilinx
ml507_flash_config: unconfig
@mkdir -p $(obj)include $(obj)board/xilinx/ppc440-generic
@mkdir -p $(obj)include $(obj)board/xilinx/ml507
@@ -1747,9 +1737,6 @@ Sandpoint8245_config: unconfig
sbc8240_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc824x sbc8240
SL8245_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc824x sl8245
utx8245_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc824x utx8245
@@ -2276,8 +2263,9 @@ MPC8313ERDB_NAND_66_config: unconfig
echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk ; \
fi ;
MPC8315ERDB_NAND_config \
MPC8315ERDB_config: unconfig
@$(MKCONFIG) -a MPC8315ERDB ppc mpc83xx mpc8315erdb freescale
@$(MKCONFIG) -t $(@:_config=) MPC8315ERDB ppc mpc83xx mpc8315erdb freescale
MPC8323ERDB_config: unconfig
@$(MKCONFIG) -a MPC8323ERDB ppc mpc83xx mpc8323erdb freescale
@@ -2391,20 +2379,7 @@ MVBLM7_config: unconfig
sbc8349_config \
sbc8349_PCI_33_config \
sbc8349_PCI_66_config: unconfig
@mkdir -p $(obj)include
@if [ "$(findstring _PCI_,$@)" ] ; then \
$(XECHO) -n "... PCI HOST at " ; \
echo "#define CONFIG_PCI" >>$(obj)include/config.h ; \
fi ; \
if [ "$(findstring _33_,$@)" ] ; then \
$(XECHO) -n "33MHz... " ; \
echo "#define PCI_33M" >>$(obj)include/config.h ; \
fi ; \
if [ "$(findstring _66_,$@)" ] ; then \
$(XECHO) -n "66MHz... " ; \
echo "#define PCI_66M" >>$(obj)include/config.h ; \
fi ;
@$(MKCONFIG) -a sbc8349 ppc mpc83xx sbc8349
@$(MKCONFIG) -t $(@:_config=) sbc8349 ppc mpc83xx sbc8349
SIMPC8313_LP_config \
SIMPC8313_SP_config: unconfig
@@ -2424,8 +2399,19 @@ SIMPC8313_SP_config: unconfig
TQM834x_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc83xx tqm834x tqc
caddy2_config \
vme8349_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc83xx vme8349 esd
@$(MKCONFIG) -t $(@:_config=) vme8349 ppc mpc83xx vme8349 esd
edb9301_config \
edb9302_config \
edb9302a_config \
edb9307_config \
edb9307a_config \
edb9312_config \
edb9315_config \
edb9315a_config: unconfig
@$(MKCONFIG) -t $(@:_config=) edb93xx arm arm920t edb93xx NULL ep93xx
#########################################################################
## MPC85xx Systems
@@ -2434,8 +2420,12 @@ vme8349_config: unconfig
ATUM8548_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc85xx atum8548
MPC8536DS_NAND_config \
MPC8536DS_SDCARD_config \
MPC8536DS_SPIFLASH_config \
MPC8536DS_36BIT_config \
MPC8536DS_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8536ds freescale
@$(MKCONFIG) -t $(@:_config=) MPC8536DS ppc mpc85xx mpc8536ds freescale
MPC8540ADS_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8540ads freescale
@@ -2496,26 +2486,36 @@ MPC8555CDS_config: unconfig
MPC8568MDS_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8568mds freescale
MPC8569MDS_ATM_config \
MPC8569MDS_NAND_config \
MPC8569MDS_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8569mds freescale
@$(MKCONFIG) -t $(@:_config=) MPC8569MDS ppc mpc85xx mpc8569mds freescale
MPC8572DS_36BIT_config \
MPC8572DS_config: unconfig
@mkdir -p $(obj)include
@if [ "$(findstring _36BIT_,$@)" ] ; then \
echo "#define CONFIG_PHYS_64BIT" >>$(obj)include/config.h ; \
$(XECHO) "... enabling 36-bit physical addressing." ; \
fi
@$(MKCONFIG) -a MPC8572DS ppc mpc85xx mpc8572ds freescale
@$(MKCONFIG) -t $(@:_config=) MPC8572DS ppc mpc85xx mpc8572ds freescale
P2020DS_36BIT_config \
P2020DS_config: unconfig
@mkdir -p $(obj)include
@if [ "$(findstring _36BIT_,$@)" ] ; then \
echo "#define CONFIG_PHYS_64BIT" >>$(obj)include/config.h ; \
$(XECHO) "... enabling 36-bit physical addressing." ; \
fi
@$(MKCONFIG) -a P2020DS ppc mpc85xx p2020ds freescale
@$(MKCONFIG) -t $(@:_config=) P2020DS ppc mpc85xx p2020ds freescale
P1011RDB_config \
P1011RDB_NAND_config \
P1011RDB_SDCARD_config \
P1011RDB_SPIFLASH_config \
P1020RDB_config \
P1020RDB_NAND_config \
P1020RDB_SDCARD_config \
P1020RDB_SPIFLASH_config \
P2010RDB_config \
P2010RDB_NAND_config \
P2010RDB_SDCARD_config \
P2010RDB_SPIFLASH_config \
P2020RDB_config \
P2020RDB_NAND_config \
P2020RDB_SDCARD_config \
P2020RDB_SPIFLASH_config: unconfig
@$(MKCONFIG) -t $(@:_config=) P1_P2_RDB ppc mpc85xx p1_p2_rdb freescale
PM854_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc85xx pm854
@@ -2526,35 +2526,25 @@ PM856_config: unconfig
sbc8540_config \
sbc8540_33_config \
sbc8540_66_config: unconfig
@mkdir -p $(obj)include
@if [ "$(findstring _66_,$@)" ] ; then \
echo "#define CONFIG_PCI_66" >>$(obj)include/config.h ; \
$(XECHO) "... 66 MHz PCI" ; \
else \
$(XECHO) "... 33 MHz PCI" ; \
fi
@$(MKCONFIG) -a SBC8540 ppc mpc85xx sbc8560
@$(MKCONFIG) -t $(@:_config=) SBC8540 ppc mpc85xx sbc8560
sbc8548_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc85xx sbc8548
sbc8548_config \
sbc8548_PCI_33_config \
sbc8548_PCI_66_config \
sbc8548_PCI_33_PCIE_config \
sbc8548_PCI_66_PCIE_config: unconfig
@$(MKCONFIG) -t $(@:_config=) sbc8548 ppc mpc85xx sbc8548
sbc8560_config \
sbc8560_33_config \
sbc8560_66_config: unconfig
@mkdir -p $(obj)include
@if [ "$(findstring _66_,$@)" ] ; then \
echo "#define CONFIG_PCI_66" >>$(obj)include/config.h ; \
$(XECHO) "... 66 MHz PCI" ; \
else \
$(XECHO) "... 33 MHz PCI" ; \
fi
@$(MKCONFIG) -a sbc8560 ppc mpc85xx sbc8560
@$(MKCONFIG) -t $(@:_config=) sbc8560 ppc mpc85xx sbc8560
socrates_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc85xx socrates
stxgp3_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc85xx stxgp3
@$(MKCONFIG) $(@:_config=) ppc mpc85xx stxgp3 stx
stxssa_config \
stxssa_4M_config: unconfig
@@ -2563,7 +2553,7 @@ stxssa_4M_config: unconfig
echo "#define CONFIG_STXSSA_4M" >>$(obj)include/config.h ; \
$(XECHO) "... with 4 MiB flash memory" ; \
fi
@$(MKCONFIG) -a stxssa ppc mpc85xx stxssa
@$(MKCONFIG) -a stxssa ppc mpc85xx stxssa stx
TQM8540_config \
TQM8541_config \
@@ -2689,6 +2679,9 @@ shannon_config : unconfig
## ARM92xT Systems
#########################################################################
a320evb_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm920t a320evb faraday a320
#########################################################################
## Atmel AT91RM9200 Systems
#########################################################################
@@ -2702,9 +2695,18 @@ at91rm9200ek_config : unconfig
cmc_pu2_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm920t cmc_pu2 NULL at91rm9200
CPUAT91_RAM_config \
CPUAT91_config : unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_$(@:_config=) 1" >$(obj)include/config.h
@$(MKCONFIG) -a cpuat91 arm arm920t cpuat91 eukrea at91rm9200
csb637_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm920t csb637 NULL at91rm9200
eb_cpux9k2_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm920t eb_cpux9k2 BuS at91
kb9202_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm920t kb9202 NULL at91rm9200
@@ -2715,7 +2717,7 @@ mp2usb_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm920t mp2usb NULL at91rm9200
#########################################################################
## Atmel ARM926EJ-S Systems
## ARM926EJ-S Systems
#########################################################################
afeb9260_config: unconfig
@@ -2832,6 +2834,14 @@ at91sam9rlek_config : unconfig
fi;
@$(MKCONFIG) -a at91sam9rlek arm arm926ejs at91sam9rlek atmel at91
CPU9G20_128M_config \
CPU9G20_config \
CPU9260_128M_config \
CPU9260_config : unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_$(@:_config=) 1" >$(obj)include/config.h
@$(MKCONFIG) -a cpu9260 arm arm926ejs cpu9260 eukrea at91
meesc_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs meesc esd at91
@@ -2863,9 +2873,29 @@ at91sam9g45ekes_config : unconfig
fi;
@$(MKCONFIG) -a at91sam9m10g45ek arm arm926ejs at91sam9m10g45ek atmel at91
otc570_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs otc570 esd at91
pm9263_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs pm9263 ronetix at91
SBC35_A9G20_NANDFLASH_config \
SBC35_A9G20_EEPROM_config \
SBC35_A9G20_config : unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_$(@:_config=) 1" >$(obj)include/config.h
@$(MKCONFIG) -a sbc35_a9g20 arm arm926ejs sbc35_a9g20 calao at91
TNY_A9G20_NANDFLASH_config \
TNY_A9G20_EEPROM_config \
TNY_A9G20_config \
TNY_A9260_NANDFLASH_config \
TNY_A9260_EEPROM_config \
TNY_A9260_config : unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_$(@:_config=) 1" >$(obj)include/config.h
@$(MKCONFIG) -a tny_a9260 arm arm926ejs tny_a9260 calao at91
########################################################################
## ARM Integrator boards - see doc/README-integrator for more info.
integratorap_config \
@@ -2892,6 +2922,9 @@ cp922_XA10_config \
cp1026_config: unconfig
@board/armltd/integrator/split_by_variant.sh cp $@
da830evm_config: unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs da830evm davinci davinci
davinci_dvevm_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs dvevm davinci davinci
@@ -2907,6 +2940,18 @@ davinci_sonata_config : unconfig
davinci_dm355evm_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs dm355evm davinci davinci
davinci_dm355leopard_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs dm355leopard davinci davinci
davinci_dm365evm_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs dm365evm davinci davinci
davinci_dm6467evm_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs dm6467evm davinci davinci
imx27lite_config: unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs imx27lite logicpd mx27
lpd7a400_config \
lpd7a404_config: unconfig
@$(MKCONFIG) $(@:_config=) arm lh7a40x lpd7a40x
@@ -2936,7 +2981,7 @@ nhk8815_onenand_config: unconfig
@$(MKCONFIG) -a nhk8815 arm arm926ejs nhk8815 st nomadik
omap1510inn_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm925t omap1510inn
@$(MKCONFIG) $(@:_config=) arm arm925t omap1510inn ti
xtract_omap1610xxx = $(subst _cs0boot,,$(subst _cs3boot,,$(subst _cs_autoboot,,$(subst _config,,$1))))
@@ -2959,10 +3004,13 @@ omap1610h2_cs_autoboot_config: unconfig
echo "#define CONFIG_CS3_BOOT" >> $(obj)include/config.h ; \
$(XECHO) "... configured for CS3 boot"; \
fi;
@$(MKCONFIG) -a $(call xtract_omap1610xxx,$@) arm arm926ejs omap1610inn NULL omap
@$(MKCONFIG) -a $(call xtract_omap1610xxx,$@) arm arm926ejs omap1610inn ti omap
omap5912osk_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs omap5912osk NULL omap
@$(MKCONFIG) $(@:_config=) arm arm926ejs omap5912osk ti omap
openrd_base_config: unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs $(@:_config=) Marvell kirkwood
xtract_omap730p2 = $(subst _cs0boot,,$(subst _cs3boot,, $(subst _config,,$1)))
@@ -2977,7 +3025,7 @@ omap730p2_cs3boot_config : unconfig
echo "#define CONFIG_CS3_BOOT" >> $(obj)include/config.h ; \
$(XECHO) "... configured for CS3 boot"; \
fi;
@$(MKCONFIG) -a $(call xtract_omap730p2,$@) arm arm926ejs omap730p2 NULL omap
@$(MKCONFIG) -a $(call xtract_omap730p2,$@) arm arm926ejs omap730p2 ti omap
rd6281a_config: unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs $(@:_config=) Marvell kirkwood
@@ -2997,6 +3045,17 @@ smdk2400_config : unconfig
smdk2410_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm920t smdk2410 samsung s3c24x0
spear300_config \
spear310_config \
spear320_config : unconfig
@$(MKCONFIG) -n $@ -t $(@:_config=) spear3xx arm arm926ejs $(@:_config=) spear spear
spear600_config : unconfig
@$(MKCONFIG) -n $@ -t $(@:_config=) spear6xx arm arm926ejs $(@:_config=) spear spear
suen3_config: unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs km_arm keymile kirkwood
SX1_stdout_serial_config \
SX1_config: unconfig
@mkdir -p $(obj)include
@@ -3037,6 +3096,10 @@ trab_old_config: unconfig
}
@$(MKCONFIG) -a $(call xtract_trab,$@) arm arm920t trab NULL s3c24x0
tx25_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs tx25 karo mx25
@echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
VCMA9_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm920t vcma9 mpl s3c24x0
@@ -3094,23 +3157,32 @@ SMN42_config : unconfig
## ARM CORTEX Systems
#########################################################################
devkit8000_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 devkit8000 timll omap3
omap3_beagle_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 beagle omap3 omap3
@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 beagle ti omap3
omap3_overo_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 overo omap3 omap3
@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 overo NULL omap3
omap3_evm_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 evm omap3 omap3
@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 evm ti omap3
omap3_pandora_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 pandora omap3 omap3
@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 pandora NULL omap3
omap3_sdp3430_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 sdp3430 ti omap3
omap3_zoom1_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 zoom1 omap3 omap3
@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 zoom1 logicpd omap3
omap3_zoom2_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 zoom2 omap3 omap3
@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 zoom2 logicpd omap3
smdkc100_config: unconfig
@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 smdkc100 samsung s5pc1xx
#########################################################################
## XScale Systems
@@ -3199,13 +3271,12 @@ zylonite_config :
apollon_config : unconfig
@mkdir -p $(obj)include
@mkdir -p $(obj)onenand_ipl/board/apollon
@echo "#define CONFIG_ONENAND_U_BOOT" > $(obj)include/config.h
@$(MKCONFIG) $(@:_config=) arm arm1136 apollon NULL omap24xx
@echo "CONFIG_ONENAND_U_BOOT = y" >> $(obj)include/config.mk
imx31_litekit_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm1136 imx31_litekit NULL mx31
@$(MKCONFIG) $(@:_config=) arm arm1136 imx31_litekit logicpd mx31
imx31_phycore_eet_config \
imx31_phycore_config : unconfig
@@ -3229,8 +3300,11 @@ mx31pdk_nand_config : unconfig
fi
@$(MKCONFIG) -a mx31pdk arm arm1136 mx31pdk freescale mx31
mx51evk_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 mx51evk freescale mx51
omap2420h4_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm1136 omap2420h4 NULL omap24xx
@$(MKCONFIG) $(@:_config=) arm arm1136 omap2420h4 ti omap24xx
qong_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm1136 qong davedenx mx31
@@ -3480,11 +3554,6 @@ microblaze-generic_config: unconfig
@mkdir -p $(obj)include
@$(MKCONFIG) -a $(@:_config=) microblaze microblaze microblaze-generic xilinx
suzaku_config: unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_SUZAKU 1" > $(obj)include/config.h
@$(MKCONFIG) -a $(@:_config=) microblaze microblaze suzaku AtmarkTechno
#========================================================================
# Blackfin
#========================================================================
@@ -3494,10 +3563,11 @@ BFIN_BOARDS = bf518f-ezbrd bf526-ezbrd bf527-ezkit bf533-ezkit bf533-stamp \
bf537-pnav bf537-stamp bf538f-ezkit bf548-ezkit bf561-ezkit
# Bluetechnix tinyboards
BFIN_BOARDS += cm-bf527 cm-bf533 cm-bf537e cm-bf548 cm-bf561 tcm-bf537
BFIN_BOARDS += cm-bf527 cm-bf533 cm-bf537e cm-bf537u cm-bf548 cm-bf561 \
tcm-bf518 tcm-bf537
# Misc third party boards
BFIN_BOARDS += bf537-minotaur bf537-srv1 blackstamp
BFIN_BOARDS += bf537-minotaur bf537-srv1 bf561-acvilon blackstamp
# I-SYST Micromodule
BFIN_BOARDS += ibf-dsp561
@@ -3505,9 +3575,9 @@ BFIN_BOARDS += ibf-dsp561
$(BFIN_BOARDS:%=%_config) : unconfig
@$(MKCONFIG) $(@:_config=) blackfin blackfin $(@:_config=)
$(BFIN_BOARDS):
$(MAKE) $@_config
$(MAKE)
bf527-ezkit-v2_config : unconfig
@$(MKCONFIG) -t BF527_EZKIT_REV_2_1 \
bf527-ezkit blackfin blackfin bf527-ezkit
#========================================================================
# AVR32
@@ -3660,6 +3730,7 @@ grsim_leon2_config : unconfig
clean:
@rm -f $(obj)examples/standalone/82559_eeprom \
$(obj)examples/standalone/atmel_df_pow2 \
$(obj)examples/standalone/eepro100_eeprom \
$(obj)examples/standalone/hello_world \
$(obj)examples/standalone/interrupt \
@@ -3685,7 +3756,8 @@ clean:
$(obj)cpu/blackfin/bootrom-asm-offsets.[chs]
@rm -f $(obj)include/bmp_logo.h
@rm -f $(obj)nand_spl/{u-boot.lds,u-boot-spl,u-boot-spl.map,System.map}
@rm -f $(obj)onenand_ipl/onenand-{ipl,ipl.bin,ipl-2k.bin,ipl-4k.bin,ipl.map}
@rm -f $(obj)onenand_ipl/onenand-{ipl,ipl.bin,ipl.map}
@rm -f $(ONENAND_BIN)
@rm -f $(obj)onenand_ipl/u-boot.lds
@rm -f $(TIMESTAMP_FILE) $(VERSION_FILE)
@find $(OBJTREE) -type f \
@@ -3701,6 +3773,8 @@ clobber: clean
@rm -f $(OBJS) $(obj)*.bak $(obj)ctags $(obj)etags $(obj)TAGS \
$(obj)cscope.* $(obj)*.*~
@rm -f $(obj)u-boot $(obj)u-boot.map $(obj)u-boot.hex $(ALL)
@rm -f $(obj)u-boot.kwb
@rm -f $(obj)u-boot.imx
@rm -f $(obj)tools/{env/crc32.c,inca-swap-bytes}
@rm -f $(obj)cpu/mpc824x/bedbug_603e.c
@rm -f $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm

154
README
View File

@@ -1,5 +1,5 @@
#
# (C) Copyright 2000 - 2008
# (C) Copyright 2000 - 2009
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
@@ -138,6 +138,7 @@ U-Boot will always have a patchlevel of "0".
Directory Hierarchy:
====================
- api Machine/arch independent API for external apps
- board Board dependent files
- common Misc architecture independent functions
- cpu CPU specific files
@@ -178,8 +179,8 @@ Directory Hierarchy:
- disk Code for disk drive partition handling
- doc Documentation (don't expect too much)
- drivers Commonly used device drivers
- dtt Digital Thermometer and Thermostat drivers
- examples Example code for standalone applications, etc.
- fs Filesystem code (cramfs, ext2, jffs2, etc.)
- include Header Files
- lib_arm Files generic to ARM architecture
- lib_avr32 Files generic to AVR32 architecture
@@ -187,9 +188,12 @@ Directory Hierarchy:
- lib_generic Files generic to all architectures
- lib_i386 Files generic to i386 architecture
- lib_m68k Files generic to m68k architecture
- lib_microblaze Files generic to microblaze architecture
- lib_mips Files generic to MIPS architecture
- lib_nios Files generic to NIOS architecture
- lib_nios2 Files generic to NIOS2 architecture
- lib_ppc Files generic to PowerPC architecture
- lib_sh Files generic to SH architecture
- lib_sparc Files generic to SPARC architecture
- libfdt Library files to support flattened device trees
- net Networking code
@@ -368,8 +372,10 @@ The following options need to be configured:
* Adds the "fdt" command
* The bootm command automatically updates the fdt
OF_CPU - The proper name of the cpus node.
OF_SOC - The proper name of the soc node.
OF_CPU - The proper name of the cpus node (only required for
MPC512X and MPC5xxx based boards).
OF_SOC - The proper name of the soc node (only required for
MPC512X and MPC5xxx based boards).
OF_TBCLK - The timebase frequency.
OF_STDOUT_PATH - The path to the console device
@@ -386,6 +392,15 @@ The following options need to be configured:
This define fills in the correct boot CPU in the boot
param header, the default value is zero if undefined.
CONFIG_OF_IDE_FIXUP
U-Boot can detect if an IDE device is present or not.
If not, and this new config option is activated, U-Boot
removes the ATA node from the DTS before booting Linux,
so the Linux IDE driver does not probe the device and
crash. This is needed for buggy hardware (uc101) where
no pull down resistor is connected to the signal IDE5V_DD7.
- vxWorks boot parameters:
bootvx constructs a valid bootline using the following
@@ -609,6 +624,7 @@ The following options need to be configured:
CONFIG_CMD_DS4510_RST * ds4510 I2C rst command
CONFIG_CMD_DTT * Digital Therm and Thermostat
CONFIG_CMD_ECHO echo arguments
CONFIG_CMD_EDITENV edit env variable
CONFIG_CMD_EEPROM * EEPROM read/write support
CONFIG_CMD_ELF * bootelf, bootvx
CONFIG_CMD_SAVEENV saveenv
@@ -629,6 +645,8 @@ The following options need to be configured:
CONFIG_CMD_KGDB * kgdb
CONFIG_CMD_LOADB loadb
CONFIG_CMD_LOADS loads
CONFIG_CMD_MD5SUM print md5 message digest
(requires CONFIG_CMD_MEMORY and CONFIG_MD5)
CONFIG_CMD_MEMORY md, mm, nm, mw, cp, cmp, crc, base,
loop, loopw, mtest
CONFIG_CMD_MISC Misc functions like sleep etc
@@ -652,6 +670,8 @@ The following options need to be configured:
(requires CONFIG_CMD_I2C)
CONFIG_CMD_SETGETDCR Support for DCR Register access
(4xx only)
CONFIG_CMD_SHA1 print sha1 memory digest
(requires CONFIG_CMD_MEMORY)
CONFIG_CMD_SOURCE "source" command Support
CONFIG_CMD_SPI * SPI serial bus support
CONFIG_CMD_USB * USB support
@@ -757,7 +777,7 @@ The following options need to be configured:
CONFIG_LBA48
Set this to enable support for disks larger than 137GB
Also look at CONFIG_SYS_64BIT_LBA ,CONFIG_SYS_64BIT_VSPRINTF and CONFIG_SYS_64BIT_STRTOUL
Also look at CONFIG_SYS_64BIT_LBA.
Whithout these , LBA48 support uses 32bit variables and will 'only'
support disks up to 2.1TB.
@@ -802,6 +822,16 @@ The following options need to be configured:
- NETWORK Support (other):
CONFIG_DRIVER_AT91EMAC
Support for AT91RM9200 EMAC.
CONFIG_RMII
Define this to use reduced MII inteface
CONFIG_DRIVER_AT91EMAC_QUIET
If this defined, the driver is quiet.
The driver doen't show link status messages.
CONFIG_DRIVER_LAN91C96
Support for SMSC's LAN91C96 chips.
@@ -826,20 +856,20 @@ The following options need to be configured:
Define this to use i/o functions instead of macros
(some hardware wont work with macros)
CONFIG_DRIVER_SMC911X
CONFIG_SMC911X
Support for SMSC's LAN911x and LAN921x chips
CONFIG_DRIVER_SMC911X_BASE
CONFIG_SMC911X_BASE
Define this to hold the physical address
of the device (I/O space)
CONFIG_DRIVER_SMC911X_32_BIT
CONFIG_SMC911X_32_BIT
Define this if data bus is 32 bits
CONFIG_DRIVER_SMC911X_16_BIT
CONFIG_SMC911X_16_BIT
Define this if data bus is 16 bits. If your processor
automatically converts one 32 bit word to two 16 bit
words you may also try CONFIG_DRIVER_SMC911X_32_BIT.
words you may also try CONFIG_SMC911X_32_BIT.
- USB Support:
At the moment only the UHCI host controller is
@@ -854,9 +884,13 @@ The following options need to be configured:
MPC5200 USB requires additional defines:
CONFIG_USB_CLOCK
for 528 MHz Clock: 0x0001bbbb
CONFIG_PSC3_USB
for USB on PSC3
CONFIG_USB_CONFIG
for differential drivers: 0x00001000
for single ended drivers: 0x00005000
for differential drivers on PSC3: 0x00000100
for single ended drivers on PSC3: 0x00004100
CONFIG_SYS_USB_EVENT_POLL
May be defined to allow interrupt polling
instead of using asynchronous interrupts
@@ -1358,6 +1392,13 @@ The following options need to be configured:
therefore be cleared to 0 (See, eg, MPC823e User's Manual
p.16-473). So, set CONFIG_SYS_I2C_SLAVE to 0.
CONFIG_SYS_I2C_INIT_MPC5XXX
When a board is reset during an i2c bus transfer
chips might think that the current transfer is still
in progress. Reset the slave devices by sending start
commands until the slave device responds.
That's all that's required for CONFIG_HARD_I2C.
If you use the software i2c interface (CONFIG_SOFT_I2C)
@@ -1862,25 +1903,6 @@ The following options need to be configured:
example, some LED's) on your board. At the moment,
the following checkpoints are implemented:
- Automatic software updates via TFTP server
CONFIG_UPDATE_TFTP
CONFIG_UPDATE_TFTP_CNT_MAX
CONFIG_UPDATE_TFTP_MSEC_MAX
These options enable and control the auto-update feature;
for a more detailed description refer to doc/README.update.
- MTD Support (mtdparts command, UBI support)
CONFIG_MTD_DEVICE
Adds the MTD device infrastructure from the Linux kernel.
Needed for mtdparts command support.
CONFIG_MTD_PARTITIONS
Adds the MTD partitioning infrastructure from the Linux
kernel. Needed for UBI support.
Legacy uImage format:
Arg Where When
@@ -2034,6 +2056,25 @@ FIT uImage format:
-150 common/cmd_nand.c Incorrect FIT image format
151 common/cmd_nand.c FIT image format OK
- Automatic software updates via TFTP server
CONFIG_UPDATE_TFTP
CONFIG_UPDATE_TFTP_CNT_MAX
CONFIG_UPDATE_TFTP_MSEC_MAX
These options enable and control the auto-update feature;
for a more detailed description refer to doc/README.update.
- MTD Support (mtdparts command, UBI support)
CONFIG_MTD_DEVICE
Adds the MTD device infrastructure from the Linux kernel.
Needed for mtdparts command support.
CONFIG_MTD_PARTITIONS
Adds the MTD partitioning infrastructure from the Linux
kernel. Needed for UBI support.
Modem Support:
--------------
@@ -2416,6 +2457,19 @@ to save the current settings.
- CONFIG_SYS_EEPROM_SIZE:
The size in bytes of the EEPROM device.
- CONFIG_ENV_EEPROM_IS_ON_I2C
define this, if you have I2C and SPI activated, and your
EEPROM, which holds the environment, is on the I2C bus.
- CONFIG_I2C_ENV_EEPROM_BUS
if you have an Environment on an EEPROM reached over
I2C muxes, you can define here, how to reach this
EEPROM. For example:
#define CONFIG_I2C_ENV_EEPROM_BUS "pca9547:70:d\0"
EEPROM which holds the environment, is reached over
a pca9547 i2c mux with address 0x70, channel 3.
- CONFIG_ENV_IS_IN_DATAFLASH:
@@ -2493,13 +2547,6 @@ use the "saveenv" command to store a valid environment.
- CONFIG_SYS_FAULT_MII_ADDR:
MII address of the PHY to check for the Ethernet link state.
- CONFIG_SYS_64BIT_VSPRINTF:
Makes vsprintf (and all *printf functions) support printing
of 64bit values by using the L quantifier
- CONFIG_SYS_64BIT_STRTOUL:
Adds simple_strtoull that returns a 64bit value
- CONFIG_NS16550_MIN_FUNCTIONS:
Define this if you desire to only have use of the NS16550_init
and NS16550_putc functions for the serial driver located at
@@ -2958,7 +3005,9 @@ environment. As long as you don't save the environment you are
working with an in-memory copy. In case the Flash area containing the
environment is erased by accident, a default environment is provided.
Some configuration options can be set using Environment Variables:
Some configuration options can be set using Environment Variables.
List of environment variables (most likely not complete):
baudrate - see CONFIG_BAUDRATE
@@ -2993,14 +3042,6 @@ Some configuration options can be set using Environment Variables:
configuration from the BOOTP server, but not try to
load any image using TFTP
autoscript - if set to "yes" commands like "loadb", "loady",
"bootp", "tftpb", "rarpboot" and "nfs" will attempt
to automatically run script images (by internally
calling "source").
autoscript_uname - if script image is in a format (FIT) this
variable is used to get script subimage unit name.
autostart - if set to "yes", an image loaded using the "bootp",
"rarpboot", "tftpboot" or "diskboot" commands will
be automatically started (by internally calling
@@ -3078,7 +3119,7 @@ Some configuration options can be set using Environment Variables:
available network interfaces.
It just stays at the currently selected interface.
netretry - When set to "no" each network operation will
netretry - When set to "no" each network operation will
either succeed or fail without retrying.
When set to "once" the network operation will
fail when all the available network interfaces
@@ -3094,7 +3135,18 @@ Some configuration options can be set using Environment Variables:
tftpdstport - If this is set, the value is used for TFTP's UDP
destination port instead of the Well Know Port 69.
vlan - When set to a value < 4095 the traffic over
tftpblocksize - Block size to use for TFTP transfers; if not set,
we use the TFTP server's default block size
tftptimeout - Retransmission timeout for TFTP packets (in milli-
seconds, minimum value is 1000 = 1 second). Defines
when a packet is considered to be lost so it has to
be retransmitted. The default is 5000 = 5 seconds.
Lowering this value may make downloads succeed
faster in networks with high packet loss rates or
with unreliable TFTP servers.
vlan - When set to a value < 4095 the traffic over
Ethernet is encapsulated/received over 802.1q
VLAN tagged frames.
@@ -3893,7 +3945,9 @@ For PowerPC, the following registers have specific use:
R30: GOT pointer
R31: frame pointer
(U-Boot also uses R14 as internal GOT pointer.)
(U-Boot also uses R12 as internal GOT pointer. r12
is a volatile register so r12 needs to be reset when
going back and forth between asm and C)
==> U-Boot will use R2 to hold a pointer to the global data
@@ -3904,10 +3958,10 @@ For PowerPC, the following registers have specific use:
average for all boards 752 bytes for the whole U-Boot image,
624 text + 127 data).
On Blackfin, the normal C ABI (except for P5) is followed as documented here:
On Blackfin, the normal C ABI (except for P3) is followed as documented here:
http://docs.blackfin.uclinux.org/doku.php?id=application_binary_interface
==> U-Boot will use P5 to hold a pointer to the global data
==> U-Boot will use P3 to hold a pointer to the global data
On ARM, the following registers are used:

View File

@@ -0,0 +1,50 @@
#
# (C) Copyright 2003-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := cpux9k2.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

View File

@@ -0,0 +1 @@
TEXT_BASE = 0x23f00000

View File

@@ -0,0 +1,387 @@
/*
* (C) Copyright 2008-2009
* BuS Elektronik GmbH & Co. KG <www.bus-elektronik.de>
* Jens Scharsig <esw@bus-elektronik.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <exports.h>
#include <net.h>
#include <netdev.h>
#include <nand.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/at91_pio.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_mc.h>
#ifdef CONFIG_STATUS_LED
#include <status_led.h>
#endif
#ifdef CONFIG_VIDEO
#include <bus_vcxk.h>
extern unsigned long display_width;
extern unsigned long display_height;
#endif
#ifdef CONFIG_CMD_NAND
void cpux9k2_nand_hw_init(void);
#endif
DECLARE_GLOBAL_DATA_PTR;
/*
* Miscelaneous platform dependent initialisations
*/
int board_init(void)
{
at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
/* Enable Ctrlc */
console_init_f();
/* Correct IRDA resistor problem / Set PA23_TXD in Output */
writel(AT91_PMX_AA_TXD2, &pio->pioa.oer);
gd->bd->bi_arch_number = MACH_TYPE_EB_CPUX9K2;
/* adress of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
#ifdef CONFIG_STATUS_LED
status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
#endif
#ifdef CONFIG_CMD_NAND
cpux9k2_nand_hw_init();
#endif
return 0;
}
#ifdef CONFIG_MISC_INIT_R
int misc_init_r(void)
{
uchar mac[8];
uchar tm;
uchar midx;
uchar macn6, macn7;
#ifdef CONFIG_NET_MULTI
if (getenv("ethaddr") == NULL) {
if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x00,
CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
(uchar *) &mac, sizeof(mac)) != 0) {
puts("Error reading MAC from EEPROM\n");
} else {
tm = 0;
macn6 = 0;
macn7 = 0xFF;
for (midx = 0; midx < 6; midx++) {
if ((mac[midx] != 0) && (mac[midx] != 0xFF))
tm++;
macn6 += mac[midx];
macn7 ^= mac[midx];
}
if ((macn6 != mac[6]) || (macn7 != mac[7]))
tm = 0;
if (tm)
eth_setenv_enetaddr("ethaddr", mac);
else
puts("Error: invalid MAC at EEPROM\n");
}
}
#endif
gd->jt[XF_do_reset] = (void *) do_reset;
#ifdef CONFIG_STATUS_LED
status_led_set(STATUS_LED_BOOT, STATUS_LED_BLINKING);
#endif
return 0;
}
#endif
#ifdef CONFIG_RESET_PHY_R
void reset_phy(void)
{
udelay(10000);
eth_init(gd->bd);
}
#endif
/*
* DRAM initialisations
*/
int dram_init(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM;
gd->bd->bi_dram[0].size =
get_ram_size((volatile long *) PHYS_SDRAM, PHYS_SDRAM_SIZE);
return 0;
}
/*
* Ethernet initialisations
*/
#ifdef CONFIG_DRIVER_AT91EMAC
int board_eth_init(bd_t *bis)
{
int rc = 0;
rc = at91emac_register(bis, (u32) AT91_EMAC_BASE);
return rc;
}
#endif
/*
* Disk On Chip (NAND) Millenium initialization.
* The NAND lives in the CS2* space
*/
#if defined(CONFIG_CMD_NAND)
#define MASK_ALE (1 << 22) /* our ALE is AD22 */
#define MASK_CLE (1 << 21) /* our CLE is AD21 */
void cpux9k2_nand_hw_init(void)
{
unsigned long csr;
at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_mc_t *mc = (at91_mc_t *) AT91_MC_BASE;
/* Setup Smart Media, fitst enable the address range of CS3 */
writel(readl(&mc->ebi.csa) | AT91_EBI_CSA_CS3A, &mc->ebi.csa);
/* RWH = 1 | RWS = 0 | TDF = 1 | NWS = 3 */
csr = AT91_SMC_CSR_RWHOLD(1) | AT91_SMC_CSR_TDF(1) |
AT91_SMC_CSR_NWS(3) |
AT91_SMC_CSR_ACSS_STANDARD | AT91_SMC_CSR_DBW_8 |
AT91_SMC_CSR_WSEN;
writel(csr, &mc->smc.csr[3]);
writel(AT91_PMX_CA_SMOE | AT91_PMX_CA_SMWE, &pio->pioc.asr);
writel(AT91_PMX_CA_BFCK | AT91_PMX_CA_SMOE | AT91_PMX_CA_SMWE,
&pio->pioc.pdr);
/* Configure PC2 as input (signal Nand READY ) */
writel(AT91_PMX_CA_BFAVD, &pio->pioc.per);
writel(AT91_PMX_CA_BFAVD, &pio->pioc.odr); /* disable output */
writel(AT91_PMX_CA_BFCK, &pio->pioc.codr);
/* PIOC clock enabling */
writel(1 << AT91_ID_PIOC, &pmc->pcer);
}
static void board_nand_hwcontrol(struct mtd_info *mtd,
int cmd, unsigned int ctrl)
{
at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
struct nand_chip *this = mtd->priv;
ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
if (ctrl & NAND_CTRL_CHANGE) {
IO_ADDR_W &= ~(MASK_ALE | MASK_CLE);
if (ctrl & NAND_CLE)
IO_ADDR_W |= MASK_CLE;
if (ctrl & NAND_ALE)
IO_ADDR_W |= MASK_ALE;
if ((ctrl & NAND_NCE))
writel(1, &pio->pioc.codr);
else
writel(1, &pio->pioc.sodr);
this->IO_ADDR_W = (void *) IO_ADDR_W;
}
if (cmd != NAND_CMD_NONE)
writeb(cmd, this->IO_ADDR_W);
}
static int board_nand_dev_ready(struct mtd_info *mtd)
{
at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
return ((readl(&pio->pioc.pdsr) & (1 << 2)) != 0);
}
int board_nand_init(struct nand_chip *nand)
{
cpux9k2_nand_hw_init();
nand->ecc.mode = NAND_ECC_SOFT;
nand->cmd_ctrl = board_nand_hwcontrol;
nand->dev_ready = board_nand_dev_ready;
nand->chip_delay = 20;
return 0;
}
#endif
#if defined(CONFIG_VIDEO)
/*
* drv_video_init
* FUNCTION: initialize VCxK device
*/
int drv_video_init(void)
{
#ifdef CONFIG_SPLASH_SCREEN
unsigned long splash;
#endif
char *s;
unsigned long csr;
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_mc_t *mc = (at91_mc_t *) AT91_MC_BASE;
printf("Init Video as ");
s = getenv("displaywidth");
if (s != NULL)
display_width = simple_strtoul(s, NULL, 10);
else
display_width = 256;
s = getenv("displayheight");
if (s != NULL)
display_height = simple_strtoul(s, NULL, 10);
else
display_height = 256;
printf("%ld x %ld pixel matrix\n", display_width, display_height);
/* RWH = 7 | RWS =7 | TDF = 15 | NWS = 0x7F */
csr = AT91_SMC_CSR_RWHOLD(7) | AT91_SMC_CSR_RWSETUP(7) |
AT91_SMC_CSR_TDF(15) | AT91_SMC_CSR_NWS(127) |
AT91_SMC_CSR_ACSS_STANDARD | AT91_SMC_CSR_DBW_16 |
AT91_SMC_CSR_BAT_16 | AT91_SMC_CSR_WSEN;
writel(csr, &mc->smc.csr[2]);
writel(1 << AT91_ID_PIOB, &pmc->pcer);
vcxk_init(display_width, display_height);
#ifdef CONFIG_SPLASH_SCREEN
s = getenv("splashimage");
if (s != NULL) {
splash = simple_strtoul(s, NULL, 16);
printf("use splashimage: %lx\n", splash);
video_display_bitmap(splash, 0, 0);
}
#endif
return 0;
}
#endif
#ifdef CONFIG_SOFT_I2C
void i2c_init_board(void)
{
u32 pin;
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
writel(1 << AT91_ID_PIOA, &pmc->pcer);
pin = AT91_PMX_AA_TWD | AT91_PMX_AA_TWCK;
writel(pin, &pio->pioa.idr);
writel(pin, &pio->pioa.pudr);
writel(pin, &pio->pioa.per);
writel(pin, &pio->pioa.oer);
writel(pin, &pio->pioa.sodr);
}
#endif
/*--------------------------------------------------------------------------*/
#ifdef CONFIG_STATUS_LED
void __led_toggle(led_id_t mask)
{
at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
if (readl(&pio->piod.odsr) & mask)
writel(mask, &pio->piod.codr);
else
writel(mask, &pio->piod.codr);
}
void __led_init(led_id_t mask, int state)
{
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
writel(1 << AT91_ID_PIOD, &pmc->pcer); /* Enable PIOB clock */
/* Disable peripherals on LEDs */
writel(STATUS_LED_BIT | STATUS_LED_BIT1, &pio->piod.per);
/* Enable pins as outputs */
writel(STATUS_LED_BIT | STATUS_LED_BIT1, &pio->piod.oer);
/* Turn all LEDs OFF */
writel(STATUS_LED_BIT | STATUS_LED_BIT1, &pio->piod.sodr);
__led_set(mask, state);
}
void __led_set(led_id_t mask, int state)
{
at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
if (state == STATUS_LED_ON)
writel(mask, &pio->piod.codr);
else
writel(mask, &pio->piod.sodr);
}
#endif
/*---------------------------------------------------------------------------*/
int do_brightness(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
int rcode = 0;
ulong side;
ulong bright;
switch (argc) {
case 3:
side = simple_strtoul(argv[1], NULL, 10);
bright = simple_strtoul(argv[2], NULL, 10);
if ((side >= 0) && (side <= 3) &&
(bright >= 0) && (bright <= 1000)) {
vcxk_setbrightness(side, bright);
rcode = 0;
} else {
printf("parameters out of range\n");
printf("Usage:\n%s\n", cmdtp->usage);
rcode = 1;
}
break;
default:
printf("Usage:\n%s\n", cmdtp->usage);
rcode = 1;
break;
}
return rcode;
}
/*---------------------------------------------------------------------------*/
U_BOOT_CMD(
bright, 3, 0, do_brightness,
"bright - sets the display brightness\n",
" <side> <0..1000>\n side: 0/3=both; 1=first; 2=second\n"
);
/* EOF cpu9k2.c */

View File

@@ -68,7 +68,6 @@ Type "run nfsboot" to mount root filesystem over NFS
Hit any key to stop autoboot: 0
LEOX_elpt860: help
askenv - get environment variables from stdin
autoscr - run script from memory
base - print or set address offset
bdinfo - print Board Info structure
bootm - boot application image from memory
@@ -100,6 +99,7 @@ run - run commands in an environment variable
saveenv - save environment variables to persistent storage
setenv - set environment variables
sleep - delay execution for some time
source - run script from memory
tftpboot- boot image via network using TFTP protocol
and env variables ipaddr and serverip
version - print monitor version

View File

@@ -80,7 +80,6 @@ SECTIONS
common/env_embedded.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

View File

@@ -73,7 +73,6 @@ SECTIONS
common/env_embedded.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

View File

@@ -65,7 +65,6 @@ SECTIONS
common/env_embedded.o(.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

View File

@@ -63,7 +63,6 @@ SECTIONS
/* common/env_embedded.o(.text) */
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

View File

@@ -63,7 +63,6 @@ SECTIONS
/* common/env_embedded.o(.text) */
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

View File

@@ -23,3 +23,6 @@
#
TEXT_BASE = 0x00600000
# Kirkwood Boot Image configuration file
KWD_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/kwbimage.cfg

View File

@@ -0,0 +1,165 @@
#
# (C) Copyright 2009
# Marvell Semiconductor <www.marvell.com>
# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
# MA 02110-1301 USA
#
# Refer docs/README.kwimage for more details about how-to configure
# and create kirkwood boot image
#
# Boot Media configurations
BOOT_FROM spi # Boot from SPI flash
# SOC registers configuration using bootrom header extension
# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
# Configure RGMII-0 interface pad voltage to 1.8V
DATA 0xFFD100e0 0x1b1b1b9b
#Dram initalization for SINGLE x16 CL=5 @ 400MHz
DATA 0xFFD01400 0x43000a00 # DDR Configuration register
# bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
# bit23-14: zero
# bit24: 1= enable exit self refresh mode on DDR access
# bit25: 1 required
# bit29-26: zero
# bit31-30: 01
DATA 0xFFD01404 0x38543000 # DDR Controller Control Low
# bit 4: 0=addr/cmd in smame cycle
# bit 5: 0=clk is driven during self refresh, we don't care for APX
# bit 6: 0=use recommended falling edge of clk for addr/cmd
# bit14: 0=input buffer always powered up
# bit18: 1=cpu lock transaction enabled
# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
# bit30-28: 3 required
# bit31: 0=no additional STARTBURST delay
DATA 0xFFD01408 0x2202433D # DDR Timing (Low) (active cycles value +1)
# bit3-0: TRAS lsbs
# bit7-4: TRCD
# bit11- 8: TRP
# bit15-12: TWR
# bit19-16: TWTR
# bit20: TRAS msb
# bit23-21: 0x0
# bit27-24: TRRD
# bit31-28: TRTP
DATA 0xFFD0140C 0x0000002A # DDR Timing (High)
# bit6-0: TRFC
# bit8-7: TR2R
# bit10-9: TR2W
# bit12-11: TW2W
# bit31-13: zero required
DATA 0xFFD01410 0x0000000D # DDR Address Control
# bit1-0: 01, Cs0width=x16
# bit3-2: 11, Cs0size=1Gb
# bit5-4: 00, Cs2width=nonexistent
# bit7-6: 00, Cs1size =nonexistent
# bit9-8: 00, Cs2width=nonexistent
# bit11-10: 00, Cs2size =nonexistent
# bit13-12: 00, Cs3width=nonexistent
# bit15-14: 00, Cs3size =nonexistent
# bit16: 0, Cs0AddrSel
# bit17: 0, Cs1AddrSel
# bit18: 0, Cs2AddrSel
# bit19: 0, Cs3AddrSel
# bit31-20: 0 required
DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
# bit0: 0, OpenPage enabled
# bit31-1: 0 required
DATA 0xFFD01418 0x00000000 # DDR Operation
# bit3-0: 0x0, DDR cmd
# bit31-4: 0 required
DATA 0xFFD0141C 0x00000C52 # DDR Mode
# bit2-0: 2, BurstLen=2 required
# bit3: 0, BurstType=0 required
# bit6-4: 4, CL=5
# bit7: 0, TestMode=0 normal
# bit8: 0, DLL reset=0 normal
# bit11-9: 6, auto-precharge write recovery ????????????
# bit12: 0, PD must be zero
# bit31-13: 0 required
DATA 0xFFD01420 0x00000046 # DDR Extended Mode
# bit0: 0, DDR DLL enabled
# bit1: 1, DDR drive strenght reduced
# bit2: 1, DDR ODT control lsd enabled
# bit5-3: 000, required
# bit6: 1, DDR ODT control msb, enabled
# bit9-7: 000, required
# bit10: 0, differential DQS enabled
# bit11: 0, required
# bit12: 0, DDR output buffer enabled
# bit31-13: 0 required
DATA 0xFFD01424 0x0000F1FF # DDR Controller Control High
# bit2-0: 111, required
# bit3 : 1 , MBUS Burst Chop disabled
# bit6-4: 111, required
# bit7 : 1 , D2P Latency enabled
# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
# bit9 : 0 , no half clock cycle addition to dataout
# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
# bit15-12: 1111 required
# bit31-16: 0 required
DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size
# bit0: 1, Window enabled
# bit1: 0, Write Protect disabled
# bit3-2: 00, CS0 hit selected
# bit23-4: ones, required
# bit31-24: 0x07, Size (i.e. 128MB)
DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
DATA 0xFFD01494 0x00010001 # DDR ODT Control (Low)
# bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
# bit3-2: 01, ODT1 active NEVER!
# bit31-4: zero, required
DATA 0xFFD0149C 0x0000E811 # CPU ODT Control
# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
# bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
# bit11-10:1, DQ_ODTSel. ODT select turned on
DATA 0xFFD01480 0x00000001 # DDR Initialization Control
#bit0=1, enable DDR init upon this register write
# End of Header extension
DATA 0x0 0x0

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@@ -0,0 +1,56 @@
#
# (C) Copyright 2009
# Net Insight <www.netinsight.net>
# Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
#
# Based on sheevaplug:
# (C) Copyright 2009
# Marvell Semiconductor <www.marvell.com>
# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
# MA 02110-1301 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := openrd_base.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

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@@ -0,0 +1,33 @@
#
# (C) Copyright 2009
# Net Insight <www.netinsight.net>
# Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
#
# Based on sheevaplug:
# (C) Copyright 2009
# Marvell Semiconductor <www.marvell.com>
# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
# MA 02110-1301 USA
#
TEXT_BASE = 0x00600000
# Kirkwood Boot Image configuration file
KWD_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/kwbimage.cfg

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@@ -0,0 +1,168 @@
#
# (C) Copyright 2009
# Marvell Semiconductor <www.marvell.com>
# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
# MA 02110-1301 USA
#
# Refer docs/README.kwimage for more details about how-to configure
# and create kirkwood boot image
#
# Boot Media configurations
BOOT_FROM nand
NAND_ECC_MODE default
NAND_PAGE_SIZE 0x0800
# SOC registers configuration using bootrom header extension
# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
# Configure RGMII-0 interface pad voltage to 1.8V
DATA 0xFFD100e0 0x1b1b1b9b
#Dram initalization for SINGLE x16 CL=5 @ 400MHz
DATA 0xFFD01400 0x43000c30 # DDR Configuration register
# bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
# bit23-14: zero
# bit24: 1= enable exit self refresh mode on DDR access
# bit25: 1 required
# bit29-26: zero
# bit31-30: 01
DATA 0xFFD01404 0x37543000 # DDR Controller Control Low
# bit 4: 0=addr/cmd in smame cycle
# bit 5: 0=clk is driven during self refresh, we don't care for APX
# bit 6: 0=use recommended falling edge of clk for addr/cmd
# bit14: 0=input buffer always powered up
# bit18: 1=cpu lock transaction enabled
# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
# bit30-28: 3 required
# bit31: 0=no additional STARTBURST delay
DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
# bit3-0: TRAS lsbs
# bit7-4: TRCD
# bit11- 8: TRP
# bit15-12: TWR
# bit19-16: TWTR
# bit20: TRAS msb
# bit23-21: 0x0
# bit27-24: TRRD
# bit31-28: TRTP
DATA 0xFFD0140C 0x00000a33 # DDR Timing (High)
# bit6-0: TRFC
# bit8-7: TR2R
# bit10-9: TR2W
# bit12-11: TW2W
# bit31-13: zero required
DATA 0xFFD01410 0x000000cc # DDR Address Control
# bit1-0: 00, Cs0width=x8
# bit3-2: 11, Cs0size=1Gb
# bit5-4: 00, Cs1width=x8
# bit7-6: 11, Cs1size=1Gb
# bit9-8: 00, Cs2width=nonexistent
# bit11-10: 00, Cs2size =nonexistent
# bit13-12: 00, Cs3width=nonexistent
# bit15-14: 00, Cs3size =nonexistent
# bit16: 0, Cs0AddrSel
# bit17: 0, Cs1AddrSel
# bit18: 0, Cs2AddrSel
# bit19: 0, Cs3AddrSel
# bit31-20: 0 required
DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
# bit0: 0, OpenPage enabled
# bit31-1: 0 required
DATA 0xFFD01418 0x00000000 # DDR Operation
# bit3-0: 0x0, DDR cmd
# bit31-4: 0 required
DATA 0xFFD0141C 0x00000C52 # DDR Mode
# bit2-0: 2, BurstLen=2 required
# bit3: 0, BurstType=0 required
# bit6-4: 4, CL=5
# bit7: 0, TestMode=0 normal
# bit8: 0, DLL reset=0 normal
# bit11-9: 6, auto-precharge write recovery ????????????
# bit12: 0, PD must be zero
# bit31-13: 0 required
DATA 0xFFD01420 0x00000042 # DDR Extended Mode
# bit0: 0, DDR DLL enabled
# bit1: 1, DDR drive strength reduced
# bit2: 0, DDR ODT control lsd (disabled)
# bit5-3: 000, required
# bit6: 1, DDR ODT control msb, (disabled)
# bit9-7: 000, required
# bit10: 0, differential DQS enabled
# bit11: 0, required
# bit12: 0, DDR output buffer enabled
# bit31-13: 0 required
DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
# bit2-0: 111, required
# bit3 : 1 , MBUS Burst Chop disabled
# bit6-4: 111, required
# bit7 : 0
# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
# bit9 : 0 , no half clock cycle addition to dataout
# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
# bit15-12: 1111 required
# bit31-16: 0 required
DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
# bit0: 1, Window enabled
# bit1: 0, Write Protect disabled
# bit3-2: 00, CS0 hit selected
# bit23-4: ones, required
# bit31-24: 0x0F, Size (i.e. 256MB)
DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb
DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1
DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
DATA 0xFFD01494 0x00120012 # DDR ODT Control (Low)
# bit3-0: 0010, (read) M_ODT[0] is asserted during read from DRAM CS1
# bit7-4: 0001, (read) M_ODT[1] is asserted during read from DRAM CS0
# bit19-16: 0010, (write) M_ODT[0] is asserted during write to DRAM CS1.
# bit23-20: 0001, (write) M_ODT[1] is asserted during write to DRAM CS0.
DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
DATA 0xFFD0149C 0x0000E40f # CPU ODT Control
# bit3-0: 1111, internal ODT is asserted during read from DRAM bank 0-3
# bit11-10: 01, M_DQ, M_DM, and M_DQS I/O buffer ODT Select: 150 ohm
# bit13-12: 10, M_STARTBURST_IN I/O buffer ODT Select: 75 ohm
# bit14: 1, M_STARTBURST_IN ODT: Enabled
# bit15: 1, DDR IO ODT Unit: Use ODT block
DATA 0xFFD01480 0x00000001 # DDR Initialization Control
#bit0=1, enable DDR init upon this register write
# End of Header extension
DATA 0x0 0x0

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@@ -0,0 +1,160 @@
/*
* (C) Copyright 2009
* Net Insight <www.netinsight.net>
* Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
*
* Based on sheevaplug.c:
* (C) Copyright 2009
* Marvell Semiconductor <www.marvell.com>
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#include <common.h>
#include <miiphy.h>
#include <asm/arch/kirkwood.h>
#include <asm/arch/mpp.h>
#include "openrd_base.h"
DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
{
/*
* default gpio configuration
* There are maximum 64 gpios controlled through 2 sets of registers
* the below configuration configures mainly initial LED status
*/
kw_config_gpio(OPENRD_OE_VAL_LOW,
OPENRD_OE_VAL_HIGH,
OPENRD_OE_LOW, OPENRD_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */
u32 kwmpp_config[] = {
MPP0_NF_IO2,
MPP1_NF_IO3,
MPP2_NF_IO4,
MPP3_NF_IO5,
MPP4_NF_IO6,
MPP5_NF_IO7,
MPP6_SYSRST_OUTn,
MPP7_GPO,
MPP8_TW_SDA,
MPP9_TW_SCK,
MPP10_UART0_TXD,
MPP11_UART0_RXD,
MPP12_SD_CLK,
MPP13_SD_CMD, /* Alt UART1_TXD */
MPP14_SD_D0, /* Alt UART1_RXD */
MPP15_SD_D1,
MPP16_SD_D2,
MPP17_SD_D3,
MPP18_NF_IO0,
MPP19_NF_IO1,
MPP20_GE1_0,
MPP21_GE1_1,
MPP22_GE1_2,
MPP23_GE1_3,
MPP24_GE1_4,
MPP25_GE1_5,
MPP26_GE1_6,
MPP27_GE1_7,
MPP28_GPIO,
MPP29_TSMP9,
MPP30_GE1_10,
MPP31_GE1_11,
MPP32_GE1_12,
MPP33_GE1_13,
MPP34_GPIO, /* UART1 / SD sel */
MPP35_TDM_CH0_TX_QL,
MPP36_TDM_SPI_CS1,
MPP37_TDM_CH2_TX_QL,
MPP38_TDM_CH2_RX_QL,
MPP39_AUDIO_I2SBCLK,
MPP40_AUDIO_I2SDO,
MPP41_AUDIO_I2SLRC,
MPP42_AUDIO_I2SMCLK,
MPP43_AUDIO_I2SDI,
MPP44_AUDIO_EXTCLK,
MPP45_TDM_PCLK,
MPP46_TDM_FS,
MPP47_TDM_DRX,
MPP48_TDM_DTX,
MPP49_TDM_CH0_RX_QL,
0
};
kirkwood_mpp_conf(kwmpp_config);
/*
* arch number of board
*/
gd->bd->bi_arch_number = MACH_TYPE_OPENRD_BASE;
/* adress of boot parameters */
gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
return 0;
}
int dram_init(void)
{
int i;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
gd->bd->bi_dram[i].start = kw_sdram_bar(i);
gd->bd->bi_dram[i].size = kw_sdram_bs(i);
}
return 0;
}
#ifdef CONFIG_RESET_PHY_R
/* Configure and enable MV88E1116 PHY */
void reset_phy(void)
{
u16 reg;
u16 devadr;
char *name = "egiga0";
if (miiphy_set_current_dev(name))
return;
/* command to read PHY dev address */
if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
printf("Err..%s could not read PHY dev address\n",
__FUNCTION__);
return;
}
/*
* Enable RGMII delay on Tx and Rx for CPU port
* Ref: sec 4.7.2 of chip datasheet
*/
miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
/* reset the phy */
miiphy_reset(name, devadr);
printf("88E1116 Initialized on %s\n", name);
}
#endif /* CONFIG_RESET_PHY_R */

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@@ -0,0 +1,46 @@
/*
* (C) Copyright 2009
* Net Insight <www.netinsight.net>
* Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
*
* Based on sheevaplug.h:
* (C) Copyright 2009
* Marvell Semiconductor <www.marvell.com>
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef __OPENRD_BASE_H
#define __OPENRD_BASE_H
#define OPENRD_OE_LOW (~(1<<28)) /* RS232 / RS485 */
#define OPENRD_OE_HIGH (~(1<<2)) /* SD / UART1 */
#define OPENRD_OE_VAL_LOW (0) /* Sel RS232 */
#define OPENRD_OE_VAL_HIGH (1 << 2) /* Sel SD */
/* PHY related */
#define MV88E1116_LED_FCTRL_REG 10
#define MV88E1116_CPRSP_CR3_REG 21
#define MV88E1116_MAC_CTRL_REG 21
#define MV88E1116_PGADR_REG 22
#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
#endif /* __OPENRD_BASE_H */

View File

@@ -23,3 +23,6 @@
#
TEXT_BASE = 0x00600000
# Kirkwood Boot Image configuration file
KWD_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/kwbimage.cfg

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@@ -0,0 +1,167 @@
#
# (C) Copyright 2009
# Marvell Semiconductor <www.marvell.com>
# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
# MA 02110-1301 USA
#
# Refer docs/README.kwimage for more details about how-to configure
# and create kirkwood boot image
#
# Boot Media configurations
BOOT_FROM nand
NAND_ECC_MODE default
NAND_PAGE_SIZE 0x0800
# SOC registers configuration using bootrom header extension
# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
# Configure RGMII-0 interface pad voltage to 1.8V
DATA 0xFFD100e0 0x1b1b1b9b
#Dram initalization for SINGLE x16 CL=5 @ 400MHz
DATA 0xFFD01400 0x43000c30 # DDR Configuration register
# bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
# bit23-14: zero
# bit24: 1= enable exit self refresh mode on DDR access
# bit25: 1 required
# bit29-26: zero
# bit31-30: 01
DATA 0xFFD01404 0x37543000 # DDR Controller Control Low
# bit 4: 0=addr/cmd in smame cycle
# bit 5: 0=clk is driven during self refresh, we don't care for APX
# bit 6: 0=use recommended falling edge of clk for addr/cmd
# bit14: 0=input buffer always powered up
# bit18: 1=cpu lock transaction enabled
# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
# bit30-28: 3 required
# bit31: 0=no additional STARTBURST delay
DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
# bit3-0: TRAS lsbs
# bit7-4: TRCD
# bit11- 8: TRP
# bit15-12: TWR
# bit19-16: TWTR
# bit20: TRAS msb
# bit23-21: 0x0
# bit27-24: TRRD
# bit31-28: TRTP
DATA 0xFFD0140C 0x00000a33 # DDR Timing (High)
# bit6-0: TRFC
# bit8-7: TR2R
# bit10-9: TR2W
# bit12-11: TW2W
# bit31-13: zero required
DATA 0xFFD01410 0x00000099 # DDR Address Control
# bit1-0: 00, Cs0width=x8
# bit3-2: 11, Cs0size=1Gb
# bit5-4: 00, Cs1width=x8
# bit7-6: 11, Cs1size=1Gb
# bit9-8: 00, Cs2width=nonexistent
# bit11-10: 00, Cs2size =nonexistent
# bit13-12: 00, Cs3width=nonexistent
# bit15-14: 00, Cs3size =nonexistent
# bit16: 0, Cs0AddrSel
# bit17: 0, Cs1AddrSel
# bit18: 0, Cs2AddrSel
# bit19: 0, Cs3AddrSel
# bit31-20: 0 required
DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
# bit0: 0, OpenPage enabled
# bit31-1: 0 required
DATA 0xFFD01418 0x00000000 # DDR Operation
# bit3-0: 0x0, DDR cmd
# bit31-4: 0 required
DATA 0xFFD0141C 0x00000C52 # DDR Mode
# bit2-0: 2, BurstLen=2 required
# bit3: 0, BurstType=0 required
# bit6-4: 4, CL=5
# bit7: 0, TestMode=0 normal
# bit8: 0, DLL reset=0 normal
# bit11-9: 6, auto-precharge write recovery ????????????
# bit12: 0, PD must be zero
# bit31-13: 0 required
DATA 0xFFD01420 0x00000004 # DDR Extended Mode
# bit0: 0, DDR DLL enabled
# bit1: 0, DDR drive strenght normal
# bit2: 1, DDR ODT control lsd (disabled)
# bit5-3: 000, required
# bit6: 0, DDR ODT control msb, (disabled)
# bit9-7: 000, required
# bit10: 0, differential DQS enabled
# bit11: 0, required
# bit12: 0, DDR output buffer enabled
# bit31-13: 0 required
DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
# bit2-0: 111, required
# bit3 : 1 , MBUS Burst Chop disabled
# bit6-4: 111, required
# bit7 : 0
# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
# bit9 : 0 , no half clock cycle addition to dataout
# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
# bit15-12: 1111 required
# bit31-16: 0 required
DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
# bit0: 1, Window enabled
# bit1: 0, Write Protect disabled
# bit3-2: 00, CS0 hit selected
# bit23-4: ones, required
# bit31-24: 0x0F, Size (i.e. 256MB)
DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb
DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1
DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
DATA 0xFFD01494 0x00120012 # DDR ODT Control (Low)
# bit3-0: 2, ODT0Rd, MODT[0] asserted during read from DRAM CS1
# bit7-4: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
# bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1
# bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
# bit3-2: 01, ODT1 active NEVER!
# bit31-4: zero, required
DATA 0xFFD0149C 0x0000E40F # CPU ODT Control
DATA 0xFFD01480 0x00000001 # DDR Initialization Control
#bit0=1, enable DDR init upon this register write
# End of Header extension
DATA 0x0 0x0

View File

@@ -23,3 +23,6 @@
#
TEXT_BASE = 0x00600000
# Kirkwood Boot Image configuration file
KWD_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/kwbimage.cfg

View File

@@ -0,0 +1,162 @@
#
# (C) Copyright 2009
# Marvell Semiconductor <www.marvell.com>
# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
# MA 02110-1301 USA
#
# Refer docs/README.kwimage for more details about how-to configure
# and create kirkwood boot image
#
# Boot Media configurations
BOOT_FROM nand
NAND_ECC_MODE default
NAND_PAGE_SIZE 0x0800
# SOC registers configuration using bootrom header extension
# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
# Configure RGMII-0 interface pad voltage to 1.8V
DATA 0xFFD100e0 0x1b1b1b9b
#Dram initalization for SINGLE x16 CL=5 @ 400MHz
DATA 0xFFD01400 0x43000c30 # DDR Configuration register
# bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
# bit23-14: zero
# bit24: 1= enable exit self refresh mode on DDR access
# bit25: 1 required
# bit29-26: zero
# bit31-30: 01
DATA 0xFFD01404 0x37543000 # DDR Controller Control Low
# bit 4: 0=addr/cmd in smame cycle
# bit 5: 0=clk is driven during self refresh, we don't care for APX
# bit 6: 0=use recommended falling edge of clk for addr/cmd
# bit14: 0=input buffer always powered up
# bit18: 1=cpu lock transaction enabled
# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
# bit30-28: 3 required
# bit31: 0=no additional STARTBURST delay
DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
# bit3-0: TRAS lsbs
# bit7-4: TRCD
# bit11- 8: TRP
# bit15-12: TWR
# bit19-16: TWTR
# bit20: TRAS msb
# bit23-21: 0x0
# bit27-24: TRRD
# bit31-28: TRTP
DATA 0xFFD0140C 0x00000a33 # DDR Timing (High)
# bit6-0: TRFC
# bit8-7: TR2R
# bit10-9: TR2W
# bit12-11: TW2W
# bit31-13: zero required
DATA 0xFFD01410 0x000000cc # DDR Address Control
# bit1-0: 00, Cs0width=x8
# bit3-2: 11, Cs0size=1Gb
# bit5-4: 00, Cs1width=x8
# bit7-6: 11, Cs1size=1Gb
# bit9-8: 00, Cs2width=nonexistent
# bit11-10: 00, Cs2size =nonexistent
# bit13-12: 00, Cs3width=nonexistent
# bit15-14: 00, Cs3size =nonexistent
# bit16: 0, Cs0AddrSel
# bit17: 0, Cs1AddrSel
# bit18: 0, Cs2AddrSel
# bit19: 0, Cs3AddrSel
# bit31-20: 0 required
DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
# bit0: 0, OpenPage enabled
# bit31-1: 0 required
DATA 0xFFD01418 0x00000000 # DDR Operation
# bit3-0: 0x0, DDR cmd
# bit31-4: 0 required
DATA 0xFFD0141C 0x00000C52 # DDR Mode
# bit2-0: 2, BurstLen=2 required
# bit3: 0, BurstType=0 required
# bit6-4: 4, CL=5
# bit7: 0, TestMode=0 normal
# bit8: 0, DLL reset=0 normal
# bit11-9: 6, auto-precharge write recovery ????????????
# bit12: 0, PD must be zero
# bit31-13: 0 required
DATA 0xFFD01420 0x00000040 # DDR Extended Mode
# bit0: 0, DDR DLL enabled
# bit1: 0, DDR drive strenght normal
# bit2: 0, DDR ODT control lsd (disabled)
# bit5-3: 000, required
# bit6: 1, DDR ODT control msb, (disabled)
# bit9-7: 000, required
# bit10: 0, differential DQS enabled
# bit11: 0, required
# bit12: 0, DDR output buffer enabled
# bit31-13: 0 required
DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
# bit2-0: 111, required
# bit3 : 1 , MBUS Burst Chop disabled
# bit6-4: 111, required
# bit7 : 0
# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
# bit9 : 0 , no half clock cycle addition to dataout
# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
# bit15-12: 1111 required
# bit31-16: 0 required
DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
# bit0: 1, Window enabled
# bit1: 0, Write Protect disabled
# bit3-2: 00, CS0 hit selected
# bit23-4: ones, required
# bit31-24: 0x0F, Size (i.e. 256MB)
DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb
DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1
DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low)
DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
# bit3-2: 01, ODT1 active NEVER!
# bit31-4: zero, required
DATA 0xFFD0149C 0x0000E803 # CPU ODT Control
DATA 0xFFD01480 0x00000001 # DDR Initialization Control
#bit0=1, enable DDR init upon this register write
# End of Header extension
DATA 0x0 0x0

View File

@@ -67,7 +67,6 @@ SECTIONS
common/env_embedded.o(.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

View File

@@ -64,7 +64,6 @@ SECTIONS
common/env_embedded.o(.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

View File

@@ -67,7 +67,6 @@ SECTIONS
common/env_embedded.o(.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

View File

@@ -64,7 +64,6 @@ SECTIONS
common/env_embedded.o(.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

View File

@@ -67,7 +67,6 @@ SECTIONS
common/env_embedded.o(.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

View File

@@ -64,7 +64,6 @@ SECTIONS
common/env_embedded.o(.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

View File

@@ -69,7 +69,6 @@ SECTIONS
common/env_embedded.o (.ppcenv)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

View File

@@ -54,7 +54,6 @@ SECTIONS
{
cpu/mpc8xx/start.o (.text)
*(.text)
*(.fixup)
*(.got1)
. = ALIGN(16);
*(.eh_frame)

View File

@@ -149,7 +149,7 @@ int board_init(void)
#ifdef CONFIG_CMD_NAND
afeb9260_nand_hw_init();
#endif
at91_spi0_hw_init((1 << 0) || (1 << 1));
at91_spi0_hw_init((1 << 0) | (1 << 1));
#ifdef CONFIG_MACB
afeb9260_macb_hw_init();
#endif

View File

@@ -25,6 +25,7 @@
*/
#include <common.h>
#include <netdev.h>
#include <nios-io.h>
#if defined(CONFIG_SEVENSEG)
#include "../common/sevenseg.h"
@@ -79,3 +80,14 @@ int ide_preinit (void)
return 0;
}
#endif
#ifdef CONFIG_CMD_NET
int board_eth_init(bd_t *bis)
{
int rc = 0;
#ifdef CONFIG_CS8900
rc = cs8900_initialize(0, CONFIG_CS8900_BASE);
#endif
return rc;
}
#endif

View File

@@ -22,6 +22,7 @@
*/
#include <common.h>
#include <netdev.h>
#if defined(CONFIG_SEVENSEG)
#include "../common/sevenseg.h"
#endif
@@ -58,3 +59,14 @@ phys_size_t initdram (int board_type)
{
return (0);
}
#ifdef CONFIG_CMD_NET
int board_eth_init(bd_t *bis)
{
int rc = 0;
#ifdef CONFIG_CS8900
rc = cs8900_initialize(0, CONFIG_CS8900_BASE);
#endif
return rc;
}
#endif

View File

@@ -22,6 +22,7 @@
*/
#include <common.h>
#include <netdev.h>
int board_early_init_f (void)
{
@@ -38,3 +39,14 @@ phys_size_t initdram (int board_type)
{
return (0);
}
#ifdef CONFIG_CMD_NET
int board_eth_init(bd_t *bis)
{
int rc = 0;
#ifdef CONFIG_SMC91111
rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
#endif
return rc;
}
#endif

View File

@@ -22,6 +22,7 @@
*/
#include <common.h>
#include <netdev.h>
int board_early_init_f (void)
{
@@ -38,3 +39,14 @@ phys_size_t initdram (int board_type)
{
return (0);
}
#ifdef CONFIG_CMD_NET
int board_eth_init(bd_t *bis)
{
int rc = 0;
#ifdef CONFIG_SMC91111
rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
#endif
return rc;
}
#endif

View File

@@ -22,6 +22,7 @@
*/
#include <common.h>
#include <netdev.h>
int checkboard (void)
{
@@ -33,3 +34,14 @@ phys_size_t initdram (int board_type)
{
return (0);
}
#ifdef CONFIG_CMD_NET
int board_eth_init(bd_t *bis)
{
int rc = 0;
#ifdef CONFIG_SMC91111
rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
#endif
return rc;
}
#endif

View File

@@ -57,7 +57,7 @@ int board_early_init_f(void)
#if !defined(CONFIG_NAND_U_BOOT)
/* don't reinit PLL when booting via I2C bootstrap option */
mfsdr(SDR_PINSTP, reg);
mfsdr(SDR0_PINSTP, reg);
if (reg != 0xf0000000)
board_pll_init_f();
#endif
@@ -65,25 +65,25 @@ int board_early_init_f(void)
acadia_gpio_init();
/* Configure 405EZ for NAND usage */
mtsdr(sdrnand0, SDR_NAND0_NDEN | SDR_NAND0_NDAREN | SDR_NAND0_NDRBEN);
mfsdr(sdrultra0, reg);
mtsdr(SDR0_NAND0, SDR_NAND0_NDEN | SDR_NAND0_NDAREN | SDR_NAND0_NDRBEN);
mfsdr(SDR0_ULTRA0, reg);
reg &= ~SDR_ULTRA0_CSN_MASK;
reg |= (SDR_ULTRA0_CSNSEL0 >> CONFIG_SYS_NAND_CS) |
SDR_ULTRA0_NDGPIOBP |
SDR_ULTRA0_EBCRDYEN |
SDR_ULTRA0_NFSRSTEN;
mtsdr(sdrultra0, reg);
mtsdr(SDR0_ULTRA0, reg);
/* USB Host core needs this bit set */
mfsdr(sdrultra1, reg);
mtsdr(sdrultra1, reg | SDR_ULTRA1_LEDNENABLE);
mfsdr(SDR0_ULTRA1, reg);
mtsdr(SDR0_ULTRA1, reg | SDR_ULTRA1_LEDNENABLE);
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000010);
mtdcr(uicpr, 0xFE7FFFF0); /* set int polarities */
mtdcr(uictr, 0x00000010); /* set int trigger levels */
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
mtdcr(UIC0CR, 0x00000010);
mtdcr(UIC0PR, 0xFE7FFFF0); /* set int polarities */
mtdcr(UIC0TR, 0x00000010); /* set int trigger levels */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
return 0;
}

View File

@@ -34,3 +34,7 @@ endif
ifeq ($(debug),1)
PLATFORM_CPPFLAGS += -DDEBUG
endif
ifdef CONFIG_NAND_U_BOOT
LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot-nand.lds
endif

View File

@@ -65,7 +65,7 @@ phys_size_t initdram(int board_type)
u32 reg;
/* don't reinit PLL when booting via I2C bootstrap option */
mfsdr(SDR_PINSTP, reg);
mfsdr(SDR0_PINSTP, reg);
if (reg != 0xf0000000)
board_pll_init_f();
#endif
@@ -81,25 +81,25 @@ phys_size_t initdram(int board_type)
gpio_config(CONFIG_SYS_GPIO_CRAM_WAIT, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG);
/* 2. EBC in Async mode */
mtebc(pb1ap, 0x078F1EC0);
mtebc(pb2ap, 0x078F1EC0);
mtebc(pb1cr, 0x000BC000);
mtebc(pb2cr, 0x020BC000);
mtebc(PB1AP, 0x078F1EC0);
mtebc(PB2AP, 0x078F1EC0);
mtebc(PB1CR, 0x000BC000);
mtebc(PB2CR, 0x020BC000);
/* 3. Set CRAM in Sync mode */
cram_bcr_write(0x7012); /* CRAM burst setting */
/* 4. EBC in Sync mode */
mtebc(pb1ap, 0x9C0201C0);
mtebc(pb2ap, 0x9C0201C0);
mtebc(PB1AP, 0x9C0201C0);
mtebc(PB2AP, 0x9C0201C0);
/* Set GPIO pins back to alternate function */
gpio_config(CONFIG_SYS_GPIO_CRAM_CLK, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG);
gpio_config(CONFIG_SYS_GPIO_CRAM_ADV, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG);
/* Config EBC to use RDY */
mfsdr(sdrultra0, val);
mtsdr(sdrultra0, val | SDR_ULTRA0_EBCRDYEN);
mfsdr(SDR0_ULTRA0, val);
mtsdr(SDR0_ULTRA0, val | SDR_ULTRA0_EBCRDYEN);
/* Wait a short while, since for NAND booting this is too fast */
for (i=0; i<200000; i++)

View File

@@ -51,11 +51,11 @@ void board_pll_init_f(void)
*/
/* Initialize PLL */
mtcpr(cprpllc, 0x0000033c);
mtcpr(cprplld, 0x0c010200);
mtcpr(cprprimad, 0x04060c0c);
mtcpr(cprperd0, 0x000c0000); /* SPI clk div. eq. OPB clk div. */
mtcpr(cprclkupd, 0x40000000);
mtcpr(CPR0_PLLC, 0x0000033c);
mtcpr(CPR0_PLLD, 0x0c010200);
mtcpr(CPC0_PRIMAD, 0x04060c0c);
mtcpr(CPC0_PERD0, 0x000c0000); /* SPI clk div. eq. OPB clk div. */
mtcpr(CPR0_CLKUP, 0x40000000);
}
#elif defined(PLLMR0_266_160_80)
@@ -83,13 +83,13 @@ void board_pll_init_f(void)
*/
/* Initialize PLL */
mtcpr(cprpllc, 0x20000238);
mtcpr(cprplld, 0x03010400);
mtcpr(cprprimad, 0x03050a0a);
mtcpr(cprperc0, 0x00000000);
mtcpr(cprperd0, 0x070a0707); /* SPI clk div. eq. OPB clk div. */
mtcpr(cprperd1, 0x07323200);
mtcpr(cprclkupd, 0x40000000);
mtcpr(CPR0_PLLC, 0x20000238);
mtcpr(CPR0_PLLD, 0x03010400);
mtcpr(CPC0_PRIMAD, 0x03050a0a);
mtcpr(CPC0_PERC0, 0x00000000);
mtcpr(CPC0_PERD0, 0x070a0707); /* SPI clk div. eq. OPB clk div. */
mtcpr(CPC0_PERD1, 0x07323200);
mtcpr(CPR0_CLKUP, 0x40000000);
}
#elif defined(PLLMR0_333_166_83)
@@ -117,12 +117,12 @@ void board_pll_init_f(void)
*/
/* Initialize PLL */
mtcpr(cprpllc, 0x0000033C);
mtcpr(cprplld, 0x0a010000);
mtcpr(cprprimad, 0x02040808);
mtcpr(cprperd0, 0x02080505); /* SPI clk div. eq. OPB clk div. */
mtcpr(cprperd1, 0xA6A60300);
mtcpr(cprclkupd, 0x40000000);
mtcpr(CPR0_PLLC, 0x0000033C);
mtcpr(CPR0_PLLD, 0x0a010000);
mtcpr(CPC0_PRIMAD, 0x02040808);
mtcpr(CPC0_PERD0, 0x02080505); /* SPI clk div. eq. OPB clk div. */
mtcpr(CPC0_PERD1, 0xA6A60300);
mtcpr(CPR0_CLKUP, 0x40000000);
}
#elif defined(PLLMR0_100_100_12)
@@ -143,12 +143,12 @@ void board_pll_init_f(void)
*/
/* Initialize PLL */
mtcpr(cprpllc, 0x000003BC);
mtcpr(cprplld, 0x06060600);
mtcpr(cprprimad, 0x02020004);
mtcpr(cprperd0, 0x04002828); /* SPI clk div. eq. OPB clk div. */
mtcpr(cprperd1, 0xC8C81600);
mtcpr(cprclkupd, 0x40000000);
mtcpr(CPR0_PLLC, 0x000003BC);
mtcpr(CPR0_PLLD, 0x06060600);
mtcpr(CPC0_PRIMAD, 0x02020004);
mtcpr(CPC0_PERD0, 0x04002828); /* SPI clk div. eq. OPB clk div. */
mtcpr(CPC0_PERD1, 0xC8C81600);
mtcpr(CPR0_CLKUP, 0x40000000);
}
#endif /* CPU_<speed>_405EZ */
@@ -167,12 +167,12 @@ unsigned long get_tbclk(void)
/*
* Read PLL Mode registers
*/
mfcpr(cprplld, cpr_plld);
mfcpr(CPR0_PLLD, cpr_plld);
/*
* Read CPR_PRIMAD register
*/
mfcpr(cprprimad, cpr_primad);
mfcpr(CPC0_PRIMAD, cpr_primad);
/*
* Determine CPU clock frequency

View File

@@ -62,7 +62,6 @@ SECTIONS
. = ALIGN(0x10000);
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

View File

@@ -1,135 +0,0 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
.resetvec 0xFFFFFFFC :
{
*(.resetvec)
} = 0xffff
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
. = ALIGN(4);
}
_end = . ;
PROVIDE (end = .);
}

View File

@@ -392,21 +392,21 @@ int board_early_init_f(void)
/*--------------------------------------------------------------------
* Setup the interrupt controller polarities, triggers, etc.
*-------------------------------------------------------------------*/
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic0er, 0x00000000); /* disable all */
mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */
mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(UIC0SR, 0xffffffff); /* clear all */
mtdcr(UIC0ER, 0x00000000); /* disable all */
mtdcr(UIC0CR, 0x00000009); /* ATI & UIC1 crit are critical */
mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */
mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */
mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(UIC0SR, 0xffffffff); /* clear all */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(uic1er, 0x00000000); /* disable all */
mtdcr(uic1cr, 0x00000000); /* all non-critical */
mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
mtdcr(UIC1ER, 0x00000000); /* disable all */
mtdcr(UIC1CR, 0x00000000); /* all non-critical */
mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */
mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */
mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
/*--------------------------------------------------------------------
* Setup the GPIO pins
@@ -466,166 +466,6 @@ phys_size_t initdram (int board_type)
#endif
}
/*************************************************************************
* pci_pre_init
*
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things. Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted.
*
* Different boards may wish to customize the pci controller structure
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller *hose)
{
unsigned long addr;
/*-------------------------------------------------------------------------+
| Set priority for all PLB3 devices to 0.
| Set PLB3 arbiter to fair mode.
+-------------------------------------------------------------------------*/
mfsdr(sdr_amp1, addr);
mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(plb3_acr);
mtdcr(plb3_acr, addr | 0x80000000);
/*-------------------------------------------------------------------------+
| Set priority for all PLB4 devices to 0.
+-------------------------------------------------------------------------*/
mfsdr(sdr_amp0, addr);
mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
mtdcr(plb4_acr, addr);
/*-------------------------------------------------------------------------+
| Set Nebula PLB4 arbiter to fair mode.
+-------------------------------------------------------------------------*/
/* Segment0 */
addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
mtdcr(plb0_acr, addr);
/* Segment1 */
addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
mtdcr(plb1_acr, addr);
return 1;
}
#endif /* defined(CONFIG_PCI) */
/*************************************************************************
* pci_target_init
*
* The bootstrap configuration provides default settings for the pci
* inbound map (PIM). But the bootstrap config choices are limited and
* may not be sufficient for a given board.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller *hose)
{
/*--------------------------------------------------------------------------+
* Set up Direct MMIO registers
*--------------------------------------------------------------------------*/
/*--------------------------------------------------------------------------+
| PowerPC440 EP PCI Master configuration.
| Map one 1Gig range of PLB/processor addresses to PCI memory space.
| PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
| Use byte reversed out routines to handle endianess.
| Make this region non-prefetchable.
+--------------------------------------------------------------------------*/
out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
/*--------------------------------------------------------------------------+
* Set up Configuration registers
*--------------------------------------------------------------------------*/
/* Program the board's subsystem id/vendor id */
pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
CONFIG_SYS_PCI_SUBSYS_VENDORID);
pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID);
/* Configure command register as bus master */
pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
/* 240nS PCI clock */
pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
/* No error reporting */
pci_write_config_word(0, PCI_ERREN, 0);
pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
}
#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
/*************************************************************************
* pci_master_init
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
void pci_master_init(struct pci_controller *hose)
{
unsigned short temp_short;
/*--------------------------------------------------------------------------+
| Write the PowerPC440 EP PCI Configuration regs.
| Enable PowerPC440 EP to be a master on the PCI bus (PMM).
| Enable PowerPC440 EP to act as a PCI memory target (PTM).
+--------------------------------------------------------------------------*/
pci_read_config_word(0, PCI_COMMAND, &temp_short);
pci_write_config_word(0, PCI_COMMAND,
temp_short | PCI_COMMAND_MASTER |
PCI_COMMAND_MEMORY);
}
#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
/*************************************************************************
* is_pci_host
*
* This routine is called to determine if a pci scan should be
* performed. With various hardware environments (especially cPCI and
* PPMC) it's insufficient to depend on the state of the arbiter enable
* bit in the strap register, or generic host/adapter assumptions.
*
* Rather than hard-code a bad assumption in the general 440 code, the
* 440 pci code requires the board to decide at runtime.
*
* Return 0 for adapter mode, non-zero for host (monarch) mode.
*
*
************************************************************************/
#if defined(CONFIG_PCI)
int is_pci_host(struct pci_controller *hose)
{
/* Bamboo is always configured as host. */
return (1);
}
#endif /* defined(CONFIG_PCI) */
/*----------------------------------------------------------------------------+
| is_powerpc440ep_pass1.
+----------------------------------------------------------------------------*/
@@ -695,8 +535,8 @@ void ext_bus_cntlr_init(void)
|
+-------------------------------------------------------------------------*/
/* NVRAM - FPGA */
mtebc(pb5ap, EBC0_BNAP_NVRAM_FPGA);
mtebc(pb5cr, EBC0_BNCR_NVRAM_FPGA_CS5);
mtebc(PB5AP, EBC0_BNAP_NVRAM_FPGA);
mtebc(PB5CR, EBC0_BNCR_NVRAM_FPGA_CS5);
/*-------------------------------------------------------------------------+
|
@@ -749,7 +589,7 @@ void ext_bus_cntlr_init(void)
case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN:
/* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */
/* Read Serial Device Strap Register1 in PPC440EP */
mfsdr(sdr_sdstp1, sdr0_sdstp1);
mfsdr(SDR0_SDSTP1, sdr0_sdstp1);
boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
@@ -822,7 +662,7 @@ void ext_bus_cntlr_init(void)
/* Default Strap Settings 5-7 */
/* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */
/* Read Serial Device Strap Register1 in PPC440EP */
mfsdr(sdr_sdstp1, sdr0_sdstp1);
mfsdr(SDR0_SDSTP1, sdr0_sdstp1);
boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
@@ -1013,8 +853,8 @@ void ext_bus_cntlr_init(void)
/*-------------------------------------------------------------------------+
| Initialize EBC CONFIG
+-------------------------------------------------------------------------*/
mtdcr(ebccfga, xbcfg);
mtdcr(ebccfgd, EBC0_CFG_EBTC_DRIVEN |
mtdcr(EBC0_CFGADDR, EBC0_CFG);
mtdcr(EBC0_CFGDATA, EBC0_CFG_EBTC_DRIVEN |
EBC0_CFG_PTD_ENABLED |
EBC0_CFG_RTC_2048PERCLK |
EBC0_CFG_EMPL_LOW |
@@ -1029,20 +869,20 @@ void ext_bus_cntlr_init(void)
| Initialize EBC Bank 0-4
+-------------------------------------------------------------------------*/
/* EBC Bank0 */
mtebc(pb0ap, ebc0_cs0_bnap_value);
mtebc(pb0cr, ebc0_cs0_bncr_value);
mtebc(PB0AP, ebc0_cs0_bnap_value);
mtebc(PB0CR, ebc0_cs0_bncr_value);
/* EBC Bank1 */
mtebc(pb1ap, ebc0_cs1_bnap_value);
mtebc(pb1cr, ebc0_cs1_bncr_value);
mtebc(PB1AP, ebc0_cs1_bnap_value);
mtebc(PB1CR, ebc0_cs1_bncr_value);
/* EBC Bank2 */
mtebc(pb2ap, ebc0_cs2_bnap_value);
mtebc(pb2cr, ebc0_cs2_bncr_value);
mtebc(PB2AP, ebc0_cs2_bnap_value);
mtebc(PB2CR, ebc0_cs2_bncr_value);
/* EBC Bank3 */
mtebc(pb3ap, ebc0_cs3_bnap_value);
mtebc(pb3cr, ebc0_cs3_bncr_value);
mtebc(PB3AP, ebc0_cs3_bnap_value);
mtebc(PB3CR, ebc0_cs3_bncr_value);
/* EBC Bank4 */
mtebc(pb4ap, ebc0_cs4_bnap_value);
mtebc(pb4cr, ebc0_cs4_bncr_value);
mtebc(PB4AP, ebc0_cs4_bnap_value);
mtebc(PB4CR, ebc0_cs4_bncr_value);
return;
}
@@ -1939,10 +1779,10 @@ void configure_ppc440ep_pins(void)
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_USB2D_SEL;
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_DISABLE;
mfsdr(sdr_usb0, sdr0_usb0);
mfsdr(SDR0_USB0, sdr0_usb0);
sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK;
sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB20D_DEVSEL;
mtsdr(sdr_usb0, sdr0_usb0);
mtsdr(SDR0_USB0, sdr0_usb0);
usb2_device_selection_in_fpga();
}
@@ -1950,19 +1790,19 @@ void configure_ppc440ep_pins(void)
/* USB1.1 Device Selection */
if (ppc440ep_core_selection[USB1_DEVICE] == CORE_SELECTED)
{
mfsdr(sdr_usb0, sdr0_usb0);
mfsdr(SDR0_USB0, sdr0_usb0);
sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK;
sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB11D_DEVSEL;
mtsdr(sdr_usb0, sdr0_usb0);
mtsdr(SDR0_USB0, sdr0_usb0);
}
/* USB1.1 Host Selection */
if (ppc440ep_core_selection[USB1_HOST] == CORE_SELECTED)
{
mfsdr(sdr_usb0, sdr0_usb0);
mfsdr(SDR0_USB0, sdr0_usb0);
sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_LEEN_MASK;
sdr0_usb0 = sdr0_usb0 | SDR0_USB0_LEEN_ENABLE;
mtsdr(sdr_usb0, sdr0_usb0);
mtsdr(SDR0_USB0, sdr0_usb0);
}
/* NAND Flash Selection */
@@ -1971,14 +1811,14 @@ void configure_ppc440ep_pins(void)
update_ndfc_ios(gpio_tab);
#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
mtsdr(sdr_cust0, SDR0_CUST0_MUX_NDFC_SEL |
mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_NDFC_SEL |
SDR0_CUST0_NDFC_ENABLE |
SDR0_CUST0_NDFC_BW_8_BIT |
SDR0_CUST0_NDFC_ARE_MASK |
SDR0_CUST0_CHIPSELGAT_EN1 |
SDR0_CUST0_CHIPSELGAT_EN2);
#else
mtsdr(sdr_cust0, SDR0_CUST0_MUX_NDFC_SEL |
mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_NDFC_SEL |
SDR0_CUST0_NDFC_ENABLE |
SDR0_CUST0_NDFC_BW_8_BIT |
SDR0_CUST0_NDFC_ARE_MASK |
@@ -1991,16 +1831,16 @@ void configure_ppc440ep_pins(void)
else
{
/* Set Mux on EMAC */
mtsdr(sdr_cust0, SDR0_CUST0_MUX_EMAC_SEL);
mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_EMAC_SEL);
}
/* MII Selection */
if (ppc440ep_core_selection[MII_SEL] == CORE_SELECTED)
{
update_zii_ios(gpio_tab);
mfsdr(sdr_mfr, sdr0_mfr);
mfsdr(SDR0_MFR, sdr0_mfr);
sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_MII;
mtsdr(sdr_mfr, sdr0_mfr);
mtsdr(SDR0_MFR, sdr0_mfr);
set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_MII);
}
@@ -2009,9 +1849,9 @@ void configure_ppc440ep_pins(void)
if (ppc440ep_core_selection[RMII_SEL] == CORE_SELECTED)
{
update_zii_ios(gpio_tab);
mfsdr(sdr_mfr, sdr0_mfr);
mfsdr(SDR0_MFR, sdr0_mfr);
sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
mtsdr(sdr_mfr, sdr0_mfr);
mtsdr(SDR0_MFR, sdr0_mfr);
set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_RMII);
}
@@ -2020,9 +1860,9 @@ void configure_ppc440ep_pins(void)
if (ppc440ep_core_selection[SMII_SEL] == CORE_SELECTED)
{
update_zii_ios(gpio_tab);
mfsdr(sdr_mfr, sdr0_mfr);
mfsdr(SDR0_MFR, sdr0_mfr);
sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_SMII;
mtsdr(sdr_mfr, sdr0_mfr);
mtsdr(SDR0_MFR, sdr0_mfr);
set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_SMII);
}
@@ -2071,13 +1911,13 @@ void configure_ppc440ep_pins(void)
/* Packet Reject Function Enable */
if (ppc440ep_core_selection[PACKET_REJ_FUNC_EN] == CORE_SELECTED)
{
mfsdr(sdr_mfr, sdr0_mfr);
mfsdr(SDR0_MFR, sdr0_mfr);
sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_PKT_REJ_MASK) | SDR0_MFR_PKT_REJ_EN;;
mtsdr(sdr_mfr, sdr0_mfr);
mtsdr(SDR0_MFR, sdr0_mfr);
}
/* Perform effective access to hardware */
mtsdr(sdr_pfc1, sdr0_pfc1);
mtsdr(SDR0_PFC1, sdr0_pfc1);
set_chip_gpio_configuration(GPIO0, gpio_tab);
set_chip_gpio_configuration(GPIO1, gpio_tab);

View File

@@ -36,3 +36,7 @@ endif
ifeq ($(dbcr),1)
PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
endif
ifdef CONFIG_NAND_U_BOOT
LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot-nand.lds
endif

View File

@@ -94,7 +94,7 @@ unsigned long flash_init(void)
* Boot Settings in IIC EEprom address 0xA8 or 0xA4
* Read Serial Device Strap Register1 in PPC440EP
*/
mfsdr(sdr_sdstp1, val);
mfsdr(SDR0_SDSTP1, val);
boot_selection = val & SDR0_SDSTP1_BOOT_SEL_MASK;
ebc_boot_size = val & SDR0_SDSTP1_EBC_ROM_BS_MASK;

View File

@@ -62,7 +62,6 @@ SECTIONS
. = ALIGN(0x10000);
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

View File

@@ -1,144 +0,0 @@
/*
* (C) Copyright 2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
.resetvec 0xFFFFFFFC :
{
*(.resetvec)
} = 0xffff
.bootpg 0xFFFFF000 :
{
cpu/ppc4xx/start.o (.bootpg)
} = 0xffff
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text)
board/amcc/bamboo/init.o (.text)
board/amcc/bamboo/bamboo.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
. = ALIGN(4);
}
_end = . ;
PROVIDE (end = .);
}

View File

@@ -29,21 +29,21 @@ long int spd_sdram(void);
int board_early_init_f(void)
{
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000010);
mtdcr(uicpr, 0xFFFF7FF0); /* set int polarities */
mtdcr(uictr, 0x00000010); /* set int trigger levels */
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
mtdcr(UIC0CR, 0x00000010);
mtdcr(UIC0PR, 0xFFFF7FF0); /* set int polarities */
mtdcr(UIC0TR, 0x00000010); /* set int trigger levels */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
/*
* Configure CPC0_PCI to enable PerWE as output
* and enable the internal PCI arbiter if selected
*/
if (in_8((void *)FPGA_REG1) & FPGA_REG1_PCI_INT_ARB)
mtdcr(cpc0_pci, CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN);
mtdcr(CPC0_PCI, CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN);
else
mtdcr(cpc0_pci, CPC0_PCI_HOST_CFG_EN);
mtdcr(CPC0_PCI, CPC0_PCI_HOST_CFG_EN);
return 0;
}

View File

@@ -106,25 +106,25 @@ unsigned long flash_init(void)
/* Re-do sizing to get full correct info */
if (size_b1) {
mtdcr(ebccfga, pb0cr);
pbcr = mfdcr(ebccfgd);
mtdcr(ebccfga, pb0cr);
mtdcr(EBC0_CFGADDR, PB0CR);
pbcr = mfdcr(EBC0_CFGDATA);
mtdcr(EBC0_CFGADDR, PB0CR);
base_b1 = -size_b1;
pbcr = (pbcr & 0x0001ffff) | base_b1 |
(((size_b1 / 1024 / 1024) - 1) << 17);
mtdcr(ebccfgd, pbcr);
/* printf("pb1cr = %x\n", pbcr); */
mtdcr(EBC0_CFGDATA, pbcr);
/* printf("PB1CR = %x\n", pbcr); */
}
if (size_b0) {
mtdcr(ebccfga, pb1cr);
pbcr = mfdcr(ebccfgd);
mtdcr(ebccfga, pb1cr);
mtdcr(EBC0_CFGADDR, PB1CR);
pbcr = mfdcr(EBC0_CFGDATA);
mtdcr(EBC0_CFGADDR, PB1CR);
base_b0 = base_b1 - size_b0;
pbcr = (pbcr & 0x0001ffff) | base_b0 |
(((size_b0 / 1024 / 1024) - 1) << 17);
mtdcr(ebccfgd, pbcr);
/* printf("pb0cr = %x\n", pbcr); */
mtdcr(EBC0_CFGDATA, pbcr);
/* printf("PB0CR = %x\n", pbcr); */
}
size_b0 = flash_get_size((vu_long *) base_b0, &flash_info[0]);

View File

@@ -1,135 +0,0 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
.resetvec 0xFFFFFFFC :
{
*(.resetvec)
} = 0xffff
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
. = ALIGN(4);
}
_end = . ;
PROVIDE (end = .);
}

View File

@@ -28,6 +28,7 @@
#include <asm/mmu.h>
#include <asm/4xx_pcie.h>
#include <asm/gpio.h>
#include <asm/errno.h>
extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
@@ -116,37 +117,37 @@ int board_early_init_f(void)
/*
* Setup the interrupt controller polarities, triggers, etc.
*/
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic0er, 0x00000000); /* disable all */
mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
mtdcr(uic0pr, 0xffffffff); /* per ref-board manual */
mtdcr(uic0tr, 0x00000000); /* per ref-board manual */
mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(UIC0SR, 0xffffffff); /* clear all */
mtdcr(UIC0ER, 0x00000000); /* disable all */
mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
mtdcr(UIC0PR, 0xffffffff); /* per ref-board manual */
mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */
mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC0SR, 0xffffffff); /* clear all */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(uic1er, 0x00000000); /* disable all */
mtdcr(uic1cr, 0x00000000); /* all non-critical */
mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */
mtdcr(uic1tr, 0x00000000); /* per ref-board manual */
mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
mtdcr(UIC1ER, 0x00000000); /* disable all */
mtdcr(UIC1CR, 0x00000000); /* all non-critical */
mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */
mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */
mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
mtdcr(uic2sr, 0xffffffff); /* clear all */
mtdcr(uic2er, 0x00000000); /* disable all */
mtdcr(uic2cr, 0x00000000); /* all non-critical */
mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */
mtdcr(uic2tr, 0x00000000); /* per ref-board manual */
mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic2sr, 0xffffffff); /* clear all */
mtdcr(UIC2SR, 0xffffffff); /* clear all */
mtdcr(UIC2ER, 0x00000000); /* disable all */
mtdcr(UIC2CR, 0x00000000); /* all non-critical */
mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */
mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */
mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC2SR, 0xffffffff); /* clear all */
mtdcr(uic3sr, 0xffffffff); /* clear all */
mtdcr(uic3er, 0x00000000); /* disable all */
mtdcr(uic3cr, 0x00000000); /* all non-critical */
mtdcr(uic3pr, 0xffffffff); /* per ref-board manual */
mtdcr(uic3tr, 0x00000000); /* per ref-board manual */
mtdcr(uic3vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic3sr, 0xffffffff); /* clear all */
mtdcr(UIC3SR, 0xffffffff); /* clear all */
mtdcr(UIC3ER, 0x00000000); /* disable all */
mtdcr(UIC3CR, 0x00000000); /* all non-critical */
mtdcr(UIC3PR, 0xffffffff); /* per ref-board manual */
mtdcr(UIC3TR, 0x00000000); /* per ref-board manual */
mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC3SR, 0xffffffff); /* clear all */
#if !defined(CONFIG_ARCHES)
/* SDR Setting - enable NDFC */
@@ -325,139 +326,17 @@ phys_size_t initdram(int board_type)
}
#endif
/*
* pci_target_init
*
* The bootstrap configuration provides default settings for the pci
* inbound map (PIM). But the bootstrap config choices are limited and
* may not be sufficient for a given board.
*/
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller * hose )
{
/*
* Disable everything
*/
out_le32((void *)PCIX0_PIM0SA, 0); /* disable */
out_le32((void *)PCIX0_PIM1SA, 0); /* disable */
out_le32((void *)PCIX0_PIM2SA, 0); /* disable */
out_le32((void *)PCIX0_EROMBA, 0); /* disable expansion rom */
/*
* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
* strapping options to not support sizes such as 128/256 MB.
*/
out_le32((void *)PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
out_le32((void *)PCIX0_PIM0LAH, 0);
out_le32((void *)PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
out_le32((void *)PCIX0_BAR0, 0);
/*
* Program the board's subsystem id/vendor id
*/
out_le16((void *)PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
out_le16((void *)PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
out_le16((void *)PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
}
#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
#if defined(CONFIG_PCI)
/*
* is_pci_host
*
* This routine is called to determine if a pci scan should be
* performed. With various hardware environments (especially cPCI and
* PPMC) it's insufficient to depend on the state of the arbiter enable
* bit in the strap register, or generic host/adapter assumptions.
*
* Rather than hard-code a bad assumption in the general 440 code, the
* 440 pci code requires the board to decide at runtime.
*
* Return 0 for adapter mode, non-zero for host (monarch) mode.
*/
int is_pci_host(struct pci_controller *hose)
int board_pcie_first(void)
{
/* Board is always configured as host. */
return (1);
}
static struct pci_controller pcie_hose[2] = {{0},{0}};
void pcie_setup_hoses(int busno)
{
struct pci_controller *hose;
int i, bus;
int ret = 0;
char *env;
unsigned int delay;
int start;
/*
* assume we're called after the PCIX hose is initialized, which takes
* bus ID 0 and therefore start numbering PCIe's from 1.
*/
bus = busno;
/*
* Canyonlands with SATA enabled has only one PCIe slot
* (2nd one).
*/
if (gd->board_type == BOARD_CANYONLANDS_SATA)
start = 1;
else
start = 0;
return 1;
for (i = start; i <= 1; i++) {
if (is_end_point(i))
ret = ppc4xx_init_pcie_endport(i);
else
ret = ppc4xx_init_pcie_rootport(i);
if (ret) {
printf("PCIE%d: initialization as %s failed\n", i,
is_end_point(i) ? "endpoint" : "root-complex");
continue;
}
hose = &pcie_hose[i];
hose->first_busno = bus;
hose->last_busno = bus;
hose->current_busno = bus;
/* setup mem resource */
pci_set_region(hose->regions + 0,
CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
CONFIG_SYS_PCIE_MEMSIZE,
PCI_REGION_MEM);
hose->region_count = 1;
pci_register_hose(hose);
if (is_end_point(i)) {
ppc4xx_setup_pcie_endpoint(hose, i);
/*
* Reson for no scanning is endpoint can not generate
* upstream configuration accesses.
*/
} else {
ppc4xx_setup_pcie_rootpoint(hose, i);
env = getenv ("pciscandelay");
if (env != NULL) {
delay = simple_strtoul(env, NULL, 10);
if (delay > 5)
printf("Warning, expect noticable delay before "
"PCIe scan due to 'pciscandelay' value!\n");
mdelay(delay * 1000);
}
/*
* Config access can only go down stream
*/
hose->last_busno = pci_hose_scan(hose);
bus = hose->last_busno + 1;
}
}
return 0;
}
#endif /* CONFIG_PCI */
@@ -475,9 +354,9 @@ int board_early_init_r (void)
/* Remap the NOR FLASH to 0xcc00.0000 ... 0xcfff.ffff */
#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
mtebc(pb3cr, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);
mtebc(PB3CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);
#else
mtebc(pb0cr, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);
mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);
#endif
/* Remove TLB entry of boot EBC mapping */

View File

@@ -39,3 +39,7 @@ endif
ifeq ($(dbcr),1)
PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
endif
ifdef CONFIG_NAND_U_BOOT
LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot-nand.lds
endif

View File

@@ -62,7 +62,6 @@ SECTIONS
. = ALIGN(0x80000);
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

View File

@@ -1,142 +0,0 @@
/*
* (C) Copyright 2008
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
.resetvec 0xFFFFFFFC :
{
*(.resetvec)
} = 0xffff
.bootpg 0xFFFFF000 :
{
cpu/ppc4xx/start.o (.bootpg)
} = 0xffff
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text)
board/amcc/canyonlands/init.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
. = ALIGN(4);
}
_end = . ;
PROVIDE (end = .);
}

View File

@@ -912,9 +912,10 @@ static int flash_erase_2(flash_info_t * info, int s_first, int s_last)
static int write_word_2(flash_info_t * info, ulong dest, ulong data)
{
volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *) dest;
volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *) & data;
ulong *data_ptr = &data;
volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]);
volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *)dest;
volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *)data_ptr;
ulong start;
int i;

View File

@@ -41,51 +41,51 @@ int board_early_init_f(void)
/*--------------------------------------------------------------------
* Setup the external bus controller/chip selects
*-------------------------------------------------------------------*/
mtdcr(ebccfga, xbcfg);
reg = mfdcr(ebccfgd);
mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */
mtdcr(EBC0_CFGADDR, EBC0_CFG);
reg = mfdcr(EBC0_CFGDATA);
mtdcr(EBC0_CFGDATA, reg | 0x04000000); /* Set ATC */
mtebc(pb1ap, 0x02815480); /* NVRAM/RTC */
mtebc(pb1cr, 0x48018000); /* BA=0x480 1MB R/W 8-bit */
mtebc(pb7ap, 0x01015280); /* FPGA registers */
mtebc(pb7cr, 0x48318000); /* BA=0x483 1MB R/W 8-bit */
mtebc(PB1AP, 0x02815480); /* NVRAM/RTC */
mtebc(PB1CR, 0x48018000); /* BA=0x480 1MB R/W 8-bit */
mtebc(PB7AP, 0x01015280); /* FPGA registers */
mtebc(PB7CR, 0x48318000); /* BA=0x483 1MB R/W 8-bit */
/* read FPGA_REG0 and set the bus controller */
status = *fpga_base;
if ((status & BOOT_SMALL_FLASH) && !(status & FLASH_ONBD_N)) {
mtebc(pb0ap, 0x9b015480); /* FLASH/SRAM */
mtebc(pb0cr, 0xfff18000); /* BAS=0xfff 1MB R/W 8-bit */
mtebc(pb2ap, 0x9b015480); /* 4MB FLASH */
mtebc(pb2cr, 0xff858000); /* BAS=0xff8 4MB R/W 8-bit */
mtebc(PB0AP, 0x9b015480); /* FLASH/SRAM */
mtebc(PB0CR, 0xfff18000); /* BAS=0xfff 1MB R/W 8-bit */
mtebc(PB2AP, 0x9b015480); /* 4MB FLASH */
mtebc(PB2CR, 0xff858000); /* BAS=0xff8 4MB R/W 8-bit */
} else {
mtebc(pb0ap, 0x9b015480); /* 4MB FLASH */
mtebc(pb0cr, 0xffc58000); /* BAS=0xffc 4MB R/W 8-bit */
mtebc(PB0AP, 0x9b015480); /* 4MB FLASH */
mtebc(PB0CR, 0xffc58000); /* BAS=0xffc 4MB R/W 8-bit */
/* set CS2 if FLASH_ONBD_N == 0 */
if (!(status & FLASH_ONBD_N)) {
mtebc(pb2ap, 0x9b015480); /* FLASH/SRAM */
mtebc(pb2cr, 0xff818000); /* BAS=0xff8 4MB R/W 8-bit */
mtebc(PB2AP, 0x9b015480); /* FLASH/SRAM */
mtebc(PB2CR, 0xff818000); /* BAS=0xff8 4MB R/W 8-bit */
}
}
/*--------------------------------------------------------------------
* Setup the interrupt controller polarities, triggers, etc.
*-------------------------------------------------------------------*/
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic0er, 0x00000000); /* disable all */
mtdcr(uic0cr, 0x00000009); /* SMI & UIC1 crit are critical */
mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(UIC0SR, 0xffffffff); /* clear all */
mtdcr(UIC0ER, 0x00000000); /* disable all */
mtdcr(UIC0CR, 0x00000009); /* SMI & UIC1 crit are critical */
mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */
mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */
mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(UIC0SR, 0xffffffff); /* clear all */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(uic1er, 0x00000000); /* disable all */
mtdcr(uic1cr, 0x00000000); /* all non-critical */
mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
mtdcr(UIC1ER, 0x00000000); /* disable all */
mtdcr(UIC1CR, 0x00000000); /* all non-critical */
mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */
mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */
mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
return 0;
}
@@ -131,11 +131,11 @@ long int fixed_sdram(void)
/*--------------------------------------------------------------------
* Setup some default
*------------------------------------------------------------------*/
mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */
mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
mtsdram(mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */
mtsdram(mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
mtsdram(SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */
mtsdram(SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
mtsdram(SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */
mtsdram(SDRAM0_WDDCTR, 0x00000000); /* wrcp=0 dcd=0 */
mtsdram(SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
/*--------------------------------------------------------------------
* Setup for board-specific specific mem
@@ -143,20 +143,20 @@ long int fixed_sdram(void)
/*
* Following for CAS Latency = 2.5 @ 133 MHz PLB
*/
mtsdram(mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
mtsdram(mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
mtsdram(SDRAM0_B0CR, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
mtsdram(SDRAM0_TR0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
/* RA=10 RD=3 */
mtsdram(mem_tr1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
mtsdram(mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */
mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
mtsdram(SDRAM0_TR1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
mtsdram(SDRAM0_RTR, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */
mtsdram(SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM */
udelay(400); /* Delay 200 usecs (min) */
/*--------------------------------------------------------------------
* Enable the controller, then wait for DCEN to complete
*------------------------------------------------------------------*/
mtsdram(mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
mtsdram(SDRAM0_CFG0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
for (;;) {
mfsdram(mem_mcsts, reg);
mfsdram(SDRAM0_MCSTS, reg);
if (reg & 0x80000000)
break;
}
@@ -164,96 +164,3 @@ long int fixed_sdram(void)
return (128 * 1024 * 1024); /* 128 MB */
}
#endif /* !defined(CONFIG_SPD_EEPROM) */
/*************************************************************************
* pci_pre_init
*
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things. Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted.
*
* Different boards may wish to customize the pci controller structure
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller *hose)
{
unsigned long strap;
/*--------------------------------------------------------------------------+
* The ebony board is always configured as the host & requires the
* PCI arbiter to be enabled.
*--------------------------------------------------------------------------*/
strap = mfdcr(cpc0_strp1);
if ((strap & 0x00100000) == 0) {
printf("PCI: CPC0_STRP1[PAE] not set.\n");
return 0;
}
return 1;
}
#endif /* defined(CONFIG_PCI) */
/*************************************************************************
* pci_target_init
*
* The bootstrap configuration provides default settings for the pci
* inbound map (PIM). But the bootstrap config choices are limited and
* may not be sufficient for a given board.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller *hose)
{
/*--------------------------------------------------------------------------+
* Disable everything
*--------------------------------------------------------------------------*/
out32r(PCIX0_PIM0SA, 0); /* disable */
out32r(PCIX0_PIM1SA, 0); /* disable */
out32r(PCIX0_PIM2SA, 0); /* disable */
out32r(PCIX0_EROMBA, 0); /* disable expansion rom */
/*--------------------------------------------------------------------------+
* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
* options to not support sizes such as 128/256 MB.
*--------------------------------------------------------------------------*/
out32r(PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
out32r(PCIX0_PIM0LAH, 0);
out32r(PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
out32r(PCIX0_BAR0, 0);
/*--------------------------------------------------------------------------+
* Program the board's subsystem id/vendor id
*--------------------------------------------------------------------------*/
out16r(PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
out16r(PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
out16r(PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
}
#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
/*************************************************************************
* is_pci_host
*
* This routine is called to determine if a pci scan should be
* performed. With various hardware environments (especially cPCI and
* PPMC) it's insufficient to depend on the state of the arbiter enable
* bit in the strap register, or generic host/adapter assumptions.
*
* Rather than hard-code a bad assumption in the general 440 code, the
* 440 pci code requires the board to decide at runtime.
*
* Return 0 for adapter mode, non-zero for host (monarch) mode.
*
*
************************************************************************/
#if defined(CONFIG_PCI)
int is_pci_host(struct pci_controller *hose)
{
/* The ebony board is always configured as host. */
return (1);
}
#endif /* defined(CONFIG_PCI) */

View File

@@ -1,142 +0,0 @@
/*
* (C) Copyright 2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
.resetvec 0xFFFFFFFC :
{
*(.resetvec)
} = 0xffff
.bootpg 0xFFFFF000 :
{
cpu/ppc4xx/start.o (.bootpg)
} = 0xffff
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text)
board/amcc/ebony/init.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
. = ALIGN(4);
}
_end = . ;
PROVIDE (end = .);
}

View File

@@ -25,9 +25,11 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o cmd_katmai.o
COBJS-y := $(BOARD).o
COBJS-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
SOBJS = init.o
COBJS := $(COBJS-y)
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))

View File

@@ -0,0 +1,55 @@
/*
* (C) Copyright 2009
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#include <common.h>
#include <asm/ppc4xx_config.h>
struct ppc4xx_config ppc4xx_config_val[] = {
{
"400-133","CPU: 400 PLB: 133 OPB: 66 EBC: 66",
{ 0x86, 0x78, 0xc2, 0xc6, 0x05, 0xa5, 0x04, 0xe1 }
},
{
"500-166","CPU: 500 PLB: 166 OPB: 83 EBC: 83",
{ 0x87, 0x78, 0xf2, 0xc6, 0x05, 0xa5, 0x04, 0xe1 }
},
{
"533-133","CPU: 533 PLB: 133 OPB: 66 EBC: 66",
{ 0x87, 0x79, 0x02, 0x52, 0x05, 0xa5, 0x04, 0xe1 }
},
{
"667-133","CPU: 667 PLB: 133 OPB: 66 EBC: 66",
{ 0x87, 0x79, 0x42, 0x56, 0x05, 0xa5, 0x04, 0xe1 }
},
{
"667-166","CPU: 667 PLB: 166 OPB: 83 EBC: 83",
{ 0x87, 0x79, 0x42, 0x06, 0x05, 0xa5, 0x04, 0xe1 }
},
{
"800-160","CPU: 800 PLB: 160 OPB: 53 EBC: 17",
{ 0x86, 0x79, 0x81, 0xa7, 0x07, 0xa5, 0x04, 0xe1 }
},
};
int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val);

View File

@@ -1,218 +0,0 @@
/*
* (C) Copyright 2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#include <common.h>
#include <command.h>
#include <i2c.h>
#include <asm/byteorder.h>
#define CONFIG_STRESS /* enable 667 MHz CPU freq selection */
#define DEBUG
static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
uchar chip;
ulong data;
int nbytes;
extern char console_buffer[];
char sysClock[4];
char cpuClock[4];
char plbClock[4];
char pcixClock[4];
if (argc < 3) {
cmd_usage(cmdtp);
return 1;
}
if (strcmp(argv[2], "prom0") == 0)
chip = IIC0_BOOTPROM_ADDR;
else
chip = IIC0_ALT_BOOTPROM_ADDR;
/* on Katmai SysClk is always 33MHz */
strcpy(sysClock, "33");
do {
#ifdef CONFIG_STRESS
printf("enter cpu clock frequency 400, 500, 533, 667 MHz or quit to abort\n");
#else
printf("enter cpu clock frequency 400, 500, 533 MHz or quit to abort\n");
#endif
nbytes = readline (" ? ");
if (strcmp(console_buffer, "quit") == 0)
return 0;
if ((strcmp(console_buffer, "400") != 0) &&
(strcmp(console_buffer, "500") != 0) &&
(strcmp(console_buffer, "533") != 0)
#ifdef CONFIG_STRESS
&& (strcmp(console_buffer, "667") != 0)
#endif
) {
nbytes = 0;
}
strcpy(cpuClock, console_buffer);
} while (nbytes == 0);
if (strcmp(cpuClock, "500") == 0)
strcpy(plbClock, "166");
else if (strcmp(cpuClock, "533") == 0)
strcpy(plbClock, "133");
else {
do {
if (strcmp(cpuClock, "400") == 0)
printf("enter plb clock frequency 100, 133 MHz or quit to abort\n");
#ifdef CONFIG_STRESS
if (strcmp(cpuClock, "667") == 0)
printf("enter plb clock frequency 133, 166 MHz or quit to abort\n");
#endif
nbytes = readline (" ? ");
if (strcmp(console_buffer, "quit") == 0)
return 0;
if (strcmp(cpuClock, "400") == 0) {
if ((strcmp(console_buffer, "100") != 0) &&
(strcmp(console_buffer, "133") != 0))
nbytes = 0;
}
#ifdef CONFIG_STRESS
if (strcmp(cpuClock, "667") == 0) {
if ((strcmp(console_buffer, "133") != 0) &&
(strcmp(console_buffer, "166") != 0))
nbytes = 0;
}
#endif
strcpy(plbClock, console_buffer);
} while (nbytes == 0);
}
do {
printf("enter Pci-X clock frequency 33, 66, 100 or 133 MHz or quit to abort\n");
nbytes = readline (" ? ");
if (strcmp(console_buffer, "quit") == 0)
return 0;
if ((strcmp(console_buffer, "33") != 0) &&
(strcmp(console_buffer, "66") != 0) &&
(strcmp(console_buffer, "100") != 0) &&
(strcmp(console_buffer, "133") != 0)) {
nbytes = 0;
}
strcpy(pcixClock, console_buffer);
} while (nbytes == 0);
printf("\nsys clk = %s MHz\n", sysClock);
printf("cpu clk = %s MHz\n", cpuClock);
printf("plb clk = %s MHz\n", plbClock);
printf("Pci-X clk = %s MHz\n", pcixClock);
do {
printf("\npress [y] to write I2C bootstrap \n");
printf("or [n] to abort. \n");
printf("Don't forget to set board switches \n");
printf("according to your choice before re-starting \n");
printf("(refer to 440spe_uboot_kit_um_1_01.pdf) \n");
nbytes = readline (" ? ");
if (strcmp(console_buffer, "n") == 0)
return 0;
} while (nbytes == 0);
if (strcmp(sysClock, "33") == 0) {
if ((strcmp(cpuClock, "400") == 0) &&
(strcmp(plbClock, "100") == 0))
data = 0x8678c206;
if ((strcmp(cpuClock, "400") == 0) &&
(strcmp(plbClock, "133") == 0))
data = 0x8678c2c6;
if ((strcmp(cpuClock, "500") == 0))
data = 0x8778f2c6;
if ((strcmp(cpuClock, "533") == 0))
data = 0x87790252;
#ifdef CONFIG_STRESS
if ((strcmp(cpuClock, "667") == 0) &&
(strcmp(plbClock, "133") == 0))
data = 0x87794256;
if ((strcmp(cpuClock, "667") == 0) &&
(strcmp(plbClock, "166") == 0))
data = 0x87794206;
#endif
}
#ifdef DEBUG
printf(" pin strap0 to write in i2c = %lx\n", data);
#endif /* DEBUG */
if (i2c_write(chip, 0, 1, (uchar *)&data, 4) != 0)
printf("Error writing strap0 in %s\n", argv[2]);
if (strcmp(pcixClock, "33") == 0)
data = 0x000007E1;
if (strcmp(pcixClock, "66") == 0)
data = 0x000006E1;
if (strcmp(pcixClock, "100") == 0)
data = 0x000005E1;
if (strcmp(pcixClock, "133") == 0)
data = 0x000004E1;
if (strcmp(plbClock, "166") == 0)
/* data |= 0x05950000; */ /* this set's DDR2 clock == PLB clock */
data |= 0x05A50000; /* this set's DDR2 clock == 2 * PLB clock */
else
data |= 0x05A50000;
#ifdef DEBUG
printf(" pin strap1 to write in i2c = %lx\n", data);
#endif /* DEBUG */
udelay(1000);
if (i2c_write(chip, 4, 1, (uchar *)&data, 4) != 0)
printf("Error writing strap1 in %s\n", argv[2]);
return 0;
}
U_BOOT_CMD(
bootstrap, 3, 1, do_bootstrap,
"program the serial device strap",
"wrclk [prom0|prom1] - program the serial device strap"
);

View File

@@ -1,5 +1,5 @@
/*
* (C) Copyright 2007-2008
* (C) Copyright 2007-2009
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
@@ -32,6 +32,7 @@
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/4xx_pcie.h>
#include <asm/errno.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -183,46 +184,46 @@ int board_early_init_f (void)
* Set critical interrupt values. Set interrupt polarities. Set interrupt
* trigger levels. Make bit 0 High priority. Clear all interrupts again.
*------------------------------------------------------------------------*/
mtdcr (uic3sr, 0xffffffff); /* Clear all interrupts */
mtdcr (uic3er, 0x00000000); /* disable all interrupts */
mtdcr (uic3cr, 0x00000000); /* Set Critical / Non Critical interrupts: */
mtdcr (uic3pr, 0xffffffff); /* Set Interrupt Polarities*/
mtdcr (uic3tr, 0x001fffff); /* Set Interrupt Trigger Levels */
mtdcr (uic3vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
mtdcr (uic3sr, 0x00000000); /* clear all interrupts*/
mtdcr (uic3sr, 0xffffffff); /* clear all interrupts*/
mtdcr (UIC3SR, 0xffffffff); /* Clear all interrupts */
mtdcr (UIC3ER, 0x00000000); /* disable all interrupts */
mtdcr (UIC3CR, 0x00000000); /* Set Critical / Non Critical interrupts: */
mtdcr (UIC3PR, 0xffffffff); /* Set Interrupt Polarities*/
mtdcr (UIC3TR, 0x001fffff); /* Set Interrupt Trigger Levels */
mtdcr (UIC3VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
mtdcr (UIC3SR, 0x00000000); /* clear all interrupts*/
mtdcr (UIC3SR, 0xffffffff); /* clear all interrupts*/
mtdcr (uic2sr, 0xffffffff); /* Clear all interrupts */
mtdcr (uic2er, 0x00000000); /* disable all interrupts*/
mtdcr (uic2cr, 0x00000000); /* Set Critical / Non Critical interrupts*/
mtdcr (uic2pr, 0xebebebff); /* Set Interrupt Polarities*/
mtdcr (uic2tr, 0x74747400); /* Set Interrupt Trigger Levels */
mtdcr (uic2vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
mtdcr (uic2sr, 0x00000000); /* clear all interrupts */
mtdcr (uic2sr, 0xffffffff); /* clear all interrupts */
mtdcr (UIC2SR, 0xffffffff); /* Clear all interrupts */
mtdcr (UIC2ER, 0x00000000); /* disable all interrupts*/
mtdcr (UIC2CR, 0x00000000); /* Set Critical / Non Critical interrupts*/
mtdcr (UIC2PR, 0xebebebff); /* Set Interrupt Polarities*/
mtdcr (UIC2TR, 0x74747400); /* Set Interrupt Trigger Levels */
mtdcr (UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
mtdcr (UIC2SR, 0x00000000); /* clear all interrupts */
mtdcr (UIC2SR, 0xffffffff); /* clear all interrupts */
mtdcr (uic1sr, 0xffffffff); /* Clear all interrupts*/
mtdcr (uic1er, 0x00000000); /* disable all interrupts*/
mtdcr (uic1cr, 0x00000000); /* Set Critical / Non Critical interrupts*/
mtdcr (uic1pr, 0xffffffff); /* Set Interrupt Polarities */
mtdcr (uic1tr, 0x001f8040); /* Set Interrupt Trigger Levels*/
mtdcr (uic1vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
mtdcr (uic1sr, 0x00000000); /* clear all interrupts*/
mtdcr (uic1sr, 0xffffffff); /* clear all interrupts*/
mtdcr (UIC1SR, 0xffffffff); /* Clear all interrupts*/
mtdcr (UIC1ER, 0x00000000); /* disable all interrupts*/
mtdcr (UIC1CR, 0x00000000); /* Set Critical / Non Critical interrupts*/
mtdcr (UIC1PR, 0xffffffff); /* Set Interrupt Polarities */
mtdcr (UIC1TR, 0x001f8040); /* Set Interrupt Trigger Levels*/
mtdcr (UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
mtdcr (UIC1SR, 0x00000000); /* clear all interrupts*/
mtdcr (UIC1SR, 0xffffffff); /* clear all interrupts*/
mtdcr (uic0sr, 0xffffffff); /* Clear all interrupts */
mtdcr (uic0er, 0x00000000); /* disable all interrupts excepted cascade to be checked */
mtdcr (uic0cr, 0x00104001); /* Set Critical / Non Critical interrupts*/
mtdcr (uic0pr, 0xffffffff); /* Set Interrupt Polarities*/
mtdcr (uic0tr, 0x010f0004); /* Set Interrupt Trigger Levels */
mtdcr (uic0vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
mtdcr (uic0sr, 0x00000000); /* clear all interrupts*/
mtdcr (uic0sr, 0xffffffff); /* clear all interrupts*/
mtdcr (UIC0SR, 0xffffffff); /* Clear all interrupts */
mtdcr (UIC0ER, 0x00000000); /* disable all interrupts excepted cascade to be checked */
mtdcr (UIC0CR, 0x00104001); /* Set Critical / Non Critical interrupts*/
mtdcr (UIC0PR, 0xffffffff); /* Set Interrupt Polarities*/
mtdcr (UIC0TR, 0x010f0004); /* Set Interrupt Trigger Levels */
mtdcr (UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
mtdcr (UIC0SR, 0x00000000); /* clear all interrupts*/
mtdcr (UIC0SR, 0xffffffff); /* clear all interrupts*/
mfsdr(sdr_mfr, mfr);
mfsdr(SDR0_MFR, mfr);
mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */
mtsdr(sdr_mfr, mfr);
mtsdr(SDR0_MFR, mfr);
mtsdr(SDR0_PFC0, CONFIG_SYS_PFC0);
@@ -259,98 +260,8 @@ u32 ddr_clktr(u32 default_val) {
return (SDRAM_CLKTR_CLKP_90_DEG_ADV);
}
/*************************************************************************
* pci_pre_init
*
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things. Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted.
*
* Different boards may wish to customize the pci controller structure
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller * hose )
{
unsigned long strap;
/*-------------------------------------------------------------------+
* The katmai board is always configured as the host & requires the
* PCI arbiter to be enabled.
*-------------------------------------------------------------------*/
mfsdr(sdr_sdstp1, strap);
if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ) {
printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
return 0;
}
return 1;
}
#endif /* defined(CONFIG_PCI) */
/*************************************************************************
* pci_target_init
*
* The bootstrap configuration provides default settings for the pci
* inbound map (PIM). But the bootstrap config choices are limited and
* may not be sufficient for a given board.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller * hose )
{
/*-------------------------------------------------------------------+
* Disable everything
*-------------------------------------------------------------------*/
out32r( PCIX0_PIM0SA, 0 ); /* disable */
out32r( PCIX0_PIM1SA, 0 ); /* disable */
out32r( PCIX0_PIM2SA, 0 ); /* disable */
out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
/*-------------------------------------------------------------------+
* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
* strapping options to not support sizes such as 128/256 MB.
*-------------------------------------------------------------------*/
out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
out32r( PCIX0_PIM0LAH, 0 );
out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
out32r( PCIX0_BAR0, 0 );
/*-------------------------------------------------------------------+
* Program the board's subsystem id/vendor id
*-------------------------------------------------------------------*/
out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
}
#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
#if defined(CONFIG_PCI)
/*************************************************************************
* is_pci_host
*
* This routine is called to determine if a pci scan should be
* performed. With various hardware environments (especially cPCI and
* PPMC) it's insufficient to depend on the state of the arbiter enable
* bit in the strap register, or generic host/adapter assumptions.
*
* Rather than hard-code a bad assumption in the general 440 code, the
* 440 pci code requires the board to decide at runtime.
*
* Return 0 for adapter mode, non-zero for host (monarch) mode.
*
*
************************************************************************/
int is_pci_host(struct pci_controller *hose)
{
/* The katmai board is always configured as host. */
return 1;
}
static int katmai_pcie_card_present(int port)
int board_pcie_card_present(int port)
{
u32 val;
@@ -366,89 +277,8 @@ static int katmai_pcie_card_present(int port)
return 0;
}
}
static struct pci_controller pcie_hose[3] = {{0},{0},{0}};
void pcie_setup_hoses(int busno)
{
struct pci_controller *hose;
int i, bus;
int ret = 0;
char *env;
unsigned int delay;
/*
* assume we're called after the PCIX hose is initialized, which takes
* bus ID 0 and therefore start numbering PCIe's from 1.
*/
bus = busno;
for (i = 0; i <= 2; i++) {
/* Check for katmai card presence */
if (!katmai_pcie_card_present(i))
continue;
if (is_end_point(i))
ret = ppc4xx_init_pcie_endport(i);
else
ret = ppc4xx_init_pcie_rootport(i);
if (ret) {
printf("PCIE%d: initialization as %s failed\n", i,
is_end_point(i) ? "endpoint" : "root-complex");
continue;
}
hose = &pcie_hose[i];
hose->first_busno = bus;
hose->last_busno = bus;
hose->current_busno = bus;
/* setup mem resource */
pci_set_region(hose->regions + 0,
CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
CONFIG_SYS_PCIE_MEMSIZE,
PCI_REGION_MEM);
hose->region_count = 1;
pci_register_hose(hose);
if (is_end_point(i)) {
ppc4xx_setup_pcie_endpoint(hose, i);
/*
* Reson for no scanning is endpoint can not generate
* upstream configuration accesses.
*/
} else {
ppc4xx_setup_pcie_rootpoint(hose, i);
env = getenv ("pciscandelay");
if (env != NULL) {
delay = simple_strtoul(env, NULL, 10);
if (delay > 5)
printf("Warning, expect noticable delay before "
"PCIe scan due to 'pciscandelay' value!\n");
mdelay(delay * 1000);
}
/*
* Config access can only go down stream
*/
hose->last_busno = pci_hose_scan(hose);
bus = hose->last_busno + 1;
}
}
}
#endif /* defined(CONFIG_PCI) */
#ifdef CONFIG_POST
/*
* Returns 1 if keys pressed to start the power-on long-running tests
* Called from board_init_f().
*/
int post_hotkeys_pressed(void)
{
return (ctrlc());
}
#endif
int board_eth_init(bd_t *bis)
{
cpu_eth_init(bis);

View File

@@ -1,139 +0,0 @@
/*
* (C) Copyright 2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
.resetvec 0xFFFFFFFC :
{
*(.resetvec)
} = 0xffff
.bootpg 0xFFFFF000 :
{
cpu/ppc4xx/start.o (.bootpg)
} = 0xffff
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
cpu/ppc4xx/start.o (.text)
board/amcc/katmai/init.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
. = ALIGN(4);
}
_end = . ;
PROVIDE (end = .);
}

View File

@@ -30,3 +30,7 @@ endif
ifeq ($(debug),1)
PLATFORM_CPPFLAGS += -DDEBUG
endif
ifdef CONFIG_NAND_U_BOOT
LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot-nand.lds
endif

View File

@@ -28,6 +28,7 @@
#include <fdt_support.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/errno.h>
#if defined(CONFIG_PCI)
#include <pci.h>
@@ -38,6 +39,37 @@ DECLARE_GLOBAL_DATA_PTR;
extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
static int board_cpld_version(void)
{
u32 cpld;
cpld = in_be32((void *)CONFIG_SYS_FPGA_FIFO_BASE);
if ((cpld & CONFIG_SYS_FPGA_MAGIC_MASK) != CONFIG_SYS_FPGA_MAGIC) {
/*
* Magic not found -> "old" CPLD revision which needs
* the "old" EBC configuration
*/
mtebc(PB2AP, EBC_BXAP_BME_ENABLED | EBC_BXAP_FWT_ENCODE(5) |
EBC_BXAP_BWT_ENCODE(0) | EBC_BXAP_BCE_DISABLE |
EBC_BXAP_BCT_2TRANS | EBC_BXAP_CSN_ENCODE(0) |
EBC_BXAP_OEN_ENCODE(0) | EBC_BXAP_WBN_ENCODE(3) |
EBC_BXAP_WBF_ENCODE(0) | EBC_BXAP_TH_ENCODE(4) |
EBC_BXAP_RE_DISABLED | EBC_BXAP_SOR_DELAYED |
EBC_BXAP_BEM_WRITEONLY | EBC_BXAP_PEN_DISABLED);
/*
* Return 0 for "old" CPLD version
*/
return 0;
}
/*
* Magic found -> "new" CPLD revision which needs no new
* EBC configuration
*/
return (cpld & CONFIG_SYS_FPGA_VER_MASK) >> 8;
}
/*
* Board early initialization function
*/
@@ -158,33 +190,33 @@ int board_early_init_f (void)
| interrupts again.
+-------------------------------------------------------------------*/
mtdcr (uic2sr, 0xffffffff); /* Clear all interrupts */
mtdcr (uic2er, 0x00000000); /* disable all interrupts */
mtdcr (uic2cr, 0x00000000); /* Set Critical / Non Critical interrupts */
mtdcr (uic2pr, 0xf7ffffff); /* Set Interrupt Polarities */
mtdcr (uic2tr, 0x01e1fff8); /* Set Interrupt Trigger Levels */
mtdcr (uic2vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
mtdcr (uic2sr, 0x00000000); /* clear all interrupts */
mtdcr (uic2sr, 0xffffffff); /* clear all interrupts */
mtdcr (UIC2SR, 0xffffffff); /* Clear all interrupts */
mtdcr (UIC2ER, 0x00000000); /* disable all interrupts */
mtdcr (UIC2CR, 0x00000000); /* Set Critical / Non Critical interrupts */
mtdcr (UIC2PR, 0xf7ffffff); /* Set Interrupt Polarities */
mtdcr (UIC2TR, 0x01e1fff8); /* Set Interrupt Trigger Levels */
mtdcr (UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
mtdcr (UIC2SR, 0x00000000); /* clear all interrupts */
mtdcr (UIC2SR, 0xffffffff); /* clear all interrupts */
mtdcr (uic1sr, 0xffffffff); /* Clear all interrupts */
mtdcr (uic1er, 0x00000000); /* disable all interrupts */
mtdcr (uic1cr, 0x00000000); /* Set Critical / Non Critical interrupts */
mtdcr (uic1pr, 0xfffac785); /* Set Interrupt Polarities */
mtdcr (uic1tr, 0x001d0040); /* Set Interrupt Trigger Levels */
mtdcr (uic1vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
mtdcr (uic1sr, 0x00000000); /* clear all interrupts */
mtdcr (uic1sr, 0xffffffff); /* clear all interrupts */
mtdcr (UIC1SR, 0xffffffff); /* Clear all interrupts */
mtdcr (UIC1ER, 0x00000000); /* disable all interrupts */
mtdcr (UIC1CR, 0x00000000); /* Set Critical / Non Critical interrupts */
mtdcr (UIC1PR, 0xfffac785); /* Set Interrupt Polarities */
mtdcr (UIC1TR, 0x001d0040); /* Set Interrupt Trigger Levels */
mtdcr (UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
mtdcr (UIC1SR, 0x00000000); /* clear all interrupts */
mtdcr (UIC1SR, 0xffffffff); /* clear all interrupts */
mtdcr (uic0sr, 0xffffffff); /* Clear all interrupts */
mtdcr (uic0er, 0x0000000a); /* Disable all interrupts */
mtdcr (UIC0SR, 0xffffffff); /* Clear all interrupts */
mtdcr (UIC0ER, 0x0000000a); /* Disable all interrupts */
/* Except cascade UIC0 and UIC1 */
mtdcr (uic0cr, 0x00000000); /* Set Critical / Non Critical interrupts */
mtdcr (uic0pr, 0xffbfefef); /* Set Interrupt Polarities */
mtdcr (uic0tr, 0x00007000); /* Set Interrupt Trigger Levels */
mtdcr (uic0vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
mtdcr (uic0sr, 0x00000000); /* clear all interrupts */
mtdcr (uic0sr, 0xffffffff); /* clear all interrupts */
mtdcr (UIC0CR, 0x00000000); /* Set Critical / Non Critical interrupts */
mtdcr (UIC0PR, 0xffbfefef); /* Set Interrupt Polarities */
mtdcr (UIC0TR, 0x00007000); /* Set Interrupt Trigger Levels */
mtdcr (UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
mtdcr (UIC0SR, 0x00000000); /* clear all interrupts */
mtdcr (UIC0SR, 0xffffffff); /* clear all interrupts */
/*
* Note: Some cores are still in reset when the chip starts, so
@@ -207,6 +239,13 @@ int board_early_init_f (void)
val = SDR0_PFC1_USBEN | SDR0_PFC1_USBBIGEN | SDR0_PFC1_GPT_FREQ;
mtsdr(SDR0_PFC1, val);
/*
* The CPLD version detection has to be the first access to
* the CPLD, so we need to make this access this early and
* save the CPLD version for later.
*/
gd->board_type = board_cpld_version();
/*
* Configure FPGA register with PCIe reset
*/
@@ -251,15 +290,19 @@ int board_emac_count(void)
return 2;
}
static int board_pcie_count(void)
/*
* Override the weak default implementation and return the
* last PCIe slot number (max number - 1).
*/
int board_pcie_last(void)
{
/*
* 405EXr only has one EMAC interface, 405EX has two
*/
if (is_405exr())
return 1;
return 1 - 1;
else
return 2;
return 2 - 1;
}
int checkboard (void)
@@ -275,102 +318,7 @@ int checkboard (void)
puts(", serial# ");
puts(s);
}
putc('\n');
printf(" (CPLD rev. %ld)\n", gd->board_type);
return (0);
}
/*************************************************************************
* pci_pre_init
*
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things. Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted.
*
* Different boards may wish to customize the pci controller structure
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller * hose )
{
return 0;
}
#endif /* defined(CONFIG_PCI) */
#ifdef CONFIG_PCI
static struct pci_controller pcie_hose[2] = {{0},{0}};
void pcie_setup_hoses(int busno)
{
struct pci_controller *hose;
int i, bus;
int ret = 0;
bus = busno;
char *env;
unsigned int delay;
for (i = 0; i < board_pcie_count(); i++) {
if (is_end_point(i))
ret = ppc4xx_init_pcie_endport(i);
else
ret = ppc4xx_init_pcie_rootport(i);
if (ret) {
printf("PCIE%d: initialization as %s failed\n", i,
is_end_point(i) ? "endpoint" : "root-complex");
continue;
}
hose = &pcie_hose[i];
hose->first_busno = bus;
hose->last_busno = bus;
hose->current_busno = bus;
/* setup mem resource */
pci_set_region(hose->regions + 0,
CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
CONFIG_SYS_PCIE_MEMSIZE,
PCI_REGION_MEM);
hose->region_count = 1;
pci_register_hose(hose);
if (is_end_point(i)) {
ppc4xx_setup_pcie_endpoint(hose, i);
/*
* Reson for no scanning is endpoint can not generate
* upstream configuration accesses.
*/
} else {
ppc4xx_setup_pcie_rootpoint(hose, i);
env = getenv ("pciscandelay");
if (env != NULL) {
delay = simple_strtoul(env, NULL, 10);
if (delay > 5)
printf("Warning, expect noticable delay before "
"PCIe scan due to 'pciscandelay' value!\n");
mdelay(delay * 1000);
}
/*
* Config access can only go down stream
*/
hose->last_busno = pci_hose_scan(hose);
bus = hose->last_busno + 1;
}
}
}
#endif
#if defined(CONFIG_POST)
/*
* Returns 1 if keys pressed to start the power-on long-running tests
* Called from board_init_f().
*/
int post_hotkeys_pressed(void)
{
return 0; /* No hotkeys supported */
}
#endif /* CONFIG_POST */

View File

@@ -62,7 +62,6 @@ SECTIONS
. = ALIGN(0x10000);
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

View File

@@ -1,135 +0,0 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* To compile successfully, uncomment the following section.
* To go in ram, remove the section.
* Added by SunHe.
*/
.resetvec 0xFFFFFFFC :
{
*(.resetvec)
} = 0xffff
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
cpu/ppc4xx/start.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
. = ALIGN(4);
}
_end = . ;
PROVIDE (end = .);
}

View File

@@ -8,8 +8,8 @@
#define EPLD0_FLASH_SRAM_SEL_N 0x01 /* 0 SRAM at mem top, 1 small flash at mem top */
#define EPLD1_CLK_CNTL0 0x80 /* FSEL-FB1 of MPC9772 */
#define EPLD1_PCIX0_CNTL1 0x40 /* S*0 of 9531 */
#define EPLD1_PCIX0_CNTL2 0x20 /* S*1 of 9531 */
#define EPLD1_PCIL0_CNTL1 0x40 /* S*0 of 9531 */
#define EPLD1_PCIL0_CNTL2 0x20 /* S*1 of 9531 */
#define EPLD1_CLK_CNTL3 0x10 /* FSEL-B1 of MPC9772 */
#define EPLD1_CLK_CNTL4 0x08 /* FSEL-B0 of MPC9772 */
#define EPLD1_MASTER_CLOCK6 0x04 /* clock source select 6 */
@@ -29,25 +29,25 @@
#define EPLD3_STATUS_LED2 0x02 /* status LED 2 (1 = LED on) */
#define EPLD3_STATUS_LED1 0x01 /* status LED 1 (1 = LED on) */
#define EPLD4_PCIX0_VTH1 0x80 /* PCI-X 0 VTH1 status */
#define EPLD4_PCIX0_VTH2 0x40 /* PCI-X 0 VTH2 status */
#define EPLD4_PCIX0_VTH3 0x20 /* PCI-X 0 VTH3 status */
#define EPLD4_PCIX0_VTH4 0x10 /* PCI-X 0 VTH4 status */
#define EPLD4_PCIL0_VTH1 0x80 /* PCI-X 0 VTH1 status */
#define EPLD4_PCIL0_VTH2 0x40 /* PCI-X 0 VTH2 status */
#define EPLD4_PCIL0_VTH3 0x20 /* PCI-X 0 VTH3 status */
#define EPLD4_PCIL0_VTH4 0x10 /* PCI-X 0 VTH4 status */
#define EPLD4_PCIX1_VTH1 0x08 /* PCI-X 1 VTH1 status */
#define EPLD4_PCIX1_VTH2 0x04 /* PCI-X 1 VTH2 status */
#define EPLD4_PCIX1_VTH3 0x02 /* PCI-X 1 VTH3 status */
#define EPLD4_PCIX1_VTH4 0x01 /* PCI-X 1 VTH4 status */
#define EPLD5_PCIX0_INT0 0x80 /* PCIX0 INT0 status, write 0 to reset */
#define EPLD5_PCIX0_INT1 0x40 /* PCIX0 INT1 status, write 0 to reset */
#define EPLD5_PCIX0_INT2 0x20 /* PCIX0 INT2 status, write 0 to reset */
#define EPLD5_PCIX0_INT3 0x10 /* PCIX0 INT3 status, write 0 to reset */
#define EPLD5_PCIL0_INT0 0x80 /* PCIX0 INT0 status, write 0 to reset */
#define EPLD5_PCIL0_INT1 0x40 /* PCIX0 INT1 status, write 0 to reset */
#define EPLD5_PCIL0_INT2 0x20 /* PCIX0 INT2 status, write 0 to reset */
#define EPLD5_PCIL0_INT3 0x10 /* PCIX0 INT3 status, write 0 to reset */
#define EPLD5_PCIX1_INT0 0x08 /* PCIX1 INT0 status, write 0 to reset */
#define EPLD5_PCIX1_INT1 0x04 /* PCIX1 INT1 status, write 0 to reset */
#define EPLD5_PCIX1_INT2 0x02 /* PCIX1 INT2 status, write 0 to reset */
#define EPLD5_PCIX1_INT3 0x01 /* PCIX1 INT3 status, write 0 to reset */
#define EPLD6_PCIX0_RESET_CTL 0x80 /* 0=enable slot reset, 1=disable slot reset */
#define EPLD6_PCIL0_RESET_CTL 0x80 /* 0=enable slot reset, 1=disable slot reset */
#define EPLD6_PCIX1_RESET_CTL 0x40 /* 0=enable slot reset, 1=disable slot reset */
#define EPLD6_ETH_INT_MODE 0x20 /* 0=IRQ5 recv's external eth int */
#define EPLD6_PCIX2_RESET_CTL 0x10 /* 0=enable slot reset, 1=disable slot reset */

View File

@@ -42,34 +42,34 @@ int board_early_init_f(void)
{
u32 mfr;
mtebc( pb0ap, 0x03800000 ); /* set chip selects */
mtebc( pb0cr, 0xffc58000 ); /* ebc0_b0cr, 4MB at 0xffc00000 CS0 */
mtebc( pb1ap, 0x03800000 );
mtebc( pb1cr, 0xff018000 ); /* ebc0_b1cr, 1MB at 0xff000000 CS1 */
mtebc( pb2ap, 0x03800000 );
mtebc( pb2cr, 0xff838000 ); /* ebc0_b2cr, 2MB at 0xff800000 CS2 */
mtebc( PB0AP, 0x03800000 ); /* set chip selects */
mtebc( PB0CR, 0xffc58000 ); /* ebc0_b0cr, 4MB at 0xffc00000 CS0 */
mtebc( PB1AP, 0x03800000 );
mtebc( PB1CR, 0xff018000 ); /* ebc0_b1cr, 1MB at 0xff000000 CS1 */
mtebc( PB2AP, 0x03800000 );
mtebc( PB2CR, 0xff838000 ); /* ebc0_b2cr, 2MB at 0xff800000 CS2 */
mtdcr( uic1sr, 0xffffffff ); /* Clear all interrupts */
mtdcr( uic1er, 0x00000000 ); /* disable all interrupts */
mtdcr( uic1cr, 0x00000000 ); /* Set Critical / Non Critical interrupts */
mtdcr( uic1pr, 0x7fff83ff ); /* Set Interrupt Polarities */
mtdcr( uic1tr, 0x001f8000 ); /* Set Interrupt Trigger Levels */
mtdcr( uic1vr, 0x00000001 ); /* Set Vect base=0,INT31 Highest priority */
mtdcr( uic1sr, 0x00000000 ); /* clear all interrupts */
mtdcr( uic1sr, 0xffffffff );
mtdcr( UIC1SR, 0xffffffff ); /* Clear all interrupts */
mtdcr( UIC1ER, 0x00000000 ); /* disable all interrupts */
mtdcr( UIC1CR, 0x00000000 ); /* Set Critical / Non Critical interrupts */
mtdcr( UIC1PR, 0x7fff83ff ); /* Set Interrupt Polarities */
mtdcr( UIC1TR, 0x001f8000 ); /* Set Interrupt Trigger Levels */
mtdcr( UIC1VR, 0x00000001 ); /* Set Vect base=0,INT31 Highest priority */
mtdcr( UIC1SR, 0x00000000 ); /* clear all interrupts */
mtdcr( UIC1SR, 0xffffffff );
mtdcr( uic0sr, 0xffffffff ); /* Clear all interrupts */
mtdcr( uic0er, 0x00000000 ); /* disable all interrupts excepted cascade */
mtdcr( uic0cr, 0x00000001 ); /* Set Critical / Non Critical interrupts */
mtdcr( uic0pr, 0xffffffff ); /* Set Interrupt Polarities */
mtdcr( uic0tr, 0x01000004 ); /* Set Interrupt Trigger Levels */
mtdcr( uic0vr, 0x00000001 ); /* Set Vect base=0,INT31 Highest priority */
mtdcr( uic0sr, 0x00000000 ); /* clear all interrupts */
mtdcr( uic0sr, 0xffffffff );
mtdcr( UIC0SR, 0xffffffff ); /* Clear all interrupts */
mtdcr( UIC0ER, 0x00000000 ); /* disable all interrupts excepted cascade */
mtdcr( UIC0CR, 0x00000001 ); /* Set Critical / Non Critical interrupts */
mtdcr( UIC0PR, 0xffffffff ); /* Set Interrupt Polarities */
mtdcr( UIC0TR, 0x01000004 ); /* Set Interrupt Trigger Levels */
mtdcr( UIC0VR, 0x00000001 ); /* Set Vect base=0,INT31 Highest priority */
mtdcr( UIC0SR, 0x00000000 ); /* clear all interrupts */
mtdcr( UIC0SR, 0xffffffff );
mfsdr(sdr_mfr, mfr);
mfsdr(SDR0_MFR, mfr);
mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */
mtsdr(sdr_mfr, mfr);
mtsdr(SDR0_MFR, mfr);
return 0;
}
@@ -126,102 +126,6 @@ u32 ddr_clktr(u32 default_val) {
return (SDRAM_CLKTR_CLKP_180_DEG_ADV);
}
/*************************************************************************
* pci_pre_init
*
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things. Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted.
*
* Different boards may wish to customize the pci controller structure
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI)
int pci_pre_init( struct pci_controller *hose )
{
unsigned long strap;
/*--------------------------------------------------------------------------+
* The luan board is always configured as the host & requires the
* PCI arbiter to be enabled.
*--------------------------------------------------------------------------*/
mfsdr(sdr_sdstp1, strap);
if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ) {
printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
return 0;
}
return 1;
}
#endif /* defined(CONFIG_PCI) */
/*************************************************************************
* pci_target_init
*
* The bootstrap configuration provides default settings for the pci
* inbound map (PIM). But the bootstrap config choices are limited and
* may not be sufficient for a given board.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller *hose)
{
/*--------------------------------------------------------------------------+
* Disable everything
*--------------------------------------------------------------------------*/
out32r( PCIX0_PIM0SA, 0 ); /* disable */
out32r( PCIX0_PIM1SA, 0 ); /* disable */
out32r( PCIX0_PIM2SA, 0 ); /* disable */
out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
/*--------------------------------------------------------------------------+
* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
* options to not support sizes such as 128/256 MB.
*--------------------------------------------------------------------------*/
out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
out32r( PCIX0_PIM0LAH, 0 );
out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
out32r( PCIX0_BAR0, 0 );
/*--------------------------------------------------------------------------+
* Program the board's subsystem id/vendor id
*--------------------------------------------------------------------------*/
out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
}
#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
/*************************************************************************
* is_pci_host
*
* This routine is called to determine if a pci scan should be
* performed. With various hardware environments (especially cPCI and
* PPMC) it's insufficient to depend on the state of the arbiter enable
* bit in the strap register, or generic host/adapter assumptions.
*
* Rather than hard-code a bad assumption in the general 440 code, the
* 440 pci code requires the board to decide at runtime.
*
* Return 0 for adapter mode, non-zero for host (monarch) mode.
*
*
************************************************************************/
#if defined(CONFIG_PCI)
int is_pci_host(struct pci_controller *hose)
{
return 1;
}
#endif /* defined(CONFIG_PCI) */
/*************************************************************************
* hw_watchdog_reset
*

View File

@@ -1,142 +0,0 @@
/*
* (C) Copyright 2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
.resetvec 0xFFFFFFFC :
{
*(.resetvec)
} = 0xffff
.bootpg 0xFFFFF000 :
{
cpu/ppc4xx/start.o (.bootpg)
} = 0xffff
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text)
board/amcc/luan/init.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
. = ALIGN(4);
}
_end = . ;
PROVIDE (end = .);
}

View File

@@ -29,6 +29,7 @@
#include <asm/gpio.h>
#include <asm/io.h>
#include <fdt_support.h>
#include <asm/errno.h>
#if defined(CONFIG_PCI)
#include <pci.h>
@@ -159,33 +160,33 @@ int board_early_init_f (void)
| interrupts again.
+-------------------------------------------------------------------*/
mtdcr (uic2sr, 0xffffffff); /* Clear all interrupts */
mtdcr (uic2er, 0x00000000); /* disable all interrupts */
mtdcr (uic2cr, 0x00000000); /* Set Critical / Non Critical interrupts */
mtdcr (uic2pr, 0xf7ffffff); /* Set Interrupt Polarities */
mtdcr (uic2tr, 0x01e1fff8); /* Set Interrupt Trigger Levels */
mtdcr (uic2vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
mtdcr (uic2sr, 0x00000000); /* clear all interrupts */
mtdcr (uic2sr, 0xffffffff); /* clear all interrupts */
mtdcr (UIC2SR, 0xffffffff); /* Clear all interrupts */
mtdcr (UIC2ER, 0x00000000); /* disable all interrupts */
mtdcr (UIC2CR, 0x00000000); /* Set Critical / Non Critical interrupts */
mtdcr (UIC2PR, 0xf7ffffff); /* Set Interrupt Polarities */
mtdcr (UIC2TR, 0x01e1fff8); /* Set Interrupt Trigger Levels */
mtdcr (UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
mtdcr (UIC2SR, 0x00000000); /* clear all interrupts */
mtdcr (UIC2SR, 0xffffffff); /* clear all interrupts */
mtdcr (uic1sr, 0xffffffff); /* Clear all interrupts */
mtdcr (uic1er, 0x00000000); /* disable all interrupts */
mtdcr (uic1cr, 0x00000000); /* Set Critical / Non Critical interrupts */
mtdcr (uic1pr, 0xfffac785); /* Set Interrupt Polarities */
mtdcr (uic1tr, 0x001d0040); /* Set Interrupt Trigger Levels */
mtdcr (uic1vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
mtdcr (uic1sr, 0x00000000); /* clear all interrupts */
mtdcr (uic1sr, 0xffffffff); /* clear all interrupts */
mtdcr (UIC1SR, 0xffffffff); /* Clear all interrupts */
mtdcr (UIC1ER, 0x00000000); /* disable all interrupts */
mtdcr (UIC1CR, 0x00000000); /* Set Critical / Non Critical interrupts */
mtdcr (UIC1PR, 0xfffac785); /* Set Interrupt Polarities */
mtdcr (UIC1TR, 0x001d0040); /* Set Interrupt Trigger Levels */
mtdcr (UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
mtdcr (UIC1SR, 0x00000000); /* clear all interrupts */
mtdcr (UIC1SR, 0xffffffff); /* clear all interrupts */
mtdcr (uic0sr, 0xffffffff); /* Clear all interrupts */
mtdcr (uic0er, 0x0000000a); /* Disable all interrupts */
mtdcr (UIC0SR, 0xffffffff); /* Clear all interrupts */
mtdcr (UIC0ER, 0x0000000a); /* Disable all interrupts */
/* Except cascade UIC0 and UIC1 */
mtdcr (uic0cr, 0x00000000); /* Set Critical / Non Critical interrupts */
mtdcr (uic0pr, 0xffbfefef); /* Set Interrupt Polarities */
mtdcr (uic0tr, 0x00007000); /* Set Interrupt Trigger Levels */
mtdcr (uic0vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
mtdcr (uic0sr, 0x00000000); /* clear all interrupts */
mtdcr (uic0sr, 0xffffffff); /* clear all interrupts */
mtdcr (UIC0CR, 0x00000000); /* Set Critical / Non Critical interrupts */
mtdcr (UIC0PR, 0xffbfefef); /* Set Interrupt Polarities */
mtdcr (UIC0TR, 0x00007000); /* Set Interrupt Trigger Levels */
mtdcr (UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
mtdcr (UIC0SR, 0x00000000); /* clear all interrupts */
mtdcr (UIC0SR, 0xffffffff); /* clear all interrupts */
/*
* Note: Some cores are still in reset when the chip starts, so
@@ -235,98 +236,3 @@ int checkboard (void)
return (0);
}
/*************************************************************************
* pci_pre_init
*
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things. Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted.
*
* Different boards may wish to customize the pci controller structure
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller * hose )
{
return 0;
}
#endif /* defined(CONFIG_PCI) */
#ifdef CONFIG_PCI
static struct pci_controller pcie_hose[2] = {{0},{0}};
void pcie_setup_hoses(int busno)
{
struct pci_controller *hose;
int i, bus;
int ret = 0;
bus = busno;
char *env;
unsigned int delay;
for (i = 0; i < 2; i++) {
if (is_end_point(i))
ret = ppc4xx_init_pcie_endport(i);
else
ret = ppc4xx_init_pcie_rootport(i);
if (ret) {
printf("PCIE%d: initialization as %s failed\n", i,
is_end_point(i) ? "endpoint" : "root-complex");
continue;
}
hose = &pcie_hose[i];
hose->first_busno = bus;
hose->last_busno = bus;
hose->current_busno = bus;
/* setup mem resource */
pci_set_region(hose->regions + 0,
CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
CONFIG_SYS_PCIE_MEMSIZE,
PCI_REGION_MEM);
hose->region_count = 1;
pci_register_hose(hose);
if (is_end_point(i)) {
ppc4xx_setup_pcie_endpoint(hose, i);
/*
* Reson for no scanning is endpoint can not generate
* upstream configuration accesses.
*/
} else {
ppc4xx_setup_pcie_rootpoint(hose, i);
env = getenv ("pciscandelay");
if (env != NULL) {
delay = simple_strtoul(env, NULL, 10);
if (delay > 5)
printf("Warning, expect noticable delay before "
"PCIe scan due to 'pciscandelay' value!\n");
mdelay(delay * 1000);
}
/*
* Config access can only go down stream
*/
hose->last_busno = pci_hose_scan(hose);
bus = hose->last_busno + 1;
}
}
}
#endif
#if defined(CONFIG_POST)
/*
* Returns 1 if keys pressed to start the power-on long-running tests
* Called from board_init_f().
*/
int post_hotkeys_pressed(void)
{
return 0; /* No hotkeys supported */
}
#endif /* CONFIG_POST */

View File

@@ -1,135 +0,0 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* To compile successfully, uncomment the following section.
* To go in ram, remove the section.
* Added by SunHe.
*/
.resetvec 0xFFFFFFFC :
{
*(.resetvec)
} = 0xffff
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
cpu/ppc4xx/start.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
. = ALIGN(4);
}
_end = . ;
PROVIDE (end = .);
}

View File

@@ -54,7 +54,7 @@ int board_early_init_f (void)
/*-------------------------------------------------------------------------+
| Initialize EBC CONFIG
+-------------------------------------------------------------------------*/
mtebc(xbcfg, EBC_CFG_LE_UNLOCK |
mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK |
EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK |
EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS |
EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT |
@@ -63,14 +63,14 @@ int board_early_init_f (void)
/*-------------------------------------------------------------------------+
| FPGA. Initialize bank 7 with default values.
+-------------------------------------------------------------------------*/
mtebc(pb7ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)|
mtebc(PB7AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)|
EBC_BXAP_BCE_DISABLE|
EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
EBC_BXAP_BEM_WRITEONLY|
EBC_BXAP_PEN_DISABLED);
mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48300000)|
mtebc(PB7CR, EBC_BXCR_BAS_ENCODE(0x48300000)|
EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
/* read FPGA base register FPGA_REG0 */
@@ -95,53 +95,53 @@ int board_early_init_f (void)
/*-------------------------------------------------------------------------+
| 1 MB FLASH / 1 MB SRAM. Initialize bank 0 with default values.
+-------------------------------------------------------------------------*/
mtebc(pb0ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs0_twt)|
mtebc(PB0AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs0_twt)|
EBC_BXAP_BCE_DISABLE|
EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
EBC_BXAP_BEM_WRITEONLY|
EBC_BXAP_PEN_DISABLED);
mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(cs0_base)|
mtebc(PB0CR, EBC_BXCR_BAS_ENCODE(cs0_base)|
cs0_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
/*-------------------------------------------------------------------------+
| 8KB NVRAM/RTC. Initialize bank 1 with default values.
+-------------------------------------------------------------------------*/
mtebc(pb1ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(10)|
mtebc(PB1AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(10)|
EBC_BXAP_BCE_DISABLE|
EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
EBC_BXAP_BEM_WRITEONLY|
EBC_BXAP_PEN_DISABLED);
mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x48000000)|
mtebc(PB1CR, EBC_BXCR_BAS_ENCODE(0x48000000)|
EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
/*-------------------------------------------------------------------------+
| 4 MB FLASH. Initialize bank 2 with default values.
+-------------------------------------------------------------------------*/
mtebc(pb2ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs2_twt)|
mtebc(PB2AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs2_twt)|
EBC_BXAP_BCE_DISABLE|
EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
EBC_BXAP_BEM_WRITEONLY|
EBC_BXAP_PEN_DISABLED);
mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(cs2_base)|
mtebc(PB2CR, EBC_BXCR_BAS_ENCODE(cs2_base)|
cs2_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
/*-------------------------------------------------------------------------+
| FPGA. Initialize bank 7 with default values.
+-------------------------------------------------------------------------*/
mtebc(pb7ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)|
mtebc(PB7AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)|
EBC_BXAP_BCE_DISABLE|
EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
EBC_BXAP_BEM_WRITEONLY|
EBC_BXAP_PEN_DISABLED);
mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48300000)|
mtebc(PB7CR, EBC_BXCR_BAS_ENCODE(0x48300000)|
EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
/*--------------------------------------------------------------------
@@ -159,39 +159,39 @@ int board_early_init_f (void)
* UIC2 UIC1
* UIC3 UIC2
*/
mtdcr (uic1sr, 0xffffffff); /* clear all */
mtdcr (uic1er, 0x00000000); /* disable all */
mtdcr (uic1cr, 0x00000009); /* SMI & UIC1 crit are critical */
mtdcr (uic1pr, 0xfffffe13); /* per ref-board manual */
mtdcr (uic1tr, 0x01c00008); /* per ref-board manual */
mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic1sr, 0xffffffff); /* clear all */
mtdcr (UIC1SR, 0xffffffff); /* clear all */
mtdcr (UIC1ER, 0x00000000); /* disable all */
mtdcr (UIC1CR, 0x00000009); /* SMI & UIC1 crit are critical */
mtdcr (UIC1PR, 0xfffffe13); /* per ref-board manual */
mtdcr (UIC1TR, 0x01c00008); /* per ref-board manual */
mtdcr (UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (UIC1SR, 0xffffffff); /* clear all */
mtdcr (uic2sr, 0xffffffff); /* clear all */
mtdcr (uic2er, 0x00000000); /* disable all */
mtdcr (uic2cr, 0x00000000); /* all non-critical */
mtdcr (uic2pr, 0xffffe0ff); /* per ref-board manual */
mtdcr (uic2tr, 0x00ffc000); /* per ref-board manual */
mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic2sr, 0xffffffff); /* clear all */
mtdcr (UIC2SR, 0xffffffff); /* clear all */
mtdcr (UIC2ER, 0x00000000); /* disable all */
mtdcr (UIC2CR, 0x00000000); /* all non-critical */
mtdcr (UIC2PR, 0xffffe0ff); /* per ref-board manual */
mtdcr (UIC2TR, 0x00ffc000); /* per ref-board manual */
mtdcr (UIC2VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (UIC2SR, 0xffffffff); /* clear all */
mtdcr (uic3sr, 0xffffffff); /* clear all */
mtdcr (uic3er, 0x00000000); /* disable all */
mtdcr (uic3cr, 0x00000000); /* all non-critical */
mtdcr (uic3pr, 0xffffffff); /* per ref-board manual */
mtdcr (uic3tr, 0x00ff8c0f); /* per ref-board manual */
mtdcr (uic3vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic3sr, 0xffffffff); /* clear all */
mtdcr (UIC3SR, 0xffffffff); /* clear all */
mtdcr (UIC3ER, 0x00000000); /* disable all */
mtdcr (UIC3CR, 0x00000000); /* all non-critical */
mtdcr (UIC3PR, 0xffffffff); /* per ref-board manual */
mtdcr (UIC3TR, 0x00ff8c0f); /* per ref-board manual */
mtdcr (UIC3VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (UIC3SR, 0xffffffff); /* clear all */
mtdcr (uic0sr, 0xfc000000); /* clear all */
mtdcr (uic0er, 0x00000000); /* disable all */
mtdcr (uic0cr, 0x00000000); /* all non-critical */
mtdcr (uic0pr, 0xfc000000); /* */
mtdcr (uic0tr, 0x00000000); /* */
mtdcr (uic0vr, 0x00000001); /* */
mfsdr (sdr_mfr, mfr);
mtdcr (UIC0SR, 0xfc000000); /* clear all */
mtdcr (UIC0ER, 0x00000000); /* disable all */
mtdcr (UIC0CR, 0x00000000); /* all non-critical */
mtdcr (UIC0PR, 0xfc000000); /* */
mtdcr (UIC0TR, 0x00000000); /* */
mtdcr (UIC0VR, 0x00000001); /* */
mfsdr (SDR0_MFR, mfr);
mfr &= ~SDR0_MFR_ECS_MASK;
/* mtsdr(sdr_mfr, mfr); */
/* mtsdr(SDR0_MFR, mfr); */
fpga_init();
return 0;
@@ -241,11 +241,11 @@ long int fixed_sdram (void)
/*--------------------------------------------------------------------
* Setup some default
*------------------------------------------------------------------*/
mtsdram (mem_uabba, 0x00000000); /* ubba=0 (default) */
mtsdram (mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
mtsdram (mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
mtsdram (mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */
mtsdram (mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
mtsdram (SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */
mtsdram (SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
mtsdram (SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */
mtsdram (SDRAM0_WDDCTR, 0x00000000); /* wrcp=0 dcd=0 */
mtsdram (SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
/*--------------------------------------------------------------------
* Setup for board-specific specific mem
@@ -253,20 +253,20 @@ long int fixed_sdram (void)
/*
* Following for CAS Latency = 2.5 @ 133 MHz PLB
*/
mtsdram (mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
mtsdram (mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
mtsdram (SDRAM0_B0CR, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
mtsdram (SDRAM0_TR0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
/* RA=10 RD=3 */
mtsdram (mem_tr1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
mtsdram (mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */
mtsdram (mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
mtsdram (SDRAM0_TR1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
mtsdram (SDRAM0_RTR, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */
mtsdram (SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM */
udelay (400); /* Delay 200 usecs (min) */
/*--------------------------------------------------------------------
* Enable the controller, then wait for DCEN to complete
*------------------------------------------------------------------*/
mtsdram (mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
mtsdram (SDRAM0_CFG0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
for (;;) {
mfsdram (mem_mcsts, reg);
mfsdram (SDRAM0_MCSTS, reg);
if (reg & 0x80000000)
break;
}
@@ -275,102 +275,6 @@ long int fixed_sdram (void)
}
#endif /* !defined(CONFIG_SPD_EEPROM) */
/*************************************************************************
* pci_pre_init
*
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things. Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted.
*
* Different boards may wish to customize the pci controller structure
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller * hose )
{
unsigned long strap;
/*--------------------------------------------------------------------------+
* The ocotea board is always configured as the host & requires the
* PCI arbiter to be enabled.
*--------------------------------------------------------------------------*/
mfsdr(sdr_sdstp1, strap);
if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){
printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
return 0;
}
return 1;
}
#endif /* defined(CONFIG_PCI) */
/*************************************************************************
* pci_target_init
*
* The bootstrap configuration provides default settings for the pci
* inbound map (PIM). But the bootstrap config choices are limited and
* may not be sufficient for a given board.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller * hose )
{
/*--------------------------------------------------------------------------+
* Disable everything
*--------------------------------------------------------------------------*/
out32r( PCIX0_PIM0SA, 0 ); /* disable */
out32r( PCIX0_PIM1SA, 0 ); /* disable */
out32r( PCIX0_PIM2SA, 0 ); /* disable */
out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
/*--------------------------------------------------------------------------+
* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
* options to not support sizes such as 128/256 MB.
*--------------------------------------------------------------------------*/
out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
out32r( PCIX0_PIM0LAH, 0 );
out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
out32r( PCIX0_BAR0, 0 );
/*--------------------------------------------------------------------------+
* Program the board's subsystem id/vendor id
*--------------------------------------------------------------------------*/
out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
}
#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
/*************************************************************************
* is_pci_host
*
* This routine is called to determine if a pci scan should be
* performed. With various hardware environments (especially cPCI and
* PPMC) it's insufficient to depend on the state of the arbiter enable
* bit in the strap register, or generic host/adapter assumptions.
*
* Rather than hard-code a bad assumption in the general 440 code, the
* 440 pci code requires the board to decide at runtime.
*
* Return 0 for adapter mode, non-zero for host (monarch) mode.
*
*
************************************************************************/
#if defined(CONFIG_PCI)
int is_pci_host(struct pci_controller *hose)
{
/* The ocotea board is always configured as host. */
return(1);
}
#endif /* defined(CONFIG_PCI) */
void fpga_init(void)
{
unsigned long group;
@@ -379,8 +283,8 @@ void fpga_init(void)
unsigned long sdr0_cust0;
unsigned long pvr;
mfsdr (sdr_pfc0, sdr0_pfc0);
mfsdr (sdr_pfc1, sdr0_pfc1);
mfsdr (SDR0_PFC0, sdr0_pfc0);
mfsdr (SDR0_PFC1, sdr0_pfc1);
group = SDR0_PFC1_EPS_DECODE(sdr0_pfc1);
pvr = get_pvr ();
@@ -390,8 +294,8 @@ void fpga_init(void)
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_EMS;
out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) |
FPGA_REG2_EXT_INTFACE_ENABLE);
mtsdr (sdr_pfc0, sdr0_pfc0);
mtsdr (sdr_pfc1, sdr0_pfc1);
mtsdr (SDR0_PFC0, sdr0_pfc0);
mtsdr (SDR0_PFC1, sdr0_pfc1);
} else {
sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_TRE_MASK) | SDR0_PFC0_TRE_ENABLE;
switch (group)
@@ -403,8 +307,8 @@ void fpga_init(void)
out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) |
FPGA_REG2_EXT_INTFACE_ENABLE);
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_EMS;
mtsdr (sdr_pfc0, sdr0_pfc0);
mtsdr (sdr_pfc1, sdr0_pfc1);
mtsdr (SDR0_PFC0, sdr0_pfc0);
mtsdr (SDR0_PFC1, sdr0_pfc1);
break;
case 3:
case 4:
@@ -412,8 +316,8 @@ void fpga_init(void)
case 6:
/* CPU trace B - Over EBMI */
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_CPUTRACE;
mtsdr (sdr_pfc0, sdr0_pfc0);
mtsdr (sdr_pfc1, sdr0_pfc1);
mtsdr (SDR0_PFC0, sdr0_pfc0);
mtsdr (SDR0_PFC1, sdr0_pfc1);
out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) |
FPGA_REG2_EXT_INTFACE_DISABLE);
break;
@@ -421,8 +325,8 @@ void fpga_init(void)
}
/* Initialize the ethernet specific functions in the fpga */
mfsdr(sdr_pfc1, sdr0_pfc1);
mfsdr(sdr_cust0, sdr0_cust0);
mfsdr(SDR0_PFC1, sdr0_pfc1);
mfsdr(SDR0_CUST0, sdr0_cust0);
if ( (SDR0_PFC1_EPS_DECODE(sdr0_pfc1) == 4) &&
((SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_GMII) ||
(SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_TBI)))
@@ -496,15 +400,3 @@ void fpga_init(void)
return;
}
#ifdef CONFIG_POST
/*
* Returns 1 if keys pressed to start the power-on long-running tests
* Called from board_init_f().
*/
int post_hotkeys_pressed(void)
{
return (ctrlc());
}
#endif

View File

@@ -1,142 +0,0 @@
/*
* (C) Copyright 2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
.resetvec 0xFFFFFFFC :
{
*(.resetvec)
} = 0xffff
.bootpg 0xFFFFF000 :
{
cpu/ppc4xx/start.o (.bootpg)
} = 0xffff
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text)
board/amcc/ocotea/init.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
. = ALIGN(4);
}
_end = . ;
PROVIDE (end = .);
}

View File

@@ -220,7 +220,7 @@ static void early_init_EBC(void)
* default value :
* 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
*/
mtebc(xbcfg, EBC_CFG_LE_UNLOCK |
mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK |
EBC_CFG_PTD_ENABLE |
EBC_CFG_RTC_16PERCLK |
EBC_CFG_ATC_PREVIOUS |
@@ -237,8 +237,8 @@ static void early_init_EBC(void)
* since some board registers values may be needed to determine the
* boot type
*/
mtebc(pb1ap, EBC_BXAP_FPGA);
mtebc(pb1cr, EBC_BXCR_FPGA_CS3);
mtebc(PB1AP, EBC_BXAP_FPGA);
mtebc(PB1CR, EBC_BXCR_FPGA_CS3);
}
@@ -399,12 +399,12 @@ static void early_reinit_EBC(int computed_boot_device)
break;
}
mtebc(pb0ap, ebc0_cs0_bxap_value);
mtebc(pb0cr, ebc0_cs0_bxcr_value);
mtebc(pb1ap, ebc0_cs1_bxap_value);
mtebc(pb1cr, ebc0_cs1_bxcr_value);
mtebc(pb2ap, ebc0_cs2_bxap_value);
mtebc(pb2cr, ebc0_cs2_bxcr_value);
mtebc(PB0AP, ebc0_cs0_bxap_value);
mtebc(PB0CR, ebc0_cs0_bxcr_value);
mtebc(PB1AP, ebc0_cs1_bxap_value);
mtebc(PB1CR, ebc0_cs1_bxcr_value);
mtebc(PB2AP, ebc0_cs2_bxap_value);
mtebc(PB2CR, ebc0_cs2_bxcr_value);
}
static void early_init_UIC(void)
@@ -416,41 +416,41 @@ static void early_init_UIC(void)
* interrupt trigger levels. Make bit 0 High priority. Clear all
* interrupts again.
*/
mtdcr(uic3sr, 0xffffffff); /* Clear all interrupts */
mtdcr(uic3er, 0x00000000); /* disable all interrupts */
mtdcr(uic3cr, 0x00000000); /* Set Critical / Non Critical
mtdcr(UIC3SR, 0xffffffff); /* Clear all interrupts */
mtdcr(UIC3ER, 0x00000000); /* disable all interrupts */
mtdcr(UIC3CR, 0x00000000); /* Set Critical / Non Critical
* interrupts */
mtdcr(uic3pr, 0xffffffff); /* Set Interrupt Polarities */
mtdcr(uic3tr, 0x001fffff); /* Set Interrupt Trigger Levels */
mtdcr(uic3vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic3sr, 0xffffffff); /* clear all interrupts */
mtdcr(UIC3PR, 0xffffffff); /* Set Interrupt Polarities */
mtdcr(UIC3TR, 0x001fffff); /* Set Interrupt Trigger Levels */
mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC3SR, 0xffffffff); /* clear all interrupts */
mtdcr(uic2sr, 0xffffffff); /* Clear all interrupts */
mtdcr(uic2er, 0x00000000); /* disable all interrupts */
mtdcr(uic2cr, 0x00000000); /* Set Critical / Non Critical
mtdcr(UIC2SR, 0xffffffff); /* Clear all interrupts */
mtdcr(UIC2ER, 0x00000000); /* disable all interrupts */
mtdcr(UIC2CR, 0x00000000); /* Set Critical / Non Critical
* interrupts */
mtdcr(uic2pr, 0xebebebff); /* Set Interrupt Polarities */
mtdcr(uic2tr, 0x74747400); /* Set Interrupt Trigger Levels */
mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic2sr, 0xffffffff); /* clear all interrupts */
mtdcr(UIC2PR, 0xebebebff); /* Set Interrupt Polarities */
mtdcr(UIC2TR, 0x74747400); /* Set Interrupt Trigger Levels */
mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC2SR, 0xffffffff); /* clear all interrupts */
mtdcr(uic1sr, 0xffffffff); /* Clear all interrupts */
mtdcr(uic1er, 0x00000000); /* disable all interrupts */
mtdcr(uic1cr, 0x00000000); /* Set Critical / Non Critical
mtdcr(UIC1SR, 0xffffffff); /* Clear all interrupts */
mtdcr(UIC1ER, 0x00000000); /* disable all interrupts */
mtdcr(UIC1CR, 0x00000000); /* Set Critical / Non Critical
* interrupts */
mtdcr(uic1pr, 0xffffffff); /* Set Interrupt Polarities */
mtdcr(uic1tr, 0x001fc0ff); /* Set Interrupt Trigger Levels */
mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic1sr, 0xffffffff); /* clear all interrupts */
mtdcr(UIC1PR, 0xffffffff); /* Set Interrupt Polarities */
mtdcr(UIC1TR, 0x001fc0ff); /* Set Interrupt Trigger Levels */
mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC1SR, 0xffffffff); /* clear all interrupts */
mtdcr(uic0sr, 0xffffffff); /* Clear all interrupts */
mtdcr(uic0er, 0x00000000); /* disable all interrupts excepted
mtdcr(UIC0SR, 0xffffffff); /* Clear all interrupts */
mtdcr(UIC0ER, 0x00000000); /* disable all interrupts excepted
* cascade to be checked */
mtdcr(uic0cr, 0x00104001); /* Set Critical / Non Critical
mtdcr(UIC0CR, 0x00104001); /* Set Critical / Non Critical
* interrupts */
mtdcr(uic0pr, 0xffffffff); /* Set Interrupt Polarities */
mtdcr(uic0tr, 0x000f003c); /* Set Interrupt Trigger Levels */
mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic0sr, 0xffffffff); /* clear all interrupts */
mtdcr(UIC0PR, 0xffffffff); /* Set Interrupt Polarities */
mtdcr(UIC0TR, 0x000f003c); /* Set Interrupt Trigger Levels */
mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC0SR, 0xffffffff); /* clear all interrupts */
}

View File

@@ -1,146 +0,0 @@
/*
* (C) Copyright 2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
.resetvec 0xFFFFFFFC :
{
*(.resetvec)
} = 0xffff
.bootpg 0xFFFFF000 :
{
cpu/ppc4xx/start.o (.bootpg)
} = 0xffff
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text)
board/amcc/redwood/init.o (.text)
/* . = env_offset;*/
/* common/env_embedded.o(.text)*/
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
. = ALIGN(4);
}
_end = . ;
PROVIDE (end = .);
}

View File

@@ -25,9 +25,11 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o cmd_sequoia.o sdram.o
COBJS-y = $(BOARD).o sdram.o
COBJS-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
SOBJS = init.o
COBJS := $(COBJS-y)
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))

View File

@@ -0,0 +1,122 @@
/*
* (C) Copyright 2009
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#include <common.h>
#include <asm/ppc4xx_config.h>
struct ppc4xx_config ppc4xx_config_val[] = {
{
"333-133-nor", "NOR CPU: 333 PLB: 133 OPB: 66 EBC: 66",
{
0x84, 0x70, 0xa2, 0xa6, 0x05, 0x57, 0xa0, 0x10,
0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
}
},
{
"333-166-nor", "NOR CPU: 333 PLB: 166 OPB: 83 EBC: 55",
{
0xc7, 0x78, 0xf3, 0x4e, 0x05, 0xd7, 0xa0, 0x30,
0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
}
},
{
"333-166-nand", "NAND CPU: 333 PLB: 166 OPB: 83 EBC: 55",
{
0xc7, 0x78, 0xf3, 0x4e, 0x05, 0xd7, 0xd0, 0x30,
0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
}
},
{
"400-133-nor", "NOR CPU: 400 PLB: 133 OPB: 66 EBC: 66",
{
0x86, 0x78, 0xc2, 0xc6, 0x05, 0x57, 0xa0, 0x30,
0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
}
},
{
"400-160-nor", "NOR CPU: 400 PLB: 160 OPB: 80 EBC: 53",
{
0x86, 0x78, 0xc2, 0xa6, 0x05, 0xd7, 0xa0, 0x10,
0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
}
},
{
"416-166-nor", "NOR CPU: 416 PLB: 166 OPB: 83 EBC: 55",
{
0xc6, 0x78, 0x52, 0xa6, 0x05, 0xd7, 0xa0, 0x10,
0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
}
},
{
"416-166-nand", "NAND CPU: 416 PLB: 166 OPB: 83 EBC: 55",
{
0xc6, 0x78, 0x52, 0xa6, 0x05, 0xd7, 0xd0, 0x10,
0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
}
},
{
"500-166-nor", "NOR CPU: 500 PLB: 166 OPB: 83 EBC: 55",
{
0xc7, 0x78, 0x52, 0xc6, 0x05, 0xd7, 0xa0, 0x30,
0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
}
},
{
"500-166-nand", "NAND CPU: 500 PLB: 166 OPB: 83 EBC: 55",
{
0xc7, 0x78, 0x52, 0xc6, 0x05, 0xd7, 0xd0, 0x30,
0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
}
},
{
"533-133-nor", "NOR CPU: 533 PLB: 133 OPB: 66 EBC: 66",
{
0x87, 0x78, 0x82, 0x52, 0x09, 0x57, 0xa0, 0x30,
0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
}
},
{
"667-133-nor", "NOR CPU: 667 PLB: 133 OPB: 66 EBC: 66",
{
0x87, 0x78, 0xa2, 0x56, 0x09, 0x57, 0xa0, 0x30,
0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
}
},
{
"667-166-nor", "NOR CPU: 667 PLB: 166 OPB: 83 EBC: 55",
{
0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xa0, 0x30,
0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
}
},
{
"667-166-nand", "NAND CPU: 667 PLB: 166 OPB: 83 EBC: 55",
{
0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xd0, 0x30,
0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
}
},
};
int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val);

View File

@@ -1,231 +0,0 @@
/*
* (C) Copyright 2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#include <common.h>
#include <command.h>
#include <i2c.h>
#include <asm/io.h>
/*
* There are 2 versions of production Sequoia & Rainier platforms.
* The primary difference is the reference clock. Those with
* 33333333 reference clocks will also have 667MHz rated
* processors. Not enough differences to have unique clock
* settings.
*
* NOR and NAND boot options change bytes 6, 7, 8, 9, 11. The
* values are independent of the rest of the clock settings.
*
* All Sequoias & Rainiers select from two possible EEPROMs in Boot
* Config F. One for 33MHz PCI, one for 66MHz PCI. The following
* values are for the 33MHz PCI configuration. Byte 5 (0 base) is
* the only value affected for a 33MHz PCI and simply needs a | 0x08.
*/
#define NAND_COMPATIBLE 0x01
#define NOR_COMPATIBLE 0x02
/* check with Stefan on CONFIG_SYS_I2C_EEPROM_ADDR */
#define I2C_EEPROM_ADDR 0x52
static char *config_labels[] = {
"CPU: 333 PLB: 133 OPB: 66 EBC: 66",
"CPU: 333 PLB: 166 OPB: 83 EBC: 55",
"CPU: 400 PLB: 133 OPB: 66 EBC: 66",
"CPU: 400 PLB: 160 OPB: 80 EBC: 53",
"CPU: 416 PLB: 166 OPB: 83 EBC: 55",
"CPU: 500 PLB: 166 OPB: 83 EBC: 55",
"CPU: 533 PLB: 133 OPB: 66 EBC: 66",
"CPU: 667 PLB: 133 OPB: 66 EBC: 66",
"CPU: 667 PLB: 166 OPB: 83 EBC: 55",
NULL
};
static u8 boot_configs[][17] = {
{
(NOR_COMPATIBLE),
0x84, 0x70, 0xa2, 0xa6, 0x05, 0x57, 0xa0, 0x10, 0x40,
0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
},
{
(NAND_COMPATIBLE | NOR_COMPATIBLE),
0xc7, 0x78, 0xf3, 0x4e, 0x05, 0xd7, 0xa0, 0x30, 0x40,
0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
},
{
(NOR_COMPATIBLE),
0x86, 0x78, 0xc2, 0xc6, 0x05, 0x57, 0xa0, 0x30, 0x40,
0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
},
{
(NOR_COMPATIBLE),
0x86, 0x78, 0xc2, 0xa6, 0x05, 0xd7, 0xa0, 0x10, 0x40,
0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
},
{
(NAND_COMPATIBLE | NOR_COMPATIBLE),
0xc6, 0x78, 0x52, 0xa6, 0x05, 0xd7, 0xa0, 0x10, 0x40,
0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
},
{
(NAND_COMPATIBLE | NOR_COMPATIBLE),
0xc7, 0x78, 0x52, 0xc6, 0x05, 0xd7, 0xa0, 0x30, 0x40,
0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
},
{
(NOR_COMPATIBLE),
0x87, 0x78, 0x82, 0x52, 0x09, 0x57, 0xa0, 0x30, 0x40,
0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
},
{
(NOR_COMPATIBLE),
0x87, 0x78, 0xa2, 0x56, 0x09, 0x57, 0xa0, 0x30, 0x40,
0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
},
{
(NAND_COMPATIBLE | NOR_COMPATIBLE),
0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xa0, 0x30, 0x40,
0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
},
{
0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
}
};
/*
* Bytes 6,8,9,11 change for NAND boot
*/
static u8 nand_boot[] = {
0xd0, 0xa0, 0x68, 0x58
};
static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
u8 *buf, bNAND;
int x, y, nbytes, selcfg;
extern char console_buffer[];
if (argc < 2) {
cmd_usage(cmdtp);
return 1;
}
if ((strcmp(argv[1], "nor") != 0) &&
(strcmp(argv[1], "nand") != 0)) {
printf("Unsupported boot-device - only nor|nand support\n");
return 1;
}
/* set the nand flag based on provided input */
if ((strcmp(argv[1], "nand") == 0))
bNAND = 1;
else
bNAND = 0;
printf("Available configurations: \n\n");
if (bNAND) {
for(x = 0, y = 0; boot_configs[x][0] != 0; x++) {
/* filter on nand compatible */
if (boot_configs[x][0] & NAND_COMPATIBLE) {
printf(" %d - %s\n", (y+1), config_labels[x]);
y++;
}
}
} else {
for(x = 0, y = 0; boot_configs[x][0] != 0; x++) {
/* filter on nor compatible */
if (boot_configs[x][0] & NOR_COMPATIBLE) {
printf(" %d - %s\n", (y+1), config_labels[x]);
y++;
}
}
}
do {
nbytes = readline(" Selection [1-x / quit]: ");
if (nbytes) {
if (strcmp(console_buffer, "quit") == 0)
return 0;
selcfg = simple_strtol(console_buffer, NULL, 10);
if ((selcfg < 1) || (selcfg > y))
nbytes = 0;
}
} while (nbytes == 0);
y = (selcfg - 1);
for (x = 0; boot_configs[x][0] != 0; x++) {
if (bNAND) {
if (boot_configs[x][0] & NAND_COMPATIBLE) {
if (y > 0)
y--;
else if (y < 1)
break;
}
} else {
if (boot_configs[x][0] & NOR_COMPATIBLE) {
if (y > 0)
y--;
else if (y < 1)
break;
}
}
}
buf = &boot_configs[x][1];
if (bNAND) {
buf[6] = nand_boot[0];
buf[8] = nand_boot[1];
buf[9] = nand_boot[2];
buf[11] = nand_boot[3];
}
/* check CPLD register +5 for PCI 66MHz flag */
if ((in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) & CONFIG_SYS_BCSR5_PCI66EN) == 0)
/*
* PLB-to-PCI divisor = 3 for 33MHz sync PCI
* instead of 2 for 66MHz systems
*/
buf[5] |= 0x08;
if (i2c_write(I2C_EEPROM_ADDR, 0, 1, buf, 16) != 0)
printf("Error writing to EEPROM at address 0x%x\n", I2C_EEPROM_ADDR);
udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
printf("Done\n");
printf("Please power-cycle the board for the changes to take effect\n");
return 0;
}
U_BOOT_CMD(
bootstrap, 2, 0, do_bootstrap,
"program the I2C bootstrap EEPROM",
"<nand|nor> - strap to boot from NAND or NOR flash"
);

View File

@@ -43,3 +43,7 @@ endif
ifeq ($(dbcr),1)
PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
endif
ifdef CONFIG_NAND_U_BOOT
LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot-nand.lds
endif

View File

@@ -40,41 +40,53 @@ extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH ch
extern void __ft_board_setup(void *blob, bd_t *bd);
ulong flash_get_size(ulong base, int banknum);
static inline u32 get_async_pci_freq(void)
{
if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) &
CONFIG_SYS_BCSR5_PCI66EN)
return 66666666;
else
return 33333333;
}
int board_early_init_f(void)
{
u32 sdr0_cust0;
u32 sdr0_pfc1, sdr0_pfc2;
u32 reg;
mtdcr(ebccfga, xbcfg);
mtdcr(ebccfgd, 0xb8400000);
mtdcr(EBC0_CFGADDR, EBC0_CFG);
mtdcr(EBC0_CFGDATA, 0xb8400000);
/*
* Setup the interrupt controller polarities, triggers, etc.
*/
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic0er, 0x00000000); /* disable all */
mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
mtdcr(uic0pr, 0xfffff7ff); /* per ref-board manual */
mtdcr(uic0tr, 0x00000000); /* per ref-board manual */
mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(UIC0SR, 0xffffffff); /* clear all */
mtdcr(UIC0ER, 0x00000000); /* disable all */
mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
mtdcr(UIC0PR, 0xfffff7ff); /* per ref-board manual */
mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */
mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC0SR, 0xffffffff); /* clear all */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(uic1er, 0x00000000); /* disable all */
mtdcr(uic1cr, 0x00000000); /* all non-critical */
mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */
mtdcr(uic1tr, 0x00000000); /* per ref-board manual */
mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
mtdcr(UIC1ER, 0x00000000); /* disable all */
mtdcr(UIC1CR, 0x00000000); /* all non-critical */
mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */
mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */
mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
mtdcr(uic2sr, 0xffffffff); /* clear all */
mtdcr(uic2er, 0x00000000); /* disable all */
mtdcr(uic2cr, 0x00000000); /* all non-critical */
mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */
mtdcr(uic2tr, 0x00000000); /* per ref-board manual */
mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic2sr, 0xffffffff); /* clear all */
mtdcr(UIC2SR, 0xffffffff); /* clear all */
mtdcr(UIC2ER, 0x00000000); /* disable all */
mtdcr(UIC2CR, 0x00000000); /* all non-critical */
mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */
mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */
mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC2SR, 0xffffffff); /* clear all */
/* Check and reconfigure the PCI sync clock if necessary */
ppc4xx_pci_sync_clock_config(get_async_pci_freq());
/* 50MHz tmrclk */
out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x04, 0x00);
@@ -107,8 +119,8 @@ int board_early_init_f(void)
mtsdr(SDR0_PFC1, sdr0_pfc1);
/* PCI arbiter enabled */
mfsdr(sdr_pci0, reg);
mtsdr(sdr_pci0, 0x80000000 | reg);
mfsdr(SDR0_PCI0, reg);
mtsdr(SDR0_PCI0, 0x80000000 | reg);
/* setup NAND FLASH */
mfsdr(SDR0_CUST0, sdr0_cust0);
@@ -144,19 +156,19 @@ int misc_init_r(void)
gd->bd->bi_flashoffset = 0;
#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
mtdcr(ebccfga, pb3cr);
mtdcr(EBC0_CFGADDR, PB3CR);
#else
mtdcr(ebccfga, pb0cr);
mtdcr(EBC0_CFGADDR, PB0CR);
#endif
pbcr = mfdcr(ebccfgd);
pbcr = mfdcr(EBC0_CFGDATA);
size_val = ffs(gd->bd->bi_flashsize) - 21;
pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
mtdcr(ebccfga, pb3cr);
mtdcr(EBC0_CFGADDR, PB3CR);
#else
mtdcr(ebccfga, pb0cr);
mtdcr(EBC0_CFGADDR, PB0CR);
#endif
mtdcr(ebccfgd, pbcr);
mtdcr(EBC0_CFGDATA, pbcr);
/*
* Re-check to get correct base address
@@ -309,8 +321,8 @@ int misc_init_r(void)
* This fix will make the MAL burst disabling patch for the Linux
* EMAC driver obsolete.
*/
reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP;
mtdcr(plb4_acr, reg);
reg = mfdcr(PLB4_ACR) & ~PLB4_ACR_WRP;
mtdcr(PLB4_ACR, reg);
return 0;
}
@@ -319,7 +331,7 @@ int checkboard(void)
{
char *s = getenv("serial#");
u8 rev;
u8 val;
u32 clock = get_async_pci_freq();
#ifdef CONFIG_440EPX
printf("Board: Sequoia - AMCC PPC440EPx Evaluation Board");
@@ -328,8 +340,7 @@ int checkboard(void)
#endif
rev = in_8((void *)(CONFIG_SYS_BCSR_BASE + 0));
val = in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) & CONFIG_SYS_BCSR5_PCI66EN;
printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
printf(", Rev. %X, PCI-Async=%d MHz", rev, clock / 1000000);
if (s != NULL) {
puts(", serial# ");
@@ -337,6 +348,15 @@ int checkboard(void)
}
putc('\n');
/*
* Reconfiguration of the PCI sync clock is already done,
* now check again if everything is in range:
*/
if (ppc4xx_pci_sync_clock_config(clock)) {
printf("ERROR: PCI clocking incorrect (async=%d "
"sync=%ld)!\n", clock, get_PCI_freq());
}
return (0);
}
@@ -344,183 +364,12 @@ int checkboard(void)
/*
* Assign interrupts to PCI devices.
*/
void sequoia_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
void board_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
{
pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIRQ2);
}
#endif
/*
* pci_pre_init
*
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things. Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted.
*
* Different boards may wish to customize the pci controller structure
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*/
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller *hose)
{
unsigned long addr;
/*
* Set priority for all PLB3 devices to 0.
* Set PLB3 arbiter to fair mode.
*/
mfsdr(sdr_amp1, addr);
mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(plb3_acr);
mtdcr(plb3_acr, addr | 0x80000000);
/*
* Set priority for all PLB4 devices to 0.
*/
mfsdr(sdr_amp0, addr);
mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
mtdcr(plb4_acr, addr);
/*
* Set Nebula PLB4 arbiter to fair mode.
*/
/* Segment0 */
addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
mtdcr(plb0_acr, addr);
/* Segment1 */
addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
mtdcr(plb1_acr, addr);
#ifdef CONFIG_PCI_PNP
hose->fixup_irq = sequoia_pci_fixup_irq;
#endif
return 1;
}
#endif /* defined(CONFIG_PCI) */
/*
* pci_target_init
*
* The bootstrap configuration provides default settings for the pci
* inbound map (PIM). But the bootstrap config choices are limited and
* may not be sufficient for a given board.
*/
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller *hose)
{
/*
* Set up Direct MMIO registers
*/
/*
* PowerPC440EPX PCI Master configuration.
* Map one 1Gig range of PLB/processor addresses to PCI memory space.
* PLB address 0xA0000000-0xDFFFFFFF
* ==> PCI address 0xA0000000-0xDFFFFFFF
* Use byte reversed out routines to handle endianess.
* Make this region non-prefetchable.
*/
out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */
/* - disabled b4 setting */
out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, */
/* and enable region */
out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute */
/* - disabled b4 setting */
out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, */
/* and enable region */
out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
/*
* Set up Configuration registers
*/
/* Program the board's subsystem id/vendor id */
pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
CONFIG_SYS_PCI_SUBSYS_VENDORID);
pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID);
/* Configure command register as bus master */
pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
/* 240nS PCI clock */
pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
/* No error reporting */
pci_write_config_word(0, PCI_ERREN, 0);
pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
}
#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
void pci_master_init(struct pci_controller *hose)
{
unsigned short temp_short;
/*
* Write the PowerPC440 EP PCI Configuration regs.
* Enable PowerPC440 EP to be a master on the PCI bus (PMM).
* Enable PowerPC440 EP to act as a PCI memory target (PTM).
*/
pci_read_config_word(0, PCI_COMMAND, &temp_short);
pci_write_config_word(0, PCI_COMMAND,
temp_short | PCI_COMMAND_MASTER |
PCI_COMMAND_MEMORY);
}
#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
/*
* is_pci_host
*
* This routine is called to determine if a pci scan should be
* performed. With various hardware environments (especially cPCI and
* PPMC) it's insufficient to depend on the state of the arbiter enable
* bit in the strap register, or generic host/adapter assumptions.
*
* Rather than hard-code a bad assumption in the general 440 code, the
* 440 pci code requires the board to decide at runtime.
*
* Return 0 for adapter mode, non-zero for host (monarch) mode.
*/
#if defined(CONFIG_PCI)
int is_pci_host(struct pci_controller *hose)
{
/* Cactus is always configured as host. */
return (1);
}
#endif /* defined(CONFIG_PCI) */
#if defined(CONFIG_POST)
/*
* Returns 1 if keys pressed to start the power-on long-running tests
* Called from board_init_f().
*/
int post_hotkeys_pressed(void)
{
return 0; /* No hotkeys supported */
}
#endif /* CONFIG_POST */
#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_SYS_RAMBOOT)
/*
* On NAND-booting sequoia, we need to patch the chips select numbers

View File

@@ -62,7 +62,6 @@ SECTIONS
. = ALIGN(0x10000);
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

View File

@@ -53,7 +53,6 @@ SECTIONS
cpu/ppc4xx/start.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

View File

@@ -1,143 +0,0 @@
/*
* (C) Copyright 2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
.resetvec 0xFFFFFFFC :
{
*(.resetvec)
} = 0xffff
.bootpg 0xFFFFF000 :
{
cpu/ppc4xx/start.o (.bootpg)
} = 0xffff
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
. = ALIGN(4);
}
ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN and TEXT_BASE may need to be modified.");
_end = . ;
PROVIDE (end = .);
}

View File

@@ -691,9 +691,10 @@ static int write_word_1(flash_info_t * info, ulong dest, ulong data)
static int write_word(flash_info_t * info, ulong dest, ulong data)
#endif
{
volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *) dest;
volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *) & data;
ulong *data_ptr = &data;
volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]);
volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *)dest;
volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *)data_ptr;
ulong start;
int i;
@@ -1039,9 +1040,10 @@ static int flash_erase_2(flash_info_t * info, int s_first, int s_last)
static int write_word_2(flash_info_t * info, ulong dest, ulong data)
{
volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *) dest;
volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *) & data;
ulong *data_ptr = &data;
volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]);
volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *)dest;
volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *)data_ptr;
ulong start;
int i;

View File

@@ -40,22 +40,22 @@ int board_early_init_f(void)
{
lcd_init();
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000);
mtdcr(uicpr, 0xFFFF7F00); /* set int polarities */
mtdcr(uictr, 0x00000000); /* set int trigger levels */
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
mtdcr(UIC0CR, 0x00000000);
mtdcr(UIC0PR, 0xFFFF7F00); /* set int polarities */
mtdcr(UIC0TR, 0x00000000); /* set int trigger levels */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
mtebc(pb3ap, CONFIG_SYS_EBC_PB3AP); /* memory bank 3 (CPLD_LCM) initialization */
mtebc(pb3cr, CONFIG_SYS_EBC_PB3CR);
mtebc(PB3AP, CONFIG_SYS_EBC_PB3AP); /* memory bank 3 (CPLD_LCM) initialization */
mtebc(PB3CR, CONFIG_SYS_EBC_PB3CR);
/*
* Configure CPC0_PCI to enable PerWE as output
* and enable the internal PCI arbiter
*/
mtdcr(cpc0_pci, CPC0_PCI_SPE | CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN);
mtdcr(CPC0_PCI, CPC0_PCI_SPE | CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN);
return 0;
}

View File

@@ -1,135 +0,0 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
.resetvec 0xFFFFFFFC :
{
*(.resetvec)
} = 0xffff
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
. = ALIGN(4);
}
_end = . ;
PROVIDE (end = .);
}

View File

@@ -33,60 +33,60 @@ void show_reset_reg(void)
/* read clock regsiter */
printf("===== Display reset and initialize register Start =========\n");
mfcpr(clk_pllc,reg);
mfcpr(CPR0_PLLC,reg);
printf("cpr_pllc = %#010lx\n",reg);
mfcpr(clk_plld,reg);
mfcpr(CPR0_PLLD,reg);
printf("cpr_plld = %#010lx\n",reg);
mfcpr(clk_primad,reg);
mfcpr(CPR0_PRIMAD0,reg);
printf("cpr_primad = %#010lx\n",reg);
mfcpr(clk_primbd,reg);
mfcpr(CPR0_PRIMBD0,reg);
printf("cpr_primbd = %#010lx\n",reg);
mfcpr(clk_opbd,reg);
mfcpr(CPR0_OPBD0,reg);
printf("cpr_opbd = %#010lx\n",reg);
mfcpr(clk_perd,reg);
mfcpr(CPR0_PERD,reg);
printf("cpr_perd = %#010lx\n",reg);
mfcpr(clk_mald,reg);
mfcpr(CPR0_MALD,reg);
printf("cpr_mald = %#010lx\n",reg);
/* read sdr register */
mfsdr(sdr_ebc,reg);
printf("sdr_ebc = %#010lx\n",reg);
mfsdr(SDR0_EBC,reg);
printf("SDR0_EBC = %#010lx\n",reg);
mfsdr(sdr_cp440,reg);
printf("sdr_cp440 = %#010lx\n",reg);
mfsdr(SDR0_CP440,reg);
printf("SDR0_CP440 = %#010lx\n",reg);
mfsdr(sdr_xcr,reg);
printf("sdr_xcr = %#010lx\n",reg);
mfsdr(SDR0_XCR,reg);
printf("SDR0_XCR = %#010lx\n",reg);
mfsdr(sdr_xpllc,reg);
printf("sdr_xpllc = %#010lx\n",reg);
mfsdr(SDR0_XPLLC,reg);
printf("SDR0_XPLLC = %#010lx\n",reg);
mfsdr(sdr_xplld,reg);
printf("sdr_xplld = %#010lx\n",reg);
mfsdr(SDR0_XPLLD,reg);
printf("SDR0_XPLLD = %#010lx\n",reg);
mfsdr(sdr_pfc0,reg);
printf("sdr_pfc0 = %#010lx\n",reg);
mfsdr(SDR0_PFC0,reg);
printf("SDR0_PFC0 = %#010lx\n",reg);
mfsdr(sdr_pfc1,reg);
printf("sdr_pfc1 = %#010lx\n",reg);
mfsdr(SDR0_PFC1,reg);
printf("SDR0_PFC1 = %#010lx\n",reg);
mfsdr(sdr_cust0,reg);
printf("sdr_cust0 = %#010lx\n",reg);
mfsdr(SDR0_CUST0,reg);
printf("SDR0_CUST0 = %#010lx\n",reg);
mfsdr(sdr_cust1,reg);
printf("sdr_cust1 = %#010lx\n",reg);
mfsdr(SDR0_CUST1,reg);
printf("SDR0_CUST1 = %#010lx\n",reg);
mfsdr(sdr_uart0,reg);
printf("sdr_uart0 = %#010lx\n",reg);
mfsdr(SDR0_UART0,reg);
printf("SDR0_UART0 = %#010lx\n",reg);
mfsdr(sdr_uart1,reg);
printf("sdr_uart1 = %#010lx\n",reg);
mfsdr(SDR0_UART1,reg);
printf("SDR0_UART1 = %#010lx\n",reg);
printf("===== Display reset and initialize register End =========\n");
}
@@ -96,69 +96,69 @@ void show_xbridge_info(void)
unsigned long reg;
printf("PCI-X chip control registers\n");
mfsdr(sdr_xcr, reg);
printf("sdr_xcr = %#010lx\n", reg);
mfsdr(SDR0_XCR, reg);
printf("SDR0_XCR = %#010lx\n", reg);
mfsdr(sdr_xpllc, reg);
printf("sdr_xpllc = %#010lx\n", reg);
mfsdr(SDR0_XPLLC, reg);
printf("SDR0_XPLLC = %#010lx\n", reg);
mfsdr(sdr_xplld, reg);
printf("sdr_xplld = %#010lx\n", reg);
mfsdr(SDR0_XPLLD, reg);
printf("SDR0_XPLLD = %#010lx\n", reg);
printf("PCI-X Bridge Configure registers\n");
printf("PCIX0_VENDID = %#06x\n", in16r(PCIX0_VENDID));
printf("PCIX0_DEVID = %#06x\n", in16r(PCIX0_DEVID));
printf("PCIX0_CMD = %#06x\n", in16r(PCIX0_CMD));
printf("PCIX0_STATUS = %#06x\n", in16r(PCIX0_STATUS));
printf("PCIX0_REVID = %#04x\n", in8(PCIX0_REVID));
printf("PCIX0_CACHELS = %#04x\n", in8(PCIX0_CACHELS));
printf("PCIX0_LATTIM = %#04x\n", in8(PCIX0_LATTIM));
printf("PCIX0_HDTYPE = %#04x\n", in8(PCIX0_HDTYPE));
printf("PCIX0_BIST = %#04x\n", in8(PCIX0_BIST));
printf("PCIL0_VENDID = %#06x\n", in16r(PCIL0_VENDID));
printf("PCIL0_DEVID = %#06x\n", in16r(PCIL0_DEVID));
printf("PCIL0_CMD = %#06x\n", in16r(PCIL0_CMD));
printf("PCIL0_STATUS = %#06x\n", in16r(PCIL0_STATUS));
printf("PCIL0_REVID = %#04x\n", in8(PCIL0_REVID));
printf("PCIL0_CACHELS = %#04x\n", in8(PCIL0_CACHELS));
printf("PCIL0_LATTIM = %#04x\n", in8(PCIL0_LATTIM));
printf("PCIL0_HDTYPE = %#04x\n", in8(PCIL0_HDTYPE));
printf("PCIL0_BIST = %#04x\n", in8(PCIL0_BIST));
printf("PCIX0_BAR0 = %#010lx\n", in32r(PCIX0_BAR0));
printf("PCIX0_BAR1 = %#010lx\n", in32r(PCIX0_BAR1));
printf("PCIX0_BAR2 = %#010lx\n", in32r(PCIX0_BAR2));
printf("PCIX0_BAR3 = %#010lx\n", in32r(PCIX0_BAR3));
printf("PCIX0_BAR4 = %#010lx\n", in32r(PCIX0_BAR4));
printf("PCIX0_BAR5 = %#010lx\n", in32r(PCIX0_BAR5));
printf("PCIL0_BAR0 = %#010lx\n", in32r(PCIL0_BAR0));
printf("PCIL0_BAR1 = %#010lx\n", in32r(PCIL0_BAR1));
printf("PCIL0_BAR2 = %#010lx\n", in32r(PCIL0_BAR2));
printf("PCIL0_BAR3 = %#010lx\n", in32r(PCIL0_BAR3));
printf("PCIL0_BAR4 = %#010lx\n", in32r(PCIL0_BAR4));
printf("PCIL0_BAR5 = %#010lx\n", in32r(PCIL0_BAR5));
printf("PCIX0_CISPTR = %#010lx\n", in32r(PCIX0_CISPTR));
printf("PCIX0_SBSSYSVID = %#010x\n", in16r(PCIX0_SBSYSVID));
printf("PCIX0_SBSSYSID = %#010x\n", in16r(PCIX0_SBSYSID));
printf("PCIX0_EROMBA = %#010lx\n", in32r(PCIX0_EROMBA));
printf("PCIX0_CAP = %#04x\n", in8(PCIX0_CAP));
printf("PCIX0_INTLN = %#04x\n", in8(PCIX0_INTLN));
printf("PCIX0_INTPN = %#04x\n", in8(PCIX0_INTPN));
printf("PCIX0_MINGNT = %#04x\n", in8(PCIX0_MINGNT));
printf("PCIX0_MAXLTNCY = %#04x\n", in8(PCIX0_MAXLTNCY));
printf("PCIL0_CISPTR = %#010lx\n", in32r(PCIL0_CISPTR));
printf("PCIL0_SBSSYSVID = %#010x\n", in16r(PCIL0_SBSYSVID));
printf("PCIL0_SBSSYSID = %#010x\n", in16r(PCIL0_SBSYSID));
printf("PCIL0_EROMBA = %#010lx\n", in32r(PCIL0_EROMBA));
printf("PCIL0_CAP = %#04x\n", in8(PCIL0_CAP));
printf("PCIL0_INTLN = %#04x\n", in8(PCIL0_INTLN));
printf("PCIL0_INTPN = %#04x\n", in8(PCIL0_INTPN));
printf("PCIL0_MINGNT = %#04x\n", in8(PCIL0_MINGNT));
printf("PCIL0_MAXLTNCY = %#04x\n", in8(PCIL0_MAXLTNCY));
printf("PCIX0_BRDGOPT1 = %#010lx\n", in32r(PCIX0_BRDGOPT1));
printf("PCIX0_BRDGOPT2 = %#010lx\n", in32r(PCIX0_BRDGOPT2));
printf("PCIL0_BRDGOPT1 = %#010lx\n", in32r(PCIL0_BRDGOPT1));
printf("PCIL0_BRDGOPT2 = %#010lx\n", in32r(PCIL0_BRDGOPT2));
printf("PCIX0_POM0LAL = %#010lx\n", in32r(PCIX0_POM0LAL));
printf("PCIX0_POM0LAH = %#010lx\n", in32r(PCIX0_POM0LAH));
printf("PCIX0_POM0SA = %#010lx\n", in32r(PCIX0_POM0SA));
printf("PCIX0_POM0PCILAL = %#010lx\n", in32r(PCIX0_POM0PCIAL));
printf("PCIX0_POM0PCILAH = %#010lx\n", in32r(PCIX0_POM0PCIAH));
printf("PCIX0_POM1LAL = %#010lx\n", in32r(PCIX0_POM1LAL));
printf("PCIX0_POM1LAH = %#010lx\n", in32r(PCIX0_POM1LAH));
printf("PCIX0_POM1SA = %#010lx\n", in32r(PCIX0_POM1SA));
printf("PCIX0_POM1PCILAL = %#010lx\n", in32r(PCIX0_POM1PCIAL));
printf("PCIX0_POM1PCILAH = %#010lx\n", in32r(PCIX0_POM1PCIAH));
printf("PCIX0_POM2SA = %#010lx\n", in32r(PCIX0_POM2SA));
printf("PCIL0_POM0LAL = %#010lx\n", in32r(PCIL0_POM0LAL));
printf("PCIL0_POM0LAH = %#010lx\n", in32r(PCIL0_POM0LAH));
printf("PCIL0_POM0SA = %#010lx\n", in32r(PCIL0_POM0SA));
printf("PCIL0_POM0PCILAL = %#010lx\n", in32r(PCIL0_POM0PCIAL));
printf("PCIL0_POM0PCILAH = %#010lx\n", in32r(PCIL0_POM0PCIAH));
printf("PCIL0_POM1LAL = %#010lx\n", in32r(PCIL0_POM1LAL));
printf("PCIL0_POM1LAH = %#010lx\n", in32r(PCIL0_POM1LAH));
printf("PCIL0_POM1SA = %#010lx\n", in32r(PCIL0_POM1SA));
printf("PCIL0_POM1PCILAL = %#010lx\n", in32r(PCIL0_POM1PCIAL));
printf("PCIL0_POM1PCILAH = %#010lx\n", in32r(PCIL0_POM1PCIAH));
printf("PCIL0_POM2SA = %#010lx\n", in32r(PCIL0_POM2SA));
printf("PCIX0_PIM0SA = %#010lx\n", in32r(PCIX0_PIM0SA));
printf("PCIX0_PIM0LAL = %#010lx\n", in32r(PCIX0_PIM0LAL));
printf("PCIX0_PIM0LAH = %#010lx\n", in32r(PCIX0_PIM0LAH));
printf("PCIX0_PIM1SA = %#010lx\n", in32r(PCIX0_PIM1SA));
printf("PCIX0_PIM1LAL = %#010lx\n", in32r(PCIX0_PIM1LAL));
printf("PCIX0_PIM1LAH = %#010lx\n", in32r(PCIX0_PIM1LAH));
printf("PCIX0_PIM2SA = %#010lx\n", in32r(PCIX0_PIM1SA));
printf("PCIX0_PIM2LAL = %#010lx\n", in32r(PCIX0_PIM1LAL));
printf("PCIX0_PIM2LAH = %#010lx\n", in32r(PCIX0_PIM1LAH));
printf("PCIL0_PIM0SA = %#010lx\n", in32r(PCIL0_PIM0SA));
printf("PCIL0_PIM0LAL = %#010lx\n", in32r(PCIL0_PIM0LAL));
printf("PCIL0_PIM0LAH = %#010lx\n", in32r(PCIL0_PIM0LAH));
printf("PCIL0_PIM1SA = %#010lx\n", in32r(PCIL0_PIM1SA));
printf("PCIL0_PIM1LAL = %#010lx\n", in32r(PCIL0_PIM1LAL));
printf("PCIL0_PIM1LAH = %#010lx\n", in32r(PCIL0_PIM1LAH));
printf("PCIL0_PIM2SA = %#010lx\n", in32r(PCIL0_PIM1SA));
printf("PCIL0_PIM2LAL = %#010lx\n", in32r(PCIL0_PIM1LAL));
printf("PCIL0_PIM2LAH = %#010lx\n", in32r(PCIL0_PIM1LAH));
printf("PCIX0_XSTS = %#010lx\n", in32r(PCIX0_STS));
printf("PCIL0_XSTS = %#010lx\n", in32r(PCIL0_STS));
}
int do_show_xbridge_info(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])

View File

@@ -47,7 +47,7 @@ int board_early_init_f (void)
/*-------------------------------------------------------------------------+
| Initialize EBC CONFIG
+-------------------------------------------------------------------------*/
mtebc(xbcfg, EBC_CFG_LE_UNLOCK |
mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK |
EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK |
EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS |
EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_DEFAULT |
@@ -56,66 +56,66 @@ int board_early_init_f (void)
/*-------------------------------------------------------------------------+
| 64MB FLASH. Initialize bank 0 with default values.
+-------------------------------------------------------------------------*/
mtebc(pb0ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(15) |
mtebc(PB0AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(15) |
EBC_BXAP_BCE_DISABLE |
EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_OEN_ENCODE(1) |
EBC_BXAP_WBN_ENCODE(1) | EBC_BXAP_WBF_ENCODE(1) |
EBC_BXAP_TH_ENCODE(3) | EBC_BXAP_RE_DISABLED |
EBC_BXAP_BEM_WRITEONLY |
EBC_BXAP_PEN_DISABLED);
mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) |
mtebc(PB0CR, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) |
EBC_BXCR_BS_64MB | EBC_BXCR_BU_RW|EBC_BXCR_BW_32BIT);
/*-------------------------------------------------------------------------+
| FPGA. Initialize bank 1 with default values.
+-------------------------------------------------------------------------*/
mtebc(pb1ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(5) |
mtebc(PB1AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(5) |
EBC_BXAP_BCE_DISABLE |
EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_OEN_ENCODE(1) |
EBC_BXAP_WBN_ENCODE(1) | EBC_BXAP_WBF_ENCODE(1) |
EBC_BXAP_TH_ENCODE(3) | EBC_BXAP_RE_DISABLED |
EBC_BXAP_BEM_WRITEONLY |
EBC_BXAP_PEN_DISABLED);
mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x41000000) |
mtebc(PB1CR, EBC_BXCR_BAS_ENCODE(0x41000000) |
EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
/*-------------------------------------------------------------------------+
| LCM. Initialize bank 2 with default values.
+-------------------------------------------------------------------------*/
mtebc(pb2ap, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(64) |
mtebc(PB2AP, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(64) |
EBC_BXAP_BCE_DISABLE |
EBC_BXAP_CSN_ENCODE(3) | EBC_BXAP_OEN_ENCODE(3) |
EBC_BXAP_WBN_ENCODE(3) | EBC_BXAP_WBF_ENCODE(3) |
EBC_BXAP_TH_ENCODE(7) | EBC_BXAP_RE_DISABLED |
EBC_BXAP_BEM_WRITEONLY |
EBC_BXAP_PEN_DISABLED);
mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(0x42000000) |
mtebc(PB2CR, EBC_BXCR_BAS_ENCODE(0x42000000) |
EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
/*-------------------------------------------------------------------------+
| TMP. Initialize bank 3 with default values.
+-------------------------------------------------------------------------*/
mtebc(pb3ap, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(128) |
mtebc(PB3AP, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(128) |
EBC_BXAP_BCE_DISABLE |
EBC_BXAP_CSN_ENCODE(3) | EBC_BXAP_OEN_ENCODE(3) |
EBC_BXAP_WBN_ENCODE(3) | EBC_BXAP_WBF_ENCODE(3) |
EBC_BXAP_TH_ENCODE(7) | EBC_BXAP_RE_DISABLED |
EBC_BXAP_BEM_WRITEONLY |
EBC_BXAP_PEN_DISABLED);
mtebc(pb3cr, EBC_BXCR_BAS_ENCODE(0x48000000) |
mtebc(PB3CR, EBC_BXCR_BAS_ENCODE(0x48000000) |
EBC_BXCR_BS_64MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
/*-------------------------------------------------------------------------+
| Connector 4~7. Initialize bank 3~ 7 with default values.
+-------------------------------------------------------------------------*/
mtebc(pb4ap,0);
mtebc(pb4cr,0);
mtebc(pb5ap,0);
mtebc(pb5cr,0);
mtebc(pb6ap,0);
mtebc(pb6cr,0);
mtebc(pb7ap,0);
mtebc(pb7cr,0);
mtebc(PB4AP,0);
mtebc(PB4CR,0);
mtebc(PB5AP,0);
mtebc(PB5CR,0);
mtebc(PB6AP,0);
mtebc(PB6CR,0);
mtebc(PB7AP,0);
mtebc(PB7CR,0);
/*--------------------------------------------------------------------
* Setup the interrupt controller polarities, triggers, etc.
@@ -132,45 +132,45 @@ int board_early_init_f (void)
* UIC2 UIC1
* UIC3 UIC2
*/
mtdcr (uic1sr, 0xffffffff); /* clear all */
mtdcr (uic1er, 0x00000000); /* disable all */
mtdcr (uic1cr, 0x00000009); /* SMI & UIC1 crit are critical */
mtdcr (uic1pr, 0xfffffe13); /* per ref-board manual */
mtdcr (uic1tr, 0x01c00008); /* per ref-board manual */
mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic1sr, 0xffffffff); /* clear all */
mtdcr (UIC1SR, 0xffffffff); /* clear all */
mtdcr (UIC1ER, 0x00000000); /* disable all */
mtdcr (UIC1CR, 0x00000009); /* SMI & UIC1 crit are critical */
mtdcr (UIC1PR, 0xfffffe13); /* per ref-board manual */
mtdcr (UIC1TR, 0x01c00008); /* per ref-board manual */
mtdcr (UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (UIC1SR, 0xffffffff); /* clear all */
mtdcr (uic2sr, 0xffffffff); /* clear all */
mtdcr (uic2er, 0x00000000); /* disable all */
mtdcr (uic2cr, 0x00000000); /* all non-critical */
mtdcr (uic2pr, 0xffffe0ff); /* per ref-board manual */
mtdcr (uic2tr, 0x00ffc000); /* per ref-board manual */
mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic2sr, 0xffffffff); /* clear all */
mtdcr (UIC2SR, 0xffffffff); /* clear all */
mtdcr (UIC2ER, 0x00000000); /* disable all */
mtdcr (UIC2CR, 0x00000000); /* all non-critical */
mtdcr (UIC2PR, 0xffffe0ff); /* per ref-board manual */
mtdcr (UIC2TR, 0x00ffc000); /* per ref-board manual */
mtdcr (UIC2VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (UIC2SR, 0xffffffff); /* clear all */
mtdcr (uic3sr, 0xffffffff); /* clear all */
mtdcr (uic3er, 0x00000000); /* disable all */
mtdcr (uic3cr, 0x00000000); /* all non-critical */
mtdcr (uic3pr, 0xffffffff); /* per ref-board manual */
mtdcr (uic3tr, 0x00ff8c0f); /* per ref-board manual */
mtdcr (uic3vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic3sr, 0xffffffff); /* clear all */
mtdcr (UIC3SR, 0xffffffff); /* clear all */
mtdcr (UIC3ER, 0x00000000); /* disable all */
mtdcr (UIC3CR, 0x00000000); /* all non-critical */
mtdcr (UIC3PR, 0xffffffff); /* per ref-board manual */
mtdcr (UIC3TR, 0x00ff8c0f); /* per ref-board manual */
mtdcr (UIC3VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (UIC3SR, 0xffffffff); /* clear all */
mtdcr (uic0sr, 0xfc000000); /* clear all */
mtdcr (uic0er, 0x00000000); /* disable all */
mtdcr (uic0cr, 0x00000000); /* all non-critical */
mtdcr (uic0pr, 0xfc000000); /* */
mtdcr (uic0tr, 0x00000000); /* */
mtdcr (uic0vr, 0x00000001); /* */
mtdcr (UIC0SR, 0xfc000000); /* clear all */
mtdcr (UIC0ER, 0x00000000); /* disable all */
mtdcr (UIC0CR, 0x00000000); /* all non-critical */
mtdcr (UIC0PR, 0xfc000000); /* */
mtdcr (UIC0TR, 0x00000000); /* */
mtdcr (UIC0VR, 0x00000001); /* */
/* Enable two GPIO 10~11 and TraceA signal */
mfsdr(sdr_pfc0,reg);
mfsdr(SDR0_PFC0,reg);
reg |= 0x00300000;
mtsdr(sdr_pfc0,reg);
mtsdr(SDR0_PFC0,reg);
mfsdr(sdr_pfc1,reg);
mfsdr(SDR0_PFC1,reg);
reg |= 0x00100000;
mtsdr(sdr_pfc1,reg);
mtsdr(SDR0_PFC1,reg);
/* Set GPIO 10 and 11 as output */
GpioOdr = (volatile unsigned int*)(CONFIG_SYS_PERIPHERAL_BASE+0x718);
@@ -209,110 +209,6 @@ int checkboard (void)
return (0);
}
/*************************************************************************
* pci_pre_init
*
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things. Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted.
*
* Different boards may wish to customize the pci controller structure
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller * hose )
{
unsigned long strap;
/*--------------------------------------------------------------------------+
* The ocotea board is always configured as the host & requires the
* PCI arbiter to be enabled.
*--------------------------------------------------------------------------*/
mfsdr(sdr_sdstp1, strap);
if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){
printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
return 0;
}
return 1;
}
#endif /* defined(CONFIG_PCI) */
/*************************************************************************
* pci_target_init
*
* The bootstrap configuration provides default settings for the pci
* inbound map (PIM). But the bootstrap config choices are limited and
* may not be sufficient for a given board.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller * hose )
{
/*--------------------------------------------------------------------------+
* Disable everything
*--------------------------------------------------------------------------*/
out32r( PCIX0_PIM0SA, 0 ); /* disable */
out32r( PCIX0_PIM1SA, 0 ); /* disable */
out32r( PCIX0_PIM2SA, 0 ); /* disable */
out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
/*--------------------------------------------------------------------------+
* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
* options to not support sizes such as 128/256 MB.
*--------------------------------------------------------------------------*/
out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
out32r( PCIX0_PIM0LAH, 0 );
out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
out32r( PCIX0_BAR0, 0 );
/*--------------------------------------------------------------------------+
* Program the board's subsystem id/vendor id
*--------------------------------------------------------------------------*/
out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
}
#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
/*************************************************************************
* is_pci_host
*
* This routine is called to determine if a pci scan should be
* performed. With various hardware environments (especially cPCI and
* PPMC) it's insufficient to depend on the state of the arbiter enable
* bit in the strap register, or generic host/adapter assumptions.
*
* Rather than hard-code a bad assumption in the general 440 code, the
* 440 pci code requires the board to decide at runtime.
*
* Return 0 for adapter mode, non-zero for host (monarch) mode.
*
*
************************************************************************/
#if defined(CONFIG_PCI)
int is_pci_host(struct pci_controller *hose)
{
/* The ocotea board is always configured as host. */
return(1);
}
#endif /* defined(CONFIG_PCI) */
#ifdef CONFIG_POST
/*
* Returns 1 if keys pressed to start the power-on long-running tests
* Called from board_init_f().
*/
int post_hotkeys_pressed(void)
{
return (ctrlc());
}
#endif
int board_eth_init(bd_t *bis)
{
cpu_eth_init(bis);

View File

@@ -1,142 +0,0 @@
/*
* (C) Copyright 2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
.resetvec 0xFFFFFFFC :
{
*(.resetvec)
} = 0xffff
.bootpg 0xFFFFF000 :
{
cpu/ppc4xx/start.o (.bootpg)
} = 0xffff
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text)
board/amcc/taishan/init.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
. = ALIGN(4);
}
_end = . ;
PROVIDE (end = .);
}

View File

@@ -102,27 +102,27 @@ unsigned long flash_init(void)
/* Re-do sizing to get full correct info */
if (size_b1) {
mtdcr(ebccfga, pb0cr);
pbcr = mfdcr(ebccfgd);
mtdcr(ebccfga, pb0cr);
mtdcr(EBC0_CFGADDR, PB0CR);
pbcr = mfdcr(EBC0_CFGDATA);
mtdcr(EBC0_CFGADDR, PB0CR);
base_b1 = -size_b1;
pbcr =
(pbcr & 0x0001ffff) | base_b1 |
(((size_b1 / 1024 / 1024) - 1) << 17);
mtdcr(ebccfgd, pbcr);
/* printf("pb1cr = %x\n", pbcr); */
mtdcr(EBC0_CFGDATA, pbcr);
/* printf("PB1CR = %x\n", pbcr); */
}
if (size_b0) {
mtdcr(ebccfga, pb1cr);
pbcr = mfdcr(ebccfgd);
mtdcr(ebccfga, pb1cr);
mtdcr(EBC0_CFGADDR, PB1CR);
pbcr = mfdcr(EBC0_CFGDATA);
mtdcr(EBC0_CFGADDR, PB1CR);
base_b0 = base_b1 - size_b0;
pbcr =
(pbcr & 0x0001ffff) | base_b0 |
(((size_b0 / 1024 / 1024) - 1) << 17);
mtdcr(ebccfgd, pbcr);
/* printf("pb0cr = %x\n", pbcr); */
mtdcr(EBC0_CFGDATA, pbcr);
/* printf("PB0CR = %x\n", pbcr); */
}
size_b0 = flash_get_size((vu_long *) base_b0, &flash_info[0]);

View File

@@ -1,136 +0,0 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
.resetvec 0xFFFFFFFC :
{
*(.resetvec)
} = 0xffff
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
. = ALIGN(4);
}
_end = . ;
PROVIDE (end = .);
}

View File

@@ -47,13 +47,13 @@ int board_early_init_f(void)
|
+-------------------------------------------------------------------------*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000020); /* set all but FPGA SMI to be non-critical */
mtdcr(uicpr, 0xFFFFFFE0); /* set int polarities */
mtdcr(uictr, 0x10000000); /* set int trigger levels */
mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
mtdcr(UIC0CR, 0x00000020); /* set all but FPGA SMI to be non-critical */
mtdcr(UIC0PR, 0xFFFFFFE0); /* set int polarities */
mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
/* set UART1 control to select CTS/RTS */
#define FPGA_BRDC 0xF0300004

View File

@@ -1,142 +0,0 @@
/*
* (C) Copyright 2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
.resetvec 0xFFFFFFFC :
{
*(.resetvec)
} = 0xffff
.bootpg 0xFFFFF000 :
{
cpu/ppc4xx/start.o (.bootpg)
} = 0xffff
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text)
board/amcc/yosemite/init.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
. = ALIGN(4);
}
_end = . ;
PROVIDE (end = .);
}

View File

@@ -33,6 +33,15 @@ DECLARE_GLOBAL_DATA_PTR;
extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
static inline u32 get_async_pci_freq(void)
{
if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) &
CONFIG_SYS_BCSR5_PCI66EN)
return 66666666;
else
return 33333333;
}
int board_early_init_f(void)
{
register uint reg;
@@ -40,9 +49,9 @@ int board_early_init_f(void)
/*--------------------------------------------------------------------
* Setup the external bus controller/chip selects
*-------------------------------------------------------------------*/
mtdcr(ebccfga, xbcfg);
reg = mfdcr(ebccfgd);
mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */
mtdcr(EBC0_CFGADDR, EBC0_CFG);
reg = mfdcr(EBC0_CFGDATA);
mtdcr(EBC0_CFGDATA, reg | 0x04000000); /* Set ATC */
/*--------------------------------------------------------------------
* Setup the GPIO pins
@@ -82,29 +91,32 @@ int board_early_init_f(void)
/*--------------------------------------------------------------------
* Setup the interrupt controller polarities, triggers, etc.
*-------------------------------------------------------------------*/
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic0er, 0x00000000); /* disable all */
mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */
mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(UIC0SR, 0xffffffff); /* clear all */
mtdcr(UIC0ER, 0x00000000); /* disable all */
mtdcr(UIC0CR, 0x00000009); /* ATI & UIC1 crit are critical */
mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */
mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */
mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(UIC0SR, 0xffffffff); /* clear all */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(uic1er, 0x00000000); /* disable all */
mtdcr(uic1cr, 0x00000000); /* all non-critical */
mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
mtdcr(UIC1ER, 0x00000000); /* disable all */
mtdcr(UIC1CR, 0x00000000); /* all non-critical */
mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */
mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */
mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
/*--------------------------------------------------------------------
* Setup other serial configuration
*-------------------------------------------------------------------*/
mfsdr(sdr_pci0, reg);
mtsdr(sdr_pci0, 0x80000000 | reg); /* PCI arbiter enabled */
mtsdr(sdr_pfc0, 0x00003e00); /* Pin function */
mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins */
mfsdr(SDR0_PCI0, reg);
mtsdr(SDR0_PCI0, 0x80000000 | reg); /* PCI arbiter enabled */
mtsdr(SDR0_PFC0, 0x00003e00); /* Pin function */
mtsdr(SDR0_PFC1, 0x00048000); /* Pin function: UART0 has 4 pins */
/* Check and reconfigure the PCI sync clock if necessary */
ppc4xx_pci_sync_clock_config(get_async_pci_freq());
/*clear tmrclk divisor */
*(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x04) = 0x00;
@@ -129,8 +141,8 @@ int misc_init_r (void)
int size_val = 0;
/* Re-do sizing to get full correct info */
mtdcr(ebccfga, pb0cr);
pbcr = mfdcr(ebccfgd);
mtdcr(EBC0_CFGADDR, PB0CR);
pbcr = mfdcr(EBC0_CFGDATA);
switch (gd->bd->bi_flashsize) {
case 1 << 20:
size_val = 0;
@@ -158,8 +170,8 @@ int misc_init_r (void)
break;
}
pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
mtdcr(ebccfga, pb0cr);
mtdcr(ebccfgd, pbcr);
mtdcr(EBC0_CFGADDR, PB0CR);
mtdcr(EBC0_CFGDATA, pbcr);
/* adjust flash start and offset */
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
@@ -178,7 +190,7 @@ int checkboard(void)
{
char *s = getenv("serial#");
u8 rev;
u8 val;
u32 clock = get_async_pci_freq();
#ifdef CONFIG_440EP
printf("Board: Yosemite - AMCC PPC440EP Evaluation Board");
@@ -187,8 +199,7 @@ int checkboard(void)
#endif
rev = in_8((void *)(CONFIG_SYS_BCSR_BASE + 0));
val = in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) & CONFIG_SYS_BCSR5_PCI66EN;
printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
printf(", Rev. %X, PCI-Async=%d MHz", rev, clock / 1000000);
if (s != NULL) {
puts(", serial# ");
@@ -196,6 +207,15 @@ int checkboard(void)
}
putc('\n');
/*
* Reconfiguration of the PCI sync clock is already done,
* now check again if everything is in range:
*/
if (ppc4xx_pci_sync_clock_config(clock)) {
printf("ERROR: PCI clocking incorrect (async=%d "
"sync=%ld)!\n", clock, get_PCI_freq());
}
return (0);
}
@@ -237,7 +257,7 @@ void sdram_tr1_set(int ram_address, int* tr1_value)
/* go through all possible SDRAM0_TR1[RDCT] values */
for (i=0; i<=0x1ff; i++) {
/* set the current value for TR1 */
mtsdram(mem_tr1, (0x80800800 | i));
mtsdram(SDRAM0_TR1, (0x80800800 | i));
/* write values */
for (j=0; j<NUM_TRIES; j++) {
@@ -289,15 +309,15 @@ phys_size_t initdram(int board)
/*--------------------------------------------------------------------
* Setup some default
*------------------------------------------------------------------*/
mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */
mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
mtsdram(mem_clktr, 0x40000000); /* ?? */
mtsdram(mem_wddctr, 0x40000000); /* ?? */
mtsdram(SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */
mtsdram(SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
mtsdram(SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */
mtsdram(SDRAM0_CLKTR, 0x40000000); /* ?? */
mtsdram(SDRAM0_WDDCTR, 0x40000000); /* ?? */
/*clear this first, if the DDR is enabled by a debugger
then you can not make changes. */
mtsdram(mem_cfg0, 0x00000000); /* Disable EEC */
mtsdram(SDRAM0_CFG0, 0x00000000); /* Disable EEC */
/*--------------------------------------------------------------------
* Setup for board-specific specific mem
@@ -305,193 +325,33 @@ phys_size_t initdram(int board)
/*
* Following for CAS Latency = 2.5 @ 133 MHz PLB
*/
mtsdram(mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
mtsdram(mem_b1cr, 0x080a4001); /* SDBA=0x080 128MB, Mode 3, enabled */
mtsdram(SDRAM0_B0CR, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
mtsdram(SDRAM0_B1CR, 0x080a4001); /* SDBA=0x080 128MB, Mode 3, enabled */
mtsdram(mem_tr0, 0x410a4012); /* ?? */
mtsdram(mem_rtr, 0x04080000); /* ?? */
mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
mtsdram(mem_cfg0, 0x30000000); /* Disable EEC */
mtsdram(SDRAM0_TR0, 0x410a4012); /* ?? */
mtsdram(SDRAM0_RTR, 0x04080000); /* ?? */
mtsdram(SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM */
mtsdram(SDRAM0_CFG0, 0x30000000); /* Disable EEC */
udelay(400); /* Delay 200 usecs (min) */
/*--------------------------------------------------------------------
* Enable the controller, then wait for DCEN to complete
*------------------------------------------------------------------*/
mtsdram(mem_cfg0, 0x80000000); /* Enable */
mtsdram(SDRAM0_CFG0, 0x80000000); /* Enable */
for (;;) {
mfsdram(mem_mcsts, reg);
mfsdram(SDRAM0_MCSTS, reg);
if (reg & 0x80000000)
break;
}
sdram_tr1_set(0x00000000, &tr1_bank1);
sdram_tr1_set(0x08000000, &tr1_bank2);
mtsdram(mem_tr1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800));
mtsdram(SDRAM0_TR1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800));
return CONFIG_SYS_SDRAM_BANKS * (CONFIG_SYS_KBYTES_SDRAM * 1024); /* return bytes */
}
/*************************************************************************
* pci_pre_init
*
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things. Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted.
*
* Different boards may wish to customize the pci controller structure
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller *hose)
{
unsigned long addr;
/*-------------------------------------------------------------------------+
| Set priority for all PLB3 devices to 0.
| Set PLB3 arbiter to fair mode.
+-------------------------------------------------------------------------*/
mfsdr(sdr_amp1, addr);
mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(plb3_acr);
mtdcr(plb3_acr, addr | 0x80000000);
/*-------------------------------------------------------------------------+
| Set priority for all PLB4 devices to 0.
+-------------------------------------------------------------------------*/
mfsdr(sdr_amp0, addr);
mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
mtdcr(plb4_acr, addr);
/*-------------------------------------------------------------------------+
| Set Nebula PLB4 arbiter to fair mode.
+-------------------------------------------------------------------------*/
/* Segment0 */
addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
mtdcr(plb0_acr, addr);
/* Segment1 */
addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
mtdcr(plb1_acr, addr);
return 1;
}
#endif /* defined(CONFIG_PCI) */
/*************************************************************************
* pci_target_init
*
* The bootstrap configuration provides default settings for the pci
* inbound map (PIM). But the bootstrap config choices are limited and
* may not be sufficient for a given board.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller *hose)
{
/*--------------------------------------------------------------------------+
* Set up Direct MMIO registers
*--------------------------------------------------------------------------*/
/*--------------------------------------------------------------------------+
| PowerPC440 EP PCI Master configuration.
| Map one 1Gig range of PLB/processor addresses to PCI memory space.
| PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
| Use byte reversed out routines to handle endianess.
| Make this region non-prefetchable.
+--------------------------------------------------------------------------*/
out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
/*--------------------------------------------------------------------------+
* Set up Configuration registers
*--------------------------------------------------------------------------*/
/* Program the board's subsystem id/vendor id */
pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
CONFIG_SYS_PCI_SUBSYS_VENDORID);
pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID);
/* Configure command register as bus master */
pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
/* 240nS PCI clock */
pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
/* No error reporting */
pci_write_config_word(0, PCI_ERREN, 0);
pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
}
#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
/*************************************************************************
* pci_master_init
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
void pci_master_init(struct pci_controller *hose)
{
unsigned short temp_short;
/*--------------------------------------------------------------------------+
| Write the PowerPC440 EP PCI Configuration regs.
| Enable PowerPC440 EP to be a master on the PCI bus (PMM).
| Enable PowerPC440 EP to act as a PCI memory target (PTM).
+--------------------------------------------------------------------------*/
pci_read_config_word(0, PCI_COMMAND, &temp_short);
pci_write_config_word(0, PCI_COMMAND,
temp_short | PCI_COMMAND_MASTER |
PCI_COMMAND_MEMORY);
}
#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
/*************************************************************************
* is_pci_host
*
* This routine is called to determine if a pci scan should be
* performed. With various hardware environments (especially cPCI and
* PPMC) it's insufficient to depend on the state of the arbiter enable
* bit in the strap register, or generic host/adapter assumptions.
*
* Rather than hard-code a bad assumption in the general 440 code, the
* 440 pci code requires the board to decide at runtime.
*
* Return 0 for adapter mode, non-zero for host (monarch) mode.
*
*
************************************************************************/
#if defined(CONFIG_PCI)
int is_pci_host(struct pci_controller *hose)
{
/* Bamboo is always configured as host. */
return (1);
}
#endif /* defined(CONFIG_PCI) */
/*************************************************************************
* hw_watchdog_reset
*

View File

@@ -914,9 +914,10 @@ static int flash_erase_2(flash_info_t * info, int s_first, int s_last)
static int write_word_2(flash_info_t * info, ulong dest, ulong data)
{
volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *) dest;
volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *) & data;
ulong *data_ptr = &data;
volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]);
volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *)dest;
volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *)data_ptr;
ulong start;
int i;
@@ -981,7 +982,7 @@ unsigned long flash_init(void)
* Boot Settings in IIC EEprom address 0xA8 or 0xA0
* Read Serial Device Strap Register1 in PPC440SPe
*/
mfsdr(sdr_sdstp1, val);
mfsdr(SDR0_SDSTP1, val);
boot_selection = val & SDR0_SDSTP1_BOOT_SEL_MASK;
ebc_boot_size = val & SDR0_SDSTP1_EBC_ROM_BS_MASK;

View File

@@ -1,142 +0,0 @@
/*
* (C) Copyright 2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
.resetvec 0xFFFFFFFC :
{
*(.resetvec)
} = 0xffff
.bootpg 0xFFFFF000 :
{
cpu/ppc4xx/start.o (.bootpg)
} = 0xffff
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text)
board/amcc/yucca/init.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
. = ALIGN(4);
}
_end = . ;
PROVIDE (end = .);
}

View File

@@ -32,6 +32,7 @@
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/4xx_pcie.h>
#include <asm/errno.h>
#include "yucca.h"
@@ -167,7 +168,7 @@ int board_early_init_f (void)
| 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
|
+-------------------------------------------------------------------*/
mtebc(xbcfg, EBC_CFG_LE_UNLOCK |
mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK |
EBC_CFG_PTD_ENABLE |
EBC_CFG_RTC_16PERCLK |
EBC_CFG_ATC_PREVIOUS |
@@ -188,8 +189,8 @@ int board_early_init_f (void)
| boot type
|
+-------------------------------------------------------------------*/
mtebc(pb1ap, EBC_BXAP_FPGA);
mtebc(pb1cr, EBC_BXCR_FPGA_CS1);
mtebc(PB1AP, EBC_BXAP_FPGA);
mtebc(PB1CR, EBC_BXCR_FPGA_CS1);
/*-------------------------------------------------------------------+
|
@@ -334,10 +335,10 @@ int board_early_init_f (void)
break;
}
mtebc(pb0ap, ebc0_cs0_bxap_value);
mtebc(pb0cr, ebc0_cs0_bxcr_value);
mtebc(pb2ap, ebc0_cs2_bxap_value);
mtebc(pb2cr, ebc0_cs2_bxcr_value);
mtebc(PB0AP, ebc0_cs0_bxap_value);
mtebc(PB0CR, ebc0_cs0_bxcr_value);
mtebc(PB2AP, ebc0_cs2_bxap_value);
mtebc(PB2CR, ebc0_cs2_bxcr_value);
/*--------------------------------------------------------------------+
| Interrupt controller setup for the AMCC 440SPe Evaluation board.
@@ -485,54 +486,54 @@ int board_early_init_f (void)
| interrupt trigger levels. Make bit 0 High priority. Clear all
| interrupts again.
+-------------------------------------------------------------------*/
mtdcr (uic3sr, 0xffffffff); /* Clear all interrupts */
mtdcr (uic3er, 0x00000000); /* disable all interrupts */
mtdcr (uic3cr, 0x00000000); /* Set Critical / Non Critical
mtdcr (UIC3SR, 0xffffffff); /* Clear all interrupts */
mtdcr (UIC3ER, 0x00000000); /* disable all interrupts */
mtdcr (UIC3CR, 0x00000000); /* Set Critical / Non Critical
* interrupts */
mtdcr (uic3pr, 0xffffffff); /* Set Interrupt Polarities */
mtdcr (uic3tr, 0x001fffff); /* Set Interrupt Trigger Levels */
mtdcr (uic3vr, 0x00000001); /* Set Vect base=0,INT31 Highest
mtdcr (UIC3PR, 0xffffffff); /* Set Interrupt Polarities */
mtdcr (UIC3TR, 0x001fffff); /* Set Interrupt Trigger Levels */
mtdcr (UIC3VR, 0x00000001); /* Set Vect base=0,INT31 Highest
* priority */
mtdcr (uic3sr, 0x00000000); /* clear all interrupts */
mtdcr (uic3sr, 0xffffffff); /* clear all interrupts */
mtdcr (UIC3SR, 0x00000000); /* clear all interrupts */
mtdcr (UIC3SR, 0xffffffff); /* clear all interrupts */
mtdcr (uic2sr, 0xffffffff); /* Clear all interrupts */
mtdcr (uic2er, 0x00000000); /* disable all interrupts */
mtdcr (uic2cr, 0x00000000); /* Set Critical / Non Critical
mtdcr (UIC2SR, 0xffffffff); /* Clear all interrupts */
mtdcr (UIC2ER, 0x00000000); /* disable all interrupts */
mtdcr (UIC2CR, 0x00000000); /* Set Critical / Non Critical
* interrupts */
mtdcr (uic2pr, 0xebebebff); /* Set Interrupt Polarities */
mtdcr (uic2tr, 0x74747400); /* Set Interrupt Trigger Levels */
mtdcr (uic2vr, 0x00000001); /* Set Vect base=0,INT31 Highest
mtdcr (UIC2PR, 0xebebebff); /* Set Interrupt Polarities */
mtdcr (UIC2TR, 0x74747400); /* Set Interrupt Trigger Levels */
mtdcr (UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest
* priority */
mtdcr (uic2sr, 0x00000000); /* clear all interrupts */
mtdcr (uic2sr, 0xffffffff); /* clear all interrupts */
mtdcr (UIC2SR, 0x00000000); /* clear all interrupts */
mtdcr (UIC2SR, 0xffffffff); /* clear all interrupts */
mtdcr (uic1sr, 0xffffffff); /* Clear all interrupts */
mtdcr (uic1er, 0x00000000); /* disable all interrupts */
mtdcr (uic1cr, 0x00000000); /* Set Critical / Non Critical
mtdcr (UIC1SR, 0xffffffff); /* Clear all interrupts */
mtdcr (UIC1ER, 0x00000000); /* disable all interrupts */
mtdcr (UIC1CR, 0x00000000); /* Set Critical / Non Critical
* interrupts */
mtdcr (uic1pr, 0xffffffff); /* Set Interrupt Polarities */
mtdcr (uic1tr, 0x001f8040); /* Set Interrupt Trigger Levels */
mtdcr (uic1vr, 0x00000001); /* Set Vect base=0,INT31 Highest
mtdcr (UIC1PR, 0xffffffff); /* Set Interrupt Polarities */
mtdcr (UIC1TR, 0x001f8040); /* Set Interrupt Trigger Levels */
mtdcr (UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest
* priority */
mtdcr (uic1sr, 0x00000000); /* clear all interrupts */
mtdcr (uic1sr, 0xffffffff); /* clear all interrupts */
mtdcr (UIC1SR, 0x00000000); /* clear all interrupts */
mtdcr (UIC1SR, 0xffffffff); /* clear all interrupts */
mtdcr (uic0sr, 0xffffffff); /* Clear all interrupts */
mtdcr (uic0er, 0x00000000); /* disable all interrupts excepted
mtdcr (UIC0SR, 0xffffffff); /* Clear all interrupts */
mtdcr (UIC0ER, 0x00000000); /* disable all interrupts excepted
* cascade to be checked */
mtdcr (uic0cr, 0x00104001); /* Set Critical / Non Critical
mtdcr (UIC0CR, 0x00104001); /* Set Critical / Non Critical
* interrupts */
mtdcr (uic0pr, 0xffffffff); /* Set Interrupt Polarities */
mtdcr (uic0tr, 0x010f0004); /* Set Interrupt Trigger Levels */
mtdcr (uic0vr, 0x00000001); /* Set Vect base=0,INT31 Highest
mtdcr (UIC0PR, 0xffffffff); /* Set Interrupt Polarities */
mtdcr (UIC0TR, 0x010f0004); /* Set Interrupt Trigger Levels */
mtdcr (UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest
* priority */
mtdcr (uic0sr, 0x00000000); /* clear all interrupts */
mtdcr (uic0sr, 0xffffffff); /* clear all interrupts */
mtdcr (UIC0SR, 0x00000000); /* clear all interrupts */
mtdcr (UIC0SR, 0xffffffff); /* clear all interrupts */
mfsdr(sdr_mfr, mfr);
mfsdr(SDR0_MFR, mfr);
mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */
mtsdr(sdr_mfr, mfr);
mtsdr(SDR0_MFR, mfr);
fpga_init();
@@ -587,98 +588,8 @@ u32 ddr_clktr(u32 default_val) {
return default_val;
}
/*************************************************************************
* pci_pre_init
*
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things. Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted.
*
* Different boards may wish to customize the pci controller structure
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller * hose )
{
unsigned long strap;
/*-------------------------------------------------------------------+
* The yucca board is always configured as the host & requires the
* PCI arbiter to be enabled.
*-------------------------------------------------------------------*/
mfsdr(sdr_sdstp1, strap);
if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ) {
printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
return 0;
}
return 1;
}
#endif /* defined(CONFIG_PCI) */
/*************************************************************************
* pci_target_init
*
* The bootstrap configuration provides default settings for the pci
* inbound map (PIM). But the bootstrap config choices are limited and
* may not be sufficient for a given board.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller * hose )
{
/*-------------------------------------------------------------------+
* Disable everything
*-------------------------------------------------------------------*/
out32r( PCIX0_PIM0SA, 0 ); /* disable */
out32r( PCIX0_PIM1SA, 0 ); /* disable */
out32r( PCIX0_PIM2SA, 0 ); /* disable */
out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
/*-------------------------------------------------------------------+
* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
* strapping options to not support sizes such as 128/256 MB.
*-------------------------------------------------------------------*/
out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
out32r( PCIX0_PIM0LAH, 0 );
out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
out32r( PCIX0_BAR0, 0 );
/*-------------------------------------------------------------------+
* Program the board's subsystem id/vendor id
*-------------------------------------------------------------------*/
out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
}
#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
#if defined(CONFIG_PCI)
/*************************************************************************
* is_pci_host
*
* This routine is called to determine if a pci scan should be
* performed. With various hardware environments (especially cPCI and
* PPMC) it's insufficient to depend on the state of the arbiter enable
* bit in the strap register, or generic host/adapter assumptions.
*
* Rather than hard-code a bad assumption in the general 440 code, the
* 440 pci code requires the board to decide at runtime.
*
* Return 0 for adapter mode, non-zero for host (monarch) mode.
*
*
************************************************************************/
int is_pci_host(struct pci_controller *hose)
{
/* The yucca board is always configured as host. */
return 1;
}
static int yucca_pcie_card_present(int port)
int board_pcie_card_present(int port)
{
u16 reg;
@@ -695,184 +606,55 @@ static int yucca_pcie_card_present(int port)
}
}
/*
* For the given slot, set rootpoint mode, send power to the slot,
* turn on the green LED and turn off the yellow LED, enable the clock
* and turn off reset.
*/
void yucca_setup_pcie_fpga_rootpoint(int port)
{
u16 power, clock, green_led, yellow_led, reset_off, rootpoint, endpoint;
switch(port) {
case 0:
rootpoint = FPGA_REG1C_PE0_ROOTPOINT;
endpoint = 0;
power = FPGA_REG1A_PE0_PWRON;
green_led = FPGA_REG1A_PE0_GLED;
clock = FPGA_REG1A_PE0_REFCLK_ENABLE;
yellow_led = FPGA_REG1A_PE0_YLED;
reset_off = FPGA_REG1C_PE0_PERST;
break;
case 1:
rootpoint = 0;
endpoint = FPGA_REG1C_PE1_ENDPOINT;
power = FPGA_REG1A_PE1_PWRON;
green_led = FPGA_REG1A_PE1_GLED;
clock = FPGA_REG1A_PE1_REFCLK_ENABLE;
yellow_led = FPGA_REG1A_PE1_YLED;
reset_off = FPGA_REG1C_PE1_PERST;
break;
case 2:
rootpoint = 0;
endpoint = FPGA_REG1C_PE2_ENDPOINT;
power = FPGA_REG1A_PE2_PWRON;
green_led = FPGA_REG1A_PE2_GLED;
clock = FPGA_REG1A_PE2_REFCLK_ENABLE;
yellow_led = FPGA_REG1A_PE2_YLED;
reset_off = FPGA_REG1C_PE2_PERST;
break;
default:
return;
}
out_be16((u16 *)FPGA_REG1A,
~(power | clock | green_led) &
(yellow_led | in_be16((u16 *)FPGA_REG1A)));
out_be16((u16 *)FPGA_REG1C,
~(endpoint | reset_off) &
(rootpoint | in_be16((u16 *)FPGA_REG1C)));
/*
* Leave device in reset for a while after powering on the
* slot to give it a chance to initialize.
*/
udelay(250 * 1000);
out_be16((u16 *)FPGA_REG1C, reset_off | in_be16((u16 *)FPGA_REG1C));
}
/*
* For the given slot, set endpoint mode, send power to the slot,
* turn on the green LED and turn off the yellow LED, enable the clock
* .In end point mode reset bit is read only.
* turn on the green LED and turn off the yellow LED, enable the
* clock. In endpoint mode reset bit is read only.
*/
void yucca_setup_pcie_fpga_endpoint(int port)
void board_pcie_setup_port(int port, int rootpoint)
{
u16 power, clock, green_led, yellow_led, reset_off, rootpoint, endpoint;
u16 power, clock, green_led, yellow_led,
reset_off, rp, ep;
switch(port) {
switch (port) {
case 0:
rootpoint = FPGA_REG1C_PE0_ROOTPOINT;
endpoint = 0;
power = FPGA_REG1A_PE0_PWRON;
green_led = FPGA_REG1A_PE0_GLED;
clock = FPGA_REG1A_PE0_REFCLK_ENABLE;
yellow_led = FPGA_REG1A_PE0_YLED;
reset_off = FPGA_REG1C_PE0_PERST;
rp = FPGA_REG1C_PE0_ROOTPOINT;
ep = 0;
break;
case 1:
rootpoint = 0;
endpoint = FPGA_REG1C_PE1_ENDPOINT;
power = FPGA_REG1A_PE1_PWRON;
green_led = FPGA_REG1A_PE1_GLED;
clock = FPGA_REG1A_PE1_REFCLK_ENABLE;
yellow_led = FPGA_REG1A_PE1_YLED;
reset_off = FPGA_REG1C_PE1_PERST;
rp = 0;
ep = FPGA_REG1C_PE1_ENDPOINT;
break;
case 2:
rootpoint = 0;
endpoint = FPGA_REG1C_PE2_ENDPOINT;
power = FPGA_REG1A_PE2_PWRON;
green_led = FPGA_REG1A_PE2_GLED;
clock = FPGA_REG1A_PE2_REFCLK_ENABLE;
yellow_led = FPGA_REG1A_PE2_YLED;
reset_off = FPGA_REG1C_PE2_PERST;
rp = 0;
ep = FPGA_REG1C_PE2_ENDPOINT;
break;
default:
return;
}
out_be16((u16 *)FPGA_REG1A,
~(power | clock | green_led) &
power = FPGA_REG1A_PWRON_ENCODE(port);
green_led = FPGA_REG1A_GLED_ENCODE(port);
clock = FPGA_REG1A_REFCLK_ENCODE(port);
yellow_led = FPGA_REG1A_YLED_ENCODE(port);
reset_off = FPGA_REG1C_PERST_ENCODE(port);
out_be16((u16 *)FPGA_REG1A, ~(power | clock | green_led) &
(yellow_led | in_be16((u16 *)FPGA_REG1A)));
out_be16((u16 *)FPGA_REG1C,
~(rootpoint | reset_off) &
(endpoint | in_be16((u16 *)FPGA_REG1C)));
}
out_be16((u16 *)FPGA_REG1C, ~(ep | reset_off) &
(rp | in_be16((u16 *)FPGA_REG1C)));
static struct pci_controller pcie_hose[3] = {{0},{0},{0}};
if (rootpoint) {
/*
* Leave device in reset for a while after powering on the
* slot to give it a chance to initialize.
*/
udelay(250 * 1000);
void pcie_setup_hoses(int busno)
{
struct pci_controller *hose;
int i, bus;
int ret = 0;
char *env;
unsigned int delay;
/*
* assume we're called after the PCIX hose is initialized, which takes
* bus ID 0 and therefore start numbering PCIe's from 1.
*/
bus = busno;
for (i = 0; i <= 2; i++) {
/* Check for yucca card presence */
if (!yucca_pcie_card_present(i))
continue;
if (is_end_point(i)) {
yucca_setup_pcie_fpga_endpoint(i);
ret = ppc4xx_init_pcie_endport(i);
} else {
yucca_setup_pcie_fpga_rootpoint(i);
ret = ppc4xx_init_pcie_rootport(i);
}
if (ret) {
printf("PCIE%d: initialization as %s failed\n", i,
is_end_point(i) ? "endpoint" : "root-complex");
continue;
}
hose = &pcie_hose[i];
hose->first_busno = bus;
hose->last_busno = bus;
hose->current_busno = bus;
/* setup mem resource */
pci_set_region(hose->regions + 0,
CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
CONFIG_SYS_PCIE_MEMSIZE,
PCI_REGION_MEM);
hose->region_count = 1;
pci_register_hose(hose);
if (is_end_point(i)) {
ppc4xx_setup_pcie_endpoint(hose, i);
/*
* Reson for no scanning is endpoint can not generate
* upstream configuration accesses.
*/
} else {
ppc4xx_setup_pcie_rootpoint(hose, i);
env = getenv("pciscandelay");
if (env != NULL) {
delay = simple_strtoul(env, NULL, 10);
if (delay > 5)
printf("Warning, expect noticable delay before "
"PCIe scan due to 'pciscandelay' value!\n");
mdelay(delay * 1000);
}
/*
* Config access can only go down stream
*/
hose->last_busno = pci_hose_scan(hose);
bus = hose->last_busno + 1;
}
out_be16((u16 *)FPGA_REG1C,
reset_off | in_be16((u16 *)FPGA_REG1C));
}
}
#endif /* defined(CONFIG_PCI) */
@@ -926,17 +708,6 @@ void fpga_init(void)
return;
}
#ifdef CONFIG_POST
/*
* Returns 1 if keys pressed to start the power-on long-running tests
* Called from board_init_f().
*/
int post_hotkeys_pressed(void)
{
return (ctrlc());
}
#endif
/*---------------------------------------------------------------------------+
| onboard_pci_arbiter_selected => from EPLD
+---------------------------------------------------------------------------*/

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