Between v2015.07-rc1 and v2015.07-rc2 this board started
silent boot failure. A bisect led to commit 6eed3786c6
("net: Move the CMD_NET config to defconfigs"). This commit
looks harmless in itself, but it did implicitly add a feature
to the image which led to this:
u-boot$git describe 6eed3786c6
v2015.07-rc1-412-g6eed3786c68c
^^^
u-boot$ls -l ../41*/u-boot.bin
-rwxrwxr-x 1 paul paul 261476 Oct 16 16:47 ../411/u-boot.bin
-rwxrwxr-x 1 paul paul 266392 Oct 16 16:43 ../412/u-boot.bin
u-boot$bc
bc 1.06.95
Copyright 1991-1994, 1997, 1998, 2000, 2004, 2006 Free Software Foundation, Inc.
This is free software with ABSOLUTELY NO WARRANTY.
For details type `warranty'.
256*1024
262144
i.e. we finally broke through the 256k monitor size. Jump it
up to 384k and fix the hard coded value used in the env offset
at the same time.
We were probably flirting with the 256k size issue without
knowing it when testing on different baselines in earlier
commits, but since this is all board specific, a rebase or
reorder to put this commit 1st is of little value.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
When debugging an env fail due to too small a malloc pool, it
was noted that the env write was 256k. But the device sector
size is 1/2 that, as can be seen from "fli" output:
Bank # 1: CFI conformant flash (16 x 16) Size: 16 MB in 131 Sectors
Intel Extended command set, Manufacturer ID: 0x89, Device ID: 0x1888
Erase timeout: 4096 ms, write timeout: 1 ms
Buffer write timeout: 2 ms, buffer size: 64 bytes
Sector Start Addresses:
FF000000 E RO FF020000 E RO FF040000 E RO FF060000 E RO FF080000 E RO
FF0A0000 E RO FF0C0000 E RO FF0E0000 E RO FF100000 E RO FF120000 E RO
[...]
FFF00000 RO FFF20000 RO FFF40000 RO FFF60000 RO FFF80000 RO
FFFA0000 RO FFFC0000 RO FFFE0000 E RO FFFE8000 RO FFFF0000 E RO
FFFF8000 RO
=>
The desired env sector is FFF40000->FFF60000, or 0x20000 in length,
just after the 256k u-boot image which starts @ FFF00000.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Currently the board fails to save its env, since the env size
is much smaller than the sector size, and the malloc fails for
the pad buffer, giving the user visible symptom of:
Unable to save the rest of sector (253952)
Allow for 1M malloc pool, the same as used on the sbc8548 board.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Used NAND chips requires at least 4-bit error correction, so use BCH8
as it is what kernel uses.
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Acked-by: Javier Martinez Canillas <javier@osg.samsung.com>
Juno R1 has an XpressRICH3 PCIe host bridge that needs to be initialised
in order for the Linux kernel to be able to enumerate the bus. Add
support code here that enables the host bridge, trains the links and
sets up the Address Translation Tables.
Signed-off-by: Liviu Dudau <Liviu.Dudau@foss.arm.com>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
[trini: Always declare vexpress64_pcie_init and continue handling logic
inside the function]
Signed-off-by: Tom Rini <trini@konsulko.com>
The dfu_alt_info_spl variable allows passing a starting point
for the binary to be flashed in the SPI NOR.
For example, if we have 'dfu_alt_info_spl=spl raw 0x400', this means
that we want to flash the binary starting at address 0x400.
In order to do so we need to erase the entire sector and write to
the the subsequent SPI NOR sectors taking such start address
into account for the address calculations.
Tested by succesfully writing SPL binary into 0x400 offset and
the u-boot.img at offset 64 kiB of a SPL NOR.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
[trini: Use lldiv for the math]
Signed-off-by: Tom Rini <trini@konsulko.com>
SPI NOR flashes need to erase the entire sector size and we cannot pass
any arbitrary length for the erase operation.
To illustrate the problem:
Copying data from PC to DFU device
Download [=========================] 100% 478208 bytes
Download done.
state(7) = dfuMANIFEST, status(0) = No error condition is present
state(10) = dfuERROR, status(14) = Something went wrong, but the
device does not know what it was
Done!
In this case, the binary has 478208 bytes and the M25P32 SPI NOR
has an erase sector of 64kB.
478208 = 7 entire sectors of 64kiB + 19456 bytes.
Erasing the first seven 64 kB sectors works fine, but when trying
to erase the remainding 19456 causes problem and the board hangs.
Fix the issue by always erasing with the erase sector size.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Upon further review when populating README.scrapyard, inetspace_v2_cmc
is a variant on netspace_v2 and not just an orphan config.
This reverts commit 653600a715.
Signed-off-by: Tom Rini <trini@konsulko.com>
Upon further review when populating README.scrapyard, d2net_v2 is a
variant on net2big_v2 and not just an orphan config. To help in the
future also add this to board/LaCie/net2big_v2/MAINTAINERS which needed
a little consolidation anyhow.
This reverts commit 1363740e79.
Cc: Simon Guinot <simon.guinot@sequanux.org>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Seen this one in the wild. Is labelled "Raspberry Pi Model A+ V1.1,
(C) Raspberry Pi 2014". A standard A+ board, much like the one with
version 0x12, didn't notice any differencies.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
The default dockstar configuration for U-Boot currently causes it to
overrun the environment area, so that a "saveenv" command bricks the
device. This patch moves the environment to a higher address to avoid
that.
Signed-off-by: Eric Cooper <ecc@cmu.edu>
On keystone2 Lamarr and Edison platforms, the PA clocksource
mux in PLL REG1, can be changed only after enabling its clock
domain.
So selecting the output of PASS PLL as input to PA only after
enabling the clockdomain.
This is as per the debug done by "Vitaly Andrianov <vitalya@ti.com>"
and based on the previous work done by "Hao Zhang <hzhang@ti.com>"
Fixes: d634a0775bcf ("ARM: keystone2: Cleanup PLL init code")
Reported-by: Vitaly Andrianov <vitalya@ti.com>
Tested-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
There are various toolchain issues that cause us to produce invalid
binaries with certain gcc 4.8.x and 4.9.x versions when we don't pass
this flag in.
Tested-by: Joakim Tjernlund <joakim.tjernlund@transmode.se>
Signed-off-by: Tom Rini <trini@konsulko.com>
We need "u-boot,dm-pre-reloc" in the socfpga_cyclone5_socdk.dts file in
order for the SPL to use SD/MMC.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Update the L2 AUX CTRL settings for the SoCFPGA.
Enabling D and I prefetch bits helps improve SDRAM performance on the
platform.
Also, we need to enable bit 22 of the L2. By not having bit 22 set in the
PL310 Auxiliary Control register (shared attribute override enable) has the
side effect of transforming Normal Shared Non-cacheable reads into Cacheable
no-allocate reads.
Coherent DMA buffers in Linux always have a Cacheable alias via the
kernel linear mapping and the processor can speculatively load cache
lines into the PL310 controller. With bit 22 cleared, Non-cacheable
reads would unexpectedly hit such cache lines leading to buffer
corruption.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
This commit fixes a typo in vf610twr DRAM init that was causing a hang in
U-Boot for the Vybrid Tower. This typo was introduced in commit 3f353cecc
(vf610: refactor DDRMC code).
Signed-off-by: Anthony Felice <tony.felice@timesys.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Add 'volatile' qualifier to the asm statement in get_cr()
so that the statement is not optimized out by the compiler.
(http://comments.gmane.org/gmane.linux.linaro.toolchain/5163)
Without the 'volatile', get_cr() returns a wrong value which
prevents enabling the MMU and later causes a PCIE VA access
failure.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
PCI driver currently hangs on mx6qp.
Toggle the reset bit with the appropriate timings to fix the issue.
Based on the FSL kernel driver implementation.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
For EL3 and EL2, the documentation says that bits 31 and 23 are reserved
but should be written as 1.
For EL1, only bit 23 is not reserved, so only write bit 31 as 1.
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Use the inner shareable attribute for memory, which makes more sense
considering that this code is called when caches are being enabled.
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Currently, the device tree relocation is disabled, likely to
keep some DDR3 RAM at the end for Cortex-M4 firmwares. This
can be archived using bootm_size, which limits the image
processing range of the boot commands.
Move the device tree standard load address to a higher address
which aligns better with what we are doing on other boards.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
Commit 3f353cecc ("vf610: refactor DDRMC code") changed the original
bstlen field from 3 to 0.
Restore the original value for proper behaviour.
Based on the patch from Anthony Felice <tony.felice@timesys.com>
for the vf610twr board.
Reported-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
This resyncs the driver changes with the Linux version of the
driver. The driver received some feedback in the LKML and got
recently acceppted, the latest version can be found here:
https://lkml.org/lkml/2015/9/2/678
Notable changes are:
- On ECC error, reread OOB and count bit flips in OOB too.
If flipped bits are below threshold, also return an empty
OOB buffer.
- Return the amount of bit flips in vf610_nfc_read_page.
- Use endianness aware vf610_nfc_read to read ECC status.
- Do not enable IDLE IRQ (since we do not operate with an
interrupt service routine).
- Use type safe struct for buffer variants (vf610_nfc_alt_buf).
- Renamed variables in struct vf610_nfc (column and page_sz)
to reflect better what they really representing.
The U-Boot version currently does not support RAW NAND write
when using the HW ECC engine.
Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Signed-off-by: Stefan Agner <stefan@agner.ch>
Tested-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
Tested-by: Stefan Agner <stefan@agner.ch>
Acked-by: Scott Wood <scottwood@freescale.com>
exynos_mmc_init() always returns zero, so for the caller
it looks like it never fails.
Correct this by returning the error code of process_nodes().
For process_nodes() do something similar and return early
when do_sdhci_init() fails.
v2: Only fail in process_nodes() if we fail on all
available nodes.
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
Signed-off-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Since commit 623d96e89aca6("imx: wdog: correct wcr register settings")
issuing a 'reset' command causes the system to hang.
Unlike i.MX and Vybrid, the watchdog controller on LS102x is big-endian.
This means that the watchdog on LS1021 has been working by accident as
it does not use the big-endian accessors in drivers/watchdog/imx_watchdog.c.
Commit 623d96e89aca6("imx: wdog: correct wcr register settings") only
revelead the endianness problem on LS102x.
In order to fix the reset hang, introduce a reset_cpu() implementation that
is specific for ls102x, which accesses the watchdog WCR register in big-endian
format. All that is required to reset LS102x is to clear the SRS bit.
This approach is a temporary workaround to avoid a regression for LS102x
in the 2015.10 release. The proper fix is to make the watchdog driver
endian-aware, so that it can work for i.MX, Vybrid and LS102x.
Reported-by: Sinan Akman <sinan@writeme.com>
Tested-by: Sinan Akman <sinan@writeme.com>
Reviewed-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Create fsl_wdog.h to store the watchdog registers and bit fields.
This can be useful when accesses to the watchdog block are made from other
parts, such as arch/arm/ cpu code.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
The changes in ed6a5d4 unintentionally broke support for reading the
environment saved to eeprom back. To correct this the crc-check and
decision on which environment to use is now moved to env_relocate_spec.
This is done for both the "redundant env" and the "single env" case.
Signed-off-by: Ludger Dreier <ludger.dreier@keymile.com>
MTD partitioning in current pcm052 configuration is inconsistent.
Fix it across MTDPARTS_DEFAULT, CONFIG_EXTRA_ENV_SETTINGS, and
CONFIG_ENV_OFFSET[_REDUND].
Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
With the changes in 7a3e70c we now get read(2) behavior so trying to
read 2MB with 1MB left in the file results in 1MB read and a warning.
We update the test logic here to make sure we read back 1MB as expected.
This change however changes the overall summary as while EXT4 continues
to not have offset support the test now fails when expected to pass
rather than fails when expected to fail (and we report that as pass).
Signed-off-by: Tom Rini <trini@konsulko.com>
Execution branches on feedback mode are swapped, this has no effect
if default direct mode is on (then p_div is equal to 1 and Fout equals
to Fcco), that's why the problem remained unnoticed for a long time.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
According to ARM PrimeCell PL175 documentation WAIT_OEN config value
is defined without any additional clocks added to the value set by a
client, the change fixes the wrong interface to WAIT_OEN config.
The change also touches a single user of LPC32xx EMC and corrects
configured "output enable delay" value on its side according to the
changed interface.
No functional change intended.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Messages on corrected bit-flips are not really useful,
as bit-flips are perfectly normal. Let's avoid cluttering
the console and make them debug.
Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
When building with SOURCE_DATE_EPOCH set, avoid use of mktime in
default_image.c, which converts the timestamp into localtime. This
causes variation based on timezone when building u-boot.img and
u-boot-sunxi-with-spl.bin targets.
Signed-off-by: Vagrant Cascadian <vagrant@debian.org>
Tested-by: Paul Kocialkowski <contact@paulk.fr>
Acked-by: Paul Kocialkowski <contact@paulk.fr>
In 2dd4632 the check for where a ramdisk is found on an Android image
was got moved into the "normal" loop here, causing people to have to
pass the kernel address in the ramdisk address location in order to have
Android boot still. This changed previous behavior so perform a check
early in the function to see if we have an Android image and if so use
that as where to look for the ramdisk (which is what the rest of the
code here expects). We allow for this to still be overridden with an
explicit ramdisk address to be passed as normal.
Cc: Rob Herring <robh@kernel.org>
Reported-by: Paul Kocialkowski <contact@paulk.fr>
Signed-off-by: Tom Rini <trini@konsulko.com>
We run 4 Arndale boards in our automated test framework, they have
been running quite happily for quite some time using a Debian Wheezy
userspace.
However when upgrading to a Debian Jessie we started seeing frequent
segmentation faults from gcc when building the kernel, to the extent
that it is unable to successfully build the kernel twice in a row, and
often fails on the first attempt.
Searching around I found https://bugs.launchpad.net/arndale/+bug/1081417
which pointed towards http://www.spinics.net/lists/kvm-arm/msg03723.html
and CPU Errata 773022 and 774769.
This errata needs to be applied to all processors in an SMP system,
meaning that the usual strategy of applying them in
arch/arm/cpu/armv7/start.S is not appropriate (since that applies to
the boot processor only). Instead we apply these errata in the secure
monitor which is code that is traversed by all processors as they are
brought up.
The net affect on Arndale is that ACTLR changes from 0x40 to
0x2000042. I ran 17 kernel compile iterations overnight with no
segfaults.
Runtime testing was done on our v2014.10 based branch and forward
ported (with only minimal and trivial contextual conflicts) to current
master, where it has been build tested only.
I suppose in theory these errata apply to any Exynos5250 based boards,
but Arndale is the only one I have access to and I have therefore
chosen to be conservative and only apply it there.
Also, reorder CONFIG_ARM_ERRATA_794072 in README to make the list
numerically sorted.
Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
If an Android boot image does not contain a ramdisk, make sure rd_len
and rd_data are returned to indicate no ramdisk rather than just relying
on returning an error.
Signed-off-by: Rob Herring <robh@kernel.org>
This patch adds support for LZ4-compressed FIT image contents. This
algorithm has a slightly worse compression ration than LZO while being
nearly twice as fast to decompress. When loading images from a fast
storage medium this usually results in a boot time win.
Sandbox-tested only since I don't have a U-Boot development system set
up right now. The code was imported unchanged from coreboot where it's
proven to work, though. I'm mostly interested in getting this recognized
by mkImage for use in a downstream project.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
Add CONFIG_SYS_GENERIC_BOARD to lwmon5.h and CONFIG_DISPLAY_BOARDINFO
to Kconfig file.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
This reverts commit 8fe11b8901.
I'll add support to lwmon5 in the next patch and will remove
support for the broken lcd4_lwmon5 as well.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Overwriting an empty file not created by U-Boot did not work, and it
could even corrupt the FAT. Moreover, creating empty files or emptying
existing files allocated a cluster, which is not standard.
Fix this by always keeping empty files clusterless as specified by
Microsoft (the start cluster must be set to 0 in the directory entry in
that case), and by supporting overwriting such files.
Signed-off-by: Benoît Thébaudeau <benoit@wsystem.com>
curclust was used instead of newclust in the debug() calls and in one
CHECK_CLUST() call, which could skip a failure case.
Signed-off-by: Benoît Thébaudeau <benoit@wsystem.com>
set_contents() had uselessly split calls to set_cluster(). Merge these
calls, which removes some cases of set_cluster() being called with a
size of zero.
Signed-off-by: Benoît Thébaudeau <benoit@wsystem.com>
set_cluster() was using a temporary buffer without enforcing its
alignment for DMA and cache. Moreover, it did not check the alignment of
the passed buffer, which can come directly from applicative code or from
the user.
This could cause random data corruption, which has been observed on
i.MX25 writing to an SD card.
Fix this by only passing ARCH_DMA_MINALIGN-aligned buffers to
disk_write(), which requires the introduction of a buffer bouncing
mechanism for the misaligned buffers passed to set_cluster().
By the way, improve the handling of the corresponding return values from
disk_write():
- print them with debug() in case of error,
- consider that there is an error is disk_write() returns a smaller
block count than the requested one, not only if its return value is
negative.
After this change, set_cluster() and get_cluster() are almost
symmetrical.
Signed-off-by: Benoît Thébaudeau <benoit@wsystem.com>
CONFIG_TWL4030_POWER is a boolean define variable. It is either defined
or not defined and should not have a value assigned to it.
Remove the value.
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
This patch changes the default "root=" parameter to "/dev/sda2".
Many linux based distros use /dev/sda1 for their boot partition; this is
often not a rootfs that can be used by the "root=" parameter.
Linaro images use /dev/sda1 as a boot partition, although this of a
different nature to a distro image. Linaro uses /dev/sda2 for the rootfs
partition.
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
The latest Juno firmware stores the files in NOR flash as "norkern" for
kernel binary, "board.dtb" for the device tree binary.
The "old" firmware used the name "Image" for the kernel binary and
"juno" for the device tree binary.
Rather than just change the default U-Boot configuration to use the new
names, breaking users with the old firmware, attempt to load the default
filename first. If that fails, attempt to load the alternate filename.
I've echo'd that we are loading the alternate file to counter the
output from "afs load" shown if the first load attempt fails. For
example, I see output like this on my Juno board when it's configured
the with the "old" firmware:
image "norkern" not found in flash
Loading Image instead of norkern
loaded region 0 from 08500000 to 80000000, 00AB6318 bytes
image "board.dtb" not found in flash
Loading juno instead of board.dtb
loaded region 0 from 0A000000 to 83000000, 00003188 bytes
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Some OS images require an initrd on Juno.
If the file ramdisk.img exists in NOR flash, then we load it and pass
the address to the kernel. Otherwise, we pass the "-" parameter as
before.
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Change the load_image so that it returns success or failure of the
command (using CMD_RET_SUCCESS or CMD_RET_FAILURE).
This way, hush scripts can optionally load different files depending
upon the system configuration.
A simple example:
if afs load ${kernel_name} ${kernel_addr}; then echo loaded; else echo \
not loaded; fi
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Add a command to the ARM flash support to check if an image exists or
not.
If the image is found, it will return CMD_RET_SUCCESS, else
CMD_RET_FAILURE. This allows hush scripts to conditionally load images.
A simple example:
if afs exists ${kernel_name}; then echo found; else echo \
not found; fi
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Linaro's Juno Android builds requires the androidboot.hardware parameter
be set to a know board name.
Non-Android kernels ignore this extra parameter because they don't
contain code to parse it.
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Create an additional FVP configuration to boot images pre-loaded into
DRAM.
Sometimes it's preferential to boot the model by loading the files
directly into DRAM via model parameters, rather than using
SemiHosting.
An example of model parmaters that are used to pre-load the files
into DRAM:
--data cluster0.cpu0=Image@0x80080000 \
--data cluster0.cpu0=fvp-base-gicv2-psci.dtb@0x83000000 \
--data cluster0.cpu0=uInitrd@0x84000000
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
[trini: Update board/armltd/vexpress64/Kconfig logic]
Signed-off-by: Tom Rini <trini@konsulko.com>
vexpress64 kernels are usually over 8 MBytes in length, so setting the
max uImage length to 64 Mbytes should give us plenty of scope for
expansion.
I mostly chose this length to match other board configs that use
"(64 << 20)".
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
The FVP and Juno settings were identical, but duplicated, so I removed
the duplication with this patch.
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
[trini: Adjust logic to keep if/endif in the file]
Signed-off-by: Tom Rini <trini@konsulko.com>
AT26DF081A is the spi flash type of TWR-MEM(SCH-26248) card.
We can access the flash through DSPI2 on LS1021ATWR board.
Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Erratum A-008022 has been fixed on LS1021A Rev2.0.
So we can use DSPI2 now, this patch enable DSPI2
in dts for LS1021ATWR.
Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
priv->mode is initialized when .set_speed triggers
with mode value, so checking mode for configuring
CPOL, CPHA using priv->mode is invalid hence use
mode from .set_speed argument, and at the end
priv->mode will initialized with mode.
This patch also replaces formatting string to use
speed instead of mode in .set_speed ops.
Signed-off-by: Jagan Teki <jteki@openedev.com>
priv->mode is initialized when .set_speed triggers
with mode value, so checking mode for configuring
CPOL, CPHA using priv->mode is invalid hence use
mode from .set_speed argument, and at the end
priv->mode will initialized with mode.
This patch also replaces formatting string to use
speed instead of mode in .set_speed ops.
Signed-off-by: Jagan Teki <jteki@openedev.com>
The pcDuino1 board unconditionally provides 5V to USB host
receptacles. The pcDuino2 board has a voltage regulator,
controlled by the PD2 pin which is pulled-up by default
(so that the USB power is also enabled by default).
Not specifying pins for enabling USB power in the defconfig
means that the PH3 and PH6 pins are driven high by default.
The PH6 pin is available on the Arduino-compatible expansion
header and touching it is not nice (this may be even dangerous,
depending on what kind of role is assigned to this particular
pin by various Arduino shields).
This patch explicitly configures the USB VBUS pins to "",
which means that no pins should be touched. The patch has
been tested on a pcDuino2 board and USB still works.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
PCI_HEADER_TYPE register (offset 0x0e) bit 7 is an indicator
for multi-function devices. We should mask it off before using
it as the header type.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
It turned out with some boards (FPGA firmwares?) and cards combos
current clock settings doesn't work as expected leading to strange
card freezes or corrupted data being read from the card.
Especially this was seen with Transcend 2Gb cards shipped as a part of
ARC SDP:
----------------->8---------------
AXS# mmcinfo
Device: Synopsys Mobile storage
Manufacturer ID: 74
OEM: 4a60
Name: SDC
Tran Speed: 50000000
Rd Block Len: 512
SD version 3.0
High Capacity: No
Capacity: 1.8 GiB
Bus Width: 4-bit
Erase Group Size: 512 Bytes
AXS# fatload mmc 0
** Unrecognized filesystem type **
----------------->8---------------
With this change that problem is fixed.
Note "Tran Speed" above doesn't match clock value set in DW MMC.
It is max value for card's speed class.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Currently 'reset' only works with the test device tree. When run without a
device tree, or with the normal device tree, the following error is
displayed:
Reset not supported on this platform
Fix the driver and the standard device tree to avoid this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
Adjust the memory leak tests to show the amount of memory leaked. This can
be a useful signal as to what is wrong.
Signed-off-by: Simon Glass <sjg@chromium.org>
Currently when driver model starts up it finds the root uclass and the
pinctrl uclass. This is because even the root node handles pinctrl
processing.
But this is not useful. The root node is not a real hardware device so
cannot require any particular pinmux settings. Also it means that the
memory leak tests fails, since they end up freeing more memory than
they allocate: the marker it set after the root device and pinctrl
uclass are allocated, and later once the pinctrl uclass is freed the memory
used by driver model is less than when the marker was set.
If a platform needs 'core' pin mulitplex settings it can do this with
a driver that is probed on start-up. It would be an abuse of the root node
to use this for pinctrl.
To avoid this problem, only process pinctrl settings for non-root nodes.
Signed-off-by: Simon Glass <sjg@chromium.org>
When malloc_base initially gets setup in the SPL it is based on the
current (early) stack pointer, which for rockchip is pointing into SRAM.
This means simple memory allocations happen in SRAM space, which is
somewhat unfortunate. Specifically a bounce buffer for the mmc allocated
in SRAM space seems to cause the mmc engine to stall/fail causing
timeouts and a failure to load the main u-boot image.
To resolve this, reconfigure the malloc_base to start at the relocated
stack pointer after DRAM has been setup.
For reference, things did work fine on rockchip before 596380db was
merged to fix memalign_simple due to a combination of rockchip SDRAM
starting at address 0 and the dw_mmc driver not checking errors from
bounce_buffer_start. As a result, when a bounce buffer needed to be
allocated mem_align simple would fail and return NULL. The mmc driver
ignored the error and happily continued with the bounce buffer address
being set to 0, which just happened to work fine..
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Simon Glass <sjg@chromium.org>
This device uses SDHCI driver, for eMMC and SD cards.
Trying bind the DW MMC driver with fdt node without all
required properties, causes printing an error.
This commit disables the DW MMC node.
Tested-on: Trats
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Łukasz Majewski <l.majewski@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
After rework of code by:
commit: d952796 Exynos5: Use clock_get_periph_rate generic API
function get_mmc_clk() always returns -1 for Exynos 4.
This was caused by omitting, that SDHCI driver for Exynos 4,
calls get_mmc_clk(), with mmc device number as argument,
instead of pinmux peripheral id, like DW MMC driver for Exynos 5.
By this commit, the code directly calls a proper function
to get mmc clock for Exynos 4, without checking the peripheral id.
Tested on: Odroid U3/X2, Trats, Trats2, Odroid XU3, Snow (by Simon).
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
After rework in lib/fdtdec.c, the function fdtdec_get_addr()
doesn't work for nodes with #size-cells property set to 0.
To get GPIO's 'reg' property, the code should use one of:
fdtdec_get_addr_size_auto_no/parent() function.
Fortunately dm core provides a function to get the property.
This commit reworks function gpio_exynos_bind(), to properly
use dev_get_addr() for GPIO device.
This prevents setting a wrong base register for Exynos GPIOs.
Tested on: Odroid U3/X2, Trats, Trats2, Odroid XU3, Snow (by Simon).
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
After rework of lib/fdtdec.c by:
commit: 02464e3 fdt: add new fdt address parsing functions
the function fdtdec_get_addr() doesn't work as previous,
because the implementation assumes that properties '#address-cells'
and '#size-cells' are equal to 1, which can be not true sometimes.
The new API introduced fdtdec_get_addr_size_auto_parent() for the 'reg'
property parsing, but the implementation assumes, that #size-cells
can't be less than 1.
This causes that the following children's 'reg' property can't be reached:
parent@0x0 {
#address-cells = <1>;
#size-cells = <0>;
children@0x100 {
reg = < 0x100 >;
};
};
Change the condition value from '1' to '0', which allows parsing property
with at least zero #size-cells, fixes the issue.
Now, fdtdec_get_addr_size_auto_parent() works properly.
Tested on: Odroid U3/X2, Trats, Trats2, Odroid XU3, Snow (by Simon).
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
fdtdec_get_addr_size() may be used in two cases:
a) With sizep supplied, in which case both an address and a size are
parsed from DT. In this case, the DT property must be large enough to
contain both values.
b) With sizep NULL, in which case only an address is parsed from DT.
In this case, the DT property only need be large enough to contain this
address value. Commit 02464e386b "fdt: add new fdt address parsing
functions" broke this relaxed checking, and required the DT property to
contain both an address and a size value in all cases.
Fix fdtdec_get_addr_size() to vary ns based on whether the size value
is being parsed from the DT or not. This is safe since the function only
parses the first entry in the property, so the overall value of (na + ns)
need not be accurate, since it is never used to step through the property
data to find other entries. Besides, this fixed behaviour essentially
matches the original behaviour before the patch this patch fixes. (The
original code validated that the property was exactly the length of
either na or (na + ns), whereas the current code only validates that the
property is at least that long. For non-failure cases, the two behaviours
are identical).
Cc: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Thierry Reding <treding@nvidia.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Michal Suchanek <hramrach@gmail.com>
Fixes: 02464e386b ("fdt: add new fdt address parsing functions")
Reported-by: Przemyslaw Marczak <p.marczak@samsung.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
This comment from README.fdt-control did not end up in the Kconfig, which
is what most people will see. Add it with a few tweaks.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Michal Simek <michal.simek@xilinx.com>
The 7" Q8 tablet enclosure is used for a ton of slightly different cheap
chinese tablets. There are some differences in which accelerometer /
wifi is used, but other then that these are all the same from a u-boot /
kernel pov.
When we get to adding accelerometer support the plan is to add some kind
of autodetection and mangle the dt accordingly (likely using the new quirks
mechanism).
For now this is a non issue as we do not yet have accelerometer
support, and in the future, some sort of auto-detect is the way to go
as we cannot expect users to exactly know what is inside their tablet.
The dts files this commit adds are identical to the ones submitted
to the upstream kernel.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
In order to make it clear what the parameters to set_config() and
set_direction() mean, and similarly for the return values from the
respective get_*(), define named constants for these values.
Disassembly shows no diff in the generated code, except that the
order of the code in the branches of tegra_gpio_get_function() gets
modified without affecting behaviour.
Suggested-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The size allocation for SPL is increased in all cases to match the
already-expanded value used on Tegra124. This is both for general
consistency, and because the seaboard build trips over the limit already
when using one of the ARM compilers packaged with 14.04. For the record,
when building Seaboard:
arm-linux-gnueabi- SPL is too big by 0x36 bytes
arm-linux-gnueabihf- SPL fits by 0x2a bytes
arm-none-eabi- SPL fits by 0xa bytes
(Those figures are from builds with the expanded SPL size allocation,
relative to the non-expanded SPL size limit; they're better by about
6 bytes in the more constrained build.)
Fixes: ba52199422 ("tegra124: Expand SPL space by 8KB")
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Tegra's GPIO driver currently enables pins as GPIO as soon as they're
requested. This is not safe, since the desired direction and output value
are not yet known. This could cause a glitch on the output pins between
gpio_request() and gpio_direction_*(), depending on what values happen to
be in the GPIO controller's in/out and out-value registers vs. the final
desired configuration.
To solve this, defer enabling pins as GPIOs until some gpio_direction_*()
is invoked, and the desired configuration is explicitly programmed.
In theory this change could cause regressions, if code exists that claims
a GPIO, never explicitly sets a direction, and then gets/sets the GPIO
value based on that assumption. However, I've read through all the Tegra-
related board files and device drivers that touch GPIOs and I do not see
such buggy code anywhere.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Tegra's gpio_config_table() currently uses common GPIO APIs. These used
to work without requesting the GPIO, but since commit 2fccd2d96b "tegra:
Convert tegra GPIO driver to use driver model" no longer do so. This
prevents any of the GPIO initialization table from being applied to HW.
Fix gpio_config_table() to directly program the HW to solve this.
Fixes: 2fccd2d96b ("tegra: Convert tegra GPIO driver to use driver model")
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
In order to avoid any assumptions about any device connected to
P2371-2180's expansion connector, the latest pinmux spreadsheet
configures all muxable pins on that connector to be GPIO inputs, with
on-chip pulls where appropriate.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add DFU support.
Tested by flashing SPL and u-boot.img into SPI NOR flash with the
following commands:
=> setenv dfu_alt_info ${dfu_alt_info_spl}
=> run dfuspi
On the host PC:
$ sudo dfu-util -D SPL -a spl
On the target:
CTRL+C
=> setenv dfu_alt_info ${dfu_alt_info_img}
=> run dfuspi
On the host PC:
$ sudo dfu-util -D u-boot.img -a u-boot
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
The driver assumed that I2C1 and I2C2 were always enabled,
and if they were not, then an asynchronous abort was (silently)
raised, to be caught much later on in the Linux kernel.
Fix this by making I2C1 and I2C2 optional just like I2C3 and I2C4
are.
To make the change binary-invariant, declare I2C1 and I2C2 in
every include/configs/ file which defines CONFIG_SYS_I2C_MXC.
Also, while updating README about CONFIG_SYS_I2C_MXC_I2C1 and
CONFIG_SYS_I2C_MXC_I2C2, add missing descriptions for I2C4 speed
(CONFIG_SYS_MXC_I2C4_SPEED) and slave (CONFIG_SYS_MXC_I2C4_SLAVE)
config options.
Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
The VF610 DDRMC driver code contains settings which are
board-specific. Move these out to boards so that new boards
can define their own without having to modify the driver.
Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
Set missing boot address in bootm command. This fixes the error:
Wrong Image Format for bootm command
ERROR: can't get kernel image!
Reported-by: Uwe Scheffler <scheffler.u@web.de>
Signed-off-by: Soeren Moch <smoch@web.de>
Tested-by: Uwe Scheffler <scheffler.u@web.de>
We should follow 'read->set/clr bit->write' flow for enable_fec_anatop_clock,
otherwise we may overridden configuration before enable_fec_anatop_clock.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Cc: Fabio Estevam <fabio.estevam@freescale.com>
If defined CONFIG_ENV_IS_IN_MMC, then u-boot environment is saved in
mmc's raw sectors. Otherwise, u-boot environment is saved as a file:
uboot.env.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Reviewed-by: Bo Shen <voice.shen@gmail.com>
Currently, kwboot only allows dynamic UART boot mode patching for SoCs
with header version 0 (Orion, Kirkwood). This patch now enables this "-p"
feature also for SoCs with header version 1 (Armada XP / 38x etc). With
this its possible now to use the UART boot mode without on images that
are generated for other boot devices, like SPI. So no need to change
BOOT_FROM to "uart" for UART xmodem booting any more.
Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Dirk Eibach <eibach@gdsys.de>
As reported by Simon Guinot, commit ade741b3
"arm: mvebu: Call timer_init early before PHY and DDR init" breaks
Kirkwood platforms. As the static variable "init_done" is not
available at that early boot time. This patch moves it to explicitly
to the data section, making it available at that time.
Signed-off-by: Stefan Roese <sr@denx.de>
Reported-by: Simon Guinot <simon.guinot@sequanux.org>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Tested-by: Simon Guinot <simon.guinot@sequanux.org>
Currently booting on A38x is broken. As the current code tries to detect
the SoC family to disable the MMU for the A38x at runtime. But before the
internal registers are switched to the new location (0xf100.0000), this
runtime detection does not work. As all macros / defines are already
assigned to the new location at 0xf100.0000. But the registers are sill
mapped to the default location at 0xd000.0000.
This patch now makes sure, no such runtime detection is used before
the internal registers are configured to the new location. After this,
the remaining cache cleanup is executed.
Signed-off-by: Stefan Roese <sr@denx.de>
Reported-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Simon Glass and Joe Hershberger suggested adding at least one
test case for the CONFIG_DM_ETH plus CONFIG_NETCONSOLE options.
This patch enables NetConsole as a default for the "Banana Pi/Pro"
sunxi boards.
(By the nature of this patch it could probably be extended later
to include all sunxi boards using CONFIG_SUNXI_[EG]MAC.)
Signed-off-by: Bernhard Nortmann <bernhard.nortmann@web.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This patch introduces CONFIG_NETCONSOLE as an option to the
Kconfig system.
Joe Hershberger pointed out that it may not be entirely free of
problems, as many boards predating the driver model define this
symbol directly via include files. In case they're not properly
migrated, their NetConsole might 'vanish' if they start to use
CONFIG_NET or CONFIG_NETDEVICES.
Signed-off-by: Bernhard Nortmann <bernhard.nortmann@web.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
CONFIG_NETCONSOLE causes common/bootm.c to call eth_unregister()
for network device shutdown. However, with CONFIG_DM_ETH this
function is no longer defined.
This is a workaround to avoid the call in that case, and solely
rely on eth_halt(). In case this is insufficient, a proper way
to unregister / remove network devices needs to be implemented.
Signed-off-by: Bernhard Nortmann <bernhard.nortmann@web.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This patch uses the eth_is_active() function to work around
issues that prevented compilation with the newer driver model.
Signed-off-by: Bernhard Nortmann <bernhard.nortmann@web.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The previous eth_device struct returned by eth_get_dev() allowed
code to directly query the state member field. However, with
CONFIG_DM_ETH this data gets encapsulated (i.e. private), and
eth_get_dev() returns a udevice struct 'abstraction' instead.
This breaks legacy code relying on the former behaviour - e.g.
netconsole.
(see http://lists.denx.de/pipermail/u-boot/2015-June/216528.html)
The patch introduces a method to retrieve the ethernet device
state in a 'clean' and uniform way, supporting both legacy code
and driver model. The new function eth_is_active() accepts a
device struct pointer and tests it for ETH_STATE_ACTIVE.
Signed-off-by: Bernhard Nortmann <bernhard.nortmann@web.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Currently when phy device is created the link variable is
initialized to 1 which denoted phy link is already up. On a power
reset there is no issue as phy status register link status will
not be set, so phy auto negotiate will be started. But when a cpu
reset is issued (ex: dra72x-evm) phy's link status bit is already
set which leads to assume that link is already setup in
genphy_update_link() initial check which results in ehternet not
working. So do not assume that link is already up and on phy
device create set link to zero. This is verified on dra72x-evm.
Reported-by: Franklin S Cooper Jr <fcooper@ti.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The 7" Q8 tablet enclosure is used for a ton of slightly different cheap
chinese tablets. There are some differences in which accelerometer /
wifi is used, but other then that these are all the same from a u-boot /
kernel pov.
When we get to adding accelerometer support the plan is to add some kind
of autodetection and mangle the dt accordingly (likely using the new quirks
mechanism).
For now this is a non issue as we do not yet have accelerometer
support, and in the future, some sort of auto-detect is the way to go
as we cannot expect users to exactly know what is inside their tablet.
The dts[i] files this commit adds are identical to the ones submitted
to the upstream kernel.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
In recent allwinner kernel sources the mmc/sdio clk-delay settings have
been slightly tweaked, and for sun9i they are completely different then
what we are using.
This commit brings us in sync with what allwinner does, fixing problems
accessing sdcards on some A33 devices (and likely others).
For pre sun9i hardware this makes the following changes:
-At 400Khz change the sample delay from 7 to 0 (first introduced in A31 sdk)
-At 50 Mhz change the sample delay from 5 to 4 (first introduced in A23 sdk)
-Above 50 MHz change the out delay from 2 to 1 (first introduced in A20 sdk)
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
We know when u-boot is written to its own partition, in this case the
layout always is:
eb 0 spl
eb 1 spl-backup
eb 2 u-boot
eb 3 u-boot-backup
eb: erase-block
So if we cannot load u-boot from its primary offset we know exactly where
to look for it.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
This patch makes use of the previous changes to add a new "fel" boot
target for sunxi boards.
When booting via FEL, it's often desirable to work around the absence
of other (usable) boot devices - or to be able to override them,
deviating from the standard boot sequence. To achieve this, the "fel"
boot target gets the highest priority, but won't actually do anything
unless certain criteria are met.
The "bootcmd_fel" implementation proposed here first tests if an actual
FEL boot takes place (using the "fel_booted" env var), and secondly
checks that "fel_scriptaddr" was set (originating from the 'loader',
i.e. the sunxi-tools fel utility). If both checks pass, then it will
try to execute the boot script (boot.scr) at the given address. In case
of an error (e.g. an invalid image), the source command might return
"false", causing "distro_bootcmd" to proceed with the next boot target.
Signed-off-by: Bernhard Nortmann <bernhard.nortmann@web.de>
Acked-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
This patch extends the misc_init_r() function on sunxi boards
to test for the presence of a suitable "sunxi" SPL header. If
found, and the loader ("fel" utility) provided a non-zero value
for the boot.scr address, then the corresponding environment
variable fel_scriptaddr gets set.
misc_init_r() also sets (or clears) the "fel_booted" variable depending
on the active boot device, using the same logic as spl_boot_device().
The goal is to provide sufficient information (within the U-Boot
environment) to make intelligent decisions on how to continue the boot
process, allowing specific customizations for the "FEL boot" case.
Signed-off-by: Bernhard Nortmann <bernhard.nortmann@web.de>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
This patch follows up on a discussion of ways to improve support
for the sunxi FEL ("USB boot") mechanism, especially with regard
to boot scripts, see:
https://groups.google.com/d/msg/linux-sunxi/wBEGUoLNRro/rHGq6nSYCQAJ
The idea is to convert the (currently unused) "pad" bytes in the
SPL header into an area where data can be passed to U-Boot. To
do this safely, we have to make sure that we're actually using
our "sunxi" flavor of the SPL, and not the Allwinner boot0.
The modified mksunxiboot introduces a special signature to the
SPL header in place of the "pub_head_size" field. This can be
used to reliably distinguish between compatible versions of sunxi
SPL and anything else (older variants or Allwinner's boot0).
Signed-off-by: Bernhard Nortmann <bernhard.nortmann@web.de>
Acked-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The sunxi platform currently doesn't seem to make any use of the
asm/arch-sunxi/spl.h file. This patch moves some declarations from
tools/mksunxiboot.c into it.
This enables us to reuse those definitions when extending the
sunxi board code (boards/sunxi/boards.c).
Signed-off-by: Bernhard Nortmann <bernhard.nortmann@web.de>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
crt0.S will both memset the bss sectioan and call board_init_r for us,
so there is no need to do either ourselves.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
For the upcoming nand support we need a bigger heap, esp. ubi[fs] uses
quite a bit of memory, increase the heap size to 64 MB.
Our video code returns unused reserved framebuffer memory to the kernel
before booting it. Drop the #ifdef-ery and simply always reserve 16 MB.
Adjust bootm_size for the above changes.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Move some #define-s around from one #ifdef block to another to
reduce the number of #ifdef blocks (note this causes no functional
changes even though the conditions are not always exactly the same)
and move generic #include statements to the top.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
We only prefix the board defconfig name with the SoC if the SoC is part
of the official board-name, such as with Olimex OLinuxIno boards, for the
Wobo i5 this is not the case so remove the A10s prefix from the defconfig
filename.
Also fix the double listing of A10s-OLinuXino-M_defconfig in MAINTAINERS
which the original Wobo i5 addition commit introduced.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The logic to calculate the number of E820 table entries is wrong
when walking through the FSP HOB tables. Fix it.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Jian Luo <jian.luo4@boschrexroth.de>
Acked-by: Simon Glass <sjg@chromium.org>
Now that PCI bridges are probed before relocation we need additional memory.
Each PCI bridge takes 240 bytes at present since it uses the same uclass as
the PCI controller. Probably we should split this out so that bridges have
their own uclass.
Expand the memory on link so that it works correctly.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The commit: d9dbb97be0
"mmc: dw_mmc: Zap endless timeout" removed endless loop waiting for end
of dw mmc transfer.
For some workloads - dfu test @ Odroid XU3 (sending 8MiB file) -
and SD cards (e.g. MicroSD Kingston 4GiB, Adata 4GiB)
the default timeout is to short.
The new value - 4 minutes (240 seconds) - is the same as the one used in
Linux kernel driver. Such fix should be good enough until we come up
with better fix for this issue.
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Tom Rini <trini@konsulko.com>
Tested-by: Przemyslaw Marczak <p.marczak@samsung.com>
As 'time(0) | getpid()' will have a lot of duplicated value. It is not a
expected behavior. We expect different value for the seed when when run
it in many times.
So this patch will left shift the getpid() and add to time(0). That
avoid duplicated value.
Test command is like:
% RUN=0; while [ $RUN -lt 10000 ]; do
tools/gen_eth_addr; RUN=$(($RUN+1)); done | sort | uniq | wc -l
10000
This patch is incorporated with suggestions made by Wolfgang Denk and Andreas
Bießmann. Thanks them a lot.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
Acked-by: Wolfgang Denk <wd@denx.de>
Tested-by: Wolfgang Denk <wd@denx.de>
DRAM region 0x3f000000 - 0x3fffffff is reserved for OP-TEE. Touching
0x3f000000 memory location from unsecure world causes the board
to hang.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Use DM for the pl01x serial driver on hikey. Also allow UART0 or
UART3 to be chosen via Kconfig.
By default we now output to UART3 as the latest version of ATF outputs
to this UART. Also UART3 comes out on the LS connector, as opposed to
UART0 which goes to a unpopulated header.
As part of this change we also enable CONFIG_BOARD_EARLY_INIT_F and
call the pinmux configuration code for the UART. Before we were
relying on ATF having already configured the pin configuration.
NB: Upstream Linux kernel doesn't yet support UART3, so serial console
will still be output on UART0 when booting a upstream kernel.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Most platforms enable these options from Kconfig rather
than the configs header file.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
This causes exceptions and other strange behaviour
when enabling CONFIG_SYS_MALLOC_F_LEN which is required to
migrate the serial driver over to DM_SERIAL.
As GD_FLG_FULL_MALLOC_INIT flag gets reset, after relocation
we don't end up using the full malloc which ultimately ends up
causing a synchronus abort.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Use the #defines in linux/sizes for malloc size as it is
more readable.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Rather than relying on an external URL in the README
include the Makefile in the hikey directory.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
The README had a few mistakes, and one of the URL's
had changed. Also update the boot log with the latest
boot trace from ATF, which now includes the mcuimage.bin.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
The gd->malloc_ptr and the gd->malloc_limit are offsets to gd->malloc_base.
But the addr variable contains the absolute address. The new_ptr must be:
addr + bytes - gd->malloc_base.
Signed-off-by: Philipp Rosenberger <ilu@linutronix.de>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
When AM437x EVM is connected to Gigabit switch, it takes
more time to finish auto-negotiation than on a 10/100 switch.
The default 4 second limit times-out more often than not. This is
observed when testing with a D-Link DGS-1008A desktop switch.
Increase the auto-negotiation time-out for AM437x EVM to handle
this case.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Currently, the USB boot mode is supported by an external loader and
U-boot proper image is put on the section 0. This commit allows
access there.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The DDR SDRAM initialization code has not been mainlined yet, but
U-Boot proper should work.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The DDR SDRAM initialization code has not been mainlined yet, but
U-Boot proper should work.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Before this commit, the Kconfig menu in mach-uniphier only allowed us
to choose one SoC to be compiled. Each SoC has its own defconfig file
for the build-test coverage. Consequently, some defconfig files are
duplicated with only the difference in CONFIG_DEFAULT_DEVICE_TREE and
CONFIG_{SOC_NAME}=y.
Now, most of board-specific parameters have been moved to device trees,
so it makes sense to include init code of multiple SoCs into a single
image as long as the SoCs have similar architecture. In fact, some
SoCs of UniPhier family are very similar:
- PH1-LD4 and PH1-sLD8
- PH1-LD6b and ProXstream2 (will be added in the upcoming commit)
This commit will be helpful to merge some defconfig files for better
maintainability.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Currently, console=ttyS0 is hard-coded in CONFIG_EXTRA_ENV_SETTINGS
and it replaces the bootargs in the chosen node of the device tree
passed to the kernel. This is not preferable because I am going to
add some boards whose console is not ttyS0.
Drop bootargs settings from U-Boot's environment and use the one in
device tree by default.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Move init code of low-level debug into a single file.
This is helpful to create an image that runs on multiple SoCs.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Currently, IECTRL is enabled after pin-mux settings for the low-level
debugging for PH1-LD4 and PH1-sLD8. While IECTRL is disabled, input
signals are pulled-down, i.e. glitch signal (Low to High transition)
problem occurs if pin-mux is set up first. As a result, one invalid
character is input to the UART block and the auto-boot counting is
terminated immediately.
The correct initialization procedure is:
[1] Enable IECTRL (if IECTRL exists for the pins)
[2] Set up pin-muxing
[3] Deassert the reset of the hardware block
Currently, the low-level debugging is working for PH1-sLD3 and
PH1-Pro4, but just in case, follow the sequence for all the SoCs.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
I want these prefixed with CONFIG_ARCH_UNIPHIER_ to clarify
they belong to UniPhier SoC family.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
It is no longer necessary to define CONFIG_SUPPORT_CARD_* globally.
Move them to a C file as local macros. Also, rename the C file.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The macro, led_write(), is now only used in C sources. There is no
more reason to keep the tricky assembly macro. Replace it with a
new C function led_puts().
Also, rename board.h to micro-support-card.h.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The wrapper functions, uniphier_board_*, are just making function
calls complex. Remove them.
Also, use empty inline functions in case CONFIG_MICRO_SUPPORT_CARD
is disabled, so that prototype checking works.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Device tree specifies the available memory ranges in its "/memory"
node. Use it to simplify the CONFIG defines.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
To achieve the complete run-time configuration by device trees, ifdef
conditionals in header files are not preferable.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
In UniPhier SoCs before ProXstream2 and PH1-LD6b, two address spaces
0x00000000 - 0x0fffffff
0x40000000 - 0x4fffffff
are both mapped to the external bus (also called system bus),
so either was OK.
In the newest two SoCs, the former (0x00000000 - 0x0fffffff) is
assigned for the serial NOR interface.
Going forward, use the latter for the external bus.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Historically (for compatibility with very old platforms), two
different types of micro support cards have been used with the
UniPhier SoC development boards. It has been painful to maintain
both. Having one of them is enough.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
These input enable settings are handled by the pinctrl drivers.
Because the external bus pins are input-enabled by default, on-board
devices such as LED still work fine even with this delayed input
enabling.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
As the UniPhier serial driver had already switched to Drive Model
and the pinctrl drivers are now enabled, these pin-muxing settings
are properly handled by the pinctrl drivers.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add "u-boot,dm-pre-reloc" for device nodes we want in SPL DTB
(spl/u-boot-spl.dtb).
The "soc" node (this is simple-bus node) also needs the property
to bind the pinctrl node located under it.
I am collecting this U-Boot specific hack to the bottom of board
DTS rather than inserting "u-boot,dm-pre-reloc" into SoC DTSI.
My goal is to sync DTSI with Linux for easier maintenance.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
In the next commit, I will add "u-boot,dm-pre-reloc" to the "soc"
(simple-bus) nodes in UniPhier device trees. But, before that,
CONFIG_SYS_MALLOC_F_LEN must be increased.
Adding "u-boot,dm-pre-reloc" to a simple-bus node causes it to bind
all of its child nodes. (See simple_bus_post_bind() function)
Actually, I want only UART0 and pinctrl to be bound in SPL and before
relocation in U-boot proper. But, with "u-boot,dm-pre-reloc" in the
simple-bus node, all the other unwanted nodes are also bound. The
default value for CONFIG_SYS_MALLOC_F_LEN, 0x400, is not enough for
that. Increase the pre-reloc malloc size to 0x2000, hoping the root
cause will be fixed later.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
In UniPhier device trees, pinctrl device nodes are located under the
simple-bus (AMBA).
This is needed to bind pinctrl devices in SPL.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
We use outer pmic reset and drop internal reset signal, bmode will
not work as expected, so drop boot mode code for 7dsabresd board.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Adrian Alonso <aalonso@freescale.com>
boot_mode_apply should be applied only with CONFIG_CMD_BMODE enabled.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Add MAINTAINERS info for mx6slevk_spl, mx6ul_9x9_evk and mx6qpsabreauto.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Some i.MXes use __NA_ or 0 to avoid setting mux_mode, but the following patch
only take i.MX6/7 into consideration.
"c3c8a5748897b24f18618047804317167a531dd3 imx-common: fix iomux settings"
Use is_soc_type(MXC_CPU_MX7) to avoid breaking other i.MXes when
setting mux_mode.
In this patch, switch to use "asm/imx-common/sys_proto.h" to avoid
build break for "is_soc_type" for vf610 and mx25.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
commit "arm: socfpga: rename socfpga_cyclone5 and socfpga_arria5 config files"
renames the configs files, so we should update the MAINTAINERS' entry. At
the same time, update the email for Dinh Nguyen.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Rename the socfpga_cyclone5.h to socfpga_cyclone5_socdk.h, and
socfpga_arria.h to socfpga_arria5_socdk.h. This matches the other SoCFPGA
board config files.
Suggested-by: Marek Vasut <marex@denx.de>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
By not defining CONFIG_SYS_ARM_CACHE_WRITEALLOC, the WRITEBACK cache
policy is selected. This leads to much better performance on the SoCFPGA.
A quick network test shows this:
Without this patch:
=> tftp 100000 big-40mb
Speed: 1000, full duplex
Using dwmac.ff702000 device
TFTP from server 192.168.1.54; our IP address is 192.168.1.252
Filename 'big-40mb'.
Load address: 0x100000
Loading: #################################################################
#################################################################
#################################################################
#################################################################
##########################
2.5 MiB/s
With this patch:
=> tftp 100000 big-40mb
Speed: 1000, full duplex
Using dwmac.ff702000 device
TFTP from server 192.168.1.54; our IP address is 192.168.1.252
Filename 'big-40mb'.
Load address: 0x100000
Loading: #################################################################
#################################################################
#################################################################
#################################################################
##########################
7.6 MiB/s
A performance improvement of factor ~3.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Marek Vasut <marex@denx.de>
The command:
ethsw [port <port_no>] ingress filtering
{ [help] | show | enable | disable }
- enable/disable VLAN ingress filtering on port
can be used to enable/disable/show VLAN ingress filtering on a port.
This command has also been added to the ethsw generic parser
from common/cmd_ethsw.c
Signed-off-by: Johnson Leung <johnson.leung@freescale.com>
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>
The command:
ethsw vlan fdb { [help] | show | shared | private }
- make VLAN learning shared or private"
configures the FDB to share the FDB entries learned on multiple VLANs
or to keep them separated. By default, the FBD uses private VLAN
learning. This command has also been added to the ethsw generic parser
from common/cmd_ethsw.c
Signed-off-by: Johnson Leung <johnson.leung@freescale.com>
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>
The new added commands can be used to configure VLANs for a port
on both ingress and egress.
The new commands are:
ethsw [port <port_no>] pvid { [help] | show | <pvid> }
- set/show PVID (ingress and egress VLAN tagging) for a port;
ethsw [port <port_no>] vlan { [help] | show | add <vid> | del <vid> }
- add a VLAN to a port (VLAN members);
ethsw [port <port_no>] untagged { [help] | show | all | none | pvid }
- set egress tagging mod for a port"
ethsw [port <port_no>] egress tag { [help] | show | pvid | classified }
- Configure VID source for egress tag. Tag's VID could be the
frame's classified VID or the PVID of the port
These commands have also been added to the ethsw generic parser from
common/cmd_ethsw.c
Signed-off-by: Johnson Leung <johnson.leung@freescale.com>
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>
The new command:
ethsw [port <port_no>] [vlan <vid>] fdb
{ [help] | show | flush | { add | del } <mac> }
Can be used to add and delete FDB entries. Also, the command can be used
to show entries from the FDB tables. When used with [port <port_no>]
and [vlan <vid>], only the matching the FDB entries can be seen or
flushed. The command has also been added to the generic ethsw parser
from cmd_ethsw.c.
Signed-off-by: Johnson Leung <johnson.leung@freescale.com>
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>
The code that checks if a string has the format of a MAC address has been
moved to a separate function called eth_validate_ethaddr_str().
This has been done to allow other components (such as vsc9953 driver)
to validate a MAC address.
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>
The command:
ethsw [port <port_no>] learning { [help] | show | auto | disable }
can be used to enable/disable HW learning on a port.
This patch also adds this command to the generic ethsw parser from
cmd_ethsw.
Signed-off-by: Johnson Leung <johnson.leung@freescale.com>
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>
The new added command:
ethsw [port <port_no>] statistics { [help] | [clear] }
will print counters like the number of Rx/Tx frames,
number of Rx/Tx bytes, number of Rx/Tx unicast frames, etc.
This patch also adds this commnd in the genereric ethsw
parser from cmd_ethsw.c
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This patch replaces the parser used by VSC9953 L2 Switch driver with
the generic one. Also, the config macro that enables the
VSC9953 commands has been replaced in all the platforms that
use this driver with the config macro that corresponds to the
generic parser.
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This patch creates a flexible parser for Ethernet Switch
configurations that should support complex commands.
The parser searches for predefined keywords in the command
and calls the proper function when a match is found.
Also, the parser allows for optional keywords, such as
"port", to apply the command on a port
or on all ports. For now, the defined commands are:
ethsw [port <port_no>] { enable | disable | show }
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
At startup, the default configuration should be:
- enable HW learning on all ports (HW default);
- all ports are VLAN aware;
- all ports are members of VLAN 1;
- all ports have Port-based VLAN 1;
- on all ports, the switch is allowed to remove
maximum one VLAN tag,
- on egress, the switch should add a VLAN tag if the
frame is classified to a different VLAN than the port's
Port-based VLAN;
Signed-off-by: Johnson Leung <johnson.leung@freescale.com>
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>
These new operations allow manipulation of bitfields
within a word by using a mask instead of width and
shift values to extract/replace the bitfields.
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>
When a port is enabled at init time, the initializing function
touches more bits than necessary to enable a port (also touches
reserved bits and default bit values). This patch fixes this issue
by changing the value of the define used to enable the port and
assures that no other bits are changes by replacing out_le32()
with setbits_le32().
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This patch groups some macros defined for registers and
replaces some magic numbers from vsc9953 with macros. Also,
"port" and "port_nr" words are replaced with "port_no",
puts each variable declaration on a line and removes
unnecessary tabs.
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>
We have defined this kconfig entry in arch/arm/cpu/armv7/mx7/Kconfig,
no need to redefine it in board Kconfig.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
drop select CPU_V7 for board target, since ARCH_MX7 selects CPU_V7.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
get_board_rev() is not actually providing the board revision.
It just returns the CPU revision instead.
As the CPU revision is already printed on boot, there is no
reason to have get_board_rev(), so let's remove it.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
get_board_rev() is not actually providing the board revision.
It just returns the CPU revision instead.
As the CPU revision is already printed on boot, there is no
reason to have get_board_rev(), so let's remove it.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Include <usb/ehci-fsl.h> in order to fix the following sparse warning:
board/freescale/mx7dsabresd/mx7dsabresd.c:538:5: warning: symbol 'board_ehci_hcd_init' was not declared. Should it be static?
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
When setting iomux for a pin mux, there is no need to check mux_ctrl_ofs.
Also If still checking mux_ctrl_ofs, we have no chance to set iomux
for i.MX7D IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO00, because the mux_ctrl_ofs
for this register is 0.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
Commit c5acf4a2b3 ("pinctrl: Add the concept of peripheral IDs")
added some additional change that was not mentioned in the git-log.
That commit added dm_scan_fdt_node() in the pinctrl uclass binding.
It should be handled by the simple-bus driver or the low-level
driver, not by the pinctrl framework.
I guess Simon's motivation was to bind GPIO banks located under the
Rockchip pinctrl device. It is true some chips have sub-devices
under their pinctrl devices, but it is basically SoC-specific matter.
This commit partly reverts commit c5acf4a2b3 to keep the only
pinctrl-generic features in the uclass. The dm_scan_fdt_node()
should be called from the rk3288_pinctrl driver.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Quark SoC does not support MSR MTRRs. Fixed and variable range MTRRs
are accessed indirectly via the message port and not the traditional
MSR mechanism. Only UC, WT and WB cache types are supported.
We configure all the fixed range MTRRs with common values (VGA RAM
as UC, others as WB) and 3 variable range MTRRs for ROM/eSRAM/RAM as
WB, which significantly improves the boot time performance.
With this commit, it takes only 2 seconds for U-Boot to boot to shell
on Intel Galileo board. Previously it took about 6 seconds.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Desktop Management Interface (DMI) is not supported by U-Boot now.
Add it to the TODO list.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Document porting considerations for Intel Quark based board,
including MRC parameters and PCIe initialization.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Now we have enabled PCIe root port on Quark SoC, add its PIRQ
routing information in the device tree as well.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Thermal sensor on Quark SoC needs to be properly initialized per
Quark firmware writer guide, otherwise when booting Linux kernel,
it triggers system shutdown because of wrong temperature in the
thermal sensor is detected by the kernel driver (see below):
[ 5.119819] thermal_sys: Critical temperature reached(206 C),shutting down
[ 5.128997] Failed to start orderly shutdown: forcing the issue
[ 5.135495] Emergency Sync complete
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
When Linux kernel boots, it hangs at:
[ 0.829408] Intel Quark side-band driver registered
This happens when Quark kernel Isolated Memory Region (IMR) driver
tries to lock an IMR register to protect kernel's text and rodata
sections. However in order to have IMR function correctly, HMBOUND
register must be locked otherwise the system just hangs.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Change existing codes to use clrbits, setbits, clrsetbits macros.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
On Intel Quark, lots of registers on the message port need be
programmed. Add handy clrbits, setbits, clrsetbits macros for
message port access.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Not like other Intel Ethernet controllers (e.g.: E1000), Intel Quark
SoC integrated designware Ethernet controller does not have a chipset
defined way to store/restore mac address. Enable random mac address
so that we can use Ethernet even without 'ethaddr'.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
This adds static register programming for PCIe and USB after memory
init as required by Quark firmware writer guide. Although not doing
this did not cause any malfunction, just do it for safety.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Convert to use DM version of Designware ethernet driver on Intel
quark/galileo.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
The Designware ethernet controller is also seen on PCI bus, e.g.
on Intel Quark SoC. Add this support in the DM version driver.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Introduce device_is_on_pci_bus() which can be utilized by driver
to test if a device is on a PCI bus.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Enabling a PLL while IDDQ is high. The Linux kernel checks for this
condition and warns about it verbosely, so while this seems to work
fine, fix it up according to the programming guidelines provided in
the Tegra K1 TRM (v02p), Section 5.3.8.1 ("PLLC and PLLC4 Startup
Sequence"). The Tegra114 TRM doesn't contain this information, but
the programming of PLLC is the same on Tegra114 and Tegra124.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Enabling a PLL while IDDQ is high. The Linux kernel checks for this
condition and warns about it verbosely, so while this seems to work
fine, fix it up according to the programming guidelines provided in
the Tegra K1 TRM (v02p), Section 5.3.8.1 ("PLLC and PLLC4 Startup
Sequence").
Reported-by: Nicolas Chauvet <kwizart@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The counter frequency is derived from clk_m on Tegra, but that clock can
be configured by the primary bootloader to run at the same frequency as
the oscillator (38.4 MHz on Tegra210) or a divided down frequency (most
typically 19.2 MHz). Remove the hard-coded frequency and allow the timer
setup code to query the correct value at runtime.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The counter frequency is derived from clk_m on Tegra, but that clock can
be configured by the primary bootloader to run at the same frequency as
the oscillator (38.4 MHz on Tegra210) or a divided down frequency (most
typically 19.2 MHz). Remove the hard-coded frequency and allow the timer
setup code to query the correct value at runtime.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The counter frequency is derived from clk_m on Tegra, but that clock can
be configured by the primary bootloader to run at the same frequency as
the oscillator (38.4 MHz on Tegra210) or a divided down frequency (most
typically 19.2 MHz). Remove the hard-coded frequency and allow the timer
setup code to query the correct value at runtime.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
While clk_m and the oscillator run at the same frequencies on Tegra114
and Tegra124, clk_m is the proper source for the architected timer. On
more recent Tegra generations, Tegra210 and later, both the oscillator
and clk_m can run at different frequencies. clk_m will be divided down
from the oscillator.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
On currently supported SoCs, clk_m always runs at the same frequency as
the oscillator input. However newer SoC generations such as Tegra210 no
longer have that restriction. Prepare for that by separating clk_m from
the oscillator clock and allow SoC code to override the clk_m rate.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Some platforms have the means to determine the counter frequency at
runtime, so give them an opportunity to do so.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Commit 181bd9dc61 "kconfig: add config option for shell prompt" replaced
define V_PROMPT with Kconfig option SYS_PROMPT. This crossed with patches
adding Tegra T210 boards. Migrate the boards to the new scheme.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
AFAIK, for all PLLs on all Tegra SoCs, the primary PLL output frequency
is (input * m) / (n * p). However, PLLP's primary output (pllP_out0) on
T210 is the VCO output, and divp is not applied. pllP_out2 does have divp
applied. All other pllP_outN are divided down from pllP_out0. We only
support pllP_out0 in U-Boot at the time of writing.
Fix clock_get_rate() to handle this special case.
This corrects the returned rate for PLLP to be 408MHz rather than 204MHz.
In turn, this causes high enough dividers to be calculated for the various
peripheral clocks that feed off of PLLP. Without this, some peripherals
failed to operate correctly. For instance, one of my SD cards worked
perfectly but an older (presumably slower) card could not be read.
Note that prior to commit 722e000ccd "Tegra: PLL: use per-SoC pllinfo
table instead of PLL_DIVM/N/P, etc.", the calculated PLL frequency was
816MHz since the wrong values were being extracted from the PLLP divider
register. This caused overly large peripheral dividers to be calculated,
which while wrong, didn't cause any correctness issues; things simply ran
slower than they could.
Reported-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
While T210 boards all have 38.4MHz crystals, per the TRM, the only
supported configuration is to divide the crystal frequency by 2 to
generate clk_m, which is what feeds the ARM generic timers amongst other
things. Fix the value of COUNTER_FREQUENCY to reflect this divide-by-2.
When I queried the 19.2 value in Tom's original T210 patches, I wasn't
aware of this extra divide-by-2, and didn't notice any effect from the
incorrect value, since its only used if U-Boot is booted in EL3, whereas
I'm booting it in EL2.
Reported-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
P2371-2180 is a P2180 CPU board married to a P2597 I/O board. The
combination contains SoC, DRAM, eMMC, SD card slot, HDMI, USB
micro-B port, Ethernet via USB3, USB3 host port, SATA, PCIe, and
two GPIO expansion headers.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The clear_config() is called just once at the beginning of this
program, but the global variable hashtab[] is already zero-filled
at the start-up.
[ Linux commit: d179e22762fd38414c4108acedd5feca4cf7e0d8 ]
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Michal Marek <mmarek@suse.com>
When enabling CONFIG_API and chain-loading GRUB2 on jetson-tk1, only the
eMMC would show up as (hd0), but not the SD card, leading to GRUB not
finding its configuration and modules, falling back to a rescue shell.
This is because enum_ended would get set for !more after returning a
cookie for the first MMC device in group 3.
Fix this by properly setting the "more" argument also in the case of the
first storage device of a group.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Commit 0abdd9d0 "arm: Remove nhk8815 boards and nomadik arch" missed one
reference to this arch. Lets remove this as well.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
This arch does not seem to be supported / used at all in the current
U-Boot mainline source tree any more. So lets remove the core u8500 code
and code that was only referenced by this platform.
Please note that this patch also removes these config options:
- CONFIG_PL011_SERIAL_RLCR
- CONFIG_PL011_SERIAL_FLUSH_ON_INIT
As they only seem to be referenced by u8500 based boards. Without any
such board in the current code, these config option don't make sense
any more. Lets remove them as well.
If someone still wants to use this platform, then please send patches
to re-enable support by adding at least one board that references this
code.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: John Rigby <john.rigby@linaro.org>
Cc: Simon Glass <sjg@chromium.org>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This patch addresses some comments raised by Scott in the last versions.
Here the changes in detail:
- Removed __maybe_unused as its not needed
- Added check for strength == 4 and error out for the unsupported
ECC strength values
- Don't set .caclulate, .correct, and .bytes for NAND_ECC_SOFT_BCH as this
will be done in nand_scan_tail()
- Set .caclulate back to fsmc_read_hwecc() in the HW case
- Added comment that this function will only be called on SPEAr platforms,
not supporting the BCH8 HW ECC (FSMC_VER8)
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Tom Rini <trini@konsulko.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Lets consider following scenario:
- One uses echo -n "key=value" to define environment variable in a file (single variable)
- The file content is "key=value" without any terminating byte (e.g. 0x0a or
0x0d).
- The file is loaded to u-boot non zero'ed RAM buffer (with load command).
- Then "env import -t -r $loadaddr $filesize" is executed.
- Due to lack of proper termination byte we have classical example of buffer
overrun.
This patch prevents from this by allocating one extra byte than size and
explicitly null terminate it.
There should be no change for normal env import operation after applying
this patch.
Signed-off-by: Lukasz Majewski <l.majewski@majess.pl>
Bigger source buffer than dest buffer could overflow when copying
strings. Source and destination buffer sizes are same now.
Signed-off-by: Imran Zaman <imran.zaman@intel.com>
Take over maintainership as well. Not tested as PG2.0 (which I have)
needs additional work over PG1.0 (which Matt has).
Cc: Matt Porter <mporter@konsulko.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
fdtdec_get_addr_size() hard-codes the number of cells used to represent
an address or size in DT. This is incorrect in many cases depending on
the DT binding for a particular node or property (e.g. it is incorrect
for the "reg" property). In most cases, DT parsing code must use the
properties #address-cells and #size-cells to parse addres properties.
This change splits up the implementation of fdtdec_get_addr_size() so
that the core logic can be used for both hard-coded and non-hard-coded
cases. Various wrapper functions are implemented that support cases
where hard-coded cell counts should or should not be used, and where
the client does and doesn't know the parent node ID that contains the
properties #address-cells and #size-cells.
dev_get_addr() is updated to use the new functions.
Core functionality in fdtdec_get_addr_size_fixed() is widely tested via
fdtdec_get_addr_size(). I tested fdtdec_get_addr_size_auto_noparent() and
dev_get_addr() by manually modifying the Tegra I2C driver to invoke them.
Much of the core implementation of fdtdec_get_addr_size_fixed(),
fdtdec_get_addr_size_auto_parent(), and
fdtdec_get_addr_size_auto_noparent() comes from Thierry Reding's
previous commit "fdt: Fix fdtdec_get_addr_size() for 64-bit".
Based-on-work-by: Thierry Reding <treding@nvidia.com>
Cc: Thierry Reding <treding@nvidia.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Michal Suchanek <hramrach@gmail.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Dropped #define DEBUG at the top of fdtdec.c:
Signed-off-by: Simon Glass <sjg@chromium.org>
On the LaCie boards netspace_max_v2 and net2big_v2, two internal hard
drives are available. Additionally on the d2net_v2 board, an extra hard
drive can be plugged via eSATA.
This patch updates CONFIG_SYS_IDE_MAXBUS and CONFIG_SYS_IDE_MAXDEVICE
accordingly for this boards.
Signed-off-by: Simon Guinot <simon.guinot@sequanux.org>
This patch enables generic board support for the following
Kirkwood-based LaCie boards:
- Network Space v2 (Mini, Lite and Max).
- Internet Space v2.
- D2 Network v2.
- 2Big Network v2.
Signed-off-by: Simon Guinot <simon.guinot@sequanux.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
We should not return 0 on failure, so return a negative error code
instead.
Also centralize the error path so that is easier to follow.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
We should not return 0 on failure, so return a negative error code
instead.
Also centralize the error path so that is easier to follow.
Cc: Markus Niebel <Markus.Niebel@tq-group.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
We should not return 0 on failure, so return a negative error code
instead.
Also centralize the error path so that is easier to follow.
Cc: Christian Gmeiner <christian.gmeiner@gmail.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Entering the maximum number of characters defined by CONFIG_SYS_CBSIZE into
the console and hitting enter afterwards, causes a hang in the system because
CONFIG_SYS_PBSIZE is not capable of storing the extra characters of the error
message:
"Unknown command '' - try 'help'".
Use the default CONFIG_SYS_PBSIZE definition from config_fallbacks.h to solve
this problem.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
CONFIG_SYS_GENERIC_BOARD is selected by mx6_common.h, so there is no
need to define it locally.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Peng Fan <Peng.Fan@freescale.com>
CONFIG_CMD_FUSE and CONFIG_MXC_OCOTP are selected by mx6_common.h,
so there is no need to define them locally.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
If the SD card does not contain the u-boot.img then we get the
following error:
U-Boot SPL 2015.10-rc2-23947-g7ad5930 (Sep 08 2015 - 14:10:29)
** Partition 1 not valid on device 0 **
spl_register_fat_device: fat register err - -1
spl_load_image_fat: error reading image u-boot.img, err - -1
Remove CONFIG_SPL_FAT_SUPPORT and let CONFIG_SPL_MMC_SUPPORT do the
job.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
If the SD card does not contain the u-boot.img then we get the
following error:
U-Boot SPL 2015.10-rc2-23947-g7ad5930 (Sep 08 2015 - 14:10:29)
** Partition 1 not valid on device 0 **
spl_register_fat_device: fat register err - -1
spl_load_image_fat: error reading image u-boot.img, err - -1
Remove CONFIG_SPL_FAT_SUPPORT and let CONFIG_SPL_MMC_SUPPORT do the
job.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
If the SD card does not contain the u-boot.img then we get the
following error:
U-Boot SPL 2015.10-rc2-23947-g7ad5930 (Sep 08 2015 - 14:10:29)
** Partition 1 not valid on device 0 **
spl_register_fat_device: fat register err - -1
spl_load_image_fat: error reading image u-boot.img, err - -1
Remove CONFIG_SPL_FAT_SUPPORT and let CONFIG_SPL_MMC_SUPPORT do the
job.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
It is not very useful to have the message below on every boot
(especially when we are using early silicon):
U-Boot 2015.10-rc2-23945-g37cf215 (Sep 08 2015 - 14:12:14 -0300)
CPU: Freescale i.MX6UL rev1.0 792 MHz (running at 396 MHz)
CPU: Commercial temperature grade (0C to 95C)CPU: Thermal invalid data, fuse: 0x0
- invalid sensor device
, so turn the error message into debug level.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
It is not very useful to have the message below on every boot
(especially when we are using early silicon):
U-Boot 2015.10-rc2-23945-g37cf215 (Sep 08 2015 - 14:12:14 -0300)
CPU: Freescale i.MX6UL rev1.0 792 MHz (running at 396 MHz)
CPU: Commercial temperature grade (0C to 95C)CPU: Thermal invalid data, fuse: 0x0
- invalid sensor device
, so turn the error message into debug level.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Discard the 'select CPU_V7' from Kconfig in arch/arm/cpu/armv7/mx6
for different targets, because ARCH_MX6 selects CPU_V7.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Old revisions of Utilite (a miniature PC based on cm-fx6) do not have
a card detect for mmc, and thus the kernel needs to be told that
there's a persistent storage on usdhc3 to force it to probe the mmc
card.
Check the baseboard revision and modify the device tree accordingly
if needed.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
cl_eeprom_read_mac_addr() doesn't differentiate between success case and
inability to access eeprom. Fix this by propagating the return value of
cl_eeprom_setup().
Cc: Stefano Babic <sbabic@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
This patch is to support mx6ul_9x9_evk board based on mx6ul_14x14_evk,
the difference between mx6ul 9x9 evk and mx6ul 14x14 evk are:
1. mx6ul 9x9 evk use pfuze3000, while mx6ul 14x14 evk use DCDC.
2. mx6ul 9x9 evk supports 256MB LPDDR2, while mx6ul 14x14 evk
supports 512MB DDR3
3. mx6ul_9x9_evk use 9x9 package, while mx6ul_14x14_evk use 14x14 package.
This patch add the following:
1. Discard PHYS_SDRAM_SIZE from header file, use imx_ddr_size()
2. Introduce a macro is_mx6ul_9x9_evk using
CONFIG_IS_ENABLED(TARGET_MX6UL_9X9_EVK) to avoid "#ifdef xxx" in non-SPL
part. To SPL part, CONFIG_IS_ENABLED(TARGET_MX6UL_9X9_EVK) can not work,
so still use "#ifdef CONFIG_TARGET_MX6UL_9X9_EVK" to differentiate with
mx6ul_14x14_evk. And we have no way to dymaically checking this chip
is 9x9 or 14x14.
3. mx6ul_9x9_evk use pfuze3000, so enabled POWER related configurations.
POWER related configurations also effect for mx6ul_14x14_evk. But
power_init_board implementation using 'if (is_mx6ul_9x9_evk())' to
do initialization for mx6ul_9x9_evk, and do nothing for mx6ul_14x14_evk.
4. mx6ul_9x9_evk use lpddr2 with size 256MB, so add related SPL DRAM
configurations.
5. Enable CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG and setting dtb file
according to board_rev and board_name.
6. Add TARGET_MX6UL_9X9_EVK Kconfig entry
Boot Log:
U-Boot SPL 2015.10-rc2-00356-g536ce34 (Sep 06 2015 - 12:22:53)
reading u-boot.img
reading u-boot.img
U-Boot 2015.10-rc2-00356-g536ce34 (Sep 06 2015 - 12:22:53 +0800)
CPU: Freescale i.MX6UL rev1.0 792 MHz (running at 396 MHz)
CPU: Commercial temperature grade (0C to 95C) at 41C
Reset cause: POR
Board: MX6UL 9x9 EVK
I2C: ready
DRAM: 256 MiB
PMIC: PFUZE3000 DEV_ID=0x30 REV_ID=0x11
MMC: FSL_SDHC: 0, FSL_SDHC: 1
In: serial
Out: serial
Err: serial
Net: FEC1
Hit any key to stop autoboot: 0
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
This reverts commit 059323fb6a8f21637bb617919715c2427f24777c.
This commit 059323fb6a8f21637bb617919715c2427f24777c use JESD79-3E which
is not the newest spec. Should use JESD79-3F in which tRFC is 260ns for
4Gb chip.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Running mxsboot on a big-endian system produces a sd image which
cannot be started by the i.MX28 ROM. It complains on the debug
uart as following:
0x8020a009
0x80502008
0x8020a009
0x80502008
...
Enforcing all fields within the BCB to little-endian make
the image bootable again.
Signed-off-by: Michael Heimpold <mhei@heimpold.de>
Acked-by: Stefano Babic <sbabic@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
Add imx-common cpu support for imx7d SoC
- Update reset_cause for imx7d
- Enable watchdog driver built for imx7d
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Extend init_aips to support imx7 SoC, use is_soc_type
and is_cpu_type to resolve at run time aips3 settings
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
* Add Clock control module (CCM) support
* iMX7D SoC introduces 3 main clock sysmtem abstraction for clock
root frequency generation denominated clock slices.
Core clock slice: hihg speed clock for ARM core
Bus clock slice: for bus clocks
IP clock slice: Peripheral clocks
* At system boot ROM enables PLL_ARM, PLL_DDR, PLL_SYS, PLL_ENET
In u-boot, we have to:
- Configure PFD3- PFD7 for freq we needed in u-boot
- Set clock root for peripherals (ip channel)
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
* Add system arch level header files
- imx-regs.h: iMX7D SoC system architecture registers
- crm_regs.h: Clock control module registers
- sys_proto.h: helper callback function for SoC setup
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
Add system counter driver for imx7d and mx6ul
imx7 and imx6ul supports system counter timer as well as
GPT timer (arch/arm/imx-common/timer.c); The default for
imx7 is systemcounter timer.
Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Move common imx6 arch init setup, init.c can be extended
and reused to support imx7 SoC keeping init arch common
code.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Rework cache settings for imx6, move cache configuration
to imx-common/cache.c so it can be reused for newer SoC
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Rework imx_thermal driver to be used across i.MX
processor that support thermal sensor
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
The MCV SoM has DDR3-1600 DRAMs on it, update the DRAM speed
to 400MHz to make use of these DRAMs completely.
Signed-off-by: Marek Vasut <marex@denx.de>
Commit 6a13241635 "ci_udc: Update the ci_udc driver to support bulk
transfers" caused the value of "len" to change without updating subsquent
users of that variable in ci_ep_submit_next_request(). This caused the
code that detects when to emit ZLPs (Zero Length Packets) never to
trigger, which in turn caused host timeouts when a ZLP was required,
which in turn broke tests/dfu/, even despite the assertion in that
commit's description that "These changes are tested for both the DFU and
lthor."
Fix this by modifying the added dtd iteration code not to modify "len",
but rather to keep state in a separate variable. Rename the variables
while we're at it so they describe their purpose better.
Fixes: 6a13241635 ("ci_udc: Update the ci_udc driver to support bulk transfers")
Cc: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Implement endpoint dequeue callback function.
Without this function, uboot will hang when executing fastboot comamnd.
See following flow:
"fastboot_tx_write_str->fastboot_tx_write->usb_ep_dequeue->ep->ops->dequeue"
without implement ci_udc dequeue function, ep->ops->dequeue is NULL, then
uboot will hang.
Tested on mx6qsabresd board with fastboot enabled.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
Cc: "Łukasz Majewski" <l.majewski@samsung.com>
Cc: Marek Vasut <marex@denx.de>
>From source code comments:
"x0: 0 flush & invalidate, 1 invalidate only"
Current value 0xffff can make invalidate work, since we only judge whether
input value is 0 or not, see following code:
"
tbz w1, #0, 1f
dc isw, x9
b 2f
1: dc cisw, x9 /* clean & invalidate by set/way */
2: subs x6, x6, #1 /* decrement the way */
"
Later we may add "2 clean only" support. So following the comments,
correct value from 0xffff to 1.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: York Sun <yorksun@freescale.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
The current comments need a bit of tweaking since we now support stack
and global_data relocation in SPL. Also add a reference to the README.
For AArch64 this is not implemented, so leave a TODO for this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Tim Harvey <tharvey@gateworks.com>
The current simplify lpc32xx gpio driver implementation assume a
maximum of 32 GPIO per port; there are a total of 22 GPI, 24 GPO
and 6 GPIO to managed on port 3.
Update the driver to fix the following:
1) When requesting GPI_xx and GPO_xx on port 3 (xx is the same number)
the second call to "gpio_request" will return -EBUSY.
2) The status of GPO_xx pin report the status of the
corresponding GPI_xx pin when using the "gpio status" command.
3) The gpio driver may setup the direction register for the wrong
gpio when calling "gpio_direction_input" (GPI_xx) or
"gpio_direction_output" (GPO_xx) on port 3; the call to the
direction is require to use the "gpio status" command.
The following change were done in the driver:
1) port3 GPI are cache in a separate 32 bits in the array.
2) port3 direction register written only for GPIO pins.
3) port3 GPO & GPIO (as output) are read using "p3_outp_state".
4) LPC32XX_GPI_P3_GRP updated to match the change.
Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
Mainline CM-T3517 U-Boot environment size differs from that one
shipped with CM-T3517 boards.
Update environment size, to avoid backward compatibility issues.
Signed-off-by: Dmitry Lifshitz <lifshitz@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
SBC-T3517 evaluation board has two Eth interfaces.
Enable network retry of another interface if the default if failed
or disconnected.
Add 'netretry=yes' in the default env. Setup relevant
timeout values in the board config file.
Signed-off-by: Dmitry Lifshitz <lifshitz@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
introduce BIT() definition, used in at91_udc gadget
driver.
Signed-off-by: Heiko Schocher <hs@denx.de>
[remove all other occurrences of BIT(x) definition]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: Anatolij Gustschin <agust@denx.de>
Since last API changes for files >2GB, the read of symlink is broken as
ext4fs_read_file now returns 0 instead of the length of the actual read.
Signed-off-by: Gary Bisson <gary.bisson@boundarydevices.com>
This patch changes a little bit the environment, current environment was broken
for a long time, and board don't as expected sometimes, on production systems
this is fixed adding boot script. I think it's time to change this to make a
system conformant environment and use generic distro configurations and
environment instead. We can use a boot script for the old way boot mode.
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Add support for Lightwriter SL50 series board, a small, robust and portable
Voice Output Communication Aids (VOCA) designed to meet the particular and
changing needs of people with speech loss resulting from a wide range of
acquired, progressive and congenital conditions.
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
This allows transferring data directly to/from RAM. For example, one
could create a boot script that starts DFU on a RAM region, then once
DFU exits (which is under the control of the attached USB host, via a
USB bus reset), uses the code/data that was received over DFU.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Writing to files is a useful feature in general, so enable it everywhere.
The primary purpose is to make DFU useful on filesystems in addition to
raw devices.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
CONFIG_SYS_DFU_DATA_BUF_SIZE defines the size of chunks transferred
across USB. This doesn't need to be particularly large, since it doesn't
limit the overall transfer size.
CONFIG_SYS_DFU_MAX_FILE_SIZE is used to buffer an entire file before
writing it to a filesystem. This define limits the maximum file size that
may be transferred. Bump this up to 32MiB in order to support large
uncompressed kernel images.
Both of these buffers are dynamically allocated, and so the size of both
needs to be taken into account when calculating the required malloc
region size.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Commit 52a7c98a17 "tegra-common: increase malloc pool len by dfu mmc
file buffer size" updated the definition of CONFIG_SYS_MALLOC_LEN for
Tegra to take account of the DFU buffer size. However, this change had
no effect, since typical Tegra board config headers don't set the DFU-
related defines until after tegra-common.h is included. Fix this by
moving the affected conditional code to tegra-common-post.h, which is
included last. Also move the definition of SYS_NONCACHED_MEMORY since
it's a related and adjacent definition.
Fix the condition to test for the DFU feature, rather than specifically
MMC DFU support, so it applies in all cases.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
When writing to files in a filesystem on MMC, dfu_mmc.c buffers up the
entire file content until the end of the transaction, at which point the
file is written in one go. This allows writing files larger than the USB
transfer size (CONFIG_SYS_DFU_DATA_BUF_SIZE); the maximum written file
size is CONFIG_SYS_DFU_MAX_FILE_SIZE (the size of the temporary buffer).
The current file reading code does not do any buffering, and so limits
the maximum read file size to the USB transfer size. Enhance the code to
do the same kind of buffering as the write path, so the same file size
limits apply.
Remove the size checking code from dfu_read() since all read paths now
support larger files than the USB transfer buffer.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
DFU currently allocates buffer memory at the start of each data transfer
operation and frees it at the end. Especially since memalign() is used to
allocate the buffer, and various other allocations happen during the
transfer, this can expose the code to heap fragmentation, which prevents
the allocation from succeeding on subsequent transfers.
Fix the code to allocate the buffer once when DFU mode is initialized,
and free the buffer once when DFU mode is exited, to reduce the exposure
to heap fragmentation.
The failure mode is:
// Internally to memalign(), this allocates a lot more than s to guarantee
// that alignment can occur, then returns chunks of memory at the start/
// end of the allocated buffer to the heap.
p = memalign(a, s);
// Various other malloc()s occur here, some of which allocate the RAM
// immediately before/after "p".
//
// DFU transfer is complete, so buffer is released.
free(p);
// By chance, no other malloc()/free() here, in DFU at least.
//
// A new DFU transfer starts, so the buffer is allocated again.
// In theory this should succeed since we just free()d a buffer of the
// same size. However, this fails because memalign() internally attempts
// to allocate much more than "s", yet free(p) above only free()d a
// little more than "s".
p = memalign(a, s);
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
root_first_block_buffer should be free()d in all cases, not just when an
error occurs. Fix the success exit path of the function to do this.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
parse_path() malloc()s the entries in the array it's passed. Those
allocations must be free()d by the caller, ext4fs_get_parent_inode_num().
Add code to do this.
For this to work, all the array entries must be dynamically allocated,
rather than a mix of dynamic and static allocations. Fix parse_path() not
to over-write arr[0] with a pointer to statically allocated data.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
ext4_write_file() is only called from the "fs" layer, which calls both
ext4fs_mount() and ext4fs_close() before/after calling ext4_write_file().
Fix ext4_write_file() not to call ext4fs_mount() again, since the mount
operation malloc()s some RAM which is leaked when a second mount call
over-writes the pointer to that data, if no intervening close call is
made.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
By the time g_dnl_unbind() is run, cdev->config has been set to NULL,
so the free() there does nothing, and the config struct is leaked.
Equally, struct usb_gadget contains a linked list of config structs, so
the code should iterate over them all and free each one, rather than
freeing one particular config struct.
composite_unbind() already iterates over the list of config structs, and
unlinks each from the linked list. Fix this loop to free() each struct as
it's unlinked and otherwise forgotten.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
It is very common that FAT code is using following pattern:
if (disk_{read|write}() < 0)
return -1;
Up till now the above code was dead, since disk_{read|write) could only
return value >= 0.
As a result some errors from medium layer (i.e. eMMC/SD) were not caught.
The above behavior was caused by block_{read|write|erase} declared at
struct block_dev_desc (@part.h). It returns unsigned long, where 0
indicates error and > 0 indicates that medium operation was correct.
This patch as error regards 0 returned from block_{read|write|erase}
when nr_blocks is grater than zero. Read/Write operation with nr_blocks=0
should return 0 and hence is not considered as an error.
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Test HW: Odroid XU3 - Exynos 5433
Enable dwc3, dwc3-omap and PHY to get DWC3 functional in OMAP5
uEVM. Also enable support for DFU.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Now that we have a new header file for cache-aligned allocation, we should
move the stack-based allocation macro there also.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present malloc.h is included everywhere since it recently was added to
common.h in this commit:
4519668 mtd/nand/ubi: assortment of alignment fixes
This seems wasteful and unnecessary. We have been trying to trim down
common.h and put separate functions into separate header files and that
change goes in the opposite direction.
Move malloc_cache_aligned() to a new header so that this can be avoided.
The header would perhaps be better named as alignmem.h but it needs to be
included after common.h and people might be confused by this. With the name
memalign.h it fits nicely after malloc() in most cases.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
To reduce the size of the U-Boot image on the x600 board, lets enable
the THUMB mode. This reduces the overall size to less than 0x6000
bytes. Fitting it again in the onboard NOR flash.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Viresh Kumar <viresh.kumar@linaro.org>
This board is equipped with a Micron NAND chip (MT29F1G08ABADAH4) that
needs 4-bit ECC. But the SPEAr600 only supports 1-bit HW ECC internally.
This patch enables the SW 4-bit BCH support for this board.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Viresh Kumar <viresh.kumar@linaro.org>
This patch adds the "nandecc" command to switch between the SPEAr600 internal
1-bit HW ECC and the 4-bit SW BCH4 ECC. This can be needed to support NAND
chips with a stronger ECC than 1-bit, as on the x600. And to dynamically
switch between both ECC schemes for backwards compatibility.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
This patch adds support for 4-bit ECC BCH4 for the SPEAr600 SoC. This can
be used by boards equipped with a NAND chip that requires 4-bit ECC strength.
The SPEAr600 HW ECC only supports 1-bit ECC strength.
To enable SW BCH4, you need to specify this in your config header:
#define CONFIG_NAND_ECC_BCH
#define CONFIG_BCH
And use the command "nandecc bch4" to select this ECC scheme upon runtime.
Tested on SPEAr600 x600 board.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Scott Wood <scottwood@freescale.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
This board has not been converted to generic board by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stefano Babic <sbabic@denx.de>
These boards have not been converted to generic board by the deadline.
Remove them.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stefano Babic <sbabic@denx.de>
These boards have not been converted to generic board by the deadline.
Remove dm355evm, dm355leopard, dm365evm, dm6467evm, dvevm, ea20, schmoogie,
sffsdr, sonata.
Signed-off-by: Simon Glass <sjg@chromium.org>
These boards have not been converted to generic board by the deadline.
Remove all cpu9260 and cpuat91 boards.
Signed-off-by: Simon Glass <sjg@chromium.org>
Linux kernel can enumerate mmc sd as either mmcblk0 or mmcblk1.
But u-boot default environment assumes that sd always populates
as mmcblk0. With this the root fs is not being mounted when
mmc sd is enumerated as mmcblk1.
So use partuuid to update root= option in default environment.
Reported-by: Yan Liu <yan-liu@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Define default mmc args in ti_armv7_common.h so that all
TI platforms can reuse.
Reported-by: Yan Liu <yan-liu@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
All TI SoCs expect filesystem to be ext4, omap4_common is the only one
with ext3. move omap4 to ext4 so that we can start consolidating MMC
arguments.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
clrsetbits_le32/clrbits_le32 takes mask of the bits as input that
are needed to be set/clear. But emif driver passes the shift of the bits.
Fixing it here.
Reported-by: Mark Mckeown <m-mckeown@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Because there is an originally defined CLK_DMA_ENABLE macro in clk.h,
no reason to add another DMA_CLK_ENABLE macro with the same value.
Remove DMA_CLK_ENABLE, since it does not follow naming convention from
the code, this implies renaming of DMA_CLK_ENABLE to CLK_DMA_ENABLE in
lpc32xx/devices.c file.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Tested-by: Sylvain Lemieux <slemieux@tycoint.com>
To simplify and having a common default IP-setup on all B&R boards we
introduce an environment variable "brdefaultip" which does following.
Test if ${ipaddr} is empty, if yes it set's up some defaults:
- ipaddr : 192.168.60.1
- netmask : 255.255.255.0
- gatewayip: 192.168.60.254
- serverip : 192.168.60.254
This environment is ran from CONFIG_PREBOOT.
All other "tricks" are dropped.
Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The FAT code contains a special case to parse the root directory. This
is needed since the root directory location/layout on disk is special
cased for FAT12/16. In particular, the location and size of the FAT12/16
root directory is hard-coded and contiguous, whereas all FAT12/16 non-root
directories, and all FAT32 directories, are stored in a non-contiguous
fashion, with the layout represented by a linked-list of clusters in the
FAT.
If a file path contains ../ (for example /extlinux/../bcm2835-rpi-cm.dtb),
it is possible to need to parse the root directory for the first element
in the path (requiring application of the special case), then a sub-
directory (in the general way), then re-parse the root directory (again
requiring the special case). However, the current code in U-Boot only
applies the special case for the very first path element, and never for
any later path element. When reparsing the root directory without
applying the special case, any file in a sector (or cluster?) other than
the first sector/cluster of the root directory will not be found.
This change modifies the non-root-dir-parsing loop of do_fat_read_at()
to detect if it's walked back to the root directory, and if so, jumps
back to the special case code that handles parsing of the root directory.
This change was tested using sandbox by executing:
./u-boot -c "host bind 0 ../sd-p1.bin; ls host 0:0"
./u-boot -c "host bind 0 ../sd-p1.bin; ls host 0:0 /"
./u-boot -c "host bind 0 ../sd-p1.bin; ls host 0:0 /extlinux"
./u-boot -c "host bind 0 ../sd-p1.bin; ls host 0:0 /extlinux/"
./u-boot -c "host bind 0 ../sd-p1.bin; ls host 0:0 /extlinux/.."
./u-boot -c "host bind 0 ../sd-p1.bin; ls host 0:0 /extlinux/../"
./u-boot -c "host bind 0 ../sd-p1.bin; ls host 0:0 /extlinux/../backup"
./u-boot -c "host bind 0 ../sd-p1.bin; ls host 0:0 /extlinux/../backup/"
./u-boot -c "host bind 0 ../sd-p1.bin; ls host 0:0 /extlinux/../backup/.."
./u-boot -c "host bind 0 ../sd-p1.bin; ls host 0:0 /extlinux/../backup/../"
./u-boot -c "host bind 0 ../sd-p1.bin; load host 0:0 0 /bcm2835-rpi-cm.dtb"
./u-boot -c "host bind 0 ../sd-p1.bin; load host 0:0 0 /extlinux/../bcm2835-rpi-cm.dtb"
./u-boot -c "host bind 0 ../sd-p1.bin; load host 0:0 0 /backup/../bcm2835-rpi-cm.dtb"
./u-boot -c "host bind 0 ../sd-p1.bin; load host 0:0 0 /extlinux/..backup/../bcm2835-rpi-cm.dtb"
./u-boot -c "host bind 0 ../sd-p1.bin; load host 0:0 0 /extlinux/../backup/../bcm2835-rpi-cm.dtb"
(/extlinux and /backup are in different sectors so trigger some different
cases, and bcm2835-rpi-cm.dtb is in a sector of the root directory other
than the first).
In all honesty, this change is a bit of a hack, using goto and all.
However, as demonstrated above it appears to work well in practice, is
quite minimal, likely doesn't introduce any risk of regressions, and
hopefully doesn't introduce any maintenance issues.
The correct fix would be to collapse the root and non-root loops in
do_fat_read_at() and get_dentfromdir() into a single loop that has a
small special-case when moving from one sector to the next, to handle
the layout difference of root/non-root directories. AFAIK all other
aspects of directory parsing are identical. However, that's a much
larger change which needs significantly more thought before it's
implemented.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
[root@pollux dfu-util]# ./src/dfu-util -l
dfu-util 0.8
Copyright 2005-2009 Weston Schmidt, Harald Welte and OpenMoko Inc.
Copyright 2010-2014 Tormod Volden and Stefan Schmidt
This program is Free Software and has ABSOLUTELY NO WARRANTY
Please report bugs to dfu-util@lists.gnumonks.org
Found DFU: [0908:02d2] ver=0212, devnum=119, cfg=1, intf=0, alt=0, name="Linux", serial="UNKNOWN"
[root@pollux dfu-util]#
Signed-off-by: Heiko Schocher <hs@denx.de>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
port at91_udc driver from linux:
original commit Message:
commit c94e289f195e0e13cf34d27f9338d28221a85751
Author: Arnd Bergmann <arnd@arndb.de>
Date: Sat Apr 11 00:14:21 2015 +0200
usb: gadget: remove incorrect __init/__exit annotations
A recent change introduced a link error for the composite
printer gadget driver:
`printer_unbind' referenced in section `.ref.data' of drivers/built-in.o: defined in discarded section `.exit.text' of drivers/built-in.o
Evidently the unbind function should not be marked __exit here,
because it is called through a callback pointer that is not necessarily
discarded, __composite_unbind() is indeed called from the error path of
composite_bind(), which can never work for a built-in driver.
Looking at the surrounding code, I found the same problem in all other
composite gadget drivers in both the bind and unbind functions, as
well as the udc platform driver 'remove' functions. Those will break
if anyone uses the 'unbind' sysfs attribute to detach a device from a
built-in driver.
This patch removes the incorrect annotations from all the gadget
drivers.
Signed-off-by: Heiko Schocher <hs@denx.de>
Entering the maximum number of characters defined by CONFIG_SYS_CBSIZE
into the console and hitting enter afterwards, causes a hang in the
system because CONFIG_SYS_PBSIZE is not capable of storing the extra
characters of the error message:
"Unknown command '' - try 'help'".
Use the default CONFIG_SYS_PBSIZE definition from config_fallbacks.h
to solve this problem.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Josh Wu <josh.wu@atmel.com>
add extensions for the axm board:
- power on LED on power up
- press both recovery buttons on power up to enter
recovery mode
- detect 64 MiB and 128 MiB ramsize
- PHY rest at reboot because of ATMEL bug
- use siemens update concept
- add axm default environment
- set CONFIG_SPL_MAX_SIZE to 15k
Signed-off-by: Heiko Schocher <hs@denx.de>
This patch adds support for NAND chips with 4KiB page size and 24/1024
ECC strength. Like the Micron MT29F32G08CBACAWP which is used on the
ICnova-A20 SoM.
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Currently some uninitialized padding bytes are written to the output
file, as can be confirmed with valgrind:
$ valgrind tools/mksunxiboot spl/u-boot-spl.bin spl/sunxi-spl.bin
==5581== Syscall param write(buf) points to uninitialised byte(s)
==5581== at 0x4F0F940: __write_nocancel (in /lib64/libc-2.20.so)
==5581== by 0x400839: main (in /tmp/u-boot/tools/mksunxiboot)
==5581== Address 0xffeff5d3c is on thread 1's stack
==5581== in frame #1, created by main (???)
This patch fixes the problem by clearing the whole structure instead
of just a portion of it.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The Forfun Q88DB tablet was unbootable since commit
b6006baf9c ("sunxi: Move all
boards to the driver-model"). Appears that this is caused
by the wrong serial console setup in the SPL. The serial
console should use PG3/PG4 pins according to the FEX file.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The Wobo i5 top set box is a somewhat curious A10s based top set box,
it uses an AXP209 rather then the AXP152 usually used in combination
with the A10s. It has an ethernet phy connected to PORTD rather then
PORTA, and its built-in usb wifi is connected via the otg controller.
The dts file changes are identical to the changes submitted to the
upstream kernel.
Signed-off-by: Jelle van der Waa <jelle@vdwaa.nl>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
This commits adds a generic support for q8 formfactor a13 based tablets.
These tablets ship in many variants, with the difference mainly being the
touchscreen controller / accelerometer / wifi chip used.
The wifi is USB based, and thus not listed in devicetree.
ATM the kernel does not support the touchscreen / accelerometer on these
devices. In the future we may need multiple configs with different
CONFIG_DEFAULT_DEVICE_TREE settings, this depends on how we solve the
hw differences on the kernel side.
For now this will suffice.
The dts files are identical to the dts files submitted to the upstream
kernel for these tablets.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The iNet-tek iNet-1 PCB is a PCB found in various generic 10.1" 1024x600
A10 based tablets such as the Point of View Protab2 XXL and the
Cherry M1007.
This patch has been tested on both rev2 and rev5 of this board / these
tablets.
These tablets feature the usual connectors: headphone, mini hdmi,
power-barrel, mini-usb and a micro-sd slot.
The dts is identical to the dts submitted to the upstream kernel.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The inet9f-rev03 pcb is specially designed for gaming tablets, such as
the qware tb-g100 tablet.
These 7" tablets feature a dpad, firebuttons and 2 joysticks on the sides
of the screen.
Besides this they have the usual connectors: power-barrel, mini usb,
mini hdmi, headphone and micro-sd slot.
The dts is identical to the dts submitted to the upstream kernel.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The Point of View protab2-ips9 is a tablet with a 9" ips 1024x768 lcd
screen, microsd slot, headphones, mini hdmi, mini usb b and power barrel
connectors.
The dts file is identical to the one submitted to the upstream kernel.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
When building dm version of designware eth driver on a platform
with 64-bit phys_addr_t, it reports the following warnings:
drivers/net/designware.c: In function 'designware_eth_probe':
drivers/net/designware.c:599:2:
warning: format '%lx' expects argument of type 'long unsigned int',
but argument 3 has type 'phys_addr_t' [-Wformat]
drivers/net/designware.c:600:21:
warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
drivers/net/designware.c:601:21:
warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
This commit fixes the build warnings.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
USB PHY needs to be properly initialized per Quark firmware writer
guide, otherwise the EHCI controller on Quark SoC won't work.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Quark SoC holds the PCIe controller in reset following a power on.
U-Boot needs to release the PCIe controller from reset. The PCIe
controller (D23:F0/F1) will not be visible in PCI configuration
space and any access to its PCI configuration registers will cause
system hang while it is held in reset.
Enable PCIe controller per Quark firmware writer guide.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
If we convert to use driver model pci on quark, we will encounter
some chicken and egg problems like below:
- To enable PCIe root ports, we need program some registers on the
message bus via pci bus. With driver model, the first time to
access pci bus, the pci enumeration process will be triggered.
But without first enabling PCIe root ports, pci enumeration
just hangs when scanning PCIe root ports.
- Similar situation happens when trying to access GPIO from the
PCIe enabling codes, as GPIO requires its block base address
to be assigned via a pci configuration register in the bridge.
To avoid such dilemma, replace all pci calls in the quark codes
to use the local version which does not go through driver model.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Intel Quark SoC has a low end x86 processor with only 400MHz
frequency. Currently it takes about 15 seconds for U-Boot to
boot to shell and the most time consuming part is with MRC,
which is about 12 seconds. MRC programs lots of registers on
the SoC internal message bus indirectly accessed via pci bus.
To speed up the boot, create an optimized version of pci config
read/write dword routines which directly operate on PCI I/O ports.
These two routines are inlined to provide better performance too.
Now it only takes about 3 seconds to finish MRC, which is really
fast (4 times faster than before).
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
At present, until a PCI bus is probed, it cannot be found by its sequence
number unless it has an alias. This is the same with any device.
However with PCI this is more annoying than usual, since bus 0 is always the
same device.
Add a function that tries a little harder to locate PCI bus 0. This means
that PCI enumeration will happen automatically on the first access.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present buildman can compare configurations between commits but the
feature is less useful than it could be. There is no summary by architecture
and changes are not reported on a per-board basis.
Correct these deficiencies so that it is possible to see exactly what is
changing for any number of boards.
Note that 'buildman -b <branch> -C' is recommended for any build where you
will be comparing configuration. Without -C the correct configuration will
not be reported since changes will often not be picked up.
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
This reverts commit 19b4a33698.
Since that commit, patman generates useless patches for file removal;
"git format -D" prints only the header but not the diff when deleting
files, and "git am" always refuses such patches.
The following is the quotation from "man git-format-patch":
-D, --irreversible-delete
Omit the preimage for deletes, i.e. print only the header but
not the diff between the preimage and /dev/null. The resulting
patch is not meant to be applied with patch nor git apply; this
is solely for people who want to just concentrate on reviewing
the text after the change. In addition, the output obviously
lack enough information to apply such a patch in reverse, even
manually, hence the name of the option.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
Now that we have converted the pch_gbe driver to driver moel,
enable it on Intel Crown Bay board.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
This commit converts pch_gbe ethernet driver to driver model.
Since this driver is only used by Intel Crown Bay board, the
conversion does not keep the non-dm version.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Simon Glass <sjg@chromium.org>
Since E1000 driver has been converted to driver model, enable it
on Intel Crown Bay. But the Intel Topcliff GbE driver has not been
converted to driver model yet, disable it for now.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
When given a device name string, we should test to see if it is
really an alias like "eth#".
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Add one more ethernet device node in the sandbox test device tree,
with name 'sbe5'. This is to support a new test case for testing
network device rotation.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
With driver model, board_eth_init() or cpu_eth_init() is not a must.
Thus we don't need print a misleading "Net Initialization Skipped".
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Commit 620776d "tftp: adjust settings to be suitable for 100Mbit ethernet"
causes the following error message when trying to load a file using 'tftp'
command via a tftp server.
TFTP error: 'Unsupported option(s) requested' (8)
This is due to with commit 620776d changes, the tftp option 'timeout'
value is now set to zero which is an invalid value as per RFC2349 [1].
Valid values range between "1" and "255" seconds, inclusive. With some
tftp servers that strictly implement the RFC requirement, it reports
such an error message.
Revert commit 620776d for RFC compliance.
[1] https://www.ietf.org/rfc/rfc2349.txt
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Add a PCI node to the device tree. This allows SPI flash and SATA to work
correctly. Also configure the video to come up correctly even though there
is no keyboard.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
With multiple microcode blobs included, the generated u-boot-dtb.bin
leaves merely several hundred bytes before the vga bios. Change the
vga bios rom address to make a bigger room for u-boot-dtb.bin.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
CONFIG_X86_OPTION_ROM_ADDR has been renamed to CONFIG_VGA_BIOS_ADDR.
Update the doc to refer to the new name.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
We have the capability to check regions written after U-Boot that
do not overlap. Since regions can also be written before U-Boot,
add such check for these too.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Andy Pont <andy.pont@sdcsystems.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
When an EHCI device is registered in device mode, the HW isn't actually
initialized at all, and hence isn't left in a running state. Consequently,
when the device is deregistered, ehci_shutdown() will fail, since the HW
bits it expects to see set in response to its shutdown requests will not
be sent, and the message "EHCI failed to shut down host controller." will
be printed.
Fix ehci-hcd.c to remember whether the device was registered in host or
device mode, and only call ehci_shutdown() for host mode registrations.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
This commit enables support for DFU_TFTP on the am335x bone black device.
Signed-off-by: Lukasz Majewski <l.majewski@majess.pl>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The dfu tftp feature can be now enabled via Kconfig. This
commit provides necessary code for it.
Signed-off-by: Lukasz Majewski <l.majewski@majess.pl>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This code allows using DFU defined mediums for storing data received via
TFTP protocol.
It reuses and preserves functionality of legacy code at common/update.c.
The update_tftp() function now accepts parameters - namely medium device
name and its number (e.g. mmc 1).
Without this information passed old behavior is preserved.
Signed-off-by: Lukasz Majewski <l.majewski@majess.pl>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This function allows writing via DFU data stored from fixed buffer address
(like e.g. loadaddr env variable).
Such predefined buffers are used in the update_tftp() code. In fact this
function is a wrapper on the dfu_write() and dfu_flush().
Signed-off-by: Lukasz Majewski <l.majewski@majess.pl>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This commit adds initial support for using tftp for downloading and
upgrading firmware on the device.
Signed-off-by: Lukasz Majewski <l.majewski@majess.pl>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Up till now it was impossible to use code from update.c when system
was not equipped with raw FLASH memory.
Such behavior prevented DFU from reusing this code.
Signed-off-by: Lukasz Majewski <l.majewski@majess.pl>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This change gives the ability to reuse the <tftp.h> header file by other
subsystems (like e.g. dfu).
Without this change compilation error emerges for the legacy update.c file.
Signed-off-by: Lukasz Majewski <l.majewski@majess.pl>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Documentation file for DFU extension. With this functionality it is now
possible to transfer FIT images with firmware updates via TFTP and use
DFU backend for storing them.
Signed-off-by: Lukasz Majewski <l.majewski@majess.pl>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Commit <8bfc288c3955> ("usb: gadget: ether: Perform board
initialization from ethernet gadget driver") added board_usb_init
and board_usb_cleanup in ethernet gadget driver. But h2200 board
didn't have board_usb_init and board_usb_cleanup implementations.
This introduced the following build errors
+drivers/usb/gadget/built-in.o: In function `usb_eth_halt':
+drivers/usb/gadget/ether.c:2498: undefined reference to `board_usb_cleanup'
+drivers/usb/gadget/built-in.o: In function `usb_eth_init':
+drivers/usb/gadget/ether.c:2316: undefined reference to `board_usb_init'
Fix it here by adding empty board_usb_init and board_usb_cleanup
functions in h2200.c.
Fixes: <8bfc288c3955> ("usb: gadget: ether: Perform board
initialization from ethernet gadget driver")
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
After extension of the dfu_get_buf() to also setup (implicitly) the dfu_buf_size
variable it is not needed to set dfu_buf_size to CONFIG_SYS_DFU_DATA_BUF_SIZE.
This variable is set in the dfu_get_buf() by not only considering
CONFIG_SYS_DFU_DATA_BUF but more importantly the "dfu_bufsiz" env variable.
Therefore, dfu_get_buf() should be used for initialization.
Signed-off-by: Lukasz Majewski <l.majewski@majess.pl>
Reviewed-by: Przemyslaw Marczak <p.marczak@samsung.com>
dfu-util allows filtering on USB device vendor:product ID by using
the -d flag (-d 0451:d022).
Such option is very handy when many DFU devices are connected to a single
host PC. This commit allows testing when above situation emerges.
Signed-off-by: Lukasz Majewski <l.majewski@majess.pl>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Lukasz Majewski <l.majewski@majess.pl>
Test HW - AM335x Beagle Bone Black
NOTE: Max size of file to transfer: 2MiB
Allocate request up to THOR_PACKET_SIZE not the ep0->maxpacket
as the descriptors data depend on the number of descriptors
and this 64 bytes were not enough and the buffer might overflow
which results in memalign failures later.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Dont perform reset at the end of thor download
if configured to do reset off.
Reset may not be required in all cases and hence
provided an option to do so.
The case would be to download the images to DDR instead
of flash device.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add support for the Terasic DE0-Nano/Atlas-SoC Kit, which is a CycloneV
based board. The board can boot from SD/MMC. Ethernet is also supported.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Add support for DENX MCV SoM, which is CycloneV based and the
associated DENX MCVEVK baseboard. The board can boot from eMMC.
Ethernet and USB is supported.
Signed-off-by: Marek Vasut <marex@denx.de>
Add support for Terasic SoCkit, which is CycloneV based board.
The board can boot either from SD/MMC or QSPI. Ethernet is also
supported.
Signed-off-by: Marek Vasut <marex@denx.de>
Instead of calling board_init_r() directly from board_init_f(), just
return from board_init_f(). This will make the code continue executing
in crt0.S _main(), from which the board_init_r() is called. This patch
aligns the SoCFPGA SPL with the correct SPL design as well as reduces
the stack utilisation slightly.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
The CONFIG_OF_CONTROL and CONFIG_SPL_OF_CONTROL is always enabled
on Altera SoCFPGA, remove the unnecessary checks.
Signed-off-by: Marek Vasut <marex@denx.de>
The SoCFPGA probes mostly from OF and the OF is mandatory both in
U-Boot itself and U-Boot SPL. Enable it by default.
Signed-off-by: Marek Vasut <marex@denx.de>
This fix makes sure that the ISWGRP0 and ISWGRP1 registers are
correctly inited. In case those registers are not initialized,
it is not possible to access the registers synthesised in the
FPGA through the bridges. Any such access produces data abort.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Rework the driver to probe the MMC controller from Device Tree
and make it mandatory. There is no longer support for probing
from the ancient qts-generated header files.
This patch now also removes previous temporary workaround.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Tom Rini <trini@konsulko.com>
It is easier to paste these into the command line if they are a single
common. Use line continuation instead of separate lines.
Signed-off-by: Simon Glass <sjg@chromium.org>
Instead of creating a rockchip SPL SD card image with 32KB of zeros
which can be written to the start of an SD card, create the images with
only the useful data that should be written to an offset of 32KB on the
SD card.
The first 32 kilobytes aren't needed for bootup and only serve as
convenient way of accidentally obliterating your partition table.
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Booting the kernel fails on RK3288 (and probably other rockchip SoCs)
when the i-cache is disabled/flushed before d-cache.
I have not investigated whether this is due to U-Boot hanging or whether
it's very early in the linux boot, but following the approach of the
various rockchip U-Boot forks (first disable d-cache then i-cache) makes
things work.
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Now that MMC works in U-Boot add config distro command support to start
Linux in a standard fashion. One oddity here is that linux fails to load
when the fdt is relocated to above 512MB, so set fdt_high to make sure it's
loaded below that.
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
With LED support enabled the SPL easily goes over the size limit (e.g.
with both Debians gcc 4.9 and 5.2 cross-compilers). Turn off LED support
in the SPL to reduce the size just enough for those compilers.
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Tweaked commit subject to remove _SUPPORT
Signed-off-by: Simon Glass <sjg@chromium.org>
U-Boot can't use the sdio card so turn it of to prevent things getting
confused/struck when trying to use the card as storage.
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
The Radxa Rock pro board is rk3188 based and thus won't work with U-Boot
built for RK3288. Change the documentation to refer to the intended
board, the Radxa Rock 2, which is an RK3288-based design very similar to
the firefly
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
The Firefly RK3288 is a suitable target board for initial mainline Rockchip
support. It includes a good set of peripherals, a recent SoC and it is
readily available.
This adds only some basic files required to allow the baord to display a
serial message in SPL and hang.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add a SPI driver for the Rockchip RK3288, using driver model. It should work
for other Rockchip SoCs also.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add an I2C driver for the Rockchip RK3288, using driver model. It should work
for other Rockchip SoCs also.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add code for starting up U-Boot SPL and U-Boot proper. This is generic and
makes use of devices provided by the board- or SoC-specific code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add an MMC driver which supports RK3288, but may also support other SoCs.
It uses the Designware MMC device.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add code to set up the SDRAM in SPL, ready for loading U-Boot. This uses
device tree for configuration so should be able to support other RAM
configurations. It may be possible to generalise the code to support other
SoCs at some point.
Signed-off-by: Simon Glass <sjg@chromium.org>
PMU is the power management unit and GRF is the general register file. Both
are heavily used in U-Boot. Add header files with register definitions.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add a full regulator driver for the ACT8846. This provides easy access to
voltage and current settings for each regulator.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add a driver for the ACT8846 PMIC. This supports several LDOs and BUCKs and
is connected to the I2C bus. This driver supports using a regulator driver
to access the regulators.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add header files for the peripherals and clocks supported on Rockchip
platforms. The particular implementation (and register set) for each is
SoC-specific, but it seems that the naming can be generic.
Signed-off-by: Simon Glass <sjg@chromium.org>
The Rockchip boot ROM requires a particular file format for booting from SPI.
It consists of a 512-byte header encoded with RC4, some padding and then up
to 32KB of executable code in 2KB blocks, separated by 2KB empty blocks.
Add support to mkimage so that an SPL image (u-boot-spl-dtb.bin) can be
converted to this format. This allows booting from SPI flash on supported
machines.
Signed-off-by: Simon Glass <sjg@chromium.org>
The Rockchip boot ROM requires a particular file format. It consists of
64KB of zeroes, a 512-byte header encoded with RC4, and then some executable
code.
Add support to mkimage so that an SPL image (u-boot-spl-dtb.bin) can be
converted to this format.
Signed-off-by: Simon Glass <sjg@chromium.org>
Rockchip SoCs require certain formats for code that they execute, The
simplest format is a 4-byte header at the start of a binary file. Add
support for this so that we can create images that the boot ROM understands.
Signed-off-by: Simon Glass <sjg@chromium.org>
Allow the image handler to store the original input file size so that it
can reference it later.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
At present there is an arbitrary limit of 4KB for padding. Rockchip needs
more than that, so remove this restriction.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
In SPL we need access to the CRU and other peripherals so we can set up
SDRAM. Mark these so that they will remain in the device tree.
Signed-off-by: Simon Glass <sjg@chromium.org>
Bring in required device tree files from Linux. Since mainline Linux is
somewhat behind, use the files from the Chromium tree. We can re-sync once
further code is acccepted upstream.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add support for the Rockchip serial device using the ns16550 driver.
This uses driver model and device tree for both SPL and U-Boot proper.
Signed-off-by: Simon Glass <sjg@chromium.org>
There can be only one do_reset(). When CONFIG_RESET is enabled this is
provided by the reset uclass, and ARM's version should be disabled.
Signed-off-by: Simon Glass <sjg@chromium.org>
All devices should bind without error. But when they don't, they can cause
driver model init to fail. A real situation where this can happen is when
there is a missing uclass.
Add a debug() call to dm_scan_fdt_node to make this easier to track.
Signed-off-by: Simon Glass <sjg@chromium.org>
When a uclass definition is missing, no drivers in that uclass can operate.
This can happen if a board has a strange collection of options (e.g. the
driver is enabled but the uclass is not).
Unfortunately this is very confusing at present. Starting up driver model
results in a -ENOENT error, which is pretty generic. Quite a big of digging
is needed to get to the root cause.
To help with this, change the error to a very strange one with no other
users in U-Boot. Also add a debug message.
Signed-off-by: Simon Glass <sjg@chromium.org>
Some SoCs want to adjust the input clock to the DWMMC block as a way of
controlling the MMC bus clock. Update the get_mmc_clk() method to support
this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
At present SPL does not have its own option. But these features can
increase SPL code size. Adjust the Kconfig and Makefile so that
separate a SPL option can be selected.
Signed-off-by: Simon Glass <sjg@chromium.org>
My original pinctrl patch operating using a peripheral ID enum. This was
shared between pinmux and clock and provides an easy way to specify a device
that needs to be controlled, even it is does not (yet) have a driver within
driver model.
Masahiro's new simple pinctrl gets around this by providing a
set_state_simple() pinctrl method. By passing a device to that call the
peripheral ID becomes unnecessary. If the driver needs it, it can calculate
it itself and use it internally.
However this does not solve the problem for peripheral clocks. The 'pure'
solution would be to pass a driver to the clock uclass also. But this
requires that all devices should have a driver, and a struct udevide. Also
a key optimisation of the clock uclass is allowing a peripheral clock to
be set even when there is no device for that clock.
There may be a better way to achive the same goal, but for now it seems
expedient to add in peripheral ID to the pinctrl uclass. Two methods are
added - one to get the peripheral ID and one to select it. The existing
set_state_simple() is effectively the union of these.
Signed-off-by: Simon Glass <sjg@chromium.org>
These have not been converted to Generic Board, so should be removed.
(See doc/README.generic-board for details.)
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Dan Malek <dan@embeddedalley.com>
This has not been converted to Generic Board, so should be removed.
(See doc/README.generic-board for details.)
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This has not been converted to Generic Board, so should be removed.
(See doc/README.generic-board for details.)
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Stefan Roese <sr@denx.de>
This has not been converted to Generic Board, so should be removed.
(See doc/README.generic-board for details.)
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This has not been converted to Generic Board, so should be removed.
(See doc/README.generic-board for details.)
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Stefan Roese <sr@denx.de>
This has not been converted to Generic Board, so should be removed.
(See doc/README.generic-board for details.)
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Stefan Roese <sr@denx.de>
This has not been converted to Generic Board, so should be removed.
(See doc/README.generic-board for details.)
Remove CONFIG_LWMON5 references.
(Also, remove undefined CONFIG_WD_MAX_RATE while I am here.)
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Stefan Roese <sr@denx.de>
These have not been converted to Generic Board, so should be removed.
(See doc/README.generic-board for details.)
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Tolunay Orkun <torkun@nextio.com>
This has not been converted to Generic Board, so should be removed.
(See doc/README.generic-board for details.)
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Stefan Roese <sr@denx.de>
SANDBOX_SERIAL depends on SANDBOX, and SANDBOX selects DM.
So, "SANDBOX_SERIAL depends on DM" is redundant.
Likewise, UNIPHIER_SERIAL depends on ARCH_UNIPHIER, and
ARCH_UNIPHIER selects DM_SERIAL.
So, "UNIPHIER_SERIAL depends on DM_SERIAL" is redundant.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
Since we need to support runtime check for different drivers, we need
to add get_cpu_rev for vf610, otherwise there will be build errors.
This patch introduces a dummy CPU id which is not read from chip
silicon. Later when we can get the real id from chip, can fix the
value of MXC_CPU_VF610 then.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Suggested-by: Stefano Babic <sbabic@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
There is a hole in shadow registers address map of size 0x100
between bank 5 and bank 6 on iMX6QP, iMX6DQ, iMX6SDL, iMX6SX and iMX6UL.
Bank 5 ends at 0x6F0 and Bank 6 starts at 0x800. When reading the fuses,
we should account for this hole in address space.
Similar hole exists between bank 14 and bank 15 of size
0x80 on iMX6QP, iMX6DQ, iMX6SDL and iMX6SX.
Note: iMX6SL has only 0-7 banks and there is no hole.
Note: iMX6UL doesn't have this one.
When reading, we use register offset, so need to account for holes
to get the correct address.
When writing, we use bank/word index, there is no need to account
for holes, always use bank/word index from fuse map.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE works better than
CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP (keyboards that previously didn't
work such as Microsoft Comfort Curve 1000 now do work, and it's also faster).
Switch to CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
On some CM-FX6 modules U-Boot attempts to configure the usb0 controller in
device mode, which renders it unavailable:
USB0: Port not available.
and also causes usb stop to report an error
EHCI failed to shut down host controller.
This happens mostly on MX6 Dual based modules, and is caused by the USBPHY_CTRL
register reporting USBPHY_CTRL_OTG_ID to be 1, even when it is pulled down.
Since we do not support device mode in cm-fx6 u-boot, force all controllers to
be configured as hosts.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
there is a 2b board version of the aristainetos2
board. Differences to the v2:
- spi cs for the nor flash and display controller
changed
- some pinmux changes
- LED gpio settings changed
Signed-off-by: Heiko Schocher <hs@denx.de>
make the spi bus and the spi chipselect configurable
for the lg4573 driver. Use it on the aristainetos
boards.
Signed-off-by: Heiko Schocher <hs@denx.de>
Acked-by: Anatolij Gustschin <agust@denx.de>
There is no need to expose SoC choice to user, we already got
the SoC according to the build target. So default "select MX6UL"
for MX6UL_14x14_EVK target.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
To i.MX6UL, SYS_L2CACHE_OFF is selected, but there is no Kconfig entry
for SYS_L2CACHE_OFF. Then "select SYS_L2CACHE_OFF" does not effect for
i.MX6UL, which is not expected.
Since SYS_L2CACHE_OFF is mainly used by ARM architecture, add it to
arch/arm/Kconfig.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@konsulko.com>
Cc: Stefano Babic <sbabic@denx.de>
Add SPL boot support for mx6slevk board.
1. Introduce a configuration file mx6slevk_spl_defconfig.
2. i.MX6SL has same DRAM space with i.MX6SX, need to change SPL DRAM SPACE.
3. Include imx6_spl.h and related SPL macro in mx6slevk.h.
4. select SUPPORT_SPL for TARGET_MX6SLEVK.
5. Add SPL board code to do related initialization.
Boot Log:
U-Boot SPL 2015.07-00544-g1594a76 (Aug 17 2015 - 01:56:59)
reading u-boot.img
reading u-boot.img
U-Boot 2015.07-00544-g1594a76 (Aug 17 2015 - 01:56:59 +0000)
CPU: Freescale i.MX6SL rev1.2 996 MHz (running at 396 MHz)
CPU: Commercial temperature grade (0C to 95C) at 50C
Reset cause: POR
Board: MX6SLEVK
I2C: ready
DRAM: 1 GiB
PMIC: PFUZE100 ID=0x10
MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
*** Warning - bad CRC, using default environment
In: serial
Out: serial
Err: serial
Net: FEC [PRIME]
Hit any key to stop autoboot: 0
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Add LPDDR2 support:
1. Implement a function mx6_lpddr2_cfg to initialize MMDC for LPDDR2.
2. Introduce a structure mx6_lpddr2_cfg, most entrys are same to
mx6_ddr3_cfg, but still keep it a single one for easy to choose
parameters for LPDDR2.
3. If ddr_type is LPDDR2, use mx6_lpddr2_cfg to init MMDC.
4. Update comments.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
To i.MX6, DDR3 and LPDDR2 is supported, so rename function mx6_dram_cfg
to mx6_ddr3_cfg and the original mx6_dram_cfg function only is a wrapper.
The new reimplemented function mx6_dram_cfg only invokes mx6_ddr3_cfg
when ddr_type is for DDR3. Later we can use ddr_type to initialize
MMDC for LPDDR2.
Initialize ddr_type for different boards which enable SPL.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Add ddr_type entry for mx6_ddr_sysinfo. It will be used for
differenrate DDR3 and LPDDR2.
Introduce an enum type for ddr_type.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Add mpzqlp2ctl entry for mx6_mmdc_calibration.
MMDC_MPZQLP2CTL register is for init tZQINIT, tZQCL, tZQCS for LPDDR2 chips.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Define two structure mx6sl_iomux_ddr_regs and mx6sl_iomux_grp_regs.
Add a new function mx6sl_dram_iocfg to configure dram io.
Add header file to define macros for register address.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
To Chip density 4Gb, tRFC should be 300ns, see
"Table 61 — Refresh parameters by device density" of JESD79-3E.
tXS(min) is max(5nCK, tRFC(min) + 10ns).
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Extend the documentation of the fec_mxc configuration by describing its
ability to read the ethaddr MAC address from the SoC eFuses.
Also add an example how to program the fuses for an imx5 to clarify the
byte order.
Cc: Stefano Babic <sbabic at denx.de>
Cc: Marek Vasut <marex at denx.de>
Signed-off-by: Olaf Mandel <o.mandel at menlosystems.com>
some small updates for the aristainetos boards:
- fix display timings for the aristainetos board
- fix pinmux for the aristainetos board
- fix pinmux for the aristainetos2 board
- fix default environment
Signed-off-by: Heiko Schocher <hs@denx.de>
* Add mxc_gpio support for imx7d SoC
* Use CONFIG_MX7 to extend mxc gpio driver support for imx7d
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
* Add imx7d support for iomux controller
* imx7d has two iomux controllers iomuxc (0x3033000) and iomuxc-lpsr
(0x302C0000) each conroller provides control and mux mode pad
registers but shares iomuxc input select register with iomuxc-lpsr
IOMUX_CONFIG_LPSR flag is used to properly set daisy chain settings
for iomuxc-lpsr pads.
* Since mx7d introduces LPSR IOMUX pins, add new base to IOMUX v3
driver for these LPSR pins.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
* Add pmic pfuze3000 support, implement power_pfuze3000_init to be
used in power_init_board callback function.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
To i.MX6SX/UL, two ethernet interfaces are supported.
Add ENET2 clock support:
1. Introduce a new input parameter "fec_id", only 0 and 1 are allowed.
To value 1, only i.MX6SX/UL can pass the check.
2. Modify board code who use this api to follow new api prototype.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Nikolaos Pasaloukos <Nikolaos.Pasaloukos@imgtec.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Move most macro definitions and prototypes into
"arch/arm/include/asm/imx-common/sys_proto.h" to avoid duplicated
function prototypes and marco definitions for different i.MX SoCs.
This patch do not remove the sys_proto.h for different i.MX SoCs,
because we need to modify lots of driver code and others. This patch
remove duplicated macros and prototypes and incude "sys_proto.h"
of imx-common for each sys_proto.h of different i.MX platforms.
Then later we should avoid add stuff in sys_proto.h of each platform,
and modify driver to include common sys_proto.h.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Rewrite get_cpu_rev, from "static const char *get_cpu_rev(void)" to
"u32 get_cpu_rev(void)". To align with get_cpu_rev of other i.MXes.
Also write get_imx_type to replace get_cpu_type, since we have
macro named get_cpu_type.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Use new formula for get_cpu_rev, since we need to use this formula
to do runtime check for all i.MXes.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
When the original HBUS divider value is retrieved in mxs_ocotp_scale_hclk()
for the purpose or restoring it back later, the value is not shifted by the
HBUS divider offset in that register. This is not a problem, since the shift
is zero on all MXS hardware. Add the shift anyway, for completeness and in
case FSL ever decides to re-use this driver on future designs.
Signed-off-by: Chris Smith <chris@zxdesign.info>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
This commit adds ethernet support to the TS4800. Note that the
MAC address is not fused on this board and have to be read from
FEC PALR PAUR registers (this is how the kernel provided by
Technologic Systems does it).
signed-off-by: Damien Riegel <damien.riegel@savoirfairelinux.com>
Cc: Stefano Babic <sbabic@denx.de>
This commit adds basic support including:
MMC, Serial console, TS4800 watchdog
The config use CONFIG_SKIP_LOWLEVEL_INIT as U-boot is used as a second
stage bootloader.
Signed-off-by: Lucile Quirion <lucile.quirion@savoirfairelinux.com>
signed-off-by: Damien Riegel <damien.riegel@savoirfairelinux.com>
Cc: Stefano Babic <sbabic@denx.de>
cgtqmx6eval can be populated with a AR8035 or KSZ9031 depending on the
board revision.
Add Ethernet support.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Remove this ad-hoc mkimage invocation in MXS Makefile and replace
it with the standard mkimage rule instead.
This patch fixes recent build issues introduced by the patch
92a655c mkimage: Set up a file size parameter and keep it updated
These build issues could be triggered by building for example the
MX28EVK and the u-boot.sb image:
$ make mx28evk_defconfig
$ make V=1 u-boot.sb
[...]
make -f ./scripts/Makefile.build obj=arch/arm/cpu/arm926ejs/mxs u-boot.sb
./tools/mkimage -n arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg -T mxsimage u-boot.sb
./tools/mkimage: Can't open (null): Bad address
arch/arm/cpu/arm926ejs/mxs/Makefile:82: recipe for target 'u-boot.sb' failed
make[1]: *** [u-boot.sb] Error 1
Makefile:989: recipe for target 'u-boot.sb' failed
make: *** [u-boot.sb] Error 2
With this patch:
./tools/mkimage -n arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg -T mxsimage -d arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg u-boot.sb
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Juha Lumme <juha.lumme@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
For pages of 2048 bytes the current setting of the ECC Error Correction Level
is only true for an oob size of 64 bytes and wrong for all others.
Instead of hard-coding every possible combination of page size and oob size use
the dynamic calculation of the ECC strength introduced in commit
6121560d77.
Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Currently we need to build one U-boot image for each of the udoo
variants: quad and dual-lite.
By switching to SPL we can support all two variants with a single binary.
Based on the SPL for wandboard.
Tested with OpenELEC (Open Embedded Linux Entertainment Center)
on both boards.
Signed-off-by: Peter Vicman <peter.vicman@gmail.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Peter Vicman <peter.vicman@gmail.com>
Acked-by: Fabio Estevam <fabio.estevam@freescale.com>
When dcd_len is 0 the Write Data command that the set_dcd_rst_v2() routine
generates is empty. This causes HAB to complain that the command is invalid.
--------- HAB Event 1 -----------------
event data:
0xdb 0x00 0x0c 0x41 0x33 0x06 0xc0 0x00
0xcc 0x00 0x04 0x04
To fix this set the DCD pointer in the IVT to NULL in this case. The DCD header
itself is still needed for detect_imximage_version() to determine the image
version.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Acked-by: Stefano Babic <sbabic@denx.de>
Setup mmu-masters property for the PCIe controllers. This would be
used by the Linux SMMU driver, while setting up stream ID table mappings
for the PCIe devices.
Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This patch rewrites MMU translation table entries. To start, all table
entries are written as "invalid", then "device-ngnrnr" and "normal" are
written to the entries to enable access to specific addresses.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
DEVDISRn registers provides a mechanism for gating clocks of IP blocks
that are not used. Here we implement hwconfig option to allow users
to disable unused peripherals on the board.
For ex. If eSDHC/qDMA/eDMA are unused and with disabled status in dts,
User can enable CONFIG_FSL_DEVICE_DISABLE and set "devdis:esdhc,qdma,edma"
in hwconfig, thus ESDHC controller & eDMA/qDMA will be clock gated to
save more power.
Signed-off-by: Zhuoyu Zhang <Zhuoyu.Zhang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
The emulator with DDR3 model was used during model bringup. DDR4
controllers are used with ls2085a. Drop the DDR4 target defconfig
and enable DDR4 in ls2085a_emu_defconfig.
Signed-off-by: York Sun <yorksun@freescale.com>
Replace the DMACTRL[LE] hack with recommended settings
for ETSECDMAMCR to get the same end effect - obtaining
big-endian buffer descriptors and frame data for eTSEC.
The reset / default value for ETSECDMAMCR is preserved,
excepting the BD and FR bits which are cleared to enable
the BE mode in accordance with the H/W specifications.
Fixes: 52d00a8 "ls102xa: etsec: Add etsec support for LS102xA"
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Acked-by: Alison Wang <alison.wang@freescale.com>
Tested-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
The X-QSGMII-16PORT is a 4xQSGMII/8xSGMII riser card with eighth SerDes
interfaces implemented in PCIe form factor board.
It supports followings
- Card can operate with up to 4 QSGMII lane simultaneously
- Card can operate with up to 8 SGMII lane simultaneously
Add support of X-QSGMII-16PORT riser card.
This patch also take care of back-ward compatiblity with old SGMII rise cards
used on LS2085QDS Platform.
Signed-off-by: King Chung Lo@freescale.com <KingChungLo@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Update 0x33 and 0x35 serdes protocol as per updated SoC document
in array serdes1_cfg_tbl.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
LS2085 targets supports following UART console
LS2085AQDS UART0
LS2085ARDB UART1
LS2085ASim UART0
LS2085AEmu UART0
So update the bootargs as per the default console present at the target
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
ISBC Key Extension feature is not applicable for RAMBOOT
as there is no way to retrieve the CSF Header and validated
IE Key table from SRAM once CPC has been disabled.
The feature is only applicable in case of NOR SECURE BOOT.
Code Cleanup:
The SECURE_BOOT specific defines have been moved from
arch-ls102xa/config.h to
arm/include/asm/fsl_secure_boot.h
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This patch adds a minimal framework for Dickens CCN-504
interconnect configuration - mainly related to adding Clusters/cores
to snoop/DVM domain and setting QoS of the RN-I ports.
LS2085A platform makes use of these configurations to support
better network data performance and to boot a SMP Linux.
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
RTC devices can generate 32KHz output if for
-DS3232 device, EN32KHz bit and BB32KHz bit are set
-DS3231 device, EN32KHz bit is set, BB32KHz bit is don't care
Patch adds rtc_enable_32khz_output() which when called
will enable 32KHz output on 32KHz pin
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Per new requirement, change default core frequency
from previous 1400MHz to 1200MHz to save power.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Convert MPC8540ADS, MPC8541CDS, MPC8544CDS, MPC8548CDS, MPC8555CDS,
MPC8560ADS, MPC8568MDS, MPC8569MDS, MPC8610HPCD to use generic board
structure.
Signed-off-by: York Sun <yorksun@freescale.com>
Recently the FMan Port and MAC compatibles were changed.
This patch aligns the FMan Port and MAC compatibles
to the new FMan device tree binding document.
The FMan device tree binding document can be found in the Linux kernel:
./Documentation/devicetree/bindings/powerpc/fsl/fman.txt
This patch doesn't affect legacy compatibles support.
Signed-off-by: Igal Liberman <igal.liberman@freescale.com>
Tested-by: Xing Lei <xing.lei@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
MPC85xx has been using locked L1 cache as init_ram. L1 cache is a write
through cache on E6500. L2 cache is enabled to to hold the data. This
patch locks/unlocks L2 cache to ensure no data cast out from L2 cache.
Signed-off-by: York Sun <yorksun@freescale.com>
Reported-by: Jeffery Zhu <Jefferry.Zhu@freescale.com>
For e6500 and e5500 SoCs, it was intended to put init_ram address in
ccsr reserved space. It is no longer true since SerDes module took the
space. Move it to another reserved space at CCSR + 0x03c000.
Signed-off-by: York Sun <yorksun@freescale.com>
This should depend on SPL_OF_CONTROL (it is not equivalent to
SPL && OF_CONTROL).
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
This driver actually does nothing but test pinctrl uclass, and
demonstrate how things work.
To try this driver, uncomment /* #define DEBUG */ in the
drivers/pinctrl/pinctrl-sandbox.c, and debug messages will be
displayed.
DRAM: 128 MiB
sandbox pinmux: group = 1 (serial_a), function = 1 (serial)
Using default environment
In: cros-ec-keyb
Out: lcd
Err: lcd
Net: Net Initialization Skipped
eth0: eth@10002000, eth1: eth@80000000, eth5: eth@90000000
=> i2c dev 0
Setting bus to 0
sandbox pinmux: group = 0 (i2c), function = 0 (i2c)
sandbox pinconf: group = 0 (i2c), param = 3, arg = 1
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
This creates a new framework for handling of pin control devices,
i.e. devices that control different aspects of package pins.
This uclass handles pinmuxing and pin configuration; pinmuxing
controls switching among silicon blocks that share certain physical
pins, pin configuration handles electronic properties such as pin-
biasing, load capacitance etc.
This framework can support the same device tree bindings, but if you
do not need full interface support, you can disable some features to
reduce memory foot print. Typically around 1.5KB is necessary to
include full-featured uclass support on ARM board (CONFIG_PINCTRL +
CONFIG_PINCTRL_FULL + CONFIG_PINCTRL_GENERIC + CONFIG_PINCTRL_PINMUX),
for example.
We are often limited on code size for SPL. Besides, we still have
many boards that do not support device tree configuration. The full
pinctrl, which requires OF_CONTROL, does not make sense for those
boards. So, this framework also has a Do-It-Yourself (let's say
simple pinctrl) interface. With CONFIG_PINCTRL_FULL disabled, the
uclass itself provides no systematic mechanism for identifying the
peripheral device, applying pinctrl settings, etc. They must be
done in each low-level driver. In return, you can save much memory
footprint and it might be useful especially for SPL.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
This is useful when we want to bind a device, but do not need the
pointer to the device.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
The TPM is listed in the device tree. Enable the driver and 'tpm' command
so that it can be used.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Christophe Ricard <christophe-h.ricard@st.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
This command provides a few useful tests so enable it for common boards.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Christophe Ricard<christophe-h.ricard@st.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
These tests come from Chrome OS code. They are not particularly tidy but can
be useful for checking that the TPM is behaving correctly. Some knowledge of
TPM operation is required to use these.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Christophe Ricard<christophe-h.ricard@st.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Add a few new functions which will be used by the test command in a future
patch.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Christophe Ricard<christophe-h.ricard@st.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Add a command to display basic information about a TPM such as the model and
open/close state. This can be useful for debugging.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Christophe Ricard <christophe-h.ricard@st.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Convert the tpm_tis_lpc driver to use driver model and update boards which
use it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Christophe Ricard<christophe-h.ricard@st.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Convert the tpm_tis_i2c driver to use driver model and update boards which
use it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Christophe Ricard<christophe-h.ricard@st.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Add a TPM node to the various Chromebooks so that driver can be converted to
driver model.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Christophe Ricard<christophe-h.ricard@st.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Rather then crashing when there is no data, print an error. The error is
printed by the caller to parse_byte_string().
Acked-by: Christophe Ricard <christophe-h.ricard@st.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Convert the sandbox TPM driver to use driver model. Add it to the device
tree so that it can be found on start-up.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Christophe Ricard <christophe-h.ricard@st.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
When a 'tpm' command fails, we set the return code but give no indication
of failure. This can be confusing.
Add an error message when any tpm command fails.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Christophe Ricard<christophe-h.ricard@st.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
I2C chips can support a register offset, with registers accessible by
sending this offset as the first part of any read or write transaction.
Most I2C chips have a single byte offset, thus the offset length is 1.
This provides access for up 256 registers.
However other offset lengths are supported, including 0.
Add a command to provide access to the offset length from the command
line. This allows the offset length to be read or written.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Christophe Ricard<christophe-h.ricard@st.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Add driver model support to the TPM command and the TPM library. Both
support only a single TPM at present.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Christophe Ricard<christophe-h.ricard@st.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Add a new uclass for TPMs which uses almost the same TIS (TPM Interface
Specification) as is currently implemented. Since init() is handled by the
normal driver model probe() method, we don't need to implement that. Also
rename the transfer method to xfer() which is a less clumbsy name.
Once all drivers and users are converted to driver model we can remove the
old code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Christophe Ricard<christophe-h.ricard@st.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Use a _US suffix for microseconds and a _MS suffic for milliseconds. Move
all timeouts and delays into one place. Use mdelay() instead of udelay()
where appropriate.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Christophe Ricard <christophe-h.ricard@st.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Some definitions are in the C file and some are in the header file. Move
everything into the header file for consistency and to reduce clutter.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
There are too many structures storing the same sort of information. Move the
fields from struct tpm into struct tpm_chip and remove the former struct.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
There are too many structures storing the same sort of information. Move the
fields from struct tpm_dev into struct tpm_chip and remove the former
struct.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
This function is misnamed since it only applies to a single driver. Merge
its fields into its parent.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
The function methods in struct tpm_vendor_specific just call local functions.
Change the code to use a direct call.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
The current Infineon I2C TPM driver is written in two parts, intended to
support use with other I2C devices. However we don't have any users and the
Atmel I2C TPM device does not use this file.
We should simplify this and remove the unused abstration. As a first step,
move the code into one file.
Also the name tpm_private.h suggests that the header file is generic to all
TPMs but it is not. Rename it indicate that it relates only to this driver
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Add new Kconfig options for TPMs in preparation for moving boards to use
Kconfig for TPM configuration.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Christophe Ricard<christophe-h.ricard@st.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
The address of the I2C TPM is now defined in the device tree so there is no
need for the CONFIG options.
Remove them from the README and board config to avoid confusion.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Christophe Ricard <christophe-h.ricard@st.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
If board uses downstream Chrome OS U-Boot as first stage
bootloader and upstream version is chained second stage,
1.1V is minimum voltage borderline.
Signed-off-by: Misha Komarovskiy <zombah@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Make "Generic Driver Options" menu show on the top in the Kconfig.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Add Kconfig entries for the simple-bus driver, both for U-Boot
and for SPL. The simple-bus is enabled by default in U-Boot and
disabled by default in SPL to preserve the original behavior.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
Modified to fit on top of Masahiro's $(SPL) setup:
Signed-off-by: Simon Glass <sjg@chromium.org>
This is a convenient way for a driver to get the hardware address of a
device, when regmap or syscon are not being used. Change existing callers
to use it as an example to others.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
This can be simply written with list_for_each_entry(), maybe
this macro was not necessary in the first place.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
Stout is an entry level development board based on R-Car H2 SoC (R8A7790)
This commit supports the following peripherals:
- SCIFA, I2C, Ethernet, QSPI, SDHI0/2, CPLD
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Add SCIFA console interface for R-Car Gen2 SoCs.
SCIFA has different registers offsets and sizes then SCI. Hence it needs to
put it's macro definitions separately.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Fix gpio_read: gpio input (INDT) and gpio output (OUTDT) registers
have different offset. gpio_read must be performed from INDT.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Originally a timeout value of 2 seconds was used regardless of the size
of data to be transfered. This prevented slow devices from working
correctly while there was no much gain for faster devices, e.g. it takes
3708ms for a transfer of uImage of size 1899008 bytes.
Signed-off-by: Yousong Zhou <yszhou4tech@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
On the A31s the RTC is by default secured. Thus when u-boot
loads the kernel in non-secure world, the RTC is unavailable. The
SoC has a TrustZone Protection Controller, which can be used to
enable non-secure access to the RTC.
On the A31 the TZPC doesn't seem to do anything, i.e. changes to
its register contents do not affect access to the RTC.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The boards are sorted by SoC, move the Mele_A1000G_quad entry to the list
of sun6i boards where it belongs.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The inet98v_rev2 is a pcb used in generic A13 based tablets. It features
volume buttons, a power barrel, micro-usb otg, headphone connector and
a power button.
The dts file is identical to the one submitted to the upstream kernel.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The inet97fv2 is a board found in the first generation of cheap allwinner
A10 based 7" tablets.
Note that this patch does not add a dts file as we already have one from
our dts syncs with the kernel.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Add otg id pin configuration, this speeds up bootup when no host cable
is plugged into the otg port.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Make CONFIG_SYS_NAND_U_BOOT_OFFS configurable through Kconfig, just like
SYS_NAND_BUSWIDTH_16BIT this is only enabled on some SoCs using depends,
to avoid double defining it for SoCs which have not yet moved to Kconfig
for this.
Having this in Kconfig is useful because this is something which may
differ from one board to the other even when using the same SoC.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Scott Wood <scottwood@freescale.com>
Some status flags remain set until you explicetly clear the bit
in the status register.
Fix the SPL implementation to avoid false positive.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
[hdegoede@redhat.com: Port from v2015.07 to v2015.10]
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
We only ever use syndrome mode for the partitions which contain the SPL,
as that is required for the BROM to be able to read the SPL.
Instead of using some arbritray limit for deciding whether or not to
use syndrome, be smart and check if u-boot-dtb.bin is directly behind
the SPL, if it is not then it is on its own partition and we should not
use syndrome.
Note the reason why we only use syndrome mode for the SPL is because it
comeswith weaker randomization, introducing a risk for more bit errors,
so we want to avoid it when possible.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
We eventually want to add full nand support, since it makes no sense
to build SPL with nand support and u-boot without, or the other way
around, a single option will suffice.
Renaming the Kconfig option now makes things easier when we add full
nand support in the future.
The "obj-$(CONFIG_NAND_SUNXI) += sunxi_nand_spl.o" is moved to an
"ifdef CONFIG_SPL_BUILD" block in the Makefile.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The BROM does not care / use bad page markings, instead it deals with
any bad pages in the first erase-block by simply trying to load "boot0"
from the next erase-block.
This commit implements the same strategy for the sunxi spl nand code,
allowing it to boot from the backup boot partition when the main boot
partition is bad (tested by erasing the main boot partition).
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Auto detect the nand configuration parameters, like the BROM does.
This allows us to get rid of various Kconfig settings, and is
necessary to support generic boards like the mk802 which have seen
many production runs with different nands.
The full blown u-boot/kernel nand driver uses the nand id to determine
this info, for the SPL we do as the BROM does and simply try a few
standard configs.
Note the table only contains configs which are known to actually be used,
rather then all the configs the BROM tries. This means that it may need
to be updated in the future as we add support for nand on more boards.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Parametrize the lowlevel nand_read_page function, instead of directly
using the CONFIG_foo settings for page-size, etc. there and add a few
wrappers / helper functions for calling it.
This is a preparation patch for adding auto-detecting of the nand
parameters like the BROM does.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Properly config page-size in the nand ctl register, it seems that things
work fine without doing this, but still lets play it safe and properly
set the page-size.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Other then having a few less chip-select lines the nand controller
on sun4i, sun5i and sun7i is identical.
Note this patch also muxes GPC7 to the NAND on sun7i where as before
it was not muxed this way. GPC7 is a standard NAND pin, so it should
always be muxed to the NAND when in use.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Sync the code for figuring out the ecc_mode and ecc_offset with the linux
kernel v4.1. Keeping this in sync seems like a good idea in general, and
it fixes / adds support for ecc strengths of 56, 60 and 64 bits.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
We are using dma, so we should flush the cache before starting the dma,
and invalidate it once the dma is done.
Things are working without this by mostly luck, but lets not rely on that.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Turn off the nand and dma clocks when we're done with the nand, this
puts the nand and dma controllers back into a clean state for when the
kernel boots.
Without this the kernel will not boot properly when it is built with
dma-controller support.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
We use DMA for nand data transfers in the SPL, so make sure the DMA
controller is enabled.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Use SYS_NAND_SELF_INIT and only setup the pinmux and clocks when we are
actually using the nand.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
In syndrome mode we set the NFC_SEQ bit in the command register, so the
spare-area register is not used. Also the value currently being written is
actual wrong, the ecc sits at "column + CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE"
not just CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE.
So the current code only serves to confuse the user -> remove it.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
There is no need to reset the nand chip for every ecc-block read.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
nand_spl_load_image() always gets called with either CONFIG_SYS_TEXT_BASE
or spl_image.load_addr as destination, both of which are properly aligened,
and have plenty of space for "overshooting" up to
CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE bytes, as we read in
CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE bytes chunks.
This saves CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE (typically 1k) in
SPL size, which is a lot on the total 24k we have.
Note this changes the dma destination from SRAM to DRAM, so this patch
updates the DDMA_DST_TYPE bits in the dma controller cfg0 reg accordingly.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
CONFIG_SPL_NAND_SUPPORT gets used via IS_ENABLED so it must be defined
to 1, rather then just being defined.
While at remove 2 other unused NAND related defines from sunxi-common.h.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Add CONFIG_MMC0_CD_PIN to various boards, this stops the SPL from still
trying to access the sdcard when there is none (e.g. when booting from
nand).
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
With the unified / cleaned up default display output selection changes,
which were done as part of adding composite video out support, our
example LCD_MODE line in the A13-OLinuxIno defconfigs causes the display
code to setup a LCD console by default, rather then a VGA console.
Given that the LCD console is only useful for people who have hooked up
the exact lcd-panel from the config, while most people will not have any
lcd panel connected to these boards, this is not a good default.
Dropping the LCD_MODE line which was intended as an example fixes this,
instead add a link to the LCD_MODE help text pointing to
http://linux-sunxi.org/LCD which contains the removed and other example
modes.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Drop the no longer accurate part of the USB_MUSB_SUNXI Kconfig help text,
since the musb-host code now supports the device-model, ehci and musb in
host mode can both be enabled at the same time without issues.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The gt90h is a pcb found in generic 9" tablets with an A23 soc, 1G RAM
and 8G nand, rtl8723as usb wifi, 1 micro usb port and 1 micro sd slot.
The pmic setup on this board is somewhat special, dcdc2 MUST be set
to 1.1V instead of the usual 1.2V otherwise the board is very unstable.
aldo1 is used to power the micro sd slot, dldo1 is used for wifi.
This commit adds a defconfig + dts (as submitted to the kernel) for
the gt90h-v4 pcb.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Allow specifying the axp221 dcdc2 voltage via Kconfig, this is necessary
because on some boards the 1.2V default does not work reliable.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Discard the empty video_set_lut function from platform video
drivers.
This commit "69d275458893eaec35229b589092c2a6bde5440f" introduces
a weak function video_set_lut, so we do not need an strong function
in platform drivers, which does nothing.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Initial version of DTSI for ProXstream2 and PH1-LD6b and DTS for
PH1-LD6b reference board.
Import from Linux with some adjustments:
- Use SPDX-License-Identifier
- Add clock-frequency to serial nodes
- Drop unusable nodes from -ref.dts
While I am here, sort Makefile entries alphabetically.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Initial version of UniPhier PH1-Pro5 device tree.
(Imported from Linux with adjustment for SPDX License Identifier)
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This commit imports device tree updates from Linux. It eventually
adds pinctrl-related nodes and properties.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This driver is enabled only for UniPhier SoCs and ARCH_UNIPHIER now
selects OF_CONTROL and SPL_OF_CONTROL.
This driver no longer needs to support platform data configuration.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Device Tree really improves code maintainability and is now
available for SPL too.
This is the state-of-the-art implementation in U-boot.
The board files (platform data) are no longer needed.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Since commit 2580a2a7e7 ("mtd: nand: Increase max sizes of OOB and
Page size"), three boards (ph1_ld4, ph1_pro4, ph1_sld8) fail to build
with the following error message:
arm-linux-gnueabi-ld.bfd: SPL image plus BSS too big
They compile drivers/mtd/nand/denali_spl.c and it has a page_buffer
as static data:
static uint8_t page_buffer[NAND_MAX_PAGESIZE];
This buffer required 8KB in .bss section before that commit and now
it has been increased to 16KB. Given limited code/memory size for SPL,
it is not a good idea to allocate a page buffer statically. In the
first place, the load address 'dst' can be used as a page buffer.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Otherwise we get:
tools/atmelimage.c:134:3: warning: format ‘%d’ expects argument of type ‘int’, but argument 2 has type ‘size_t’ [-Wformat=]
debug("atmelimage: interrupt vector #%d is 0x%08X\n", pos+1,
^
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Now that we have separate function to enable USB clocks, remove
enabling USB clocks from enable_basic_clocks(). Now board_usb_init()
should take care to invoke enable_usb_clocks() for enabling
USB clocks.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
invoke enable_usb_clocks during board_usb_init and disable_usb_clocks
during board_usb_exit to enable and disable clocks respectively.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Added functions to enable and disable USB clocks which can be invoked
during USB init and USB exit respectively.
Cc: Roger Quadros <rogerq@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>
Cc: Nishanth Menon <nm@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Added functions to enable and disable USB clocks which can be invoked
during USB init and USB exit respectively.
Cc: Roger Quadros <rogerq@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>
Cc: Nishanth Menon <nm@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Implemented board_usb_init(), board_usb_cleanup() and
usb_gadget_handle_interrupts() in omap5 board file that
can be invoked by various gadget drivers.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Implemented board_usb_init(), board_usb_cleanup() and
usb_gadget_handle_interrupts() in beagle_x15 board file that
can be invoked by various gadget drivers.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
The usbboot environment variable has 'usb start' command but
doesn't have the corresponding 'usb stop' command. This breaks
usb peripheral mode if tried after 'run usbboot' fails to load
the images in usb host mode.
Fix it here by adding 'usb stop' command in usbboot env.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
vbus_id_status is initialized in board_usb_init. So remove it
while creating dwc3_device objects.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Added support to power on/power off the second USB PHY present in
DRA7xx and AM57xx.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Enabled clocks for the second dwc3 controller and second USB PHY present in
DRA7.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Writing "0x00" to the USBOTGSS_IRQENABLE_SET_MISC and
USBOTGSS_IRQENABLE_SET_0 doesn't disable the interrupts. Used
USBOTGSS_IRQENABLE_CLR_MISC and USBOTGSS_IRQENABLE_CLR_0 instead.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
The SOURCE_DATE_EPOCH mechanism for reproducible builds require some date(1)
with -d switch to print the relevant date and time strings of another point of
time.
In other words it requires some date(1) that behaves like the GNU date(1) [1].
The BSD date(1) [2] on the other hand has the same switch but with a different
meaning.
Respect this and check the date(1) abilities before usage, error on non
working version. Use the well known pre- and suffixes for the GNU variant of
a tool on *BSD hosts to search for a working date(1) version.
[1] http://man7.org/linux/man-pages/man1/date.1.html [2]
http://www.freebsd.org/cgi/man.cgi?query=date
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Commit 181bd9dc61 introduced Kconfig selection
for SYS_PROMPT. When applying the new picosam9g45 board this change slipped
through, adopt it.
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
This fixes the following genboardscfg.py warnings:
---8<---
WARNING: no status for 'at91sam9g20ek_2mmc'
WARNING: no maintainers for 'at91sam9g20ek_2mmc'
--->8---
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
This fixes following genboardscfg.py warning:
---8<---
WARNING: no status for 'at91sam9rlek_mmc'
WARNING: no maintainers for 'at91sam9rlek_mmc'
--->8---
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
The SYS_BOOT-based fallback shouldn't only check for one of the conditions of
use and then let the switch/case handle each boot device without enforcing the
conditions for each type of boot device again.
For instance, this behaviour would trigger the fallback for UART when
BOOT_DEVICE_UART is defined, CONFIG_SPL_YMODEM_SUPPORT is enabled (which should
be a show-stopper) and e.g. BOOT_DEVICE_USB is enabled and not
CONFIG_SPL_USB_SUPPORT.
Separating the logic for USB and UART solves this.
In addition, this adds support for more peripheral devices (USBETH and CPGMAC)
to the fallback mechanism. Note that the USBETH boot device should always be
different from the USB boot device (each should match a different bootrom
handoff case).
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Acked-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Tested-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Various U-Boot adoptions/extensions to MTD/NAND/UBI did not take buffer
alignment into account which led to failures of the following form:
ERROR: v7_dcache_inval_range - start address is not aligned - 0x1f7f0108
ERROR: v7_dcache_inval_range - stop address is not aligned - 0x1f7f1108
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Scott Wood <scottwood@freescale.com>
[trini: Add __UBOOT__ hunk to lib/zlib/zutil.c due to malloc.h in common.h]
Signed-off-by: Tom Rini <trini@konsulko.com>
This patch brings the following changes to the x600 board support:
- Add USB EHCI support
- Add VFAT support for USB key file access
- Increase malloc size (for UBI / UBIFS usage)
- Enable Thumb mode to save some image space
- Remove unreferenced CONFIG_STACKSIZE
- Remove unreferenced CONFIG_SPL_NO_PRINTF
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Vipin Kumar <vk.vipin@gmail.com>
The designware ethernet driver supports d-cache now. So there is nothing
stopping us now to enable the caches completely on SPEAr.
Tested on SPEAr600 x600 board.
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Vipin Kumar <vk.vipin@gmail.com>
The SPL implementation for SPEAr600 is older than the common SPL
infrastructure. This patch now moves the SPEAr600 SPL over to the
common SPL code.
Tested on the only SPEAr board that currently uses SPL in mainline
U-Boot, the x600.
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Vipin Kumar <vk.vipin@gmail.com>
Booting SPEAr600 eval board doesn't work with current mainline U-Boot. With
this patch the low-vector bit is left to '0'. Resulting in the common
relocation of the vectors to 0 (SDRAM) to work correctly.
Tested on the SPEAr600 EVB.
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Vipin Kumar <vk.vipin@gmail.com>
ARM supported speeds and init value of core_pll for SDP1200
are programmed wrong as part for the device speed cleanups.
Fixing it here.
Thanks to "Vitaly Andrianov <vitalya@ti.com>" for bisecting this issue
Fixes: c37ed9f11b61 ("ARM: keystone2: Fix dev and arm speed detection")
Tested-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
MLO(NAND/MMC boot image), is used for all the ks2 platforms.
Enabling it in config.mk so that these images will be automatically
built upon calling make. u-boot-spi.gph is already the build target,
so not including here.
Reported-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
NAND boot mode, ROM expects an image with a gp header in the
beginning and an 8bytes filled with zeros at the end. The same is
true for SD boot on K2G platforms but the file name should be MLO.
Renaming u-boot-nand.gph to MLO, so that same image can be used for
NAND and SD boots. And also not including all the u-boot only images
under CONFIG_SPL_BUILD.
Reported-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Keystone has build rules introduced by commit ef509b9063 ("k2hk: add
support for k2hk SOC and EVM") and commit 0e7f2dbac6 ("keystone: add
support for NAND gpheader image").
These are not reused by other platforms for the build, hence there is no
clear benefit is maintaining them in the generic makefile as a build
target. move these to the keystone specific make option
Original idea of using config.mk by Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Currently u-boot stack is defined at the beginning of MSMC RAM.
This is a problem for uart boot mode as ROM downloads directly to
starting of MSMC RAM.
Fixing it by moving stack to the end of u-boot section and shifting
SYS_TEXT_BASE to the start of MSMC RAM.
Updated division of MSMC RAM is shown below:
-----------------------------------------
| | | |
| U-Boot text |U-Boot | SPL text |
| download | Stack | Download + |
| | | SPL_BSS + |
| | | SPL_STACK |
-----------------------------------------
[1] [2] [3] [4]
[1] SYS_TEXT_BASE (Start of MSMC RAM)
[2] SPL_TEXT_BASE - GBL_DATA_SIZE
[3] SPL_TEXT_BASE
[4] END of SPL
[1] + [2] is at least 1M on all platforms, so no chance of overlap.
Reviewed-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
The set_default_env() function from env_common.c expects either
a fully formatted error msg, e.g.: "## Resetting to default environment\n"
or an error msg prefixed with an !, in which case it will format it.
Fix the init_mmc_for_env() error messages to be prefixed with a !
this changes the bootup-log on sunxi when no mmc card is found from:
MMC: SUNXI SD/MMC: 0
No MMC card foundIn: serial
Out: serial
To:
MMC: SUNXI SD/MMC: 0
*** Warning - No MMC card found, using default environment
In: serial
Out: serial
Which clearly is how things should look.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
This should use the align parameter, not bytes. Natural alignment is one
use case but should not be the only one supported by this function.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Corresponds to ba71a0e (Fix _parse_block() 'parent' documentation re.
ifs.) from upstream, just adding the SPDX tag.
Has performance improvements, code cleanup, Python 3 support, and various
small fixes, including the following:
- Unset user values when loading a zero-byte .config. (5e54e2c)
- Ignore indented .config assignments. (f8a7510)
- Do not require $srctree to be set for non-kernel projects. (d56e9c1)
- Report correct locations in the presence of continuation lines.
(0cebc87)
Signed-off-by: Ulf Magnusson <ulfalizer@gmail.com>
DP83865 ethernet phy used on DRA74x-evm is quirky and the datasheet
provided IODELAY values for standard RGMII phys do not work.
Silicon Revision(SR) 2.0 provides an alternative bit configuration
that allows us to do a "gross adjustment" to launch the data off a
different internal clock edge. Manual IO Delay overrides are still
necessary to fine tune the clock-to-data delays. This is a necessary
workaround for the quirky ethernet Phy we have on the platform.
NOTE: SMA registers are spare "kitchen sink" registers that does
contain bits for other workaround as necessary as well. Hence the
control for the same is introduced in a generic SoC specific, board
generic location.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Silicon revision 2.0 has new signal routing hence has an updated set of
iodelay parameters to be used. Update the configuration for the same.
Padmux remains the same.
Based on data from VayuES2_EVM_Base_Config-20150807.
NOTE: With respect to the RGMII values, the Manual IODelay values
are used for the fine adjusments needed to meet the tight RGMII
specification.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Add support for detection of ES2.0 version of DRA7 family of
processors. ES2.0 is an incremental revision with various fixes
including the following:
- reset logic fixes
- few assymetric aging logic fixes
- MMC clock rate fixes
- Ethernet speed fixes
- edma fixes for mcasp
[ravibabu@ti.com: posted internal for an older bootloader]
Signed-off-by: Ravi Babu <ravibabu@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
When building with SOURCE_DATE_EPOCH the timezone is in UTC. When
building normally the timezone is taken from the build machine's locale
setting.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Paul Kocialkowski <contact@paulk.fr>
Tested-by: Andreas Bießmann <andreas.devel@googlemail.com>
Build without CONFIG_SPL_SERIAL_SUPPORT does not print the cpu freq.
I have seen this in the odroid U3 board, where on boot one sees this:
CPU: Exynos4412 @ GHz
instead of:
CPU: Exynos4412 @ 1 GHz
I am assuming that this change was done to get rid of compiler
warnings related to unused variables when building with
CONFIG_SPL_SERIAL_SUPPORT not being defined in an SPL build.
Signed-off-by: Suriyan Ramasami <suriyan.r@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Raspberry Pi by default loads the FDT to 0x00000100 so set fdt_addr_r to
match and move scriptaddr to 0x02000000 to avoid clobbering the FDT.
Signed-off-by: Jonathan Liu <net147@gmail.com>
GCC 5.1 starts warning for comparisons such as !a > 0, assuming that the
negation was meant to apply to the whole expression rather than just the
left operand.
Indeed the comparison in the FIT loadable code is confusingly written,
though it does end up doing the right thing. Rewrite the condition to be
more explicit, that is, iterate over strings until they're exhausted.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
In order to make a pci uart device node to be properly bound to its
driver, we need make sure its parent node has a compatible string
which matches a driver that scans all of its child device nodes in
the device tree.
Change all pci bridge nodes under root pci node to use "pci-bridge"
compatible driver, as well as corresponding <reg> properties to
indicate its devfn. At last, adding "u-boot,dm-pre-reloc" to each
of these nodes for driver model to initialize them before relocation.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
The device might have already been probed during the call to
device_probe() on its parent device (e.g. PCI bridge devices).
In its parent device's probe routine, it might probe all of
its child devices via device_probe() thus the codes reenter
device_probe_child(). To support code reentrancy, test these
allocated memory against NULL to avoid memory leak, and return
to the caller if dev->flags has DM_FLAG_ACTIVATED set after
device_probe() returns, so that we don't mess up the device.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
If there is no pci device listed in the device tree,
don't bother scanning the device tree.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
So far we only enabled one legacy serial port on the SMSC LPC47m
superio chipset on Intel Crown Bay board. As the board also has
dual PS/2 ports routed out, enable the keyboard controller which
is i8042 compatible so that we can use PS/2 keyboard and mouse.
In order to make PS/2 keyboard work with the VGA console, remove
CONFIG_VGA_AS_SINGLE_DEVICE. To boot Linux kernel with PIC mode
using PIRQ routing table, adjust the mask in the device tree to
reserve irq12 which is used by PS/2 mouse.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
So far if CONFIG_VGA_AS_SINGLE_DEVICE is not defined, the VGA device
will try to initialize a keyboard device (for x86, it is i8042). But
if i8042 controller initialization fails (eg: there is no keyboard
connected to the PS/2 port), drv_video_init() just simply returns.
This kills the opportunity of using a usb keyboard later with the vga
console, as the vga initialization part is actually ok, only keyboard
part fails. Change the code logic to allow this.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
The existing i8042 keyboard controller driver has some issues.
First of all, it does not issue a self-test command (0xaa) to the
controller at the very beginning. Without this, the controller
does not respond to any command at all. Secondly, it initializes
the configuration byte register to turn on the keyboard's interrupt,
as U-Boot does not normally allow interrupts to be processed.
Finally, at the end of the initialization routine, it wrongly
sets the controller to disable all interfaces including both
keyboard and mouse.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
- Rename CamelCase variables to conform U-Boot coding convention
- Rename wait_until_kbd_output_full() to kbd_output_full()
- Change to use macros for i8042 command and control register bits
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Reorder those static function so that their declarations
can be removed.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
This function can return an error. Correct the detection of this error so
that it works even with large 32-bit addresses.
The return value is set up for returning an I/O address but the function is
also used to return a memory-mapped address. Adjust the return code to make
this work.
Also add a bit more debugging.
Signed-off-by: Simon Glass <sjg@chromium.org>
These calls seem to be incorrect. The function expects an I/O address but
the existing callers pass the value at an I/O address. Fix it.
Signed-off-by: Simon Glass <sjg@chromium.org>
These functions are defined by macros so do not show up with grep. Add
a comment to help.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
These GPIOs are accessible on the pin header. Add pinctrl settings for them
so that we they can be adjusted using the 'gpio' command.
Signed-off-by: Simon Glass <sjg@chromium.org>
The DSDT table contains a bytecode that is executed by a driver in the kernel.
Signed-off-by: Saket Sinha <saket.sinha89@gmail.com>
Tested with QEMU '-M q35'
Tested-by: Bin Meng <bmeng.cn@gmail.com>
This patch mainly adds ACPI support to QEMU.
Verified by booting Linux kernel on QEMU Q35.
Signed-off-by: Saket Sinha <saket.sinha89@gmail.com>
Minor whitespace fixes and dropped mention of i440FX in commit message:
Signed-off-by: Simon Glass <sjg@chromium.org>
Implement write_acpi_table() to create a minimal working ACPI table.
This includes writing FACS, XSDT, RSDP, FADT, MCFG, MADT, DSDT & SSDT
ACPI table entries.
Use a Kconfig option GENERATE_ACPI_TABLE to tell U-Boot whether we need
actually write the APCI table just like we did for PIRQ routing, MP table
and SFI tables. With ACPI table existence, linux kernel gets control of
power management, thermal management, configuration management and
monitoring in hardware.
Signed-off-by: Saket Sinha <saket.sinha89@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tidied up whitespace and aligned some tabs:
Signed-off-by: Simon Glass <sjg@chromium.org>
In pci_uclass_child_post_bind(), bdf is extracted from fdt_pci_addr.
Mask bus number before save it to pplat->devfn.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
When there is no valid compatible string in current list,
we should advance to next one in the compatible string list.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Add an api to enable and configure the integrated keyboard controller
on SMSC LPC47m superio chipset. It also adds several macros to help
future extension.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Per Intel FSP specification, we should call FSP notify API to
inform FSP that PCI enumeration has been done so that FSP will
do any necessary initialization as required by the chipset's
BIOS Writer's Guide (BWG).
Unfortunately we have to put this call here as with driver model,
the enumeration is all done on a lazy basis as needed, so until
something is touched on PCI it won't happen.
Note we only call this after U-Boot is relocated and root bus has
finished probing.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
It turns out that calling fsp_init_phase_pci() in arch_misc_init()
is subject to break pci device drivers as with driver model, when
the bus enumeration happens is not deterministic.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
With dm pci conversion, pci config read/write in unprotect_spi_flash()
silently fails as at that time dm pci is not ready and bus enumeration
is not done yet. Actually we don't need to do this in that early phase,
hence we delay this call to arch_misc_init().
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Add some comments in start.S for the fact that with FSP U-Boot
actually enters the code twice. Also change to use fsp_init()
and fsp_continue for accuracy.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
After fsp_init() returns, the stack has already been switched to a
place within system memory as defined by CONFIG_FSP_TEMP_RAM_ADDR.
Enlarge the size of malloc() pool before relocation since we have
plenty of memory now.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Move x86_fsp_init() call after initf_malloc() so that we can fix up
the gd->malloc_limit later.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
On some platforms pci devices behind bridge need to be probed (eg:
a pci uart on recent x86 chipset) before relocation. But we won't
bind all devices found during the enumeration. Only devices whose
driver with DM_FLAG_PRE_RELOC set will be bound. Any other generic
devices except bridges won't be bound.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
When ifdtool collates the microcode into one place it effectively creates
a copy of the 'data' properties in the device tree microcode nodes. This
is wasteful since we now have two copies of the microcode in the ROM.
To avoid this, remove the microcode data from the device tree and shrink it
down. This means that there is only one copy and the overall ROM space used
by the microcode does not increase.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
The Intel Firmware Support Package (FSP) requires that microcode be provided
very early before the device tree can be scanned. We already support adding
a pointer to the microcode data in a place where early init code can access.
However this just points into the device tree and can only point to a single
lot of microcode. For boards which may have different CPU types we must
support multiple microcodes and pass all of them to the FSP in one place.
Enhance ifdtool to scan all the microcode, place it together in the ROM and
update the microcode pointer to point there. This allows us to pass multiple
microcode blocks to the FSP using its existing API.
Enable the flag in the Makefile so that this feature is used by default for
all boards.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
The code to set up the microcode pointer in the ROM shares almost nothing
with the write_uboot() function.
Move it into its own function so it will be easier to extend.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Since U-Boot and its device tree can grow we should check that it does not
overlap the regions above it. Track the ROM offset that U-Boot reaches and
check that other regions (written after U-Boot) do not interfere.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Intel FSP has the capability to walk through the microcode blocks
which are passed as the TempRamInit() parameter from U-Boot and
finds the most appropriate microcode which is suitable for the cpu
on which it is running. Now we've seen several steppings for Intel
BayTrail series processors, adding those microcodes to the Intel
BayleyBay and MinnowMax board device tree files.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
This commit adds the microcode blob for BayTrail-I D0 stepping,
CPUID signature 30679h.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
This is incorrect since we require the -m parameter to the microcode tool.
Update the two examples to show this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The doc has a misleading 'make menuconfig' when building the EFI
application and payload. Clarify this and also update information
on test with QEMU.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Currenlty we only set up video framebuffer when VIDEO_VESA driver is
used. With coreboot, VIDEO_COREBOOT driver is used instead. Since we
already saved VESA mode in the VIDEO_COREBOOT driver, now we can also
set up video framebuffer for coreboot before loading Linux kernel.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
When booting as a coreboot payload, the framebuffer details are
passed from coreboot via configuration tables. We save these
information into vesa_mode_info structure for future use.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
It looks that x86 chipset always contains a host bridge at pci
b.d.f 0.0.0, so enable this for all boards.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
When booting as a coreboot payload, we don't need write any
configuration tables as coreboot does that for us.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Some platforms may have >=4GiB memory, so we need make U-Boot report
such configuration correctly when booting as the coreboot payload.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Now that we have generic routine to calculate relocation address,
remove the x86 specific one which is now only used by coreboot.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
coreboot has some extensions (type 6 & 16) to the E820 types.
When we detect this, mark it as E820_RESERVED.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Increase lib_sysinfo memrange entry number to 32 to sync with coreboot.
This allows a complete E820 table to be reported to the kernel, as on
some platforms (eg: Bayley Bay) having only 16 entires does not cover
all the memory ranges.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
With recent EFI support, the entry point address of coreboot payload
was changed. Now we update the address to use _x86boot_start, which
is the same one for EFI.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
commit 6497e37 "net: e1000: Support 64-bit physical address" causes
compiler warnings on 32-bit U-Boot build below.
drivers/net/e1000.c: In function 'e1000_configure_tx':
drivers/net/e1000.c:4982:2: warning: right shift count >= width of type [enabled by default]
drivers/net/e1000.c: In function 'e1000_configure_rx':
drivers/net/e1000.c:5126:2: warning: right shift count >= width of type [enabled by default]
This commit fixes the build warnings.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Follow linux dma flow:
Before DMA read, be sure to invalidate the cache over the address
range of DMA buffer to prevent cache coherency problems.
After DMA read, invalidate dcache again.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Tim Harvey <tharvey@gateworks.com>
If ecc chunk data size is 512 and oobsize is bigger than 512, there is
a chance that block_mark_bit_offset conflicts with bch ecc area.
The following graph is modified from kernel gpmi-nand.c driver with
each data block 512 bytes. We can see that Block Mark conflicts with
ecc area from bch view. We can enlarge the ecc chunk size to avoid
this problem to those oobsize which is larger than 512.
| P |
|<----------------------------------------------------------------->|
| |
| (Block Mark) |
| P' | | | |
|<--------------------------------------------------->| D | | O'|
| |<--------->| |<->|
V V V V V
+---+--------------+-+--------------+-+--------------+-+----------+-+---+
| M | data |E| data |E| data |E| data |E| |
+---+--------------+-+--------------+-+--------------+-+----------+-+---+
^ ^
| O |
|<---------------->|
P : the page size for BCH module.
E : The ECC strength.
G : the length of Galois Field.
N : The chunk count of per page.
M : the metasize of per page.
C : the ecc chunk size, aka the "data" above.
P': the nand chip's page size.
O : the nand chip's oob size.
O': the free oob.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Tested-By: Tim Harvey <tharvey@gateworks.com>
This patch enables NAND support on the Marvell Armada XP
DB-MV784MP-GP eval board.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Peter Morrow <peter@senient.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Update the NAND code to match Linux v4.1. The previous sync was
from Linux v3.15 in commit 4e67c57125.
CONFIG_SYS_NAND_RESET_CNT is removed, as the upstream Linux code now
has its own timeout. Plus, CONFIG_SYS_NAND_RESET_CNT was undocumented
and not selected by any board.
Signed-off-by: Scott Wood <scottwood@freescale.com>
In addition to mtd_block_isbad(), which checks if a block is bad or
reserved, it's needed to check if a block is reserved only (but not
bad). This commit adds an MTD interface for it, in a similar fashion to
mtd_block_isbad().
While here, fix mtd_block_isbad() so the out-of-bounds checking is done
before the callback check.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Pekon Gupta <pekon@ti.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
[scottwood: Cherry-picked from Linux 8471bb73ba10ed67]
Signed-off-by: Scott Wood <scottwood@freescale.com>
Add optional LCD support. Note that depending on the toolchain used
one might have to drop some other features to stay within the 0x40000
size limit.
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Looks like the define CONFIG_SYS_LCD_PXA_NO_L_BIAS is not used anywhere
else throughout the U-Boot sources any more. Drop it.
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Cleaning up order of include files by sorting them alphabetically
keeping in mind to leave common.h on top.
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Cleaning up order of include files by sorting them alphabetically
keeping in mind to leave common.h on top.
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Cleaning up order of include files by sorting them alphabetically
keeping in mind to leave common.h on top.
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Cleaning up order of include files by sorting them alphabetically
keeping in mind to leave common.h on top.
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Cleaning up order of include files by sorting them alphabetically
keeping in mind to leave common.h on top.
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
This patch moves pxa to the common timer functions added in commit
8dfafdd - Introduce common timer functions <Rob Herring>
The (removed) pxa timer code (specifically __udelay()) could deadlock at
the 32-bit boundary of get_ticks(). get_ticks() returned a 32-bit value
cast up to a 64-bit value. If get_ticks() + tmo in __udelay() crossed
the 32-bit boundary, the while condition became unconditionally true and
locked the processor. Rather than patch the specific pxa issues, simply
move everything over to the common code.
Signed-off-by: Andrew Ruder <andrew.ruder@elecsyscorp.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@konsuiko.com>
Since commit 3ff46cc42b ("arm: relocate the exception vectors")
pxa does not boot anymore.
Add a specific relocate_vectors macro that skips the vector relocation,
as the pxa SoC does not provide RAM at the high vectors address
(0xFFFF0000), and (0x00000000) maps to ROM.
This allows pxa to boot again.
Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Andrew Ruder <andrew.ruder@elecsyscorp.com>
Conflicts:
configs/socfpga_arria5_defconfig
configs/socfpga_cyclone5_defconfig
configs/socfpga_socrates_defconfig
Merged these by hand and re-ran savedefconfig on them.
Signed-off-by: Tom Rini <trini@konsulko.com>
Pull out the ArriaV SoCDK clock config from ancient Altera U-Boot
"rel_socfpga_v2013.01.01_15.05.01_pr" and implant those values into
mainline to get a booting ArriaV SoCDK.
Signed-off-by: Marek Vasut <marex@denx.de>
Synchronise the config options with Cyclone V SoCDK and other boards.
This enables ethernet on the ArriaV SoCDK.
Signed-off-by: Marek Vasut <marex@denx.de>
Add the missing DT nodes, so that ArriaV SoCDK can boot from SD
card. The SD card must be in slot J5 and BSEL must be 0x5.
Signed-off-by: Marek Vasut <marex@denx.de>
Add "bank-name" property to each GPIO bank to give it unique name.
The approach here is exactly the same as with the "regulator-name"
property for regulators.
Signed-off-by: Marek Vasut <marex@denx.de>
Add driver for the DesignWare APB GPIO IP block.
This driver is DM capable and probes from DT.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Now that we're actually converting the QTS-generated header files,
we can even adjust their data types. A good candidate for this is
the pinmux table, where each entry can have value in the range of
0..3, but each element is declared as unsigned long. By changing
the type to u8, we can save over 600 Bytes from the SPL, so do it.
This patch also constifies the array.
Signed-off-by: Marek Vasut <marex@denx.de>
Add script which loads the QTS-generated sources and headers and converts
them into sensible format which can be used with much more easy in mainline
U-Boot. The script also filters out macros which makes no sense anymore, so
they don't pollute namespace and waste space.
Signed-off-by: Marek Vasut <marex@denx.de>
The board/altera/socfpga directory is not a generic SoCFPGA machine
anymore, but instead it represents the Altera SoCDK board. To make
matters more complicated, it represents both CycloneV and ArriaV
variant.
On the other hand, nowadays, the content of this board directory is
mostly comprised of QTS-generated header files, while all the generic
code is in arch/arm/mach-socfpga already.
Thus, this patch splits the board/altera/socfpga into a separate
board directory for ArriaV SoCDK and CycloneV SoCDK, so that each
can be populated with the correct QTS-generated header files for
that particular board.
Signed-off-by: Marek Vasut <marex@denx.de>
The CONFIG_TARGET_SOCFPGA_CYCLONE5 and CONFIG_TARGET_SOCFPGA_ARRIA5
selected both a board and a CPU. This is not correct as these macros
are supposed to select only board.
All would be good, if QTS-generated header files didn't check for
these macros exactly to determine if the platform is Cyclone V or
Arria V. Thus, for the sake of compatibility with not well fleshed
out header file generator, this patch makes these two macros into
a stub config option and introduces new CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK
and CONFIG_TARGET_SOCFPGA_ARRIA5_SOCDK targets, which select the
previous stub config option.
The result is that compatibility with QTS is preserved and the new
CONFIG_TARGET_* select actual target boards.
Signed-off-by: Marek Vasut <marex@denx.de>
Move the wrappers for QTS-generated files into platform directory
out of the board directory. The trick here is to add -I to CFLAGS
such that it points to the board directory in source tree and thus
the qts/ directory there is still reachable.
Signed-off-by: Marek Vasut <marex@denx.de>
The GMAC which is enabled is purely board property, so do not enable
arbitrary GMAC in DT include files. Same goes for PHY mode, which is
again a board property. The CycloneV SoCDK does this correctly, but
SoCrates doesn't. This bug never manifested itself though, since all
the boards ever used the GMAC1 . This bug manifests itself only on
boards that utilise GMAC0.
Signed-off-by: Marek Vasut <marex@denx.de>
The socfpga_cyclone5.dtsi has an mmc0 node, socrates has mmc node.
This makes aliases not very usable, so make everything into mmc0.
Moreover, zap the useless mmc alias while at this.
Signed-off-by: Marek Vasut <marex@denx.de>
This code claims it needs to wait 7us, yet it uses get_timer() function
which operates with millisecond granularity. Use timer_get_us() instead,
which operates with microsecond granularity.
Signed-off-by: Marek Vasut <marex@denx.de>
Based on observation, this udelay(20) was apparently too high and caused
subsequent failure to calibrate DDR when U-Boot was compiled with certain
toolchains. Lowering this delay fixed the problem.
Instead of permanently lowering the delay, calculate the correct delay
based on the original comment, that is, obtain EOSC1 frequency and use
it to calculate the precise delay.
Signed-off-by: Marek Vasut <marex@denx.de>
Fix the following problem:
drivers/ddr/altera/sequencer.c: In function 'sdram_calibration_full':
drivers/ddr/altera/sequencer.c:1943:25: warning: 'found_failing_read' may be used uninitialized in this function [-Wmaybe-uninitialized]
if (found_passing_read && found_failing_read)
^
drivers/ddr/altera/sequencer.c:1803:26: note: 'found_failing_read' was declared here
u32 found_passing_read, found_failing_read, initial_failing_dtap;
^
Signed-off-by: Marek Vasut <marex@denx.de>
This gem is really really rare, there was an actual float used in
the Altera DDR init code, which pulled in floating point ops from
the libgcc, just wow.
Since we don't support floating point operations the same way Linux
does not support them, replace this with an integer multiplication
and division combo. This removes some 2kiB of size from the SPL as
the floating point ops are no longer pulled in from libgcc.
This was detected by enabling CONFIG_USE_PRIVATE_LIBGCC=y , which
does not contain the floating point bits.
Signed-off-by: Marek Vasut <marex@denx.de>
Move config for the E1000 Ethernet driver to Kconfig and tidy up affected
boards.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Several files are out of order. This means that when the moveconfig tool
moves CONFIG options to Kconfig it generates a large diff. To avoid this,
reorder the files first.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add Kconfig options in preparation for moving boards to use Kconfig.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Since struct eth_device does not exist with CONFIG_DM_ETH defined, avoid
using it in the driver unless necessary. Most of the time it is better to
pass the private driver pointer anyway.
Also refactor the code so that code that the driver model implementation
will share are available in functions that can be called. Add stubs where
necessary.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Apalis T30 2GB on Apalis Evaluation Board
We cannot currently include any header files in the C files since common.h
needs to be included first, and it is in the header file. Move it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Apalis T30 2GB on Apalis Evaluation Board
Current behavior is that if CTRL+C is pressed command returns 0 that was
successful which is not correct behavior.
The easiest test case is "tftpboot 80000 uImage && echo yes"
and press CTRL+C. Then the second command is called which is incorrect.
Error log:
zynq-uboot> tftpb 80000 uImage && echo yes
Gem.e000b000:7 is connected to Gem.e000b000. Reconnecting to
Gem.e000b000
Gem.e000b000 Waiting for PHY auto negotiation to complete....... done
Using Gem.e000b000 device
TFTP from server 192.168.0.102; our IP address is 192.168.0.101
Filename 'uImage'.
Load address: 0x80000
Loading: ################
Abort
yes
zynq-uboot>
This patch adds -EINTR return value when CTRL+C is pressed.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Adjust timouts and retry counts to be suitable for loaded ethernet
network. With 5 seconds timeout, 10 retries maximum, tftp is
impossible even on local network with single full-speed TCP
connection.
100msec timeout should be suitable for most networks tftp is used on,
that is local ethernets. Timeout count really needs to be way higher,
as lost packets are normal when TCP is running over the same network.
Enforce 10msec minimum.
Signed-off-by: Pavel Machek <pavel@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Also move the spi flash configurations to the at91-sama5_common.h.
Current at91 zImage size is about 3.3M, the old mapping is not
suitable. So update the spi flash map as following:
0x0 ~ 0x004000: at91bootstrap(16k)
0x04000 ~ 0x008000: u-boot env(16k)
0x08000 ~ 0x060000: u-boot(352k)
0x60000 ~ 0x06c000: dtb (48k)
0x6c000 ~ 0x400000: kernel (3M+592k)
In AT91Bootstrap, the U-Boot in spi flash also update to 0x8000, refer
to following commit in AT91Bootstrap:
3e91e54 Kconfig: fix spi flash address
So also update SPL's u-boot load address to 0x8000 in spi flash.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Since sama5d3xek boards has different type of dtb blobs, so we need to detect
the cpu type in runtime.
So we add a new variable $dtb_name. if $dtb_name is not defined, we just use
at91-${board_name}.dtb
as the $dtb_name. Otherwise, we will just load the dtb with
$dtb_name.
For sama5d3xek, we will detect cpu type and make up $dtb_name in
runtime.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
As almost all sama5 sd/mmc env configurations are same, so move them to
at91-sama5_common.h.
Also define CONFIG_ENV_VARS_UBOOT_CONFIG to have the varaible: $board_name.
Then we can use 'at91-${board_name}.dtb' as the dtb name.
TODO: since sama5d3xek has different dtb name, we need to some extra
stuff to make it work on sama5d3xek boards.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
To enable the clocks on the at91 boards a constant (0x4) is used.
This is replaced with a define in at91_pmc.h (1 << 2).
Signed-off-by: Erik van Luijk <evanluijk@interact.nl>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
On these boards the DDR is connected to a dedicated controller and not
to chip select 1 of the EBI.
Signed-off-by: Erik van Luijk <evanluijk@interact.nl>
Tested-by: Erik van Luijk <evanluijk@interact.nl>
The mpddr.c depends on ATMEL_BASE_MPDDRC for the base address to configure the controller.
This cannot be used when there is more than one controller (i.e. AT91SAM9G45, AT91SAM9M10).
Signed-off-by: Erik van Luijk <evanluijk@interact.nl>
[remove 'new blank line at EOF']
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
The syntax for the fdt_chosen/initrd
functions seem to deprecated in usage
from MIPS bootm implementation.
Third parameter is no more used in these api's
Refer to : include/fdt_support.h
Signed-off-by: Govindraj Raja <govindraj.raja@imgtec.com>
In commit a18a477 (MIPS: use common code from lib/time.c) MIPS platforms
started using common the common timer functions which are based around
the fact that many platforms have a 32-bit free running counter register
that can be used see commit 8dfafdd (Introduce common timer functions).
Even MIPS64 has such a 32-bit register (some have an additional 64-bit free
running counter, but that's something for another time).
The problem is that in __read_32bit_c0_register() we read the value from
this register into an _signed_ int and as it's returned up the call
chain to timer_read_counter() it gets assigned to an unsigned long. On a
32-bit system there is no problem. On a 64-bit system odd things happen,
sign extension seems to kick in and all of a sudden if the counter
register happens to have the MSb (i.e. the sign bit) set the negative
int gets sign extended into a very large unsigned long value. This in
turn throws out things from get_ticks() up.
Update __read_32bit_c0_register() and __read_32bit_c0_ctrl_register() to
use "unsigned int res;" instead of "int res;". There seems to be little
reason to treat these register values as signed. They are either
counters (which by definition are unsigned) or are made up of various
bit fields to be interpreted as per the CPU datasheet.
Reported-by: Sachin Surendran <sachin.surendran@alliedtelesis.co.nz>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
This has not been converted to Generic Board, so should be removed.
(See doc/README.generic-board for details.)
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Heiko Schocher <hs@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
This driver is not used only on exynos, but also on Altera SoCFPGA,
HiSilicon SoCs, RPi etc, so rename it accordingly to prevent confusion.
Signed-off-by: Marek Vasut <marex@denx.de>
populate _reset_ callback to the USB ethernet gadget since UDC core
expects every gadget driver to have the reset callback. This shouldn't
be needed once the ethernet gadget driver is adapted to use the
composite driver.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
xhci omap driver has board_usb_init in xhci_hcd_init but doesn't have
the corresponding cleanup function in xhci_hcd_stop.
Fix it here by invoking board_usb_cleanup() in xhci_hcd_stop().
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Ethernet gadget driver can be used both by both SPL and u-boot. Since
usb_eth_init() is the entry point for ethernet gadget driver, perform
board initialization there. Also perform the cleanup in usb_eth_halt.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
This patch fixes a potential NULL pointer dereference arising on
non-present/non-initialized xHCI controllers and adds some error
handling to xHCI code
Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com>
Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com>
USB EHCI on SPEAr600 has not been tested for a while. The base controller
addresses are missing. This patch adds the defines to the header. And adds
the missing code.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Vipin Kumar <vk.vipin@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Document target board specific functions
board_ehci_hcd_init - override usb phy mode
board_ehci_hcd_init - set usb vbus voltage
board_ehci_power - enables/disables usb vbus voltage
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
We have to set a MAC address to use network.
Otherwise, the tftpboot command fails with the following message:
Gem.e000b000 Waiting for PHY auto negotiation to complete........ done
*** ERROR: `ethaddr' not set
Since commit 92ac520821 ("net: Remove all references to
CONFIG_ETHADDR and friends"), we can not use CONFIG_ETHADDR.
The easiest way to set a MAC address is to enable
CONFIG_NET_RANDOM_ETHADDR.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
zynq-7000.dtsi include skeleton.dtsi which contains memory node with
base address and size zero. If you add memory@0 node to the platform DTS
in final DTB there are two memory nodes and U-Boot works with the first
one (with zeros) which end up in failing in dram_init because size is
zero.
Platform memory node should rewrite default memory node setup from
skeleton.dtsi that's why platfroms needs to also use memory as node name
instead of memory@0.
Reported-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
We have to set a MAC address to use network.
Otherwise, the tftpboot command fails with the following message:
Gem.e000b000 Waiting for PHY auto negotiation to complete........ done
*** ERROR: `ethaddr' not set
Since commit 92ac520821 ("net: Remove all references to
CONFIG_ETHADDR and friends"), we can not use CONFIG_ETHADDR.
The easiest way to set a MAC address is to enable
CONFIG_NET_RANDOM_ETHADDR.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Use embedded DTB to let users use u-boot instead of u-boot-dtb.bin.
And fix SPL to use this target.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Added usb dwc3 driver support for zynqmp
this also supports the DFU and LTHOR to download
the linux images on to RAM and cen be booted from
those linux images.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
One disadvantage of commit a26cd04920 (arch: Make board selection
choices optional) is that Kconfig could create such an insane
.config file that no board is selected.
Rip off the "optional" again in favor of ZC702 as the default
target.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Based on the patch:
"armv8: caches: Added routine to set non cacheable region"
(sha1: dad17fd510)
it is necessary to add platform specific hook.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
We have flipped CONFIG_SPL_DISABLE_OF_CONTROL. We have cleansing
devices, $(SPL_) and CONFIG_IS_ENABLED(), so we are ready to clear
away the ugly logic in include/fdtdec.h:
#ifdef CONFIG_OF_CONTROL
# if defined(CONFIG_SPL_BUILD) && !defined(SPL_OF_CONTROL)
# define OF_CONTROL 0
# else
# define OF_CONTROL 1
# endif
#else
# define OF_CONTROL 0
#endif
Now CONFIG_IS_ENABLED(OF_CONTROL) is the substitute. It refers to
CONFIG_OF_CONTROL for U-boot proper and CONFIG_SPL_OF_CONTROL for
SPL.
Also, we no longer have to cancel CONFIG_OF_CONTROL in
include/config_uncmd_spl.h and scripts/Makefile.spl.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
As we discussed a couple of times, negative CONFIG options make our
life difficult; CONFIG_SYS_NO_FLASH, CONFIG_SYS_DCACHE_OFF, ...
and here is another one.
Now, there are three boards enabling OF_CONTROL on SPL:
- socfpga_arria5_defconfig
- socfpga_cyclone5_defconfig
- socfpga_socrates_defconfig
This commit adds CONFIG_SPL_OF_CONTROL for them and deletes
CONFIG_SPL_DISABLE_OF_CONTROL from the other boards to invert
the logic.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
We do not want to compile the DM remove code for SPL. Currently,
we undef it in include/config_uncmd_spl.h (for C files) and in
scripts/Makefile.uncmd_spl (for Makefiles). This is really ugly.
This commit demonstrates how we can deprecate those two files.
Use $(SPL_) for the entry in the Makfile and CONFIG_IS_ENABLED()
in C files.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Just preparing for upcoming cleaning.
The board-specific linker script board/vpac270/u-boot-spl.lds
has been touched to avoid build error. It does not change the
size of spl/u-boot-spl.bin for this board, so it should be OK.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
The previous commit introduced a useful macro used in makefiles,
in order to reference to different variables (CONFIG_... or
CONFIG_SPL_...) depending on the build context.
Per-image config option control is a PITA in C sources, too.
Here are some macros useful in C/CPP expressions.
CONFIG_IS_ENABLED(FOO) can be used as a shorthand for
(!defined(CONFIG_SPL_BUILD) && defined(CONFIG_FOO)) || \
(defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_FOO))
For example, it is useful to describe C code as follows,
#if CONFIG_IS_ENABLED(OF_CONTROL)
(device tree code)
#else
(board file code)
#endif
The ifdef conditional above is switched by CONFIG_OF_CONTROL during
the U-Boot proper building (CONFIG_SPL_BUILD is not defined), and by
CONFIG_SPL_OF_CONTROL during SPL building (CONFIG_SPL_BUILD is
defined).
The macro can be used in C context as well, so you can also write the
equivalent code as follows:
if (CONFIG_IS_ENABLED(OF_CONTROL)) {
(device tree code)
} else {
(board file code)
}
Another useful macro is CONFIG_VALUE().
CONFIG_VALUE(FOO) is expanded into CONFIG_FOO if CONFIG_SPL_BUILD is
undefined, and into CONFIG_SPL_FOO if CONFIG_SPL_BUILD is defined.
You can write as follows:
text_base = CONFIG_VALUE(TEXT_BASE);
instead of:
#ifdef CONFIG_SPL_BUILD
text_base = CONFIG_SPL_TEXT_BASE;
#else
text_base = CONFIG_TEXT_BASE;
#endif
This commit also adds slight hacking on fixdep so that it can
output a correct list of fixed dependencies.
If the fixdep finds CONFIG_IS_ENABLED(FOO) in a source file,
we want
$(wildcard include/config/foo.h)
in the U-boot proper building context, while we want
$(wildcard include/config/spl/foo.h)
in the SPL build context.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Commit e02ee2548a ("kconfig: switch to single .config
configuration") made the configuration itself pretty simple,
instead, we lost the way to systematically enable/disable config
options for each image independently.
Our current strategy is, put entries into Makefile.spl for options
we need separate enabling, or once enable the options globally in
Kconfig and then undef them in Makefile.uncmd_spl if we do not want
to compile the features for SPL at all. Things are getting really
messy. Besides, "ifdef CONFIG_SPL_BUILD" are sprinkled everywhere
in makefiles.
This commit adds a variable to help describe makefile simpler.
$(SPL_) evaluates to "SPL_" during the SPL build, while to an empty
string during building U-boot proper.
So, you can write
obj-$(CONFIG_$(SPL_)FOO) += foo.o
instead of
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_SPL_FOO) += foo.o
else
obj-$(CONFIG_FOO) += foo.o
endif
If CONFIG_SPL_FOO does not exist in Kconfig, it is equivalent to
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_SPL_FOO) += foo.o
endif
This is the pattern we often see in our current makefiles.
To take advantage of this macro, we should prefix SPL_ for the SPL
version of the option when we need independent control between
U-boot and SPL. With this naming scheme, I hope our makefiles will
be much simplified.
It means we want to rename existing config options as follows
in the long run:
CONFIG_SPL_SERIAL_SUPPORT -> CONFIG_SPL_SERIAL
CONFIG_SPL_I2C_SUPPORT -> CONFIG_SPL_I2C
CONFIG_SPL_GPIO_SUPPORT -> CONFIG_SPL_GPIO
CONFIG_SPL_SPI_SUPPORT -> CONFIG_SPL_SPI
CONFIG_SPL_DISABLE_OF_CONTROL -> CONFIG_SPL_OF_CONTROL
(inverting the logic)
Then drivers/Makefile would be re-worked as follows:
obj-$(CONFIG_$(SPL_)SERIAL) += serial/
obj-$(CONFIG_$(SPL_)I2C) += i2c/
obj-$(CONFIG_$(SPL_)GPIO) += gpio/
obj-$(CONFIG_$(SPL_)SPI) += spi/
...
Eventually, SPL-specialized entries in Makefile.spl would go away.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
If the target string matches "CONFIG_", move the pointer p
forward. This saves several 7-chars adjustments.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
- Re-direct stderr into the log files, so any errors U-Boot emits are
visible in the logs. This is relevant if the "reset" shell command
attempts to report that it's not supported on the sandbox board.
- Fix test_fs_nonfs() to name the files it created differently for each
invocation. Otherwise, the logs from different tests overwrite
each-other.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Suriyan Ramasami <suriyan.r@gmail.com>
LPC32xx has 3 I2C bus controllers, 2 of them are used as generic ones
and their parent clock is HCLK and CLK_HI/CLK_LO registers are 10 bit
wide. This means that if HCLK is 104MHz, then minimal configurable I2C
clock speed is about 51KHz.
Only USB OTG I2C bus controller CLK registers are 8 bit wide, thus in
assumption that peripheral clock is 13MHz it allows to set the minimal
bus speed about 25.5KHz.
Check for negative half clock value is removed since it is always false.
The change fixes the following problem for I2C busses 0 and 1:
=> i2c dev 0
Setting bus to 0
=> i2c speed 100000
Setting bus speed to 100000 Hz
Failure changing bus speed (-22)
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Tested-by: Sylvain Lemieux <slemieux@tycoint.com>
The change adds a number of macro definitions used by USB OHCI driver,
if CONFIG_USB_OHCI_LPC32XX is selected from a board config file.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Tested-by: Sylvain Lemieux <slemieux@tycoint.com>
Incorporate USB driver from legacy LPCLinux NXP BSP.
The files taken from the legacy patch are:
- lpc32xx USB driver
- lpc3250 header file USB registers definition.
The legacy driver was updated and clean-up as part of the integration with the latest u-boot.
Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
Acked-by: Marek Vasut <marex@denx.de>
Tested-by: Vladimir Zapolskiy <vz@mleia.com>
Updated the LPC32xx I2C driver to support
the OTG I2C that is part of the USB module.
Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
Acked-by: Marek Vasut <marex@denx.de>
Incorporate ECC layout for small page NAND from legacy LPCLinux NXP BSP.
The code taken from the legacy patch is:
- lpc32xx SLC NAND driver (ECC layout for small page)
This layout is matching the lpc32xx NAND SLC Linux Kernel driver.
Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
Incorporate NAND SLC hardware ECC support from legacy LPCLinux NXP BSP.
The code taken from the legacy patch is:
- lpc32xx SLC NAND driver (hardware ECC support)
- lpc3250 header file missing SLC NAND registers definition
The legacy driver was updated and clean-up as part of the integration with the existing NAND SLC driver.
Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
Tested-by: Vladimir Zapolskiy <vz@mleia.com>
A number of LPC32xx SLC NAND defines is dictated by controller
hardware limits and OOB layout is defined by operating system, the
definitions are common for all users. Since those macro are used
in out of NAND SLC driver code (simple NAND SPL framework), they can
not be placed into the driver, therefore move them from board config
files to arch/config.h
The change also adds OOB layout details specific to small page NAND
devices taken from Linux kernel.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Tested-by: Sylvain Lemieux <slemieux@tycoint.com>
Incorporate DMA driver from legacy LPCLinux NXP BSP.
The files taken from the legacy patch are:
- lpc32xx DMA driver
- lpc3250 header file DMA registers definition.
The legacy driver was updated and clean-up as part of the integration with the latest u-boot.
Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
Acked-by: Marek Vasut <marex@denx.de>
Tested-by: Vladimir Zapolskiy <vz@mleia.com>
This causes widespread breakage due to the operation of the low-level code
in crt0.S and cro0_64.S for ARM at least.
The fix is not complicated but it seems safer to revert this for now.
This reverts commit 2afddae075.
Signed-off-by: Simon Glass <sjg@chromium.org>
Enable TI_EDMA3 and SPL_DMA support, so as to reduce boot time. With
DMA enabled there is almost 3x improvement in read performance. This
helps in reducing boot time in qspiboot mode
Also add EDMA3 base address for DRA7XX and AM57XX.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
ti_qspi uses memory map mode for faster read. Enabling DMA will increase
read speed by 3x @48MHz on DRA74 EVM.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
When doing a memory mapped copy we may have DMA available and thus need
to have this copy abstracted so that the driver can do it, rather than a
simple memcpy.
Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Adds functions to enable and disable edma3 clocks which can be invoked
by drivers using edma3 to control the clocks.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Adds functions to enable and disable edma3 clocks which can be invoked
by drivers using edma3 to control the clocks.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Add do_disable_clocks() to disable clock domains and module clocks.
These clocks are enabled using do_enable_clocks().
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Add do_disable_clocks() to disable clock domains and module clocks.
These clocks are enabled using do_enable_clocks().
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Use memalign() with ARCH_DMA_MINALIGN to allocate read buffers.
This is required because, flash drivers may use DMA for read operations
and may have to invalidate the buffer before read.
Signed-off-by: Ravi Babu <ravibabu@ti.com>
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Tested-by: Jagan Teki <jteki@openedev.com>
Use memalign() with ARCH_DMA_MINALIGN to allocate read buffers.
This is required because, flash drivers may use DMA for read operations
and may have to invalidate the buffer before read.
Signed-off-by: Ravi Babu <ravibabu@ti.com>
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Tested-by: Jagan Teki <jteki@openedev.com>
Update op_mode_rx flag based on CONFIG_QSPI_QUAD_SUPPORT flag,
instead of platform.
Signed-off-by: Vishal Mahaveer <vishalm@ti.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
This patch enabled the MVEBU PCIe support on the db-88f6820-gp A38x
eval board. It also enabled the Intel E1000 driver support and
adds the initialization of PCIe network controllers to the
board code.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Anton Schubert <anton.schubert@gmx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Dirk Eibach <eibach@gdsys.de>
This patch enabled the MVEBU PCIe support on the db-mv784mp-gp AXP
eval board. It also enabled the Intel E1000 driver support and
adds the initialization of PCIe network controllers to the
board code.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Anton Schubert <anton.schubert@gmx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
This adds a PCI driver for the controllers found on Marvell MVEBU SoCs.
Besides the driver, this patch also removes the statically defined
PCI MBUS windows. As they are not needed anymore, since this PCIe
driver now creates the windows dynamically.
Tested on Armada XP db-mv784mp-gp eval board using an Intel E1000
PCIe card in all 3 PCIe slots. And on the Armada 38x db-88f6820-gp
eval board using this Intel E1000 PCIe card in the PCIe 0 slot.
This port was done in cooperation with Anton Schubert.
Signed-off-by: Anton Schubert <anton.schubert@gmx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Dirk Eibach <eibach@gdsys.de>
This patch introduces the SDRAM scrubbing for ECC enabled board
to fill/initialize the ECC bytes. This is done via the XOR engine
to speed up the process. The scrubbing is a 2-stage process:
1) SPL scrubs the area 0 - 0x100.0000 (16MiB) for the main U-Boot
2) U-Boot scrubs the remaining SDRAM area(s)
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Rework these functions so that dram_init_banksize() does not call
dram_init() again. It only needs to set the banksize values in the
bdinfo struct.
Make sure to also clip the size of the last bank if it exceeds the
maximum allowed value of 3 GiB (0xc000.0000). Otherwise other
address windows (e.g. PCIe) will overlap with this memory window.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
This patch moves CONFIG_SYS_TEXT_BASE to 0x00800000 for all Armada
XP / 38x boards in mainline U-Boot. This is done in preparation for
the ECC SDRAM scrubbing that needs to be done in the main U-Boot.
The SPL (previously bin_hdr) has already scrubbed the area:
0x0000.0000 - 0x0100.0000
In this area this main U-Boot needs to get loaded. The main U-Boot
then can scrub the remaining SDRAM area while running from this
location.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
This patch adds "(ECC enabled)" or "(ECC disabled)" to the DRAM
bootup text. Making it easier for board with SPD DIMM's to see,
if ECC is enabled or not.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
This patch adds support for multiple hostcontrollers to the ehci-marvell driver
and enables all 3 usb-hcs on the db-mv784mp-gp board.
It depends on the initial Armada XP usb support patch from Stefan.
Signed-off-by: Anton Schubert <anton.schubert@gmx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
This patch enables the USB EHCI support for the Marvell Armada XP (AXP)
SoCs. In compatism to the Armada 38x (A38x), the AXP needs to configure
the USB PLL and the USB PHY's specifically in U-Boot. The A38x has done
this already in the bin_hdr (SPL U-Boot). Without this, accessing the
controller registers in U-Boot or Linux will hang the CPU.
Additionally, the AXP uses a different USB EHCI base address. This
patch also takes care of this by runtime SoC detection in the Marvell
EHCI driver.
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Anton Schubert <anton.schubert@gmx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
This patch enables the NAND controller on the Armada XP/38x and provides
a new function that returns the NAND controller input clock. This
function will be used by the MVEBU NAND driver.
As part of this patch, the multiple BIT macro definitions are moved
to a common place in soc.h.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Peter Morrow <peter@senient.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Accessing MBUS windows not backed-up by e.g. PCIe devices will
hang the SoC. Disable MBUS error propagation back to CPU allows
to read 0xffffffff instead of hanging the SoC.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Only with disabled MMU its possible to switch the base register address
on Armada 38x. Without this the SDRAM located at >= 0x4000.0000 is also
not accessible, as its still locked to cache.
So to fully release / unlock this area from cache, we need to first
flush all caches, then disable the MMU and disable the L2 cache.
On Armada XP this does not seem to be needed. Even worse, with this
code added, I sometimes see strange input charactes loss from the
console.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
With this patch, the MBUS bridge registers (base and size) are
configured upon each call to mbus_dt_setup_win(). This is needed, since
the board code can also call this function in later boot stages. As
done in the maxbcm board.
This is needed to fix a problem with the secondary CPU's not booting
in Linux on AXP.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Peter Morrow <peter@senient.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
This patch changes the MBUS base addresses and sizes to use more
generic names and also adds defines for the sizes. It also moves
the base address to higher addresses.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
This is tested on the DB-MV784MP-GP eval board. To really enable ECC
support on this board the I2C EEPROM needs to get changed. As it
saves the enabling of ECC support internally. For this the following
commands can be used to enable ECC support on this board:
Its recommended for first save (print) the value(s) in this EEPROM
address:
=> i2c md 4e 0.1 2
0000: 05 00 ..
To enable ECC support you need to set bit 1 in the 2nd byte:
Marvell>> i2c mw 4e 1.1 02
Marvell>> i2c md 4e 0.1 2
0000: 05 02 ..
To disable ECC support again, please use this command:
Marvell>> i2c mw 4e 1.1 00
Marvell>> i2c md 4e 0.1 2
0000: 05 00 ..
On other AXP boards, simply plugging an ECC DIMM should be enough to
enable ECC support.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
CONFIG_SYS_BOARD_DRAM_INIT is not defined anywhere. So lets get rid
of all references here.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Fix a condition that generate watchdog timeout inside "lpc32xx_i2c_write" when parameters alen = 0 and len = 0.
Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
Fix a condition that generate watchdog timeout inside "lpc32xx_i2c_read" when parameters alen != 0 and len = 0.
Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
The HCLK is not constant and can take different value; use the api function to get the value of the HCLK for the I2C clock high and low computation.
Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
Add support for optional soft reset (i.e. "RESOUT_N" not asserted during reset).
To be compatible with the original U-Boot code, when the "addr" parameter is 0, a hard is performed; for any other values, a soft reset is done.
Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
Add missing registers in struct definition.
Update GPIO MUX base register to match GPIO base (refer to "LPC32x0 User manual" Rev. 3 - 22 July 2011).
Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
Make the support for 4K subpage I/O on a SPI NOR flash configurable.
A board which requires the SPI NOR to be accessed in larger 32KiB
or 64KiB pages can disable the 4K subpage support, but by default,
the support for 4K subpage I/O is enabled. The functionality of this
option is the same as CONFIG_MTD_SPI_NOR_USE_4K_SECTORS in Linux.
This is extremely useful in case one uses UBI on a SPI NOR flash.
UBI needs at least 15k EBs and can not work on a flash which uses
4k ones, so disabling the support for 4k subpages lets UBI work on
such flash.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagan Teki <jteki@openedev.com>
The do_lowlevel_init() function includes certian CA15 specific L2 cache
configuration which is only applicable on Exynos5420 and members of its
family. Fix the regression on Origen4210 by skipping the Exynos5420
specific portions of the code.
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Tested-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
The default boot command searches for dofastboot varaiable
and does a fastboot if it is set to 1.
But the condition "if test ${dofastboot} -eq 1" always
returns true if dofastboot is not defined and breaking mmc boot.
So make dofastboot as 0 by default and let the runtime
environment set it if fastboot is required.
Reported-by: Yan Liu <yan-liu@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
This reverts commit 5b34436035.
This function has a few problems. It calls fdt_parent_offset() which as
mentioned in code review is very slow.
https://patchwork.ozlabs.org/patch/499482/https://patchwork.ozlabs.org/patch/452604/
It also happens to break SPI flash on Minnowboard max which is how I noticed
that this was applied. I can send a patch to tidy that up, but in any case
I think we should consider a revert until the function is better implemented.
Signed-off-by: Simon Glass <sjg@chromium.org>
It is a bit tedious to figure out the interrupt configuration for a new
x86 platform. Add a script which can do this, based on the output of
'pci long'. This may be helpful in some cases.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Set up interrupts correctly so that Linux can use all devices. Use
savedefconfig to regenerate the defconfig file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* Explicitly list the targets supported in each section of the
instructions from the x86 README.
* Drop references to 'raw mode', in favor of 'bare mode'.
Signed-off-by: Igor Stoppa <igor.stoppa@intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This can fail for internal reasons, so return a sensible value rather than
a random one.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Now that we have an efi.h header we can use that for FSP error defines.
Drop the FSP ones.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Multiple APs are brought up simultaneously and they may get the same
seq num in the uclass_resolve_seq() during device_probe(). To avoid
this, set req_seq to the reg number in the device tree in advance.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
When trying to figure out where an exception has occured, the relocated
address is not a lot of help. Its value depends on various factors. Show
the un-relocated IP as well. This can be looked up in System.map directly.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This reverts commit df189d9ba3.
Unfortunately this commit breaks chromebook_link because it adds lots of PCI devices
before relocation and there is not enough pre-reloc malloc() memory.
Rathar then increase this memory, revert for now until we figure this out.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
There is quite a bit of assembler code that can be removed if we use the
generic global_data setup. Less arch-specific code makes it easier to add
new features and maintain the start-up code.
Drop the unneeded code and adjust the hooks in board_f.c to cope.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Rather than keeping track of the Global Descriptor Table in its own memory
we may as well put it in global_data with everything else. As a first step,
stop using the separately allocated GDT.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present we have a simple assignment to gd. With some archs this is
implemented as a register or through some other means; a simple assignment
does not suit in all cases.
Change this to a function and add documentation to describe how this all
works.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <yorksun@freescale.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Some archs like to have larger alignment for their global data. Use 16 bytes
which suits all current archs.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Remove FAT function prototypes from the cm5200 firmware update code, and
include the relevant headers instead.
This exposes the fact that the custom prototyoe for do_fat_read() in
this file was incorrect. Rather than simply fixing the call-site, replace
do_fat_read() with fat_exists(). This removes the only use of
do_fat_read() outside of the FAT code.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
This part of mentioned commit, was missed by my mistake during the rebase.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Original commit message:
power: pmic: pfuze100 support driver model
1. Support driver model for pfuze100.
2. Introduce a new Kconfig entry DM_PMIC_PFUZE100 for pfuze100
3. This driver intends to support PF100, PF200 and PF3000, so add
the device id into the udevice_id array.
4. Rename PMIC_NUM_OF_REGS macro to PFUZE100_NUM_OF_REGS.
Change-Id: I4fc88414f3c0285f9648e47ec7aed60addeccc4d
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
We should not fiddle with interrupts or the FSP when running as an EFI
payload. Detect this and skip this code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
We should signal to the FSP that PCI enumeration is complete. Perform this
task in a suitable place.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This function can fail. In this case we should return the error rather than
swallowing it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This code may be useful for boards that use driver model for PCI.
Note: It would be better to have driver model automatically call this
function somehow. However for now it is probably safer to have it under
board control.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This code could use a little tightening up. There is some repetition and
an odd use of fdtdec_get_int_array().
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
These functions allow iteration through all PCI devices including bridges.
The children of each PCI bus are returned in turn. This can be useful for
configuring, checking or enumerating all the devices.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present there are no PCI functions which allow access to PCI
configuration using a struct udevice. This is a sad situation for driver
model as it makes use of PCI harder. Add these functions.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
When using different release version of Intel FSP, the VPD_IMAGE_REV
is different (ie: BayTrail Gold 3 is 0x0303 while Gold 4 is 0x0304).
Remove the asserting of this so that U-Boot does not hang in a debug
build.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Allow for configuration of FSP UPD from the device tree which will
override any settings which the FSP was built with itself.
Modify the MinnowMax and BayleyBay boards to transfer sensible UPD
settings from the Intel FSPv4 Gold release to the respective dts files,
with the condition that the memory-down parameters for MinnowMax are
also used.
Signed-off-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Removed fsp,mrc-debug-msg and fsp,enable-xhci for minnowmax, bayleybay
Fixed lines >80col
Signed-off-by: Simon Glass <sjg@chromium.org>
The BayTrail SoC has 4 different PCI devices IDs regarding to IDE
and AHCI. Add these IDs in pci_ids.h and also add the other SATA
ID in the Bayley Bay and MinnowMax board configuration header.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
bd->bi_dram[] has both start address and size defined as 32-bit,
which is not the case on some platforms where >=4GiB memory bank
is used. Change them to support such memory banks.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Add support for 4 1.62G lane eDP panels connected via an anx9804 bridge,
such as found on the Colombus devkit.
While at it also fix the wrong indentation of the SSD2828 Kconfig help text
in board/sunxi/Kconfig.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Add support for the ANX9804 bridge chip, which can take pixel data coming
from a parallel LCD interface and translate it on the fly into a DP
interface for driving eDP TFT displays. It uses I2C for configuration.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Anatolij Gustschin <agust@denx.de>
Add support for using the mipi pll as lcd clock source, this is
necessary for getting higher dotclocks with lcd panels.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Anatolij Gustschin <agust@denx.de>
Add support for the mipi pll, this is necessary for getting higher dotclocks
with lcd panels.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
sun6i and later have a couple of io-blocks which are shared between the
main CPU core and the "R" cpu which is small embedded cpu which can be
active while the main system is suspended.
These gpio banks sit at a different mmio address then the normal banks,
and have a separate devicetree node and compatible, this adds support for
these banks to the sunxi-gpio code when built with device-model support.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The phy is using a RGMII interface, which we need to specify in our
board-config, and the dts needs a gmac section (the dts changes have
also been submitted to the kernel).
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The sun5i die has a hdmi encoder onboard, but the A13 package does not
route this to the outside, disable hdmi support on A13 based boards.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Enable composite video support on all boards which have a composite video
out connector (either cinch or jack).
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The Auxtek-T003 HDMI stick is an A10s based HDMI stick with USB wifi,
and composite video out support.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Sync the sunxi dts files with the changes queued up for kernel-4.3 in
mripard's sunxi/dt-for-4.3 branch.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The tv-encoder on sun5i is slightly different compared to the one on
sun4i/sun7i.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Add support for making the visual area of the framebuffer smaller and
drawing a black border around it. This is intended for use with
overscanning monitors (esp. with composite video out), to avoid part
of the picture being invisible.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Anatolij Gustschin <agust@denx.de>
cfbconsole currently assumes that the width and stride of the framebuffer
are the same, in most places where stride matters it uses a VIDEO_LINE_LEN
helper macro.
This commit changes the few places not using VIDEO_LINE_LEN to also use
VIDEO_LINE_LEN, and protects the default VIDEO_LINE_LEN with a #ifndef
guard, allowing the boards config.h to override and, and thus support
cases where stride != width.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Anatolij Gustschin <agust@denx.de>
The passed in width is always VIDEO_COLS. This is a preparation patch
for adding stride != width support to the cfbconsole code.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Anatolij Gustschin <agust@denx.de>
Represent all available RAM in either one or two banks. The first bank
describes any RAM below 4GB. The second bank describes any RAM above 4GB.
This split is driven by the following requirements:
- The NVIDIA L4T kernel requires separate entries in the DT /memory/reg
property for memory below and above the 4GB boundary. The layout of that
DT property is directly driven by the entries in the U-Boot bank array.
- On systems with RAM beyond a physical address of 4GB, the potential
existence of a carve-out at the end of RAM below 4GB can only be
represented using multiple banks, since usable RAM is not contiguous.
While making this change, add a lot more comments re: how and why RAM is
represented in banks, and implement a few more "semantic" functions that
define (and perhaps later detect at run-time) the size of any carve-out.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The return value of query_sdram_size() is assigned directly to
gd->ram_size in dram_init(). Adjust the return type to match the field
it's assigned to. This has the beneficial effect that on 64-bit systems,
the return value can correctly represent large RAM sizes over 4GB.
For similar reasons, change the type of variable size_bytes in the same
way.
query_sdram_size() would previously clip the detected RAM size to at most
just under 4GB in all cases, since on 32-bit systems, larger values could
not be represented. Disable this feature on 64-bit systems since the
representation restriction does not exist.
On 64-bit systems, never call get_ram_size() to validate the detected/
calculated RAM size. On any system with a secure OS/... carve-out, RAM
may not have a single contiguous usable area, and this can confuse
get_ram_size(). Ideally, we'd make this call conditional upon some other
flag that indicates specifically that a carve-out is actually in use. At
present, building for a 64-bit system is the best indication we have of
this fact. In fact, the call to get_ram_size() is not useful by the time
U-Boot runs on any system, since U-Boot (and potentially much other early
boot software) always runs from RAM on Tegra, so any mistakes in memory
controller register programming will already have manifested themselves
and prevented U-Boot from running to this point. In the future, we may
simply delete the call to get_ram_size() in all cases.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The new value is the most likely value where the kernel wants to end up
at run-time. Selecting this value as the load address likely avoids the
need to copy the kernel image from the actual load address to the desired
load address. Note that this isn't guaranteed since the kernel may wish
to run at an arbitrary location. In that case, U-Boot will still relocate
the image according to its wishes; this change is a performance
optimization, not a hard-coding of the final image location.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The logic for simple PLLs on T124 was broken by this commit:
722e000c Tegra: PLL: use per-SoC pllinfo table instead of PLL_DIVM/N/P, etc.
Correct it by reading from the same pll_misc register that it writes to and
adding an entry for the DP PLL in the pllinfo table.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This header file uses type definitions (u8, u32) from linux/types.h but
doesn't include it. If includes aren't carefully ordered this can cause
build failures.
Cc: Tom Warren <twarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Unfortunately currently both Apalis T30 as well as Colibri T30 crash
upon starting USB host support. This is due to the following patch not
having taken into account that our T30 device trees were defaulting to
peripheral only mode instead of otg:
commit ddb9a502d1
dm: usb: tegra: Move most of init/uninit into a function
This patch fixes this by defaulting to otg now.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Make sure SODIMM pin 87 nRESET_OUT is released properly by explicitly
setting its pin mux function to GMI. This solves some issues with e.g.
USB not being fully operational on carrier boards with USB hubs
connected to reset if U-Boot got loaded via recovery mode aka rcm.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Various clean-ups either in comments, order or spacing without any
functional impact:
- Add some comments in the device trees resp. reorder some parameters
for consistency across all our modules.
- Sort some include files alphabetically (while leaving common.h on
top of course).
- Streamline some comments in the configuration files and fix the
spacing from using spaces to tabs.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Enable CONFIG_IP_DEFRAG and set CONFIG_TFTP_BLOCKSIZE to 16384.
This increases the tftp download speed considerably.
While at it enable CONFIG_TFTP_TSIZE which limits the progress bar to
fifty '#' independent of the downloaded file size.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Now as all is in place actually enable UBI/UBIFS support to be able to
boot the Linux kernel and root file system from NAND.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Fix PIO read_byte() implementation not only used for the legacy READ ID
but also the PARAM command required for proper ONFI detection.
This fix is inspired by Lucas Stach's Linux Tegra NAND driver of late
(not mainline yet but getting there soon I hope).
I vaguely remember that those commands are special on 16-bit bus NAND
(e.g. always return 8-bit data regardless) and later Linux MTD fixed/
changed the way this is handled which in turn broke once U-Boot pulled
that in. Basically instead of doing PIO read regular DMA block read is
now used which this patch actually fixes.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The Colibri T20's PMIC enters a sleep mode on low supply voltage < 3.0V
±2.5% (2.92...3.08V). Rising the main supply voltage again does not
bring it back to regular operation. Not even a full reset does bring
the module back. A full power cycle was required to reboot the system.
A long positive pulse on the PMICs resume pin also reboots the system
but this pin is only accessible as a test point on the module.
This patch configures the PMIC through I2C to not enter this sleep mode
plus force it to normal state upon sleep request exit should this ever
happen.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Use toradex,colibri_t20 as the device-tree compatible node value rather
than toradex,t20 in accordance to our Apalis/Colibri T30 products.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Allow detecting whether or not U-Boot was launched through the
recovery mode of the resp. NVIDIA SoC.
Make use of a board specific arch_misc_init() and enable the same via
CONFIG_ARCH_MISC_INIT configuration option.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add defines to allow reading recovery mode (RCM) boot type from the boot
information table (BIT) written by the boot ROM (BR) to the IRAM.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add support to specify the Ethernet buffer base address;
if none are supply by the board, the default value is use (from existing code).
Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Use the boot loader splash screen from WinCE which matches our
wallpapers position wise. Although the logo is an 8-bit indexed BMP as
well colours looked odd at first in U-Boot. After converting to full
RGB palette and converting back to an indexed BMP using imagemagick
the Logo showed up properly.
$ convert tools/logos/toradex-rgb.bmp -type Palette -colors 256 \
-compress none -verbose BMP3:tools/logos/toradex.bmp
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
This fixes the following warning (and the runtime error reporting):
../common/image-fdt.c:491:4: warning: 'fdt_ret' may be used
uninitialized in this function [-Wmaybe-uninitialized]
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Simon Glass <sjg@chromium.org>
Allow showing custom board info from a checkboard() function being
implemented if CONFIG_CUSTOM_BOARDINFO is specified. Previously the
device tree model was always displayed not taking any
CONFIG_CUSTOM_BOARDINFO into account.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
http://lists.denx.de/pipermail/u-boot/2012-September/134347.html
allows for reading files in chunks from the shell.
When this feature is used to read past the end of a file an error
was returned instead of returning the bytes read up to the end of
file. Thus the following fails in the shell:
offset = 0
len = chunksize
do
read file, offset, len
write data
until bytes_read < len
The patch changes the behaviour to printing an informational
message and returning the actual read number of bytes aka read(2)
behaviour for convenient use in U-Boot scripts.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Marek Vasut <marex@denx.de>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
9MB reserved for initrd is not enough for default ramfs used for keystone
devices, which is ~33MB. This patch increases the size up to 80MB.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
This patch set the correct initrd address to much rdaddr, which used at
get_fs_ramfs commad.
Fixes: 3e97f0b63c8e ("configs: ti_armv7_keystone2: switch addresses
to generic addresses")
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
The following commit changed the order of the column vs. row parameter
to the lcd_init_console() function but missed actually changing it as
well the second time it is called from lcd_clear() which resulted in a
garbled text console which this patch fixes.
commit 604c7d4a5a
common/lcd_console: introduce display/framebuffer rotation
Tested on Colibri T20 with my latest assortment of tegra
fixes/enhancements patch set.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Simon Glass <sjg@chromium.org>
Add option to set shell prompt string from menuconfig and migrate
boards globally.
The migration is done as follows:
- Boards that explicitly and unconditionally set CONFIG_SYS_PROMPT had the
entry moved to their defconfig files.
- Boards that defined some kind of #ifdef logic which selects the
CONFIG_SYS_PROMPT (for example qemu-mips) got an #undef CONFIG_SYS_PROMPT
right before the #ifdef logic and were left alone.
- This change forces CONFIG_SYS_PROMPT to be a per board decision, and thus
CONFIG_SYS_PROMPT was removed from all <soc>_common.h and <arch>_common.h
files. This results in a streamlined default value across platforms, and
includes the following files: spear-common, sunxi-common, mv-common,
ti_armv7_common, tegra-common, at91-sama5_common, and zynq-common.
- Boards that relied on <arch/soc>_common.h values of CONFIG_SYS_PROMPT were
not updated in their respective defconfig files under the assumption that
since they did not explicitly define a value, they're fine with whatever
the default is.
- On the other hand, boards that relied on a value defined in some
<boards>_common.h file such as woodburn_common, rpi-common,
bur_am335x_common, ls2085a_common, siemens_am33x_common, and
omap3_evm_common, had their values moved to the respective defconfig files.
- The define V_PROMPT was removed, since it is not used anywhere except for
assigning a value for CONFIG_SYS_PROMPT.
Cc: Tom Rini <trini@konsulko.com>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
[trini: Add spring, sniper, smartweb to conversion]
Signed-off-by: Tom Rini <trini@konsulko.com>
Currently implement always swap for big-endian value.
So doesn't work big-endian environment.
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
We can calculate this. Add code to do this if it is not provided.
panto: prefix changed to dw_mmc to make things easier to grep
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Since commit a26cd04920 ("arch: Make board selection choices
optional"), Kconfig could create such an insane .config file that
no SoC/board is selected.
This is now a real problem for Buildroot, for example.
(http://lists.busybox.net/pipermail/buildroot/2015-July/135125.html)
This commit drops the "optional" from the ARM target select menu
in favor of "Versatile family".
Rationale:
- Historically, Linux chose versatile_defconfig as the default
of ARM defconfig. (arch/arm/Makefile of Linux describes:
KBUILD_DEFCONFIG := versatile_defconfig)
- It was published by ARM Ltd.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
- Import various DT files for DRA7 / DR72x / dra72-evm from Linux Kernel
v4.1
- Add config file for this board, enable DM and DM_GPIO
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
- Move the CONS_INDEX selection out of CONFIG_SYS_EXTRA_OPTIONS and
into Kconfig proper.
- While in here, enable CONFIG_SPL_STACK_ADDR
Signed-off-by: Tom Rini <trini@konsulko.com>
We now have the CONFIG_SPL_DM for code within SPL to toggle caring about
DM or not. Without this change platforms that do enable CONFIG_DM but
not CONFIG_SPL_DM may be broken (such as OMAP5).
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Signed-off-by: Tom Rini <trini@konsulko.com>
The "method" parameter was part of the original port of the driver from
the kernel. At some point this may have been added to allow for future
differentiation (as omap1 and omap2 have different GPIO IP blocks, so
this wasn't an unreasonable thing to do). At this point however it's
just extra overhead, so drop.
Signed-off-by: Tom Rini <trini@konsulko.com>
- Re-sync DT files for am33xx with Linux Kernel v4.1
- Include DT file now for the "AM335x GP EVM" and build target for it,
via device tree and DM.
- We only need to provide platform data for UART when OF_CONTROL isn't
also enabled really. We can just push GPIO to coming from DT
Signed-off-by: Tom Rini <trini@konsulko.com>
HiKey is the first 96boards consumer edition compliant board. It features a hi6220
SoC which has eight ARM A53 cpu's.
This initial port adds support for: -
1) Serial
2) eMMC / SD card
3) USB
4) GPIO
It has been tested with Arm Trusted Firmware running u-boot as the BL33 executable.
Notes:
eMMC has been tested with basic reading of eMMC partition into DDR. I have not
tested writing / erasing. Due to lack of clock control it won't be
running in the most performant high speed mode.
SD card slot has been tested for reading and booting kernels into DDR.
It is also currently configured to save the u-boot environment to the
SD card.
USB has been tested with ASIX networking adapter to tftpboot kernels
into DDR. On v2015.07-rc2 dhcp now works, and also USB mass storage
are correctly enumerated.
GPIO has been tested using gpio toggle GPIO4_1-3 to flash the LEDs.
Basic SoC datasheet can be found here: -
https://github.com/96boards/documentation/blob/master/hikey/
Hi6220V100_Multi-Mode_Application_Processor_Function_Description.pdf
Board schematic can be found here: -
https://github.com/96boards/documentation/blob/master/hikey/
96Boards-Hikey-Rev-A1.pdf
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
This patch adds the glue code for hi6220 SoC which has 2x synopsis
dw_mmc controllers. This will be used by the hikey board support
in subsequent patches.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
This adds a simple pmic driver for the hi6553 pmic which is used in
conjunction with the hi6220 SoC on the hikey board. Eventually this
driver will be updated to be a proper UCLASS PMIC driver which
can parse the voltages direct from device tree.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
This patch adds the header files which will be used in the subsquent
board / drivers to enable support for hi6220 hikey board.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Modify the data pointer type from ulong* to u32*.
For arm64 type "ulong" could be 64-bit. Then in line 89 of common/cmd_source.c:
"while (*data++);" data will point to the next 64 bits each time. As the uImage
file generated by mkimage tool keeps the same data format in either 32-bit or 64-bit
platform, the difference would cause failure in 64-bit platform.
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
The semantics for non-static functions declared inline have changed in
gcc5, causing the empty functions not to be emitted as an external
symbol.
Since lowlevel_init() is only referenced from start.S, it should not be
declared inline at all.
Reported-by: Otavio Salvador <otavio@ossystems.com.br>
Tested-by: Otavio Salvador <otavio@ossystems.com.br>
[trini: Reword commit message]
Signed-off-by: Tom Rini <trini@konsulko.com>
Since all the clocks are defined common, and has the same logic to get
the frequencies, use a common definition for for clk_get_rate().
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Remove unused external clocks and make a common definition
for all keystone platforms.
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
This is just a cosmetic change that makes
the calling of pll init code looks much cleaner.
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Register Base addresses are same for PLLs in all
keystone platforms. If a PLL is not available, the corresponding
register addresses are marked as reserved.
Hence use a common definition.
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Use common devspeed and armspeed definitions.
Also fix reading efuse bootrom register.
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
There are two types of PLL for all keystone platforms:
Main PLL, Secondary PLL. Instead of duplicating the same definition
for each secondary PLL, have a common function which does
initialization for both PLLs. And also add proper register
definitions.
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Add print_cpuinfo() function and enable
CONFIG_DISPLAY_CPUINFO for keystone platforms,
so that cpu info can be displayed during boot.
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
DRA72x processor variants are single core and it does not export ACP[1].
Hence, we have no source for generating an external snoop requests which
appear to be key to the deadlock in DRA72x design.
Since we build the same image for DRA74x and DRA72x platforms, lets
runtime detect and disable the workaround (in favor of performance) on
DRA72x platforms.
[1] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0438i/BABIAJAG.html
Suggested-by: Richard Woodruff <r-woodruff2@ti.com>
Suggested-by: Brad Griffis <bgriffis@ti.com>
Reviewed-by: Brad Griffis <bgriffis@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Add workaround for Cortex-A15 ARM erratum 801819 which says in summary
that "A livelock can occur in the L2 cache arbitration that might
prevent a snoop from completing. Under certain conditions this can
cause the system to deadlock. "
Recommended workaround is as follows:
Do both of the following:
1) Do not use the write-back no-allocate memory type.
2) Do not issue write-back cacheable stores at any time when the cache
is disabled (SCTLR.C=0) and the MMU is enabled (SCTLR.M=1). Because it
is implementation defined whether cacheable stores update the cache when
the cache is disabled it is not expected that any portable code will
execute cacheable stores when the cache is disabled.
For implementations of Cortex-A15 configured without the “L2 arbitration
register slice” option (typically one or two core systems), you must
also do the following:
3) Disable write-streaming in each CPU by setting ACTLR[28:25] = 0b1111
So, we provide an option to disable write streaming on OMAP5 and DRA7.
It is a rare condition to occur and may be enabled selectively based
on platform acceptance of risk.
Applies to: A15 revisions r2p0, r2p1, r2p2, r2p3 or r2p4 and REVIDR[3]
is set to 0.
Note: certain unicore SoCs *might* not have REVIDR[3] not set, but
might not meet the condition for the erratum to occur when they donot
have ACP (Accelerator Coherency Port) hooked to ACE (AXI Coherency
Extensions). Such SoCs will need the work around handled in the SoC
specific manner, since there is no ARM generic manner to detect such
configurations.
Based on ARM errata Document revision 18.0 (22 Nov 2013)
Suggested-by: Richard Woodruff <r-woodruff2@ti.com>
Suggested-by: Brad Griffis <bgriffis@ti.com>
Reviewed-by: Brad Griffis <bgriffis@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Remove the CONFIG_DM_USB limitation to enable cache support functions.
Tested on SAMA5D3x-EK board.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Current many cpu use the same flush_cache() function, which just call
the flush_dcache_range().
So implement a weak flush_cache() for all the cpus to use.
In original weak flush_cache() in arch/arm/lib/cache.c, there has some
code for ARM1136 & ARM926ejs. But in the arch/arm/cpu/arm1136/cpu.c and
arch/arm/cpu/arm926ejs/cache.c, there implements a real flush_cache()
function as well. That means the original code for ARM1136 & ARM926ejs
in weak flush_cache() of arch/arm/lib/cache.c is totally useless.
So in this patch remove such code in flush_cache() and only call
flush_dcache_range().
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Since some driver like ohci, lcd used dcache functions. But some ARM
cpu don't implement the invalidate_dcache_range()/flush_dcache_range()
functions.
To avoid compiling errors this patch adds an weak empty stub function
for all ARM cpu in arch/arm/lib/cache.c.
And ARM cpu still can implemnt its own cache functions on the cpu folder.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Since some driver like ohci, lcd used dcache functions. But m68k don't
implement the invalidate_dcache_range()/flush_dcache_range() functions.
To avoid compiling errors this patch adds an weak empty stub function
for all m68k cpu.
Also each cpu can implement its own implementation. If not implemented
then by default is using an empty function.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Acked-by: Angelo Dureghello <angelo@sysam.it>
gpio.h - Added missing copyright in few files.
rsa-mod-exp.h - Corrected copyright in the file.
fsl_sec.h - Added missing license in files
drivers/crypto/fsl/Makefile - Removed the incomplete GPLv2 license and replaced it with GPLv2+ license
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
The menuconfig for drivers are getting more and more cluttered
and unreadable because too many entries are displayed in a single
flat menu. Use hierarchic menu for each category.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
[trini: Update to apply again in a few places, drop USB hunk]
Signed-off-by: Tom Rini <trini@konsulko.com>
This adds dcache support for dwc2. The DMA buffers must be DMA aligned and
is flushed for outgoing transactions before starting transfer. For
ingoing transactions it is invalidated after the transfer has finished.
Signed-off-by: Alexander Stein <alexanders83@web.de>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
[trini: Update to apply again on top of DM patches]
Signed-off-by: Tom Rini <trini@konsulko.com>
When using dcache the setup data for the mailbox must be actually written
into memory before calling into firmware. Thus flush and invalidate the
memory.
Signed-off-by: Alexander Stein <alexanders83@web.de>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
The mailbox buffer is required to be at least 16 bytes aligned, but for
cache invalidation and/or flush it needs to be cacheline aligned.
Use ALLOC_CACHE_ALIGN_BUFFER for all mailbox buffer allocations.
Signed-off-by: Alexander Stein <alexanders83@web.de>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
The cacheline is always 32 bytes for arm1176 CPUs, so define it at board
config level for cache handling code.
The ARM Cortex-A7 has a dcache line size of 64 bytes.
Signed-off-by: Alexander Stein <alexanders83@web.de>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
As both cores are similar merge the cache handling code for both CPUs
to arm11 directory.
Signed-off-by: Alexander Stein <alexanders83@web.de>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
[trini: Add hunk to arch/arm/cpu/arm1136/Makefile]
Signed-off-by: Tom Rini <trini@konsulko.com>
Apparently lcd_panel_disable is not defined anywhere, so no config for
an arm1136 board would have set CONFIG_LCD. Remove the unused code.
Signed-off-by: Alexander Stein <alexanders83@web.de>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
Using the twl4030 keypad allows booting directly into some special boot modes,
such as recovery or fastboot. the VOL+ key will trigger a boot to recovery while
the VOL- key will trigger a boot to fastboot.
The G (gesture) key remains unused at this point.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
In most cases, userspace will attempt to power off the device with HALT instead
of POWER_OFF, which triggers a reset instead of a proper power off from the
TWL4030. Hence, it is up to the bootloader to actually turn the device off when
there is no reason to turn it on.
A reboot identified with the OMAP reboot mode bits set is acceptable, as well as
a power on reason from either the power button, USB or charger plug.
Other cases should trigger a power off. Note that for the U-Boot reset command
to take effect, we have to fill-in the OMAP reboot bits.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
This adds support for resetting the device on a long press on the power button.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
This adds support for the fastboot USB gadget, including flashing to the
internal MMC and reboot to bootloader or not.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
[trini: Update to use Kconfig for MUSB]
Signed-off-by: Tom Rini <trini@konsulko.com>
Now that the serial number is correctly defined, we can pass it to the kernel
using the (legacy) ATAG method. It will be automatically passed via device-tree
when enabled.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
The OMAP3 has some die-specific ID bits that we can use to give the device a
(more or less) unique serial number. This is particularly useful for e.g. USB.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
This adds support for the omap3 reboot mode mechanism and exports the reboot
mode via an environment variable, that is used in the boot command to make it
possible to boot from the recovery partition.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
The LG Optimus Black (P970) codename sniper is a smartphone that was designed
and manufactured by LG Electronics (LGE) and released back in 2011.
It is using an OMAP3630 SoC GP version, which allows running U-Boot and the
U-Boot SPL from the ground up. This port is aimed at running an Android version
such as Replicant, the fully free Android distribution. However, support for
upstream Linux with device-tree and common GNU/Linux distros boot commands
could be added in the future.
For more information about the journey to freeing this device, please read the
series of blog posts at:
http://code.paulk.fr/article20/a-hacker-s-journey-freeing-a-phone-from-the-ground-up-first-part
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
[trini: Add CONFIG_OF_SUPPORT]
Signed-off-by: Tom Rini <trini@konsulko.com>
Reboot mode is written in scratchpad memory before reboot in the form of a
single char, that is the first letter of the reboot mode string as passed to the
reboot function.
This mechanism is supported on OMAP3 both my the upstream kernel and by various
TI kernels.
It is up to each board to make use of this mechanism or not.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
This allows scanning the twl4030 keypad, storing the result in a 64-byte long
matrix with the twl4030_keypad_scan function.
Detecting a key at a given column and row is made easier with the
twl4030_keypad_key function.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
This adds support for detecting a few inputs exported by the TWL4030.
Currently-supported inputs are the power button, USB and charger presence.
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
This adds support for powering off (the omap3 SoC) from the twl4030. This is
especially useful when the kernel does not actually power off the device using
this method but reboots and leaves it up to the bootloader to actually turn the
power off.
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
The change adds SPL build support to Timll DevKit3250 board, the
generated SPL image can be uploaded over UART5, JTAG or stored on
NAND. SPL is designed to load U-boot image from NAND.
All new NAND chip defines in board configuration are needed by
SPL NAND "simple" framework, the framework is used to reduce
potentially duplicated code from LPC32xx SLC NAND driver.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
This change adds more peripherals to Timll DevKit3250 board, namely
MAC and SMSC phy, SLC NAND, GPIO, SPI and I2C.
Also the default serial console is changed to UART5, added an option
to pass device tree blob by means of bootm, predefined environment
variables are slightly extended and reserved space on NAND to store
user defined U-boot environment.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
The change adds support of LPC32xx SLC NAND controller.
LPC32xx SoC has two different mutually exclusive NAND controllers to
communicate with single and multiple layer chips.
This simple driver allows to specify NAND chip timings and defines
custom read_buf()/write_buf() operations, because access to 8-bit data
register must be 32-bit aligned.
Support of hardware ECC calculation is not implemented (data
correction is always done by software), since it requires a working
DMA engine.
The driver can be included to an SPL image.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Tested-by: Sylvain Lemieux <slemieux@tycoint.com>
Some NAND controllers define custom functions to read data out,
respect this in order to correctly support bad block handling in
simple SPL NAND framework.
NAND controller specific read_buf() is used even to read 1 byte in
case of connected 8-bit NAND device, it turns out that read_byte()
may become outdated.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Tom Warren <twarren@nvidia.com>
Acked-by: Scott Wood <scottwood@freescale.com>
If a dtb is specified on the command-line, the Android boot image ramdisk
will not be found. Fix this so that we can specify the ramdisk address and
dtb address. The syntax is to enter the Android boot image address for
both the kernel and ramdisk.
Signed-off-by: Rob Herring <robh@kernel.org>
When building the file system the existing code does an insertion into
a linked list. It attempts to speed this up by keeping a pointer to
where the last entry was inserted but it's still slow.
Now the nodes are just inserted into the list without searching
through for the correct place. This unsorted list is then sorted once
using mergesort after all the entries have been added to the list.
This speeds up the scanning of the flash file system considerably.
Signed-off-by: Mark Tomlinson <mark.tomlinson@alliedtelesis.co.nz>
If a sector has a CLEANMARKER at the beginning, it indicates that the
entire sector has been erased. Therefore, if this is found, we can skip the
entire block. This was not being done before this patch.
The code now does the same as the kernel does when encountering a
CLEANMARKER. It still checks that the next few words are FFFFFFFF, and if
so, the block is assumed to be empty, and so is skipped.
Signed-off-by: Mark Tomlinson <mark.tomlinson@alliedtelesis.co.nz>
The scan code is similar to the linux kernel, but the kernel defines a much
smaller size to scan through before deciding a sector is blank. Assuming
that what is in the kernel is OK, make these two match.
On its own, this change makes no difference to scanning of any sectors
which have a clean marker at the beginning, since the entire sector is not
blank.
Signed-off-by: Mark Tomlinson <mark.tomlinson@alliedtelesis.co.nz>
If the flash is slow, reading less from the flash into buffers makes
the process faster.
Signed-off-by: Mark Tomlinson <mark.tomlinson@alliedtelesis.co.nz>
jffs2_1pass_read_inode() would read the entire data for each node
in the filesystem, regardless of whether it was part of the file
to be loaded or not. By only reading the header data for an inode,
and then reading the data only when it is found to be part of the
file to be loaded, much copying of data is saved.
jffs2_1pass_list_inodes() read each inode for every file in the
directory into a buffer. By using NULL as a buffer pointer, NOR
flash simply returns a pointer, and therefore avoids a memory copy.
Signed-off-by: Mark Tomlinson <mark.tomlinson@alliedtelesis.co.nz>
If multiple versions of a file exist, only the most recent version
should be used. The scheme to write 0 for the inode in older versions
did not work, since this would have required writing to flash.
The only time this caused an issue was listing a directory, where older
versions of the file would still be seen. Since the directory entries
are sorted, just look at the next entry in the list, and if it's the same
move to that entry instead.
Signed-off-by: Mark Tomlinson <mark.tomlinson@alliedtelesis.co.nz>
Copying complete nodes from flash can be slow if the flash is slow
to read. By only reading the data needed, the sorting operation can
be made much faster.
The directory entry comparison function also had a two bugs. First, it
did not ensure the name was copied, so the name comparison may have
been faulty (although it would have worked with NOR flash). Second,
setting the ino to zero to ignore the entry did not work, since this
was either writing to a temporary buffer, or (for NOR flash) directly
to flash. Either way, the change was not remembered.
Signed-off-by: Mark Tomlinson <mark.tomlinson@alliedtelesis.co.nz>
If a destination is not provided, jffs2_1pass_read_inode() only
returns the length of the file. In this case, avoid reading all
the data nodes, and return as soon as the length of the file is
known.
Signed-off-by: Mark Tomlinson <mark.tomlinson@alliedtelesis.co.nz>
add support for the at91sam9260 based board smartweb from
siemens. SPL is used without serial support, as this
SoC has only 4k sram for running SPL. Here a U-Boot
bootlog:
RomBOOT
>
U-Boot 2015.07-rc2-00109-g4ae828c (Jun 15 2015 - 09:31:16 +0200)
CPU: AT91SAM9260
Crystal frequency: 18.432 MHz
CPU clock : 198.656 MHz
Master clock : 99.328 MHz
Watchdog enabled
DRAM: 64 MiB
WARNING: Caches not enabled
NAND: 256 MiB
In: serial
Out: serial
Err: serial
Net: macb0
Hit any key to stop autoboot: 0
U-Boot>
Signed-off-by: Heiko Schocher <hs@denx.de>
remove unneeded udelay() in this function, as we use
the dev_ready pin.
Signed-off-by: Heiko Schocher <hs@denx.de>
Acked-by: Scott Wood <scottwood@freescale.com>
This patch enables building SPL without
CONFIG_SPL_SERIAL_SUPPORT support.
Signed-off-by: Heiko Schocher <hs@denx.de>
[trini: Ensure we build arch/arm/imx-common on mx28]
Signed-off-by: Tom Rini <trini@konsulko.com>
The current 4.5 timeout for the autonegotiation are not enough to
complete it on my platform. Using the Intel E1000 PCIe card in the
Marvell db-mv784mp-gp eval board. So lets increase the timeout to
8 seconds.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Simon Glass <sjg@chromium.org>
CONFIG_TFTP_TSIZE should limit a tftp downloads progress to 50 '#'
chars. Make this work also for small files.
If the file size is small, i.e. smaller than 2 tftp block sizes the
number of '#' can get much larger. i.e. with a 1 byte file 65000
characters are printed, with a 512 byte file around 500.
When using CONFIG TFTP BLOCKSIZE together with CONFIG_IP_DEFRAG the
issue is more notable.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
On the highbank platform the SoC's management controller firmware
will probe the DRAM modules and populates the initial device tree with
the correct values. Therefore the memory sizes in the DT are already
correct, so remove U-Boot's DRAM bank setup so the memory node is not
"fixed up" by u-boot.
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Andre Przywara <osp@andrep.de>
The return type of pmic_read and pmic_write is signed int, so
correct variable 'ret' from type unsigned int to int.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Przemyslaw Marczak <p.marczak@samsung.com>
If enable DM PMIC and REGULATOR, we should not use original power
framework. So need to comment out the pfuze code for original power
framework, when CONFIG_DM_PMIC_PFUZE100 defined.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
1. Add new regulator driver pfuze100.
* Introduce struct pfuze100_regulator_desc for maintaining info
for one regulator.
2. Add new Kconfig entry DM_REGULATOR_PFUZE100 for pfuze100.
3. This driver intends to support PF100, PF200 and PF3000.
4. Add related macro definition in pfuze header file.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
1. Support driver model for pfuze100.
2. Introduce a new Kconfig entry DM_PMIC_PFUZE100 for pfuze100
3. This driver intends to support PF100, PF200 and PF3000, so add
the device id into the udevice_id array.
4. Rename PMIC_NUM_OF_REGS macro to PFUZE100_NUM_OF_REGS.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
We do not need that "regulator-name" property must be provided in dts.
If "regulator-name" property is not provided in dts, node name
will chosen for settings '.name' field of uc_pdata.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
If there is no property named 'regulator-name' for regulators,
choose node name instead, but not directly return failure value.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
According to datasheet, SWBST_MODE starts from bit 2 and it occupies 2 bits.
So SWBST_MODE_MASK should be 0xC, and SWBST_MODE_xx should be ([mode] << 2).
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
The dw_mmc driver uses printf() in various places.
These bloat the code and cause problems for SPL. Use debug() where possible
and try to return a useful error code instead.
panto: Small rework to make it apply against top of tree.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
With commit e3a77218a2 the MII bus is only
reset if a reset handler is registered. If there is no reset handler there
is no need to wait for a device to come out of the reset.
Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks>
The rxbd is not correctly handled in case of a frame physical error
(FPE) or frame size error (FSE). The rxbd must be cleared and
advanced in case of an error to avoid receive stall.
Signed-off-by: Daniel Inderbitzin <daniel.inderbitzin@gmail.com>
LPC32xx MAC and clock control configuration requires some minor quirks
to deal with a phy connected by RMII.
It's worth to mention that the kernel and legacy BSP from NXP sets
SUPP_RESET_RMII == (1 << 11) bit, however the description of this bit is
missing in shared LPC32x0 User Manual UM10326 Rev. 3, July 22, 2011
and in LPC32x0 Draft User Mannual Rev. 00.27, November 20, 2008, also
in my tests an SMSC LAN8700 phy device connected over RMII seems to
work correctly without touching this bit.
Add support of RMII, if CONFIG_RMII is defined, this option is aligned
with a number of boards, which already define the same config value.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Tested-by: Sylvain Lemieux <slemieux@tycoint.com>
This change rearranges general MAC configuration and PHY specific
configuration of MAC registers (duplex mode and speed), before this
change set bits related to PHY configuration in MAC2 and COMMAND
registers are rewritten by the following writing to the registers.
Without the change auto negotiation on boot quite often is not
completed in reasonable time:
Waiting for PHY auto negotiation to complete......... TIMEOUT !
Additionally MAC1_SOFT_RESET clear bit is removed since it is done in
preceding lpc32xx_eth_initialize() and in lpc32xx_eth_halt(), instead
added missing MCFG_RESET_MII_MGMT on device initialization.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
The lpc32xx_eth_phylib_init() function is capable to connect LPC32XX
MAC to some specified phy by phy id, by chance the single user of
lpc32xx_eth has CONFIG_PHY_ADDR set to 0, however other boards may
have non-zero CONFIG_PHY_ADDR value, fix it.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Acked-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
According to LPC32x0 User Manual the following bits in Command
register 0x3106_0100 are defined:
Bit Symbol
2 - Unused
3 RegReset
4 TxReset
5 RxReset
Fix wrong (1-bit shifted right) COMMAND_RESETS value, which sets
an unused bit, but neglects RxReset.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Acked-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Tearing down an unitialized rx channel causes a pending address hole
event to be queued. When booting linux it will report this pending
as something like "Address Hole seen by USB_OTG at address 57fff584",
since u-boot did not handled this interrupt. Prevent that by not
tearing down the rx channel, when not receiving.
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
This patch refer to linux kernel commit: d8b763e1e79f
net/macb: add TX multiqueue support for gem
by: Cyrille Pitchen
1. macb driver will check the register to find how many queues support for
this chip.
2. Then as we only use queue0 for tx, so we will set up all other queues
use a dummy descriptor, which USED bit is set. So those queues are not used.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The driver didn't stop the bounce buffer in case a data transfer
failed. This would lead to memory leakage if the communication
between the CPU and the card is unreliable. Add the missing call
to stop the bounce buffer.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Tom Rini <trini@konsulko.com>
Currently the serial code assumes that there is always at least one serial
port (and panics / crashes due to null pointer dereferences when there is
none).
This makes it impossible to use u-boot on boards where there is no (debug)
serial port, because e.g. all uart pins are muxed to another function.
This commit adds a CONFIG_REQUIRE_SERIAL_CONSOLE Kconfig option, which
defaults to y (preserving existing behavior), which can be set to n on
such boards to make them work.
This commit only implements this for CONFIG_DM_SERIAL=y configs, as allowing
running without a serial port for CONFIG_DM_SERIAL=n configs is non trivial,
and is not necessary at this moment.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Simon Glass <sjg@chromium.org>
Add composite video out support.
This only gets enabled on the Mele M3 for now, since that is were it
was tested. It will be enabled on more boards after testing.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Add support for interlaced modes, this is a preparation patch for adding
composite out support.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Add a few extra sunxi display registers and constant defines.
Also rename some existing defines (e.g. dropping _GCTRL) and make
some more generic (e.g. dropping the 2x scaling from
SUNXI_LCDC_TCON1_TIMING_V_TOTAL).
This is a preparation patch for adding composite video out support.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
We should only subtract 2 from the vblank time when using tcon1.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
All the #ifdef-ery in selecting the default and fallback monitor type is
becoming unyielding and makes the code hard to read, replace it with a few
helper functions.
This will also be useful with the upcoming CHIP board which has display
adapter daughterboards which should be runtime detectable.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The Jesurun Q5 has the musb hooked up to an usb-a receptacle, enable it
in host-only mode.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Do not add a bogus (pointing to a non existing serial port) stdout-path
alias to dts on boards without a serial port.
Note that we still define CONS_INDEX as this is used by the SPL where we do
not use DM_SERIAL and thus CONFIG_REQUIRE_SERIAL_CONSOLE is not honored.
We are getting away with this because the sun5i die actually has
an uart0, which in the A13 package is not routed to the outside,
so we are simply sending SPL bootup messages to the tx pin at the
edge of the die, and they go no further from there...
And sofar we only have one A13 board which does not have a serial
port, all others do have a serial port. This kinda makes sense since
the A13 is a much lower pincount package compared to all the other
sunxi SoCs.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Now that we have code to check the id-pin and detect usb-host adapters
plugged into the otg port that way, enable it on the tablets which I own.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
USB devices are not really designed to get the power bounced off and on
at them. Esp. USB powered harddisks do not like this.
Currently we power off the USB ports both on a "usb reset" and when
booting the kernel, causing the usb-power to bounce off and then back
on again.
This patch removes the powering off calls, fixing the undesirable power
bouncing.
Note this requires some special handling for the OTG port:
1) We must skip the external vbus check if we've already enabled our own
vbus to avoid false positives
2) If on an usb reset we no longer detect that the id-pin is grounded, turn
off vbus as that means an external vbus may be present now
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Add code which uses the new functions for obtaining FPGA ID from
the scan manager. This new code prints the FPGA model attached to
the SoCFPGA during boot and sets environment variable "fpgatype",
which can be used to determine the FPGA model in U-Boot scripts.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Add code to get the FPGA type for Altera's SoCFPGA family of FPGA. The code
uses the scan manager to send jtag pulses that will return the FPGA ID.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Factor out the code which sends JTAG instruction followed by data
into separate function to tidy the code up a little.
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Clean up the horrible macros present in the scan_manager.h . Firstly,
the function scan_mgr_io_scan_chain_prg() is static, yet all the macros
are used only within it, thus there is no point in having them in the
header file. Moreover, the macros are just making the code much less
readable, so remove them instead.
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Introduce generic function for accessing the JTAG scan chains in the
SCC manager. Make use of this function throughout the SCC manager to
replace the ad-hoc writes to registers and make the code less cryptic.
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Rework this function so it's clear that it is only polling for certain
bits to be cleared. Add kerneldoc. Fix it's return value to be either
0 on success and -ETIMEDOUT on error and propagate this through the
scan manager code.
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Fix most of the dangling checkpatch issues, no functional change.
There are still 7 warnings, 1 checks , but those are left in place
for the sake of readability of the code.
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Actually convert the sequencer code to use socfpga_sdram_misc_config
instead of the various macros. This is just an sed exercise here, no
manual coding needed.
This patch actually removes the need to include any board-specific
files in sequencer.c , so sequencer.c namespace is now no longer
poluted by QTS-generated macros.
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
This is another macro used to obfuscate the real code. The
T(INIT|RESET)_CNTR._VAL is always defined, so this indirection
is unnecessary. Get rid of this.
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Just use READ_VALID_FIFO_SIZE directly, no need for this macro obfuscation.
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Introduce structure socfpga_sdram_misc_config to wrap the remaining
misc configuration values in board file. Again, introduce a function,
socfpga_get_sdram_misc_config(), which returns this the structure. This
is almost the final step toward wrapping the nasty QTS generated macros
in board files and reducing the pollution of the namespace.
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Actually convert the sequencer code to use socfpga_sdram_io_config
instead of the IO_* macros. This is just an sed excercise here, no
manual coding needed.
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Introduce structure socfpga_sdram_io_config to wrap the IO configuration
values in board file. Introduce socfpga_get_sdram_io_config() function,
which returns this the structure. This is another step toward wrapping
the nasty QTS generated macros in board files and reducing the pollution
of the namespace.
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Actually convert the sequencer code to use socfpga_sdram_rw_mgr_config
instead of the RW_MGR_* macros. This is just an sed exercise here, no
manual coding needed.
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Introduce structure socfpga_sdram_rw_mgr_config to wrap the RW manager
configuration values in board file. Introduce a complementary function,
socfpga_get_sdram_rwmgr_config(), which returns this the structure.
This is another step toward wrapping the nasty QTS generated macros
in board files and reducing the pollution of the namespace.
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Introduce two wrapper functions, socfpga_get_seq_ac_init() and
socfpga_get_seq_inst_init() to avoid direct inclusion of the
sequencer_auto_ac_init.h and sequencer_auto_inst_init.h QTS
generated files. This reduces namespace pollution again.
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
This is defined in the QTS-generated headers, so it must not be
re-defined in sequencer.h .
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
These parameters are not used in the code, zap them and the
macros which are used by them as well.
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Zap non-existent functions and place function prototypes at the
beginning of the header file.
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Move the files generated by QTS into the board directory, they should not
be part of the driver files at all.
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Originally, both sdram_start and sdram_end were 64b values. The
sdram_start had no reason for being so, since our address space
is only 32b, so switching sdram_start to u32 is simple.
The sdram_end is a bit more complex, since it can actually be
set to (1 << 32) if someone really wanted to use an SoCFPGA with
4 GiB of DRAM and fixed the code around a little. But, the code
handling the protection rules internally decrements the sdram_end
variable anyway. Thus, instead of calling the code and passing in
the address of the SDRAM end, pass in the address already decremented
by one. This lets the sdram_end be 32b as well.
Signed-off-by: Marek Vasut <marex@denx.de>
Clean the function up so that it's obvious what it is doing,
fix the formating strings in debug outputs, add kerneldoc.
Make the function return proper errno-compliant return values
and propagate this change throughout sdram.c
Signed-off-by: Marek Vasut <marex@denx.de>
Clean up coding style, mostly clean up comments, add kerneldoc.
Also, zap assignment of the "cs" variable, which is outright
dead code, so just remove it.
Signed-off-by: Marek Vasut <marex@denx.de>
Pluck out all of the CONFIG_HPS_SDR_CTRLCFG_* macros. This change
makes sdram.c completely clear of these macros and allows removing
of the ugly include of sdram.h . The namespace is now a much nicer
place!
Signed-off-by: Marek Vasut <marex@denx.de>
Introduce socfpga_sdram_get_config() function implement in a board file,
which returns the socfpga_sdram_config structure. This is the last step
in cleaning up the socfpga_mmr_init_full(), but not the last step which
allows removing the inclusion of sdram.h from drivers/ddr/altera/sdram.c
thus far.
Signed-off-by: Marek Vasut <marex@denx.de>
Rework remaining two register setting functions such that they only
return the final register value. Move the register setting into the
block of register I/O in sdram_mmr_init_full().
Signed-off-by: Marek Vasut <marex@denx.de>
Merge sdr_set_*() functions which are just setting registers among
the sea of register setting in sdram_mmr_init_full(). There is no
need to keep them separate this way, there is nothing special about
them.
Signed-off-by: Marek Vasut <marex@denx.de>
Suck out all the CONFIG_HPS_SDR_CTRLCFG_* from sdram_mmr_init_full()
into the socfpga_sdram_config structure. There is still one ugly
macro left behind, but this will be taken care of in subsequent patch.
Signed-off-by: Marek Vasut <marex@denx.de>
Zap all the ad-hoc readbacks from the registers and other useless
and broken debug output. This is really not useful and is only
confusing.
Signed-off-by: Marek Vasut <marex@denx.de>
Introduce this seemingly massive structure, which holds required values
of all the registers of the SDRAM controller. The idea here is to avoid
including the sdram.h header file, which is full of ad-hoc macros that
polute the global namespace. Once the cleanup of sdram.c would be complete
and all registers would be loaded from this new socfpga_sdram_config, a
board file will only pass this structure into the sdram.c . This will
hide all the horrors generated by QTS in the board directory.
Signed-off-by: Marek Vasut <marex@denx.de>
Get rid of the constant clrsetbits_le32(), instead prepare the whole
content of the register once and write it at the end of the function.
Signed-off-by: Marek Vasut <marex@denx.de>
Get rid of the constant clrsetbits_le32(), instead prepare the whole
content of the register once and write it at the end of the function.
Signed-off-by: Marek Vasut <marex@denx.de>
Get rid of the constant clrsetbits_le32(), instead prepare the whole
content of the register once and write it at the end of the function.
Signed-off-by: Marek Vasut <marex@denx.de>
Get rid of the constant clrsetbits_le32(), instead prepare the whole
content of the register once and write it at the end of the function.
Signed-off-by: Marek Vasut <marex@denx.de>
Get rid of the constant clrsetbits_le32(), instead prepare the whole
content of the register once and write it at the end of the function.
Signed-off-by: Marek Vasut <marex@denx.de>
Get rid of the constant clrsetbits_le32(), instead prepare the whole
content of the register once and write it at the end of the function.
Signed-off-by: Marek Vasut <marex@denx.de>
Get rid of the constant clrsetbits_le32(), instead prepare the whole
content of the register once and write it at the end of the function.
Merge set_sdr_dram_timing{1,2,3,4,lowpwr}() into single function
set_sdr_dram_timing() , since there's no point in keeping all this
stuff separate anymore.
Signed-off-by: Marek Vasut <marex@denx.de>
Get rid of the constant clrsetbits_le32(), instead prepare the whole
content of the register once and write it at the end of the function.
The big plan here is to remove all the CONFIG_HPS_SDR_ macros, hide
them in QTS compatibility layer in board implementation and pass only
a small structure into the driver.
Signed-off-by: Marek Vasut <marex@denx.de>
Remove all parameters of this function, since they are only constants
passed in from another function, so make them local. Also, rename the
function to get_errata_rows() as this is closer to what it does.
Signed-off-by: Marek Vasut <marex@denx.de>
Add a small workaround into the platform code which forces the SDMMC
into 8-bit mode (the default configuration for all socfpga platforms)
to work around breakage caused by missing patches in mainline which
switch the probing of SD/MMC to OF instead of static configuraiton.
The patches will hit mainline after the SPL series, so to avoid build
issues, add this small temporary workaround.
Signed-off-by: Marek Vasut <marex@denx.de>
This function is implementing the DDR calibration Stage 3 as
described in Altera EMI_RM 2015.05.04 . The main body of this
function is almost identical to Stage 1.3 (DQ/DQS centering)
for all but two flags -- use_read_test and update_fom. Convert
this function to call rw_mgr_mem_calibrate_dq_dqs_centering()
with the correct flags set to trim down the code duplication.
Moreover, reorder the remnants in the function a little and
convert the function to return either 0 or -EIO in case of
success and failure respectively, to match the common return
value convention.
Signed-off-by: Marek Vasut <marex@denx.de>
Clean up coding style, mostly broken multiline formatting strings
in debug output. Also clean up data types and constify where applicable.
Signed-off-by: Marek Vasut <marex@denx.de>
Fix data types and constify where applicable, fix broken multiline
debug strings and fix comments. No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
Fix the return value of the function to match common convention
where 0 means success and negative means error. Fix the return
values in case of an error to use errno.h codes.
Signed-off-by: Marek Vasut <marex@denx.de>
The read_group and write_group arguments are the same in all
cases when this function is invoked, just merge them into one
rw_group argument. Also, clean up the function argument data
types and constify them.
Signed-off-by: Marek Vasut <marex@denx.de>
The search_stop_check() always resets the bit_chk to a new value,
so bit_chk will never survive between search_left_edge() and
search_right_edge() invocation. There is thus no need to pass
it into these functions, so make bit_chk local to them.
Signed-off-by: Marek Vasut <marex@denx.de>
Factor out center_dq_windows(), which is common code between
stage 2 and stage 3 of the calibration again and cater for
the minor differences.
Signed-off-by: Marek Vasut <marex@denx.de>
Factor out the get_window_mid_index() for finding the best DQ
window centering. This is again code common to two stages, so
pull it out.
Signed-off-by: Marek Vasut <marex@denx.de>
First of all, don't break strings in the debug_cond() calls across
multiple lines. Next, zap a couple of really odd casts in the code.
Finally, make i into a signed variable, so it is possible to avoid
constructs of the form:
for (i = FOO;; i--) { <code>; if (i == 0) break; }.
Signed-off-by: Marek Vasut <marex@denx.de>
Factor out common code from search_left_edge() and search_right_edge()
which checks whether searching for the window edge should stop. The
code is almost identical, so pull it into separate function and cater
for the minor differences.
Signed-off-by: Marek Vasut <marex@denx.de>
Factor out common code from rw_mgr_mem_calibrate_writes_center()
and rw_mgr_mem_calibrate_vfifo_center() for searching for the
left edge of the window. The code is almost identical, so pull
it into separate function and cater for the minor differences.
Signed-off-by: Marek Vasut <marex@denx.de>
Factor out common code from rw_mgr_mem_calibrate_writes_center()
and rw_mgr_mem_calibrate_vfifo_center() for searching for the
right edge of the window. The code is almost identical, so pull
it into separate function and cater for the minor differences.
Signed-off-by: Marek Vasut <marex@denx.de>
Reorder the content of the function a little and fix the comments
so they at least become full sentences. Constify function args.
Fix the return value to match the common convention of 0 meaning
success.
Signed-off-by: Marek Vasut <marex@denx.de>
The C language has signed types, so make use of them. Fix this
obscene loop, which tries to do away with unsigned type, but
just makes the code more cryptic.
Signed-off-by: Marek Vasut <marex@denx.de>
Clean up the debug output handling at the end of the function
and factor out common function call from the condition.
Signed-off-by: Marek Vasut <marex@denx.de>
Implement common sdr_find_phase_delay() function and convert all
places which use such code to this unified function. No functional
change to the code.
Signed-off-by: Marek Vasut <marex@denx.de>
If d != 0 after sdr_working_phase() finishes, the else branch
of the condition has no impact on anything at all, since work_end
was already set independently of the value of "d" . Zap this
useless code.
Signed-off-by: Marek Vasut <marex@denx.de>
Fix data types, constify where applicable, fix comments and debug
strings. In case enough failing reads are detected, just return
right away instead of breaking from the loop. This lets us make
the error handling at the end much simpler.
Signed-off-by: Marek Vasut <marex@denx.de>
Pluck out all this VFIFO value counting, which turns out to be
completely unused. Thus, remove it to simplify the code.
Signed-off-by: Marek Vasut <marex@denx.de>
The "d" variable is set to 0 in sdr_backup_phase() and is not used
at all in sdr_nonworking_phase(). Make it local and zap it respectively.
Signed-off-by: Marek Vasut <marex@denx.de>
Wrap dtaps_per_ptap into the sdr_working_phase() function to trim
down the number of params. It's a constant too.
Signed-off-by: Marek Vasut <marex@denx.de>
It is now clear that the max_working_cnt variable is totally unused.
Zap the variable and zap other variables which became unused due to
this change too.
Signed-off-by: Marek Vasut <marex@denx.de>
Pull out the loop for eaching working/non-working DQS enable phase
into a separate function, as this is mostly common code between.
Clean up sdr_working_phase() and sdr_nonworking_phase() while switching
these two functions to the common sdr_find_phase().
Signed-off-by: Marek Vasut <marex@denx.de>
Get rid of found_{begin,end} variables. Instead of breaking out
through all of the loops, just return when the begin/end of the
window is found and be done with it. Also clean up the trailing
conditional expression, which is now much easier.
Signed-off-by: Marek Vasut <marex@denx.de>
Fix the arguments passed to these functions. The bit_chk is
overriden by rw_mgr_mem_calibrate_read_test_all_ranks() which
is invoked by all three sdr_*_phase() functions, so just make
this into local variable.
Signed-off-by: Marek Vasut <marex@denx.de>
Fix the arguments passed to these functions. The grp argument
does not have to be passed via reference, it's never modified
within either of those functions, so make it into a value.
Signed-off-by: Marek Vasut <marex@denx.de>
Reorder the end of the function a little by moving the conditional
debug output around a little. Rename the function from _centre() to
_center(). Document the function in kerneldoc.
Signed-off-by: Marek Vasut <marex@denx.de>
This function is a treasure trove of ad-hoc iterative
implementations of mathematical functions. Replace all
of those with their non-iterative counterpart.
Signed-off-by: Marek Vasut <marex@denx.de>
Clean up the arguments of this function. Most of the pointers
passed into the function are either not needed at all, or can
be passed as value instead of reference. Also fix the broken
multiline debug strings. No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
This function is only invoked from rw_mgr_mem_calibrate_dqs_enable_calibration()
and at this point, it is just one level of indirection, so wrap the
rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay() into
rw_mgr_mem_calibrate_dqs_enable_calibration() to get rid of the level
of indirection.
Signed-off-by: Marek Vasut <marex@denx.de>
Replace at least one of the loops in this function with call of a
standard function call instead of the ad-hoc implementation. The
other one cannot be replaced, since the delay is incremented for
each group.
Signed-off-by: Marek Vasut <marex@denx.de>
The read_group and write_group params have the same value for all (one)
invocations of this function, just merge them into a single param.
Signed-off-by: Marek Vasut <marex@denx.de>
Start cleaning up this function. In the first part, just fix
the incorrectly broken debug strings and fix return value to
respect the common convention.
Signed-off-by: Marek Vasut <marex@denx.de>
Rework this function such that the code is more readable. Zap
unused parameter "num_tries" while at it. Also wrap parameter
"bit_chk" into this function as it's value is not used outside.
Finally, fix the return value from this function to match the
common expectation, where 0 means success.
Signed-off-by: Marek Vasut <marex@denx.de>
This function is called from one single place and it's sole purpose
is to call one single function with slightly modified arguments.
Zap this function to skip this useless intermediate step.
Signed-off-by: Marek Vasut <marex@denx.de>
Just extract this piece of functionality into separate function
to make the code better separated. This matches the division in
Altera documentation, Altera EMI_RM 2015.05.04 , section 1, the
UniPHY Calibration Stages.
Signed-off-by: Marek Vasut <marex@denx.de>
Just extract this piece of functionality into separate function
to make the code better separated. This matches the division in
Altera documentation, Altera EMI_RM 2015.05.04 , section 1, the
UniPHY Calibration Stages.
Signed-off-by: Marek Vasut <marex@denx.de>
Just extract this piece of functionality into separate function
to make the code better separated. This matches the division in
Altera documentation, Altera EMI_RM 2015.05.04 , section 1, the
UniPHY Calibration Stages.
Signed-off-by: Marek Vasut <marex@denx.de>
This is kind of microseries-within-series indent cleanup.
It is clear that the read_group and write_group variables
have the same value, to just make them into one variable
called rw_group. While doing this, constify the variables
as they are constant.
It is likely that this patch has checkpatch warnings, but
for the sake of not breaking the code, these are ignored.
No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
This is kind of microseries-within-series indent cleanup.
This patch fixes the broken formatting strings in debug_cond()
invocations.
It is likely that this patch has checkpatch warnings, but
for the sake of not breaking the code, these are ignored.
No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
This is kind of microseries-within-series indent cleanup.
This patch cleans up the handling of grp_calibrated such
that the variable isn't used all over the place, but just
very localy. This allows trimming down the indent issues.
It is likely that this patch has checkpatch warnings, but
for the sake of not breaking the code, these are ignored.
No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
This is kind of microseries-within-series indent cleanup.
This patch just tweaks the indentation so it is visible
what to do with the grp_calibrated variable.
It is likely that this patch has checkpatch warnings, but
for the sake of not breaking the code, these are ignored.
No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
This is kind of microseries-within-series indent cleanup.
This patch just tweaks the indentation so it is visible
what is supposed to go where.
It is likely that this patch has checkpatch warnings, but
for the sake of not breaking the code, these are ignored.
No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
This patch just adds an expanded documentation header to the
aforementioned function. This is needed to make it easier to
match the purpose of this function with the documentation.
No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
This is kind of microseries-within-series indent cleanup.
Rework the code for the the middle-loop of the mega-loop
this time and deal with the group_failed variable. Instead
of checking if the group failed in the previous calibration
part, just jump to the end of the loop if calibration did
fail and increment the counter. This shaves away one more
level of indent while making the code slightly more readable.
It is likely that this patch has checkpatch warnings, but
for the sake of not breaking the code, these are ignored.
No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
This is kind of microseries-within-series indent cleanup.
Rework the code for the last loop within the mega-loop
to make it actually readable and not an insane cryptic pile
of indent failure.
It is likely that this patch has checkpatch warnings, but
for the sake of not breaking the code, these are ignored.
No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
This is kind of microseries-within-series indent cleanup.
Rework the code for the third loop within the middle-loop
of the mega-loop to make it actually readable and not an
insane cryptic pile of indent failure.
It is likely that this patch has checkpatch warnings, but
for the sake of not breaking the code, these are ignored.
No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
This is kind of microseries-within-series indent cleanup.
Rework the code for the second loop within the middle-loop
of the mega-loop to make it actually readable and not an
insane cryptic pile of indent failure.
It is likely that this patch has checkpatch warnings, but
for the sake of not breaking the code, these are ignored.
No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
This is kind of microseries-within-series indent cleanup.
Rework the code for the first loop within the middle-loop
of the mega-loop to make it actually readable and not an
insane cryptic pile of indent failure.
It is likely that this patch has checkpatch warnings, but
for the sake of not breaking the code, these are ignored.
No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
Redo the mega-condition such that if the calibration is to be skipped,
the positive branch of the condition does all the work and returns.
The negative branch, which is in fact the default behavior, is then
converted to a code which is no longer conditional. This trims down
the indent by one level.
Signed-off-by: Marek Vasut <marex@denx.de>
Perform minor coding style cleanup of the mem_skip_calibrate() function,
clean up comments and add kerneldoc. No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
Turn the big inner if (RW_MGR_MEM_NUMBER_OF_RANKS == ...) conditional
into a switch {} statement instead. No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
First, invert the logic of the if (odt_mode == ...) conditional to make
the OFF mode harder to miss. It is a short piece of code right at the
end, so move it up.
Also, clean up data types and constify where applicable and clean up
the cs_and_odt_mask assignment. No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
Clean mem_config() function. First, reorder the math done in the
function such that WLAT and RLAT computation is together. Then,
scrap contradictory comments which do not match the result of the
math at all. Next, extract the mem_precharge_and_activate() call
from the end of the function as it is completely unrelated here.
Finally, rename the function to mem_init_latency().
Signed-off-by: Marek Vasut <marex@denx.de>
Clean the function up slightly by using clrsetbits_le32() to flip
bits in registers instead of cryptic bitmasks. Zap condition checking
for PHY_DEBUG_IN_DEBUG_MODE flag, which is never set. Split the
calibration report into separate debug_mem_calibrate() function.
Signed-off-by: Marek Vasut <marex@denx.de>
Init both structures with zeroes and zap all those zeroing shenanigans
further down in the sdram_calibration_full().
Signed-off-by: Marek Vasut <marex@denx.de>
Clean the function up by getting rid of all the insane XOR-leftshift
combos when assembling register values. While at it, remove all the
ad-hoc variables necessary for this XOR-leftshift voodoo. Finally,
get rid of the iterative division implementation of two constants
and replace it with a DIV_ROUND_UP() macro :-)
Signed-off-by: Marek Vasut <marex@denx.de>
Contemporary CPUs can perform division just fine, use this
functionality and zap another implementation of iterative
division :-)
Signed-off-by: Marek Vasut <marex@denx.de>
Factor out almost common code from rw_mgr_mem_handoff() and
rw_mgr_mem_initialize() into separate rw_mgr_mem_load_user().
No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
Clean the DQS and OCT parts of the function, clean up the chopped
formatting strings in debug_cond() and slightly improve the code.
Zap group_bgn argument as it is used only in debug messages. Document
the function using kerneldoc. No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
Apparently, in case of the DQ and DM, the value if the new_delay variable
is calculated, but the value is not used. Zap the entire code which does
calculate the value.
It is not clear to me whether or not the code is doing the right thing
in the first place. Right now, it calls scc_mgr_load_dq() and
scc_mgr_load_dm() respectively, but I suspect it might need to call
scc_mgr_apply_group_dq_out1_delay() and scc_mgr_apply_group_dm_out1_delay()
instead. This is something Altera must investigate.
Signed-off-by: Marek Vasut <marex@denx.de>
First, zap unused argument of the function. Next, clean up
the data types, constify where applicable, clean up comments
and add kerneldoc.
Signed-off-by: Marek Vasut <marex@denx.de>
Move scc_mgr_set_hhp_extras() out of scc_set_bypass_mode() as it
has nothing to do in there. Instead, invoke it from mem_calibrate()
just before invoking scc_set_bypass_mode().
Signed-off-by: Marek Vasut <marex@denx.de>
Minor coding style cleanup for this function. Furthermore, move
ad-hoc debug_cond() calls from the only location from where this
function is invoked into this actual function.
Signed-off-by: Marek Vasut <marex@denx.de>
Make this function more readable, no functional change. Also, zap the
forward declaration, which is no longer needed.
Signed-off-by: Marek Vasut <marex@denx.de>
Implement universal scc_mgr_set_all_ranks() function and convert
various ad-hoc implementations of similar functionality to use
this single function. Document the function in kerneldoc.
Signed-off-by: Marek Vasut <marex@denx.de>
Implement unified scc_mgr_set() function and convert all those
9 scc_mgr_set_*() ad-hoc functions to call this one function.
Signed-off-by: Marek Vasut <marex@denx.de>
This patch just puts functions which look similar next to each
other, so they can be sorted out. No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
Turn the insides of these functions into trivial clrsetbits_le32()
and fix the data type of their argument to reflect it's actual size.
Signed-off-by: Marek Vasut <marex@denx.de>
Remove the remaining invocations of sdr_get_addr() and the function
itself. This makes the code a bit less cryptic.
Signed-off-by: Marek Vasut <marex@denx.de>
Add build target for generating boot partition images recognised by
the SoCFPGA BootROM. The SoCFPGA BootROM expects four copies of the
u-boot-spl-dtb.sfp at the beginning of boot partition. Those are
u-boot-spl-dtb.bin augmented by a header with which the BootROM can
work. The u-boot-dtb.img uImage is appended to this to produce a
full boot partition image, the u-boot-with-spl-dtb.sfp . This is
the name of the final target.
Signed-off-by: Marek Vasut <marex@denx.de>
Enable the mtdparts command and related options to make support
for SPI NOR MTD useful in any way. With the mtdparts command in
place, it is possible to use partition of the SPI NOR in U-Boot.
Signed-off-by: Marek Vasut <marex@denx.de>
Setting LOADADDR to 0x8000 is a bad idea, it is very likely that
some kind of overlap will happen. Move the LOADADDR 0x01000000
(16MiB from start of RAM) to make sure no overlap happens when
loading kernel for example.
Signed-off-by: Marek Vasut <marex@denx.de>
This is needed to access broken (read: Micron) SPI flashes which
are larger than 16 MiB and don't correctly support 4-byte addressing.
Signed-off-by: Marek Vasut <marex@denx.de>
We do not need full MTD support in the SPL build, it only adds size
and is not usable in any way. Exclude it.
Signed-off-by: Marek Vasut <marex@denx.de>
There is no need to disable support for partitions in the SPL,
we can support partitions in SPL perfectly well. This is likely
some remnant from old times, so just remove this configuration
option.
Moreover, the CRC32 chunk size doesn't have to be adjusted anymore,
since both the GD and malloc area are in RAM by the time this CRC
check can be used and there's plenty of space. Zap this abomination
as well.
Signed-off-by: Marek Vasut <marex@denx.de>
Now that the SPL structure is organised such that it matches the
U-Boot's SPL design, it is possible to use the option of relocating
GD to RAM. And since we have GD in RAM, move malloc area to RAM as
well. We point the malloc base pointer 1 MiB past U-Boot's load
address. We use simple malloc for SPL because it is 3kiB smaller
in terms of code size than regular malloc which was used thus far.
Signed-off-by: Marek Vasut <marex@denx.de>
Reset the GMAC ethernets based on the "resets" OF node instead of ad-hoc
hardcoded values in the U-Boot code. Since we don't have a proper reset
framework in place yet, we have to do this slightly ad-hoc parsing of the
OF tree instead.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
setenv an environment variable called "bootmode" , which contains the
board boot mode. This can be in turn used in scripts to determine from
where to load kernel and such.
Signed-off-by: Marek Vasut <marex@denx.de>
Add support for printing from which device the SoCFPGA board booted.
This decodes the BSEL settings and prints it in human readable form.
Signed-off-by: Marek Vasut <marex@denx.de>
Write necessary magic value into the Warm Boot from ON-Chip RAM
group Enable register to enable Warm reset support. Instead of
doing this in the reset_cpu() function, we do it in arch early
init to avoid breaking old kernel code which expects this magic
value to be already written into this register.
This magic is originally excavated from common/spl/spl.c in the
u-boot port from altera, where this value was written just before
the SPL jumped to actual U-Boot in the RAM.
Signed-off-by: Marek Vasut <marex@denx.de>
Rework spl_boot_device() such that it reads the BSEL settings from
system manager and decides from where to load U-Boot based on this
information.
Signed-off-by: Marek Vasut <marex@denx.de>
Add code and configuration options to support booting from QSPI NOR.
Enable support for booting from QSPI NOR.
Signed-off-by: Marek Vasut <marex@denx.de>
Add code and configuration options to support booting from RAW
SD/MMC card as well as for ext4/vfat filesystems. Enable support
for booting from SD/MMC card, but don't enable the filesystem
support just yet to retain compatibility with old SoCFPGA card
format.
Signed-off-by: Marek Vasut <marex@denx.de>
Remove the custom SPL linker script, use the generic one instead.
The custom script doesn't bring in anything new and is only burden
to maintain.
Signed-off-by: Marek Vasut <marex@denx.de>
The code in spl_board_init() should have been in board_init_f()
from the beginning, since it is code which configures system and
then starts DRAM. Thus, it cannot be in spl_board_init(), which
is called from board_init_r() , which already expects a working
DRAM.
Signed-off-by: Marek Vasut <marex@denx.de>
Make sure that all the peripherals are correctly reset and then
brought out of reset in the SPL. Not going through proper reset
cycle might leave the IP blocks in inconsistent state.
Signed-off-by: Marek Vasut <marex@denx.de>
Configure the ARM SCU and NIC301 very early. The ARM SCU SNSAC register
must be configured, so we can access all peripherals. The NIC-301 must
be configured so that the BootROM is not mapped into the SDRAM address
space.
Signed-off-by: Marek Vasut <marex@denx.de>
Synchronise the SPL behavior with the original Altera code and
toggle the Warm Reset Config I/O bit accordingly.
Signed-off-by: Marek Vasut <marex@denx.de>
Implement new accessor, sysmgr_get_pinmux_table(), used to obtain pinmux
table and it's size from the QTS-generated pinmux_config.c. The target
here is again to get rid of poluting global namespace by including the
pinmux_config.h into it.
Furthermore, the pinmux_config.h declares some CONFIG_HPS_* macros,
which are explicitly useless to us in U-Boot. Instead, U-Boot does
use DT to detect exactly these configuration options. This patch
makes sure that while this QTS-generated file can stay in the tree,
these obscure macros do not ooze into the namespace anymore.
Signed-off-by: Marek Vasut <marex@denx.de>
Rework sysmgr_enable_warmrstcfgio() into sysmgr_config_warmrstcfgio(),
which allows both enabling and disabling the warm reset config I/O
functionality.
Signed-off-by: Marek Vasut <marex@denx.de>
Introduce accessor iocsr_get_config_table() for retrieving IOCSR config
tables. This patch is again trimming down the namespace polution.
The IOCSR config tables are used only by scan manager, they are generated
by qts and are board specific. Before this patch, the approach to use
these tables in scan manager was to define an extern variable to silence
the compiler and compile board-specific iocsr_config.c into U-Boot which
defined those extern variables. Furthermore, since these are tables and
the scan manager needs to know the size of those tables, iocsr_config.h
is included build-wide.
This patch wraps all this into a single accessor which takes the scan
chain ID and returns pointer to the table and it's size. All this is
wrapped in wrap_iocsr_config.c board-specific file. The file includes
the iocsr_config.c (!) to access the original tables and transitively
iocsr_config.h . It is thus no longer necessary to include iocsr_config.h
build-wide and the namespace polution is trimmed some more.
Signed-off-by: Marek Vasut <marex@denx.de>
It is sufficient to pass in the scan chain ID into the function to determine
the remaining two parameters, so drop those params and determine them locally
in the function. The big-ish switch in the function is temporary and will be
replaced by a proper function call in subsequent patch.
Signed-off-by: Marek Vasut <marex@denx.de>
This function is never used outside of scan_manager.c , so make it static.
Zap the prototype in scan_manager.h and move the documentation above the
function. Make the documentation kerneldoc compliant.
Signed-off-by: Marek Vasut <marex@denx.de>
Extract the clock configuration horribleness caused by pll_config.h in
the following manner.
First of all, introduce a few new accessors which return values of
various clocks used in clock_manager.c and use them in clock_manager.c .
These accessors replace those few macros which came from pll_config.h
originally. Also introduce an accessor which returns the struct cm_config
default configuration for the clock manager used in SPL.
The accessors are implemented in a board-specific wrap_pll_config.c
file, whose sole purpose is to include the qts-generated pll_config.h
and provide only the necessary values to the clock manager.
The purpose of this design is to limit the scope of inclusion for the
pll_config.h , which thus far was included build-wide and poluted the
namespace. With this change, the inclusion is limited to just the new
wrap_pll_config.c file, which in turn provides three simple functions
for the clock_manager.c to use.
Signed-off-by: Marek Vasut <marex@denx.de>
Add socfpga_per_reset_all() function to reset all peripherals
but the L4 watchdog. This is needed in the SPL.
Signed-off-by: Marek Vasut <marex@denx.de>
The current bridge reset code, which de-asserted the bridge reset,
was activelly polling whether the FPGA is programmed and ready and
in case it was (!), the code called hang(). This makes no sense at
all. Repair it such that the code instead checks whether the FPGA
is programmed, but without any polling involved, and only if it is
programmed, it de-asserts the reset.
Signed-off-by: Marek Vasut <marex@denx.de>
Replace all those ad-hoc reset functions, which were all copies
of the same invocation of clrbits_le32() anyway, with one single
unified function, socfpga_per_reset(), with necessary parameters.
Signed-off-by: Marek Vasut <marex@denx.de>
Implement function socfpga_per_reset(), which allows asserting or
de-asserting reset of each reset manager peripheral in a unified
manner. Use this function throughout reset manager.
Signed-off-by: Marek Vasut <marex@denx.de>
Implement macro SOCFPGA_RESET(name), which produces an abstract
reset number. Implement macros which allow extracting the reset
offset in permodrstN register and which permodrstN register the
reset is located in from this abstract reset number. Use these
macros throughout the reset manager.
Signed-off-by: Marek Vasut <marex@denx.de>
It is the configuration data that should go into the register,
not the register mask, just like the surrounding code does it.
Fix this typo.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Tom Rini <trini@konsulko.com>
Move the structure prototype from sdram.h header file into sdram.c
source file, since it is used only there and for local purpose only.
There is no point in having it global.
While at this move, fix the data types in the structure from uintNN_t
to uNN and fix the coding style a bit.
Signed-off-by: Marek Vasut <marex@denx.de>
This patch enables the SDRAM controller that is used on Altera's SoCFPGA
family. This patch configures the SDRAM controller based on a configuration
file that is generated from the Quartus tool, sdram_config.h.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Move all the files generated by Quartus into the qts/ subdir of the
board/altera/socfpga dir to make them explicitly separate from the
generic U-Boot code.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
The SPI aliases are completely wrong. First, they point to non-existing
/spi@.* nodes instead of the correct /soc/spi@.* nodes. Second, the use
ad-hoc string instead of a handle. Furthermore, they are copied multiple
times in each board DTS.
So fix it such that we move these into socfpga.dtsi and make them use
the usual handles.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
In case the FPGA bitstream is aligned to 4 bytes, skip the
part of the assembler which handles unaligned bitstream.
Otherwise, that part will loop indefinitelly.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
P2371-0000 is a P2581 or P2530 CPU board married to a P2595 I/O
board. The combination contains SoC, DRAM, eMMC, SD card slot,
HDMI, USB micro-B port, Ethernet via USB3, USB3 host port, SATA,
a GPIO expansion header, and an analog audio jack.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
E2220-1170 is a Tegra210 bringup board with onboard SoC, DRAM,
eMMC, SD card slot, HDMI, USB micro-B port, and sockets for various
expansion modules.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
CONFIG_MAX77620_POWER isn't used anywhere. Don't define it in p2571.h.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
T124/210 requires some specific configuration (VPR setup) to
be performed by the bootloader before the GPU can be used.
For this reason, the GPU node in the device tree is disabled
by default. This patch enables the node if U-boot has performed
VPR configuration.
Boards enabled by this patch are T124's Jetson TK1 and Venice2
and T210's P2571.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Tom Warren <twarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
U-boot is responsible for enabling the GPU DT node after all necessary
configuration (VPR setup for T124) is performed. In order to be able to
check whether this configuration has been performed right before booting
the kernel, make it happen during board_init().
Also move VPR configuration into the more generic gpu.c file, which will
also host other GPU-related functions, and let boards specify
individually whether they need VPR setup or not.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Tom Warren <twarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add a comment block to the top of each generated Tegra pinmux header file
indicating that the file was auto-generated, should not be manually
edited, and with a pointer to the tool and command used to generate it.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Additionally, ARM64 devices typically run a secure monitor in EL3 and
U-Boot in EL2, and set up some secure RAM carve-outs to contain the EL3
code and data. These carve-outs are located at the top of 32-bit address
space. Restrict U-Boot's RAM usage to well below the location of those
carve-outs. Ideally, we would the secure monitor would inform U-Boot of
exactly which RAM it could use at run-time. However, I'm not sure how to
do that at present (and even if such a mechanism does exist, it would
likely not be generic across all forms of secure monitor).
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
At present lower case is used for the regulator names in the device tree.
The kernel uses upper case and U-Boot will require this also since it will
move to a case-sensitive name check.
Signed-off-by: Simon Glass <sjg@chromium.org>
Enable the debug UART and emit a single 'a' early in the init sequence to
show that it is working.
Unfortunately the debug UART implementation needs a stack to work. I cannot
seem to remove this limitation as the absolute 'jmp %eax' instruction goes
off into the weeds.
So this means that the character output cannot be any earlier than
car_init_ret, where memory is available for a stack.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Some devices are bound entirely by probing and do not have the benefit of
a device tree to give them a name. This is very common with PCI and USB. In
most cases this is fine, but we should add an official way to set a device
name. This should be called in the device's bind() method.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This should be used for sandbox. We can convert at least one driver to use
it, but in the meantime, enable the feature so that the code is
build-tested.
Signed-off-by: Simon Glass <sjg@chromium.org>
This new command can dump all device resources associated to
each device. The fields in every line shows:
- The address of the resource
- The size of the resource
- The name of the release function
- The stage in which the resource has been acquired (BIND/PROBE)
Currently, there is no driver using devres, but if such drivers are
implemented, the output of this command should look like this:
=> dm devres
- root_driver
- soc
- extbus
- serial@54006800
bfb541e8 (8 byte) devm_kmalloc_release BIND
bfb54440 (4 byte) devm_kmalloc_release PROBE
bfb54460 (4 byte) devm_kmalloc_release PROBE
- serial@54006900
bfb54270 (8 byte) devm_kmalloc_release BIND
- gpio@55000000
- i2c@58780000
bfb5bce8 (12 byte) devm_kmalloc_release PROBE
bfb5bd10 (4 byte) devm_kmalloc_release PROBE
- eeprom
bfb54418 (12 byte) devm_kmalloc_release BIND
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
Currently, Devres requires additional 16 byte for each allocation,
which is not so insignificant in some cases.
Add CONFIG_DEVRES to make this framework optional.
If the option is disabled, devres functions fall back to
non-managed variants. For example, devres_alloc() to kzalloc(),
devm_kmalloc() to kmalloc(), etc.
Because devres_head is also surrounded by an ifdef conditional,
there is no memory overhead when CONFIG_DEVRES is disabled.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Suggested-by: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
devm_kmalloc() is identical to kmalloc() except that the memory
allocated with it is managed and will be automatically released
when the device is removed/unbound.
Likewise for the other variants.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
In U-Boot's driver model, memory is basically allocated and freed
in the core framework. So, low level drivers generally only have
to specify the size of needed memory with .priv_auto_alloc_size,
.platdata_auto_alloc_size, etc. Nevertheless, some drivers still
need to allocate/free memory on their own in case they cannot
statically know the necessary memory size. So, I believe it is
reasonable enough to port Devres into U-boot.
Devres, which originates in Linux, manages device resources for each
device and automatically releases them on driver detach. With devres,
device resources are guaranteed to be freed whether initialization
fails half-way or the device gets detached.
The basic idea is totally the same to that of Linux, but I tweaked
it a bit so that it fits in U-Boot's driver model.
In U-Boot, drivers are activated in two steps: binding and probing.
Binding puts a driver and a device together. It is just data
manipulation on the system memory, so nothing has happened on the
hardware device at this moment. When the device is really used, it
is probed. Probing initializes the real hardware device to make it
really ready for use.
So, the resources acquired during the probing process must be freed
when the device is removed. Likewise, what has been allocated in
binding should be released when the device is unbound. The struct
devres has a member "probe" to remember when the resource was
allocated.
CONFIG_DEBUG_DEVRES is also supported for easier debugging.
If enabled, debug messages are printed each time a resource is
allocated/freed.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
Currently, we only have DM_FLAG_ACTIVATED to indicate the device
status, but we still cannot know in which stage is in progress,
binding or probing.
This commit introduces a new flag, DM_FLAG_BOUND, which is set when
the device is really bound, and cleared when it is unbound.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
The 'ranges' property can be used to specify a translation from the system
address to the bus address. Add support for this using the dev_get_addr()
function, which devices should use to find their address.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present struct eth_device is passed around all over the place. This does
not exist with driver model. Add explicit arguments instead, so that with
driver model we can pass the correct things.
Signed-off-by: Simon Glass <sjg@chromium.org>
The AX_ prefix comes from the Asix driver. Since this is not that, we should
avoid this confusing prefix.
Signed-off-by: Simon Glass <sjg@chromium.org>
Put all global data in a structure and move (what will be) common code into
common functions. This will make the driver-model conversion much easier.
Signed-off-by: Simon Glass <sjg@chromium.org>
Not all boards use garbage collection in their link step, so we should avoid
adding options that rely on this for prevention of code bloat. Add separate
Kconfig options for syscon and regmap uclasses.
Signed-off-by: Simon Glass <sjg@chromium.org>
fdt_addr_t is a physical address. It can be either 64-bit or 32-bit,
depending on the architecture. It should be phys_addr_t instead of
u64 or u32. Similarly, fdt_size_t is changed to phys_size_t.
Signed-off-by: York Sun <yorksun@freescale.com>
CC: Simon Glass <sjg@chromium.org>
fdt_addr_t is changed to phys_addr_t. The format in debug should be updated
to %pa to match the type.
Signed-off-by: York Sun <yorksun@freescale.com>
CC: Simon Glass <sjg@chromium.org>
Spring is the first ARM-based HP Chromebook 11. It is similar to snow
and it uses the same Samsung Exynos5250 chip. But has some unusual
features. Mainline support for it has lagged snow (both in kernel and
U-Boot). Now that the exynos5 code is common we can support spring just
by adding a device tree and a few lines of configuration.
Signed-off-by: Simon Glass <sjg@chromium.org>
Remove the old drivers (both the normal one and the cros_ec one) now that
we have new drivers that use driver model.
Signed-off-by: Simon Glass <sjg@chromium.org>
Now that most exynos5250 boards can use the generic exynos5 code, switch
over to it and remove the old code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Now that exynos5420 boards can use the generic exynos5 code, switch over to
it and remove the old code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
Many options are duplicated on the exynos5 boards. Move these to the common
files. Also some options are not used so can be removed.
Tidy this up to make the files easier to maintain.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
Some boards use device tree for almost all board-specific configuration.
They therefore do not need their own separate board code, but can all use
the same version. Add a common version of the board code. It uses the
PMIC, regulator and video bridge uclasses. This will support smdk5250,
smdk5420, snow, spring, pit and pi.
Signed-off-by: Simon Glass <sjg@chromium.org>
While the AP can access the main PMIC on snow, it must coordinate with the
EC which also wants access. Drop the old definition, which can in principle
generate collision errors. We will use the new arbitration driver instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
The new driver supports driver model and configuration via device tree. Add
a node for pit, which needs this driver.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add a description of the snow memory layout to assist flashing tools which
want to be able to deal with any exynos image.
Signed-off-by: Simon Glass <sjg@chromium.org>
Since a gpio_desc is allowed to be invalid we should return an error
indicating that the operation cannot be completed. This can happen if the
GPIO is optional - e.g. some devices may have a reset line and some may
not.
Signed-off-by: Simon Glass <sjg@chromium.org>
Line up the display with the line below, e.g.:
CPU: Exynos5250 @ 1.7 GHz
Model: Google Spring
DRAM: 2 GiB
MMC: EXYNOS DWMMC: 0
Also show the speed as GHz where appropriate.
Signed-off-by: Simon Glass <sjg@chromium.org>
We should not print a message from the driver when the display is set up.
This is normal behaviour. Change this message to use debug().
Also remove the double newline on another debug message.
Signed-off-by: Simon Glass <sjg@chromium.org>
Since the timeout is reported through normal channels, and is sometimes
expected (e.g. if the bus is being probed for a non-existent device),
don't display the message in the driver.
In general, drivers should not write to the console as this limits their
usefulness in error conditions.
Signed-off-by: Simon Glass <sjg@chromium.org>
This chip provides an eDP to LVDS bridge which is useful for SoCs that don't
support LVDS displays (or it would waste scarce pins). There is no setup
required by this chip, other than to adjust power-down and reset pins, and
those are managed by the uclass.
Signed-off-by: Simon Glass <sjg@chromium.org>
This chip provides an eDP to LVDS bridge which is useful for SoCs that don't
support LVDS displays (or it would waste scarce pins). The setup is included
in the device tree.
Signed-off-by: Simon Glass <sjg@chromium.org>
We haven't quite got pinctrl ready to apply to mainline. We don't want to
GPIO pull-up/down support to the driver model GPIO layer either. So work
around this for now.
We can address this when pinctrl is complete.
Signed-off-by: Simon Glass <sjg@chromium.org>
A video bridge typically converts video from one format to another, e.g.
DisplayPort to LVDS. Add driver model support for these with a simple
interface to control activation and backlight. The uclass supports GPIO
control of power and reset lines.
Signed-off-by: Simon Glass <sjg@chromium.org>
When a regulator command cannot honour the requested voltage, display the
limits to try to be helpful.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
Not all regulators can be set up automatically. Adjust the code so that
regulators_enable_boot_on() will return success when some are skipped.
Only genuine errors are reported.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
Some regulators use the wrong voltage register and thus it is not possible
to control them. Fix this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
This should write the register, not read it. Fix this bug.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
The driver name should not have a space in it. Also the regulator names
should match the case of the device tree. Fix these problems.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
This PMIC is used with SoCs which need a combination of BUCKs and LDOs. The
driver supports changing voltage and enabling/disabling each regulator. It
supports the standard device tree binding and supports driver model.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
This PMIC is used with SoCs which need a combination of BUCKs and LDOs. The
driver supports probing and basic register access. It supports the standard
device tree binding and supports driver model. A regulator driver can be
provided also.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
The TPS65090 has 7 FETs which are modelled as regulators. This allows them
to be controlled by drivers easier, accessed through the 'regulator' command
and used by other drivers.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
The existing TPS65090 driver does not support driver model. Add a new one
that does. This can be used as a base for a regulator driver also. It uses
the standard device tree binding.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
As a debugging aid, allow UART3 to be used as a debug UART in SPL. This
is a precursor to proper UART support, which requires a substantial
refactor.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add a debug UART implementation for this serial driver. It does not set up
pinmux automatically - this must be done before calling debug_uart_init().
Signed-off-by: Simon Glass <sjg@chromium.org>
The debug UART code needs to perform the same init as the normal UART
driver. In preparation for this, move the init code into two functions, one
for the basic init and one for setting the baud rate. This will make adding
debug UART support easier.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add a driver to support the special LDO access used by spring. This is a
custom method in the cros_ec protocol - it does not use an I2C
pass-through.
There are two implementation choices:
1. Write a special LDO driver which can talk across the EC. Duplicate all
the logic from TPS65090 for retrying when the LDO fails to come up.
2. Write a special I2C bus driver which pretends to be a TPS65090 and
transfers reads and writes using the LDO message.
Either is distasteful. The latter method is chosen since it results in less
code duplication and a fairly simple (30-line) implementation of the core
logic.
The crosec 'ldo' subcommand could be removed (since i2c md/mw will work
instead) but is retained as a convenience.
Signed-off-by: Simon Glass <sjg@chromium.org>
The Chrome OS EC supports tunnelling through to an I2C bus on the EC. This
currently uses a copy of the I2C command code and a special 'crosec'
sub-command.
With driver model we can define an I2C bus which tunnels through to the EC,
and use the normal 'i2c' command to access it. This simplifies the code and
removes some duplication.
Add an I2C driver which tunnels through to the EC. Adjust the EC code to
support binding child devices so that it can be set up. Adjust the existing
I2C xfer function to fit driver model better.
For now the old code remains to allow things to still work. It will be
removed in a later patch once the new flow is fully enabled.
Signed-off-by: Simon Glass <sjg@chromium.org>
On pit and pi the TPS65090 regulator is connected only to the EC and we
must use a tunnel to get to it. The existing U-Boot support relies on a
special driver. Add a tunnel definition so that the new device-model
TPS65090 driver can be used unmodified.
Signed-off-by: Simon Glass <sjg@chromium.org>
Snow and smdk5250 use a max77686 PMIC. We have a driver for this, so add
the relevant node to the device tree so it can be used.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
The kernel uses upper case for I2C unit addresses. Follow the same
convention to reduce differences.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
The existing driver model implementation uses the old non-driver-model code
to operate, but has become impossibly tangled as a result. The actual
algorithm is quite simple.
Also the normal-speed and high-speed buses are quite different and it
doesn't seem that useful to put them in the same driver.
Finally, there is a bug which breaks communication with the Maxim sound
codec and may cause problems with other device.
Rewrite the driver model code for normal-speed operation so that it is
easier to understand, and fix the bug. Add a TODO to split the drivers.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
This function should not use mixed case, and it is simpler to use
clrbits_le32() when clearing bits. Fix it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
While I2C supports multi-master buses this is difficult to get right.
The implementation on the master side in software is quite complex.
Clock-stretching and the arbitrary time that an I2C transaction can take
make it difficult to share the bus fairly in the face of high traffic.
When one or more masters can be reset independently part-way through a
transaction it is hard to know the state of the bus.
This driver provides a scheme based on two 'claim' GPIOs, one driven by the
AP (Application Processor, meaning the main CPU) and one driven by the EC
(Embedded Controller, a small CPU aimed at handling system tasks). With
these they can communicate and reliably share the bus. This scheme has
minimal overhead and involves very little code. It is used on snow to
permit the EC and the AP to share access to the main system PMIC and
battery. The scheme can survive reboots by either side without difficulty.
This scheme has been tested in the field with millions of devices.
Since U-Boot runs on the AP, the terminology used is 'our' claim GPIO,
meaning the AP's, and 'their' claim GPIO, meaning the EC's. This terminology
is used by the device tree bindings in Linux also.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add a new I2C_MUX uclass. Devices in this class can multiplex between
several I2C buses, selecting them one at a time for use by the system.
The multiplexing mechanism is left to the driver to decide - it may be
controlled by GPIOs, for example.
The uclass supports only two methods: select() and deselect().
The current mux state is expected to be stored in the mux itself since
it is the only thing that knows how to make things work. The mux can
record the current state and then avoid switching unless it is necessary.
So select() can be skipped if the mux is already in the correct state.
Also deselect() can be made a nop if required.
Signed-off-by: Simon Glass <sjg@chromium.org>
Sometimes it is useful to be able to transfer a raw I2C message. This
happens when the chip address needs to be set manually, or when the data to
be sent/received is in another buffer.
Add a function to provide access to this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Move the flags and struct definitions higher in the file so that we can
reference them with functions declared in the driver model section.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Add a way to dump the contents of an I2C message for debugging purposes.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
It is common for one node to reference another via a phandle. Add support
for obtaining an attached device by this method. As an example, a node may
have a 'power-supply' property which references a regulator, allowing the
driver to turn on its power.
Signed-off-by: Simon Glass <sjg@chromium.org>
The following commit enforces CONFIG_DM_ETH for USB Ethernet which
breaks any board using CONFIG_USB_HOST_ETHER without CONFIG_DM_ETH
which this patch fixes.
commit 69559093f6
dm: usb: Avoid using USB ethernet with CONFIG_DM_USB and no DM_ETH
Tested on Colibri T20/T30 as well as Apalis T30 with
CONFIG_USB_HOST_ETHER and CONFIG_USB_ETHER_ASIX enabled and a LevelOne
USB-0301 ASIX AX88772 dongle.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Simon Glass <sjg@chromium.org>
Removed NS16550_COM1 #define, not used since there's no SPL for T210
Also changed the number of USB controllers to 1 as only USBD is used.
Signed-off-by: Tom Warren <twarren@nvidia.com>
All T114+ Tegra boards should be using the Kconfig
TEGRA114_SPI switch. Remove it from include/config
and put it into defconfig. Also removed unused
TEGRA114_SPI_CTRLS from T114+ configs.
All Tegra SoCs build OK with this change.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Added PLL variables (dividers mask/shift, lock enable/detect, etc.)
to new pllinfo struct for each Soc/PLL. PLLA/C/D/E/M/P/U/X.
Used pllinfo struct in all clock functions, validated on T210.
Should be equivalent to prior code on T124/114/30/20. Thanks
to Marcel Ziswiler for corrections to the T20/T30 values.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Added 38.4MHz/48MHz entries to pll_x_table for CPU PLL. Needs
to be measured - should be close to 700MHz (1.4G/2).
Note that some freqs aren't in the PLLU table in T210 TRM
(13, 26MHz), so I used the 12MHz table entry for them. They
shouldn't be selected since they're not viable T210 OSC freqs.
Since there are now 2 new OSC defines, all tables (pll_x_table,
PLLU) had to increase by two entries, but since 38.4/48MHz are
not viable osc freqs on T20/30/114, etc, they're just set to 0.
Signed-off-by: Tom Warren <twarren@nvidia.com>
CPU board (E2530) has a fan - turn it on via GPIO to keep
the SoC cool.
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The tegra-common-usb-gadget.h include was causing
some build problems in ci_udc.c with a 64-bit gcc
in an earlier version of the T210 patches, but it
is working fine now, so restore it.
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This was done in the 32-bit AVP loader (SPL) but is
board-specific so should be moved to the CPU portion.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Document the development flow on figuring out PIRQ information
during the U-Boot porting.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
The code in question polls an USB port status via USB_REQ_GET_STATUS
to determine whether there is a device on the port or not. The way to
figure that out is to check two bits. Those are wPortChange[0] and
wPortStatus[0].
The wPortChange[0] indicates whether some kind of a connection status
change happened on a port (a device was plugged or unplugged). The
wPortStatus[0] bit indicates the status of the connection (plugged or
unplugged).
The current code tests whether wPortChange[0] == wPortStatus[0] and
if that's the case, considers the loop polling for the presence of a
USB device on port finished.
This works for most USB sticks, since they come up really quickly and
trigger the USB port change detection before the first iteration of the
detection loop happens. Thus, both wPortChange[0] and wPortStatus[0]
are set to 1 and thus equal. The loop is existed in it's first iteration
and the stick is detected correctly.
The problem is with some obscure USB sticks, which take some time before
they pop up on the bus after the port was enabled. In this case, both
the wPortChange[0] and wPortStatus[0] are 0. They are equal again, so
the loop again exits in the first iteration, but this is incorrect, as
such USB stick didn't have the opportunity to get detected on the bus.
Rework the code such, that it checks for wPortChange[0] first to test
if any connection change happened at all. If no change occured, keep
polling. If a change did occur, test the wPortStatus[0] to see there is
some device present on the port and only if this is the case, break out
of the polling loop.
This patch also trims down the duration of the polling loop from 10s
per port to 1s per port. This is still annoyingly long, but there is
no better option in case of U-Boot unfortunatelly. This change will
most likely increase the duration of 'usb start' on some platforms,
but this is needed to fix a bug.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Hans de Goede <hdegoede@redhat.com>
This patch fixes operation of our on-board AX88772B chip without EEPROM
but with a ethaddr coming from the regular U-Boot environment. This is
a forward port of some remaining parts initially implemented by
Antmicro.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Marek Vasut <marex@denx.de>
usb_stor_reset is only defined when USB storage support is enabled, thus the
function is not declared when such support is missing.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
This adds some config options to the sunxi-common config to enable the USB
download gadget and the fastboot and USB mass storage functions.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Currently, the second use of a gadget will fail, while the first one works.
Forcing the EP0 at every enable fix this issue.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Now that some things were updated in Kconfig, they should be reflected on the
sunxi-common config too.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Now that the musb-new driver has a Kconfig, we can move Kconfig options to
enable controllers to it, so that it's easier in e.g. menuconfig.
In addition, this allows declaring support for USB_MUSB_HOST/GADGET in
defconfigs instead of the USB_MUSB_SUNXI controller, that will get selected
automatically when needed.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Having MUSB_HOST and MUSB_GADGET in Kconfig allows more flexibility with regard
to what Kconfig options to enable, such as USB_STORAGE or USB_KEYBOARD.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
USB-related options are usually prefixed with CONFIG_USB and platform-specific
adaptation for the MUSB controller already have a CONFIG_USB_MUSB prefix, so
this switches all MUSB-related options to a CONFIG_USB_MUSB prefix, for
consistency.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
There is no particular reason why the USB Kconfig option should be specific to
host mode. In prevision of adding MUSB host and gadget to Kconfig, this moves
the title and help message of the USB Kconfig option to a more generic format.
Adding comments to the usb Kconfig allows for a better separation and more
readability in generated configs and in menuconfig.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
The USB_ARCH_HAS_HCD currently serves no purpose and adds some confusion to the
required Kconfig options that are required to have USB support.
Dropping it makes things easier and doesn't break anything, since it was unused
anyways.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
This patch makes the dwc2 controller like ehci / ohci / xhci controllers
by calling the board_usb_init() function from usb_lowlevel_init.
This can then be implemented by specific platforms to initialise
their USB hardware (phys / clocks etc).
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
We cannot use this driver when running from EFI as we have no direct hardware
access. In fact coreboot uses a different driver which uses tables provided
by coreboot. So far it does not seem possible to use a normal video driver
when booting from EFI.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Disable a few things which interfere with the EFI init. This allows QEMU to
to boot into EFI, load a U-Boot payload then boot to the U-Boot prompt.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Disable a few things which interfere with the EFI init. This allows the
Minnowboard MAX to boot into EFI, load a U-Boot payload then boot to the
U-Boot prompt.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
When U-Boot is running from EFI some of the x86 init is replaced with
EFI-specific init. For example, since DRAM has already been set up, we only
need to find it, not init it. Add these functions so that boards can easily
allow booting from EFI if required.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
When U-Boot runs as an EFI payload it needs to avoid setting up the CPU
again. Also U-Boot currently does not handle interrupts for many devices, so
run with interrupts disabled.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The EFI memory map is passed from the stub to U-Boot in a table. Add a
command to display it in a vaguely readable fashion.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested on QEMU
Tested-by: Bin Meng <bmeng.cn@gmail.com>
The EFI stub can pass a table to U-Boot with information about the memory map
Potentially other things will follow. Add a way to access this table.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The EFI stub provides information to U-Boot in a table. This includes the
memory map which is needed to decide where to relocate U-Boot. Collect this
information in the early init code and store it in global_data.
Fix up the BIST code at the same time since we don't have it when booting
from EFI and can assume it is 0.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Most EFI implementations use 64-bit. Add a way to build U-Boot as a 64-bit
EFI payload. The payload unpacks a (32-bit) U-Boot and starts it. This can
be enabled for x86 boards at present.
Signed-off-by: Simon Glass <sjg@chromium.org>
Improvements to how the payload is built:
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
The procedure to drop from 64-bit mode to 32-bit is a bit messy. Add a
function to take care of it. It requires identity-mapped pages and that
the calling code is running below 4GB.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Rather than add these as open-coded values, create an enum with the commonly
used flags.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add support for building a 32/64-bit EFI stub for x86. This involves
building the startup and relocation code for either i386 or x86_64.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
It is useful to be able to load U-Boot onto a board even if is it already
running EFI. This can allow access to the U-Boot command interface, flexible
booting options and easier development.
The easiest way to do this is to build U-Boot as a binary blob and have an
EFI stub copy it into RAM. Add support for this feature, targeting 32-bit
initially.
Also add a way to detect when U-Boot has been loaded via a stub. This goes
in common.h since it needs to be widely available so that we avoid redoing
initialisation that should be skipped.
Signed-off-by: Simon Glass <sjg@chromium.org>
Improvements to how the payload is built:
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Add a linker script and relocation code for building 64-bit EFI
applications. This can be used for the EFI stub.
Signed-off-by: Simon Glass <sjg@chromium.org>
Improvements to how the payload is built:
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This code currently requires CONFIG_SYS_TEXT_BASE but this should be
unnecessary. As a first step, remove the build-time limitation and report an
error instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add the required x86 glue code. This includes the initial start-up,
relocation and jumping to efi_main(). We also need to avoid fiddling with
interrupts.
Signed-off-by: Ben Stoltz <stoltz@google.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Bring in this file from Linux 4.1. It supports relocation features specific
to x86.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
When running as an EFI application we must skip relocation. Add support for
this in the x86 relocation code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add support for building U-Boot as an EFI application with a .efi suffix.
This can be loaded by EFI provided that EFI has the same bit width (32-
or 64-bit) as U-Boot. This unfortunate limitation is imposed by EFI.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
When U-Boot runs as an EFI application is does not have a definition of
CONFIG_SYS_TEXT_BASE. U-Boot is a relocatable application and the relocation
is done by EFI. U-Boot can be loaded at any address.
Ensure that this CONFIG option is not set in this case.
Signed-off-by: Ben Stoltz <stoltz@google.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add a serial driver which makes use of EFI's console in/out service.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested on Intel Crown Bay and QEMU
Tested-by: Bin Meng <bmeng.cn@gmail.com>
When running U-Boot as an EFI application we cannot relocate since we do not
have relocation information. U-Boot has already been relocated to a suitable
address.
Add a global_data flag to control skipping relocation.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The steps required to boot a Linux distribution from U-Boot on x86 are not
very complicated, but it is a good idea to have these written down in an
accessible place.
Document how to examine the boot media from U-Boot, how to load a kernel,
load a ramdisk, set the kernel boot arguments and start the kernel. With
these instructions Ubuntu boots mostly normally on Minnowmax.
Note that the TSC timer does not operate correctly and gives warnings in
the boot log. I expect that ACPI support will solve this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
These are now in the device tree so we don't need to use the CONFIG options.
Drop them.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present this function does not specify its return value. Fix it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present the PCI output displays 'Mem' when it allocates memory for a PCI
device, whether it is prefetchable or not. There is a distinction since the
memory comes from separate pools. Use 'Prf' instead of 'Mem' when allocating
prefetchable memory.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
With EFI the start address of U-Boot is specified differently. We could
consider just setting GD_FLG_RELOC and then setting up reloc_off. But that
flag has other implementations and we are not able to use U-Boot relocation
which this flag implies.
Instead, just add a special case for EFI.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
When U-Boot runs as an EFI application is does not have a definition of
CONFIG_SYS_TEXT_BASE. U-Boot is a relocatable application and the relocation
is done by EFI. U-Boot can be loaded at any address.
This is similar to how sandbox works. Adjust the early board init to deal
with this.
Signed-off-by: Ben Stoltz <stoltz@google.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
When running as an EFI application, U-Boot must request memory from EFI,
and provide access to the boot services U-Boot needs.
Add library code to perform these tasks. This includes efi_main() which is
the entry point from EFI. U-Boot is built as a shared library.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
On x86 the global_data pointer is provided through a somewhat-bizarre and
x86-specific mechanism: the F segment register is set to a pointer to the
start of global_data, so that accesses can use this build-in register.
When running as an EFI application we don't want to mess with the Global
Descriptor Table (GDT) and there is little advantage (in terms of code size)
to doing so.
Allow global_data to be a simple variable in this case.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This option is not used by any board but appears to still be useful, at least
for testing. With recent commits it does not build, so fix it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This file does not need its own way of doing debug(). Clean it up to use the
new way.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Pavel Machek <pavel@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Fix a typo, remove an unused field and make sure to use existing #define
constants instead of open-coded values.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The GDT works but technically the length is incorrect. Fix this and add a
comment.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This is now handled by generic U-Boot code so we do not need an x86 version.
It is no-longer called, so remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
These flags now overlap some global ones. Adjust the x86-specific flags to
avoid this. Since this requires a change to the start.S code, add a way for
tools to find the 32-bit cold reset entry point. Previously this was at a
fixed offset.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add a convention that the generic global_data only occupy the bottom 16 bits
of the flags word, so that there is less chance of a conflict. At present the
x86 flags conflict.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Fix a typo, improve some comments and add a little more detail in some
cases.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
These will be used for efi.h both for U-Boot running as an EFI application
and as a payload. They come from Linux 4.1.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This is currently done for all targets, since 0xff is the default erased
value for most flash devices. In some cases this is not what we want (e.g.
for EFI images) so provide a command to do a vanilla objcopy.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
In a final attempt to find a console UART this function uses the first
first available serial device. However the check for a valid device is
inverted.
This code is only executed when there is in fact no serial UART, but at
present it can fail to reach the panic_str() call in this case, and start
trying to use a non-existent UART.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This function needs to check the list has entries before traversing it.
Fix this bug.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The CFLAGS_REMOVE_<file> feature allows default C compiler flags to be
removed for particular files. Add the same feature for assembler, using
AFLAGS_REMOVE_<file>.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Match the depth of indentation between #ifdef and #endif
for better readability.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
Add PCI IRQ routing information in the board device tree and enable
writing PIRQ routing table and MP table.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Intel Bayley Bay board is a BayTrail based board. Add this board
with existing baytrail fsp support.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
This commit adds the microcode blob for BayTrail-I B0 stepping,
CPUID signature 30671h.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
BayTrail FSP Gold4 release adds one UPD parameter to control IGD
enable/disable.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
On Intel BayTrail SoC, there is a legacy UART (I/O 0x3f8) integrated
into the SoC which is enabled by the FSP. Remove the smsc47x superio
initialization codes.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
We should not set up kernel screen_info when the vesa parameters are
insane, otherwise kernel will panic.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Add a cpu1 node to the device tree and enable the MP initialization
on QEMU targets (i440fx and q35).
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
When running SMP configuration on QEMU (tcg mode, no kvm), there is
a busy loop in start_aps(), calling udelay(), that waits for APs to
show up online. However, there is a chance that VCPU1 will be timeout
waiting, IOW the secondary VCPUs haven't started their execution yet.
This patch adds a 'pause' instruction in __udelay() only for QEMU
target, to give other VCPUs a chance to run. When QEMU sees the
'pause' instruction, it will yeild the execution to other CPUs.
Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
On some platforms pci devices behind bridge need to be probed (eg:
a pci uart on recent x86 chipset) before relocation. Remove such
limitation so that dm pci can be used before relocation.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
This patch replaces not existing addr_uboot environment variable by
loadaddr at get_uboot_net and burn_uboot_xxx commands. Otherwise these
commands are broken.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
Define base address of both usb xhci controllers in lsch3 config
in the format (IMMR + offset) for LS2085A
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Define CONFIG_SYS_CACHELINE_SIZE for LS2085A which is required by
USB XHCI stack for alignment
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
By default the bstopre value has been set to 0x100, used to be 1/4
value of refint. Modern DDR has increased the refresh time. Adjust
to 1/4 of refresh interval dynamically. Individual board can still
override this value in board ddr file, or to use auto-precharge.
Signed-off-by: York Sun <yorksun@freescale.com>
HW coherency won't work properly for CAAM write transactions
if AWCACHE is left to default (POR) value - 4'b0001.
It has to be programmed to 4'b0010.
For platforms that have HW coherency support:
-PPC-based: the update has no effect; CAAM coherency already works
due to the IOMMU (PAMU) driver setting the correct memory coherency
attributes
-ARM-based: the update fixes cache coherency issues,
since IOMMU (SMMU) driver is not programmed to behave similar to PAMU
Fixes: b9eebfade9 ("fsl_sec: Add hardware accelerated SHA256 and SHA1")
Signed-off-by: Horia Geantă <horia.geanta@freescale.com>
Reviewed-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Acked-by: Ruchika Gupta<ruchika.gupta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
The patch will initialize PCIe controller on EP mode
1. Setup bar:
bar0 32bit 4K for specific configuration
bar1 32bit 8K for MSIX
bar2 64bit 4K for descriptor of memory
bar4 64bit 1M for DMA memory test
2. Setup iATU:
iATU inbound 0-3 to map bar transaction to memory address
started at CONFIG_SYS_PCI_EP_MEMORY_BASE
iATU outbound 0 to map 4G memory space
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
PCIe extends device's configuration space to 4k and provides
extended capability. The patch adds function to find them.
The code is ported from Linux PCIe driver.
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: York Sun <yorksun@freescale.com>
MC firware version 8.0.0 contains new command flags. This patch
contains modifications in FLIB files to support the new command flags.
Signed-off-by: Itai Katz <itai.katz@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
The sampling of the oscillator can be done in multiple modes for
generating the entropy value. By default, this is set to von
Neumann. This patch changes the sampling to raw data, since it
has been discovered that the generated entropy has a better
'quality'.
Signed-off-by: Alex Porosanu <alexandru.porosanu@freescale.com>
Acked-by: Ruchika Gupta<ruchika.gupta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
The entropy delay (the length in system clocks of each
entropy sample) for the RNG4 block of CAAM is dependent
on the frequency of the SoC. By elaborate methods, it
has been determined that a good starting value for all
platforms integrating the CAAM IP is 3200. Using a
higher value has additional benefit of speeding up
the process of instantiating the RNG, since the entropy
delay will be increased and instantiation of the RNG
state handles will be reattempted by the driver. If the
starting value is low, for certain platforms, this can
lead to a quite lengthy process.
This patch changes the starting value of the length of
the entropy sample to 3200 system clocks.
In addition to this change, the attempted entropy delay
values are now printed on the console upon initialization
of the RNG block.
Signed-off-by: Alex Porosanu <alexandru.porosanu@freescale.com>
Acked-by: Ruchika Gupta<ruchika.gupta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
The rtfrqmax & rtfrqmin set the bounds of the expected frequency of the
oscillator, when SEC runs at its maximum frequency. For certain platforms
(f.i. T2080), the oscillator is very fast and thus if the SEC runs at
a lower than normal frequency, the ring oscillator is incorrectly detected
as being out of bounds.
This patch effectively disables the maximum frequency check, by setting a
high enough maximum allowable frequency for the oscillator. The reasoning
behind this is that usually a broken oscillator will run too slow
(i.e. not run at all) rather than run too fast.
Signed-off-by: Alex Porosanu <alexandru.porosanu@freescale.com>
Acked-by: Ruchika Gupta<ruchika.gupta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
To improve eTSEC performance on LS1021A Rev2.0,
snooping of all transmit frames from memory and
all transmit BD memory accesses in enabled.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
On LS1021A Rev2.0, OCRAM's security level needs to be changed to
non-secure access for SD boot. This patch will allow OCRAM
access permission as R/W in SPL.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Bootrom will put cpus into WFE state when boot cpu release cpus, so
target cpu cannot correctly go to spin state.
Add 'sev' to wakeup non-boot cpu that hold on bootrom space, let target
cpu can fall into u-boot spin table.
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Enable bootscript support in secure boot for establishing
chain of trust on LS1021atwr.
Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
when using printf, the parameter type need to be compatible
type, so transform them to compatible type
Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Fix:
undefined reference to `spi_flash_free'
undefined reference to `spi_flash_probe'
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Stefan Roese <sr@denx.de>
Cc: Markus Niebel <Markus.Niebel@tq-group.com>
Acked-by: Stefan Roese <sr@denx.de>
1. Define two structures mx6ul_iomux_ddr_regs and mx6ul_iomux_grp_regs.
2. Add a new function mx6ul_dram_iocfg to configure dram io.
3. Refactor MMDC1 macro, discard "#ifdef CONFIG_MX6SX". Since
only mmdc0 channel exists on i.MX6SX/UL, redefine MMDC1 macro support
runtime check, but not hardcoding #ifdef macros.
4. Introduce mx6ul-ddr.h, which includes the register address for DRAM
IO configuration.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
i.MX6UL features an Cortex-A7 core, it does not have PL310 as other i.MX6
chips. To Cortex-A7 core, If D-Cache is enabled, L2 Cache is enabled.
There is on specific switch for on/off L2 Cache, so default select
SYS_L2CACHE_OFF.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
1. Add enet, uart, i2c, ipg clock support for i.MX6UL.
2. Correct get_periph_clk, it should account for
MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK.
3. Refactor get_mmdc_ch0_clk to make all i.MX6 share one function,
but not use 'ifdef'.
4. Use CONFIG_FSL_QSPI for enable_qspi_clk, but not #ifdef CONFIG_MX6SX.
5. Use CONFIG_PCIE_IMX for pcie clock settings, use CONFIG_CMD_SATA for
sata clock settings. In this way, we not need "#if defined(CONFIG_MX6Q)
|| defined....", only need one CONFIG_PCIE_IMX in header file.
Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Since i.MX6UL use A7 core, but not A9 core, we do not need
the erratas for i.MX6UL.
Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Since i.MX6UL's cache line size is 64bytes, need to
define the macro CONFIG_SYS_CACHELINE_SIZE to 64 for i.MX6UL.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
1. Update imx register base address for i.MX6UL.
2. Remove duplicated MXS_APBH/GPMI/BCH_BASE.
3. Remove #ifdef for register addresses that equal to
"AIPS2_OFF_BASE_ADDR + 0x34000" for different chips.
4. According fuse map, complete fuse_bank4_regs.
5. Move AIPS3_ARB_BASE_ADDR and AIPS3_ARB_END_ADDR out of #ifdef CONFIG_MX6SX,
because we can use runtime check
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Add MXC_CPU_MX6UL for i.MX6UL CPU type which is got at runtime from
DIGPROG register. But the value has been occupied by MXC_CPU_MX6D which
is not real id from DIGPROG register, so change i.MX6D to value 0x67 which
was not occupied.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
With recent additions to USB Kconfig the number of USB options had grown
large enough to warrant a separate menu for USB.
Add a Kconfig menu for USB.
Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Add support for selecting display preset using the environment variable
"displaytype". This is a preparation for future merging of compulab
omap3_display.c display selection code with the cm-fx6 display selection code.
The "panel" environment variable is retained for backwards compatibility.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Implement a cm-fx6 specific board_video_skip() to provide the option to not
initialize the display.
The new function does not init display if the environment variable "panel" is
not defined, or if it is set to an unsupported value.
Collateral changes:
- Don't use the global displays array (it's CONFIG_IMX_VIDEO_SKIP specific).
- Don't use detect_hdmi(), since env controlled init makes it unnecessary.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
U-Boot does not explicitly assign the display to an IPU interface. Instead, it
relies on the power-on default of DI0.
Since the kernel reassigns HDMI display to DI1, after a warm reset the HDMI
display no longer works in U-Boot.
Fix this by explicitly assigning HDMI to IPU1 DI0 in U-Boot.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
1. Add DDR script for mx6qpsabreauto board.
2. On CPU3 board, enet RGMII tx clock is from internal PLL. Set the GPR5[9]
and init the enet pll output to 125Mhz.
3. On CPU3 board, SW1ABC=VDDSOC_IN, SW2=VDDARM_IN.
Build target: mx6qpsabreauto_config
Boot Log:
U-Boot 2015.07-rc2-00071-gfd985ff (Jun 29 2015 - 22:10:55 +0800)
CPU: Freescale i.MX6QP rev1.0 996 MHz (running at 792 MHz)
CPU: Automotive temperature grade (-40C to 125C) at 34C
Reset cause: POR
Board: MX6Q-Sabreauto revA
I2C: ready
DRAM: 2 GiB
PMIC: PFUZE100 ID=0x10
Flash: 32 MiB
NAND: 0 MiB
MMC: FSL_SDHC: 0
*** Warning - bad CRC, using default environment
No panel detected: default to HDMI
Display: HDMI (1024x768)
In: serial
Out: serial
Err: serial
Net: FEC [PRIME]
Hit any key to stop autoboot: 0
Note:
In this patch, we still add a new config mx6qpsabreauto_config,
since SPL is not supported now, and IMX_CONFIG is needed at
build time, so add this config. Future, when SPL is converted,
this config can be removed.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Robin Gong <b38343@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Detect the SOC and board variant at runtime and change the dtb name,
but not hardcoding the fdt_file env variable.
Take the following patch as a reference.
Íd58699b157df75f1aa0b363ea9c21add21a0c
"mx6cuboxi: Load the correct 'fdtfile' variable"
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Since i.MX6QP changes some CCM registers, so modify the clocks settings to
follow the hardware changes.
In c files, use runtime check and discard #ifdef.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Add cpu type for i.MX6QP/DP.
This patch also fix is_mx6dqp(), since get_cpu_rev can return MXC_CPU_MX6QP
and MXC_CPU_MX6DP, we should use:
(is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP)).
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
sw variable in checkboard function is storing vbank value
which can only take 3-bit value.
So check of sw value for if greater than 7 is redundant.
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
eMMC has no CD and WP pins, it needs to add board-specific
board_mmc_getcd() and board_mmc_getwp() in SPL to support
eMMC boot without external SD card inserted.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Serdes Lanes availability on T4160 and T4080 are same, which serdes 2 & 3
support 8 Lanes, but serdes 1 & 4 support only 4 Lanes E/F/G/H, Lanes
A/B/C/D are not available, updated the serdes table accordingly with
some minor fix.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Add support for NOR flash and GPIO/I2C switch control on RevC.
- NOR support
- bank0/bank4 switch
- SD/eMMC switch
- board version
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
For running Chain of Trust when doing Secure Boot from NAND,
the Bootscript header and bootscript must be copied from NAND
to RAM(DDR).
The addresses and commands for the same have been defined.
Signed-off-by: Saksham Jain <saksham@freescale.com>
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Secure Boot Target is added for NAND for P5020 and P5040.
The Secure boot target has already been added for P3041 by
enabling CONFIG_SYS_RAMBOOT and configuring CPC as SRAM.
The targets for P5020 and P5040 are added in the same manner.
Signed-off-by: Saksham Jain <saksham@freescale.com>
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Secure Boot Target is added for NAND for P3041.
For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC.
In case of secure boot, this default address maps to Boot ROM.
The Boot ROM code requires that the bootloader(U-boot) must lie
in 0 to 3.5G address space i.e. 0x0 - 0xDFFFFFFF.
In case of NAND Secure Boot, CONFIG_SYS_RAMBOOT is enabled and CPC is
configured as SRAM. U-Boot binary will be located on SRAM configured
at address 0xBFF00000.
In the U-Boot code, TLB entries are created to map the virtual address
0xFFF00000 to physical address 0xBFF00000 of CPC configured as SRAM.
Signed-off-by: Saksham Jain <saksham@freescale.com>
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Commit 488d19c (patman: add distutils based installer) has the side effect
of making patman run twice with each invocation. Fix this by checking for
'main program' invocation in patman.py. This is good practice in any case.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
Added routine mmu_set_region_dcache_behaviour() to set a
particular region as non cacheable.
Define dummy routine for mmu_set_region_dcache_behaviour()
to handle incase of dcache off.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
IFC nand ecc encode and decode mode are not correctly
set in CSOR register during nand initialization.Enable
ecc encode/decode in 4-bit mode
Signed-off-by: Jaiprakash Singh <b44839@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Correct the value CONFIG_USB_MAX_CONTROLLER_COUNT macro to 1
for p1025 as it has one USB controller
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
The board manual desribes ON as boolean 1 and OFF as boolean 0.
Updating README with correct boolean values.
Signed-off-by: Raghav Dogra <raghav@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
MAC1 acts as 1G/10G dual-role MAC on T1024. We introduce
macro SET_FMAN_RX_10G_TYPE2_LIODN for 10G MACs which have
same Port ID and same offset of address with 1G MAC.
Update it to match with the setting of fman in t1024 device
tree, otherwise there is no 'fsl,liodn' in
/proc/device-tree/soc@ffe000000/fman@400000/port@88000/
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Update PBI command in pbi_cfg files to keep register bit
to default reset value while configuring CPC
as SRAM
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Because the function ft_board_setup() delete the USB2 device node, it
leads to can't find the device node and hung up.
In fact only P1020RDB needs to delete the USB2 node, this patch fixes
this issue.
Signed-off-by: Ying Zhang <b40530@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
T1040D4RDB is a Freescale reference board that hosts the T1040 SoC.
T1040D4RDB is re-designed T1040RDB board with following changes :
- Support of DDR4 memory
- Support of 0x66 serdes protocol which can support following interfaces
- 2 RGMII's on DTSEC4, DTSEC5
- 1 SGMII on DTSEC3
- Support of QE-TDM
Similarily T1042D4RDB is a Freescale reference board that hosts the T1040
SoC. T1042D4RDB is re-designed T1042RDB board with following changes :
- Support of DDR4 memory
- Support for 0x86 serdes protocol which can support following interfaces
- 2 RGMII's on DTSEC4, DTSEC5
- 3 SGMII on DTSEC1, DTSEC2 & DTSEC3
- Support of DIU
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Based on Venice2, incorporates Stephen Warren's
latest P2571 pinmux table.
With Thierry Reding's 64-bit build fixes, this
will build and and boot in 64-bit on my P2571
(when used with a 32-bit AVP loader).
Signed-off-by: Tom Warren <twarren@nvidia.com>
Derived from Tegra124, modified as appropriate during T210
board bringup. Cleaned up debug statements to conserve
string space, too. This also adds misc 64-bit changes
from Thierry Reding/Stephen Warren.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
All based off of Tegra124. As a Tegra210 board is brought
up, these may change a bit to match the HW more closely,
but probably 90% of this is identical to T124.
Note that since T210 is a 64-bit build, it has no SPL
component, and hence no cpu.c for Tegra210.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Moved Tegra config options to mach-tegra/Kconfig so that both
32-bit and 64-bit builds can co-exist for Tegra SoCs.
T210 will be 64-bit only (no SPL) and will require a 32-bit
AVP/BPMP loader.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Simon's 'tegra124: Implement spl_was_boot_source()' needs
a prototype for save_boot_params_ret() to build cleanly
for 64-bit Tegra210.
Signed-off-by: Tom Warren <twarren@nvidia.com>
ARMv8 requires an architected timer to be present, so it can be used
instead of the Tegra US timer. This allows for better code reuse.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
A subsequent patch will enable the use of the architected timer on
ARMv8. Doing so implies that udelay() will be backed by this timer
implementation, and hence the architected timer must be ready when
udelay() is first called. The first time udelay() is used is while
resetting the debug UART, which happens very early. Make sure that
arch_timer_init() is called before that.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
For 64-bit ARM SoCs we rely on non-U-Boot code to bring up the CPU in
AArch64 mode so that we don't need the SPL. Non-cached memory is not
implemented (yet) for 64-bit ARM.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
On 64-bit SoCs the I-cache isn't enabled in early code, so the default
cache enable functions for 64-bit ARM can be used.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Most peripherals on Tegra can do DMA only to the lower 32-bit
address space, even on 64-bit SoCs. This limitation is
typically overcome by the use of an IOMMU. Since the IOMMU is
not entirely trivial to set up and serves no other purpose
(I/O protection, ...) in U-Boot, restrict 64-bit Tegra SoCs to
the lower 32-bit address space for RAM. This ensures that the
physical addresses of buffers that are programmed into the
various DMA engines are valid and don't alias to lower addresses.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
While generating the page tables, a running integer index is shifted by
SECTION_SHIFT (29) and causes overflow for any integer bigger than 7.
The page tables therefore alias to the same 8 sections and cause U-Boot
to hang once the MMU is enabled.
Fix this by making the index a 64-bit unsigned integer and so avoid the
overflow.
swarren notes: currently "i" ranges from 0..8191 on all ARM64 boards, and
"j" varies depending on RAM size; from 4 to 11 for a board with 4GB at
physical address 2GB, as some Tegra boards have.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
To make it easier to use patman on other projects add a distutils style
installer. Now patman can be installed with
cd u-boot/tools/patman && python setup.py install
There are also the usual distutils options for creating source/binary
distributions of patman.
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
We should mark PCIe ECAM address range in the E820 table as reserved
otherwise kernel will not attempt to use ECAM.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Currently cpu-x86 driver is probed only for SMP. We add the same
support for UP when there is only one cpu node in the deive tree.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
The PIIX3 chipset does not integrate an I/O APIC, instead it supports
connecting to an external I/O APIC which needs to be enabled manually.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
On some platforms the I/O APIC interrupt pin#0-15 may be connected
to platform pci devices' interrupt pin. In such cases the legacy ISA
IRQ is not available so we should not write ISA interrupt entry if
it is already occupied.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Currently during writing MP table I/O interrupt assignment entry, we
assume the PIRQ is directly mapped to I/O APIC INTPIN#16-23, which
however is not always the case on some platforms.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Commit aec241d "dm: pci: Use the correct hose when configuring devices"
was an attempt to fix pci bridge device configuration, but unfortunately
that does not work 100%. In pciauto_config_devices(), the fix tried to
call pciauto_config_device() with a ctlr_hose which is supposed to be
the root controller hose, however when walking through a pci topology
with 2 or more pci bridges this logic simply fails.
The call chain is: pciauto_config_devices()->pciauto_config_device()
->dm_pci_hose_probe_bus(). Here the call to dm_pci_hose_probe_bus()
does not make any sense as the given hose is not the bridge device's
hose, instead it is either the root controller's hose (case#1: if it
is the 2nd pci bridge), or the bridge's parent bridge's hose (case#2:
if it is the 3rd pci bridge). In both cases the logic is wrong.
For example, for failing case#1 if the bridge device to config has the
same devfn as one of the devices under the root controller, the call
to pci_bus_find_devfn() will return the udevice of that pci device
under the root controller as the bus, but this is wrong as the udevice
is not a bus which does not contain all the necessary bits associated
with the udevice which causes further failures.
To correctly support pci bridge device configuration, we should still
call pciauto_config_device() with the pci bridge's hose directly.
In order to access valid pci region information, we need to refer to
the root controller simply by a call to pci_bus_to_hose(0) and get the
region information there in the pciauto_prescan_setup_bridge(),
pciauto_postscan_setup_bridge() and pciauto_config_device().
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
In dm_pci_hose_probe_bus(), pci_bus_find_devfn() is called with a bdf
which includes a bus number, but it really should not as this routine
only expects a device/function encoding.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Currently pci_bus_read_config() and pci_bus_write_config() are
called with bus number masked off in the parameter bdf, and bus
number is supposed to be added back in the bridge driver's pci
config read/write ops if the device is behind a pci bridge.
However this logic only works for a pci topology where there is
only one bridge off the root controller. If there is addtional
bridge in the system, the logic will create a non-existent bdf
where its bus number gets accumulated across bridges.
To correct this, we change all pci config read/write routines
to use complete bdf all the way up to the root controller.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
In driver model, each pci bridge device has its own hose structure.
hose->first_busno points to the bridge device's device number, so
we should not substract hose->first_busno before programming the
bridge device's primary/secondary/subordinate bus number registers.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
This corrects several typos in the comment block as well as some
indentions and nits in the linker_lists.h.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
The doc wrongly put sandbox in the '--fetch-arch' command. Remove it.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
We need walk through all functions within a PCI device and assign
their IRQs accordingly.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Add a RTC node in the device tree to enable DM RTC support.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
(Squashed in 'x86: Fix RTC build error on ivybridge')
Turn on cache on the pci option rom area to improve the performance.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Instead of using switch..case for architecture defined exceptions,
simply unify the handling by printing a message of exception name,
followed by registers dump then halt the CPU.
With this unification, it also fixes the wrong exception numbers
for #MF/#AC/#MC/#XM which should be 16/17/18/19 not 15/16/17/18.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Some exceptions cause an error code to be saved on the current stack
after the EIP value. We should extract CS/EIP/EFLAGS from different
position on the stack based on the exception number.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Use one command for showing overall CPU status than several without
knowing how many cpus is available in the system.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Adds the two MIO connected pushbuttons on the zc702 board to the
devicetree as a single multi-key device for us with the gpio-keys driver.
Signed-off-by: Ezra Savard <ezra.savard@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Remove unneeded address-cells form intc node because it is already setup
in parent node.
Add missing address-cells and size-cells to eth node to be shared for
every platform DTSes.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Use the new zynq binding for macb ethernet, since it will disable half
duplex gigabit like the Zynq TRM says to do. Also allow the compatible
cadence gem binding that won't disable half duplex but works otherwise.
Signed-off-by: Nathan Sullivan <nathan.sullivan@ni.com>
Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Zynq is using Cadence IP where binding is documented in the Linux kernel
and there is no reason to use different binding.
Synchronize it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Due to dependencies between timer and CPU frequency, only changes by
powers of two are allowed. The clocksource driver prevents other
changes, but with cpufreq and its governors it can result in being
spammed with error messages constantly. Hence, remove the 222 MHz OPP.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
To silence the warning
cpufreq_cpu0: failed to get cpu0 regulator: -19
from the cpufreq driver regarding a missing regulator,
add a fixed regulator to the DT.
Zynq does not support voltage scaling and the CPU rail should always be
supplied with 1 V, hence it is added in the SOC-level dtsi.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Pass directly boot_addr which is LOVEC (0) or HIVEC (0xffff0000).
No reason to use magic values 0 and 1.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Provide option to enable uart dcc support for zynqmp
This config can be enabled as per board config file.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Move CONFIG_SYS_TEXT_BASE of ZynqMP_ep to its
respective defconfig
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Define a new config "zynqmp_ep" for ZynqMP instead
of xilinx_zynqmp. This defconfig supports all emulation
platforms of ZynqMP. Also renamed TARGET_XILINX_ZYNQMP
to ARCH_ZYNQMP.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Move the zynqmp Kconfig from board to arch
as there may be different boards under same
architecture.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Increase the Rx Buffer descriptors to 32. This will avoid
Rx buffer descriptors overflow if more packets were received
at one shot before we process the received ones.
This fixes the issue of intermittent timeouts during tftp
on a 1Gb connection with tftp server running on windows.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Flush and invalidate the rx buffers while sending the
tx packet it self as armv8 does flush also while doing
invalidation.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The encoding of the sub instruction used to handle CONFIG_SYS_MALLOC_F_LEN
can only accept certain values, and the set of acceptable values differs
between the AArch32 and AArch64 instructions sets. The default value of
CONFIG_SYS_MALLOC_F_LEN works with either ISA. Tegra uses a non-default
value that can only be encoded in the AArch32 ISA. Fix the AArch64 crt0
assembly so it can handle completely arbitrary values.
Signed-off-by: Thierry Reding <treding@nvidia.com>
[twarren: trimmed Thierry's patch to remove changes already present]
Signed-off-by: Tom Warren <twarren@nvidia.com>
[swarren, cleaned up patch, wrote description, re-wrote subject]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Use %p to print pointers.
The max value of (i_buf - i_buf_start) should be dfu_buf_size, which is
an unsigned long, so cast the pointer difference to that type to print.
Change-Id: Iee242df9f8eb091aecfe0cea4c282b28b547acfe
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The sysboot and pxe commands currently support either U-Boot formats or
raw zImages. Add support for the AArch64 Linux port's native image format
too.
As with zImage support, there is no auto-detection of the native image
format. Rather, if the image is auto-detected as a U-Boot format, U-Boot
will try to interpret it as such. Otherwise, U-Boot will fall back to a
raw/native image format, if one is enabled.
My belief is that CONFIG_CMD_BOOTZ won't ever be enabled for any AArch64
port, hence there's never a need to differentiate between CONFIG_CMD_
_BOOTI and _BOOTZ at run-time; compile-time will do. Even if this isn't
true, we want to prefer _BOOTI over _BOOTZ when defined, since _BOOTI is
definitely the native format for AArch64.
Change-Id: I83c5cc7566032afd72516de46f4e5eb7a780284a
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
We are getting very close to running out of space in SPL, and with the
currently Chrome OS gcc 4.9 we exceed the limit. Add a litle more space.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Enable the I2C3 pins so that the TPM can be used.
Note: There is an DP change also, caused by running board-to-uboot.py
script in the latest tegra-pinmux-script tree.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
In order to achieve reproducible builds in U-Boot, timestamps that are defined
at build-time have to be somewhat eliminated. The SOURCE_DATE_EPOCH environment
variable allows setting a fixed value for those timestamps.
Simply by setting SOURCE_DATE_EPOCH to a fixed value, a number of targets can be
built reproducibly. This is the case for e.g. sunxi devices.
However, some other devices might need some more tweaks, especially regarding
the image generation tools.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
This is commented out in the Makefile for more than 10 years.
I assume it is proof that this tool is unused.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Pantelis Antoniou <panto@intracom.gr>
Switch to using zImage instead of uImage. and while at it, start using
bootz as default. While at it, get rid of BOOTIMAGE define and start
using Linux upstream dtb file names.
Reviewed-by: Murali Karicheri <m-karicheri2@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Use the defaults defined in DEFAULT_LINUX_BOOT_ENV
Reviewed-by: Murali Karicheri <m-karicheri2@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Try to maintain as much commonality by conditionally including stuff
in armv7_common as necessary and removing the common defines from
keystone2 header.
Note: as part of this change, all keystone2 platforms will now start
using the generic u-boot prompt instead of the custom prompt.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
rename the keystone2 common header into an keystone2 architecture
specific header which can then reuse the common ti_armv7 config headers.
Acked-by: Vitaly Andrianov <vitalya@ti.com>
Acked-By: Murali Karicheri <m-karicheri2@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
CONFIG_LINUX_BOOT_PARAM_ADDR is not a valid configuration option. Do
just like what the rest of the world does.
Acked-by: Vitaly Andrianov <vitalya@ti.com>
Acked-By: Murali Karicheri <m-karicheri2@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Commit bd2c4522c2 ("ti: armv7: enable EXT support in SPL (using
ti_armv7_common.h)") enabled thumb mode only for SPL builds, however,
All TI armv7 platforms do support thumb, and there is no reason why the
space savings cannot be exploited for u-boot as well.
Reported-by: Murali Karicheri <m-karicheri2@ti.com>
Suggested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
TI armv7 based SoCs are based on two architectures - one based on OMAP
generation architecture and others based on Keystone architecture.
Many of the options are architecture specific, however a lot are common
with v7 architecture. So, step 1 will be to move out OMAP specific stuff
from ti_armv7_common into a ti_armv7_omap.h header which is then used
by all the relevant architecture headers.
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Read device unique ID and set environment variable "serial#".
Value would then be passed to kernel through DTB.
To read ID from DTB, kernel is required to have commit:
3f599875e5202986b350618a617527ab441bf206 (ARM: 8355/1: arch: Show
the serial number from devicetree in cpuinfo)
This commit is already mainline since v4.1-rc1.
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
To: Albert Aribaud <albert.u.boot@aribaud.net>
To: Tom Rini <trini@konsulko.com>
To: Kamil Lulko <rev13@wp.pl>
Cc: u-boot@lists.denx.de
Because the top-level Makefile forces all the source files
to include include/linux/kconfig.h (see the UBOOTINCLUDE define),
these includes are redundant.
By the way, there are exceptions for the statement above; host
programs. In fact, host tools in U-Boot depend on a particular
board configuration, although I think they should not. So, some
files still include <linux/config.h> to work around build errors
on host tools.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Simon Glass <sjg@chromium.org>
All am33xx device tree are using device-tree, so get_board_rev is never actually
called. Thus, we can get rid of it to make the code easier to maintain.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
Despite being defined with __weak, this declaration of get_board_rev will
conflict with the fallback one when ONFIG_REVISION_TAG is not defined.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
This introduces code to read the value of the SYS_BOOT pins on the OMAP5, as
well as the memory-preferred scheme for the interpretation of each value.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
This introduces code to read the value of the SYS_BOOT pins on the OMAP4, as
well as the memory-preferred scheme for the interpretation of each value.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
This introduces code to read the value of the SYS_BOOT pins on the OMAP3, as
well as the memory-preferred scheme for the interpretation of each value.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
OMAP devices might boot from peripheral devices, such as UART or USB.
When that happens, the U-Boot SPL tries to boot the next stage (complete U-Boot)
from that peripheral device, but in most cases, this is not a valid boot device.
This introduces a fallback option that reads the SYS_BOOT pins, that are used by
the bootrom to determine which device to boot from. It is intended for the
SYS_BOOT value to be interpreted in the memory-preferred scheme, so that the
U-Boot SPL can load the next stage from a valid location.
Practically, this options allows loading the U-Boot SPL through USB and have it
load the next stage according to the memory device selected by SYS_BOOT instead
of stalling.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
The config file for the siemens-am33x-common was using OMAP_I2C_STANDARD, which
is defined in a header that is not included in the config header. In most cases,
it was being included by the code using CONFIG_SYS_OMAP24_I2C_SPEED, but it
might not always be the case.
In particular, when introducing I2C SPL support in omap-common's boot-common.c,
the header is missing and including it breaks other devices.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Now that SPL boot devices are clearly defined, we can use BOOT_DEVICE_QSPI_4
instead of a hardcoded value.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
This cleans up the SPL boot devices for omap platforms and introduces support
for missing boot devices.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
This introduces OMAP3 support for the common omap boot code, as well as a
major cleanup of the common omap boot code.
First, the omap_boot_parameters structure becomes platform-specific, since its
definition differs a bit across omap platforms. The offsets are removed as well
since it is U-Boot's coding style to use structures for mapping such kind of
data (in the sense that it is similar to registers). It is correct to assume
that romcode structure encoding is the same as U-Boot, given the description
of these structures in the TRMs.
The original address provided by the bootrom is passed to the U-Boot binary
instead of a duplicate of the structure stored in global data. This allows to
have only the relevant (boot device and mode) information stored in global data.
It is also expected that the address where the bootrom stores that information
is not overridden by the U-Boot SPL or U-Boot.
The save_omap_boot_params is expected to handle all special cases where the data
provided by the bootrom cannot be used as-is, so that spl_boot_device and
spl_boot_mode only return the data from global data.
All of this is only relevant when the U-Boot SPL is used. In cases it is not,
save_boot_params should fallback to its weak (or board-specific) definition.
save_omap_boot_params should not be called in that context either.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
The symbolic link to SoC/CPU specific header directory is created
during the build, while it is only necessary for ARM, AVR32, SPARC,
x86, and some CPUs of PowerPC. For the other architectures, it just
results in a broken symbolic link.
Introduce CONFIG_CREATE_ARCH_SYMLINK to not create unneeded symbolic
links.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
There are only two SoC-specific headers for this architecture:
- arch/nds32/include/asm/arch-ag101/ag101.h
- arch/nds32/include/asm/arch-ag102/ag102.h
Those two have different file names, so there is no advantage to
include them via symbolic linked directory.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
In case of enable CONFIG_OF_CONTROL and has a "model" property in the root node,
the board special "checkboard" will not be called.
Usually we show some useful version information in the function.
This patch enable call "checkboard" in any case.
It is not conflicting with showing "model" at the same time.
For example on LS2085AQDS:
Showing "model" only:
Model: Freescale Layerscape 2085a QDS Board
Showing "checkboard" only:
Board: LS2085E-QDS, Board Arch: V1, Board version: B, boot from vBank: 4
Showing both:
Model: Freescale Layerscape 2085a QDS Board
Board: LS2085E-QDS, Board Arch: V1, Board version: B, boot from vBank: 4
Signed-off-by: Haikun Wang <haikun.wang@freescale.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The MCAST_TFTP support requires that network drivers has mcast functon
implemented. This commit adds dummy keystone2_eth_bcast_addr() to meet
the requirement. As far as the driver doesn't use ALE and doesn't filter
any incoming packets, the function is empty.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
When core A turning of core B, via tetris DPSC it places the core
B DPSC into transitional state. The core B has to execute wfi instruction
to move its DPSC to the OFF state. This patch add such instruction.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Only 2 frequencies are supported. The current driver implementation does
not always use the 2 last configured blink frequencies. This patch
fixes this problem. So that the last two entered frequencies are
active.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Tom Rini <trini@konsulko.com>
Prior to this commit, it was impossible to use relative path to
include Makefiles from the top level Makefile because the option
"--include-dir=$(srctree)" becomes effective when Make enters into
sub Makefiles.
To use relative path in any places, this commit moves the option
above the "sub-make" target.
This was imported from Linux (commit a436bb7b8063) and adjusted for
U-Boot.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Michal Marek <mmarek@suse.cz>
$(always) is added to targets by scripts/Makefile.build.
Moreover, filechk does not need .*.cmd files.
Adding these two files to targets is redundant.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Update some build scripts to match Linux 4.1. Commit-based syncing
was done so as not to break U-Boot specific changes.
The previous big sync was from Linux 3.18-rc1 by commit 176d098277
(kbuild: sync misc scripts with Linux 3.18-rc1).
The commits imported from Linux (some with adjustments) are:
[1] commit 9fb5e5372208973984a23ee6f5f025c05d364633
Author: Robert Richter <rrichter@cavium.com>
dts, kbuild: Factor out dtbs install rules to Makefile.dtbinst
[2] commit 371fdc77af44f4cb32475fd499e1d912ccc30890
Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
kbuild: collect shorthands into scripts/Kbuild.include
[3] commit a29b82326ed4eb5567b03c85b52c6891578d5a03
Author: Michal Marek <mmarek@suse.cz>
kbuild: Remove duplicate $(cmd) definition in Makefile.clean
[4] commit 1846dfbde3e8a53f3673dcb1c1b79fd9b3f8d40d
Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
kbuild: remove redundant -rR flag of hdr-inst
[5] commit 34948e0bbf98640fc1821751b01d2f0cd17d84d5
Author: Michal Marek <mmarek@suse.cz>
kbuild: Drop support for clean-rule
[6] commit a16c5f99a28c9945165c46da27fff8e6f26f8736
Author: Michal Marek <mmarek@suse.cz>
kbuild: Fix removal of the debian/ directory
[7] commit d0d38cd9e853db11e0242b3df4c9c3c4a663fbb4
Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
kbuild: use mixed-targets when two or more config targets are given
[8] commit dd33c03b18b3f2db791eb6a17c37d2de66e4de18
Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
kbuild: fix cc-ifversion macro
[9] commit 665d92e38f65d70796aad2b8e49e42e80815d4a4
Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
kbuild: do not add $(call ...) to invoke cc-version or cc-fullversion
[10] commit 6dcb4e5edf39e3b65a75ca76f087b2fdbee8a808
Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
kbuild: allow cc-ifversion to have the argument for false condition
[11] commit c0a80c0c27e5e65b180a25e6c4c2f7ef9e386cd3
Author: Heiko Carstens <heiko.carstens@de.ibm.com>
ftrace: allow architectures to specify ftrace compile options
[12] commit 0b24becc810dc3be6e3f94103a866f214c282394
Author: Andrey Ryabinin <a.ryabinin@samsung.com>
kasan: add kernel address sanitizer infrastructure
[13] commit 4218affdf57f938c04e3a916a9685ee27079f377
Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
kbuild: remove warning about "make depend"
[14] commit 77479b38e2f58890eb221a0418357502a5b41cd6
Author: Nathan Rossi <nathan.rossi@xilinx.com>
kbuild: Create directory for target DTB
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Robert Richter <rrichter@cavium.com>
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Signed-off-by: Andrey Ryabinin <a.ryabinin@samsung.com>
Signed-off-by: Nathan Rossi <nathan.rossi@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Michal Marek <mmarek@suse.cz>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Update the files under scripts/kconfig/ to match Linux 4.1.
Some Kconfig sources have diverged from those in the kernel,
so commit-base syncing was done not to lose U-Boot specific updates.
The commits cherry-picked from Linux are:
[1] commit be8af2d54a66911693eddc556e4f7a866670082b
Author: Bjørn Forsman <bjorn.forsman@gmail.com>
kconfig/lxdialog: get ncurses CFLAGS with pkg-config
[2] commit 3943f42c11896ce82ad3da132c8a5630313bdd0e
Author: Andrey Utkin <andrey.krieger.utkin@gmail.com>
Replace mentions of "list_struct" to "list_head"
[3] commit e4e458b45c5861808674eebfea94cee2258bb2ea
Author: Arjun Sreedharan <arjun024@gmail.com>
calloc/xcalloc: Fix argument order
[4] commit 09950bc256e3628d275f90e016e6f5a039fbdcab
Author: Olof Johansson <olof@lixom.net>
merge_config.sh: Display usage if given too few arguments
[5] commit b6a2ab2cd4739a9573ed41677e53171987b8da34
Author: Colin Ian King <colin.king@canonical.com>
kconfig: use va_end to match corresponding va_start
[6] commit 70529b1a1784503169416df19ce3d68746401340
Author: Michal Marek <mmarek@suse.cz>
kconfig: Get rid of the P() macro in headers
[7] commit 463157444e377bf9b279101b1f16a94c4648c03a
Author: Michal Marek <mmarek@suse.cz>
kconfig: Remove dead code
[8] commit ad8d40cda3ad22ad9e8863d55a5c88f85c0173f0
Author: Michal Marek <mmarek@suse.cz>
kconfig: Remove unnecessary prototypes from headers
[9] commit de4619937229378e81f95e99c9866acc8e207d34
Author: Masahiro Yamada <yamada.masahiro@socionext.com>
kbuild: mergeconfig: fix "jobserver unavailable" warning
[10] commit b9fe99c5b994c6ddc57780993966b18899526c0b
Author: Masahiro Yamada <yamada.masahiro@socionext.com>
kbuild: mergeconfig: move an error check to merge_config.sh
[11] commit 371cfd4ff0611d8bc5d18bbb9cc6a2bc3d56cd3d
Author: Masahiro Yamada <yamada.masahiro@socionext.com>
kbuild: mergeconfig: remove redundant $(objtree)
[12] commit 3a975b8cfcbe026b535f83bde9a3c009bae214f9
Author: Masahiro Yamada <yamada.masahiro@socionext.com>
merge_config.sh: improve indentation
[13] commit bc8f8f5fc47cd02c2c5f3580dac2fe6695af1edd
Author: Masahiro Yamada <yamada.masahiro@socionext.com>
merge_config.sh: rename MAKE to RUNMAKE
[14] commit 63a91033d52e64a22e571fe84924c0b7f21c280d
Author: Masahiro Yamada <yamada.masahiro@socionext.com>
kbuild: add generic mergeconfig target, %.config
[15] commit 1cba0c305758c3c1786ecaceb03e142c95a4edc9
Author: Michal Marek <mmarek@suse.cz>
kconfig: Simplify Makefile
[16] commit 0a1f00a1c86421cc07cec87011c7cf4df68ee54b
Author: Michal Marek <mmarek@suse.cz>
kconfig: Do not print status messages in make -s mode
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Bjørn Forsman <bjorn.forsman@gmail.com>
Signed-off-by: Andrey Utkin <andrey.krieger.utkin@gmail.com>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
Signed-off-by: Arjun Sreedharan <arjun024@gmail.com>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Michal Marek <mmarek@suse.cz>
Palmas power support is required for OMAP5 devices such as the OMAP5 uEVM, that
need to e.g. enable MMC power at SPL stage.
This is especially important when booting from a peripheral (such as USB, UART),
where the bootrom will not enable power for the MMC device that will hold the
main U-Boot.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
Add thermal support so that we can see the following message on boot:
CPU: Industrial temperature grade (-40C to 105C) at 33C
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Perfoming an OR operation on the error is not a good approach.
Return the error immediately for each ESDHC instance instead.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Entering the maximum number of characters defined by CONFIG_SYS_CBSIZE into
the console and hitting enter afterwards, causes a hang in the system because
CONFIG_SYS_PBSIZE is not capable of storing the extra characters of the error
message:
"Unknown command '' - try 'help'".
Use the default CONFIG_SYS_PBSIZE definition from config_fallbacks.h to solve
this problem.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
DCIMVAC is upgraded to DCCIMVAC for the individual processor
(Cortex-A7) that the DCIMVAC is executed on.
We should follow the linux dma follow. Before DMA read, first
invalidate dcache then after DMA read, invalidate dcache again.
With the DMA direction DMA_FROM_DEVICE, the dcache need be
invalidated again after the DMA completion. The reason is
that we need explicity make sure the dcache been invalidated
thus to get the DMA'ed memory correctly from the physical memory.
Any cache-line fill during the DMA operations such as the
pre-fetching can cause the DMA coherency issue, thus CPU get the stale data.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
Signed-off-by: Jason Liu <r64343@freescale.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
The variable 'ret' is used to store the value returned by pfuze_mode_init(),
so it should be of type 'int' instead of 'unsigned int' in order to
correctly handle negative numbers.
Fix the variable type.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
The variable 'ret' is used to store the value returned by pfuze_mode_init(),
so it should of type 'int' instead of 'unsigned int' in order to correctly
handle negative numbers.
Fix the variable type.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
This patch adds support for the "OHB System AG" baseboard
with is equipped with the TQMa6S SoM.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Markus Niebel <Markus.Niebel@tq-group.com>
Cc: Stefano Babic <sbabic@denx.de>
Now that the device-model port of the musb mode makes it possible, enable
both the ehci and otg in host mode on boards where the musb is wired up in
host only mode, either via an usb-a receptacle or via an usb <-> sata
converter.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
This allows using devices plugged into both ports of the tablet.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
On some boards the otg is wired up in host-only mode in this case we
have no vbus-det gpio.
Stop logging an error from sunxi_usb_phy_vbus_detect() in this case, and
stop treating sunxi_usb_phy_vbus_detect() returning a negative errno, as
if a charger is plugged into the otg port.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
When we return an error the usb core will print an error-message, so in this
case do not print anything.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Acked-by: Ian Campbell <ian.campbell@citrix.com>
Modify the sunxi musb glue to use the device-model for musb host mode.
This allows using musb in host mode together with other host drivers
such as ehci / ohci, which is esp. useful on boards which use the
musb controller in host-only mode, these boards have e.g. an usb-a
receptacle or an usb to sata converter attached to the musb controller.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Move the musb config and platdata to the sunxi-musb glue, which is where
it really belongs. This is preparation patch for adding device-model
support for the sunxi-musb-host code.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
When in host mode check if there is a host cable inserted into the otg
port by checking the id pin. If there is no host cable return an error to
make usb_lowlevel_init() exit early, rather then waiting for 1 second
for a device which will never show up.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Add support for reading the id pin value of the otg connector to the usb
phy code.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Start using the new Kconfig options which are available for these now,
and simply always enable them by selecting them as sunxi builds always
include USB support.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Reviewed-by: Simon Glass <sjg@chromium.org>
With certain features being convert to DM now we want sunxi to default
to having DM enabled for ETH/SERIAL and USB in some cases.
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Tom Rini <trini@konsulko.com>
[hdegoede@redhat.com: Also select CONFIG_USB for all sunxi builds]
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Reviewed-by: Simon Glass <sjg@chromium.org>
At one point in time the utoo-p66 dts file in the kernel had a bogus
uart entry, and it seems like we synced with the kernel at just the wrong
moment.
This commit removes the bogus uart entry, which breaks booting the utoo-p66
when DM_SERIAL=y.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The ci_udc driver request allocation assumes that the endpoint descriptor
pointer is set to retrieve the endpoint number, but that is only true
when the endpoint is enabled. This results in a NULL ptr dereference
which for me happens to return 0 value. This causes the EP0 request
struct to be returned for other endpoints. Some gadget drivers like
fastboot and USB MS work fine, but ethernet does not.
Really, the ci_udc driver is the oddball here doing this EP0 special
case handling Stephen added. All the other drivers alloc/free functions
are pretty much the same with the only variation being the size of the
private struct. This could all be consolidated to a common function.
Signed-off-by: Rob Herring <robh@kernel.org>
Cc: Marek Vasut <marex@denx.de>
Acked-by: Stephen Warren <swarren@nvidia.com>
Remove the boot signature check from board_mmc_init() in spl mode, as it
is already done in spl_boot_device() in this case, and update the comments
to reflect this.
Signed-off-by: Daniel Kochmański <dkochmanski@turtle-solutions.eu>
CC: Roy Spliet <r.spliet@ultimaker.com>
Cc: Ian Campbell <ijc@hellion.org.uk>
[hdegoede@redhat.com: Disable the check only for SPL instead of always]
Acked-by: Hans De Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Make possible using a single `u-boot-sunxi-with-spl.bin` binary for both NAND
memory and SD card. Detection where SPL was read from is implemented in
`spl_boot_device`.
Signed-off-by: Daniel Kochmański <dkochmanski@turtle-solutions.eu>
CC: Roy Spliet <r.spliet@ultimaker.com>
Cc: Ian Campbell <ijc@hellion.org.uk>
[hdegoede@redhat.com: Some small coding style fixes]
Acked-by: Hans De Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
This patch extracts checking for valid SD card "eGON.BT0" signature from
`board_mmc_init` into function `sunxi_mmc_has_egon_boot_signature`.
Buffer for mmc sector is allocated and freed at runtime. `panic` is
triggered on malloc failure.
Signed-off-by: Daniel Kochmański <dkochmanski@turtle-solutions.eu>
CC: Roy Spliet <r.spliet@ultimaker.com>
Cc: Ian Campbell <ijc@hellion.org.uk>
[hdegoede@redhat.com: Small bugfix to make it work for devs other then mmc0]
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
This patch adds the configuration options to boot via SDIO/MMC on the
Marvell DB-88F6820-GP Armada A38x board. The default boot device
is still SPI NOR flash.
To enable MMC booting on this board 2 things need to be changes:
a) Change kwbimage.cfg
BOOT_FROM sdio
b) In the config header select
#define CONFIG_SPL_BOOT_DEVICE SPL_BOOT_SDIO_MMC_CARD
The generated image needs to be copied to the first bootable MMC
partition:
dd if=u-boot-spl.kwb of=/dev/sdX1
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Dirk Eibach <eibach@gdsys.de>
This patch introduces the option to boot from a MMC card parition with
an offset. This can be done by using both defines together:
define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1
define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR ((160 << 10) / 512)
The example above loads the main U-Boot at offset 160KiB from the MMC
partition 1.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Dirk Eibach <eibach@gdsys.de>
Cc: Tom Rini <trini@konsulko.com>
To use this offset for other boot device (like SDIO/MMC), lets rename
it to a more generic name. This will be used be the SDIO/MMC SPL boot
support for the A38x.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Dirk Eibach <eibach@gdsys.de>
This patch adds support to select the "sdio" as boot device in the
kwbimage.cfg file. This line selects this SDIO device:
BOOT_FROM sdio
Tested on Marvell DB-88F6820-GP board.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Dirk Eibach <eibach@gdsys.de>
This patch adds basic SDIO/MMC booting support to MVEBU SoC's. Since
I don't know of a way to test the boot-device upon runtime, this patch
hardcodes the spl_boot_device instead.
Tested on Marvell DB-88F6820-GP board.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Dirk Eibach <eibach@gdsys.de>
The init code for UMC (Unified Memory Controller) and PLL has not
been mainlined yet, but U-boot proper should work.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
To use FIT boot, we have to describe Image Tree Source in addition.
So, it is not intended for beginners. Disable it by default.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The command "run tftpboot" downloads some files onto the RAM
via TFTP and boots the kernel.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Currently, the environment variables "norboot" and "nandboot" only
work with CONFIG_FIT, but we do not want to depend on CONFIG_FIT to
boot the kernel.
This commit adds environments useful for booting Linux with separate
uImage + ramdisk + DTB.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
For the record, describe exactly which device of which vendor
is used on this board.
I2C EEPROM is bound by the generic compatible string, "i2c-eeprom",
so this commit has no impact on the functionality.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This patch adds SPL support for the Marvell DB-88F6820-GP board.
With this change, the bin_hdr from the original Marvell U-boot
is not needed any more on this board. The sources from bin_hdr
(SERDES/PHY and DDR setup) are now integrated in mainline
U-Boot. And this patch enables them for this board.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch adds the DDR3 setup and training code taken from the Marvell
U-Boot repository. This code used to be included as a binary (bin_hdr)
into the Armada A38x boot image. Not linked with the main U-Boot. With this
code addition and the serdes/PHY setup code, the Armada A38x support
in mainline U-Boot is finally self-contained. So the complete image
for booting can be built from mainline U-Boot. Without any additional
external inclusion.
Note:
This code has undergone many hours (days!) of coding-style cleanup and
refactoring. It still is not checkpatch clean though, I'm afraid. As the
factoring of the code has so many levels of indentation that many lines
are longer than 80 chars.
Signed-off-by: Stefan Roese <sr@denx.de>
With the upcoming addition of the Armada 38x DDR support, which is not
compatible to the Armada XP DDR init code, we need to introduce a new
directory infrastructure. To support multiple Marvell DDR controller.
This will be the new structure:
drivers/ddr/marvell/axp
Supporting Armada XP (AXP) devices (and perhaps Armada 370)
drivers/ddr/marvell/a38x
Supporting Armada 38x devices (and perhaps Armada 39x)
Signed-off-by: Stefan Roese <sr@denx.de>
This code is ported from the Marvell bin_hdr code into mainline
SPL U-Boot. It needs to be executed very early so that the devices
connected to the serdes PHY are configured correctly.
Signed-off-by: Stefan Roese <sr@denx.de>
With the upcoming addition of the Armada 38x SPL support, which is not
compatible to the Armada XP SERDES init code, we need to introduce a new
directory infrastructure. So lets move the AXP serdes init code into
a new directory. This way the A38x code can be added in a clean way.
Signed-off-by: Stefan Roese <sr@denx.de>
Only with disabled MMU its possible to switch the base register address on
Armada 38x. Without this the SDRAM located at >= 0x4000.0000 is also not
accessible, as its still locked to cache.
Signed-off-by: Stefan Roese <sr@denx.de>
Pin muxing needs to be done before UART output, since on A38x the UART
pins need some re-muxing for output to work.
Signed-off-by: Stefan Roese <sr@denx.de>
On A38x switching the regs base address without running from
SDRAM doesn't seem to work. So let the SPL still use the
default base address and switch to the new address in the
mail u-boot later.
Signed-off-by: Stefan Roese <sr@denx.de>
Without calling timer_init(), the xdelay() functions return immediately.
We need to call timer_init() early, so that these functions work and
the PHY and DDR init code works correctly.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Anton Schubert <anton.schubert@gmx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
This patch initializes the SATA address windows on Armada XP and
allows it to work with the existing mvsata_ide driver.
It also adds the necessary configuration for the db-mv784mp-gp board.
Signed-off-by: Anton Schubert <anton.schubert@gmx.de>
Tested-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Currently, kzalloc() returns zero-filled memory, while kmalloc()
simply ignores the second argument and never fills the memory
area with zeros.
I want kmalloc(size, __GFP_ZERO) to behave as kzalloc() does,
which will make it easier to add more memory allocator variants.
With the introduction of __GFP_ZERO flag, going forward, kzmalloc()
variants can fall back to kmalloc() enabling the __GFP_ZERO flag.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Acked-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
The vzalloc(size) is equivalent to kzalloc(size, 0). Move it to
include/linux/compat.h as an inline function in order to avoid the
function call overhead.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Acked-by: Simon Glass <sjg@chromium.org>
The macro cpu_relax() is defined by several headers in different
ways.
arch/{arm,avr32,mips}/include/asm/processor.h defines it as follows:
#define cpu_relax() barrier()
On the other hand, include/linux/compat.h defines it as follows:
#define cpu_relax() do {} while (0)
If both headers are included from the same source file, the warning
warning: "cpu_relax" redefined [enabled by default]
is displayed.
It effectively makes it impossible to include <linux/compat.h>
from some sources. Drop the latter.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Acked-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
These two declarations in arch/x86/include/asm/interrupt.h conflict
with ones in include/linux/compat.h, so x86 boards cannot include
<linux/compat.h>.
The comment /* arch/x86/lib/interrupts.c */ is bogus now, and we do
not see any definitions of disable_irq() and enable_irq() in there.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
This patch removes the wrl accessor function from the Marvell EHCI
driver by replacing it with the writel function.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>
FASTBOOT is defined both by CONFIG_USB_FUNCTION_FASTBOOT AND CONFIG_CMD_FASTBOOT, so it doesn't
make much sense to have a CONFIG_USB_FASTBOOT prefix for fastboot-specific options, especially
given that other config options for fastboot use the CONFIG_FASTBOOT prefix.
This replaces the CONFIG_USB_FASTBOOT prefix with CONFIG_FASTBOOT, for consistency.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Add the required files for the Broadcom UDC OTG interface.
Signed-off-by: Jiandong Zheng <jdzheng@broadcom.com>
Signed-off-by: Steve Rae <srae@broadcom.com>
Recent versions of the fastboot tool will query the partition type before doing
an operation on a partition (such as erase, flash, etc). It will then submit
the operation as soon as the response for the partition type is received.
Usually, the MUSB controller will see that the partition type request return
status was read by the host at the very same time as the actual operation
request is submitted by the host. However, the operation will be read first
(int_rx is handled first in musb_interrupt) and after it is completed, the
fastboot USB gadget driver will send another return status. Hence, this happens
before the musb gadget framework has had a chance to handle the previous
acknowledgement that the host read the return status and dequeue the request.
The host will then usually empty the FIFO by the time musb_interrupt gets around
handling the return status acknowledgement (for the previous request, this is
still on the same musb_interrupt call), so no other interrupt is generated and
the most recent return status acknowledgement remains unaccounted for.
It will then be used as a response for the next command, and the proper response
for it will be delayed to the next command, and so on.
Dequeuing the previous IN request in the fastboot code ensures that no previous
return status remains. It is acceptable to do it since there is no callback to
it anyways.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
This avoids handling requests that have an error status or no data.
In particular, this avoids showing unnecessary error messages when the USB
gadget gets disconnected (e.g. with fastboot continue) and the fastboot USB
gadget driver sends an error back to the host (that has disconnected already).
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Since we're now using a dynamic controller index for fastboot too,
usb_gadget_handle_interrupts should be using it instead of 0 (despite the fact
that it's currently not being used at all in the musb-new implementation).
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Weak versions of board_usb_init and board_usb_cleanup are defined in common USB
host code, but it is also used for USB device gadgets, so we also need a weak
definition of it when there is no USB host enabled.
Both weak definitions do not conflict.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
Test HW: Odroid_XU3 (Exynos5422), trats (Exynos4210)
Each USB download function command calls board_usb_init before registering the
USB gadget and board_usb_cleanup after de-registering it. On devices currently
using fasboot, musb-new is usually initialized earlier, but some other boards
might need the board_usb_init call to properly initialize musb-new.
This requires adding an argument (the USB controller index) to the fastboot
command, as it is currently done with other USB download gadget functions.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
Test HW: Odroid_XU3 (Exynos5422), trats (Exynos4210)
USB download gadget functions such as thor and dfu have a separate config option
for the USB gadget part of the code, independent from the command part.
This switches the fastboot USB gadget to the same scheme, for better
consistency.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
Test HW: Odroid_XU3 (Exynos5422), trats (Exynos4210)
This introduces a coherent scheme for naming USB download gadget and functions
config options. The download USB gadget config option is moved to
CONFIG_USB_GADGET_DOWNLOAD for better consistency with other gadgets and each
function's config option is moved to a CONFIG_USB_FUNCTION_ prefix.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
Test HW: Odroid_XU3 (Exynos5422), trats (Exynos4210)
Remove LS102XA immap header inclusion from xhci fsl driver.
It removes redefinition warnings when built for platforms
other than LS102XA
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Move USB controller Base address mapping from ls102xa immap
to fsl xhci header. This is required to remove any warnings when
controller base addresses are mapped for multiple platforms
in their respective files.
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
This adjusts (micro)frame length to appropriate value thus
avoiding USB devices to time out over a longer run
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Some drivers may want to implement this method for some of their devices but
not for others. So it is not possible to just leave the operation out of
the table. Drivers could get around this by masquerading as two separate
drivers but that seems unpleasant.
Allow the driver to return an error when it does not want to process the
write_hwaddr() method.
Signed-off-by: Simon Glass <sjg@chromium.org>
This USB Ethernet driver is quite widely use. Allow it to work with
CONFIG_DM_ETH enabled. Most of the code remains common but there is a new
packet receive flow which is handled specially.
Signed-off-by: Simon Glass <sjg@chromium.org>
Support driver model in this driver. This uses the normal USB driver search
mechanism. Any EHCI controllers will be set up as they are found during
usb_init().
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
Now that the RTL8169 driver warning is fixed we can drop this. The incorrect
value is causing problems with USB EHCI.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
In Linux USB_DEVICE() is used to declare a USB device by vendor/device ID.
We should follow the same convention in U-Boot. Rename the existing
USB_DEVICE() macro to U_BOOT_USB_DEVICE() and bring in the USB_DEVICE()
macro from Linux for use in U-Boot.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present USB Ethernet does not work with CONFIG_DM_ETH. Add driver model
support to this feature, so that it can work alongside other Ethernet
devices with driver model.
It was found that quite a bit of code is common in most of the USB Ethernet
drivers. Add this code to the common layer to reduce the amount of duplicate
code needed in USB Ethernet drivers when CONFIG_DM_ETH is used.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
Some devices can take a long time to work out whether they have a new packet
or now. For example the ASIX USB Ethernet dongle can take 5 seconds to do
this, since it waits until it gets a new packet on the wire before allowing
the USB bulk read packet to be submitted.
At present with driver mode the Ethernet receive code reads 32 packets. This
can take a very long time if we must wait for all 32 packets. The old code
(before driver model) worked by reading a single set of packets from the USB
device, then processing all the packets with in. It would be nice to use
the same behaviour with driver model.
Add a flag to the receive method which indicates that the driver should try
to find a packet if available, by consulting the hardware. When the flag is
not set, it should just return any packet data it has already received. If
there is none, it should return -EAGAIN so that the loop will terminate.
Signed-off-by: Simon Glass <sjg@chromium.org>
If driver model is used for Ethernet then USB Ethernet does not build. This
can be made to work with driver model is used for USB also. Add #ifdef logic
to make this clear when building.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
It is useful to be able to find the full PCI address (bus, device and
function) for a PCI device. Add a function to provide this.
Adjust the existing code to use this.
Signed-off-by: Simon Glass <sjg@chromium.org>
This driver is used by the Intel Minnowmax board. Convert it to driver model
so it can use the new Ethernet implementation.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present all PCI devices must be present in the device tree in order to
be used. Many or most PCI devices don't require any configuration other than
that which is done automatically by U-Boot. It is inefficent to add a node
with nothing but a compatible string in order to get a device working.
Add a mechanism whereby PCI drivers can be declared along with the device
parameters they support (vendor/device/class). When no suitable driver is
found in the device tree the list of such devices is consulted to determine
the correct driver. If this also fails, then a generic driver is used as
before.
The mechanism used is very similar to that provided by Linux and the header
file defintions are copied from Linux 4.1.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Add device-model support to the musb-host u-boot glue, note this only
adds device-model support to the musb-core glue code, it does not add
support for device-model to any of the SoC specific musb glue code.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Simon Glass <sjg@chromium.org>
Add a musb_host_data struct to hold all the global data host related musb
data. This is a preparation patch for adding device-model support.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Simon Glass <sjg@chromium.org>
Rename and wrap the usb host API public functions, this is a preparation
patch for adding device-model support.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Simon Glass <sjg@chromium.org>
When building with CONFIG_DM_USB=y struct usb_device does not have a parent
pointer. This commit adds support to the musb code to deal with this.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Simon Glass <sjg@chromium.org>
Allow musb_platform_enable to return an error code and propagate it up to
usb_lowlevel_init().
This allows moving the checks for an external vbus being present to be
moved from platform_init to platform_enable, so that the user can unplug a
charger, plug in a host adapter with a usb-device, do a "usb reset" and
have things working.
This also allows adding a check for the id-pin to platform_enable, so that
it can short circuit the 1s delay in usb_lowlevel_init() when no host cable
is plugged in and thus waiting for a device to show up is useless.
Note that all the changes to code shared with the kernel are wrapped in
the kernel.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Simon Glass <sjg@chromium.org>
On some single port (otg) controllers there is no emulated root hub, so
the first child (if any) may be one of: UCLASS_MASS_STORAGE,
UCLASS_USB_DEV_GENERIC or UCLASS_USB_HUB.
All three of these (and in the future others) are suitable for our
purposes, remove the check for the device being a hub, and add a check to
deal with the fact that there may be no child-dev.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Simon Glass <sjg@chromium.org>
Allow usb uclass host drivers to implement usb_reset_root_port, this is
used by single port usb hosts which do not emulate a hub, such as otg
controllers.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Simon Glass <sjg@chromium.org>
Now that we unbind usb devices from usb_stop() usb_find_child() is
only necessary to deal with emulated usb devices.
Rename it to make this clear and add a #ifdef to make it a nop in
other cases.
Note the #ifdef turns usb_find_emul_child() into a nop, rather then not
building it and adding another #ifdef to the caller, this is done this way
because adding a #ifdef to the caller is somewhat hairy.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Simon Glass <sjg@chromium.org>
On an usb stop instead of leaving orphan usb devices behind simply remove
them.
The result of this commit is best seen in the output of "dm tree" after
plugging out an usb hub with 2 devices plugges in and plugging in a keyb.
instead, before this commit the output would be:
usb [ + ] `-- sunxi-musb
usb_hub [ ] |-- usb_hub
usb_mass_st [ ] | |-- usb_mass_storage
usb_dev_gen [ ] | `-- generic_bus_0_dev_3
usb_dev_gen [ + ] `-- generic_bus_0_dev_1
Notice the non active usb_hub child and its 2 non active children. The
first child being non-active as in this example also causes usb_get_dev_index
to return NULL when probing the first child, which results in the usb kbd
code not binding to the keyboard.
With this commit in place the output after swapping and "usb reset" is:
usb [ + ] `-- sunxi-musb
usb_dev_gen [ + ] `-- generic_bus_0_dev_1
As expected, and usb_get_dev_index works properly and the keyboard works.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Simon Glass <sjg@chromium.org>
Document that mixing DM_DEVICE_REMOVE and DM_USB is a bad idea, and also why
this is a bad idea.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Simon Glass <sjg@chromium.org>
last_child was abused by the old usb code to first store 1 if the
usb_device was not the root of the usb tree, and then later on re-used
to store whether or not the usb_device is actually the last child.
The dm-usb code was always setting it to actually reflect the last-child
status which is wrong for the last child leading to output like this:
USB device tree:
1 Hub (12 Mb/s, 100mA)
| ALCOR USB Hub 2.0
|
| 2 Mass Storage (12 Mb/s, 100mA)
| USB Flash Disk 4C0E960F
|
+-3 Human Interface (1.5 Mb/s, 100mA)
SINO WEALTH USB Composite Device
Instead of this:
USB device tree:
1 Hub (12 Mb/s, 100mA)
| ALCOR USB Hub 2.0
|
+-2 Mass Storage (12 Mb/s, 100mA)
| USB Flash Disk 4C0E960F
|
+-3 Human Interface (1.5 Mb/s, 100mA)
SINO WEALTH USB Composite Device
This commit fixes this by first checking that the device is not root,
and then setting last_child. This commit also updates the old code to not
abuse the last_child variable to store the root check result.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Simon Glass <sjg@chromium.org>
These functions are useful to remove all children from an usb bus before
rescanning the bus. Give them a better name and export them.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Simon Glass <sjg@chromium.org>
Add an usb_device parameter to usb_reset_root_port so that it knows which
root-port it is resetting. This is necessary for proper device-model support
for usb_reset_root_port.
Also remove a duplicate declaration of usb_reset_root_port() from usb.h .
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Simon Glass <sjg@chromium.org>
Pass the usb_device instead of the portnr to usb_legacy_port_reset and
rename it to usb_hub_port_reset as there is nothing legacy about it.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Simon Glass <sjg@chromium.org>
Drop the unneeded portnr function argument, the portnr is part of the
usb_device struct which is passed via the dev argument.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Simon Glass <sjg@chromium.org>
The device-model usb_legacy_port_reset function calls the device-model
usb_port_reset function which is a 1 on 1 copy of the non dm
usb_legacy_port_reset and this is the only use of usb_port_reset in all
of u-boot.
Drop both, and alway use the usb_legacy_port_reset() version in
common/usb.c .
Also while at it make it static as it is only used in common/usb.c .
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Simon Glass <sjg@chromium.org>
As you see in driver/Makefile, Kbuild descends into the driver/core/
directory only when CONFIG_DM is enabled.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
Currently, DM_FLAG_ACTIVATED is set twice; before calling
uclass_pre_probe_device() and again before calling drv->probe().
It looks like Simon's intention is the first one.
The DM_FLAG_ACTIVATED was moved twice, by commit 02eeb1bbb1
(dm: core: Mark device as active before calling its probe()
method), and then by commit 206d4d2b4b (dm: core: Mark device
as active before calling uclass probe() methods).
The first marking was added by the last move.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
The command "dm uclass" tries to display all the UClasses, but
some of them might be disabled by Kconfig.
The function do_dm_dump_uclass() iterates over all the UClass IDs
and calls uclass_get() for each of them. Then, it displays annoying
message "Cannot find uclass for id ..." every time it fails to get
the UClass.
As a result, we get much noisier log for the "dm uclass" command.
=> dm uclass
uclass 0: root
- * root_driver @ bfb54028, seq 0, (req -1)
Cannot find uclass for id 1: please add the UCLASS_DRIVER() ...
Cannot find uclass for id 2: please add the UCLASS_DRIVER() ...
Cannot find uclass for id 3: please add the UCLASS_DRIVER() ...
Cannot find uclass for id 4: please add the UCLASS_DRIVER() ...
Cannot find uclass for id 5: please add the UCLASS_DRIVER() ...
Cannot find uclass for id 6: please add the UCLASS_DRIVER() ...
This commit suppresses these warnings.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
This function can only handle a syscon device. It is possible that someone
will make a mistake, so add a check for this.
Also we should return -ENODEV when a device cannot be found, so update the
syscon_get_regmap_by_driver_data() to follow this convention.
Signed-off-by: Simon Glass <sjg@chromium.org>
Some functions can return ERR_PTR(errval). Add a unit test macro to check
that no error is returned in a pointer.
Signed-off-by: Simon Glass <sjg@chromium.org>
Each sandbox peripheral should have a size as well as a base address. This
is required for regmaps to work, so make this change for all nodes that have
an address.
Signed-off-by: Simon Glass <sjg@chromium.org>
We normally use -ENODEV for a missing device, rather than -ENOENT. The
latter is reserved for when we have a device but cannot find something
within it.
Also avoid looking at the root LED device since it is only a container.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add a test to confirm that we can probe this device. Since there is no
MMC stack support in sandbox at present, this is as far as the test goes.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add tests that confirm that the drivers work as expected, and we can walk
through the available reset types trying to reset the board.
Signed-off-by: Simon Glass <sjg@chromium.org>
Move sandbox over to use the reset uclass for reset, instead of a direct
call to do_reset(). This allows us to add tests.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add drivers for sandbox. One can only perform a warm reset (which does
nothing). The other can perform a cold reset or a power reset (the
latter will quit U-Boot). These can be used for testing the reset uclass.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add a new reset_walk_halt() function to cause a reset and then halt on
failure. The reset_walk() function returns an error code.
This is needed for testing since otherwise U-Boot will halt in the middle
of a test.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add settings for the last reset generated, and the types of resets which
are permitted. This will be used for testing.
Signed-off-by: Simon Glass <sjg@chromium.org>
All driver model tests have a dm_test_ prefix. Ignore it when matching a
test name. This makes it easier to run individual tests, like this:
./sandbox/u-boot -d ./sandbox/arch/sandbox/dts/test.dtb \
-c "ut dm clk_periph"
We can use 'clk_periph' instead of 'dm_test_clk_periph'.
Also print a message if the requested test is not found.
Signed-off-by: Simon Glass <sjg@chromium.org>
We should guide people more strongly towards device tree to avoid the
proliferation of platform data structures. Add documentation to the driver
model README, and also the platform data header file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Use the common function to obtain the number from the end of the string,
instead of a local function. Also tweak the position of a debug() statement.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
Clocks are an important feature of platforms and have become increasing
complex with time. Most modern SoCs have multiple PLLs and dozens of clock
dividers which distribute clocks to on-chip peripherals.
Some SoC implementations have a clock API which is private to that SoC family,
e.g. Tegra and Exynos. This is useful but it would be better to have a
common API that can be understood and used throughout U-Boot.
Add a simple clock API as a starting point. It supports querying and setting
the rate of a clock. Each clock is a device. To reduce memory and processing
overhead the concept of peripheral clocks is provided. These do not need to
be explicit devices - it is possible to write a driver that can adjust the
I2C clock (for example) without an explicit I2C clock device. This can
dramatically reduce the number of devices (and associated overhead) in a
complex SoC.
Clocks are referenced by a number, and it is expected that SoCs will define
that numbering themselves via an enum.
Signed-off-by: Simon Glass <sjg@chromium.org>
Since we want clk_ops to be used in U-Boot as a whole, rename the Zynq
version until it can be converted to driver model.
Signed-off-by: Simon Glass <sjg@chromium.org>
It is common for system reset to be available at multiple levels in modern
hardware. For example, an SoC may provide a reset option, and a board may
provide its own reset for reasons of security or thoroughness. It is useful
to be able to model this hardware without hard-coding the behaviour in the
SoC or board. Also there is a distinction sometimes between resetting just
the CPU (leaving GPIO state alone) and resetting all the PMICs, just cutting
power.
To achieve this, add a simple system reset uclass. It allows multiple devices
to provide reset functionality and provides a way to walk through them,
requesting a particular reset type until is it provided.
Signed-off-by: Simon Glass <sjg@chromium.org>
Some functions called by mkimage would like to know the output file size.
Initially this is the same as the input file size, but it may be affected by
adding headers, etc.
Add this information to the image parameters.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
As a debug option, add positive confirmation that SPL has completed
execution. This can help with diagnosing the location of unexpected hangs.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add an spl_init() function that does basic init such that board_init_f() can
use simple malloc(), device tree and driver model. Each one is set up only
if enabled for SPL.
Note: We really should refactor SPL such that there is a single
board_init_f() and rename the existing weak board_init_f() functions
provided by boards, calling them from the single board_init_f().
Signed-off-by: Simon Glass <sjg@chromium.org>
It can be quite confusing with a new platform to figure out why the device
tree cannot be located. Add some debug information for this case.
Signed-off-by: Simon Glass <sjg@chromium.org>
Split out the code in fdtdec which finds a number at the end of a string. It
can be useful in other situations.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add an implementation of RC4. This will be used by Rockchip booting but may
be useful in other situations.
Signed-off-by: Simon Glass <sjg@chromium.org>
Since Rockchip requires 32-bit serial access, add this to the driver.
Refactor a little to make this easier.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add support for a driver which sets up DRAM and can return information about
the amount of RAM available. This is a first step towards moving RAM init
to driver model.
Signed-off-by: Simon Glass <sjg@chromium.org>
This bloats the code size quite a bit and is less useful in SPL where there
is no command line.
Avoid including this code in SPL.
Signed-off-by: Simon Glass <sjg@chromium.org>
It is a common requirement to update some PMIC registers. Provide some
simple convenience functions to do this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
To reduce unnecessary code size in an uncommon code path, use debug()
where possible(). The driver returns an error which indicates failure.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
The device tree provides information about which regulators should be
on at boot, or always on. Use this to set them up automatically.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
The regulator_autoset() function mixes printf() output and PMIC adjustment
code. It provides a boolean to control the output. It is better to avoid
missing logic and output, and this permits a smaller SPL code size. So
split the output into a separate function.
Also rename the function to have a by_name() suffix, since we would like
to be able to pass a device when we know it, and thus avoid the name
search.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
Decide when the regulator is set up whether we want to auto-set the voltage
or current. This avoids the complex logic spilling into the processing code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
This is not user input (i.e. from the command line). It should be possible
to get the case correct and avoid the case-insensitive match. This will
help avoid sloppy device tree setups.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
It took a little while to figure this out, so this patch adds documentation
to help the next person who needs to do this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add basic support for MMC, providing a uclass which can set up an MMC
device. This allows MMC drivers to move to using driver model.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add a simple uclass for LEDs, so that these can be controlled by the device
tree and activated when needed. LEDs are referred to by their label.
This implementation requires a driver for each type of LED (e.g GPIO, I2C).
Signed-off-by: Simon Glass <sjg@chromium.org>
Many SoCs have a number of system controllers which are dealt with as a
group by a single driver. It is a pain to have to add lots of compatible
strings and/or separate drivers for each. Instead we can identify the
controllers by a number and request the address of the one we want.
Add a simple implementation of this which can be used by SoC driver code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add a simple implementaton of register maps, supporting only direct I/O
for now. This can be enhanced later to support buses which have registers,
such as I2C, SPI and PCI.
It allows drivers which can operate with multiple buses to avoid dealing
with the particulars of register access on that bus.
Signed-off-by: Simon Glass <sjg@chromium.org>
This function can be used for testing to manually request a GPIO for use,
without resorting to the legacy GPIO API.
Signed-off-by: Simon Glass <sjg@chromium.org>
In some rare cases it is useful to be able to locate a device given a device
tree node offset. An example is when you have an alias that points to a node
and you want to find the associated device. The device may be SPI, MMC or
something else, but you don't need to know the uclass to find it.
Add a function to do a global search for a device, given its device tree
offset.
Signed-off-by: Simon Glass <sjg@chromium.org>
To avoid bloating SPL code, use debug() where possible in the driver model
core code. The error code is already returned, and can be investigated as
needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
In SPL it is sometimes useful to be able to obtain a dump of the current
driver model state. Since commands are not available, provide a way to
directly call the functions to output this information.
Adjust the existing commands to use these functions.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present printf() skips output if it can see there is no console. This
is really just an optimisation, and is not necessary. Also it is currently
incorrect in some cases. Rather than update the logic, just remove it so
that we don't need to keep it in sync.
Signed-off-by: Simon Glass <sjg@chromium.org>
When there is no console ready, allow the debug UART to be used for output.
This makes debugging of early code considerably easier.
Signed-off-by: Simon Glass <sjg@chromium.org>
This does not actually help any current arch. For x86 it makes it harder
to call (requires stack) and for ARM it has no effect. Drop it.
Signed-off-by: Simon Glass <sjg@chromium.org>
U-Boot uses structures for hardware access so it is important that these
structures are correct. Add a way of asserting that a structure member is
at a particular offset. This can be created using the datasheet for the
hardware.
This implementation uses Static_assert() since BUILD_BUG_ON() only works
within functions.
Signed-off-by: Simon Glass <sjg@chromium.org>
Driver-model I2C drivers can be picked up by the linker script rule for
legacy drivers. Change the order to avoid this.
We could make the legacy code depend on !CONFIG_DM_I2C but that is not
necessary and it is good to keep conditions to a minimum.
Signed-off-by: Simon Glass <sjg@chromium.org>
The SPL device tree size must be minimised to save memory. Only include
properties that are needed by SPL - this is determined by the presence
of the "u-boot,dm-pre-reloc" property. Also remove a predefined list of
unused properties from the nodes that remain.
Signed-off-by: Simon Glass <sjg@chromium.org>
This tool allows us to extract subsets of a device tree file. It is used by
the SPL vuild, which needs to cut down the device tree size for use in
limited memory.
This tool was originally written for libfdt but it has not been accepted
upstream, so for now, include it in U-Boot. Several utilfdt library
functions been included inline here.
If fdtgrep is eventually accepted in libfdt then we can bring that version
of libfdt in here, and drop fdtgrep (requiring that fdtgrep is provided by
the user).
If it is not accepted then another approach would be to write a special
tool for chopping down device tree files for SPL. While it would use the
same libfdt support, it would be less code than fdtgrep.c because it would
not have general-purpose functions.
Another approach (which was used with v1 of this series) is to sprinkler all
the device tree files with #ifdef. I don't like that idea.
Signed-off-by: Simon Glass <sjg@chromium.org>
These have been sent upstream but not accepted to libfdt. For now, bring
these into U-Boot to enable fdtgrep to operate. We will use fdtgrep to
cut device tree files down for SPL.
Signed-off-by: Simon Glass <sjg@chromium.org>
Property names are stored in a string table. When a node property is
removed, the string table is not updated since other nodes may have a
property with the same name.
Thus it is possible for the string table to build up a number of unused
strings. Add a function to remove these. This works by building a new device
tree from the old one, adding strings one by one as needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Offer to display the available image types in help. Also, rather than
hacking the genimg_get_type_id() function to display a list of types,
do this in the tool. Also, sort the list.
The list of image types is quite long, and hard to discover. Print it out
when we show help information.
Signed-off-by: Simon Glass <sjg@chromium.org>
Drystone provides a convenient sanity check that the CPU is running at full
speed. Add this as a command which can be enabled as needed.
Note: I investigated using Coremark for this but there was a license
agreement and I could not work out if it was GPL-compatible.
Signed-off-by: Simon Glass <sjg@chromium.org>
When final MMU table is setup in DDR, TCR attributes must match
those of the memroy for cacheability and shareability.
Signed-off-by: Zhichun Hua <zhichun.hua@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
For ARMv8, outer shareable is 0b10, inner shareable is 0b11 at bit
position [13:12] of TCR_ELx register.
Signed-off-by: Zhichun Hua <zhichun.hua@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Freescale DSPI driver has been converted to Driver Model.
The new driver depends on OF_CONTROL, DM, DM_SPI.
This patch enable FSL_DSPI and its dependence configure options.
Signed-off-by: Haikun Wang <haikun.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
DSPI has pin muxing with SDHC and other IPs, this patch check the
value of RCW SPI_PCS_BASE and SPI_BASE_BASE fields, it also check
the "hwconfig" variable. If those pins are configured to DSPI and
"hwconfig" enable DSPI, set the BRDCFG5 of QIXIS CPLD to configure
the routing to on-board SPI memory. Otherwise will configure to SDHC.
DSPI is enabled in "hwconfig" by appending "dspi", eg.
setenv hwconfig "$hwconfig;dspi"
Signed-off-by: Haikun Wang <Haikun.Wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
DSPI has pin muxing with SDHC and other IPs, this patch check the
value of RCW SPI_PCS_BASE and SPI_BASE_BASE fields, it also check
the "hwconfig" variable. If those pins are configured to DSPI and
"hwconfig" enable DSPI, set the BRDCFG5 of QIXIS FPGA to configure
the routing to on-board SPI memory. Otherwise will configure to SDHC.
DSPI is enabled in "hwconfig" by appending "dspi", eg.
setenv hwconfig "$hwconfig;dspi"
Signed-off-by: Haikun Wang <haikun.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Bring in required device tree files for ls2085a from Linux. These are
initially unchanged and have a number of pieces not needed by U-Boot.
Signed-off-by: Haikun Wang <Haikun.Wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
As SCFG_ENDIANCR register is added to choose little-endian or big-endian
for audio IPs on Rev2.0 silion, little-endian mode is selected.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Base on PSCI services, implement CPU_ON/CPU_OFF for ls102xa platform.
Tested on LS1021AQDS, LS1021ATWR.
Test CPU hotplug times: 60K
Test kernel boot times: 1.2K
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Acked-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
timer_wait is moved from sunxi/psci_sun7i.S, and it can be converted
completely into a reusable armv7 generic timer. LS1021A will use it
as well.
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: York Sun <yorksun@freescale.com>
As the function 'sprintf' does not check buffer boundaries but outputs
to the buffer 'enet' of fixed size (16), this patch removes the function
'sprintf', and uses 'strcpy' instead. It will assign the character
arrays 'enet' and 'phy' the corresponding character strings.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Linux itb image size has been increased from 30MB.
So updating kernel_size to 40MB in env variable.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Change infinite loop mechanism to timer based polling for QBMAN release in
ldpaa_eth_rx.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Polling of TX conf frames is not a mandatory option.
Packets can be transferred via WRIOP without TX conf frame.
Configure ldpaa_eth driver to use TX path without confirmation frame
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Volatile command does not return frame immidiately, need to wait till a frame
is available in DQRR. Ideally it should be a blocking call.
Add timeout handling for DQRR frame instead of retry counter.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Do not immediately return if the enqueue function returns -EBUSY; re-try
mulitple times.
if timeout occures, release the buffer.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This patch adds the infrastructure to update device
tree nodes to convey SMMU stream IDs in the device
tree. Fixups are implemented for PCI controllers
initially.
Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Stream IDs on ls2085a devices are not hardwired and are
programmed by sw. There are a limited number of stream IDs
available, and the partitioning of them is scenario dependent.
This header defines the partitioning between legacy, PCI,
and DPAA2 devices.
Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Management complex major version should match to the firmware present in flash.
Return error during mismatch of major version.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Update flibs changes to mc-0.6.0.1 for dpmang, dprc, dpni and dpio objects
Also rename qbman_portal_ce/ci_paddr to qbman_portal_ce/ci_offset in
dpio_attr. These are now offsets from the SoC QBMan portals base.
Signed-off-by: J. German Rivera <German.Rivera@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Flush buffer before releasing to BMan after TX_conf to ensure, the core does
not have any cachelines that the WRIOP will DMA to.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Signed-off-by: Stuart Yoder <stuart.yoder at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
The agreed split of the top of memory is 256M for debug server and 256M
for MC. This patch implements the split.
In addition, the MC mem must be 512MB aligned, so the amount of memory
to hide must be 512MB to achieve that alignment.
Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This patch updates the setting of required bits for A57 cores erratas
- 828024 and 826974
Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com>
Signed-off-by: Dai Haruki <dai.haruki at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This patch fixes the DDR hide logic for LS2085a, correcting the way
the Debug Server FW and MC FW images are placed on the top of system
DDR and how the rest of the system DDR space is made visibile to Linux.
Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Update SoC README to provide details of
- Memory regions
- Memory used by MC and Debug server
Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This patch allows u-boot to expose the complete DDR region(s) to Linux
(after subtracting the memory hidden via MEM_TOP_HIDE mechanism).
This allows the u-boot to support the 48-bit VA support provided by
ARM64 Linux in flavors 3.18 and above, by passing the appropriate
'memory' DTS nodes.
Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Board rev C and earlier has duplicated SPD address on 2nd DDR
controller slots. It is fixed on rev D and later. SPD addresses
need to be updated accordingly.
Signed-off-by: York Sun <yorksun at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
In case SPD address changes between board revisions, updating SPD
address can be called from board file.
Signed-off-by: York Sun <yorksun at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
LS2085A supports 6 personalities i.e. LS2045AE, LS2045A, LS2080AE,
LS2080A, LS2085AE and LS2085A personlities.
Instead of hard-coding, board name should change as per selected
personality.
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This patch adds support to print out the SoC personality.
Freescale LS20xx SoCs (compliant to Chassis-3 specifications) can
have 6 personalities: LS2045AE, LS2045A, LS2080AE, LS2080A,
LS2085AE and LS2085A
Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
DDR speed should be in MT/s, not MHz.
Signed-off-by: York Sun <yorksun at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
As per updated board document, no need to substract 1 from arch[BRD]
bit field. Default value + 'A' represents the board revision.
So update board version print logic to reflect the same.
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
SYSTEM ID EPPROM always store SYSTEM version info in big endian format.
SoC with ARM or PowerPC core should read/write version info from eeprom
in BIG endian format.
So use cpu-specific APIs to read SYSTEM version.
Signed-off-by: Jaiprakash Singh <b44839 at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Increases the kernel size supported for LS2085A platforms:-
- Update environment variables
- Add ramdisk_size in bootargs env variable
- Define CONFIG_SYS_BOOTM_LEN to 64MB
Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Primary Mux on I2C1 controller has slave address as 0x75.
So update its address.
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
FPGA BRDCFG9[SFP_TX] should be clear in order to enable XFI ports.
Signed-off-by: Dai Haruki <Dai.Haruki at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
call ft_pci_setup() to disable PCIe dts node if corresponding
PCIe controller is disabled according to RCW
Signed-off-by: Minghuan Lian <Minghuan.Lian at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Compatible field "fsl,20851a-pcie" is not correct.
So update it to "fsl,ls2085a-pcie"
Signed-off-by: Minghuan Lian <Minghuan.Lian at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
SerDes Protocol 0x49 enables 4 SGMII, PEX4, SATA1 and SATA2.
Add support of 0x49 SerDes protocol to enable 4SGMII on slot4 of
ls2085aqds platform.
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Enable "date" command for QDS and RDB boards
Signed-off-by: Priyanka Jain <Priyanka.Jain at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Add hwconfig setting for eSDHC since it shares some pins with other
IP block.
Signed-off-by: Yangbo Lu <yangbo.lu at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Add support for board eth initialization and support for loading phy
firmware. PHY firmware needs to be loaded from board_eth_init() because
all the MACs are not initialized by ldpaa_eth driver.
Signed-off-by: pankaj chauhan <pankaj.chauhan at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Currently, this function returns a positive value on error,
so we never know whether this function has succeeded or failed.
For example, if the given property is not found, fdt_getprop()
returns -FDT_ERR_NOTFOUND, and then this function inverts it,
i.e., returns FDT_ERR_NOTFOUND (=1).
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Fixes: bc4147ab2d ("fdt: Add a function to count strings")
Acked-by: Simon Glass <sjg@chromium.org>
As mentioned in the comment block in include/libfdt.h,
fdt_get_string_index() is supposed to return a negative value
on error.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Fixes: 5094eb408a ("fdt: Add functions to retrieve strings")
Acked-by: Simon Glass <sjg@chromium.org>
Looks like this comment was copied from that of
fdt_get_string_index().
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Fixes: 5094eb408a ("fdt: Add functions to retrieve strings")
Acked-by: Simon Glass <sjg@chromium.org>
Commit 90fbee3e40 ("cmd_fdt: Actually fix fdt command in sandbox")
changed the format(from hex address to unsigned long) in which "fdtaddr"
is saved . However do_fdt continues reads the "fdtaddr" assuming it to
be in hex format. This may lead to fdt being either loaded or attempted
to load at erroneous address generating fault if the address is out of
memory.
This patch changes back the format to hex while saving the "fdtaddr"
as it was done before.
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Hua Yanghao <huayanghao@gmail.com>
Cc: Heiko Schocher <hs@denx.de>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Simon Glass <sjg@chromium.org>
Fix below build warnings on armv8,
drivers/spi/fsl_dspi.c: In function ‘fsl_dspi_ofdata_to_platdata’:
drivers/spi/fsl_dspi.c:667:2:
warning: format ‘%x’ expects argument of type ‘unsigned int’,
but argument 2 has type ‘fdt_addr_t’ [-Wformat=]
debug("DSPI: regs=0x%x, max-frequency=%d, endianess=%s, num-cs=%d\n",
^
lib/fdtdec.c: In function ‘fdtdec_get_addr_size’:
lib/fdtdec.c:105:4:
warning: format ‘%lx’ expects argument of type ‘long unsigned int’,
but argument 3 has type ‘fdt_size_t’ [-Wformat=]
debug("addr=%08lx, size=%08lx\n",
^
Signed-off-by: Haikun Wang <haikun.wang@freescale.com>
Acked-by: Simon Glass <sjg@chromium.org>
Avoid clearing the reg property in the memory DT node if no memory
banks have been specified for a board (CONFIG_NR_DRAM_BANKS == 0).
This allows boards to let U-Boot skip the DT memory tinkering in case
other firmware has already setup the node properly before.
This should be safe as all callers of fdt_fixup_memory_banks that use
a computed <banks> value put at least 1 in there.
Add some documentation comments to the header file.
Signed-off-by: Andre Przywara <osp@andrep.de>
Acked-by: Simon Glass <sjg@chromium.org>
Currently PCI expansion ROM address is assigned by a call to
pciauto_setup_rom() outside of the pci auto config process.
This does not work when expansion ROM is on a device behind
PCI bridge where bridge's memory limit register was already
programmed to a value that does not cover the newly assigned
expansion ROM address. To fix this, we should configure the
ROM address during the auto config process.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
This driver was originally added to support the native IDE mode for
Intel chipset, however it has some bugs like not supporting ATAPI
devices, endianness issue, or even broken build when CONFIG_LAB48.
Given no board is using this driver as of today, rather than fixing
all these issues we just remove it from the source tree.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Update crownbay_defconfig and minnowmax_defconfig with 'savedefconfig'
result so that the config option order matches Kconfig.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
On 32-bit machine strtol() returns LONG_MAX which is 0x7fffffff,
which is wrong for u-boot.rom components like u-boot-x86-16bit.bin.
Change to use strtoll() so that it works on both 32-bit and 64-bit
machines.
Reported-by: Fei Wang <wangfei.jimei@gmail.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
To try to reduce the pain of confusion of binary blobs, add MD5 checksums
for the current versions. This may worsen the situation as new versions
appear, but it should still be possible to obtain these versions, and thus
get a working setup.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Commit afbbd413a fixed this for non-driver-model. Make sure that the driver
model code handles this also.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Adjust minnowmax to use driver model for PCI. This requires adding a device
tree node to specify the ranges, removing the board-specific PCI code and
ensuring that the host bridge is configured.
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
This driver should use the x86 PCI configuration functions. Also adjust its
compatible string to something generic (i.e. without a vendor name).
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The layout of the ROM is a bit hard to discover by reading the code. Add
a table to make it easier.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The logic is incorrect and currently has no effect. Fix it so that we can
write to SPI flash, since by default it is write-protected.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
The status register on ICH9 is a single byte, so use byte access when
writing to it, to avoid updating the control register also.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Enable graphics support on Intel Crown Bay board With the help of
vgabios for Intel TunnelCreek IGD. Tested with an external LVDS
panel connected to X4 connector and SDVO adapter connected to X9
connector on the board.
Signed-off-by: Jian Luo <jian.luo4@boschrexroth.de>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
MARK_GRAPHICS_MEM_WRCOMB is not referenced anywhere in the code,
hence remove it.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Move X86_OPTION_ROM_FILE & X86_OPTION_ROM_ADDR to arch/x86/Kconfig
and rename them to VGA_BIOS_FILE & VGA_BIOS_ADDR which depend on
HAVE_VGA_BIOS. The new names are consistent with other x86 binary
blob options like HAVE_FSP/FSP_FILE/FSP_ADDR.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Print the meaningful base address and mask of an MTRR range without showing
the memory type encoding or valid bit.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Per CPUID:80000008h result, the maximum physical address bits of
TunnelCreek processor is 32 instead of default 36. This will fix
the incorrect decoding of MTRR range mask.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
We should setup fixed range MTRRs for some legacy regions like VGA
RAM and PCI ROM areas as uncacheable. Note FSP may setup these to
other cache settings, but we can override this in x86_cpu_init_f().
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
The TunnelCreek IGD VBE reports 32-bit color depth regardless 24-bit
color depth is configured. Since 24-bit mode already uses 4 bytes
internally, it should be OK to just add this option in switch case.
Signed-off-by: Jian Luo <jian.luo4@boschrexroth.de>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
We should allow pci config read/write to host bridge (b.d.f = 0.0.0)
in the int1a_handler() which is a valid pci device.
Signed-off-by: Jian Luo <jian.luo4@boschrexroth.de>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
PCI option rom may use different SS during its execution, so it is not
safe to assume esp pointed to the same location in the protected mode.
Signed-off-by: Jian Luo <jian.luo4@boschrexroth.de>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Per PCI spec, VGA device reports its class as standard 030000h in
its configuration space, so we can use it to determine if we need
run option rom instead of testing the supported vendor/device ids.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
The sub-bus passed to pciauto_prescan_setup_bridge() is incorrect. Fix it
so that sub-buses are numbered correctly.
Signed-off-by: Simon Glass <sjg@chromium.org>
Only the PCI controller has access to the PCI region information. Make sure
to use the controller (rather than any attached bridges) when configuring
devices.
This corrects a failure to scan and configure devices when driver model is
enabled for PCI.
Also add a comment to explain the problem.
Signed-off-by: Simon Glass <sjg@chromium.org>
So far interrupt routing works pretty well for any on-chip devices
on Intel Crown Bay. When inserting any PCIe card to any PCIe slot,
Linux kernel is smart enough to do interrupt swizzling and figure
out device's irq using its parent bridge's interrupt routing info
all the way up to its root port. In U-Boot all PCIe root ports'
interrupts were routed to PIRQ E/F/G/H before, while actually all
PCIe downstream ports received INTx are routed to PIRQ A/B/C/D
directly and not configurable. Now we change this mapping so that
any external PCIe device can work correctly.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Document U-Boot multi-processor support as well as configuration
tables like SFI and MP tables for SMP OS kernel.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Implement write_mp_table() to create a minimal working MP table.
This includes an MP floating table, a configuration table header
and all of the 5 base configuration table entries. The I/O interrupt
assignment table entry is created based on the same information used
in the creation of PIRQ routing table from device tree. A check
duplicated entry logic is applied to prevent writing multiple I/O
interrupt entries with the same information.
Use a Kconfig option GENERATE_MP_TABLE to tell U-Boot whether we
need actually write the MP table at the F seg, just like we did for
PIRQ routing and SFI tables. With MP table existence, linux kernel
will switch to I/O APIC and local APIC to process all the peripheral
interrupts instead of 8259 PICs. This takes full advantage of the
multicore hardware and the SMP kernel.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
The MP table provides a way for the operating system to support
for symmetric multiprocessing as well as symmetric I/O interrupt
handling with the local APIC and I/O APIC. We provide a bunch of
APIs for U-Boot to write the floating table, configuration table
header as well as base and extended table entries.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Remove inline for lapic access routines and expose lapic_read()
& lapic_write() as APIs to read/write lapic registers. Also move
stop_this_cpu() to mp_init.c as it has nothing to do with lapic.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
I/O APIC registers are addressed indirectly. Add io_apic_read() and
io_apic_write() routines to help register access. Two macros for I/O
APIC ID and version register offset are also added.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
There is no need to populate multiple irq info entries with the same
bus number and device number, but with different interrupt pin. We
can use the same entry to store all the 4 interrupt pin (INT A/B/C/D)
routing information to reduce the whole PIRQ routing table size.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
In fill_irq_info() pci device's function number is written into
the table, however this is not really necessary. The function
number can be anything as OS doesn't care about this field,
neither does the PIRQ routing specification. Change to always
writing 0 as the function number.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
We should write correct bus number to the PIRQ routing table for the
irq router from device tree, instead of hard-coded zero.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
There are 4 usb ports on the Intel Crown Bay board, 2 of which are
connected to Topcliff usb host 0 and the other 2 connected to usb
host 1. USB devices inserted in the ports connected to usb host 1
cannot get detected due to wrong IRQ assigned to the controller.
Actually we need apply the PCI interrupt pin swizzling logic to all
devices on the Topcliff chipset when configuring the PIRQ routing.
This was observed on usb ports, but device 6 and 10 irqs are also
wrong. Correct them all together.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Currently CONFIG_DM_I2C is used in cmd_date.c for driver model,
but it should be actually CONFIG_DM_RTC.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Add driver model support to the mc146818 rtc driver. Also clean up
the driver a little bit for coding convention issues.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Intel Crown Bay board has a TunnelCreek processor which supports
hyper-threading. Add /cpus node in the crownbay.dts and enable
the MP initialization.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
(modified to remove error:
overriding the value of OF_CONTROL. Old value: "y", new value: "y")
This commit cleans up the lapic codes:
- Delete arch/x86/include/asm/lapic_def.h, and move register and bit
defines into arch/x86/include/asm/lapic.h
- Use MSR defines from msr-index.h in enable_lapic() and disable_lapic()
- Remove unnecessary stuff like NEED_LAPIC, X86_GOOD_APIC and
CONFIG_AP_IN_SIPI_WAIT
- Move struct x86_cpu_priv defines to asm/arch-ivybridge/bd82x6x.h, as
it is not apic related and only used by ivybridge
- Fix coding convention issues
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Currently lapic_setup() is called before calling mp_init(), which
then calls init_bsp() where it calls enable_lapic(), which was
already enabled in lapic_setup(). Hence move lapic_setup() call
into init_bsp() to avoid the duplication.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Most of the MP initialization codes in arch/x86/cpu/baytrail/cpu.c is
common to all x86 processors, except detect_num_cpus() which varies
from cpu to cpu. Move these to arch/x86/cpu/cpu.c and implement the
new 'get_count' method for baytrail and cpu_x86 drivers. Now we call
cpu_get_count() in mp_init() to get the number of CPUs.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Introduce a new method 'get_count' in the UCLASS_CPU ops to get
the number of CPUs in the system.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Move MAX_CPUS definition after SMP so that it shows below SMP in the
menuconfig. Also replace the leading spaces in the MAX_CPUS section
with tabs to conform coding standard.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
This commit does the following to clean up x86 cpu dm drivers:
- Move cpu_x86 driver codes from arch/x86/cpu/cpu.c to a dedicated
file arch/x86/cpu/cpu_x86.c
- Rename x86_cpu_get_desc() to cpu_x86_get_desc() to keep consistent
naming with other dm drivers
- Add a new cpu_x86_bind() in the cpu_x86 driver which does exactly
the same as the one in the intel baytrail cpu driver
- Update intel baytrail cpu driver to use cpu_x86_get_desc() and
cpu_x86_bind()
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
In cpu_get_info() it wrongly tests against cpu_ops->get_desc to see
if it is NULL. It should test against cpu_ops->get_info.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Rather than just 'ERROR', display the error code, which may be useful, at
least with driver model.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagan Teki <jteki@openedev.com>
The call to FspInitEntry is done in arch/x86/lib/fsp/fsp_car.S so far.
It worked pretty well but looks not that good. Apart from doing too
much work than just enabling CAR, it cannot read the configuration
data from device tree at that time. Now we want to move it a little
bit later as part of init_sequence_f[] being called by board_init_f().
This way it looks and works better in the U-Boot initialization path.
Due to FSP's design, after calling FspInitEntry it will not return to
its caller, instead it jumps to a continuation function which is given
by bootloader with a new stack in system memory. The original stack in
the CAR is gone, but its content is perserved by FSP and described by
a bootloader temporary memory HOB. Technically we can recover anything
we had before in the previous stack, but that is way too complicated.
To make life much easier, in the FSP continuation routine we just
simply call fsp_init_done() and jump back to car_init_ret() to redo
the whole board_init_f() initialization, but this time with a non-zero
HOB list pointer saved in U-Boot's global data so that we can bypass
the FspInitEntry for the second time.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
Tested-by: Simon Glass <sjg@chromium.org>
Currently the FSP execution environment GDT is setup by U-Boot in
arch/x86/cpu/start16.S, which works pretty well. But if we try to
move the FspInitEntry call a little bit later to better fit into
U-Boot's initialization sequence, FSP will fail to bring up the AP
due to #GP fault as AP's GDT is duplicated from BSP whose GDT is
now moved into CAR, and unfortunately FSP calls AP initialization
after it disables the CAR. So basically the BSP's GDT still refers
to the one in the CAR, whose content is no longer available, so
when AP starts up and loads its segment register, it blows up.
To resolve this, we load GDT before calling into FspInitEntry.
The GDT is the same one used in arch/x86/cpu/start16.S, which is
in the ROM and exists forever.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
Tested-by: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
Since buildman now includes most of the features of MAKEALL it is probably
time to talk about deprecating MAKEALL.
Comments welcome.
Signed-off-by: Simon Glass <sjg@chromium.org>
Commit 2b42c9317d ("ahci: support LBA48 data reads for 2+TB drives")
introduced conditional code which triggers a warning when compiled
with DEBUG enabled:
In file included from common/cmd_scsi.c:12:0:
common/cmd_scsi.c: In function 'scsi_read':
include/common.h:109:4: warning: 'smallblks' may be used uninitialized in this function [-Wmaybe-uninitialized]
...
Since this is for debug only, take the easy way and initialize the
variable explicitly on declaration to avoid the warning.
(Fix a nearby whitespace error on the way.)
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Andre Przywara <osp@andrep.de>
Since commit 09c3280754 (mtd, nand: Move common functions from
cmd_nand.c to common place), NAND commands would not work at all
on large devices.
=> nand read 80000000 10000 10000
NAND read: Offset exceeds device limit
=> nand erase 100000 100000
NAND erase: Offset exceeds device limit
The type of the "size" of "struct mtd_info" is uint64_t, while
mtd_arg_off_size() and mtd_arg_off() treat chipsize as int type.
The chipsize is wrapped around if the argument is given with 2GB
or larger.
Acked-by: Heiko Schocher <hs@denx.de>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This patch enabled the USB/EHCI support for the Marvell
DB-88F6820-GP eval board.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
This patch adds USB EHCI host support for the common mvebu platform.
Including the Armada 38x.
Tested on DB-88F6280-GP eval board.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Configure and enable the SATA/SCSI (AHCI) support for the Marvell
DB-88F6820-GP eval board.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
This patch adds support for the common AHCI controller on the Marvell
Armada 38x.
Tested on the Marvell DB-88F6820-GP eval board.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
This patch changes the initialization of the AHCI controller to not
enable the default interrupts (DEF_PORT_IRQ). As interrupts are
not used in U-Boot in general, this should not break the common AHCI
driver operation.
This change is needed to support the Marvell Armada 38x AHCI
controller. With interrupts enabled, this results in timeouts in
ahci_device_data_io(). Not enabling these interrupts fixes this
problem and the common AHCI driver works fine.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
This patch adds MMC/SDIO support to the Marvell DB-88F6820-GP board
configuration. Including support for the common partitions and
filesystems.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Armada A38x implements an SDHCI compatible SDIO controller. This patch
enables the Marvell driver to support this SoC. And enables the
SDIO controller if selected by the board configuration.
Tested on Marvell DB-88F6820-GP board.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
While implementing SDIO/MMC SPL booting for the Marvell Armada 38x, the
following problem occured. The SPL runs in internal SRAM which is
the L2 cache locked to memory. When the MMC buffers now are located
on the stack (or bss), the SDIO controller (SDHCI) can't write into
this L2 cache memory.
This patch introduces a method to use a fixed buffer that will be
used for all transfers by defining CONFIG_FIXED_SDHCI_ALIGNED_BUFFER.
This way, the board can use this buffer address located in SDRAM
for all transfers. This solves this SPL problem on the A38x and
should only be used in the SPL U-Boot version.
Tested for SPL booting on Marvell Armada 38x DB-88F6820-GP board.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
The loop counter based timeout detection does not work on the Armada
38x based board (DB-88F6820-GP). At least with dcache enabled a
timeout is detected. Without dcache enabled, the timeout does not
occur. Increasing the loop counter solves this issue. But a better
solution is to use a timer based timeout detection instead. This
patch now implements this timer based detection.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
When driver model is not used the current code does not correctly select
the pinmux for the I2C bus. This bug was introduced by this commit:
8dfcbaa dm: i2c: s3c24x0: adjust to dm-i2c api
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Przemyslaw Marczak <p.marczak@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
The temperature calculation must be typecasted to keep the compiler
from sign extending a negative value prior to division.
This fixes an issue where if the CPU temperature is <0C it will get stuck
in the busywait loop until the CPU heats up to 0C.
Cc: Ye Li <b37916@freescale.com>
Cc: Jason Liu <r64343@freescale.com>
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
imximage header size is 4-byte, not 8-byte aligned.
This produces .imx images that a Vybrid cannot boot
on.
Fix by adding a "padding" field in header.
Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
Add support in mxc_i2c driver, iomux_v3 and vf610 architecture for the four
I2C instances available in VF610.
Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
This locally defined struct is actually only used once
and as an opaque type. Remove it for clarity.
Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
hab_status command returns a memory dump of the hab event log. But the
raw data is not human-readable. Parsing such data into readable event
will help to minimize debbuging time.
Signed-off-by: Ulises Cardenas <Ulises.Cardenas@freescale.com>
Add I2C4 clock support for i.MX6SX. Since we use runtime check,
but not macro, we need to remove `#ifdef ..` in crm_regs.h, or
gcc will fail to compile the code succesfully.
Making the macros only for i.MX6SX open to other i.MX6x maybe not
a good choice, but we have runtime check.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
enable_spi_clock does the same thing with enable_cspi_clock, so
remove enable_cspi_clock.
Remove enable_cspi_clock prototype in header file
convert cm_fx6/spl.c to use enable_spi_clk
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
According to README.mxc_ocotp the OCOTP is a stanard i.MX6 SoC feature
so centralise the config in mx6_common.h so functionality is standard
across all boards
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Remove the check for temperature being within the min/max range and enter the
busywait cooling loop whenever the CPU temperature is over the critical temp.
This fixes the issue where if a board was booted at a temp greater than
the CPU temperature max, it would skip the loop and never indicate or try
to address the overtemp issue.
Cc: Ye Li <b37916@freescale.com>
Cc: Jason Liu <r64343@freescale.com>
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
When compling under 64bit platforms, there are lots of warnings,
like:
drivers/block/ahci.c:114:18: warning: cast to pointer from integer
of different size [-Wint-to-pointer-cast]
u8 *port_mmio = (u8 *)probe_ent->port[port].port_mmio;
^
drivers/block/ahci.c: In function ?.hci_host_init?.
drivers/block/ahci.c:218:49: warning: cast from pointer to integer
of different size [-Wpointer-to-int-cast]
probe_ent->port[i].port_mmio = ahci_port_base((u32) mmio, i);
......
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Baltos has USB0 connected to a USB hub and thus is host-only. USB1
is connected to microUSB connector and thus should use OTG mode.
Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
Because it is possible for the MTD number to change, causing a
filesystem mount failure, we should use the volume name instead
of the MTD number and let Linux resolve the correct one.
Signed-off-by: Mike Scherban <m-scherban@ti.com>
On STM32F429 gpio PC6/PC7 can be allocated for USART6, as
reported in the comment.
But current code in
drivers/serial/serial_stm32.c
uses a different gpio mapping (PG14/PG9) for USART6.
Fix the comment to match current code in the driver.
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
To: u-boot@lists.denx.de
To: Kamil Lulko <rev13@wp.pl>
Cc: Tom Rini <trini@konsulko.com>
When "scripts/get_maintainer.pl" parses "board/.../MAINTAINERS",
it uses the line containing board name as delimiter.
Without this line, the script happily mixes the lines from current
board MAINTAINERS file with lines from another file.
Fix it by adding a reasonable board name.
Tested by comparing output of:
cat board/st/stm32f429-discovery/MAINTAINERS
./scripts/get_maintainer.pl -f board/st/stm32f429-discovery
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
To: u-boot@lists.denx.de
To: Kamil Lulko <rev13@wp.pl>
Cc: Tom Rini <trini@konsulko.com>
Use one mtd partition for rootfs and configuration by
means of ubi volumes and get rid of configuration partition.
We can use partition layout for both 256MB and 512MB flash.
Signed-off-by: Samuel Egli <samuel.egli@siemens.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Roger Meier <r.meier@siemens.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Heiko Schocher <hs@denx.de>
Specify proper U-Boot offset, enable prefetch mode,
increase bootm size and add FIT fallback, if board_name
is not present in kernel-fit.itb image.
Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
This action is need to make I2C communication with PMIC
stable for low temperature. Print current I2C speed in
SPL for visual control.
Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
If board is booted with transitions happening on DCAN1 pins then
the following warning is seen in the kernel at boot when the
hwmod layer initializes.
"omap_hwmod: dcan1: _wait_target_disable failed"
This is because DCAN1 module's SWAKEUP mechanism is broken
and it fails to correctly turn OFF if it sees a transition on the
DCAN1 pins. Suggested workaround is to keep DCAN1 pins in safe mode
while enabling/disabling DCAN1 module.
The hwmod layer enables and disables all modules at boot
and we have no opportunity to put the DCAN1 pins in safe mode
at that point.
DCAN1 is not used by u-boot so it doesn't matter to it if these
pins are in safe mode. The kernel driver correctly configures
the right mode when DCAN1 is active.
Signed-off-by: Roger Quadros <rogerq@ti.com>
[trini: s/PULLUP/PULL_UP/ based on DRA7xx EVM version of this patch]
Signed-off-by: Tom Rini <trini@konsulko.com>
If board is booted with transitions happening on DCAN1 pins then
the following warning is seen in the kernel at boot when the
hwmod layer initializes.
"omap_hwmod: dcan1: _wait_target_disable failed"
This is because DCAN1 module's SWAKEUP mechanism is broken
and it fails to correctly turn OFF if it sees a transition on the
DCAN1 pins. Suggested workaround is to keep DCAN1 pins in safe mode
while enabling/disabling DCAN1 module.
The hwmod layer enables and disables all modules at boot
and we have no opportunity to put the DCAN1 pins in safe mode
at that point.
DCAN1 is not used by u-boot so it doesn't matter to it if these
pins are in safe mode. The kernel driver correctly configures
the right mode when DCAN1 is active.
Signed-off-by: Roger Quadros <rogerq@ti.com>
-fdelete-null-pointer-checks flag controls global dataflow analyses and
eliminate useless checks for null pointers; It assume that if a pointer is
checked after it has already been dereferenced, it cannot be null.
This flag is enabled by default.
gcc v4.9 has more optimizations added to this option. Hence it is very
aggressive with GCC v4.9 series. Add -fno-delete-null-pointer-checks to
disable the optimization
Signed-off-by: Rohit Dharmakan <rohitarulraj@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
The word "partition" is doubled. Keep decent forms for the
following lines.
Also, fix some other typos while we are here.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
bf533-stamp, bf538f-ezkit, and cm-bf548 are very space limited.
This was introduced by:
6e0d26c050 (net: Handle ethaddr changes as an env callback)
by enabling CONFIG_REGEX, which is too big for these boards.
This patch disables CONFIG_REGEX at the expense of working with more
than the first ethaddr.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Instead of selecting REGEX when NET is enabled, make it the default, but
allow boards that are tiny to disable it and lose functionality on all
but the first Ethernet adapter.
cm-bf548, bf538f-ezkit, and bf533-stamp need this. None appear to have
more than one Ethernet interface.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
commit f566c99 "net: Update hardware MAC address if it changes in env"
removes writing MAC address to designware controller after soft reset.
This makes designware ethernet port fail to work. Actually the MAC
address should always be programmed after soft reset.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
sun8i-a33-ippo-q8h-v1.2-lcd1024x600.dts has been merged into the upstream
Linux kernel as sun8i-a33-ippo-q8h-v1.2.dts, adjust u-boot to follow.
Note we've never shipped a final u-boot version with the old name, so this
is safe todo.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
we currently use in-development IODelay values for DRA72x which are
proposed in the data sheet, however, DRA72x EVM uses DP83865 ethernet
Phy over RGMII. The PHY characteristics and routing choices made on
the EVM, make the current iodelay values fail ethernet communication.
Instead, we need to choose custom values for DRA72x-evm specifically
designed for the PHY and routing on the platform for ethernet to
function.
Cc: Nishanth Menon <nm@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Tested-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
We have not supported the private library for ARM 64bit.
Prohibit ARM64 boards from enabling it until we make things ready.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
am43xx_evm_ethboot/usbhost_boot_defconfig entries are
missing in MAINTAINER file. Adding entries for them.
Reported-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
This removes the following two warnings from buildman:
WARNING: no status info for 'cairo'
WARNING: no maintainers for 'cairo'
Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
The root cause of this problem should now be fixed.
This reverts commit a6a4c542d3.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Pavel Machek <pavel@denx.de>
Tested-by: Pavel Machek <pavel@denx.de>
When CONFIG_SYS_THUMB_BUILD is defined these functions may be called from
Thumb code. Add the required ENTRY and ENDPROC bracketing so that BLX is
used to call these ARM functions, instead of plain BL, which will fail.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Pavel Machek <pavel@denx.de>
The LPC32XX GPIO driver platdata currently contains GPIO state information,
which should go into priv_data. Thus rename lpc32xx_gpio_platdata to
lpc32xx_gpio_priv and convert to use dev_get_priv() instead.
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Tested-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
This patch uses generic 'load' command instead of 'fatload' for 'loadbootscript', 'loadimage' and 'loadfdt' for mx53loco board.
This allows to use EXT partition instead of FAT, while keeping FAT compatibility.
Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr>
Cc: Jason Liu <r64343@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Jason Liu <r64343@freescale.com>
Sinlinx SinA33 is a core/daughter board SDK kit from Sinlinx. It has
the A33 SoC, USB host, USB OTG, audio input/output, LCD, camera, SDIO
and GPIO headers.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Copy over all the latest dts changes from mripard/sunxi/dt-for-4.2.
This adds a dts file for Sinlinx SinA33 dev board, and the required
changes in the .dtsi files.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The A33 adds a pinmux function for UART0 in the PB pin group.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The original code was configuring the external pins after enabling
the R_PIO clock, which meant the configuration never made it to
the pin controller the first time in SPL.
Why this was working before is uncertain. Maybe the state was left
from a previous boot sequence, or RSB just happened to be the default
configuration. However with some A33 chips, SPL failed to configure
the PMIC. This was seen by me and Maxime on the Sinlinx SinA33 dev
board.
Reordering the calls fixed this.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Tested-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Commit 487b327 ("sunxi: GPIO pin mux hardware-feature-specific function
index defines") renamed all GPIO index defines, but missed the PORT F
UART0 setup functions.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
This patch adds the device tree binding doc for the cadence qspi controller &
also removes the not needed properties from the stv0991 device tree.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Jagannadh Teki <jteki@openedev.com>
This patch makes the code compatible with FIFO depths other than 4
bytes. It also simplify read/write FIFO loops.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Jagannadh Teki <jteki@openedev.com>
sram size could be different on different socs, e.g. on stv0991 it is 256 while
on altera platform it is 128. It is better to receive it from device tree.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Jagannadh Teki <jteki@openedev.com>
There is no need to re-configure sram partition for every read/write for
better full use of sram for read or write. This patch divides the half
sram for read & half for write once at initialization.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Jagannadh Teki <jteki@openedev.com>
This patch add the device tree entry for qspi controller & spi flash
memory.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Jagannadh Teki <jteki@openedev.com>
This patch does all the board configurations required to use the qspi
controller & attached spi flash memory.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Jagannadh Teki <jteki@openedev.com>
stv0991 has cadence qspi controller for flash interfacing, this
patch configures the device pads & clock for the controller.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Jagannadh Teki <jteki@openedev.com>
CONFIG_OF_SEPARATE is default define with CONFIG_OF_CONTROL, removing
this define from the board file to avoid multiple definition warning.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Jagannadh Teki <jteki@openedev.com>
Increase console IO buffer size to 1024 from the previous value of 256.
The previous value was too short for editing environment variables like
ubiboot from the console.
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
DM supported spi drivers are enbled only when DM_SPI enabled,
so added DM_SPI if condition in Kconfig to show thoese only
when it enabled.
Also re-order the config items as incresing alphabetic order.
Signed-off-by: Jagan Teki <jteki@openedev.com>
The current GPL only licensing on the device trees makes it very
impractical for other software components licensed under another
license.
To make it easier to reuse them, the device trees for UniPhier
SoCs and boards have already been dual-licensed in Linux.
Follow this trend in U-boot too.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This makes code diff much easier.
Device trees describe hardware attributes, which are independent
of software architecture. It generally makes sense to synchronize
them beyond software projects.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
There is no good reason to use a particular key to stop autobooting.
The default allows us to stop the autoboot with any key input.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Added SPI_FLASH_DATAFLASH entry on Kconfig with help description.
data flash driver comes with good decription, hence moved the
same on to kconfig help decription.
Signed-off-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Haikun Wang <haikun.wang@freescale.com>
Rename CONFIG_SF_DATAFLASH into CONFIG_SPI_FLASH_DATAFLASH
as it follows the naming convention same as remaining configs.
Signed-off-by: Jagan Teki <jteki@openedev.com>
This patch includes asm/io.h for readl and writel calls.
build errors:
drivers/spi/xilinx_spi.c: In function 'xilinx_spi_probe':
drivers/spi/xilinx_spi.c:119:2: warning: implicit declaration of function 'writel' [-Wimplicit-function-declaration]
drivers/spi/xilinx_spi.c: In function 'xilinx_spi_xfer':
drivers/spi/xilinx_spi.c:193:2: warning: implicit declaration of function 'readl' [-Wimplicit-function-declaration]
Signed-off-by: Jagan Teki <jteki@openedev.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Now zynq spi driver platform data is controlled by devicetree,
enable the status by saying "okay" on respective board dts to use
the devicetree generated platdata.
Ex:
&spi1 {
status = "okay";
};
Signed-off-by: Jagan Teki <jteki@openedev.com>
Acked-by: Simon Glass <sjg@chromium.org>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Tested-by: Jagan Teki <jteki@openedev.com>
This converts the zynq spi driver to use the driver model.
Minimal functional changes like using meaningful name on
structure members wrt mainlined dm spi drivers.
- input_hz -> frequency
- req_hz -> freq
- base -> regs
Signed-off-by: Jagan Teki <jteki@openedev.com>
Acked-by: Simon Glass <sjg@chromium.org>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Tested-by: Jagan Teki <jteki@openedev.com>
Move the header code into driver for more readable and
easy to access it.
Signed-off-by: Jagan Teki <jteki@openedev.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Zap oc_tiny_spi driver since the boards used this driver
is no longer been active.
Signed-off-by: Jagan Teki <jteki@openedev.com>
Cc: Thomas Chou <thomas@wytron.com.tw>
Zap andes_spi driver since the boards used this driver
is no longer been active.
Signed-off-by: Jagan Teki <jteki@openedev.com>
Cc: Macpaul Lin <macpaul@andestech.com>
Looks like I forgot to add myself as a maintainer for AXS103 defconfig.
Fixing this now.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Tom Rini <trini@konsulko.com>
[1] Align cache management functions to those in Linux kernel. I.e.:
a) Use the same functions for all cache ops (D$ Inv/Flush)
b) Split cache ops in 3 sub-functions: "before", "lineloop" and
"after". That way we may re-use "before" and "after" functions for
region and full cache ops.
[2] Implement full-functional L2 (SLC) management. Before SLC was
simply disabled early on boot. It's also possible to enable or disable
L2 cache from config utility.
[3] Disable/enable corresponding caches early on boot. So if U-Boot is
configured to use caches they will be used at all times (this is useful
in partucular for speed-up of relocation).
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
With new SMP-enabled CPUs with ARC HS38 cores and corresponding support
in Linux kernel it's required to add basic SMP support in U-Boot.
Currently we assume the one and only core starts execution after
power-on. So most of things in U-Boot is handled in UP mode.
But when U-Boot is used for loading and starting Linux kernel right
before jumping to kernel's entry point U-Boot:
[1] Sets all slave cores to jump to the same address [kernel's entry
point]
[2] Really starts all slav cores
In ARC's implemetation of SMP in Linux kernel all cores are supposed to
run the same start-up code. But only core with ID 0 (master core)
processes further while others are looping waiting for master core to
complete some initialization.
That means it's safe to un-pause slave cores and let them execute kernel
- they will wait for master anyway.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Vineet Gupta <vgupta@synopsys.com>
If flash pointer is used free it, before probing a new
flash and storing it in flash.
Signed-off-by: Heiko Schocher <hs@denx.de>
Tested-by: Jagannadh Teki <jteki@openedev.com>
Reviewed-by: Jagannadh Teki <jteki@openedev.com>
With this patch, it is possible to get the offset and size information
from the mtdpartiton setting in "mtdparts", similiar to the
"nand" commandos.
=> sf
sf - SPI flash sub-system
Usage:
sf probe [[bus:]cs] [hz] [mode] - init flash device on given SPI bus
and chip select
sf read addr offset|partition len - read `len' bytes starting at
`offset' to memory at `addr'
sf write addr offset|partition len - write `len' bytes from memory
at `addr' to flash at `offset'
sf erase offset|partition [+]len - erase `len' bytes from `offset'
`+len' round up `len' to block size
sf update addr offset|partition len - erase and write `len' bytes from memory
at `addr' to flash at `offset'
=>
for example "env" is defined in mtdparts:
=> sf read 13000000 env
device 0 offset 0xd0000, size 0x10000
SF: 65536 bytes @ 0xd0000 Read: OK
zynq-uboot> mtdparts add nor0 0x10000@0x0 env
zynq-uboot> sf erase env 0x10000
SF: 65536 bytes @ 0x0 Erased: OK
zynq-uboot> sf write 0x100 env
device 0 offset 0x0, size 0x10000
SF: 65536 bytes @ 0x0 Written: OK
zynq-uboot> sf read 0x40000 env
device 0 offset 0x0, size 0x10000
SF: 65536 bytes @ 0x0 Read: OK
Signed-off-by: Heiko Schocher <hs@denx.de>
Tested-by: Jagannadh Teki <jteki@openedev.com>
Reviewed-by: Jagannadh Teki <jteki@openedev.com>
Move common functions from cmd_nand.c (for calculating offset
and size from cmdline paramter) to common place, so they could
used from other commands which use mtd partitions.
For onenand the arg_off_size() is left in common/cmd_onenand.c.
It should use now the common arg_off() function, but as I could
not test onenand I let it there ...
Signed-off-by: Heiko Schocher <hs@denx.de>
Acked-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: Jagannadh Teki <jteki@openedev.com>
Add MTD layer driver for spi, original patch from:
http://git.denx.de/?p=u-boot/u-boot-mips.git;a=commitdiff;h=bb246819cdc90493dd7089eaa51b9e639765cced
Changes from Heiko Schocher against this patch:
- Remove compile error if not defining CONFIG_SPI_FLASH_MTD:
LD drivers/mtd/spi/built-in.o
drivers/mtd/spi/sf_probe.o: In function `spi_flash_mtd_unregister':
/home/hs/abb/imx6/u-boot/drivers/mtd/spi/sf_internal.h:168: multiple definition of `spi_flash_mtd_unregister'
drivers/mtd/spi/sf_params.o:/home/hs/abb/imx6/u-boot/drivers/mtd/spi/sf_internal.h:168: first defined here
drivers/mtd/spi/sf_ops.o: In function `spi_flash_mtd_unregister':
/home/hs/abb/imx6/u-boot/drivers/mtd/spi/sf_internal.h:168: multiple definition of `spi_flash_mtd_unregister'
drivers/mtd/spi/sf_params.o:/home/hs/abb/imx6/u-boot/drivers/mtd/spi/sf_internal.h:168: first defined here
make[1]: *** [drivers/mtd/spi/built-in.o] Fehler 1
make: *** [drivers/mtd/spi] Fehler 2
- Add a README entry.
- Add correct writebufsize, to fit with Linux v3.14
MTD, UBI/UBIFS sync.
Note (From Jagan): For testing raw mtd parition erase/read/write operations
using cmd_sf, sf_mtd should be required to register the spi flash device to
MTD layer but the sf_mtd_info ops were not required until and unless if we
use any flash filesystem layer say for example UBI. Due to this the foot-print
got increased ~290bytes in non-UBI case here that should be acceptible.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Heiko Schocher <hs@denx.de>
Tested-by: Jagannadh Teki <jteki@openedev.com>
Reviewed-by: Jagannadh Teki <jteki@openedev.com>
Enable Driver Model SPI for ls1021aqds board.
DSPI and QSPI is enabled only when boot from QSPI.
DSPI and QSPI are compatible under Driver Model SPI.
Signed-off-by: Haikun Wang <Haikun.Wang@freescale.com>
Tested-by: Haikun Wang <haikun.wang@freescale.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
The type of DSPI flash on ls1021aqds is AT45DB021, it has specail
commands and page-size.
Use the special spi flash driver instead of "spi_flash_std" driver.
Signed-off-by: Haikun Wang <haikun.wang@freescale.com>
Tested-by: Haikun Wang <haikun.wang@freescale.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Atmel DataFlash chips have commands different from common spi
flash commands.
Atmel DataFlash also have special page-size.
This driver add support for accessing Atmel DataFlash.
It is based on the Driver Model.
Example:
=> sf probe 1:0
SPI DataFlash: Detected AT45DB021B with page size 264 Bytes, erase size 264 Bytes, total 264 KiB, revision d
=> sf erase 0 42000
SF: 270336 bytes @ 0x0 Erased: OK
=> mw.l 82000000 45444342 20000
=> sf write 82000000 0 42000
SF: 270336 bytes @ 0x0 Written: OK
=> sf read 83000000 0 42000
SF: 270336 bytes @ 0x0 Read: OK
=> cmp.b 82000000 83000000 42000
Total of 270336 byte(s) were the same
Signed-off-by: Haikun Wang <haikun.wang@freescale.com>
Tested-by: Haikun Wang <haikun.wang@freescale.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Chakra Divi <cdivi@openedev.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
By default on this platform, u-boot loads data into high memory
in the range of 0x7Fxxxxxx, which generates a data abort when the
kernel tries to read it. Config the u-boot environment to load
the device tree and initrd image into lower memory to make them
accessible to the kernel.
Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Acked-by: Stefan Roese <sr@denx.de>
This reverts commit f76eba38b3.
This patch did not have a full and proper copyright/S-o-b chain.
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Conflicts:
include/configs/sun6i.h
include/configs/sun8i.h
These options were merged into mx6_common and were seemingly missed
in mx6cuboxi so drop the duplicates
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Add a new revision CHIP_REV_2_0.
Introudce macro is_mx6dqp, dqp means Dual/Quad Plus.
Since Dual/Quad Plus use same cpu type with Dual/Quad, but different
revision(Major Lower), we use this macro for Dual/Quad Plus.
Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
The DIGPROG register map:
23 ------- 16 | 15 ------ 8 | 7 --- 0 |
Major upper | Major Lower | Minor |
We also need to account for Major Lower.
Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
is_soc_rev should return a bool value, so use "==", but not "-",
change (is_soc_rev(CHIP_REV_1_0) > 0) to (soc_rev() > CHIP_REV_1_0).
This patch also add space between "&" for cpu_type(rev) macro.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Now that we have the Kconfig based CPU type selection,
use this to fill the IMX_CONFIG automatically
Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com>
This is the first patch to remove the
CONFIG_SYS_EXTRA_OPTIONS.
This patch implements CPU type selection from Kconfig.
Further Kconfig stuff is added later.
Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com>
This sets the default commands Kconfig to match
include/config_cmd_default.h commands in the common/Kconfig and removes
them from include/configs.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
[trini: rastaban, am43xx_evm_usbhost_boot, am43xx_evm_ethboot updates]
Signed-off-by: Tom Rini <trini@konsulko.com>
Some archs/boards specify their own default by pre-defining the config
which causes the Kconfig system to mix up the order of the configs in
the defconfigs... This will cause merge pain if allowed to proliferate.
Remove the configs that behave this way from the archs.
A few configs still remain, but that is because they only exist as
defaults and do not have a proper Kconfig entry. Those appear to be:
SPIFLASH
DISPLAY_BOARDINFO
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
[trini: rastaban, am43xx_evm_usbhost_boot, am43xx_evm_ethboot updates,
drop DM_USB from MSI_Primo81 as USB_MUSB_SUNXI isn't converted yet to DM]
Signed-off-by: Tom Rini <trini@konsulko.com>
Boards using link-local need lib rand.
When link-local is moved to Kconfig, this dependency will be described
there.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
This command needs to exist in the Kconfig so that it can be moved from
the config_cmd_default.h.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Patch 33fe2fb8df titled
"mmc: bcm283x: Remove get_timer_us() from mmc driver"
incorrectly replaced ad-hoc get_timer_us() function
with a plain get_timer(). The get_timer() operates in
mSec units instead of uSec though, which caused very
slow operation of the driver.
Restore the original behavior of the driver, but avoid
get_timer_us() and use timer_get_us() instead. The later
is part of the standard API.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Jakub Kiciński <moorray3@wp.pl>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Jakub Kicinski <kubakici@wp.pl>
rastaban is a draco version with more flash, more RAM
and faster CPU. Number of partitions is the same but
rootfs partition is different.
Signed-off-by: Samuel Egli <samuel.egli@siemens.com>
Acked-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Unlike most configuration options defining this actually disables
support for a feature (parallel flash). Eventually the logic behind this
should probably be flipped so that '#ifndef CONFIG_SYS_NO_FLASH' becomes
'#ifdef CONFIG_HAS_PARALLEL_FLASH' but for now lets document the
existing behaviour.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
BeagleBoard-X15 uses a vtt regulator for DDR3 termination
and this is controlled by gpio7_11. Configuring gpio7_11.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
add cpsw ethernet boot mode support to download spl and
u-boot.img via tftp protocol. Also adding a seperate config
for ethernet boot mode as the default build falcon mode and
environment on MMC is defined for ethernet boot mode
environment should be set to nowhere.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
While booting via usb host mode, ROM uses DMA to copy MLO over USB so
ARM internal RAM cannot be used. Adding USB host boot support by
introducing new config target which sets SPL_TEXT_BASE to OCMC ram.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
With 1.2 silicon this is now the documented starting usable point for
downloading images to (and corrects a problem with peripheral booting
with prior silicon). Prior silicon is OK using this address as well.
Signed-off-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
DRA7/AM57xx devices can be operated in many different configurations.
When the SoC is supposed to support a configuration where low power mode
state may involve the SoC completely powered off and DDR is in self
refresh, SoC EMIF controller should not be the master of the reset
signal and an external entity might be in control of things.
The default configuration of Linux on TI evms involve not powering off
the voltage rails (due to various reasons including reliability concerns)
and must not allow DDR reset to be controlled by EMIF. On platforms
where external entity might control the reset signal, this configuration
will be a "dont care".
Fixes: 536d874708 ("ARM: DRA7: Update DDR IO registers")
Tested-by: Keerthy <j-keerthy@ti.com>
Acked-by: Brad Griffis <bgriffis@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Tested on Pandaboard (rev. A3) and Beagleboard xM (rev. B).
Compilation tested on TI armv7 boards and OMAP boards from other vendors.
Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
updates for the siemens am335x based boards:
- draco: add delay for DDR3 configuration
- change MTD partition layout and add a possibility
to redefine MTD layout in board header.
- move ubi support to common header file
- draco: improve dtb naming
- draco: set CONFIG_SYS_CBSIZE to 1024
- add generic env based led
Leds can now be defined in Environment
- add generic env based dfu button
Which gpio is used for the dfu button can be defined
through the Environment
- set MACH_TYPE only if defined
- draco: increase CPU freq to 300MHz
- Add time command to siemens am33xx boards
- DDR3: increase default tRFC
- draco: enable pullup for DFU and ERST pin
- change print format DDR3
Signed-off-by: Samuel Egli <samuel.egli@siemens.com>
Acked-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Heiko Schocher <hs@denx.de>
This introduces the part start and part size sub-commands. The purpose of these
is to store the start block and size of a partition in a variable, given the
device and partition number.
This allows reading raw data that fits a single partition more easily.
For instance, this could be used to figure out the start block and size of a
kernel partition when a partition table is present, given the partition number.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Acked-by: Stephen Warren <swarren@nvidia.com>
[trini: Change "%lx" to LBAF]
Signed-off-by: Tom Rini <trini@konsulko.com>
The get_max_arm_speed() and get_max_dev_speed() used wrong register
fields to get the maximum speeds. This commit fixes the bug.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
When we're polling and thus handling key-repeat in software, make sure
to disable idle reports, some keyboards may have these enabled by default
messing up our software keyrepeat.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Without this we loose every other interrupt packet. We never noticed this
because with keyboards the packets which we were loosing would normally
be key release packets.
But now that we do keyrepeat in software instead of relying on the hid
idle functionality, missing a release will result in key repeat triggering.
This commit fixes this.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
There is no harm in declaring the function prototypes even if nothing
implements them, and when CONFIG_DM_USB=y the various usb functions are
available regardless of any controller drivers being enabled.
This fixes compile warnings due to missing prototypes on ARCHs where
the ARCH Kconfig always enables CONFIG_DM_USB and various usb drivers.
One could argue that in the case of no controllers CONFIG_DM_USB should not
be set, but this problem is typically seen during bringup of boards which
do actually have usb controllers.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
With the change to make sure that CONFIG_CMD_NET is enabled this board
no longer fits into the linker script:
powerpc-linux-ld.bfd: section .resetvec loaded at [fffffffc,ffffffff] overlaps section .u_boot_list loaded at [ffffff58,00000723]
powerpc-linux-ld.bfd: u-boot: section .resetvec lma 0xfffffffc adjusted to 0x724
powerpc-linux-ld.bfd: u-boot: section `.resetvec' can't be allocated in segment 0
LOAD: .data.init .text .rodata .reloc .data .u_boot_list .resetvec
powerpc-linux-ld.bfd: final link failed: File truncated
Drop CONFIG_SYS_LONGHELP to free up space.
Cc: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
This allows using only one of either raw or fs mode for SPL mmc boot, without
the need to have provisions for the other. In particular, a device may have
U-Boot installed on a file system on the mmc, without ever needing to read
U-Boot from raw memory. Thus, there is no reason to provide a sector or
partition for raw mode. This allows this behaviour and still provides a robust
fallback mechanism in case provisions for both modes are defined.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
When building tools-only (or env) we need to be sure that we do use
<linux/kconfig.h> and do not use <generated/autoconf.h>. This will fix
problems such as running 'make defconfig' or 'make sandbox_config' and
then 'make tools-only'.
Based on the responses below to the thread add linux/kconfig.h higher in
the includes and drop the now unneeded autoconf.h lower down to ensure
the default environment is included correctly
http://lists.denx.de/pipermail/u-boot/2015-June/216849.html
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
since we have now various processor-speeds it isn't useful anymore to
preinitialize kernels-delay loop.
Rather we want the kernel to calibrate it on every boot.
This wastes around 80ms boottime but is compatible to all CPU-speeds.
Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>
in future we support yet another b&r am335x based board, where Timer 5 is
wired to backlight-driver.
So we introduce a new driver-type '2' to setup timer5 instead timer6.
Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Reviewed-by: Simon Glass <sjg@chromium.org>
Currently there is no default value for NETARGS if CONFIG_CMD_NET=y isn't set.
This results in build errors which was first discovered when trying to run
make env.
By defining a blank NETARGS these errors can be avoided.
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Tested-by: Maxin B. John <maxin.john@enea.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
The MSI Primo 81 is an Allwinner A31s-based tablet on which the
OTG port is the only accessible USB interface. The existing
defconfig had VGA console on the LCD enabled, but was missing
keyboard support because the prerequisites for that (sunxi MUSB
support and AXP221 GPIO support) had not been available before.
All previously missing dependencies are available now, so this
patch enables keyboard support and its prerequisites in the
defconfig.
Signed-off-by: Karsten Merker <merker@debian.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Currently on sun6i after a "reset" the prompt returns and the user can
even type stuff until the watchdog triggers and does the actual reset.
This is somewhat unexpected behavior for the "reset" command, this
commit adds an endless loop to wait for the watchdog to trigger so that
we do not return to the prompt.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Remove the unused sunxi_musb_exit method, there is no code in u-boot
calling the exit method, and our implementation was broken as it did
not disable the clocks and asserted reset.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Fully resetting the controller is a too big hammer, and the musb_core will
then afterwards fail to communicate with any endpoints other then 0 as
too much state was cleared.
Instead report vbus low for 200ms which will effectively end the current
session without needing to do a full reset.
This fixes usb mass-storage devices no longer working after a "usb reset"
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
In the cases where we make use of environment in SPL we do not need
these defaults compiled in and available. These are taking up space
that in some cases now prevent linking, so drop.
Signed-off-by: Tom Rini <trini@konsulko.com>
Vision Systems's Baltos is based on AM335x SoC
from Texas Instruments. This patch adds support
such Industrial PCs in mainline u-boot.
[ balbi@ti.com: updated original patch to current u-boot ]
Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
Unlike OMAP5, EMIF PHY used in DRA7 will be left in unknown state after
warm reset, emif needs to be configured to bring it back to a known
state. So configure EMIF during warm reset.
Reported-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Now all the AVR32 boards have been converted into Generic Board.
Select it in Kconfig and clean up defines in header files.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
The recent changes for hw leveling on am33xx were not intended for
DDR2 boards, only DDR3. Update emif_sdram_type to take a sdram_config
value to check against. This lets us pass in the value we would use to
configure, when we have not yet configured the board yet. In other cases
update the call to be as functional as before and check an already
programmed value in.
Tested-by: Yan Liu <yan-liu@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
On AM57xx evm I2C5 is used to detect the LCD board by reading the
EEPROM present on the bus.
Enable i2c5 clocks to help that.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Use the correct partition names from with the Device Tree blob
and the kernel is picked up. Also use partition name instead of
number for the root filesystem in the kernel boot arguments.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
We almost always use UBIFS for user accessible NAND file systems and
the UBIFS file system might contain more than one volume within the
single NAND partition. The last NAND partition is therefore more
appropriately named as "NAND.file-system" instead of "NAND.rootfs"
The Linux kernel (as of v3.16) also uses "NAND.file-system" to name the
last NAND partition. This patch makes the partition name consistent
between u-boot and the kernel.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
The Calxeda highbank SOC needs a custom sequence to bring up SATA links,
so override ahci_link_up with custom function to handle combophy setup.
Signed-off-by: Mark Langsdorf <mark.langsdorf@gmail.com>
Signed-off-by: Richard Gibbs
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Andre Przywara <osp@andrep.de>
Hummingboard dual-lite is picking the incorrect calibration structure.
Fix it so that it can boot.
While at it, also fix p1_mpdgctrl1 register to match Solid-run's
setting.
Reported-by: Andrei Gherzan <andrei@gherzan.ro>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Tested-by: Andrei Gherzan <andrei@gherzan.ro>
To support the Armada 38x, new values for the request-delay and the
response-timeout are needed. As the values already implemented in
this tool (for Kirkwood and Armada XP) don't seem to work here.
To make this more flexible, lets add make those 2 parameters
configurable via the cmdline. Here the new parameters:
-q <req-delay>: use specific request-delay
-s <resp-timeo>: use specific response-timeout
For the Marvell DB-88F6820 these values are known to work:
One board:
-q 2 -s 1
2nd board:
-q 5 -s 5
So this seems to be even board specific. But with this patch now
those values can be specified and tested via the cmdline.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Kevin Smith <kevin.smith@elecsyscorp.com>
Cc: Dirk Eibach <dirk.eibach@gdsys.cc>
Cc: Luka Perkov <luka.perkov@sartura.hr>
SMP-enabled Linux kernels read the CBAR register in CP15 to find
the address of the SCU registers. After remapping internal
registers, also update the CBAR so the kernel can find them.
Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Acked-by: Stefan Roese <sr@denx.de>
L2 cache may still be enabled by the BootROM. We need to first disable
it before enabling d-cache support.
Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Kevin Smith <kevin.smith@elecsyscorp.com>
If defined, the macro CONFIG_SYS_SPI_U_BOOT_OFFS allows a board
to specify the offset of the payload image into the kwb image
file. This value was being used to locate the image, but was not
used in the "header size" field of the main header. Move the
use of this macro into the function that returns the header size
so that the same value is used in all places.
Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Tested-by: Stefan Roese <sr@denx.de>
The AHCI driver currently waits 5s before timing out when sending a
data command to a drive. Some drives take upwards of 8s to respond to
the initial data command while they're spinning up. Increase the
data io timeout to 10s so that those drives can be found on initial
scsi scan.
Signed-off-by: Mark Langsdorf <mark.langsdorf@gmail.com>
Signed-off-by: Andre Przywara <osp@andrep.de>
Enable full 48-bit LBA48 data reads by passing the upper word of the
LBA block pointer in bytes 9 and 10 of the FIS.
This allows uboot to load data from any arbitrary sector on a drive
with 2 or more TB of available data connected to an AHCI controller.
Signed-off-by: Mark Langsdorf <mark.langsdorf@gmail.com>
Signed-off-by: Andre Przywara <osp@andrep.de>
[trini: Make use of CONFIG_SYS_64BIT_LBA in a few places to drop
warnings on platforms that don't enable that feature ]
Signed-off-by: Tom Rini <trini@konsulko.com>
The Calxeda Midway part has A15 cores, which do not have the Highbank
A9's SCU used there for resetting the chip.
Add code to distinguish between the A9 and the A15 and invoke the
appropriate register writes to support the newer part.
Andre: rework detection of Highbank vs. Midway
Rob: fix Andre's reworked detection
Signed-off-by: Mark Langsdorf <mark.langsdorf@gmail.com>
Signed-off-by: Andre Przywara <osp@andrep.de>
Signed-off-by: Rob Herring <robh@kernel.org>
Now all manual mode configurations are done as part of
IO delay recalibration sequence, remove the hack done for
CPSW.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Enabling IO delay recalibration sequence for DRA7 EVM.
UART and I2C are configured before IO delay recalibration sequence
as these are used earlier and safe to use.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
In addition to the regular mux configuration, certain pins of DRA7
require to have "manual mode" also programmed, when predefined
delay characteristics cannot be used for the interface.
struct iodelay_cfg_entry is introduced for populating
manual mode IO timings.
For configuring manual mode, along with the normal pad
configuration do the following steps:
- Select MODESELECT field of each assocaited PAD.
CTRL_CORE_PAD_XXX[8]:MODESELECT = 1(Enable MANUAL_MODE macro along with mux)
- Populate A_DELAY, G_DELAY values that are specified in DATA MANUAL.
And pass the offset of the CFG_XXX register in iodelay_cfg_entry.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
On DRA7, in addition to the regular muxing of pins, an additional
hardware module called IODelay which is also expected to be
configured. This "IODelay" module has it's own register space that is
independent of the control module.
It is advocated strongly in TI's official documentation considering
the existing design of the DRA7 family of processors during mux or
IODelay recalibration, there is a potential for a significant glitch
which may cause functional impairment to certain hardware. It is
hence recommended to do muxing as part of IOdelay recalibration.
IODELAY recalibration sequence:
- Complete AVS voltage change on VDD_CORE_L
- Unlock IODLAY config registers.
- Perform IO delay calibration with predefined values.
- Isolate all the IOs
- Update the delay mechanism for each IO with new calibrated values.
- Configure PAD configuration registers
- De-isolate all the IOs.
- Relock IODELAY config registers.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
In addition to the regular mux configuration, certain pins of DRA7
require to have "virtual mode" also programmed.
This allows for predefined delay characteristics to be used by the SoC
to meet timing characterstics needed for the interface.
Provide easy to use macro to do the same.
For configuring virtual mode, along with normal pad configuration add
the following two steps:
- Select MODESELECT field of each assocaited PAD.
CTRL_CORE_PAD_XXX[8]:MODESELECT = 1
- DELAYMODE filed should be configured with value given in DATA Manual.
CTRL_CORE_PAD_XXX[7:4]:DELAYMODE =[0-15] (as given in DATA manual).
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Adopting the pinctrl register definitions from Linux kernel
to be consistent.
Old definitions will be removed once all the pinctrl data
is adapted to new definitions.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
do_set_mux32() is redefined in dra7xx and beagle_x15 boards.
IO delay recalibration sequence also needs this.
Making it generic to avoid duplication.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
When DLL_CALIB_INTERVAL is set, an extra delay is added
which is not required and it consumes EMIF bandwidth.
So making the DLL_CALIB_CTRL[8:0]DLL_CALIB_INTERVAL bits to 0.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
DDRIO_2 and LPDDR2CH1_1 registers are not present
for DRA7. So not configuring these registers for DRA7xx
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
A generic is_dra72x cpu check is useful for grouping
all the revisions under that. This is used in the
subsequent patches.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Updating EMIF registers to enable HW leveling
on DRA72-evm.
Also updating the timing registers.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
DRA7 EMIF supports Full leveling for DDR3.
Adding support for the Full leveling sequence.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
This commit imports some updates of kconfiglib.py from
https://github.com/ulfalizer/Kconfiglib
- Warn about and ignore the "allnoconfig_y" Kconfig option
- Statements in choices inherit menu/if deps
- Add Symbol.is_allnoconfig_y()
- Hint that modules are still supported despite warnings.
- Add warning related to get_defconfig_filename().
- Fix typo in docs.
- Allow digits in $-references to symbols.
Signed-off-by: Ulf Magnusson <ulfalizer@gmail.com>
Signed-off-by: Philip Craig <philipjcraig@gmail.com>
Signed-off-by: Jakub Sitnicki <jsitnicki@gmail.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Commit e11c6c279d broke calculating lr register
in function save_boot_params() and caused U-Boot to crash at early boot time
on Nokia N900 board.
This patch fix calculating return address in lr register and make Nokia N900
board bootable again. Patch was tested in qemu and also on real N900 HW.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Pali Rohár <pali.rohar@gmail.com>
sometimes it is usefull to know if board-detection has
written the correct value into gd->board_type.
For this we add some output to the bdinfo command.
Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Commit 9ba9e85f3f (net: Fix NET_RANDOM_ETHADDR dependencies)
accidentally dropped CONFIG_LIB_RAND defines for 14 Blackfin boards.
Prior to that commit, those boards defined CONFIG_LIB_RAND, but not
CONFIG_NET_RANDOM_ETHADDR. So, commit 9ba9e85f3f should not have
touched them, but in fact it ripped CONFIG_LIB_RAND off from all the
header files, which caused undefined reference to srand and rand.
CONFIG_LIB_RAND=y must be revived for such boards.
BTW, this commit indeed makes it better, but even with this fix,
three boards (bf533-stamp, bf538f-ezkit, cm-bf548) still can not
build due to region 'ram' overflowed error. This was cause by
commit 6eed3786c6 (net: Move the CMD_NET config to defconfigs)
because CMD_NET selects NET, and NET selects REGEX. Eventually,
some boards were newly enabled with CONFIG_REGEX, increasing the
memory footprint. A patch is expected to fix the build error.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Some AVR32 boards were dropped by the following commits:
9eb45aabe0 (avr32: delete non generic board favr-32-ezkit)
e369307644 (avr32: delete non generic board hammerhead)
c62d2f8fc5 (avr32: delete non generic board mimc200)
e5354b8a9e (avr32: delete non generic board's atstk100{3, 4, 6})
Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Allow SPL to be built with this option so that we can support device tree
control. Disable the simple bus for now in SPL. It may be needed later.
Signed-off-by: Simon Glass <sjg@chromium.org>
This feature should be deprecated for new boards, and significantly adds
to SPL code size. Drop it. Instead, we can use stdout-path in the /chosen
node.
Signed-off-by: Simon Glass <sjg@chromium.org>
We plan to enable device tree in SPL by default. Before doing this,
explicitly disable it for all boards.
Signed-off-by: Simon Glass <sjg@chromium.org>
The 4KB padding doesn't seem necessary since we don't normally adjust the
control device tree file within U-Boot. Also drop the memory table space.
Signed-off-by: Simon Glass <sjg@chromium.org>
This option is used by some boards, so support it with driver model. This
is really ugly - we should rewrite this driver once all users are moved to
driver model.
Signed-off-by: Simon Glass <sjg@chromium.org>
For 16-bit-per-pixel displays it is useful to support 8 bit-per-pixel
images to reduce image size. Add support for this when drawing BMP images.
Signed-off-by: Simon Glass <sjg@chromium.org>
We try to avoid typedefs and these ones are easy enough to remove. Before
changing this header in the next patch, remove the typedefs.
Signed-off-by: Simon Glass <sjg@chromium.org>
Suggested-by: Joe Hershberger <joe.hershberger@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This function is used before jumping to U-Boot, but in that case we don't
always want to disable caches.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
For secure boot systems it is common to have a read-only U-Boot which starts
the machine and jumps to a read-write U-Boot for actual booting the OS. This
allows the read-write U-Boot to be upgraded without risk of permanently
bricking the machine. In the event that the read-write U-Boot is corrupted,
the read-only U-Boot can detect this with a checksum and boot into a
recovery flow.
To support this, add a way to detect when U-Boot is run from SPL as opposed
to some other method, such as booted directly (no SPL) or started from
another source (e.g. a primary U-Boot). This works by putting a special value
in r0.
For now we rely on board-specific code to actually check the register and
set a flag. At some point this could be generalised, perhaps by using a spare
register and passing a flag to _main and/or board_init_f().
This commit does not implement any feature, but merely provides the API for
boards to implement.
Signed-off-by: Simon Glass <sjg@chromium.org>
Somehow this change was dropped in the various merges. I noticed when I
came to turn off the non-driver-model support for Tegra. We need to make
this change (and deal with any problems) before going further.
Change-Id: Ib9389a0d41008014eb0df0df98c27be65bc79ce6
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Marek Vasut <marex@denx.de>
Add the legacy i2c_reg_read/write() functions to the compatibility layer
so that they can be used when CONFIG_DM_I2C_COMPAT is defined.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Due to absence of CONFIG_SYS_64BIT_LBA, u-boot-sunxi currently has
no support for the (GPT) partioning scheme of large disks > 2TB.
While the AHCI driver seems to handle this nicely, the problem is
that lbaint_t values get truncated to 32-bit.
This patch sets CONFIG_SYS_64BIT_LBA from sunxi_common.h for all
SoCs that support AHCI (CONFIG_SUNXI_AHCI).
Signed-off-by: Bernhard Nortmann <bernhard.nortmann@web.de>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
This fixes ethernet no longer working on boards which use a gpio to enable
the phy.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
This commit cleanup MAX77686 regulator node by:
- remove the sub-nodes of unconnected regulators
- remove the "regulator-compatible" properties of all regulators
This prevents printing init errors for the regulators,
with duplicated name strings.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
We need to match the device tree in the FIT with the U-Boot model so we
can automatically select the right device tree. Also adjust the load address
so that the device tree is not in the way when a zImage kernel tries to
extract itself.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
With the rename the MAINTAINER file was not updated. Fix it and the
'Chrombook' typo in Kconfig.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
We need to turn on all audio-related clocks for the Chrome OS kernel to
boot. Otherwise it will hang when trying to enable audio.
Also for Linux set up graphics driver video protection.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add a hook to allows boards to add their own init to board_init().
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
When setting up large environment variables we can exceed 16 arguemnts.
Increase this to avoid problems.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This is required in order to avoid instability when running from caches
after the kernel starts.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
A harmless but confusing warning is displayed when looking up the
DisplayPort PLL. Correct this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Use the oscillator as the source clock when we cannot achieve a low-enough
speed with the peripheral clock. This happens when we request 3MHz on a SPI
clock, for example.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Enable the EC and keyboard, using the SPI bus.
The EC driver requires a particular format and a deactivation delay. Also
U-Boot does not support interrupts.
For now, adjust the device tree to comply. At some point we should tidy
this up to support interrupts and make tegra and exynos use the same setup.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
At present the driver does not properly honour the requested SPI CS
deactivation delay since the SPI bus is changed in the claim_bus() method.
Everything the claim_bus() method does can be done when the device is probed
(setting the speed and mode) and at the start of a new transfer (where the
fifo_status is already cleared). So drop this method.
Also, until the delay is complete, we should not touch the bus, so make sure
that spi_cs_activate() is called before other things are done in the xfer()
method.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This requires a change to stdin to include the 'cros-ec-keyb' input device.
Put this in the common file, enabled by the relevant CONFIG.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Commit a380ce6e96 removed CONFIG_FAT_WRITE
from novena.h , so Novena lost ability to write FAT partitions. Add this
functionality back.
Signed-off-by: Marek Vasut <marex at denx.de>
Cc: Peter Robinson <pbrobinson at gmail.com>
Cc: Stefano Babic <sbabic at denx.de>
This patch adds the feature to only stop the autobooting, and therefor
boot into the U-Boot prompt, when the input string / password matches
a values that is encypted via a SHA256 hash and saved in the environment.
This feature is enabled by defined these config options:
CONFIG_AUTOBOOT_KEYED
CONFIG_AUTOBOOT_STOP_STR_SHA256
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
This patch moves the following config options to Kconfig:
CONFIG_AUTOBOOT_KEYED
CONFIG_AUTOBOOT_PROMPT
CONFIG_AUTOBOOT_DELAY_STR
CONFIG_AUTOBOOT_STOP_STR
AUTOBOOT_KEYED_CTRLC
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
[trini: Drop ip04 and pm9263 configs/ additions, those boards previously
set CONFIG_AUTOBOOT_PROMPT but never used it, re-run savedefconfig over
all boards that did change. Make digsy_mtc_* string include seconds to
match others and not warn. ]
Signed-off-by: Tom Rini <trini@konsulko.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
These defines for a 2nd autoboot stop and delay string are nearly unused. Only
sc3 defines CONFIG_AUTOBOOT_DELAY_STR2. And a patch to remove this most likely
unmaintained board is also posted to the list.
By removing these defines the code will become cleaner and moving the remaining
compile options to Kconfig will get easier.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Heiko Schocher <hs@denx.de>
I might have missed something, but I failed to use the escape char '\'
in strings. To pass a printf format string like "foo %d bar\n" via
Kconfig to the code.
Right now its not possible to use the escape character '\' in Kconfig
string values correctly to e.g. set this string value "test output\n".
The '\n' will be converted to 'n'.
The current implementation removes some of the '\' chars from the input
string in conf_set_sym_val(). Examples:
'\' -> ''
'\\' -> '\'
'\\\' -> '\'
'\\\\' -> '\\'
...
And then doubles the backslash chars in the output string in
sym_escape_string_value(). Example:
'\' -> '' -> ''
'\\' -> '\' -> '\\'
'\\\' -> '\' -> '\\'
'\\\\' -> '\\' -> '\\\\'
...
As you see in these examples, its impossible to generate a single '\'
charater in the output string as its needed for something like '\n'.
This patch now changes this behavior to not drop some backslashes in
conf_set_sym_val() and to not add new backslashes in the resulting
output string. Removing the function sym_escape_string_value()
completely as its not needed anymore.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
This commit adds example scripts of boot.scr:
- bootzimg.cmd - check if dtb exists and boot zImage
- autoboot.cmd - check which image exists: Image.itb, zImage or uImage
and optionally load fdt file for u/zImage
The blank spaces are added to improve readability and can be removed
before use mkimage.
Required U-Boot environment variables: $boardname, $fdtfile, $console,
$mmcbootdev, $mmcbootpart, $mmcrootdev, $mmcrootpart, $rootfstype.
Making boot.scr from file.cmd:
mkimage -C none -A arm -T script -d file.cmd boot.scr
The Odroid XU3 default environment is ready for those boot scripts and
the right script can be loaded by DFU.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
This patch enables all functions required to use DFU/THOR and UMS:
- DWC3: core, gadget, Samsung DWC3 PHY
- USB gadget: endpoint autoconf, downloader, DFU, THOR, UMS
The CONFIG_EXTRA_ENV_SETINGS from exynos5-common.h is redefined
and appended by dfu environment setting and some system settings.
The boot is still using $distro_boot as previous.
Signed-off-by: Inha Song <ideal.song@samsung.com>
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
This change decreases the interval of calls to:
- display busy indicator
- check ctrlc()
- check cable connection
By this change, breaking the UMS command is more easy on Odroid XU3.
Signed-off-by: Inha Song <ideal.song@samsung.com>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Marek Vasut <marex@denx.de>
This commit extends SMDK5420 board's file by adding functions:
- get_dfu_alt_system()
- get_dfu_alt_boot()
This allows setting the DFU environment by function set_dfu_alt_info()
from: board/samsung/common/misc.c
Signed-off-by: Inha Song <ideal.song@samsung.com>
Cc: Akshay Saraswat <akshay.s@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
This commit adds implementation of function calls:
- usb_gadget_handle_interrupts()
- board_usb_init()
Which allow enable USB DWC3 gadget for this board.
Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Inha Song <ideal.song@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
New files, namely samsung_usb_phy.c and samsung-usb-phy-uboot.h have
been added to u-boot to provide proper PHY handling at Exynos5 SoCs.
This code is used thereafter in the board_usb_init() call.
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Marek Vasut <marex@denx.de>
After that change it would be possible to call samsung_get_base_usb3_phy()
function to get proper base address
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Add IOMUX for the pad used as USB pen. This needs to be driven low for
the Iris and Viola boards where it is pulled up high by default. This is
required for the USB host functionality to work on these boards. Use the
board specific weak initialisation function, to drive the pin low which
would be called on "usb start".
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Add a weak function board_ehci_hcd_init which can be used by the board
file for board specific initialisation.
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Most of the drivers available for Vybrid are not yet converted
to OF model to use device tree model, only few drivers
like SPI and GPIO drivers use device trees.
Add separate defconfig for who needs to use device tree model.
Later this can be integrated to single defconfig.
Acked-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Add device tree files for Freescale Vybrid platform and
Toradex Colibri VF50, VF61 modules.
Device tree files are taken from upstream Kernel.
Removed the stuff which are not used/supported yet in U-Boot.
Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Inorder to use the pins as GPIO, apart from setting the alt-function,
pinmuxing need to be done, this patch adds pinmux entries of
few GPIOs.
Acked-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Like SPI and I2C few GPIO controllers also have
multiple chip instances. This patch adds the
flag 'DM_UC_FLAG_SEQ_ALIAS' in gpio_uclass driver
to control device sequence numbering. By defalut
the dev->r_seq for gpio_uclass will alwalys
returns -1, which leads the gpio driver probe
failure when using the driver with device trees.
Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Commit 8183058188 ("imx6: centralise common boot options in
mx6_common.h") broke boot on mx6sl and mx6sx by assuming that all mx6
SoCs use the same LOADADDR/SYS_TEXT_BASE range, which is not correct.
DDR on mx6sx/mx6sl starts at 0x80000000.
Adjust LOADADDR/SYS_TEXT_BASE to the proper values for mx6sx/mx6sl,
so that these SoCs can boot again.
Also, TQMA6 requires a custom CONFIG_SYS_TEXT_BASE value, so move
its setting prior to the inclusion of mx6_common.h.
Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
There are two revisions of wandboard: version B1 and C1.
Add the revision detection support, so that the correct dtb file can
be automatically loaded.
Based on the patch from Richard Hu <hakahu@gmail.com>.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Tested-By: Vagrant Cascadian <vagrant@aikidev.net>
Return if USB_MAX_CONTROLLER_COUNT hence the index of the controller
to be initialised is incorrect
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
This fixes the following compiler warning:
In file included from tools/common/image-fit.c:1:0:
./tools/../common/image-fit.c: In function ‘fit_conf_print’:
./tools/../common/image-fit.c:1470:27: warning: logical not is only applied
to the left hand side of comparison [-Wlogical-not-parentheses]
(const char **)&uname) > 0;
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Select CONFIG_CMD_NET and CONFIG_CMD_SETEXPR by default rather then
needing to have this in every sunxi defconfig file.
This also fixes the Merrii_A80_Optimus defconfig no longer building.
Cc: Maxin B. John <maxin.john@enea.com>
Reported-by: Maxin B. John <maxin.john@enea.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Add and use a proper dts for the ga10h a33 based tablet, as
submitted upstream.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
This instroduces comments that explain the purpose, parameters and return codes
of a few fdt support functions, that are used to fill the fdt.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Acked-by: Simon Glass <sjg@chromium.org>
Before device-tree, the device serial number used to be passed to the kernel
using ATAGs (on ARM). This is now deprecated and all the handover to the kernel
should now be done using device-tree. Thus, this passes the serial-number
property to the kernel using the serial-number property of the root node, as
expected by the kernel.
The serial number is a string that somewhat represents the device's serial
number. It might come from some form of storage (e.g. an eeprom) and be
programmed at factory-time by the manufacturer or come from identification
bits available in e.g. the SoC.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Simon Glass <sgj@chromium.org>
Rename the Astar_MID756 to Et_q8_v1_6 to match the kernel dts name.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Copy over all the latest dts changes from mripard/sunxi/dt-for-4.2 ,
this gives us a proper dtsi file for the A33 rather then abusing
sun8i-a23.dtsi for this.
And this replaces our minimal (dummy) sun7i-a20-mk808c and
sun8i-a33-astar-mid756 dts files with proper ones.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Add "allwinner,sun8i-a33-pinctrl", this is used by the latest upstream
linux sunxi dts files.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The Mele A1000G-quad and the Mele M9 have the same PCB, sofar we've been
using the same defconfig (and dts on the kernel side) for both models.
Unfortunately this does not work for the otg controller, on the M9 this
is routed to a micro-usb connector on the outside, while as on the
A1000G-quad it is connected to an usb to sata bridge.
This commit adds a new defconfig for the Mele-A1000G-quad to allow using
different otg controller settings on the 2 boards.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Before this commit the code for determining the disconnect threshold was
checking for sun4i or sun6i assuming that those where the exception and
that newer SoCs use a disconnect threshold of 2 like sun7i does.
But it turns out that newer SoCs actually use a disconnect threshold of 3
and sun5i and sun7i are the exceptions, so check for those instead.
Here are the settings from the various Allwinner SDK sources:
sun4i-a10: USBC_Phy_Write(usbc_no, 0x2a, 3, 2);
sun5i-a13: USBC_Phy_Write(usbc_no, 0x2a, 2, 2);
sun6i-a31: USBC_Phy_Write(usbc_no, 0x2a, 3, 2);
sun7i-a20: USBC_Phy_Write(usbc_no, 0x2a, 2, 2);
sun8i-a23: USBC_Phy_Write(usbc_no, 0x2a, 3, 2);
sun8i-h3: USBC_Phy_Write(usbc_no, 0x2a, 3, 2);
sun9i-a80: USBC_Phy_Write(usbc_no, 0x2a, 3, 2);
Note this commit makes no functional changes for sun4i - sun7i, and
changes the disconnect threshold for sun8i to match what Allwinner uses.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
A conflict between the PMIC and unit test work means that the sandbox test
device tree file is no-longer built. Fix this.
Series-to: u-boot
Series-cc: joe, prz
Change-Id: I6616428e05713e5306f848e7dd0a645dedf0934e
Signed-off-by: Simon Glass <sjg@chromium.org>
There are some core test nodes near the beginning of the file which should
be grouped together. But for other nodes, let's sort them.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Commit 9cc36a2 'dm: core: Add a flag to control sequence numbering' changed
the default uclass behaviour to not support bus numbering. This is incorrect
for PCI and that commit should have enabled the flag for PCI.
Enable it so that PCI buses can be found and the 'pci' command works again.
Also add a test for this.
Signed-off-by: Simon Glass <sjg@chromium.org>
For some reason 'u-boot -D' does not restore the terminal correctly when
the 'reset' command is used. Call the terminal restore function explicitly
in this case.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Every pin can be configured now from the device tree. A dt-bindings
has been added to describe the different property available.
Change-Id: I1668886062655f83700d0e7bbbe3ad09b19ee975
Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
Acked-by: Simon Glass <sjg@chromium.org>
Baytrail physically maps the first 2 GB of SDRAM from 0x0 to 0x7FFFFFFF
and additional SDRAM is mapped from 0x100000000 and up. There is a
physical memory hole from 0x80000000 to 0xFFFFFFFF for other uses.
Because of this, PCI region 3 should only try to use up to the amount of
SDRAM or 0x80000000, which ever is less.
Signed-off-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Support QEMU PIRQ routing via device tree on both i440fx and q35
platforms. With this commit, Linux booting on QEMU from U-Boot
has working ATA/SATA, USB and ethernet.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Writing 0xcb to I/O port 0xb2 (Advanced Power Management Control) causes
U-Boot to hang on QEMU q35 target. We introduce a config option in the
device tree "u-boot,no-apm-finalize" under /config node if we don't want
to do that.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Although the two qemu-x86 targets (i440fx and q35) share a lot in
common, they still have something that cannot easily handled in one
single device tree). Split to create two dedicated device tree files
and make the i440fx be the default build target.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
We should ignore those regions whose size is negative. These are
typically optional and unused regions (like GbE and platform data).
Change-Id: I65ad01746144604a1dc0588b617af21f2722ebbf
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
As VGA option rom needs to run at C segment, although QEMU PAM emulation
seems to only guard E/F segments, for correctness, move VGA initialization
after PAM decode C/D/E/F segments.
Also since we already tested QEMU targets to differentiate I440FX and Q35
platforms, change to locate the VGA device via hardcoded b.d.f instead of
dynamic search for its vendor id & device id pair.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
QEMU always decode legacy IDE I/O ports on PIIX chipset. However Linux ata_piix
driver does sanity check to see whether legacy ports decode is turned on.
To make Linux ata_piix driver happy, turn on the decode via IDE_TIMING register.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
By default the legacy segments C/D/E/F do not decode to system RAM.
Turn on the decode via Programmable Attribute Map (PAM) registers
so that we can write configuration tables in the F segment.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
The default weak version of pci_skip_dev() in drivers/pci/pci_common.c
skips the host bridge (b.d.f = 0.0.0) which is actually the i440fx/q35
chipset for QEMU targets. Define CONFIG_PCI_CONFIG_HOST_BRIDGE to make
it visible in the PCI configuration space.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
If pirq_routing_table points to NULL, that means U-Boot fails to
generate the table before in create_pirq_routing_table(), so we
test it against NULL before actually writing it.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Intel Quark SoC has the same interrupt routing mechanism as the
Queensbay platform, only the difference is that PCI devices'
INTA/B/C/D are harcoded and cannot be changed freely.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Describe all required properties needed by the irq router device tree.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
PIRQ routing is pretty much common in Intel chipset. It has several
PIRQ links (normally 8) and corresponding registers (either in PCI
configuration space or memory-mapped IBASE) to configure the legacy
8259 IRQ vector mapping. Refactor current Queensbay PIRQ routing
support using device tree and move it to a common place, so that we
can easily add PIRQ routing support on a new platform.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Enable legacy IDE support on the pc target and AHCI support on the
q35 target. Default configuration is to support the pc target.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Enable CONFIG_LBA48 to support large disks. CONFIG_ATAPI is only needed
by cmd_ide.c which is not common for modern x86 targets, hence remove it.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Eliminate the following build warning in atapi_inquiry():
"warning: assignment from incompatible pointer type [enabled by default]"
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
The legacy IDE device has a BAR4 (Bus Master Interface BAR) which
needs to be configured.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
Remove the '#undef DEBUG' in pci_auto.c so that we can enable debug
message output via '-DDEBUG'.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
It turns out that QEMU x86 emulated graphic card has a built-in
option ROM which can be run perfectly with native mode by U-Boot.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
CONFIG_FRAMEBUFFER_SET_VESA_MODE and CONFIG_FRAMEBUFFER_VESA_MODE
are not x86-specific, so move them to drivers/video/Kconfig and
make them depend on VIDEO_VESA driver. Some cosmetic fixes are
applied to the Kconfig help text as well.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
There is no reason to prevent CONFIG_VIDEO_VESA driver working on
non-x86 boards, so remove such limitation.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
gd is not referenced in those board files so DECLARE_GLOBAL_DATA_PTR
should be removed.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
QEMU is much easier for us test booting U-Boot as a coreboot payload
than having a real board like chromebook_link.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Some x86 boards set CONFIG_NR_DRAM_BANKS to 1, which causes incorrect
DRAM size printed when booting from coreboot, like this:
CPU: x86, vendor Intel, device 663h
DRAM: 636 KiB
Using default environment
Change it to 8 which should be enough for both coreboot and bare
cases, and move it to x86-common.h.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Now that we have QEMU support, make it the default vendor in the
'make menuconfig' screen.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
This commit introduces the initial U-Boot support for QEMU x86 targets.
U-Boot can boot from coreboot as a payload, or directly without coreboot.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Merged in patch 'x86: qemu: Add CMD_NET to qemu-x86_defconfig
https://patchwork.ozlabs.org/patch/479745/
pci_hose_phys_to_bus() is needed by several drivers. Move it to
pci_common.c to avoid a broken build when CONFIG_DM_PCI is on.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
netconsole had become defective over time and cleanups.
Because the feature is used very rarely nobody did take notice about this
defect.
With this patch the resulting syntax error on call will be fixed.
Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>
CONFIG_NET_MULTI is not used anywhere and thus can safely be removed
from the configs.
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Lars Poeschel <poeschel@lemonage.de>
The config for pcm051 still undef'd CONFIG_USE_IRQ. This is not
needed any more since it is not defined in the whole include path
before.
Signed-off-by: Lars Poeschel <poeschel@lemonage.de>
NET_RANDOM_ETHADDR depends on lib/rand.c. This patch adds dependency to
Kconfig to ensure that library is also compiled.
Remove the definitions from Blackfin boards' include/configs.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This also selects CONFIG_NET for any CONFIG_CMD_NET board.
Remove the imx default for CONFIG_NET.
This moves the config that was defined by 60296a8 (commands: add more
command entries in Kconfig).
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Another shell scripting command that has not been moved.
Moved using tools/moveconfig.py using these settings:
CMD_SETEXPR bool n y
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Commit 76ec988b06 (net: Remove all calls to net_random_ethaddr())
accidentally deleted CONFIG_TARGET_BCT_BRETTL2=y, and since then
bct-brettl2 would not build.
Since commit a26cd04920 (arch: Make board selection choices
optional), Kconfig actually allows such a .config file in which no
board is selected, but the build never succeeds.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Commit 92ac520821 (net: Remove all references to CONFIG_ETHADDR
and friends) accidentally dropped #endif. Since then, gr_ep2s60
could not build.
scripts/kconfig/conf --silentoldconfig Kconfig
CHK include/config.h
GEN include/autoconf.mk
In file included from include/config.h:5:0,
from ./include/common.h:18:
include/configs/gr_ep2s60.h:15:0: error: unterminated #ifndef
#ifndef __CONFIG_H__
^
make[1]: *** [include/autoconf.mk] Error 1
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
this removes a config entry and uses the default value
defined in config_fallbacks.h. This implements the same
behaviour as a patch series for other i.MX6 boards from
Freescale
Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com>
If the EEPROM could not be read or is corrupt we always want to hang.
Note that an error message will have been displayed by read_eeprom in this
case.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
The fdt_file1 and fdt_file2 vars provide fallbacks for the fdt file loading
script. There is no need to allow the user to override these as if they
want to specify the fdt, they should do so in the first attempt which is
the fdt_file var.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
We want to model env var to always reflect what was in the EEPROM. There
is no point in allowing a user to override this.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
- Added iomux for CAN_STBY and RS484_TEN (GW52xx/GW53xx/GW54xx/GW551x)
- Moved iomux of USBHUB_RST# out of board_ehci_hcd_init so that it is
done regardless of USB being initialized in bootloader
- Added usb_sel iomux/hwconfig for GW552x
- Fixed mezzanine DIO for GW54xx
- Fixed PANLEDR# for GW54xx
- Fixed dio iomux/hwconfig for GW552x
- Fixed dio iomux for GW551x
- removed redundant #define
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
In case the DC-DC is already enabled mxs_enable_4p2_dcdc_input() returns
without reenabling brown out detection. So fix this issue by
moving the return before brown out deactivation.
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Ethernet function of Alt board can select normal and B by DIP switch
on board. But user need to set not only DIP switch but also pin function.
This adds pin function of Ethernet function B. This can select from Kconfig.
Signed-off-by: Mitsuhiro Kimura <mitsuhiro.kimura.kc@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
The chip select 1 of the NAND controller is available if you want to
use, although the pins are shared with UART port 2.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
PH1-Pro5 includes a newer version of DDR PHY IP. Some registers
have been added to the reserved areas.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Since commit 92ac520821 (net: Remove all references to
CONFIG_ETHADDR and friends), the ethernet device on UniPhier boards
is not working because of the incorrect (all-zero) MAC address.
Enable CONFIG_NET_RANDOM_ETHADDR to generate the random one.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
One disadvantage of commit a26cd04920 (arch: Make board selection
choices optional) is that Kconfig could create such an insane
.config file that no board is selected.
As PH1-Pro4 is the main stream of UniPhier SoC family, rip off the
"optional" again in favor of PH1-Pro4 as the default SoC.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This file is only built for SPL. These ifdef conditionals are
unnecessary because UniPhier platform now supports UART on SPL.
Show appropriate messages on error.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Cache coherency for SMP is cared by Linux. In U-Boot, the secondary
CPU(s) are just sleeping. Nothing in memory is shared with the
primary CPU.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
For the same reason as commit d0c47b3ef7 (serial: UniPhier: use
32 bit register access), use "str" instead of "strb" for the LCR
register setting.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The business for UniPhier Soc family has been transferred from
Panasonic Corporation to Socionext Inc.
Update the SoC select menu in Kconfig.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
In the Linux coding style, it is recommended to include <linux/io.h>
rather than <asm/io.h>. Follow this trend.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
sun8i uses the same PSCI backend as sun6i, without power clamps.
Since there is no secure SRAM, the backend is placed at the end
of DRAM.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
sun8i can share the PSCI backend with sun6i. Only difference
is sun8i does not have CPU power clamp controls.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
This adds PSCI support for sun6i. So far it only supports
the PWR_ON method.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The PSCI code only works for sun7i. Rename it with _sun7i suffix,
and build only if building for sun7i.
This paves the way for adding PSCI support for other platforms.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The PSCI CPU_ON code accesses quite a few registers. Document
their names to make it easier to cross reference.
Also explain "lock cpu" and "unlock cpu" as enabling/disabling
debug access.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
This commit adds support to the sunxi SPL to load u-boot from the internal
NAND. Note this only adds support to access the boot partitions to load
u-boot, full NAND support to load the kernel, etc. from the nand data
partition will come later.
Signed-off-by: Roy Spliet <r.spliet@ultimaker.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
This change is necessary to calculate correct checksum for NAND
boot. Works both for MMC and NAND. Without it BROM rejects boot image
as invalid (bad checksum). (Changes block size from 0x200 to 0x2000).
Signed-off-by: Daniel Kochmański <dkochmanski@turtle-solutions.eu>
Signed-off-by: Roy Spliet <r.spliet@ultimaker.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Add initial sun9i (A80) support, only uart + mmc are supported for now.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The A1 SRAM Base differs between sun9i and the others, update sunxi-common.h
to deal with this, so that we do not set the initial stack pointer to point
to the BROM.
This avoids the need for the weird undocumented register write I previously
took from the allwiner u-boot sources and which needed #ifdef-ery in start.S
as it needed to be done really early on.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The DRAM Base differs between sun9i and the others, update sunxi-common.h to
deal with this.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The latest versions of the fel tool support loading normal u-boot builds
directly, and this is now the preferred way to use the fel boot method.
This commit removes support for the old deprecated standalone fel builds.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Unlike the A31 and the A23 the A33 actually has a SID inside the SoC again,
but sid[3] is 0 (at least on some SoCs), so it is better to use the axp221
sid.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The usb-kbd key repeat code assumes that reports get repeated every 40 ms,
this is never true when using CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP, and
does not always works for CONFIG_SYS_USB_EVENT_POLL and
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE since not all usb keyboards honor
the usb_set_idle() command.
For CONFIG_SYS_USB_EVENT_POLL we must use usb_set_idle() since we do a
blocking wait for the hid report, so if we do not tell the keyboard to send
a hid report every 40ms even if nothing changes then we will block u-boot
for 1s (the default u-boot usb interrupt packet timeout). Note that in this
case on keyboards which do not support usb_set_idle() we loose and we actually
get 1s latencies on other u-boot activities.
For the other poll-methods this commit stops using usb_set_idle() and instead
repeats the last received hid-report every 40 ms as long as no new hid-report
is received. This fixes key-repeat not working at all with
CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP and fixes it not working with
keyboards which do not implement usb_set_idle() when using
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
This has been tested to the extent that I can enumerate
a asix usb networking adapter and boot a kernel over usb
on the 96boards hikey u-boot port I'm currently doing.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Update the ci_udc driver to support bulk transfer
and also added capability of having multiple dtds
if requested data is more than 16K.
These changes are tested for both the DFU and lthor.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Since i've been married, i also have a new surname.
Mr. Petermaier moved to Mr. Schmelzer.
In this patch i update all files in which my (old) name is present.
Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>
a6b541b090: TI ARMv7: Don't use GD before crt0.S has set it
moves the init of the debug uart at the very end of SPL code.
Enable it for the siemens board earlier, as they print
ddr settings ... all debug output before board_init_r()
is here currently useless. Maybe we must rework this
globally?
Signed-off-by: Heiko Schocher <hs@denx.de>
Function 'sprintf' does not check buffer boundaries but outputs
to the buffer of fixed size which could potentially cause buffer
overflow. Use a safer function to replace it.
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
On ARM v7M, the processor will return to ARM mode when executing
a blx instruction with bit 0 of the address == 0. Always set it
to 1 to stay in thumb mode.
Signed-off-by: Matt Porter <mporter@konsulko.com>
common/image.c currently implicitly depends on CONFIG_NR_DRAM_BANKS
when CONFIG_ARM is enabled. Make this requirement explicit.
Signed-off-by: Matt Porter <mporter@konsulko.com>
The foundation model (FVP) emulator nominally boots using
a clean, uncompressed kernel and the "booti" command. Augment
the default U-Boot script to do this.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Since 741e58e0fc (Create a .cfg file containing the CONFIG options
used to build), all the Blackfin boards fail to build if the parallel
(-j) option is passed.
$ make -s bf506f-ezkit_defconfig
#
# configuration written to .config
#
$ make -j8 CROSS_COMPILE=bfin-elf-
scripts/kconfig/conf --silentoldconfig Kconfig
CHK include/config.h
UPD include/config.h
GEN include/autoconf.mk
GEN include/autoconf.mk.dep
CHK include/config/uboot.release
CHK include/generated/timestamp_autogenerated.h
UPD include/generated/timestamp_autogenerated.h
CFG u-boot.cfg
include/asm-offsets.h:3:43: fatal error:
generated/generic-asm-offsets.h: No such file or directory
compilation terminated.
make: *** [u-boot.cfg] Error 1
When parsing header files for defined CONFIG options, DO_DEPS_ONLY
must be defined to exclude generated headers that might not have
been available yet.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
gd->ram_size is stored as phys_size_t type which can be bigger than an
unsigned long on some architectures. When using unsigned long type,
SDRAM of 4GiB or larger will not print the correct size, but using
phys_size_t will.
Signed-off-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
This introduces a distinction between return codes that are read bytes counts
and errors. Read bytes counts are erroneous when null (no data was read) while
errors are erroneous when non-null.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Tested-by: Tim Harvey <tharvey@gateworks.com>
Nothing too fancy. A simple test that attmpts to load two loadables and
verify that they are properly unpacked in the u-boot sandbox.
Signed-off-by: Karl Apsite <Karl.Apsite@dornerworks.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
bootm_find_ramdisk_fdt() renamed to bootm_find_images() for readability.
The function bootm_find_ramdisk_fdt() appears to be a simple wrapper for
bootm_find_ramdisk(), bootm_find_fdt(), and now bootm_find_loadables().
I didn't see any other callers entering a bootm_find<thing>, so removing
the wrapper, and condensing these together hopefully makes the code a
little simpler.
Signed-off-by: Karl Apsite <Karl.Apsite@dornerworks.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Added a trimmed down instance of boot_get_<thing>() to satisfy the
minimum requierments of the added feature. The function follows the
normal patterns set by other boot_get<thing>'s, which should make it a
bit easier to combine them all together into one boot_get_image()
function in a later refactor.
Documentation for the new function can be found in source:
include/image.h
Signed-off-by: Karl Apsite <Karl.Apsite@dornerworks.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Added FIT_LOADABLE_PROP, so the user can identify an optional entry
named "loadables" in their .its configuration. "loadables" is a comma
separated list in the .its
Documentation can be found in doc/uImage.FIT/source_file_format.txt and
doc/uImage.Fit/multi-with-loadables.its
Signed-off-by: Karl Apsite <Karl.Apsite@dornerworks.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Instead of hardcoding -lssl -lcrypto as the flags needed to build
mkimage with FIT signature enabled, use pkg-config when
available. This allows to properly support cases where static linking
is used, which requires linking with -lz, since OpenSSL uses zlib
internally.
We gracefully fallback on the previous behavior of hardcoding -lssl
-lcrypto if pkg-config is not available or fails with an error.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
In the latest Linux coding style, <linux/io.h> should be included
rather than <asm/io.h>. To follow this standard also in U-Boot,
add include/linux/io.h. Currently, it just includes <asm/io.h>.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The Juno reference design typically plugs the root FS
on a USB stick. We need to wait a bit for the root to
appear so tell this on the default command line.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
DM3730 CPU used on beagleboard-xm doesn't have any gpio
multiplexed with wait0 pin,
but gpio_63 multiplexed with wait1, so it looks like typo.
At current form it has no sense,
because of wait0 have no function "4".
Signed-off-by: Evgneiy A. Dushistov <dushistov@mail.ru>
Generic board support seems to work just fine. Tested on ml507 with
bitstream generated on the latest ISE software.
Tested-by: Georg Schardt <schardt@team-ctech.de>
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
After the mx6 config consolidation, 'save' command is no longer
recognized.
Pass the full command name 'saveenv' instead.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
CONFIG_SUPPORT_EMMC_BOOT is important to enable the boot partition via
'mmc partconf 0 1 1 0' command, for example.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Adjust CONFIG_SYS_DFU_DATA_BUF_SIZE in order to avoid the following error
when running the dfu command:
=> dfu 0 mmc 0
dfu_get_buf: Could not memalign 0x2000000 bytes
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
The ARM Trusted Firmware or other security solutions are
eating memory from the top of the physical SDRAM1 space,
moving backward from 0xffffffff, currently occupying e.g.
0xfe000000-0xffffffff with Trusted Firmware.
This solution to reserving memory for secure world is not
optimal, so we need to think of how the secure world and
earlier boot stages should communicate to U-Boot what
memory they are eating up. For now let's just put 16MB
aside.
Also enable the memory test command and define start and
end of the test range so we can check that we actually have
all that memory available and working.
Suggested-by: Axel Haslam <ahaslam@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Define U_BOOT_TZ alongside U_BOOT_TIME and U_BOOT_DATE and use it to
include the timezone in the version output.
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
If we are displaying detected PCI devices (CONFIG_PCI_SCAN_SHOW) display
a 'PCI:' header prior to scan.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Add an error message that gets passed to set_default_env() like
env_nand implements. This message is displayed to the user as the
reason for falling back to the default environment.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Testing on the ARM Versatile Express Juno board showed intermittent CFI
flash detection problems.
Debug output in exception cases showed that the NOR flash was returning
incorrect values to a query command:
fwc addr 0000000008000000 cmd f0 f0f0f0f0 32bit x 8 bit
fwc addr 0000000008000000 cmd ff ffffffff 32bit x 8 bit
fwc addr 0000000008000154 cmd 98 98989898 32bit x 8 bit
is= cmd 51(Q) addr 0000000008000040 is= 00800051 51515151
fwc addr 0000000008001554 cmd 98 98989898 32bit x 8 bit
is= cmd 51(Q) addr 0000000008000040 is= 00800051 51515151
fwc addr 0000000008000000 cmd f0 00f000f0 32bit x 16 bit
fwc addr 0000000008000000 cmd ff 00ff00ff 32bit x 16 bit
fwc addr 0000000008000154 cmd 98 00980098 32bit x 16 bit
is= cmd 51(Q) addr 0000000008000040 is= 00800051 00510051
fwc addr 0000000008001554 cmd 98 00980098 32bit x 16 bit
is= cmd 51(Q) addr 0000000008000040 is= 00800051 00510051
Debugging showed that the problem could be solved by preventing u-boot
from scanning different flash widths by specifying
CONFIG_SYS_FLASH_CFI_WIDTH so that only using the 'correct' width was
used.
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
UART3 RX and TX pins are now moved to support uart download capability
on the platform. Old pins are now GPIOs routed to expansion ports.
All original boards should either have been returned for modifications
or already modified for the required change and maintaining
compatibility for older boards are no longer needed.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Previously, if the menu activated by the 'sysboot' command gets
interrupted by a Ctrl-C, the behaviour is as if the menu timeout was
reached - i.e. boot the default menu entry. This patch fixes that
so a Ctrl-C now terminates the command as the user would expect.
Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Reviewed-by: Simon Glass <sjg@chromium.org>
Previously, a NULL pointer dereference would occur if the 'sysboot'
command is executed without any arguments.
Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Reviewed-by: Simon Glass <sjg@chromium.org>
Due to a misunderstanding, in 698a12b we reverted changes that we in
fact wanted to keep. So lets fix that mistake and bring the code back
to how it should have been.
This reverts commit 698a12bef9.
Signed-off-by: Tom Rini <trini@konsulko.com>
In some cases the build for the autoconf breaks. This outputs the errors
following the status so that action can be taken without building again
manually.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
A common case for failed builds is a missing compiler. Print a message
for that case to tell the user concisely which compiler was expected
that was not found.
This patch also has the effect of not printing build errors any longer.
The next patch will add a switch to optionally bring that back.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
If boards fail, output that list to a file so that it can easily be
passed back into moveconfig.py using the -d option.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Some config.h files live in arch and board directories. They will need
to be cleaned up as well, so run the same filters there.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
In some case you may want to only cleanup the headers. Make it possible
without waiting for all boards to compile.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This is helpful to re-attempt to move failed boards from a previous run
without starting over.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
When moving configs, it is important to know what was defined in the
config header even if it duplicates the configs coming from Kconfig.
This is specifically needed for the case where a config is set to
default 'y' in the Kconfig. This would previously cause the actual value
from the include config to be filtered out, and moveconfig.py would
think that it was 'n'... This means that the value that should be 'y'
is now (in every defconfig) set to 'not set'.
tools/moveconfig.py now defines KCONFIG_IGNORE_DUPLICATES to prevent the
filtering from happening and selecting wrong values for the defconfig.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This will ensure that the order of the defconfig entries will always
match that of the Kconfig files. After one slightly painful (but
still early in the process) pass over all boards, this should keep
the defconfigs clean from here on.
Users must edit the Kconfig first to add the menu entries and then run
moveconfig.py to update the defconfig files and the include configs.
As such, moveconfig.py cannot compare against the '.config' contents.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This tool was originally written for my local use to ease the task
of tons of CONFIG moves, but there have been some requests for
mainlining it.
So, I have tidied up the code with nicer comments, and here it is.
See the comment block of the script for usage.
The first draft was
http://patchwork.ozlabs.org/patch/430422/
Main updates are:
- Adapted to the single .config configuration
- Support colored log
- Support moving multiple options at once
(and take configs via input file only)
- Continue even if some boards fail
(Idea provided by Joe Hershberger)
- Add more options
- More comments and code cleanups
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Move CONFIG_CMD_CACHE to mx6_common and standardise the way it's defined.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Tom Rini <trini at konsulko.com>
Move generic miscellaneous options that are standard across most, if not all,
mx6 boards to central mx6_common define to ensure consistent features.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
All boards define CONFIG_MX6, CONFIG_DISPLAY_BOARDINFO, CONFIG_DISPLAY_CPUINFO
and CONFIG_SYS_GENERIC_BOARD so define them in mx6_common
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Tom Rini <trini at konsulko.com>
The linux/sizes.h, asm/arch/imx-regs.h, asm/imx-common/gpio.h,
config_cmd_default.h includes are used fairly universally across imx6 boards
so include them in mx6_common.h by default.
We define CONFIG_SYS_NO_FLASH before config_cmd_default.h so that we
don't have to undef CONFIG_CMD_FLASH / CONFIG_CMD_IMLS everywhere.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Standardise mx6_common.h to the same as other mx6 boards
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Tom Rini <trini at konsulko.com>
91199f4a5a broke mmc based Falcon mode.
The block_read function returns the number of blocks read thus the error
check needs to look for a return of 0 blocks read.
Cc: Paul Kocialkowski <contact@paulk.fr>
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Acked-by: Paul Kocialkowski <contact@paulk.fr>
The CPU temperature grade from OTP is now used to define the critical
threshold at which point we busyloop until we are below, however this
threshold is still too low.
Instead of 20C below the max CPU temperature, change it to 5C defined now
by TEMPERATURE_HOT_DETLA for clarity. Rename 'passive' to 'critical'
as that better defines our use case here. Additionally change the output
of the busyloop message to show the max CPU temperature as well as current.
Before:
CPU Temperature is 101 C, too hot to boot, waiting...
CPU Temperature is 101 C, too hot to boot, waiting...
After:
CPU Temperature (101C) too close to max (105C) waiting...
CPU Temperature (101C) too close to max (105C) waiting...
Cc: Stefan Roese <sr@denx.de>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Jon Nettleton <jon.nettleton@gmail.com>
Cc: Jason Liu <r64343@freescale.com>
Cc: Ye Li <b37916@freescale.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Christian Gmeiner <christian.gmeiner@gmail.com>
Cc: Markus Niebel <Markus.Niebel@tq-group.com>
Cc: Peng Fan <b51431@freescale.com>
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
We should not hardcode MXS_DMA_ALIGNMENT to 32, since we can not guarantee
that socs' cache line size is 32 bytes.
If on chips whose cache line size is 64 bytes, error occurs:
"
NAND: ERROR: v7_dcache_inval_range - start address is not aligned - 0xbdf1d1a0
ERROR: v7_dcache_inval_range - stop address is not aligned - 0xbdf1f4a0
ERROR: v7_dcache_inval_range - start address is not aligned - 0xbdf1d1a0
"
Align MXS_DMA_ALIGNMENT with ARCH_DMA_MINALIGN whose value is same to
CONFIG_SYS_CACHELINE_SIZE if CONFIG_SYS_CACHELINE_SIZE defined.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
The break after return is unreachable code, remove it.
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>
pwm_id_to_reg() can return NULL, so add NULL testing to prevent NULL pointer
dereference.
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>
Due to licensing issues, the files ps7_init.c/h are not able to be
distributed with U-Boot source code. Recent Xilinx tools also
provide the GPL variants (ps7_init_gpl.c/h), compatible with U-Boot
license.
Prior to this commit, we had to copy ps7_init files into
board/xilinx/zynq/ before the compile.
To be more user-friendly, let's include ps7_init_gpl.c/h for
Zedboard, MicroZed, ZC702, ZC706.
These init code have been taken from the hwplatform_templates
directory of Xilinx SDK 2014.4.
You can still use customized ps7_init_gpl.c/h by enabling
CONFIG_ZYNQ_CUSTOM_INIT. The recommended directory for storing them
is now board/xilinx/zynq/custom_hw_platform, but board/xilinx/zynq
is still supported for backward compatibility. The latter emits
a warning message to prompt users to gradually switch to the new
directory.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Prior to this commit, ZC702 and ZC706 shared the same configuration
and were built as follows:
ZC702: make zynq_zc70x_defconfig && make
ZC706: make zynq_zc70x_defconfig && make DEVICE_TREE=zynq-zc706
This commit introduces separate configuration for them, which makes
the next commit much easier.
Going forward, the recommended build commands are:
ZC702: make zynq_zc702_defconfig && make
ZC706: make zynq_zc706_defconfig && make
Although the old work flow is still supported, CONFIG_TARGET_ZC70X
has been marked as deprecated. If used, the warning message is
shown to prompt users to switch to the new scheme.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Don't use error-prone arch timer code and instead use system
timer implementation to simplify our code.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This changes enable ONFI detection. The Read ID command now allows
one address byte which is needed for ONFI detection. To read the
ONFI parameter page, the NAND_CMD_PARAM need to be supported. The
CMD code enables one command and one address byte along with reading
data from flash using R/B#, as specified by ONFI.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Add option to choose between current 24-error correction and 32-error
correction through Kconfig. 32-error correction allow to use NAND
chips which require up to 8-bit error correction per 512 byte (when
using 2K pages).
Signed-off-by: Stefan Agner <stefan@agner.ch>
This commit allows users to enable/disable the Freescale NFC
controller found in systems like Vybrid (VF610), MPC5125, MCF54418
or Kinetis K70 via Kconfig with more detailed help docs.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Acked-by: Stefano Babic <sbabic@denx.de>
[scottwood: updated vf610twr_nand_defconfig]
Signed-off-by: Scott Wood <scottwood@freescale.com>
Use in-band bad block table (NAND_BBT_NO_OOB) which allows to
use the full OOB for hardare ECC purposes. Since there is no
ECC correction on the OOB it is also safer to use in-band area
to store the bad block table marker.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Implement read of OOB area only. When using column and sector size
properties, only parts of the page can be read. However, this works
only when hardware ECC is disabled, otherwise the ECC engine would
ruin the data in the buffer. To allow OOB only reads, three points
had to be addressed:
- Set ECC mode per command.
- Handle NAND_CMD_READOOB seperate. Make sure column and sector
size is correctly set up, while disabling ECC.
- Now, the OOB data end up at the beginning of the buffer. Remove
the special handling of OOB (spareonly).
Especially bad block scans benefit from this change. On a 512MiB
SLC NAND device, the bad block scan took 1.5s less than before.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Since we do not support sub-page writes anyway, reading the page
back to the controller on SEQIN command is not required. Remove
the page read on SEQIN.
However, the column/page values relevant to the SEQIN command, hence
set the column/row address on SEQIN command.
Signed-off-by: Stefan Agner <stefan@agner.ch>
To improve performance we remember the current page in the buffer
and avoid reading it twice. This implicit page cache increases
complexity while does not increase performance in real world cases.
This patch removes that feature.
Acked-by: Bill Pringlemeir <bpringlemeir@nbsps.com>
Signed-off-by: Stefan Agner <stefan@agner.ch>
Calculating the ECC strength dynamically to be aligned with the mxs NAND
driver and the Linux Kernel.
Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks>
Reviewed-by: Marek Vasut <marex@denx.de>
Freeing allocated memory to priv before returning
from the function
Signed-off-by: Raghav Dogra <raghav@freescale.com>
[scottwood: removed unnecessary cast]
Signed-off-by: Scott Wood <scottwood@freescale.com>
On systems with caches enabled, NAND I/O may need to flush/invalidate
the cache during read/write operations. For this to work correctly, all
buffers must be cache-aligned. Fix nand_verify*() to allocate aligned
buffers.
This prevents cache alignment warnings from being spewed when using
U-Boot to write an updated version of itself to flash on NVIDIA Tegra
Seaboard (after perturbation of stack/data layout in current
u-boot-dm/next branch).
I have validatd (executed) nand_verify(), but I don't think I've executed
nand_verify_page_oob(); testing of that would be useful.
Cc: Peter Tyser <ptyser@xes-inc.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Scott Wood <scottwood@freescale.com>
Fixes: 59b5a2ad83 ("nand: Add verification functions")
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Scott Wood <scottwood@freescale.com>
Currently we need to build one U-boot image for each of the wandboard
variants: quad, dual-lite and solo.
By switching to SPL we can support all these variants with a single binary,
which is very convenient.
Based on the work from Richard Hu.
Tested kernel booting on the three boards.
Signed-off-by: Richard Hu <hakahu@gmail.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Tested-by: Vagrant Cascadian <vagrant@aikidev.net>
Reviewed-by: Stefano Babic <sbabic@denx.de>
The behavior of the env attrs depends on CONFIG_REGEX. Add an additional
test if that variable is set.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add a new "env" subcommand to the ut command.
This will run unit tests on the env code. This should be targetable to
any device that supports the env features needed for the tests.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Put the driver model for the system back into a good state after
completing the DM testing.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Simon Glass <sjg@chromium.org>
The asserts are sometimes called from the context of the test command
itself so make sure that a return that happens as a result of a failure
is compatible with that command return. When called within a test, the
return value is ignored.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
There's not much point in having a failure count if we always give up on
the first failure. Also stop clearing the entire state between tests.
Make sure that any failures are still passed out to the command line.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Make all unit tests selectable as a menu of test suites instead of just
sitting in the top-level menu individually.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Simon Glass <sjg@chromium.org>
Unify the command for running unit tests further by moving the "ut_time"
command over to "ut time".
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Unify the command for running unit tests further by moving the "dm test"
command over to "ut dm".
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Simon Glass <sjg@chromium.org>
Add a command that all other unit tests should be a sub-command of.
Also include a command that will run all tests.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Simon Glass <sjg@chromium.org>
Separate the ability to define tests and assert status of test functions
from the dm tests so they can be used more consistently throughout all
tests.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
When the ethaddr is changed in the env, update the device pdata at the
same time (only if it is probed for the DM case; only if registered for
the non-DM case). Again this gets us closer to completely non-polled
env needed to simplify the net_loop.
This requires that the NET feature select the REGEX feature.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
The bootfile env var is already kept up to date by the callback in net.c
so there is no need to poll it too.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Check that the common network stack's env vars conform to the proper
format for IP addresses.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Instead of checking for changes to the env each time we enter the
net_loop, use the env callbacks to update the values of the variables.
Don't update the variables when the source was programmatic, since the
variables were the source of the new value.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Use a regular expression to apply the default formatting flags for all
ethaddr env vars.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
We already could tell the difference in the callback between an import
and "other" which we called interactive. Now add further distinction
between interactive (i.e. running env set / env edit / env ask / etc.
from the U-Boot command line) and programmatic (i.e. when u-boot source
calls any variant of setenv() ).
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Allow the features that use env_attrs to specify regexs for the name
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
In some cases it can be helpful to have context in the callback about
the calling situation. This is needed for following patches.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The logic to find the whole matching name was split needlessly between
the reverse_strstr function and its caller. Fully contain it to make the
interface for calling it more consistent.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
This function returned numbers for error codes. Change them to error
codes.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Enable some additional ENV commands in sandbox to aid in build testing
and run testing.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Stop using the sandbox arch Kconfig to override defaults for config
options. This is a bit of abuse and may be causing build problems.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
The defconfigs should not be edited directly. They should be generated
by editing the .config (through menuconfig or whatever) and then run
make savedefconfig to have the Kconfig system generate a clean defconfig
I did this for sandbox here with no actual changes.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This register is reserved and shouldn't have been exposed.
Accessing it may have unexpected result on different SoCs.
Signed-off-by: York Sun <yorksun@freescale.com>
The original load address of U-Boot is 0x67f80000. The address
space of NOR flash is 0x60000000 to 0x67ffffff. It will cause
the size of u-boot couldn't be larger than 512K. As more features
are supported in u-boot, the size of u-boot is larger than 512K.
To fix this issue, the load address of U-Boot for NOR boot is
adjusted to 0x60100000.
In RCW, the PBI command needs to change as follows:
.pbi
-write 0xee0200, 0x67f80000
+write 0xee0200, 0x60100000
.end
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Remove the calls to net_random_ethaddr() that some boards and some
drivers are calling. This is now implemented inside of net/eth.c
Enable the feature for all boards that previously enabled it.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-By: Michael Walle <michael@walle.cc> (for the lsxl board part)
Series-changes: 2
-Fixed bfin build errors
We really don't want boards defining fixed MAC addresses in their config
so we just remove the option to set it in a fixed way. If you must have
a MAC address that was not provisioned, then use the random MAC address
functionality.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Implement the random ethaddr fallback in eth.c so it is in a common
place and not reimplemented in each board or driver that wants this
behavior.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Targets with CONFIG_NEEDS_MANUAL_RELOC do not use REL/RELA
relocation (mostly only GOT) where functions aray are not
updated. This patch is fixing function pointers passed to phy_register
function.
This patch was tested on Microblaze architecture.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
When the ethaddr changes in the env, the hardware should also be updated
so that MAC filtering will work properly without resetting U-Boot.
Also remove the manual calls to set the hwaddr that was included in a
few drivers as a result of the framework not doing it.
Reported-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Tested-by: Michal Simek <michal.simek@xilinx.com>
RTL8211F has different registers from RTL8211E.
This patch adds support for RTL8211F PHY which
can be found on Freescale's T1023 RDB board.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Sunxi platforms use ARM Cortex A8, A7 and A15 (unsupported yet) CPU cores,
which all have 64 bytes cache line size.
This is required to e.g. enable USB gadget.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
sunxi_usbc_vbus_detect was renamed to sunxi_usb_phy_vbus_detect but
g_dnl_board_usb_cable_connected was still using the old name, breaking the build
when USB gadget is enabled.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The ga10h is an 10" tablet with an A33 or A23 soc, 1G RAM, 8G or 16G nand,
sdio wifi, 2 micro usb ports, 1 otg and 1 host and 1 micro sd slot.
This commit adds a defconfig for the v1.1 pcb with an a33 soc.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
We've never tested the lvds panel support on sun6i+ SoCs until now, and
unsurprisingly the lvds code needed some fixes to work on my ga10h A33
tablet with lvds panel. This makes the panel on that tablet actually work.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Make DRAM_ODT_EN Kconfig setting a bool, add a separate DRAM_ODT_CORRECTION
setting for A23 SoCs and use DRAM_ODT_EN Kconfig everywhere instead of
only in dram_sun4i.c and hardcoding odt_en elsewhere.
Note this commit makes no functional changes for existing boards,
its purpose is to allow changing the odt_en value on future A33 boards.
For sun4i/sun5i/sun7i boards which set DRAM_ODT_EN=y (which no defconfigs
currently do) this patch turns on odt for both the DQ and the DQS lines,
whereas previously it was possibly (but not desirable) to turn odt on only
for one of them by setting the in DRAM_ODT_EN option to 1 or 2 instead of 3.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
When porting the allwinner dram init code to u-boot we missed some code
setting an extra bit when doing auto dram config.
This commits add this bit, fixing dram init not working on the ga10h
10" a33 tablet which I'm bringing up atm.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Add support for UART2 (2-pin version but note that RTS/CTS pins are available
pn that port for possible future use), can be selected in config
by using CONFIG_CONS_INDEX=3
Signed-off-by: Laurent Itti <laurentitti@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
On my A10 OlinuxIno Lime I noticed a huge (5+ seconds) delay coming from
console_init_r. This turns out to be caused by the preconsole buffer flushing
to the cfb_console. The Lime only has a 16 bit memory bus and that is already
heavy used to scan out the 1920x1080 framebuffer.
The problem is that print_pre_console_buffer() was printing the buffer once
character at a time and the cfb_console code then ends up doing a cache-flush
for touched display lines for each character.
This commit fixes this by first building a 0 terminated buffer and then
printing it in one puts() call, avoiding unnecessary cache flushes.
This changes the time for the flush from 5+ seconds to not noticable.
The downside of this approach is that the pre-console buffer needs to fit
on the stack, this is not that much to ask since we are talking about plain
text here. This commit also adjusts the sunxi CONFIG_PRE_CON_BUF_SZ to
actually fit on the stack. Sunxi currently is the only user of the pre-console
code so no other boards need to be adjusted.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
We don't need this on sunxi, as we always use calloc or memset when
initialised memory is required. Clearing this shaves some time of our
boot time.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Replace the hard-coded values for min/max/passive with values derived from
the CPU temperature grade.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
The MX6 has a temperature grade defined by OCOTP_MEM0[7:6] which is at 0x480
in the Fusemap Description Table in the reference manual. Return this value
as well as min/max temperature based on the value.
Note that the IMX6SDLRM and the IMX6SXRM do not indicate this in the
their Fusemap Description Table however Freescale has confirmed that these
eFUSE bits match the description within the IMX6DQRM and that they will
be added to the next revision of the respective reference manuals.
This has been tested with IMX6 Automative and Industrial parts.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
The IMX6 has four different speed grades determined by eFUSE SPEED_GRADING
indicated by OCOTP_CFG3[17:16] which is at 0x440 in the Fusemap Description
Table. Return this frequency so that it can be used elsewhere.
Note that the IMX6SDLRM and the IMX6SXRM do not indicate this in the
their Fusemap Description Table however Freescale has confirmed that these
eFUSE bits match the description within the IMX6DQRM and that they will
be added to the next revision of the respective reference manuals.
These have been tested with IMX6 Quad/Solo/Dual-light 800Mhz and 1GHz grades.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Commit fa8b7d66f49f0c7bd41467fe78f6488d8af6976a introduced fast-exit support
to the MMDC however enabling it on the DDR3 got missed. Make sure we enable
it on the DDR3 as well.
Gateworks uses Micron memory as well as Winbond in MX6. We have found in
testing that we need to enable fast-exit for Winbond stability. Gateworks
boards are currently the only boards using the MX6 SPL and enabling
fast-exit mode.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Fix below warning
arch/arm/imx-common/cpu.c:29:14: warning: ‘get_reset_cause’ defined but
not used
static char *get_reset_cause(void)
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: Eric Nelson <eric.nelson@boundarydevices.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Enable IOMUX_CONFIG_SION for all I2C pin mux settings, otherwise
we will get erros when doing i2c operations.
error log like the following:
"
wait_for_sr_state: failed sr=81 cr=a0 state=2020
i2c_init_transfer: failed for chip 0xb retry=1
"
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
The 'mx6-microsom' directory was only used for the previous mx6solo
hummingboard support, which has been removed in favour of the SPL
version.
Remove the remaining piece of the old mx6solo hummingboard support.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
The readenv() implementation of env_nand uses the mtd layer which is
unnecessary overhead in SPL when we already have a nand_spl_load_image()
function that doesn't need it. Using this instead eliminates the need
to provide a mtd_read for SPL env as well as reduces code (4KB savings in IMX6
SPL).
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Certain features we desire require a larger stack than is available by using
iRAM (most notably for us, env_mmc). Relocate the stack to DRAM so that
we can use these features.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
If the SPL is to be used for Falcon mode then we need to make sure the SPL
disable the GSC boot watchdog.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
If the SPL is to be used for Falcon mode then we need to make sure it
configures basic GPIO (iomux, padconf, and default output levels).
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Now that uart and i2c setup functions have been moved to common.c we can
use these and remove code duplication.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Avoid requiring board-model and probe pmic by its i2c address.
This is in preparation for being able to call pmic_setup() from SPL
and not need board type.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Move shared functions used by both SPL and U-Boot to common.c:
- setup_iomux_uart() and uart pad config
- gpio pad config
In the process also moved the following to common.c in preparation for
calling it from the SPL:
- split i2c setup into a shared function
- move pmic init to setup_pmic() function to call directly from
power_init_board()
- split gpio setup into early (iomux and default pin config)
and late (output configuration based on env)
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
PCI enumeration occurs early, before we fully configure our GPIO's. Make
sure we steer the MSATA/PCI mux to PCI in board_init to ensure PCI is
selected before enumeration.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
The re-assignment of pcie_rst gpio for GW522x needs to occur earlier, before
the PCI subsystem calls the toggle funciton.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Prior to using a gpio a call to gpio_request() should be called to register
it with the gpio subsystem.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Bootscripts for some distro's such as Android can benefit from knowing
what boot media its script was loaded from.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Having bit 22 cleared in the PL310 Auxiliary Control register (shared
attribute override enable) has the side effect of transforming Normal
Shared Non-cacheable reads into Cacheable no-allocate reads.
Coherent DMA buffers in Linux always have a Cacheable alias via the
kernel linear mapping and the processor can speculatively load cache
lines into the PL310 controller. With bit 22 cleared, Non-cacheable
reads would unexpectedly hit such cache lines leading to buffer
corruption.
This was inspired by a patch from Catalin Marinas [1] and also from recent
discussions in the linux-arm-kernel list [2] where Russell King and Rob Herring
suggested that bootloaders should initialize the cache.
[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2010-November/031810.html
[2] https://lkml.org/lkml/2015/2/20/199
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Since there is a default CONFIG_SYS_PBSIZE definition in config_fallbacks.h,
this setting is no longer required in board configurations.
Signed-off-by: Soeren Moch <smoch@web.de>
Only enable graphical output for stdout/stderr (and a usb keyboard for stdin)
when a hdmi device is detected.
Serial console is always enabled for stdin/stdout/stderr.
Signed-off-by: Soeren Moch <smoch@web.de>
Add support for USB OTG host mode. Only high speed devices supported so far
(e.g. usb 2.0 hub required to connect a keyboard).
Signed-off-by: Soeren Moch <smoch@web.de>
Hummingboard dual, dual-lite and solo are now supported via SPL mechanism.
Remove the previous hummingboard support, which does not use SPL and supported
only the solo variant.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
This fixes a regression caused by e25fbe3fe5
(gw_ventana: Move the DCD settings to spl code)
The clock gating must be setup prior to calling arch_cpu_init(). Without this
booting to SD (directly via eFuse or via bmode) will hang.
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Boards such as imx6q_sabresd might not have mapmem.h as part of
their common library. This causes a build error if the DEK blob
command is enabled.
Fix: make explicit the include of mapmem.h
Signed-off-by: Ulises Cardenas <Ulises.Cardenas@freescale.com>
Reviewed-by: Ruchika Gupta <Ruchika.gupta@freescale.com>
Prevent overflow by casting duty_ns to ull first. This bug came up when trying to create a 200 Hz PWM
Signed-off-by: Brecht Neyrinck <bnrn@psicontrol.com>
Acked-by: Heiko Schocher<hs@denx.de>
Starting USB initialization is useful for those who use Cuboxi/Hummingboard
with HDMI and USB keyboard.
However, when booting without a HDMI connection we can skip the usb
initialization, which makes the boot faster.
Signed-off-by: Jon Nettleton <jon.nettleton@gmail.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Tested-By: Vagrant Cascadian <vagrant@aikidev.net>
By making the tqma6_iomuxc_spi() weak, this patch adds the possibility to
add a different function for this SPI configuration. This can be used
by other baseboards, that might have a different SPI setup.
This patch will be used by the upcoming WRU-IV board support which also
uses the TQMa6 SoM.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch fixes the USB EHCI support on the TQMa6 SoM. Additionally
some filesystems are added, included the generic FS commands (e.g.
ls...).
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Markus Niebel <Markus.Niebel@tq-group.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-By: Markus Niebel <Markus.Niebel@tq-group.com>
Configure PAD_ENET_RXD0/RXD1 pads as pull down because these pads are directly
connected to the Atheros 8035/8030 although they should be functional
only in the RMII mode - 8030.
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Tested-By: Vagrant Cascadian <vagrant@aikidev.net>
mx6cuboxi sometimes fails to recognize the Ethernet PHY:
Net: Phy 0 not found
The explanation for this behavior comes from from Rabeeh Khoury:
"The LED_ACT pin on the carrier-one boards had a pull down that
forces the phy address to 0x0; where on CuBox-i and the production
HummingBoard that pin is connected directly to LED that depending
on the pull down strength of the LED it might be sampled as '0' or '1' thus
the phy address might appear as either address 0x0 or 0x4."
"This is AR8035 implementation; in reset stage the LED pin is configured as
input, and pull up/down does matter. In this case it configures the PHY
address.
After reset is deasserted the same LED pin becomes output and then
according to the previous pull/up it should be active high/low"
One way to properly fix this behavior is to place external pull-up/down
resistors in the LED line, but from a software standpoint we can fix it
by telling phy_find_by_mask() to scan the PHY at addresses
0x0 and 0x4.
Reported-by: Vagrant Cascadian <vagrant@aikidev.net>
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Tested-By: Vagrant Cascadian <vagrant@aikidev.net>
There are users of Cuboxi and Hummingboard that use these boards without
connecting them to a USB/serial adapter.
Allow such usage by allowing the HDMI port to act as stdout and USB keyboard
as stdin.
The serial console still also works as stdin/stdout.
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Tested-by: Vagrant Cascadian <vagrant@aikidev.net>
Add HDMI output using PLL5 as the source for the IPU clocks,
and accurate VESA timings.
These settings are based on the patch from Soeren Moch <smoch@web.de>
submitted for the tbs2910 mx6 based board.
It allows the display to work properly at 1024x768@60.
This should make the hdmi output signal compatible with most if not all
modern displays.
Signed-off-by: Jon Nettleton <jon.nettleton@gmail.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Tested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Tested-by: Vagrant Cascadian <vagrant@aikidev.net>
It is necessary to modify the configuration file for the target
board. It wasn't well documented that to enable any of the secure
boot modes, it is required to add CONFIG_SECURE_BOOT to the board
configuration file.
Also, fixed a typo in the encrypted boot section.
Signed-off-by: Ulises Cardenas <Ulises.Cardenas@freescale.com>
This is proposal for clamping the MMDC/DDR3 clocks to the maximum supported
frequencies as per imx6 SOC models, and for dynamically calculating valid
clock value based on mem_speed.
Currently the code uses impossible values for mem_speed (1333, 1600 MT/s) for
calculating the DDR timings, and uses fixed clock (528 or 400 MHz) which
doesn't take into account DDR3 memory limitations.
Signed-off-by: Nikolay Dimitrov <picmaster@mail.bg>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
This commit adds dtsi file for Sandbox PMIC.
It fully describes the PMIC by:
- i2c emul node - with a default settings of 16 registers
- 2x buck regulator nodes
- 2x ldo regulator nodes
The default register settings are set with preprocessor macros:
- VAL2REG(min[uV/uA], step[uV/uA], val[uV/uA])
- VAL2OMREG(mode id)
Both defined in file:
- include/dt-bindings/pmic/sandbox_pmic.h
The Voltage ranges of each regulator can be found in:
- include/power/sandbox_pmic.h
The new file is included into:
- sandbox.dts
- test.dts
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested on sandbox:
Tested-by: Simon Glass <sjg@chromium.org>
The file test.dts from driver model test directory,
was compiled by call dtc in script: test/dm/test-dm.sh.
This doesn't allow for including of dtsi files and using
of C preprocessor routines in this dts file.
Since the mentioned script builds U-Boot before tests,
then moving the test.dts file into sandbox dts directory
is reasonable.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested on sandbox:
Tested-by: Simon Glass <sjg@chromium.org>
This change adds new file to sandbox driver model test environment.
The file is: test/dm/power.c, and it includes tests for PMIC framework,
which includes PMIC uclass and REGULATOR uclass.
All tests are based od Sandbox PMIC emulated device. Some test constants for
this device are defined in the header: include/power/sandbox_pmic.h
PMIC tests includes:
- pmic get - tests, that pmic_get() returns the requested device
- pmic I/O - tests I/O by writing and reading some values to PMIC's registers
and then compares, that the write/read values are equal.
The regulator tests includes:
- Regulator get by devname/platname
- Voltage set/get
- Current set/get
- Enable set/get
- Mode set/get
- Autoset
- List autoset
For the regulator 'get' test, the returned device pointers are compared,
and their names are also compared to the requested one.
Every other test, first sets the given attribute and next try to get it.
The test pass, when the set/get values are equal.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested on sandbox:
Tested-by: Simon Glass <sjg@chromium.org>
This commit adds emulation of sandbox PMIC device, which includes:
- PMIC I2C emulation driver
- PMIC I/O driver (UCLASS_PMIC)
- PMIC regulator driver (UCLASS_REGULATOR)
The sandbox PMIC has 12 significant registers and 4 as padding to 16 bytes,
which allows using 'i2c md' command with the default count (16).
The sandbox PMIC provides regulators:
- 2x BUCK
- 2x LDO
Each, with adjustable output:
- Enable state
- Voltage
- Current limit (LDO1/BUCK1 only)
- Operation mode (different for BUCK and LDO)
Each attribute has it's own register, beside the enable state, which depends
on operation mode.
The header file: sandbox_pmic.h includes PMIC's default register values,
which are set on i2c pmic emul driver's probe() method.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested on sandbox:
Tested-by: Simon Glass <sjg@chromium.org>
The function get_emul() in sandbox i2c bus driver, always returns
first child as i2c emul device. This may only work for i2c devices
with a single child, which is an only i2c emul device.
In case when i2c device has more than one child (e.g. PMIC), and
one is i2c emul, then the function should search it by check uclass
id for each child. This patch add this change to the get_emul().
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
Tested on sandbox:
Tested-by: Simon Glass <sjg@chromium.org>
This commit cleanups the PMIC framework documentation.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested on sandbox:
Tested-by: Simon Glass <sjg@chromium.org>
This commit cleanups the regulator command.
The first change, is adjusting "regulator dev" command to use
"regulator-name" constraint, for setting the operating device.
Thanks to this, the regulator_get() function is removed.
This also updates do_list() function, with loop over uclass_find_*
function calls, to prevent probe of all listed regulators.
This also cleanups the printing in command.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested on sandbox:
Tested-by: Simon Glass <sjg@chromium.org>
This commit cleanups the use of function: failed().
The new function name is: failure(), and it is used
for print errno and the errno-related message only.
The second change is choosing PMIC device by it's name,
instead of seq number. Thanks to this change, for set
the current device, call of pmic_get() is enough.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested on sandbox:
Tested-by: Simon Glass <sjg@chromium.org>
This cleanup includes:
- remove of the preprocessor macros which pointed to long name functions
- update of the names of some regulator uclass driver functions
- cleanup of the function regulator_autoset()
- reword of some comments of regulator uclass header file
- regulator_get_by_platname: check error for uclass_find_* function calls
- add function: regulator_name_is_unique
- regulator post_bind(): check regulator name uniqueness
- fix mistakes in: regulator/Kconfig
- regulator.h: update comments
- odroid u3: cleanup the regulator calls
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested on sandbox:
Tested-by: Simon Glass <sjg@chromium.org>
The cleanup includes:
- pmic.h - fix mistakes in a few comments
- pmic operations: value 'reg_count' - redefine as function call
- fix function name: pmic_bind_childs() -> pmic_bind_children()
- pmic_bind_children: change the 'while' loop with the 'for'
- add implementation of pmic_reg_count() method
- pmic_bind_children() - update function call name
- Kconfig: add new line at the end of file
- Update MAX77686 driver code
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested on sandbox:
Tested-by: Simon Glass <sjg@chromium.org>
This change enables the configs required to init and setup max77686
regulator driver, using the new driver model pmic and regulator API.
And also changes the old pmic framework calls to the new ones.
This commits enables:
- CONFIG_ERRNO_STR
- CONFIG_DM_PMIC
- CONFIG_DM_PMIC_CMD
- CONFIG_DM_PMIC_MAX77686
- CONFIG_DM_REGULATOR
- CONFIG_DM_REGULATOR_CMD
- CONFIG_DM_REGULATOR_MAX77686
And removes the unused:
- CONFIG_DM_I2C_COMPAT
- CONFIG_POWER
- CONFIG_POWER_I2C
- CONFIG_POWER_MAX77686
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Adding regulators subnode to fdt max77686 node, allows properly init
regulators by the max77686 regulator driver. This enables the complete
functionality of the regulator command.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
In the power_init_board function call, regulator driver init is called,
so before compile, make sure that any power framework is defined.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Since this framework is still under the construction, the main
documentation is kept in the header files.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
This driver implements regulator operations for fixed Voltage/Current
value regulators. beside the standard regulator constraints, which are
put into the uclass platform data, a typical fixed regulator node provides
few additional properties like:
- gpio
- gpio-open-drain
- enable-active-high
- startup-delay-us
The only 'gpio' is used by this driver and is kept in structure of type
'fixed_regulator_platdata', as a device platform data (dev->platdata).
The driver implements:
- get_value
- get_current
- get_enable
- set_enable
The regulator calls and commands can be used for fixed-regulator devices,
and the proper error will be returned for prohibited.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
This commit adds support to MAX77686 regulator driver,
based on a driver model regulator's API. It implements
almost all regulator operations, beside those for setting
and geting the Current value.
For proper bind and operation it requires the MAX77686 PMIC driver.
New file: drivers/power/regulator/max77686.c
New config: CONFIG_DM_REGULATOR_MAX77686
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
This is the implementation of driver model PMIC driver.
The max77686 PMIC driver implements read/write operations and driver
bind method - to bind its childs.
This driver will try to bind the regulator devices by using it's child
info array with regulator prefixes and driver names. This should succeed
when compatible regulator driver is compiled. If no regulator driver found,
then the pmic can still provide read/write operations, and can be used with
PMIC function calls.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
This command is based on driver model regulator's API.
The user interface provides:
- list UCLASS regulator devices
- show or [set] operating regulator device
- print constraints info
- print operating status
- print/[set] voltage value [uV] (force)
- print/[set] current value [uA]
- print/[set] operating mode id
- enable the regulator output
- disable the regulator output
The 'force' option can be used for setting the value which exceeds
the constraints min/max limits.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
This is new command for the PMIC devices based on driver model PMIC API.
Command features are unchanged:
- list UCLASS pmic devices
- show or [set] operating pmic device (NEW)
- dump registers
- read byte of register at address
- write byte to register at address
The only one change for this command is 'dev' subcommand.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
This commit introduces the implementation of dm regulator API.
Device tree support allows for auto binding. And by the basic
uclass operations, it allows to driving the devices in a common
way. For detailed informations, please look into the header file.
Core files:
- drivers/power/regulator-uclass.c - provides regulator common functions api
- include/power/regulator.h - define all structures required by the regulator
Changes:
- new uclass-id: UCLASS_REGULATOR
- new config: CONFIG_DM_REGULATOR
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
This commit introduces the PMIC uclass implementation.
It allows providing the basic I/O interface for PMIC devices.
For the multi-function PMIC devices, this can be used as I/O
parent device, for each IC's interface. Then, each PMIC particular
function can be provided by the child device's operations, and the
child devices will use its parent for read/write by the common API.
Core files:
- 'include/power/pmic.h'
- 'drivers/power/pmic/pmic-uclass.c'
The old pmic framework is still kept and is independent.
For more detailed informations, please look into the header file.
Changes:
- new uclass-id: UCLASS_PMIC
- new config: CONFIG_DM_PMIC
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
This config name was never used, because the present pmic command
was precompiled for the CONFIG_POWER.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Move the configs listed below from exynos5-dt-common.h to exynos5-common.h:
- CONFIG_POWER
- CONFIG_POWER_I2C
fixes build break for Arndale and Smdk5250 boards.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
1. Introduce a new structure `struct mxc_i2c_bus`, this structure will
used for non-DM and DM.
2. Remove `struct mxc_i2c_regs` structure, but use register offset to access
registers based on `base` entry of `struct mxc_i2c_bus`.
3. Remove most `#ifdef I2C_QUIRK_REG`. Using driver_data to contain platform
flags. A new flag is introduced, I2C_QUIRK_FLAG.
4. Most functions use `struct mxc_i2c_bus` as one of the parameters.
Make most functions common to DM and non-DM, try to avoid duplicated code.
5. Support DM, but pinctrl is not included. Pinmux setting is still set
by setup_i2c, but we do not need bus_i2c_init for DM.
6. struct i2c_parms and struct sram_data are removed.
7. Remove bus_i2c_read bus_i2c_write prototype in header file. The frist
paramter of bus_i2c_init is modified to i2c index. Add new prototype
i2c_idle_bus and force_bus_idle. Since bus_i2c_init is not good for
DM I2C and pinctrl is missed, we use a weak function for i2c_idle_bus.
Board file take the responsibility to implement this function, like this:
"
int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus)
{
if (i2c_bus->index == 0)
force_bus_idle(i2c_pads_info0);
else if (i2c_bus->index == 1)
force_bus_idle(i2c_pads_info1);
else
xxxxxx
}
"
8. Introduce a weak function, enable_i2c_clk
9. Tested on an i.MX7 platform. Log info:
=> dm tree
Class Probed Name
----------------------------------------
root [ + ] root_driver
simple_bus [ ] |-- soc
simple_bus [ ] | |-- aips-bus@30000000
simple_bus [ ] | | |-- anatop@30360000
simple_bus [ ] | | `-- snvs@30370000
simple_bus [ ] | |-- aips-bus@30400000
simple_bus [ ] | `-- aips-bus@30800000
i2c [ ] | |-- i2c@30a20000
i2c [ ] | `-- i2c@30a40000
simple_bus [ ] `-- regulators
=> i2c dev 0
Setting bus to 0
=> i2c probe
Valid chip addresses: 08 50
=> i2c md 8 31
0031: 08 08 08 08 08 08 08 08 08 08 08 08 08 08 08 08
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Acked-by: Simon Glass <sjg@chromium.org>
These GPIO_PORTx macros should be in gpio.h, but not in imx-regs.h.
Also, imx-regs.h and iomux-v3.h has same macro defintion for
GPIO_PORTx, and both of them are included in mxc_i2c.c(include
mxc_i2c.h). This will incur build warnings with macro redefinition.
Since iomux-v3.h is not compatible with mx27, we can not simply
include iomux-v3.h for mx27, so move the GPIO_PORTx to gpio.h to
fix the build warning.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Now that the ohci code supports usb interrupt queues we can switch (back)
to using an usb interrupt queue for usb-kbd interrupt polling. This
greatly reduces u-boot's latency when dealing with usb keyboards.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Reviewed-by: Marek Vasut <marex@denx.de>
Add support for interrupt queues to the ohci hcd code, bringing it inline
with the ehci and musb-new(host) code.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Add an ohci_alloc_urb() function, this is a preparation patch for adding
interrupt queue support.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Marek Vasut <marex@denx.de>
When submitting interrupt packets to an endpoint we only link in the ed
once to avoid some races surrounding unlinking of periodic endpoints,
but we share one ohci_device struct / one set of ed-s for all devices,
which means that if we have an interrupt endpoint at endpoint 1 with one
device, and a non interrupt endpoint 1 with another device we end up
with the same ed linked into both the periodic and async lists, which is
not good (tm).
This commit switches over to using separate ohci_device structs, and thus
separate ed-s for devices with interrupt endpoints, fixing this.
This fixes e.g. matching a usb storage device and keyboard on the same
usb-1 hub not working.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Marek Vasut <marex@denx.de>
This fixes a warning in the print_buffer() function with some toolchains.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
This function should return a useful error for U-Boot, rather than -1.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
It is convenient for some boards to implement save_boot_params() in C rather
than assembler. Provide a way to return in this case.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Commit 47ed5dd0 dropped the .got section from U-Boot binaries. This is needed
for some relocations, and causes failures if missing. Add it back.
Signed-off-by: Simon Glass <sjg@chromium.org>
We can currently set this but there is no API function to get it. Add one.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Heiko Schocher<hs@denx.de>
This command was missed in the conversion. Add it back for driver model.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Heiko Schocher <hs@denx.de>
We maintain an accumulator for time spent reading from SPI flash, since
this can be significant on some platforms. Also add one for decompression
time.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Provide a function to detect USB device insertion/removal in order to
avoid having to do USB enumeration in a tight loop when trying to detect
peripheral hotplugging.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
This commit adds support for the OHCI companion controller, which makes
usb-1 devices directly plugged into to usb root port work.
Note for now this switches usb-keyboard support for sunxi back from int-queue
support to the old interrupt polling method. Adding int-queue support to the
ohci code and switching back to int-queue support is in the works.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
For some reason the ohci code is full with:
#ifdef DEBUG
pkt_print(...)
#else
mdelay(1);
#endif
AFAICT there is no reason for the mdelay(1) calls. This commit disables them
when building the ohci code for new driver-model using boards. It leaves
the mdelay(1) calls in place when building for older boards, so as to avoid
causing any regressions there.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The usb spec says that we must wait a minimum amount of time after port
power on (exact time is in the hub descriptor), this is something which
we must not only do for root ports but also for external hub ports, which
is why the common usb_hub code already waits a full second after powering
up ports. Having a separate wait for just the root hub in the ohci-hcd
code only leads to doing the waiting twice for the root ports, so drop the
wait from the ohci-hcd code.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The u-boot usb code uses polling for all endpoints, including interrupt
endpoints, so urbs should never be automatically resubmitted.
This also fixes a leak of the urb, as submit_int_msg() did not check if
an already re-submitted urb exists before creating a new one.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Marek Vasut <marex@denx.de>
USB scanning is slow, and there is no need to scan the companion buses
if no usb devices where handed over to the companinon controllers by any
of the main controllers.
This saves e.g. 2 seconds when booting a A10 OLinuxIno Lime with no USB-1
devices plugged into the root usb ports.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Simon Glass <sjg@chromium.org>
USB companion controllers must be scanned after the main controller has
been scanned, so that any devices which the main controller which to hand
over to the companion have actually been handed over before we scan the
companion.
As there are no guarantees that this will magically happen in the right
order, split the scanning of the buses in 2 phases, first main controllers,
and then companion controllers.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Simon Glass <sjg@chromium.org>
Move printing of usb scan status to usb_scan_bus().
This is a preparation patch for adding companion controller support to the
usb uclass.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Simon Glass <sjg@chromium.org>
Interrupt endpoints typically are polled for a long time by the usb
controller before they return anything, so calls to submit_int_msg() can
take a long time to complete this.
To avoid this the u-boot code has the an interrupt queue mechanism / API,
add support for this to the driver-model usb code and implement it for the
dm ehci code.
See the added doc comments for more details.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Simon Glass <sjg@chromium.org>
This is a preparation patch for adding interrupt-queue support to the
ehci dm code.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Simon Glass <sjg@chromium.org>
Short circuit the retry loop in legacy_hub_port_reset() by returning an
error from usb_control_msg() when a device was handed over to a companion
by the ehci code. This avoids trying to reset low / fullspeed devices 5
times needlessly. Also do not print an error when a device has been handed
over.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Propagate the error returned by submit_control_msg() rather then always
returning -EIO when the hcd code indicates an error.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
When after a reset the port status connection bit is still set and the enable
bit is not then we're dealing with a full-speed device and should hand it over
to the companion controller.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
With d6b72da0 we started including this file unconditionally. This
isn't allowed in a file that we also use on armv8. This will get
cleaned up a bit better once we really start using these same features
(and have similar fdt updates needed) on armv8.
Signed-off-by: Tom Rini <trini@konsulko.com>
The setexpr command used to segfault when accessing memory in sandbox.
The pointer accesses should be mapped.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
During the Kconfig conversion one of the changes was missed.
CONFIG_SPL_STACK_R should be CONFIG_SPL_STACK_R_ADDR since we want the
address.
Reported-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
All the Tegra boards borrow the files from board/nvidia/common/
directory, i.e., board/nvidia/common/* are not vendor-common files,
but SoC-common files.
Move NVIDIA common files to arch/arm/mach-tegra/ to clean up
Makefiles.
As arch/arm/mach-tegra/board.c already exists, this commit renames
board/nvidia/common/board.c to arch/arm/mach-tegra/board2.c,
expecting they will be consolidated as a second step.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Tom Warren <twarren@nvidia.com>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Upstream Linux is broken with default configs when PSCI, thus non-secure
mode is enabled. So the user should explicitly enable this mode, e.g.
when she disabled CONFIG_CPU_IDLE in Linux (in which case it's safe to
use). We can revert this workaround once Linux got fixed.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Make sure to enable the SMMU when booting the kernel in non-secure mode.
This is necessary because some of the SMMU registers are restricted to
TrustZone-secured requestors, hence the kernel wouldn't be able to turn
the SMMU on. At the same time, enable translation for all memory clients
for the same reasons. The kernel will still be able to control SMMU IOVA
translation using the per-SWGROUP enable bits.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
We only set CNTFRQ in arch_timer_init for the boot CPU. But this has to
happen for all cores.
Fixing this resolves problems of KVM with emulating the generic
timer/counter.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Tested-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Tom Warren <twarren@nvidia.com>
These registers can be used to prevent non-secure world from accessing a
megabyte aligned region of RAM, use them to protect the u-boot secure monitor
code.
At first I tried to do this from s_init(), however this inexplicably causes
u-boot's networking (e.g. DHCP) to fail, while networking under Linux was fine.
So instead I have added a new weak arch function protect_secure_section()
called from relocate_secure_section() and reserved the region there. This is
better overall since it defers the reservation until after the sec vs. non-sec
decision (which can be influenced by an envvar) has been made when booting the
os.
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
[Jan: tiny style adjustment]
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Tested-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This is based on Thierry Reding's work and uses Ian Campell's
preparatory patches. It comes with full support for CPU_ON/OFF PSCI
services. The algorithm used in this version for turning CPUs on and
off was proposed by Peter De Schrijver and Thierry Reding in
http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/210881. It
consists of first enabling CPU1..3 via the PMC, just to powergate them
again with the help of the Flow Controller. Once the Flow Controller is
in place, we can leave the PMC alone while processing CPU_ON and CPU_OFF
PSCI requests.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Tegra boards will have to initialize power management for the PSCI
support this way.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
In this case the secure code lives in RAM, and hence the memory node in
the device tree needs to be adjusted. This avoids that the OS will map
and possibly access the reservation.
Add support for setting CONFIG_ARMV7_SECURE_RESERVE_SIZE to carve out
such a region. We only support cutting off memory from the beginning or
the end of a RAM bank as we do not want to increase their number (which
would happen if punching a hole) for simplicity reasons
This will be used in a subsequent patch for Jetson-TK1.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
_sunxi_cpu_entry can be converted completely into a reusable
psci_cpu_entry. Tegra124 will use it as well.
As with psci_disable_smp, also the enabling is designed to be overloaded
in cased SMP is not controlled via ACTLR.
CC: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Tested-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Move parts of sunxi's psci_cpu_off into psci_cpu_off_common, namely
cache disabling and flushing, clrex and the disabling of SMP for the
dying CPU. These steps are apparently generic for ARMv7 and will be
reused for Tegra124 support.
As the way of disabled SMP is not architectural, though commonly done
via ACLTR, the related function can be overloaded.
CC: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Tested-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Will be required for obtaining the ID of the current CPU in shared PSCI
functions. The default implementation requires a dense ID space and only
supports a single cluster. Therefore, the functions can be overloaded in
cases where these assumptions do not hold.
CC: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Tested-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Tom Warren <twarren@nvidia.com>
At the very least when USB keyboard support is enabled, we need to enable
CONFIG_SYS_STDIO_DEREGISTER, so the "usb reset" is able to re-scan USB
ports and find new devices. Enable it everywhere per request from Simon
Glass.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
As best I can tell, CONFIG_SYS_LOAD_ADDR and CONFIG_LOADADDR/$loadaddr
serve essentially the same purpose. Roughly, if a command takes a load
address, then CONFIG_SYS_LOAD_ADDR or $loadaddr (or both) are the default
if the command-line does not specify the address. Different U-Boot
commands are inconsistent re: which of the two default values they use.
As such, set the two to the same value, and move the logic that does this
into tegra-common-post.h so it's not duplicated. A number of other non-
Tegra boards do this too.
The values chosen for these macros are no longer consistent with anything
in MEM_LAYOUT_ENV_SETTINGS. Regain consistency by setting $kernel_addr_r
to CONFIG_LOADADDR. Older scripts tend to use $loadaddr for the default
kernel load address, whereas newer scripts and features tend to use
$kernel_addr_r, along with other variables for other purposes such as
DTBs and initrds. Hence, it's logical they should share the same value.
I had originally thought to make the $kernel_addr_r and CONFIG_LOADADDR
have different values. This would guarantee no interference if a script
used the two variables for different purposes. However, that scenario is
unlikely given the semantic meaning associated with the two variables.
The lowest available value is 0x90200000; see comments for
MEM_LAYOUT_ENV_SETTINGS in tegra30-common-post.h for details. However,
that value would be problematic for a script that loaded a raw zImage to
$loadaddr, since it's more than 128MB beyond the start of SDRAM, which
would interfere with the kernel's CONFIG_AUTO_ZRELADDR. So, let's not do
that.
The only potential fallout I could foresee from this patch is if someone
has a script that loads the kernel to $loadaddr, but some other file
(DTB, initrd) to a hard-coded address that the new value of $loadaddr
interferes with. This seems unlikely. A user should not do that; they
should either hard-code all load addresses, or use U-Boot-supplied
variables for all load addresses. Equally, any fallout due to this change
is trivial to fix; simply modify the load addresses in that script.
Cc: Paul Walmsley <pwalmsley@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Paul Walmsley <pwalmsley@nvidia.com>
Reviewed-by: Simon Glass
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add full link training as a fallback in case the fast link training
fails.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add the PMIC, LCD settings, PWM and also show the board info at the top of
the LCD when starting up.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Connect up the clocks and the eDP driver to make these displays work with
Tegra124-based devices.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This interface is used on laptop devices based on Tegra. Add a driver which
provides access to the eDP interface. The driver uses the display port
uclass.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The SOR is required for talking to eDP LCD panels. Add a driver for this
which will be used by the DisplayPort driver.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add the various host1x peripherals to allow an eDP display to be connected.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
eDP (Embedded DisplayPort) is a standard widely used in laptops to drive
LCD panels. Add a uclass for this which supports a few simple operations.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
For digital displays (such as EDP LCDs) we would like to read the EDID
information and use that to set display timings. Provide a function to do
this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This file (from Linux 3.17) provides defines for display port. Use it so
that our naming is consistent with Linux.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add functions to provide access to the display clocks on Tegra124 including
setting the clock rate for an EDP display.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Create a function which sets the source clock for a peripheral, given
the number of mux bits to adjust. This can then be used more generally.
For now, don't export it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The get_pll() function can do the wrong thing if passed values that are
out of range. Add checks for this and add a function which can return
a 'simple' PLL. This can be defined by SoCs with their own clocks.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Instead of CONFIG_VIDEO_TEGRA, use CONFIG_LCD to determine whether an LCD
is present. Tegra124 uses a different driver.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This peripheral is required to get the LCD display running. Add it to
tegra124 and also bring in the binding file from Linux 3.18
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add required setup for the LCD display, and a function to provide the
board ID. This requires GPIOs to be available prior to relocation.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add support for this PMIC which is used on some Tegra124 boards.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Some LCDs require a PMIC to be set up - add a function for this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
With the full PMIC framework we may be able to avoid this. But for now
we need access to the PMIC.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This is only used by Nvidia boards, so move it into nvidia/common to
simplify things.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
When enabling a PWM, allow the existing clock rate and source to stand
unchanged.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This is needed for tegra124 also, so make it common and add a header file
for tegra124.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This is useful for display parameters. Add a simple decode function to read
from this device tree node.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
gpio_get_values_as_int() should return an error if something goes wrong.
Also provide gpio_claim_vector(), a function to request the GPIOs and set
them to input mode. Otherwise callers have to do this themselves.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Sort uclasses into alphabetical order and tidy up the comments.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
As doc/README.ARC says, pre-build ARC toolchains are available at
the Synopsys GitHub page.
The bin files are prefixed with arc(eb)-buildroot-linux- for earlier
releases, but with arc(eb)-snps-linux- for the latest releases.
The symbolic links prefixed with arc(eb)-linux- are also available
for all the release, so those prefixes can be used as the default
CROSS_COMPILE regardless of the toolchains version/variants.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
In order to reduce merge conflicts and to maintain the simplest possible
defconfig files, we should be using the savedefconfig feature of Kconfig
every time a new feature is added. This keeps the defconfig settings to
a minimum (only those things not default) and keeps them in the same
order as the Kconfig options.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Cc: Tom Rini <trini@konsulko.com>
By making the board selections optional, every defconfig will include
the board selection when running savedefconfig so if a new board is
added to the top of the list of choices the former top's defconfig will
still be correct.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Cc: Tom Rini <trini@konsulko.com>
As per the author, we don't need this patch really since the other patch
"stm32f4: fix serial output" superseded it.
This reverts commit 85e5f5b7a7.
Signed-off-by: Tom Rini <trini@konsulko.com>
Having this as a Kconfig allows it to be a dependent feature.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
As this board seems to be unmaintained for quite some time, and its
not moved to the generic board ingrastructure, lets remove it.
This will also enable us to remove the CONFIG_AUTOBOOT_DELAY_STR2
and CONFIG_AUTOBOOT_STOP_STR2 macros, as this sc3 board is the
only one using one of this macros. A removal patch will follow
soon.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Juergen Beisert <jbeisert@eurodsn.de>
Acked-by: Heiko Schocher <hs@denx.de>
This patch adds device tree support for arm pl010/pl011 driver.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Acked-by: Simon Glass <sjg@chromium.org>
Introduced in change d20a40de9d
"Roll crc32 into hash infrastructure"
The crc32 command with no -v expects an optional 3rd argument to be an
address to store the result in. With the -v switch, the last argument
is a crc, not an address. In the case where -v is set, we should set the
HASH_FLAG_ENV flag since that will first look for the value to be a
digest value, which matches the expected API for the crc32 command.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Introduced in change d20a40de9d
"Roll crc32 into hash infrastructure"
Use a consistent define to enable the verify feature in crc32 command.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Simon Glass <sjg@chromium.org>
This patch ignores the serial port static platform data at compilation time
in case of device tree control.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This patch adds device tree for the ST Micro stv0991 board & enables
device tree control. Progressively device tree support for the drivers
being used will also be added.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
U-Boot has been broken on Overo boards since commit
a6b541b090.
This is because the gd pointer is not set early enough anymore,
such that the i2c_set_bus_num in get_board_revision can safely
execute. This results in a console hang at SPL and the boot does
not proceed.
This piece of code is anyway necessary only for really old Overo
boards with revision numbers <= 2410 and not required for the newer
boards. For these older boards, u-boot v2014.10 still works fine.
Signed-off-by: Arun Bharadwaj <arun@gumstix.com>
This separates the SPL-specific code from the u-boot-specific code for
the Overo board following the discussion at
http://lists.denx.de/pipermail/u-boot/2015-April/211622.html
The code is split up into spl.c, overo.c and common.c (which
has the code common to both)
Signed-off-by: Arun Bharadwaj <arun@gumstix.com>
If regular NAND booting fails to find a valid uImage in the
kernel partition in NAND, try to boot using a zImage and dtb found
in a UBI volume in the rootfs partition. This is the NAND analog
of mmc zImage booting for device-tree based kernels.
Signed-off-by: Ash Charles <ashcharles@gmail.com>
Signed-off-by: Arun Bharadwaj <arun@gumstix.com>
Overo COMs have NAND flash that requires 4-bit ECC or better except for
the first sector which can use 1-bit ECC. The boot ROM expects to load
a payload from NAND written using 1-bit hardware-based ECC. In short,
write SPL to NAND something like this (4 times for redundancy):
#> nandecc hw
#> nand write ${loadaddr} 0x0 ${filesize}
#> nand write ${loadaddr} 0x20000 ${filesize}
#> nand write ${loadaddr} 0x40000 ${filesize}
#> nand write ${loadaddr} 0x60000 ${filesize}
Then, switch back to software-based BCH8 for everything else:
#> nandecc sw bch8
After [1], enlarge the max size of the SPL so the BCH code can fit.
[1] https://www.mail-archive.com/u-boot@lists.denx.de/msg163912.html
Signed-off-by: Ash Charles <ashcharles@gmail.com>
Fix the usage info from:
part part uuid <interface> <dev>:<part>
to
part uuid <interface> <dev>:<part>
Signed-off-by: Maxin B. John <maxin.john@enea.com>
Reviewed-By: Sjoerd Simons <sjoerd.simons@collabora.co.uk
Add the stm32F4 board's serial ports support.
User can use it easily.
The user only need to edit the number of the usart.
The patch also fix the serial print out.
Last, this version of patch fix the first patch checkpatch.pl error.
Thanks to Kamil Lulko.
Signed-off-by: kunhuahuang <huangkunhua@gmail.com>
This patch fix the serial output.
The source is from Kamil Lulko's "stm32f429-discovery board support"
Thanks, Varcain. I learned a lot.
Signed-off-by: kunhuahuang <huangkunhua@gmail.com>
This refactors spl_mmc_load_image to use a switch/case structure and easier
to understand spl_start_uboot checks. This also introduces some more automatic
fallback on the next mmc boot mode as long as it keeps failing.
Lines that go beyond 80 chars are also reduced by reducing the number of tabs.
Debug and error strings are refctored to match a common style.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
[trini: Fix a thinko in the SPL_EXT_SUPPORT + SPL_OS conversion, make part be
__maybe_unused]
Signed-off-by: Tom Rini <trini@konsulko.com>
usbupdate in real does allways load some script from usb-storage and execute
it, on all B&R targets.
So we do following 2 things:
- rename it to what it really does
- move it from boards to common environment
Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
Since we display in future the splash screen out of linux-os, we don't need
this support anymore within the common section.
But kwb-target is still using BMP_DISPLAY feature, so we move the related
from the common section into the target-specific.
Also the default environment of tseries will be adapted to this.
Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
Since the used AM3352 SoC doesn't have GPU it isn't allways necessary to build
in complete drm-stuff into linux kernel. In very small applications only we use
the simple-framebuffer.
So we have 2 use-cases:
- device operating on drm-driver (let simplefb node disabled)
- device operating on simplefb-driver (activate simplefb node and reserve mem)
The decision is made by means of "simplefb" environment variable.
simplefb = 0
we don't enable the (maybe) existing simplefb node and all the rest around
display is up to the linux-kernel. We just disable the backlight, beceause we
do not want see the flicker during take over of drm-driver.
simplefb = 1
we enable the (maybe) existing simplefb node and reserve framebuffers size
in memory.
Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
the CONFIG_LCD_NOSTDOUT feature never had become mainline in uboot due to the
fact that the problem of "not writing out whole console to lcd" can be solved
with another way.
So we remove this unnary define.
Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
We take use of the new LCD_ROTATION feature.
The information about how the display is rotated is taken from B&R specific
(/factory-settings/rotation) information in the devicetree.
The information there is stored as string (cw, ud, ccw, none) since starting
support of this devices and cannot be changed, so we have to convert it into
none = 0
cw = 1
ud = 2
ccw = 3
Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
The two tools that create android boot images, mkbootimg and the fastboot
client, set the kernel address by default to 0x10008000.
U-boot always honors this field, and will try to relocate the kernel to
whatever value is set in the header, which won't be mapped to the actual RAM on
most platforms, resulting in the kernel obviously not booting.
All the targets in U-Boot right now will download the android boot image to
CONFIG_SYS_LOAD_ADDR, which means that it will already have been downloaded to
some location that is suitable for execution.
In order to have the kernel booting even with the default boot image kernel
address, if that address is used, just execute the kernel where it is.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This patch fixes cross-compiling U-Boot tools with the musl C library:
* including <sys/types.h> is needed for ulong
* defining _GNU_SOURCE is needed for loff_t
Tested for target at91sam9261ek_dataflash_cs3.
Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks>
Cc: Tom Rini <trini@konsulko.com>
Across several devices network environment variables are duplicated.
Move these variables to a common include file which insures the environment
variables are reused and insures devices across product lines share the same
values.
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Switch to a more standard way of board select; put the SoC select
into arch/arm/Kconfig and move the board select menu under
arch/arm/mach-socfpga/Kconfig.
Also, consolidate SYS_BOARD, SYS_VENDOR, SYS_SOC, SYS_CONFIG_NAME.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Because all the SOCFPGA boards define CONFIG_SPL_FRAMEWORK
(see include/configs/socfpga_common.h), u-boot.img is automatically
added to the target image list by the top Makefile.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The compiler option "-Iboard/$(VENDOR)/$(BOARD)" just exists here
for iocsr_config.c to be able to include iocsr_config.h.
Use "..." instead of <...> to include a header in the same directory.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Default name of spi flash like this "0:0", update it to "spi_flash@0:0".
Signed-off-by: Haikun Wang <haikun.wang@freescale.com>
Acked-by: Simon Glass <sjg@chromium.org>
Sometimes the time functions are incorrect due to bad time support on a
board. Add a unit test which tries to detect this.
Signed-off-by: Simon Glass <sjg@chromium.org>
For the distro_bootcmds to succeed on the sandbox a bit of setup is
required (e.g. network configured or host image bound), so running them
by default isn't that useful.
Add a -b/--boot command to the sandbox binary, which triggers the
distro_bootcmds to run after the other command-line commands.
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: Simon Glass <sjg@chromium.org>
Interrupts transfers timing out is normal, so do not log an error for this.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Marek Vasut <marex@denx.de>
Add proper cache flushing / invalidating for non cache coherent cpus, for now
only enable this for new (driver-model) usb code to avoid regressions.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Non static function and variable declarations do not belong in a .h file.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Marek Vasut <marex@denx.de>
This is a preparation patch for adding driver-model support.
Note we do keep ohci_dev as a separate struct so that we can later add
support for interrupt-queues which requires allocating a separate ohci_dev
per interrupt-queue.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Marek Vasut <marex@denx.de>
devgone is never assigned a value, so the one comparisson reading it will
never be true, and devgone can be completely removed.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Marek Vasut <marex@denx.de>
This fixes descriptor reading of lowspeed devices through ohci not working.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Marek Vasut <marex@denx.de>
The GPIO driver didn't correctly compute the bank offset
from the GPIO number and caused random writes into the
GPIO block address space. Fix the driver so it actually
does the writes correctly. While at it, make use of the
clrsetbits_le32() mechanisms.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Without this usb-1 device descriptors do not get read properly.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Simon Glass <sjg@chromium.org>
The ehci driver model code for finding the first upstream usb-2 hub before
this commit has a number of issues:
1) "if (!ttdev->speed != USB_SPEED_HIGH)" does not work because the '!'
takes presedence over the '!=' this should simply be
"if (ttdev->speed == USB_SPEED_HIGH)"
2) It makes ttdev point to the first upstream usb-2 hub, but ttdev should
point to the last usb-1 device before the first usb-2 hub (when going
upstream from the device), as ttdev is used to find the port of the
first usb-2 hub to which the the last usb-1 device is connected.
3) parent_devnum however should be set to the devnum of the first usb-2
hub, so we need to keep pointers around to both usb_device structs.
To complicate things further during enumeration usb_device.dev will point
to the parent udevice, where as during normal use it will point to
the actual udevice, we must handle both cases correctly.
This commit fixes all this making usb-1 devices attached to usb-2 hubs,
including usb-1 devices attached to usb-1 hubs attached to usb-2 hubs, work.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Simon Glass <sjg@chromium.org>
Use usb_get_bus in dm ehci code rather then re-implementing it.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Simon Glass <sjg@chromium.org>
Currently we copy over a number of usb_device values stored in the on stack
struct usb_device probed in usb_scan_device() to the final driver-model managed
struct usb_device in usb_child_pre_probe() through usb_device_platdata, and
then call usb_select_config() to fill in the rest.
There are 3 problems with this approach:
1) It does not fill in enough fields before calling usb_select_config(),
specifically it does not fill in ep0's maxpacketsize causing a div by zero
exception in the ehci driver.
2) It unnecessarily redoes a number of usb requests making usb probing slower
3) Calling usb_select_config() a second time fails on some usb-1 devices
plugged into usb-2 hubs, causing u-boot to not recognize these devices.
This commit fixes these issues by removing (*) the usb_select_config() call
from usb_child_pre_probe(), and instead of copying over things field by field
through usb_device_platdata, store a pointer to the in stack usb_device
(which is still valid when usb_child_pre_probe() gets called) and copy
over the entire struct.
*) Except for devices which are explictly instantiated through device-tree
rather then discovered through usb_scan_device() such as emulated usb devices
in the sandbox.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Simon Glass <sjg@chromium.org>
Make usb_get_bus easier to use for callers, by directly returning the bus
rather then returning it via a pass-by-ref argument.
This also removes the error checking from the current callers, as
we already have an assert() for bus not being NULL in usb_get_bus().
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Simon Glass <sjg@chromium.org>
Do not use bus->seq before device_probe(bus), as bus->seq is not set until
after the device_probe() call. This fixes u-boot printing: "USB-1: " for
each bus it scans.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Simon Glass <sjg@chromium.org>
dm_gpio_set_dir_flags() will also set gpio output value when switching to
gpio output. So it's not necessary to call dm_gpio_set_value() after
dm_gpio_set_dir_flags() call.
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Simon Glass <sjg@chromium.org>
Sort these aliases to avoid confusion as to what is present.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Adjust this command so that it supports using driver model for I2C, i.e.
CONFIG_DM_I2C. This will permit it to be used in sandbox also.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add a driver which communicates with the sandbox I2C emulation RTC device
and permits it to be used in U-Boot. This driver is very simple - it just
reads and writes selected I2C registers in the device.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add a sandbox I2C emulation device which emulates a real-time clock. The
clock works off an offset from the current system time, and supports setting
and getting the clock, as well as access to byte-width regisers in the RTC.
It does not support changing the system time.
This device can be used for testing the 'date' command on sandbox, as well
as the RTC uclass.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add a uclass for real-time clocks which support getting the current time,
setting it and resetting the chip to a known-working state. Some RTCs have
additional registers which can be used to store settings, so also provide
an interface to these.
Signed-off-by: Simon Glass <sjg@chromium.org>
Move the definition of struct rtc_time into a separate file so that sandbox
can include it without requiring common.h and the like.
Signed-off-by: Simon Glass <sjg@chromium.org>
We don't need to use u8, and if we avoid it, it isn't so much of a problem
that rtc.h includes this header. With this change we can include rtc.h from
sandbox files.
Signed-off-by: Simon Glass <sjg@chromium.org>
Most callers unpack the structure and pass each member. It seems better to
pass the whole structure instead, as with the C library. Also add an rtc_
prefix.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Rename this function so that it is clear that it is provided by the RTC.
Also return an error when it cannot function as expected. This is unlikely
to occur since it works for dates since 1752 and many RTCs do not support
such old dates. Still it is better to be accurate.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Change this function name to something more descriptive. Also return a
failure code if it cannot calculate a correct value.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
At present this driver has a few test features. They are needed for running
the driver model unit tests but are confusing and unnecessary if using
sandbox at the command line. Add a flag to enable the test mode, and don't
enable it by default.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add driver model versions of the legacy functions to read and write a
single byte register. These are a useful shortcut in many cases.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
This comment should refer to SPI, not serial.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
With several chips using the SPI protocol it seems better to put the single
duplex functionality in the EC rather than the SPI driver.
Signed-off-by: Simon Glass <sjg@chromium.org>
Only set the speed if it has changed from last time. Since the speed will
be 0 when the device is probed it will always be changed on the first
transfer after the device is probed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Indicate to the emulated sandbox Ethernet driver when we expect a
timeout and tell it to leap forward.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Simon Glass <sjg@chromium.org>
When called, the next call to receive will trigger a 10-second leap
forward in time to avoid waiting for time to pass when tests are
evaluating timeout behavior.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Simon Glass <sjg@chromium.org>
Add a function that maintains an offset to include in the system timer
values returned from the lib/time.c APIs.
This will allow timeouts to be skipped instantly in tests
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Simon Glass <sjg@chromium.org>
Without this, when CONFIG_ENV_VARS_UBOOT_CONFIG is active we get
a compile time error when doing 'make env'.
In file included from tools/env/fw_env.c:117:0:
include/env_default.h:110:11: error: expected ‘}’ before ‘CONFIG_SYS_ARCH’
When building U-Boot this is included indirectly by the compiler switch
-include
/home/trdx/git.toradex.com/u-boot-2014.10-toradex/include/linux/kconfig.h
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
By removing this default build target, the "u-boot.kwb" target is not
automatically generated. This fixes a temporary build error when using
out-of-tree builds, as buildman does per default (reported by Simon).
When the full SPL support is added for these targets with the DDR training
code, the "u-boot-spl.kwb" image will be generated automatically.
Users providing a special bin_hdr binary (binary.0) file can always add
this binary file and generate the full firmware image by issuing the
"make u-boot.kwb" command directly.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
The macro to select the I2C address for ECC bus-width detection
was defined incorrectly for the Marvell DB-MV784MP-GP board. This
patch changes the macro to the correct value to fix this issue.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch adds support for the Marvell DB-88F6820-GP Armada A38x
evaluation board.
Supported peripherals are:
- UART
- Ethernet (mvneta)
- I2C
- SPI (including SPI NOR flash)
Please note that this board support right now only supports the
main U-Boot. Without the bin_hdr integration (DDR training etc). This
will be added in a few days / weeks to complete this board port. But
till then this U-Boot version can be run on the target via the
original Marvell U-Boot via this command:
tftpboot 4000000 db-88f6820-gp/u-boot.bin;go 4000000
Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Tested-by: Dirk Eibach <dirk.eibach@gdsys.cc>
This solves some RX problems that have been seen, when using the
mvneta ethernet driver. The cache needs to be reset into a "clean"
state before using it.
Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Tested-by: Dirk Eibach <dirk.eibach@gdsys.cc>
With the introduction of the Armada 38x support, its necessary to change
the mvneta ethernet driver init call from always 4 times to a
configurable value. Lets make this init call more flexible by moving
the actually used devices to the config header.
Additionally this patch takes care of the slightly different base
addresses for the ethernet controllers on A38x.
Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Tested-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This patch adds support for the Marvell Armada 38x SoC family.
Supported peripherals are:
- UART
- Ethernet (mvneta)
- I2C
- SPI (including SPI NOR flash)
Tested on Marvell DB-88F6820-GP evaluation board.
Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Tested-by: Dirk Eibach <dirk.eibach@gdsys.cc>
This way, new MVEBU boards don't need to specifiy the common location
for the SPL linker script.
Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Tested-by: Dirk Eibach <dirk.eibach@gdsys.cc>
This define is used by the DDR training code for Armada XP. With the
upcoming addition of Armada 38x support, lets only define it for
Armada XP in this common header.
Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Tested-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Since these files will be used for other MVEBU SoC's, lets reflect this
in the headers marcos as well.
Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Tested-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Move arch/arm/include/asm/arch-armada-xp/*
-> arch/arm/mach-mvebu/include/mach/*
Additionally the SYS_SOC is renamed from "armada-xp" to "mvebu". With this
change all these files can better be shared with other, newer Mavell
MVEBU SoC's. Like the upcoming Armada 38x support.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Tested-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Tested-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Move arch/arm/cpu/armv7armada-xp/* -> arch/arm/mach-mvebu/*
Since this platform will be extended to support other Marvell SoC's as
well, lets rename it directly to mvebu.
This will be used by the upcoming Armada 38x suport (A38x).
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Tested-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Tested-by: Dirk Eibach <dirk.eibach@gdsys.cc>
The get_timer_us() function is something which is no longer
existing in case we use generic timer framework, so replace
it with get_timer().
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Tyler Baker <tyler.baker@linaro.org>
If the mmc device is non-removable (as indicated by the device tree), set
the flag so that users of the device know.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
We need to clear the allocated memory explicitly as the included
struct sdhci_host has function pointers. Those are compared to NULL to
test if this (optional) feature is supported. Leaving them undefined let
u-boot jump to arbitrary memory.
Signed-off-by: Alexander Stein <alexanders83@web.de>
Freescale eMMC44 adapter card uses Micron N2M400FDB311A3CF eMMC
memory. According to the silicon datasheet, secure erase timeout
is 600ms. So increase erase timeout value from 250ms to 600ms.
Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com>
Cc: York Sun <yorksun@freescale.com>
Timeout interrupt also work for response busy command(R1b) like
cmd38/cmd6. So need to set it accordingly. Current code only
set timeout for data command.
Signed-off-by: Kevin Liu <kliu5@marvell.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
High capacity support is not a host capability, but a device capability
that is queried via the OCR. The flag in the operating conditions
request argument can just be set unconditionally. This matches the Linux
implementation.
[panto] Hand merged and renumbering MMC_MODE_DDR_52MHz.
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
Cc: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
Starting part of device initialization sets the init_in_progress flag
only if the MMC card did not yet come to ready state and needs to continue
polling. If the card is SD or if the MMC card became ready quickly,
the flag is not set and (if using pre-initialization) the starting
phase will be re-executed from mmc_init function.
Set the init_in_progress flag in all non-error cases. Also, move flags
setting statements around so that the flags are not set in error paths.
Also, IN_PROGRESS return status becomes unnecessary, so get rid of it.
Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
The polling loops in sd_send_op_cond and mmc_complete_op_cond functions
check the ready flag state at the end of the loop, that is after executing
a delay inside the loop, which, in case of exiting with no error,
is not needed. Also, one of these loops, as well as the loop
in mmc_send_status, have the delay just before exiting on timeout
conditions.
Restructure all these loops to check the respective conditions before making
a delay for the next loop pass, and to appropriately exit without the delay.
Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
Some MMC cards come to ready state quite quickly, so that the respective
flag appears to be set in mmc_send_op_cond already. In this case trying
to continue polling the card with CMD1 in mmc_complete_op_cond is incorrect
and may lead to unpredictable results. So check the flag before polling
and skip it appropriately.
Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
The previous change to use 'ocr' structure field for storing send_op_cond
command response also stopped using command response directly
outside of mmc_send_op_cond_iter(). Now it becomes possible to use
command structure in mmc_send_op_cond_iter() locally, removing a necessity
to pass it as an argument from the caller.
Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
The 'op_cond_response' field in mmc structure contains the response
from the last SEND_OP_COND MMC command while making iterational
polling of the card. Later it is copied to 'ocr' field, designed
to contain the OCR register value, which is actually the same
response from the same command. So, these fields have actually
the same data, just in different time periods. It's easier to use
the same 'ocr' field in both cases at once, without temporary using
of the 'op_cond_response' field.
Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
To replicate:
1. add to include/configs/p1_p2_rdb_pc.h "#define CONFIG_CMD_GPIO"
2. run `make P1020RDB-PC_defconfig`
3. run CROSS_COMPILE=powerpc-linux- make
and you will get:
common/built-in.o: In function `do_gpio':
u-boot/common/cmd_gpio.c:186: undefined reference to `gpio_request'
u-boot/common/cmd_gpio.c:194: undefined reference to `gpio_direction_input'
u-boot/common/cmd_gpio.c:195: undefined reference to `gpio_get_value'
u-boot/common/cmd_gpio.c:200: undefined reference to `gpio_get_value'
u-boot/common/cmd_gpio.c:203: undefined reference to `gpio_direction_output'
u-boot/common/cmd_gpio.c:209: undefined reference to `gpio_free
Signed-off-by: Michael Durrant <mdurrant@arcturusnetworks.com>
Signed-off-by: Oleksandr G Zhadan <oleks@arcturusnetworks.com>
Reviewed-by: York Sun <yorksun@freescale.com>
1. board/freescale/t4qds/t4_rcw.cfg
1.8GHz support is requested as default frequency, so update the rcw.
2. remove un-used configs
configs/T4160QDS_SPIFLASH_defconfig
configs/T4240QDS_SPIFLASH_defconfig
SPI boot is not available on T4QDS, so the configs should be removed.
3. board/freescale/t4qds/MAINTAINERS
Updated MAINTAINERS accordingly.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
[York Sun: revise subject]
Reviewed-by: York Sun <yorksun@freescale.com>
T2080RDB RevC uses new SODIMM 1867MT/s instead of previous 1600MT/s.
So update RCW to support new DDR frequency 1867MT/s by default.
Reserve the old 1600MT/s in comment for users in needed.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
The SD clock could be generated by platform clock or peripheral
clock for some platforms. This patch adds peripheral clock
support for T1024/T1040/T2080. To enable it, define
CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK.
Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com>
Cc: York Sun <yorksun@freescale.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Add adapter card type identification support by reading
FPGA STAT_PRES1 register SDHC Card ID[0:2] bits. To use this function,
define CONFIG_FSL_ESDHC_ADAPTER_IDENT.
Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com>
Cc: York Sun <yorksun@freescale.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
[York Sun: resolve conflicts in README.fsl-esdhc]
Reviewed-by: York Sun <yorksun@freescale.com>
CS4315 PHY doesn't support phy-reset by software, it
needs to reset it by hardware via CPLD control.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Function dp_ddr_restore is to restore the first 128-byte space
of DDR. However those codes may be optimized out by compiler
since the destination address is at 0x0. In order to avoid
compiler optimization, we restore the space from high address,
which is not at 0x0, to low address.
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This patch defines the 2 flush_dcache_range and invalidate_dcache_range
functions for all the powerpc architecture. Their implementation is
borrowed from the kernel's misc_32.S file and replace the ones from
mpc86xx and ppc4xx since they were equivalent.
This is a fix for the problem introduced by this patch:
http://patchwork.ozlabs.org/patch/448849/
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: York Sun <yorksun@freescale.com>
T1023RDB is a Freescale Reference Design Board that hosts the T1023 SoC.
T1023RDB board Overview
-----------------------
- T1023 SoC integrating two 64-bit e5500 cores up to 1.4GHz
- CoreNet fabric supporting coherent and noncoherent transactions with
prioritization and bandwidth allocation
- Memory: 2GB Micron MT40A512M8HX unbuffered 32-bit fixed DDR4 without ECC
- Accelerator: DPAA components consist of FMan, BMan, QMan, DCE and SEC
- Ethernet interfaces:
- one 1G RGMII port on-board(RTL8211F PHY)
- one 1G SGMII port on-board(RTL8211F PHY)
- one 2.5G SGMII port on-board(AQR105 PHY)
- PCIe: Two Mini-PCIe connectors on-board.
- SerDes: 4 lanes up to 10.3125GHz
- NOR: 128MB S29GL01GS110TFIV10 Spansion NOR Flash
- NAND: 512MB S34MS04G200BFI000 Spansion NAND Flash
- eSPI: 64MB S25FL512SAGMFI010 Spansion SPI flash.
- USB: one Type-A USB 2.0 port with internal PHY
- eSDHC: support SD/MMC card and eMMC on-board
- 256Kbit M24256 I2C EEPROM
- RTC: Real-time clock DS1339 on I2C bus
- UART: one serial port on-board with RJ45 connector
- Debugging: JTAG/COP for T1023 debugging
As well updated T1024RDB to add T1023RDB.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
[York Sun: fix defconfig files]
Reviewed-by: York Sun <yorksun@freescale.com>
Freescale PCIe controllers v3.0 and later need to set bit
CFG_READY to allow all inbound configuration transactions
to be processed normally when in EP mode. However, bit
CFG_READY has been moved from PCIe configuration space to
CCSR PCIe configuration register comparing previous version.
The patch is to set this bit according to PCIe version.
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
T2080QDS PEX1/Slot#1 will down-train from x4 to x2,
with SRDS_PRTCL_S1 = 0x66 and SRDS_PRTCL_S2 = 0x15.
Soft reset PCIe can fix this issue.
Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This patch adds SD boot support for T4240RDB board. SPL
framework is used. PBL initializes the internal RAM and
copies SPL to it. Then SPL initializes DDR using SPD and
copies u-boot from SD card to DDR, finally SPL transfers
control to u-boot.
Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
[York Sun: Fix T4240RDB_SDCARD_defcofig]
Reviewed-by: York Sun <yorksun@freescale.com>
Add a delay of 1 microsecond before issuing soft reset to the
controller to let ongoing ULPI transaction complete.
This prevents corruption of ULPI Function Control Register which
eventually prevents phy clock from entering to low power mode
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Commit 96d2bb952b ("powerpc/mpc85xx: Don't relocate exception vectors")
simplified IVOR initialization a bit too much, failing to use the
post-relocation offset. This doesn't cause a problem with normal NOR
boot, in which both the pre-relocation and post-relocation addresses
are 64 KiB aligned. However, if TEXT_BASE is only 4 KiB aligned, such
as for NAND/SD/etc. boot on some targets, as well as the QEMU target,
the post-relocation address will not be the same in the lower 16 bits,
as reserve_uboot() ensures that the relocation address is always 64
KiB aligned even if the pre-relocation address was not.
Use the GOT to get the proper post-relocation offsets.
Fixes: 96d2bb952b ("powerpc/mpc85xx: Don't relocate exception vectors")
Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Alexander Graf <agraf@suse.de>
Cc: Shaohui Xie <Shaohui.Xie@freescale.com>
Tested-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Once we add support for the ohci controller the phy-init and phy-power-on
functions may be called twice (once by the ehci code and once by the ohci
code) protect them against this.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The 2/3 usb-phys on the sunxi SoCs are really a single separate functional
block, and are modelled as such in devicetree. So once we've moved all the
sunxi usb code to the driver-model then phy_probe will be called once
for the entire block from the driver-model enumeration code.
Move to this now as this also avoids problems with phy_probe being called
multiple times once we introduce ohci support. This also allows us to get rid
of the sunxi_usb_phy_enabled_count variable as phy_probe now is guaranteed
to be called only once.
Since we're effectively rewriting the probe / remove functions, move them
to the end of the file while we are at it, as that is the most logical place
for them.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The usbc.? files now only contain usb-phy related code, rename them to make
this clear.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Rename the sunxi_usbc_foo functions to sunxi_usb_phy_bar to make it clear
that these are usb-phy functions. Also change the verbs & nouns in the suffix
to match the verbs & nouns used in the Linux kernels generic phy framework.
This patch purely renames things, it contains no functional changes.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
This is the only function left in sunxi/usbc.c which is not phy related,
so remove it.
This is a preparation patch for turning the usbc.c code into a proper
usb phy driver.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The sunxi "usbc" code is mostly about phy setup, but currently also sets up
the host controller clocks, which is something which really belongs in the
host controller drivers, so move it there.
This is a preparation patch for moving the sunxi ehci code to the driver
model and for adding ohci support.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Now that all sunxi boards are using driver-model for gpio (*), we can remove
the non driver-model support from the axp gpio code, and the glue to call
into the axp gpio code from the sunxi_gpio non driver-model code.
*) For the regular u-boot build, SPL still uses non driver-model gpio for
now, but the SPL never uses axp gpios support and we were already not building
axp-gpio support for the SPL.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
All sunxi boards now use the driver-model, so remove the non driver-model
code.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Now that we've everything prepared for it remove the DM settings from the
defconfig(s) and simply always set them for sunxi.
This makes all sunxi boards allways use the driver model for gpios and
ethernet, and allows us to move over more bits to the driver-model without
the need to introduce #ifdef-ery for boards which are not yet using DM.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
This is a preparation patch for switching all sunxi boards over to using
the driver model.
Note that rather then defining both CONFIG_DEFAULT_DEVICE_TREE (for u-boot)
and CONFIG_FDTFILE (for the kernel), this commit simply replaces all
CONFIG_FDTFILE defconfig settings with CONFIG_DEFAULT_DEVICE_TREE and
uses CONFIG_DEFAULT_DEVICE_TREE for setting the default fdtfile env value
in sunxi-common.h .
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
u-boot has support for a number of boards for which a dts file still needs
to be written, add minimal dts files for these boards so that we can switch
them over to driver-model / fdt.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
We need dts files for all boards we support, so bring in a few unmerged ones,
these will be replaced with the upstream merged versions the next time we
sync dts files.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Bring all the sunxi dts files (and update existing ones) from
mripard/sunxi/dt-for-4.1 (which will be merged into upstream master any
day now). This is necessary so that we can move all sunxi boards over to
the driver model.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Modify the sunxi-emac eth driver to support driver model.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Reviewed-by: Stefan Roese <sr@denx.de>
Besides being spelled wrong, the DMA_CPU_TRRESHOLD define actually has
nothing to do with DMA as we only use mmio fifo access. Rename it to
EMAC_RX_BUFSIZE to properly reflect what it does.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Reviewed-by: Stefan Roese <sr@denx.de>
Split all the core functionality out into functions taking a
struct emac_eth_dev *priv argument as preparation for adding driver-model
support.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Reviewed-by: Stefan Roese <sr@denx.de>
This is a preparation-patch for adding device-model support to the emac
driver.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Reviewed-by: Stefan Roese <sr@denx.de>
netdev.h should not be included in driver-model enabled builds (doing so
causes compiler warnings about struct eth_driver not being declared), but
we do use sunxi_gmac_initialize in the driver-model case, so move it out of
netdev.h .
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Add driver-model support to the axp_gpio code, note that this needs a small
tweak to the driver-model version of sunxi_name_to_gpio to deal with the
vbus detect and enable pins which are not standard numbered gpios.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Move the axp-gpio code out of the drivers/power/axp*.c code, and into
a new separate axpi-gpio driver.
This change drops supports for the gpio3 pin on the axp209, as that requires
special handling, and no boards are using it.
Besides cleaning things up by moving the code to a separate driver, as
a bonus this change also adds support for the (non vusb) gpio pins on the
axp221 and the gpio pins on the axp152.
The new axp-gpio driver gets its own Kconfig option, and is only enabled
on boards which need it. Besides that it only gets enabled in the regular
u-boot build and not for the SPL as we never need it in the SPL.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Add support for the axp152 and axp209 PMICs to the pmic register access
helpers. This is a preparation patch for moving the axp gpio code to a
separate gpio driver.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Move the register helpers used to access the registers via p2wi resp.
rsb bus on the otherwise identical axp221 and axp223 pmics to a separate
file, so that they can be used by the upcoming standalone axp gpio driver
too.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Change the axp_gpio_foo function prototypes to match the gpio uclass op
prototypes, this is a preparation patch for moving the axp gpio code to
a separate driver-model gpio driver.
Note that the ugly calls with a NULL udev pointer in drivers/gpio/sunxi_gpio.c
this adds are removed in a later patch.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
When doing a driver-model enabled build we still need sunxi_name_to_gpio_bank
(for now) for the mmc pinmux code in board/sunxi/board.c, so build it for
driver-model enabled builds too.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
We want to use driver-model/fdt with other model SoCs too, so add
compatible strings for the other SoCs to the dm sunxi gpio code.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Until sunxi moves to device tree (e.g. for USB) we need to convert named
GPIOs to numbers. Add a function to do this.
This fixes the USB / EHCI support not working on the LinkSprite pcDuino3
(which uses devicemodel).
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
By convention, sunxi GPIOs are named PA1, PA2 instead of A1, A2. Change
the driver model GPIO driver for sunxi to use these names.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
i2c_init_board() gets called before the driver-model (gpio) code is
initialized, so move the setup of the soft-i2c pins out of i2c_init_board()
and into board_init(), at which time the driver-model setup has been done.
Also add proper error checking and properly request the gpios as that is
mandatory with the driver-model.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The driver-model gpio functions may return another value then -1 as error,
make the sunxi display code properly handle this.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The driver-model gpio functions may return another value then -1 as error,
make the sunxi usbc properly handle this.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The driver-model gpio functions may return another value then -1 as error,
make the sunxi mmc code properly handle this.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
This fixes the following errors being printed during boot:
Error, wrong i2c adapter 0 max 0 possible
Error, wrong i2c adapter 0 max 0 possible
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Add a defconfig for generic 7" tablets using the Ippo q8h v1.2 pcb,
with an A33 SoC (the pcb can take an A23 or an A33), and a 1024x600 LCD.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Add support for the new second DRAM PLL found on the A33 SoC.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
This is a preparation patch for adding A33 support, which will have a
mach name of sun8i-a33.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
sun6i and newer (derived) SoCs such as the sun8i-a23, sun8i-a33 and sun9i
have a various things in common, like having separate ahb reset control
registers, the SID living inside the pmic, custom pmic busses, new style
watchdog, etc.
This commit introduces a new hidden SUNXI_GEN_SUN6I Kconfig bool which can be
used to check for these features avoiding the need for an ever growing list
of "#if defined CONFIG_MACH_SUN?I" conditionals as we add support for more
"new style" sunxi SoCs.
Note that this commit changes the behavior of the gmac and hdmi code for
sun8i and the upcoming sun9i devices. This does not matter as sun8i does
not have gmac nor hdmi, and sun9i has new hardware-blocks for these so
the old code will not work there.
Also this is intentional as if a sun8i / sun9i variant which does use the
old hwblocks shows up then the GEN_SUN6I code paths will be the right ones
to use.
For completeness this also adds a SUNXI_GEN_SUN4I bool for A10/A13/A20.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
We do not use irqs in u-boot so remove the unused irq field, and all the
#ifdef-ery around the irq initialization.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
There is no reason not to and this make the #ifdef-ery easier to read.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Enable the CPU uclass and Simple Firmware interface for Minnowbaord MAX. This
enables multi-core support in Linux.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This driver supports multi-core init and sets up the CPU frequencies
correctly.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This permits init of additional CPU cores after relocation and when driver
model is ready.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Since we do these sorts of operations a lot, it is useful to have a simpler
API, similar to clrsetbits_le32().
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Most modern x86 CPUs include more than one CPU core. The OS normally requires
that these 'Application Processors' (APs) be brought up by the boot loader.
Add the required support to U-Boot to init additional APs.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add a function to return the address of the Interrupt Descriptor Table.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
When we start up additional CPUs we want them to use the same Global
Descriptor Table. Store the address of this in global_data so we can
reference it later.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add a subset of this header file from Linux 4.0 to support atomic operations
in U-Boot.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add a simple command which provides access to a list of available CPUs along
with descriptions and basic information.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This provides a way of passing information to Linux without requiring the
full ACPI horror. Provide a rudimentary implementation sufficient to be
recognised and parsed by Linux.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
It is useful to be able to keep track of the available CPUs in a multi-CPU
system. This uclass is mostly intended for use with SMP systems.
The uclass provides methods for getting basic information about each CPU.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add a function similar to print_size() that works for frequencies. It can
handle from Hz to GHz.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Before adding one more function, create a separate header to help reduce
the size of common.h. Add the missing function comments and tidy up.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This is annoying during development and serves no useful purpose since
warnings are clearly displayed now that we are using Kbuild. Remove this
option.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Some device tree nodes do not have compatible strings but do require
drivers. This is pretty rare, and somewhat unfortunate. Add a function
to permit creation of a driver for any device tree node.
Signed-off-by: Simon Glass <sjg@chromium.org>
Now that reset_cpu() functions correctly, use it instead of directly
accessing the port on boards that use a Firmware Support Package (FSP).
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Now that reset_cpu() functions correctly, use it instead of directly
accessing the port.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Now that reset_cpu() functions correctly, use it instead of directly
accessing the port.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The existing code is pretty ancient and is unreliable on modern hardware.
Generally it will hang.
We can use port 0xcf9 to initiate reset on more modern hardware (say in the
last 10 years). Update the reset_cpu() function to do this, and add a new
'full reset' function to perform a full power cycle.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
U-Boot on coreboot does not have a driver for the PCH so cannot see the
SPI peripheral now that it has moved inside the PCH. Add a simple driver so
that SPI flash works again.
Signed-off-by: Simon Glass <sjg@chromium.org>
Currently all x86 boards still use CONFIG_SYS_EXTRA_OPTIONS to define
the text base address. Since it is deprecated, just remove it and use
CONFIG_SYS_TEXT_BASE directly.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Since all x86 boards have been converted to use DM_SPI and
DM_SPI_FLASH, move them to arch/Kconfig x86 section.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Remove the ending period of the MARK_GRAPHICS_MEM_WRCOMB option. Also
fix the indention of its help text.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Move platform-specific options under in arch/x86/Kconfig forward right
after the board-specific options but before any architecture-specific
options. When it comes to the same Kconfig option, board-specific one
takes take the highest precedence, then platform-specific one, and
finally architecture-specific one.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Let arch/x86/Kconfig prompt board vendor first, then select
the board model under that vendor. This way arch/x86/Kconfig
only needs concern board vendor and leave the supported target
list to board/<vendor>/Kconfig.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
By default the legacy segments (A0000h-B0000h, E0000h-F0000h)
do not decode to system RAM. Turn on the decode so that we can
write configuration tables in the F segment.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Previously the PIRQ routing table sanity check was performed against
the original table provided by the platform codes. Now we switch to
check its sanity on the final table in the F segment as this one is
the one seen by the OS.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
There are 6 banks:
4 banks for CORE: available in S0 mode
2 banks for SUS (Suspend): available in S0-S5 mode
Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
The descriptor provided with the FSP does not seem to work. Update the
instructions to use the descriptor from the original Intel firmware.
Signed-off-by: Simon Glass <sjg@chromium.org>
For x86, vga_info->BIOSImage points to 0xc0000 which cannot be freed.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
We should pass a u32 class number to pci_rom_probe() instead of a u16.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Implement Intel Queensbay platform-specific PIRQ routing support.
The chipset PIRQ routing setup is called in the arch_misc_init().
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
On x86 boards, platform chipset receives up to four different
interrupt signals from PCI devices (INTA/B/C/D), which in turn
will be routed to chipset internal PIRQ lines then routed to
8259 PIC finally if configuring the whole system to work under
the so-called PIC mode (in contrast to symmetric IO mode which
uses IOAPIC).
We add two major APIs to aid this, one for routing PIRQ and the
other one for generating a PIRQ routing table.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
We can write the configuration table in last_stage_init() for all x86
boards, but not with coreboot since coreboot already has them.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Add a function to assign an IRQ number to PCI device's interrupt
line register in its configuration space, so that the PCI device
can have its interrupt working under PIC mode after OS boots up.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Create a default e820 table with 3 entries which is enough to boot
a Linux kernel.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Since Intel ICH SPI driver has been converted to driver model, we need
add an alias for SPI node in the board dts files otherwise SPI flash
won't be detected due to 'invalid bus' error.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
For starting a Linux console on the superio serial port under
interrupt mode, the IRQ number must be configured.
Signed-off-by: Jian Luo <jian.luo4@boschrexroth.de>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Since all x86 boards use spi flash as its bootloader storage media,
it makes sense to make CONFIG_ENV_IS_IN_SPI_FLASH a common option.
So far only minnowmax board does not support it so undefine it in
its board configuration file.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
The prefix PCH was taken from ivybridge port. However Queensbay
platform official document does not mention PCH. It is composed
of TunnelCreek processor and Topcliff IOH chipset. For accuracy,
avoid using PCH prefix in the macro.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
The comment line in arch/arm/cpu/armv7/zynq/config.mk says that
the option "-mfpu=neon" is necessary for compiling lowlevel_init.S.
We do not have to give it to all the source files.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Provide an option to write filesystem independend commands.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Added the SPI driver support for ZynqMP
The controller is same as zynq SPI controller
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Enable the i2c driver for ZynqMP
Also enable the eeprom for read and writes
to eeprom on ZynqMP
ZynqMP uses the same i2c controller as in Zynq
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Fix wrong timer calculation in get_timer_masked incase of
overflow.
This fixes the issue of getting wrong time from get_timer()
calls.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Remove the quirk SDHCI_QUIRK_NO_CD as it is not
required.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add support for loading sw for R5 with enabling for zynqmp.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Disable all level shifters before enabling
the PS-to-PL level shifters as it would
be good to disable all level shifters before
enabling the PS-to-PL in order to ensure that
it is in proper state
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
We are about to change the location for ps7_init files, breaking the
current work-flows. It is good time to drop the legacy ps7_init.c/h
support.
Going forward, please use ps7_init_gpl.c/h all the time.
If you are still using old Xilinx tools that are only able to
generate ps7_init.c/h, rename them into ps7_init_gpl.c/h.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Suggested-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The PicoZed is a System-on-Module board which is marketed as part of
the ZedBoard/MicroZed/etc. collection. It includes a Zynq-7000
processor.
This patch adds support that covers all the variants of the PicoZed
including the SKUs with Z7010/Z7020 and Z7015/Z7030 Zynq chips. This
patch set however only covers support for the System-on-Module and does
not cover any extra components that are available on carrier boards
(except those that are fanned out of the module itself).
More information on this board, its variants and available carrier
boards is available at: http://zedboard.org/product/picozed
Signed-off-by: Nathan Rossi <nathan.rossi@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
On slow platforms not all baudrate setting is valid.
Check it directly in the driver and setup maximum possible
frequency.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Most of the code is taken (and adapted) from Linux kernel driver.
Just add CONFIG_ZYNQ_GPIO to you config to enable it
Signed-off-by: Andrea Scian <andrea.scian@dave.eu>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
It is possible for CONFIG_XILINX_EMACLITE to be defined without
XILINX_EMACLITE_BASEADDR being defined as the EMAC Lite driver support
OF init. Check that the driver is enabled and the base address is
available before initializing with a static base address.
Signed-off-by: Nathan Rossi <nathan.rossi@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
These functions now rely on uclass_find_first/next_device() and assume that
they will either return failure (-ve error code) or a device. In fact,
coming to the end of a list is not considered failure and they return 0
in that case.
The logic to deal with this was replaced in commit acb9ca2a with just using
uclass_get_device_tail(). Add back the missing logic. This bug was
caught by unit tests but since they were broken for other reasons at the
time, this was not noticed.
Signed-off-by: Simon Glass <sjg@chromium.org>
This was accidentally added by commit dd0b0122ba
"serial: ns16550: Add an option to specify the debug UART register shift".
Remove it.
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Simon Glass <sjg@chromium.org>
Upto now flash sector_size is assigned from params which isn't
necessarily a sector size from vendor, so based on the SECT_*
flags from flash_params the erase_size will compute and it will
become the sector_size finally.
Bug report (from Bin Meng):
=> sf probe
SF: Detected SST25VF016B with page size 256 Bytes, erase size 4 KiB,
total 2 MiB, mapped at ffe00000
=> sf erase 0 +100
SF: 65536 bytes @ 0x0 Erased: OK
Signed-off-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Reported-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
With SPI flash moving to driver model, commit fbb0991 "dm: Convert
spi_flash_probe() and 'sf probe' to use driver model" ignored the
SST flash-specific write op (byte program & word program), which
actually broke the SST flash from wroking.
This commit makes SST flash work again under driver model, by adding
SST flash-specific handling in the spi_flash_std_write().
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Add a new member 'flags' in struct spi_flash to store the flash flags
during spi_flash_validate_params().
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Instead of hardcoding the 'fdtfile' variable, let's detect the SoC and
board variant on the fly and change the dtb name.
Based on the scheme done on am335x board.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Tested-By: Vagrant Cascadian <vagrant@debian.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
README file suggests to use 'fdtfile' for the dtb file name and
'fdt_addr_r' for the dtb address in RAM, so do as suggested.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Introduce is_hummingboard() function that reads GPIOs that can distinguish
between Cubox-i and Hummingboard.
Print the board name accordingly.
Based on a patch from Rabeeh Khoury.
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Cubox-i and Hummingboard support several MX6 SoCs: mx6solo, mx6dual-lite,
mx6dual and mx6quad. Add support for the different SoC/memory sizes
combinations.
DDR initialization values were extracted from Solid-run internal U-boot.
Tested on a CuBox-i4Pro, HummingBoard-i2eX and HummingBoard-i1.
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Cubox-i and Hummingboard support several MX6 SoCs: mx6solo, mx6dual-lite,
mx6dual and mx6quad.
Use IOMUX_PADS() macro in order to prepare for the multi-SoC support.
Also pass 'MX6QDL' in the defconfig to indicate it.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Add device-tree handover to Linux kernel conforming with MIPS UHI [1].
Register $a0 will be set to the reserved value -2. The address of
the device-tree blob will be stored as KSEG0 address in $a1. $a2 and
$a3 are set to zero.
[1] http://prplfoundation.org/wiki/MIPS_documentation
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
After syncing the sunxi dts files with the upstream kernel dm/fdt sunxi
builds would no longer boot.
The problem is that stdout-path is now set like this in the upstream dts
files: stdout-path = "serial0:115200n8". The use of options in of-paths,
either after an alias name, or after a full path, e.g. stdout-path =
"/soc@01c00000/serial@01c28000:115200", is standard of usage, but something
which the u-boot dts code so far did not handle.
This commit fixes this, adding support for both path formats.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Simon Glass <sjg@chromium.org>
This erratum requires setting GLITCH_EN bit in debug register to
enable digital filter to improve clock stability.
Signed-off-by: York Sun <yorksun@freescale.com>
CC: Heiko Schocher <hs@denx.de>
Enable NAND boot support using SPL framework. To boot from
NAND, either use DIP switches on board, or "qixis_reset nand"
command. Details of forming NAND image can be found in README.
Signed-off-by: Scott Wood <scottwood@freescale.com>
[York Sun: Remove +S from defconfig after commit 252ed872]
Signed-off-by: York Sun <yorksun@freescale.com>
This adds NAND boot support for LS2085AQDS, using SPL framework.
Details of forming NAND image can be found in README.
Signed-off-by: Scott Wood <scottwood@freescale.com>
[York Sun: Remove +S from defconfig after commit 252ed872]
Signed-off-by: York Sun <yorksun@freescale.com>
IFC has two register pages.Till IFC version 1.4 each
register page is 4KB each.But IFC ver 2.0 register page
size is 64KB each.IFC regiters structure is break into
two viz FCM and RUNTIME.FCM(Flash control machine) registers
are defined in PAGE0 and controls IFC generic functionality.
RUNTIME registers are defined in PAGE1 and controls NAND and
GPCM funcinality.
FCM and RUNTIME structures defination is common for IFC
version 1.4 and 2.0.
Signed-off-by: Jaiprakash Singh <b44839@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Add support of ethernet:
- eth.c: mapping lane to slot for (0x2A, 0x07)
- ls2085a.c: To enable/disable dpmac and get link type
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
This adds initial support for Colibri VF50/VF61 based on Freescale
Vybrid SoC.
- CPU clocked at 396/500 MHz
- DDR3 at 396MHz
- for VF50, use PLL2 as memory clock (synchronous mode)
- for VF61, use PLL1 as memory clock (asynchronous mode)
- Console on UART0 (Colibri UART_A)
- Ethernet on FEC1
- PLL5 based RMII clocking (E.g. No external crystal)
- UART_A and UART_C I/O muxing
- Boot from NAND by default
Tested on Colibri VF50/VF61 booting using serial loader over UART.
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Acked-by: Stefan Agner <stefan@agner.ch>
Enables caches which provides a rather huge speedup of the boot loader.
Also mark the on-chip RAM as cachable since this is the area U-Boot runs
from.
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Vybrid product family consists of several rather similar SoC which
can be determined by softare during boot time. This allows use of
variable ${soc} for Linux device tree files. Detect VF5xx CPU's by
reading the CPU count register. We can determine the second number
of the CPU type (VF6x0) which indicates the presence of a L2 cache.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Enable the SCSC (Slow Clock Source Controller) and select the external
32KHz oscillator. This improves the accuracy of the RTC.
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
In order to avoid code duplication, move the DDR3 initialization to the
common place under imx-common. Currently ROW_DIFF and COL_DIFF can be
chosen from the board file. The JEDEC timings are specified using a
common ddr3_jedec_timings structure.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Some RTC chips tend to set garbage date after reset.
This patch sets the date to 2000-01-01 00:00 immediatelly
after the RTC chip reset is issued using the "date reset"
command.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Add architecture-specific u-boot.lds and remove all board-specific
u-boot.lds.
All the .text customization that was board-specific have been
moved inside the related include/configs, inside a
LDS_BOARD_TEXT define.
Signed-off-by: Angelo Dureghello <angelo@sysam.it>
Implemented fb_set_reboot_flag() for OMAP5 to set
an environment variable 'dofastboot' when reboot-bootloader called.
This environment variable will be checked in boot command and fastboot
will be called if the variable is set.
If the bootcmd env variable of OMAP5 common is overwritten with board-specific
command, then these changes will not apply.
This was originally intended for DRA7 platform, but now applies to all OMAP5.
Ref:
http://git.omapzoom.org/?p=repo/u-boot.git;a=commit;h=19da2e436e9806259cf1f4988b9e046ab256bf2c
Signed-off-by: Angela Stegmaier <angelabaker@ti.com>
Signed-off-by: Dileep Katta <dileep.katta@linaro.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
[trini: Make it check for !CONFIG_ENV_IS_NOWHERE as we can't saveenv()
in that case]
Signed-off-by: Tom Rini <trini@konsulko.com>
For the local project, we may specified format.subjectprefix setting.
Then the patch will be formated as [Project_prefix][PATCH].
But patman will not check this setting. It will remove the
format.subjectprefix.
So This patch will let patman check this setting and add it as a
project prefix.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Also read gcc 4.9.0 at kernel.org which also have Microblaze toolchain.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Fixed unit test failure by updating the test:
Signed-off-by: Simon Glass <sjg@chromium.org>
The Marvell GPIO driver can be used on Marvell platforms other than
Sheeva, so remove the ifdef to enable it for others.
Signed-off-by: Rob Herring <robh@kernel.org>
1. The bits 11..10 for mfp driver strength is only valid for
aspen and old xscale family, for newer Marvell chip, this range
has been moved to 12..11.
2. add sleep bit support
Signed-off-by: Xiang Wang <wangx@marvell.com>
[robh: rebase to current mainline]
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Peter Howard <phoward@gme.net.au>
[trini: Add config file, update for ..._ether_addr() -> ..._ethaddr() rename]
Signed-off-by: Tom Rini <trini@konsulko.com>
The LS2085AQDS is an evaluatoin platform that supports the LS2085A
family SoCs. This patch add basic support of the platform.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Wire rate IO Processor (WRIOP) provide support of receive and transmit
ethernet frames from the ethernet MAC. Here Each WRIOP block supports
upto 64 DPMACs.
Create a house keeping data structure to support upto 16 DPMACs and
store external phy related information.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
The memac for PHY management on little endian SoCs is similar on big
endian SoCs, so we modify the driver by using I/O accessor function to
handle the endianness, so the driver can be reused on little endian
SoCs, we introduce CONFIG_SYS_MEMAC_LITTLE_ENDIAN for little endian
SoCs, if the CONFIG_SYS_MEMAC_LITTLE_ENDIAN is defined, the I/O access
is little endian, if not, the I/O access is big endian. Move fsl_memac.h
out of powerpc include.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Changed MC firmware loading to comply with the new MC boot architecture.
Flush D-cache hierarchy after loading MC images. Add environment
variables "mcboottimeout" for MC boot timeout in milliseconds,
"mcmemsize" for MC DRAM block size. Check MC boot status before calling
flib functions.
Signed-off-by: J. German Rivera <German.Rivera@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Add support of SerDes framework for Layerscape Architecture.
- Add support of 2 SerDes block
- Add SerDes protocol parsing and detection
- Create table of SerDes protocol supported by LS2085A
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Fix flush_dcache_range() input parameter to use start and end addresses.
Change ethernet interface name to DPNI. Update entry criteria for
ldpaa_eth_stop. Ethernet stack first stop the device before performing
next operation. At the time of Ethernet driver registration,
net_dev->state is set as ETH_STATE_INIT So take care net_dev->state as
ETH_STATE_INIT in ldpaa_eth_stop.
Undef CONFIG_PHYLIB temorarily because ldpaa_eth driver currently does
not support PHYLIB.
Instead of clearing pull descriptor one time, clear it before issuing any
volatile dequeue command.
Volatile command does not return frame immidiately, wait till a frame
is available in DQRR. This frame can be valid or expired.
Flush buffer before releasing to BMan ensure the core does not have any
cachelines that the WRIOP will DMA to.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: pankaj chauhan <pankaj.chauhan@freescale.com>
Signed-off-by: Roy Pledge <Roy.Pledge@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
The serial nodes in the fsl-lsch3 device trees have compatible =
"fsl,ns16550", "ns16550a" -- so don't look for "ns16550".
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Without this "USB may not work" according to the erratum text, though I
did not notice a problem without it.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
During booting, IFC is mapped to low region. After booting up, IFC is
remapped to high region for larger space. The environmental variables are
also stored at high region. In order to read the variables during booting,
a virtual mapping is required.
Cache was enabled for entire IFC space before. Actually the first two
entries are big enough (4MB) to cover the boot code and environmental
variables. Remove extra entries. Move OCRAM entry out of ifdef.
Signed-off-by: York Sun <yorksun@freescale.com>
The timer clock is system clock divided by 4, not fixed 12MHz.
This is common to the SoC, not board specific. Primary core is
fixed when u-boot still runs in board_f. Secondary cores are
fixed by reading a variable set by u-boot.
Signed-off-by: York Sun <yorksun@freescale.com>
CC: Mark Rutland <mark.rutland@arm.com>
Platform clock is half of platform PLL. There is an additional divisor
in place. Clean up code copied from powerpc.
Signed-off-by: York Sun <yorksun@freescale.com>
ls2085a_common.h contains hard-coded information for NOR/NAND flash,
I2C, DDR, etc. These are platform specific. Move them out of common
header file and placed into respective board header files.
Move TEXTBASE to 1MB offset to fit NOR flash with up to 1MB sector
size.
Enable command auto complete. Update prompt symbol. Set fdt_high to
0xa0000000 because Linux requires that the fdt be 8-byte aligned
and below 512 MiB. Besides ensuring compliance with the 512 MiB
limit, this avoids problems with the dtb being misaligned within
the FIT image.
Change the MC FW, MC DPL and Debug server NOR addresses in compliance
with the NOR flash layouts for 128MB flash.
Add PCIe macros. Enable "loadb" command. Disable debug server.
Enable workaround for erratum A008511.
Stop reset on panic for postmortem debugging.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Generic Timer may contain an erroneous value. The workaround is to
read it twice until getting the same value.
Signed-off-by: York Sun <yorksun@freescale.com>
This erratum only applies to general purpose DDR controllers in LS2.
It shouldn't be applied to DP-DDR controller. Check DDRC versoin number
before applying workaround.
Signed-off-by: York Sun <yorksun@freescale.com>
Add built-in memory test to catch errors after DDR is initialized, before
any other transactions. To enable this test, define CONFIG_FSL_DDR_BIST.
An environmental variable "ddr_bist" is checked before starting test.
It takes a while (several seconds) depending on system memory size.
Signed-off-by: York Sun <yorksun@freescale.com>
CS0 was not allowed to be empty by u-boot driver in the past to simplify
the driver. This may be inconvenient for some debugging. This patch lifts
the restrictions. Controller interleaving still requires CS0 populated.
Signed-off-by: York Sun <yorksun@freescale.com>
Add/update registers for DDR4, including DQ mappings. Allow raw timing
method used for all controllers. Update mode_9 register to 0x500 for
improved stability. Check DDR controller version number individually
in case a SoC has multiple DDR controllers of different versions.
Increase read-write turnaround for DDR4 high speeds.
Signed-off-by: York Sun <yorksun@freescale.com>
Some SoCs have more than two I2C busses. Instead of adding ifdef
to the driver, macros are put into board header file where
CONFIG_SYS_I2C_MXC is defined.
Signed-off-by: York Sun <yorksun@freescale.com>
CC: Heiko Schocher <hs@denx.de>
IFC 2.0 doubled the SRAM size, which means double the number of
ECCSTAT registers. Fix the resulting array overflow.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
For fsl-lsch3, IFC is binded with address within 32-bit at fist.
After u-boot relocates to DDR, CS1, CS3 can be binded to higher
address to support large space.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
LDPAA Ethernet driver is a freescale's new ethernet driver based on
Layerscape architecture.
Every ethernet driver controls on DPNI object. Where all DPNIs share
one common DPBP and DPIO object to support Rx and Tx flows.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
CC: Cristian Sovaiala <cristian.sovaiala@freescale.com>
CC: Bogdan Hamciuc <bogdan.hamciuc@freescale.com>
CC: J. German Rivera <German.Rivera@freescale.com>
[York Sun: s/NetReceive/net_process_received_packet]
Reviewed-by: York Sun <yorksun@freescale.com>
Some boards cannot support device tree due to lack of memory. Add an option
to allow these boards to continue to work (and even use driver model).
This is a 'negative' option since most boards are expected to support device
tree in SPL.
Signed-off-by: Simon Glass <sjg@chromium.org>
There is little reason to split these two functions. Bring them together
which simplifies the init sequence.
Signed-off-by: Simon Glass <sjg@chromium.org>
When CONFIG_DM_DEVICE_REMOVE is not enabled, such as in SPL, we cannot
remove or unbind devices and do not expect to get errors when binding
and probing devices. So drop the error path to reduce code size.
Signed-off-by: Simon Glass <sjg@chromium.org>
The printf() in panic() adds about 1.5KB of code size to SPL when compiled
with Thumb-2. Provide a smaller version that does not support printf()-style
arguments and use it in two commonly compiled places.
Signed-off-by: Simon Glass <sjg@chromium.org>
The CONFIG_DM_DEVICE_REMOVE option takes out code related to removing
devices. It should also remove the 'unbind' code since if we cannot
remove we probably don't need to unbind.
Signed-off-by: Simon Glass <sjg@chromium.org>
In many cases SPL only uses a single serial port and there is no need for
alias sequence support. We will just use the serial port pointed to by
stdout-path in the /chosen node.
Signed-off-by: Simon Glass <sjg@chromium.org>
This reverts commit 562f8df18d.
Note: Even un-reverting this patch couldn't works as expected, based
on the latest testing from Heiko Schocher.
Signed-off-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Cc: Heiko Schocher <hs@denx.de>
This patch extends the U-Boot "led" command to support automatic blinking
by setting a blink frequency in milliseconds. Additionally the number of
supported LEDs is increased to 6 (0...5).
This will be used by the PCA9551 LED driver.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
This assignment conflicts with code that add flags with
gd->flags |= FOO prior to the execution of this function.
Seems like a historical artifact and creates bugs with
early alloc().
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Simon Glass <sjg@chromium.org>
Select integrator boards by the combination of platform select (AP/CP)
and core module select (CM720T, CM920T, ...).
This allows us to remove CONFIG_SYS_EXTRA_OPTIONS and make Kconfig
much cleaner.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
The board/SoC select menu in arch/arm/Kconfig is still cluttered.
Add ARCH_INTEGRATOR into arch/arm/Kconfig and move the board select
under arch/arm/mach-integrator.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
These is a growing trend to license DT files dual GPL and X11
especially in the Linux community. It allows easier reuse of
device trees for other software projects.
This commit prepares for doing so in U-Boot too, since DT files are
often copied from the kernel to U-Boot.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Commit d8bafe1310
"ARMv8: enable DM in vexpress64 board" only enabled DM
for the simulated vexpress64 board (FVP) with the
hardcoded clock value for the simulated board, causing
a console regression on the Juno board which was using
a different clock setting.
Fix this by enabling DM for all vexpress64 boards,
defining the clock frequency per-board, deleting the
static array of PL01x ports from the config file and
relying solely on the port defined in the boardfile
using platform data.
Cc: David Feng <fenghua@phytium.com.cn>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
some pins on the board have been rerouted to other peripherals, so we
change the pinmux to apply with hardware-design.
Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
The NAND-version has been become a bit orphan.
Now we need to reactivate it, so bring necessary things:
- loading devicetree
- switch control signal to correct pins
- setup pinmux
- default-environment
up to date.
Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
instead of polling everytime the environment, we take usage of the global
gd->fdt_blob variable and check it only against NULL.
Variable "dtbaddr" from environment is needed only one time on loading the
devicetree within "load_devicetree()"
Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
These methods should be passed a slave device, not a bus. This matches the
old SPI interface. It is important to know which device is claiming the bus
so passing a bus is not that useful.
Reported-by: Haikun Wang <haikun.wang@freescale.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Peng Fan <Peng.Fan@freescale.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
It is not necessary to write a zero baud rate to the device, and for some
chips this will cause problems. Drop this code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Allow this driver to support boards where the register shift is not 0.
This fixes some compiler warnings which appear in that case.
Signed-off-by: Simon Glass <sjg@chromium.org>
This UART permits different register spacing. To support the debug UART on
devices which have a spacing other than 1 byte, allow the shift value to
be specified.
Signed-off-by: Simon Glass <sjg@chromium.org>
For some files I neglected to add a license. Rectify this:
arch/arm/dts/exynos4210-pinctrl-uboot.dtsi
arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi
arch/arm/dts/exynos5250-pinctrl-uboot.dtsi
arch/arm/dts/exynos54xx-pinctrl-uboot.dtsi
arch/arm/dts/s5pc100-pinctrl.dtsi
arch/arm/dts/s5pc110-pinctrl.dtsi
This file came from Linux and has no license information there, so add a
comment to that effect:
arch/sandbox/include/asm/bitops.h
This file also came from Linux - presumably someone from TI could add the
license:
include/dt-bindings/pinctrl/omap.h
Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Ingrid Viitanen <ingrid.viitanen@nokia.com>
We must not clear global_data even in tests, since the ram_buffer (which
is used by malloc()) will also be lost, and subsequent tests will fail.
Zero only the global_data fields that are required for the test to function.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Tested-by: Joe Hershberger <joe.hershberger@ni.com>
There are a lot more tests now. To avoid confusion add the updated test
output to the driver model README.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Since a device can have children in the same uclass as itself, we need
to handle unbinding carefully: we must allow that unbinding a device in a
uclass may cause another device in the same uclass to be unbound.
Adjust the code to cope.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Tested-by: Joe Hershberger <joe.hershberger@ni.com>
The functions:
- uclass_find_device_by_name()
- uclass_get_device_by_name()
searches the required device for the exactly given name.
This patch, presice this fact for both function's comments.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
This commit introduces simple tests for functions:
- uclass_find_device_by_name()
- uclass_get_device_by_name()
Tests added by this commit:
- Test: dm_test_uclass_devices_find_by_name: for uclass id: UCLASS_TEST_FDT
* get uclass's devices by uclass_find_first/next_device() each as 'testdev',
* for each returned device, call: uclass_find_device_by_name(),
with previously returned device's name as an argument ('testdev->name').
* for the found device ('founddev') check if:
* founddev != NULL
* testdev == founddev
* testdev->name == founddev->name (by strcmp)
- Test: dm_test_uclass_devices_get_by_name: for uclass id: UCLASS_TEST_FDT
* get uclass's devices by uclass_get_first/next_device() each as 'testdev',
* for each returned device, call: uclass_get_device_by_name(),
with previously returned device's name as an argument ('testdev->name').
* for the found device ('founddev') check if:
* founddev != NULL
* founddev is active
* testdev == founddev
* testdev->name == founddev->name (by strcmp)
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
Uclass API provides a few functions for get/find the device.
To provide a complete function set of uclass-internal functions,
for use by the drivers, the function uclass_get_device_tail()
should be non-static.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
This commit extends the driver model device's API by function:
- dev_get_uclass_name()
And this function returns the device's uclass driver name if:
- given dev pointer, is non_NULL
otherwise, the NULL pointer is returned.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
This commit extends the driver model device's API by function:
- dev_get_driver_ops()
And this function returns the device's driver's operations if given:
- dev pointer, is non-NULL
- dev->driver->ops pointer, is non-NULL
in other case the, the NULL pointer is returned.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
This commit extends the driver model uclass's API by function:
- uclass_get_device_by_name()
And this function returns the device if:
- uclass with given ID, exists,
- device with exactly given name(dev->name), exists,
- device probe, doesn't return an error.
The returned device is activated and ready to use.
Note:
This function returns the first device, which name is equal
to the given one. This means, that using this function you must
assume, that the device name is unique in the given uclass's ID
device list.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
This commit extends the driver model uclass's API by function:
- uclass_find_device_by_name()
And this function returns the device if:
- uclass with given ID, exists,
- device with exactly given name(dev->name), exists.
The returned device is not activated - need to be probed before use.
Note:
This function returns the first device, which name is equal
to the given one. This means, that using this function you must
assume, that the device name is unique in the given uclass's ID
device list.
uclass-internal.h: cleanup - move the uclass_find_device_by_seq()
declaration and description, near the other uclass_find*() functions.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
This commit introduces simple tests for functions:
- uclass_find_first_device()
- uclass_find_next_device()
- uclass_first_device()
- uclass_next_device()
Tests added by this commit:
- Test: dm_test_uclass_devices_find:
* call uclass_find_first_device(), then check if: (dev != NULL), (ret == 0)
* for the rest devices, call uclass_find_next_device() and do the same check
- Test: dm_test_uclass_devices_get:
* call uclass_first_device(), then check if:
-- (dev != NULL), (ret == 0), device_active()
* for the rest devices, call uclass_next_device() and do the same check
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
This test introduces new test structure type:dm_test_perdev_uc_pdata.
The structure consists of three int values only. For the test purposes,
three pattern values are defined by enum, starting with TEST_UC_PDATA_INTVAL1.
This commit adds two test cases for uclass platform data:
- Test: dm_test_autobind_uclass_pdata_alloc - this tests if:
* uclass driver sets: .per_device_platdata_auto_alloc_size field
* the devices's: dev->uclass_platdata is non-NULL
- Test: dm_test_autobind_uclass_pdata_valid - this tests:
* if the devices's: dev->uclass_platdata is non-NULL
* the structure of type 'dm_test_perdev_uc_pdata' allocated at address
pointed by dev->uclass_platdata. Each structure field, should be equal
to proper pattern data, starting from .intval1 == TEST_UC_PDATA_INTVAL1.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
This commit adds 'uclass_platdata' field to 'struct udevice', which
can be automatically allocated at bind. The allocation size is defined
in 'struct uclass_driver' as 'per_device_platdata_auto_alloc_size'.
New device's flag is added: DM_FLAG_ALLOC_UCLASS_PDATA, which is used
for memory freeing at device unbind method.
As for other udevice's fields, a complementary function is added:
- dev_get_uclass_platdata()
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
This commit extends the uclass-internal functions by:
- uclass_find_first_device()
- uclass_find_next_device()
For both functions, the returned device is not probed.
After some cleanup, the above functions are called by:
- uclass_first_device()
- uclass_next_device()
for which, the returned device is probed.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
Current driver assumes the AHCI is connected to PCI, this is not
true on some SoCs, e.g. LS1021A, which has PCI but the AHCI is
in SoC. This patch will enable embedded AHCI devices on platforms
with PCI.
PCI AHCI devices still can be used by commenting CONFIG_SCSI_AHCI_PLAT
option in head file.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Add gzwrite command to write gzip-compressed images to block devices.
Input must be gzip-compressed according to RFC1952, since the crc
and file size in the trailer will be confirmed during operation.
The decompressed file size must be specified on the command line
for images with decompressed sizes >= 4GiB because the trailer
only contains the low 32 bits of the original file size.
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Initial filesystem images are generally highly compressible.
Add a routine gzwrite that allows gzip-compressed images to be
written to block devices.
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Reviewed-by: Tom Rini <trini@ti.com>
mx6sabresd has four MT41K128M16JT-125 chips. Each memory has 16-bit bus
and 2GiB, so fix the width and density fields accordingly.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Move the compilation of file fsl_validate.c in MACRO CONFIG_CMD_ESBC_VALIDATE.
This file should be compiled only when the above MACRO is defined
This caused a break in compilation of iMX platforms when compiling for SECURE_BOOT
Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com>
This patch extracts all baseboard specific defines into a separate config file.
This makes it easier to add other baseboards that use the TQMa6 SoM.
This patch will be used by the upcoming WRU-IV board support which also
uses the TQMa6 SoM.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Markus Niebel <Markus.Niebel@tq-group.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-By: Markus Niebel <Markus.Niebel@tq-group.com>
The LDO_EN is bit 4, not value 4. This is only used on the Ventana boards so
we will change it in the header as the other values there are in terms of
values and not bit numbers.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
This commit combines catching missing memory and calibration data into
one if() block. It further prints pertinent information in determining
why the failure occurred.
Signed-off-by: Pushpal Sidhu <psidhu@gateworks.com>
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
The initial revision of the GW551x does not connect enough signals between
the HDMI receiver and the IMX6 CSI for 16bit capture mode necessary for
yuv422smp capture. Future revisions will, but for the initial rev force it
to yuv422bt656 mode which requires an 8bit video data bus.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
The HDMI receiver used on the GW54xx and GW551x has a 16bit video data bus
interconnect between it and the IMX6 CSI. This can be used in two different
modes, each having advantages and disadvantages. Allow the hdmiinfmt env
var to specify which format is desired (yuv422smp or yuv422bt656).
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
The GW522x is functionally the same as a GW52xx except for PCIE_RST#
GPIO. Add a DT fixup to change this gpio upon bootup.
Signed-off-by: Pushpal Sidhu <psidhu@gateworks.com>
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
This adds information about the Gateworks System Controller to the gsc command
such as the firmware version, firmware CRC and status of the GSC watchdog
(if its enabled and if its tripped).
Additionally the 'gsc wd' command can be used to enable or disable the
watchdog with the following usage:
gsc wd enable [30|60]
gsc wd disable
Note that the GSC registers are battery-backed by the GSC coincell so once
eanbled, they remain enabled across power-cycles or until either the GSC
firmware has been updated or FLASH has been re-programmed by the Gateworks
JTAG adapter.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Configure kernel device-tree for display from env var. This is useful
to specify the display present when the device-tree supports multiple
non-detectable display configurations.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Certain older kernels in use by some customers erroneously define a uart3
for GW54xx with a pinmux that conflicts with NAND. This will remove
that node to avoid such conflicts.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Updated 16bit DDR calibration using values obtained from running the
i.MX6 DDR Stress Test tool over a set of boards over full operationg
temperature.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
The GW551x-A revision does not have the CSI0_DATA_EN pin connected, therefore
we need to make sure that signal is not muxed to the CSI_DATA_EN signal
internally and do so by steering it to the unused GPIO5_IO20.
We do this so that the kernel device-tree can properly define the signal for
RevB and beyond boards that do have this hooked up properly and require it.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Add a new voltage rail added in various -C revision PCB's.
Additionally make VDD_CORE, VDD_SOC, and VDD_IO2 common as all Ventana boards
have those.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Certain OS bootscripts need to know how much memory a board has to adjust
kernel parameters (namely Android). This allows those boards to determine
mem size in MB.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
The min/max of each depends not only on board but on CPU. Simplify by removing
this rarely needed and difficult to maintain feature and just display the
rails and their values.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Added support in default boot scripts to find kernel/dtbs on a boot volume
separate from rootfs volume.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
The GW551x is a small form factor board based on the IMX6 SoC that includes:
* up to 512MB DDR3 memory
* up to 2GB NAND flash
* 1x miniPCIe socket (with USB)
* HDMI out (micro-HDMI)
* HDMI in (micro-HDMI)
* TTL level I/O (supported by GW16111 breakout board):
* I2C
* 2x UART
* CAN
* 2x DIO (GPIO/PWM)
* USB OTG
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
A board level errata causes the IMX6 watchdog to be unstable on the GW51xx
RevA and RevB boards which can cause the watchdog to trip extremely early
(under 5seconds) under certain operating conditions. Disable the watchdog
node in the device-tree to work around this issue.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Enable the 'i2c edid' command to query and display data from an attached
HDMI monitor of LVDS display with an EDID device.
Example:
Ventana > i2c dev 2 && i2c edid 0x50
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Add support for the USB mass storage gadget to enable access to on-board
storage.
Example:
Ventana > ums 0 mmc 0 # provide ums access to the uSD
Ventana > ums 0 usb 0 # provide ums access to the first USB device
Ventana > ums 0 sata 0 # provide ums access to an mSATA device
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
The IMX6 Datasheets specifies that when the IMX6 LDO is enabled
(internal Anatop LDO's for VDD_ARM, VDD_SOC, and VDD_xPU) you need to
provide 1350mV on VDD_ARM_IN and VDD_SOC_IN for IMX6Q@1GHz (Automotive)
and 1275mV for IMX6DL@800MHz (Industrial). While we are still about 50mV
shy on the IMX6Q operating at 1GHz we set it to the max we can and leave it
up to the kernel to implement a regulator driver for the LTC3676 and put
the LDO's in bypass mode which allows us to drop the voltages by 125mV
respectively.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
The GW52xx has a MUX that can direct front-panel USB OTG to one of the
miniPCIe sockets (for use with a cellular modem for example). Use hwconfig
to steer this.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Gateworks Ventana boards don't all use IMX6 FEC, so lets define default
ethprime based off the first detected device.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
I've encountered issues when using 4k packets through certain switches. For
now disable this and go back to using MTU size packets.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Add 'fdt_fixup_display' function to fixup device-tree native-mode property
of display-timings node to select timings for a specific display.
This is useful if a device-tree has configurations for multiple
display timings for undetectable displays.
see kernel Documentation/devicetree/bindings/video/display-timing.txt
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Acked-by: Simon Glass <sjg@chromium.org>
DDR3 has a special Precharge power-down mode: fast-exit vs slow-exit.
In slow-exit mode the DLL is off but in some quiescent state that makes it easy
to turn on again in tXPDLL cycles (about 10tCK) vs the full tDLLK (512tCK).
In fast-exist mode the DLL is maintained such that it is ready again in about
3tCK.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reading the boot mode pins after power-up does not necessarily represent the
boot mode used by the ROM loader. For example the state of a pin may have
changed because a recovery switch which was pressed to enter USB mode is
already released after plugging in USB.
The ROM loader stores the value a fixed address in OCRAM. Use this value
instead of reading the boot map pins.
The GLOBAL_BOOT_MODE_ADDR for i.MX28 is taken from an U-Boot patch for the
MX28EVK:
http://repository.timesys.com/buildsources/u/u-boot/u-boot-2009.08/u-boot-2009.08-mx28-201012211513.patch
Leave the boot mode detection for the i.MX23 untouched. Someone has to test
whether the i.MX ROM loader does also store the boot mode in OCRAM and if the
address match.
This patch superseeds my incorrect patch:
ARM: mxs: get boot mode from OTP
http://patchwork.ozlabs.org/patch/454930/
Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks>
Cc: Stefano Babic <sbabic@denx.de>
Need to check value of spi_setup_slave and spi_setup_slave_fdt.
If their return value 'bus' is NULL, there is no need to pass it
to following spi_flash_probe_tail.
If 'bus' is null, the original function flow is as following:
spi_flash_probe
|->spi_setup_slave
|->spi_probe_bus_tail
|->spi_flash_probe_slave
|->spi_free_slave
Alougth check the pointer in spi_free_slave is ok, checking the return value
of spi_setup_slave and spi_setup_slave_fdt is better.
Before this fix:
"
=> sf probe 0:2
FSL_QSPI: Not a valid cs !
SF: Failed to set up slave
data abort
pc : [<fff66dcc>] lr : [<fff7628c>]
reloc pc : [<87814dcc>] lr : [<8782428c>]
sp : fdf4fcf0 ip : e630396c fp : fe0d0888
r10: fffa2538 r9 : fdf4feb8 r8 : 02625a00
r7 : 00000002 r6 : fff94ec0 r5 : 00000000 r4 : 9355553c
r3 : 1af0593c r2 : cb3fe030 r1 : fff94eb8 r0 : e59ff018
Flags: nZCv IRQs off FIQs off Mode SVC_32
Resetting CPU ...
"
After this fix:
"
=> sf probe 0:2
FSL_QSPI: Not a valid cs !
Failed to initialize SPI flash at 0:2
"
No data abort using this patch.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
On SoCFPGA, using "sf update" with an non-4byte aligned length leads
to a hangup (and reboot via watchdog). This is because of the unaligned
access in the cadence QSPI driver which is hard to prevent since the
data is written into a 4-byte wide FIFO. This patch fixes this problem
by changing the behavior of the last sector write (not sector aligned).
The new code is even simpler and copies the source data into the temp
buffer and now uses the temp buffer to write the complete sector. So
only one SPI sector write is used now instead of 2 in the old version.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Gerlando Falauto <gerlando.falauto@keymile.com>
Cc: Valentin Longchamp <valentin.longchamp@keymile.com>
Cc: Holger Brunck <holger.brunck@keymile.com>
Acked-by: Gerlando Falauto <gerlando.falauto@keymile.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Removed the unnecessary error check from spi_xfer
as the bitlen zero is possible now to deassert the
chip select for which no data is required to be transfered.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Poll both the Read status and Flag status registers
for sucessful erase and program operations for the
Micron devices with E_FSR flag set in params table.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Correct the macros as per insertion of array fast read
command CMD_READ_ARRAY_FAST in spi_read_cmds_array in file
sf_probe.c
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
This patch adds description for NOR flash layout (firmware images)
in the README file for LS2085A platforms.
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
The Debug Server driver is responsible for loading the Debug
server FW on the Service Processor (Cortex-A5 core) on LS2085A like
SoCs and then polling for the successful initialization of the same.
TOP MEM HIDE is adjusted to ensure the space required by Debug Server
FW is accounted for. MC uses the DDR area which is calculated as:
MC DDR region start = Top of DDR - area reserved by Debug Server FW
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Muram will power off during deepsleep, and the microcode of qe
in muram will be lost, it should be reload when resume.
Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Muram will power off during deepsleep, and the microcode of qe
in muram will be lost, it should be reload when resume.
Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Check if USB Erratum A005697 is applicable on BSC913x and
add corresponding property in the device tree via device
tree fixup which is used by linux driver
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
1. LS2085a provides PCIE_LUT_DBG register rather than PCIE_LDBG
to show the link status, so the patch fixes it.
2. Increase the delay time to make sure that link training
has finished.
3. Return invalid value when accessing multi-function device
4. For LS2085a DBI_RO_WR_EN bit is cleared as default, so we
must set this bit before change DBI register value.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
The patch uses the common function name ft_pci_setup to replace
ft_pcie_setup, then removes unnecessary pcie_layerscape.h because
all the functions have been declared in common.h.
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Add following affected SOCs and their personalities for USB
Erratum A007792 :
T1040 Rev 1.1
T1024 Rev 1.0
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Identify soc(s) having dual phy so as to add "utmi_dual" as phy_mode
for all these socs. This is required for supporting deel-sleep feature
in linux for usb driver
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
1. Default environment will be used for secure boot flow
which can't be edited or saved.
2. Command for secure boot is predefined in the default
environment which will run on autoboot (and autoboot is
the only option allowed in case of secure boot) and it
looks like this:
#define CONFIG_SECBOOT \
"setenv bs_hdraddr 0xe8e00000;" \
"esbc_validate $bs_hdraddr;" \
"source $img_addr;" \
"esbc_halt;"
#endif
3. Boot Script can contain esbc_validate commands and bootm command.
Uboot source command used in default secure boot command will
run the bootscript.
4. Command esbc_halt added to ensure either bootm executes
after validation of images or core should just spin.
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
On QDS board with DDR4 DIMM, LPUART is used as console
output to verify DCU driver. This patch adds
ls1021aqds_ddr4_nor_lpuart_defconfig for this support.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Freescale LS1021ATWR share some pins. Hwconfig option is used to
allows users to choose the pin functions.
Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
[York Sun: revised commit message]
Reviewed-by: York Sun <yorksun@freescale.com>
For LS102xA, some workarounds are only used in VER1.0, so silicon
version detection are added for QDS and TWR boards.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
commit aed2fbef5e
"dm: serial: Tidy up the pl01x driver"
caused a regression on (real hardware) PL010 by omitting
to update the line control register when switching baudrate.
Fix this by inlining the missing write to the baud control
register.
Also renaming the set_line_control() function to
pl011_set_line_control() since this function is clearly
PL011-specific, and it won't suffice to call that to
set up line control.
Tested on the Integrator/AP hardware.
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
"commit 0d13a0051b2c arm: socfpga: Sync Cyclone V DK PLL configuration"
mistakenly changed CONFIG_HPS_MAINPLLGRP_VCO_NUMER to 39, the correct
value should be 79.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Add a stub s_init function in the board file. The reason why the stub function
is needed is that most of the work is now being done in board_init_f(), there
is no need for the SPL to do anything s_init(). However, since lowlevel_init()
is still branching to s_init(), we need stub function for now, until
lowlevel_init() morphs into s_init().
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
commit "07d30b6c3129 arm: socfpga: Sync Cyclone V DK pinmux configuration"
incorrectly set the muxing for UART0 on the Cyclone V DK.
This fixes it up so UART0 is working again.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
For SoCFGPA, use the common ARMv7 lowlevel_init. Thus, we can delete the
SoCFPGA lowlevel_init.S file.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
These functions will be needed for use by the SPL for enabling the
console and sdram initialization.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
The name "pch_gbe.%x" exceeds the limit of the name in the
'struct eth_device'. Rename it as just "pch_gbe".
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
commit 3c6928fd7b "net: phy: fix warnings with W=1" caused
some PHYs(e.g. CS4315/CS4340) not working. This patch fixes the
warning and make those special PHYs working as well.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
When accessing PHY registers it is often desirable to only update
selected bits, so it is necessary to first read the current value
before writing back an modified value with the relevant bits
updated.
To simplify this and to allow such operations to be incorporated
into simple shell scripts propose adding a 'modify' option to the
existing mii command, which takes a mask indicating the bits to
be updated in addition to a data value containing the new bits,
ie, <updated> = (<data> & <mask>) | (<current> & ~<mask>).
Signed-off-by: Tim <tim.james@macltd.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Jeroen Hofstee <jeroen@myspectrum.nl>
Cc: Tom Rini <trini@konsulko.com>
Cc: Tim <tim.james@macltd.com>
Turn ioaddr into an unsigned long rather than a sized 32-bit variable.
While at it, fix a couple of pointer to integer cast size mismatch
warnings by casting through unsigned long going from pointers to
integers and vice versa.
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Some Realtek Ethernet PHYs, like RTL8211D(G/N) and RTL8211E(G), have
interrupts enabled by default. If the interrupt is not treated later by
the OS and the PHY's interrupt line is enabled and shared with other
interrupts, the system will get an interrupt storm. This patch disables
the interrupt for PHY devices that use one of the current Realtek
Ethernet PHY drivers. Some of Realtek Ethernet PHYs, such as RTL8211B(L)
have the interrupt masked. In this case, the functionality of the PHY
should not be afected since this patch brings INER and INSR registers to
their default values.
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
U-Boot on this board grew a long time ago past the 384 KiB that
it reserves for the U-Boot image, before the environment. Thus,
saveenv overwrites the U-Boot image and bricks the board.
I tried to find out when U-Boot grew beyond this point, but there is a
long stretch in the history where this board did not build -- and
AFAICT when it did fit in 384 KiB, it was missing vital features such
as fdt support. Turning off CONFIG_VIDEO was not enough to make it
fit. Thus, I don't think we have any choice other than to move the
environment.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
U-Boot does not have system calls (the services it exposes to
standalone commands use a different mechanism), so the syscall handler
is dead code. It's also broken code, as it assumes it is located at
0xc00 -- while even before the patch to stop relocating exception
vectors to 0, U-Boot had the syscall at 0x900.
The critical and machine check return paths are never called -- the
regular exception return path is used instead, which works because
xSRR0/1 have already been saved and can be restored via the regular
SRR0/1 (we don't care too much in U-Boot about taking a critical/mcheck
inside another exception prolog/epilog).
Also remove a few other small unused functions.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Booke does not require exception vectors to be located at address zero.
U-Boot was doing so anyway, simply because that's how it had been done
on other PPC. The downside of this is that once the OS is loaded to
address zero, the exception vectors have been overwritten -- which
makes it difficult to diagnose a crash that happens after that point.
The IVOR setup and trap entry code is simplified somewhat as a result.
Also, there is no longer a need to align individual exceptions on 0x100
byte boundaries.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Support SODIMM D3XP12081XL10AA 1866MT/s on T2080RDB.
Enable CONFIG_CMD_MEMTEST as well.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Now cortina driver uses macro CONFIG_SYS_CORTINA_FW_IN_NOR
to define that firmware of cortina driver is stored in the
nor flash.
Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
The fuse status register provides the values from on-chip
voltage ID efuses programmed at the factory.
These values define the voltage requirements for
the chip. u-boot reads FUSESR and translates the values
into the appropriate commands to set the voltage output
value of an external voltage regulator.
Signed-off-by: Ying Zhang <b40530@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
QEMU 2.3 changes the address layout of the CCSR map in the PV ppce500 machine
to reside in higher address space.
Unfortunately, this exposed a glitch in u-boot for ppce500: While providing
a function to dynamically evaluate the CCSR region's position in physical
address space, we never used it. Plus we forgot to support 64bit physical
addresses.
This patch fixes that mishap, making u-boot work fine with latest QEMU again.
Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
According to the MPC8555/MPC8541 reference manual the SS_EN (source
synchronous enable) bit in the DDR_SDRAM_CLK_CNLT register must be set
during initialization.
>From section 9.4.1.8 of that manual:
Source synchronous enable. This bit field must be set during
initialization. See Section 9.6.1, "DDR SDRAM Initialization
Sequence," details.
0 - Reserved
1 - The address and command are sent to the DDR SDRAMs source
synchronously.
In addition, Freescale application note AN2805 is also very clear that
this bit must be set.
This patch reverts a change introduced by commit
457caecdbc.
Testing Done:
Compiled targets CONFIG_TARGET_MPC8555CDS and CONFIG_TARGET_MPC8541CDS
and inspected the generated assembly code to verify the SS_EN bit was being
set. There is one extra instruction emitted:
fff9b774: 65 29 80 00 oris r9,r9,32768
Compiled the CONFIG_TARGET_MPC8548CDS target and verified that no
additional instructions were emitted related to this patch.
Booted an image on a MPC8541 based board successfully.
Signed-off-by: Curt Brune <curt@cumulusnetworks.com>
Reviewed-by: York Sun <yorksun@freescale.com>
the ldb clock can be setup in board code (for example set through PLL5).
Update the ldb_clock rate also through board code.
This should be removed, if a clock framework is availiable.
Signed-off-by: Heiko Schocher <hs@denx.de>
Tested-by: Eric Nelson <eric.nelson@boundarydevices.com>
make the ldb_clock configurable through the new define
CONFIG_SYS_LDB_CLOCK. This is needed as the ldb clock is not
always 650000000, for example on the aristainetos2 board,
where the ldb clock derives from PLL5 clock.
Signed-off-by: Heiko Schocher <hs@denx.de>
Tested-by: Eric Nelson <eric.nelson@boundarydevices.com>
Make the sandbox setup more generic/examplary by including
config_distro_defaults.h and config_distro_bootcmd.h.
Among other things this makes it easy to test whether images will boot
though with the standard distro bootcmds by running e.g:
u-boot -c 'host bind 0 myimage.img ; boot'
By default there are 2 target host devices to emulate device with
multiple storage devices (e.g. internal ("host 0") and external
("host 1") and verify that the prioritization and fallbacks do work
correctly.
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Reviewed by: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
Define default PXE client architecture identifiers for IA32 (0x0 aka
Intel x86PC) and Intel x86-64 (0x9 aka EFI x86-64).
This prepares for usage for config_distro_defaults in the sandbox
architecture
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Properly map memory through map_sysmem so that pxe can be used from the
sandbox.
Tested in sandbox as well as on jetson-tk1, odroid-xu3, snow as peach-pi
boards
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: Simon Glass <sjg@chromium.org>
Define the common shared block environment for the host interface in
preperation for the sandbox build to use config_distro_bootcmd.
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
A common pattern to check if a certain device exists (e.g. in
config_distro_bootcmd) is to use: <interface> dev [device]
Implement host dev [device] so this pattern can be used for sandbox host
devices.
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: Simon Glass <sjg@chromium.org>
As suggested by Simon Glass, rename the sb command to host but keep the
old sb command as an alias
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: Simon Glass <sjg@chromium.org>
Add dummy bootz_setup implementation allowing the u-boot sandbox to
run bootz. This recognizes both ARM and x86 zImages to validate a
valid zImage was loaded.
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: Simon Glass <sjg@chromium.org>
Follow the convention of other architectures and move the platform
specific linux bootm code into sandbox/lib/bootm.c.
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: Simon Glass <sjg@chromium.org>
Only do sandbox filesystem access when using the hostfs device
interface, rather then falling back to it in all cases. This prevents
confusion situations due to the fallback being taken rather then an
unsupported error being raised.
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
The help text for -V says we will pass V=1 but all it really did was not
pass in -s. Change the logic to pass make V=1 with given to buildman -V or
-s to make otherwise.
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Simon Glass <sjg@chromium.org>
When told to keep outputs, be much more liberal in what files we keep.
In addition to adding 'MLO', keep anything that matches u-boot-spl.* (so
that we keep the map file as well) and anything we generate about
'u-boot itself. A large number of bootable formats now match this and
thus it's easier to build many targets and then boot them afterwards
using buildman.
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Simon Glass <sjg@chromium.org>
It is useful to be able to see CONFIG changes made by commits. Add this
feature to buildman using the -K flag so that all CONFIG changes are
reported.
The CONFIG options exist in a number of files. Each is reported
individually as well as a summary that covers all files. The output
shows three parts: green for additions, red for removals and yellow for
changes.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present buildman tries to detect an aborted build and doesn't record a
result in that case. This is to make sure that an abort (e.g. with Ctrl-C)
does not mark the build as done. Without this option, buildman would never
retry the build unless -f/-F are provided. The effect is that aborting the
build creates 'fake errors' on whatever builds buildman happens to be
working on at the time.
Unfortunately the current test is not reliable and this detection can
trigger if a required toolchain tool is missing. In this case the toolchain
problem is never reported.
Adjust the logic to continue processing the build result, mark the build as
done (and failed), but with a return code which indicates that it should be
retried.
The correct fix is to fully and correctly detect an aborted build, quit
buildman immediately and not write any partial build results in this case.
Unfortunately this is currently beyond my powers and is left as an exercise
for the reader (and patches are welcome).
Signed-off-by: Simon Glass <sjg@chromium.org>
At present CONFIG options are split across Kconfig and board config headers
files. Also we have multiple files containing these CONFIG options.
In order to see exactly what is being used for building, create a .cfg
file which holds these options as reported by the C preprocessor.
Signed-off-by: Simon Glass <sjg@chromium.org>
Don't store it in a u32.
Don't dereference the bus address as if it were a virtual address
(fixes 284231e49a ("ahci: Support splitting of read transactions
into multiple chunks")).
Fixes crash on boot in MPC8641HPCN_36BIT target.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Vadim Bendebury <vbendeb@chromium.org>
Acked-by: York Sun <yorksun@freescale.com>
Adjust the Ethernet initialisation code to support driver model.
It is no-longer necessary to call designware_initialize(). The device will
be probed when it is used. The PHY type and GMAC base will come from the
device tree.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add driver model support to the designware driver. This reuses most of the
existing code except for some duplication in the probe() method.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Adjust the error handling to use errno.h instead of returning -1. Change
leaf functions to pass in the arguments they require rather than struct
eth_device. Apart from simplifying the code it makes is easier to reuse
these functions for driver model, since mostly they actually only use
struct dw_eth_priv (which we can keep).
Create a stub for each Ethernet operation function. This will allow use to
share code with the driver model versions.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
When driver model is used for Ethernet a few functions are passed a udevice
instead of an eth_device. Also add a function to find a PHY type given its
name. This will be used to decode the device tree node.
Finally, put a phy_interface field in struct eth_pdata since this is an
important part of the platform data for Ethernet.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
At present even with driver model is used there is still much manual init
of related devices: PHY, environment and board init. Until these requirements
are dealt with in another way we need to keep them around.
Break out the init portion of the legacy eth_initialize() into a separate
function and call it from both the legacy and driver model eth_initialize()
functions.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Since we will use these bindings on sunxi, bring them in from Linux
4.0-rc1.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Move this to Kconfig and clean up board config files that use it. Also
rename it to CONFIG_ETH_DESIGNWARE to fit with the naming that exists
in drivers/net/Kconfig.
Signed-off-by: Simon Glass <sjg@chromium.org>
Version 1:
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
We currently have Linksprite_pcDuino3 and Linksprite_pcDuino3_fdt. Drop the
former in favour of the latter.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
More net features enabled and supported on sandbox to allow more testing
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Simon Glass <sjg@chromium.org>
When SNTP is enabled and DATE is not, to_tm() is not built in. It could
be defined when TIMESTAMP is defined, so check for that.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Simon Glass <sjg@chromium.org>
This commit fixes incorrect DHCP/BOOTP packet layout caused by
'ulong' type size difference on 64 and 32-bit architectures.
It also renames NetReadLong()/NetCopyLong() to
net_read_u32/net_copy_u32() accordingly.
Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com>
Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com>
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Simon Glass <sjg@chromium.org>
Finish eliminating CamelCase from net.c and other failures
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Simon Glass <sjg@chromium.org>
There were still a few remaining complains in the legacy eth_device
definition that hadn't been addressed.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Simon Glass <sjg@chromium.org>
There were still a few failures in net/eth.c, especially in the legacy
part of the code.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Simon Glass <sjg@chromium.org>
A few new rules in checkpatch.pl since linklocal.c was added.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Simon Glass <sjg@chromium.org>
Make a thorough pass through all variables and function names contained
within common/cmd_net.c and remove CamelCase and improve naming.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Simon Glass <sjg@chromium.org>
Make a thorough pass through all variables and function names contained
within netconsole.c and remove CamelCase and improve naming.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Simon Glass <sjg@chromium.org>
Make a thorough pass through all variables and function names contained
within dns.c and remove CamelCase and improve naming.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Simon Glass <sjg@chromium.org>
Make a thorough pass through all variables and function names contained
within cdp.c and remove CamelCase and improve naming.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Simon Glass <sjg@chromium.org>
Make a thorough pass through all variables and function names contained
within ping.c and remove CamelCase and improve naming.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Simon Glass <sjg@chromium.org>
Make a thorough pass through all variables and function names contained
within sntp.c and remove CamelCase and improve naming.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Simon Glass <sjg@chromium.org>
Make a thorough pass through all variables and function names contained
within rarp.c and remove CamelCase and improve naming.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Simon Glass <sjg@chromium.org>
Make a thorough pass through all variables and function names contained
within nfs.c and remove CamelCase and improve naming.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Simon Glass <sjg@chromium.org>
Make a thorough pass through all variables and function names contained
within bootp.c and remove CamelCase and improve naming.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Simon Glass <sjg@chromium.org>
Make a thorough pass through all variables and function names contained
within arp and remove CamelCase and improve naming.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Simon Glass <sjg@chromium.org>
Make a thorough pass through all variables and function names contained
within tftp and remove CamelCase and improve naming.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Simon Glass <sjg@chromium.org>
Update the naming convention used in the network stack functions and
variables that Ethernet drivers use to interact with it.
This cleans up the temporary hacks that were added to this interface
along with the DM support.
This patch has a few remaining checkpatch.pl failures that would be out
of the scope of this patch to fix (drivers that are in gross violation
of checkpatch.pl).
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Simon Glass <sjg@chromium.org>
This patch cleans up the names of internal packet buffer names that are
used within the network stack and the functions that use them.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Use "_ethaddr" at the end of variables and drop CamelCase.
Make constant values actually 'const'.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Simon Glass <sjg@chromium.org>
Remove CamelCase variable naming.
Move the definition to the same compilation unit as the primary use.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Simon Glass <sjg@chromium.org>
The variables around the bootfile were inconsistent and used CamelCase.
Update them to make the code more readable.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Simon Glass <sjg@chromium.org>
This patch is simply clean-up to make the IPv4 type that is used match
what Linux uses. It also attempts to move all variables that are IP
addresses use good naming instead of CamelCase. No functional change.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Simon Glass <sjg@chromium.org>
All the Zynq boards have switch to Driver Model.
"select DM" is better than default value in each defconfig.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
All the UniPhier boards have switch to Driver Model.
"select DM" is better than default value in each defconfig.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
As mentioned in the previous commit, adding default values in each
Kconfig causes problems because it does not co-exist with the
"depends on" syntax. (Please note this is not a bug of Kconfig.)
We should not do so unless we have a special reason. Actually,
for CONFIG_DM*, we have no good reason to do so.
Generally, CONFIG_DM is not a user-configurable option. Once we
convert a driver into Driver Model, the board only works with Driver
Model, i.e. CONFIG_DM must be always enabled for that board.
So, using "select DM" is more suitable rather than allowing users to
modify it. Another good thing is, Kconfig warns unmet dependencies
for "select" syntax, so we easily notice bugs.
Actually, CONFIG_DM and other related options have been added
without consistency: some into arch/*/Kconfig, some into
board/*/Kconfig, and some into configs/*_defconfig.
This commit prefers "select" and cleans up the following issues.
[1] Never use "CONFIG_DM=n" in defconfig files
It is really rare to add "CONFIG_FOO=n" to disable CONFIG options.
It is more common to use "# CONFIG_FOO is not set". But here, we
do not even have to do it.
Less than half of OMAP3 boards have been converted to Driver Model.
Adding the default values to arch/arm/cpu/armv7/omap3/Kconfig is
weird. Instead, add "select DM" only to appropriate boards, which
eventually eliminates "CONFIG_DM=n", etc.
[2] Delete redundant CONFIGs
Sandbox sets CONFIG_DM in arch/sandbox/Kconfig and defines it again
in configs/sandbox_defconfig.
Likewise, OMAP3 sets CONFIG_DM arch/arm/cpu/armv7/omap3/Kconfig and
defines it also in omap3_beagle_defconfig and devkit8000_defconfig.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
CONFIG_SPI does not exist in Kconfig in the first place, so the
dependency "depends on DM && SPI" is never met, i.e., DM_SPI_FLASH
can never be enabled (unless you ignore the dependency in an illegal
way. See below.)
Actually, some defconfigs such as socfpga_*_defconfig define
CONFIG_DM_SPI_FLASH=y, but it never appears in the .config file
because of this wrong dependency.
On the other hand, all the Tegra boards enable DM_SPI_FLASH because
config DM_SPI_FLASH
default y
silently ignores the dependency.
Unfortunately, this style of CONFIG definition is abused everywhere
in U-Boot, so we easily miss such a wrong dependency.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
Add some documentation describing how USB is implemented with USB. This
might make things easier for people to understand.
Signed-off-by: Simon Glass <sjg@chromium.org>
This adds a simple test for probing and a functional test using the flash
stick emulator, which tests a large chunk of the USB stack.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
As well as running all tests, it is useful to be able to run a selected test.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
Enable USB emulation and associated features so that USB can be used in
sandbox.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
Add a few more shifts/masks to make it easier to decode a pipe value (rather
than just building it). We need this for USB device emulation.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
This is useful for creating lists of descriptors, and is better than using
void * for this purpose.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
Since we can support both controllers now, enable this in the device tree.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
Convert Exynos boards over to use driver model for USB. This does not remove
any unnecessary code so far.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
Add driver model support in the XHCI support code so that it can be used by
XHCI USB drivers.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
Since driver model will want to use most of the same code for XHCI init
and uninit, put it in a separate function.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
This function should not be delving into struct usb_device. Pass in the
parameters it needs directly.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
This function should not be delving into struct usb_device. Pass in the
parameters it needs directly.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
Rather than getting this directly from struct usb_device, call a function
to obtain it. This will make it possible for driver model to provide it
another way.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
We want to use mostly the same init and uninit code for driver model, so move
the common part into two functions.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
Try to return useful error numbers where possible. Also avoid swallowing
an error number when it is returned by a called function.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
This variable is a bit of a hack. We can obtain the same information from
the normal device config. This will fit better with driver model, where
global variables are best avoided.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
Add support for scanning USB etghernet devices with driver model. This mostly
involves scanning all buses since device numbering is not unique across
buses.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
These allow basic testing of the USB functionality within sandbox.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
This driver supports using emulation devices to provide a USB bus within
sandbox.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
All USB controllers need a root hub. Add a sandbox emulation for this so
that we can add USB devices to sandbox.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
This emulator supports USB enumeration and allows a local file to be provided
as the contents of the emulated flash stick. U-Boot can then use the file as
it would a normal device, with all access passing through the usb_stor layer
and the USB stack.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
These devices must have their addresses removed ready for the next USB
bus enumeration. Add this logic to usb_stop().
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
With sandbox we want to be able to emulate USB devices so that we can test
the USB stack. Add a uclass to support this. It implements the same
operations as a normal USB device driver, but in this case passes them on
to an emulation driver.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
This is needed for sandbox USB device emulation, so move it to a place
where it can be found by things other than gadgets.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
These are needed to enable the USB bus (although not sufficient since it
still does not work).
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
Allow USB keyboards to work with driver model. The main difference is that
we can have multiple buses (each with its own device numbering) and each
bus must be scanned.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
Before adding driver model support, split out code from this over-long
function.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
Some controllers support OTG (on-the-go) where they can operate as either
host or device. The gadget layer in U-Boot supports this.
While this layer does not interact with driver model, we can provide a
function which sets up the controller in the correct way. This way the code
at least builds (although it likely will not work).
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
At present USB devices with no driver model driver cannot be seen in the
device list, and we fail to set them up correctly. This means they cannot
be used.
While having real drivers that support driver model for all USB devices
is the eventual goal, we are not there yet.
As a stop-gap, add a generic USB driver which is bound when we do not have
a real driver. This allows the device to be set up and shown on the bus.
It also allows ad-hoc code (such as usb_ether) to find these devices and
set them up.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
USB devices in U-Boot are currently probed only after all devices have
been enumerated. Each type of device is probed by custom code, e.g.:
- USB storage
- Keyboard
- Ethernet
With driver model this approach doesn't work very well. We could build
a picture of the bus and then go back and add the devices later, but
this means that the data structures are incomplete for quite a while.
It also does not follow the model of being able to bind a device when we
discover it.
We would prefer to have devices automatically be bound as the device is
enumerated. This allows us to attach drivers to particular USB classes
or product/vendor IDs. This is the method used by Linux.
Add the required #defines from Linux, a way of declaring a USB driver and
the logic to locate the correct driver given the USB device's descriptors.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
Add a way for EHCI controller drivers to support driver model. Drivers can
call ehci_register() to register themselves in their probe() methods.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
The index cannot be used with driver model, and isn't needed anyway. Change
the parameter to a pointer.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
These are a pain with driver model because we might have different EHCI
drivers which want to implement them differently. Now that they use
consistent function signatures, we can in good conscience move them to
a struct.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
Fix non-driver-model EHCI to set up the EHCI operations correctly:
Signed-off-by: Tom Rini <trini@konsulko.com>
Move the bulk of the code in usb_lowlevel_init() into a separate function
which will also be used by driver model. Keep the CONFIG options out of
this function by providing a tweak flag for Faraday. We need to avoid using
CONFIG options in driver model code where possible, since it makes it
impossible to use multiple controllers in that code where they have
different options.
The CONFIG_EHCI_HCD_INIT_AFTER_RESET option is also kept out of the
common init function. With driver model the controller will be able to
perform this extra init itself after registering with the EHCI layer.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
With driver model we want to remove the controller pointer in struct udevice
and use driver model data structures instead. To prepare for this, move
access to this field to a function which can provide a different
implementation for driver model.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
Adjust this function so that it is passed an EHCI controller pointer so that
implementations can look up their controller. This makes the weak functions
use a consistent API.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
Adjust this function so that it is passed an EHCI controller pointer so that
implementations can look up their controller. This makes the weak functions
use a consistent API.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
We don't need this anymore, so adjust the code to avoid using it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
Adjust this function so that it is passed an EHCI controller pointer so that
implementations can look up their controller.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
At present the tegra driver uses a separate pointer to know which controller
type is in use. This works because only one controller type is used at a
time.
With driver model we want to make the controller state hermetic in the sense
that it is not necessary to look elsewhere to know the controller type. This
will permit a controller to implement the EHCI weak functions without
reference to global data structures.
To achieve this, define an enum for the controller type and store it with
the information on each EHCI controller.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
Add a private data pointer that clients of EHCI can use to access their
private information. This establishes a link between struct ehci_ctrl and
its associated controller data structure.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
Adjust this function so that it is passed an EHCI controller pointer so that
implementations can look up their controller.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
Put these at the top of the file so they are in one place. Also add function
prototypes to the header file to avoid call site mismatches.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
Add support for scanning USB storage devices with driver model. This mostly
involves adding a USB device ID for storage devices.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
The usb_stor_scan() function is quite long, so split out the code that scans
each device into its own function. Also, rather than setting up the block
device list once at the start, set it up as each device is scanned. This
makes it possible to use this code from driver model.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
With a few tweaks we can compile this code with sandbox and enable testing
of the USB storage layer.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
The for() loop is not needed since the value is immediately accessible.
Use this instead to simplify the code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
This function assumes that unsigned long is 32-bits wide, but it is not
on 64-bit machines. Use the correct type, and add a few debug() lines also.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
These are better off in a header file so they can be used by other code (e.g.
the sandbox USB storage emulator).
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
Adjust the existing hub code to support driver model, and add a USB driver
for hubs.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
Split out the hub detection logic so it can be used by driver model. Also
adjust the code to return errors correctly.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
Add the required #ifdefs and remove unwanted data structures so that the
USB uclass will be able to use this file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
This function now calls usb_setup_device() to set up the device and
usb_hub_probe() to check if it is a hub. The XHCI special case is now a
parameter to usb_setup_device(). The latter will be used by the USB uclass
when it is added, since it does not rely on any CONFIGs or legacy data
structures.
Signed-off-by: Simon Glass <sjg@chromium.org>
Bug-fixes for descriptor reading and usb_new_device() return value
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Tested-by: Tom Rini <trini@konsulko.com>
Move the code that sets up the device with a new address into its own
function, usb_prepare_device().
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
usb_new_device() is far too long and does far too much. As a first step, move
the code that does initial setup and reads a descriptor into its own function
called usb_setup_descriptor().
For XHCI the init order is different - we set up the device but don't
actually read the descriptor until after we set an address. Support this
option as a parameter to usb_setup_descriptor().
Avoid changing this torturous code more than necessary to make it easy to
review.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
Move the port reset code into its own function. Rename usb_hub_reset() to
indicate that is is now a legacy function.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
Adjust this command to work with the new driver model uclass. It needs to
iterate through multiple independent controllers to find hubs, and work
through their children recursively in a different way. Otherwise the
functionality is much the same.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
This function returns NULL on error at present. Adjust it so that we can
return a real error, as is needed with driver model. Also improve the
error handling in its caller, usb_hub_port_connect_change(), and adjust
the code order to prepare for driver model.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
Use 'udev' instead of 'dev' in a few places, reserving 'dev' for driver
model's struct udevice. Also adjust the code in a few minor ways to make
it easier to plumb in driver model.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
Add a uclass that can represent a USB controller. For now we do not create
devices for things attached to the controller. This will be added later.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
This has a prototype but no implementation. It returns the global GPIO number
given a gpio_desc. It is useful for debugging in some cases.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
Add some utility functions to check for children and for the last sibling in
a device's parent.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
The uclass pre-probe functions may end up calling back into the device in
some circumstances. This can fail if recursion takes place. Adjust the
ordering so that we mark the device as active early, then retract this
later if needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
The existing get_get_of_data() function provides access to both the driver's
compatible string and its driver data. However only the latter is actually
useful. Update the interface to reflect this and fix up existing users.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
The driver is not modified by driver model, so update driver_bind() to
recognise that.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
Some driver want to put DMA buffers in their private data. Add a flag
to tell driver model to align driver-private data to a cache boundary so
that DMA will work correctly in this case.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
Once declared, you cannot access a linker_list entry since you do not have
a symbol name for it. Add llsym() macro to provide this. This avoids
searching for the symbol at run-time based on name.
An example usage is to declare a driver with U_BOOT_DRIVER(), then obtain
a pointer to that driver later.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
Some drivers need a chance to manage their receive buffers after the
packet has been handled by the network stack. Add an operation that
will allow the driver to be called in that case.
Reported-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Tested-on: pcduino3
Add QSPI controller dts node in ls1021a.dtsi.
Add QSPI slave device dts node in ls1021a-twr.dts and ls1021a-qds.dts.
Signed-off-by: Haikun Wang <Haikun.Wang@freescale.com>
Acked-by: Simon Glass <sjg@chromium.org>
Update DSPI controller node in ls1021a.dtsi.
Update flash device node in ls1021a-qds.dts.
Ls1021a-twr board doesn't support DSPI, so remove DSPI node
in ls1021a-twr.dts.
Signed-off-by: Haikun Wang <Haikun.Wang@freescale.com>
Acked-by: Simon Glass <sjg@chromium.org>
Change address_cells and size_cells of root node and 'soc' node
from 2 to 1.
We backport ls1021a device tree source files from kernel to u-boot.
Kernel files set address_cells and size_cells to 2 in order to access
more than 4GB space.
But we don't have this requirement now and u-boot fdtdec_get_xxx interfaces
can't support property whose size is 'u64' completely.
So make this change.
Signed-off-by: Haikun Wang <Haikun.Wang@freescale.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bring in required device tree files for ls1021a from Linux.
These are initially unchanged and have a number of pieces not needed by U-Boot.
Signed-off-by: Haikun Wang <Haikun.Wang@freescale.com>
Acked-by: Simon Glass <sjg@chromium.org>
Backport of kernel commits:
7c14f6c719de092d69c81877786e83ce7ae1a860
35faad2a1563b3d4dc983a82ac41033fe053870c
Signed-off-by: Haikun Wang <Haikun.Wang@freescale.com>
Acked-by: Simon Glass <sjg@chromium.org>
This commit adds driver model support to software emulated i2c bus driver.
This driver supports kernel-style device tree bindings. Fdt properties in use:
- compatible - "i2c-gpio"
- gpios - data and clock GPIO pin phandles
- delay-us - micro seconds delay between GPIOs toggle operations,
which is 1/4 of I2C speed clock period.
Added:
- Config: CONFIG_DM_I2C_GPIO
- File: drivers/i2c/i2c-gpio.c
- File: doc/device-tree-bindings/i2c/i2c-gpio.txt
Driver base code is taken from: drivers/i2c/soft-i2c.c, changes:
- use "i2c-gpio" naming
- update comments style
- move preprocesor macros into functions
- add device tree support
- add driver model i2c support
- code cleanup,
- add Kconfig entry
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Added braces in i2c_gpio_xfer() to fix style nit:
Signed-off-by: Simon Glass <sjg@chromium.org>
The function gpio_request_list_by_name_nodev() returned -ENOSPC error,
when the loop count was greater than requested count. This was wrong,
because function should return the requested gpio count, when meets
the call request without errors. Now, the loop ends on requested
max_count.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
This code appears to be missing a piece that is needed on some keyboards
to enable the keyboard. Add this in.
This makes the keyboard work correctly on chromebook_link.
Signed-off-by: Simon Glass <sjg@chromium.org>
The U-Boot device trees are slightly different in a few places. Adjust them
to remove most of the differences. Note that U-Boot does not support the
concept of interrupts as distinct from GPIOs, so this difference remains.
For sandbox, use the same keyboard file as for ARM boards and drop the
host emulation bus which seems redundant.
Signed-off-by: Simon Glass <sjg@chromium.org>
This command is supposed to reinit the device. At present with driver
model is does nothing. Implement this feature.
Signed-off-by: Simon Glass <sjg@chromium.org>
The PCH (Platform Controller Hub) is on the PCI bus, so show it as such.
The LPC (Low Pin Count) and SPI bus are inside the PCH, so put these in the
right place also.
Rename the compatible strings to be more descriptive since this board is the
only user. Once we are using driver model fully on x86, these will be
dropped.
Signed-off-by: Simon Glass <sjg@chromium.org>
On x86 systems this device is commonly used to provide legacy port access.
It is sort-of a replacement for the old ISA bus.
Add a uclass for this, and allow it to have child devices.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add a simple uclass for this chip which is often found in x86 systems
where the CPU is a separate device.
The device can have children, so make it scan the device tree for these.
Signed-off-by: Simon Glass <sjg@chromium.org>
Convert this driver over to use driver model. Since all x86 platforms use
it, move x86 to use driver model for SPI and SPI flash. Adjust all dependent
code and remove the old x86 spi_init() function.
Note that this does not make full use of the new PCI uclass as yet. We still
scan the bus looking for the device. It should move to finding its details
in the device tree.
Signed-off-by: Simon Glass <sjg@chromium.org>
Permit use of a udevice to talk to SPI flash. Ultimately we would like
to retire the use of 'struct spi_flash' for this purpose, so create the
new API for those who want to move to it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Take a pass at plumbing errors through to the users of the network stack
Currently only the start() function errors will be returned from
NetLoop(). recv() tends not to have errors, so that is likely not worth
adding. send() certainly can return errors, but this patch does not
attempt to plumb them yet. halt() is not expected to error.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The 'lo' interface on Linux doesn't support thinks like ARP or
link-layer access like we use to talk to a normal network interface.
A higher-level network API must be used to access localhost.
As written, this interface is limited to not supporting ICMP since the
API doesn't allow the socket to be opened for all IP traffic and be able
to receive at the same time. UDP is far more useful to test with, so it
was selected over ICMP. Ping won't work, but things like TFTP should
work.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Implement a bridge between U-Boot's network stack and Linux's raw packet
API allowing the sandbox to send and receive packets using the host
machine's network interface.
This raw Ethernet API requires elevated privileges. You can either run
as root, or you can add the capability needed like so:
sudo /sbin/setcap "CAP_NET_RAW+ep" /path/to/u-boot
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The effect of the "netretry" env var was recently changed. This test
checks that behavior.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This is needed to test the netretry functionality (make the command fail
on a sandbox eth device).
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Make sure that the ethrotate behavior occurs as expected.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The ethprime env var is used to indicate the starting device if none is
specified in ethact. Also support aliases specified in the ethprime var.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Allow network devices to be referred to as "eth0" instead of
"eth@12345678" when specified in ethact.
Add tests to verify this behavior.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add a test for the eth uclass using the sandbox eth driver. Verify basic
functionality of the network stack / eth uclass by exercising the ping
function.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The sandbox driver will now generate response traffic to exercise the
ping command even when no network exists. This allows the basic data
pathways of the DM to be tested.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add basic network support to sandbox which includes a network driver.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Stop forcing drivers to call net_process_received_packet() - formerly
called NetReceive(). Now the uclass will handle calling the driver for
each packet until the driver errors or has nothing to return. The uclass
will then pass the good packets off to the network stack by calling
net_process_received_packet().
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Take the opportunity to enforce better names on newly written or
retrofitted Ethernet drivers.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The return codes in common/cmd_net.c had a number of inconsistencies.
Update them to all use the enum from command.h
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Previously the net functions would access memory assuming physmem did
not need to be mapped. In sandbox, that's not the case.
Now we map the physmem specified by the user in loadaddr to the buffer
that represents that space.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
netretry previously would only retry in one specific case (your MAC
address is not set) and no other. This is basically useless. In the DM
implementation for eth it turns this into a completely useless case
since an un-configured MAC address results in not even entering the
NetLoop. The behavior is now changed to retry any failed command
(rotating through the eth adapters if ethrotate != no).
It also defaulted to retry forever. It is now changed to default to not
retry
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This value is not used by the network stack and is available in the
global data, so stop passing it around. For the one legacy function
that still expects it (init op on old Ethernet drivers) pass in the
global pointer version directly to avoid changing that interface.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reported-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
(Trival fix to remove an unneeded variable declaration in 4xx_enet.c)
Many functions returned -1 previously. Change them to return appropriate error
codes.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reported-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Move some things around and organize things so that the driver model
implementation will fit in more easily.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Many of the functions in net.h were preceded extern needlessly. Removing
them to limit the number of checkpatch.pl complaints.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Make it clear that the helper is checking the addr, not setting it.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The current implementation exposes the eth_device struct to code that
needs to access the MAC address. Add a wrapper function for this to
abstract away the pointer for this operation.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
In the case where the arch defines a custom map_sysmem(), make sure that
including just mapmem.h is sufficient to have these functions as they
are when the arch does not override it.
Also split the non-arch specific functions out of common.h
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Move chromebook_link over to driver model for PCI.
This involves:
- adding a uclass for platform controller hub
- removing most of the existing PCI driver
- adjusting how CPU init works to use driver model instead
- rename the lpc compatible string (it will be removed later)
This does not really take advantage of driver model fully, but it does work.
Furture work will improve the code structure to remove many of the explicit
calls to init the board.
Signed-off-by: Simon Glass <sjg@chromium.org>
This device sits on the sandbox PCI bus and provides a case-swapping
service for sandbox. It illustrates the use of both PCI I/O and PCI
memory accesses.
Signed-off-by: Simon Glass <sjg@chromium.org>
Sometimes, for example if the display is mounted in portrait mode or even if it
is mounted landscape but rotated by 180 degrees, we need to rotate our content
of the display respectively the framebuffer, so that user can read the messages
which are printed out.
For this we introduce the feature called "CONFIG_LCD_ROTATION", this may be
defined in the board-configuration if needed. After this the lcd_console will
be initialized with a given rotation from "vl_rot" out of "vidinfo_t" which is
provided by the board specific code.
If CONFIG_LCD_ROTATION is not defined, the console will be initialized with
0 degrees rotation.
Signed-off-by: Hannes Petermaier <hannes.petermaier@br-automation.com>
Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
Acked-by: Nikita Kiryanov <nikita@compulab.co.il>
[agust: fixed 'struct vidinfo' has no member named 'vl_rot' errors]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
For coming implementation of lcd_console rotation, we will need some more
variables for holding information about framebuffer size, rotation, ...
For better readability we catch all them into a common structure.
Signed-off-by: Hannes Petermaier <hannes.petermaier@br-automation.com>
Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
Acked-by: Nikita Kiryanov <nikita@compulab.co.il>
the capability of drawing some *str with count from lcd_drawchars is unnary.
It is always called from lcd_putc_xy with one character of and count = 1.
So we simply rename lcd_drawchars into lcd_putc_xy and remove the loops inside.
Signed-off-by: Hannes Petermaier <hannes.petermaier@br-automation.com>
Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
Acked-by: Nikita Kiryanov <nikita@compulab.co.il>
Since sandbox does not have real devices (unless it borrows those from the
host) it must use emulations. Provide a uclass which permits PCI operations
to be passed through to an emulation device.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add the required header information, device tree nodes and I/O accessor
functions to support PCI on sandbox. All devices are emulated by drivers
which can be added as required for testing or development.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add a uclass for PCI controllers and a generic one for PCI devices. Adjust
the 'pci' command and the existing PCI support to work with this new uclass.
Keep most of the compatibility code in a separate file so that it can be
removed one day.
TODO: Add more header file comments to the new parts of pci.h
Signed-off-by: Simon Glass <sjg@chromium.org>
Driver model will share many functions with the existing PCI implementation.
Move these into their own file to avoid duplication and confusion.
Signed-off-by: Simon Glass <sjg@chromium.org>
Both of these values are useful for understanding what is going on, so show
them both.
The requested number comes from a device tree alias. The allocated one is
set up when the device is activated, and is unique throughout the uclass.
Signed-off-by: Simon Glass <sjg@chromium.org>
Some uclasses want to set up a device before it is probed. Add a method
for this.
An example is with PCI, where a PCI uclass wants to set up its private
data for later use. This allows the device's uclass() method to make calls
whcih use that data (for example, read PCI memory regions from device
tree, set up bus numbers).
Signed-off-by: Simon Glass <sjg@chromium.org>
At present the device is not active when the probe() method is called. But
some probe() methods want to set up the device and this can involve
accessing it through normal methods. For example a PCI bus may wish to
set up its PCI parameters using calls to pci_hose_write_config_dword() and
similar.
At present this does not work because every such call within the probe()
method sees that the device is not active and attempts to probe it.
Already we mark the device as probed before calling the uclass post_probe()
method. This is a subtle change but I believe the new approach is better.
Since the scope of the change is only the probe() method and all its callees
it should still be within the control of the board author.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add a convenience function to access the private data that a uclass stores
for each of its devices. Convert over most existing uses for consistency
and to provide an example for others.
Signed-off-by: Simon Glass <sjg@chromium.org>
This function returns -ENOENT when the property is missing (which the caller
might forgive) and also when the property is present but incorrectly
formatted (which many callers would like to report).
Update the error return value to allow these different situations to be
distinguished.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present we do more in this function than we should. Split out the
post-driver-model part into a separate function.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Since driver model is set up after arch_cpu_init(), that function cannot
use drivers. Add a new arch_cpu_init_dm() function which is called
immediately after driver model is ready, and can reference devices.
This can be used to probe essential devices for the CPU.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
These functions currently use a generic name, but they are for x86 only.
This may introduce confusion and prevents U-Boot from using these names
more widely.
In fact it should be possible to remove these at some point and use
generic functions, but for now, rename them.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This function is missing a prototype but is more widey useful. Add it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
We should have a size value for these. Add one in each case. This will
be needed for PCI.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Support running U-Boot as a coreboot payload. Tested peripherals include:
- Video (HDMI and DisplayPort)
- SATA disk
- Gigabit Ethernet
- SPI flash
USB3 does not work. This may be a problem with the USB3 PCI driver or
something in the USB3 stack and has not been investigated So far this is
disabled. The SD card slot also does not work.
For video, coreboot will need to run the OPROM to set this up.
With this board, bare support (running without coreboot) is not available
as yet.
Signed-off-by: Simon Glass <sjg@chromium.org>
Since Chromebooks mostly have similar configuration, put it in a common
file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add Lynxpoint to the driver so that the Asus Chromebox can be supported.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
At present a VGA console assumes a keyboard unless a CONFIG option is set.
This difference can be dealt with by a device tree option, allowing boards
that are otherwise the same to use the same configuration.
Signed-off-by: Simon Glass <sjg@chromium.org>
Some systems have more than 4GB of RAM. U-Boot can only place things below
4GB so any memory above that should not be used. Ignore any such memory so
that the memory size will not exceed the maximum.
This prevents gd->ram_size exceeding 4GB which causes problems for PCI
devices which use DMA.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Commit d3cfcb3 (ARM: DRA7: Enable clocks for USB OTGSS and USB PHY)
changed the member names of prcm_regs from cm_l3init_usb_otg_ss_clkctrl
to cm_l3init_usb_otg_ss1_clkctrl and from cm_coreaon_usb_phy_core_clkctrl
to cm_coreaon_usb_phy1_core_clkctrl in order to differentiate between
the two dwc3 controllers present in dra7xx/am43xx and enabled these
clocks in enable_basic_clocks() in hw_data.c. However these clocks
continued to be enabled in board files/driver files for dwc3 host
mode functionality causing compilation break with few configs.
Fixed it here by making all the clocks enabled in enable_basic_clocks()
and removing it from board files/driver files here.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
The TTBR0 register and Table Descriptors of the ARMv7 TLB weren't being
properly set to allow for the configuration specified caching modes to
be active over DRAM. This commit fixes those issues.
Signed-off-by: Bryan Brinsko <bryan.brinsko@rockwellcollins.com>
This enables ARMv7 barrier operations support when
march=armv7-a is enabled.
Using CP15 barriers causes U-Boot bootm command crash when
transferring control to the loaded image on Renesas R8A7794 Cortex A7 CPU.
Using ARMv7 barrier operations instead of the deprecated CP15 barriers
helps to avoid these issues.
Signed-off-by: Valentine Barshak <valentine.barshak+renesas@cogentembedded.com>
Signed-off-by: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Linux-arm64 require that CNTVOFF_EL2 should be programmed with
a consistent value on all cpus. Initializing CNTVOFF_EL2 at state
transition instead of start.S could prevent potential different value
on cpus if ATF exist and u-boot runs at only one cpu.
Signed-off-by: David Feng <fenghua@phytium.com.cn>
This commit copies implementation of the find_next_zero_bit() from
git://git.denx.de/u-boot.git/arch/mips/include/asm/bitops.h. v2014.07
The function is required to enable MCAST_TFTP support for ARM platforms.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Sunxi platforms come with at least 3 TWI (I2C) controllers and some platforms
even have up to 5. This adds support for every controller on each supported
platform, which is especially useful when using expansion ports on single-board-
computers.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Orion5x, Kirkwood and Armada XP platforms come with a single TWSI (I2C) MVTWSI
controller. However, other platforms using MVTWSI may come with more: this is
the case on Allwinner (sunxi) platforms, where up to 4 controllers can be found
on the same chip.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Acked-by: Heiko Schocher <hs@denx.de>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
A few dram files were still listed as maintained even though they were removed
some time ago
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
vbus-usable may not get set if power is provided through both the power barrel
connector and external 5v is also present on the otg connector, at least on
boards where vbus is also controlled through the axp221-pmic.
One way to reproduce this is to bootup an Ippo-q8h board with a usb-host
cable plugged into the otg (so that it will get powered), then unplug the
usb-host cable and plug in a charger, and then do "reset" on the u-boot
console, vbus-usable will then report 0, leading to uboot trying to provide
power to the otg port even though external 5v is present, this commit fixes
this.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
When u-boot boots the board may be powering vbus, we turn off vbus in
sunxi_usbc_request_resources, if we are too quick with reading vusb-detect
after this we may see a residual charge and assume we've an external vusb
connected even though we do not. So when we see an external vusb wait a bit
and try again.
Without this when dealing with a pmic controller vbus and doing "reset" on
the u-boot console the musb host will only init once every other boot, because
the other boot it thinks an external vbus is present, this commit fixes this.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
On boards which use the pmic to enable/disable vbus on the otg port, the
vbus value is not reset to 0 on reset, as reset only resets the SoC and not
the pmic, so explicitly set vbus to 0 on init (request_resources) by moving
the gpio_direction_output call into request_resources.
For consistency also move the gpio_direction_input call for vbus-detect into
request_resources.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The Yones Toptech BD1078 is an A20 based 10" tablet with a 1024x600 lcd screen,
volume up/down and back buttons, headphones jack, mini hdmi, micro usb (otg),
micro usb (host), external micro-sd slot and a separate internal micro-sd slot.
Also see: http://linux-sunxi.org/Yones_Toptech_BD1078
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Sunxi platforms have different possible mmc pin mux setups (except for mmc0),
which are different across platforms.
This lets users configure which is used through the CONFIG_MMC*_PINS Kconfig
options. This is especially relevant when a second (in addition to mmc0) port
is used and CONFIG_MMC_SUNXI_SLOT_EXTRA is enabled.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Each hardware feature exposed through the GPIO pin mux is usually using the same
function index (for a given port), so there is no need to define one value per
pin: one value per hardware feature per port is sufficient, avoids duplication
and makes everything easier to understand.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The Ainol AW1 is an A20 based tablet with a 800x480 lcd screen, sdio wifi,
volume up/down and home buttons, micro-sd slot, micro usb (otg), headphones
connector and a SPCI modem connector.
Also see: http://linux-sunxi.org/Ainol_AW1
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
VBUS detection could be needed not only by the musb code (to prevent host mode),
but also by e.g. gadget drivers to start only when a cable is connected.
In addition, this allows more flexibility in vbus detection, as it could easily
be extended to other USBC indexes. Eventually, this would help making musb
support independent from a hardcoded USB controller index (0).
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
VBUS detection and enable is now be used with virtual AXP GPIOs, so all the USB
code has to use GPIO in every case and let sunxi_gpio do the heavy lifting.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
This converts the VBUS detection and enable logic to GPIO instead of separate
axp functions and checks that have to be used aside usual GPIO functions.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The Mixtile LOFT-Q is an A31 based board with 2G RAM, 8G EMMC, sdio wifi,
1Gbit ethernet, HDMI display, toslink audio plug, 4 USB2.0 port, external
USB2SATA connector, sd card plug, 3x60 external fpic expansion connector,
NXP JN5168 zigbee gw, remote support.
Also see http://focalcrest.com/en/pc.html#pro02
Signed-off-by: Han Pengfei <pengphei@sina.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The "fastboot reboot-bootloader" command is defined to
re-enter into fastboot mode after rebooting into
bootloader. This command is usually used after updating
bootloader via fastboot.
This commit implements only a generic side of the
command - setting of the reset flag and then resetting.
Setting of the reset flag is implemented using __weak
fb_set_reboot_flag() function. The actual setting and
checking of the reset flag should be implemented by
a boot script and/or board/SoC specific code.
Signed-off-by: Alexey Firago <alexey_firago@mentor.com>
Tested-by: Steve Rae <srae@broadcom.com>
[Test HW: bcm28155_ap board]
Implement an alias name check for devices where GPT limitations prevent
user-friendly partition names such as "boot", "system" and "cache". Or,
where the actual partition name doesn't match a standard partition name
used commonly with fastboot.
To set an alias, add an environment setting as follows:
fastboot_partition_alias_<alias partition name>=<actual partition name>
Example: fastboot_partition_alias_boot=LNX
Signed-off-by: Michael Scott <michael.scott@linaro.org>
Acked-by: Steve Rae <srae@broadcom.com>
Cc: Steve Rae <srae@broadcom.com>
Cc: Lukasz Majewski <l.majewski@samsung.com>
trigger watchdog before calling usb_gadget_handle_interrupts()
This prevents board resets when calling dfu command on boards
which have a watchdog.
Signed-off-by: Heiko Schocher <hs@denx.de>
[ Reedition by Lukasz Majewski <l.majewski@samsung.com> to apply to
v2014.04 release ]
For u-boot dwc3 driver the scatter gather list support has been removed
from original linux code. It is correct, since we try to send one request
at a time.
However, the cleanup left spurious break, which caused early exit from
loop at dwc3_cleanup_done_reqs() function. As a result the dwc3_gadget_giveback()
wasn't called and caused USB Mass Storage to hang.
This commit removes this problem and refactor the code to remove superfluous
do { } while(1) loop.
Test HW: Odroid XU3 (with ./test/ums/ums_gadget_test.sh)
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Commit "drivers/dwc3: add a workaround for too small OUT requests"
sets max packet for OUT requests when transfer is smaller.
Until this change the default maxpacket for non EP0 EPs was 1024. This is
too much, since UMS LBA size is 512B
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
It turned out that current dwc3 gadget code is preparing multiple TRBs
for a transfer. Unfortunately, when multiple requests are in the same
queue, only for the last one the LST (last) ctrl bit is set.
Due to that dwc3 HW executes all TRBs up till the one marked as last.
Unfortunately, UMS requires call of ->complete callback after any send TRB.
This is the reason for "hangs" in executing UMS.
This code simplifies this situation and set each TRB's ctrl field bit to be
last (LST bit).
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
There is no point in calling dwc3_thread_interrupt() if no event is
pending. There is also no point in flushing event cache in EVERY loop
iteration.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
This patch adds code to select standard, commonly used usb endpoint
configuration (ep1in-bulk, ep2out-bulk, ep3in-int) to dwc3 driver. This
ensures compatibility with old userspace and windows drivers, which
expects hardcoded endpoint numbers.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
DWC3 hangs on OUT requests smaller than maxpacket size,
so HACK the request length to be at least equal to maxpacket size.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
This commit makes the dwc3_set_mode() as static, to prevent collisions.
Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
The BIT() macro is used only in those places, so it is reasonable to
replace it by a constant value.
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
DWC3 UDC driver requires presence of .reset callback in a composite driver.
This setting is similar to the one nowadays present in linux kernel.
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
This patch invokes board-specific USB cleanup (board_usb_cleanup)
function in the mass storage gadget
Signed-off-by: Inha Song <ideal.song@samsung.com>
Since we support multiple dwc3 controllers to be existent at the same
time, in order to handle the interrupts of a particular dwc3 controller
usb_gadget_handle_interrutps should take controller index as an
argument.
Hence the API of usb_gadget_handle_interrupts is modified to take
controller index as an argument and made the corresponding changes to all
the usb_gadget_handle_interrupts calls.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Enabled dwc3, dwc3-omap and PHY for dwc3 are enabled. Also enabled
support for DFU.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Implemented board_usb_init(), board_usb_cleanup() and
usb_gadget_handle_interrupts() in am43xx board file that
can be invoked by various gadget drivers.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Enabled dwc3, dwc3-omap and PHY for dwc3 are enabled. Also enabled
support for DFU.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Implemented board_usb_init(), board_usb_cleanup() and
usb_gadget_handle_interrupts() in dra7xx board file that
can be invoked by various gadget drivers.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Invoked board_usb_cleanup for cleaning up initialized USB. It
will be invoked if the user enterts ctrl-C.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Taken from linux kernel with commit
commit 765f5b830e547229bb752e7b232ee83e2b3d49d5
Author: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Date: Thu Jun 23 14:26:11 2011 +0200
usb: gadget: defer setting maxpacket till ->setup()
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Now that the entire dwc3 driver is adapted to compile with uboot build,
modify the Makefiles so that the dwc3 driver can be built.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
dwc3 can do only max packet aligned transfers. So in case request length
is not max packet aligned and is bigger than DWC3_EP0_BOUNCE_SIZE
two chained TRBs is required to handle the transfer.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
No functional change. Modified few things so that there are no
code duplication while implementing chained TRB.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
In the linux kernel, non cacheable buffers are used. However in uboot
since there are no APIs to allocate non cacheable memory, all
the buffers should be flushed before using it.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Added a single driver for both USB2 PHY programming and USB3 PHY
programming.
USB3 PHY is taken from drivers/phy/phy-ti-pipe3.c in linux kernel.
commit 56042e : phy: ti-pipe3: Fix suspend/resume and module reload.
USB2 PHY is taken from drivers/phy/phy-omap-usb2.c in linux kernel.
commit eb82a3 : phy: omap-usb2: Balance pm_runtime_enable() on probe
failure and remove.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Added an API to check for interrupt status. This API is generally
called from board file to check for interrupt status.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Added support for multiple dwc3 omap controllers. This gives uboot
the capability to control multiple dwc3 omap controllers.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Removed probe and remove that are specific to linux and replaced it with
uboot init and uboot exit. These functions will be invoked from boardfile.
This will change once we have dwc3-omap driver adapted to use the uboot
driver model.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Added a structure to populate dwc3 omap platform data. The board file should
populate these platform data before invoking dwc3 omap driver.
This will be removed once dwc3-omap driver is adapted to use the driver model.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
*) Changed the included header files to that used in u-boot.
*) Removed extcon_* APIs
*) Removed regulator_* APIs
*) Fixed other misc warnings
*) Added dwc3-omap.h to include the definitions of UTMI modes.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Since interrupt support is not present in u-boot, added an
API to handle the interrupts in dwc3 core. This API can be
polled to handle the interrupts.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Added support for multiple dwc3 controllers. This gives uboot
the capability to control multiple dwc3 controllers.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Removed probe and remove that are specific to linux and replaced it with
uboot init and uboot exit. These functions will be invoked from boardfile.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Added a structure to populate dwc3 core platform data. The board file should
populate these platform data before invoking dwc3 driver.
This will be removed once we have dwc3 driver adapted to use the driver model.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
*) Changed the include header files to that used in u-boot.
*) Removed phy_* APIs
*) Removed jiffies and used a simple while loop
*) Used dma_alloc_coherent and dma_free_coherent APIs of u-boot
*) Fixed other misc warnings
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Added USB_GADGET_DELAYED_STATUS to avoid the following compilation error.
error: ‘USB_GADGET_DELAYED_STATUS’ undeclared (first use in this function)
while compiling dwc3/ep0.c
While this is been added only to avoid compilation error, the complete fix
should be something like the one added in linux kernel. The complete fix
will be ported once we have the composite driver in u-boot look similar to
the one in linux kernel.
commit 1b9ba000177ee47bcc5b44c7c34e48e735f5f9b1
Author: Roger Quadros <roger.quadros@nokia.com>
Date: Mon May 9 13:08:06 2011 +0300
usb: gadget: composite: Allow function drivers to pause control transfers
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
*) Changed the included header files to that used in u-boot.
*) added dwc3_ep_event_string() used in ep0.c
*) Fixed other misc warnings
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Added resource_size_t type in order to get rid of the following
compilation error whiel building dwc3 gadget.
include/linux/ioport.h:19:2: error: unknown type name ‘resource_size_t’
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Did a bunch of things to get dwc3/gadget.c compile in u-boot without
build errors and warnings
*) Changed the included header files to that used in u-boot.
*) Used dma_alloc_coherent and dma_free_coherent APIs of u-boot
*) removed sg support
*) remove jiffies and used a simple while loop
*) removed irq support and added a function to call these interrupt handler.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Added a header file to include various linux specific APIs like
pr_debug, WARN_ WARN_ON_ONCE etc.. in order to avoid compilation
error while building dwc3 driver.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Added dma_free_coherent corresponding to the dma_alloc_coherent in
dma-mapping.h in order to free memory allocated using dma_alloc_coherent.
This API is used in dwc3 driver.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Removed all pm related operations including pm_runtime APIs,
suspend/resume hooks as support for these are not present in u-boot.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Changed the header files included in core.h and io.h to the u-boot header
files so that these files can be included in other dwc3 source files and
be compiled in uboot. Also added otg.h which has the defines for dr_mode.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Removed most of the trace_* APIs from dwc3 driver since tracepoints are not
supported in u-boot. Replaced some of the trace_* API with dev_dbg/dev/vdbg.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Review-by: Lukasz Majewski <l.majewski@samsung.com>
Modified the file header to the format that is used in u-boot. Also
included in the header, the commit in linux kernel from which each of
these files are added.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
removed un-used/un-supported files from dwc3. These files can be added
later as and when the support is added.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Added dwc3 folder from linux kernel 3.19-rc1 (97bf6af1f9)
to u-boot. This will be adapted to work with u-boot in the
following patches.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Fixed the following warning here.
"warning: ‘dma_alloc_coherent’ defined but not used" while compiling
udc-core
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Make udc-core compile in u-boot by removing all linux specific
stuff and having only the bare minimal udc-core required for
usb gadget drivers. Also modified the file header to a format that is
generally being used in u-boot.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Made changes in gadget.h that is required after adding udc-core.c
except changes that might break other platforms.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Added udc-core.c from linux kernel 3.19-rc1 (97bf6af1f9) to u-boot.
This will be adapted to work with u-boot in the
following patches.
Adding support for udc will help to seamlessly port dwc3 driver from
linux kernel to u-boot (since dwc3 uses udc-core) and it'll also help
to add support for multiple gadget controllers to be functional at the
same time.
All other gadget drivers can also be adapted to use udc-core.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Enabled clocks for dwc3 controller and USB PHY present in AM43xx.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Enabled clocks for dwc3 controller and USB PHY present in DRA7.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
IIUC, interrupt transfers are NAK'd by devices until they wish to trigger
an interrupt, and e.g. EHCI controllers retry these in HW until they are
ACK'd. However, DWC2 doesn't seem to retry, so we need to do this in SW.
In practice, I've seen DWC2_HCINT_FRMOVRUN happen too. I'm not quite sure
what this error implies; perhaps it's related to how near the end of a
USB frame we're at when the interrupt transfer is initiated? Anyway,
retrying this temporary error seems to be necessary too.
With all these commits applied, both my USB keyboards (one LS Lenovo and
one FS Dell) work correctly when there is no USB hub between the SoC and
the keyboard; We still need split transactions to be implemented for hubs
to work.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
As best I can tell, there's no difference between bulk and interrupt
transfers in terms of how the HW should be programmed, at least given
that we're executing one transaction at a time rather than scheduling
them into frames for maximum throughput.
This patch ends up sharing the toggle bit state between bulk and
interrupt transfers on a particular EP. However I believe this is fine;
AFAIK a given EP either uses bulk or interrupt transfers and doesn't mix
them.
This patch doesn't do anything with the "interval" parameter for
interrupt transfers, but then most other USB controller drivers in U-Boot
don't either.
It turns out that one of my keyboards is happy to work using control
transfers but the other only gives non-zero "HID reports" via interrupt
transfers.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
A bit must be set in HCCHAR when communicating with low-speed devices.
I have no idea why there's no corresponding bit to distinguish between
full-speed and high-speed devices, but no matter; they all work now!
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
When we communicate with the VideoCore to perform property mailbox
transactions, that is a DMA operation as far as the property buffer
is concerned. Use phys_to_bus() on that buffer.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
This doesn't make my LS keyboard work any better, but it does at least
report the correct speed in "usb tree".
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Use of these APIs is required on the Raspberry Pi. With this change, USB
on RPi1 should be more reliable, and USB on the RPi2 will start working.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
The BCM283[56] contain both a L1 and L2 cache between the GPU (a/k/a
VideoCore CPU?) and DRAM. DMA-capable peripherals can also optionally
access DRAM via this same L2 cache (although they always bypass the L1
cache). Peripherals select whether to use or bypass the cache via the
top two bits of the bus address.
An IOMMU exists between the ARM CPU and the rest of the system. This
controls whether the ARM CPU's accesses use or bypass the L1 and/or L2
cache. This IOMMU is configured/controlled exclusively by the VideoCore
CPU.
In order for DRAM accesses made by the ARM core to be coherent with
accesses made by other DMA peripherals, we must program a bus address
into those peripherals that causes the peripheral's accesses to use the
same set of caches that the ARM core's accesses will use.
On the RPi1, the VideoCore firmware sets up the IOMMU to enable use of
the L2 cache. This corresponds to addresses based at 0x40000000.
On the RPi2, the VideoCore firmware sets up the IOMMU to disable use of
the L2 cache. This corresponds to addresses based at 0xc0000000.
This patch implements U-Boot's phys_to_bus/bus_to_phys APIs according
to those rules.
For full details of this setup, please see Dom Cobley's description at:
http://lists.denx.de/pipermail/u-boot/2015-March/208201.htmlhttp://permalink.gmane.org/gmane.comp.boot-loaders.u-boot/215038https://www.mail-archive.com/u-boot@lists.denx.de/msg166568.html
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
On some SoCs, DMA-capable peripherals see a different address space to
the CPU's physical address space. Create an API to allow platform-agnostic
drivers to convert between the two address spaces when programming DMA
operations.
This API will exist on all platforms, but will have a dummy implementation
when this feature is not required. Other platforms will enable
CONFIG_PHYS_TO_BUS and provide the required implementation.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
When I created wait_for_chhltd(), I noticed that some instances of the
code it replaced expected the ACK bit to be set and others didn't. I
assumed this was an accidental inconsistency in the code, so wrote
wait_for_chhltd() to always expect ACK to be set. This code appeared to
work correctly for both enumeration of USB keyboards and operation of
USB Ethernet devices. However, this change broke USB Mass Storage (at
least my USB SD card reader). This change reverts to exactly the
original behaviour. I'm not sure why the ACK bit isn't always set
(perhaps a quirk in the USB HW or DWC2 controller), but the code works
this way!
Fixes: 5be4ca7d6ac8 ("usb: dwc2: unify waiting for transfer completion")
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Each USB transfer is split up into chunks that are held in an aligned
buffer. This imposes a limit on the size of each chunk, but no limit on
the total size of transferred data. Fix the logic in chunk_msg() not to
reject large transfers, but simply take the size of the aligned buffer
into account when calculating the chunk size.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
The original aligned_buffer usage:
a) Uselessly copied data into the aligned buffer even for IN
transactions. Fix this my making the copy conditional.
b) Always programmed the HW to transfer to/from the start of the aligned
buffer. This worked fine for OUT transactions since the memcpy copied
the OUT data to this location too. However, for large IN transactions,
since the copy from the aligned buffer to the "client" buffer was
deferred until after all chunks were transferred. it resulted in each
chunk's transfer over-writing the data for the first transfer. Fix
this by copying IN data as soon as it's received.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
The control data toggle resets to DATA1 at the start of the data phase
of every setup transaction. We don't need a global variable to store
the value; we can just store it on the stack.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Move the body of submit_bulk_msg() into new function chunk_msg(). This
can be shared with submit_control_msg() to reduce code duplication, and
allow control messages larger than maxpacket.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Some USB devices break the spec and require longer warm-up times. Allow
the usb_pgood_delay env variable to override the calculated time.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
When fetching the first descriptor from a new device, only validate that
we received at least 8 bytes, not that we received the entire descriptor.
The reasoning is:
- The code only uses fields in the first 8 bytes, so that's all we need
to have fetched at this stage.
- The smallest maxpacket size is 8 bytes. Before we know the actual
maxpacket the device uses, the USB controller may only accept a single
packet (see the DWC2 note in the comment added in the commit).
Consequently we are only guaranteed to receive 1 packet (at least 8
bytes) even in a non-error case.
Fixes: 1a7758044b04 ("usb: Early failure when the first descriptor read
fails or is invalid")
Cc: Paul Kocialkowski <contact@paulk.fr>
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
This may happen when using an USB1 device on a controller that only supports
USB2 (e.g. EHCI). Reading the first descriptor will fail (read 0 byte), so we
can abort the process at this point instead of failing later and wasting time.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
This checks that a new USB device is correctly initialized and frees it if not.
In addition, this doesn't report that USB was started when no device was found.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
This patch fixes USB storage capacity detection breakage on 64-bit systems
which arises due to 'unsigned long' length difference. Old code assumes that
to be 32 bit and breaks because of inappropriate response buffer layout.
Also this fixes a number of build warnings and changes big-endian values
treatment style to be architecture-independent
Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com>
Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com>
This commit allows xHCI to use both 64 and 32 bit memory
physical addresses depending on architecture it's being built for.
Also it makes use of readq()/writeq() on 64-bit systems
Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com>
Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com>
This patch converts USB protocol headers to use explicitly sized
fields like the rest of the code
Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com>
Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com>
Cast pointers to unsigned long instead of a sized 32-bit type to avoid
pointer to integer cast size mismatch warnings.
Cc: Tom Warren <twarren@nvidia.com>
Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Change addresses to unsigned long to be compatible with 64-bit builds.
Regardless of fixing warnings, the device is still only 32-bit capable.
Signed-off-by: Rob Herring <robh@kernel.org>
Cc: Marek Vasut <marex@denx.de>
Change addresses to unsigned long to be compatible with 64-bit builds.
Regardless of fixing warnings, the device is still only 32-bit capable.
Signed-off-by: Rob Herring <robh@kernel.org>
Cc: "Łukasz Majewski" <l.majewski@samsung.com>
Cc: Marek Vasut <marex@denx.de>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Mass storage is not necessary present on interface 0. This
patch allow usb_stor_scan to look in every available interface.
Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
2015-04-14 05:47:47 +02:00
5298 changed files with 336828 additions and 114482 deletions
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