Add 'Peng Fan' as MAINTAINERS of configs/mx6ull_14x14_evk_plugin_defconfig
which is missing in below commit
"imx: mx6ull_14x14_evk: add plugin defconfig"
(sha1: b90ebf49bb)
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jagan Teki <jagan@openedev.com>
The SPL load address changes based on boot type in HS devices,
ISW_ENTRY_ADDR is used to set this address for AM43xx based SoCs
for similar reasons. Add this same logic for AM33xx devices.
Also make the default value for ISW_ENTRY_ADDR correct for GP
devices based on SoC, HS devices already pick the correct
value in their defconfig.
Signed-off-by: Andrew F. Davis <afd@ti.com>
When TI_SECURE_DEV_PKG is not defined we warn that the file '*_HS' was
not generated but generate an unsigned one anyway, first fix this
warning to say that it was generated but not secured.
When the user then exports TI_SECURE_DEV_PKG after getting this warning,
and tries to re-build, 'make' will detect the build artifacts as
unchanged and so assume they do not need to be re-generated. This causes
it to fail to sign the files and it will pack unsigned files into the
final image, even though TI_SECURE_DEV_PKG is now correctly defined and
working.
Fix this by using FORCE on the targets causes them to be re-run even if
the dependent files have not changed.
This then causes another issue. We currently rename the signed dtb files
to overwrite the non-signed ones. We do this so the 'mkimage' tool gives
the packaged dtb sections the correct name. If we do not rename the files
then SPL will not find them during boot.
Fix this by renaming the dtb files by appending _HS to the end of the
filename, after the ".dtb", this causes them to still be named correctly
in the FIT blob.
Signed-off-by: Andrew F. Davis <afd@ti.com>
These two macros are used for the same thing, the total number of DDR
controllers for a given SoC. Use SYS_NUM_DDR_CTRLS in Kconfig and
merge existing usage.
Signed-off-by: York Sun <york.sun@nxp.com>
Use option NUM_DDR_CONTROLLERS in ddr Kconfig and clean up existing
usage in ls102xa and fsl-layerscape. Remove all powerpc macros in
config header and board header files.
Signed-off-by: York Sun <york.sun@nxp.com>
Add option SYS_FSL_ERRATUM_ESDHC111, SYS_FSL_ERRATUM_ESDHC13,
SYS_FSL_ERRATUM_ESDHC135, SYS_FSL_ERRATUM_ESDHC_A001 to mmc Kconfig.
Move existing macros to related Kconfig.
Signed-off-by: York Sun <york.sun@nxp.com>
[trini: Migrate bk4r1]
Signed-off-by: Tom Rini <trini@konsulko.com>
Create driver/ddr/fsl/Kconfig and move existing options. Clean up
existing macros.
Signed-off-by: York Sun <york.sun@nxp.com>
[trini: Migrate sbc8641d, xpedite537x and MPC8536DS, run a moveconfig.py -s]
Signed-off-by: Tom Rini <trini@konsulko.com>
Use TARGET_T1024RDB from Kconfig instead.
Signed-off-by: York Sun <york.sun@nxp.com>
[trini: Get missing hunk in board/freescale/t102xrdb/ddr.c]
Signed-off-by: Tom Rini <trini@konsulko.com>
Instead of define CONFIG_SYS_FSL_SEC_COMPAT in header files for PowerPC
and ARM SoCs, move it to Kconfig under the driver.
Signed-off-by: York Sun <york.sun@nxp.com>
Use Kconfig SYS_PPC_E500_DEBUG_TLB and clean up existing macros.
Signed-off-by: York Sun <york.sun@nxp.com>
[trini: Migrate 8572]
Signed-off-by: Tom Rini <trini@konsulko.com>
SPL from nand will print 'NAND' in boot_from_devices based on
the image_loader name, remove the extra 'NAND ' in mxs_nand_spl driver.
Original behaviour:
-------------------
U-Boot SPL 2017.01-rc2-gf84dd8b (Jan 02 2017 - 22:24:19)
Trying to boot from NANDNAND : 512 MiB
After the fix:
-------------
U-Boot SPL 2017.01-rc2-gf84dd8b-dirty (Jan 02 2017 - 23:17:00)
Trying to boot from NAND: 512 MiB
Cc: Tom Rini <trini@konsulko.com>
Signed-off-by: Jagan Teki <jagan@openedev.com>
According to Section 11.15.4.9.1 Indirect Read Controller of K2G SoC
TRM SPRUHY8D[1], the external master is only permitted to issue 32-bit
data interface reads until the last word of an indirect transfer
So, make sure that QSPI indirect reads are 32 bit sized except for the
final read. If the rxbuf is unaligned then use bounce buffer, so that
readsl() can be used instead of readsb() to avoid non 32-bit accesses.
[1]www.ti.com/lit/ug/spruhy8d/spruhy8d.pdf
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagan Teki <jagan@openedev.com>
According to Section 11.15.4.9.2 Indirect Write Controller of K2G SoC
TRM SPRUHY8D[1], the external master is only permitted to issue 32-bit
data interface writes until the last word of an indirect transfer
otherwise indirect writes is known to fails sometimes. So, make sure
that QSPI indirect writes are 32 bit sized except for the last write. If
the txbuf is unaligned then use bounce buffer to avoid data aborts.
So, now that the driver uses bounce_buffer, enable CONFIG_BOUNCE_BUFFER
for all boards that use Cadence QSPI driver.
[1]www.ti.com/lit/ug/spruhy8d/spruhy8d.pdf
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Fix ULPI reset polarity which caused a hard hang on Colibri T20 upon
attempting to start the USB subsystem:
This fixes my late commit d5a24d8b53
(colibri_t20: fix usb operation and controller order) inadvertently
having overwritten Stephen's previous commit
2f6a7e8ce5 (ARM: tegra: fix USB ULPI PHY
reset signal inversion confusion).
While at it also fix comment about on-module USB port.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Some users may wish to pass the cboot-supplied DTB to the booted kernel
rather than having U-Boot load the DTB itself. To allow this, expose the
address of the cboot-supplied DTB in environment variable $fdt_addr. At
least when using extlinux.conf, if the user doesn't explicitly specify
which DTB to pass to the kernel, U-Boot passes the DTB referred to by
this variable.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Enabling FIT along with Signature will make bootm to
not-understanding u-boot legacy image formats like uImage, etc.
So this patch enabling legacy image format for backward compatibility.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
For writing Linux or rootfs on to NAND, the best suitable way
is to use MMC commands since MMC driver by default enabled by
mx6_common.h, hence enabled MMC commands in nand defconfigs.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
gpmi-nand is the proper name used in nand driver from Linux for all
imx related nand boards, so rename mtdparts name as gpmi-nand instead
of nand, this will eventually reflects all nand info to Linux from
u-boot like mtdparts.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Add MAC support.
Use PHY, connected to RGMII1 as a default Eth adapter,
by appropriate setting of 'cpsw_data.active_slave'.
'cpsw_phy' env variable can override this setting.
Set the MAC addresses in the U-Boot environment.
The addresses are retrieved from the on-board EEPROM or from the SOC's
MAC fuses.
Set the following PHYs RGMII clock delays:
- Enable RX delay
- Disable TX delay
Signed-off-by: Dmitry Lifshitz <lifshitz@compulab.co.il>
[uri.mashiach@compulab.co.il: add RGMII clock delays]
Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Reviewed-by: Tom Rini <trini@konsulko.com>
Features supported :
* Serial console
* SPI Flash
* MMC/SD Card
* eMMC storage
* SATA
* PCA9555 - GPIO expander over I2C5 bus
* USB
Use spl alternate boot device feature to define fallback to
the main boot device as it is defined by hardware.
Signed-off-by: Dmitry Lifshitz <lifshitz@compulab.co.il>
[uri.mashiach@compulab.co.il: Adjust to v2016.11]
Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Some OS (all BSD and probably others) do not have python in /usr/bin
but in another directory.
It is a common usage to use /usr/bin/env python as shebang for python
scripts so use this for binman.
Signed-off-by: Emmanuel Vadot <manu@bidouilliste.com>
The display is done in the device tree now, and there is no need
to pass 'display' kernel parameter any longer.
Signed-off-by: Adam Ford <aford173@gmail.com>
First, update the code snippet referenced in the README file. And
since there are only two boards that override flash_cmd_reset(),
might as well show them both.
Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
On the MX6Q the aclk_eim_slow_podf field is '1' after POR, while on the
MX6DQP it is '3'.
This makes the EIM clock to be only 66MHz on the mx6qp variant, instead of
132 MHz.
Instead of relying on the POR values for the CSMR1 register, make sure to
manually configure the clk_eim_slow_sel field as '00' so that EIM clock is
derived from AXI clock and the aclk_eim_slow_podf field as '1' so that EIM
clock can be AXI clock divided by 2.
This way a consistent EIM clock frequency is configured for all the mx6
variants.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Enable USB gadget ethernet by default to have networking capabilities.
Tested using DHCP and TFTP to transfer kernel, DT, ramdisk.
Cc: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
'fdtfile' is the preferred name for the variable that contains the
device tree blob according to the README file.
It also makes it consistent with other i.MX boards that use config_distro,
so change it accordingly.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
To being able to sign created binaries, we need to know the HAB Blocks
for that image. Especially for the imximage type the HAB Blocks are
only available during creation of the image. We want to preserve the
information until we get to sign the files.
In the verbose case we still get them printed out instead of writing
to log files.
Cc: sbabic@denx.de
v2-Changes:
- No usage of MKIMAGEOUTPUT_$(@F) macro.
- Predefine default value /dev/null in every involved Makefile.
Signed-off-by: Sven Ebenfeld <sven.ebenfeld@gmail.com>
Reviewed-by: George McCollister <george.mccollister@gmail.com>
Tested-by: George McCollister <george.mccollister@gmail.com>
When we want to use Secure Boot with HAB from SPL over U-Boot.img,
we need to append the IVT to the image and leave space for the CSF.
Images generated as firmware_ivt can directly be signed using the
Freescale code signing tool. For creation of a CSF, mkimage outputs
the correct HAB Blocks for the image.
The changes to the usual firmware image class are quite small,
that is why I implemented that directly into the default_image.
Cc: sbabic@denx.de
v2-Changes: None
Signed-off-by: Sven Ebenfeld <sven.ebenfeld@gmail.com>
Reviewed-by: George McCollister <george.mccollister@gmail.com>
Tested-by: George McCollister <george.mccollister@gmail.com>
When using HAB as secure boot mechanism on Wandboard, the chain of
trust breaks immediately after the SPL. As this is not checking
the authenticity of the loaded image before jumping to it.
The HAB status output will not be implemented in SPL as it adds
a lot of strings that are only required in debug cases. With those
it exceeds the maximum size of the available OCRAM (69 KiB).
The SPL MISC driver support must be enabled, so that the driver can use OTP fuse
to check if HAB is enabled.
Cc: sbabic@denx.de
v2-Changes: None
Signed-off-by: Sven Ebenfeld <sven.ebenfeld@gmail.com>
Reviewed-by: George McCollister <george.mccollister@gmail.com>
Tested-by: George McCollister <george.mccollister@gmail.com>
These files are blowing up the SPL and should not be required
there as the SPL delivers no command console. Because building fails
for mx27 and mx31 machines with SPL build, we remove the linker flag
for them from the Makefile. Nothing is built for them to be linked
in that directory.
Cc: sbabic@denx.de
v2 Changes:
- Remove mx27 and mx31 from Makefile during SPL build as nothing is built for
them in that directory. And removing the commands with the libs-y directive
lead to linker failures. e.g. "armv5te-ld.bfd: cannot find arch/arm/imx-common/built-in.o: No such file or directory)"
Signed-off-by: Sven Ebenfeld <sven.ebenfeld@gmail.com>
Reviewed-by: George McCollister <george.mccollister@gmail.com>
Tested-by: George McCollister <george.mccollister@gmail.com>
Commit c94981efa2 ("udoo_neo: Remove USDHC3 support") removed
the SDHC3 support, but missed to remove the entry from the usdhc_cfg
structure, so just remove it.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
This is a user-unconfigurable option that is selected by the
drivers that need to overwrite SDHCI IO memory accessors.
(BCM2835 SDHCI seems the only driver that needs to do so.)
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
While I moved the options, I also renamed them so that they are all
prefixed with MMC_SDHCI_.
This commit was created in the following steps.
[1] Rename with the following command
find . -name .git -prune -o ! -path ./scripts/config_whitelist.txt \
-type f -print | xargs sed -i -e '
s/CONFIG_MMC_SDMA/CONFIG_MMC_SDHCI_SDMA/g
s/CONFIG_BCM2835_SDHCI/CONFIG_MMC_SDHCI_BCM2835/g
s/CONFIG_KONA_SDHCI/CONFIG_MMC_SDHCI_KONA/g
s/CONFIG_MV_SDHCI/CONFIG_MMC_SDHCI_MV/g
s/CONFIG_S5P_SDHCI/CONFIG_MMC_SDHCI_S5P/g
s/CONFIG_SPEAR_SDHCI/CONFIG_MMC_SDHCI_SPEAR/g
'
[2] create the Kconfig entries in drivers/mmc/Kconfig
[3] Move the options by the following command
tools/moveconfig.py -y MMC_SDHCI_SDMA MMC_SDHCI_BCM2835 \
MMC_SDHCI_KONA MMC_SDHCI_MV MMC_SDHCI_S5P MMC_SDHCI_SPEAR
[4] Sort drivers/mmc/Makefile for readability
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Move CONFIG_SDHCI to Kconfig and rename it to CONFIG_MMC_SDHCI.
My motivation for the rename is, ultimately, to make all the MMC
options prefixed with MMC_ and SDHCI options with MMC_SDHCI_,
like Linux.
This commit was created as follows:
[1] Rename the config option with the following command:
find . -name .git -prune -o ! -path ./scripts/config_whitelist.txt \
-type f -print | xargs sed -i -e 's/CONFIG_SDHCI/CONFIG_MMC_SDHCI/g'
[2] create the entry for MMC_SDHCI in drivers/mmc/Kconfig
[3] run "tools/moveconfig.py -y MMC_SDHCI"
[4] add "depends on MMC_SDHCI" to existing SDHCI driver entries
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Currently, CONFIG_MMC is not related to any other options by
"depends on" or "select". One of big advantages of using Kconfig
is automatic dependency tracking, but the current state is lacking
it. As the first step, make the existing MMC driver entries depend
on MMC.
This commit was created by the following steps:
[1] Run the following script:
--------------------8<--------------------
rm -f tmp.txt
for d in $(find . -path './configs/*_defconfig')
do
if grep -q -e 'CONFIG_MSM_SDHCI=y' $d ||
grep -q -e 'CONFIG_ATMEL_SDHCI=y' $d ||
grep -q -e 'CONFIG_ROCKCHIP_DWMMC=y' $d ||
grep -q -e 'CONFIG_SH_SDHI=y' $d ||
grep -q -e 'CONFIG_PIC32_SDHCI=y' $d ||
grep -q -e 'CONFIG_ZYNQ_SDHCI=y' $d ||
grep -q -e 'CONFIG_ROCKCHIP_SDHCI=y' $d ||
grep -q -e 'CONFIG_MMC_UNIPHIER=y' $d ||
grep -q -e 'CONFIG_SANDBOX_MMC=y' $d
then
echo CONFIG_MMC=y >> $d
echo ${d#./configs/} >> tmp.txt
fi
done
tools/moveconfig.py -y -s -d tmp.txt
rm tmp.txt
--------------------8<--------------------
[2] surround MMC driver entries with "if MMC" and "endif"
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Commit 7a777f6d6f ("mmc: Add generic Kconfig option") created
a Kconfig entry for this option without any actual moves, then
commit 44c798799f ("sunxi: Use Kconfig CONFIG_MMC") moved
instances only for SUNXI.
We generally do not like such partial moves. This kind of work
is automated by tools/moveconfig.py, so it is pretty easy to
complete this move.
I am adding "default ARM || PPC || SANDBOX" (suggested by Tom).
This shortens the configs and will ease new board porting.
This commit was created as follows:
[1] Edit Kconfig (remove the "depends on", add the "default",
copy the prompt and help message from Linux)
[2] Run 'tools/moveconfig.py -y -s -r HEAD MMC'
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
In commit 7044c6bb6 (net: cosmetic: Clean up DHCP variables and functions)
BootpCopyNetParams() was renamed to store_net_params(). Update the reference in
comment.
Cc: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
With capacities getting bigger, we can see see messages with negative
numbers like "Capacity: 1907729.0 MB = 1863.0 GB (-387938128 x 512)".
Here the printed LBA is -387938128 when it should have been 3907029168.
To fix this, use the right format when displaying the unsigned integers.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reported-by: Yan Liu <yan-liu@ti.com>
This patch is fixing missing fclose() calls
in error patch introduced by:
"tools: mkimage: Use fstat instead of stat to avoid malicious hacks"
(sha1: ebe0f53f48)
Reported-by: Coverity (CID: 155064, 155065)
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Commit be72591bcd ("Kconfig: Move USE_ARCH_MEMCPY/MEMSET to
Kconfig") is misconversion.
The original logic in include/configs/uniphier.h was as follows:
#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_ARM64)
#define CONFIG_USE_ARCH_MEMSET
#define CONFIG_USE_ARCH_MEMCPY
#endif
This means those configs were enabled when building U-Boot proper,
but disabled when building SPL. Likewise for Tegra.
Now "depends on !SPL" prevents any boards with SPL support
from reaching these options. This changed the behavior for
UniPhier and Tegra SoC family.
Please notice these two options only control the U-Boot proper
build. As you see arch/arm/Makefile, ARM-specific memset/memcpy
are never compiled for SPL. So, __HAVE_ARCH_MEMCPY/MEMSET should
not set for SPL.
Fixes: be72591bcd ("Kconfig: Move USE_ARCH_MEMCPY/MEMSET to Kconfig")
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Przemyslaw didn't maintain the PMIC anymore.
Update the pmic maintainer from Przeymyslaw to me.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Instead of shuffling bits from two adjacent 16 bit words, use one 16 bit
word with the appropriate byte offset in the buffer.
Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
get_fatent_value(...) flushes changed FAT entries to disk when fetching
the next FAT blocks, in every other aspect it is identical to
get_fatent(...).
Provide a stub implementation for flush_dirty_fat_buffer if
CONFIG_FAT_WRITE is not set. Calling flush_dirty_fat_buffer during read
only operation is fine as it checks if any buffers needs flushing.
Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
The FAT is read/flushed in segments of 6 (FATBUFBLOCKS) disk sectors. The
last segment may be less than 6 sectors, cap the length.
Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
Fix "Memory" and "initialize" typos in the CMD_MEMORY help text.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
The u-boot command fatwrite empties FAT clusters from the beginning
till the end of the file.
Specifically for FAT12 it fails to detect the end of the file and goes
beyond the file bounds thus corrupting the file system.
Additionally, FAT entry chaining-up into a file is not implemented
for FAT12.
The users normally workaround this by re-formatting the partition as
FAT16/FAT32, like here:
https://github.com/FEDEVEL/openrex-uboot-v2015.10/issues/1
The patch fixes the bounds of a file and FAT12 entries chaining into
a file, including EOF markup.
Signed-off-by: Philipp Skadorov <philipp.skadorov@savoirfairelinux.com>
Use the endian macros from u-boot's compiler.h instead of duplicating
the definitions.
This also avoids a build error on OpenBSD by removing swap64 which
collides with a system definition in endian.h pulled in by inttypes.h.
Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Earlier timer driver needed a clock-frequency property in compatible
device-tree nodes. Another way is to reference a clock via a phandle.
So now timer_pre_probe tries to get clock by reference through device
tree. In case it is impossible to get clock device through the
reference, clock-frequency property of the timer node is read to provide
backward compatibility.
Signed-off-by: Vlad Zakharov <vzakhar@synopsys.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add support to handle enable-active-high DT property. This property is
used to drive the gpio controlling fixed regulator as active high when
claiming gpio line.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Acked-by: Simon Glass <sjg@chromium.org>
Now that we have added file names from Kconfig in x86 u-boot.dtsi,
update binman to avoid using hard-coded names.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Since we already have a bunch of Kconfig options for CMC/FSP/VGA file
names, add these from Kconfig in the corresponding dts nodes.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
With the conversion to use binman to build x86 boards, Intel Galileo
board does not build anymore due to missing ucode entry. In fact
ucode is not needed for quark-based boards.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
To use driver-model adds the pmic node for max8998.
This is used as kerel device-tree in Linux.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Add the max8998 controller for Driver model.
Samsung S5P series are using max8998 pmic controller.
In future, it should be supported the regulator framework.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Remove the entire spear_sdhci.c file.
There is no use case. This is dead codes.
Also there is no place to call "spear_sdhci_init()" anywhere.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Fix the MMU mapping for A8K device family:
- Separate A7K and A8K memory mappings
- Fix memory regions by including IO mapping for all
3 PCIe interfaces existing on each connected CP110 controller
Add A8K memory mapping documentation with all regions
configured by Marvell ATF.
Change-Id: I9c930569b1853900f5fba2d5db319b092cc7a2a6
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
When setting the compatible property for the L2 cache ensure that we
follow the documented binding by setting both
"<chip>-l2-cache-controller" and "cache" as values.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: York Sun <york.sun@nxp.com>
H3 SID controller has some bug, which makes the initial SID value at
SUNXI_SID_BASE wrong when boot.
Change the SID retrieve code to call the SID Controller directly on H3,
which can get the correct value, and also fix the SID value at
SUNXI_SID_BASE, so that it can be used by further operations.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
The dram_init and dram_init_banksize functions were using a board
specific implementation for decoding the memory banks from the fdt. This
board specific implementation uses a static variable 'tmp' which makes
these functions unsafe for execution from within the board_init_f
context.
This change makes the dram_init* functions use a generic implementation
of decoding and populating memory bank and size data.
Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
Fixes: 8d59d7f63b ("ARM64: zynqmp: Read RAM information from DT")
Cc: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The dram_init and dram_init_banksize functions were using a board
specific implementation for decoding the memory banks from the fdt. This
board specific implementation uses a static variable 'tmp' which makes
these functions unsafe for execution from within the board_init_f
context.
This unsafe use of a static variable was causing a specific bug when
using the zynq_zybo configuration, U-Boot would generate the following
error during image load. This was caused due to dram_init overwriting
the relocations for the 'image' variable within the do_bootm function.
Out of coincidence the un-initialized memory has a compression type
which is the same as the value for the relocation type R_ARM_RELATIVE.
Uncompressing Invalid Image ... Unimplemented compression type 23
It should be noted that this is just one way the issue could surface,
other cases my not be observed in normal boot flow. Depending on the
size of various sections, and location of relocations within __rel_dyn
and the compiler/linker the outcome of this bug can differ greatly.
This change makes the dram_init* functions use a generic implementation
of decoding and populating memory bank and size data.
Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
Fixes: 758f29d0f8 ("ARM: zynq: Support systems with more memory banks")
Cc: Michal Simek <monstr@monstr.eu>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add two functions for use by board implementations to decode the memory
banks of the /memory node so as to populate the global data with
ram_size and board info for memory banks.
The fdtdec_setup_memory_size() function decodes the first memory bank
and sets up the gd->ram_size with the size of the memory bank. This
function should be called from the boards dram_init().
The fdtdec_setup_memory_banksize() function decode the memory banks
(up to the CONFIG_NR_DRAM_BANKS) and populates the base address and size
into the gd->bd->bi_dram array of banks. This function should be called
from the boards dram_init_banksize().
Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Michal Simek <monstr@monstr.eu>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Stop boot process if fpga programming fails.
Without this patch boot process continues even if fpga programming
failed.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This patch also includes ARM64 zynqmp changes:
- Remove platform non DM initialization
- Remove hardcoded sata base address
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
All sata based drivers are bind and corresponding block
device is created. Based on this find_scsi_device() is able
to get back block device based on scsi_curr_dev pointer.
intr_scsi() is commented now but it can be replaced by calling
find_scsi_device() and scsi_scan().
scsi_dev_desc[] is commented out but common/scsi.c heavily depends on
it. That's why CONFIG_SYS_SCSI_MAX_DEVICE is hardcoded to 1 and symbol
is reassigned to a block description allocated by uclass.
There is only one block description by device now but it doesn't need to
be correct when more devices are present.
scsi_bind() ensures corresponding block device creation.
uclass post_probe (scsi_post_probe()) is doing low level init.
SCSI/SATA DM based drivers requires to have 64bit base address as
the first entry in platform data structure to setup mmio_base.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
By adding labels to the cpu nodes in the dtsi, a dts that
includes it can change the OPPs by referencing the cpu0
through the label.
[Based on linux (400b6a0cbef55d1ae32808eaa1ef1c28820bf6ac)]
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: u-boot@lists.denx.de
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
axi_emac, emaclite and gem have the same issue with registering
multiple instances with mdio busses. mdio bus name has to be uniq but
drivers are setting up only one name for all.
Use mdio_register_seq() and pass dev->seq number to allow multiple
mdio instances registration.
Reported-by: Phani Kiran Kara <phanikiran.kara@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The most of ethernet drivers are using this mdio registration sequence.
strcpy(priv->bus->name, "emac");
mdio_register(priv->bus);
Where driver can be used only with one MDIO bus because only unique
name should be used.
Other drivers are using unique device name for MDIO registration to
support multiple instances.
snprintf(priv->bus->name, sizeof(bus->name), "%s", name);
With DM dev->seq is used more even in logs
(like random MAC address generation:
printf("\nWarning: %s (eth%d) using random MAC address - %pM\n",
dev->name, dev->seq, pdata->enetaddr);
)
where eth%d prefix is used.
Simplify driver code to register mdio device with dev->seq number
to simplify mdio registration and reduce code duplication across
all drivers. With DM_SEQ_ALIAS enabled dev->seq reflects alias setting.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Now that binman supports creating images with microcode, drop the code from
ifdtool.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Change x86 boards to use binman to produce the ROM. This involves adding the
image definition to the device tree and using it in the Makefile. The
existing ifdtool features are no-longer needed.
Note that the u-boot.dtsi file is common and is used for all x86 boards which
use microcode. A separate emulation-u-boot-dtsi is used for the others.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Move sunxi boards to use binman. This involves adding the image definition
to the device tree and using it in the Makefile.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
With the new device-tree rules it is possible to put device-tree changes
needed by U-Boot into their own file. As an example of this approach, move
Tegra over to use it.
Signed-off-by: Simon Glass <sjg@chromium.org>
For boards that need U-Boot-specific additions to the device tree, it is
a minor annoyance to have to add these each time the tree is synced with
upstream.
Add a means to include a file (e.g. u-boot.dtsi) automatically into the .dts
file before it is compiled.
The file uses is the first one that exists in this list:
arch/<arch>/dts/<board.dts>-u-boot.dtsi
arch/<arch>/dts/<soc>-u-boot.dtsi
arch/<arch>/dts/<cpu>-u-boot.dtsi
arch/<arch>/dts/<vendor>-u-boot.dtsi
arch/<arch>/dts/u-boot.dtsi
Signed-off-by: Simon Glass <sjg@chromium.org>
Suggested-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
It is sometimes useful to be able to reference configuration options in a
device tree source file. Add the necessary includes so that this works.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Add a standard command definition for binman so that it can be used in
makefiles.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Add support for two more from the inexhaustible supply of x86 binary blob
types.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
When building for 64-bit x86 we need an SPL binary in the ROM. Add support
for this. Also increase entry test code coverage to 100%.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Add an entry type for u-boot.img (a legacy U-Boot image) and a simple test.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
The structure of x86 ROMs is pretty complex. There are various binary blobs
to place in the image. Microcode requires special handling so that it is
available to very early code and can be used without any memory whatsoever.
Add support for the various entry types that are currently needed, along
with some tests.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Add entries to support some standard U-Boot binaries, such as u-boot.bin,
u-boot.dtb, etc. Also add some tests for these.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
This adds the basic code for binman, including command parsing, processing
of entries and generation of images.
So far no entry types are supported. These will be added in future commits
as examples of how to add new types.
See the README for documentation.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
The EVP_MD_CTX and EVP_CIPHER_CTX are made opaque since 1.1.x , so instead
of embedding them directly into struct sb_image_ctx and initializing them
using EVP_*_CTX_init(), we use pointers and allocate the crypto contexts
using EVP_*_CTX_new().
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Shuffle the macros around a little to remove the following warning
when building for i.MX28:
arch/arm/cpu/arm926ejs/mxs/spl_boot.c:44:26: warning: ‘iomux_boot’ defined but not used [-Wunused-const-variable=]
static const iomux_cfg_t iomux_boot[] = {
^~~~~~~~~~
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Stefano Babic <sbabic@denx.de>
Add driver data to each compatible string to identify the type of
the port. Since all the ports in the driver are entirely compatible
with 16550 for now, all are marked with PORT_NS16550. But, there
are ports which have specific quirks, like the JZ4780 UART, which
do not have any DT property to denote the quirks. Instead, Linux
uses the compatible string to discern such ports and enable the
necessary quirks.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Add function which allows fetching the default FCR register setting
from platform data for DM , while retaining old behavior for non-DM
by returning UART_FCRVAL.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
0c0f719ad2 accidentally changed the
endianness of the i2c read and write addresses. This was noticable when
accessing EEPROMs that use 2 byte addressing as the LSB was being sent
first.
Signed-off-by: Bradley Bolen <bradleybolen@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Some I2C bus devicetree nodes, doesn't require to have
gpio pinctrl so replace the dev_info to debug so the
print never comes on the console and for bus that uses
gpio pinctrl anyway have dev_err.
Before:
------
U-Boot> i2c dev 1
Setting bus to 1
i2c bus 1 at 0x21a4000, no gpio pinctrl state.
After:
------
U-Boot> i2c dev 1
Setting bus to 1
Cc: Simon Glass <sjg@chromium.org>
Cc: Heiko Schocher <hs@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Heiko Schocher <hs@denx.de>
Better to print the hex value for bus address instead of
decimal, for more readbility on bus addressing.
Before:
------
U-Boot> i2c dev 1
Setting bus to 1
i2c bus 1 at 35274752, no gpio pinctrl state.
After:
------
U-Boot> i2c dev 1
Setting bus to 1
i2c bus 1 at 0x21a4000, no gpio pinctrl state.
Cc: Simon Glass <sjg@chromium.org>
Cc: Heiko Schocher <hs@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Heiko Schocher <hs@denx.de>
- Remove exctra space
- Add space
- Add tab space
- Fix single line comments quotes
- Fix 'CHECK: Avoid CamelCase'
- Fix 'CHECK: Alignment should match open parenthesis'
- Fix 'WARNING: line over 80 characters'
- Re-arrage header include files
Cc: Simon Glass <sjg@chromium.org>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Move USE_ARCH_MEMCPY/MEMSET options to Kconfig.
Make it "default y" for the ARMv7 architecture and make it
depend on !ARM64 && !SPL.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Add CX9020 board based on mx53loco.
Add simplified imx53 base device tree from kernel v4.8-rc8, to reuse
serial_mxc with DTE and prepare for device tree migration of other
functions and imx53 devices.
The CX9020 differs from i.MX53 Quick Start Board by:
- use uart2 instead of uart1
- DVI-D connector instead of VGA
- no audio
- CCAT FPGA connected to emi
- enable rtc
Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com>
Add the i.MX6SLL support to OCOTP driver.
The i.MX6SLL reuses the i.MX6ULL fuse, bank 7 and bank8 have 4 words
each, and there is a hole between bank 5 and bank 6.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
The LCDIF Pixel clock mux is not glitchless, so need
to gate before changing mux.
Also change enable_lcdif_clock prototype with a new input
parameter to indicate disable or enable.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
The mux for the lcd clock is not glitchless,
so need to first gate the clock before changing the mux.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
>From RM, per_periph2_clk_sel option3 is:
"derive clock from 198MHz clock (divided 392MHz PLL2 PFD)."
So fix it.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Add i.MX6SLL cpu type.
MXC_CPU_MX6D is not a real value in chip, so change it to 0x6A.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
u-boot allows modifying a device tree after it is loaded into
memory. Add fdt_fixup hook in u-boot environment which can
facilitate such modifications.
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
liteBoard is a development board which uses liteSOM as its base.
Hardware specification:
* liteSOM (i.MX6UL, DRAM, eMMC)
* Ethernet PHY (id 0)
* USB host (usb_otg1)
* MicroSD slot (uSDHC1)
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
liteSOM is a System On Module (http://grinn-global.com/litesom/). It
can't exists on its own, but will be used as part of other boards.
Hardware specification:
* NXP i.MX6UL processor
* 256M or 512M DDR3 memory
* optional eMMC (uSDHC2)
Here we treat SOM similar to SOC, so we place it inside arch/arm/mach-*
directory and make it possible to reuse initialization code (i.e. DDR,
eMMC init) for all boards that use it.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
UDOO Neo boards has one FEC port connected to KSZ8091, add support for it.
Tested on a UDOO Neo Full with "dhcp zImage" command.
Signed-off-by: Breno Lima <breno.lima@nxp.com>
UDOO Neo boards has a PFUZE300 connected to I2C1 bus.
Tested on a UDOO Neo Full with "pmic PFUZE3000 dump" command.
Signed-off-by: Breno Lima <breno.lima@nxp.com>
Add pfuze3000 voltage configuration macro for SW1AB, SW3 and VLDO1/2 according
to tables 53, 57 and 62 on PF3000 datasheet.
Signed-off-by: Breno Lima <breno.lima@nxp.com>
It's not necessary to define the console option as we use the distro config.
Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
It's not necessary to define the mmcautodetect as it is not used anywhere.
Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Change board_string() function to static because it's being used locally.
Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
It's not necessary to define the processor in the defconfig file.
The preferred method to select the SoC is via Kconfig file.
Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
It's not necessary to support USDHC3 in U-Boot as it's being used for
the WLAN.
Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
This adds board support for the Toradex module family Colibri iMX6.
The familiy consists of a module with i.MX6 DualLite, i.MX6 Solo, both
with a version for commercial and industrial temperature range.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
This adds board support for the Toradex module family Apalis iMX6.
The familiy consists of a module with i.MX6 Dual, i.MX6 Quad with
commercial and industrial temperature range.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Add proper reg values for the two AIPS bus nodes. This avoids this
two warnings:
Node /soc/aips-bus@40000000 has a unit name, but no reg property
Node /soc/aips-bus@40080000 has a unit name, but no reg property
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Currently a divider of 6 has been used, leading to following NAND
Flash Controller (NFC) clocks:
VF61: 27.7 MHz (166.7MHz bus clock)
VF50: 22 MHz (132MHz bus clock)
The NAND Flash Memory used on VF50 allows to use clock speed of
up to 33MHz, while the Flash Memory of VF61 allows 50MHz. We can
use the same divider of 4 on both modules to configure the maximal
possible clock speeds:
VF61: 41.7 MHz
VF50: 33 MHz
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Use the same preprocessor define to enable clocks as we use to
enable the driver. Make sure that the necessary PLL's are on
(they get enabled by boot ROM by default, so this is more for
completness).
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Use device-tree fixup to communicate the MTD partitions to the
kernel. U-Boot's mtdparts environment variable will be used as
partition source for the device-tree based partition table too.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
The config block support currently uses the ft_board_setup function
to patch the device tree with config block information. However, this
does not allow to patch the device tree with board specific information.
Rename the common setup function to ft_common_board_setup and use the
call it from the board files directly.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
A most basic PSCI implementation with only one psci_version is added for
LS1043A, this can verify the generic PSCI framework, and more platform specific
implementation will be added later.
Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Newly add ARMv8 PSCI needs to be initialized, be copied or reserved in right
place, this patch does all the setup steps.
Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This patch introduces a generic ARMv8 PSCI framework, with all functions
returning a dummy ARM_PSCI_RET_NI (Not Implemented), then it is up to each
platform to implement their own functions based on this framework.
Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This patch adds secure_text, secure_data and secure_stack sections for ARMv8 to
hold PSCI text and data, and it is based on the legacy implementation of ARMv7.
ARMV8_SECURE_BASE defines the address for PSCI secure sections, ARMV8_PSCI and
ARMV8_PSCI_NR_CPUS are firstly used in this patch, so they are introduce here
in Kconfig too.
Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: York Sun <york.sun@nxp.com>
NXP/Freescale uses macro CONFIG_ARMV8_PSCI to enable their private PSCI
implementation in PPA firmware, but this macro naming too generic, so this
patch replaces it with a specic one CONFIG_FSL_PPA_ARMV8_PSCI.
And this macro CONFIG_ARMV8_PSCI will be used for a generic PSCI for ARMv8
which will be added in following patchs.
Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: York Sun <york.sun@nxp.com>
LS2080A SoC family has QBMAN ver 4.0 whereas newer
SoCs like LS2088A, LS1088A has QBMAN ver 4.1
QBMAN ver 4.0 and ver 4.1 supports dqrr size as 4 and 8 respectively.
Add support of
to check QBMAN version based on SoC SVR
update dqrr_size accordingly
update code to support larger dqrr_size
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The unit-address should be the same as the I2C address of the device.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Enable ERRATUM_A009942 workaround for B-series and T-series platforms.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This reverts commit c56ae7519f.
Once the 'Quad Enable' bit is cleared in their Enhanced Volatile
Configuration Register (EVCR), Micron memories expect ALL commands to use
the SPI 4-4-4 protocol. Commands using SPI 1-y-z protocols are no longer
accepted.
Within the reverted commit, the write_evcr() function is implemented using
the spi_flash_write_common(), which is a shortcut for the
[ spi_flash_cmd_write_enable(), spi_flash_cmd_write(),
spi_flash_cmd_wait_ready() ] sequence.
Since the internal state of the Micron memory has been changed when the
spi_flash_cmd_write() function completes, the later call of the
spi_flash_cmd_wait_ready() function fails.
Indeed the SPI controller driver is not aware of the SPI protocol switch.
Further patches will fix the support of Micron QSPI memories.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
[Rebase on master, use JEDEC_MFR(info) in place of idcode0]
Signed-off-by: Jagan Teki <jagan@openedev.com>
As long as the memory mapped size specifeid in the DT is the same or
bigger than the device size, it will work. So do not force the sizes
to be identical.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
In spi_flash_scan, 'ret' is initialled to -1, but 'ret' is not always
used to store a return value, in that case, even when the function
succeed, an error (-1) will be returned.
Lets just return 0 if we hit the end of the function.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Move the code to read the "sram-size" property into the other code
that reads properties from the node, rather than the SF subnode.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
The Cadence QSPI controller has specified overheads for the various CS
times that are in addition to those programmed in to the Device Delay
register. The overheads are different for the delays.
In addition, the existing code does not handle the case when the delay
is less than a SCLK period.
This change accurately calculates the additional delays in Ref clocks.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Instead of extracting mode settings and passing them as separate
args to another function, just pass the SPI mode as an arg.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
A lot of the #defines are for single bits in a register, where the
name has _MASK on the end. Since this can be used for both a mask
and the value, remove _MASK from them.
Whilst doing so, also remove the unnecessary brackets around the
constants.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Most of the code already uses #defines for the bit value, rather
than the shift required to get the value. This changes the remaining
code over.
Whislt at it, fix the names of the "Rd Data Capture" register defs.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
With the existing code, when the requested SPI clock rate is near
to the lowest that can be achieved by the hardware (max divider
of the ref clock is 32), the generated clock rate is wrong.
For example, with a 50MHz ref clock, when asked for anything less
than a 1.5MHz SPI clock, the code sets up the divider to generate
25MHz.
This change fixes the calculation.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
At present an invalid bus width prints a message but does not return an
error. This is the opposite of the correct behaviour. Adjust it to avoid
code bloat in the common case, and avoid hard-to-debug failure in the
uncommon case.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Unlike Linux kernel, U-Boot depends on "spi-flash" compatible to probe
m25p80 spi-nor devices. Hence, add "spi-flash" compatible string to
m25p80 node. Without this patch, flash device DT data is not parsed and
QSPI operates in unsupported mode leading to data corruption.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Since I leave Samsung by the end of the year, I will not have access to
OneNAND devices anymore.
Hence the custodian position has been marked as "Orphaned".
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Add missing L3 cache flush functionality which absence prevents
Linux kernel from normal boot in case the L3 cache is enabled
by ATF.
The L3 cache is named the "last level" cache in order to keep
the terminology similar to the ATF code.
This cache should not be disabled by u-boot since the Linux
kernel cannot activate it, so it is activates at ATF stage.
However the cache flush is required for preventing data corruption
after disabling the MMU and the data cache before passing control
to the loaded Linux image.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Align the Armada-8040-db and Armada-7040-db SPI and I2C
DTS settings with latest DB settings:
- 8040-db: disable i2c0 and spi0 on AP (MPPs are reserved for SDIO)
- 8040-db: disable cps_i2c0 on CP1
- 8040-db: enable spi1 on CP1 (the new location of the boot flash)
The spi1 on CP1 is aliased as spi0 since this is the way
the driver enumerates it.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This is a user configurable option, but "select BLK" forces users to
enable it.
Even with this commit, BLK is still enabled by "default y if DM_MMC"
for UniPhier SoCs; the difference is users can disable it if they
do not need it.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Initialize EMIF OCP_CONFIG registers REG_COS_COUNT_1, REG_COS_COUNT_2,
and REG_PR_OLD_COUNT field for Beaglebone-Black and am335x-evm. With
the default values LCDC suffers from DMA FIFO underflows and frame
synchronization lost errors. The initialization values are the highest
that work flawlessly when heavy memory load is generated by CPU. 32bpp
colors were used in the test. On BBB the video mode used 110MHz pixel
clock. The mode supported by the panel of am335x-evm uses 30MHz pixel
clock.
Signed-off-by: Jyri Sarha <jsarha@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Do not overwrite the memory nodes in the kernel DT where some parts
of the memory region might be carved out.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
First, there are a number of features in newer QEMU that will allow us
to test a wider range of platforms, so we want to use at least v2.8.0.
Second, making use of a PPA for QEMU fails from time to time. So we
change to checking out and building a copy of QEMU when we know that we
are going to use test.py and need QEMU to be installed. This adds
around 4 minutes per test.py job that we run.
Signed-off-by: Tom Rini <trini@konsulko.com>
The patch is fixing:
"tools: mkimage: Check if file is regular file"
(sha1: 56c7e80155)
which contains two issues reported by Coverity
Unchecked return value from stat and incorrect calling sequence where
attack can happen between calling stat and fopen.
Using pair in opposite order (fopen and fstat) is fixing this issue
because fstat is using the same file descriptor (FILE *).
Also fixing issue with:
"tools: mkimage: Add support for initialization table for Zynq and
ZynqMP" (sha1: 3b6460809c)
where file wasn't checked that it is regular file.
Reported-by: Coverity (CID: 154711, 154712)
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Currently we let U-Boot find a spot at the end of DRAM at runtime, this
forces us to build an OPTEE image based on the size of DRAM for an EVM.
Add a default address that works across all current AM57xx EVMs.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Currently we let U-Boot find a spot at the end of DRAM at runtime, this
forces us to build an OPTEE image based on the size of DRAM for an EVM.
Add a default address that works across all current DRA7xx EVMs.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
The configuration used to error correction was not in line with what
linux and the ROM code is using. Fix it by using the correct
configuration. Now u-boot and the SPL are able to read correctly
anything written by them.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
A size of 0x200 seems way too short for u-boot. Increase the size
to 512k.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Currently the PCI command only allows to see the BAR register
values but not the size and actual base address.
This little extension parses the BAR registers and displays
the base, size and type of each BAR.
Signed-off-by: Yehuda Yitschak <yehuday@marvell.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Create a boot_from_devices() function to handle trying each device. This
helps to reduce the size of the already-large board_init_r() function.
Signed-off-by: Simon Glass <sjg@chromium.org>
It is useful to name each method so that we can print out this name when
using the method. Currently this happens using a separate function. In
preparation for unifying this, add a name to each method.
The name is only available if we have libcommon support (i.e can use
printf()).
Signed-off-by: Simon Glass <sjg@chromium.org>
The GPIO7 pad mux should be programmed to POWERHOLD value
as per board design. In cases where the PMIC is shut off the
mux is set to GPIO7 mode. So during initialization to be on the
safer side set the mode to POWERHOLD.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Enable Linear Physical Address Extension mode which is a
prerequisite for hypervisor mode.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
solve issue when bootstage is used with armV7 generic timer
first call of timer_get_boot_us() use the function get_timer()
before timer initialization (arch.timer_rate_hz = 0)
=> div by 0
Commit-notes
When I activate bootstage on ARMV7 architecture with platform
using the generic armv7 timer defined in file
./arch/arm/cpu/armv7m/timer.c
I have a issue because gd->arch.timer_rate_hz = 0
For me the get_timer() function should not used before timer_init
(which initialize gd->arch.timer_rate_hz) at least for the ARMV7
timer.
But in the init sequence, the first bootstage fucntion is called
before timer_init and this function use the timer function.
For me it is a error in the generic init sequence :
mark_bootstage is called before timer_init.
static init_fnc_t init_sequence_f[] = {
....
arch_cpu_init_dm,
mark_bootstage, /* need timer, go after init dm */
...
#if defined(CONFIG_ARM) || defined(CONFIG_MIPS) || \
defined(CONFIG_BLACKFIN) || defined(CONFIG_NDS32) || \
defined(CONFIG_SPARC)
timer_init, /* initialize timer */
#endif
.......
To solve the issue for all the paltform, we can move timer_init()
call just before mark_bootstage() in this array...
It should be ok for ARMV7 but I don't sure for other platform
impacted
- the other ARM platform or ARMV7 wich don't use generic timer
- MIPS BLACKFIN NDS32 or SPARC
and I don't sure of impact for other function called
(board_early_init_f for example....)
=> This patch solve issue only in timer armv7
get_boot_us() can be called everytime without div by 0 issue
(gd->arch.timer_rate_hz is not used)
END
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay73@gmail.com>
The VSC8601 config tried to add an RGMII skew based on #defines that
no config defines. That's quite an ugly way to do it. Since the skew
is only needed on RGMII interfaces, check the interface mode at
runtime, and apply the settings accordingly.
Tested on custom board with AM3352 SOC and VSC801 PHY.
Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Testing on theadorable (Armada XP) has shown, that using this driver
results in many cache misaligned warning, such as:
CACHE: Misaligned operation at range [7fabd8fc, 7fabd900]
This patch now uses the ALLOC_CACHE_ALIGN_BUFFER() macro to allocate the
buffers on a cache aligned boundary. This fixes all warnings seen on the
Armada XP platform.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Ted Chen <tedchen@realtek.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The settings for 2.5G SGMII are wrong, which the 2.5G case is missed in
set_if_mode(), and the serdes PCS configuration are wrong, this patch uses
the correct settings took from Linux.
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Commit 525d187af ("net: phy: Optionally force master mode for RTL PHY")
added the define to force the PHY into master mode. Unfortunatly this is
an all or nothing switch. So it applies to either all PHY's or no PHY's.
The bug that define tried to solve was a buggy PLL in the RTL8211C only.
The Olimex OLinuXino Lime2 has gotten an upgrade where the PHY was
replaced with an RTL8211E. With this define however, both lime2 boards
are either forced to master mode or not. We could of course have a
binary for each board, but the following patch fixes this by adding a
'quirk' to the flags to the rtl8211b and rtl8211c only. It is now
possible to force master mode, but only have it apply to the rtl8211b
and rtl8211c.
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
All internal defines in the realtek phy are with a small X,
except MIIM_RTL8211X_CTRL1000T_MASTER. Make this more consistent
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The BIT macro is the preferred method to set bits.
This patch adds the bit macro and converts bit invocations.
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Fix the following error, the $ret variable handling must
be part of the loop, while due to the missing parenthesis
it was not.
drivers/net/phy/micrel.c: In function ‘ksz9021_of_config’:
drivers/net/phy/micrel.c:303:2: warning: this ‘for’ clause does not guard... [-Wmisleading-indentation]
for (i = 0; i < ARRAY_SIZE(ofcfg); i++)
^~~
drivers/net/phy/micrel.c:305:3: note: ...this statement, but the latter is misleadingly indented as if it is guarded by the ‘for’
if (ret)
^~
drivers/net/phy/micrel.c: In function ‘ksz9031_of_config’:
drivers/net/phy/micrel.c:411:2: warning: this ‘for’ clause does not guard... [-Wmisleading-indentation]
for (i = 0; i < ARRAY_SIZE(ofcfg); i++)
^~~
drivers/net/phy/micrel.c:413:3: note: ...this statement, but the latter is misleadingly indented as if it is guarded by the ‘for’
if (ret)
^~
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
axi_emac, emaclite and gem have the same issue with registering
multiple instances with mdio busses. mdio bus name has to be uniq but
drivers are setting up only one name for all.
Use mdio_register_seq() and pass dev->seq number to allow multiple
mdio instances registration.
Reported-by: Phani Kiran Kara <phanikiran.kara@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Series-to: u-boot
Series-cc: Phani Kiran Kara <phanikiran.kara@gmail.com>
The most of ethernet drivers are using this mdio registration sequence.
strcpy(priv->bus->name, "emac");
mdio_register(priv->bus);
Where driver can be used only with one MDIO bus because only unique
name should be used.
Other drivers are using unique device name for MDIO registration to
support multiple instances.
snprintf(priv->bus->name, sizeof(bus->name), "%s", name);
With DM dev->seq is used more even in logs
(like random MAC address generation:
printf("\nWarning: %s (eth%d) using random MAC address - %pM\n",
dev->name, dev->seq, pdata->enetaddr);
)
where eth%d prefix is used.
Simplify driver code to register mdio device with dev->seq number
to simplify mdio registration and reduce code duplication across
all drivers. With DM_SEQ_ALIAS enabled dev->seq reflects alias setting.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
For example:
Board: Xilinx Zynq
Net: ZYNQ GEM: e000b000, phyaddr 7, interface rgmii-id
Warning: ethernet@e000b000 (eth0) using random MAC address -
7a:fc:90:53:6a:41
eth0: ethernet@e000b000ZYNQ GEM: e000c000, phyaddr ffffffff, interface
rgmii-id
Warning: ethernet@e000c000 (eth3) using random MAC address -
1a:ff:d7:1a:a1:b2
, eth3: ethernet@e000c000
** Bad device size - mmc 0 **
Checking if uenvcmd is set ...
Hit any key to stop autoboot: 0
Zynq> mdio list
eth0:
17 - Marvell 88E1111S <--> ethernet@e000b000
eth3:
17 - Marvell 88E1111S <--> ethernet@e000c000
Zynq>
The dram_init* functions for the zynq board are not safe for use from
the board_init_f stage due to its use of the 'tmp' static variable.
This incorrect use of a static variable was causing rare issues where
the dram_init function would overwrite some parts the __rel_dyn section
which caused obscure failures.
Using the zynq_zybo configuration, U-Boot would generate the following
error during image load. This was caused due to dram_init overwriting
the relocations for the "image" variable within the do_bootm function.
Out of coincidence the un-initialized memory has a compression type
which is the same as the value for the relocation type R_ARM_RELATIVE.
Uncompressing Invalid Image ... Unimplemented compression type 23
It should be noted that this is just one way the issue could surface,
other cases my not be observed in normal boot flow.
This change removes the existing code and copies the implementation of
the dram_init and dram_init_banksize from the
arch/arm/mach-uniphier/dram_init.c source. This version of these
functions does not use static variables and behaves the same (reading
banks from fdt, and using the first bank as the ram_size).
Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
Fixes: 758f29d0f8 ("ARM: zynq: Support systems with more memory banks")
Cc: Michal Simek <monstr@monstr.eu>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The patch is fixing:
"tools: mkimage: Check if file is regular file"
(sha1: 56c7e80155)
which contains two issues reported by Coverity
Unchecked return value from stat and incorrect calling sequence where
attack can happen between calling stat and fopen.
Using pair in opposite order (fopen and fstat) is fixing this issue
because fstat is using the same file descriptor (FILE *).
Also fixing issue with:
"tools: mkimage: Add support for initialization table for Zynq and
ZynqMP" (sha1: 3b6460809c)
where file wasn't checked that it is regular file.
Reported-by: Coverity (CID: 154711, 154712)
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Series-to: trini
Series-cc: u-boot
All sata based drivers are bind and corresponding block
device is created. Based on this find_scsi_device() is able
to get back block device based on scsi_curr_dev pointer.
intr_scsi() is commented now but it can be replaced by calling
find_scsi_device() and scsi_scan().
scsi_dev_desc[] is commented out but common/scsi.c heavily depends on
it. That's why CONFIG_SYS_SCSI_MAX_DEVICE is hardcoded to 1 and symbol
is reassigned to a block description allocated by uclass.
There is only one block description by device now but it doesn't need to
be correct when more devices are present.
scsi_bind() ensures corresponding block device creation.
uclass post_probe (scsi_post_probe()) is doing low level init.
SCSI/SATA DM based drivers requires to have 64bit base address as
the first entry in platform data structure to setup mmio_base.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Series-changes: 2
- Use CONFIG_DM_SCSI instead of mix of DM_SCSI and DM_SATA
Ceva sata has never used sata commands that's why keep it in
SCSI part only.
- Separate scsi_scan() for DM_SCSI and do not change cmd/scsi.c
- Extend platdata
Series-changes: 3
- Fix scsi_scan return path
- Fix header location uclass-internal.h
- Add scsi_max_devs under !DM_SCSI
- Add new header device-internal because of device_probe()
- Redesign block device creation algorithm
- Use device_unbind in error path
- Create block device with id and lun numbers (lun was there in v2)
- Cleanup dev_num initialization in block device description
with fixing parameters in blk_create_devicef
- Create new Kconfig menu for SATA/SCSI drivers
- Extend description for DM_SCSI
- Fix Kconfig dependencies
- Fix kernel doc format in scsi_platdata
- Fix ahci_init_one - vendor variable
Series-changes: 4
- Fix Kconfig entry
- Remove SPL ifdef around SCSI uclass
- Clean ahci_print_info() ifdef logic
This patch adds DM support to the xHCI PCI driver. Enabling its use
e.g. in x86 platforms.
Status: On the congatec BayTrail SoM, xHCI still does not work
correctly with this patch. Some internal timeouts lead to resets (BUG).
Additional work is needed here. I'm posting this version as WIP so that
other developers interested in this support might use it as a start.
I might get back to it in a few weeks as well.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: George McCollister <george.mccollister@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Replace arch/arm/cpu/armv7/socfpga/ path with
arch/arm/mach-socfpga/ and removed board file path
since board/altera has different boards with relevant
board maintainers.
Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Jagan Teki <jagan@openedev.com>
With the acquisition of Altera by Intel, my Altera email may be going
away soon. Update the contact to a more reliable address.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Some Altera Quartus generated files have long lines that are split with a '\' at
the end of the line. It also wOn Windows, rites files in DOS format, which can
confuse some of the processing scripts in this file. This patch solves both issues.
Signed-off-by: Bill Randle <bill.randle@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Valid Altera SoCFPGA preloader image must contain special data at
offsets 0x40, 0x44, 0x48 and valid instructions at address 0x4c or
0x50. These addresses are by default used by U-Boot's vector table
and a piece of reset handler, thus a valid preloader corrupts those
addresses slightly. While this works most of the time, this can and
does prevent the board from rebooting sometimes and triggering this
issue may even depend on compiler.
The problem is that when SoCFPGA performs warm reset, it checks the
addresses 0x40..0x4b in SRAM for a valid preloader signature and
header checksum. If those are found, it jumps to address 0x4c or
0x50 (this is unclear). These addresses are populated by the first
few instructions of arch/arm/cpu/armv7/start.S:
ffff0040 <data_abort>:
ffff0040: ebfffffe bl ffff0040 <data_abort>
ffff0044 <reset>:
ffff0044: ea000012 b ffff0094 <save_boot_params>
ffff0048 <save_boot_params_ret>:
ffff0048: e10f0000 mrs r0, CPSR
ffff004c: e200101f and r1, r0, #31
ffff0050: e331001a teq r1, #26
Without this patch, the CPU will enter the code at 0xffff004c or
0xffff0050 , at which point the value of r0 and r1 registers is
undefined. Moreover, jumping directly to the preloader entry point
at address 0xffff0000 will also fail, because address 0xffff004.
is invalid and contains the preloader magic.
Add BOOT0 hook which reserves the area at offset 0x40..0x5f and
populates offset 0x50 with jump to the entry point. This way, the
preloader signature is stored in reserved space and can not corrupt
the SPL code.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Stefan Roese <sr@denx.de>
Tested-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Add CycloneV based Terasic DE1-SoC board. The board boots
from SD/MMC. Ethernet and USB host is supported.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Marek Vasut <marex@denx.de>
The default configuration for QSPI AHB bus can't support 16MB+.
But some flash on NXP layerscape board are more than 16MB.
Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Add the name for register space and memory space.
<0x1550000 0x10000 > is the QSPI register space.
<0x40000000 0x4000000> is the QSPI memory space.
Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
- add additional function erratum_a009942_check_cpo to check if the
board needs tuning CPO calibration for optimal setting.
- move ERRATUM_A009942(with revision to check cpo_sample option) from
fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts.
- move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c
- remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
[YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500]
Reviewed-by: York Sun <york.sun@nxp.com>
Fix following warning in case multiple erratum macro was not defined.
warning: unused variable 'tmp'
warning: unused variable 'ddr_freq'
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Its easier to watch the output of the build process when the platforms
specific boards are grouped in a separate job. This patch adds a job
for all mvebu boards (arm and aarch64).
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
The LCDC controller on the lcdk board has high memory throughput
requirements. Even with the kernel-side tweaks to master peripheral
and peripheral bus burst priorities, the default PLL0 frquency of
300 MHz is not enough to service the LCD controller and causes
DMA FIFO underflows.
Increment the PLL0 multiplier to 37, resulting in PLL0 frequency of
456 MHz - the same value that downstream reference u-boot from Texas
Instruments uses.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
First of all U-Boot would search for a USB mass storage device
with either uEnv.txt or kernel-fit.itb and boot.
If USB mass storage device is not available or doesn't provide
these files then MMC will be tried.
Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Baltos devices provide a mPCIe slot, whose power is turned off by
default. This patch activates mPCIe slot in U-Boot, so that for example
GSM modem can be already available in user space.
Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
The bootrom may corrupt the area of SRAM used to store the ti_common_eeprom
structure. This patch makes sure that it's always read after a reset, even
if a valid MAGIC number is found in the SRAM.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
The patch
"dm: spl: mmc: Support CONFIG_BLK in SPL MMC"
(sha1: 87bce4e5c0)
converted FAT part of spl_mmc_do_fs_boot() but forget to update also EXT
part by 's/&mmc->block_dev/mmc_get_blk_desc(mmc)/'.
This patch is fixing compilation error when CONFIG_SPL_EXT_SUPPORT
is enabled.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This patch fixes the warnings about misaligned cache on Armada XP:
CACHE: Misaligned operation at range [7facb400, 7facb460]
Signed-off-by: Stefan Roese <sr@denx.de>
Not all memory is mapped in the MMU. So we need to restrict the memory
size so that U-Boot does not try to access it. Also, the internal
registers are located at 0xf000.0000 - 0xffff.ffff. Currently only 2GiB
are mapped for system memory. This is what we pass to the U-Boot
subsystem here.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
This patch adds PCI support to the Marvell Armada-8K devel board.
Additionally the Intel E1000 ethernet driver is enabled so that
network support is available on this board, even without the
internal network interfaces being supported (yet).
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
This patch adds a driver for the PCIe controller integrated in the
Marvell Armada-8K SoC. This controller is based on the DesignWare
IP core.
The original version was written by Shadi and Yehuda. I ported this
driver to the latest mainline U-Boot version with DM support.
Tested on the Marvell DB-88F8040 Armada-8K eval board.
Signed-off-by: Shadi Ammouri <shadi@marvell.com>
Signed-off-by: Yehuda Yitschak <yehuday@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
This patch adds the necessary files to support the Marvell Armada 8k
devel board. Most board specfic files are shared with the Armada 7k
boards under the name "armada-8k*". So only minimal changes are
necessary to add this basic board support (except the DT files of
course).
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
This patch uses of_machine_is_compatible() to detect the board at runtime
and only configured the I2C IO expander for the xHCI power / reset on
the DB-88F7040 board. As this code will be used by other Armada-7k/8k
ports, its necessary to use this runtime detection here.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
This moves some of the Armada DB-88F7040 board specific files to a more
generic name: armada-8k. This is in preparation for the Armada-8k
support which will be added soon. And since both platforms share
most devices, lets also share most source files to not duplicate
the code here.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
Add a README with a brief guide to porting i2c drivers over to use driver
model.
Add a timeline also. All I2C drivers should be converted by the end
of June 2017.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Maintainers need to be notified more directly of the need to convert these
drivers. Add a note to the top each affected file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Now that driver model is used for I2C on all boards, we can split the
high-speed code into its own driver. There is virtually no common code,
and this significantly reduces confusion.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
These are the last two samsung boards that don't use DM_I2C. Move them
over, leaving #ifdefs to allow the maintainer to complete this work.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Three boards are still not converting to use DM_I2C. They are also using
the old PMIC framework. Rather than removing them, add #ifdefs to allow
them to continue to build. This will give the maintainers a little more
time to decide whether to convert them or not.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Commit 54e4fcfa3c ("ARM: mx6: add MMC2 boot device detection
support in SPL") prevents UDOO neo board to boot:
Trying to boot from MMC2
port 1
MMC Device 1 not found
spl: could not find mmc device. error: -19
SPL: failed to boot from all boot devices
This reverts commit 54e4fcfa3c.
Signed-off-by: Breno Lima <breno.lima@nxp.com>
Commit 4c4e3b37750f3("ARM: AM43xx: Enable FIT") accidentally disabled
DM_SPI and DM_SPI_FLASH. Add back DM_SPI and DM_SPI_FLASH to
am43xx_evm_defconfig in order to make use of DM framework for QSPI.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
After an image is selected out of a FIT blob for further processing we
run an optional, platform specific, post-processing function on this
component. This post-processing may modify the position and size of the
image, so after post-processing we update the location and size for this
image in the FIT header. This can cause problems as the position of
subsequent components in the FIT blob are only referenced by relative
position to the end of the last component. When we resize or move a
component the following components position will be calculated
incorrectly. To fix this, we do not update the FIT header but instead
only update our local understanding of the image data. This also allows
us to re-run post-processing steps if needed.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Tested-by: Carlos Hernandez <ceh@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
The shortname variable isn't referenced anywhere in the code, so just
remove it.
Pointed out by a GCC 6.2 default warning option.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Apparently the indentation is wrong in this case, as the second message
should be printed indepdently of the if statement.
Fix this indentation to avoid both compiler warnings and puzzled readers.
Pointed out by GCC 6.2's -Wmisleading-indentation warning.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Apparently the indentation is wrong here, fix this to avoid compiler
warnings and puzzled readers.
Pointed out by GCC 6.2's -Wmisleading-indentation warning.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Obviously the mask for the rx and tx select field cannot be right,
as it would overlap in one and exceed the 32-bit register in the other
case. From looking at the neighbouring bits it looks like the mask
should be really 4 bits wide instead of 8.
Pointed out by a GCC 6.2 (default) warning.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
The rtl8169_intr_mask variable isn't used anywhere in the code, so
just remove it to avoid a GCC 6.2 compiler warning.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Apparently the indentation is off here, for the IGB model just want to
bail out early.
Fix this to avoid both compiler warnings and puzzled readers.
Pointed out by GCC 6.2's -Wmisleading-indentation warning.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The indentation is misleading here and suggests that the write command
will be only executed in the else clause.
It seems like this is not intended, so fix the indentation to avoid
both compiler warnings and puzzled readers.
Pointed out by GCC 6.2's -Wmisleading-indentation warning.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Stefan Roese <sr@denx.de>
This board has not been converted to DM_SERIAL by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: David Müller <d.mueller@elsoft.ch>
There are certain environment variables whose length is greater than
the defined IO buffer size. So, increase the IO buffer size to print the
entire variables.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
The AM571x Industrial Development Kit (IDK) is a board based on TI's
AM571x SoC which has a single core 1.5GHz Cortex-A15processor. This
board is a development platform for the Industrial Market with:
- 1GB of DDR3L
- Dual 1Gbps Ethernet
- HDMI
- PRU-ICSS
- uSD
- 16GB eMMC
- CAN
- RS-485
- PCIe
- USB3.0
- Video Input Port
- Industrial IO port and expansion connector
The PRU/ICSS will be supported by 3rd party software for EtherCat,
Profibus, and other Industrial protocols.
The link to the data sheet and TRM can be found here:
http://www.ti.com/product/AM5718
Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Update the timing for RGMII0 interface based on
PCT_DRA75x_DRA74x_SR1.1_v1.3.10 version (Jan 2016). This update
is for SR1.1
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
BeagleBoard-X15 Rev B1 with SR1.1 platform have incompatible changes for HDMI
GPIO requiring new dtb support. This implies we have to properly identify
the platform now as well. Hence provide a different board name for the
Rev B1 variants.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
AM57xx evm Rev A3 with SR2.0 platform have incompatible changes for HDMI
GPIO requiring new dtb support. This implies we have to properly identify
the platform now as well. Hence provide a different board name for the
Rev A3 variations.
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Add DT support for dra71-evm and built it as part of FIT image.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Palmas driver assumes it is always TPS659xx regulator on all DRA7xx based
boards to enable mmc regulator. This is not true always like in case of
DRA71x-evm. So get this information based on the board.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
[trini: Delete omap4_vmmc_pbias_config from omap_hsmmc.c]
Signed-off-by: Tom Rini <trini@konsulko.com>
Add the pmic_data for LP873x PMIC which is used to power
up dra71x-evm.
Note: As per the DM[1] DRA71x supports only OP_NOM. So, updating
the efuse registers only to use OPP_NOM irrespective of any
CONFIG_DRA7_<VOLT>_OPP_{NOM,od,high} is defined.
[1] http://www.ti.com/product/DRA718/technicaldocuments
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Rev C version of EVM does require IODelay to be configured for RGMII
pins in MANUAL_1 configuration. Update the same based on PG2.0 initial
simulation values.
Data based on PCT_DRA72x_SR2.0_SR1.0_v1.3.0.7
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Add mux and iodelay settings for dra71x-evm.
Data generated using PCT_DRA71x_SR2.0_v1.0.0.0 version (June 2016).
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
The dra71x-evm is a board based on TI's DRA718 processor targeting BOM-optimized
entry infotainment systems such as display audio and is a software compatible
derivative of the highly successful DRA74 and DRA72 processor families.
More information can be found here[1].
Add epprom detection for dra71-evm.
[1] http://www.ti.com/product/dra718
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
This patch adds support to update the device-tree blob to adjust the
DSP and IVA DPLL clocks pertinent to the selected OPP choice, with
the default being OPP_NOM. The voltage settings are done in u-boot,
but the actual clock configuration itself is done in kernel because
of the following reasons:
1. SoC definition constraints us to NOT to do dynamic voltage
scaling ever after the initial avs0 setting in bootloader
- so the voltage must be set in bootloader.
2. The voltage level must be set even if the IP blocks like
GPU/DSP are unused.
3. The IVA, GPU and DSP DPLLs are not essential for u-boot functionality,
and similar DPLL clock configuration code has been cleaned up in
v2014.10 u-boot release. See commit, 02c41535b6 ("ARM: OMAP4/5:
Remove dead code against CONFIG_SYS_CLOCKS_ENABLE_ALL").
The non-essential DPLLs are configured within the kernel during
the clock init step when parsing the device tree and creating
the clock devices. This approach meets both the u-boot and kernel
needs.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Subhajit Paul <subhajit_paul@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Redefine the macros used to define the voltage values and the
efuse register offsets based on OPP for all the voltage domains.
This is done using Kconfig macros that can be set in a defconfig
or selected during a config step. This allows a voltage domain
to be configured/set to a corresponding voltage value depending
on the OPP selection choice.
The Kconfig choices have been added for MPU, DSPEVE, IVA and GPU
voltage domains, with the MPU domain restricted to OPP_NOM. The
OPP_OD and OPP_HIGH options will be added when the support for
configuring the MPU clock frequency is added. The clock
configuration for other voltage domains is out of scope in
u-boot code.
The CORE voltage domain does not have separate voltage values
and efuse register offset at different OPPs, while the MPU
voltage domain only has different efuse register offsets for
different OPPs, but uses the same voltage value. Any different
choices of OPPs for voltage domains on common ganged-rails
is automatically taken care to select the corresponding
highest OPP voltage value.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
It can be expected that different paper spins of a SoC can have
different definitions for OPP and can have their own constraints
on the boot up OPP for each voltage rail. In order to have this
flexibility, add support for dynamically selecting the OPP voltage
based on the board to handle any such exceptions.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Currently, CMD_PXE is forcibly enabled in config_distro_defaults.h, so
that general purpose distributions can rely on it being defined. This
header is included, under conditions or not, by various archs or
famillies of archs / SoCs.
However, it is very possible that boards based on those SoCs will not
have a physical ethernet connector at all, even if the have a MAC; for
example, the Nanopi Neo AIR (sunxi H3) does not. It is also possible
that network booting is absolutely not necessary for a device.
However, it is not possible to disable the PXE command, as it is
forcibly enabled and is non-configurable.
But it turns out we already have a config option to build a distro-ready
image, in the name of DISTRO_DEFAULTS.
Move CMD_PXE out of the hard-coded config_distro_defaults.h into a
Kconfig option, that gets selected by DISTRO_DEFAULTS when it is set.
Signed-off-by: "Yann E. MORIN" <yann.morin.1998@free.fr>
Cc: Joe Hershberger <joe.hershberger@ni.com>
[trini: Make it select MENU, run moveconfig.py]
Signed-off-by: Tom Rini <trini@konsulko.com>
A number of platforms had been using the distro default feature before
it was moved to Kconfig but did not enable the new Kconfig option when
it was enabled. This caused a regression in terms of features and this
introduces breakage when more things move to Kconfig.
Signed-off-by: Tom Rini <trini@konsulko.com>
Populate the corresponding TEE image processing call to be
performed during FIT loadable processing.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Populate the corresponding TEE image processing call to be
performed during FIT loadable processing.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Add an OPTEE node to the FDT when TEE installation has completed
successfully. This informs the kernel of the presence of OPTEE.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
secure_tee_install is used to install and initialize a secure TEE OS such as
Linaro OP-TEE into the secure world. This function takes in the address
where the signed TEE image is loaded as an argument. The signed TEE image
consists of a header (struct tee_header), TEE code+data followed by the
signature generated using image signing tool from TI security development
package (SECDEV). Refer to README.ti-secure for more information.
This function uses 2 new secure APIs.
1. PPA_SERV_HAL_TEE_LOAD_MASTER - Must be called on CPU Core 0. Protected
memory for TEE must be reserved before calling this function. This API
needs arguments filled into struct ppa_tee_load_info. The TEE image is
authenticated and if there are no errors, the control passes to the TEE
entry point.
2. PPA_SERV_HAL_TEE_LOAD_SLAVE - Called on other CPU cores only after
a TEE_LOAD_MASTER call. Takes no arguments. Checks if TEE was
successfully loaded (on core 0) and transfers control to the same TEE
entry point.
The code at TEE entry point is expected perform OS initialization steps
and return back to non-secure world (U-Boot).
Signed-off-by: Harinarayan Bhatta <harinarayan@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
On DRA7xx platform, CPU Core 1 is not used in u-boot. However, in some
cases it is need to make secure API calls from Core 1. This patch adds
an assembly function to make a secure (SMC) call from CPU Core #1.
Signed-off-by: Harinarayan Bhatta <harinarayan@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Add a new image type representing Trusted Execution Environment (TEE)
image types. For example, an OP-TEE OS binary image.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
To help automate the loading of custom image types we add the ability
to define custom handlers for the loadable section types. When we find
a compatible type while loading a "loadable" image from a FIT image we
run its associated handlers to perform any additional steps needed for
loading this image.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
When booting from EMMC, load the DTB and pass it to the kernel.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Improve the readability of the boot command. This will help a later
commit that adds DT support.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
NAND SPL boot was missing. Add it. The README specific to omapl138-lcdk
is also removed because its content does not apply anymore, i.e. the
generated AIS image can be flashed directly to the NAND without
using any external tool to create and bootable AIS image.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
NAND_MAX_CHIPS is not used anymore and has been replaced by
CONFIG_SYS_MAX_NAND_DEVICE. There is no need to keep the former
define.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
CONFIG_SYS_ALE_MASK is not used anywhere. It has probably been
renamed to CONFIG_SYS_NAND_MASK_ALE. Rename it and remove the former
from the config_whitelist.txt file.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
CONFIG_SYS_CLE_MASK is not used anywhere. It has probably been
renamed to CONFIG_SYS_NAND_MASK_CLE. Rename it and remove the former
from the config_whitelist.txt file.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
The omapl138_lcdk header defines CONFIG_SYS_NAND_BUSWIDTH_16_BIT while
the correct name is CONFIG_SYS_NAND_BUSWIDTH_16BIT.
While renaming the only occurrence of CONFIG_SYS_NAND_BUSWIDTH_16_BIT,
let's also remove it from the config_whitelist.txt file.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
The OMAPL138-LCD board uses a NAND chip with a 16 bits bus. Add
support into the davinci driver for 16 bit bus NAND chips.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Set the correct CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR value in order
to be able to boot from MMC/SD.
The SPL is stored at sector 0x75, while u-boot will follow at
sector 0xb5.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
The list of available boot method is not part of the binary which
prevent the SPL from booting u-boot or Linux.
Add the missing .u_boot_list* sections to the binary to fix it.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
The SPL is unable to load u-boot because the DDR2 is not configured.
Configure the DDR2.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
The SPL is not able to boot properly because the PLL0 is not
configured. Configure it.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Clean config headers by moving CONFIG_SYS_DA850_DDR_INIT away to a
Kconfig file.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Clean config headers by moving CONFIG_SYS_DA850_PLL_INIT away to a
Kconfig file.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
CONFIG_AM57XX is just an unnecessary macro that is redundant given So,
remove the same instead of spreading through out the u-boot source
code and getting in the way to maintain common code for DRA7x family.
Acked-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Both AM57xx and DRA7xx share the same set of base addresses for DWC
controllers. The usage however differ with DWC2 instance used typically
in AM57xx evms while DWC1 instances used in DRA7x platforms.
Use TARGET_SOC config to differentiate so that CONFIG_AM57XX can be dropped.
Eventually, this needs to be dt-fied.
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
For ECC enabled DDR, we use EDMA to reset all memory values to 0. For
K2E/L/H/K the priv ID of 8 was indicative of ARM, but that is not the
case for K2G, where it is 1.
Unfortunately, ddr3 code had hard coded the privID and had missed
identification previously. Fix the same, else unforeseen behavior can
be expected in our reset of DDR contents to 0 for ECC enablement.
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Verification has to be done before booting any images on HS devices. So
default the boot to FIT on HS devices.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Verification has to be done before booting any images on HS devices. So
default the boot to FIT on HS devices.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Verification has to be done before booting any images on HS devices. So
default the boot to FIT on HS devices.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
FIT is a new image format which is a Tree like structure and gives more
flexibility in handling of various images. Mainly used for unification of
multiple images in a single blob and provide security information for each
image.
U-Boot already has support for loading such images, so adding the environment
support to load FIT image on all TI platforms.
Reviewed-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Support for loading images from mmc is duplicated in all TI platforms.
Add this information to DEFAULT_MMC_TI_ARGS so that it can be reused
in all TI platforms.
Reviewed-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
An issue in the TI secure image generation tool causes the ROM to
load the SPL at a different load address than what is specified by
CONFIG_ISW_ENTRY_ADDR while doing a peripheral boot.
This causes the SPL to fail on secure devices during peripheral
boot.
The TI secure image generation tool has been fixed so that the SPL
will always be loaded at 0x403018E0 by the ROM code for both
peripheral and memory boot modes. am43x hs defconfig file have been
updated to reflect this change.
Signed-off-by: Madan Srinivas <madans@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Add a TI MUSB host driver with driver model support and the
driver will be bound by the MUSB wrapper driver based on the
dr_mode device tree entry.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Currently all backend driver ops uses hard coded physical
address, so to adopt the driver to DM, add device pointer to ops
call backs so that drivers can get physical addresses from the
usb driver priv/plat data.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
MUSB wrapper driver is bound as MISC device and underlying usb
devices are bind to usb drivers based on dr_mode, so probing the
MISC wrapper driver to register musb devices.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Add a misc driver for MUSB wrapper, so that based on dr_mode the
USB devices can bind to USB host or USB device drivers.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Do not register usb devices when CONFIG_DM_USB is define.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Since OMAP's spl doesn't support DM currently, do not define
CONFIG_DM_USB for spl build.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
The currently available functions accessing the 'reg' property of a
device only retrieve the address. Sometimes its also necessary to
retrieve the size described by the 'reg' property. This patch adds
the new function dev_get_addr_size_index() which retrieves both,
the address and the size described by the 'reg' property.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
Commit e2f88dfd2d ("libfdt: Introduce new ARCH_FIXUP_FDT option")
allows us to skip memory setup of DTB, but a problem for ARM is that
spin_table_update_dt() and psci_update_dt() are skipped as well if
CONFIG_ARCH_FIXUP_FDT is disabled.
This commit allows us to skip only fdt_fixup_memory_banks() instead
of the whole of arch_fixup_fdt(). It will be useful when we want to
use a memory node from a kernel DTB as is, but need some fixups for
Spin-Table/PSCI.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Alexey Brodkin <abrodkin@synopsys.com>
Acked-by: Simon Glass <sjg@chromium.org>
Fixed build error for x86:
Signed-off-by: Simon Glass <sjg@chromium.org>
The function that is processing the 'fdt' parameters is one big
if-else if. In order to be able to type command faster only the first
few letter are checked to know which block of code to execute. For
systemsetup, the block of code that was executed was always the wrong
one and ended up in a failure.
} else if (argv[1][0] == 's') {
process "fdt set" command
} else if (strncmp(argv[1], "sys", 3) == 0) {
process "fdt systemsetup" command.
}
When typing "fdt systemsetup", the code that was executed was the code
for "fdt set".
This commit fix this issue by moving the "else if" for systemsetup
before the else if for "fdt set". This allow us to keep compatibility
with any script that make use of "fdt s" to set node values.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Acked-by: Simon Glass <sjg@chromium.org>
Consolidate the net device, usb eth device and gadget device
struct to single struct and a single global variable so that the
same can be passed as priv of ethernet driver.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
network_started of struct eth_dev can be accessed using local
variable dev and no reason to access it with the global struct.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Current get_desc() implementation is not able to succesfully
finish and return pointer to block device descriptor.
Also function always return non zero value even device is found.
The patch fills block device descriptor and return 0 if device is found.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
When CONFIG_SPL_STACK_R is enabled, and spl_init() is called before
board_init_r(), spl_relocate_stack_gd() will move global_data to a new
place in memory. This affects driver model since it uses a list for the
uclasses. Unless this is updated the list will become invalid. When
looking for a non-existent uclass, such as when adding a new one, the loop
in uclass_find() may continue forever, thus causing a hang.
Add a function to correct this rather obscure bug.
Signed-off-by: Simon Glass <sjg@chromium.org>
This change allows to reserve enough space at the end of board SDRAM
to store two copies of U-Boot and malloc heap.
Due to selection of the CONFIG_SYS_TEXT_BASE the second code/data
copying is not avoided, first of all this may depend on a used
toolchain, secondly at this point some level of volatility is wanted
to do more platform changes and do not care about probably changed
calculated in runtime relocation offset.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Finally add fpic compilation option to produce relocatable code.
Note that this requires to define CONFIG_NEEDS_MANUAL_RELOC for all
board files, also relocation support still has some limitations
(e.g. a developer should care not to overwrite the executing code or
memset() with zeroes not yet relocated data on malloc init etc.),
which may be fixed while switching to PIE.
Due to short investigation the architecture code is not ready for PIE
linking, this will require some manipulations with .dyn* sections.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
It is easy to note that SH2/SH3/SH4 start.S code is practically
the same with a minor difference for SH2 where a short data header is
present. To avoid unwanted code duplication and to automatically
convert SH2 and SH3 platforms to generic board support move fixed SH4
start.S into arch/sh/lib/start.S and share it among all platforms.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Like on ARM platform keep the first code relocation from a U-boot
image storage to RAM at CONFIG_SYS_TEXT_BASE, then pass execution to a
generic board_init_f() with empty GD flags. If CONFIG_SYS_TEXT_BASE is
equal to a calculated by board_init_f() relocation address there will
be no more code and data copy, however it's worth to mention that the
first copy happens even if $pc on _start is the same as
CONFIG_SYS_TEXT_BASE, on practice this works without a problem.
Also note that _sh_start is renamed back to _start to correct
gd->mon_len calculation by setup_mon_len(), the opposite rename was
done in pre-generic board commit 2024b968ee ("sh: Fix build in start.S").
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Commits b61e90e6fd ("sh: Drop the arch-specific board init") and
f41e6088eb ("sh: Fix build errors for generic board") left code and
data relocation done in start.S, however further actual U-boot
configuration is not started anymore. Practically SH boards with the
code relocated into the expected position by start.S still can be
booted, so the change adds this option and provides an option how to
relocate code for board_init_r() execution.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Generic board support assumes a different method of specifying
DRAM size on board, also it can be shared among all boards, notably
only sh7763rdp board has a custom legacy dram_init(), however
the difference is only in printing some additional information,
this feature can be removed.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
All SH boards define a checkboard() function which outputs basic board
information on boot, however generic board support requires to define
CONFIG_DISPLAY_BOARDINFO to do that, so define it for the boards.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
By default this undef is a noop, moreover at this point when the
platform support is broken is prevents debugging of U-boot by manual
insertion of #define DEBUG into common files, so it makes sense to
remove the option from all SH boards as a harmful one.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
At the moment in runtime all defined sections are copied into or
created in RAM, specify this explicitly to assert potential out of RAM
placements of the sections.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
No functional change, concentrate linker script commands in one
place for convenience. Entry point is set to CONFIG_SYS_TEXT_BASE by
default on build, so this option can be omitted from being added to
the linker script.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reference lowlevel_init of all supported SH2A/SH3/SH4/SH4A boards
from a shared linker script, the lowlevel_init function will be called
by a relative address.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Three supported SH4/SH4A boards with the bootloader image stored on
SPI flash have own flavour of a linker script, in turn they are equal
among each other. The only difference is that the text from
lowlevel_init.o is placed right after start.o, which makes sense.
Note that .bss section is not marked as NOLOAD, because for about
10 years this is a default option of a GNU linker, either the
attribute is found or not the resulting image file is the same.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Since a platform conversion to generic board support has not been
accomplished some architecture specific bits are missing from board_f
init sequence, the change adds a number of basic expected callbacks
into early init sequence.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
CONFIG_RTL8139 was moved to a board defconfig by a commit 86e9dc86b1
("net: Move CONFIG_RTL8139 to Kconfig"), however it was done
incorrectly due to a missing CONFIG_NETDEVICES selection, thus
virtually it was just a removal of the driver compilation.
As an unlucky consequence the option was completely removed by a purge
commit adad96e60d ("configs: Re-sync HUSH options"), restore the
driver inclusion back.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
While both options are acceptable use P1 area physical addresses
instead of external memory space of text base and PCI system memory
for unification purposes, all other supported superh boards have the
same selection.
This allows to easily ensure that CONFIG_SYS_TEXT_BASE is located
within available DRAM.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Defined __io is no-op for the SH architecture and it can be removed
from board files without any functional change.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
For ease of use and accounting a condition that on SH4
pci_phys_to_bus() and pci_bus_to_phys() are one in one mappings due to
unimplemented __iomem() conversion, this change fixes access to SDRAM
memory by PCI devices.
This change also generalizes PCI system memory configuration, which is
taken from board specific defines rather than hardcoded in the PCI
host driver.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
The change actually maps PCI I/O window to the same address on PCI bus
as it is stated by a comment, before the change transfers to the PCI I/O
space are failed due to misconfiguration of the most significant 14 bits
of the PCI address in PCIIOBR (note that it is set to 0x0).
Most probably the problem remained unnoticed, because communcation
to all tested PCI devices is done over PCI memory space only.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
No functional change, moving cache manipulation functions into cache.c
allows to collect all of them in a single location and as a pleasant
side effect cache_control() function can be unexported now.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
cache_wback_all() is a local function and it is called from
cache_control() only, which is in turn jumps to P2 area.
The change fixes an issue when cache_wback_all() returns from P2 to
P1, however cache_control() continues to manipulate with CCR
register, according to the User's Manual this is restricted.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Both jump_to_P2() and back_to_P1() functions are found in asm/system.h
header file and functionally they are the same, don't redefine them.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The change is similar to commit 994b56616b ("sh: delete an unused
source file") for SH2, however here the removed cache.c file was
built and included into an image as a dead code.
If it is needed in future the contents can be reused from a similar
arch/sh/cpu/sh4/cache.c file, which is in turn will be moved to
a shared among all core flavours location at arch/sh/lib/cache.c.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
In common usecases flush_cache() assumes both cache invalidation and
write-back to memory, instead of doing cache invalidation only with
the wrapped 'ocbi' instruction pin flush_cache() to cache invalidation
with memory write-back done by 'ocbp'.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
In common usecases flush_cache() assumes both cache invalidation and
write-back to memory, thus in flush_dcache_range() implementation
change SH4 cache write-back only instruction 'ocbwb' with cache purge
instruction 'ocbp', according to the User's Manual there should be no
performance penalty for that.
Note that under circumstances only cache invalidation is expected from
flush_cache() call, in these occasional cases the current version of
flush_cache() works, which is a wrapper over invalidate_dcache_range()
at the moment, this will be fixed in the following change.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
When building u-boot on sparc64 and powerpc hosts it became clear that
u-boot expects endian conversion defines to be macros:
lib/crc32.c:87: error: braced-group within expression allowed only inside a function
For OpenBSD switch from using system definitions equivalent to the u-boot ones
and define glibc __BYTE_ORDER __BIG_ENDIAN __LITTLE_ENDIAN names, as at least
some parts of the non-cross build assumes those names are present (ie crc32.c).
Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
AM57xx GP EVM has USB2 port of the SoC exposed as
USB client port.
It is useful to be able to use this port for USB
DFU downloads.
Enable USB DFU support. Tested on AM57x GP EVM Rev
A3 using DFU to download to connected SD card.
configs for HS version of the AM57x EVM are
included in the patch but not really tested.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Introduce include/environment/ti/dfu.h that
consolidates environment variable definitions
for various TI boards that support DFU today.
Tested on AM335x EVM, AM437x SK EVM and DRA74x
EVM by using DFU to write to SD card.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Some header files have this macro defined conditionally and
redefined unconditionally. Remove all existing definitions.
Signed-off-by: York Sun <york.sun@nxp.com>
When using #define CONFIG_SOME_OPTION, the value it set to '1'. When using
defconfig (i.e. CONFIG_SOME_OPTION=y) the value is set to 'y'. This results
in differences showing up with -K. These differences are seldom useful.
Adjust buildman to suppress these differences by default.
Signed-off-by: Simon Glass <sjg@chromium.org>
Normally buildman does a full build of a board. This includes creating the
u-boot.cfg file which contains all the configuration options. Buildman uses
this file with the -K option, to show differences in effective configuration
for each commit.
Doing a full build of U-Boot just to create the u-boot.cfg file is wasteful.
Add a -D option which causes buildman to only create the configuration. This
is enough to support use of -K and can be done much more quickly (typically
5-10 times faster).
Signed-off-by: Simon Glass <sjg@chromium.org>
A common requirement when converting CONFIG options to Kconfig is to check
that the effective configuration has not changed due to the conversion. Add
a target which creates this configuration (in the form of u-boot.cfg) but
does not build U-Boot. This speeds up the checking.
Signed-off-by: Simon Glass <sjg@chromium.org>
Now that we free resources in sandbox_fs_ls Coverity is letting us know
that in some cases we might leak. So in case of error we should still
let os_dirent_free free anything that was allocated.
Fixes: 86167089b7 ("sandbox/fs: Free memory allocated by os_dirent_ls")
Reported-by: Coverity (CID: 153450)
Cc: Stefan Brüns <stefan.bruens@rwth-aachen.de>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The Atmel AT97SC3204 is also TIS compliant.
Modify the tpm_tis_lpc driver to check for the vid/did used by the
Atmel AT97SC3204 and report an appropriate description.
Signed-off-by: George McCollister <george.mccollister@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
GCC 6.2 reasonably complains about the current code:
../cmd/tpm_test.c: In function ‘do_tpmtest’:
../cmd/tpm_test.c:540:3: warning: this ‘for’ clause does not guard... [-Wmisleading-indentation]
for (i = 0; i < argc; i++)
^~~
../cmd/tpm_test.c:542:4: note: ...this statement, but the latter is misleadingly indented as if it is guarded by the ‘for’
printf("\n------\n");
^~~~~~
Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Updated to remove C99 variable decl:
Signed-off-by: Simon Glass <sjg@chromium.org>
Now all mpc85xx and mpc86xx have converted to use SYS_CCSRBAR_DEFAULT
in Kconfig. Drop this macro for LSCH2 and remove from white list.
Signed-off-by: York Sun <york.sun@nxp.com>
Two functions should be static because they are not exported to any
other file.
Warnings were reported by sparse C=1.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
When blk_create_device() is called some parameters in blk_desc are
automatically filled. Separate SCSI private initialization and SCSI full
block device initialization not to rewrite already prepared data.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Several functions should be static because they are not exported to any
other file.
Warnings were reported by sparse C=1.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
These functions are not called for any location.
This patch removes them scsi_trim_trail(), scsi_get_disk_count()
and scsi_setup_read6().
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
There is no reason to directly point to static allocated array
when we have proper block_dev pointer available via parameter
in !CONFIG_BLK. For CONFIG_BLK this is read directly from uclass
platdata.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
pccb is pointer to temporary buffer which is used only for sending
command. Make it local as is done in scsi_read/scsi_write.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Prepare LUN(Logical unit number) directly in block description structure
and reuse it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The patch enables running detection algorithm on block device
description structure.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
It is confusing that mdio commands work and report phy id as
decimal value when mii is working with hex values.
For example:
ZynqMP> mdio list
gem:
21 - TI DP83867 <--> ethernet@ff0e0000
ZynqMP> mdio read ethernet@ff0e0000 0
Reading from bus gem
PHY at address 21:
0 - 0x1140
ZynqMP> mii dump 21 0
Incorrect PHY address. Range should be 0-31
...
ZynqMP> mii dump 15
0. (1140) -- PHY control register --
(8000:0000) 0.15 = 0 reset
U-Boot normally takes hex values that's why this patch is changing mdio
command to handle hex instead of changing mii command to handle decimal
values.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Using alternative bootmode field to support automatic secondary boot
modes. It is purely software setting where SW modes are using free
bootmode combinations.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
CONFIG_SYS_CONFIG_NAME is not proper config option for different low
level init files because different board revisions requires different
psu_init_gpl* files.
Also at the end of moving drivers to DM all board specific configuration
files should be removed.
The same changes was done for Zynq.
"ARM: zynq: Simplify zynq configuration"
(sha1: ad5b580126)
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
ZynqMP provides an option to overwrite bootmode setting which
can change SPL behavior.
For example: boot SPL via JTAG and then SPL loads images from SD.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Offset 0x1 in the generated kwb image file is a set of flags, bit 0
enables debug output from the BootROM firmware. Allow a DEBUG option in
the kwb configuration to request debug output from the BootROM firmware.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Offset 0x18 in some Marvell datasheets this field is redacted as
"reserved". This offset is actually a set of options and bits 2:0 allow
the selection of the UART baudrate.
Allow a BAUDRATE option to set the UART baudrate for any messages coming
from the BootROM firmware.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
The main PLL frequency is 2GHz for Armada-XP and 1GHZ for Armada 375,
38x and 39x.
[ Linux commit ae142bd9976532aa5232ab0b00e621690d8bfe6a ]
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Make the spl_mmc_load_image() available globally, so it can be
invoked directly by SPL on extremely space-constrained systems.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Add new configuration option CONFIG_MMC_TINY which strips away all
memory allocation within the MMC code and code for handling multiple
cards. This allows extremely space-constrained SPL code use the MMC
framework.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
If debug() is not used, then the whole content of debug(...) will
be removed by the preprocessor, which will result in the following
warning. This patch adds __maybe_unused annotation to fix this.
drivers/mmc/mmc.c: In function ‘mmc_init’:
drivers/mmc/mmc.c:1685:11: warning: variable ‘start’ set but not used [-Wunused-but-set-variable]
unsigned start;
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Add new command that provides possibility to enable the
background operations handshake functionality
(BKOPS_EN, EXT_CSD byte [163]) on eMMC devices.
This is an optional feature of eMMCs, the setting is write-once.
The command must be explicitly taken into use with
CONFIG_CMD_BKOPS_ENABLE.
Signed-off-by: Tomas Melin <tomas.melin@vaisala.com>
At sdhci_get_config(), there was wrong condition to check pimux
id, so this patch fixes to check proper pinmux id.
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Without this change we see:
../arch/arm/cpu/arm926ejs/mxs/mxs.c: In function ‘print_cpuinfo’:
../arch/arm/cpu/arm926ejs/mxs/mxs.c:181:23: warning: unused variable ‘data’ [-Wunused-variable]
../arch/arm/cpu/arm926ejs/mxs/mxs.c:180:6: warning: variable ‘cpurev’ set but not used [-Wunused-but-set-variable]
So the easy solution is to disable CONFIG_DISPLAY_CPUINFO
Reviewed-by: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
In order to avoid running into the time limit, split the 32bit and 64bit
Freescale boards into separate jobs. We could either pass
"freescale & armv8" to buildman or exclude all of the 32bit CPUs. While
the former is shorter I fear the amount of possible escaping required
would make things less readable.
Signed-off-by: Tom Rini <trini@konsulko.com>
map_physmem should return a pointer that can be used by the CPU to
access the given memory - on MIPS simply returning the physical address
as it does prior to this patch doesn't achieve that. Instead return a
pointer to the memory within (c)kseg0, which matches up consistently
with the (c)kseg1 pointer that uncached mappings return via ioremap.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
When calculating the region to reserve for the stack in
arch_lmb_reserve, make use of ram_top instead of adding bi_memsize to
CONFIG_SYS_SDRAM_BASE. This avoids overflow if the system has enough
memory to reach the end of the address space.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Enable initr_trap hook also for MIPS to install and enable
U-Boot's specific MIPS exception handlers.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add exception handlers for generic and EJTAG exceptions. Most of
the assembly code is imported from Linux kernel and adapted to U-Boot.
The exception vector table will be reserved above the stack before
U-Boot is relocated. The exception handlers will be installed and
activated after relocation in the initr_traps hook function.
Generic exceptions are handled by showing a CPU register dump similar
to Linux kernel. For example:
malta # md 1
00000001:
Ooops:
$ 0 : 00000000 00000000 00000009 00000004
$ 4 : 8ff7e108 00000000 0000003a 00000000
$ 8 : 00000008 00000001 8ff7cd18 00000004
$12 : 00000002 00000000 00000005 0000003a
$16 : 00000004 00000040 00000001 00000001
$20 : 00000000 8fff53c0 00000008 00000004
$24 : ffffffff 8ffdea44
$28 : 90001650 8ff7cd00 00000004 8ffe6818
Hi : 00000000
Lo : 00000004
epc : 8ffe6848 (text bfc28848)
ra : 8ffe6818 (text bfc28818)
Status: 00000006
Cause : 00000410 (ExcCode 04)
BadVA : 8ff9e928
PrId : 00019300
### ERROR ### Please RESET the board ###
EJTAG exceptions are checked for SDBBP and delegated to the SDBBP handler
if necessary. Otherwise the debug mode will simply be exited. The SDBBP
handler currently prints the contents of registers c0_depc and c0_debug.
This could be extended in the future to handle semi-hosting according to
the MIPS UHI specification.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Paul Burton <paul.burton@imgtec.com>
Tested-by: Paul Burton <paul.burton@imgtec.com>
In order to set own exception handlers, a table with the exception
vectors must be built in DRAM and the CPU EBase register must be
set to the base address of this table.
Reserve the space above the stack and use gd->irq_sp as storage
for the exception base address.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Import asm-offsets.c from kernel to generate offset for struct pt_regs
needed by exception handlers.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
This adds a new Kconfig option CONFIG_MIPS_INIT_STACK_IN_SRAM which
a SoC can select if it supports some kind of SRAM. Together with
CONFIG_SYS_INIT_SP_ADDR the initial stack and global data can be
set up in that SRAM. This can be used to provide a C environment
also for lowlevel_init().
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Move the code for setting up the initial stack and global data
to a macro to be able to use it more than once.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Clear cp0 status while preserving implementation specific bits.
Set bits BEV and ERL as the arch specification requires after
a reset or soft-reset exception.
Extend and fix initialization of watch registers. Check if additional
watch register sets are implemented and initialize them too.
Initialize cp0 count as early as possible to get the most
accurate boot timing.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
When booting from ROM, early exceptions can't be handled
properly. Instead of busy-looping give the developer the
possibilty to examine the situation. Invoke an UHI
exception operation which can be read as unhandled exception
by a hardware debugger if one is attached. If the debugger
doesn't support UHI, the exception is read as unexpected
breakpoint.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
This adds a compile time option to include code for static
exception vectors. Static exception vectors are only needed,
when the U-Boot entry point is equal to the CPU reset exception
vector address. For instance this is the case when U-Boot is
used as ROM in Qemu or booted from parallel NOR flash. When
U-Boot is booted from RAM (e.g. loaded there by SPL), the
exception vectors need to be setup dynamically, which is done
in follow-up commits.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
This patch extends the imx6 clock code to enable or disable the EIM
slow clock, which in necessary when one wants to use EIM interface t
o read/write from external memory (e.g. NOR).
Signed-off-by: Lukasz Majewski <l.majewski@majess.pl>
The catch-all job is failing due to time limits depending on factors out
of our control, so move Samsung and Rockchip boards into their own jobs
and then exclude them from the general ARM and AArch64 jobs.
Signed-off-by: Tom Rini <trini@konsulko.com>
Enable the escpi3 nets attached to the mikroBUS slot
on the i.MX7 Sabre evalution board. Also enble the SPI flash
commands to work with the "flash click" board.
This is V2 of this patch with changes recommended by the maintainer
CC: Jagan Teki <jteki@openedev.com>
Specify standard padding for payload to 68KB. This is derived from
the maximum header size plus maximum SPL size. It matches the
already defined offset for SD/eMMC devices (69KB) too. This allows
to use the u-boot-with-spl.imx build target to generate a directly
flashable image which can be flashed using:
dd if=u-boot-with-spl.imx of=/dev/mmcblk0 bs=512 skip=2
While the patch has been created with SD/eMMC in mind, this also
works with other boot media. The board file needs to configure the
media specific (absolute) payload offset accordingly. Especially
the IVT offset is boot media specific and can be retrieved from the
reference manual (Table 8-25. Image Vector Table Offset and Initial
Load Region Size). For NAND boot a define like this should do the
job:
#define CONFIG_SYS_NAND_U_BOOT_OFFS (SPL_PAD_TO + 0x400)
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
UDOO Neo Board is a development board from Seco that has three models:
- UDOO Neo Basic
- UDOO Neo Basic Kick Starter
- UDOO Neo Extended
- UDOO Neo Full
All versions are based on the i.MX6 SoloX processor.
For more details about the UDOO Neo board, please refer to:
http://www.udoo.org/udoo-neo/
This work is based on a previous commit of Francesco Montefoschi
<francesco.monte@gmail.com>:
877b71184a
Only tested on the UDOO Neo Full board.
Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Our update scripts write the kernel and device tree in seperate
UBI volumes. This allows to use a lot less UBI/UBIFS support in
U-Boot, which should lower the risk of hitting bugs in this area.
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Change the PMIC bulk configuration from auto mode to sync mode to avoid
voltage dropout issue seen in auto mode.
Signed-off-by: Ken Lin <ken.lin@advantech.com.tw>
Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
The DDR calibration routines are gated by conditionals for the
i.MX6DQ SOCs, but with the use of the sysinfo parameter, these
are usable on at least i.MX6SDL and i.MX6SL variants with DDR3.
Also, since only the Novena board currently uses the dynamic
DDR calibration routines, these routines waste space on other
boards using SPL.
Add a KConfig entry to allow boards to selectively include the
DDR calibration routines.
Signed-off-by: Eric Nelson <eric@nelint.com>
Add routine mmdc_read_calibration() to return the output of DDR
calibration. This can be used for debugging or to aid in construction
of static memory configuration.
This routine will be used in a subsequent patch set adding a virtual
"mx6memcal" board, but could also be useful when gathering statistics
during an initial production run.
Signed-off-by: Eric Nelson <eric@nelint.com>
The DDR calibration routines have scattered support for bus
widths other than 64-bits:
-- The mmdc_do_write_level_calibration() routine assumes the
presence of PHY1, and
-- The mmdc_do_dqs_calibration() routine tries to determine
whether one or two DDR PHYs are active by reading MDCTL.
Since a caller of these routines must have a valid struct mx6_ddr_sysinfo
for use in calling mx6_dram_cfg(), and the bus width is available in the
"dsize" field, use this structure to inform the calibration routines which
PHYs are active.
This allows the use of the DDR calibration routines on CPU variants
like i.MX6SL that only have a single MMDC port.
Signed-off-by: Eric Nelson <eric@nelint.com>
Reviewed-by: Marek Vasut <marex@denx.de>
The DDR calibration code is only setting flag DG_CMP_CYC (DQS gating sample
cycle) for the first PHY.
Set the 32-cycle flag for both PHYs and clear when done so the MPDGCTRL0
output value isn't polluted with calibration artifacts.
Signed-off-by: Eric Nelson <eric@nelint.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Add constants for the MPZQLP2CTL DDR register for both
banks to allow setting the LPDDR2 timing values in
.cfg files using a named constant instead of hex addresses
as is currently done in mx6slevk and other board files.
Signed-off-by: Eric Nelson <eric@nelint.com>
When I tried to deactivate VIDEO support for the Wandboard, it still
tried to initialize the Framebuffer and so on. That is the reason for
the added ifdefs. CONFIG_VIDEO is enabled in the configuration as default
and therefore nothing changes for the default user.
The structs mx6dl_i2c2_pad_info and mx6q_i2c2_pad_info are only available
when CONFIG_IPUV3 are set and should not be tried to access, when that
define is not defined.
Signed-off-by: Sven Ebenfeld <sven.ebenfeld@gmail.com>
This patch increases supported PWMs from previously PWM4 now up to PWM8
if i.MX6SX is in use.
Signed-off-by: Christoph Fritz <chf.fritz@googlemail.com>
Configure the PHY to output a 125MHz clk from CLK_25M and set tx clock delay.
This patch is similar to commit 4b6035da48
("mx6sabresd: Make Ethernet functional again").
Signed-off-by: Soeren Moch <smoch@web.de>
The ipu has two display interfaces. Make the used one a parameter
in struct display_info_t instead of using unconditionally DI0.
DI0 is the default setting.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Reviewed-by: Eric Nelson <eric@nelint.com>
If CONFIG_SPL_LIBCOMMON_SUPPORT is not defined there is a lone case statement
at the end of the switch leading to a compile error.
Remove the offending case statement.
| common/spl/spl_mmc.c:339:7: error: label at end of compound statement
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Marek Vasut <marex@denx.de>
Check BOOT_CFG2[3:4] to determine which SD/MMC port is selected to boot
from. If MMC2 is selected return BOOT_DEVICE_MMC2. In all other cases
return BOOT_DEVICE_MMC1, as we do not have corresponding macro for MMC3
and MMC4.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
Before disable cache, need to first flush cache.
There maybe dirty data in D-Cache before disable D-Cache.
After disable D-Cache, the first store instructions in
psci_v7_flush_dcache_all will directly store registers
{r4-r5, r7, r9-r11, lr} to memory.
If there is dirty data before disable D-Cache,
psci_v7_flush_dcache_all will flush data to memory,
and may overwrite the memory that hold the registers
{r4-r5, r7, r9-r11, lr}.
So before disable cache, first flush D-Cache.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Chen-Yu Tsai <wens@csie.org>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Hongbo Zhang <hongbo.zhang@nxp.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Tom Rini <trini@konsulko.com>
Juno uses a 1:1 mapping between CPU and PCI addresses for IO. First,
that will trip devices that cannot use more than 16 bits of addresses
for IO, second it is un-necessary as the system can handle zero-based
PCI addresses just fine.
Change the mapping to start IO bus addresses from zero.
Signed-off-by: Liviu Dudau <Liviu.Dudau@foss.arm.com>
Firmware provides a spin table on the raspberry pi. This table shouldn't
get overwritten by payloads, so we need to mark it as reserved.
Signed-off-by: Alexander Graf <agraf@suse.de>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
To enable working efifb support, let's map the frame buffer as 32bpp
instead of 16bpp.
Signed-off-by: Alexander Graf <agraf@suse.de>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
The rpi has a pretty simple way of resetting the whole system. All it takes
is to poke a few registers at a well defined location in MMIO space.
This patch adds support for the EFI loader implementation to allow an OS to
reset and power off the system when we're outside of boot time.
Signed-off-by: Alexander Graf <agraf@suse.de>
Add support to detect RGMII link interface from link-interface
device tree entry. Also rename the existing link type enums so
that it provides meaningful interface like SGMII.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reported-by: Sekhar Nori <nsekhar@ti.com>
Tested-by: Sekhar Nori <nsekhar@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This patch removes use of U_BOOT_DEVICE in board/raspberrypi/rpi/rpi.c,
enables OF_CONTROL in the config and adjusts the rpi_*defconfig configs.
Signed-off-by: Fabian Vogt <fvogt@suse.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
When using OF_CONTROL, the disabled value of the mini UART platdata
gets reset after board_early_init_f. So move detection and disabling
to board_init and remove board_early_init_f.
This uses the first device using the mini uart driver, as this method
works reliably with different device trees or even no device tree at all.
Signed-off-by: Fabian Vogt <fvogt@suse.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
For the Raspberry Pi 3 it needs to be possible to disable the serial
device after initialization happens, as only after the GPIO device is available
it is known whether the mini uart is usable.
Signed-off-by: Fabian Vogt <fvogt@suse.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The information currently set via platdata has to be represented in the
device tree now. bcm283x-uboot.dtsi adds the u-boot specific "skip-init"
property to the serial nodes and enables initialization in the pre-reloc phase.
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Signed-off-by: Fabian Vogt <fvogt@suse.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This patch adds device trees for the bcm283x platform to be used with
OF_CONTROL. The version 4.8-rc7 of the linux kernel was used as source.
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Signed-off-by: Fabian Vogt <fvogt@suse.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This patch adds dt-bindings as used by the linux kernel device trees
for the bcm283x family.
Albert Aribaud <albert.u.boot@aribaud.net>
Signed-off-by: Fabian Vogt <fvogt@suse.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
To be able to represent the skip-init platdata element with OF_CONTROL,
it needs to be read from the device tree as well and put into the platform data.
Cc: Eric Anholt <eric@anholt.net>
Signed-off-by: Fabian Vogt <fvogt@suse.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This patch adds device tree support for the bcm283x mini-uart driver.
Signed-off-by: Fabian Vogt <fvogt@suse.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This patch adds device tree support for the bcm2835 GPIO driver.
Signed-off-by: Fabian Vogt <fvogt@suse.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
fill_dir_slot use get_contents_vfatname_block as a temporary buffer for
constructing a list of dir_slot entries. To save the memory and providing
correct type of memory for above usage, a local buffer with accurate size
declaration is introduced.
The local array size 640 is used because for long file name entry,
each entry use 32 bytes, one entry can store up to 13 characters.
The maximum number of entry possible is 20. So, total size is
32*20=640bytes.
Signed-off-by: Genevieve Chan <ccheauya@altera.com>
Signed-off-by: Tien Fong Chee <tfchee@altera.com>
Introduce USB Gadget config option. This allows to combine Makefile
entries for SPL_USBETH_SUPPORT and SPL_DFU_SUPPORT.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Tested-by: Ravi Babu <ravibabu@ti.com>
The DFU Kconfig menu entries should be part of the SPL
Kconfig file. Also avoid using the top level Makefile by
moving the config dependent build artifacts to the driver/
and driver/usb/gadget/ Makfiles.
With that, DFU can be built again in SPL if
CONFIG_SPL_DFU_SUPPORT is enabled.
Fixes: 6ad6102246 ("usb:gadget: Disallow DFU in SPL for now")
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Some devices (e.g. dra7xx) support loading to RAM using DFU without
having direct boot from RAM support. Make sure the linker list
does not contain BOOT_DEVICE_RAM if CONFIG_SPL_RAM_DEVICE is not
enabled.
Fixes: 98136b2f26 ("spl: Convert spl_ram_load_image() to use linker list")
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
This fixes the loop delay when using a hw watchdog.
In case a watchdog is used that accesses CPU registers,
the defined delay of 20us in a tight loop will cause a
huge delay in the actual timeout seen. This is caused
by the fact that udelay will inheritantly call WATCHDOG_RESET.
Together with the omap wdt implementation, the seen timeout increases up to
around 30s. This makes the loop very slow and causes long
delays when using the modem.
Instead, implement the 2 sec loop by using the timer interface to know
when to break out of the timeout loop. Watchdog kicking is taken care of
by getc().
Signed-off-by: Tomas Melin <tomas.melin@vaisala.com>
Commit d97dc8a0 separated the non-command code into its own file
which caused variable sata_curr_device can not be set to a correct
value.
Before commit d97dc8a0, variable sata_curr_device can be set
correctly in sata_initialize().
After commit d97dc8a0, sata_initialize() is moved out to its own file.
Accordingly, variable sata_curr_device is removed from sata_initialize()
too. This caused sata_curr_device never gets a chance to be set properly
which prevent other commands from being executed.
This patch sets variable sata_curr_device properly.
Fixes: d97dc8a0 (dm: sata: Separate the non-command code into its
own file)
Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
commit 183923d3e4 enforces that the
environment must start at an erase block boundary.
For block devices the sample fw_env.config does not mandate a erase block size
for block devices. A missing setting defaults to the full env size.
Depending on the environment location the alignment check now errors out for
perfectly legal settings.
Fix this by defaulting to the standard blocksize of 0x200 for environments
stored in a block device.
That keeps the fw_env.config files for block devices working even with that
new check.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
The Makefile in tools/ tries to find the "swig" utility by calling "which".
If nothing is found in the path, some versions of which will print an error
message:
$ make clean
which: no swig in (/usr/local/bin:/usr/bin:/bin)
This does not apply to all version of "which", though:
$ echo $0
bash
$ type which
which is aliased to `type -path'
$ which foo <== this version is OK
$ /usr/bin/which foo <== this one is chatty
/usr/bin/which: no foo in (/usr/local/bin:/usr/bin:/bin)
$ sh <== make uses /bin/sh
sh-4.3$ which foo <== no alias here
which: no foo in (/usr/local/bin:/usr/bin:/bin)
This error message is rather pointless in our case, since we just have
this very check to care for this. So add stderr redirection to suppress
the message.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
NFS loading support has been added to the default environment for
most boot components, as PMMC and MON loading were added later they
did not originally get the NFS commands added, add these now.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
The config option TARGET_K2x_EVM is set by the k2x defconfigs to pick
a board target, but the header configs also set K2x_EVM. This config
is redundant, remove it and use TARGET_K2x_EVM everywhere in its place.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
This patch fixes the warning about misaligned cache on Armada XP:
CACHE: Misaligned operation at range [7ffff000, 7fffffac]
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Valentin Longchamp <valentin.longchamp@keymile.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Commit c68c62 ("i2c: mvtwsi: Make delay times frequency-dependent")
extensively used the ndelay function with a calculated parameter
which is dependant on the configured frequency of the I2C bus. If
standard speed is employed, the parameter is usually 10000 (10000ns
period length for 100kHz frequency).
But, since the arm architecture does not implement a proper version of
ndelay, the fallback default from include/linux/compat.h is used,
which defines every ndelay as udelay(1). This causes problems for
slower speeds on arm, since the delay time is now 9us too short for
the desired frequency, which leads to random failures of the I2C
interface.
To remedy this, we implement a proper, parameter-aware ndelay fallback
for architectures that don't implement a real ndelay function.
Reported-By: Jason Brown <Jason.brown@apcon.com>
To: Tom Rini <trini@konsulko.com>
To: Heiko Schocher <hs@denx.de>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Now with the config block handling in place move the U-Boot environment
location before the config block at the end of 1st "boot sector" as
deployed during production using our downstream BSP.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
Add Toradex factory configuration block handling. The config block is a
data structure which gets stored to flash during production testing. The
structure holds such information as board resp. hardware revision,
product ID and serial number which is used as the NIC part of the
Ethernet MAC address as well. The config block will be read upon boot by
the show_board_info() function, displayed as part of the board
information and passed to Linux via device tree or ATAGs.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
Deactivate CONFIG_DISPLAY_BOARDINFO in favour of
CONFIG_DISPLAY_BOARDINFO_LATE which also displays on the LCD.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
Drop CONFIG_CUSTOM_BOARDINFO as it is not Kconfig compliant and anyway
not really used anywhere plus the upcoming weak show_board_info()
approach seems much superior.
This reverts commit a9ad18c9d5.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
Add check for FDT_MAGIC, otherwise also legacy images will be loaded as
a FIT. With this check in place, the loader works correct both
with legacy and FIT images.
Signed-off-by: Tomas Melin <tomas.melin@vaisala.com>
Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
To send a parametrized command to the PHY over MDIO, we should write
the data first, the trigger the execution by the command register
write. Fix the access pattern in our MDIO write routine.
Apparently this doesn't really matter with the Realtek PHY on the
Pine64, but other PHYs (which require more setup) will choke on
the wrong order.
[Andre: add commit message]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Jagan Teki <jagan@openedev.com>
Add board support for sun8i_r16 Nintendo NES Classic edition.
Signed-off-by: FUKAUMI Naoki <naobsd@gmail.com>
[jagan: Add commit message body]
Signed-off-by: Jagan Teki <jagan@openedev.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
And also remove it from scripts/config_whitelist.txt as the
Mele_M5_defconfig was the only one defining it.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Set CONFIG_SYS_MMC_MAX_DEVICE to 4 for sunxi SoC.
This define is needed in the API code.
Signed-off-by: Emmanuel Vadot <manu@bidouilliste.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Currently, USB is forced-enabled for the sunxi familly, and there is no
way to disable it.
However, USB takes a long time to initiliase, delaying the boot by up to
5 seconds (without any USB device attached!). This is a very long delay,
especially in cases where USB booting is not wanted at all, and where
the device is expected to boot relatively often (even in production).
Change the way the dependencies are handled, by only forcibly selecting
USB when CONFIG_DISTRO_DEFAULTS ("defaults suitable for booting general
purpose Linux distributions") is set. This option defaults to y for the
sunxi familly, so the current default behaviour is kept unchanged. Users
interested in boot time and/or size will be able to disable this to
further disable USB.
With USB disabled, the time spent in U-Boot before handing control to
the Linux kernel is about 1s now, down from ~5s (Nanopi Neo, sunxi H3).
Signed-off-by: "Yann E. MORIN" <yann.morin.1998@free.fr>
Cc: Ian Campbell <ijc@hellion.org.uk>
Cc: Hans De Goede <hdegoede@redhat.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Use the already available Kconfig option for AHCI. Tested on the
BananaPi.
Signed-off-by: Jelle van der Waa <jelle@vdwaa.nl>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
We have all the building blocks now to run arbitrary efi applications
in travis. The most important one out there is grub2, so let's add
a simple test to verify that grub2 still comes up.
Signed-off-by: Alexander Graf <agraf@suse.de>
Most of the time when running the sleep test in Travis for
the integratorcp_cm926ejs target I get errors like this:
E assert 2.999901056289673 >= 3
The deviation is tiny, but fails the overall build result. Since
the sleep test is not terribly important as gate keeper for travis
tests, let's just exclude it for this board.
Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Today we can compile a self-contained hello world efi test binary that
allows us to quickly verify whether the EFI loader framwork works.
We can use that binary outside of the self-contained test case though,
by providing it to a to-be-tested system via tftp.
This patch separates compilation of the helloworld.efi file from
including it in the u-boot binary for "bootefi hello". It also modifies
the efi_loader test case to enable travis to pick up the compiled file.
Because we're now no longer bloating the resulting u-boot binary, we
can enable compilation always, giving us good travis test coverage.
Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Now that we have working network tests and a hello world efi application
built inside our tree, we can automatically test that efi binary running
inside of U-Boot.
Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
When running in travis-ci, we want to pass environment configuration to
the tests. These reside in a path available through PYTHONPATH, so let's
define that one to point to the unit test repo.
Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Some travis QEMU tests can transfer files between the build directory
and the guest U-Boot instance. For that to work, both need to have access
to the same directory.
This patch puts the current build path into an environment variable, so
that the environment generating python scripts can extract it from there
and read the respective files.
Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
The network test currently downloads files at 0MB offset of RAM start.
This works for most ARM systems, but x86 has weird memory layout constraints
on the first MB of RAM.
To not get caught into any of these, let's add a 4MB pad from start
of RAM to the default memory offset.
Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
This adds support for the Asus Chromebook Flip, an RK3288-based clamshell
device which can flip into 'tablet' mode. The device tree file comes from
Linux v4.8. The SDRAM parameters are for 4GB Samsung LPDDR3.
Signed-off-by: Simon Glass <sjg@chromium.org>
This adds support for the Asus Chromebit, and RK3288-based device designed
to plug directly into an HDMI monitor. The device tree file comes from
Linux v4.8.
Signed-off-by: Simon Glass <sjg@chromium.org>
It makes not sense using u8 to hold a value on a 32-bit or 64-bit machine.
It can only bloat the code by forcing the compiler to mask the value.
Change it to uint.
Signed-off-by: Simon Glass <sjg@chromium.org>
Update board_init() to increase the ARM clock to the maximum speed on
veyron boards. This makes quite a large difference in performance. With
this change, speed goes from about 750 DMIPS to 2720 DMIPs.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add basic support for setting the ARM clock, since this allows us to run
at maximum speed in U-Boot. Currently only a single speed is supported
(1.8GHz).
Signed-off-by: Simon Glass <sjg@chromium.org>
At present we have a single rk3288-based Chromebook: chromebook_jerry. But
all such Chromebooks can use the same binary with only device-tree
differences. The family name is 'veyron', so rename the files accordingly.
Also update the device-tree filename since this currently differs from
Linux.
Signed-off-by: Simon Glass <sjg@chromium.org>
Adjust jerry to use of-platdata like other rk3288 boards. This reduces the
SPL size enough that it boots again.
Signed-off-by: Simon Glass <sjg@chromium.org>
Check whether a display device is in use before using it. Add a comment as
to why two displays cannot currently be used at the same time.
This allows us to remove the device-tree change that disables vopb on
jerry.
Signed-off-by: Simon Glass <sjg@chromium.org>
Mark a display as in use when display_enable() is called. This can avoid
a display being used by multiple video-output devices.
Signed-off-by: Simon Glass <sjg@chromium.org>
Sometimes the frame buffer is not a multiple of the cache line size.
Adjust the cache-flushing code to avoid cache warnings/errors in this
case.
Signed-off-by: Simon Glass <sjg@chromium.org>
Some boards may want to use these subsystems with of-platdata in SPL. Add
support for this by avoiding any device tree access in this case.
Signed-off-by: Simon Glass <sjg@chromium.org>
The current code assumes that the devices are ordered corresponding to
their alias value. But (for example) video1 can come before video0 in the
device tree.
Correct this, by always looking for device 0 first. After that we can fall
back to finding the first available device.
Signed-off-by: Simon Glass <sjg@chromium.org>
This board always boots from SPI, so update the code to support that with
of-platdata. The boot source is not currently available with of-platdata.
Signed-off-by: Simon Glass <sjg@chromium.org>
This code incorrectly uses the oscillator. It should use the clock
selected in the device tree.
Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes: 135aa95 (clk: convert API to match reset/mailbox style)
This code currently always selects the second source. It only worked
because both sources are set up.
With the change to only init video devices that are present in the stdout
environment variable, this fails. Fix it.
Signed-off-by: Simon Glass <sjg@chromium.org>
PWM_ROCKCHIP need to enable for PWM regulator, this config
is missing during rebase and new patch set in previous submission.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
The size dram node need to be deduced by the same amount of reserved space.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Currently the specific set ops functions are directly
called without any check for min/max current limits for a regulator.
Check for them and proceed.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Fixed checking of current limits:
Signed-off-by: Simon Glass <sjg@chromium.org>
Currently the specific set ops functions are directly
called without any check for voltage limits for a regulator.
Check for them and proceed.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Fixed checking of voltate limits:
Signed-off-by: Simon Glass <sjg@chromium.org>
In case we want to force a particular value on a regulator
irrespective of the min/max constraints for testing purposes
one can call regulator_set_value_force function.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This configuration has been moved into Kconfig for mpc85xx, and
dropped for mpc86xx. Remove the default value in config.h.
Signed-off-by: York Sun <york.sun@nxp.com>
CONFIG_T104xRDB is defined in T104xRDB.h, so it is always enabled for
all T1040RDB, T1040D4RDB, T1042RDB, T1042D4RDB, T1042RDB_PI.
CONFIG_T104XD4RDB is defined for all T1040D4RDB, T1042D4RDB.
Signed-off-by: York Sun <york.sun@nxp.com>
Use TARGET_T1040D4RDB in Kconfig to simplify config macros. Replace
CONFIG_T1040D4RDB with TARGET_T1040D4RDB and clean up existing macros.
Signed-off-by: York Sun <york.sun@nxp.com>
P2010 is a single-core version of P2020. There is no P2010 target
configured. Drop related macros. P2010 SoC is still supported.
Signed-off-by: York Sun <york.sun@nxp.com>
All boards covered by this group have been converted to their own
targers. Drop TARGET_P1_P2_RDB_PC from Kconfig.
Signed-off-by: York Sun <york.sun@nxp.com>
Use TARGET_P2020RDB_PC instead of sharing with P1_P2_RDB_PC to
simplify Kconfig and config macros.
Remove macro CONFIG_P2020RDB.
Signed-off-by: York Sun <york.sun@nxp.com>
Use TARGET_P1025RDB instead of sharing with P1_P2_RDB_PC to
simplify Kconfig and config macros.
Remove macro CONFIG_P1025RDB.
Signed-off-by: York Sun <york.sun@nxp.com>
Use TARGET_P1024RDB instead of sharing with TARGET_P1_P2_RDB_PC to
simplify Kconfig and macros.
Remove macro CONFIG_P1024RDB.
Signed-off-by: York Sun <york.sun@nxp.com>
Use TARGET_P1021RDB instead of sharing with TARGET_P1_P2_RDB_PC to
simplify Kconfig and macros.
Remove macro CONFIG_P1021RDB.
Signed-off-by: York Sun <york.sun@nxp.com>
Use TARGET_P1020UTM instead of sharing with TARGET_P1_P2_RDB_PC
to simplify Kconfig and config macros.
Remove macro CONFIG_P1020UTM.
Signed-off-by: York Sun <york.sun@nxp.com>
Use TARGET_P1020RDB_PD instead of sharing with P1_P2_RDB_PC
to simplify Kconfig and config macros.
Remove macro CONFIG_P1020RDB_PD.
Signed-off-by: York Sun <york.sun@nxp.com>
Use TARGET_P1020RDB_PC instead of sharing with TARGET_P1_P2_RDB_PC
to simplify Kconfig and config macros.
Remove macro CONFIG_P1020RDB_PC.
Signed-off-by: York Sun <york.sun@nxp.com>
Use TARGET_P1020MBG instead of sharing with TARGET_P1_P2_RDB_PC to
simplify Kconfig and other macros.
Remove macro CONFIG_P1020MBG.
Signed-off-by: York Sun <york.sun@nxp.com>
P1017 is a single-core version of P1023. There is no P1017 target
configured. Drop related macros. P1017 SoC is still supported.
Signed-off-by: York Sun <york.sun@nxp.com>
P1014 is a variant of P1010. There is no P1014 target configured.
Drop related macros. P1014 SoC is still supported.
Signed-off-by: York Sun <york.sun@nxp.com>
P1013 is a single-core version of P1022. There is no P1022 target
configured. Drop related macros. P1022 SoC is still supported.
Signed-off-by: York Sun <york.sun@nxp.com>
P1012 is a single-core version of P1021. There is no P1012 target
configured. Drop related macros. P1012 SoC is still supported.
Signed-off-by: York Sun <york.sun@nxp.com>
Remove CONFIG_P1010RDB_PA and CONFIG_P1010RDB_PB and split TARGET_P1010RDB
to TARGET_P1010RDB_PA and TARGET_P1010RDB_PB in Kconfig.
Signed-off-by: York Sun <york.sun@nxp.com>
Replace CONFIG_BSC9131, CONFIG_BSC9132 with ARCH_BSC9131, ARCH_BSC9132
Kconfig options.
Also drop #ifdef in BSC9131RDB.h since it is redundant.
Signed-off-by: York Sun <york.sun@nxp.com>
While we move some config macros to Kconfig, kconfig header is needed
to avoid compiling error if not already included.
Signed-off-by: York Sun <york.sun@nxp.com>
Commit ec6617c3 includes autoconf.h in image-fit.c, causing conflict
for board odroid-xu3 which overwrites CONFIG_SYS_BOARD in header
file. Move the include higher and use linux/kconfig.h instead of
generated/autoconf.h.
Signed-off-by: York Sun <york.sun@nxp.com>
CC: Alison Wang <alison.wang@nxp.com>
To align with SPL change 38fed8ab and 693d4c9f, add Kconfig option
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR to defconfig, and remove
CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS.
Signed-off-by: York Sun <york.sun@nxp.com>
CC: Feng Li <feng.li_2@nxp.com>
With em humble DM and Kconfig migraters U-Boot binary size keeps
increasing. Drop a bunch of less needed stuff to save another precious
20+ KB.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Migrate the PXA serial driver to be configured via Kconfig.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Marek Vasut <marex@denx.de>
As PSCI and secure monitor firmware framework are enabled, this patch is
to support loading 32-bit OS in such case. The default target exception
level returned to U-Boot is EL2, so the corresponding work to switch to
AArch32 EL2 and jump to 32-bit OS are done in U-Boot and secure firmware
together.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Spin-table method is used for secondary cores to load 32-bit OS. The
architecture information will be got through checking FIT image and
saved in the os_arch element of spin-table, then the secondary cores
will check os_arch and jump to 32-bit OS or 64-bit OS automatically.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
To support loading a 32-bit OS, the execution state will change from
AArch64 to AArch32 when jumping to kernel.
The architecture information will be got through checking FIT image,
then U-Boot will load 32-bit OS or 64-bit OS automatically.
Signed-off-by: Ebony Zhu <ebony.zhu@nxp.com>
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Remove the custom low-level initialization function and reuse the
default low-level initialization function. But this requires the
ARMV8_MULTIENTRY config option to be enabled for Exynos7420.
On Exynos7420, the boot CPU belongs to the second cluster and so
with ARMV8_MULTIENTRY config option enabled, the 'branch_if_master'
macro fails to detect the CPU as boot CPU. As a temporary workaround
the CPU_RELEASE_ADDR is set to point to '_main'.
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Reviewed-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
NXP ARMv8 SoC LS2080A release all secondary cores in one-go.
But other new SoCs like LS2088A, LS1088A release secondary
cores one by one.
Update code to release secondary cores based on SoC SVR
Add code to release cores one by one for non LS2080A SoCs
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
[YS: remove "inline" from declaration of initiator_type]
Reviewed-by: York Sun <york.sun@nxp.com>
The QorIQ LS2088A SoC is built on layerscape architecture.
It is similar to LS2080A SoC with some differences like
1)Timer controller offset is different
2)It has A72 cores
3)It supports TZASC module
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
LS2080 SoC and its personalities does not support TZASC
But other new SoCs like LS2088A, LS1088A supports TZASC
Hence, skip initializing TZASC for Ls2080A based on SVR
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
TZASC registers like TZASC_GATE_KEEPER, TZASC_REGION_ATTRIBUTES
are 32-bit regsiters.
So while doing register load-store operations, 32-bit intermediate
register, w0 should be used.
Update x0 register to w0 register type.
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Timer controller base address has been changed from
LS2080A SoC (and its personalities) to new SoCs like
LS2088A, LS1088A.
Use SVR based timer base address detection to avoid compile time #ifdef.
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This commit adds support for the Macronix MX66U51235F,
MX66L1G45G and Micron MT25QU02G, MT25QL02G flash parts.
Signed-off-by: Radu Bacrau <dumitru.bacrau@intel.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Radu Bacrau <radu.bacrau@gmail.com>
[Update proper commit header and 80-line cut on body]
Reviewed-by: Jagan Teki <jagan@openedev.com>
Starting with the changes to fix USB host on am57xx/am43xx we stopped
using usb_otg_ss1/related stuff and but we hadn't been enabling the
relevant options to cause the warnings until just recently.
Fixes: 55efadde7e (ARM: AM57xx: AM43xx: Fix USB host)
Fixes: a48d687c57 (configs: am57xx: Enable download gadget)
Signed-off-by: Tom Rini <trini@konsulko.com>
Currently, the fastboot item in menuconfig is a comment followed by a
boolean option withan empty prompt, followed by a menu:
*** FASTBOOT ***
[*]
Fastboot support --->
This is not "nice-looking" at all...
Change the logic to make the boolean option a "menuconfig" rather than a
mere "config", so that all dependent options gets groupped under a menu.
The layout is now:
*** FASTBOOT ***
[*] Fastboot support --->
Signed-off-by: "Yann E. MORIN" <yann.morin.1998@free.fr>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
The previous partition table did not support a separate device tree
and the kernel size was limited to 4MB. This update shows the
location of the device tree (labeled as spl-os) for those who
want to use Falcon Mode or use U-Boot to store the Flattened
Device Tree (FDT) to NAND without appending it to the kernel.
This also grows the kernel to 6MB since 4MB was becomming tight
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Commit ("2cd1ff84037a: OMAP3_LOGIC: Setup defconfig to enable
SPL and NAND booting") accidentally enabled FIT support.
This patch removes the FIT support.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
The memory map defined in commit ("49c7303f0e52: OMAP3: Enable SPL
on omap3_logic) was used by a copy-paste of another board without
fully understanding how the map works in Falcon mode. This patch
undoes the customization and uses the default SPL Memory Map
for OMAP3.
When building the uImage, set LOADADDR=0x82000000 and Falcon
mode should properly load.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Raspberry firmware used to pass a FDT blob at a fixed address (0x100),
but this is not true anymore. The address now depends on both the
memory size and the blob size [1].
If one wants to passthrough this FDT blob to the kernel, the most
reliable way is to save its address from the r2/x0 register in the
U-Boot entry point and expose it in a environment variable for
further processing.
This patch just does this:
- save the provided address in the global variable fw_dtb_pointer
- expose it in ${fdt_addr} if it points to a a valid FDT blob
There are many different ways to use it. One can, for example, use
the following script which will extract from the tree the command
line built by the firmware, then hand over the blob to a previously
loaded kernel:
fdt addr ${fdt_addr}
fdt get value bootargs /chosen bootargs
bootz ${kernel_addr_r} - ${fdt_addr}
Alternatively, users relying on sysboot/pxe can simply omit any FDT
statement in their extlinux.conf file, U-Boot will automagically pick
${fdt_addr} and pass it to the kernel.
[1] https://www.raspberrypi.org/forums//viewtopic.php?f=107&t=134018
Signed-off-by: Cédric Schieli <cschieli@gmail.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Implement a hook to allow boards to save boot-time CPU state for later
use. When U-Boot is chain-loaded by another bootloader, CPU registers may
contain useful information such as system configuration information. This
feature mirrors the equivalent ARMv7 feature.
Signed-off-by: Cédric Schieli <cschieli@gmail.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Remove the need to explicitly add SHA/RSA pairings. Invalid SHA/RSA
pairings will still fail on verify operations when the hash length is
longer than the key length.
Follow the same naming scheme "checksum,crytpo" without explicitly
defining the string.
Indirectly adds support for "sha1,rsa4096" signing/verification.
Signed-off-by: Andrew Duda <aduda@meraki.com>
Signed-off-by: aduda <aduda@meraki.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cut down on the repetition of algorithm information by defining separate
checksum and crypto structs. image_sig_algos are now simply pairs of
unique checksum and crypto algos.
Signed-off-by: Andrew Duda <aduda@meraki.com>
Signed-off-by: aduda <aduda@meraki.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Padding verification was done against static SHA/RSA pair arrays which
take up a lot of static memory, are mostly 0xff, and cannot be reused
for additional SHA/RSA pairings. The padding can be easily computed
according to PKCS#1v2.1 as:
EM = 0x00 || 0x01 || PS || 0x00 || T
where PS is (emLen - tLen - 3) octets of 0xff and T is DER encoding
of the hash.
Store DER prefix in checksum_algo and create rsa_verify_padding
function to handle verification of a message for any SHA/RSA pairing.
Signed-off-by: Andrew Duda <aduda@meraki.com>
Signed-off-by: aduda <aduda@meraki.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
checksum_algo's pad_len field isn't actually used to store the length of
the padding but the total length of the RSA key (msg_len + pad_len)
Signed-off-by: Andrew Duda <aduda@meraki.com>
Signed-off-by: aduda <aduda@meraki.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
With the move to arch/arm/mach-omap2 there are now very few uses of
CONFIG_OMAP_COMMON and further they can all be replaced with
CONFIG_ARCH_OMAP2, so do so.
Signed-off-by: Tom Rini <trini@konsulko.com>
This moves what was in arch/arm/cpu/armv7/omap-common in to
arch/arm/mach-omap2 and moves
arch/arm/cpu/armv7/{am33xx,omap3,omap4,omap5} in to arch/arm/mach-omap2
as subdirectories. All refernces to the former locations are updated to
the current locations. For the logic to decide what our outputs are,
consolidate the tests into a single config.mk rather than including 4.
Signed-off-by: Tom Rini <trini@konsulko.com>
To start consolidating various TI-related code, introduce the ARCH_OMAP2
symbol. While we have removed omap2-specific boards some time ago,
matching up with the kernel naming here will help overall.
Signed-off-by: Tom Rini <trini@konsulko.com>
Support was already implemented, but not hooked up. This fixes several
fails in the test cases.
Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
A sparse file may have regions not mapped by any extents, at the start
or at the end of the file, or anywhere between, thus not finding a
matching extent region is never an error.
Found by python filesystem tests.
Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
If a test uses a fixture which is expensive to setup, the fixture can
possibly created with session or module scope. As u_boot_console has
function scope, it can not be used in this case.
Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
The IP supports two ports, A and B, each providing up to 32 gpios.
The driver already creates a 2nd gpio bank by reading the 2nd node
from DT, so this is quite a simple change to support the 2nd bank.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Make Android partition table the same as for AM57x EVM.
1. Make "bootloader" partition start from 0x300 sectors offset, so
DRA7 is bootable in Android mode (see
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR option).
2. Increase "bootloader" partition size, because size of u-boot.img is
about 632 KiB (when building DT defconfig, with FIT image enabled).
3. Specify "reserved" partition explicitly, rather than specifying
"efs" partition start. Reserved area will be used to store U-Boot
environment on eMMC. It's convenient to have it exposed explicitly
so we can read/write U-Boot environment.
4. Keep all Android partitions locations intact, by reducing
"reserved" partition size. CONFIG_ENV_SIZE is considered.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
"fastboot oem format" command reuses "gpt write" command, which in turn
requires correct partitions defined in $partitions variable. This patch
adds such definition of Android partitions for DRA7XX EVM board.
By default $partitions variable contains Linux partition table. In order
to prepare Android environment one can run next commands from U-Boot
shell:
=> env set partitions $partitions_android
=> env save
After those operations one can go to fastboot mode and perform
"fastboot oem format" to create Android partition table.
While at it, enable CONFIG_RANDOM_UUID to spare user from providing
UUIDs for each partition manually.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Add support for distro_bootcmd on MMC and fall back to prior
behavior if distro_bootcmd fails.
Tested on Beagleboad xM to boot GRUB2 (and then Linux kernel) in EFI mode
from MMC.
Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Enable USB download gadget (needed for fastboot support) and all
dependencies.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
On "fastboot reboot-bootloader" we check "dofastboot" variable and do
"fastboot 0" command in U-Boot if it's 1. But there are boards which have
USB controller number other than 0, so it should be respected when
performing "fastboot" command.
This patch reuses CONFIG_FASTBOOT_USB_DEV option toprovide correct USB
controller number to "fastboot" command.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Some boards (like AM57x EVM) has USB OTG controller other than 0. So in
order to use correct controller number in compiled environment we should
define CONFIG_FASTBOOT_USB_DEV option.
For example, when doing "fastboot reboot-bootloader" we want to enter
fastboot mode automatically. But to do so we need to provide controller
number to "fastboot" command. If this procedure is defined in some config
which is common to bunch of boards, and boards have different USB
controller numbers, we can't just hardcode "fastboot 0" in the
environment. We need to use configurable option, which this patch adds.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Detect the board very early and avoid reading eeprom multiple times.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
This is similar to Commit 93e6253d11 ("ARM: OMAP4/5: Centralize
early clock initialization") that was done for OMAP4+, reflecting the same
for AM33xx and AM43xx SoCs to centralize clock initialization.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
[trini: Add setup_early_clocks that calls setup_clocks_for_console for
ti81xx]
Signed-off-by: Tom Rini <trini@konsulko.com>
Update CONFIG_LS2080A to CONFIG_FSL_LSCH3 to make those workaround
implementing of erratum reusable for more SoCs.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Change core clock to 1.2GHz in the configurations for SD and NAND boot.
Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The current value to check whether the PHY was configured has dependency
on MC, it expects MC to start PCS AN, this is not true during boot up,
so it should be changed to remove the dependency.
The PHY's register space should be restore to default after accessing
extended space.
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
It's not always true that LPUART clock is CONFIG_SYS_CLK_FREQ. This
patch provides a weak function get_lpuart_clk(), so that the clock
can be ovreridden on a specific board which uses different clock
for LPUART.
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
[YS: Reformat commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
The patch adds support for Freescale ls1021a-iot board.
Signed-off-by: Feng Li <feng.li_2@nxp.com>
[YS: rewrite commit message, fix whitespace in Kconfig]
Reviewed-by: York Sun <york.sun@nxp.com>
There is the stmicro DSPI flash on LS12080ARDB.
Enable DSPI flash related configure options.
Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Early system initialization is being done before initf_dm is being called
in U-Boot. Then system will fail to boot if any of the DM enabled driver
is being called in this system initialization code. So, rearrange the
code a bit so that DM enabled drivers can be called during early system
initialization. This is inspired by commit e850ed82bc ("ARM: OMAP4+: Allow
arch specific code to use early DM")
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Somehow an int returning function without a return statement sneaked
in, fix it.
Also fix some whitespace damage on the way.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
s25fs512s and s25fl512s_256k have common id information
till 5 bytes and 6th byte have different family id
like FS and FL-S as 0x81 and 0x80.
Reported-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Jagan Teki <jagan@openedev.com>
- fix single line comments
- remove unneeded spaces
- ascending order of include files
- rename SPI DATAFLASH to dataflash
- rename SPI DataFlash to dataflash
- return NULL replaced with error code
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: York Sun <york.sun@nxp.com>
Signed-off-by: Jagan Teki <jagan@openedev.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Flash id detection should be the first step to enumerate
the connected flash on the board, once ie done checking
with respective id codes locally in the driver all this
should be part of jedec_probe instead of id detection and
validated through flash_info{} table separatly.
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: York Sun <york.sun@nxp.com>
Signed-off-by: Jagan Teki <jagan@openedev.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Dual flash code in spi are usually take the spi controller
to work with dual connected flash devices. Usually these
dual connection operation's are referred to flash controller
protocol rather with spi controller protocol, these are still
present in flash side for the usage of spi-nor controllers.
So, this patch remove the dual_flash options or flags in sf
which are triggered from spi controller side.
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Vignesh R <vigneshr@ti.com>
Cc: Mugunthan V N <mugunthanvnm@ti.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Jagan Teki <jagan@openedev.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
In spansion S25FS-S family the physical sectors are grouped as
normal and parameter sectors. Parameter sectors are 4kB in size
with 8 set located at the bottom or top address of a device.
Normal sectors are similar to other flash family with sizes of
64kB or 32 kB.
To erase whole flash using sector erase(D8h or DCh) won't effect
the parameter sectors, so in order to erase these we must use 4K
sector erase commands (20h or 21h) separately.
So better to erase the whole flash using 4K sector erase instead
of detecting these family parts again and do two different erase
operations.
For this:
- Removed spansion_s25fss_disable_4KB_erase code
- Add SECT_4K for S25FS512S chip
Cc: Yunhui Cui <yunhui.cui@nxp.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Vignesh R <vigneshr@ti.com>
Cc: Mugunthan V N <mugunthanvnm@ti.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Jagan Teki <jagan@openedev.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@openedev.com>
Add Spansion S25FS256S_64K spi flash to the list of spi_flash_ids.
In spansion S25FS-S family the physical sectors are grouped as
normal and parameter sectors. Parameter sectors are 4kB in size
with 8 set located at the bottom or top address of a device.
Normal sectors are similar to other flash family with sizes of
64kB or 32 kB.
To erase whole flash using sector erase(D8h or DCh) won't effect
the parameter sectors, so in order to erase these we must use 4K
sector erase commands (20h or 21h) separately.
So better to erase the whole flash using 4K sector erase instead
of detecting these family parts again and do two different erase
operations.
Cc: Yunhui Cui <yunhui.cui@nxp.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Vignesh R <vigneshr@ti.com>
Cc: Mugunthan V N <mugunthanvnm@ti.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Jagan Teki <jagan@openedev.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Set the appropriate bits in the interface config register based
on the SPI_ mode flags.
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Patch queue for efi - 2016-11-17
Highlights this time around:
- x86 efi_loader support
- hello world efi test case
- network device name is now representative
- terminal output reports modes correctly
- fix psci reset for ls1043/ls1046
- fix efi_add_runtime_mmio definition for x86
- efi_loader support for ls2080
Most new systems in U-Boot these days make use of the generic "distro"
framework which allows a user to have U-Boot scan for a bootable OS
on all available media types.
This patch extends the LS2080ARDB board to use that framework if the
hard coded NOR flash location does not contain a bootable image.
Signed-off-by: Alexander Graf <agraf@suse.de>
When implementing efi loader support, we can expose runtime services
for payloads. One such service is CPU reset.
This patch implements RTS CPU reset support for layerscape systems.
Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: York Sun <york.sun@nxp.com>
The efi loader code has its own memory map, so it needs to be aware where
the spin tables are located, to ensure that no code writes into those
regions.
Signed-off-by: Alexander Graf <agraf@suse.de>
The DP-DDR shouldn't be exposed as conventional memory to an OS, so let's
rather claim it's a reserved region in the EFI memory map
Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: York Sun <york.sun@nxp.com>
On ls2080 we have a separate network fabric component which we need to
shut down before we enter Linux (or any other OS). Along with that also
comes configuration of the fabric using a description file.
Today we always stop and configure the fabric in the boot script and
(again) exit it on device tree generation. This works ok for the normal
booti case, but with bootefi the payload we're running may still want to
access the network.
So let's add a new fsl_mc command that defers configuration and stopping
the hardware to when we actually exit U-Boot, so that we can still use
the fabric from an EFI payload.
For existing boot scripts, nothing should change with this patch.
Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: York Sun <york.sun@nxp.com>
[agraf: Fix x86 build]
The efi_add_runtime_mmio prototype for disabled CONFIG_EFI_LOADER
was different from the enabled one. Sync them.
Signed-off-by: Alexander Graf <agraf@suse.de>
The NXP ls1043 and ls1046 systems do not (yet) have PSCI enablement
for reset. Don't enable generic PSCI reset code on them.
Signed-off-by: Alexander Graf <agraf@suse.de>
Some boards decided not to run ATF or other secure firmware in EL3, so
they instead run U-Boot there. The uEFI spec doesn't know what EL3 is
though - it only knows about EL2 and EL1. So if we see that we're running
in EL3, let's get into EL2 to make payloads happy.
Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: York Sun <york.sun@nxp.com>
Hardware revision "e" of the board introduces
a GPIO to reduce power consumption in stand-by mode.
This must be enable (active low) at the startup
for normal behaviour.
Signed-off-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Heiko Schocher <hs@denx.de>
Drop local function to setup SDRAM controller
and use the common one for i.MX35.
Signed-off-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Heiko Schocher <hs@denx.de>
According to design team, we need to set REFTOP_VBGADJ
in PMU MISC0 according to the REFTOP_TRIM[2:0] fuse. the
actually table is as below:
'000" - set REFTOP_VBGADJ[2:0] to 3'b000
'001" - set REFTOP_VBGADJ[2:0] to 3'b001
'010" - set REFTOP_VBGADJ[2:0] to 3'b010
'011" - set REFTOP_VBGADJ[2:0] to 3'b011
'100" - set REFTOP_VBGADJ[2:0] to 3'b100
'101" - set REFTOP_VBGADJ[2:0] to 3'b101
'110" - set REFTOP_VBGADJ[2:0] to 3'b110
'111" - set REFTOP_VBGADJ[2:0] to 3'b111
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Need to gate ENET clock when switching to a new clock parent, because
the mux is not glitchless.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye.Li <ye.li@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Some eMMC will fail at the first switch, but would succeed in a subsequent
one.
Make sure we try several times to cover those cases. The number of retries
(and the behaviour) is currently what is being used in Linux.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Adding prefetchable memory space to pcie device tree node.
Shifting configuration space to 64-bit address space.
Removing pcie device tree node from amba as it requires size-cells=<2>
in order to access 64-bit address space.
Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Zynqmp DMA driver expects two clocks (main clock and apb clock)
For LPDDMA channels the two clocks are missing in the
Dma node resulting probe failure.
xilinx-zynqmp-dma ffa80000.dma: main clock not found.
xilinx-zynqmp-dma ffa80000.dma: Probing channel failed
xilinx-zynqmp-dma: probe of ffa80000.dma failed with error -2
This patch fixes this issue.
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
LPDDMA default allows only secured access.
inorder to enable these dma channels,
one should ensure that it allows non secure access.
This patch updates the same.
Reported-by: Sai Pavan Boddu <saipava@xilinx.com>
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Use 64bit size cell for main amba bus instead of 32bit because PCIe
node requires it Change 64bit sizes also for all others IPs.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This reverts commit bd750e7a6c
Implemented the new workaround for auto tuning based on
zynqmp compatible string, so removed the 'broken-tuning'
property.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch changes the compatible string for sdhci node,
adds "xlnx,device_id" and "xlnx,mio_bank" property to sdhci node.
Signed-off-by: Sai Krishna Potthuri <lakshmis@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch adds edac node for arm cortexa53 to report
errors on L1 and L2 caches.
Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This reverts commit 786db82bd5.
Since we are using serdes driver , no need of mapping serdes register
space into DP driver.
Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Tested-by: Hyun Kwon <hyunk@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Each plane can be associated with multiple DMA channels. So add
index for each DMA channel.
Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Updating required device tree changes as per mainlined driver
from 4.6 kernel.
Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Previously, it was assumed that there is a 1:1 mapping between
PM ID defined in the platform firmware and a PM domain. However, there
can be a situation where multiple PM IDs belong to a single PM domain
(e.g. PM IDs for GPU and two pixel processors correspond to a single
PM domain).
This patch adds support for assigning more than one PM ID to
a single PM domain.
Updated documentation accordingly.
Assigned pixel processors PM IDs to GPU PM domain.
Signed-off-by: Filip Drazic <filip.drazic@aggios.com>
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
DDR power states are handled by the PM firmware, so this domain is
redundant. Also, since there is no device using this PM domain,
it will be powered off during boot, which is wrong.
Signed-off-by: Filip Drazic <filip.drazic@aggios.com>
Acked-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add dcc to dtsi for supporting system without serial port.
DCC is enabled by default on ZynqMP.
Adding dcc to zcu100 and zcu102 which were tested.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Zynqmp DMA driver expects two clocks (main clock and apb clock)
LPDDMA clock cofiguration is missing for the same in the
zynqmp-clk.dtsi file.
This patch updates for the same.
Reported-by: Sai Pavan Boddu <saipava@xilinx.com>
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
DTC 1.4.2 reports these warnings:
Warning (unit_address_vs_reg): Node /amba_apu has a reg or ranges
property, but no unit name
Warning (unit_address_vs_reg): Node /amba has a reg or ranges property,
but no unit name
Warning (unit_address_vs_reg): Node /amba/usb@fe200000 has a unit name,
but no reg property
Warning (unit_address_vs_reg): Node /amba/usb@fe300000 has a unit name,
but no reg property
Warning (unit_address_vs_reg): Node
/amba/dma@fd4c0000/dma-video0channel@fd4c0000 has a unit name, but no
reg property
Warning (unit_address_vs_reg): Node
/amba/dma@fd4c0000/dma-video1channel@fd4c0000 has a unit name, but no
reg property
Warning (unit_address_vs_reg): Node
/amba/dma@fd4c0000/dma-video2channel@fd4c0000 has a unit name, but no
reg property
Warning (unit_address_vs_reg): Node
/amba/dma@fd4c0000/dma-graphicschannel@fd4c0000 has a unit name, but no
reg property
Warning (unit_address_vs_reg): Node
/amba/dma@fd4c0000/dma-audio0channel@fd4c0000 has a unit name, but no
reg property
Warning (unit_address_vs_reg): Node
/amba/dma@fd4c0000/dma-audio1channel@fd4c0000 has a unit name, but no
reg property
Warning (unit_address_vs_reg): Node /memory has a reg or ranges
property, but no unit name
This patch is fixing them.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
DTC 1.4.2 reports these warnings:
Warning (unit_address_vs_reg): Node /memory has a reg or ranges
property, but no unit name
Warning (unit_address_vs_reg): Node /pmu has a reg or ranges property,
but no unit name
Warning (unit_address_vs_reg): Node /fixedregulator@0 has a unit name,
but no reg property
This patch is fixing them.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Correct the sdhci minimum frequency for ep platform.
It should be right shift instead of left shift operand.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Autogenerated files contain casting issues and missing function
declaration and even usleep implementation. Suppress them for now
till these files are fixed.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Do not setup use_alt bit which copy alternative boot mode to
boot mode. The reason is that this bit is cleared after POR
but not after any software reset which will cause
that after SW reset bootrom will look for different boot image.
This patch setups alternative boot mode selection (purely SW
handling) and extends code to read this alternative boot mode first and
use it if it is setup.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add support for SD1 with level shifters bootmode.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Zynq 7000S (Single A9 core) devices is using different ID code.
This patch adds this new codes and assign them.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Clear ecc ON bit while sending read command as all types
of read command(like reading spare) doesnt need ECC to be
enabled. It has been anyway taken care in other places
whereever required using arasan_nand_enable_ecc().
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch adds support to check the buswidth on nand flash
at runtime based on nand MIO configurations done by FSBL.
User needs to correctly configure the MIO's based on the
buswidth supported by the nand flash which is present on the board.
Added nand8 and nand16 @periph names on slcr driver.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The topic-miami SoMs contain a Zynq xc7z015 or xc7z030 SoC, 1GB DDR3L RAM,
32MB QSPI NOR flash and 256MB NAND flash.
The topic-miamiplus SoMs contain a Zynq xc7z035, xc7z045 or xc7z100 SoC,
2x 1GB DDR3L RAM, 64MB dual-parallel QSPI flash, clock sources
and a fan controller.
The "Florida" carrier boards add SD, USB, ethernet and other interfaces.
Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add a string description for SYS_VENDOR to allow configuring boards from
other vendors than just "xilinx".
Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Current Makefile.spl passes -R parameter which is not empty
and pointing to ./ folder.
"./tools/mkimage -T zynqmpimage -R ./"" -d spl/u-boot-spl.bin
spl/boot.bin"
That's why mkimage is trying to parse ./ file and generate
register init which is wrong.
Check that passed filename is regular file. If not do not work with it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The Zynq/ZynqMP boot.bin file contains a region for register initialization
data. Filling in proper values in this table can reduce boot time
(e.g. about 50ms faster on QSPI boot) and also reduce the size of
the SPL binary.
The table is a simple text file with register+data on each line. Other
lines are simply skipped. The file can be passed to mkimage using the
"-R" parameter.
It is recommended to add reg init file to board folder.
For example:
CONFIG_BOOT_INIT_FILE="board/xilinx/zynqmp/xilinx_zynqmp_zcu102/reg.int
Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Enable this so that EFI applications (notably grub) can be run under U-Boot
on x86 platforms.
At present the 'hello world' EFI application is not supported for the
qemu-x86_efi_payload64 board. That board builds a payload consisting of a
64-bit header and a 32-bit U-Boot, which is incompatible with the way the
EFI loader builds its EFI application. The following error is obtained:
x86_64-linux-ld.bfd: i386 architecture of input file
`lib/efi_loader/helloworld.o' is incompatible with i386:x86-64 output
This could be corrected with additional Makefile rules. For now, this
feature is disabled for that board.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[agraf: drop hello kconfig bits]
Signed-off-by: Alexander Graf <agraf@suse.de>
Add compiler flags and make a few minor adjustments to support the efi
loader.
Signed-off-by: Simon Glass <sjg@chromium.org>
[agraf: Add Kconfig dep]
Signed-off-by: Alexander Graf <agraf@suse.de>
These files now need to be in a standard place so that they can be located
by generic Makefile rules. Move them to the 'lib' directory.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
These files now need to be in a standard place so that they can be located
by generic Makefile rules. Move them to the 'lib' directory.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
Add support for EFI apps on aarch64. This includes start-up and relocation
code plus a link script.
Signed-off-by: Simon Glass <sjg@chromium.org>
[agraf: add kconfig dep]
Signed-off-by: Alexander Graf <agraf@suse.de>
Add support for EFI apps on ARM. This includes start-up and relocation
code, plus a link script and some compiler setting changes.
Signed-off-by: Simon Glass <sjg@chromium.org>
[agraf: Remove whitespace change, add kconfig dep]
Signed-off-by: Alexander Graf <agraf@suse.de>
Rather than hard-coding the relocation type, add it to the ELF header file
and use it from there.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
It is useful to have a basic sanity check for EFI loader support. Add a
'bootefi hello' command which loads HelloWord.efi and runs it under U-Boot.
Signed-off-by: Simon Glass <sjg@chromium.org>
[agraf: Fix documentation, add unfulfilled kconfig dep]
Signed-off-by: Alexander Graf <agraf@suse.de>
When building an EFI app we need three things:
- start-up code
- relocation code
- link script
These are all different for each architecture. We also need special
compiler flags in some cases.
Add top-level Makefile variables for these along with documentation.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
At present we use a CONFIG option in efi.h to determine whether we are
building the EFI stub or not. This means that the same header cannot be
used for EFI_LOADER support. The CONFIG option will be enabled for the
whole build, even when not building the stub.
Use a different define instead, set up just for the files that make up the
stub.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
This should use U-Boot's standard format for hex address. Fix it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
Make sure that the cache flushes correctly by ensuring that the end
address is correctly aligned.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
There is a build warning for three x86 boards since
write_smbios_table_wrapper() is not used. Fix it.
Fixes: e824cf3f (smbios: Allow compilation on 64bit systems)
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
Add support for EFI console modes.
Mode 0 is always 80x25 and present by EFI specification.
Mode 1 is always 80x50 and not mandatory.
Mode 2 and above is freely usable.
If the terminal can handle mode 1, we mark it as supported.
If the terminal size is greater than mode 0 and different than mode 1,
we install it as mode 2.
Modes can be switch with cout_set_mode.
Changes in V5:
Correctly detect mode before enabling mode 2.
Changes in V4:
Reset cursor positon on mode switch
Use local variables in console query code
Changes in V3:
Valid mode are 0 to EFIMode-1
Fix style
Changes in V2:
Add mode switch
Report only the modes that we support
Signed-off-by: Emmanuel Vadot <manu@bidouilliste.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
When adding network interface node use Messaging device path with
subtype MAC Address and device's MAC address as a value instead
of Media Device path type with subtype File Path and path "Net"
Signed-off-by: Oleksandr Tymoshenko <gonzo@bluezbox.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
This line is shown as
depends on (ARM64 ||\302\240ARM) && OF_LIBFDT
on my Emacs. Use ASCII characters only.
Assuming it is (ARM64 || ARM), remove the redundancy.
Unlike Linux, CONFIG_ARM includes CONFIG_ARM64 in U-Boot.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2016-11-14 23:24:02 +01:00
2293 changed files with 57292 additions and 17581 deletions
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