Prepare v2016.09.01

Signed-off-by: Tom Rini <trini@konsulko.com>

.travis.yml

@@ -3,15 +3,12 @@
 
 # build U-Boot on Travis CI - https://travis-ci.org/
 
-sudo: required
-dist: trusty
+sudo: true
 
 language: c
 
 addons:
   apt:
-    sources:
-    - sourceline: 'ppa:gns3/qemu'
     packages:
     - cppcheck
     - sloccount
@@ -21,26 +18,27 @@ addons:
     - libsdl1.2-dev
     - python
     - python-virtualenv
-    - qemu-system-arm
-    - qemu-system-mips
-    - qemu-system-ppc
-    - qemu-system-x86
-    - gcc-powerpc-linux-gnu
-    - gcc-arm-linux-gnueabihf
-    - gcc-aarch64-linux-gnu
-    - iasl
+
+cache:
+ - apt
 
 install:
  # install latest device tree compiler
- - git clone --depth=1 git://git.kernel.org/pub/scm/utils/dtc/dtc.git /tmp/dtc
+ - git clone --depth=1 https://git.kernel.org/pub/scm/utils/dtc/dtc.git /tmp/dtc
  - make -j4 -C /tmp/dtc
- # Clone uboot-test-hooks
- - git clone --depth=1 git://github.com/swarren/uboot-test-hooks.git /tmp/uboot-test-hooks
- - ln -s travis-ci /tmp/uboot-test-hooks/bin/`hostname`
- - ln -s travis-ci /tmp/uboot-test-hooks/py/`hostname`
  # prepare buildman environment
- - echo -e "[toolchain]\nroot = /usr" > ~/.buildman
- - echo -e "\n[toolchain-alias]\nblackfin = bfin\nsh = sh4\nopenrisc = or32" >> ~/.buildman
+ - export BUILDMAN_ROOT="root:"
+ - export BUILDMAN_PPC="ppc:"
+ - export BUILDMAN_ARM="arm:"
+ - export BUILDMAN_SANDBOX="sandbox:"
+ - echo -e "[toolchain]\n${BUILDMAN_ROOT} /\n" > ~/.buildman
+ - echo -e "${BUILDMAN_PPC} /opt/eldk-5.4/powerpc/sysroots/i686-eldk-linux/usr/bin/powerpc-linux/\n" >> ~/.buildman
+ - echo -e "${BUILDMAN_ARM} /opt/eldk-5.4/armv5te/sysroots/i686-eldk-linux/usr/bin/armv5te-linux-gnueabi/\n" >> ~/.buildman
+ - echo -e "${BUILDMAN_SANDBOX} /usr/bin/gcc\n" >> ~/.buildman
+ - export BUILDMAN_ALIAS="x86:"
+ - export BUILDMAN_ALIAS_ARM="arm:"
+ - echo -e "\n\n[toolchain-alias]\n${BUILDMAN_ALIAS} i386\n" >> ~/.buildman
+ - echo -e "${BUILDMAN_ALIAS_ARM} armv5te\n" >> ~/.buildman
  - cat ~/.buildman
  - virtualenv /tmp/venv
  - . /tmp/venv/bin/activate
@@ -48,48 +46,30 @@ install:
 
 env:
   global:
-    - PATH=/tmp/dtc:/tmp/uboot-test-hooks/bin:$PATH
+    - PATH=/tmp/dtc:$PATH
     - BUILD_DIR=build
     - HOSTCC="cc"
     - HOSTCXX="c++"
 
 before_script:
   # install toolchains based on TOOLCHAIN} variable
+  - if [[ "${TOOLCHAIN}" == *aarch64* ]]; then ./tools/buildman/buildman --fetch-arch aarch64 ; fi
+  - if [[ "${TOOLCHAIN}" == *arm* ]]; then wget ftp://ftp.denx.de/pub/eldk/5.4/targets/armv5te/eldk-eglibc-i686-arm-toolchain-gmae-5.4.sh ; fi
+  - if [[ "${TOOLCHAIN}" == *arm* ]]; then sh eldk-eglibc-i686-arm-toolchain-gmae-5.4.sh -y ; fi
   - if [[ "${TOOLCHAIN}" == *avr32* ]]; then ./tools/buildman/buildman --fetch-arch avr32 ; fi
-  - if [[ "${TOOLCHAIN}" == *bfin* ]]; then ./tools/buildman/buildman --fetch-arch bfin ; fi
+  - if [[ "${TOOLCHAIN}" == *i386* ]]; then ./tools/buildman/buildman sandbox --fetch-arch i386 ; fi
   - if [[ "${TOOLCHAIN}" == *m68k* ]]; then ./tools/buildman/buildman --fetch-arch m68k ; fi
-  - if [[ "${TOOLCHAIN}" == *microblaze* ]]; then ./tools/buildman/buildman --fetch-arch microblaze ; fi
   - if [[ "${TOOLCHAIN}" == *mips* ]]; then ./tools/buildman/buildman --fetch-arch mips ; fi
-  - if [[ "${TOOLCHAIN}" == *or32* ]]; then ./tools/buildman/buildman --fetch-arch or32 ; fi
-  - if [[ "${TOOLCHAIN}" == *sh4* ]]; then ./tools/buildman/buildman --fetch-arch sh4 ; fi
-  - if [[ "${TOOLCHAIN}" == *x86_64* ]]; then
-      ./tools/buildman/buildman --fetch-arch x86_64;
-      echo -e "\n[toolchain-prefix]\nx86 = ${HOME}/.buildman-toolchains/gcc-4.9.0-nolibc/x86_64-linux/bin/x86_64-linux-" >> ~/.buildman;
-    fi
-  - if [[ "${TOOLCHAIN}" == *xtensa* ]]; then ./tools/buildman/buildman --fetch-arch xtensa ; fi
+  - if [[ "${TOOLCHAIN}" == *ppc* ]]; then wget ftp://ftp.denx.de/pub/eldk/5.4/targets/powerpc/eldk-eglibc-i686-powerpc-toolchain-gmae-5.4.sh ; fi
+  - if [[ "${TOOLCHAIN}" == *ppc* ]]; then sh eldk-eglibc-i686-powerpc-toolchain-gmae-5.4.sh -y ; fi
 
 script:
- # Comments must be outside the command strings below, or the Travis parser
- # will get confused.
- #
- # Exit code 129 means warnings only.
- - if [[ "${BUILDMAN}" != "" ]]; then
-     set +e;
-     tools/buildman/buildman -P ${BUILDMAN};
-     ret=$?;
-     if [[ $ret -ne 0 && $ret -ne 129 ]]; then
-       tools/buildman/buildman -sdeP ${BUILDMAN};
-       exit $ret;
-     fi;
+ # the execution sequence for each test
+ - if [[ "${TEST_CMD}" != "" ]]; then
+     ${TEST_CMD};
    fi
- # "not a_test_which_does_not_exist" is a dummy -k parameter which will
- # never prevent any test from running. That way, we can always pass
- # "-k something" even when $TEST_PY_TEST_SPEC doesnt need a custom
- # value.
- - if [[ "${TEST_PY_BD}" != "" ]]; then
-     ./test/py/test.py --bd ${TEST_PY_BD} ${TEST_PY_ID}
-       -k "${TEST_PY_TEST_SPEC:-not a_test_which_does_not_exist}"
-       --build-dir `cd .. && pwd`/.bm-work/${TEST_PY_BD};
+ - if [[ "${BUILDMAN}" != "" ]]; then
+     tools/buildman/buildman ${BUILDMAN};
    fi
 
 matrix:
@@ -97,182 +77,113 @@ matrix:
   # we need to build by vendor due to 50min time limit for builds
   # each env setting here is a dedicated build
     - env:
-        - BUILDMAN="arm11"
+        - BUILDMAN="arm1136"
+          TOOLCHAIN="arm"
     - env:
-        - BUILDMAN="arm7"
+        - BUILDMAN="arm1136"
+          TOOLCHAIN="arm"
+    - env:
+        - BUILDMAN="arm1176"
+          TOOLCHAIN="arm"
+    - env:
+        - BUILDMAN="arm720t"
+          TOOLCHAIN="arm"
     - env:
         - BUILDMAN="arm920t"
-    - env:
-        - JOB="arm926ejs"
-          BUILDMAN="arm926ejs -x mx,siemens,atmel"
-    - env:
-        - BUILDMAN="arm946es"
+          TOOLCHAIN="arm"
     - env:
         - BUILDMAN="atmel -x avr32"
+          TOOLCHAIN="arm"
     - env:
         - BUILDMAN="avr32"
           TOOLCHAIN="avr32"
+    - env:
+        - BUILDMAN="davinci"
+          TOOLCHAIN="arm"
     - env:
         - BUILDMAN="denx"
+          TOOLCHAIN="arm"
     - env:
-        - JOB="Freescale ARM"
-          BUILDMAN="freescale -x powerpc,m68k"
-    - env:
-        - JOB="i.MX (non-Freescale)"
-          BUILDMAN="mx -x freescale"
-    - env:
-        - BUILDMAN="sun4i"
-    - env:
-        - BUILDMAN="sun5i"
-    - env:
-        - BUILDMAN="sun6i"
-    - env:
-        - BUILDMAN="sun7i"
-    - env:
-        - BUILDMAN="sun8i"
-    - env:
-        - BUILDMAN="sun9i"
-    - env:
-        - BUILDMAN="sun50i"
-    - env:
-        - JOB="Catch-all ARM"
-          BUILDMAN="arm -x arm11,arm7,arm9,aarch64,atmel,denx,freescale,kirkwood,siemens,tegra,uniphier,mx,sunxi,am33xx,omap3,omap4,omap5,pxa"
+        - BUILDMAN="freescale -x powerpc,m68k,aarch64"
+          TOOLCHAIN="arm"
     - env:
         - BUILDMAN="sandbox x86"
-          TOOLCHAIN="x86_64"
+          TOOLCHAIN="i386"
     - env:
         - BUILDMAN="kirkwood"
-    - env:
-        - BUILDMAN="pxa"
+          TOOLCHAIN="arm"
     - env:
         - BUILDMAN="m68k"
           TOOLCHAIN="m68k"
-    - env:
-        - BUILDMAN="microblaze"
-          TOOLCHAIN="microblaze"
     - env:
         - BUILDMAN="mips"
           TOOLCHAIN="mips"
     - env:
         - BUILDMAN="mpc512x"
+          TOOLCHAIN="ppc"
     - env:
         - BUILDMAN="mpc5xx"
+          TOOLCHAIN="ppc"
     - env:
         - BUILDMAN="mpc5xxx"
+          TOOLCHAIN="ppc"
     - env:
         - BUILDMAN="mpc8260"
+          TOOLCHAIN="ppc"
     - env:
         - BUILDMAN="mpc83xx"
+          TOOLCHAIN="ppc"
     - env:
         - BUILDMAN="mpc85xx -x freescale"
+          TOOLCHAIN="ppc"
     - env:
         - BUILDMAN="mpc85xx -x t208xrdb -x t4qds -x t102* -x p1_p2_rdb_pc -x p1010rdb -x corenet_ds -x b4860qds -x sbc8548 -x bsc91*"
+          TOOLCHAIN="ppc"
     - env:
         - BUILDMAN="t208xrdb t4qds t102*"
+          TOOLCHAIN="ppc"
     - env:
         - BUILDMAN="p1_p2_rdb_pc p1010rdb"
+          TOOLCHAIN="ppc"
     - env:
         - BUILDMAN="corenet_ds b4860qds sbc8548 bsc91*"
+          TOOLCHAIN="ppc"
     - env:
         - BUILDMAN="mpc86xx"
+          TOOLCHAIN="ppc"
     - env:
         - BUILDMAN="mpc8xx"
+          TOOLCHAIN="ppc"
     - env:
         - BUILDMAN="siemens"
+          TOOLCHAIN="arm"
     - env:
-        - BUILDMAN="tegra"
+        - BUILDMAN="ti"
+          TOOLCHAIN="arm"
     - env:
-        - JOB="am33xx"
-          BUILDMAN="am33xx -x siemens"
-    - env:
-        - BUILDMAN="omap3"
-    - env:
-        - BUILDMAN="omap4"
-    - env:
-        - BUILDMAN="omap5"
-    - env:
-        - BUILDMAN="uniphier"
-    - env:
-        - BUILDMAN="aarch64 -x tegra,freescale,uniphier,sunxi"
+        - BUILDMAN="aarch64"
           TOOLCHAIN="aarch64"
-    - env:
-        - BUILDMAN="sh4"
-          TOOLCHAIN="sh4"
-    - env:
-        - BUILDMAN="xtensa"
-          TOOLCHAIN="xtensa"
 
     # QA jobs for code analytics
     # static code analysis with cppcheck (we can add --enable=all later)
     - env:
-        - JOB="cppcheck"
-      script:
-        - cppcheck --force --quiet --inline-suppr .
+        - TEST_CMD="cppcheck --force --quiet --inline-suppr ."
     # search for TODO within source tree
     - env:
-        - JOB="grep TODO"
-      script:
-        - grep -r TODO .
+        - TEST_CMD="grep -r TODO ."
     # search for FIXME within source tree
     - env:
-        - JOB="grep FIXME HACK"
-      script:
-        - grep -r FIXME .
+        - TEST_CMD="grep -r FIXME ."
     # search for HACK within source tree and ignore HACKKIT board
+    - env:
+        - TEST_CMD="grep -r HACK . | grep -v HACKKIT"
       script:
         - grep -r HACK . | grep -v HACKKIT
     # some statistics about the code base
     - env:
-        - JOB="sloccount"
-      script:
-        - sloccount .
-
+        - TEST_CMD="sloccount ."
     # test/py
     - env:
-        - TEST_PY_BD="sandbox"
-          BUILDMAN="^sandbox$"
-          TOOLCHAIN="x86_64"
-    - env:
-        - TEST_PY_BD="vexpress_ca15_tc2"
-          TEST_PY_ID="--id qemu"
-          BUILDMAN="^vexpress_ca15_tc2$"
-    - env:
-        - TEST_PY_BD="vexpress_ca9x4"
-          TEST_PY_ID="--id qemu"
-          BUILDMAN="^vexpress_ca9x4$"
-    - env:
-        - TEST_PY_BD="integratorcp_cm926ejs"
-          TEST_PY_ID="--id qemu"
-          BUILDMAN="^integratorcp_cm926ejs$"
-    - env:
-        - TEST_PY_BD="qemu_mips"
-          TEST_PY_TEST_SPEC="not sleep"
-          BUILDMAN="^qemu_mips$"
-          TOOLCHAIN="mips"
-    - env:
-        - TEST_PY_BD="qemu_mipsel"
-          TEST_PY_TEST_SPEC="not sleep"
-          BUILDMAN="^qemu_mipsel$"
-          TOOLCHAIN="mips"
-    - env:
-        - TEST_PY_BD="qemu_mips64"
-          TEST_PY_TEST_SPEC="not sleep"
-          BUILDMAN="^qemu_mips64$"
-          TOOLCHAIN="mips"
-    - env:
-        - TEST_PY_BD="qemu_mips64el"
-          TEST_PY_TEST_SPEC="not sleep"
-          BUILDMAN="^qemu_mips64el$"
-          TOOLCHAIN="mips"
-    - env:
-        - TEST_PY_BD="qemu-ppce500"
-          TEST_PY_TEST_SPEC="not sleep"
-          BUILDMAN="^qemu-ppce500$"
-    - env:
-        - TEST_PY_BD="qemu-x86"
-          TEST_PY_TEST_SPEC="not sleep"
-          BUILDMAN="^qemu-x86$"
-          TOOLCHAIN="x86_64"
-          BUILD_ROM="yes"
+        - TEST_CMD="./test/py/test.py --bd sandbox --build"
 
 # TODO make it perfect ;-r

Kconfig

@@ -137,6 +137,74 @@ endmenu		# General setup
 
 menu "Boot images"
 
+config SUPPORT_SPL
+	bool
+
+config SUPPORT_TPL
+	bool
+
+config SPL
+	bool
+	depends on SUPPORT_SPL
+	prompt "Enable SPL"
+	help
+	  If you want to build SPL as well as the normal image, say Y.
+
+config SPL_SYS_MALLOC_SIMPLE
+	bool
+	depends on SPL
+	prompt "Only use malloc_simple functions in the SPL"
+	help
+	  Say Y here to only use the *_simple malloc functions from
+	  malloc_simple.c, rather then using the versions from dlmalloc.c;
+	  this will make the SPL binary smaller at the cost of more heap
+	  usage as the *_simple malloc functions do not re-use free-ed mem.
+
+config SPL_STACK_R
+	depends on SPL
+	bool "Enable SDRAM location for SPL stack"
+	help
+	  SPL starts off execution in SRAM and thus typically has only a small
+	  stack available. Since SPL sets up DRAM while in its board_init_f()
+	  function, it is possible for the stack to move there before
+	  board_init_r() is reached. This option enables a special SDRAM
+	  location for the SPL stack. U-Boot SPL switches to this after
+	  board_init_f() completes, and before board_init_r() starts.
+
+config SPL_STACK_R_ADDR
+	depends on SPL_STACK_R
+	hex "SDRAM location for SPL stack"
+	help
+	  Specify the address in SDRAM for the SPL stack. This will be set up
+	  before board_init_r() is called.
+
+config SPL_STACK_R_MALLOC_SIMPLE_LEN
+	depends on SPL_STACK_R && SPL_SYS_MALLOC_SIMPLE
+	hex "Size of malloc_simple heap after switching to DRAM SPL stack"
+	default 0x100000
+	help
+	  Specify the amount of the stack to use as memory pool for
+	  malloc_simple after switching the stack to DRAM. This may be set
+	  to give board_init_r() a larger heap then the initial heap in
+	  SRAM which is limited to SYS_MALLOC_F_LEN bytes.
+
+config SPL_SEPARATE_BSS
+	depends on SPL
+	bool "BSS section is in a different memory region from text"
+	help
+	  Some platforms need a large BSS region in SPL and can provide this
+	  because RAM is already set up. In this case BSS can be moved to RAM.
+	  This option should then be enabled so that the correct device tree
+	  location is used. Normally we put the device tree at the end of BSS
+	  but with this option enabled, it goes at _image_binary_end.
+
+config TPL
+	bool
+	depends on SPL && SUPPORT_TPL
+	prompt "Enable TPL"
+	help
+	  If you want to build TPL as well as the normal image and SPL, say Y.
+
 config FIT
 	bool "Support Flattened Image Tree"
 	help
@@ -291,33 +359,6 @@ config FIT_IMAGE_POST_PROCESS
 	  injected into the FIT creation (i.e. the blobs would have been pre-
 	  processed before being added to the FIT image).
 
-config SPL_DFU_SUPPORT
-	bool "Enable SPL with DFU to load binaries to memory device"
-	depends on USB
-	help
-	  Currently the SPL does not have capability to load the
-	  binaries or boot images to boot devices like ram,eMMC,SPI,etc.
-	  This feature enables the DFU (Device Firmware Upgarde) in SPL with
-	  RAM memory device support. The ROM code will load and execute
-	  the SPL built with dfu. The user can load binaries (u-boot/kernel) to
-	  selected device partition from host-pc using dfu-utils.
-		This feature will be useful to flash the binaries to factory
-	  or bare-metal boards using USB interface.
-
-choice
-	bool "DFU device selection"
-	depends on SPL_DFU_SUPPORT
-
-config SPL_DFU_RAM
-	bool "RAM device"
-	depends on SPL_DFU_SUPPORT
-	help
-	 select RAM/DDR memory device for loading binary images
-	 (u-boot/kernel) to the selected device partition using
-	 DFU and execute the u-boot/kernel from RAM.
-
-endchoice
-
 config SYS_CLK_FREQ
 	depends on ARC || ARCH_SUNXI
 	int "CPU clock frequency"

MAINTAINERS

@@ -167,7 +167,9 @@ F:	arch/arm/cpu/armv7/stv0991/
 F:	arch/arm/include/asm/arch-stv0991/
 
 ARM SUNXI
-S:	Orphan
+M:	Ian Campbell <ijc@hellion.org.uk>
+M:	Hans De Goede <hdegoede@redhat.com>
+S:	Maintained
 T:	git git://git.denx.de/u-boot-sunxi.git
 F:	arch/arm/cpu/armv7/sunxi/
 F:	arch/arm/include/asm/arch-sunxi/
@@ -415,7 +417,7 @@ T:	git git://git.denx.de/u-boot-sparc.git
 F:	arch/sparc/
 
 SPI
-M:	Jagan Teki <jagan@openedev.com>
+M:	Jagan Teki <jteki@openedev.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-spi.git
 F:	drivers/mtd/spi/

Makefile

@@ -3,8 +3,8 @@
 #
 
 VERSION = 2016
-PATCHLEVEL = 11
-SUBLEVEL =
+PATCHLEVEL = 09
+SUBLEVEL = 01
 EXTRAVERSION =
 NAME =
 
@@ -655,7 +655,6 @@ libs-y += drivers/power/ \
 libs-y += drivers/spi/
 libs-$(CONFIG_FMAN_ENET) += drivers/net/fm/
 libs-$(CONFIG_SYS_FSL_DDR) += drivers/ddr/fsl/
-libs-$(CONFIG_SYS_FSL_MMDC) += drivers/ddr/fsl/
 libs-$(CONFIG_ALTERA_SDRAM) += drivers/ddr/altera/
 libs-y += drivers/serial/
 libs-y += drivers/usb/dwc3/
@@ -741,7 +740,7 @@ DO_STATIC_RELA =
 endif
 
 # Always append ALL so that arch config.mk's can add custom ones
-ALL-y += u-boot.srec u-boot.bin u-boot.sym System.map binary_size_check
+ALL-y += u-boot.srec u-boot.bin u-boot.sym System.map u-boot.cfg binary_size_check
 
 ALL-$(CONFIG_ONENAND_U_BOOT) += u-boot-onenand.bin
 ifeq ($(CONFIG_SPL_FSL_PBL),y)
@@ -820,11 +819,6 @@ ifeq ($(CONFIG_DM_I2C_COMPAT)$(CONFIG_SANDBOX),y)
 	@echo "before sending patches to the mailing list."
 	@echo "===================================================="
 endif
-	@# Check that this build does not use CONFIG options that we do not
-	@# know about unless they are in Kconfig. All the existing CONFIG
-	@# options are whitelisted, so new ones should not be added.
-	$(srctree)/scripts/check-config.sh u-boot.cfg \
-		$(srctree)/scripts/config_whitelist.txt ${srctree} 1>&2
 
 PHONY += dtbs
 dtbs: dts/dt.dtb
@@ -849,12 +843,6 @@ endif
 %.imx: %.bin
 	$(Q)$(MAKE) $(build)=arch/arm/imx-common $@
 
-%.vyb: %.imx
-	$(Q)$(MAKE) $(build)=arch/arm/cpu/armv7/vf610 $@
-
-quiet_cmd_copy = COPY    $@
-      cmd_copy = cp $< $@
-
 u-boot.dtb: dts/dt.dtb
 	$(call cmd,copy)
 
@@ -947,6 +935,9 @@ u-boot.sha1:	u-boot.bin
 u-boot.dis:	u-boot
 		$(OBJDUMP) -d $< > $@
 
+u-boot.cfg:	include/config.h FORCE
+	$(call if_changed,cpp_cfg)
+
 ifdef CONFIG_TPL
 SPL_PAYLOAD := tpl/u-boot-with-tpl.bin
 else
@@ -1096,7 +1087,7 @@ u-boot-x86-16bit.bin: u-boot FORCE
 	$(call if_changed,objcopy)
 endif
 
-ifneq ($(CONFIG_ARCH_SUNXI),)
+ifneq ($(CONFIG_SUNXI),)
 OBJCOPYFLAGS_u-boot-sunxi-with-spl.bin = -I binary -O binary \
 				   --pad-to=$(CONFIG_SPL_PAD_TO) --gap-fill=0xff
 u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin u-boot.img FORCE

README

@@ -127,7 +127,7 @@ releases in "stable" maintenance trees.
 Examples:
 	U-Boot v2009.11	    - Release November 2009
 	U-Boot v2009.11.1   - Release 1 in version November 2009 stable tree
-	U-Boot v2010.09-rc1 - Release candidate 1 for September 2010 release
+	U-Boot v2010.09-rc1 - Release candiate 1 for September 2010 release
 
 
 Directory Hierarchy:
@@ -325,6 +325,27 @@ The following options need to be configured:
 - CPU Daughterboard Type: (if CONFIG_ATSTK1000 is defined)
 		Define exactly one, e.g. CONFIG_ATSTK1002
 
+- CPU Module Type: (if CONFIG_COGENT is defined)
+		Define exactly one of
+		CONFIG_CMA286_60_OLD
+--- FIXME --- not tested yet:
+		CONFIG_CMA286_60, CONFIG_CMA286_21, CONFIG_CMA286_60P,
+		CONFIG_CMA287_23, CONFIG_CMA287_50
+
+- Motherboard Type: (if CONFIG_COGENT is defined)
+		Define exactly one of
+		CONFIG_CMA101, CONFIG_CMA102
+
+- Motherboard I/O Modules: (if CONFIG_COGENT is defined)
+		Define one or more of
+		CONFIG_CMA302
+
+- Motherboard Options: (if CONFIG_CMA101 or CONFIG_CMA102 are defined)
+		Define one or more of
+		CONFIG_LCD_HEARTBEAT	- update a character position on
+					  the LCD display every second with
+					  a "rotator" |\-/|\-/
+
 - Marvell Family Member
 		CONFIG_SYS_MVFS		- define it if you want to enable
 					  multiple fs option at one time
@@ -557,6 +578,20 @@ The following options need to be configured:
 		CONFIG_SYS_FSL_SEC_LE
 		Defines the SEC controller register space as Little Endian
 
+- Intel Monahans options:
+		CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO
+
+		Defines the Monahans run mode to oscillator
+		ratio. Valid values are 8, 16, 24, 31. The core
+		frequency is this value multiplied by 13 MHz.
+
+		CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO
+
+		Defines the Monahans turbo mode to oscillator
+		ratio. Valid values are 1 (default if undefined) and
+		2. The core frequency as calculated above is multiplied
+		by this value.
+
 - MIPS CPU options:
 		CONFIG_SYS_INIT_SP_OFFSET
 
@@ -695,6 +730,11 @@ The following options need to be configured:
 		This causes ft_system_setup() to be called before booting
 		the kernel.
 
+		CONFIG_OF_BOOT_CPU
+
+		This define fills in the correct boot CPU in the boot
+		param header, the default value is zero if undefined.
+
 		CONFIG_OF_IDE_FIXUP
 
 		U-Boot can detect if an IDE device is present or not.
@@ -770,6 +810,59 @@ The following options need to be configured:
 		port routines must be defined elsewhere
 		(i.e. serial_init(), serial_getc(), ...)
 
+		CONFIG_CFB_CONSOLE
+		Enables console device for a color framebuffer. Needs following
+		defines (cf. smiLynxEM, i8042)
+			VIDEO_FB_LITTLE_ENDIAN	graphic memory organisation
+						(default big endian)
+			VIDEO_HW_RECTFILL	graphic chip supports
+						rectangle fill
+						(cf. smiLynxEM)
+			VIDEO_HW_BITBLT		graphic chip supports
+						bit-blit (cf. smiLynxEM)
+			VIDEO_VISIBLE_COLS	visible pixel columns
+						(cols=pitch)
+			VIDEO_VISIBLE_ROWS	visible pixel rows
+			VIDEO_PIXEL_SIZE	bytes per pixel
+			VIDEO_DATA_FORMAT	graphic data format
+						(0-5, cf. cfb_console.c)
+			VIDEO_FB_ADRS		framebuffer address
+			VIDEO_KBD_INIT_FCT	keyboard int fct
+						(i.e. rx51_kp_init())
+			VIDEO_TSTC_FCT		test char fct
+						(i.e. rx51_kp_tstc)
+			VIDEO_GETC_FCT		get char fct
+						(i.e. rx51_kp_getc)
+			CONFIG_VIDEO_LOGO	display Linux logo in
+						upper left corner
+			CONFIG_VIDEO_BMP_LOGO	use bmp_logo.h instead of
+						linux_logo.h for logo.
+						Requires CONFIG_VIDEO_LOGO
+			CONFIG_CONSOLE_EXTRA_INFO
+						additional board info beside
+						the logo
+			CONFIG_HIDE_LOGO_VERSION
+						do not display bootloader
+						version string
+
+		When CONFIG_CFB_CONSOLE_ANSI is defined, console will support
+		a limited number of ANSI escape sequences (cursor control,
+		erase functions and limited graphics rendition control).
+
+		When CONFIG_CFB_CONSOLE is defined, video console is
+		default i/o. Serial console can be forced with
+		environment 'console=serial'.
+
+		When CONFIG_SILENT_CONSOLE is defined, all console
+		messages (by U-Boot and Linux!) can be silenced with
+		the "silent" environment variable. See
+		doc/README.silent for more information.
+
+		CONFIG_SYS_CONSOLE_BG_COL: define the backgroundcolor, default
+			is 0x00.
+		CONFIG_SYS_CONSOLE_FG_COL: define the foregroundcolor, default
+			is 0xa0.
+
 - Console Baudrate:
 		CONFIG_BAUDRATE - in bps
 		Select one of the baudrates listed in
@@ -784,6 +877,23 @@ The following options need to be configured:
 		must be defined, to setup the maximum idle timeout for
 		the SMC.
 
+- Pre-Console Buffer:
+		Prior to the console being initialised (i.e. serial UART
+		initialised etc) all console output is silently discarded.
+		Defining CONFIG_PRE_CONSOLE_BUFFER will cause U-Boot to
+		buffer any console messages prior to the console being
+		initialised to a buffer of size CONFIG_PRE_CON_BUF_SZ
+		bytes located at CONFIG_PRE_CON_BUF_ADDR. The buffer is
+		a circular buffer, so if more than CONFIG_PRE_CON_BUF_SZ
+		bytes are output before the console is initialised, the
+		earlier bytes are discarded.
+
+		Note that when printing the buffer a copy is made on the
+		stack so CONFIG_PRE_CON_BUF_SZ must fit on the stack.
+
+		'Sane' compilers will generate smaller code if
+		CONFIG_PRE_CON_BUF_SZ is a power of 2
+
 - Autoboot Command:
 		CONFIG_BOOTCOMMAND
 		Only needed when CONFIG_BOOTDELAY is enabled;
@@ -1227,6 +1337,10 @@ The following options need to be configured:
 		CONFIG_LAN91C96
 		Support for SMSC's LAN91C96 chips.
 
+			CONFIG_LAN91C96_BASE
+			Define this to hold the physical address
+			of the LAN91C96's I/O space
+
 			CONFIG_LAN91C96_USE_32_BIT
 			Define this to enable 32 bit addressing
 
@@ -1291,7 +1405,7 @@ The following options need to be configured:
 
 - PWM Support:
 		CONFIG_PWM_IMX
-		Support for PWM module on the imx6.
+		Support for PWM modul on the imx6.
 
 - TPM Support:
 		CONFIG_TPM
@@ -1411,6 +1525,10 @@ The following options need to be configured:
 				Derive USB clock from external clock "blah"
 				- CONFIG_SYS_USB_EXTC_CLK 0x02
 
+				CONFIG_SYS_USB_BRG_CLK 0xBLAH
+				Derive USB clock from brgclk
+				- CONFIG_SYS_USB_BRG_CLK 0x04
+
 		If you have a USB-IF assigned VendorID then you may wish to
 		define your own vendor specific values either in BoardName.h
 		or directly in usbd_vendor_info.h. If you don't define
@@ -1563,23 +1681,26 @@ The following options need to be configured:
 		to generate and write the Backup GUID Partition Table.)
 		This occurs when the specified "partition name" on the
 		"fastboot flash" command line matches this value.
-		The default is "gpt" if undefined.
-
-		CONFIG_FASTBOOT_MBR_NAME
-		The fastboot "flash" command supports writing the downloaded
-		image to DOS MBR.
-		This occurs when the "partition name" specified on the
-		"fastboot flash" command line matches this value.
-		If not defined the default value "mbr" is used.
+		Default is GPT_ENTRY_NAME (currently "gpt") if undefined.
 
 - Journaling Flash filesystem support:
-		CONFIG_JFFS2_NAND
+		CONFIG_JFFS2_NAND, CONFIG_JFFS2_NAND_OFF, CONFIG_JFFS2_NAND_SIZE,
+		CONFIG_JFFS2_NAND_DEV
 		Define these for a default partition on a NAND device
 
 		CONFIG_SYS_JFFS2_FIRST_SECTOR,
 		CONFIG_SYS_JFFS2_FIRST_BANK, CONFIG_SYS_JFFS2_NUM_BANKS
 		Define these for a default partition on a NOR device
 
+		CONFIG_SYS_JFFS_CUSTOM_PART
+		Define this to create an own partition. You have to provide a
+		function struct part_info* jffs2_part_info(int part_num)
+
+		If you define only one JFFS2 partition you may also want to
+		#define CONFIG_SYS_JFFS_SINGLE_PART	1
+		to disable the command chpart. This is the default when you
+		have not defined a custom partition
+
 - FAT(File Allocation Table) filesystem write function support:
 		CONFIG_FAT_WRITE
 
@@ -1589,7 +1710,7 @@ The following options need to be configured:
 		This will also enable the command "fatwrite" enabling the
 		user to write files to FAT.
 
-- CBFS (Coreboot Filesystem) support:
+CBFS (Coreboot Filesystem) support
 		CONFIG_CMD_CBFS
 
 		Define this to enable support for reading from a Coreboot
@@ -1614,6 +1735,45 @@ The following options need to be configured:
 		instead.
 
 - Video support:
+		CONFIG_VIDEO
+
+		Define this to enable video support (for output to
+		video).
+
+		CONFIG_VIDEO_CT69000
+
+		Enable Chips & Technologies 69000 Video chip
+
+		CONFIG_VIDEO_SMI_LYNXEM
+		Enable Silicon Motion SMI 712/710/810 Video chip. The
+		video output is selected via environment 'videoout'
+		(1 = LCD and 2 = CRT). If videoout is undefined, CRT is
+		assumed.
+
+		For the CT69000 and SMI_LYNXEM drivers, videomode is
+		selected via environment 'videomode'. Two different ways
+		are possible:
+		- "videomode=num"   'num' is a standard LiLo mode numbers.
+		Following standard modes are supported	(* is default):
+
+		      Colors	640x480 800x600 1024x768 1152x864 1280x1024
+		-------------+---------------------------------------------
+		      8 bits |	0x301*	0x303	 0x305	  0x161	    0x307
+		     15 bits |	0x310	0x313	 0x316	  0x162	    0x319
+		     16 bits |	0x311	0x314	 0x317	  0x163	    0x31A
+		     24 bits |	0x312	0x315	 0x318	    ?	    0x31B
+		-------------+---------------------------------------------
+		(i.e. setenv videomode 317; saveenv; reset;)
+
+		- "videomode=bootargs" all the video parameters are parsed
+		from the bootargs. (See drivers/video/videomodes.c)
+
+
+		CONFIG_VIDEO_SED13806
+		Enable Epson SED13806 driver. This driver supports 8bpp
+		and 16bpp modes defined by CONFIG_VIDEO_SED13806_8BPP
+		or CONFIG_VIDEO_SED13806_16BPP
+
 		CONFIG_FSL_DIU_FB
 		Enable the Freescale DIU video driver.	Reference boards for
 		SOCs that have a DIU should define this macro to enable DIU
@@ -1693,6 +1853,12 @@ The following options need to be configured:
 		here, since it is cheaper to change data cache settings on
 		a per-section basis.
 
+		CONFIG_CONSOLE_SCROLL_LINES
+
+		When the console need to be scrolled, this is the number of
+		lines to scroll by. It defaults to 1. Increasing this makes
+		the console jump but can help speed up operation when scrolling
+		is slow.
 
 		CONFIG_LCD_ROTATION
 
@@ -2165,6 +2331,8 @@ The following options need to be configured:
 		  - CONFIG_SYS_I2C_SH_SPEED3 for for the speed channel 3
 		  - CONFIG_SYS_I2C_SH_BASE4 for setting the register channel 4
 		  - CONFIG_SYS_I2C_SH_SPEED4 for for the speed channel 4
+		  - CONFIG_SYS_I2C_SH_BASE5 for setting the register channel 5
+		  - CONFIG_SYS_I2C_SH_SPEED5 for for the speed channel 5
 		  - CONFIG_SYS_I2C_SH_NUM_CONTROLLERS for number of i2c buses
 
 		- drivers/i2c/omap24xx_i2c.c
@@ -2218,7 +2386,10 @@ The following options need to be configured:
 		additional defines:
 
 		CONFIG_SYS_NUM_I2C_BUSES
-		Hold the number of i2c buses you want to use.
+		Hold the number of i2c buses you want to use. If you
+		don't use/have i2c muxes on your i2c bus, this
+		is equal to CONFIG_SYS_NUM_I2C_ADAPTERS, and you can
+		omit this define.
 
 		CONFIG_SYS_I2C_DIRECT_BUS
 		define this, if you don't use i2c muxes on your hardware.
@@ -2432,7 +2603,7 @@ The following options need to be configured:
 		will skip addresses 0x50 and 0x68 on a board with one I2C bus
 
 			#define CONFIG_I2C_MULTI_BUS
-			#define CONFIG_SYS_I2C_NOPROBES	{{0,0x50},{0,0x68},{1,0x54}}
+			#define CONFIG_SYS_I2C_MULTI_NOPROBES	{{0,0x50},{0,0x68},{1,0x54}}
 
 		will skip addresses 0x50 and 0x68 on bus 0 and address 0x54 on bus 1
 
@@ -3338,6 +3509,21 @@ FIT uImage format:
 		CONFIG_SPL_INIT_MINIMAL
 		Arch init code should be built for a very small image
 
+		CONFIG_SPL_LIBCOMMON_SUPPORT
+		Support for common/libcommon.o in SPL binary
+
+		CONFIG_SPL_LIBDISK_SUPPORT
+		Support for disk/libdisk.o in SPL binary
+
+		CONFIG_SPL_I2C_SUPPORT
+		Support for drivers/i2c/libi2c.o in SPL binary
+
+		CONFIG_SPL_GPIO_SUPPORT
+		Support for drivers/gpio/libgpio.o in SPL binary
+
+		CONFIG_SPL_MMC_SUPPORT
+		Support for drivers/mmc/libmmc.o in SPL binary
+
 		CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR,
 		CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS,
 		Address and partition on the MMC to load U-Boot from
@@ -3361,6 +3547,12 @@ FIT uImage format:
 		Partition on the MMC to load U-Boot from when the MMC is being
 		used in fs mode
 
+		CONFIG_SPL_FAT_SUPPORT
+		Support for fs/fat/libfat.o in SPL binary
+
+		CONFIG_SPL_EXT_SUPPORT
+		Support for EXT filesystem in SPL binary
+
 		CONFIG_SPL_FS_LOAD_PAYLOAD_NAME
 		Filename to read to load U-Boot when reading from filesystem
 
@@ -3399,10 +3591,18 @@ FIT uImage format:
 		Support for a lightweight UBI (fastmap) scanner and
 		loader
 
+		CONFIG_SPL_MTD_SUPPORT
+		Support for the MTD subsystem within SPL.  Useful for
+		environment on NAND support within SPL.
+
 		CONFIG_SPL_NAND_RAW_ONLY
 		Support to boot only raw u-boot.bin images. Use this only
 		if you need to save space.
 
+		CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+		Set for the SPL on PPC mpc8xxx targets, support for
+		drivers/ddr/fsl/libddr.o in SPL binary.
+
 		CONFIG_SPL_COMMON_INIT_DDR
 		Set for common ddr init with serial presence detect in
 		SPL binary.
@@ -3438,9 +3638,29 @@ FIT uImage format:
 		Support for an OMAP3-specific set of functions to return the
 		ID and MFR of the first attached NAND chip, if present.
 
+		CONFIG_SPL_SERIAL_SUPPORT
+		Support for drivers/serial/libserial.o in SPL binary
+
+		CONFIG_SPL_SPI_FLASH_SUPPORT
+		Support for drivers/mtd/spi/libspi_flash.o in SPL binary
+
+		CONFIG_SPL_SPI_SUPPORT
+		Support for drivers/spi/libspi.o in SPL binary
+
 		CONFIG_SPL_RAM_DEVICE
 		Support for running image already present in ram, in SPL binary
 
+		CONFIG_SPL_LIBGENERIC_SUPPORT
+		Support for lib/libgeneric.o in SPL binary
+
+		CONFIG_SPL_ENV_SUPPORT
+		Support for the environment operating in SPL binary
+
+		CONFIG_SPL_NET_SUPPORT
+		Support for the net/libnet.o in SPL binary.
+		It conflicts with SPL env from storage medium specified by
+		CONFIG_ENV_IS_xxx but CONFIG_ENV_IS_NOWHERE
+
 		CONFIG_SPL_PAD_TO
 		Image offset to which the SPL should be padded before appending
 		the SPL payload. By default, this is defined as
@@ -3527,6 +3747,21 @@ Configuration Settings:
 - CONFIG_SYS_BAUDRATE_TABLE:
 		List of legal baudrate settings for this board.
 
+- CONFIG_SYS_CONSOLE_INFO_QUIET
+		Suppress display of console information at boot.
+
+- CONFIG_SYS_CONSOLE_IS_IN_ENV
+		If the board specific function
+			extern int overwrite_console (void);
+		returns 1, the stdin, stderr and stdout are switched to the
+		serial port, else the settings in the environment are used.
+
+- CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+		Enable the call to overwrite_console().
+
+- CONFIG_SYS_CONSOLE_ENV_OVERWRITE
+		Enable overwrite of previous console environment settings.
+
 - CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END:
 		Begin and End addresses of the area used by the
 		simple memory test.
@@ -3574,6 +3809,10 @@ Configuration Settings:
 - CONFIG_SYS_SDRAM_BASE:
 		Physical start address of SDRAM. _Must_ be 0 here.
 
+- CONFIG_SYS_MBIO_BASE:
+		Physical start address of Motherboard I/O (if using a
+		Cogent motherboard)
+
 - CONFIG_SYS_FLASH_BASE:
 		Physical start address of Flash memory.
 
@@ -4005,7 +4244,7 @@ to save the current settings.
 	  This setting describes a second storage area of CONFIG_ENV_SIZE
 	  size used to hold a redundant copy of the environment data, so
 	  that there is a valid backup copy in case there is a power failure
-	  during a "saveenv" operation. CONFIG_ENV_OFFSET_REDUND must be
+	  during a "saveenv" operation. CONFIG_ENV_OFFSET_RENDUND must be
 	  aligned to an erase sector boundary.
 
 	- CONFIG_ENV_SPI_BUS (optional):
@@ -4056,7 +4295,7 @@ but it can not erase, write this NOR flash by SRIO or PCIE interface.
 	  This setting describes a second storage area of CONFIG_ENV_SIZE
 	  size used to hold a redundant copy of the environment data, so
 	  that there is a valid backup copy in case there is a power failure
-	  during a "saveenv" operation.	 CONFIG_ENV_OFFSET_REDUND must be
+	  during a "saveenv" operation.	 CONFIG_ENV_OFFSET_RENDUND must be
 	  aligned to an erase block boundary.
 
 	- CONFIG_ENV_RANGE (optional):
@@ -4357,7 +4596,7 @@ Low Level (hardware related) configuration options:
 		CONFIG_SYS_GBL_DATA_OFFSET is chosen such that the initial
 		data is located at the end of the available space
 		(sometimes written as (CONFIG_SYS_INIT_RAM_SIZE -
-		GENERATED_GBL_DATA_SIZE), and the initial stack is just
+		CONFIG_SYS_INIT_DATA_SIZE), and the initial stack is just
 		below that area (growing from (CONFIG_SYS_INIT_RAM_ADDR +
 		CONFIG_SYS_GBL_DATA_OFFSET) downward.
 
@@ -4416,6 +4655,11 @@ Low Level (hardware related) configuration options:
 		enable SPI microcode relocation patch (MPC8xx);
 		define relocation offset in DPRAM [SCC4]
 
+- CONFIG_SYS_USE_OSCCLK:
+		Use OSCM clock mode on MBX8xx board. Be careful,
+		wrong setting might damage your board. Read
+		doc/README.MBX before setting this variable!
+
 - CONFIG_SYS_CPM_POST_WORD_ADDR: (MPC8xx, MPC8260 only)
 		Offset of the bootmode word in DPRAM used by post
 		(Power On Self Tests). This definition overrides
@@ -4659,6 +4903,10 @@ within that device.
 	Specifies that QE/FMAN firmware is located on the primary SD/MMC
 	device.  CONFIG_SYS_FMAN_FW_ADDR is the byte offset on that device.
 
+- CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH
+	Specifies that QE/FMAN firmware is located on the primary SPI
+	device.  CONFIG_SYS_FMAN_FW_ADDR is the byte offset on that device.
+
 - CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 	Specifies that QE/FMAN firmware is located in the remote (master)
 	memory space.	CONFIG_SYS_FMAN_FW_ADDR is a virtual address which
@@ -4677,12 +4925,34 @@ within that device.
 - CONFIG_FSL_MC_ENET
 	Enable the MC driver for Layerscape SoCs.
 
+- CONFIG_SYS_LS_MC_FW_ADDR
+	The address in the storage device where the firmware is located.  The
+	meaning of this address depends on which CONFIG_SYS_LS_MC_FW_IN_xxx macro
+	is also specified.
+
+- CONFIG_SYS_LS_MC_FW_LENGTH
+	The maximum possible size of the firmware.  The firmware binary format
+	has a field that specifies the actual size of the firmware, but it
+	might not be possible to read any part of the firmware unless some
+	local storage is allocated to hold the entire firmware first.
+
+- CONFIG_SYS_LS_MC_FW_IN_NOR
+	Specifies that MC firmware is located in NOR flash, mapped as
+	normal addressable memory via the LBC. CONFIG_SYS_LS_MC_FW_ADDR is the
+	virtual address in NOR flash.
+
 Freescale Layerscape Debug Server Support:
 -------------------------------------------
 The Freescale Layerscape Debug Server Support supports the loading of
 "Debug Server firmware" and triggering SP boot-rom.
 This firmware often needs to be loaded during U-Boot booting.
 
+- CONFIG_FSL_DEBUG_SERVER
+	Enable the Debug Server for Layerscape SoCs.
+
+- CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE
+	Define minimum DDR size required for debug server image
+
 - CONFIG_SYS_MC_RSV_MEM_ALIGN
 	Define alignment of reserved memory MC requires
 

api/api_storage.c

@@ -41,7 +41,7 @@ struct stor_spec {
 	char		*name;
 };
 
-static struct stor_spec specs[ENUM_MAX] = { { 0, 0, 0, 0, NULL }, };
+static struct stor_spec specs[ENUM_MAX] = { { 0, 0, 0, 0, "" }, };
 
 
 void dev_stor_init(void)
@@ -105,10 +105,6 @@ static int dev_stor_get(int type, int first, int *more, struct device_info *di)
 
 	struct blk_desc *dd;
 
-	/* Wasn't configured for this type, return 0 directly */
-	if (specs[type].name == NULL)
-		return 0;
-
 	if (first) {
 		di->cookie = (void *)blk_get_dev(specs[type].name, 0);
 		if (di->cookie == NULL)

arch/Kconfig

@@ -62,7 +62,6 @@ config SANDBOX
 	bool "Sandbox"
 	select SUPPORT_OF_CONTROL
 	select DM
-	select DM_KEYBOARD
 	select DM_SPI_FLASH
 	select DM_SERIAL
 	select DM_I2C
@@ -84,7 +83,6 @@ config X86
 	select HAVE_PRIVATE_LIBGCC
 	select SUPPORT_OF_CONTROL
 	select DM
-	select DM_KEYBOARD
 	select DM_SERIAL
 	select DM_GPIO
 	select DM_SPI

arch/arc/config.mk

@@ -31,15 +31,15 @@ CONFIG_MMU = 1
 endif
 
 ifdef CONFIG_CPU_ARC750D
-PLATFORM_CPPFLAGS += -mcpu=arc700
+PLATFORM_CPPFLAGS += -marc700
 endif
 
 ifdef CONFIG_CPU_ARC770D
-PLATFORM_CPPFLAGS += -mcpu=arc700 -mlock -mswape
+PLATFORM_CPPFLAGS += -marc700 -mlock -mswape
 endif
 
 ifdef CONFIG_CPU_ARCEM6
-PLATFORM_CPPFLAGS += -mcpu=arcem
+PLATFORM_CPPFLAGS += -marcem
 endif
 
 ifdef CONFIG_CPU_ARCHS34

arch/arc/include/asm/errno.h

@@ -0,0 +1 @@
+#include <asm-generic/errno.h>

arch/arm/Kconfig

@@ -164,7 +164,9 @@ config KIRKWOOD
 	select CPU_ARM926EJS
 
 config ARCH_MVEBU
-	bool "Marvell MVEBU family (Armada XP/375/38x/3700/7K/8K)"
+	bool "Marvell MVEBU family (Armada XP/375/38x)"
+	select CPU_V7
+	select SUPPORT_SPL
 	select OF_CONTROL
 	select OF_SEPARATE
 	select DM
@@ -172,6 +174,10 @@ config ARCH_MVEBU
 	select DM_SERIAL
 	select DM_SPI
 	select DM_SPI_FLASH
+	select SPL_DM
+	select SPL_DM_SEQ_ALIAS
+	select SPL_OF_CONTROL
+	select SPL_SIMPLE_BUS
 
 config TARGET_DEVKIT3250
 	bool "Support devkit3250"
@@ -335,6 +341,38 @@ config TARGET_BRPPT1
 	select CPU_V7
 	select SUPPORT_SPL
 
+config TARGET_CM_T335
+	bool "Support cm_t335"
+	select CPU_V7
+	select SUPPORT_SPL
+	select DM
+	select DM_SERIAL
+	select DM_GPIO
+
+config TARGET_PEPPER
+	bool "Support pepper"
+	select CPU_V7
+	select SUPPORT_SPL
+	select DM
+	select DM_SERIAL
+	select DM_GPIO
+
+config TARGET_AM335X_IGEP0033
+	bool "Support am335x_igep0033"
+	select CPU_V7
+	select SUPPORT_SPL
+	select DM
+	select DM_SERIAL
+	select DM_GPIO
+
+config TARGET_PCM051
+	bool "Support pcm051"
+	select CPU_V7
+	select SUPPORT_SPL
+	select DM
+	select DM_SERIAL
+	select DM_GPIO
+
 config TARGET_DRACO
 	bool "Support draco"
 	select CPU_V7
@@ -383,6 +421,62 @@ config TARGET_RUT
 	select DM_SERIAL
 	select DM_GPIO
 
+config TARGET_PENGWYN
+	bool "Support pengwyn"
+	select CPU_V7
+	select SUPPORT_SPL
+	select DM
+	select DM_SERIAL
+	select DM_GPIO
+
+config TARGET_AM335X_BALTOS
+	bool "Support am335x_baltos"
+	select CPU_V7
+	select SUPPORT_SPL
+	select DM
+	select DM_SERIAL
+	select DM_GPIO
+
+config TARGET_AM335X_EVM
+	bool "Support am335x_evm"
+	select CPU_V7
+	select SUPPORT_SPL
+	select DM
+	select DM_SERIAL
+	select DM_GPIO
+	select TI_I2C_BOARD_DETECT
+
+config TARGET_AM335X_SHC
+	bool "Support am335x based shc board from bosch"
+	select CPU_V7
+	select SUPPORT_SPL
+	select DM
+	select DM_SERIAL
+	select DM_GPIO
+
+config TARGET_AM335X_SL50
+	bool "Support am335x_sl50"
+	select CPU_V7
+	select SUPPORT_SPL
+	select DM
+	select DM_GPIO
+	select DM_SERIAL
+
+config TARGET_BAV335X
+	bool "Support bav335x"
+	select CPU_V7
+	select SUPPORT_SPL
+	select DM
+	select DM_SERIAL
+	help
+	  The BAV335x OEM Network Processor integrates all the functions of an
+	  embedded network computer in a small, easy to use SODIMM module which
+	  incorporates the popular Texas Instruments Sitara 32bit ARM Coretex-A8
+	  processor, with fast DDR3 512MB SDRAM, 4GB of embedded MMC and a Gigabit
+	  ethernet with simple connection to external connectors.
+
+	  For more information, visit: http://birdland.com/oem
+
 config TARGET_TI814X_EVM
 	bool "Support ti814x_evm"
 	select CPU_V7
@@ -512,17 +606,6 @@ config AM43XX
 	  protocols, dual camera support, optional 3D graphics
 	  and an optional customer programmable secure boot.
 
-config AM33XX
-	bool "AM33XX SoC"
-	select CPU_V7
-	select SUPPORT_SPL
-	help
-	  Support for AM335x SOC from Texas Instruments.
-	  The AM335x high performance SOC features a Cortex-A8
-	  ARM core, a dual core PRU-ICSS for industrial Ethernet
-	  protocols, optional 3D graphics and an optional customer
-	  programmable secure boot.
-
 config ARCH_RMOBILE
 	bool "Renesas ARM SoCs"
 	select DM
@@ -595,10 +678,6 @@ config TARGET_PCM052
 	bool "Support pcm-052"
 	select CPU_V7
 
-config TARGET_BK4R1
-	bool "Support BK4r1"
-	select CPU_V7
-
 config ARCH_ZYNQ
 	bool "Xilinx Zynq Platform"
 	select CPU_V7
@@ -656,7 +735,6 @@ config TARGET_VEXPRESS64_JUNO
 
 config TARGET_LS2080A_EMU
 	bool "Support ls2080a_emu"
-	select ARCH_LS2080A
 	select ARM64
 	select ARMV8_MULTIENTRY
 	help
@@ -667,7 +745,6 @@ config TARGET_LS2080A_EMU
 
 config TARGET_LS2080A_SIMU
 	bool "Support ls2080a_simu"
-	select ARCH_LS2080A
 	select ARM64
 	select ARMV8_MULTIENTRY
 	help
@@ -678,7 +755,6 @@ config TARGET_LS2080A_SIMU
 
 config TARGET_LS2080AQDS
 	bool "Support ls2080aqds"
-	select ARCH_LS2080A
 	select ARM64
 	select ARMV8_MULTIENTRY
 	select SUPPORT_SPL
@@ -690,7 +766,6 @@ config TARGET_LS2080AQDS
 
 config TARGET_LS2080ARDB
 	bool "Support ls2080ardb"
-	select ARCH_LS2080A
 	select ARM64
 	select ARMV8_MULTIENTRY
 	select SUPPORT_SPL
@@ -713,7 +788,6 @@ config TARGET_HIKEY
 
 config TARGET_LS1012AQDS
 	bool "Support ls1012aqds"
-	select ARCH_LS1012A
 	select ARM64
 	help
 	  Support for Freescale LS1012AQDS platform.
@@ -723,7 +797,6 @@ config TARGET_LS1012AQDS
 
 config TARGET_LS1012ARDB
 	bool "Support ls1012ardb"
-	select ARCH_LS1012A
 	select ARM64
 	help
 	  Support for Freescale LS1012ARDB platform.
@@ -733,7 +806,6 @@ config TARGET_LS1012ARDB
 
 config TARGET_LS1012AFRDM
 	bool "Support ls1012afrdm"
-	select ARCH_LS1012A
 	select ARM64
 	help
 	  Support for Freescale LS1012AFRDM platform.
@@ -744,26 +816,17 @@ config TARGET_LS1012AFRDM
 config TARGET_LS1021AQDS
 	bool "Support ls1021aqds"
 	select CPU_V7
-	select CPU_V7_HAS_NONSEC
-	select CPU_V7_HAS_VIRT
 	select SUPPORT_SPL
-	select ARCH_LS1021A
 	select ARCH_SUPPORT_PSCI
-	select LS1_DEEP_SLEEP
 
 config TARGET_LS1021ATWR
 	bool "Support ls1021atwr"
 	select CPU_V7
-	select CPU_V7_HAS_NONSEC
-	select CPU_V7_HAS_VIRT
 	select SUPPORT_SPL
-	select ARCH_LS1021A
 	select ARCH_SUPPORT_PSCI
-	select LS1_DEEP_SLEEP
 
 config TARGET_LS1043AQDS
 	bool "Support ls1043aqds"
-	select ARCH_LS1043A
 	select ARM64
 	select ARMV8_MULTIENTRY
 	select SUPPORT_SPL
@@ -772,39 +835,12 @@ config TARGET_LS1043AQDS
 
 config TARGET_LS1043ARDB
 	bool "Support ls1043ardb"
-	select ARCH_LS1043A
 	select ARM64
 	select ARMV8_MULTIENTRY
 	select SUPPORT_SPL
 	help
 	  Support for Freescale LS1043ARDB platform.
 
-config TARGET_LS1046AQDS
-	bool "Support ls1046aqds"
-	select ARCH_LS1046A
-	select ARM64
-	select ARMV8_MULTIENTRY
-	select SUPPORT_SPL
-	select DM_SPI_FLASH if DM_SPI
-	help
-	  Support for Freescale LS1046AQDS platform.
-	  The LS1046A Development System (QDS) is a high-performance
-	  development platform that supports the QorIQ LS1046A
-	  Layerscape Architecture processor.
-
-config TARGET_LS1046ARDB
-	bool "Support ls1046ardb"
-	select ARCH_LS1046A
-	select ARM64
-	select ARMV8_MULTIENTRY
-	select SUPPORT_SPL
-	select DM_SPI_FLASH if DM_SPI
-	help
-	  Support for Freescale LS1046ARDB platform.
-	  The LS1046A Reference Design Board (RDB) is a high-performance
-	  development platform that supports the QorIQ LS1046A
-	  Layerscape Architecture processor.
-
 config TARGET_H2200
 	bool "Support h2200"
 	select CPU_PXA
@@ -819,25 +855,18 @@ config TARGET_COLIBRI_PXA270
 
 config ARCH_UNIPHIER
 	bool "Socionext UniPhier SoCs"
-	select BLK
 	select CLK_UNIPHIER
+	select SUPPORT_SPL
+	select SPL
+	select OF_CONTROL
+	select SPL_OF_CONTROL
+	select OF_LIBFDT
 	select DM
+	select SPL_DM
 	select DM_GPIO
+	select DM_SERIAL
 	select DM_I2C
 	select DM_MMC
-	select DM_RESET
-	select DM_SERIAL
-	select DM_USB
-	select OF_CONTROL
-	select OF_LIBFDT
-	select PINCTRL
-	select SPL
-	select SPL_DM
-	select SPL_LIBCOMMON_SUPPORT
-	select SPL_LIBGENERIC_SUPPORT
-	select SPL_OF_CONTROL
-	select SPL_PINCTRL
-	select SUPPORT_SPL
 	help
 	  Support for UniPhier SoC family developed by Socionext Inc.
 	  (formerly, System LSI Business Division of Panasonic Corporation)
@@ -863,9 +892,6 @@ config ARCH_ROCKCHIP
 	select DM_SERIAL
 	select DM_SPI
 	select DM_SPI_FLASH
-	select DM_USB if USB
-	select DM_PWM
-	select DM_REGULATOR
 
 config TARGET_THUNDERX_88XX
 	bool "Support ThunderX 88xx"
@@ -893,8 +919,6 @@ source "arch/arm/mach-kirkwood/Kconfig"
 
 source "arch/arm/mach-mvebu/Kconfig"
 
-source "arch/arm/cpu/armv7/ls102xa/Kconfig"
-
 source "arch/arm/cpu/armv7/mx7/Kconfig"
 
 source "arch/arm/cpu/armv7/mx6/Kconfig"
@@ -903,8 +927,6 @@ source "arch/arm/cpu/armv7/mx5/Kconfig"
 
 source "arch/arm/cpu/armv7/omap-common/Kconfig"
 
-source "arch/arm/cpu/armv8/fsl-layerscape/Kconfig"
-
 source "arch/arm/mach-orion5x/Kconfig"
 
 source "arch/arm/mach-rmobile/Kconfig"
@@ -962,9 +984,7 @@ source "board/freescale/ls2080ardb/Kconfig"
 source "board/freescale/ls1021aqds/Kconfig"
 source "board/freescale/ls1043aqds/Kconfig"
 source "board/freescale/ls1021atwr/Kconfig"
-source "board/freescale/ls1046aqds/Kconfig"
 source "board/freescale/ls1043ardb/Kconfig"
-source "board/freescale/ls1046ardb/Kconfig"
 source "board/freescale/ls1012aqds/Kconfig"
 source "board/freescale/ls1012ardb/Kconfig"
 source "board/freescale/ls1012afrdm/Kconfig"

arch/arm/config.mk

@@ -144,7 +144,4 @@ else
 ALL-y += u-boot.imx
 endif
 endif
-ifneq ($(CONFIG_VF610),)
-ALL-y += u-boot.vyb
-endif
 endif

arch/arm/cpu/arm1136/mx35/generic.c

@@ -10,7 +10,7 @@
 #include <common.h>
 #include <div64.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/clock.h>

arch/arm/cpu/arm1136/mx35/mx35_sdram.c

@@ -5,7 +5,7 @@
  */
 
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/imx-regs.h>
 #include <linux/types.h>
 #include <asm/arch/sys_proto.h>

arch/arm/cpu/arm920t/imx/timer.c

@@ -78,7 +78,11 @@ unsigned long long get_ticks(void)
  */
 ulong get_tbclk (void)
 {
-	return CONFIG_SYS_HZ;
+	ulong tbclk;
+
+	tbclk = CONFIG_SYS_HZ;
+
+	return tbclk;
 }
 
 /*

arch/arm/cpu/arm926ejs/mxs/clock.c

@@ -11,7 +11,7 @@
  */
 
 #include <common.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/imx-regs.h>

arch/arm/cpu/arm926ejs/mxs/iomux.c

@@ -8,7 +8,7 @@
  */
 
 #include <common.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/iomux.h>

arch/arm/cpu/arm926ejs/mxs/mxs.c

@@ -11,7 +11,7 @@
  */
 
 #include <common.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/imx-common/dma.h>

arch/arm/cpu/arm926ejs/spear/timer.c

@@ -37,7 +37,7 @@ int timer_init(void)
 	writel(MISC_PRSC_CFG, &misc_regs_p->prsc1_clk_cfg);
 	synth = MISC_GPT3SYNTH;
 #else
-# error Incorrect config. Can only be SPEAR{600|300|310|320}
+# error Incorrect config. Can only be spear{600|300|310|320}
 #endif
 
 	writel(readl(&misc_regs_p->periph_clk_cfg) | synth,

arch/arm/cpu/armv7/Makefile

@@ -12,7 +12,7 @@ obj-y	+= cache_v7.o cache_v7_asm.o
 obj-y	+= cpu.o cp15.o
 obj-y	+= syslib.o
 
-ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_MX7)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_ARCH_SUNXI)$(CONFIG_ARCH_SOCFPGA)$(CONFIG_LS102XA),)
+ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_MX7)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_SUNXI)$(CONFIG_ARCH_SOCFPGA),)
 ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y)
 obj-y	+= lowlevel_init.o
 endif

arch/arm/cpu/armv7/am33xx/Kconfig

@@ -1,99 +1,4 @@
-if AM33XX
-
-choice
-	prompt "AM33xx board select"
-	optional
-
-config TARGET_AM335X_EVM
-	bool "Support am335x_evm"
-	select DM
-	select DM_SERIAL
-	select DM_GPIO
-	select TI_I2C_BOARD_DETECT
-	help
-	  This option specifies support for the AM335x
-	  GP and HS EVM development platforms. The AM335x
-	  GP EVM is a standalone test, development, and
-	  evaluation module system that enables developers
-	  to write software and develop hardware around
-	  an AM335x processor subsystem.
-
-config TARGET_AM335X_BALTOS
-	bool "Support am335x_baltos"
-	select DM
-	select DM_SERIAL
-	select DM_GPIO
-
-config TARGET_AM335X_IGEP0033
-	bool "Support am335x_igep0033"
-	select DM
-	select DM_SERIAL
-	select DM_GPIO
-
-config TARGET_AM335X_SHC
-	bool "Support am335x based shc board from bosch"
-	select DM
-	select DM_SERIAL
-	select DM_GPIO
-
-config TARGET_AM335X_SL50
-	bool "Support am335x_sl50"
-	select DM
-	select DM_SERIAL
-	select DM_GPIO
-
-config TARGET_BAV335X
-	bool "Support bav335x"
-	select DM
-	select DM_SERIAL
-	help
-	  The BAV335x OEM Network Processor integrates all the functions of an
-	  embedded network computer in a small, easy to use SODIMM module which
-	  incorporates the popular Texas Instruments Sitara 32bit ARM Coretex-A8
-	  processor, with fast DDR3 512MB SDRAM, 4GB of embedded MMC and a Gigabit
-	  ethernet with simple connection to external connectors.
-
-	  For more information, visit: http://birdland.com/oem
-
-config TARGET_CM_T335
-	bool "Support cm_t335"
-	select DM
-	select DM_SERIAL
-	select DM_GPIO
-
-config TARGET_PCM051
-	bool "Support pcm051"
-	select DM
-	select DM_SERIAL
-	select DM_GPIO
-
-config TARGET_PENGWYN
-	bool "Support pengwyn"
-	select DM
-	select DM_SERIAL
-	select DM_GPIO
-
-config TARGET_PEPPER
-	bool "Support pepper"
-	select DM
-	select DM_SERIAL
-	select DM_GPIO
-
-endchoice
-
-endif
-
 if AM43XX
-
-config SPL_EXT_SUPPORT
-	default y
-
-config SPL_GPIO_SUPPORT
-	default y
-
-config SPL_I2C_SUPPORT
-	default y
-
 config TARGET_AM43XX_EVM
 	bool "Support am43xx_evm"
 	select TI_I2C_BOARD_DETECT
@@ -104,9 +9,7 @@ config TARGET_AM43XX_EVM
 	  evaluation module system that enables developers
 	  to write software and develop hardware around
 	  an AM43xx processor subsystem.
-endif
 
-if AM43XX || AM33XX
 config ISW_ENTRY_ADDR
 	hex "Address in memory or XIP flash of bootloader entry point"
 	help

arch/arm/cpu/armv7/am33xx/board.c

@@ -28,7 +28,7 @@
 #include <i2c.h>
 #include <miiphy.h>
 #include <cpsw.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <linux/compiler.h>
 #include <linux/usb/ch9.h>
 #include <linux/usb/gadget.h>

arch/arm/cpu/armv7/am33xx/config.mk

@@ -12,32 +12,16 @@ ifeq ($(CONFIG_TI_SECURE_DEVICE),y)
 # For booting from SPI use
 # u-boot-spl_HS_SPI_X-LOADER to program flash
 #
-# On AM43XX:
-#
-# For booting spl from all other media use
-# u-boot-spl_HS_ISSW
-#
-# On AM33XX:
-#
-# For booting spl from NAND flash use
-# u-boot-spl_HS_X-LOADER
-#
-# For booting spl from SD/MMC/eMMC media use
-# u-boot-spl_HS_MLO
-#
-# For booting spl over UART, USB, or Ethernet use
-# u-boot-spl_HS_2ND
+# For booting spl from all other  media
+# use u-boot-spl_HS_ISSW
 #
 # Refer to README.ti-secure for more info
 #
 ALL-y	+= u-boot-spl_HS_ISSW
-ALL-y += u-boot-spl_HS_SPI_X-LOADER
-ALL-y += u-boot-spl_HS_X-LOADER
-ALL-y += u-boot-spl_HS_MLO
-ALL-y += u-boot-spl_HS_2ND
+ALL-$(CONFIG_SPL_SPI_SUPPORT) += u-boot-spl_HS_SPI_X-LOADER
 else
 ALL-y	+= MLO
-ALL-y += MLO.byteswap
+ALL-$(CONFIG_SPL_SPI_SUPPORT) += MLO.byteswap
 endif
 else
 ifeq ($(CONFIG_TI_SECURE_DEVICE),y)

arch/arm/cpu/armv7/am33xx/sys_info.c

@@ -65,7 +65,9 @@ u32 get_device_type(void)
  */
 u32 get_sysboot_value(void)
 {
-	return readl(&cstat->statusreg) & SYSBOOT_MASK;
+	int mode;
+	mode = readl(&cstat->statusreg) & (SYSBOOT_MASK);
+	return mode;
 }
 
 #ifdef CONFIG_DISPLAY_CPUINFO
@@ -95,9 +97,6 @@ int print_cpuinfo(void)
 	case TI81XX:
 		cpu_s = "TI81XX";
 		break;
-	case AM437X:
-		cpu_s = "AM437X";
-		break;
 	default:
 		cpu_s = "Unknown CPU type";
 		break;
@@ -113,7 +112,7 @@ int print_cpuinfo(void)
 	else
 		sec_s = "?";
 
-	printf("CPU  : %s-%s rev %s\n", cpu_s, sec_s, rev_s);
+	printf("%s-%s rev %s\n", cpu_s, sec_s, rev_s);
 
 	return 0;
 }

arch/arm/cpu/armv7/bcm235xx/clk-bcm235xx.c

@@ -12,7 +12,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/sysmap.h>
 #include <asm/kona-common/clk.h>
 #include "clk-core.h"

arch/arm/cpu/armv7/bcm235xx/clk-bsc.c

@@ -6,7 +6,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/sysmap.h>
 #include <asm/kona-common/clk.h>
 #include "clk-core.h"

arch/arm/cpu/armv7/bcm235xx/clk-core.c

@@ -12,7 +12,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <bitfield.h>
 #include <asm/arch/sysmap.h>
 #include <asm/kona-common/clk.h>

arch/arm/cpu/armv7/bcm235xx/clk-eth.c

@@ -6,7 +6,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/sysmap.h>
 #include <asm/kona-common/clk.h>
 #include "clk-core.h"

arch/arm/cpu/armv7/bcm235xx/clk-sdio.c

@@ -6,7 +6,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/sysmap.h>
 #include <asm/kona-common/clk.h>
 #include "clk-core.h"

arch/arm/cpu/armv7/bcm235xx/clk-usb-otg.c

@@ -5,7 +5,7 @@
  */
 
 #include <common.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/sysmap.h>
 #include "clk-core.h"
 

arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c

@@ -12,7 +12,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/sysmap.h>
 #include <asm/kona-common/clk.h>
 #include "clk-core.h"

arch/arm/cpu/armv7/bcm281xx/clk-bsc.c

@@ -6,7 +6,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/sysmap.h>
 #include <asm/kona-common/clk.h>
 #include "clk-core.h"

arch/arm/cpu/armv7/bcm281xx/clk-core.c

@@ -12,7 +12,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <bitfield.h>
 #include <asm/arch/sysmap.h>
 #include <asm/kona-common/clk.h>

arch/arm/cpu/armv7/bcm281xx/clk-eth.c

@@ -6,7 +6,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/sysmap.h>
 #include <asm/kona-common/clk.h>
 #include "clk-core.h"

arch/arm/cpu/armv7/bcm281xx/clk-sdio.c

@@ -6,7 +6,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/sysmap.h>
 #include <asm/kona-common/clk.h>
 #include "clk-core.h"

arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c

@@ -5,7 +5,7 @@
  */
 
 #include <common.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/sysmap.h>
 #include "clk-core.h"
 

arch/arm/cpu/armv7/lowlevel_init.S

@@ -19,11 +19,7 @@ ENTRY(lowlevel_init)
 	/*
 	 * Setup a temporary stack. Global data is not available yet.
 	 */
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
-	ldr	sp, =CONFIG_SPL_STACK
-#else
 	ldr	sp, =CONFIG_SYS_INIT_SP_ADDR
-#endif
 	bic	sp, sp, #7 /* 8-byte alignment for ABI compliance */
 #ifdef CONFIG_SPL_DM
 	mov	r9, #0

arch/arm/cpu/armv7/ls102xa/Kconfig

@@ -1,89 +0,0 @@
-config ARCH_LS1021A
-	bool
-	select SYS_FSL_ERRATUM_A010315
-	select SYS_FSL_SRDS_1
-	select SYS_HAS_SERDES
-	select SYS_FSL_DDR_BE
-	select SYS_FSL_DDR_VER_50
-
-menu "LS102xA architecture"
-	depends on ARCH_LS1021A
-
-config LS1_DEEP_SLEEP
-	bool "Deep sleep"
-	depends on ARCH_LS1021A
-
-config MAX_CPUS
-	int "Maximum number of CPUs permitted for LS102xA"
-	depends on ARCH_LS1021A
-	default 2
-	help
-	  Set this number to the maximum number of possible CPUs in the SoC.
-	  SoCs may have multiple clusters with each cluster may have multiple
-	  ports. If some ports are reserved but higher ports are used for
-	  cores, count the reserved ports. This will allocate enough memory
-	  in spin table to properly handle all cores.
-
-config NUM_DDR_CONTROLLERS
-	int "Maximum DDR controllers"
-	default 1
-
-config SYS_FSL_ERRATUM_A010315
-	bool "Workaround for PCIe erratum A010315"
-
-config SYS_FSL_SRDS_1
-	bool
-
-config SYS_FSL_SRDS_2
-	bool
-
-config SYS_HAS_SERDES
-	bool
-
-config SYS_FSL_DDR
-	bool "Freescale DDR driver"
-	help
-	  Select Freescale General DDR driver, shared between most Freescale
-	  PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM-
-	  based Layerscape SoCs (such as ls2080a).
-
-config SYS_FSL_DDR_BE
-	bool
-	default y
-	help
-	  Access DDR registers in big-endian.
-
-config SYS_FSL_DDR_VER
-	int
-	default 50 if SYS_FSL_DDR_VER_50
-
-config SYS_FSL_DDR_VER_50
-	bool
-
-config SYS_FSL_DDRC_ARM_GEN3
-	bool
-
-config SYS_FSL_DDRC_GEN4
-	bool
-
-config SYS_FSL_DDR3
-	bool "Freescale DDR3 controller"
-	depends on !SYS_FSL_DDR4
-	select SYS_FSL_DDR
-	select SYS_FSL_DDRC_ARM_GEN3
-	help
-	  Enable Freescale DDR3 controller on ARM-based SoCs.
-
-config SYS_FSL_DDR4
-	bool "Freescale DDR4 controller"
-	select SYS_FSL_DDR
-	select SYS_FSL_DDRC_GEN4
-	help
-	  Enable Freescale DDR4 controller.
-
-config SYS_FSL_IFC_BANK_COUNT
-	int "Maximum banks of Integrated flash controller"
-	depends on ARCH_LS1021A
-	default 8
-
-endmenu

arch/arm/cpu/armv7/ls102xa/Makefile

@@ -16,5 +16,5 @@ obj-$(CONFIG_SYS_HAS_SERDES) += fsl_ls1_serdes.o ls102xa_serdes.o
 obj-$(CONFIG_SPL) += spl.o
 
 ifdef CONFIG_ARMV7_PSCI
-obj-y  += psci.o ls102xa_psci.o
+obj-y  += psci.o
 endif

arch/arm/cpu/armv7/ls102xa/fsl_epu.c

@@ -9,163 +9,6 @@
 
 #include "fsl_epu.h"
 
-struct fsm_reg_vals epu_default_val[] = {
-	/* EPGCR (Event Processor Global Control Register) */
-	{EPGCR, 0},
-	/* EPECR (Event Processor Event Control Registers) */
-	{EPECR0 + EPECR_STRIDE * 0, 0},
-	{EPECR0 + EPECR_STRIDE * 1, 0},
-	{EPECR0 + EPECR_STRIDE * 2, 0xF0004004},
-	{EPECR0 + EPECR_STRIDE * 3, 0x80000084},
-	{EPECR0 + EPECR_STRIDE * 4, 0x20000084},
-	{EPECR0 + EPECR_STRIDE * 5, 0x08000004},
-	{EPECR0 + EPECR_STRIDE * 6, 0x80000084},
-	{EPECR0 + EPECR_STRIDE * 7, 0x80000084},
-	{EPECR0 + EPECR_STRIDE * 8, 0x60000084},
-	{EPECR0 + EPECR_STRIDE * 9, 0x08000084},
-	{EPECR0 + EPECR_STRIDE * 10, 0x42000084},
-	{EPECR0 + EPECR_STRIDE * 11, 0x90000084},
-	{EPECR0 + EPECR_STRIDE * 12, 0x80000084},
-	{EPECR0 + EPECR_STRIDE * 13, 0x08000084},
-	{EPECR0 + EPECR_STRIDE * 14, 0x02000084},
-	{EPECR0 + EPECR_STRIDE * 15, 0x00000004},
-	/*
-	 * EPEVTCR (Event Processor EVT Pin Control Registers)
-	 * SCU8 triger EVT2, and SCU11 triger EVT9
-	 */
-	{EPEVTCR0 + EPEVTCR_STRIDE * 0, 0},
-	{EPEVTCR0 + EPEVTCR_STRIDE * 1, 0},
-	{EPEVTCR0 + EPEVTCR_STRIDE * 2, 0x80000001},
-	{EPEVTCR0 + EPEVTCR_STRIDE * 3, 0},
-	{EPEVTCR0 + EPEVTCR_STRIDE * 4, 0},
-	{EPEVTCR0 + EPEVTCR_STRIDE * 5, 0},
-	{EPEVTCR0 + EPEVTCR_STRIDE * 6, 0},
-	{EPEVTCR0 + EPEVTCR_STRIDE * 7, 0},
-	{EPEVTCR0 + EPEVTCR_STRIDE * 8, 0},
-	{EPEVTCR0 + EPEVTCR_STRIDE * 9, 0xB0000001},
-	/* EPCMPR (Event Processor Counter Compare Registers) */
-	{EPCMPR0 + EPCMPR_STRIDE * 0, 0},
-	{EPCMPR0 + EPCMPR_STRIDE * 1, 0},
-	{EPCMPR0 + EPCMPR_STRIDE * 2, 0x000000FF},
-	{EPCMPR0 + EPCMPR_STRIDE * 3, 0},
-	{EPCMPR0 + EPCMPR_STRIDE * 4, 0x000000FF},
-	{EPCMPR0 + EPCMPR_STRIDE * 5, 0x00000020},
-	{EPCMPR0 + EPCMPR_STRIDE * 6, 0},
-	{EPCMPR0 + EPCMPR_STRIDE * 7, 0},
-	{EPCMPR0 + EPCMPR_STRIDE * 8, 0x000000FF},
-	{EPCMPR0 + EPCMPR_STRIDE * 9, 0x000000FF},
-	{EPCMPR0 + EPCMPR_STRIDE * 10, 0x000000FF},
-	{EPCMPR0 + EPCMPR_STRIDE * 11, 0x000000FF},
-	{EPCMPR0 + EPCMPR_STRIDE * 12, 0x000000FF},
-	{EPCMPR0 + EPCMPR_STRIDE * 13, 0},
-	{EPCMPR0 + EPCMPR_STRIDE * 14, 0x000000FF},
-	{EPCMPR0 + EPCMPR_STRIDE * 15, 0x000000FF},
-	/* EPCCR (Event Processor Counter Control Registers) */
-	{EPCCR0 + EPCCR_STRIDE * 0, 0},
-	{EPCCR0 + EPCCR_STRIDE * 1, 0},
-	{EPCCR0 + EPCCR_STRIDE * 2, 0x92840000},
-	{EPCCR0 + EPCCR_STRIDE * 3, 0},
-	{EPCCR0 + EPCCR_STRIDE * 4, 0x92840000},
-	{EPCCR0 + EPCCR_STRIDE * 5, 0x92840000},
-	{EPCCR0 + EPCCR_STRIDE * 6, 0},
-	{EPCCR0 + EPCCR_STRIDE * 7, 0},
-	{EPCCR0 + EPCCR_STRIDE * 8, 0x92840000},
-	{EPCCR0 + EPCCR_STRIDE * 9, 0x92840000},
-	{EPCCR0 + EPCCR_STRIDE * 10, 0x92840000},
-	{EPCCR0 + EPCCR_STRIDE * 11, 0x92840000},
-	{EPCCR0 + EPCCR_STRIDE * 12, 0x92840000},
-	{EPCCR0 + EPCCR_STRIDE * 13, 0},
-	{EPCCR0 + EPCCR_STRIDE * 14, 0x92840000},
-	{EPCCR0 + EPCCR_STRIDE * 15, 0x92840000},
-	/* EPSMCR (Event Processor SCU Mux Control Registers) */
-	{EPSMCR0 + EPSMCR_STRIDE * 0, 0},
-	{EPSMCR0 + EPSMCR_STRIDE * 1, 0},
-	{EPSMCR0 + EPSMCR_STRIDE * 2, 0x6C700000},
-	{EPSMCR0 + EPSMCR_STRIDE * 3, 0x2F000000},
-	{EPSMCR0 + EPSMCR_STRIDE * 4, 0x002F0000},
-	{EPSMCR0 + EPSMCR_STRIDE * 5, 0x00002E00},
-	{EPSMCR0 + EPSMCR_STRIDE * 6, 0x7C000000},
-	{EPSMCR0 + EPSMCR_STRIDE * 7, 0x30000000},
-	{EPSMCR0 + EPSMCR_STRIDE * 8, 0x64300000},
-	{EPSMCR0 + EPSMCR_STRIDE * 9, 0x00003000},
-	{EPSMCR0 + EPSMCR_STRIDE * 10, 0x65000030},
-	{EPSMCR0 + EPSMCR_STRIDE * 11, 0x31740000},
-	{EPSMCR0 + EPSMCR_STRIDE * 12, 0x7F000000},
-	{EPSMCR0 + EPSMCR_STRIDE * 13, 0x00003100},
-	{EPSMCR0 + EPSMCR_STRIDE * 14, 0x00000031},
-	{EPSMCR0 + EPSMCR_STRIDE * 15, 0x76000000},
-	/* EPACR (Event Processor Action Control Registers) */
-	{EPACR0 + EPACR_STRIDE * 0, 0},
-	{EPACR0 + EPACR_STRIDE * 1, 0},
-	{EPACR0 + EPACR_STRIDE * 2, 0},
-	{EPACR0 + EPACR_STRIDE * 3, 0x00000080},
-	{EPACR0 + EPACR_STRIDE * 4, 0},
-	{EPACR0 + EPACR_STRIDE * 5, 0x00000040},
-	{EPACR0 + EPACR_STRIDE * 6, 0},
-	{EPACR0 + EPACR_STRIDE * 7, 0},
-	{EPACR0 + EPACR_STRIDE * 8, 0},
-	{EPACR0 + EPACR_STRIDE * 9, 0x0000001C},
-	{EPACR0 + EPACR_STRIDE * 10, 0x00000020},
-	{EPACR0 + EPACR_STRIDE * 11, 0},
-	{EPACR0 + EPACR_STRIDE * 12, 0x00000003},
-	{EPACR0 + EPACR_STRIDE * 13, 0x06000000},
-	{EPACR0 + EPACR_STRIDE * 14, 0x04000000},
-	{EPACR0 + EPACR_STRIDE * 15, 0x02000000},
-	/* EPIMCR (Event Processor Input Mux Control Registers) */
-	{EPIMCR0 + EPIMCR_STRIDE * 0, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 1, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 2, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 3, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 4, 0x44000000},
-	{EPIMCR0 + EPIMCR_STRIDE * 5, 0x40000000},
-	{EPIMCR0 + EPIMCR_STRIDE * 6, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 7, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 8, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 9, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 10, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 11, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 12, 0x44000000},
-	{EPIMCR0 + EPIMCR_STRIDE * 13, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 14, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 15, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 16, 0x6A000000},
-	{EPIMCR0 + EPIMCR_STRIDE * 17, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 18, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 19, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 20, 0x48000000},
-	{EPIMCR0 + EPIMCR_STRIDE * 21, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 22, 0x6C000000},
-	{EPIMCR0 + EPIMCR_STRIDE * 23, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 24, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 25, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 26, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 27, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 28, 0x76000000},
-	{EPIMCR0 + EPIMCR_STRIDE * 29, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 30, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 31, 0x76000000},
-	/* EPXTRIGCR (Event Processor Crosstrigger Control Register) */
-	{EPXTRIGCR, 0x0000FFDF},
-	/* end */
-	{FSM_END_FLAG, 0},
-};
-
-/**
- * fsl_epu_setup - Setup EPU registers to default values
- */
-void fsl_epu_setup(void *epu_base)
-{
-	struct fsm_reg_vals *data = epu_default_val;
-
-	if (!epu_base || !data)
-		return;
-
-	while (data->offset != FSM_END_FLAG) {
-		out_be32(epu_base + data->offset, data->value);
-		data++;
-	}
-}
-
 /**
  * fsl_epu_clean - Clear EPU registers
  */

arch/arm/cpu/armv7/ls102xa/fsl_epu.h

@@ -63,14 +63,6 @@
 #define EPCTR31		0xA7C
 #define EPCTR_STRIDE	FSL_STRIDE_4B
 
-#define FSM_END_FLAG	0xFFFFFFFFUL
-
-struct fsm_reg_vals {
-	u32 offset;
-	u32 value;
-};
-
-void fsl_epu_setup(void *epu_base);
 void fsl_epu_clean(void *epu_base);
 
 #endif

arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c

@@ -7,7 +7,7 @@
 #include <common.h>
 #include <asm/arch/fsl_serdes.h>
 #include <asm/arch/immap_ls102xa.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/io.h>
 #include "fsl_ls1_serdes.h"
 
@@ -23,15 +23,9 @@ int is_serdes_configured(enum srds_prtcl device)
 	u64 ret = 0;
 
 #ifdef CONFIG_SYS_FSL_SRDS_1
-	if (!(serdes1_prtcl_map & (1ULL << NONE)))
-		fsl_serdes_init();
-
 	ret |= (1ULL << device) & serdes1_prtcl_map;
 #endif
 #ifdef CONFIG_SYS_FSL_SRDS_2
-	if (!(serdes2_prtcl_map & (1ULL << NONE)))
-		fsl_serdes_init();
-
 	ret |= (1ULL << device) & serdes2_prtcl_map;
 #endif
 
@@ -93,24 +87,19 @@ u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift)
 		serdes_prtcl_map |= (1ULL << lane_prtcl);
 	}
 
-	/* Set the first bit to indicate serdes has been initialized */
-	serdes_prtcl_map |= (1ULL << NONE);
-
 	return serdes_prtcl_map;
 }
 
 void fsl_serdes_init(void)
 {
 #ifdef CONFIG_SYS_FSL_SRDS_1
-	if (!(serdes1_prtcl_map & (1ULL << NONE)))
-		serdes1_prtcl_map = serdes_init(FSL_SRDS_1,
+	serdes1_prtcl_map = serdes_init(FSL_SRDS_1,
 					CONFIG_SYS_FSL_SERDES_ADDR,
 					RCWSR4_SRDS1_PRTCL_MASK,
 					RCWSR4_SRDS1_PRTCL_SHIFT);
 #endif
 #ifdef CONFIG_SYS_FSL_SRDS_2
-	if (!(serdes2_prtcl_map & (1ULL << NONE)))
-		serdes2_prtcl_map = serdes_init(FSL_SRDS_2,
+	serdes2_prtcl_map = serdes_init(FSL_SRDS_2,
 					CONFIG_SYS_FSL_SERDES_ADDR +
 					FSL_SRDS_2 * 0x1000,
 					RCWSR4_SRDS2_PRTCL_MASK,

arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c

@@ -1,236 +0,0 @@
-/*
- * Copyright 2016 Freescale Semiconductor, Inc.
- * Author: Hongbo Zhang <hongbo.zhang@nxp.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- * This file implements LS102X platform PSCI SYSTEM-SUSPEND function
- */
-
-#include <config.h>
-#include <asm/io.h>
-#include <asm/psci.h>
-#include <asm/arch/immap_ls102xa.h>
-#include <fsl_immap.h>
-#include "fsl_epu.h"
-
-#define __secure __attribute__((section("._secure.text")))
-
-#define CCSR_GICD_CTLR			0x1000
-#define CCSR_GICC_CTLR			0x2000
-#define DCSR_RCPM_CG1CR0		0x31c
-#define DCSR_RCPM_CSTTACR0		0xb00
-#define DCFG_CRSTSR_WDRFR		0x8
-#define DDR_RESV_LEN			128
-
-#ifdef CONFIG_LS1_DEEP_SLEEP
-/*
- * DDR controller initialization training breaks the first 128 bytes of DDR,
- * save them so that the bootloader can restore them while resuming.
- */
-static void __secure ls1_save_ddr_head(void)
-{
-	const char *src = (const char *)CONFIG_SYS_SDRAM_BASE;
-	char *dest = (char *)(OCRAM_BASE_S_ADDR + OCRAM_S_SIZE - DDR_RESV_LEN);
-	struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
-	int i;
-
-	out_le32(&scfg->sparecr[2], dest);
-
-	for (i = 0; i < DDR_RESV_LEN; i++)
-		*dest++ = *src++;
-}
-
-static void __secure ls1_fsm_setup(void)
-{
-	void *dcsr_epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
-	void *dcsr_rcpm_base = (void *)SYS_FSL_DCSR_RCPM_ADDR;
-
-	out_be32(dcsr_rcpm_base + DCSR_RCPM_CSTTACR0, 0x00001001);
-	out_be32(dcsr_rcpm_base + DCSR_RCPM_CG1CR0, 0x00000001);
-
-	fsl_epu_setup((void *)dcsr_epu_base);
-
-	/* Pull MCKE signal low before enabling deep sleep signal in FPGA */
-	out_be32(dcsr_epu_base + EPECR0, 0x5);
-	out_be32(dcsr_epu_base + EPSMCR15, 0x76300000);
-}
-
-static void __secure ls1_deepsleep_irq_cfg(void)
-{
-	struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
-	struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR;
-	u32 ippdexpcr0, ippdexpcr1, pmcintecr = 0;
-
-	/* Mask interrupts from GIC */
-	out_be32(&rcpm->nfiqoutr, 0x0ffffffff);
-	out_be32(&rcpm->nirqoutr, 0x0ffffffff);
-	/* Mask deep sleep wake-up interrupts while entering deep sleep */
-	out_be32(&rcpm->dsimskr, 0x0ffffffff);
-
-	ippdexpcr0 = in_be32(&rcpm->ippdexpcr0);
-	/*
-	 * Workaround: There is bug of register ippdexpcr1, when read it always
-	 * returns zero, so its value is saved to a scrachpad register to be
-	 * read, that is why we don't read it from register ippdexpcr1 itself.
-	 */
-	ippdexpcr1 = in_le32(&scfg->sparecr[7]);
-
-	if (ippdexpcr0 & RCPM_IPPDEXPCR0_ETSEC)
-		pmcintecr |= SCFG_PMCINTECR_ETSECRXG0 |
-			     SCFG_PMCINTECR_ETSECRXG1 |
-			     SCFG_PMCINTECR_ETSECERRG0 |
-			     SCFG_PMCINTECR_ETSECERRG1;
-
-	if (ippdexpcr0 & RCPM_IPPDEXPCR0_GPIO)
-		pmcintecr |= SCFG_PMCINTECR_GPIO;
-
-	if (ippdexpcr1 & RCPM_IPPDEXPCR1_LPUART)
-		pmcintecr |= SCFG_PMCINTECR_LPUART;
-
-	if (ippdexpcr1 & RCPM_IPPDEXPCR1_FLEXTIMER)
-		pmcintecr |= SCFG_PMCINTECR_FTM;
-
-	/* Always set external IRQ pins as wakeup source */
-	pmcintecr |= SCFG_PMCINTECR_IRQ0 | SCFG_PMCINTECR_IRQ1;
-
-	out_be32(&scfg->pmcintlecr, 0);
-	/* Clear PMC interrupt status */
-	out_be32(&scfg->pmcintsr, 0xffffffff);
-	/* Enable wakeup interrupt during deep sleep */
-	out_be32(&scfg->pmcintecr, pmcintecr);
-}
-
-static void __secure ls1_delay(unsigned int loop)
-{
-	while (loop--) {
-		int i = 1000;
-		while (i--)
-			;
-	}
-}
-
-static void __secure ls1_start_fsm(void)
-{
-	void *dcsr_epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
-	void *ccsr_gic_base = (void *)SYS_FSL_GIC_ADDR;
-	struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
-	struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
-
-	/* Set HRSTCR */
-	setbits_be32(&scfg->hrstcr, 0x80000000);
-
-	/* Place DDR controller in self refresh mode */
-	setbits_be32(&ddr->sdram_cfg_2, 0x80000000);
-
-	ls1_delay(2000);
-
-	/* Set EVT4_B to lock the signal MCKE down */
-	out_be32(dcsr_epu_base + EPECR0, 0x0);
-
-	ls1_delay(2000);
-
-	out_be32(ccsr_gic_base + CCSR_GICD_CTLR, 0x0);
-	out_be32(ccsr_gic_base + CCSR_GICC_CTLR, 0x0);
-
-	/* Enable all EPU Counters */
-	setbits_be32(dcsr_epu_base + EPGCR, 0x80000000);
-
-	/* Enable SCU15 */
-	setbits_be32(dcsr_epu_base + EPECR15, 0x90000004);
-
-	/* Enter WFI mode, and EPU FSM will start */
-	__asm__ __volatile__ ("wfi" : : : "memory");
-
-	/* NEVER ENTER HERE */
-	while (1)
-		;
-}
-
-static void __secure ls1_deep_sleep(u32 entry_point)
-{
-	struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
-	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
-	struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR;
-#ifdef QIXIS_BASE
-	u32 tmp;
-	void *qixis_base = (void *)QIXIS_BASE;
-#endif
-
-	/* Enable cluster to enter the PCL10 state */
-	out_be32(&scfg->clusterpmcr, SCFG_CLUSTERPMCR_WFIL2EN);
-
-	/* Save the first 128 bytes of DDR data */
-	ls1_save_ddr_head();
-
-	/* Save the kernel resume entry */
-	out_le32(&scfg->sparecr[3], entry_point);
-
-	/* Request to put cluster 0 in PCL10 state */
-	setbits_be32(&rcpm->clpcl10setr, RCPM_CLPCL10SETR_C0);
-
-	/* Setup the registers of the EPU FSM for deep sleep */
-	ls1_fsm_setup();
-
-#ifdef QIXIS_BASE
-	/* Connect the EVENT button to IRQ in FPGA */
-	tmp = in_8(qixis_base + QIXIS_CTL_SYS);
-	tmp &= ~QIXIS_CTL_SYS_EVTSW_MASK;
-	tmp |= QIXIS_CTL_SYS_EVTSW_IRQ;
-	out_8(qixis_base + QIXIS_CTL_SYS, tmp);
-
-	/* Enable deep sleep signals in FPGA */
-	tmp = in_8(qixis_base + QIXIS_PWR_CTL2);
-	tmp |= QIXIS_PWR_CTL2_PCTL;
-	out_8(qixis_base + QIXIS_PWR_CTL2, tmp);
-
-	/* Pull down PCIe RST# */
-	tmp = in_8(qixis_base + QIXIS_RST_FORCE_3);
-	tmp |= QIXIS_RST_FORCE_3_PCIESLOT1;
-	out_8(qixis_base + QIXIS_RST_FORCE_3, tmp);
-#endif
-
-	/* Enable Warm Device Reset */
-	setbits_be32(&scfg->dpslpcr, SCFG_DPSLPCR_WDRR_EN);
-	setbits_be32(&gur->crstsr, DCFG_CRSTSR_WDRFR);
-
-	ls1_deepsleep_irq_cfg();
-
-	psci_v7_flush_dcache_all();
-
-	ls1_start_fsm();
-}
-
-#else
-static void __secure ls1_sleep(void)
-{
-	struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
-	struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR;
-
-#ifdef QIXIS_BASE
-	u32 tmp;
-	void *qixis_base = (void *)QIXIS_BASE;
-
-	/* Connect the EVENT button to IRQ in FPGA */
-	tmp = in_8(qixis_base + QIXIS_CTL_SYS);
-	tmp &= ~QIXIS_CTL_SYS_EVTSW_MASK;
-	tmp |= QIXIS_CTL_SYS_EVTSW_IRQ;
-	out_8(qixis_base + QIXIS_CTL_SYS, tmp);
-#endif
-
-	/* Enable cluster to enter the PCL10 state */
-	out_be32(&scfg->clusterpmcr, SCFG_CLUSTERPMCR_WFIL2EN);
-
-	setbits_be32(&rcpm->powmgtcsr, RCPM_POWMGTCSR_LPM20_REQ);
-
-	__asm__ __volatile__ ("wfi" : : : "memory");
-}
-#endif
-
-void __secure ls1_system_suspend(u32 fn, u32 entry_point, u32 context_id)
-{
-#ifdef CONFIG_LS1_DEEP_SLEEP
-	ls1_deep_sleep(entry_point);
-#else
-	ls1_sleep();
-#endif
-}

arch/arm/cpu/armv7/ls102xa/psci.S

@@ -29,7 +29,6 @@
 #define PSCI_FN_AFFINITY_INFO_FEATURE_MASK	0x0
 #define PSCI_FN_SYSTEM_OFF_FEATURE_MASK		0x0
 #define PSCI_FN_SYSTEM_RESET_FEATURE_MASK	0x0
-#define PSCI_FN_SYSTEM_SUSPEND_FEATURE_MASK	0x0
 
 	.pushsection ._secure.text, "ax"
 
@@ -62,8 +61,6 @@ _ls102x_psci_supported_table:
 	.word	PSCI_FN_SYSTEM_OFF_FEATURE_MASK
 	.word	ARM_PSCI_0_2_FN_SYSTEM_RESET
 	.word	PSCI_FN_SYSTEM_RESET_FEATURE_MASK
-	.word	ARM_PSCI_1_0_FN_SYSTEM_SUSPEND
-	.word	PSCI_FN_SYSTEM_SUSPEND_FEATURE_MASK
 	.word	0
 	.word	ARM_PSCI_RET_NI
 
@@ -246,12 +243,4 @@ psci_system_reset:
 1:	wfi
 	b	1b
 
-.globl	psci_system_suspend
-psci_system_suspend:
-	push	{lr}
-
-	bl	ls1_system_suspend
-
-	pop	{pc}
-
 	.popsection

arch/arm/cpu/armv7/ls102xa/soc.c

@@ -7,11 +7,9 @@
 #include <common.h>
 #include <asm/arch/clock.h>
 #include <asm/io.h>
-#include <asm/arch/fsl_serdes.h>
 #include <asm/arch/immap_ls102xa.h>
 #include <asm/arch/ls102xa_soc.h>
 #include <asm/arch/ls102xa_stream_id.h>
-#include <fsl_csu.h>
 
 struct liodn_id_table sec_liodn_tbl[] = {
 	SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10),
@@ -60,33 +58,12 @@ unsigned int get_soc_major_rev(void)
 	return major;
 }
 
-void s_init(void)
-{
-}
-
-#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
-void erratum_a010315(void)
-{
-	int i;
-
-	for (i = PCIE1; i <= PCIE2; i++)
-		if (!is_serdes_configured(i)) {
-			debug("PCIe%d: disabled all R/W permission!\n", i);
-			set_pcie_ns_access(i, 0);
-		}
-}
-#endif
-
 int arch_soc_init(void)
 {
 	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
 	unsigned int major;
 
-#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
-	enable_layerscape_ns_access();
-#endif
-
 #ifdef CONFIG_FSL_QSPI
 	out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
 #endif

arch/arm/cpu/armv7/mx5/clock.c

@@ -9,7 +9,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/clock.h>

arch/arm/cpu/armv7/mx5/soc.c

@@ -12,7 +12,7 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/sys_proto.h>
 
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/io.h>
 #include <asm/imx-common/boot_mode.h>
 

arch/arm/cpu/armv7/mx6/Kconfig

@@ -31,10 +31,6 @@ config MX6UL
 	select ROM_UNIFIED_SECTIONS
 	bool
 
-config MX6ULL
-	bool
-	select MX6UL
-
 choice
 	prompt "MX6 board select"
 	optional
@@ -95,16 +91,6 @@ config TARGET_MX6CUBOXI
 config TARGET_MX6QARM2
 	bool "mx6qarm2"
 
-config TARGET_MX6Q_ICORE
-	bool "Support Engicam i.Core"
-	select MX6QDL
-	select OF_CONTROL
-	select DM
-	select DM_GPIO
-	select DM_MMC
-	select DM_THERMAL
-	select SUPPORT_SPL
-
 config TARGET_MX6QSABREAUTO
 	bool "mx6qsabreauto"
 	select DM
@@ -147,12 +133,6 @@ config TARGET_MX6UL_14X14_EVK
 	select DM_THERMAL
 	select SUPPORT_SPL
 
-config TARGET_MX6ULL_14X14_EVK
-	bool "Support mx6ull_14x14_evk"
-	select MX6ULL
-	select DM
-	select DM_THERMAL
-
 config TARGET_NITROGEN6X
 	bool "nitrogen6x"
 
@@ -235,7 +215,6 @@ source "board/compulab/cm_fx6/Kconfig"
 source "board/congatec/cgtqmx6eval/Kconfig"
 source "board/el/el6x/Kconfig"
 source "board/embest/mx6boards/Kconfig"
-source "board/engicam/icorem6/Kconfig"
 source "board/freescale/mx6qarm2/Kconfig"
 source "board/freescale/mx6qsabreauto/Kconfig"
 source "board/freescale/mx6sabresd/Kconfig"
@@ -243,7 +222,6 @@ source "board/freescale/mx6slevk/Kconfig"
 source "board/freescale/mx6sxsabresd/Kconfig"
 source "board/freescale/mx6sxsabreauto/Kconfig"
 source "board/freescale/mx6ul_14x14_evk/Kconfig"
-source "board/freescale/mx6ullevk/Kconfig"
 source "board/phytec/pcm058/Kconfig"
 source "board/gateworks/gw_ventana/Kconfig"
 source "board/kosagi/novena/Kconfig"

arch/arm/cpu/armv7/mx6/clock.c

@@ -7,7 +7,7 @@
 #include <common.h>
 #include <div64.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/clock.h>
@@ -97,10 +97,7 @@ void enable_enet_clk(unsigned char enable)
 {
 	u32 mask, *addr;
 
-	if (is_mx6ull()) {
-		mask = MXC_CCM_CCGR0_ENET_CLK_ENABLE_MASK;
-		addr = &imx_ccm->CCGR0;
-	} else if (is_mx6ul()) {
+	if (is_mx6ul()) {
 		mask = MXC_CCM_CCGR3_ENET_MASK;
 		addr = &imx_ccm->CCGR3;
 	} else {
@@ -120,7 +117,7 @@ void enable_uart_clk(unsigned char enable)
 {
 	u32 mask;
 
-	if (is_mx6ul() || is_mx6ull())
+	if (is_mx6ul())
 		mask = MXC_CCM_CCGR5_UART_MASK;
 	else
 		mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
@@ -171,7 +168,7 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
 			reg &= ~mask;
 		__raw_writel(reg, &imx_ccm->CCGR2);
 	} else {
-		if (is_mx6sx() || is_mx6ul() || is_mx6ull()) {
+		if (is_mx6sx() || is_mx6ul()) {
 			mask = MXC_CCM_CCGR6_I2C4_MASK;
 			addr = &imx_ccm->CCGR6;
 		} else {
@@ -282,7 +279,7 @@ static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
 
 	switch (pll) {
 	case PLL_BUS:
-		if (!is_mx6ul() && !is_mx6ull()) {
+		if (!is_mx6ul()) {
 			if (pfd_num == 3) {
 				/* No PFD3 on PLL2 */
 				return 0;
@@ -383,7 +380,7 @@ static u32 get_ipg_per_clk(void)
 
 	reg = __raw_readl(&imx_ccm->cscmr1);
 	if (is_mx6sl() || is_mx6sx() ||
-	    is_mx6dqp() || is_mx6ul() || is_mx6ull()) {
+	    is_mx6dqp() || is_mx6ul()) {
 		if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
 			return MXC_HCLK; /* OSC 24Mhz */
 	}
@@ -399,8 +396,7 @@ static u32 get_uart_clk(void)
 	u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
 	reg = __raw_readl(&imx_ccm->cscdr1);
 
-	if (is_mx6sl() || is_mx6sx() || is_mx6dqp() || is_mx6ul() ||
-	    is_mx6ull()) {
+	if (is_mx6sl() || is_mx6sx() || is_mx6dqp() || is_mx6ul()) {
 		if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
 			freq = MXC_HCLK;
 	}
@@ -419,8 +415,7 @@ static u32 get_cspi_clk(void)
 	cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >>
 		     MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
 
-	if (is_mx6dqp() || is_mx6sl() || is_mx6sx() || is_mx6ul() ||
-	    is_mx6ull()) {
+	if (is_mx6dqp() || is_mx6sl() || is_mx6sx() || is_mx6ul()) {
 		if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK)
 			return MXC_HCLK / (cspi_podf + 1);
 	}
@@ -482,7 +477,7 @@ static u32 get_mmdc_ch0_clk(void)
 
 	u32 freq, podf, per2_clk2_podf, pmu_misc2_audio_div;
 
-	if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl()) {
+	if (is_mx6sx() || is_mx6ul() || is_mx6sl()) {
 		podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >>
 			MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
 		if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) {
@@ -620,7 +615,7 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq)
 
 	debug("mxs_set_lcdclk, freq = %dKHz\n", freq);
 
-	if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull()) {
+	if (!is_mx6sx() && !is_mx6ul()) {
 		debug("This chip not support lcd!\n");
 		return;
 	}
@@ -754,7 +749,7 @@ int enable_lcdif_clock(u32 base_addr)
 			 MXC_CCM_CCGR3_DISP_AXI_MASK) :
 			(MXC_CCM_CCGR3_LCDIF1_PIX_MASK |
 			 MXC_CCM_CCGR3_DISP_AXI_MASK);
-	} else if (is_mx6ul() || is_mx6ull()) {
+	} else if (is_mx6ul()) {
 		if (base_addr != LCDIF1_BASE_ADDR) {
 			puts("Wrong LCD interface!\n");
 			return -EINVAL;
@@ -852,7 +847,7 @@ int enable_fec_anatop_clock(int fec_id, enum enet_freq freq)
 		reg |= BF_ANADIG_PLL_ENET_DIV_SELECT(freq);
 	} else if (fec_id == 1) {
 		/* Only i.MX6SX/UL support ENET2 */
-		if (!(is_mx6sx() || is_mx6ul() || is_mx6ull()))
+		if (!(is_mx6sx() || is_mx6ul()))
 			return -EINVAL;
 		reg &= ~BM_ANADIG_PLL_ENET2_DIV_SELECT;
 		reg |= BF_ANADIG_PLL_ENET2_DIV_SELECT(freq);
@@ -1074,27 +1069,17 @@ void hab_caam_clock_enable(unsigned char enable)
 {
 	u32 reg;
 
-	if (is_mx6ull()) {
-		/* CG5, DCP clock */
-		reg = __raw_readl(&imx_ccm->CCGR0);
-		if (enable)
-			reg |= MXC_CCM_CCGR0_DCP_CLK_MASK;
-		else
-			reg &= ~MXC_CCM_CCGR0_DCP_CLK_MASK;
-		__raw_writel(reg, &imx_ccm->CCGR0);
-	} else {
-		/* CG4 ~ CG6, CAAM clocks */
-		reg = __raw_readl(&imx_ccm->CCGR0);
-		if (enable)
-			reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
-				MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
-				MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
-		else
-			reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
-				MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
-				MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
-		__raw_writel(reg, &imx_ccm->CCGR0);
-	}
+	/* CG4 ~ CG6, CAAM clocks */
+	reg = __raw_readl(&imx_ccm->CCGR0);
+	if (enable)
+		reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
+			MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
+			MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
+	else
+		reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
+			MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
+			MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
+	__raw_writel(reg, &imx_ccm->CCGR0);
 
 	/* EMI slow clk */
 	reg = __raw_readl(&imx_ccm->CCGR6);

arch/arm/cpu/armv7/mx6/mp.c

@@ -9,7 +9,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/imx-regs.h>
 

arch/arm/cpu/armv7/mx6/soc.c

@@ -8,7 +8,7 @@
  */
 
 #include <common.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/clock.h>
@@ -126,7 +126,7 @@ u32 get_cpu_speed_grade_hz(void)
 	val >>= OCOTP_CFG3_SPEED_SHIFT;
 	val &= 0x3;
 
-	if (is_mx6ul() || is_mx6ull()) {
+	if (is_mx6ul()) {
 		if (val == OCOTP_CFG3_SPEED_528MHZ)
 			return 528000000;
 		else if (val == OCOTP_CFG3_SPEED_696MHZ)
@@ -293,7 +293,7 @@ static void clear_mmdc_ch_mask(void)
 	reg = readl(&mxc_ccm->ccdr);
 
 	/* Clear MMDC channel mask */
-	if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl())
+	if (is_mx6sx() || is_mx6ul() || is_mx6sl())
 		reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK);
 	else
 		reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
@@ -314,12 +314,6 @@ static void init_bandgap(void)
 	 * be set.
 	 */
 	writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
-	/*
-	 * On i.MX6ULL, the LDO 1.2V bandgap voltage is 30mV higher. so set
-	 * VBGADJ bits to 2b'110 to adjust it.
-	 */
-	if (is_mx6ull())
-		writel(BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ, &anatop->ana_misc0_set);
 }
 
 
@@ -349,7 +343,7 @@ int arch_cpu_init(void)
 	 */
 	init_bandgap();
 
-	if (!is_mx6ul() && !is_mx6ull()) {
+	if (!IS_ENABLED(CONFIG_MX6UL)) {
 		/*
 		 * When low freq boot is enabled, ROM will not set AHB
 		 * freq, so we need to ensure AHB freq is 132MHz in such
@@ -362,41 +356,14 @@ int arch_cpu_init(void)
 			set_ahb_rate(132000000);
 	}
 
-	if (is_mx6ul()) {
-		if (is_soc_rev(CHIP_REV_1_0) == 0) {
-			/*
-			 * According to the design team's requirement on
-			 * i.MX6UL,the PMIC_STBY_REQ PAD should be configured
-			 * as open drain 100K (0x0000b8a0).
-			 * Only exists on TO1.0
-			 */
-			writel(0x0000b8a0, IOMUXC_BASE_ADDR + 0x29c);
-		} else {
-			/*
-			 * From TO1.1, SNVS adds internal pull up control
-			 * for POR_B, the register filed is GPBIT[1:0],
-			 * after system boot up, it can be set to 2b'01
-			 * to disable internal pull up.It can save about
-			 * 30uA power in SNVS mode.
-			 */
-			writel((readl(MX6UL_SNVS_LP_BASE_ADDR + 0x10) &
-			       (~0x1400)) | 0x400,
-			       MX6UL_SNVS_LP_BASE_ADDR + 0x10);
-		}
-	}
-
-	if (is_mx6ull()) {
+	if (IS_ENABLED(CONFIG_MX6UL) && is_soc_rev(CHIP_REV_1_0) == 0) {
 		/*
-		 * GPBIT[1:0] is suggested to set to 2'b11:
-		 * 2'b00 : always PUP100K
-		 * 2'b01 : PUP100K when PMIC_ON_REQ or SOC_NOT_FAIL
-		 * 2'b10 : always disable PUP100K
-		 * 2'b11 : PDN100K when SOC_FAIL, PUP100K when SOC_NOT_FAIL
-		 * register offset is different from i.MX6UL, since
-		 * i.MX6UL is fixed by ECO.
+		 * According to the design team's requirement on i.MX6UL,
+		 * the PMIC_STBY_REQ PAD should be configured as open
+		 * drain 100K (0x0000b8a0).
+		 * Only exists on TO1.0
 		 */
-		writel(readl(MX6UL_SNVS_LP_BASE_ADDR) |
-			0x3, MX6UL_SNVS_LP_BASE_ADDR);
+		writel(0x0000b8a0, IOMUXC_BASE_ADDR + 0x29c);
 	}
 
 	/* Set perclk to source from OSC 24MHz */
@@ -492,7 +459,7 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 	struct fuse_bank4_regs *fuse =
 			(struct fuse_bank4_regs *)bank->fuse_regs;
 
-	if ((is_mx6sx() || is_mx6ul() || is_mx6ull()) && dev_id == 1) {
+	if ((is_mx6sx() || is_mx6ul()) && dev_id == 1) {
 		u32 value = readl(&fuse->mac_addr2);
 		mac[0] = value >> 24 ;
 		mac[1] = value >> 16 ;
@@ -527,7 +494,7 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 const struct boot_mode soc_boot_modes[] = {
 	{"normal",	MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
 	/* reserved value should start rom usb */
-	{"usb",		MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
+	{"usb",		MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)},
 	{"sata",	MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
 	{"ecspi1:0",	MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
 	{"ecspi1:1",	MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
@@ -556,7 +523,7 @@ void s_init(void)
 	u32 mask528;
 	u32 reg, periph1, periph2;
 
-	if (is_mx6sx() || is_mx6ul() || is_mx6ull())
+	if (is_mx6sx() || is_mx6ul())
 		return;
 
 	/* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs

arch/arm/cpu/armv7/mx7/clock.c

@@ -10,7 +10,7 @@
 #include <common.h>
 #include <div64.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/clock.h>

arch/arm/cpu/armv7/mx7/clock_slice.c

@@ -10,7 +10,7 @@
 #include <common.h>
 #include <div64.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/clock.h>

arch/arm/cpu/armv7/omap-common/Kconfig

@@ -1,6 +1,6 @@
 config TI_SECURE_DEVICE
 	bool "HS Device Type Support"
-	depends on OMAP54XX || AM43XX || AM33XX
+	depends on OMAP54XX || AM43XX
 	help
 	  If a high secure (HS) device type is being used, this config
 	  must be set. This option impacts various aspects of the

arch/arm/cpu/armv7/omap-common/boot-common.c

@@ -90,11 +90,6 @@ void save_omap_boot_params(void)
 		case BOOT_DEVICE_CPGMAC:
 			sys_boot_device = 1;
 			break;
-#endif
-#if defined(BOOT_DEVICE_DFU) && !defined(CONFIG_SPL_DFU_SUPPORT)
-		case BOOT_DEVICE_DFU:
-			sys_boot_device = 1;
-			break;
 #endif
 	}
 

arch/arm/cpu/armv7/omap-common/emif-common.c

@@ -14,7 +14,6 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/omap_common.h>
-#include <asm/omap_sec_common.h>
 #include <asm/utils.h>
 #include <linux/compiler.h>
 
@@ -1478,20 +1477,6 @@ void sdram_init(void)
 			debug("get_ram_size() successful");
 	}
 
-#if defined(CONFIG_TI_SECURE_DEVICE)
-	/*
-	 * On HS devices, do static EMIF firewall configuration
-	 * but only do it if not already running in SDRAM
-	 */
-	if (!in_sdram)
-		if (0 != secure_emif_reserve())
-			hang();
-
-	/* On HS devices, ensure static EMIF firewall APIs are locked */
-	if (0 != secure_emif_firewall_lock())
-		hang();
-#endif
-
 	if (sdram_type == EMIF_SDRAM_TYPE_DDR3 &&
 	    (!in_sdram && !warm_reset()) && (!is_dra7xx())) {
 		if (emif1_enabled)

arch/arm/cpu/armv7/omap-common/lowlevel_init.S

@@ -24,30 +24,6 @@ ENTRY(save_boot_params)
 	str	r0, [r1]
 	b	save_boot_params_ret
 ENDPROC(save_boot_params)
-
-#if !defined(CONFIG_TI_SECURE_DEVICE) && defined(CONFIG_ARMV7_LPAE)
-ENTRY(switch_to_hypervisor)
-
-/*
- * Switch to hypervisor mode
- */
-	adr	r0, save_sp
-	str	sp, [r0]
-	adr	r1, restore_from_hyp
-	ldr	r0, =0x102
-	b	omap_smc1
-restore_from_hyp:
-	adr	r0, save_sp
-	ldr	sp, [r0]
-	MRC p15, 4, R0, c1, c0, 0
-	ldr     r1, =0X1004	@Set cache enable bits for hypervisor mode
-	orr     r0, r0, r1
-	MCR p15, 4, R0, c1, c0, 0
-	b	switch_to_hypervisor_ret
-save_sp:
-	.word	0x0
-ENDPROC(switch_to_hypervisor)
-#endif
 #endif
 
 ENTRY(omap_smc1)

arch/arm/cpu/armv7/omap-common/omap-cache.c

@@ -17,28 +17,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-/*
- * Without LPAE short descriptors are used
- * Set C - Cache Bit3
- * Set B - Buffer Bit2
- * The last 2 bits set to 0b10
- * Do Not set XN bit4
- * So value is 0xe
- *
- * With LPAE cache configuration happens via MAIR0 register
- * AttrIndx value is 0x3 for picking byte3 for MAIR0 which has 0xFF.
- * 0xFF maps to Cache writeback with Read and Write Allocate set
- * The bits[1:0] should have the value 0b01 for the first level
- * descriptor.
- * So the value is 0xd
- */
-
-#ifdef CONFIG_ARMV7_LPAE
-#define ARMV7_DCACHE_POLICY	DCACHE_WRITEALLOC
-#else
-#define ARMV7_DCACHE_POLICY	DCACHE_WRITEBACK & ~TTB_SECT_XN_MASK
-#endif
-
+#define ARMV7_DCACHE_WRITEBACK  0xe
 #define ARMV7_DOMAIN_CLIENT	1
 #define ARMV7_DOMAIN_MASK	(0x3 << 0)
 
@@ -53,13 +32,13 @@ void dram_bank_mmu_setup(int bank)
 	bd_t *bd = gd->bd;
 	int	i;
 
-	u32 start = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;
-	u32 size = bd->bi_dram[bank].size >> MMU_SECTION_SHIFT;
+	u32 start = bd->bi_dram[bank].start >> 20;
+	u32 size = bd->bi_dram[bank].size >> 20;
 	u32 end = start + size;
 
 	debug("%s: bank: %d\n", __func__, bank);
 	for (i = start; i < end; i++)
-		set_section_dcache(i, ARMV7_DCACHE_POLICY);
+		set_section_dcache(i, ARMV7_DCACHE_WRITEBACK);
 }
 
 void arm_init_domains(void)

arch/arm/cpu/armv7/omap-common/pipe3-phy.c

@@ -12,7 +12,7 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include "pipe3-phy.h"
 
 /* PLLCTRL Registers */

arch/arm/cpu/armv7/omap3/Kconfig

@@ -1,38 +1,5 @@
 if OMAP34XX
 
-config SPL_EXT_SUPPORT
-	default y
-
-config SPL_FAT_SUPPORT
-	default y
-
-config SPL_GPIO_SUPPORT
-	default y
-
-config SPL_I2C_SUPPORT
-	default y
-
-config SPL_LIBCOMMON_SUPPORT
-	default y
-
-config SPL_LIBDISK_SUPPORT
-	default y
-
-config SPL_LIBGENERIC_SUPPORT
-	default y
-
-config SPL_MMC_SUPPORT
-	default y
-
-config SPL_NAND_SUPPORT
-	default y
-
-config SPL_POWER_SUPPORT
-	default y
-
-config SPL_SERIAL_SUPPORT
-	default y
-
 choice
 	prompt "OMAP3 board select"
 	optional

arch/arm/cpu/armv7/omap4/Kconfig

@@ -1,41 +1,5 @@
 if OMAP44XX
 
-config SPL_EXT_SUPPORT
-	default y
-
-config SPL_FAT_SUPPORT
-	default y
-
-config SPL_GPIO_SUPPORT
-	default y
-
-config SPL_I2C_SUPPORT
-	default y
-
-config SPL_LIBCOMMON_SUPPORT
-	default y
-
-config SPL_LIBDISK_SUPPORT
-	default y
-
-config SPL_LIBGENERIC_SUPPORT
-	default y
-
-config SPL_MMC_SUPPORT
-	default y
-
-config SPL_NAND_SUPPORT
-	default y
-
-config SPL_POWER_SUPPORT
-	default y
-
-config SPL_SERIAL_SUPPORT
-	default y
-
-config SPL_DISPLAY_PRINT
-	default y
-
 choice
 	prompt "OMAP4 board select"
 	optional

arch/arm/cpu/armv7/omap5/Kconfig

@@ -1,41 +1,5 @@
 if OMAP54XX
 
-config SPL_EXT_SUPPORT
-	default y
-
-config SPL_FAT_SUPPORT
-	default y
-
-config SPL_GPIO_SUPPORT
-	default y
-
-config SPL_I2C_SUPPORT
-	default y
-
-config SPL_LIBCOMMON_SUPPORT
-	default y
-
-config SPL_LIBDISK_SUPPORT
-	default y
-
-config SPL_LIBGENERIC_SUPPORT
-	default y
-
-config SPL_MMC_SUPPORT
-	default y
-
-config SPL_NAND_SUPPORT
-	default y
-
-config SPL_POWER_SUPPORT
-	default y
-
-config SPL_SERIAL_SUPPORT
-	default y
-
-config SPL_DISPLAY_PRINT
-	default y
-
 choice
 	prompt "OMAP5 board select"
 	optional
@@ -60,32 +24,6 @@ endchoice
 config SYS_SOC
 	default "omap5"
 
-config TI_SECURE_EMIF_REGION_START
-	hex "Reserved EMIF region start address"
-	depends on TI_SECURE_DEVICE
-	default 0x0
-	help
-	  Reserved EMIF region start address. Set to "0" to auto-select
-	  to be at the end of the external memory region.
-
-config TI_SECURE_EMIF_TOTAL_REGION_SIZE
-	hex "Reserved EMIF region size"
-	depends on TI_SECURE_DEVICE
-	default 0x0
-	help
-	  Total reserved EMIF region size. Default is 0, which means no reserved EMIF
-	  region on secure devices.
-
-config TI_SECURE_EMIF_PROTECTED_REGION_SIZE
-	hex "Size of protected region within reserved EMIF region"
-	depends on TI_SECURE_DEVICE
-	default 0x0
-	help
-	  This config option is used to specify the size of the portion of the total
-	  reserved EMIF region set aside for secure OS needs that will  be protected
-	  using hardware memory firewalls. This value must be smaller than the
-	  TI_SECURE_EMIF_TOTAL_REGION_SIZE value.
-
 source "board/compulab/cm_t54/Kconfig"
 source "board/ti/omap5_uevm/Kconfig"
 source "board/ti/dra7xx/Kconfig"

arch/arm/cpu/armv7/omap5/Makefile

@@ -14,4 +14,3 @@ obj-y	+= hw_data.o
 obj-y	+= abb.o
 obj-y	+= fdt.o
 obj-$(CONFIG_IODELAY_RECALIBRATION) += dra7xx_iodelay.o
-obj-$(CONFIG_TI_SECURE_DEVICE) += sec-fxns.o

arch/arm/cpu/armv7/omap5/fdt.c

@@ -153,73 +153,13 @@ static int ft_hs_fixup_sram(void *fdt, bd_t *bd)
 static int ft_hs_fixup_sram(void *fdt, bd_t *bd) { return 0; }
 #endif
 
-#if (CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE != 0)
-static int ft_hs_fixup_dram(void *fdt, bd_t *bd)
-{
-	const char *path, *subpath;
-	int offs;
-	u32 sec_mem_start = CONFIG_TI_SECURE_EMIF_REGION_START;
-	u32 sec_mem_size = CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE;
-	fdt64_t temp[2];
-
-	/* If start address is zero, place at end of DRAM */
-	if (0 == sec_mem_start)
-		sec_mem_start =
-			(CONFIG_SYS_SDRAM_BASE +
-			(omap_sdram_size() - sec_mem_size));
-
-	/* Delete any original secure_reserved node */
-	path = "/reserved-memory/secure_reserved";
-	offs = fdt_path_offset(fdt, path);
-	if (offs >= 0)
-		fdt_del_node(fdt, offs);
-
-	/* Add new secure_reserved node */
-	path = "/reserved-memory";
-	offs = fdt_path_offset(fdt, path);
-	if (offs < 0) {
-		debug("Node %s not found\n", path);
-		path = "/";
-		subpath = "reserved-memory";
-		fdt_path_offset(fdt, path);
-		offs = fdt_add_subnode(fdt, offs, subpath);
-		if (offs < 0) {
-			printf("Could not create %s%s node.\n", path, subpath);
-			return 1;
-		}
-		path = "/reserved-memory";
-		offs = fdt_path_offset(fdt, path);
-	}
-
-	subpath = "secure_reserved";
-	offs = fdt_add_subnode(fdt, offs, subpath);
-	if (offs < 0) {
-		printf("Could not create %s%s node.\n", path, subpath);
-		return 1;
-	}
-
-	temp[0] = cpu_to_fdt64(((u64)sec_mem_start));
-	temp[1] = cpu_to_fdt64(((u64)sec_mem_size));
-	fdt_setprop_string(fdt, offs, "compatible",
-			   "ti,dra7-secure-memory");
-	fdt_setprop_string(fdt, offs, "status", "okay");
-	fdt_setprop(fdt, offs, "no-map", NULL, 0);
-	fdt_setprop(fdt, offs, "reg", temp, sizeof(temp));
-
-	return 0;
-}
-#else
-static int ft_hs_fixup_dram(void *fdt, bd_t *bd) { return 0; }
-#endif
-
 static void ft_hs_fixups(void *fdt, bd_t *bd)
 {
 	/* Check we are running on an HS/EMU device type */
 	if (GP_DEVICE != get_device_type()) {
 		if ((ft_hs_fixup_crossbar(fdt, bd) == 0) &&
 		    (ft_hs_disable_rng(fdt, bd) == 0) &&
-		    (ft_hs_fixup_sram(fdt, bd) == 0) &&
-		    (ft_hs_fixup_dram(fdt, bd) == 0))
+		    (ft_hs_fixup_sram(fdt, bd) == 0))
 			return;
 	} else {
 		printf("ERROR: Incorrect device type (GP) detected!");
@@ -231,7 +171,7 @@ static void ft_hs_fixups(void *fdt, bd_t *bd)
 static void ft_hs_fixups(void *fdt, bd_t *bd)
 {
 }
-#endif /* #ifdef CONFIG_TI_SECURE_DEVICE */
+#endif
 
 /*
  * Place for general cpu/SoC FDT fixups. Board specific

arch/arm/cpu/armv7/omap5/sec-fxns.c

@@ -1,126 +0,0 @@
-/*
- *
- * Security related functions for OMAP5 class devices
- *
- * (C) Copyright 2016
- * Texas Instruments, <www.ti.com>
- *
- * Daniel Allred <d-allred@ti.com>
- * Harinarayan Bhatta <harinarayan@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <stdarg.h>
-
-#include <asm/arch/sys_proto.h>
-#include <asm/omap_common.h>
-#include <asm/omap_sec_common.h>
-#include <asm/spl.h>
-#include <spl.h>
-
-/* Index for signature PPA-based TI HAL APIs */
-#define PPA_HAL_SERVICES_START_INDEX        (0x200)
-#define PPA_SERV_HAL_SETUP_SEC_RESVD_REGION (PPA_HAL_SERVICES_START_INDEX + 25)
-#define PPA_SERV_HAL_SETUP_EMIF_FW_REGION   (PPA_HAL_SERVICES_START_INDEX + 26)
-#define PPA_SERV_HAL_LOCK_EMIF_FW           (PPA_HAL_SERVICES_START_INDEX + 27)
-
-static u32 get_sec_mem_start(void)
-{
-	u32 sec_mem_start = CONFIG_TI_SECURE_EMIF_REGION_START;
-	u32 sec_mem_size = CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE;
-	/*
-	 * Total reserved region is all contiguous with protected
-	 * region coming first, followed by the non-secure region.
-	 * If 0x0 start address is given, we simply put the reserved
-	 * region at the end of the external DRAM.
-	 */
-	if (sec_mem_start == 0)
-		sec_mem_start =
-			(CONFIG_SYS_SDRAM_BASE +
-			(omap_sdram_size() - sec_mem_size));
-	return sec_mem_start;
-}
-
-int secure_emif_firewall_setup(uint8_t region_num, uint32_t start_addr,
-			       uint32_t size, uint32_t access_perm,
-			       uint32_t initiator_perm)
-{
-	int result = 1;
-
-	/*
-	 * Call PPA HAL API to do any other general firewall
-	 * configuration for regions 1-6 of the EMIF firewall.
-	 */
-	debug("%s: regionNum = %x, startAddr = %x, size = %x", __func__,
-	      region_num, start_addr, size);
-
-	result = secure_rom_call(
-			PPA_SERV_HAL_SETUP_EMIF_FW_REGION, 0, 0, 4,
-			(start_addr & 0xFFFFFFF0) | (region_num & 0x0F),
-			size, access_perm, initiator_perm);
-
-	if (result != 0) {
-		puts("Secure EMIF Firewall Setup failed!\n");
-		debug("Return Value = %x\n", result);
-	}
-
-	return result;
-}
-
-#if	(CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE <  \
-	CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE)
-#error	"TI Secure EMIF: Protected size cannot be larger than total size."
-#endif
-int secure_emif_reserve(void)
-{
-	int result = 1;
-	u32 sec_mem_start = get_sec_mem_start();
-	u32 sec_prot_size = CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE;
-
-	/* If there is no protected region, there is no reservation to make */
-	if (sec_prot_size == 0)
-		return 0;
-
-	/*
-	 * Call PPA HAL API to reserve a chunk of EMIF SDRAM
-	 * for secure world use. This region should be carved out
-	 * from use by any public code. EMIF firewall region 7
-	 * will be used to protect this block of memory.
-	 */
-	result = secure_rom_call(
-			PPA_SERV_HAL_SETUP_SEC_RESVD_REGION,
-			0, 0, 2, sec_mem_start, sec_prot_size);
-
-	if (result != 0) {
-		puts("SDRAM Firewall: Secure memory reservation failed!\n");
-		debug("Return Value = %x\n", result);
-	}
-
-	return result;
-}
-
-int secure_emif_firewall_lock(void)
-{
-	int result = 1;
-
-	/*
-	 * Call PPA HAL API to lock the EMIF firewall configurations.
-	 * After this API is called, none of the PPA HAL APIs for
-	 * configuring the EMIF firewalls will be usable again (that
-	 * is, calls to those APIs will return failure and have no
-	 * effect).
-	 */
-
-	result = secure_rom_call(
-			PPA_SERV_HAL_LOCK_EMIF_FW,
-			0, 0, 0);
-
-	if (result != 0) {
-		puts("Secure EMIF Firewall Lock failed!\n");
-		debug("Return Value = %x\n", result);
-	}
-
-	return result;
-}

arch/arm/cpu/armv7/psci.S

@@ -187,7 +187,7 @@ ENDPROC(psci_get_cpu_id)
 .weak psci_get_cpu_id
 
 /* Imported from Linux kernel */
-ENTRY(psci_v7_flush_dcache_all)
+LENTRY(v7_flush_dcache_all)
 	stmfd	sp!, {r4-r5, r7, r9-r11, lr}
 	dmb					@ ensure ordering with previous memory accesses
 	mrc	p15, 1, r0, c0, c0, 1		@ read clidr
@@ -234,7 +234,7 @@ finished:
 	isb
 	ldmfd	sp!, {r4-r5, r7, r9-r11, lr}
 	bx	lr
-ENDPROC(psci_v7_flush_dcache_all)
+ENDPROC(v7_flush_dcache_all)
 
 ENTRY(psci_disable_smp)
 	mrc	p15, 0, r0, c1, c0, 1		@ ACTLR
@@ -264,7 +264,7 @@ ENTRY(psci_cpu_off_common)
 	isb
 	dsb
 
-	bl	psci_v7_flush_dcache_all
+	bl	v7_flush_dcache_all
 
 	clrex					@ Why???
 

arch/arm/cpu/armv7/start.S

@@ -17,7 +17,6 @@
 #include <config.h>
 #include <asm/system.h>
 #include <linux/linkage.h>
-#include <asm/armv7.h>
 
 /*************************************************************************
  *
@@ -31,24 +30,11 @@
 
 	.globl	reset
 	.globl	save_boot_params_ret
-#ifdef CONFIG_ARMV7_LPAE
-	.global	switch_to_hypervisor_ret
-#endif
 
 reset:
 	/* Allow the board to save important registers */
 	b	save_boot_params
 save_boot_params_ret:
-#ifdef CONFIG_ARMV7_LPAE
-/*
- * check for Hypervisor support
- */
-	mrc	p15, 0, r0, c0, c1, 1		@ read ID_PFR1
-	and	r0, r0, #CPUID_ARM_VIRT_MASK	@ mask virtualization bits
-	cmp	r0, #(1 << CPUID_ARM_VIRT_SHIFT)
-	beq	switch_to_hypervisor
-switch_to_hypervisor_ret:
-#endif
 	/*
 	 * disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode,
 	 * except if in HYP mode already
@@ -117,13 +103,6 @@ ENTRY(save_boot_params)
 ENDPROC(save_boot_params)
 	.weak	save_boot_params
 
-#ifdef CONFIG_ARMV7_LPAE
-ENTRY(switch_to_hypervisor)
-	b	switch_to_hypervisor_ret
-ENDPROC(switch_to_hypervisor)
-	.weak	switch_to_hypervisor
-#endif
-
 /*************************************************************************
  *
  * cpu_init_cp15

arch/arm/cpu/armv7/vf610/Makefile

@@ -6,8 +6,3 @@
 
 obj-y	+= generic.o
 obj-y	+= timer.o
-
-MKIMAGEFLAGS_u-boot.vyb = -T vybridimage
-
-u-boot.vyb: u-boot.imx
-	$(call if_changed,mkimage)

arch/arm/cpu/armv7/vf610/generic.c

@@ -322,7 +322,7 @@ int arch_misc_init(void)
 {
 	char soc[6];
 
-	strcpy(soc, "vf");
+	strcat(soc, "vf");
 	strcat(soc, soc_type);
 	setenv("soc", soc);
 

arch/arm/cpu/armv8/Kconfig

@@ -21,22 +21,4 @@ config ARMV8_SPIN_TABLE
 	    - Reserve the code for the spin-table and the release address
 	      via a /memreserve/ region in the Device Tree.
 
-config PSCI_RESET
-	bool "Use PSCI for reset and shutdown"
-	default y
-	depends on !ARCH_EXYNOS7 && !ARCH_BCM283X && !TARGET_LS2080A_EMU && \
-		   !TARGET_LS2080A_SIMU && !TARGET_LS2080AQDS && \
-		   !TARGET_LS2080ARDB && !TARGET_LS1012AQDS && \
-		   !TARGET_LS1012ARDB && !TARGET_LS1012AFRDM && \
-		   !TARGET_LS1043ARDB && !ARCH_UNIPHIER && !ARCH_SNAPDRAGON && \
-		   !TARGET_S32V234EVB
-	help
-	  Most armv8 systems have PSCI support enabled in EL3, either through
-	  ARM Trusted Firmware or other firmware.
-
-	  On these systems, we do not need to implement system reset manually,
-	  but can instead rely on higher level firmware to deal with it.
-
-	  Select Y here to make use of PSCI calls for system reset
-
 endif

arch/arm/cpu/armv8/cache.S

@@ -150,23 +150,11 @@ ENTRY(__asm_invalidate_icache_all)
 	ret
 ENDPROC(__asm_invalidate_icache_all)
 
-ENTRY(__asm_invalidate_l3_dcache)
+ENTRY(__asm_flush_l3_cache)
 	mov	x0, #0			/* return status as success */
 	ret
-ENDPROC(__asm_invalidate_l3_dcache)
-	.weak	__asm_invalidate_l3_dcache
-
-ENTRY(__asm_flush_l3_dcache)
-	mov	x0, #0			/* return status as success */
-	ret
-ENDPROC(__asm_flush_l3_dcache)
-	.weak	__asm_flush_l3_dcache
-
-ENTRY(__asm_invalidate_l3_icache)
-	mov	x0, #0			/* return status as success */
-	ret
-ENDPROC(__asm_invalidate_l3_icache)
-	.weak	__asm_invalidate_l3_icache
+ENDPROC(__asm_flush_l3_cache)
+	.weak	__asm_flush_l3_cache
 
 /*
  * void __asm_switch_ttbr(ulong new_ttbr)

arch/arm/cpu/armv8/cache_v8.c

@@ -421,20 +421,19 @@ __weak void mmu_setup(void)
 void invalidate_dcache_all(void)
 {
 	__asm_invalidate_dcache_all();
-	__asm_invalidate_l3_dcache();
 }
 
 /*
  * Performs a clean & invalidation of the entire data cache at all levels.
  * This function needs to be inline to avoid using stack.
- * __asm_flush_l3_dcache return status of timeout
+ * __asm_flush_l3_cache return status of timeout
  */
 inline void flush_dcache_all(void)
 {
 	int ret;
 
 	__asm_flush_dcache_all();
-	ret = __asm_flush_l3_dcache();
+	ret = __asm_flush_l3_cache();
 	if (ret)
 		debug("flushing dcache returns 0x%x\n", ret);
 	else
@@ -624,7 +623,7 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
 
 void icache_enable(void)
 {
-	invalidate_icache_all();
+	__asm_invalidate_icache_all();
 	set_sctlr(get_sctlr() | CR_I);
 }
 
@@ -641,7 +640,6 @@ int icache_status(void)
 void invalidate_icache_all(void)
 {
 	__asm_invalidate_icache_all();
-	__asm_invalidate_l3_icache();
 }
 
 #else	/* CONFIG_SYS_ICACHE_OFF */

arch/arm/cpu/armv8/fsl-layerscape/Kconfig

@@ -1,138 +0,0 @@
-config ARCH_LS1012A
-	bool
-	select FSL_LSCH2
-	select SYS_FSL_DDR_BE
-	select SYS_FSL_MMDC
-	select SYS_FSL_ERRATUM_A010315
-
-config ARCH_LS1043A
-	bool
-	select FSL_LSCH2
-	select SYS_FSL_DDR_BE
-	select SYS_FSL_DDR_VER_50
-	select SYS_FSL_ERRATUM_A010315
-	select SYS_FSL_ERRATUM_A010539
-
-config ARCH_LS1046A
-	bool
-	select FSL_LSCH2
-	select SYS_FSL_DDR_BE
-	select SYS_FSL_DDR4
-	select SYS_FSL_DDR_VER_50
-	select SYS_FSL_ERRATUM_A010539
-	select SYS_FSL_SRDS_2
-
-config ARCH_LS2080A
-	bool
-	select FSL_LSCH3
-	select SYS_FSL_DDR4
-	select SYS_FSL_DDR_LE
-	select SYS_FSL_DDR_VER_50
-	select SYS_FSL_HAS_DP_DDR
-	select SYS_FSL_SRDS_2
-
-config FSL_LSCH2
-	bool
-	select SYS_FSL_SRDS_1
-	select SYS_HAS_SERDES
-
-config FSL_LSCH3
-	bool
-	select SYS_FSL_SRDS_1
-	select SYS_HAS_SERDES
-
-menu "Layerscape architecture"
-	depends on FSL_LSCH2 || FSL_LSCH3
-
-config SYS_FSL_MMDC
-	bool
-
-config SYS_FSL_ERRATUM_A010315
-	bool "Workaround for PCIe erratum A010315"
-
-config SYS_FSL_ERRATUM_A010539
-	bool "Workaround for PIN MUX erratum A010539"
-
-config MAX_CPUS
-	int "Maximum number of CPUs permitted for Layerscape"
-	default 4 if ARCH_LS1043A
-	default 4 if ARCH_LS1046A
-	default 16 if ARCH_LS2080A
-	default 1
-	help
-	  Set this number to the maximum number of possible CPUs in the SoC.
-	  SoCs may have multiple clusters with each cluster may have multiple
-	  ports. If some ports are reserved but higher ports are used for
-	  cores, count the reserved ports. This will allocate enough memory
-	  in spin table to properly handle all cores.
-
-config NUM_DDR_CONTROLLERS
-	int "Maximum DDR controllers"
-	default 3 if ARCH_LS2080A
-	default 1
-
-config SYS_FSL_IFC_BANK_COUNT
-	int "Maximum banks of Integrated flash controller"
-	depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
-	default 4 if ARCH_LS1043A
-	default 4 if ARCH_LS1046A
-	default 8 if ARCH_LS2080A
-
-config SYS_FSL_HAS_DP_DDR
-	bool
-
-config SYS_FSL_SRDS_1
-	bool
-
-config SYS_FSL_SRDS_2
-	bool
-
-config SYS_HAS_SERDES
-	bool
-
-config SYS_FSL_DDR
-	bool "Freescale DDR driver"
-	help
-	  Select Freescale General DDR driver, shared between most Freescale
-	  PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM-
-	  based Layerscape SoCs (such as ls2080a).
-
-config SYS_FSL_DDR_BE
-	bool
-	help
-	  Access DDR registers in big-endian.
-
-config SYS_FSL_DDR_LE
-	bool
-	help
-	  Access DDR registers in little-endian.
-
-config SYS_FSL_DDR_VER
-	int
-	default 50 if SYS_FSL_DDR_VER_50
-
-config SYS_FSL_DDR_VER_50
-	bool
-
-config SYS_FSL_DDRC_ARM_GEN3
-	bool
-
-config SYS_FSL_DDRC_GEN4
-	bool
-
-config SYS_FSL_DDR3
-	bool "Freescale DDR3 controller"
-	depends on !SYS_FSL_DDR4
-	select SYS_FSL_DDR
-	select SYS_FSL_DDRC_ARM_GEN3
-	help
-	  Enable Freescale DDR3 controller on ARM-based SoCs.
-
-config SYS_FSL_DDR4
-	bool "Freescale DDR4 controller"
-	select SYS_FSL_DDR
-	select SYS_FSL_DDRC_GEN4
-	help
-	  Enable Freescale DDR4 controller.
-
-endmenu

arch/arm/cpu/armv8/fsl-layerscape/Makefile

@@ -30,10 +30,10 @@ ifneq ($(CONFIG_LS1043A),)
 obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o
 endif
 
-ifneq ($(CONFIG_ARCH_LS1012A),)
+ifneq ($(CONFIG_LS1012A),)
 obj-$(CONFIG_SYS_HAS_SERDES) += ls1012a_serdes.o
 endif
 
-ifneq ($(CONFIG_ARCH_LS1046A),)
+ifneq ($(CONFIG_LS1046A),)
 obj-$(CONFIG_SYS_HAS_SERDES) += ls1046a_serdes.o
 endif

arch/arm/cpu/armv8/fsl-layerscape/cpu.c

@@ -6,7 +6,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/system.h>
 #include <asm/armv8/mmu.h>
 #include <asm/io.h>
@@ -18,6 +18,7 @@
 #include <asm/arch/mp.h>
 #endif
 #include <fm_eth.h>
+#include <fsl_debug_server.h>
 #include <fsl-mc/fsl_mc.h>
 #ifdef CONFIG_FSL_ESDHC
 #include <fsl_esdhc.h>
@@ -44,9 +45,6 @@ void cpu_name(char *name)
 
 			if (IS_E_PROCESSOR(svr))
 				strcat(name, "E");
-
-			sprintf(name + strlen(name), " Rev%d.%d",
-				SVR_MAJ(svr), SVR_MIN(svr));
 			break;
 		}
 
@@ -203,27 +201,6 @@ static inline u32 initiator_type(u32 cluster, int init_id)
 	return 0;
 }
 
-u32 cpu_pos_mask(void)
-{
-	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
-	int i = 0;
-	u32 cluster, type, mask = 0;
-
-	do {
-		int j;
-
-		cluster = gur_in32(&gur->tp_cluster[i].lower);
-		for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
-			type = initiator_type(cluster, j);
-			if (type && (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM))
-				mask |= 1 << (i * TP_INIT_PER_CLUSTER + j);
-		}
-		i++;
-	} while ((cluster & TP_CLUSTER_EOC) == 0x0);
-
-	return mask;
-}
-
 u32 cpu_mask(void)
 {
 	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
@@ -480,6 +457,10 @@ phys_size_t board_reserve_ram_top(phys_size_t ram_size)
 #ifdef CONFIG_SYS_MEM_TOP_HIDE
 #error CONFIG_SYS_MEM_TOP_HIDE not to be used together with this function
 #endif
+/* Carve the Debug Server private DRAM block from the end of DRAM */
+#ifdef CONFIG_FSL_DEBUG_SERVER
+	ram_top -= debug_server_get_dram_block_size();
+#endif
 
 /* Carve the MC private DRAM block from the end of DRAM */
 #ifdef CONFIG_FSL_MC_ENET

arch/arm/cpu/armv8/fsl-layerscape/fdt.c

@@ -108,24 +108,6 @@ remove_psci_node:
 }
 #endif
 
-void fsl_fdt_disable_usb(void *blob)
-{
-	int off;
-	/*
-	 * SYSCLK is used as a reference clock for USB. When the USB
-	 * controller is used, SYSCLK must meet the additional requirement
-	 * of 100 MHz.
-	 */
-	if (CONFIG_SYS_CLK_FREQ != 100000000) {
-		off = fdt_node_offset_by_compatible(blob, -1, "snps,dwc3");
-		while (off != -FDT_ERR_NOTFOUND) {
-			fdt_status_disabled(blob, off);
-			off = fdt_node_offset_by_compatible(blob, off,
-							    "snps,dwc3");
-		}
-	}
-}
-
 void ft_cpu_setup(void *blob, bd_t *bd)
 {
 #ifdef CONFIG_FSL_LSCH2
@@ -168,6 +150,4 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 #ifdef CONFIG_SYS_DPAA_FMAN
 	fdt_fixup_fman_firmware(blob);
 #endif
-	fsl_fdt_disable_usb(blob);
-
 }

arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c

@@ -6,7 +6,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/fsl_serdes.h>
 #include <asm/arch/soc.h>
 
@@ -22,15 +22,9 @@ int is_serdes_configured(enum srds_prtcl device)
 	int ret = 0;
 
 #ifdef CONFIG_SYS_FSL_SRDS_1
-	if (!serdes1_prtcl_map[NONE])
-		fsl_serdes_init();
-
 	ret |= serdes1_prtcl_map[device];
 #endif
 #ifdef CONFIG_SYS_FSL_SRDS_2
-	if (!serdes2_prtcl_map[NONE])
-		fsl_serdes_init();
-
 	ret |= serdes2_prtcl_map[device];
 #endif
 
@@ -104,9 +98,6 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
 	u32 cfg;
 	int lane;
 
-	if (serdes_prtcl_map[NONE])
-		return;
-
 	memset(serdes_prtcl_map, 0, sizeof(u8) * SERDES_PRCTL_COUNT);
 
 	cfg = gur_in32(&gur->rcwsr[4]) & sd_prctl_mask;
@@ -124,9 +115,6 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
 		else
 			serdes_prtcl_map[lane_prtcl] = 1;
 	}
-
-	/* Set the first element to indicate serdes has been initialized */
-	serdes_prtcl_map[NONE] = 1;
 }
 
 void fsl_serdes_init(void)

arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c

@@ -60,7 +60,7 @@ void get_sys_info(struct sys_info *sys_info)
 	sys_info->freq_ddrbus = sysclk;
 #endif
 
-#ifdef CONFIG_ARCH_LS1012A
+#ifdef CONFIG_LS1012A
 	sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
 			FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
 			FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
@@ -91,7 +91,7 @@ void get_sys_info(struct sys_info *sys_info)
 			freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
 	}
 
-#ifdef CONFIG_ARCH_LS1012A
+#ifdef CONFIG_LS1012A
 	sys_info->freq_systembus = sys_info->freq_ddrbus / 2;
 	sys_info->freq_ddrbus *= 2;
 #endif

arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c

@@ -6,7 +6,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/fsl_serdes.h>
 #include <asm/arch/soc.h>
 #include <fsl-mc/ldpaa_wriop.h>
@@ -28,15 +28,9 @@ int is_serdes_configured(enum srds_prtcl device)
 	int ret = 0;
 
 #ifdef CONFIG_SYS_FSL_SRDS_1
-	if (!serdes1_prtcl_map[NONE])
-		fsl_serdes_init();
-
 	ret |= serdes1_prtcl_map[device];
 #endif
 #ifdef CONFIG_SYS_FSL_SRDS_2
-	if (!serdes2_prtcl_map[NONE])
-		fsl_serdes_init();
-
 	ret |= serdes2_prtcl_map[device];
 #endif
 
@@ -85,9 +79,6 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
 	u32 cfg;
 	int lane;
 
-	if (serdes_prtcl_map[NONE])
-		return;
-
 	memset(serdes_prtcl_map, 0, sizeof(u8) * SERDES_PRCTL_COUNT);
 
 	cfg = gur_in32(&gur->rcwsr[28]) & sd_prctl_mask;
@@ -145,9 +136,6 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
 #endif
 		}
 	}
-
-	/* Set the first element to indicate serdes has been initialized */
-	serdes_prtcl_map[NONE] = 1;
 }
 
 void fsl_serdes_init(void)

arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S

@@ -179,21 +179,6 @@ ENTRY(lowlevel_init)
 	isb
 	dsb	sy
 #endif
-
-#ifdef CONFIG_ARCH_LS1046A
-	/* Initialize the L2 RAM latency */
-	mrs   x1, S3_1_c11_c0_2
-	mov   x0, #0x1C7
-	/* Clear L2 Tag RAM latency and L2 Data RAM latency */
-	bic   x1, x1, x0
-	/* Set L2 data ram latency bits [2:0] */
-	orr   x1, x1, #0x2
-	/* set L2 tag ram latency bits [8:6] */
-	orr   x1,  x1, #0x80
-	msr   S3_1_c11_c0_2, x1
-	isb
-#endif
-
 	mov	lr, x29			/* Restore LR */
 	ret
 ENDPROC(lowlevel_init)
@@ -245,7 +230,7 @@ hnf_set_pstate:
 
 	ret
 
-ENTRY(__asm_flush_l3_dcache)
+ENTRY(__asm_flush_l3_cache)
 	/*
 	 * Return status in x0
 	 *    success 0
@@ -275,7 +260,7 @@ ENTRY(__asm_flush_l3_dcache)
 	mov	x0, x8
 	mov	lr, x29
 	ret
-ENDPROC(__asm_flush_l3_dcache)
+ENDPROC(__asm_flush_l3_cache)
 #endif
 
 #ifdef CONFIG_MP

arch/arm/cpu/armv8/fsl-layerscape/mp.c

@@ -104,11 +104,6 @@ int is_core_valid(unsigned int core)
 	return !!((1 << core) & cpu_mask());
 }
 
-static int is_pos_valid(unsigned int pos)
-{
-	return !!((1 << pos) & cpu_pos_mask());
-}
-
 int is_core_online(u64 cpu_id)
 {
 	u64 *table;
@@ -131,9 +126,9 @@ int cpu_disable(int nr)
 	return 0;
 }
 
-static int core_to_pos(int nr)
+int core_to_pos(int nr)
 {
-	u32 cores = cpu_pos_mask();
+	u32 cores = cpu_mask();
 	int i, count = 0;
 
 	if (nr == 0) {
@@ -144,17 +139,14 @@ static int core_to_pos(int nr)
 	}
 
 	for (i = 1; i < 32; i++) {
-		if (is_pos_valid(i)) {
+		if (is_core_valid(i)) {
 			count++;
 			if (count == nr)
 				break;
 		}
 	}
 
-	if (count != nr)
-		return -1;
-
-	return i;
+	return count;
 }
 
 int cpu_status(int nr)

arch/arm/cpu/armv8/fsl-layerscape/ppa.c

@@ -17,9 +17,6 @@
 #ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
 #include <asm/armv8/sec_firmware.h>
 #endif
-#ifdef CONFIG_CHAIN_OF_TRUST
-#include <fsl_validate.h>
-#endif
 
 int ppa_init(void)
 {
@@ -27,30 +24,12 @@ int ppa_init(void)
 	u32 *boot_loc_ptr_l, *boot_loc_ptr_h;
 	int ret;
 
-#ifdef CONFIG_CHAIN_OF_TRUST
-	uintptr_t ppa_esbc_hdr = CONFIG_SYS_LS_PPA_ESBC_ADDR;
-	uintptr_t ppa_img_addr = 0;
-#endif
-
 #ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP
 	ppa_fit_addr = (void *)CONFIG_SYS_LS_PPA_FW_ADDR;
 #else
 #error "No CONFIG_SYS_LS_PPA_FW_IN_xxx defined"
 #endif
 
-#ifdef CONFIG_CHAIN_OF_TRUST
-	ppa_img_addr = (uintptr_t)ppa_fit_addr;
-	if (fsl_check_boot_mode_secure() != 0) {
-		ret = fsl_secboot_validate(ppa_esbc_hdr,
-					   CONFIG_PPA_KEY_HASH,
-					   &ppa_img_addr);
-		if (ret != 0)
-			printf("PPA validation failed\n");
-		else
-			printf("PPA validation Successful\n");
-	}
-#endif
-
 #ifdef CONFIG_FSL_LSCH3
 	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 	boot_loc_ptr_l = &gur->bootlocptrl;

arch/arm/cpu/armv8/fsl-layerscape/soc.c

@@ -8,14 +8,10 @@
 #include <fsl_ifc.h>
 #include <ahci.h>
 #include <scsi.h>
-#include <asm/arch/fsl_serdes.h>
 #include <asm/arch/soc.h>
 #include <asm/io.h>
 #include <asm/global_data.h>
 #include <asm/arch-fsl-layerscape/config.h>
-#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
-#include <fsl_csu.h>
-#endif
 #ifdef CONFIG_SYS_FSL_DDR
 #include <fsl_ddr_sdram.h>
 #include <fsl_ddr.h>
@@ -62,13 +58,11 @@ static void erratum_a008336(void)
 #ifdef CONFIG_SYS_FSL_ERRATUM_A008336
 #ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR
 	eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
-	if (fsl_ddr_get_version(0) == 0x50200)
-		out_le32(eddrtqcr1, 0x63b30002);
+	out_le32(eddrtqcr1, 0x63b30002);
 #endif
 #ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR
 	eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
-	if (fsl_ddr_get_version(0) == 0x50200)
-		out_le32(eddrtqcr1, 0x63b30002);
+	out_le32(eddrtqcr1, 0x63b30002);
 #endif
 #endif
 }
@@ -228,13 +222,10 @@ int sata_init(void)
 {
 	struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA;
 
-#ifdef CONFIG_ARCH_LS1046A
-	/* Disable SATA ECC */
-	out_le32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + 0x520, 0x80000000);
-#endif
 	out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
+	out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY_2_CFG);
+	out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY_3_CFG);
 	out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
-	out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
 
 	ahci_init((void __iomem *)CONFIG_SYS_SATA);
 	scsi_scan(0);
@@ -307,41 +298,11 @@ void erratum_a008850_post(void)
 #endif
 }
 
-#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
-void erratum_a010315(void)
-{
-	int i;
-
-	for (i = PCIE1; i <= PCIE4; i++)
-		if (!is_serdes_configured(i)) {
-			debug("PCIe%d: disabled all R/W permission!\n", i);
-			set_pcie_ns_access(i, 0);
-		}
-}
-#endif
-
-static void erratum_a010539(void)
-{
-#if defined(CONFIG_SYS_FSL_ERRATUM_A010539) && defined(CONFIG_QSPI_BOOT)
-	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
-	u32 porsr1;
-
-	porsr1 = in_be32(&gur->porsr1);
-	porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK;
-	out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
-		 porsr1);
-#endif
-}
-
 void fsl_lsch2_early_init_f(void)
 {
 	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
 	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 
-#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
-	enable_layerscape_ns_access();
-#endif
-
 #ifdef CONFIG_FSL_IFC
 	init_early_memctl_regs();	/* tighten IFC timing */
 #endif
@@ -351,9 +312,7 @@ void fsl_lsch2_early_init_f(void)
 #endif
 	/* Make SEC reads and writes snoopable */
 	setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
-		     SCFG_SNPCNFGCR_SECWRSNP |
-		     SCFG_SNPCNFGCR_SATARDSNP |
-		     SCFG_SNPCNFGCR_SATAWRSNP);
+		     SCFG_SNPCNFGCR_SECWRSNP);
 
 	/*
 	 * Enable snoop requests and DVM message requests for
@@ -366,7 +325,6 @@ void fsl_lsch2_early_init_f(void)
 	erratum_a008850_early(); /* part 1 of 2 */
 	erratum_a009929();
 	erratum_a009660();
-	erratum_a010539();
 }
 #endif
 

arch/arm/cpu/armv8/fsl-layerscape/spl.c

@@ -8,6 +8,7 @@
 #include <spl.h>
 #include <asm/io.h>
 #include <fsl_ifc.h>
+#include <fsl_csu.h>
 #include <i2c.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -61,5 +62,13 @@ void board_init_f(ulong dummy)
 	i2c_init_all();
 #endif
 	dram_init();
+
+	/* Clear the BSS */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+	enable_layerscape_ns_access();
+#endif
+	board_init_r(NULL, 0);
 }
 #endif

arch/arm/cpu/armv8/fwcall.c

@@ -6,7 +6,6 @@
 
 #include <asm-offsets.h>
 #include <config.h>
-#include <efi_loader.h>
 #include <version.h>
 #include <asm/macro.h>
 #include <asm/psci.h>
@@ -18,7 +17,7 @@
  * x0~x7: input arguments
  * x0~x3: output arguments
  */
-static void __efi_runtime hvc_call(struct pt_regs *args)
+void hvc_call(struct pt_regs *args)
 {
 	asm volatile(
 		"ldr x0, %0\n"
@@ -52,7 +51,7 @@ static void __efi_runtime hvc_call(struct pt_regs *args)
  * x0~x3: output arguments
  */
 
-void __efi_runtime smc_call(struct pt_regs *args)
+void smc_call(struct pt_regs *args)
 {
 	asm volatile(
 		"ldr x0, %0\n"
@@ -76,21 +75,13 @@ void __efi_runtime smc_call(struct pt_regs *args)
 		  "x16", "x17");
 }
 
-/*
- * For now, all systems we support run at least in EL2 and thus
- * trigger PSCI calls to EL3 using SMC. If anyone ever wants to
- * use PSCI on U-Boot running below a hypervisor, please detect
- * this and set the flag accordingly.
- */
-static const __efi_runtime_data bool use_smc_for_psci = true;
-
-void __noreturn __efi_runtime psci_system_reset(void)
+void __noreturn psci_system_reset(bool conduit_smc)
 {
 	struct pt_regs regs;
 
 	regs.regs[0] = ARM_PSCI_0_2_FN_SYSTEM_RESET;
 
-	if (use_smc_for_psci)
+	if (conduit_smc)
 		smc_call(&regs);
 	else
 		hvc_call(&regs);
@@ -98,45 +89,3 @@ void __noreturn __efi_runtime psci_system_reset(void)
 	while (1)
 		;
 }
-
-void __noreturn __efi_runtime psci_system_off(void)
-{
-	struct pt_regs regs;
-
-	regs.regs[0] = ARM_PSCI_0_2_FN_SYSTEM_OFF;
-
-	if (use_smc_for_psci)
-		smc_call(&regs);
-	else
-		hvc_call(&regs);
-
-	while (1)
-		;
-}
-
-#ifdef CONFIG_PSCI_RESET
-void reset_misc(void)
-{
-	psci_system_reset();
-}
-
-#ifdef CONFIG_EFI_LOADER
-void __efi_runtime EFIAPI efi_reset_system(
-			enum efi_reset_type reset_type,
-			efi_status_t reset_status,
-			unsigned long data_size, void *reset_data)
-{
-	switch (reset_type) {
-	case EFI_RESET_COLD:
-	case EFI_RESET_WARM:
-		psci_system_reset();
-		break;
-	case EFI_RESET_SHUTDOWN:
-		psci_system_off();
-		break;
-	}
-
-	while (1) { }
-}
-#endif /* CONFIG_EFI_LOADER */
-#endif /* CONFIG_PSCI_RESET */

arch/arm/cpu/armv8/generic_timer.c

@@ -9,8 +9,6 @@
 #include <command.h>
 #include <asm/system.h>
 
-DECLARE_GLOBAL_DATA_PTR;
-
 /*
  * Generic timer implementation of get_tbclk()
  */
@@ -43,15 +41,6 @@ unsigned long timer_read_counter(void)
 	return cntpct;
 }
 
-unsigned long long get_ticks(void)
-{
-	unsigned long ticks = timer_read_counter();
-
-	gd->arch.tbl = ticks;
-
-	return ticks;
-}
-
 unsigned long usec2ticks(unsigned long usec)
 {
 	ulong ticks;

arch/arm/cpu/armv8/sec_firmware.c

@@ -19,22 +19,12 @@ extern void c_runtime_cpu_setup(void);
 #define SEC_FIRMWARE_LOADED	0x1
 #define SEC_FIRMWARE_RUNNING	0x2
 #define SEC_FIRMWARE_ADDR_MASK	(~0x3)
-/*
- * Secure firmware load addr
- * Flags used: 0x1 secure firmware has been loaded to secure memory
- *             0x2 secure firmware is running
- */
-phys_addr_t sec_firmware_addr;
-
-#ifndef SEC_FIRMWARE_FIT_IMAGE
-#define SEC_FIRMWARE_FIT_IMAGE		"firmware"
-#endif
-#ifndef SEC_FIRMEWARE_FIT_CNF_NAME
-#define SEC_FIRMEWARE_FIT_CNF_NAME	"config@1"
-#endif
-#ifndef SEC_FIRMWARE_TARGET_EL
-#define SEC_FIRMWARE_TARGET_EL		2
-#endif
+	/*
+	 * Secure firmware load addr
+	 * Flags used: 0x1 secure firmware has been loaded to secure memory
+	 *             0x2 secure firmware is running
+	 */
+	phys_addr_t sec_firmware_addr;
 
 static int sec_firmware_get_data(const void *sec_firmware_img,
 				const void **data, size_t *size)

arch/arm/cpu/armv8/zynqmp/Kconfig

@@ -1,29 +1,5 @@
 if ARCH_ZYNQMP
 
-config SPL_FAT_SUPPORT
-	default y
-
-config SPL_LIBCOMMON_SUPPORT
-	default y
-
-config SPL_LIBDISK_SUPPORT
-	default y
-
-config SPL_LIBGENERIC_SUPPORT
-	default y
-
-config SPL_MMC_SUPPORT
-	default y
-
-config SPL_SERIAL_SUPPORT
-	default y
-
-config SPL_SPI_FLASH_SUPPORT
-	default y if ZYNQ_QSPI
-
-config SPL_SPI_SUPPORT
-	default y if ZYNQ_QSPI
-
 config SYS_BOARD
 	default "zynqmp"
 
@@ -47,53 +23,5 @@ config ZYNQMP_USB
 config SYS_MALLOC_F_LEN
 	default 0x600
 
-config SPL_ZYNQMP_ALT_BOOTMODE_ENABLED
-	bool "Overwrite SPL bootmode"
-	depends on SPL
-	help
-	  Overwrite bootmode selected via boot mode pins to tell SPL what should
-	  be the next boot device.
-
-config SPL_ZYNQMP_ALT_BOOTMODE
-	hex
-	default 0x0 if JTAG_MODE
-	default 0x1 if QSPI_MODE_24BIT
-	default 0x2 if QSPI_MODE_32BIT
-	default 0x3 if SD_MODE
-	default 0x4 if NAND_MODE
-	default 0x5 if SD_MODE1
-	default 0x6 if EMMC_MODE
-	default 0x7 if USB_MODE
-
-choice
-	prompt "Boot mode"
-	depends on ZYNQMP_ALT_BOOTMODE_ENABLED
-	default JTAG
-
-config JTAG_MODE
-	bool "JTAG_MODE"
-
-config QSPI_MODE_24BIT
-	bool "QSPI_MODE_24BIT"
-
-config QSPI_MODE_32BIT
-	bool "QSPI_MODE_32BIT"
-
-config SD_MODE
-	bool "SD_MODE"
-
-config SD_MODE1
-	bool "SD_MODE1"
-
-config NAND_MODE
-	bool "NAND_MODE"
-
-config EMMC_MODE
-	bool "EMMC_MODE"
-
-config USB_MODE
-	bool "USB"
-
-endchoice
 
 endif

arch/arm/cpu/armv8/zynqmp/spl.c

@@ -35,29 +35,10 @@ void board_init_f(ulong dummy)
 	board_init_r(NULL, 0);
 }
 
-static void ps_mode_reset(ulong mode)
-{
-	writel(mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT,
-	       &crlapb_base->boot_pin_ctrl);
-	udelay(5);
-	writel(mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT |
-	       mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT,
-	       &crlapb_base->boot_pin_ctrl);
-}
-
-/*
- * Set default PS_MODE1 which is used for USB ULPI phy reset
- * Also other resets can be connected to this certain pin
- */
-#ifndef MODE_RESET
-# define MODE_RESET	PS_MODE1
-#endif
-
 #ifdef CONFIG_SPL_BOARD_INIT
 void spl_board_init(void)
 {
 	preloader_console_init();
-	ps_mode_reset(MODE_RESET);
 	board_init();
 }
 #endif
@@ -67,13 +48,6 @@ u32 spl_boot_device(void)
 	u32 reg = 0;
 	u8 bootmode;
 
-#if defined(CONFIG_SPL_ZYNQMP_ALT_BOOTMODE_ENABLED)
-	/* Change default boot mode at run-time */
-	writel(BOOT_MODE_USE_ALT |
-	       CONFIG_SPL_ZYNQMP_ALT_BOOTMODE << BOOT_MODE_ALT_SHIFT,
-	       &crlapb_base->boot_mode);
-#endif
-
 	reg = readl(&crlapb_base->boot_mode);
 	bootmode = reg & BOOT_MODES_MASK;
 
@@ -85,10 +59,6 @@ u32 spl_boot_device(void)
 	case SD_MODE:
 	case SD_MODE1:
 		return BOOT_DEVICE_MMC1;
-#endif
-#ifdef CONFIG_SPL_DFU_SUPPORT
-	case USB_MODE:
-		return BOOT_DEVICE_DFU;
 #endif
 	default:
 		printf("Invalid Boot Mode:0x%x\n", bootmode);

arch/arm/cpu/sa1100/timer.c

@@ -66,5 +66,8 @@ unsigned long long get_ticks(void)
  */
 ulong get_tbclk (void)
 {
-	return CONFIG_SYS_HZ;
+	ulong tbclk;
+
+	tbclk = CONFIG_SYS_HZ;
+	return tbclk;
 }

arch/arm/cpu/u-boot.lds

@@ -74,7 +74,6 @@ SECTIONS
 		*(._secure.data)
 	}
 
-#ifdef CONFIG_ARMV7_PSCI
 	.secure_stack ALIGN(ADDR(.secure_data) + SIZEOF(.secure_data),
 			    CONSTANT(COMMONPAGESIZE)) (NOLOAD) :
 #ifdef __ARMV7_PSCI_STACK_IN_RAM
@@ -84,10 +83,10 @@ SECTIONS
 #endif
 	{
 		KEEP(*(.__secure_stack_start))
-
+#ifdef CONFIG_ARMV7_PSCI
 		/* Skip addreses for stack */
 		. = . + CONFIG_ARMV7_PSCI_NR_CPUS * ARM_PSCI_STACK_SIZE;
-
+#endif
 		/* Align end of stack section to page boundary */
 		. = ALIGN(CONSTANT(COMMONPAGESIZE));
 
@@ -108,8 +107,6 @@ SECTIONS
 #ifndef __ARMV7_PSCI_STACK_IN_RAM
 	/* Reset VMA but don't allocate space if we have secure SRAM */
 	. = LOADADDR(.secure_stack);
-#endif
-
 #endif
 
 	.__secure_end : AT(ADDR(.__secure_end)) {

arch/arm/dts/Makefile

@@ -67,30 +67,27 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
 	tegra210-p2571.dtb
 
 dtb-$(CONFIG_ARCH_MVEBU) +=			\
-	armada-3720-db.dtb			\
 	armada-375-db.dtb			\
 	armada-388-clearfog.dtb			\
 	armada-388-gp.dtb			\
-	armada-385-amc.dtb			\
-	armada-7040-db.dtb			\
 	armada-xp-gp.dtb			\
 	armada-xp-maxbcm.dtb			\
 	armada-xp-synology-ds414.dtb		\
 	armada-xp-theadorable.dtb
 
 dtb-$(CONFIG_ARCH_UNIPHIER) += \
-	uniphier-ld11-ref.dtb \
-	uniphier-ld20-ref.dtb \
-	uniphier-ld4-ref.dtb \
-	uniphier-ld6b-ref.dtb \
-	uniphier-pro4-ace.dtb \
-	uniphier-pro4-ref.dtb \
-	uniphier-pro4-sanji.dtb \
-	uniphier-pro5-4kbox.dtb \
-	uniphier-pxs2-gentil.dtb \
-	uniphier-pxs2-vodka.dtb \
-	uniphier-sld3-ref.dtb \
-	uniphier-sld8-ref.dtb
+	uniphier-ph1-ld11-ref.dtb \
+	uniphier-ph1-ld20-ref.dtb \
+	uniphier-ph1-ld4-ref.dtb \
+	uniphier-ph1-ld6b-ref.dtb \
+	uniphier-ph1-pro4-ace.dtb \
+	uniphier-ph1-pro4-ref.dtb \
+	uniphier-ph1-pro4-sanji.dtb \
+	uniphier-ph1-pro5-4kbox.dtb \
+	uniphier-ph1-sld3-ref.dtb \
+	uniphier-ph1-sld8-ref.dtb \
+	uniphier-proxstream2-gentil.dtb \
+	uniphier-proxstream2-vodka.dtb
 dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \
 	zynq-zc706.dtb \
 	zynq-zed.dtb \
@@ -133,8 +130,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=				\
 	socfpga_cyclone5_sr1500.dtb			\
 	socfpga_cyclone5_vining_fpga.dtb
 
-dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb	\
-	dra72-evm-revc.dtb
+dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb
 dtb-$(CONFIG_TARGET_AM57XX_EVM) += am57xx-beagle-x15.dtb \
 	am572x-idk.dtb
 dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb
@@ -147,8 +143,6 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
 dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
 	fsl-ls1043a-qds-lpuart.dtb \
 	fsl-ls1043a-rdb.dtb \
-	fsl-ls1046a-qds-duart.dtb \
-	fsl-ls1046a-rdb.dtb \
 	fsl-ls1012a-qds.dtb \
 	fsl-ls1012a-rdb.dtb \
 	fsl-ls1012a-frdm.dtb
@@ -267,8 +261,7 @@ dtb-$(CONFIG_MACH_SUN8I_H3) += \
 	sun8i-h3-orangepi-pc.dtb \
 	sun8i-h3-orangepi-pc-plus.dtb \
 	sun8i-h3-orangepi-plus.dtb \
-	sun8i-h3-orangepi-plus2e.dtb \
-	sun8i-h3-nanopi-neo.dtb
+	sun8i-h3-orangepi-plus2e.dtb
 dtb-$(CONFIG_MACH_SUN50I) += \
 	sun50i-a64-pine64-plus.dtb \
 	sun50i-a64-pine64.dtb
@@ -279,14 +272,7 @@ dtb-$(CONFIG_MACH_SUN9I) += \
 dtb-$(CONFIG_VF610) += vf500-colibri.dtb \
 	vf610-colibri.dtb \
 	vf610-twr.dtb \
-	pcm052.dtb \
-	bk4r1.dtb
-
-dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \
-	imx6dl-icore.dtb \
-	imx6q-icore.dtb
-
-dtb-$(CONFIG_MX7) += imx7-colibri.dtb
+	pcm052.dtb
 
 dtb-$(CONFIG_SOC_KEYSTONE) += k2hk-evm.dtb \
 	k2l-evm.dtb \

arch/arm/dts/armada-371x.dtsi

@@ -1,53 +0,0 @@
-/*
- * Device Tree Include file for Marvell Armada 371x family of SoCs
- * (also named 88F3710)
- *
- * Copyright (C) 2016 Marvell
- *
- * Gregory CLEMENT <gregory.clement@free-electrons.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This file is distributed in the hope that it will be useful
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include "armada-37xx.dtsi"
-
-/ {
-	model = "Marvell Armada 3710 SoC";
-	compatible = "marvell,armada3710", "marvell,armada3700";
-};

arch/arm/dts/armada-3720-db.dts

@@ -1,123 +0,0 @@
-/*
- * Device Tree file for Marvell Armada 3720 development board
- * (DB-88F3720-DDR3)
- * Copyright (C) 2016 Marvell
- *
- * Gregory CLEMENT <gregory.clement@free-electrons.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This file is distributed in the hope that it will be useful
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/dts-v1/;
-
-#include "armada-372x.dtsi"
-
-/ {
-	model = "Marvell Armada 3720 Development Board DB-88F3720-DDR3";
-	compatible = "marvell,armada-3720-db", "marvell,armada3720", "marvell,armada3710";
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	aliases {
-		ethernet0 = &eth0;
-		i2c0 = &i2c0;
-		spi0 = &spi0;
-	};
-
-	memory {
-		device_type = "memory";
-		reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
-	};
-};
-
-&comphy {
-	phy0 {
-		phy-type = <PHY_TYPE_PEX0>;
-		phy-speed = <PHY_SPEED_2_5G>;
-	};
-
-	phy1 {
-		phy-type = <PHY_TYPE_USB3_HOST0>;
-		phy-speed = <PHY_SPEED_5G>;
-	};
-};
-
-&eth0 {
-	status = "okay";
-	phy-mode = "rgmii";
-};
-
-&i2c0 {
-	status = "okay";
-};
-
-/* CON3 */
-&sata {
-	status = "okay";
-};
-
-&spi0 {
-	status = "okay";
-
-	spi-flash@0 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "st,m25p128", "spi-flash";
-		reg = <0>; /* Chip select 0 */
-		spi-max-frequency = <50000000>;
-		m25p,fast-read;
-	};
-};
-
-/* Exported on the micro USB connector CON32 through an FTDI */
-&uart0 {
-	status = "okay";
-};
-
-/* CON29 */
-&usb2 {
-	status = "okay";
-};
-
-/* CON31 */
-&usb3 {
-	status = "okay";
-};

arch/arm/dts/armada-372x.dtsi

@@ -1,62 +0,0 @@
-/*
- * Device Tree Include file for Marvell Armada 372x family of SoCs
- * (also named 88F3720)
- *
- * Copyright (C) 2016 Marvell
- *
- * Gregory CLEMENT <gregory.clement@free-electrons.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This file is distributed in the hope that it will be useful
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include "armada-37xx.dtsi"
-
-/ {
-	model = "Marvell Armada 3720 SoC";
-	compatible = "marvell,armada3720", "marvell,armada3710";
-
-	cpus {
-		cpu@1 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a53","arm,armv8";
-			reg = <0x1>;
-			enable-method = "psci";
-		};
-	};
-};

arch/arm/dts/armada-37xx.dtsi

@@ -1,189 +0,0 @@
-/*
- * Device Tree Include file for Marvell Armada 37xx family of SoCs.
- *
- * Copyright (C) 2016 Marvell
- *
- * Gregory CLEMENT <gregory.clement@free-electrons.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This file is distributed in the hope that it will be useful
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/comphy/comphy_data.h>
-
-/ {
-	model = "Marvell Armada 37xx SoC";
-	compatible = "marvell,armada3700";
-	interrupt-parent = <&gic>;
-	#address-cells = <2>;
-	#size-cells = <2>;
-
-	aliases {
-		serial0 = &uart0;
-	};
-
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		cpu@0 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a53", "arm,armv8";
-			reg = <0>;
-			enable-method = "psci";
-		};
-	};
-
-	psci {
-		compatible = "arm,psci-0.2";
-		method = "smc";
-	};
-
-	timer {
-		compatible = "arm,armv8-timer";
-		interrupts = <GIC_PPI 13
-			(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
-			     <GIC_PPI 14
-			(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
-			     <GIC_PPI 11
-			(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
-			     <GIC_PPI 10
-			(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
-	};
-
-	soc {
-		compatible = "simple-bus";
-		#address-cells = <2>;
-		#size-cells = <2>;
-		ranges;
-
-		internal-regs {
-			#address-cells = <1>;
-			#size-cells = <1>;
-			compatible = "simple-bus";
-			/* 32M internal register @ 0xd000_0000 */
-			ranges = <0x0 0x0 0xd0000000 0x2000000>;
-
-			uart0: serial@12000 {
-				compatible = "marvell,armada-3700-uart";
-				reg = <0x12000 0x400>;
-				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
-				status = "disabled";
-			};
-
-			usb3: usb@58000 {
-				compatible = "marvell,armada3700-xhci",
-				"generic-xhci";
-				reg = <0x58000 0x4000>;
-				interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
-				status = "disabled";
-			};
-
-			usb2: usb@5e000 {
-				compatible = "marvell,armada3700-ehci";
-				reg = <0x5e000 0x450>;
-				status = "disabled";
-			};
-
-			xor@60900 {
-				compatible = "marvell,armada-3700-xor";
-				reg = <0x60900 0x100
-				       0x60b00 0x100>;
-
-				xor10 {
-					interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
-				};
-				xor11 {
-					interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
-				};
-			};
-
-			sata: sata@e0000 {
-				compatible = "marvell,armada-3700-ahci";
-				reg = <0xe0000 0x2000>;
-				interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
-				status = "disabled";
-			};
-
-			gic: interrupt-controller@1d00000 {
-				compatible = "arm,gic-v3";
-				#interrupt-cells = <3>;
-				interrupt-controller;
-				reg = <0x1d00000 0x10000>, /* GICD */
-				      <0x1d40000 0x40000>; /* GICR */
-			};
-
-			eth0: neta@30000 {
-				compatible = "marvell,armada-3700-neta";
-				reg = <0x30000 0x20>;
-				status = "disabled";
-			};
-
-			eth1: neta@40000 {
-				compatible = "marvell,armada-3700-neta";
-				reg = <0x40000 0x20>;
-				status = "disabled";
-			};
-
-			i2c0: i2c@11000 {
-				compatible = "marvell,armada-3700-i2c";
-				reg = <0x11000 0x100>;
-				status = "disabled";
-			};
-
-			spi0: spi@10600 {
-				compatible = "marvell,armada-3700-spi";
-				reg = <0x10600 0x50>;
-				#address-cells = <1>;
-				#size-cells = <0>;
-				#clock-cells = <0>;
-				clock-frequency = <160000>;
-				spi-max-frequency = <40000>;
-				status = "disabled";
-			};
-
-			comphy: comphy@18300 {
-				compatible = "marvell,mvebu-comphy", "marvell,comphy-armada-3700";
-				reg = <0x18300 0x28>,
-				      <0x1f300 0x3d000>;
-				mux-bitcount = <1>;
-				max-lanes = <2>;
-			};
-		};
-	};
-};

arch/arm/dts/armada-385-amc.dts

@@ -1,163 +0,0 @@
-/*
- * Device Tree file for Marvell Armada 385 development board
- * (DB-88F6820-AMC)
- *
- * Copyright (C) 2014 Marvell
- *
- * Gregory CLEMENT <gregory.clement@free-electrons.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is licensed under the terms of the GNU General Public
- *     License version 2.  This program is licensed "as is" without
- *     any warranty of any kind, whether express or implied.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/dts-v1/;
-#include "armada-385.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-	model = "Marvell Armada 385 AMC";
-	compatible = "marvell,a385-amc", "marvell,armada385", "marvell,armada380";
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	aliases {
-		ethernet0 = &eth0;
-		ethernet1 = &eth1;
-		spi1 = &spi1;
-	};
-
-	memory {
-		device_type = "memory";
-		reg = <0x00000000 0x80000000>; /* 2 GB */
-	};
-
-	soc {
-		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
-			  MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
-
-		internal-regs {
-			i2c@11000 {
-				pinctrl-names = "default";
-				pinctrl-0 = <&i2c0_pins>;
-				status = "okay";
-			};
-
-			serial@12000 {
-				/*
-				 * Exported on the micro USB connector CON16
-				 * through an FTDI
-				 */
-
-				pinctrl-names = "default";
-				pinctrl-0 = <&uart0_pins>;
-				status = "okay";
-				u-boot,dm-pre-reloc;
-			};
-
-			ethernet@34000 {
-				status = "okay";
-				phy = <&phy1>;
-				phy-mode = "sgmii";
-			};
-
-			usb@58000 {
-				status = "okay";
-			};
-
-			ethernet@70000 {
-				pinctrl-names = "default";
-				/*
-				 * The Reference Clock 0 is used to provide a
-				 * clock to the PHY
-				 */
-				pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>;
-				status = "okay";
-				phy = <&phy0>;
-				phy-mode = "rgmii-id";
-			};
-
-
-			mdio@72004 {
-				pinctrl-names = "default";
-				pinctrl-0 = <&mdio_pins>;
-
-				phy0: ethernet-phy@1 {
-					reg = <1>;
-				};
-
-				phy1: ethernet-phy@0 {
-					reg = <0>;
-				};
-			};
-
-			flash@d0000 {
-				status = "okay";
-				num-cs = <1>;
-				marvell,nand-keep-config;
-				marvell,nand-enable-arbiter;
-				nand-on-flash-bbt;
-			};
-		};
-
-		pcie-controller {
-			status = "okay";
-			pcie@1,0 {
-				/* Port 0, Lane 0 */
-				status = "okay";
-			};
-
-		};
-	};
-};
-
-&spi1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&spi1_pins>;
-	status = "okay";
-	u-boot,dm-pre-reloc;
-
-	spi-flash@0 {
-		u-boot,dm-pre-reloc;
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "st,m25p128", "jedec,spi-nor";
-		reg = <0>; /* Chip select 0 */
-		spi-max-frequency = <50000000>;
-		m25p,fast-read;
-	};
-};
-
-&refclk {
-	clock-frequency = <20000000>;
-};

arch/arm/dts/armada-7040-db.dts

@@ -1,193 +0,0 @@
-/*
- * Copyright (C) 2016 Marvell Technology Group Ltd.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPLv2 or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This library is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This library is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Device Tree file for Marvell Armada 7040 Development board platform
- */
-
-#include "armada-7040.dtsi"
-
-/ {
-	model = "Marvell Armada 7040 DB board";
-	compatible = "marvell,armada7040-db", "marvell,armada7040",
-		     "marvell,armada-ap806-quad", "marvell,armada-ap806";
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	aliases {
-		i2c0 = &cpm_i2c0;
-		spi0 = &cpm_spi1;
-	};
-
-	memory@00000000 {
-		device_type = "memory";
-		reg = <0x0 0x0 0x0 0x80000000>;
-	};
-};
-
-&i2c0 {
-	status = "okay";
-	clock-frequency = <100000>;
-};
-
-&spi0 {
-	status = "okay";
-
-	spi-flash@0 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <10000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "U-Boot";
-				reg = <0 0x200000>;
-			};
-			partition@400000 {
-				label = "Filesystem";
-				reg = <0x200000 0xce0000>;
-			};
-		};
-	};
-};
-
-&uart0 {
-	status = "okay";
-};
-
-
-&cpm_pcie2 {
-	status = "okay";
-};
-
-&cpm_i2c0 {
-	status = "okay";
-	clock-frequency = <100000>;
-};
-
-&cpm_spi1 {
-	status = "okay";
-
-	spi-flash@0 {
-		#address-cells = <0x1>;
-		#size-cells = <0x1>;
-		compatible = "jedec,spi-nor";
-		reg = <0x0>;
-		spi-max-frequency = <20000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "U-Boot";
-				reg = <0x0 0x200000>;
-			};
-
-			partition@400000 {
-				label = "Filesystem";
-				reg = <0x200000 0xe00000>;
-			};
-		};
-	};
-};
-
-&cpm_sata0 {
-	status = "okay";
-};
-
-&cpm_usb3_0 {
-	status = "okay";
-};
-
-&cpm_usb3_1 {
-	status = "okay";
-};
-
-&comphy_cp110 {
-	phy0 {
-		phy-type = <PHY_TYPE_SGMII2>;
-		phy-speed = <PHY_SPEED_3_125G>;
-	};
-
-	phy1 {
-		phy-type = <PHY_TYPE_USB3_HOST0>;
-		phy-speed = <PHY_SPEED_5G>;
-	};
-
-	phy2 {
-		phy-type = <PHY_TYPE_SGMII0>;
-		phy-speed = <PHY_SPEED_1_25G>;
-	};
-
-	phy3 {
-		phy-type = <PHY_TYPE_SATA1>;
-		phy-speed = <PHY_SPEED_5G>;
-	};
-
-	phy4 {
-		phy-type = <PHY_TYPE_USB3_HOST1>;
-		phy-speed = <PHY_SPEED_5G>;
-	};
-
-	phy5 {
-		phy-type = <PHY_TYPE_PEX2>;
-		phy-speed = <PHY_SPEED_5G>;
-	};
-};
-
-&utmi0 {
-	status = "okay";
-};
-
-&utmi1 {
-	status = "okay";
-};

arch/arm/dts/armada-7040.dtsi

@@ -1,55 +0,0 @@
-/*
- * Copyright (C) 2016 Marvell Technology Group Ltd.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPLv2 or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This library is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This library is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Device Tree file for the Armada 7040 SoC, made of an AP806 Quad and
- * one CP110.
- */
-
-#include "armada-ap806-quad.dtsi"
-#include "armada-cp110-master.dtsi"
-
-/ {
-	model = "Marvell Armada 7040";
-	compatible = "marvell,armada7040", "marvell,armada-ap806-quad",
-		     "marvell,armada-ap806";
-};

arch/arm/dts/armada-ap806-quad.dtsi

@@ -1,82 +0,0 @@
-/*
- * Copyright (C) 2016 Marvell Technology Group Ltd.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPLv2 or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This library is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This library is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Device Tree file for Marvell Armada AP806.
- */
-
-#include "armada-ap806.dtsi"
-
-/ {
-	model = "Marvell Armada AP806 Quad";
-	compatible = "marvell,armada-ap806-quad", "marvell,armada-ap806";
-
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		cpu@000 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a72", "arm,armv8";
-			reg = <0x000>;
-			enable-method = "psci";
-		};
-		cpu@001 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a72", "arm,armv8";
-			reg = <0x001>;
-			enable-method = "psci";
-		};
-		cpu@100 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a72", "arm,armv8";
-			reg = <0x100>;
-			enable-method = "psci";
-		};
-		cpu@101 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a72", "arm,armv8";
-			reg = <0x101>;
-			enable-method = "psci";
-		};
-	};
-};

arch/arm/dts/armada-ap806.dtsi

@@ -1,230 +0,0 @@
-/*
- * Copyright (C) 2016 Marvell Technology Group Ltd.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPLv2 or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This library is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This library is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Device Tree file for Marvell Armada AP806.
- */
-
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-
-/dts-v1/;
-
-/ {
-	model = "Marvell Armada AP806";
-	compatible = "marvell,armada-ap806";
-	#address-cells = <2>;
-	#size-cells = <2>;
-
-	aliases {
-		serial0 = &uart0;
-		serial1 = &uart1;
-	};
-
-	psci {
-		compatible = "arm,psci-0.2";
-		method = "smc";
-	};
-
-	ap806 {
-		#address-cells = <2>;
-		#size-cells = <2>;
-		compatible = "simple-bus";
-		interrupt-parent = <&gic>;
-		ranges;
-
-		config-space {
-			#address-cells = <1>;
-			#size-cells = <1>;
-			compatible = "simple-bus";
-			ranges = <0x0 0x0 0xf0000000 0x1000000>;
-
-			gic: interrupt-controller@210000 {
-				compatible = "arm,gic-400";
-				#interrupt-cells = <3>;
-				#address-cells = <1>;
-				#size-cells = <1>;
-				ranges;
-				interrupt-controller;
-				interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
-				reg = <0x210000 0x10000>,
-				      <0x220000 0x20000>,
-				      <0x240000 0x20000>,
-				      <0x260000 0x20000>;
-
-				gic_v2m0: v2m@280000 {
-					compatible = "arm,gic-v2m-frame";
-					msi-controller;
-					reg = <0x280000 0x1000>;
-					arm,msi-base-spi = <160>;
-					arm,msi-num-spis = <32>;
-				};
-				gic_v2m1: v2m@290000 {
-					compatible = "arm,gic-v2m-frame";
-					msi-controller;
-					reg = <0x290000 0x1000>;
-					arm,msi-base-spi = <192>;
-					arm,msi-num-spis = <32>;
-				};
-				gic_v2m2: v2m@2a0000 {
-					compatible = "arm,gic-v2m-frame";
-					msi-controller;
-					reg = <0x2a0000 0x1000>;
-					arm,msi-base-spi = <224>;
-					arm,msi-num-spis = <32>;
-				};
-				gic_v2m3: v2m@2b0000 {
-					compatible = "arm,gic-v2m-frame";
-					msi-controller;
-					reg = <0x2b0000 0x1000>;
-					arm,msi-base-spi = <256>;
-					arm,msi-num-spis = <32>;
-				};
-			};
-
-			timer {
-				compatible = "arm,armv8-timer";
-				interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>,
-					     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>,
-					     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>,
-					     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
-			};
-
-			odmi: odmi@300000 {
-				compatible = "marvell,odmi-controller";
-				interrupt-controller;
-				msi-controller;
-				marvell,odmi-frames = <4>;
-				reg = <0x300000 0x4000>,
-				      <0x304000 0x4000>,
-				      <0x308000 0x4000>,
-				      <0x30C000 0x4000>;
-				marvell,spi-base = <128>, <136>, <144>, <152>;
-			};
-
-			xor@400000 {
-				compatible = "marvell,mv-xor-v2";
-				reg = <0x400000 0x1000>,
-				      <0x410000 0x1000>;
-				msi-parent = <&gic_v2m0>;
-				dma-coherent;
-			};
-
-			xor@420000 {
-				compatible = "marvell,mv-xor-v2";
-				reg = <0x420000 0x1000>,
-				      <0x430000 0x1000>;
-				msi-parent = <&gic_v2m0>;
-				dma-coherent;
-			};
-
-			xor@440000 {
-				compatible = "marvell,mv-xor-v2";
-				reg = <0x440000 0x1000>,
-				      <0x450000 0x1000>;
-				msi-parent = <&gic_v2m0>;
-				dma-coherent;
-			};
-
-			xor@460000 {
-				compatible = "marvell,mv-xor-v2";
-				reg = <0x460000 0x1000>,
-				      <0x470000 0x1000>;
-				msi-parent = <&gic_v2m0>;
-				dma-coherent;
-			};
-
-			spi0: spi@510600 {
-				compatible = "marvell,armada-380-spi";
-				reg = <0x510600 0x50>;
-				#address-cells = <1>;
-				#size-cells = <0>;
-				cell-index = <0>;
-				interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&ap_syscon 3>;
-				status = "disabled";
-			};
-
-			i2c0: i2c@511000 {
-				compatible = "marvell,mv78230-i2c";
-				reg = <0x511000 0x20>;
-				#address-cells = <1>;
-				#size-cells = <0>;
-				interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
-				timeout-ms = <1000>;
-				clocks = <&ap_syscon 3>;
-				status = "disabled";
-			};
-
-			uart0: serial@512000 {
-				compatible = "snps,dw-apb-uart";
-				reg = <0x512000 0x100>;
-				reg-shift = <2>;
-				interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
-				reg-io-width = <1>;
-				clocks = <&ap_syscon 3>;
-				status = "disabled";
-				clock-frequency = <200000000>;
-			};
-
-			uart1: serial@512100 {
-				compatible = "snps,dw-apb-uart";
-				reg = <0x512100 0x100>;
-				reg-shift = <2>;
-				interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
-				reg-io-width = <1>;
-				clocks = <&ap_syscon 3>;
-				status = "disabled";
-
-			};
-
-			ap_syscon: system-controller@6f4000 {
-				compatible = "marvell,ap806-system-controller",
-					     "syscon";
-				#clock-cells = <1>;
-				clock-output-names = "ap-cpu-cluster-0",
-						     "ap-cpu-cluster-1",
-						     "ap-fixed", "ap-mss";
-				reg = <0x6f4000 0x1000>;
-			};
-		};
-	};
-};