Prepare v2016.09.01

Signed-off-by: Tom Rini <trini@konsulko.com>

.gitignore

@@ -31,7 +31,7 @@
 # Top-level generic files
 #
 /MLO*
-/SPL*
+/SPL
 /System.map
 /u-boot*
 /boards.cfg

.travis.yml

@@ -3,8 +3,7 @@
 
 # build U-Boot on Travis CI - https://travis-ci.org/
 
-sudo: required
-dist: trusty
+sudo: true
 
 language: c
 
@@ -19,104 +18,58 @@ addons:
     - libsdl1.2-dev
     - python
     - python-virtualenv
-    - swig
-    - libpython-dev
-    - gcc-powerpc-linux-gnu
-    - iasl
-    - grub-efi-ia32-bin
-    - rpm2cpio
-    - wget
-    - device-tree-compiler
+
+cache:
+ - apt
 
 install:
  # install latest device tree compiler
- #- git clone --depth=1 git://git.kernel.org/pub/scm/utils/dtc/dtc.git /tmp/dtc
- #- make -j4 -C /tmp/dtc
- # Clone uboot-test-hooks
- - git clone --depth=1 git://github.com/swarren/uboot-test-hooks.git /tmp/uboot-test-hooks
- - ln -s travis-ci /tmp/uboot-test-hooks/bin/`hostname`
- - ln -s travis-ci /tmp/uboot-test-hooks/py/`hostname`
+ - git clone --depth=1 https://git.kernel.org/pub/scm/utils/dtc/dtc.git /tmp/dtc
+ - make -j4 -C /tmp/dtc
  # prepare buildman environment
- - echo -e "[toolchain]\nroot = /usr" > ~/.buildman
- - echo -e "aarch64 = /tmp/gcc-linaro-6.3.1-2017.02-x86_64_aarch64-linux-gnu" >> ~/.buildman
- - echo -e "arm = /tmp/gcc-linaro-6.3.1-2017.02-x86_64_arm-linux-gnueabihf" >> ~/.buildman
- - echo -e "arc = /tmp/arc_gnu_2016.09_prebuilt_uclibc_le_archs_linux_install" >> ~/.buildman
- - echo -e "\n[toolchain-alias]\nsh = sh4\nopenrisc = or32" >> ~/.buildman
+ - export BUILDMAN_ROOT="root:"
+ - export BUILDMAN_PPC="ppc:"
+ - export BUILDMAN_ARM="arm:"
+ - export BUILDMAN_SANDBOX="sandbox:"
+ - echo -e "[toolchain]\n${BUILDMAN_ROOT} /\n" > ~/.buildman
+ - echo -e "${BUILDMAN_PPC} /opt/eldk-5.4/powerpc/sysroots/i686-eldk-linux/usr/bin/powerpc-linux/\n" >> ~/.buildman
+ - echo -e "${BUILDMAN_ARM} /opt/eldk-5.4/armv5te/sysroots/i686-eldk-linux/usr/bin/armv5te-linux-gnueabi/\n" >> ~/.buildman
+ - echo -e "${BUILDMAN_SANDBOX} /usr/bin/gcc\n" >> ~/.buildman
+ - export BUILDMAN_ALIAS="x86:"
+ - export BUILDMAN_ALIAS_ARM="arm:"
+ - echo -e "\n\n[toolchain-alias]\n${BUILDMAN_ALIAS} i386\n" >> ~/.buildman
+ - echo -e "${BUILDMAN_ALIAS_ARM} armv5te\n" >> ~/.buildman
  - cat ~/.buildman
  - virtualenv /tmp/venv
  - . /tmp/venv/bin/activate
  - pip install pytest
- - grub-mkimage -o ~/grub_x86.efi -O i386-efi normal  echo lsefimmap lsefi lsefisystab efinet tftp minicmd
- - mkdir ~/grub2-arm
- - ( cd ~/grub2-arm; wget -O - http://download.opensuse.org/ports/armv7hl/distribution/leap/42.2/repo/oss/suse/armv7hl/grub2-arm-efi-2.02~beta2-87.1.armv7hl.rpm | rpm2cpio | cpio -di )
 
 env:
   global:
-    - PATH=/tmp/dtc:/tmp/qemu-install/bin:/tmp/uboot-test-hooks/bin:$PATH
-    - PYTHONPATH=/tmp/uboot-test-hooks/py/travis-ci
+    - PATH=/tmp/dtc:$PATH
     - BUILD_DIR=build
     - HOSTCC="cc"
     - HOSTCXX="c++"
 
 before_script:
   # install toolchains based on TOOLCHAIN} variable
+  - if [[ "${TOOLCHAIN}" == *aarch64* ]]; then ./tools/buildman/buildman --fetch-arch aarch64 ; fi
+  - if [[ "${TOOLCHAIN}" == *arm* ]]; then wget ftp://ftp.denx.de/pub/eldk/5.4/targets/armv5te/eldk-eglibc-i686-arm-toolchain-gmae-5.4.sh ; fi
+  - if [[ "${TOOLCHAIN}" == *arm* ]]; then sh eldk-eglibc-i686-arm-toolchain-gmae-5.4.sh -y ; fi
   - if [[ "${TOOLCHAIN}" == *avr32* ]]; then ./tools/buildman/buildman --fetch-arch avr32 ; fi
+  - if [[ "${TOOLCHAIN}" == *i386* ]]; then ./tools/buildman/buildman sandbox --fetch-arch i386 ; fi
   - if [[ "${TOOLCHAIN}" == *m68k* ]]; then ./tools/buildman/buildman --fetch-arch m68k ; fi
-  - if [[ "${TOOLCHAIN}" == *microblaze* ]]; then ./tools/buildman/buildman --fetch-arch microblaze ; fi
   - if [[ "${TOOLCHAIN}" == *mips* ]]; then ./tools/buildman/buildman --fetch-arch mips ; fi
-  - if [[ "${TOOLCHAIN}" == *or32* ]]; then ./tools/buildman/buildman --fetch-arch or32 ; fi
-  - if [[ "${TOOLCHAIN}" == *sh4* ]]; then ./tools/buildman/buildman --fetch-arch sh4 ; fi
-  - if [[ "${TOOLCHAIN}" == *x86_64* ]]; then
-      ./tools/buildman/buildman --fetch-arch x86_64;
-      echo -e "\n[toolchain-prefix]\nx86 = ${HOME}/.buildman-toolchains/gcc-4.9.0-nolibc/x86_64-linux/bin/x86_64-linux-" >> ~/.buildman;
-    fi
-  - if [[ "${TOOLCHAIN}" == arc ]]; then
-       wget https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/releases/download/arc-2016.09-release/arc_gnu_2016.09_prebuilt_uclibc_le_archs_linux_install.tar.gz &&
-       tar -C /tmp -xf arc_gnu_2016.09_prebuilt_uclibc_le_archs_linux_install.tar.gz;
-    fi
-  - if [[ "${TOOLCHAIN}" == *xtensa* ]]; then ./tools/buildman/buildman --fetch-arch xtensa ; fi
-  # If TOOLCHAIN is unset, we're on some flavour of ARM.
-  - if [[ "${TOOLCHAIN}" == "" ]]; then
-       wget http://releases.linaro.org/components/toolchain/binaries/6.3-2017.02/aarch64-linux-gnu/gcc-linaro-6.3.1-2017.02-x86_64_aarch64-linux-gnu.tar.xz &&
-       wget http://releases.linaro.org/components/toolchain/binaries/6.3-2017.02/arm-linux-gnueabihf/gcc-linaro-6.3.1-2017.02-x86_64_arm-linux-gnueabihf.tar.xz &&
-       tar -C /tmp -xf gcc-linaro-6.3.1-2017.02-x86_64_aarch64-linux-gnu.tar.xz &&
-       tar -C /tmp -xf gcc-linaro-6.3.1-2017.02-x86_64_arm-linux-gnueabihf.tar.xz;
-    fi
-  - if [[ "${QEMU_TARGET}" != "" ]]; then
-       git clone git://git.qemu.org/qemu.git /tmp/qemu;
-       pushd /tmp/qemu;
-       git submodule update --init dtc &&
-       git checkout v2.8.0-rc3 &&
-       ./configure --prefix=/tmp/qemu-install --target-list=${QEMU_TARGET} &&
-       make -j4 all install;
-       popd;
-    fi
+  - if [[ "${TOOLCHAIN}" == *ppc* ]]; then wget ftp://ftp.denx.de/pub/eldk/5.4/targets/powerpc/eldk-eglibc-i686-powerpc-toolchain-gmae-5.4.sh ; fi
+  - if [[ "${TOOLCHAIN}" == *ppc* ]]; then sh eldk-eglibc-i686-powerpc-toolchain-gmae-5.4.sh -y ; fi
 
 script:
- # Comments must be outside the command strings below, or the Travis parser
- # will get confused.
- #
- # Exit code 129 means warnings only.
- - if [[ "${BUILDMAN}" != "" ]]; then
-     set +e;
-     tools/buildman/buildman -P ${BUILDMAN};
-     ret=$?;
-     if [[ $ret -ne 0 && $ret -ne 129 ]]; then
-       tools/buildman/buildman -sdeP ${BUILDMAN};
-       exit $ret;
-     fi;
+ # the execution sequence for each test
+ - if [[ "${TEST_CMD}" != "" ]]; then
+     ${TEST_CMD};
    fi
- # "not a_test_which_does_not_exist" is a dummy -k parameter which will
- # never prevent any test from running. That way, we can always pass
- # "-k something" even when $TEST_PY_TEST_SPEC doesnt need a custom
- # value.
- - export UBOOT_TRAVIS_BUILD_DIR=`cd .. && pwd`/.bm-work/${TEST_PY_BD};
-   cp ~/grub_x86.efi $UBOOT_TRAVIS_BUILD_DIR/;
-   cp ~/grub2-arm/usr/lib/grub2/arm-efi/grub.efi $UBOOT_TRAVIS_BUILD_DIR/grub_arm.efi;
-   if [[ "${TEST_PY_BD}" != "" ]]; then
-     ./test/py/test.py --bd ${TEST_PY_BD} ${TEST_PY_ID}
-       -k "${TEST_PY_TEST_SPEC:-not a_test_which_does_not_exist}"
-       --build-dir "$UBOOT_TRAVIS_BUILD_DIR";
+ - if [[ "${BUILDMAN}" != "" ]]; then
+     tools/buildman/buildman ${BUILDMAN};
    fi
 
 matrix:
@@ -124,214 +77,113 @@ matrix:
   # we need to build by vendor due to 50min time limit for builds
   # each env setting here is a dedicated build
     - env:
-        - BUILDMAN="arc"
-          TOOLCHAIN="arc"
+        - BUILDMAN="arm1136"
+          TOOLCHAIN="arm"
     - env:
-        - BUILDMAN="arm11"
+        - BUILDMAN="arm1136"
+          TOOLCHAIN="arm"
     - env:
-        - BUILDMAN="arm7"
+        - BUILDMAN="arm1176"
+          TOOLCHAIN="arm"
+    - env:
+        - BUILDMAN="arm720t"
+          TOOLCHAIN="arm"
     - env:
         - BUILDMAN="arm920t"
-    - env:
-        - JOB="arm926ejs"
-          BUILDMAN="arm926ejs -x mx,siemens,atmel"
-    - env:
-        - BUILDMAN="arm946es"
+          TOOLCHAIN="arm"
     - env:
         - BUILDMAN="atmel -x avr32"
+          TOOLCHAIN="arm"
     - env:
         - BUILDMAN="avr32"
           TOOLCHAIN="avr32"
+    - env:
+        - BUILDMAN="davinci"
+          TOOLCHAIN="arm"
     - env:
         - BUILDMAN="denx"
+          TOOLCHAIN="arm"
     - env:
-        - JOB="Freescale ARM32"
-          BUILDMAN="freescale -x powerpc,m68k,aarch64"
-    - env:
-        - JOB="Freescale AArch64"
-          BUILDMAN="freescale&aarch64"
-    - env:
-        - JOB="i.MX6 (non-Freescale)"
-          BUILDMAN="mx6 -x freescale"
-    - env:
-        - JOB="i.MX (non-Freescale, non-i.MX6)"
-          BUILDMAN="mx -x freescale,mx6"
-    - env:
-        - BUILDMAN="samsung"
-    - env:
-        - BUILDMAN="sun4i"
-    - env:
-        - BUILDMAN="sun5i"
-    - env:
-        - BUILDMAN="sun6i"
-    - env:
-        - BUILDMAN="sun7i"
-    - env:
-        - BUILDMAN="sun8i"
-    - env:
-        - BUILDMAN="sun9i"
-    - env:
-        - BUILDMAN="sun50i"
-    - env:
-        - JOB="Catch-all ARM"
-          BUILDMAN="arm -x arm11,arm7,arm9,aarch64,atmel,denx,freescale,kirkwood,mvebu,siemens,tegra,uniphier,mx,samsung,sunxi,am33xx,omap3,omap4,omap5,pxa,rockchip"
+        - BUILDMAN="freescale -x powerpc,m68k,aarch64"
+          TOOLCHAIN="arm"
     - env:
         - BUILDMAN="sandbox x86"
-          TOOLCHAIN="x86_64"
+          TOOLCHAIN="i386"
     - env:
         - BUILDMAN="kirkwood"
-    - env:
-        - BUILDMAN="mvebu"
-    - env:
-        - BUILDMAN="pxa"
+          TOOLCHAIN="arm"
     - env:
         - BUILDMAN="m68k"
           TOOLCHAIN="m68k"
-    - env:
-        - BUILDMAN="microblaze"
-          TOOLCHAIN="microblaze"
     - env:
         - BUILDMAN="mips"
           TOOLCHAIN="mips"
     - env:
         - BUILDMAN="mpc512x"
+          TOOLCHAIN="ppc"
     - env:
         - BUILDMAN="mpc5xx"
+          TOOLCHAIN="ppc"
     - env:
         - BUILDMAN="mpc5xxx"
+          TOOLCHAIN="ppc"
     - env:
         - BUILDMAN="mpc8260"
+          TOOLCHAIN="ppc"
     - env:
         - BUILDMAN="mpc83xx"
+          TOOLCHAIN="ppc"
     - env:
         - BUILDMAN="mpc85xx -x freescale"
+          TOOLCHAIN="ppc"
     - env:
         - BUILDMAN="mpc85xx -x t208xrdb -x t4qds -x t102* -x p1_p2_rdb_pc -x p1010rdb -x corenet_ds -x b4860qds -x sbc8548 -x bsc91*"
+          TOOLCHAIN="ppc"
     - env:
         - BUILDMAN="t208xrdb t4qds t102*"
+          TOOLCHAIN="ppc"
     - env:
-        - BUILDMAN="p1_p2_rdb_pc"
-    - env:
-        - BUILDMAN="p1010rdb"
+        - BUILDMAN="p1_p2_rdb_pc p1010rdb"
+          TOOLCHAIN="ppc"
     - env:
         - BUILDMAN="corenet_ds b4860qds sbc8548 bsc91*"
+          TOOLCHAIN="ppc"
     - env:
         - BUILDMAN="mpc86xx"
+          TOOLCHAIN="ppc"
     - env:
         - BUILDMAN="mpc8xx"
+          TOOLCHAIN="ppc"
     - env:
         - BUILDMAN="siemens"
+          TOOLCHAIN="arm"
     - env:
-        - BUILDMAN="tegra"
+        - BUILDMAN="ti"
+          TOOLCHAIN="arm"
     - env:
-        - JOB="am33xx"
-          BUILDMAN="am33xx -x siemens"
-    - env:
-        - BUILDMAN="omap3"
-    - env:
-        - BUILDMAN="omap4"
-    - env:
-        - BUILDMAN="omap5"
-    - env:
-        - BUILDMAN="uniphier"
-    - env:
-        - BUILDMAN="aarch64 -x tegra,freescale,mvebu,uniphier,sunxi,samsung,rockchip"
-    - env:
-        - BUILDMAN="rockchip"
-    - env:
-        - BUILDMAN="sh4"
-          TOOLCHAIN="sh4"
-    - env:
-        - BUILDMAN="xtensa"
-          TOOLCHAIN="xtensa"
+        - BUILDMAN="aarch64"
+          TOOLCHAIN="aarch64"
 
     # QA jobs for code analytics
     # static code analysis with cppcheck (we can add --enable=all later)
     - env:
-        - JOB="cppcheck"
-      script:
-        - cppcheck --force --quiet --inline-suppr .
+        - TEST_CMD="cppcheck --force --quiet --inline-suppr ."
     # search for TODO within source tree
     - env:
-        - JOB="grep TODO"
-      script:
-        - grep -r TODO .
+        - TEST_CMD="grep -r TODO ."
     # search for FIXME within source tree
     - env:
-        - JOB="grep FIXME HACK"
-      script:
-        - grep -r FIXME .
+        - TEST_CMD="grep -r FIXME ."
     # search for HACK within source tree and ignore HACKKIT board
+    - env:
+        - TEST_CMD="grep -r HACK . | grep -v HACKKIT"
       script:
         - grep -r HACK . | grep -v HACKKIT
     # some statistics about the code base
     - env:
-        - JOB="sloccount"
-      script:
-        - sloccount .
-
+        - TEST_CMD="sloccount ."
     # test/py
     - env:
-        - TEST_PY_BD="sandbox"
-          BUILDMAN="^sandbox$"
-          TOOLCHAIN="x86_64"
-    - env:
-        - TEST_PY_BD="vexpress_ca15_tc2"
-          TEST_PY_ID="--id qemu"
-          QEMU_TARGET="arm-softmmu"
-          BUILDMAN="^vexpress_ca15_tc2$"
-    - env:
-        - TEST_PY_BD="vexpress_ca9x4"
-          TEST_PY_ID="--id qemu"
-          QEMU_TARGET="arm-softmmu"
-          BUILDMAN="^vexpress_ca9x4$"
-    - env:
-        - TEST_PY_BD="integratorcp_cm926ejs"
-          TEST_PY_TEST_SPEC="not sleep"
-          TEST_PY_ID="--id qemu"
-          QEMU_TARGET="arm-softmmu"
-          BUILDMAN="^integratorcp_cm926ejs$"
-    - env:
-        - TEST_PY_BD="qemu_mips"
-          TEST_PY_TEST_SPEC="not sleep"
-          QEMU_TARGET="mips-softmmu"
-          BUILDMAN="^qemu_mips$"
-          TOOLCHAIN="mips"
-    - env:
-        - TEST_PY_BD="qemu_mipsel"
-          TEST_PY_TEST_SPEC="not sleep"
-          QEMU_TARGET="mipsel-softmmu"
-          BUILDMAN="^qemu_mipsel$"
-          TOOLCHAIN="mips"
-    - env:
-        - TEST_PY_BD="qemu_mips64"
-          TEST_PY_TEST_SPEC="not sleep"
-          QEMU_TARGET="mips64-softmmu"
-          BUILDMAN="^qemu_mips64$"
-          TOOLCHAIN="mips"
-    - env:
-        - TEST_PY_BD="qemu_mips64el"
-          TEST_PY_TEST_SPEC="not sleep"
-          QEMU_TARGET="mips64el-softmmu"
-          BUILDMAN="^qemu_mips64el$"
-          TOOLCHAIN="mips"
-    - env:
-        - TEST_PY_BD="qemu-ppce500"
-          TEST_PY_TEST_SPEC="not sleep"
-          QEMU_TARGET="ppc-softmmu"
-          BUILDMAN="^qemu-ppce500$"
-    - env:
-        - TEST_PY_BD="qemu-x86"
-          TEST_PY_TEST_SPEC="not sleep"
-          QEMU_TARGET="i386-softmmu"
-          BUILDMAN="^qemu-x86$"
-          TOOLCHAIN="x86_64"
-          BUILD_ROM="yes"
-    - env:
-        - TEST_PY_BD="zynq_zc702"
-          TEST_PY_TEST_SPEC="not sleep"
-          QEMU_TARGET="arm-softmmu"
-          TEST_PY_ID="--id qemu"
-          BUILDMAN="^zynq_zc702$"
+        - TEST_CMD="./test/py/test.py --bd sandbox --build"
 
 # TODO make it perfect ;-r

Kconfig

@@ -55,22 +55,17 @@ config CC_OPTIMIZE_FOR_SIZE
 
 config DISTRO_DEFAULTS
 	bool "Select defaults suitable for booting general purpose Linux distributions"
-	default y if ARCH_SUNXI || TEGRA
-	default y if ARCH_LS2080A
-	default y if ARCH_MESON
-	default y if ARCH_ROCKCHIP
+	default y if ARCH_SUNXI
 	default n
 	select CMD_BOOTZ if ARM && !ARM64
 	select CMD_BOOTI if ARM64
 	select CMD_DHCP
-	select CMD_PXE
 	select CMD_EXT2
 	select CMD_EXT4
 	select CMD_FAT
 	select CMD_FS_GENERIC
 	select CMD_MII
 	select CMD_PING
-	select CMD_PART
 	select HUSH_PARSER
 	help
 	  Select this to enable various options and commands which are suitable
@@ -129,7 +124,7 @@ config TOOLS_DEBUG
 	  it is possible to set breakpoints on particular lines, single-step
 	  debug through the source code, etc.
 
-endif # EXPERT
+endif
 
 config PHYS_64BIT
 	bool "64bit physical address support"
@@ -142,30 +137,106 @@ endmenu		# General setup
 
 menu "Boot images"
 
+config SUPPORT_SPL
+	bool
+
+config SUPPORT_TPL
+	bool
+
+config SPL
+	bool
+	depends on SUPPORT_SPL
+	prompt "Enable SPL"
+	help
+	  If you want to build SPL as well as the normal image, say Y.
+
+config SPL_SYS_MALLOC_SIMPLE
+	bool
+	depends on SPL
+	prompt "Only use malloc_simple functions in the SPL"
+	help
+	  Say Y here to only use the *_simple malloc functions from
+	  malloc_simple.c, rather then using the versions from dlmalloc.c;
+	  this will make the SPL binary smaller at the cost of more heap
+	  usage as the *_simple malloc functions do not re-use free-ed mem.
+
+config SPL_STACK_R
+	depends on SPL
+	bool "Enable SDRAM location for SPL stack"
+	help
+	  SPL starts off execution in SRAM and thus typically has only a small
+	  stack available. Since SPL sets up DRAM while in its board_init_f()
+	  function, it is possible for the stack to move there before
+	  board_init_r() is reached. This option enables a special SDRAM
+	  location for the SPL stack. U-Boot SPL switches to this after
+	  board_init_f() completes, and before board_init_r() starts.
+
+config SPL_STACK_R_ADDR
+	depends on SPL_STACK_R
+	hex "SDRAM location for SPL stack"
+	help
+	  Specify the address in SDRAM for the SPL stack. This will be set up
+	  before board_init_r() is called.
+
+config SPL_STACK_R_MALLOC_SIMPLE_LEN
+	depends on SPL_STACK_R && SPL_SYS_MALLOC_SIMPLE
+	hex "Size of malloc_simple heap after switching to DRAM SPL stack"
+	default 0x100000
+	help
+	  Specify the amount of the stack to use as memory pool for
+	  malloc_simple after switching the stack to DRAM. This may be set
+	  to give board_init_r() a larger heap then the initial heap in
+	  SRAM which is limited to SYS_MALLOC_F_LEN bytes.
+
+config SPL_SEPARATE_BSS
+	depends on SPL
+	bool "BSS section is in a different memory region from text"
+	help
+	  Some platforms need a large BSS region in SPL and can provide this
+	  because RAM is already set up. In this case BSS can be moved to RAM.
+	  This option should then be enabled so that the correct device tree
+	  location is used. Normally we put the device tree at the end of BSS
+	  but with this option enabled, it goes at _image_binary_end.
+
+config TPL
+	bool
+	depends on SPL && SUPPORT_TPL
+	prompt "Enable TPL"
+	help
+	  If you want to build TPL as well as the normal image and SPL, say Y.
+
 config FIT
 	bool "Support Flattened Image Tree"
-	select MD5
 	help
-	  This option allows you to boot the new uImage structure,
+	  This option allows to boot the new uImage structrure,
 	  Flattened Image Tree.  FIT is formally a FDT, which can include
 	  images of various types (kernel, FDT blob, ramdisk, etc.)
 	  in a single blob.  To boot this new uImage structure,
 	  pass the address of the blob to the "bootm" command.
 	  FIT is very flexible, supporting compression, multiple images,
 	  multiple configurations, verification through hashing and also
-	  verified boot (secure boot using RSA).
+	  verified boot (secure boot using RSA). This option enables that
+	  feature.
 
-if FIT
+config SPL_FIT
+	bool "Support Flattened Image Tree within SPL"
+	depends on FIT
+	depends on SPL
+
+config FIT_VERBOSE
+	bool "Display verbose messages on FIT boot"
+	depends on FIT
 
 config FIT_SIGNATURE
 	bool "Enable signature verification of FIT uImages"
+	depends on FIT
 	depends on DM
 	select RSA
 	help
 	  This option enables signature verification of FIT uImages,
 	  using a hash signed and verified using RSA. If
 	  CONFIG_SHA_PROG_HW_ACCEL is defined, i.e support for progressive
-	  hashing is available using hardware, then the RSA library will use
+	  hashing is available using hardware, then then RSA library will use
 	  it. See doc/uImage.FIT/signature.txt for more details.
 
 	  WARNING: When relying on signed FIT images with a required signature
@@ -174,16 +245,15 @@ config FIT_SIGNATURE
 	  format support in this case, enable it using
 	  CONFIG_IMAGE_FORMAT_LEGACY.
 
-config FIT_VERBOSE
-	bool "Show verbose messages when FIT images fail"
-	help
-	  Generally a system will have valid FIT images so debug messages
-	  are a waste of code space. If you are debugging your images then
-	  you can enable this option to get more verbose information about
-	  failures.
+config SPL_FIT_SIGNATURE
+	bool "Enable signature verification of FIT firmware within SPL"
+	depends on SPL_FIT
+	depends on SPL_DM
+	select SPL_RSA
 
 config FIT_BEST_MATCH
 	bool "Select the best match for the kernel device tree"
+	depends on FIT
 	help
 	  When no configuration is explicitly selected, default to the
 	  one whose fdt's compatibility field best matches that of
@@ -191,55 +261,14 @@ config FIT_BEST_MATCH
 	  most specific compatibility entry of U-Boot's fdt's root node.
 	  The order of entries in the configuration's fdt is ignored.
 
-config FIT_IMAGE_POST_PROCESS
-	bool "Enable post-processing of FIT artifacts after loading by U-Boot"
-	depends on TI_SECURE_DEVICE
+config FIT_VERBOSE
+	bool "Show verbose messages when FIT images fails"
+	depends on FIT
 	help
-	  Allows doing any sort of manipulation to blobs after they got extracted
-	  from FIT images like stripping off headers or modifying the size of the
-	  blob, verification, authentication, decryption etc. in a platform or
-	  board specific way. In order to use this feature a platform or board-
-	  specific implementation of board_fit_image_post_process() must be
-	  provided. Also, anything done during this post-processing step would
-	  need to be comprehended in how the images were prepared before being
-	  injected into the FIT creation (i.e. the blobs would have been pre-
-	  processed before being added to the FIT image).
-
-config SPL_FIT
-	bool "Support Flattened Image Tree within SPL"
-	depends on SPL
-
-config SPL_FIT_SIGNATURE
-	bool "Enable signature verification of FIT firmware within SPL"
-	depends on SPL_FIT
-	depends on SPL_DM
-	select SPL_RSA
-
-config SPL_LOAD_FIT
-	bool "Enable SPL loading U-Boot as a FIT"
-	help
-	  Normally with the SPL framework a legacy image is generated as part
-	  of the build. This contains U-Boot along with information as to
-	  where it should be loaded. This option instead enables generation
-	  of a FIT (Flat Image Tree) which provides more flexibility. In
-	  particular it can handle selecting from multiple device tree
-	  and passing the correct one to U-Boot.
-
-config SPL_FIT_IMAGE_POST_PROCESS
-	bool "Enable post-processing of FIT artifacts after loading by the SPL"
-	depends on SPL_LOAD_FIT && TI_SECURE_DEVICE
-	help
-	  Allows doing any sort of manipulation to blobs after they got extracted
-	  from the U-Boot FIT image like stripping off headers or modifying the
-	  size of the blob, verification, authentication, decryption etc. in a
-	  platform or board specific way. In order to use this feature a platform
-	  or board-specific implementation of board_fit_image_post_process() must
-	  be provided. Also, anything done during this post-processing step would
-	  need to be comprehended in how the images were prepared before being
-	  injected into the FIT creation (i.e. the blobs would have been pre-
-	  processed before being added to the FIT image).
-
-endif # FIT
+	  Generally a system will have valid FIT images so debug messages
+	  are a waste of code space. If you are debugging your images then
+	  you can enable this option to get more verbose information about
+	  failures.
 
 config OF_BOARD_SETUP
 	bool "Set up board-specific details in device tree before boot"
@@ -284,14 +313,51 @@ config SYS_EXTRA_OPTIONS
 	  new boards should not use this option.
 
 config SYS_TEXT_BASE
-	depends on ARC || X86 || ARCH_UNIPHIER || ARCH_ZYNQMP || \
-		(M68K && !TARGET_ASTRO_MCF5373L) || MICROBLAZE || MIPS || \
-		ARCH_ZYNQ || ARCH_KEYSTONE
+	depends on SPARC || ARC || X86 || ARCH_UNIPHIER || ARCH_ZYNQMP || \
+		(M68K && !TARGET_ASTRO_MCF5373L) || MICROBLAZE || MIPS
 	depends on !EFI_APP
 	hex "Text Base"
 	help
 	  TODO: Move CONFIG_SYS_TEXT_BASE for all the architecture
 
+config SPL_LOAD_FIT
+	bool "Enable SPL loading U-Boot as a FIT"
+	depends on FIT
+	help
+	  Normally with the SPL framework a legacy image is generated as part
+	  of the build. This contains U-Boot along with information as to
+	  where it should be loaded. This option instead enables generation
+	  of a FIT (Flat Image Tree) which provides more flexibility. In
+	  particular it can handle selecting from multiple device tree
+	  and passing the correct one to U-Boot.
+
+config SPL_FIT_IMAGE_POST_PROCESS
+	bool "Enable post-processing of FIT artifacts after loading by the SPL"
+	depends on SPL_LOAD_FIT && TI_SECURE_DEVICE
+	help
+	  Allows doing any sort of manipulation to blobs after they got extracted
+	  from the U-Boot FIT image like stripping off headers or modifying the
+	  size of the blob, verification, authentication, decryption etc. in a
+	  platform or board specific way. In order to use this feature a platform
+	  or board-specific implementation of board_fit_image_post_process() must
+	  be provided. Also, anything done during this post-processing step would
+	  need to be comprehended in how the images were prepared before being
+	  injected into the FIT creation (i.e. the blobs would have been pre-
+	  processed before being added to the FIT image).
+
+config FIT_IMAGE_POST_PROCESS
+	bool "Enable post-processing of FIT artifacts after loading by U-Boot"
+	depends on FIT && TI_SECURE_DEVICE
+	help
+	  Allows doing any sort of manipulation to blobs after they got extracted
+	  from FIT images like stripping off headers or modifying the size of the
+	  blob, verification, authentication, decryption etc. in a platform or
+	  board specific way. In order to use this feature a platform or board-
+	  specific implementation of board_fit_image_post_process() must be
+	  provided. Also, anything done during this post-processing step would
+	  need to be comprehended in how the images were prepared before being
+	  injected into the FIT creation (i.e. the blobs would have been pre-
+	  processed before being added to the FIT image).
 
 config SYS_CLK_FREQ
 	depends on ARC || ARCH_SUNXI
@@ -299,8 +365,9 @@ config SYS_CLK_FREQ
 	help
 	  TODO: Move CONFIG_SYS_CLK_FREQ for all the architecture
 
-config ARCH_FIXUP_FDT_MEMORY
-	bool "Enable arch_fixup_memory_banks() call"
+config ARCH_FIXUP_FDT
+	bool "Enable arch_fixup_fdt() call"
+	depends on ARM || MIPS
 	default y
 	help
 	  Enable FDT memory map syncup before OS boot. This feature can be
@@ -309,14 +376,10 @@ config ARCH_FIXUP_FDT_MEMORY
 
 endmenu		# Boot images
 
-source "api/Kconfig"
-
 source "common/Kconfig"
 
 source "cmd/Kconfig"
 
-source "disk/Kconfig"
-
 source "dts/Kconfig"
 
 source "net/Kconfig"
@@ -328,5 +391,3 @@ source "fs/Kconfig"
 source "lib/Kconfig"
 
 source "test/Kconfig"
-
-source "scripts/Kconfig"

MAINTAINERS

@@ -69,7 +69,8 @@ ARM ALTERA SOCFPGA
 M:	Marek Vasut <marex@denx.de>
 S:	Maintainted
 T:	git git://git.denx.de/u-boot-socfpga.git
-F:	arch/arm/mach-socfpga/
+F:	arch/arm/cpu/armv7/socfpga/
+F:	board/altera/socfpga/
 
 ARM ATMEL AT91
 M:	Andreas Bießmann <andreas@biessmann.org>
@@ -93,9 +94,10 @@ S:	Maintained
 T:	git git://git.denx.de/u-boot-imx.git
 F:	arch/arm/cpu/arm1136/mx*/
 F:	arch/arm/cpu/arm926ejs/mx*/
+F:	arch/arm/cpu/arm926ejs/imx/
 F:	arch/arm/cpu/armv7/mx*/
 F:	arch/arm/cpu/armv7/vf610/
-F:	arch/arm/imx-common/
+F:	arch/arm/cpu/imx-common/
 F:	arch/arm/include/asm/arch-imx/
 F:	arch/arm/include/asm/arch-mx*/
 F:	arch/arm/include/asm/arch-vf610/
@@ -164,21 +166,13 @@ S:	Maintained
 F:	arch/arm/cpu/armv7/stv0991/
 F:	arch/arm/include/asm/arch-stv0991/
 
-ARM STI
-M:	Patrice Chotard <patrice.chotard@st.com>
-S:	Maintained
-F:	arch/arm/mach-sti/
-F:	arch/arm/include/asm/arch-sti*/
-
 ARM SUNXI
-M:	Jagan Teki <jagan@openedev.com>
-M:	Maxime Ripard <maxime.ripard@free-electrons.com>
+M:	Ian Campbell <ijc@hellion.org.uk>
+M:	Hans De Goede <hdegoede@redhat.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-sunxi.git
 F:	arch/arm/cpu/armv7/sunxi/
 F:	arch/arm/include/asm/arch-sunxi/
-F:	arch/arm/mach-sunxi/
-F:	board/sunxi/
 
 ARM TEGRA
 M:	Tom Warren <twarren@nvidia.com>
@@ -224,6 +218,12 @@ S:	Maintained
 T:	git git://git.denx.de/u-boot-avr32.git
 F:	arch/avr32/
 
+BLACKFIN
+M:	Sonic Zhang <sonic.adi@gmail.com>
+S:	Maintained
+T:	git git://git.denx.de/u-boot-blackfin.git
+F:	arch/blackfin/
+
 BUILDMAN
 M:	Simon Glass <sjg@chromium.org>
 S:	Maintained
@@ -244,7 +244,7 @@ T:	git git://git.denx.de/u-boot-coldfire.git
 F:	arch/m68k/
 
 DFU
-M:	Lukasz Majewski <lukma@denx.de>
+M:	Lukasz Majewski <l.majewski@samsung.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-dfu.git
 F:	drivers/dfu/
@@ -273,7 +273,7 @@ F:	lib/fdtdec*
 F:	lib/libfdt/
 F:	include/fdt*
 F:	include/libfdt*
-F:	cmd/fdt.c
+F.	common/cmd_fdt.c
 F:	common/fdt_support.c
 
 FREEBSD
@@ -310,6 +310,11 @@ S:	Maintained
 T:	git git://git.denx.de/u-boot-mmc.git
 F:	drivers/mmc/
 
+OPENRISC
+M:	Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
+S:	Maintained
+F:	arch/openrisc/
+
 PATMAN
 M:	Simon Glass <sjg@chromium.org>
 S:	Maintained
@@ -363,12 +368,6 @@ S:	Maintained
 T:	git git://git.denx.de/u-boot-ppc4xx.git
 F:	arch/powerpc/cpu/ppc4xx/
 
-POWER
-M:	Jaehoon Chung <jh80.chung@samsung.com>
-S:	Maintained
-T:	git git://git.denx.de/u-boot-pmic.git
-F:	drivers/power/
-
 NETWORK
 M:	Joe Hershberger <joe.hershberger@ni.com>
 S:	Maintained
@@ -395,8 +394,8 @@ T:	git git://git.denx.de/u-boot-nios.git
 F:	arch/nios2/
 
 ONENAND
-#M:	Lukasz Majewski <l.majewski@majess.pl>
-S:	Orphaned (Since 2017-01)
+M:	Lukasz Majewski <l.majewski@samsung.com>
+S:	Maintained
 T:	git git://git.denx.de/u-boot-onenand.git
 F:	drivers/mtd/onenand/
 
@@ -411,8 +410,14 @@ S:	Maintained
 T:	git git://git.denx.de/u-boot-sh.git
 F:	arch/sh/
 
+SPARC
+#M:	Francois Retief <fgretief@spaceteq.co.za>
+S:	Orphaned (Since 2016-02)
+T:	git git://git.denx.de/u-boot-sparc.git
+F:	arch/sparc/
+
 SPI
-M:	Jagan Teki <jagan@openedev.com>
+M:	Jagan Teki <jteki@openedev.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-spi.git
 F:	drivers/mtd/spi/
@@ -425,21 +430,6 @@ S:	Maintained
 F:	drivers/spmi/
 F:	include/spmi/
 
-TI SYSTEM SECURITY
-M:	Andrew F. Davis <afd@ti.com>
-S:	Supported
-F:	arch/arm/mach-omap2/omap5/sec_entry_cpu1.S
-F:	arch/arm/mach-omap2/omap5/sec-fxns.c
-F:	arch/arm/mach-omap2/sec-common.c
-F:	arch/arm/mach-omap2/config_secure.mk
-F:	configs/am335x_hs_evm_defconfig
-F:	configs/am43xx_hs_evm_defconfig
-F:	configs/am57xx_hs_evm_defconfig
-F:	configs/dra7xx_hs_evm_defconfig
-F:	configs/k2hk_hs_evm_defconfig
-F:	configs/k2e_hs_evm_defconfig
-F:	configs/k2g_hs_evm_defconfig
-
 TQ GROUP
 #M:	Martin Krause <martin.krause@tq-systems.de>
 S:	Orphaned (Since 2016-02)

Makefile

@@ -2,9 +2,9 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-VERSION = 2017
-PATCHLEVEL = 05
-SUBLEVEL =
+VERSION = 2016
+PATCHLEVEL = 09
+SUBLEVEL = 01
 EXTRAVERSION =
 NAME =
 
@@ -348,7 +348,7 @@ OBJCOPY		= $(CROSS_COMPILE)objcopy
 OBJDUMP		= $(CROSS_COMPILE)objdump
 AWK		= awk
 PERL		= perl
-PYTHON		?= python
+PYTHON		= python
 DTC		= dtc
 CHECK		= sparse
 
@@ -371,7 +371,7 @@ export ARCH CPU BOARD VENDOR SOC CPUDIR BOARDDIR
 export CONFIG_SHELL HOSTCC HOSTCFLAGS HOSTLDFLAGS CROSS_COMPILE AS LD CC
 export CPP AR NM LDR STRIP OBJCOPY OBJDUMP
 export MAKE AWK PERL PYTHON
-export HOSTCXX HOSTCXXFLAGS CHECK CHECKFLAGS DTC DTC_FLAGS
+export HOSTCXX HOSTCXXFLAGS DTC CHECK CHECKFLAGS
 
 export KBUILD_CPPFLAGS NOSTDINC_FLAGS UBOOTINCLUDE OBJCOPYFLAGS LDFLAGS
 export KBUILD_CFLAGS KBUILD_AFLAGS
@@ -482,13 +482,6 @@ else
 # Build targets only - this includes vmlinux, arch specific targets, clean
 # targets and others. In general all targets except *config targets.
 
-# Additional helpers built in scripts/
-# Carefully list dependencies so we do not try to build scripts twice
-# in parallel
-PHONY += scripts
-scripts: scripts_basic include/config/auto.conf
-	$(Q)$(MAKE) $(build)=$(@)
-
 ifeq ($(dot-config),1)
 # Read in config
 -include include/config/auto.conf
@@ -534,15 +527,6 @@ endif
 endif
 endif
 
-# These are set by the arch-specific config.mk. Make sure they are exported
-# so they can be used when building an EFI application.
-export EFI_LDS		# Filename of EFI link script in arch/$(ARCH)/lib
-export EFI_CRT0		# Filename of EFI CRT0 in arch/$(ARCH)/lib
-export EFI_RELOC	# Filename of EFU relocation code in arch/$(ARCH)/lib
-export CFLAGS_EFI	# Compiler flags to add when building EFI app
-export CFLAGS_NON_EFI	# Compiler flags to remove when building EFI app
-export EFI_TARGET	# binutils target if EFI is natively supported
-
 # If board code explicitly specified LDSCRIPT or CONFIG_SYS_LDSCRIPT, use
 # that (or fail if absent).  Otherwise, search for a linker script in a
 # standard location.
@@ -624,9 +608,8 @@ KBUILD_CFLAGS += $(KCFLAGS)
 UBOOTINCLUDE    := \
 		-Iinclude \
 		$(if $(KBUILD_SRC), -I$(srctree)/include) \
-		$(if $(CONFIG_$(SPL_)SYS_THUMB_BUILD), \
-			$(if $(CONFIG_HAS_THUMB2),, \
-				-I$(srctree)/arch/$(ARCH)/thumb1/include),) \
+		$(if $(CONFIG_SYS_THUMB_BUILD), $(if $(CONFIG_HAS_THUMB2),, \
+			-I$(srctree)/arch/$(ARCH)/thumb1/include),) \
 		-I$(srctree)/arch/$(ARCH)/include \
 		-include $(srctree)/include/linux/kconfig.h
 
@@ -672,7 +655,6 @@ libs-y += drivers/power/ \
 libs-y += drivers/spi/
 libs-$(CONFIG_FMAN_ENET) += drivers/net/fm/
 libs-$(CONFIG_SYS_FSL_DDR) += drivers/ddr/fsl/
-libs-$(CONFIG_SYS_FSL_MMDC) += drivers/ddr/fsl/
 libs-$(CONFIG_ALTERA_SDRAM) += drivers/ddr/altera/
 libs-y += drivers/serial/
 libs-y += drivers/usb/dwc3/
@@ -758,7 +740,7 @@ DO_STATIC_RELA =
 endif
 
 # Always append ALL so that arch config.mk's can add custom ones
-ALL-y += u-boot.srec u-boot.bin u-boot.sym System.map binary_size_check
+ALL-y += u-boot.srec u-boot.bin u-boot.sym System.map u-boot.cfg binary_size_check
 
 ALL-$(CONFIG_ONENAND_U_BOOT) += u-boot-onenand.bin
 ifeq ($(CONFIG_SPL_FSL_PBL),y)
@@ -771,11 +753,7 @@ ALL-$(CONFIG_RAMBOOT_PBL) += u-boot.pbl
 endif
 endif
 ALL-$(CONFIG_SPL) += spl/u-boot-spl.bin
-ifeq ($(CONFIG_MX6)$(CONFIG_SECURE_BOOT), yy)
-ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot-ivt.img
-else
 ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot.img
-endif
 ALL-$(CONFIG_TPL) += tpl/u-boot-tpl.bin
 ALL-$(CONFIG_OF_SEPARATE) += u-boot.dtb
 ifeq ($(CONFIG_SPL_FRAMEWORK),y)
@@ -805,10 +783,6 @@ ALL-y += $(CONFIG_BUILD_TARGET:"%"=%)
 endif
 
 LDFLAGS_u-boot += $(LDFLAGS_FINAL)
-
-# Avoid 'Not enough room for program headers' error on binutils 2.28 onwards.
-LDFLAGS_u-boot += $(call ld-option, --no-dynamic-linker)
-
 ifneq ($(CONFIG_SYS_TEXT_BASE),)
 LDFLAGS_u-boot += -Ttext $(CONFIG_SYS_TEXT_BASE)
 endif
@@ -825,11 +799,9 @@ cmd_zobjcopy = $(OBJCOPY) $(OBJCOPYFLAGS) $(OBJCOPYFLAGS_$(@F)) $< $@
 quiet_cmd_efipayload = OBJCOPY $@
 cmd_efipayload = $(OBJCOPY) -I binary -O $(EFIPAYLOAD_BFDTARGET) -B $(EFIPAYLOAD_BFDARCH) $< $@
 
-MKIMAGEOUTPUT ?= /dev/null
-
 quiet_cmd_mkimage = MKIMAGE $@
 cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \
-	$(if $(KBUILD_VERBOSE:1=), >$(MKIMAGEOUTPUT))
+	$(if $(KBUILD_VERBOSE:1=), >/dev/null)
 
 quiet_cmd_cat = CAT     $@
 cmd_cat = cat $(filter-out $(PHONY), $^) > $@
@@ -839,12 +811,6 @@ append = cat $(filter-out $< $(PHONY), $^) >> $@
 quiet_cmd_pad_cat = CAT     $@
 cmd_pad_cat = $(cmd_objcopy) && $(append) || rm -f $@
 
-cfg: u-boot.cfg
-
-quiet_cmd_cfgcheck = CFGCHK  $2
-cmd_cfgcheck = $(srctree)/scripts/check-config.sh $2 \
-		$(srctree)/scripts/config_whitelist.txt $(srctree)
-
 all:		$(ALL-y)
 ifeq ($(CONFIG_DM_I2C_COMPAT)$(CONFIG_SANDBOX),y)
 	@echo "===================== WARNING ======================"
@@ -853,10 +819,6 @@ ifeq ($(CONFIG_DM_I2C_COMPAT)$(CONFIG_SANDBOX),y)
 	@echo "before sending patches to the mailing list."
 	@echo "===================================================="
 endif
-	@# Check that this build does not use CONFIG options that we do not
-	@# know about unless they are in Kconfig. All the existing CONFIG
-	@# options are whitelisted, so new ones should not be added.
-	$(call cmd,cfgcheck,u-boot.cfg)
 
 PHONY += dtbs
 dtbs: dts/dt.dtb
@@ -881,12 +843,6 @@ endif
 %.imx: %.bin
 	$(Q)$(MAKE) $(build)=arch/arm/imx-common $@
 
-%.vyb: %.imx
-	$(Q)$(MAKE) $(build)=arch/arm/cpu/armv7/vf610 $@
-
-quiet_cmd_copy = COPY    $@
-      cmd_copy = cp $< $@
-
 u-boot.dtb: dts/dt.dtb
 	$(call cmd,copy)
 
@@ -898,7 +854,7 @@ u-boot.hex u-boot.srec: u-boot FORCE
 	$(call if_changed,objcopy)
 
 OBJCOPYFLAGS_u-boot-nodtb.bin := -O binary \
-		$(if $(CONFIG_X86_16BIT_INIT),-R .start16 -R .resetvec)
+		$(if $(CONFIG_X86_RESET_VECTOR),-R .start16 -R .resetvec)
 
 binary_size_check: u-boot-nodtb.bin FORCE
 	@file_size=$(shell wc -c u-boot-nodtb.bin | awk '{print $$1}') ; \
@@ -924,12 +880,6 @@ u-boot.ldr:	u-boot
 		$(LDR) -T $(CONFIG_CPU) -c $@ $< $(LDR_FLAGS)
 		$(BOARD_SIZE_CHECK)
 
-# binman
-# ---------------------------------------------------------------------------
-quiet_cmd_binman = BINMAN  $@
-cmd_binman = $(srctree)/tools/binman/binman -d u-boot.dtb -O . \
-		-I . -I $(srctree)/board/$(BOARDDIR) $<
-
 OBJCOPYFLAGS_u-boot.ldr.hex := -I binary -O ihex
 
 OBJCOPYFLAGS_u-boot.ldr.srec := -I binary -O srec
@@ -959,11 +909,6 @@ else
 MKIMAGEFLAGS_u-boot.img = -A $(ARCH) -T firmware -C none -O u-boot \
 	-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
 	-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board"
-MKIMAGEFLAGS_u-boot-ivt.img = -A $(ARCH) -T firmware_ivt -C none -O u-boot \
-	-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
-	-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board"
-u-boot-ivt.img: MKIMAGEOUTPUT = u-boot-ivt.img.log
-CLEAN_FILES += u-boot-ivt.img.log u-boot-dtb.imx.log SPL.log u-boot.imx.log
 endif
 
 MKIMAGEFLAGS_u-boot-dtb.img = $(MKIMAGEFLAGS_u-boot.img)
@@ -972,13 +917,12 @@ MKIMAGEFLAGS_u-boot.kwb = -n $(srctree)/$(CONFIG_SYS_KWD_CONFIG:"%"=%) \
 	-T kwbimage -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE)
 
 MKIMAGEFLAGS_u-boot-spl.kwb = -n $(srctree)/$(CONFIG_SYS_KWD_CONFIG:"%"=%) \
-	-T kwbimage -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) \
-	$(if $(KEYDIR),-k $(KEYDIR))
+	-T kwbimage -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE)
 
 MKIMAGEFLAGS_u-boot.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \
 		-R $(srctree)/$(CONFIG_SYS_FSL_PBL_PBI:"%"=%) -T pblimage
 
-u-boot-dtb.img u-boot.img u-boot.kwb u-boot.pbl u-boot-ivt.img: \
+u-boot-dtb.img u-boot.img u-boot.kwb u-boot.pbl: \
 		$(if $(CONFIG_SPL_LOAD_FIT),u-boot-nodtb.bin dts/dt.dtb,u-boot.bin) FORCE
 	$(call if_changed,mkimage)
 
@@ -991,6 +935,9 @@ u-boot.sha1:	u-boot.bin
 u-boot.dis:	u-boot
 		$(OBJDUMP) -d $< > $@
 
+u-boot.cfg:	include/config.h FORCE
+	$(call if_changed,cpp_cfg)
+
 ifdef CONFIG_TPL
 SPL_PAYLOAD := tpl/u-boot-with-tpl.bin
 else
@@ -1080,11 +1027,50 @@ endif
 
 # x86 uses a large ROM. We fill it with 0xff, put the 16-bit stuff (including
 # reset vector) at the top, Intel ME descriptor at the bottom, and U-Boot in
-# the middle. This is handled by binman based on an image description in the
-# board's device tree.
+# the middle.
 ifneq ($(CONFIG_X86_RESET_VECTOR),)
 rom: u-boot.rom FORCE
 
+IFDTOOL=$(objtree)/tools/ifdtool
+IFDTOOL_FLAGS  = -f 0:$(objtree)/u-boot.dtb
+IFDTOOL_FLAGS += -m 0x$(shell $(NM) u-boot |grep _dt_ucode_base_size |cut -d' ' -f1)
+IFDTOOL_FLAGS += -U $(CONFIG_SYS_TEXT_BASE):$(objtree)/u-boot-nodtb.bin
+IFDTOOL_FLAGS += -w $(CONFIG_SYS_X86_START16):$(objtree)/u-boot-x86-16bit.bin
+IFDTOOL_FLAGS += -C
+
+ifneq ($(CONFIG_HAVE_INTEL_ME),)
+IFDTOOL_ME_FLAGS  = -D $(srctree)/board/$(BOARDDIR)/descriptor.bin
+IFDTOOL_ME_FLAGS += -i ME:$(srctree)/board/$(BOARDDIR)/me.bin
+endif
+
+ifneq ($(CONFIG_HAVE_MRC),)
+IFDTOOL_FLAGS += -w $(CONFIG_X86_MRC_ADDR):$(srctree)/board/$(BOARDDIR)/mrc.bin
+endif
+
+ifneq ($(CONFIG_HAVE_FSP),)
+IFDTOOL_FLAGS += -w $(CONFIG_FSP_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_FSP_FILE)
+endif
+
+ifneq ($(CONFIG_HAVE_CMC),)
+IFDTOOL_FLAGS += -w $(CONFIG_CMC_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_CMC_FILE)
+endif
+
+ifneq ($(CONFIG_HAVE_VGA_BIOS),)
+IFDTOOL_FLAGS += -w $(CONFIG_VGA_BIOS_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_VGA_BIOS_FILE)
+endif
+
+ifneq ($(CONFIG_HAVE_REFCODE),)
+IFDTOOL_FLAGS += -w $(CONFIG_X86_REFCODE_ADDR):refcode.bin
+endif
+
+quiet_cmd_ifdtool = IFDTOOL $@
+cmd_ifdtool  = $(IFDTOOL) -c -r $(CONFIG_ROM_SIZE) u-boot.tmp;
+ifneq ($(CONFIG_HAVE_INTEL_ME),)
+cmd_ifdtool += $(IFDTOOL) $(IFDTOOL_ME_FLAGS) u-boot.tmp;
+endif
+cmd_ifdtool += $(IFDTOOL) $(IFDTOOL_FLAGS) u-boot.tmp;
+cmd_ifdtool += mv u-boot.tmp $@
+
 refcode.bin: $(srctree)/board/$(BOARDDIR)/refcode.bin FORCE
 	$(call if_changed,copy)
 
@@ -1092,19 +1078,20 @@ quiet_cmd_ldr = LD      $@
 cmd_ldr = $(LD) $(LDFLAGS_$(@F)) \
 	       $(filter-out FORCE,$^) -o $@
 
-u-boot.rom: u-boot-x86-16bit.bin u-boot.bin \
-		$(if $(CONFIG_SPL_X86_16BIT_INIT),spl/u-boot-spl.bin) \
-		$(if $(CONFIG_HAVE_REFCODE),refcode.bin) FORCE
-	$(call if_changed,binman)
+u-boot.rom: u-boot-x86-16bit.bin u-boot.bin FORCE \
+		$(if $(CONFIG_HAVE_REFCODE),refcode.bin)
+	$(call if_changed,ifdtool)
 
 OBJCOPYFLAGS_u-boot-x86-16bit.bin := -O binary -j .start16 -j .resetvec
 u-boot-x86-16bit.bin: u-boot FORCE
 	$(call if_changed,objcopy)
 endif
 
-ifneq ($(CONFIG_ARCH_SUNXI),)
-u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin u-boot.img u-boot.dtb FORCE
-	$(call if_changed,binman)
+ifneq ($(CONFIG_SUNXI),)
+OBJCOPYFLAGS_u-boot-sunxi-with-spl.bin = -I binary -O binary \
+				   --pad-to=$(CONFIG_SPL_PAD_TO) --gap-fill=0xff
+u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin u-boot.img FORCE
+	$(call if_changed,pad_cat)
 endif
 
 ifneq ($(CONFIG_TEGRA),)
@@ -1135,7 +1122,7 @@ quiet_cmd_u-boot_payload ?= LD      $@
       cmd_u-boot_payload ?= $(LD) $(LDFLAGS_EFI_PAYLOAD) -o $@ \
       -T u-boot-payload.lds arch/x86/cpu/call32.o \
       lib/efi/efi.o lib/efi/efi_stub.o u-boot.bin.o \
-      $(addprefix arch/$(ARCH)/lib/,$(EFISTUB))
+      $(addprefix arch/$(ARCH)/lib/efi/,$(EFISTUB))
 
 u-boot-payload: u-boot.bin.o u-boot-payload.lds FORCE
 	$(call if_changed,u-boot_payload)
@@ -1349,17 +1336,13 @@ spl/u-boot-spl: tools prepare \
 spl/sunxi-spl.bin: spl/u-boot-spl
 	@:
 
-spl/sunxi-spl-with-ecc.bin: spl/sunxi-spl.bin
-	@:
-
 spl/u-boot-spl.sfp: spl/u-boot-spl
 	@:
 
 spl/boot.bin: spl/u-boot-spl
 	@:
 
-tpl/u-boot-tpl.bin: tools prepare \
-		$(if $(CONFIG_OF_SEPARATE)$(CONFIG_SPL_OF_PLATDATA),dts/dt.dtb)
+tpl/u-boot-tpl.bin: tools prepare
 	$(Q)$(MAKE) obj=tpl -f $(srctree)/scripts/Makefile.spl all
 
 TAG_SUBDIRS := $(patsubst %,$(srctree)/%,$(u-boot-dirs) include)
@@ -1437,7 +1420,7 @@ CLEAN_DIRS  += $(MODVERDIR) \
 	       $(foreach d, spl tpl, $(patsubst %,$d/%, \
 			$(filter-out include, $(shell ls -1 $d 2>/dev/null))))
 
-CLEAN_FILES += include/bmp_logo.h include/bmp_logo_data.h \
+CLEAN_FILES += include/bmp_logo.h include/bmp_logo_data.h include/license.h \
 	       boot* u-boot* MLO* SPL System.map
 
 # Directories & files removed with 'make mrproper'
@@ -1526,7 +1509,6 @@ help:
 	@echo  '  cscope	  - Generate cscope index'
 	@echo  '  ubootrelease	  - Output the release version string (use with make -s)'
 	@echo  '  ubootversion	  - Output the version stored in Makefile (use with make -s)'
-	@echo  "  cfg		  - Don't build, just create the .cfg files"
 	@echo  ''
 	@echo  'Static analysers'
 	@echo  '  checkstack      - Generate a list of stack hogs'
@@ -1558,6 +1540,11 @@ tests:
 	$(Q)$(MAKE) $(build)=scripts build_docproc
 	$(Q)$(MAKE) $(build)=doc/DocBook $@
 
+# Dummies...
+PHONY += prepare scripts
+prepare: ;
+scripts: ;
+
 endif #ifeq ($(config-targets),1)
 endif #ifeq ($(mixed-targets),1)
 

README

@@ -127,7 +127,7 @@ releases in "stable" maintenance trees.
 Examples:
 	U-Boot v2009.11	    - Release November 2009
 	U-Boot v2009.11.1   - Release 1 in version November 2009 stable tree
-	U-Boot v2010.09-rc1 - Release candidate 1 for September 2010 release
+	U-Boot v2010.09-rc1 - Release candiate 1 for September 2010 release
 
 
 Directory Hierarchy:
@@ -137,6 +137,7 @@ Directory Hierarchy:
   /arc			Files generic to ARC architecture
   /arm			Files generic to ARM architecture
   /avr32		Files generic to AVR32 architecture
+  /blackfin		Files generic to Analog Devices Blackfin architecture
   /m68k			Files generic to m68k architecture
   /microblaze		Files generic to microblaze architecture
   /mips			Files generic to MIPS architecture
@@ -146,6 +147,7 @@ Directory Hierarchy:
   /powerpc		Files generic to PowerPC architecture
   /sandbox		Files generic to HW-independent "sandbox"
   /sh			Files generic to SH architecture
+  /sparc		Files generic to SPARC architecture
   /x86			Files generic to x86 architecture
 /api			Machine/arch independent API for external apps
 /board			Board dependent files
@@ -323,6 +325,27 @@ The following options need to be configured:
 - CPU Daughterboard Type: (if CONFIG_ATSTK1000 is defined)
 		Define exactly one, e.g. CONFIG_ATSTK1002
 
+- CPU Module Type: (if CONFIG_COGENT is defined)
+		Define exactly one of
+		CONFIG_CMA286_60_OLD
+--- FIXME --- not tested yet:
+		CONFIG_CMA286_60, CONFIG_CMA286_21, CONFIG_CMA286_60P,
+		CONFIG_CMA287_23, CONFIG_CMA287_50
+
+- Motherboard Type: (if CONFIG_COGENT is defined)
+		Define exactly one of
+		CONFIG_CMA101, CONFIG_CMA102
+
+- Motherboard I/O Modules: (if CONFIG_COGENT is defined)
+		Define one or more of
+		CONFIG_CMA302
+
+- Motherboard Options: (if CONFIG_CMA101 or CONFIG_CMA102 are defined)
+		Define one or more of
+		CONFIG_LCD_HEARTBEAT	- update a character position on
+					  the LCD display every second with
+					  a "rotator" |\-/|\-/
+
 - Marvell Family Member
 		CONFIG_SYS_MVFS		- define it if you want to enable
 					  multiple fs option at one time
@@ -374,6 +397,15 @@ The following options need to be configured:
 		Defines the string to utilize when trying to match PCIe device
 		tree nodes for the given platform.
 
+		CONFIG_SYS_PPC_E500_DEBUG_TLB
+
+		Enables a temporary TLB entry to be used during boot to work
+		around limitations in e500v1 and e500v2 external debugger
+		support. This reduces the portions of the boot code where
+		breakpoints and single stepping do not work.  The value of this
+		symbol should be set to the TLB1 entry to be used for this
+		purpose.
+
 		CONFIG_SYS_FSL_ERRATUM_A004510
 
 		Enables a workaround for erratum A004510.  If set,
@@ -502,12 +534,6 @@ The following options need to be configured:
 		CONFIG_SYS_FSL_IFC_LE
 		Defines the IFC controller register space as Little Endian
 
-		CONFIG_SYS_FSL_IFC_CLK_DIV
-		Defines divider of platform clock(clock input to IFC controller).
-
-		CONFIG_SYS_FSL_LBC_CLK_DIV
-		Defines divider of platform clock(clock input to eLBC controller).
-
 		CONFIG_SYS_FSL_PBL_PBI
 		It enables addition of RCW (Power on reset configuration) in built image.
 		Please refer doc/README.pblimage for more details
@@ -552,6 +578,20 @@ The following options need to be configured:
 		CONFIG_SYS_FSL_SEC_LE
 		Defines the SEC controller register space as Little Endian
 
+- Intel Monahans options:
+		CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO
+
+		Defines the Monahans run mode to oscillator
+		ratio. Valid values are 8, 16, 24, 31. The core
+		frequency is this value multiplied by 13 MHz.
+
+		CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO
+
+		Defines the Monahans turbo mode to oscillator
+		ratio. Valid values are 1 (default if undefined) and
+		2. The core frequency as calculated above is multiplied
+		by this value.
+
 - MIPS CPU options:
 		CONFIG_SYS_INIT_SP_OFFSET
 
@@ -590,6 +630,29 @@ The following options need to be configured:
 		Select high exception vectors of the ARM core, e.g., do not
 		clear the V bit of the c1 register of CP15.
 
+		CONFIG_SYS_THUMB_BUILD
+
+		Use this flag to build U-Boot using the Thumb instruction
+		set for ARM architectures. Thumb instruction set provides
+		better code density. For ARM architectures that support
+		Thumb2 this flag will result in Thumb2 code generated by
+		GCC.
+
+		CONFIG_ARM_ERRATA_716044
+		CONFIG_ARM_ERRATA_742230
+		CONFIG_ARM_ERRATA_743622
+		CONFIG_ARM_ERRATA_751472
+		CONFIG_ARM_ERRATA_761320
+		CONFIG_ARM_ERRATA_773022
+		CONFIG_ARM_ERRATA_774769
+		CONFIG_ARM_ERRATA_794072
+
+		If set, the workarounds for these ARM errata are applied early
+		during U-Boot startup. Note that these options force the
+		workarounds to be applied; no CPU-type/version detection
+		exists, unlike the similar options in the Linux kernel. Do not
+		set these options unless they apply!
+
 		COUNTER_FREQUENCY
 		Generic timer clock source frequency.
 
@@ -598,6 +661,15 @@ The following options need to be configured:
 		different from COUNTER_FREQUENCY, and can only be determined
 		at run time.
 
+		NOTE: The following can be machine specific errata. These
+		do have ability to provide rudimentary version and machine
+		specific checks, but expect no product checks.
+		CONFIG_ARM_ERRATA_430973
+		CONFIG_ARM_ERRATA_454179
+		CONFIG_ARM_ERRATA_621766
+		CONFIG_ARM_ERRATA_798870
+		CONFIG_ARM_ERRATA_801819
+
 - Tegra SoC options:
 		CONFIG_TEGRA_SUPPORT_NON_SECURE
 
@@ -658,6 +730,11 @@ The following options need to be configured:
 		This causes ft_system_setup() to be called before booting
 		the kernel.
 
+		CONFIG_OF_BOOT_CPU
+
+		This define fills in the correct boot CPU in the boot
+		param header, the default value is zero if undefined.
+
 		CONFIG_OF_IDE_FIXUP
 
 		U-Boot can detect if an IDE device is present or not.
@@ -733,6 +810,59 @@ The following options need to be configured:
 		port routines must be defined elsewhere
 		(i.e. serial_init(), serial_getc(), ...)
 
+		CONFIG_CFB_CONSOLE
+		Enables console device for a color framebuffer. Needs following
+		defines (cf. smiLynxEM, i8042)
+			VIDEO_FB_LITTLE_ENDIAN	graphic memory organisation
+						(default big endian)
+			VIDEO_HW_RECTFILL	graphic chip supports
+						rectangle fill
+						(cf. smiLynxEM)
+			VIDEO_HW_BITBLT		graphic chip supports
+						bit-blit (cf. smiLynxEM)
+			VIDEO_VISIBLE_COLS	visible pixel columns
+						(cols=pitch)
+			VIDEO_VISIBLE_ROWS	visible pixel rows
+			VIDEO_PIXEL_SIZE	bytes per pixel
+			VIDEO_DATA_FORMAT	graphic data format
+						(0-5, cf. cfb_console.c)
+			VIDEO_FB_ADRS		framebuffer address
+			VIDEO_KBD_INIT_FCT	keyboard int fct
+						(i.e. rx51_kp_init())
+			VIDEO_TSTC_FCT		test char fct
+						(i.e. rx51_kp_tstc)
+			VIDEO_GETC_FCT		get char fct
+						(i.e. rx51_kp_getc)
+			CONFIG_VIDEO_LOGO	display Linux logo in
+						upper left corner
+			CONFIG_VIDEO_BMP_LOGO	use bmp_logo.h instead of
+						linux_logo.h for logo.
+						Requires CONFIG_VIDEO_LOGO
+			CONFIG_CONSOLE_EXTRA_INFO
+						additional board info beside
+						the logo
+			CONFIG_HIDE_LOGO_VERSION
+						do not display bootloader
+						version string
+
+		When CONFIG_CFB_CONSOLE_ANSI is defined, console will support
+		a limited number of ANSI escape sequences (cursor control,
+		erase functions and limited graphics rendition control).
+
+		When CONFIG_CFB_CONSOLE is defined, video console is
+		default i/o. Serial console can be forced with
+		environment 'console=serial'.
+
+		When CONFIG_SILENT_CONSOLE is defined, all console
+		messages (by U-Boot and Linux!) can be silenced with
+		the "silent" environment variable. See
+		doc/README.silent for more information.
+
+		CONFIG_SYS_CONSOLE_BG_COL: define the backgroundcolor, default
+			is 0x00.
+		CONFIG_SYS_CONSOLE_FG_COL: define the foregroundcolor, default
+			is 0xa0.
+
 - Console Baudrate:
 		CONFIG_BAUDRATE - in bps
 		Select one of the baudrates listed in
@@ -747,6 +877,23 @@ The following options need to be configured:
 		must be defined, to setup the maximum idle timeout for
 		the SMC.
 
+- Pre-Console Buffer:
+		Prior to the console being initialised (i.e. serial UART
+		initialised etc) all console output is silently discarded.
+		Defining CONFIG_PRE_CONSOLE_BUFFER will cause U-Boot to
+		buffer any console messages prior to the console being
+		initialised to a buffer of size CONFIG_PRE_CON_BUF_SZ
+		bytes located at CONFIG_PRE_CON_BUF_ADDR. The buffer is
+		a circular buffer, so if more than CONFIG_PRE_CON_BUF_SZ
+		bytes are output before the console is initialised, the
+		earlier bytes are discarded.
+
+		Note that when printing the buffer a copy is made on the
+		stack so CONFIG_PRE_CON_BUF_SZ must fit on the stack.
+
+		'Sane' compilers will generate smaller code if
+		CONFIG_PRE_CON_BUF_SZ is a power of 2
+
 - Autoboot Command:
 		CONFIG_BOOTCOMMAND
 		Only needed when CONFIG_BOOTDELAY is enabled;
@@ -823,9 +970,13 @@ The following options need to be configured:
 		CONFIG_CMD_AES		  AES 128 CBC encrypt/decrypt
 		CONFIG_CMD_ASKENV	* ask for env variable
 		CONFIG_CMD_BDI		  bdinfo
+		CONFIG_CMD_BEDBUG	* Include BedBug Debugger
+		CONFIG_CMD_BMP		* BMP support
+		CONFIG_CMD_BSP		* Board specific commands
 		CONFIG_CMD_BOOTD	  bootd
 		CONFIG_CMD_BOOTI	* ARM64 Linux kernel Image support
 		CONFIG_CMD_CACHE	* icache, dcache
+		CONFIG_CMD_CLK   	* clock command support
 		CONFIG_CMD_CONSOLE	  coninfo
 		CONFIG_CMD_CRC32	* crc32
 		CONFIG_CMD_DATE		* support for RTC, date/time...
@@ -1186,6 +1337,10 @@ The following options need to be configured:
 		CONFIG_LAN91C96
 		Support for SMSC's LAN91C96 chips.
 
+			CONFIG_LAN91C96_BASE
+			Define this to hold the physical address
+			of the LAN91C96's I/O space
+
 			CONFIG_LAN91C96_USE_32_BIT
 			Define this to enable 32 bit addressing
 
@@ -1250,7 +1405,7 @@ The following options need to be configured:
 
 - PWM Support:
 		CONFIG_PWM_IMX
-		Support for PWM module on the imx6.
+		Support for PWM modul on the imx6.
 
 - TPM Support:
 		CONFIG_TPM
@@ -1370,6 +1525,10 @@ The following options need to be configured:
 				Derive USB clock from external clock "blah"
 				- CONFIG_SYS_USB_EXTC_CLK 0x02
 
+				CONFIG_SYS_USB_BRG_CLK 0xBLAH
+				Derive USB clock from brgclk
+				- CONFIG_SYS_USB_BRG_CLK 0x04
+
 		If you have a USB-IF assigned VendorID then you may wish to
 		define your own vendor specific values either in BoardName.h
 		or directly in usbd_vendor_info.h. If you don't define
@@ -1425,6 +1584,9 @@ The following options need to be configured:
 			CONFIG_SH_MMCIF_CLK
 			Define the clock frequency for MMCIF
 
+		CONFIG_GENERIC_MMC
+		Enable the generic MMC driver
+
 		CONFIG_SUPPORT_EMMC_BOOT
 		Enable some additional features of the eMMC boot partitions.
 
@@ -1519,23 +1681,26 @@ The following options need to be configured:
 		to generate and write the Backup GUID Partition Table.)
 		This occurs when the specified "partition name" on the
 		"fastboot flash" command line matches this value.
-		The default is "gpt" if undefined.
-
-		CONFIG_FASTBOOT_MBR_NAME
-		The fastboot "flash" command supports writing the downloaded
-		image to DOS MBR.
-		This occurs when the "partition name" specified on the
-		"fastboot flash" command line matches this value.
-		If not defined the default value "mbr" is used.
+		Default is GPT_ENTRY_NAME (currently "gpt") if undefined.
 
 - Journaling Flash filesystem support:
-		CONFIG_JFFS2_NAND
+		CONFIG_JFFS2_NAND, CONFIG_JFFS2_NAND_OFF, CONFIG_JFFS2_NAND_SIZE,
+		CONFIG_JFFS2_NAND_DEV
 		Define these for a default partition on a NAND device
 
 		CONFIG_SYS_JFFS2_FIRST_SECTOR,
 		CONFIG_SYS_JFFS2_FIRST_BANK, CONFIG_SYS_JFFS2_NUM_BANKS
 		Define these for a default partition on a NOR device
 
+		CONFIG_SYS_JFFS_CUSTOM_PART
+		Define this to create an own partition. You have to provide a
+		function struct part_info* jffs2_part_info(int part_num)
+
+		If you define only one JFFS2 partition you may also want to
+		#define CONFIG_SYS_JFFS_SINGLE_PART	1
+		to disable the command chpart. This is the default when you
+		have not defined a custom partition
+
 - FAT(File Allocation Table) filesystem write function support:
 		CONFIG_FAT_WRITE
 
@@ -1545,6 +1710,13 @@ The following options need to be configured:
 		This will also enable the command "fatwrite" enabling the
 		user to write files to FAT.
 
+CBFS (Coreboot Filesystem) support
+		CONFIG_CMD_CBFS
+
+		Define this to enable support for reading from a Coreboot
+		filesystem. Available commands are cbfsinit, cbfsinfo, cbfsls
+		and cbfsload.
+
 - FAT(File Allocation Table) filesystem cluster size:
 		CONFIG_FS_FAT_MAX_CLUSTSIZE
 
@@ -1563,6 +1735,45 @@ The following options need to be configured:
 		instead.
 
 - Video support:
+		CONFIG_VIDEO
+
+		Define this to enable video support (for output to
+		video).
+
+		CONFIG_VIDEO_CT69000
+
+		Enable Chips & Technologies 69000 Video chip
+
+		CONFIG_VIDEO_SMI_LYNXEM
+		Enable Silicon Motion SMI 712/710/810 Video chip. The
+		video output is selected via environment 'videoout'
+		(1 = LCD and 2 = CRT). If videoout is undefined, CRT is
+		assumed.
+
+		For the CT69000 and SMI_LYNXEM drivers, videomode is
+		selected via environment 'videomode'. Two different ways
+		are possible:
+		- "videomode=num"   'num' is a standard LiLo mode numbers.
+		Following standard modes are supported	(* is default):
+
+		      Colors	640x480 800x600 1024x768 1152x864 1280x1024
+		-------------+---------------------------------------------
+		      8 bits |	0x301*	0x303	 0x305	  0x161	    0x307
+		     15 bits |	0x310	0x313	 0x316	  0x162	    0x319
+		     16 bits |	0x311	0x314	 0x317	  0x163	    0x31A
+		     24 bits |	0x312	0x315	 0x318	    ?	    0x31B
+		-------------+---------------------------------------------
+		(i.e. setenv videomode 317; saveenv; reset;)
+
+		- "videomode=bootargs" all the video parameters are parsed
+		from the bootargs. (See drivers/video/videomodes.c)
+
+
+		CONFIG_VIDEO_SED13806
+		Enable Epson SED13806 driver. This driver supports 8bpp
+		and 16bpp modes defined by CONFIG_VIDEO_SED13806_8BPP
+		or CONFIG_VIDEO_SED13806_16BPP
+
 		CONFIG_FSL_DIU_FB
 		Enable the Freescale DIU video driver.	Reference boards for
 		SOCs that have a DIU should define this macro to enable DIU
@@ -1570,6 +1781,7 @@ The following options need to be configured:
 
 			CONFIG_SYS_DIU_ADDR
 			CONFIG_VIDEO
+			CONFIG_CMD_BMP
 			CONFIG_CFB_CONSOLE
 			CONFIG_VIDEO_SW_CURSOR
 			CONFIG_VGA_AS_SINGLE_DEVICE
@@ -1630,6 +1842,9 @@ The following options need to be configured:
 
 			320x240. Black & white.
 
+		Normally display is black on white background; define
+		CONFIG_SYS_WHITE_ON_BLACK to get it inverted.
+
 		CONFIG_LCD_ALIGNMENT
 
 		Normally the LCD is page-aligned (typically 4KB). If this is
@@ -1638,6 +1853,12 @@ The following options need to be configured:
 		here, since it is cheaper to change data cache settings on
 		a per-section basis.
 
+		CONFIG_CONSOLE_SCROLL_LINES
+
+		When the console need to be scrolled, this is the number of
+		lines to scroll by. It defaults to 1. Increasing this makes
+		the console jump but can help speed up operation when scrolling
+		is slow.
 
 		CONFIG_LCD_ROTATION
 
@@ -1722,6 +1943,12 @@ The following options need to be configured:
 		can be displayed via the splashscreen support or the
 		bmp command.
 
+- Do compressing for memory range:
+		CONFIG_CMD_ZIP
+
+		If this option is set, it would use zlib deflate method
+		to compress the specified memory at its best effort.
+
 - Compression support:
 		CONFIG_GZIP
 
@@ -1981,7 +2208,7 @@ The following options need to be configured:
 
 		A byte containing the id of the VLAN.
 
-- Status LED:	CONFIG_LED_STATUS
+- Status LED:	CONFIG_STATUS_LED
 
 		Several configurations allow to display the current
 		status using a LED. For instance, the LED will blink
@@ -1989,15 +2216,15 @@ The following options need to be configured:
 		soon as a reply to a BOOTP request was received, and
 		start blinking slow once the Linux kernel is running
 		(supported by a status LED driver in the Linux
-		kernel). Defining CONFIG_LED_STATUS enables this
+		kernel). Defining CONFIG_STATUS_LED enables this
 		feature in U-Boot.
 
 		Additional options:
 
-		CONFIG_LED_STATUS_GPIO
+		CONFIG_GPIO_LED
 		The status LED can be connected to a GPIO pin.
 		In such cases, the gpio_led driver can be used as a
-		status LED backend implementation. Define CONFIG_LED_STATUS_GPIO
+		status LED backend implementation. Define CONFIG_GPIO_LED
 		to include the gpio_led driver in the U-Boot binary.
 
 		CONFIG_GPIO_LED_INVERTED_TABLE
@@ -2104,6 +2331,8 @@ The following options need to be configured:
 		  - CONFIG_SYS_I2C_SH_SPEED3 for for the speed channel 3
 		  - CONFIG_SYS_I2C_SH_BASE4 for setting the register channel 4
 		  - CONFIG_SYS_I2C_SH_SPEED4 for for the speed channel 4
+		  - CONFIG_SYS_I2C_SH_BASE5 for setting the register channel 5
+		  - CONFIG_SYS_I2C_SH_SPEED5 for for the speed channel 5
 		  - CONFIG_SYS_I2C_SH_NUM_CONTROLLERS for number of i2c buses
 
 		- drivers/i2c/omap24xx_i2c.c
@@ -2157,7 +2386,10 @@ The following options need to be configured:
 		additional defines:
 
 		CONFIG_SYS_NUM_I2C_BUSES
-		Hold the number of i2c buses you want to use.
+		Hold the number of i2c buses you want to use. If you
+		don't use/have i2c muxes on your i2c bus, this
+		is equal to CONFIG_SYS_NUM_I2C_ADAPTERS, and you can
+		omit this define.
 
 		CONFIG_SYS_I2C_DIRECT_BUS
 		define this, if you don't use i2c muxes on your hardware.
@@ -2371,7 +2603,7 @@ The following options need to be configured:
 		will skip addresses 0x50 and 0x68 on a board with one I2C bus
 
 			#define CONFIG_I2C_MULTI_BUS
-			#define CONFIG_SYS_I2C_NOPROBES	{{0,0x50},{0,0x68},{1,0x54}}
+			#define CONFIG_SYS_I2C_MULTI_NOPROBES	{{0,0x50},{0,0x68},{1,0x54}}
 
 		will skip addresses 0x50 and 0x68 on bus 0 and address 0x54 on bus 1
 
@@ -2731,6 +2963,19 @@ The following options need to be configured:
 		this is instead controlled by the value of
 		/config/load-environment.
 
+- Parallel Flash support:
+		CONFIG_SYS_NO_FLASH
+
+		Traditionally U-Boot was run on systems with parallel NOR
+		flash. This option is used to disable support for parallel NOR
+		flash. This option should be defined if the board does not have
+		parallel flash.
+
+		If this option is not defined one of the generic flash drivers
+		(e.g.  CONFIG_FLASH_CFI_DRIVER or CONFIG_ST_SMI) must be
+		selected or the board must provide an implementation of the
+		flash API (see include/flash.h).
+
 - DataFlash Support:
 		CONFIG_HAS_DATAFLASH
 
@@ -2834,6 +3079,16 @@ The following options need to be configured:
 		This enables 'hdmidet' command which returns true if an
 		HDMI monitor is detected.  This command is i.MX 6 specific.
 
+		CONFIG_CMD_BMODE
+		This enables the 'bmode' (bootmode) command for forcing
+		a boot from specific media.
+
+		This is useful for forcing the ROM's usb downloader to
+		activate upon a watchdog reset which is nice when iterating
+		on U-Boot.  Using the reset button or running bmode normal
+		will set it back to normal.  This command currently
+		supports i.MX53 and i.MX6.
+
 - bootcount support:
 		CONFIG_BOOTCOUNT_LIMIT
 
@@ -2842,6 +3097,8 @@ The following options need to be configured:
 
 		CONFIG_AT91SAM9XE
 		enable special bootcounter support on at91sam9xe based boards.
+		CONFIG_BLACKFIN
+		enable special bootcounter support on blackfin based boards.
 		CONFIG_SOC_DA8XX
 		enable special bootcounter support on da850 based boards.
 		CONFIG_BOOTCOUNT_RAM
@@ -3218,6 +3475,10 @@ FIT uImage format:
 		consider that a completely unreadable NAND block is bad,
 		and thus should be skipped silently.
 
+		CONFIG_SPL_ABORT_ON_RAW_IMAGE
+		When defined, SPL will proceed to another boot method
+		if the image it has loaded does not have a signature.
+
 		CONFIG_SPL_RELOC_STACK
 		Adress of the start of the stack SPL will use after
 		relocation.  If unspecified, this is equal to
@@ -3248,6 +3509,26 @@ FIT uImage format:
 		CONFIG_SPL_INIT_MINIMAL
 		Arch init code should be built for a very small image
 
+		CONFIG_SPL_LIBCOMMON_SUPPORT
+		Support for common/libcommon.o in SPL binary
+
+		CONFIG_SPL_LIBDISK_SUPPORT
+		Support for disk/libdisk.o in SPL binary
+
+		CONFIG_SPL_I2C_SUPPORT
+		Support for drivers/i2c/libi2c.o in SPL binary
+
+		CONFIG_SPL_GPIO_SUPPORT
+		Support for drivers/gpio/libgpio.o in SPL binary
+
+		CONFIG_SPL_MMC_SUPPORT
+		Support for drivers/mmc/libmmc.o in SPL binary
+
+		CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR,
+		CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS,
+		Address and partition on the MMC to load U-Boot from
+		when the MMC is being used in raw mode.
+
 		CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
 		Partition on the MMC to load U-Boot from when the MMC is being
 		used in raw mode
@@ -3266,6 +3547,12 @@ FIT uImage format:
 		Partition on the MMC to load U-Boot from when the MMC is being
 		used in fs mode
 
+		CONFIG_SPL_FAT_SUPPORT
+		Support for fs/fat/libfat.o in SPL binary
+
+		CONFIG_SPL_EXT_SUPPORT
+		Support for EXT filesystem in SPL binary
+
 		CONFIG_SPL_FS_LOAD_PAYLOAD_NAME
 		Filename to read to load U-Boot when reading from filesystem
 
@@ -3304,10 +3591,18 @@ FIT uImage format:
 		Support for a lightweight UBI (fastmap) scanner and
 		loader
 
+		CONFIG_SPL_MTD_SUPPORT
+		Support for the MTD subsystem within SPL.  Useful for
+		environment on NAND support within SPL.
+
 		CONFIG_SPL_NAND_RAW_ONLY
 		Support to boot only raw u-boot.bin images. Use this only
 		if you need to save space.
 
+		CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+		Set for the SPL on PPC mpc8xxx targets, support for
+		drivers/ddr/fsl/libddr.o in SPL binary.
+
 		CONFIG_SPL_COMMON_INIT_DDR
 		Set for common ddr init with serial presence detect in
 		SPL binary.
@@ -3343,9 +3638,29 @@ FIT uImage format:
 		Support for an OMAP3-specific set of functions to return the
 		ID and MFR of the first attached NAND chip, if present.
 
+		CONFIG_SPL_SERIAL_SUPPORT
+		Support for drivers/serial/libserial.o in SPL binary
+
+		CONFIG_SPL_SPI_FLASH_SUPPORT
+		Support for drivers/mtd/spi/libspi_flash.o in SPL binary
+
+		CONFIG_SPL_SPI_SUPPORT
+		Support for drivers/spi/libspi.o in SPL binary
+
 		CONFIG_SPL_RAM_DEVICE
 		Support for running image already present in ram, in SPL binary
 
+		CONFIG_SPL_LIBGENERIC_SUPPORT
+		Support for lib/libgeneric.o in SPL binary
+
+		CONFIG_SPL_ENV_SUPPORT
+		Support for the environment operating in SPL binary
+
+		CONFIG_SPL_NET_SUPPORT
+		Support for the net/libnet.o in SPL binary.
+		It conflicts with SPL env from storage medium specified by
+		CONFIG_ENV_IS_xxx but CONFIG_ENV_IS_NOWHERE
+
 		CONFIG_SPL_PAD_TO
 		Image offset to which the SPL should be padded before appending
 		the SPL payload. By default, this is defined as
@@ -3432,6 +3747,21 @@ Configuration Settings:
 - CONFIG_SYS_BAUDRATE_TABLE:
 		List of legal baudrate settings for this board.
 
+- CONFIG_SYS_CONSOLE_INFO_QUIET
+		Suppress display of console information at boot.
+
+- CONFIG_SYS_CONSOLE_IS_IN_ENV
+		If the board specific function
+			extern int overwrite_console (void);
+		returns 1, the stdin, stderr and stdout are switched to the
+		serial port, else the settings in the environment are used.
+
+- CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+		Enable the call to overwrite_console().
+
+- CONFIG_SYS_CONSOLE_ENV_OVERWRITE
+		Enable overwrite of previous console environment settings.
+
 - CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END:
 		Begin and End addresses of the area used by the
 		simple memory test.
@@ -3479,6 +3809,10 @@ Configuration Settings:
 - CONFIG_SYS_SDRAM_BASE:
 		Physical start address of SDRAM. _Must_ be 0 here.
 
+- CONFIG_SYS_MBIO_BASE:
+		Physical start address of Motherboard I/O (if using a
+		Cogent motherboard)
+
 - CONFIG_SYS_FLASH_BASE:
 		Physical start address of Flash memory.
 
@@ -3910,7 +4244,7 @@ to save the current settings.
 	  This setting describes a second storage area of CONFIG_ENV_SIZE
 	  size used to hold a redundant copy of the environment data, so
 	  that there is a valid backup copy in case there is a power failure
-	  during a "saveenv" operation. CONFIG_ENV_OFFSET_REDUND must be
+	  during a "saveenv" operation. CONFIG_ENV_OFFSET_RENDUND must be
 	  aligned to an erase sector boundary.
 
 	- CONFIG_ENV_SPI_BUS (optional):
@@ -3961,7 +4295,7 @@ but it can not erase, write this NOR flash by SRIO or PCIE interface.
 	  This setting describes a second storage area of CONFIG_ENV_SIZE
 	  size used to hold a redundant copy of the environment data, so
 	  that there is a valid backup copy in case there is a power failure
-	  during a "saveenv" operation.	 CONFIG_ENV_OFFSET_REDUND must be
+	  during a "saveenv" operation.	 CONFIG_ENV_OFFSET_RENDUND must be
 	  aligned to an erase block boundary.
 
 	- CONFIG_ENV_RANGE (optional):
@@ -4020,7 +4354,7 @@ but it can not erase, write this NOR flash by SRIO or PCIE interface.
 
          Define this to a string that is the name of the block device.
 
-       - FAT_ENV_DEVICE_AND_PART:
+       - FAT_ENV_DEV_AND_PART:
 
          Define this to a string to specify the partition of the device. It can
          be as following:
@@ -4262,7 +4596,7 @@ Low Level (hardware related) configuration options:
 		CONFIG_SYS_GBL_DATA_OFFSET is chosen such that the initial
 		data is located at the end of the available space
 		(sometimes written as (CONFIG_SYS_INIT_RAM_SIZE -
-		GENERATED_GBL_DATA_SIZE), and the initial stack is just
+		CONFIG_SYS_INIT_DATA_SIZE), and the initial stack is just
 		below that area (growing from (CONFIG_SYS_INIT_RAM_ADDR +
 		CONFIG_SYS_GBL_DATA_OFFSET) downward.
 
@@ -4321,6 +4655,11 @@ Low Level (hardware related) configuration options:
 		enable SPI microcode relocation patch (MPC8xx);
 		define relocation offset in DPRAM [SCC4]
 
+- CONFIG_SYS_USE_OSCCLK:
+		Use OSCM clock mode on MBX8xx board. Be careful,
+		wrong setting might damage your board. Read
+		doc/README.MBX before setting this variable!
+
 - CONFIG_SYS_CPM_POST_WORD_ADDR: (MPC8xx, MPC8260 only)
 		Offset of the bootmode word in DPRAM used by post
 		(Power On Self Tests). This definition overrides
@@ -4503,6 +4842,12 @@ Low Level (hardware related) configuration options:
 		addressable memory. This option causes some memory accesses
 		to be mapped through map_sysmem() / unmap_sysmem().
 
+- CONFIG_USE_ARCH_MEMCPY
+  CONFIG_USE_ARCH_MEMSET
+		If these options are used a optimized version of memcpy/memset will
+		be used if available. These functions may be faster under some
+		conditions but may increase the binary size.
+
 - CONFIG_X86_RESET_VECTOR
 		If defined, the x86 reset vector code is included. This is not
 		needed when U-Boot is running from Coreboot.
@@ -4558,6 +4903,10 @@ within that device.
 	Specifies that QE/FMAN firmware is located on the primary SD/MMC
 	device.  CONFIG_SYS_FMAN_FW_ADDR is the byte offset on that device.
 
+- CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH
+	Specifies that QE/FMAN firmware is located on the primary SPI
+	device.  CONFIG_SYS_FMAN_FW_ADDR is the byte offset on that device.
+
 - CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 	Specifies that QE/FMAN firmware is located in the remote (master)
 	memory space.	CONFIG_SYS_FMAN_FW_ADDR is a virtual address which
@@ -4576,12 +4925,34 @@ within that device.
 - CONFIG_FSL_MC_ENET
 	Enable the MC driver for Layerscape SoCs.
 
+- CONFIG_SYS_LS_MC_FW_ADDR
+	The address in the storage device where the firmware is located.  The
+	meaning of this address depends on which CONFIG_SYS_LS_MC_FW_IN_xxx macro
+	is also specified.
+
+- CONFIG_SYS_LS_MC_FW_LENGTH
+	The maximum possible size of the firmware.  The firmware binary format
+	has a field that specifies the actual size of the firmware, but it
+	might not be possible to read any part of the firmware unless some
+	local storage is allocated to hold the entire firmware first.
+
+- CONFIG_SYS_LS_MC_FW_IN_NOR
+	Specifies that MC firmware is located in NOR flash, mapped as
+	normal addressable memory via the LBC. CONFIG_SYS_LS_MC_FW_ADDR is the
+	virtual address in NOR flash.
+
 Freescale Layerscape Debug Server Support:
 -------------------------------------------
 The Freescale Layerscape Debug Server Support supports the loading of
 "Debug Server firmware" and triggering SP boot-rom.
 This firmware often needs to be loaded during U-Boot booting.
 
+- CONFIG_FSL_DEBUG_SERVER
+	Enable the Debug Server for Layerscape SoCs.
+
+- CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE
+	Define minimum DDR size required for debug server image
+
 - CONFIG_SYS_MC_RSV_MEM_ALIGN
 	Define alignment of reserved memory MC requires
 
@@ -5882,6 +6253,11 @@ For PowerPC, the following registers have specific use:
     average for all boards 752 bytes for the whole U-Boot image,
     624 text + 127 data).
 
+On Blackfin, the normal C ABI (except for P3) is followed as documented here:
+	http://docs.blackfin.uclinux.org/doku.php?id=application_binary_interface
+
+    ==> U-Boot will use P3 to hold a pointer to the global data
+
 On ARM, the following registers are used:
 
 	R0:	function argument word/integer result

api/Kconfig

@@ -1,9 +0,0 @@
-menu "API"
-
-config API
-	bool "Enable U-Boot API"
-	default n
-	help
-	  This option enables the U-Boot API. See api/README for more information.
-
-endmenu

api/api.c

@@ -495,47 +495,45 @@ static int API_env_set(va_list ap)
  */
 static int API_env_enum(va_list ap)
 {
-	int i, buflen;
-	char *last, **next, *s;
-	ENTRY *match, search;
-	static char *var;
+	int i, n;
+	char *last, **next;
 
 	last = (char *)va_arg(ap, unsigned long);
 
 	if ((next = (char **)va_arg(ap, uintptr_t)) == NULL)
 		return API_EINVAL;
 
-	if (last == NULL) {
-		var = NULL;
-		i = 0;
-	} else {
-		var = strdup(last);
-		s = strchr(var, '=');
-		if (s != NULL)
-			*s = 0;
-		search.key = var;
-		i = hsearch_r(search, FIND, &match, &env_htab, 0);
-		if (i == 0) {
-			i = API_EINVAL;
-			goto done;
+	if (last == NULL)
+		/* start over */
+		*next = ((char *)env_get_addr(0));
+	else {
+		*next = last;
+
+		for (i = 0; env_get_char(i) != '\0'; i = n + 1) {
+			for (n = i; env_get_char(n) != '\0'; ++n) {
+				if (n >= CONFIG_ENV_SIZE) {
+					/* XXX shouldn't we set *next = NULL?? */
+					return 0;
+				}
+			}
+
+			if (envmatch((uchar *)last, i) < 0)
+				continue;
+
+			/* try to get next name */
+			i = n + 1;
+			if (env_get_char(i) == '\0') {
+				/* no more left */
+				*next = NULL;
+				return 0;
+			}
+
+			*next = ((char *)env_get_addr(i));
+			return 0;
 		}
 	}
 
-	/* match the next entry after i */
-	i = hmatch_r("", i, &match, &env_htab);
-	if (i == 0)
-		goto done;
-	buflen = strlen(match->key) + strlen(match->data) + 2;
-	var = realloc(var, buflen);
-	snprintf(var, buflen, "%s=%s", match->key, match->data);
-	*next = var;
 	return 0;
-
-done:
-	free(var);
-	var = NULL;
-	*next = NULL;
-	return i;
 }
 
 /*

api/api_storage.c

@@ -37,11 +37,11 @@ struct stor_spec {
 	int		max_dev;
 	int		enum_started;
 	int		enum_ended;
-	int		type;	/* "external" type: DT_STOR_{IDE,USB,etc} */
+	int		type;		/* "external" type: DT_STOR_{IDE,USB,etc} */
 	char		*name;
 };
 
-static struct stor_spec specs[ENUM_MAX] = { { 0, 0, 0, 0, NULL }, };
+static struct stor_spec specs[ENUM_MAX] = { { 0, 0, 0, 0, "" }, };
 
 
 void dev_stor_init(void)
@@ -88,67 +88,88 @@ void dev_stor_init(void)
  *
  * type:	storage group type - ENUM_IDE, ENUM_SCSI etc.
  *
+ * first:	if 1 the first device in the storage group is returned (if
+ *              exists), if 0 the next available device is searched
+ *
  * more:	returns 0/1 depending if there are more devices in this group
  *		available (for future iterations)
  *
  * returns:	0/1 depending if device found in this iteration
  */
-static int dev_stor_get(int type, int *more, struct device_info *di)
+static int dev_stor_get(int type, int first, int *more, struct device_info *di)
 {
-	struct blk_desc *dd;
 	int found = 0;
-	int i = 0;
+	*more = 0;
 
-	/* Wasn't configured for this type, return 0 directly */
-	if (specs[type].name == NULL)
-		return 0;
+	int i;
 
-	if (di->cookie != NULL) {
-		/* Find the last device we've returned  */
-		for (i = 0; i < specs[type].max_dev; i++) {
+	struct blk_desc *dd;
+
+	if (first) {
+		di->cookie = (void *)blk_get_dev(specs[type].name, 0);
+		if (di->cookie == NULL)
+			return 0;
+		else
+			found = 1;
+
+		/* provide hint if there are more devices in
+		 * this group to enumerate */
+		if (1 < specs[type].max_dev)
+			*more = 1;
+
+	} else {
+		for (i = 0; i < specs[type].max_dev; i++)
 			if (di->cookie ==
 			    (void *)blk_get_dev(specs[type].name, i)) {
-				i += 1;
+				/* previous cookie found -- advance to the
+				 * next device, if possible */
+
+				if (++i >= specs[type].max_dev) {
+					/* out of range, no more to enum */
+					di->cookie = NULL;
+					break;
+				}
+
+				di->cookie = (void *)blk_get_dev(
+							specs[type].name, i);
+				if (di->cookie == NULL)
+					return 0;
+				else
+					found = 1;
+
+				/* provide hint if there are more devices in
+				 * this group to enumerate */
+				if ((i + 1) < specs[type].max_dev)
+					*more = 1;
+
 				break;
 			}
-		}
 	}
 
-	for (; i < specs[type].max_dev; i++) {
-		di->cookie = (void *)blk_get_dev(specs[type].name, i);
-
-		if (di->cookie != NULL) {
-			found = 1;
-			break;
-		}
-	}
-
-	if (i == specs[type].max_dev)
-		*more = 0;
-	else
-		*more = 1;
-
 	if (found) {
 		di->type = specs[type].type;
 
-		dd = (struct blk_desc *)di->cookie;
-		if (dd->type == DEV_TYPE_UNKNOWN) {
-			debugf("device instance exists, but is not active..");
-			found = 0;
-		} else {
-			di->di_stor.block_count = dd->lba;
-			di->di_stor.block_size = dd->blksz;
+		if (di->cookie != NULL) {
+			dd = (struct blk_desc *)di->cookie;
+			if (dd->type == DEV_TYPE_UNKNOWN) {
+				debugf("device instance exists, but is not active..");
+				found = 0;
+			} else {
+				di->di_stor.block_count = dd->lba;
+				di->di_stor.block_size = dd->blksz;
+			}
 		}
-	} else {
+
+	} else
 		di->cookie = NULL;
-	}
 
 	return found;
 }
 
 
-/* returns: ENUM_IDE, ENUM_USB etc. based on struct blk_desc */
-
+/*
+ * returns:	ENUM_IDE, ENUM_USB etc. based on struct blk_desc
+ */
 static int dev_stor_type(struct blk_desc *dd)
 {
 	int i, j;
@@ -162,8 +183,9 @@ static int dev_stor_type(struct blk_desc *dd)
 }
 
 
-/* returns: 0/1 whether cookie points to some device in this group */
-
+/*
+ * returns:	0/1 whether cookie points to some device in this group
+ */
 static int dev_is_stor(int type, struct device_info *di)
 {
 	return (dev_stor_type(di->cookie) == type) ? 1 : 0;
@@ -194,16 +216,18 @@ static int dev_enum_stor(int type, struct device_info *di)
 	 */
 
 	if (di->cookie == NULL) {
+
 		debugf("group%d - enum restart\n", type);
 
 		/*
 		 * 1. Enumeration (re-)started: take the first available
 		 * device, if exists
 		 */
-		found = dev_stor_get(type, &more, di);
+		found = dev_stor_get(type, 1, &more, di);
 		specs[type].enum_started = 1;
 
 	} else if (dev_is_stor(type, di)) {
+
 		debugf("group%d - enum continued for the next device\n", type);
 
 		if (specs[type].enum_ended) {
@@ -212,9 +236,10 @@ static int dev_enum_stor(int type, struct device_info *di)
 		}
 
 		/* 2a. Attempt to take a next available device in the group */
-		found = dev_stor_get(type, &more, di);
+		found = dev_stor_get(type, 0, &more, di);
 
 	} else {
+
 		if (specs[type].enum_ended) {
 			debugf("group %d - already enumerated, skipping\n", type);
 			return 0;
@@ -226,7 +251,7 @@ static int dev_enum_stor(int type, struct device_info *di)
 			/*
 			 * 2b.  If enumerating devices in this group did not
 			 * happen before, it means the cookie pointed to a
-			 * device from some other group (another storage
+			 * device frome some other group (another storage
 			 * group, or network); in this case try to take the
 			 * first available device from our group
 			 */
@@ -236,7 +261,7 @@ static int dev_enum_stor(int type, struct device_info *di)
 			 * Attempt to take the first device in this group:
 			 *'first element' flag is set
 			 */
-			found = dev_stor_get(type, &more, di);
+			found = dev_stor_get(type, 1, &more, di);
 
 		} else {
 			errf("group%d - out of order iteration\n", type);
@@ -253,7 +278,7 @@ static int dev_enum_stor(int type, struct device_info *di)
 
 	if (found)
 		debugf("device found, returning cookie 0x%08x\n",
-		       (u_int32_t)di->cookie);
+			(u_int32_t)di->cookie);
 	else
 		debugf("no device found\n");
 
@@ -274,7 +299,9 @@ int dev_enum_storage(struct device_info *di)
 {
 	int i;
 
-	/* check: ide, usb, scsi, mmc */
+	/*
+	 * check: ide, usb, scsi, mmc
+	 */
 	for (i = ENUM_IDE; i < ENUM_MAX; i ++) {
 		if (dev_enum_stor(i, di))
 			return 1;
@@ -331,14 +358,10 @@ lbasize_t dev_read_stor(void *cookie, void *buf, lbasize_t len, lbastart_t start
 	if (!dev_stor_is_valid(type, dd))
 		return 0;
 
-#ifdef CONFIG_BLK
-	return blk_dread(dd, start, len, buf);
-#else
 	if ((dd->block_read) == NULL) {
 		debugf("no block_read() for device 0x%08x\n", cookie);
 		return 0;
 	}
 
 	return dd->block_read(dd, start, len, buf);
-#endif	/* defined(CONFIG_BLK) */
 }

arch/Kconfig

@@ -12,10 +12,6 @@ config ARC
 	bool "ARC architecture"
 	select HAVE_PRIVATE_LIBGCC
 	select SUPPORT_OF_CONTROL
-	select ARCH_EARLY_INIT_R
-	select CLK
-	select TIMER
-	select ARC_TIMER
 
 config ARM
 	bool "ARM architecture"
@@ -27,6 +23,9 @@ config AVR32
 	bool "AVR32 architecture"
 	select CREATE_ARCH_SYMLINK
 
+config BLACKFIN
+	bool "Blackfin architecture"
+
 config M68K
 	bool "M68000 architecture"
 	select HAVE_PRIVATE_LIBGCC
@@ -51,6 +50,9 @@ config NIOS2
 	select DM
 	select CPU
 
+config OPENRISC
+	bool "OpenRISC architecture"
+
 config PPC
 	bool "PowerPC architecture"
 	select HAVE_PRIVATE_LIBGCC
@@ -58,10 +60,8 @@ config PPC
 
 config SANDBOX
 	bool "Sandbox"
-	select BOARD_LATE_INIT
 	select SUPPORT_OF_CONTROL
 	select DM
-	select DM_KEYBOARD
 	select DM_SPI_FLASH
 	select DM_SERIAL
 	select DM_I2C
@@ -73,13 +73,16 @@ config SH
 	bool "SuperH architecture"
 	select HAVE_PRIVATE_LIBGCC
 
+config SPARC
+	bool "SPARC architecture"
+	select CREATE_ARCH_SYMLINK
+
 config X86
 	bool "x86 architecture"
 	select CREATE_ARCH_SYMLINK
 	select HAVE_PRIVATE_LIBGCC
 	select SUPPORT_OF_CONTROL
 	select DM
-	select DM_KEYBOARD
 	select DM_SERIAL
 	select DM_GPIO
 	select DM_SPI
@@ -151,13 +154,16 @@ config SYS_CONFIG_NAME
 source "arch/arc/Kconfig"
 source "arch/arm/Kconfig"
 source "arch/avr32/Kconfig"
+source "arch/blackfin/Kconfig"
 source "arch/m68k/Kconfig"
 source "arch/microblaze/Kconfig"
 source "arch/mips/Kconfig"
 source "arch/nds32/Kconfig"
 source "arch/nios2/Kconfig"
+source "arch/openrisc/Kconfig"
 source "arch/powerpc/Kconfig"
 source "arch/sandbox/Kconfig"
 source "arch/sh/Kconfig"
+source "arch/sparc/Kconfig"
 source "arch/x86/Kconfig"
 source "arch/xtensa/Kconfig"

arch/arc/Kconfig

@@ -118,7 +118,7 @@ config SYS_DCACHE_OFF
 
 choice
 	prompt "Target select"
-	default TARGET_AXS103
+	default TARGET_AXS10X
 
 config TARGET_TB100
 	bool "Support tb100"
@@ -126,11 +126,8 @@ config TARGET_TB100
 config TARGET_NSIM
 	bool "Support standalone nSIM & Free nSIM"
 
-config TARGET_AXS101
-	bool "Support Synopsys Designware SDP board AXS101"
-
-config TARGET_AXS103
-	bool "Support Synopsys Designware SDP board AXS103"
+config TARGET_AXS10X
+	bool "Support Synopsys Designware SDP board (AXS101 & AXS103)"
 
 endchoice
 

arch/arc/config.mk

@@ -31,15 +31,15 @@ CONFIG_MMU = 1
 endif
 
 ifdef CONFIG_CPU_ARC750D
-PLATFORM_CPPFLAGS += -mcpu=arc700
+PLATFORM_CPPFLAGS += -marc700
 endif
 
 ifdef CONFIG_CPU_ARC770D
-PLATFORM_CPPFLAGS += -mcpu=arc700 -mlock -mswape
+PLATFORM_CPPFLAGS += -marc700 -mlock -mswape
 endif
 
 ifdef CONFIG_CPU_ARCEM6
-PLATFORM_CPPFLAGS += -mcpu=arcem
+PLATFORM_CPPFLAGS += -marcem
 endif
 
 ifdef CONFIG_CPU_ARCHS34

arch/arc/dts/Makefile

@@ -2,8 +2,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-dtb-$(CONFIG_TARGET_AXS101) +=  axs101.dtb
-dtb-$(CONFIG_TARGET_AXS103) +=  axs103.dtb
+dtb-$(CONFIG_TARGET_AXS10X) +=  axs10x.dtb
 dtb-$(CONFIG_TARGET_NSIM) +=  nsim.dtb
 dtb-$(CONFIG_TARGET_TB100) +=  abilis_tb100.dtb
 

arch/arc/dts/abilis_tb100.dts

@@ -8,19 +8,13 @@
 #include "skeleton.dtsi"
 
 / {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
 	aliases {
 		console = &uart0;
 	};
 
-	cpu_card {
-		core_clk: core_clk {
-			#clock-cells = <0>;
-			compatible = "fixed-clock";
-			clock-frequency = <500000000>;
-			u-boot,dm-pre-reloc;
-		};
-	};
-
 	uart0: serial@ff100000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0xff100000 0x1000>;

arch/arc/dts/axc001.dtsi

@@ -1,19 +0,0 @@
-/*
- * Copyright (C) 2017 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/include/ "skeleton.dtsi"
-
-/ {
-	cpu_card {
-		core_clk: core_clk {
-			#clock-cells = <0>;
-			compatible = "fixed-clock";
-			clock-frequency = <750000000>;
-			u-boot,dm-pre-reloc;
-		};
-	};
-};
-

arch/arc/dts/axc003.dtsi

@@ -1,19 +0,0 @@
-/*
- * Copyright (C) 2017 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/include/ "skeleton.dtsi"
-
-/ {
-	cpu_card {
-		core_clk: core_clk {
-			#clock-cells = <0>;
-			compatible = "fixed-clock";
-			clock-frequency = <100000000>;
-			u-boot,dm-pre-reloc;
-		};
-	};
-};
-

arch/arc/dts/axs101.dts

@@ -1,17 +0,0 @@
-/*
- * Copyright (C) 2017 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-/dts-v1/;
-
-/include/ "axc001.dtsi"
-/include/ "axs10x_mb.dtsi"
-
-
-/ {
-	chosen {
-		stdout-path = &uart0;
-	};
-};
-

arch/arc/dts/axs103.dts

@@ -1,17 +0,0 @@
-/*
- * Copyright (C) 2017 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-/dts-v1/;
-
-/include/ "axc003.dtsi"
-/include/ "axs10x_mb.dtsi"
-
-
-/ {
-	chosen {
-		stdout-path = &uart0;
-	};
-};
-

arch/arc/dts/axs10x.dts

@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2015 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+/dts-v1/;
+
+#include "skeleton.dtsi"
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	aliases {
+		console = &uart0;
+	};
+
+	clocks {
+		apbclk: apbclk {
+			compatible = "fixed-clock";
+			clock-frequency = <50000000>;
+			#clock-cells = <0>;
+		};
+	};
+
+	uart0: serial0@e0022000 {
+		compatible = "snps,dw-apb-uart";
+		reg = <0xe0022000 0x1000>;
+		reg-shift = <2>;
+		reg-io-width = <4>;
+	};
+
+	ethernet@e0018000 {
+		#interrupt-cells = <1>;
+		compatible = "altr,socfpga-stmmac";
+		reg = < 0xe0018000 0x2000 >;
+		interrupts = < 25 >;
+		interrupt-names = "macirq";
+		phy-mode = "gmii";
+		snps,pbl = < 32 >;
+		clocks = <&apbclk>;
+		clock-names = "stmmaceth";
+		max-speed = <100>;
+	};
+
+	ehci@0xe0040000 {
+		compatible = "generic-ehci";
+		reg = < 0xe0040000 0x100 >;
+		interrupts = < 8 >;
+	};
+
+	ohci@0xe0060000 {
+		compatible = "generic-ohci";
+		reg = < 0xe0060000 0x100 >;
+		interrupts = < 8 >;
+	};
+};

arch/arc/dts/axs10x_mb.dtsi

@@ -1,66 +0,0 @@
-/*
- * Copyright (C) 2017 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/ {
-	axs10x_mb@e0000000 {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0x00000000 0xe0000000 0x10000000>;
-		u-boot,dm-pre-reloc;
-
-		clocks {
-			compatible = "simple-bus";
-			u-boot,dm-pre-reloc;
-
-			apbclk: apbclk {
-				compatible = "fixed-clock";
-				clock-frequency = <50000000>;
-				#clock-cells = <0>;
-			};
-
-			uartclk: uartclk {
-				compatible = "fixed-clock";
-				clock-frequency = <33333333>;
-				#clock-cells = <0>;
-				u-boot,dm-pre-reloc;
-			};
-		};
-
-		ethernet@18000 {
-			#interrupt-cells = <1>;
-			compatible = "altr,socfpga-stmmac";
-			reg = < 0x18000 0x2000 >;
-			interrupts = < 25 >;
-			interrupt-names = "macirq";
-			phy-mode = "gmii";
-			snps,pbl = < 32 >;
-			clocks = <&apbclk>;
-			clock-names = "stmmaceth";
-			max-speed = <100>;
-		};
-
-		ehci@0x40000 {
-			compatible = "generic-ehci";
-			reg = < 0x40000 0x100 >;
-			interrupts = < 8 >;
-		};
-
-		ohci@0x60000 {
-			compatible = "generic-ohci";
-			reg = < 0x60000 0x100 >;
-			interrupts = < 8 >;
-		};
-
-		uart0: serial0@22000 {
-			compatible = "snps,dw-apb-uart";
-			reg = <0x22000 0x100>;
-			clocks = <&uartclk>;
-			reg-shift = <2>;
-			reg-io-width = <4>;
-		};
-	};
-};

arch/arc/dts/nsim.dts

@@ -8,23 +8,17 @@
 #include "skeleton.dtsi"
 
 / {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
 	aliases {
 		console = &arcuart0;
 	};
 
-	cpu_card {
-		core_clk: core_clk {
-			#clock-cells = <0>;
-			compatible = "fixed-clock";
-			clock-frequency = <70000000>;
-			u-boot,dm-pre-reloc;
-		};
-	};
-
 	arcuart0: serial@0xc0fc1000 {
 		compatible = "snps,arc-uart";
 		reg = <0xc0fc1000 0x100>;
-		clock-frequency = <70000000>;
+		clock-frequency = <80000000>;
 	};
 
 };

arch/arc/dts/skeleton.dtsi

@@ -9,22 +9,5 @@
 	#size-cells = <1>;
 	chosen { };
 	aliases { };
-
-	cpu_card {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		u-boot,dm-pre-reloc;
-
-		timer@0 {
-			compatible = "snps,arc-timer";
-			clocks = <&core_clk>;
-			reg = <0 1>;
-		};
-	};
-
-	memory@80000000 {
-		device_type = "memory";
-		reg = <0x80000000 0x10000000>; /* 256M */
-	};
+	memory { device_type = "memory"; reg = <0 0>; };
 };

arch/arc/include/asm/arcregs.h

@@ -33,10 +33,6 @@
 #define ARC_AUX_TIMER0_CTRL	0x22	/* Timer 0 control */
 #define ARC_AUX_TIMER0_LIMIT	0x23	/* Timer 0 limit */
 
-#define ARC_AUX_TIMER1_CNT	0x100	/* Timer 1 count */
-#define ARC_AUX_TIMER1_CTRL	0x101	/* Timer 1 control */
-#define ARC_AUX_TIMER1_LIMIT	0x102	/* Timer 1 limit */
-
 #define ARC_AUX_INTR_VEC_BASE	0x25
 
 /* Data cache related auxiliary registers */

arch/arc/include/asm/config.h

@@ -8,6 +8,7 @@
 #define __ASM_ARC_CONFIG_H_
 
 #define CONFIG_SYS_BOOT_RAMDISK_HIGH
+#define CONFIG_ARCH_EARLY_INIT_R
 
 #define CONFIG_LMB
 

arch/arc/include/asm/errno.h

@@ -0,0 +1 @@
+#include <asm-generic/errno.h>

arch/arc/include/asm/init_helpers.h

@@ -0,0 +1,12 @@
+/*
+ * Copyright (C) 2013-2015 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ASM_ARC_INIT_HELPERS_H
+#define _ASM_ARC_INIT_HELPERS_H
+
+int init_cache_f_r(void);
+
+#endif	/* _ASM_ARC_INIT_HELPERS_H */

arch/arc/include/asm/relocate.h

@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) 2013-2015 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ASM_ARC_RELOCATE_H
+#define _ASM_ARC_RELOCATE_H
+
+#include <common.h>
+
+int copy_uboot_to_ram(void);
+int clear_bss(void);
+int do_elf_reloc_fixups(void);
+
+#endif	/* _ASM_ARC_RELOCATE_H */

arch/arc/lib/Makefile

@@ -18,6 +18,7 @@ obj-y += memcmp.o
 obj-y += memcpy-700.o
 obj-y += memset.o
 obj-y += reset.o
+obj-y += timer.o
 obj-y += ints_low.o
 obj-y += init_helpers.o
 

arch/arc/lib/bootm.c

@@ -37,11 +37,6 @@ void arch_lmb_reserve(struct lmb *lmb)
 	lmb_reserve(lmb, sp, (CONFIG_SYS_SDRAM_BASE + gd->ram_size - sp));
 }
 
-int arch_fixup_fdt(void *blob)
-{
-	return 0;
-}
-
 static int cleanup_before_linux(void)
 {
 	disable_interrupts();

arch/arc/lib/cache.c

@@ -59,16 +59,10 @@ static unsigned int __before_slc_op(const int op)
 
 static void __after_slc_op(const int op, unsigned int reg)
 {
-	if (op & OP_FLUSH) {	/* flush / flush-n-inv both wait */
-		/*
-		 * Make sure "busy" bit reports correct status,
-		 * see STAR 9001165532
-		 */
-		read_aux_reg(ARC_AUX_SLC_CTRL);
+	if (op & OP_FLUSH)	/* flush / flush-n-inv both wait */
 		while (read_aux_reg(ARC_AUX_SLC_CTRL) &
 		       DC_CTRL_FLUSH_STATUS)
 			;
-	}
 
 	/* Switch back to default Invalidate mode */
 	if (op == OP_INV)

arch/arc/lib/cpu.c

@@ -28,9 +28,3 @@ int arch_early_init_r(void)
 	gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
 	return 0;
 }
-
-/* This is a dummy function on arc */
-int dram_init(void)
-{
-	return 0;
-}

arch/arc/lib/start.S

@@ -10,22 +10,6 @@
 #include <asm/arcregs.h>
 
 ENTRY(_start)
-	; Non-masters will be halted immediately, they might be kicked later
-	; by platform code right before passing control to the Linux kernel
-	; in bootm.c:boot_jump_linux().
-	lr 	r5, [identity]
-	lsr	r5, r5, 8
-	bmsk	r5, r5, 7
-	cmp	r5, 0
-	mov.nz	r0, r5
-	bz	.Lmaster_proceed
-	flag	1
-	nop
-	nop
-	nop
-
-.Lmaster_proceed:
-
 	/* Setup interrupt vector base that matches "__text_start" */
 	sr	__ivt_start, [ARC_AUX_INTR_VEC_BASE]
 

arch/arc/lib/timer.c

@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/arcregs.h>
+
+#define NH_MODE	(1 << 1)	/* Disable timer if CPU is halted */
+
+int timer_init(void)
+{
+	write_aux_reg(ARC_AUX_TIMER0_CTRL, NH_MODE);
+	/* Set max value for counter/timer */
+	write_aux_reg(ARC_AUX_TIMER0_LIMIT, 0xffffffff);
+	/* Set initial count value and restart counter/timer */
+	write_aux_reg(ARC_AUX_TIMER0_CNT, 0);
+	return 0;
+}
+
+unsigned long timer_read_counter(void)
+{
+	return read_aux_reg(ARC_AUX_TIMER0_CNT);
+}

arch/arm/Makefile

@@ -50,7 +50,6 @@ PLATFORM_CPPFLAGS += $(arch-y) $(tune-y)
 
 # Machine directory name.  This list is sorted alphanumerically
 # by CONFIG_* macro name.
-machine-$(CONFIG_ARCH_ASPEED)		+= aspeed
 machine-$(CONFIG_ARCH_AT91)		+= at91
 machine-$(CONFIG_ARCH_BCM283X)		+= bcm283x
 machine-$(CONFIG_ARCH_DAVINCI)		+= davinci
@@ -64,7 +63,6 @@ machine-$(CONFIG_ARCH_MVEBU)		+= mvebu
 # TODO: rename CONFIG_TEGRA -> CONFIG_ARCH_TEGRA
 # TODO: rename CONFIG_ORION5X -> CONFIG_ARCH_ORION5X
 machine-$(CONFIG_ORION5X)		+= orion5x
-machine-$(CONFIG_ARCH_OMAP2PLUS)	+= omap2
 machine-$(CONFIG_ARCH_S5PC1XX)		+= s5pc1xx
 machine-$(CONFIG_ARCH_SUNXI)		+= sunxi
 machine-$(CONFIG_ARCH_SNAPDRAGON)	+= snapdragon
@@ -95,11 +93,11 @@ libs-y += arch/arm/cpu/
 libs-y += arch/arm/lib/
 
 ifeq ($(CONFIG_SPL_BUILD),y)
-ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35))
+ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx31 mx35))
 libs-y += arch/arm/imx-common/
 endif
 else
-ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs vf610))
+ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx31 mx35 mxs vf610))
 libs-y += arch/arm/imx-common/
 endif
 endif

arch/arm/config.mk

@@ -6,16 +6,13 @@
 #
 
 ifndef CONFIG_STANDALONE_LOAD_ADDR
-ifneq ($(CONFIG_ARCH_OMAP2PLUS),)
+ifneq ($(CONFIG_OMAP_COMMON),)
 CONFIG_STANDALONE_LOAD_ADDR = 0x80300000
 else
 CONFIG_STANDALONE_LOAD_ADDR = 0xc100000
 endif
 endif
 
-CFLAGS_NON_EFI := -fno-pic -ffixed-r9 -ffunction-sections -fdata-sections
-CFLAGS_EFI := -fpic -fshort-wchar
-
 LDFLAGS_FINAL += --gc-sections
 PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections \
 		     -fno-common -ffixed-r9
@@ -31,7 +28,7 @@ PLATFORM_RELFLAGS	+= $(LLVM_RELFLAGS)
 PLATFORM_CPPFLAGS += -D__ARM__
 
 # Choose between ARM/Thumb instruction sets
-ifeq ($(CONFIG_$(SPL_)SYS_THUMB_BUILD),y)
+ifeq ($(CONFIG_SYS_THUMB_BUILD),y)
 AFLAGS_IMPLICIT_IT	:= $(call as-option,-Wa$(comma)-mimplicit-it=always)
 PF_CPPFLAGS_ARM		:= $(AFLAGS_IMPLICIT_IT) \
 			$(call cc-option, -mthumb -mthumb-interwork,\
@@ -44,8 +41,9 @@ PF_CPPFLAGS_ARM := $(call cc-option,-marm,) \
 endif
 
 # Only test once
-ifeq ($(CONFIG_$(SPL_)SYS_THUMB_BUILD),y)
-archprepare: checkthumb checkgcc6
+ifneq ($(CONFIG_SPL_BUILD),y)
+ifeq ($(CONFIG_SYS_THUMB_BUILD),y)
+archprepare: checkthumb
 
 checkthumb:
 	@if test "$(call cc-name)" = "gcc" -a \
@@ -55,17 +53,8 @@ checkthumb:
 		echo '*** Your board is configured for THUMB mode.'; \
 		false; \
 	fi
-else
-archprepare: checkgcc6
 endif
-
-checkgcc6:
-	@if test "$(call cc-name)" = "gcc" -a \
-			"$(call cc-version)" -lt "0600"; then \
-		echo -n '*** Your GCC is older than 6.0 and will not be '; \
-		echo 'supported starting in v2018.01.'; \
-	fi
-
+endif
 
 # Try if EABI is supported, else fall back to old API,
 # i. e. for example:
@@ -107,7 +96,7 @@ LDFLAGS_u-boot += -pie
 #
 # http://sourceware.org/bugzilla/show_bug.cgi?id=12532
 #
-ifeq ($(CONFIG_$(SPL_)SYS_THUMB_BUILD),y)
+ifeq ($(CONFIG_SYS_THUMB_BUILD),y)
 ifeq ($(GAS_BUG_12532),)
 export GAS_BUG_12532:=$(shell if [ $(call binutils-version) -lt 0222 ] ; \
 	then echo y; else echo n; fi)
@@ -129,8 +118,7 @@ endif
 
 # limit ourselves to the sections we want in the .bin.
 ifdef CONFIG_ARM64
-OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .data \
-		-j .u_boot_list -j .rela.dyn -j .got -j .got.plt
+OBJCOPYFLAGS += -j .text -j .rodata -j .data -j .u_boot_list -j .rela.dyn
 else
 OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .hash \
 		-j .data -j .got -j .got.plt -j .u_boot_list -j .rel.dyn
@@ -156,11 +144,4 @@ else
 ALL-y += u-boot.imx
 endif
 endif
-ifneq ($(CONFIG_VF610),)
-ALL-y += u-boot.vyb
 endif
-endif
-
-EFI_LDS := elf_arm_efi.lds
-EFI_CRT0 := crt0_arm_efi.o
-EFI_RELOC := reloc_arm_efi.o

arch/arm/cpu/arm1136/mx35/generic.c

@@ -10,7 +10,7 @@
 #include <common.h>
 #include <div64.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/clock.h>

arch/arm/cpu/arm1136/mx35/mx35_sdram.c

@@ -5,7 +5,7 @@
  */
 
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/imx-regs.h>
 #include <linux/types.h>
 #include <asm/arch/sys_proto.h>

arch/arm/cpu/arm1176/start.S

@@ -16,7 +16,6 @@
 
 #include <asm-offsets.h>
 #include <config.h>
-#include <linux/linkage.h>
 
 #ifndef CONFIG_SYS_PHY_UBOOT_BASE
 #define CONFIG_SYS_PHY_UBOOT_BASE	CONFIG_SYS_UBOOT_BASE
@@ -38,11 +37,6 @@
 	.globl reset
 
 reset:
-	/* Allow the board to save important registers */
-	b	save_boot_params
-.globl	save_boot_params_ret
-save_boot_params_ret:
-
 	/*
 	 * set the cpu to SVC32 mode
 	 */
@@ -116,7 +110,3 @@ mmu_disable_phys:
 c_runtime_cpu_setup:
 
 	mov	pc, lr
-
-WEAK(save_boot_params)
-	b	save_boot_params_ret	/* back to my caller */
-ENDPROC(save_boot_params)

arch/arm/cpu/arm720t/interrupts.c

@@ -12,6 +12,12 @@
 
 #include <common.h>
 
+#ifdef CONFIG_USE_IRQ
+void do_irq (struct pt_regs *pt_regs)
+{
+}
+#endif
+
 #if defined(CONFIG_TEGRA)
 static ulong timestamp;
 static ulong lastdec;

arch/arm/cpu/arm920t/Makefile

@@ -8,6 +8,7 @@
 extra-y	= start.o
 
 obj-y	+= cpu.o
+obj-$(CONFIG_USE_IRQ)	+= interrupts.o
 
 obj-$(CONFIG_EP93XX) += ep93xx/
 obj-$(CONFIG_IMX) += imx/
@@ -15,6 +16,6 @@ obj-$(CONFIG_S3C24X0) += s3c24x0/
 
 # some files can only build in ARM mode
 
-ifdef CONFIG_$(SPL_)SYS_THUMB_BUILD
+ifdef CONFIG_SYS_THUMB_BUILD
 CFLAGS_cpu.o := -marm
 endif

arch/arm/cpu/arm920t/ep93xx/led.c

@@ -9,16 +9,16 @@
 #include <config.h>
 #include <status_led.h>
 
-static uint8_t saved_state[2] = {CONFIG_LED_STATUS_OFF, CONFIG_LED_STATUS_OFF};
-static uint32_t gpio_pin[2] = {1 << CONFIG_LED_STATUS_GREEN,
-			       1 << CONFIG_LED_STATUS_RED};
+static uint8_t saved_state[2] = {STATUS_LED_OFF, STATUS_LED_OFF};
+static uint32_t gpio_pin[2] = {1 << STATUS_LED_GREEN,
+			       1 << STATUS_LED_RED};
 
 static inline void switch_LED_on(uint8_t led)
 {
 	register struct gpio_regs *gpio = (struct gpio_regs *)GPIO_BASE;
 
 	writel(readl(&gpio->pedr) | gpio_pin[led], &gpio->pedr);
-	saved_state[led] = CONFIG_LED_STATUS_ON;
+	saved_state[led] = STATUS_LED_ON;
 }
 
 static inline void switch_LED_off(uint8_t led)
@@ -26,27 +26,27 @@ static inline void switch_LED_off(uint8_t led)
 	register struct gpio_regs *gpio = (struct gpio_regs *)GPIO_BASE;
 
 	writel(readl(&gpio->pedr) & ~gpio_pin[led], &gpio->pedr);
-	saved_state[led] = CONFIG_LED_STATUS_OFF;
+	saved_state[led] = STATUS_LED_OFF;
 }
 
 void red_led_on(void)
 {
-	switch_LED_on(CONFIG_LED_STATUS_RED);
+	switch_LED_on(STATUS_LED_RED);
 }
 
 void red_led_off(void)
 {
-	switch_LED_off(CONFIG_LED_STATUS_RED);
+	switch_LED_off(STATUS_LED_RED);
 }
 
 void green_led_on(void)
 {
-	switch_LED_on(CONFIG_LED_STATUS_GREEN);
+	switch_LED_on(STATUS_LED_GREEN);
 }
 
 void green_led_off(void)
 {
-	switch_LED_off(CONFIG_LED_STATUS_GREEN);
+	switch_LED_off(STATUS_LED_GREEN);
 }
 
 void __led_init(led_id_t mask, int state)
@@ -56,14 +56,13 @@ void __led_init(led_id_t mask, int state)
 
 void __led_toggle(led_id_t mask)
 {
-	if (CONFIG_LED_STATUS_RED == mask) {
-		if (CONFIG_LED_STATUS_ON == saved_state[CONFIG_LED_STATUS_RED])
+	if (STATUS_LED_RED == mask) {
+		if (STATUS_LED_ON == saved_state[STATUS_LED_RED])
 			red_led_off();
 		else
 			red_led_on();
-	} else if (CONFIG_LED_STATUS_GREEN == mask) {
-		if (CONFIG_LED_STATUS_ON ==
-		    saved_state[CONFIG_LED_STATUS_GREEN])
+	} else if (STATUS_LED_GREEN == mask) {
+		if (STATUS_LED_ON == saved_state[STATUS_LED_GREEN])
 			green_led_off();
 		else
 			green_led_on();
@@ -72,13 +71,13 @@ void __led_toggle(led_id_t mask)
 
 void __led_set(led_id_t mask, int state)
 {
-	if (CONFIG_LED_STATUS_RED == mask) {
-		if (CONFIG_LED_STATUS_ON == state)
+	if (STATUS_LED_RED == mask) {
+		if (STATUS_LED_ON == state)
 			red_led_on();
 		else
 			red_led_off();
-	} else if (CONFIG_LED_STATUS_GREEN == mask) {
-		if (CONFIG_LED_STATUS_ON == state)
+	} else if (STATUS_LED_GREEN == mask) {
+		if (STATUS_LED_ON == state)
 			green_led_on();
 		else
 			green_led_off();

arch/arm/cpu/arm920t/imx/timer.c

@@ -78,7 +78,11 @@ unsigned long long get_ticks(void)
  */
 ulong get_tbclk (void)
 {
-	return CONFIG_SYS_HZ;
+	ulong tbclk;
+
+	tbclk = CONFIG_SYS_HZ;
+
+	return tbclk;
 }
 
 /*

arch/arm/cpu/arm920t/interrupts.c

@@ -0,0 +1,27 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/proc-armv/ptrace.h>
+
+#if defined (CONFIG_ARCH_INTEGRATOR)
+void do_irq (struct pt_regs *pt_regs)
+{
+	/* ASSUMED to be a timer interrupt  */
+	/* Just clear it - count handled in */
+	/* integratorap.c                   */
+	*(volatile ulong *)(CONFIG_SYS_TIMERBASE + 0x0C) = 0;
+}
+#endif

arch/arm/cpu/arm920t/s3c24x0/Makefile

@@ -5,6 +5,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
+obj-$(CONFIG_USE_IRQ) += interrupts.o
 obj-$(CONFIG_DISPLAY_CPUINFO)	+= cpu_info.o
 obj-y	+= speed.o
 obj-y	+= timer.o

arch/arm/cpu/arm920t/s3c24x0/interrupts.c

@@ -0,0 +1,26 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+
+#include <asm/arch/s3c24x0_cpu.h>
+#include <asm/proc-armv/ptrace.h>
+
+void do_irq (struct pt_regs *pt_regs)
+{
+	struct s3c24x0_interrupt *irq = s3c24x0_get_base_interrupt();
+	u_int32_t intpnd = readl(&irq->INTPND);
+
+}

arch/arm/cpu/arm926ejs/Makefile

@@ -23,7 +23,7 @@ obj-$(if $(filter spear,$(SOC)),y) += spear/
 
 # some files can only build in ARM or THUMB2, not THUMB1
 
-ifdef CONFIG_$(SPL_)SYS_THUMB_BUILD
+ifdef CONFIG_SYS_THUMB_BUILD
 ifndef CONFIG_HAS_THUMB2
 
 CFLAGS_cpu.o := -marm

arch/arm/cpu/arm926ejs/armada100/dram.c

@@ -108,9 +108,7 @@ int dram_init(void)
  * If this function is not defined here,
  * board.c alters dram bank zero configuration defined above.
  */
-int dram_init_banksize(void)
+void dram_init_banksize(void)
 {
 	dram_init();
-
-	return 0;
 }

arch/arm/cpu/arm926ejs/cache.c

@@ -63,6 +63,6 @@ void flush_dcache_all(void)
 
 __weak void l2_cache_disable(void) {}
 
-#if CONFIG_IS_ENABLED(SYS_THUMB_BUILD)
+#if defined CONFIG_SYS_THUMB_BUILD
 __weak void invalidate_l2_cache(void) {}
 #endif

arch/arm/cpu/arm926ejs/lpc32xx/devices.c

@@ -45,14 +45,10 @@ void lpc32xx_uart_init(unsigned int uart_id)
 
 #if !CONFIG_IS_ENABLED(OF_CONTROL)
 static const struct ns16550_platdata lpc32xx_uart[] = {
-	{ .base = UART3_BASE, .reg_shift = 2,
-	  .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
-	{ .base = UART4_BASE, .reg_shift = 2,
-	  .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
-	{ .base = UART5_BASE, .reg_shift = 2,
-	  .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
-	{ .base = UART6_BASE, .reg_shift = 2,
-	  .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
+	{ .base = UART3_BASE, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
+	{ .base = UART4_BASE, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
+	{ .base = UART5_BASE, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
+	{ .base = UART6_BASE, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
 };
 
 #if defined(CONFIG_LPC32XX_HSUART)

arch/arm/cpu/arm926ejs/mx27/generic.c

@@ -13,7 +13,7 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/gpio.h>
 #include <asm/imx-common/sys_proto.h>
-#ifdef CONFIG_MMC_MXC
+#ifdef CONFIG_MXC_MMC
 #include <asm/arch/mxcmmc.h>
 #endif
 
@@ -196,7 +196,7 @@ int cpu_eth_init(bd_t *bis)
  */
 int cpu_mmc_init(bd_t *bis)
 {
-#ifdef CONFIG_MMC_MXC
+#ifdef CONFIG_MXC_MMC
 	return mxc_mmc_init(bis);
 #else
 	return 0;
@@ -340,7 +340,7 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 }
 #endif /* CONFIG_FEC_MXC */
 
-#ifdef CONFIG_MMC_MXC
+#ifdef CONFIG_MXC_MMC
 void mx27_sd1_init_pins(void)
 {
 	int i;
@@ -374,7 +374,7 @@ void mx27_sd2_init_pins(void)
 		imx_gpio_mode(mode[i]);
 
 }
-#endif /* CONFIG_MMC_MXC */
+#endif /* CONFIG_MXC_MMC */
 
 #ifndef CONFIG_SYS_DCACHE_OFF
 void enable_caches(void)

arch/arm/cpu/arm926ejs/mxs/clock.c

@@ -11,7 +11,7 @@
  */
 
 #include <common.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/imx-regs.h>

arch/arm/cpu/arm926ejs/mxs/iomux.c

@@ -8,7 +8,7 @@
  */
 
 #include <common.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/iomux.h>

arch/arm/cpu/arm926ejs/mxs/mxs.c

@@ -11,7 +11,7 @@
  */
 
 #include <common.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/imx-common/dma.h>

arch/arm/cpu/arm926ejs/mxs/spl_boot.c

@@ -40,17 +40,17 @@ void early_delay(int delay)
 		;
 }
 
-#if defined(CONFIG_MX23)
 #define	MUX_CONFIG_BOOTMODE_PAD	(MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
 static const iomux_cfg_t iomux_boot[] = {
+#if defined(CONFIG_MX23)
 	MX23_PAD_LCD_D00__GPIO_1_0 | MUX_CONFIG_BOOTMODE_PAD,
 	MX23_PAD_LCD_D01__GPIO_1_1 | MUX_CONFIG_BOOTMODE_PAD,
 	MX23_PAD_LCD_D02__GPIO_1_2 | MUX_CONFIG_BOOTMODE_PAD,
 	MX23_PAD_LCD_D03__GPIO_1_3 | MUX_CONFIG_BOOTMODE_PAD,
 	MX23_PAD_LCD_D04__GPIO_1_4 | MUX_CONFIG_BOOTMODE_PAD,
 	MX23_PAD_LCD_D05__GPIO_1_5 | MUX_CONFIG_BOOTMODE_PAD,
-};
 #endif
+};
 
 static uint8_t mxs_get_bootmode_index(void)
 {

arch/arm/cpu/arm926ejs/spear/timer.c

@@ -37,7 +37,7 @@ int timer_init(void)
 	writel(MISC_PRSC_CFG, &misc_regs_p->prsc1_clk_cfg);
 	synth = MISC_GPT3SYNTH;
 #else
-# error Incorrect config. Can only be SPEAR{600|300|310|320}
+# error Incorrect config. Can only be spear{600|300|310|320}
 #endif
 
 	writel(readl(&misc_regs_p->periph_clk_cfg) | synth,

arch/arm/cpu/armv7/Makefile

@@ -12,24 +12,25 @@ obj-y	+= cache_v7.o cache_v7_asm.o
 obj-y	+= cpu.o cp15.o
 obj-y	+= syslib.o
 
-ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_MX7)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_ARCH_SUNXI)$(CONFIG_ARCH_SOCFPGA)$(CONFIG_ARCH_MX7ULP)$(CONFIG_ARCH_LS1021A),)
+ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_MX7)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_SUNXI)$(CONFIG_ARCH_SOCFPGA),)
 ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y)
 obj-y	+= lowlevel_init.o
 endif
 endif
 
-obj-$(CONFIG_ARM_SMCCC)		+= smccc-call.o
 obj-$(CONFIG_ARMV7_NONSEC)	+= nonsec_virt.o virt-v7.o virt-dt.o
 obj-$(CONFIG_ARMV7_PSCI)	+= psci.o psci-common.o
 
 obj-$(CONFIG_IPROC) += iproc-common/
 obj-$(CONFIG_KONA) += kona-common/
+obj-$(CONFIG_OMAP_COMMON) += omap-common/
 obj-$(CONFIG_SYS_ARCH_TIMER) += arch_timer.o
 
 ifneq (,$(filter s5pc1xx exynos,$(SOC)))
 obj-y += s5p-common/
 endif
 
+obj-$(if $(filter am33xx,$(SOC)),y) += am33xx/
 obj-$(if $(filter bcm235xx,$(SOC)),y) += bcm235xx/
 obj-$(if $(filter bcm281xx,$(SOC)),y) += bcm281xx/
 obj-$(if $(filter bcmcygnus,$(SOC)),y) += bcmcygnus/
@@ -38,7 +39,9 @@ obj-$(if $(filter ls102xa,$(SOC)),y) += ls102xa/
 obj-$(if $(filter mx5,$(SOC)),y) += mx5/
 obj-$(CONFIG_MX6) += mx6/
 obj-$(CONFIG_MX7) += mx7/
-obj-$(CONFIG_ARCH_MX7ULP) += mx7ulp/
+obj-$(CONFIG_OMAP34XX) += omap3/
+obj-$(CONFIG_OMAP44XX) += omap4/
+obj-$(CONFIG_OMAP54XX) += omap5/
 obj-$(CONFIG_RMOBILE) += rmobile/
 obj-$(if $(filter stv0991,$(SOC)),y) += stv0991/
 obj-$(CONFIG_ARCH_SUNXI) += sunxi/

arch/arm/cpu/armv7/am33xx/Kconfig

@@ -0,0 +1,40 @@
+if AM43XX
+config TARGET_AM43XX_EVM
+	bool "Support am43xx_evm"
+	select TI_I2C_BOARD_DETECT
+	help
+	  This option specifies support for the AM43xx
+	  GP and HS EVM development platforms.The AM437x
+	  GP EVM is a standalone test, development, and
+	  evaluation module system that enables developers
+	  to write software and develop hardware around
+	  an AM43xx processor subsystem.
+
+config ISW_ENTRY_ADDR
+	hex "Address in memory or XIP flash of bootloader entry point"
+	help
+	  After any reset, the boot ROM on the AM43XX SOC
+	  searches the boot media for a valid boot image.
+	  For non-XIP devices, the ROM then copies the
+	  image into internal memory.
+	  For all boot modes, after the ROM processes the
+	  boot image it eventually computes the entry
+	  point address depending on the device type
+	  (secure/non-secure), boot media (xip/non-xip) and
+	  image headers.
+	default 0x402F4000
+
+config PUB_ROM_DATA_SIZE
+	hex "Size in bytes of the L3 SRAM reserved by ROM to store data"
+	help
+	  During the device boot, the public ROM uses the top of
+	  the public L3 OCMC RAM to store r/w data like stack,
+	  heap, globals etc. When the ROM is copying the boot
+	  image from the boot media into memory, the image must
+	  not spill over into this area. This value can be used
+	  during compile time to determine the maximum size of a
+	  boot image. Once the ROM transfers control to the boot
+	  image, this area is no longer used, and can be reclaimed
+	  for run time use by the boot image.
+	default 0x8400
+endif

arch/arm/cpu/armv7/am33xx/Makefile

@@ -0,0 +1,22 @@
+#
+# Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-$(CONFIG_AM33XX)	+= clock_am33xx.o
+obj-$(CONFIG_TI814X)	+= clock_ti814x.o
+obj-$(CONFIG_AM43XX)	+= clock_am43xx.o
+
+ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX),)
+obj-y	+= clock.o
+endif
+
+obj-$(CONFIG_TI816X)	+= clock_ti816x.o
+obj-y	+= sys_info.o
+obj-y	+= ddr.o
+obj-y	+= emif4.o
+obj-y	+= board.o
+obj-y	+= mux.o
+
+obj-$(CONFIG_CLOCK_SYNTHESIZER)	+= clk_synthesizer.o

arch/arm/cpu/armv7/am33xx/board.c

@@ -0,0 +1,300 @@
+/*
+ * board.c
+ *
+ * Common board functions for AM33XX based boards
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <ns16550.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <cpsw.h>
+#include <asm/errno.h>
+#include <linux/compiler.h>
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+#include <linux/usb/musb.h>
+#include <asm/omap_musb.h>
+#include <asm/davinci_rtc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if !CONFIG_IS_ENABLED(OF_CONTROL)
+static const struct ns16550_platdata am33xx_serial[] = {
+	{ .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
+# ifdef CONFIG_SYS_NS16550_COM2
+	{ .base = CONFIG_SYS_NS16550_COM2, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
+#  ifdef CONFIG_SYS_NS16550_COM3
+	{ .base = CONFIG_SYS_NS16550_COM3, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
+	{ .base = CONFIG_SYS_NS16550_COM4, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
+	{ .base = CONFIG_SYS_NS16550_COM5, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
+	{ .base = CONFIG_SYS_NS16550_COM6, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
+#  endif
+# endif
+};
+
+U_BOOT_DEVICES(am33xx_uarts) = {
+	{ "ns16550_serial", &am33xx_serial[0] },
+#  ifdef CONFIG_SYS_NS16550_COM2
+	{ "ns16550_serial", &am33xx_serial[1] },
+#   ifdef CONFIG_SYS_NS16550_COM3
+	{ "ns16550_serial", &am33xx_serial[2] },
+	{ "ns16550_serial", &am33xx_serial[3] },
+	{ "ns16550_serial", &am33xx_serial[4] },
+	{ "ns16550_serial", &am33xx_serial[5] },
+#   endif
+#  endif
+};
+
+#ifdef CONFIG_DM_GPIO
+static const struct omap_gpio_platdata am33xx_gpio[] = {
+	{ 0, AM33XX_GPIO0_BASE },
+	{ 1, AM33XX_GPIO1_BASE },
+	{ 2, AM33XX_GPIO2_BASE },
+	{ 3, AM33XX_GPIO3_BASE },
+#ifdef CONFIG_AM43XX
+	{ 4, AM33XX_GPIO4_BASE },
+	{ 5, AM33XX_GPIO5_BASE },
+#endif
+};
+
+U_BOOT_DEVICES(am33xx_gpios) = {
+	{ "gpio_omap", &am33xx_gpio[0] },
+	{ "gpio_omap", &am33xx_gpio[1] },
+	{ "gpio_omap", &am33xx_gpio[2] },
+	{ "gpio_omap", &am33xx_gpio[3] },
+#ifdef CONFIG_AM43XX
+	{ "gpio_omap", &am33xx_gpio[4] },
+	{ "gpio_omap", &am33xx_gpio[5] },
+#endif
+};
+#endif
+#endif
+
+#ifndef CONFIG_DM_GPIO
+static const struct gpio_bank gpio_bank_am33xx[] = {
+	{ (void *)AM33XX_GPIO0_BASE },
+	{ (void *)AM33XX_GPIO1_BASE },
+	{ (void *)AM33XX_GPIO2_BASE },
+	{ (void *)AM33XX_GPIO3_BASE },
+#ifdef CONFIG_AM43XX
+	{ (void *)AM33XX_GPIO4_BASE },
+	{ (void *)AM33XX_GPIO5_BASE },
+#endif
+};
+
+const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
+#endif
+
+#if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
+int cpu_mmc_init(bd_t *bis)
+{
+	int ret;
+
+	ret = omap_mmc_init(0, 0, 0, -1, -1);
+	if (ret)
+		return ret;
+
+	return omap_mmc_init(1, 0, 0, -1, -1);
+}
+#endif
+
+/* AM33XX has two MUSB controllers which can be host or gadget */
+#if (defined(CONFIG_USB_MUSB_GADGET) || defined(CONFIG_USB_MUSB_HOST)) && \
+	(defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1))
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+/* USB 2.0 PHY Control */
+#define CM_PHY_PWRDN			(1 << 0)
+#define CM_PHY_OTG_PWRDN		(1 << 1)
+#define OTGVDET_EN			(1 << 19)
+#define OTGSESSENDEN			(1 << 20)
+
+static void am33xx_usb_set_phy_power(u8 on, u32 *reg_addr)
+{
+	if (on) {
+		clrsetbits_le32(reg_addr, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN,
+				OTGVDET_EN | OTGSESSENDEN);
+	} else {
+		clrsetbits_le32(reg_addr, 0, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN);
+	}
+}
+
+static struct musb_hdrc_config musb_config = {
+	.multipoint     = 1,
+	.dyn_fifo       = 1,
+	.num_eps        = 16,
+	.ram_bits       = 12,
+};
+
+#ifdef CONFIG_AM335X_USB0
+static void am33xx_otg0_set_phy_power(u8 on)
+{
+	am33xx_usb_set_phy_power(on, &cdev->usb_ctrl0);
+}
+
+struct omap_musb_board_data otg0_board_data = {
+	.set_phy_power = am33xx_otg0_set_phy_power,
+};
+
+static struct musb_hdrc_platform_data otg0_plat = {
+	.mode           = CONFIG_AM335X_USB0_MODE,
+	.config         = &musb_config,
+	.power          = 50,
+	.platform_ops	= &musb_dsps_ops,
+	.board_data	= &otg0_board_data,
+};
+#endif
+
+#ifdef CONFIG_AM335X_USB1
+static void am33xx_otg1_set_phy_power(u8 on)
+{
+	am33xx_usb_set_phy_power(on, &cdev->usb_ctrl1);
+}
+
+struct omap_musb_board_data otg1_board_data = {
+	.set_phy_power = am33xx_otg1_set_phy_power,
+};
+
+static struct musb_hdrc_platform_data otg1_plat = {
+	.mode           = CONFIG_AM335X_USB1_MODE,
+	.config         = &musb_config,
+	.power          = 50,
+	.platform_ops	= &musb_dsps_ops,
+	.board_data	= &otg1_board_data,
+};
+#endif
+#endif
+
+int arch_misc_init(void)
+{
+#ifdef CONFIG_AM335X_USB0
+	musb_register(&otg0_plat, &otg0_board_data,
+		(void *)USB0_OTG_BASE);
+#endif
+#ifdef CONFIG_AM335X_USB1
+	musb_register(&otg1_plat, &otg1_board_data,
+		(void *)USB1_OTG_BASE);
+#endif
+	return 0;
+}
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+/*
+ * In the case of non-SPL based booting we'll want to call these
+ * functions a tiny bit later as it will require gd to be set and cleared
+ * and that's not true in s_init in this case so we cannot do it there.
+ */
+int board_early_init_f(void)
+{
+	prcm_init();
+	set_mux_conf_regs();
+
+	return 0;
+}
+
+/*
+ * This function is the place to do per-board things such as ramp up the
+ * MPU clock frequency.
+ */
+__weak void am33xx_spl_board_init(void)
+{
+	do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
+	do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
+}
+
+#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
+static void rtc32k_enable(void)
+{
+	struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
+
+	/*
+	 * Unlock the RTC's registers.  For more details please see the
+	 * RTC_SS section of the TRM.  In order to unlock we need to
+	 * write these specific values (keys) in this order.
+	 */
+	writel(RTC_KICK0R_WE, &rtc->kick0r);
+	writel(RTC_KICK1R_WE, &rtc->kick1r);
+
+	/* Enable the RTC 32K OSC by setting bits 3 and 6. */
+	writel((1 << 3) | (1 << 6), &rtc->osc);
+}
+#endif
+
+static void uart_soft_reset(void)
+{
+	struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
+	u32 regval;
+
+	regval = readl(&uart_base->uartsyscfg);
+	regval |= UART_RESET;
+	writel(regval, &uart_base->uartsyscfg);
+	while ((readl(&uart_base->uartsyssts) &
+		UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
+		;
+
+	/* Disable smart idle */
+	regval = readl(&uart_base->uartsyscfg);
+	regval |= UART_SMART_IDLE_EN;
+	writel(regval, &uart_base->uartsyscfg);
+}
+
+static void watchdog_disable(void)
+{
+	struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
+
+	writel(0xAAAA, &wdtimer->wdtwspr);
+	while (readl(&wdtimer->wdtwwps) != 0x0)
+		;
+	writel(0x5555, &wdtimer->wdtwspr);
+	while (readl(&wdtimer->wdtwwps) != 0x0)
+		;
+}
+
+#ifdef CONFIG_SPL_BUILD
+void board_init_f(ulong dummy)
+{
+	board_early_init_f();
+	sdram_init();
+}
+#endif
+
+void s_init(void)
+{
+	/*
+	 * The ROM will only have set up sufficient pinmux to allow for the
+	 * first 4KiB NOR to be read, we must finish doing what we know of
+	 * the NOR mux in this space in order to continue.
+	 */
+#ifdef CONFIG_NOR_BOOT
+	enable_norboot_pin_mux();
+#endif
+	watchdog_disable();
+	set_uart_mux_conf();
+	setup_clocks_for_console();
+	uart_soft_reset();
+#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
+	/* Enable RTC32K clock */
+	rtc32k_enable();
+#endif
+}
+#endif

arch/arm/cpu/armv7/am33xx/clock.c

@@ -0,0 +1,241 @@
+/*
+ * clock.c
+ *
+ * Clock initialization for AM33XX boards.
+ * Derived from OMAP4 boards
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+
+static void setup_post_dividers(const struct dpll_regs *dpll_regs,
+			 const struct dpll_params *params)
+{
+	/* Setup post-dividers */
+	if (params->m2 >= 0)
+		writel(params->m2, dpll_regs->cm_div_m2_dpll);
+	if (params->m3 >= 0)
+		writel(params->m3, dpll_regs->cm_div_m3_dpll);
+	if (params->m4 >= 0)
+		writel(params->m4, dpll_regs->cm_div_m4_dpll);
+	if (params->m5 >= 0)
+		writel(params->m5, dpll_regs->cm_div_m5_dpll);
+	if (params->m6 >= 0)
+		writel(params->m6, dpll_regs->cm_div_m6_dpll);
+}
+
+static inline void do_lock_dpll(const struct dpll_regs *dpll_regs)
+{
+	clrsetbits_le32(dpll_regs->cm_clkmode_dpll,
+			CM_CLKMODE_DPLL_DPLL_EN_MASK,
+			DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT);
+}
+
+static inline void wait_for_lock(const struct dpll_regs *dpll_regs)
+{
+	if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK,
+			   (void *)dpll_regs->cm_idlest_dpll, LDELAY)) {
+		printf("DPLL locking failed for 0x%x\n",
+		       dpll_regs->cm_clkmode_dpll);
+		hang();
+	}
+}
+
+static inline void do_bypass_dpll(const struct dpll_regs *dpll_regs)
+{
+	clrsetbits_le32(dpll_regs->cm_clkmode_dpll,
+			CM_CLKMODE_DPLL_DPLL_EN_MASK,
+			DPLL_EN_MN_BYPASS << CM_CLKMODE_DPLL_EN_SHIFT);
+}
+
+static inline void wait_for_bypass(const struct dpll_regs *dpll_regs)
+{
+	if (!wait_on_value(ST_DPLL_CLK_MASK, 0,
+			   (void *)dpll_regs->cm_idlest_dpll, LDELAY)) {
+		printf("Bypassing DPLL failed 0x%x\n",
+		       dpll_regs->cm_clkmode_dpll);
+	}
+}
+
+static void bypass_dpll(const struct dpll_regs *dpll_regs)
+{
+	do_bypass_dpll(dpll_regs);
+	wait_for_bypass(dpll_regs);
+}
+
+void do_setup_dpll(const struct dpll_regs *dpll_regs,
+		   const struct dpll_params *params)
+{
+	u32 temp;
+
+	if (!params)
+		return;
+
+	temp = readl(dpll_regs->cm_clksel_dpll);
+
+	bypass_dpll(dpll_regs);
+
+	/* Set M & N */
+	temp &= ~CM_CLKSEL_DPLL_M_MASK;
+	temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK;
+
+	temp &= ~CM_CLKSEL_DPLL_N_MASK;
+	temp |= (params->n << CM_CLKSEL_DPLL_N_SHIFT) & CM_CLKSEL_DPLL_N_MASK;
+
+	writel(temp, dpll_regs->cm_clksel_dpll);
+
+	setup_post_dividers(dpll_regs, params);
+
+	/* Wait till the DPLL locks */
+	do_lock_dpll(dpll_regs);
+	wait_for_lock(dpll_regs);
+}
+
+static void setup_dplls(void)
+{
+	const struct dpll_params *params;
+
+	params = get_dpll_core_params();
+	do_setup_dpll(&dpll_core_regs, params);
+
+	params = get_dpll_mpu_params();
+	do_setup_dpll(&dpll_mpu_regs, params);
+
+	params = get_dpll_per_params();
+	do_setup_dpll(&dpll_per_regs, params);
+	writel(0x300, &cmwkup->clkdcoldodpllper);
+
+	params = get_dpll_ddr_params();
+	do_setup_dpll(&dpll_ddr_regs, params);
+}
+
+static inline void wait_for_clk_enable(u32 *clkctrl_addr)
+{
+	u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
+	u32 bound = LDELAY;
+
+	while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
+		(idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
+		clkctrl = readl(clkctrl_addr);
+		idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
+			 MODULE_CLKCTRL_IDLEST_SHIFT;
+		if (--bound == 0) {
+			printf("Clock enable failed for 0x%p idlest 0x%x\n",
+			       clkctrl_addr, clkctrl);
+			return;
+		}
+	}
+}
+
+static inline void enable_clock_module(u32 *const clkctrl_addr, u32 enable_mode,
+				       u32 wait_for_enable)
+{
+	clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
+			enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT);
+	debug("Enable clock module - %p\n", clkctrl_addr);
+	if (wait_for_enable)
+		wait_for_clk_enable(clkctrl_addr);
+}
+
+static inline void wait_for_clk_disable(u32 *clkctrl_addr)
+{
+	u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL;
+	u32 bound = LDELAY;
+
+	while ((idlest != MODULE_CLKCTRL_IDLEST_DISABLED)) {
+		clkctrl = readl(clkctrl_addr);
+		idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
+			  MODULE_CLKCTRL_IDLEST_SHIFT;
+		if (--bound == 0) {
+			printf("Clock disable failed for 0x%p idlest 0x%x\n",
+			       clkctrl_addr, clkctrl);
+			 return;
+		}
+	}
+}
+static inline void disable_clock_module(u32 *const clkctrl_addr,
+					u32 wait_for_disable)
+{
+	clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
+			MODULE_CLKCTRL_MODULEMODE_SW_DISABLE <<
+			MODULE_CLKCTRL_MODULEMODE_SHIFT);
+	debug("Disable clock module - %p\n", clkctrl_addr);
+	if (wait_for_disable)
+		wait_for_clk_disable(clkctrl_addr);
+}
+
+static inline void enable_clock_domain(u32 *const clkctrl_reg, u32 enable_mode)
+{
+	clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
+			enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT);
+	debug("Enable clock domain - %p\n", clkctrl_reg);
+}
+
+static inline void disable_clock_domain(u32 *const clkctrl_reg)
+{
+	clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
+			CD_CLKCTRL_CLKTRCTRL_SW_SLEEP <<
+			CD_CLKCTRL_CLKTRCTRL_SHIFT);
+	debug("Disable clock domain - %p\n", clkctrl_reg);
+}
+
+void do_enable_clocks(u32 *const *clk_domains,
+		      u32 *const *clk_modules_explicit_en, u8 wait_for_enable)
+{
+	u32 i, max = 100;
+
+	/* Put the clock domains in SW_WKUP mode */
+	for (i = 0; (i < max) && clk_domains[i]; i++) {
+		enable_clock_domain(clk_domains[i],
+				    CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
+	}
+
+	/* Clock modules that need to be put in SW_EXPLICIT_EN mode */
+	for (i = 0; (i < max) && clk_modules_explicit_en[i]; i++) {
+		enable_clock_module(clk_modules_explicit_en[i],
+				    MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
+				    wait_for_enable);
+	};
+}
+
+void do_disable_clocks(u32 *const *clk_domains,
+			u32 *const *clk_modules_disable,
+			u8 wait_for_disable)
+{
+	u32 i, max = 100;
+
+
+	/* Clock modules that need to be put in SW_DISABLE */
+	for (i = 0; (i < max) && clk_modules_disable[i]; i++)
+		disable_clock_module(clk_modules_disable[i],
+				     wait_for_disable);
+
+	/* Put the clock domains in SW_SLEEP mode */
+	for (i = 0; (i < max) && clk_domains[i]; i++)
+		disable_clock_domain(clk_domains[i]);
+}
+
+/*
+ * Before scaling up the clocks we need to have the PMIC scale up the
+ * voltages first.  This will be dependent on which PMIC is in use
+ * and in some cases we may not be scaling things up at all and thus not
+ * need to do anything here.
+ */
+__weak void scale_vcores(void)
+{
+}
+
+void prcm_init()
+{
+	enable_basic_clocks();
+	scale_vcores();
+	setup_dplls();
+	timer_init();
+}

arch/arm/cpu/armv7/am33xx/clock_ti814x.c

@@ -386,12 +386,6 @@ void setup_clocks_for_console(void)
 	while (readl(&cmalwon->uart0clkctrl) != PRCM_MOD_EN)
 		;
 }
-
-void setup_early_clocks(void)
-{
-	setup_clocks_for_console();
-}
-
 /*
  * Configure the PLL/PRCM for necessary peripherals
  */

arch/arm/cpu/armv7/am33xx/clock_ti816x.c

@@ -429,11 +429,6 @@ void setup_clocks_for_console(void)
 		;
 }
 
-void setup_early_clocks(void)
-{
-	setup_clocks_for_console();
-}
-
 void prcm_init(void)
 {
 	/* Enable the control */

arch/arm/cpu/armv7/am33xx/config.mk

@@ -0,0 +1,32 @@
+#
+# Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+include  $(srctree)/$(CPUDIR)/omap-common/config_secure.mk
+
+ifdef CONFIG_SPL_BUILD
+ifeq ($(CONFIG_TI_SECURE_DEVICE),y)
+#
+# For booting from SPI use
+# u-boot-spl_HS_SPI_X-LOADER to program flash
+#
+# For booting spl from all other  media
+# use u-boot-spl_HS_ISSW
+#
+# Refer to README.ti-secure for more info
+#
+ALL-y	+= u-boot-spl_HS_ISSW
+ALL-$(CONFIG_SPL_SPI_SUPPORT) += u-boot-spl_HS_SPI_X-LOADER
+else
+ALL-y	+= MLO
+ALL-$(CONFIG_SPL_SPI_SUPPORT) += MLO.byteswap
+endif
+else
+ifeq ($(CONFIG_TI_SECURE_DEVICE),y)
+ALL-$(CONFIG_QSPI_BOOT) += u-boot_HS_XIP_X-LOADER
+ALL-$(CONFIG_SPL_LOAD_FIT) += u-boot_HS.img
+endif
+ALL-y	+= u-boot.img
+endif

arch/arm/cpu/armv7/am33xx/ddr.c

@@ -0,0 +1,377 @@
+/*
+ * DDR Configuration for AM33xx devices.
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/arch/cpu.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+
+/**
+ * Base address for EMIF instances
+ */
+static struct emif_reg_struct *emif_reg[2] = {
+				(struct emif_reg_struct *)EMIF4_0_CFG_BASE,
+				(struct emif_reg_struct *)EMIF4_1_CFG_BASE};
+
+/**
+ * Base addresses for DDR PHY cmd/data regs
+ */
+static struct ddr_cmd_regs *ddr_cmd_reg[2] = {
+				(struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR,
+				(struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR2};
+
+static struct ddr_data_regs *ddr_data_reg[2] = {
+				(struct ddr_data_regs *)DDR_PHY_DATA_ADDR,
+				(struct ddr_data_regs *)DDR_PHY_DATA_ADDR2};
+
+/**
+ * Base address for ddr io control instances
+ */
+static struct ddr_cmdtctrl *ioctrl_reg = {
+			(struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR};
+
+static inline u32 get_mr(int nr, u32 cs, u32 mr_addr)
+{
+	u32 mr;
+
+	mr_addr |= cs << EMIF_REG_CS_SHIFT;
+	writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg);
+
+	mr = readl(&emif_reg[nr]->emif_lpddr2_mode_reg_data);
+	debug("get_mr: EMIF1 cs %d mr %08x val 0x%x\n", cs, mr_addr, mr);
+	if (((mr & 0x0000ff00) >>  8) == (mr & 0xff) &&
+	    ((mr & 0x00ff0000) >> 16) == (mr & 0xff) &&
+	    ((mr & 0xff000000) >> 24) == (mr & 0xff))
+		return mr & 0xff;
+	else
+		return mr;
+}
+
+static inline void set_mr(int nr, u32 cs, u32 mr_addr, u32 mr_val)
+{
+	mr_addr |= cs << EMIF_REG_CS_SHIFT;
+	writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg);
+	writel(mr_val, &emif_reg[nr]->emif_lpddr2_mode_reg_data);
+}
+
+static void configure_mr(int nr, u32 cs)
+{
+	u32 mr_addr;
+
+	while (get_mr(nr, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
+		;
+	set_mr(nr, cs, LPDDR2_MR10, 0x56);
+
+	set_mr(nr, cs, LPDDR2_MR1, 0x43);
+	set_mr(nr, cs, LPDDR2_MR2, 0x2);
+
+	mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK;
+	set_mr(nr, cs, mr_addr, 0x2);
+}
+
+/*
+ * Configure EMIF4D5 registers and MR registers For details about these magic
+ * values please see the EMIF registers section of the TRM.
+ */
+void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
+{
+	writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl);
+	writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw);
+	writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
+
+	writel(regs->temp_alert_config, &emif_reg[nr]->emif_temp_alert_config);
+	writel(regs->emif_rd_wr_lvl_rmp_win,
+	       &emif_reg[nr]->emif_rd_wr_lvl_rmp_win);
+	writel(regs->emif_rd_wr_lvl_rmp_ctl,
+	       &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl);
+	writel(regs->emif_rd_wr_lvl_ctl, &emif_reg[nr]->emif_rd_wr_lvl_ctl);
+	writel(regs->emif_rd_wr_exec_thresh,
+	       &emif_reg[nr]->emif_rd_wr_exec_thresh);
+
+	/*
+	 * for most SOCs these registers won't need to be changed so only
+	 * write to these registers if someone explicitly has set the
+	 * register's value.
+	 */
+	if(regs->emif_cos_config) {
+		writel(regs->emif_prio_class_serv_map, &emif_reg[nr]->emif_prio_class_serv_map);
+		writel(regs->emif_connect_id_serv_1_map, &emif_reg[nr]->emif_connect_id_serv_1_map);
+		writel(regs->emif_connect_id_serv_2_map, &emif_reg[nr]->emif_connect_id_serv_2_map);
+		writel(regs->emif_cos_config, &emif_reg[nr]->emif_cos_config);
+	}
+
+	/*
+	 * Sequence to ensure that the PHY is in a known state prior to
+	 * startting hardware leveling.  Also acts as to latch some state from
+	 * the EMIF into the PHY.
+	 */
+	writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
+	writel(0x2411, &emif_reg[nr]->emif_iodft_tlgc);
+	writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
+
+	clrbits_le32(&emif_reg[nr]->emif_sdram_ref_ctrl,
+			EMIF_REG_INITREF_DIS_MASK);
+
+	writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
+	writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
+
+	/* Wait 1ms because of L3 timeout error */
+	udelay(1000);
+
+	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
+	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
+
+	/* Perform hardware leveling for DDR3 */
+	if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3) {
+		writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36) |
+		       0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36);
+		writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw) |
+		       0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw);
+
+		writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl);
+
+		/* Enable read leveling */
+		writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_ctl);
+
+		/*
+		 * Enable full read and write leveling.  Wait for read and write
+		 * leveling bit to clear RDWRLVLFULL_START bit 31
+		 */
+		while ((readl(&emif_reg[nr]->emif_rd_wr_lvl_ctl) & 0x80000000)
+		      != 0)
+			;
+
+		/* Check the timeout register to see if leveling is complete */
+		if ((readl(&emif_reg[nr]->emif_status) & 0x70) != 0)
+			puts("DDR3 H/W leveling incomplete with errors\n");
+
+	} else {
+		/* DDR2 */
+		configure_mr(nr, 0);
+		configure_mr(nr, 1);
+	}
+}
+
+/**
+ * Configure SDRAM
+ */
+void config_sdram(const struct emif_regs *regs, int nr)
+{
+	if (regs->zq_config) {
+		writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
+		writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
+		writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
+
+		/* Trigger initialization */
+		writel(0x00003100, &emif_reg[nr]->emif_sdram_ref_ctrl);
+		/* Wait 1ms because of L3 timeout error */
+		udelay(1000);
+
+		/* Write proper sdram_ref_cref_ctrl value */
+		writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
+		writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
+	}
+	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
+	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
+	writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
+}
+
+/**
+ * Set SDRAM timings
+ */
+void set_sdram_timings(const struct emif_regs *regs, int nr)
+{
+	writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1);
+	writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1_shdw);
+	writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2);
+	writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2_shdw);
+	writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3);
+	writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3_shdw);
+}
+
+/*
+ * Configure EXT PHY registers for software leveling
+ */
+static void ext_phy_settings_swlvl(const struct emif_regs *regs, int nr)
+{
+	u32 *ext_phy_ctrl_base = 0;
+	u32 *emif_ext_phy_ctrl_base = 0;
+	__maybe_unused const u32 *ext_phy_ctrl_const_regs;
+	u32 i = 0;
+	__maybe_unused u32 size;
+
+	ext_phy_ctrl_base = (u32 *)&(regs->emif_ddr_ext_phy_ctrl_1);
+	emif_ext_phy_ctrl_base =
+			(u32 *)&(emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
+
+	/* Configure external phy control timing registers */
+	for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
+		writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
+		/* Update shadow registers */
+		writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
+	}
+
+#ifdef CONFIG_AM43XX
+	/*
+	 * External phy 6-24 registers do not change with ddr frequency.
+	 * These only need to be set on DDR2 on AM43xx.
+	 */
+	emif_get_ext_phy_ctrl_const_regs(&ext_phy_ctrl_const_regs, &size);
+
+	if (!size)
+		return;
+
+	for (i = 0; i < size; i++) {
+		writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++);
+		/* Update shadow registers */
+		writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++);
+	}
+#endif
+}
+
+/*
+ * Configure EXT PHY registers for hardware leveling
+ */
+static void ext_phy_settings_hwlvl(const struct emif_regs *regs, int nr)
+{
+	/*
+	 * Enable hardware leveling on the EMIF.  For details about these
+	 * magic values please see the EMIF registers section of the TRM.
+	 */
+	writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
+	writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1_shdw);
+	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_22);
+	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_22_shdw);
+	writel(0x00600020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_23);
+	writel(0x00600020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_23_shdw);
+	writel(0x40010080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_24);
+	writel(0x40010080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_24_shdw);
+	writel(0x08102040, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_25);
+	writel(0x08102040, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_25_shdw);
+	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_26);
+	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_26_shdw);
+	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_27);
+	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_27_shdw);
+	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_28);
+	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_28_shdw);
+	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_29);
+	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_29_shdw);
+	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_30);
+	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_30_shdw);
+	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_31);
+	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_31_shdw);
+	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_32);
+	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_32_shdw);
+	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_33);
+	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_33_shdw);
+	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_34);
+	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_34_shdw);
+	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35);
+	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35_shdw);
+	writel(0x000000FF, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36);
+	writel(0x000000FF, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw);
+
+	/*
+	 * Sequence to ensure that the PHY is again in a known state after
+	 * hardware leveling.
+	 */
+	writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
+	writel(0x2411, &emif_reg[nr]->emif_iodft_tlgc);
+	writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
+}
+
+/**
+ * Configure DDR PHY
+ */
+void config_ddr_phy(const struct emif_regs *regs, int nr)
+{
+	/*
+	 * Disable initialization and refreshes for now until we finish
+	 * programming EMIF regs and set time between rising edge of
+	 * DDR_RESET to rising edge of DDR_CKE to > 500us per memory spec.
+	 * We currently hardcode a value based on a max expected frequency
+	 * of 400MHz.
+	 */
+	writel(EMIF_REG_INITREF_DIS_MASK | 0x3100,
+		&emif_reg[nr]->emif_sdram_ref_ctrl);
+
+	writel(regs->emif_ddr_phy_ctlr_1,
+		&emif_reg[nr]->emif_ddr_phy_ctrl_1);
+	writel(regs->emif_ddr_phy_ctlr_1,
+		&emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw);
+
+	if (get_emif_rev((u32)emif_reg[nr]) == EMIF_4D5) {
+		if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3)
+			ext_phy_settings_hwlvl(regs, nr);
+		else
+			ext_phy_settings_swlvl(regs, nr);
+	}
+}
+
+/**
+ * Configure DDR CMD control registers
+ */
+void config_cmd_ctrl(const struct cmd_control *cmd, int nr)
+{
+	if (!cmd)
+		return;
+
+	writel(cmd->cmd0csratio, &ddr_cmd_reg[nr]->cm0csratio);
+	writel(cmd->cmd0iclkout, &ddr_cmd_reg[nr]->cm0iclkout);
+
+	writel(cmd->cmd1csratio, &ddr_cmd_reg[nr]->cm1csratio);
+	writel(cmd->cmd1iclkout, &ddr_cmd_reg[nr]->cm1iclkout);
+
+	writel(cmd->cmd2csratio, &ddr_cmd_reg[nr]->cm2csratio);
+	writel(cmd->cmd2iclkout, &ddr_cmd_reg[nr]->cm2iclkout);
+}
+
+/**
+ * Configure DDR DATA registers
+ */
+void config_ddr_data(const struct ddr_data *data, int nr)
+{
+	int i;
+
+	if (!data)
+		return;
+
+	for (i = 0; i < DDR_DATA_REGS_NR; i++) {
+		writel(data->datardsratio0,
+			&(ddr_data_reg[nr]+i)->dt0rdsratio0);
+		writel(data->datawdsratio0,
+			&(ddr_data_reg[nr]+i)->dt0wdsratio0);
+		writel(data->datawiratio0,
+			&(ddr_data_reg[nr]+i)->dt0wiratio0);
+		writel(data->datagiratio0,
+			&(ddr_data_reg[nr]+i)->dt0giratio0);
+		writel(data->datafwsratio0,
+			&(ddr_data_reg[nr]+i)->dt0fwsratio0);
+		writel(data->datawrsratio0,
+			&(ddr_data_reg[nr]+i)->dt0wrsratio0);
+	}
+}
+
+void config_io_ctrl(const struct ctrl_ioregs *ioregs)
+{
+	if (!ioregs)
+		return;
+
+	writel(ioregs->cm0ioctl, &ioctrl_reg->cm0ioctl);
+	writel(ioregs->cm1ioctl, &ioctrl_reg->cm1ioctl);
+	writel(ioregs->cm2ioctl, &ioctrl_reg->cm2ioctl);
+	writel(ioregs->dt0ioctl, &ioctrl_reg->dt0ioctl);
+	writel(ioregs->dt1ioctl, &ioctrl_reg->dt1ioctl);
+#ifdef CONFIG_AM43XX
+	writel(ioregs->dt2ioctrl, &ioctrl_reg->dt2ioctrl);
+	writel(ioregs->dt3ioctrl, &ioctrl_reg->dt3ioctrl);
+	writel(ioregs->emif_sdram_config_ext,
+	       &ioctrl_reg->emif_sdram_config_ext);
+#endif
+}

arch/arm/cpu/armv7/am33xx/emif4.c

@@ -0,0 +1,140 @@
+/*
+ * emif4.c
+ *
+ * AM33XX emif4 configuration file
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+	sdram_init();
+#endif
+
+	/* dram_init must store complete ramsize in gd->ram_size */
+	gd->ram_size = get_ram_size(
+			(void *)CONFIG_SYS_SDRAM_BASE,
+			CONFIG_MAX_RAM_BANK_SIZE);
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].size = gd->ram_size;
+}
+
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#ifdef CONFIG_TI81XX
+static struct dmm_lisa_map_regs *hw_lisa_map_regs =
+				(struct dmm_lisa_map_regs *)DMM_BASE;
+#endif
+#ifndef CONFIG_TI816X
+static struct vtp_reg *vtpreg[2] = {
+				(struct vtp_reg *)VTP0_CTRL_ADDR,
+				(struct vtp_reg *)VTP1_CTRL_ADDR};
+#endif
+#ifdef CONFIG_AM33XX
+static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
+#endif
+#ifdef CONFIG_AM43XX
+static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
+static struct cm_device_inst *cm_device =
+				(struct cm_device_inst *)CM_DEVICE_INST;
+#endif
+
+#ifdef CONFIG_TI81XX
+void config_dmm(const struct dmm_lisa_map_regs *regs)
+{
+	enable_dmm_clocks();
+
+	writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
+	writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
+	writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
+	writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
+
+	writel(regs->dmm_lisa_map_3, &hw_lisa_map_regs->dmm_lisa_map_3);
+	writel(regs->dmm_lisa_map_2, &hw_lisa_map_regs->dmm_lisa_map_2);
+	writel(regs->dmm_lisa_map_1, &hw_lisa_map_regs->dmm_lisa_map_1);
+	writel(regs->dmm_lisa_map_0, &hw_lisa_map_regs->dmm_lisa_map_0);
+}
+#endif
+
+#ifndef CONFIG_TI816X
+static void config_vtp(int nr)
+{
+	writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_ENABLE,
+			&vtpreg[nr]->vtp0ctrlreg);
+	writel(readl(&vtpreg[nr]->vtp0ctrlreg) & (~VTP_CTRL_START_EN),
+			&vtpreg[nr]->vtp0ctrlreg);
+	writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_START_EN,
+			&vtpreg[nr]->vtp0ctrlreg);
+
+	/* Poll for READY */
+	while ((readl(&vtpreg[nr]->vtp0ctrlreg) & VTP_CTRL_READY) !=
+			VTP_CTRL_READY)
+		;
+}
+#endif
+
+void __weak ddr_pll_config(unsigned int ddrpll_m)
+{
+}
+
+void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
+		const struct ddr_data *data, const struct cmd_control *ctrl,
+		const struct emif_regs *regs, int nr)
+{
+	ddr_pll_config(pll);
+#ifndef CONFIG_TI816X
+	config_vtp(nr);
+#endif
+	config_cmd_ctrl(ctrl, nr);
+
+	config_ddr_data(data, nr);
+#ifdef CONFIG_AM33XX
+	config_io_ctrl(ioregs);
+
+	/* Set CKE to be controlled by EMIF/DDR PHY */
+	writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
+
+#endif
+#ifdef CONFIG_AM43XX
+	writel(readl(&cm_device->cm_dll_ctrl) & ~0x1, &cm_device->cm_dll_ctrl);
+	while ((readl(&cm_device->cm_dll_ctrl) & CM_DLL_READYST) == 0)
+		;
+
+	config_io_ctrl(ioregs);
+
+	/* Set CKE to be controlled by EMIF/DDR PHY */
+	writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
+
+	if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3)
+		/* Allow EMIF to control DDR_RESET */
+		writel(0x00000000, &ddrctrl->ddrioctrl);
+#endif
+
+	/* Program EMIF instance */
+	config_ddr_phy(regs, nr);
+	set_sdram_timings(regs, nr);
+	if (get_emif_rev(EMIF1_BASE) == EMIF_4D5)
+		config_sdram_emif4d5(regs, nr);
+	else
+		config_sdram(regs, nr);
+}
+#endif

arch/arm/cpu/armv7/am33xx/sys_info.c

@@ -0,0 +1,175 @@
+/*
+ * sys_info.c
+ *
+ * System information functions
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * Derived from Beagle Board and 3430 SDP code by
+ *      Richard Woodruff <r-woodruff2@ti.com>
+ *      Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clock.h>
+#include <power/tps65910.h>
+#include <linux/compiler.h>
+
+struct ctrl_stat *cstat = (struct ctrl_stat *)CTRL_BASE;
+
+/**
+ * get_cpu_rev(void) - extract rev info
+ */
+u32 get_cpu_rev(void)
+{
+	u32 id;
+	u32 rev;
+
+	id = readl(DEVICE_ID);
+	rev = (id >> 28) & 0xff;
+
+	return rev;
+}
+
+/**
+ * get_cpu_type(void) - extract cpu info
+ */
+u32 get_cpu_type(void)
+{
+	u32 id = 0;
+	u32 partnum;
+
+	id = readl(DEVICE_ID);
+	partnum = (id >> 12) & 0xffff;
+
+	return partnum;
+}
+
+/**
+ * get_device_type(): tell if GP/HS/EMU/TST
+ */
+u32 get_device_type(void)
+{
+	int mode;
+	mode = readl(&cstat->statusreg) & (DEVICE_MASK);
+	return mode >>= 8;
+}
+
+/**
+ * get_sysboot_value(void) - return SYS_BOOT[4:0]
+ */
+u32 get_sysboot_value(void)
+{
+	int mode;
+	mode = readl(&cstat->statusreg) & (SYSBOOT_MASK);
+	return mode;
+}
+
+#ifdef CONFIG_DISPLAY_CPUINFO
+static char *cpu_revs[] = {
+		"1.0",
+		"2.0",
+		"2.1"};
+
+
+static char *dev_types[] = {
+		"TST",
+		"EMU",
+		"HS",
+		"GP"};
+
+/**
+ * Print CPU information
+ */
+int print_cpuinfo(void)
+{
+	char *cpu_s, *sec_s, *rev_s;
+
+	switch (get_cpu_type()) {
+	case AM335X:
+		cpu_s = "AM335X";
+		break;
+	case TI81XX:
+		cpu_s = "TI81XX";
+		break;
+	default:
+		cpu_s = "Unknown CPU type";
+		break;
+	}
+
+	if (get_cpu_rev() < ARRAY_SIZE(cpu_revs))
+		rev_s = cpu_revs[get_cpu_rev()];
+	else
+		rev_s = "?";
+
+	if (get_device_type() < ARRAY_SIZE(dev_types))
+		sec_s = dev_types[get_device_type()];
+	else
+		sec_s = "?";
+
+	printf("%s-%s rev %s\n", cpu_s, sec_s, rev_s);
+
+	return 0;
+}
+#endif	/* CONFIG_DISPLAY_CPUINFO */
+
+#ifdef CONFIG_AM33XX
+int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev)
+{
+	int sil_rev;
+
+	sil_rev = readl(&cdev->deviceid) >> 28;
+
+	if (sil_rev == 1)
+		/* PG 2.0, efuse may not be set. */
+		return MPUPLL_M_800;
+	else if (sil_rev >= 2) {
+		/* Check what the efuse says our max speed is. */
+		int efuse_arm_mpu_max_freq;
+		efuse_arm_mpu_max_freq = readl(&cdev->efuse_sma);
+		switch ((efuse_arm_mpu_max_freq & DEVICE_ID_MASK)) {
+		case AM335X_ZCZ_1000:
+			return MPUPLL_M_1000;
+		case AM335X_ZCZ_800:
+			return MPUPLL_M_800;
+		case AM335X_ZCZ_720:
+			return MPUPLL_M_720;
+		case AM335X_ZCZ_600:
+		case AM335X_ZCE_600:
+			return MPUPLL_M_600;
+		case AM335X_ZCZ_300:
+		case AM335X_ZCE_300:
+			return MPUPLL_M_300;
+		}
+	}
+
+	/* PG 1.0 or otherwise unknown, use the PG1.0 max */
+	return MPUPLL_M_720;
+}
+
+int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency)
+{
+	/* For PG2.1 and later, we have one set of values. */
+	if (sil_rev >= 2) {
+		switch (frequency) {
+		case MPUPLL_M_1000:
+			return TPS65910_OP_REG_SEL_1_3_2_5;
+		case MPUPLL_M_800:
+			return TPS65910_OP_REG_SEL_1_2_6;
+		case MPUPLL_M_720:
+			return TPS65910_OP_REG_SEL_1_2_0;
+		case MPUPLL_M_600:
+		case MPUPLL_M_300:
+			return TPS65910_OP_REG_SEL_1_1_3;
+		}
+	}
+
+	/* Default to PG1.0/PG2.0 values. */
+	return TPS65910_OP_REG_SEL_1_1_3;
+}
+#endif

arch/arm/cpu/armv7/arch_timer.c

@@ -8,7 +8,6 @@
 #include <common.h>
 #include <asm/io.h>
 #include <div64.h>
-#include <bootstage.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -18,6 +17,7 @@ int timer_init(void)
 	gd->arch.tbu = 0;
 
 	gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ;
+
 	return 0;
 }
 
@@ -39,11 +39,6 @@ ulong get_timer(ulong base)
 	return lldiv(get_ticks(), gd->arch.timer_rate_hz) - base;
 }
 
-ulong timer_get_boot_us(void)
-{
-	return lldiv(get_ticks(), CONFIG_SYS_HZ_CLOCK / (CONFIG_SYS_HZ * 1000));
-}
-
 void __udelay(unsigned long usec)
 {
 	unsigned long long endtime;

arch/arm/cpu/armv7/bcm235xx/clk-bcm235xx.c

@@ -12,7 +12,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/sysmap.h>
 #include <asm/kona-common/clk.h>
 #include "clk-core.h"

arch/arm/cpu/armv7/bcm235xx/clk-bsc.c

@@ -6,7 +6,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/sysmap.h>
 #include <asm/kona-common/clk.h>
 #include "clk-core.h"

arch/arm/cpu/armv7/bcm235xx/clk-core.c

@@ -12,7 +12,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <bitfield.h>
 #include <asm/arch/sysmap.h>
 #include <asm/kona-common/clk.h>

arch/arm/cpu/armv7/bcm235xx/clk-eth.c

@@ -6,7 +6,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/sysmap.h>
 #include <asm/kona-common/clk.h>
 #include "clk-core.h"

arch/arm/cpu/armv7/bcm235xx/clk-sdio.c

@@ -6,7 +6,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/sysmap.h>
 #include <asm/kona-common/clk.h>
 #include "clk-core.h"

arch/arm/cpu/armv7/bcm235xx/clk-usb-otg.c

@@ -5,7 +5,7 @@
  */
 
 #include <common.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/sysmap.h>
 #include "clk-core.h"
 

arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c

@@ -12,7 +12,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/sysmap.h>
 #include <asm/kona-common/clk.h>
 #include "clk-core.h"

arch/arm/cpu/armv7/bcm281xx/clk-bsc.c

@@ -6,7 +6,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/sysmap.h>
 #include <asm/kona-common/clk.h>
 #include "clk-core.h"

arch/arm/cpu/armv7/bcm281xx/clk-core.c

@@ -12,7 +12,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <bitfield.h>
 #include <asm/arch/sysmap.h>
 #include <asm/kona-common/clk.h>

arch/arm/cpu/armv7/bcm281xx/clk-eth.c

@@ -6,7 +6,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/sysmap.h>
 #include <asm/kona-common/clk.h>
 #include "clk-core.h"

arch/arm/cpu/armv7/bcm281xx/clk-sdio.c

@@ -6,7 +6,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/sysmap.h>
 #include <asm/kona-common/clk.h>
 #include "clk-core.h"

arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c

@@ -5,7 +5,7 @@
  */
 
 #include <common.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/sysmap.h>
 #include "clk-core.h"
 

arch/arm/cpu/armv7/cache_v7_asm.S

@@ -7,7 +7,7 @@
 #include <linux/sizes.h>
 #include <asm/system.h>
 
-#if CONFIG_IS_ENABLED(SYS_THUMB_BUILD)
+#ifdef CONFIG_SYS_THUMB_BUILD
 #define ARM(x...)
 #define THUMB(x...)	x
 #else

arch/arm/cpu/armv7/lowlevel_init.S

@@ -19,11 +19,7 @@ ENTRY(lowlevel_init)
 	/*
 	 * Setup a temporary stack. Global data is not available yet.
 	 */
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
-	ldr	sp, =CONFIG_SPL_STACK
-#else
 	ldr	sp, =CONFIG_SYS_INIT_SP_ADDR
-#endif
 	bic	sp, sp, #7 /* 8-byte alignment for ABI compliance */
 #ifdef CONFIG_SPL_DM
 	mov	r9, #0

arch/arm/cpu/armv7/ls102xa/Kconfig

@@ -1,70 +0,0 @@
-config ARCH_LS1021A
-	bool
-	select SYS_FSL_ERRATUM_A008378
-	select SYS_FSL_ERRATUM_A008407
-	select SYS_FSL_ERRATUM_A009663
-	select SYS_FSL_ERRATUM_A009942
-	select SYS_FSL_ERRATUM_A010315
-	select SYS_FSL_SRDS_1
-	select SYS_HAS_SERDES
-	select SYS_FSL_DDR_BE if SYS_FSL_DDR
-	select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR
-	select SYS_FSL_HAS_DDR3 if SYS_FSL_DDR
-	select SYS_FSL_HAS_DDR4 if SYS_FSL_DDR
-	select SYS_FSL_HAS_SEC
-	select SYS_FSL_SEC_COMPAT_5
-	select SYS_FSL_SEC_LE
-
-menu "LS102xA architecture"
-	depends on ARCH_LS1021A
-
-config FSL_PCIE_COMPAT
-	string "PCIe compatible of Kernel DT"
-	depends on PCIE_LAYERSCAPE
-	default "fsl,ls1021a-pcie" if ARCH_LS1021A
-	help
-	  This compatible is used to find pci controller node in Kernel DT
-	  to complete fixup.
-
-config LS1_DEEP_SLEEP
-	bool "Deep sleep"
-	depends on ARCH_LS1021A
-
-config MAX_CPUS
-	int "Maximum number of CPUs permitted for LS102xA"
-	depends on ARCH_LS1021A
-	default 2
-	help
-	  Set this number to the maximum number of possible CPUs in the SoC.
-	  SoCs may have multiple clusters with each cluster may have multiple
-	  ports. If some ports are reserved but higher ports are used for
-	  cores, count the reserved ports. This will allocate enough memory
-	  in spin table to properly handle all cores.
-
-config SECURE_BOOT
-	bool	"Secure Boot"
-	help
-		Enable Freescale Secure Boot feature. Normally selected
-		by defconfig. If unsure, do not change.
-
-config SYS_FSL_ERRATUM_A010315
-	bool "Workaround for PCIe erratum A010315"
-
-config SYS_FSL_SRDS_1
-	bool
-
-config SYS_FSL_SRDS_2
-	bool
-
-config SYS_HAS_SERDES
-	bool
-
-config SYS_FSL_IFC_BANK_COUNT
-	int "Maximum banks of Integrated flash controller"
-	depends on ARCH_LS1021A
-	default 8
-
-config SYS_FSL_ERRATUM_A008407
-	bool
-
-endmenu

arch/arm/cpu/armv7/ls102xa/Makefile

@@ -16,5 +16,5 @@ obj-$(CONFIG_SYS_HAS_SERDES) += fsl_ls1_serdes.o ls102xa_serdes.o
 obj-$(CONFIG_SPL) += spl.o
 
 ifdef CONFIG_ARMV7_PSCI
-obj-y  += psci.o ls102xa_psci.o
+obj-y  += psci.o
 endif

arch/arm/cpu/armv7/ls102xa/clock.c

@@ -19,6 +19,10 @@ DECLARE_GLOBAL_DATA_PTR;
 void get_sys_info(struct sys_info *sys_info)
 {
 	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+#ifdef CONFIG_FSL_IFC
+	struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
+	u32 ccr;
+#endif
 	struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_LS1_CLK_ADDR);
 	unsigned int cpu;
 	const u8 core_cplx_pll[6] = {
@@ -70,7 +74,10 @@ void get_sys_info(struct sys_info *sys_info)
 	}
 
 #if defined(CONFIG_FSL_IFC)
-	sys_info->freq_localbus = sys_info->freq_systembus;
+	ccr = in_be32(&ifc_regs.gregs->ifc_ccr);
+	ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
+
+	sys_info->freq_localbus = sys_info->freq_systembus / ccr;
 #endif
 }
 

arch/arm/cpu/armv7/ls102xa/fdt.c

@@ -94,6 +94,8 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 	}
 #endif
 
+	fdt_fixup_ethernet(blob);
+
 	off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
 	while (off != -FDT_ERR_NOTFOUND) {
 		val = gd->cpu_clk;

arch/arm/cpu/armv7/ls102xa/fsl_epu.c

@@ -9,163 +9,6 @@
 
 #include "fsl_epu.h"
 
-struct fsm_reg_vals epu_default_val[] = {
-	/* EPGCR (Event Processor Global Control Register) */
-	{EPGCR, 0},
-	/* EPECR (Event Processor Event Control Registers) */
-	{EPECR0 + EPECR_STRIDE * 0, 0},
-	{EPECR0 + EPECR_STRIDE * 1, 0},
-	{EPECR0 + EPECR_STRIDE * 2, 0xF0004004},
-	{EPECR0 + EPECR_STRIDE * 3, 0x80000084},
-	{EPECR0 + EPECR_STRIDE * 4, 0x20000084},
-	{EPECR0 + EPECR_STRIDE * 5, 0x08000004},
-	{EPECR0 + EPECR_STRIDE * 6, 0x80000084},
-	{EPECR0 + EPECR_STRIDE * 7, 0x80000084},
-	{EPECR0 + EPECR_STRIDE * 8, 0x60000084},
-	{EPECR0 + EPECR_STRIDE * 9, 0x08000084},
-	{EPECR0 + EPECR_STRIDE * 10, 0x42000084},
-	{EPECR0 + EPECR_STRIDE * 11, 0x90000084},
-	{EPECR0 + EPECR_STRIDE * 12, 0x80000084},
-	{EPECR0 + EPECR_STRIDE * 13, 0x08000084},
-	{EPECR0 + EPECR_STRIDE * 14, 0x02000084},
-	{EPECR0 + EPECR_STRIDE * 15, 0x00000004},
-	/*
-	 * EPEVTCR (Event Processor EVT Pin Control Registers)
-	 * SCU8 triger EVT2, and SCU11 triger EVT9
-	 */
-	{EPEVTCR0 + EPEVTCR_STRIDE * 0, 0},
-	{EPEVTCR0 + EPEVTCR_STRIDE * 1, 0},
-	{EPEVTCR0 + EPEVTCR_STRIDE * 2, 0x80000001},
-	{EPEVTCR0 + EPEVTCR_STRIDE * 3, 0},
-	{EPEVTCR0 + EPEVTCR_STRIDE * 4, 0},
-	{EPEVTCR0 + EPEVTCR_STRIDE * 5, 0},
-	{EPEVTCR0 + EPEVTCR_STRIDE * 6, 0},
-	{EPEVTCR0 + EPEVTCR_STRIDE * 7, 0},
-	{EPEVTCR0 + EPEVTCR_STRIDE * 8, 0},
-	{EPEVTCR0 + EPEVTCR_STRIDE * 9, 0xB0000001},
-	/* EPCMPR (Event Processor Counter Compare Registers) */
-	{EPCMPR0 + EPCMPR_STRIDE * 0, 0},
-	{EPCMPR0 + EPCMPR_STRIDE * 1, 0},
-	{EPCMPR0 + EPCMPR_STRIDE * 2, 0x000000FF},
-	{EPCMPR0 + EPCMPR_STRIDE * 3, 0},
-	{EPCMPR0 + EPCMPR_STRIDE * 4, 0x000000FF},
-	{EPCMPR0 + EPCMPR_STRIDE * 5, 0x00000020},
-	{EPCMPR0 + EPCMPR_STRIDE * 6, 0},
-	{EPCMPR0 + EPCMPR_STRIDE * 7, 0},
-	{EPCMPR0 + EPCMPR_STRIDE * 8, 0x000000FF},
-	{EPCMPR0 + EPCMPR_STRIDE * 9, 0x000000FF},
-	{EPCMPR0 + EPCMPR_STRIDE * 10, 0x000000FF},
-	{EPCMPR0 + EPCMPR_STRIDE * 11, 0x000000FF},
-	{EPCMPR0 + EPCMPR_STRIDE * 12, 0x000000FF},
-	{EPCMPR0 + EPCMPR_STRIDE * 13, 0},
-	{EPCMPR0 + EPCMPR_STRIDE * 14, 0x000000FF},
-	{EPCMPR0 + EPCMPR_STRIDE * 15, 0x000000FF},
-	/* EPCCR (Event Processor Counter Control Registers) */
-	{EPCCR0 + EPCCR_STRIDE * 0, 0},
-	{EPCCR0 + EPCCR_STRIDE * 1, 0},
-	{EPCCR0 + EPCCR_STRIDE * 2, 0x92840000},
-	{EPCCR0 + EPCCR_STRIDE * 3, 0},
-	{EPCCR0 + EPCCR_STRIDE * 4, 0x92840000},
-	{EPCCR0 + EPCCR_STRIDE * 5, 0x92840000},
-	{EPCCR0 + EPCCR_STRIDE * 6, 0},
-	{EPCCR0 + EPCCR_STRIDE * 7, 0},
-	{EPCCR0 + EPCCR_STRIDE * 8, 0x92840000},
-	{EPCCR0 + EPCCR_STRIDE * 9, 0x92840000},
-	{EPCCR0 + EPCCR_STRIDE * 10, 0x92840000},
-	{EPCCR0 + EPCCR_STRIDE * 11, 0x92840000},
-	{EPCCR0 + EPCCR_STRIDE * 12, 0x92840000},
-	{EPCCR0 + EPCCR_STRIDE * 13, 0},
-	{EPCCR0 + EPCCR_STRIDE * 14, 0x92840000},
-	{EPCCR0 + EPCCR_STRIDE * 15, 0x92840000},
-	/* EPSMCR (Event Processor SCU Mux Control Registers) */
-	{EPSMCR0 + EPSMCR_STRIDE * 0, 0},
-	{EPSMCR0 + EPSMCR_STRIDE * 1, 0},
-	{EPSMCR0 + EPSMCR_STRIDE * 2, 0x6C700000},
-	{EPSMCR0 + EPSMCR_STRIDE * 3, 0x2F000000},
-	{EPSMCR0 + EPSMCR_STRIDE * 4, 0x002F0000},
-	{EPSMCR0 + EPSMCR_STRIDE * 5, 0x00002E00},
-	{EPSMCR0 + EPSMCR_STRIDE * 6, 0x7C000000},
-	{EPSMCR0 + EPSMCR_STRIDE * 7, 0x30000000},
-	{EPSMCR0 + EPSMCR_STRIDE * 8, 0x64300000},
-	{EPSMCR0 + EPSMCR_STRIDE * 9, 0x00003000},
-	{EPSMCR0 + EPSMCR_STRIDE * 10, 0x65000030},
-	{EPSMCR0 + EPSMCR_STRIDE * 11, 0x31740000},
-	{EPSMCR0 + EPSMCR_STRIDE * 12, 0x7F000000},
-	{EPSMCR0 + EPSMCR_STRIDE * 13, 0x00003100},
-	{EPSMCR0 + EPSMCR_STRIDE * 14, 0x00000031},
-	{EPSMCR0 + EPSMCR_STRIDE * 15, 0x76000000},
-	/* EPACR (Event Processor Action Control Registers) */
-	{EPACR0 + EPACR_STRIDE * 0, 0},
-	{EPACR0 + EPACR_STRIDE * 1, 0},
-	{EPACR0 + EPACR_STRIDE * 2, 0},
-	{EPACR0 + EPACR_STRIDE * 3, 0x00000080},
-	{EPACR0 + EPACR_STRIDE * 4, 0},
-	{EPACR0 + EPACR_STRIDE * 5, 0x00000040},
-	{EPACR0 + EPACR_STRIDE * 6, 0},
-	{EPACR0 + EPACR_STRIDE * 7, 0},
-	{EPACR0 + EPACR_STRIDE * 8, 0},
-	{EPACR0 + EPACR_STRIDE * 9, 0x0000001C},
-	{EPACR0 + EPACR_STRIDE * 10, 0x00000020},
-	{EPACR0 + EPACR_STRIDE * 11, 0},
-	{EPACR0 + EPACR_STRIDE * 12, 0x00000003},
-	{EPACR0 + EPACR_STRIDE * 13, 0x06000000},
-	{EPACR0 + EPACR_STRIDE * 14, 0x04000000},
-	{EPACR0 + EPACR_STRIDE * 15, 0x02000000},
-	/* EPIMCR (Event Processor Input Mux Control Registers) */
-	{EPIMCR0 + EPIMCR_STRIDE * 0, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 1, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 2, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 3, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 4, 0x44000000},
-	{EPIMCR0 + EPIMCR_STRIDE * 5, 0x40000000},
-	{EPIMCR0 + EPIMCR_STRIDE * 6, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 7, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 8, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 9, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 10, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 11, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 12, 0x44000000},
-	{EPIMCR0 + EPIMCR_STRIDE * 13, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 14, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 15, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 16, 0x6A000000},
-	{EPIMCR0 + EPIMCR_STRIDE * 17, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 18, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 19, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 20, 0x48000000},
-	{EPIMCR0 + EPIMCR_STRIDE * 21, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 22, 0x6C000000},
-	{EPIMCR0 + EPIMCR_STRIDE * 23, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 24, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 25, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 26, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 27, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 28, 0x76000000},
-	{EPIMCR0 + EPIMCR_STRIDE * 29, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 30, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 31, 0x76000000},
-	/* EPXTRIGCR (Event Processor Crosstrigger Control Register) */
-	{EPXTRIGCR, 0x0000FFDF},
-	/* end */
-	{FSM_END_FLAG, 0},
-};
-
-/**
- * fsl_epu_setup - Setup EPU registers to default values
- */
-void fsl_epu_setup(void *epu_base)
-{
-	struct fsm_reg_vals *data = epu_default_val;
-
-	if (!epu_base || !data)
-		return;
-
-	while (data->offset != FSM_END_FLAG) {
-		out_be32(epu_base + data->offset, data->value);
-		data++;
-	}
-}
-
 /**
  * fsl_epu_clean - Clear EPU registers
  */

arch/arm/cpu/armv7/ls102xa/fsl_epu.h

@@ -63,14 +63,6 @@
 #define EPCTR31		0xA7C
 #define EPCTR_STRIDE	FSL_STRIDE_4B
 
-#define FSM_END_FLAG	0xFFFFFFFFUL
-
-struct fsm_reg_vals {
-	u32 offset;
-	u32 value;
-};
-
-void fsl_epu_setup(void *epu_base);
 void fsl_epu_clean(void *epu_base);
 
 #endif

arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c

@@ -7,7 +7,7 @@
 #include <common.h>
 #include <asm/arch/fsl_serdes.h>
 #include <asm/arch/immap_ls102xa.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/io.h>
 #include "fsl_ls1_serdes.h"
 
@@ -23,15 +23,9 @@ int is_serdes_configured(enum srds_prtcl device)
 	u64 ret = 0;
 
 #ifdef CONFIG_SYS_FSL_SRDS_1
-	if (!(serdes1_prtcl_map & (1ULL << NONE)))
-		fsl_serdes_init();
-
 	ret |= (1ULL << device) & serdes1_prtcl_map;
 #endif
 #ifdef CONFIG_SYS_FSL_SRDS_2
-	if (!(serdes2_prtcl_map & (1ULL << NONE)))
-		fsl_serdes_init();
-
 	ret |= (1ULL << device) & serdes2_prtcl_map;
 #endif
 
@@ -93,24 +87,19 @@ u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift)
 		serdes_prtcl_map |= (1ULL << lane_prtcl);
 	}
 
-	/* Set the first bit to indicate serdes has been initialized */
-	serdes_prtcl_map |= (1ULL << NONE);
-
 	return serdes_prtcl_map;
 }
 
 void fsl_serdes_init(void)
 {
 #ifdef CONFIG_SYS_FSL_SRDS_1
-	if (!(serdes1_prtcl_map & (1ULL << NONE)))
-		serdes1_prtcl_map = serdes_init(FSL_SRDS_1,
+	serdes1_prtcl_map = serdes_init(FSL_SRDS_1,
 					CONFIG_SYS_FSL_SERDES_ADDR,
 					RCWSR4_SRDS1_PRTCL_MASK,
 					RCWSR4_SRDS1_PRTCL_SHIFT);
 #endif
 #ifdef CONFIG_SYS_FSL_SRDS_2
-	if (!(serdes2_prtcl_map & (1ULL << NONE)))
-		serdes2_prtcl_map = serdes_init(FSL_SRDS_2,
+	serdes2_prtcl_map = serdes_init(FSL_SRDS_2,
 					CONFIG_SYS_FSL_SERDES_ADDR +
 					FSL_SRDS_2 * 0x1000,
 					RCWSR4_SRDS2_PRTCL_MASK,

arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c

@@ -1,236 +0,0 @@
-/*
- * Copyright 2016 Freescale Semiconductor, Inc.
- * Author: Hongbo Zhang <hongbo.zhang@nxp.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- * This file implements LS102X platform PSCI SYSTEM-SUSPEND function
- */
-
-#include <config.h>
-#include <asm/io.h>
-#include <asm/psci.h>
-#include <asm/arch/immap_ls102xa.h>
-#include <fsl_immap.h>
-#include "fsl_epu.h"
-
-#define __secure __attribute__((section("._secure.text")))
-
-#define CCSR_GICD_CTLR			0x1000
-#define CCSR_GICC_CTLR			0x2000
-#define DCSR_RCPM_CG1CR0		0x31c
-#define DCSR_RCPM_CSTTACR0		0xb00
-#define DCFG_CRSTSR_WDRFR		0x8
-#define DDR_RESV_LEN			128
-
-#ifdef CONFIG_LS1_DEEP_SLEEP
-/*
- * DDR controller initialization training breaks the first 128 bytes of DDR,
- * save them so that the bootloader can restore them while resuming.
- */
-static void __secure ls1_save_ddr_head(void)
-{
-	const char *src = (const char *)CONFIG_SYS_SDRAM_BASE;
-	char *dest = (char *)(OCRAM_BASE_S_ADDR + OCRAM_S_SIZE - DDR_RESV_LEN);
-	struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
-	int i;
-
-	out_le32(&scfg->sparecr[2], dest);
-
-	for (i = 0; i < DDR_RESV_LEN; i++)
-		*dest++ = *src++;
-}
-
-static void __secure ls1_fsm_setup(void)
-{
-	void *dcsr_epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
-	void *dcsr_rcpm_base = (void *)SYS_FSL_DCSR_RCPM_ADDR;
-
-	out_be32(dcsr_rcpm_base + DCSR_RCPM_CSTTACR0, 0x00001001);
-	out_be32(dcsr_rcpm_base + DCSR_RCPM_CG1CR0, 0x00000001);
-
-	fsl_epu_setup((void *)dcsr_epu_base);
-
-	/* Pull MCKE signal low before enabling deep sleep signal in FPGA */
-	out_be32(dcsr_epu_base + EPECR0, 0x5);
-	out_be32(dcsr_epu_base + EPSMCR15, 0x76300000);
-}
-
-static void __secure ls1_deepsleep_irq_cfg(void)
-{
-	struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
-	struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR;
-	u32 ippdexpcr0, ippdexpcr1, pmcintecr = 0;
-
-	/* Mask interrupts from GIC */
-	out_be32(&rcpm->nfiqoutr, 0x0ffffffff);
-	out_be32(&rcpm->nirqoutr, 0x0ffffffff);
-	/* Mask deep sleep wake-up interrupts while entering deep sleep */
-	out_be32(&rcpm->dsimskr, 0x0ffffffff);
-
-	ippdexpcr0 = in_be32(&rcpm->ippdexpcr0);
-	/*
-	 * Workaround: There is bug of register ippdexpcr1, when read it always
-	 * returns zero, so its value is saved to a scrachpad register to be
-	 * read, that is why we don't read it from register ippdexpcr1 itself.
-	 */
-	ippdexpcr1 = in_le32(&scfg->sparecr[7]);
-
-	if (ippdexpcr0 & RCPM_IPPDEXPCR0_ETSEC)
-		pmcintecr |= SCFG_PMCINTECR_ETSECRXG0 |
-			     SCFG_PMCINTECR_ETSECRXG1 |
-			     SCFG_PMCINTECR_ETSECERRG0 |
-			     SCFG_PMCINTECR_ETSECERRG1;
-
-	if (ippdexpcr0 & RCPM_IPPDEXPCR0_GPIO)
-		pmcintecr |= SCFG_PMCINTECR_GPIO;
-
-	if (ippdexpcr1 & RCPM_IPPDEXPCR1_LPUART)
-		pmcintecr |= SCFG_PMCINTECR_LPUART;
-
-	if (ippdexpcr1 & RCPM_IPPDEXPCR1_FLEXTIMER)
-		pmcintecr |= SCFG_PMCINTECR_FTM;
-
-	/* Always set external IRQ pins as wakeup source */
-	pmcintecr |= SCFG_PMCINTECR_IRQ0 | SCFG_PMCINTECR_IRQ1;
-
-	out_be32(&scfg->pmcintlecr, 0);
-	/* Clear PMC interrupt status */
-	out_be32(&scfg->pmcintsr, 0xffffffff);
-	/* Enable wakeup interrupt during deep sleep */
-	out_be32(&scfg->pmcintecr, pmcintecr);
-}
-
-static void __secure ls1_delay(unsigned int loop)
-{
-	while (loop--) {
-		int i = 1000;
-		while (i--)
-			;
-	}
-}
-
-static void __secure ls1_start_fsm(void)
-{
-	void *dcsr_epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
-	void *ccsr_gic_base = (void *)SYS_FSL_GIC_ADDR;
-	struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
-	struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
-
-	/* Set HRSTCR */
-	setbits_be32(&scfg->hrstcr, 0x80000000);
-
-	/* Place DDR controller in self refresh mode */
-	setbits_be32(&ddr->sdram_cfg_2, 0x80000000);
-
-	ls1_delay(2000);
-
-	/* Set EVT4_B to lock the signal MCKE down */
-	out_be32(dcsr_epu_base + EPECR0, 0x0);
-
-	ls1_delay(2000);
-
-	out_be32(ccsr_gic_base + CCSR_GICD_CTLR, 0x0);
-	out_be32(ccsr_gic_base + CCSR_GICC_CTLR, 0x0);
-
-	/* Enable all EPU Counters */
-	setbits_be32(dcsr_epu_base + EPGCR, 0x80000000);
-
-	/* Enable SCU15 */
-	setbits_be32(dcsr_epu_base + EPECR15, 0x90000004);
-
-	/* Enter WFI mode, and EPU FSM will start */
-	__asm__ __volatile__ ("wfi" : : : "memory");
-
-	/* NEVER ENTER HERE */
-	while (1)
-		;
-}
-
-static void __secure ls1_deep_sleep(u32 entry_point)
-{
-	struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
-	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
-	struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR;
-#ifdef QIXIS_BASE
-	u32 tmp;
-	void *qixis_base = (void *)QIXIS_BASE;
-#endif
-
-	/* Enable cluster to enter the PCL10 state */
-	out_be32(&scfg->clusterpmcr, SCFG_CLUSTERPMCR_WFIL2EN);
-
-	/* Save the first 128 bytes of DDR data */
-	ls1_save_ddr_head();
-
-	/* Save the kernel resume entry */
-	out_le32(&scfg->sparecr[3], entry_point);
-
-	/* Request to put cluster 0 in PCL10 state */
-	setbits_be32(&rcpm->clpcl10setr, RCPM_CLPCL10SETR_C0);
-
-	/* Setup the registers of the EPU FSM for deep sleep */
-	ls1_fsm_setup();
-
-#ifdef QIXIS_BASE
-	/* Connect the EVENT button to IRQ in FPGA */
-	tmp = in_8(qixis_base + QIXIS_CTL_SYS);
-	tmp &= ~QIXIS_CTL_SYS_EVTSW_MASK;
-	tmp |= QIXIS_CTL_SYS_EVTSW_IRQ;
-	out_8(qixis_base + QIXIS_CTL_SYS, tmp);
-
-	/* Enable deep sleep signals in FPGA */
-	tmp = in_8(qixis_base + QIXIS_PWR_CTL2);
-	tmp |= QIXIS_PWR_CTL2_PCTL;
-	out_8(qixis_base + QIXIS_PWR_CTL2, tmp);
-
-	/* Pull down PCIe RST# */
-	tmp = in_8(qixis_base + QIXIS_RST_FORCE_3);
-	tmp |= QIXIS_RST_FORCE_3_PCIESLOT1;
-	out_8(qixis_base + QIXIS_RST_FORCE_3, tmp);
-#endif
-
-	/* Enable Warm Device Reset */
-	setbits_be32(&scfg->dpslpcr, SCFG_DPSLPCR_WDRR_EN);
-	setbits_be32(&gur->crstsr, DCFG_CRSTSR_WDRFR);
-
-	ls1_deepsleep_irq_cfg();
-
-	psci_v7_flush_dcache_all();
-
-	ls1_start_fsm();
-}
-
-#else
-static void __secure ls1_sleep(void)
-{
-	struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
-	struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR;
-
-#ifdef QIXIS_BASE
-	u32 tmp;
-	void *qixis_base = (void *)QIXIS_BASE;
-
-	/* Connect the EVENT button to IRQ in FPGA */
-	tmp = in_8(qixis_base + QIXIS_CTL_SYS);
-	tmp &= ~QIXIS_CTL_SYS_EVTSW_MASK;
-	tmp |= QIXIS_CTL_SYS_EVTSW_IRQ;
-	out_8(qixis_base + QIXIS_CTL_SYS, tmp);
-#endif
-
-	/* Enable cluster to enter the PCL10 state */
-	out_be32(&scfg->clusterpmcr, SCFG_CLUSTERPMCR_WFIL2EN);
-
-	setbits_be32(&rcpm->powmgtcsr, RCPM_POWMGTCSR_LPM20_REQ);
-
-	__asm__ __volatile__ ("wfi" : : : "memory");
-}
-#endif
-
-void __secure ls1_system_suspend(u32 fn, u32 entry_point, u32 context_id)
-{
-#ifdef CONFIG_LS1_DEEP_SLEEP
-	ls1_deep_sleep(entry_point);
-#else
-	ls1_sleep();
-#endif
-}

arch/arm/cpu/armv7/ls102xa/psci.S

@@ -29,7 +29,6 @@
 #define PSCI_FN_AFFINITY_INFO_FEATURE_MASK	0x0
 #define PSCI_FN_SYSTEM_OFF_FEATURE_MASK		0x0
 #define PSCI_FN_SYSTEM_RESET_FEATURE_MASK	0x0
-#define PSCI_FN_SYSTEM_SUSPEND_FEATURE_MASK	0x0
 
 	.pushsection ._secure.text, "ax"
 
@@ -37,7 +36,7 @@
 
 	.align	5
 
-#define	ONE_MS		(COUNTER_FREQUENCY / 1000)
+#define	ONE_MS		(GENERIC_TIMER_CLK / 1000)
 #define	RESET_WAIT	(30 * ONE_MS)
 
 .globl	psci_version
@@ -62,8 +61,6 @@ _ls102x_psci_supported_table:
 	.word	PSCI_FN_SYSTEM_OFF_FEATURE_MASK
 	.word	ARM_PSCI_0_2_FN_SYSTEM_RESET
 	.word	PSCI_FN_SYSTEM_RESET_FEATURE_MASK
-	.word	ARM_PSCI_1_0_FN_SYSTEM_SUSPEND
-	.word	PSCI_FN_SYSTEM_SUSPEND_FEATURE_MASK
 	.word	0
 	.word	ARM_PSCI_RET_NI
 
@@ -246,12 +243,4 @@ psci_system_reset:
 1:	wfi
 	b	1b
 
-.globl	psci_system_suspend
-psci_system_suspend:
-	push	{lr}
-
-	bl	ls1_system_suspend
-
-	pop	{pc}
-
 	.popsection

arch/arm/cpu/armv7/ls102xa/soc.c

@@ -7,11 +7,9 @@
 #include <common.h>
 #include <asm/arch/clock.h>
 #include <asm/io.h>
-#include <asm/arch/fsl_serdes.h>
 #include <asm/arch/immap_ls102xa.h>
 #include <asm/arch/ls102xa_soc.h>
 #include <asm/arch/ls102xa_stream_id.h>
-#include <fsl_csu.h>
 
 struct liodn_id_table sec_liodn_tbl[] = {
 	SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10),
@@ -60,38 +58,17 @@ unsigned int get_soc_major_rev(void)
 	return major;
 }
 
-void s_init(void)
-{
-}
-
-#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
-void erratum_a010315(void)
-{
-	int i;
-
-	for (i = PCIE1; i <= PCIE2; i++)
-		if (!is_serdes_configured(i)) {
-			debug("PCIe%d: disabled all R/W permission!\n", i);
-			set_pcie_ns_access(i, 0);
-		}
-}
-#endif
-
 int arch_soc_init(void)
 {
 	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
 	unsigned int major;
 
-#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
-	enable_layerscape_ns_access();
-#endif
-
 #ifdef CONFIG_FSL_QSPI
 	out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
 #endif
 
-#ifdef CONFIG_VIDEO_FSL_DCU_FB
+#ifdef CONFIG_FSL_DCU_FB
 	out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
 #endif
 

arch/arm/cpu/armv7/ls102xa/timer.c

@@ -62,7 +62,7 @@ int timer_init(void)
 	/* Enable System Counter */
 	writel(SYS_COUNTER_CTRL_ENABLE, &sctr->cntcr);
 
-	freq = COUNTER_FREQUENCY;
+	freq = GENERIC_TIMER_CLK;
 	asm("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));
 
 	/* Set PL1 Physical Timer Ctrl */

arch/arm/cpu/armv7/mx5/Kconfig

@@ -14,63 +14,15 @@ choice
 	prompt "MX5 board select"
 	optional
 
-config TARGET_M53EVK
-	bool "Support m53evk"
-	select MX53
-	select SUPPORT_SPL
-
-config TARGET_MX51EVK
-	bool "Support mx51evk"
-	select BOARD_LATE_INIT
-	select MX51
-
-config TARGET_MX53ARD
-	bool "Support mx53ard"
-	select MX53
-
-config TARGET_MX53CX9020
-	bool "Support CX9020"
-	select BOARD_LATE_INIT
-	select MX53
-	select DM
-	select DM_SERIAL
-
-config TARGET_MX53EVK
-	bool "Support mx53evk"
-	select BOARD_LATE_INIT
-	select MX53
-
-config TARGET_MX53LOCO
-	bool "Support mx53loco"
-	select BOARD_LATE_INIT
-	select MX53
-
-config TARGET_MX53SMD
-	bool "Support mx53smd"
-	select MX53
-
-config TARGET_TS4800
-	bool "Support TS4800"
-	select MX51
-	select SYS_FSL_ERRATUM_ESDHC_A001
-
 config TARGET_USBARMORY
 	bool "Support USB armory"
-	select MX53
+	select CPU_V7
 
 endchoice
 
 config SYS_SOC
 	default "mx5"
 
-source "board/aries/m53evk/Kconfig"
-source "board/beckhoff/mx53cx9020/Kconfig"
-source "board/freescale/mx51evk/Kconfig"
-source "board/freescale/mx53ard/Kconfig"
-source "board/freescale/mx53evk/Kconfig"
-source "board/freescale/mx53loco/Kconfig"
-source "board/freescale/mx53smd/Kconfig"
 source "board/inversepath/usbarmory/Kconfig"
-source "board/technologic/ts4800/Kconfig"
 
 endif

arch/arm/cpu/armv7/mx5/clock.c

@@ -9,7 +9,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/clock.h>