Prepare v2016.09.01

Signed-off-by: Tom Rini <trini@konsulko.com>

Kconfig

@@ -137,6 +137,74 @@ endmenu		# General setup
 
 menu "Boot images"
 
+config SUPPORT_SPL
+	bool
+
+config SUPPORT_TPL
+	bool
+
+config SPL
+	bool
+	depends on SUPPORT_SPL
+	prompt "Enable SPL"
+	help
+	  If you want to build SPL as well as the normal image, say Y.
+
+config SPL_SYS_MALLOC_SIMPLE
+	bool
+	depends on SPL
+	prompt "Only use malloc_simple functions in the SPL"
+	help
+	  Say Y here to only use the *_simple malloc functions from
+	  malloc_simple.c, rather then using the versions from dlmalloc.c;
+	  this will make the SPL binary smaller at the cost of more heap
+	  usage as the *_simple malloc functions do not re-use free-ed mem.
+
+config SPL_STACK_R
+	depends on SPL
+	bool "Enable SDRAM location for SPL stack"
+	help
+	  SPL starts off execution in SRAM and thus typically has only a small
+	  stack available. Since SPL sets up DRAM while in its board_init_f()
+	  function, it is possible for the stack to move there before
+	  board_init_r() is reached. This option enables a special SDRAM
+	  location for the SPL stack. U-Boot SPL switches to this after
+	  board_init_f() completes, and before board_init_r() starts.
+
+config SPL_STACK_R_ADDR
+	depends on SPL_STACK_R
+	hex "SDRAM location for SPL stack"
+	help
+	  Specify the address in SDRAM for the SPL stack. This will be set up
+	  before board_init_r() is called.
+
+config SPL_STACK_R_MALLOC_SIMPLE_LEN
+	depends on SPL_STACK_R && SPL_SYS_MALLOC_SIMPLE
+	hex "Size of malloc_simple heap after switching to DRAM SPL stack"
+	default 0x100000
+	help
+	  Specify the amount of the stack to use as memory pool for
+	  malloc_simple after switching the stack to DRAM. This may be set
+	  to give board_init_r() a larger heap then the initial heap in
+	  SRAM which is limited to SYS_MALLOC_F_LEN bytes.
+
+config SPL_SEPARATE_BSS
+	depends on SPL
+	bool "BSS section is in a different memory region from text"
+	help
+	  Some platforms need a large BSS region in SPL and can provide this
+	  because RAM is already set up. In this case BSS can be moved to RAM.
+	  This option should then be enabled so that the correct device tree
+	  location is used. Normally we put the device tree at the end of BSS
+	  but with this option enabled, it goes at _image_binary_end.
+
+config TPL
+	bool
+	depends on SPL && SUPPORT_TPL
+	prompt "Enable TPL"
+	help
+	  If you want to build TPL as well as the normal image and SPL, say Y.
+
 config FIT
 	bool "Support Flattened Image Tree"
 	help
@@ -291,33 +359,6 @@ config FIT_IMAGE_POST_PROCESS
 	  injected into the FIT creation (i.e. the blobs would have been pre-
 	  processed before being added to the FIT image).
 
-config SPL_DFU_SUPPORT
-	bool "Enable SPL with DFU to load binaries to memory device"
-	depends on USB
-	help
-	  Currently the SPL does not have capability to load the
-	  binaries or boot images to boot devices like ram,eMMC,SPI,etc.
-	  This feature enables the DFU (Device Firmware Upgarde) in SPL with
-	  RAM memory device support. The ROM code will load and execute
-	  the SPL built with dfu. The user can load binaries (u-boot/kernel) to
-	  selected device partition from host-pc using dfu-utils.
-		This feature will be useful to flash the binaries to factory
-	  or bare-metal boards using USB interface.
-
-choice
-	bool "DFU device selection"
-	depends on SPL_DFU_SUPPORT
-
-config SPL_DFU_RAM
-	bool "RAM device"
-	depends on SPL_DFU_SUPPORT
-	help
-	 select RAM/DDR memory device for loading binary images
-	 (u-boot/kernel) to the selected device partition using
-	 DFU and execute the u-boot/kernel from RAM.
-
-endchoice
-
 config SYS_CLK_FREQ
 	depends on ARC || ARCH_SUNXI
 	int "CPU clock frequency"

Makefile

@@ -3,9 +3,9 @@
 #
 
 VERSION = 2016
-PATCHLEVEL = 11
-SUBLEVEL =
-EXTRAVERSION = -rc1
+PATCHLEVEL = 09
+SUBLEVEL = 01
+EXTRAVERSION =
 NAME =
 
 # *DOCUMENTATION*
@@ -655,7 +655,6 @@ libs-y += drivers/power/ \
 libs-y += drivers/spi/
 libs-$(CONFIG_FMAN_ENET) += drivers/net/fm/
 libs-$(CONFIG_SYS_FSL_DDR) += drivers/ddr/fsl/
-libs-$(CONFIG_SYS_FSL_MMDC) += drivers/ddr/fsl/
 libs-$(CONFIG_ALTERA_SDRAM) += drivers/ddr/altera/
 libs-y += drivers/serial/
 libs-y += drivers/usb/dwc3/
@@ -741,8 +740,7 @@ DO_STATIC_RELA =
 endif
 
 # Always append ALL so that arch config.mk's can add custom ones
-ALL-y += u-boot.srec u-boot.bin u-boot.sym System.map u-boot.cfg \
-	binary_size_check no_new_adhoc_configs_check
+ALL-y += u-boot.srec u-boot.bin u-boot.sym System.map u-boot.cfg binary_size_check
 
 ALL-$(CONFIG_ONENAND_U_BOOT) += u-boot-onenand.bin
 ifeq ($(CONFIG_SPL_FSL_PBL),y)
@@ -937,26 +935,8 @@ u-boot.sha1:	u-boot.bin
 u-boot.dis:	u-boot
 		$(OBJDUMP) -d $< > $@
 
-# If .u-boot.cfg.d is still present, then either:
-# a) The previous build used a Makefile that used if_changed rather than
-#    if_changed_dep when building u-boot.cfg, and hence any later builds will
-#    be unaware of the dependencies for u-boot.cfg. In this case, we must
-#    delete u-boot.cfg to force it and .u-boot.cfg.cmd to be rebuilt the
-#    correct way.
-# b) The previous build failed or was interrupted while building u-boot.cfg,
-#    so deleting u-boot.cfg isn't going to cause any additional work.
-ifneq ($(wildcard $(obj)/.u-boot.cfg.d),)
-  unused := $(shell rm -f $(obj)/u-boot.cfg)
-endif
 u-boot.cfg:	include/config.h FORCE
-	$(call if_changed_dep,cpp_cfg)
-
-# Check that this build does not use CONFIG options that we don't know about
-# unless they are in Kconfig. All the existing CONFIG options are whitelisted,
-# so new ones should not be added.
-no_new_adhoc_configs_check: u-boot.cfg FORCE
-	$(srctree)/scripts/check-config.sh $< \
-		$(srctree)/scripts/config_whitelist.txt ${srctree} 1>&2
+	$(call if_changed,cpp_cfg)
 
 ifdef CONFIG_TPL
 SPL_PAYLOAD := tpl/u-boot-with-tpl.bin

README

@@ -1681,14 +1681,7 @@ The following options need to be configured:
 		to generate and write the Backup GUID Partition Table.)
 		This occurs when the specified "partition name" on the
 		"fastboot flash" command line matches this value.
-		The default is "gpt" if undefined.
-
-		CONFIG_FASTBOOT_MBR_NAME
-		The fastboot "flash" command supports writing the downloaded
-		image to DOS MBR.
-		This occurs when the "partition name" specified on the
-		"fastboot flash" command line matches this value.
-		If not defined the default value "mbr" is used.
+		Default is GPT_ENTRY_NAME (currently "gpt") if undefined.
 
 - Journaling Flash filesystem support:
 		CONFIG_JFFS2_NAND, CONFIG_JFFS2_NAND_OFF, CONFIG_JFFS2_NAND_SIZE,
@@ -3516,6 +3509,21 @@ FIT uImage format:
 		CONFIG_SPL_INIT_MINIMAL
 		Arch init code should be built for a very small image
 
+		CONFIG_SPL_LIBCOMMON_SUPPORT
+		Support for common/libcommon.o in SPL binary
+
+		CONFIG_SPL_LIBDISK_SUPPORT
+		Support for disk/libdisk.o in SPL binary
+
+		CONFIG_SPL_I2C_SUPPORT
+		Support for drivers/i2c/libi2c.o in SPL binary
+
+		CONFIG_SPL_GPIO_SUPPORT
+		Support for drivers/gpio/libgpio.o in SPL binary
+
+		CONFIG_SPL_MMC_SUPPORT
+		Support for drivers/mmc/libmmc.o in SPL binary
+
 		CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR,
 		CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS,
 		Address and partition on the MMC to load U-Boot from
@@ -3539,6 +3547,12 @@ FIT uImage format:
 		Partition on the MMC to load U-Boot from when the MMC is being
 		used in fs mode
 
+		CONFIG_SPL_FAT_SUPPORT
+		Support for fs/fat/libfat.o in SPL binary
+
+		CONFIG_SPL_EXT_SUPPORT
+		Support for EXT filesystem in SPL binary
+
 		CONFIG_SPL_FS_LOAD_PAYLOAD_NAME
 		Filename to read to load U-Boot when reading from filesystem
 
@@ -3577,10 +3591,18 @@ FIT uImage format:
 		Support for a lightweight UBI (fastmap) scanner and
 		loader
 
+		CONFIG_SPL_MTD_SUPPORT
+		Support for the MTD subsystem within SPL.  Useful for
+		environment on NAND support within SPL.
+
 		CONFIG_SPL_NAND_RAW_ONLY
 		Support to boot only raw u-boot.bin images. Use this only
 		if you need to save space.
 
+		CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+		Set for the SPL on PPC mpc8xxx targets, support for
+		drivers/ddr/fsl/libddr.o in SPL binary.
+
 		CONFIG_SPL_COMMON_INIT_DDR
 		Set for common ddr init with serial presence detect in
 		SPL binary.
@@ -3616,9 +3638,29 @@ FIT uImage format:
 		Support for an OMAP3-specific set of functions to return the
 		ID and MFR of the first attached NAND chip, if present.
 
+		CONFIG_SPL_SERIAL_SUPPORT
+		Support for drivers/serial/libserial.o in SPL binary
+
+		CONFIG_SPL_SPI_FLASH_SUPPORT
+		Support for drivers/mtd/spi/libspi_flash.o in SPL binary
+
+		CONFIG_SPL_SPI_SUPPORT
+		Support for drivers/spi/libspi.o in SPL binary
+
 		CONFIG_SPL_RAM_DEVICE
 		Support for running image already present in ram, in SPL binary
 
+		CONFIG_SPL_LIBGENERIC_SUPPORT
+		Support for lib/libgeneric.o in SPL binary
+
+		CONFIG_SPL_ENV_SUPPORT
+		Support for the environment operating in SPL binary
+
+		CONFIG_SPL_NET_SUPPORT
+		Support for the net/libnet.o in SPL binary.
+		It conflicts with SPL env from storage medium specified by
+		CONFIG_ENV_IS_xxx but CONFIG_ENV_IS_NOWHERE
+
 		CONFIG_SPL_PAD_TO
 		Image offset to which the SPL should be padded before appending
 		the SPL payload. By default, this is defined as
@@ -4905,6 +4947,12 @@ The Freescale Layerscape Debug Server Support supports the loading of
 "Debug Server firmware" and triggering SP boot-rom.
 This firmware often needs to be loaded during U-Boot booting.
 
+- CONFIG_FSL_DEBUG_SERVER
+	Enable the Debug Server for Layerscape SoCs.
+
+- CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE
+	Define minimum DDR size required for debug server image
+
 - CONFIG_SYS_MC_RSV_MEM_ALIGN
 	Define alignment of reserved memory MC requires
 

arch/Kconfig

@@ -62,7 +62,6 @@ config SANDBOX
 	bool "Sandbox"
 	select SUPPORT_OF_CONTROL
 	select DM
-	select DM_KEYBOARD
 	select DM_SPI_FLASH
 	select DM_SERIAL
 	select DM_I2C
@@ -84,7 +83,6 @@ config X86
 	select HAVE_PRIVATE_LIBGCC
 	select SUPPORT_OF_CONTROL
 	select DM
-	select DM_KEYBOARD
 	select DM_SERIAL
 	select DM_GPIO
 	select DM_SPI

arch/arc/config.mk

@@ -31,15 +31,15 @@ CONFIG_MMU = 1
 endif
 
 ifdef CONFIG_CPU_ARC750D
-PLATFORM_CPPFLAGS += -mcpu=arc700
+PLATFORM_CPPFLAGS += -marc700
 endif
 
 ifdef CONFIG_CPU_ARC770D
-PLATFORM_CPPFLAGS += -mcpu=arc700 -mlock -mswape
+PLATFORM_CPPFLAGS += -marc700 -mlock -mswape
 endif
 
 ifdef CONFIG_CPU_ARCEM6
-PLATFORM_CPPFLAGS += -mcpu=arcem
+PLATFORM_CPPFLAGS += -marcem
 endif
 
 ifdef CONFIG_CPU_ARCHS34

arch/arc/include/asm/errno.h

@@ -0,0 +1 @@
+#include <asm-generic/errno.h>

arch/arm/Kconfig

@@ -164,7 +164,9 @@ config KIRKWOOD
 	select CPU_ARM926EJS
 
 config ARCH_MVEBU
-	bool "Marvell MVEBU family (Armada XP/375/38x/3700/7K/8K)"
+	bool "Marvell MVEBU family (Armada XP/375/38x)"
+	select CPU_V7
+	select SUPPORT_SPL
 	select OF_CONTROL
 	select OF_SEPARATE
 	select DM
@@ -172,6 +174,10 @@ config ARCH_MVEBU
 	select DM_SERIAL
 	select DM_SPI
 	select DM_SPI_FLASH
+	select SPL_DM
+	select SPL_DM_SEQ_ALIAS
+	select SPL_OF_CONTROL
+	select SPL_SIMPLE_BUS
 
 config TARGET_DEVKIT3250
 	bool "Support devkit3250"
@@ -335,6 +341,38 @@ config TARGET_BRPPT1
 	select CPU_V7
 	select SUPPORT_SPL
 
+config TARGET_CM_T335
+	bool "Support cm_t335"
+	select CPU_V7
+	select SUPPORT_SPL
+	select DM
+	select DM_SERIAL
+	select DM_GPIO
+
+config TARGET_PEPPER
+	bool "Support pepper"
+	select CPU_V7
+	select SUPPORT_SPL
+	select DM
+	select DM_SERIAL
+	select DM_GPIO
+
+config TARGET_AM335X_IGEP0033
+	bool "Support am335x_igep0033"
+	select CPU_V7
+	select SUPPORT_SPL
+	select DM
+	select DM_SERIAL
+	select DM_GPIO
+
+config TARGET_PCM051
+	bool "Support pcm051"
+	select CPU_V7
+	select SUPPORT_SPL
+	select DM
+	select DM_SERIAL
+	select DM_GPIO
+
 config TARGET_DRACO
 	bool "Support draco"
 	select CPU_V7
@@ -383,6 +421,62 @@ config TARGET_RUT
 	select DM_SERIAL
 	select DM_GPIO
 
+config TARGET_PENGWYN
+	bool "Support pengwyn"
+	select CPU_V7
+	select SUPPORT_SPL
+	select DM
+	select DM_SERIAL
+	select DM_GPIO
+
+config TARGET_AM335X_BALTOS
+	bool "Support am335x_baltos"
+	select CPU_V7
+	select SUPPORT_SPL
+	select DM
+	select DM_SERIAL
+	select DM_GPIO
+
+config TARGET_AM335X_EVM
+	bool "Support am335x_evm"
+	select CPU_V7
+	select SUPPORT_SPL
+	select DM
+	select DM_SERIAL
+	select DM_GPIO
+	select TI_I2C_BOARD_DETECT
+
+config TARGET_AM335X_SHC
+	bool "Support am335x based shc board from bosch"
+	select CPU_V7
+	select SUPPORT_SPL
+	select DM
+	select DM_SERIAL
+	select DM_GPIO
+
+config TARGET_AM335X_SL50
+	bool "Support am335x_sl50"
+	select CPU_V7
+	select SUPPORT_SPL
+	select DM
+	select DM_GPIO
+	select DM_SERIAL
+
+config TARGET_BAV335X
+	bool "Support bav335x"
+	select CPU_V7
+	select SUPPORT_SPL
+	select DM
+	select DM_SERIAL
+	help
+	  The BAV335x OEM Network Processor integrates all the functions of an
+	  embedded network computer in a small, easy to use SODIMM module which
+	  incorporates the popular Texas Instruments Sitara 32bit ARM Coretex-A8
+	  processor, with fast DDR3 512MB SDRAM, 4GB of embedded MMC and a Gigabit
+	  ethernet with simple connection to external connectors.
+
+	  For more information, visit: http://birdland.com/oem
+
 config TARGET_TI814X_EVM
 	bool "Support ti814x_evm"
 	select CPU_V7
@@ -512,17 +606,6 @@ config AM43XX
 	  protocols, dual camera support, optional 3D graphics
 	  and an optional customer programmable secure boot.
 
-config AM33XX
-	bool "AM33XX SoC"
-	select CPU_V7
-	select SUPPORT_SPL
-	help
-	  Support for AM335x SOC from Texas Instruments.
-	  The AM335x high performance SOC features a Cortex-A8
-	  ARM core, a dual core PRU-ICSS for industrial Ethernet
-	  protocols, optional 3D graphics and an optional customer
-	  programmable secure boot.
-
 config ARCH_RMOBILE
 	bool "Renesas ARM SoCs"
 	select DM
@@ -705,7 +788,6 @@ config TARGET_HIKEY
 
 config TARGET_LS1012AQDS
 	bool "Support ls1012aqds"
-	select ARCH_LS1012A
 	select ARM64
 	help
 	  Support for Freescale LS1012AQDS platform.
@@ -715,7 +797,6 @@ config TARGET_LS1012AQDS
 
 config TARGET_LS1012ARDB
 	bool "Support ls1012ardb"
-	select ARCH_LS1012A
 	select ARM64
 	help
 	  Support for Freescale LS1012ARDB platform.
@@ -725,7 +806,6 @@ config TARGET_LS1012ARDB
 
 config TARGET_LS1012AFRDM
 	bool "Support ls1012afrdm"
-	select ARCH_LS1012A
 	select ARM64
 	help
 	  Support for Freescale LS1012AFRDM platform.
@@ -737,21 +817,16 @@ config TARGET_LS1021AQDS
 	bool "Support ls1021aqds"
 	select CPU_V7
 	select SUPPORT_SPL
-	select ARCH_LS1021A
 	select ARCH_SUPPORT_PSCI
-	select LS1_DEEP_SLEEP
 
 config TARGET_LS1021ATWR
 	bool "Support ls1021atwr"
 	select CPU_V7
 	select SUPPORT_SPL
-	select ARCH_LS1021A
 	select ARCH_SUPPORT_PSCI
-	select LS1_DEEP_SLEEP
 
 config TARGET_LS1043AQDS
 	bool "Support ls1043aqds"
-	select ARCH_LS1043A
 	select ARM64
 	select ARMV8_MULTIENTRY
 	select SUPPORT_SPL
@@ -760,39 +835,12 @@ config TARGET_LS1043AQDS
 
 config TARGET_LS1043ARDB
 	bool "Support ls1043ardb"
-	select ARCH_LS1043A
 	select ARM64
 	select ARMV8_MULTIENTRY
 	select SUPPORT_SPL
 	help
 	  Support for Freescale LS1043ARDB platform.
 
-config TARGET_LS1046AQDS
-	bool "Support ls1046aqds"
-	select ARCH_LS1046A
-	select ARM64
-	select ARMV8_MULTIENTRY
-	select SUPPORT_SPL
-	select DM_SPI_FLASH if DM_SPI
-	help
-	  Support for Freescale LS1046AQDS platform.
-	  The LS1046A Development System (QDS) is a high-performance
-	  development platform that supports the QorIQ LS1046A
-	  Layerscape Architecture processor.
-
-config TARGET_LS1046ARDB
-	bool "Support ls1046ardb"
-	select ARCH_LS1046A
-	select ARM64
-	select ARMV8_MULTIENTRY
-	select SUPPORT_SPL
-	select DM_SPI_FLASH if DM_SPI
-	help
-	  Support for Freescale LS1046ARDB platform.
-	  The LS1046A Reference Design Board (RDB) is a high-performance
-	  development platform that supports the QorIQ LS1046A
-	  Layerscape Architecture processor.
-
 config TARGET_H2200
 	bool "Support h2200"
 	select CPU_PXA
@@ -807,24 +855,18 @@ config TARGET_COLIBRI_PXA270
 
 config ARCH_UNIPHIER
 	bool "Socionext UniPhier SoCs"
-	select BLK
 	select CLK_UNIPHIER
+	select SUPPORT_SPL
+	select SPL
+	select OF_CONTROL
+	select SPL_OF_CONTROL
+	select OF_LIBFDT
 	select DM
+	select SPL_DM
 	select DM_GPIO
+	select DM_SERIAL
 	select DM_I2C
 	select DM_MMC
-	select DM_SERIAL
-	select DM_USB
-	select OF_CONTROL
-	select OF_LIBFDT
-	select PINCTRL
-	select SPL
-	select SPL_DM
-	select SPL_LIBCOMMON_SUPPORT
-	select SPL_LIBGENERIC_SUPPORT
-	select SPL_OF_CONTROL
-	select SPL_PINCTRL
-	select SUPPORT_SPL
 	help
 	  Support for UniPhier SoC family developed by Socionext Inc.
 	  (formerly, System LSI Business Division of Panasonic Corporation)
@@ -850,9 +892,6 @@ config ARCH_ROCKCHIP
 	select DM_SERIAL
 	select DM_SPI
 	select DM_SPI_FLASH
-	select DM_USB if USB
-	select DM_PWM
-	select DM_REGULATOR
 
 config TARGET_THUNDERX_88XX
 	bool "Support ThunderX 88xx"
@@ -880,8 +919,6 @@ source "arch/arm/mach-kirkwood/Kconfig"
 
 source "arch/arm/mach-mvebu/Kconfig"
 
-source "arch/arm/cpu/armv7/ls102xa/Kconfig"
-
 source "arch/arm/cpu/armv7/mx7/Kconfig"
 
 source "arch/arm/cpu/armv7/mx6/Kconfig"
@@ -890,8 +927,6 @@ source "arch/arm/cpu/armv7/mx5/Kconfig"
 
 source "arch/arm/cpu/armv7/omap-common/Kconfig"
 
-source "arch/arm/cpu/armv8/fsl-layerscape/Kconfig"
-
 source "arch/arm/mach-orion5x/Kconfig"
 
 source "arch/arm/mach-rmobile/Kconfig"
@@ -949,9 +984,7 @@ source "board/freescale/ls2080ardb/Kconfig"
 source "board/freescale/ls1021aqds/Kconfig"
 source "board/freescale/ls1043aqds/Kconfig"
 source "board/freescale/ls1021atwr/Kconfig"
-source "board/freescale/ls1046aqds/Kconfig"
 source "board/freescale/ls1043ardb/Kconfig"
-source "board/freescale/ls1046ardb/Kconfig"
 source "board/freescale/ls1012aqds/Kconfig"
 source "board/freescale/ls1012ardb/Kconfig"
 source "board/freescale/ls1012afrdm/Kconfig"

arch/arm/cpu/arm1136/mx35/generic.c

@@ -10,7 +10,7 @@
 #include <common.h>
 #include <div64.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/clock.h>

arch/arm/cpu/arm1136/mx35/mx35_sdram.c

@@ -5,7 +5,7 @@
  */
 
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/imx-regs.h>
 #include <linux/types.h>
 #include <asm/arch/sys_proto.h>

arch/arm/cpu/arm920t/imx/timer.c

@@ -78,7 +78,11 @@ unsigned long long get_ticks(void)
  */
 ulong get_tbclk (void)
 {
-	return CONFIG_SYS_HZ;
+	ulong tbclk;
+
+	tbclk = CONFIG_SYS_HZ;
+
+	return tbclk;
 }
 
 /*

arch/arm/cpu/arm926ejs/mxs/clock.c

@@ -11,7 +11,7 @@
  */
 
 #include <common.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/imx-regs.h>

arch/arm/cpu/arm926ejs/mxs/iomux.c

@@ -8,7 +8,7 @@
  */
 
 #include <common.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/iomux.h>

arch/arm/cpu/arm926ejs/mxs/mxs.c

@@ -11,7 +11,7 @@
  */
 
 #include <common.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/imx-common/dma.h>

arch/arm/cpu/arm926ejs/spear/timer.c

@@ -37,7 +37,7 @@ int timer_init(void)
 	writel(MISC_PRSC_CFG, &misc_regs_p->prsc1_clk_cfg);
 	synth = MISC_GPT3SYNTH;
 #else
-# error Incorrect config. Can only be SPEAR{600|300|310|320}
+# error Incorrect config. Can only be spear{600|300|310|320}
 #endif
 
 	writel(readl(&misc_regs_p->periph_clk_cfg) | synth,

arch/arm/cpu/armv7/am33xx/Kconfig

@@ -1,99 +1,4 @@
-if AM33XX
-
-choice
-	prompt "AM33xx board select"
-	optional
-
-config TARGET_AM335X_EVM
-	bool "Support am335x_evm"
-	select DM
-	select DM_SERIAL
-	select DM_GPIO
-	select TI_I2C_BOARD_DETECT
-	help
-	  This option specifies support for the AM335x
-	  GP and HS EVM development platforms. The AM335x
-	  GP EVM is a standalone test, development, and
-	  evaluation module system that enables developers
-	  to write software and develop hardware around
-	  an AM335x processor subsystem.
-
-config TARGET_AM335X_BALTOS
-	bool "Support am335x_baltos"
-	select DM
-	select DM_SERIAL
-	select DM_GPIO
-
-config TARGET_AM335X_IGEP0033
-	bool "Support am335x_igep0033"
-	select DM
-	select DM_SERIAL
-	select DM_GPIO
-
-config TARGET_AM335X_SHC
-	bool "Support am335x based shc board from bosch"
-	select DM
-	select DM_SERIAL
-	select DM_GPIO
-
-config TARGET_AM335X_SL50
-	bool "Support am335x_sl50"
-	select DM
-	select DM_SERIAL
-	select DM_GPIO
-
-config TARGET_BAV335X
-	bool "Support bav335x"
-	select DM
-	select DM_SERIAL
-	help
-	  The BAV335x OEM Network Processor integrates all the functions of an
-	  embedded network computer in a small, easy to use SODIMM module which
-	  incorporates the popular Texas Instruments Sitara 32bit ARM Coretex-A8
-	  processor, with fast DDR3 512MB SDRAM, 4GB of embedded MMC and a Gigabit
-	  ethernet with simple connection to external connectors.
-
-	  For more information, visit: http://birdland.com/oem
-
-config TARGET_CM_T335
-	bool "Support cm_t335"
-	select DM
-	select DM_SERIAL
-	select DM_GPIO
-
-config TARGET_PCM051
-	bool "Support pcm051"
-	select DM
-	select DM_SERIAL
-	select DM_GPIO
-
-config TARGET_PENGWYN
-	bool "Support pengwyn"
-	select DM
-	select DM_SERIAL
-	select DM_GPIO
-
-config TARGET_PEPPER
-	bool "Support pepper"
-	select DM
-	select DM_SERIAL
-	select DM_GPIO
-
-endchoice
-
-endif
-
 if AM43XX
-
-config SPL_EXT_SUPPORT
-	default y
-
-config SPL_GPIO_SUPPORT
-	default y
-
-config SPL_I2C_SUPPORT
-	default y
-
 config TARGET_AM43XX_EVM
 	bool "Support am43xx_evm"
 	select TI_I2C_BOARD_DETECT
@@ -104,9 +9,7 @@ config TARGET_AM43XX_EVM
 	  evaluation module system that enables developers
 	  to write software and develop hardware around
 	  an AM43xx processor subsystem.
-endif
 
-if AM43XX || AM33XX
 config ISW_ENTRY_ADDR
 	hex "Address in memory or XIP flash of bootloader entry point"
 	help

arch/arm/cpu/armv7/am33xx/board.c

@@ -28,7 +28,7 @@
 #include <i2c.h>
 #include <miiphy.h>
 #include <cpsw.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <linux/compiler.h>
 #include <linux/usb/ch9.h>
 #include <linux/usb/gadget.h>

arch/arm/cpu/armv7/am33xx/config.mk

@@ -12,32 +12,16 @@ ifeq ($(CONFIG_TI_SECURE_DEVICE),y)
 # For booting from SPI use
 # u-boot-spl_HS_SPI_X-LOADER to program flash
 #
-# On AM43XX:
-#
-# For booting spl from all other media use
-# u-boot-spl_HS_ISSW
-#
-# On AM33XX:
-#
-# For booting spl from NAND flash use
-# u-boot-spl_HS_X-LOADER
-#
-# For booting spl from SD/MMC/eMMC media use
-# u-boot-spl_HS_MLO
-#
-# For booting spl over UART, USB, or Ethernet use
-# u-boot-spl_HS_2ND
+# For booting spl from all other  media
+# use u-boot-spl_HS_ISSW
 #
 # Refer to README.ti-secure for more info
 #
 ALL-y	+= u-boot-spl_HS_ISSW
-ALL-y += u-boot-spl_HS_SPI_X-LOADER
-ALL-y += u-boot-spl_HS_X-LOADER
-ALL-y += u-boot-spl_HS_MLO
-ALL-y += u-boot-spl_HS_2ND
+ALL-$(CONFIG_SPL_SPI_SUPPORT) += u-boot-spl_HS_SPI_X-LOADER
 else
 ALL-y	+= MLO
-ALL-y += MLO.byteswap
+ALL-$(CONFIG_SPL_SPI_SUPPORT) += MLO.byteswap
 endif
 else
 ifeq ($(CONFIG_TI_SECURE_DEVICE),y)

arch/arm/cpu/armv7/am33xx/sys_info.c

@@ -65,7 +65,9 @@ u32 get_device_type(void)
  */
 u32 get_sysboot_value(void)
 {
-	return readl(&cstat->statusreg) & SYSBOOT_MASK;
+	int mode;
+	mode = readl(&cstat->statusreg) & (SYSBOOT_MASK);
+	return mode;
 }
 
 #ifdef CONFIG_DISPLAY_CPUINFO

arch/arm/cpu/armv7/bcm235xx/clk-bcm235xx.c

@@ -12,7 +12,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/sysmap.h>
 #include <asm/kona-common/clk.h>
 #include "clk-core.h"

arch/arm/cpu/armv7/bcm235xx/clk-bsc.c

@@ -6,7 +6,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/sysmap.h>
 #include <asm/kona-common/clk.h>
 #include "clk-core.h"

arch/arm/cpu/armv7/bcm235xx/clk-core.c

@@ -12,7 +12,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <bitfield.h>
 #include <asm/arch/sysmap.h>
 #include <asm/kona-common/clk.h>

arch/arm/cpu/armv7/bcm235xx/clk-eth.c

@@ -6,7 +6,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/sysmap.h>
 #include <asm/kona-common/clk.h>
 #include "clk-core.h"

arch/arm/cpu/armv7/bcm235xx/clk-sdio.c

@@ -6,7 +6,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/sysmap.h>
 #include <asm/kona-common/clk.h>
 #include "clk-core.h"

arch/arm/cpu/armv7/bcm235xx/clk-usb-otg.c

@@ -5,7 +5,7 @@
  */
 
 #include <common.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/sysmap.h>
 #include "clk-core.h"
 

arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c

@@ -12,7 +12,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/sysmap.h>
 #include <asm/kona-common/clk.h>
 #include "clk-core.h"

arch/arm/cpu/armv7/bcm281xx/clk-bsc.c

@@ -6,7 +6,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/sysmap.h>
 #include <asm/kona-common/clk.h>
 #include "clk-core.h"

arch/arm/cpu/armv7/bcm281xx/clk-core.c

@@ -12,7 +12,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <bitfield.h>
 #include <asm/arch/sysmap.h>
 #include <asm/kona-common/clk.h>

arch/arm/cpu/armv7/bcm281xx/clk-eth.c

@@ -6,7 +6,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/sysmap.h>
 #include <asm/kona-common/clk.h>
 #include "clk-core.h"

arch/arm/cpu/armv7/bcm281xx/clk-sdio.c

@@ -6,7 +6,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/sysmap.h>
 #include <asm/kona-common/clk.h>
 #include "clk-core.h"

arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c

@@ -5,7 +5,7 @@
  */
 
 #include <common.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/sysmap.h>
 #include "clk-core.h"
 

arch/arm/cpu/armv7/ls102xa/Kconfig

@@ -1,6 +0,0 @@
-config ARCH_LS1021A
-	bool "Freescale Layerscape LS1021A SoC"
-	select SYS_FSL_ERRATUM_A010315
-
-config LS1_DEEP_SLEEP
-	bool "Freescale Layerscape 1 deep sleep"

arch/arm/cpu/armv7/ls102xa/Makefile

@@ -16,5 +16,5 @@ obj-$(CONFIG_SYS_HAS_SERDES) += fsl_ls1_serdes.o ls102xa_serdes.o
 obj-$(CONFIG_SPL) += spl.o
 
 ifdef CONFIG_ARMV7_PSCI
-obj-y  += psci.o ls102xa_psci.o
+obj-y  += psci.o
 endif

arch/arm/cpu/armv7/ls102xa/fsl_epu.c

@@ -9,163 +9,6 @@
 
 #include "fsl_epu.h"
 
-struct fsm_reg_vals epu_default_val[] = {
-	/* EPGCR (Event Processor Global Control Register) */
-	{EPGCR, 0},
-	/* EPECR (Event Processor Event Control Registers) */
-	{EPECR0 + EPECR_STRIDE * 0, 0},
-	{EPECR0 + EPECR_STRIDE * 1, 0},
-	{EPECR0 + EPECR_STRIDE * 2, 0xF0004004},
-	{EPECR0 + EPECR_STRIDE * 3, 0x80000084},
-	{EPECR0 + EPECR_STRIDE * 4, 0x20000084},
-	{EPECR0 + EPECR_STRIDE * 5, 0x08000004},
-	{EPECR0 + EPECR_STRIDE * 6, 0x80000084},
-	{EPECR0 + EPECR_STRIDE * 7, 0x80000084},
-	{EPECR0 + EPECR_STRIDE * 8, 0x60000084},
-	{EPECR0 + EPECR_STRIDE * 9, 0x08000084},
-	{EPECR0 + EPECR_STRIDE * 10, 0x42000084},
-	{EPECR0 + EPECR_STRIDE * 11, 0x90000084},
-	{EPECR0 + EPECR_STRIDE * 12, 0x80000084},
-	{EPECR0 + EPECR_STRIDE * 13, 0x08000084},
-	{EPECR0 + EPECR_STRIDE * 14, 0x02000084},
-	{EPECR0 + EPECR_STRIDE * 15, 0x00000004},
-	/*
-	 * EPEVTCR (Event Processor EVT Pin Control Registers)
-	 * SCU8 triger EVT2, and SCU11 triger EVT9
-	 */
-	{EPEVTCR0 + EPEVTCR_STRIDE * 0, 0},
-	{EPEVTCR0 + EPEVTCR_STRIDE * 1, 0},
-	{EPEVTCR0 + EPEVTCR_STRIDE * 2, 0x80000001},
-	{EPEVTCR0 + EPEVTCR_STRIDE * 3, 0},
-	{EPEVTCR0 + EPEVTCR_STRIDE * 4, 0},
-	{EPEVTCR0 + EPEVTCR_STRIDE * 5, 0},
-	{EPEVTCR0 + EPEVTCR_STRIDE * 6, 0},
-	{EPEVTCR0 + EPEVTCR_STRIDE * 7, 0},
-	{EPEVTCR0 + EPEVTCR_STRIDE * 8, 0},
-	{EPEVTCR0 + EPEVTCR_STRIDE * 9, 0xB0000001},
-	/* EPCMPR (Event Processor Counter Compare Registers) */
-	{EPCMPR0 + EPCMPR_STRIDE * 0, 0},
-	{EPCMPR0 + EPCMPR_STRIDE * 1, 0},
-	{EPCMPR0 + EPCMPR_STRIDE * 2, 0x000000FF},
-	{EPCMPR0 + EPCMPR_STRIDE * 3, 0},
-	{EPCMPR0 + EPCMPR_STRIDE * 4, 0x000000FF},
-	{EPCMPR0 + EPCMPR_STRIDE * 5, 0x00000020},
-	{EPCMPR0 + EPCMPR_STRIDE * 6, 0},
-	{EPCMPR0 + EPCMPR_STRIDE * 7, 0},
-	{EPCMPR0 + EPCMPR_STRIDE * 8, 0x000000FF},
-	{EPCMPR0 + EPCMPR_STRIDE * 9, 0x000000FF},
-	{EPCMPR0 + EPCMPR_STRIDE * 10, 0x000000FF},
-	{EPCMPR0 + EPCMPR_STRIDE * 11, 0x000000FF},
-	{EPCMPR0 + EPCMPR_STRIDE * 12, 0x000000FF},
-	{EPCMPR0 + EPCMPR_STRIDE * 13, 0},
-	{EPCMPR0 + EPCMPR_STRIDE * 14, 0x000000FF},
-	{EPCMPR0 + EPCMPR_STRIDE * 15, 0x000000FF},
-	/* EPCCR (Event Processor Counter Control Registers) */
-	{EPCCR0 + EPCCR_STRIDE * 0, 0},
-	{EPCCR0 + EPCCR_STRIDE * 1, 0},
-	{EPCCR0 + EPCCR_STRIDE * 2, 0x92840000},
-	{EPCCR0 + EPCCR_STRIDE * 3, 0},
-	{EPCCR0 + EPCCR_STRIDE * 4, 0x92840000},
-	{EPCCR0 + EPCCR_STRIDE * 5, 0x92840000},
-	{EPCCR0 + EPCCR_STRIDE * 6, 0},
-	{EPCCR0 + EPCCR_STRIDE * 7, 0},
-	{EPCCR0 + EPCCR_STRIDE * 8, 0x92840000},
-	{EPCCR0 + EPCCR_STRIDE * 9, 0x92840000},
-	{EPCCR0 + EPCCR_STRIDE * 10, 0x92840000},
-	{EPCCR0 + EPCCR_STRIDE * 11, 0x92840000},
-	{EPCCR0 + EPCCR_STRIDE * 12, 0x92840000},
-	{EPCCR0 + EPCCR_STRIDE * 13, 0},
-	{EPCCR0 + EPCCR_STRIDE * 14, 0x92840000},
-	{EPCCR0 + EPCCR_STRIDE * 15, 0x92840000},
-	/* EPSMCR (Event Processor SCU Mux Control Registers) */
-	{EPSMCR0 + EPSMCR_STRIDE * 0, 0},
-	{EPSMCR0 + EPSMCR_STRIDE * 1, 0},
-	{EPSMCR0 + EPSMCR_STRIDE * 2, 0x6C700000},
-	{EPSMCR0 + EPSMCR_STRIDE * 3, 0x2F000000},
-	{EPSMCR0 + EPSMCR_STRIDE * 4, 0x002F0000},
-	{EPSMCR0 + EPSMCR_STRIDE * 5, 0x00002E00},
-	{EPSMCR0 + EPSMCR_STRIDE * 6, 0x7C000000},
-	{EPSMCR0 + EPSMCR_STRIDE * 7, 0x30000000},
-	{EPSMCR0 + EPSMCR_STRIDE * 8, 0x64300000},
-	{EPSMCR0 + EPSMCR_STRIDE * 9, 0x00003000},
-	{EPSMCR0 + EPSMCR_STRIDE * 10, 0x65000030},
-	{EPSMCR0 + EPSMCR_STRIDE * 11, 0x31740000},
-	{EPSMCR0 + EPSMCR_STRIDE * 12, 0x7F000000},
-	{EPSMCR0 + EPSMCR_STRIDE * 13, 0x00003100},
-	{EPSMCR0 + EPSMCR_STRIDE * 14, 0x00000031},
-	{EPSMCR0 + EPSMCR_STRIDE * 15, 0x76000000},
-	/* EPACR (Event Processor Action Control Registers) */
-	{EPACR0 + EPACR_STRIDE * 0, 0},
-	{EPACR0 + EPACR_STRIDE * 1, 0},
-	{EPACR0 + EPACR_STRIDE * 2, 0},
-	{EPACR0 + EPACR_STRIDE * 3, 0x00000080},
-	{EPACR0 + EPACR_STRIDE * 4, 0},
-	{EPACR0 + EPACR_STRIDE * 5, 0x00000040},
-	{EPACR0 + EPACR_STRIDE * 6, 0},
-	{EPACR0 + EPACR_STRIDE * 7, 0},
-	{EPACR0 + EPACR_STRIDE * 8, 0},
-	{EPACR0 + EPACR_STRIDE * 9, 0x0000001C},
-	{EPACR0 + EPACR_STRIDE * 10, 0x00000020},
-	{EPACR0 + EPACR_STRIDE * 11, 0},
-	{EPACR0 + EPACR_STRIDE * 12, 0x00000003},
-	{EPACR0 + EPACR_STRIDE * 13, 0x06000000},
-	{EPACR0 + EPACR_STRIDE * 14, 0x04000000},
-	{EPACR0 + EPACR_STRIDE * 15, 0x02000000},
-	/* EPIMCR (Event Processor Input Mux Control Registers) */
-	{EPIMCR0 + EPIMCR_STRIDE * 0, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 1, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 2, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 3, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 4, 0x44000000},
-	{EPIMCR0 + EPIMCR_STRIDE * 5, 0x40000000},
-	{EPIMCR0 + EPIMCR_STRIDE * 6, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 7, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 8, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 9, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 10, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 11, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 12, 0x44000000},
-	{EPIMCR0 + EPIMCR_STRIDE * 13, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 14, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 15, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 16, 0x6A000000},
-	{EPIMCR0 + EPIMCR_STRIDE * 17, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 18, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 19, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 20, 0x48000000},
-	{EPIMCR0 + EPIMCR_STRIDE * 21, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 22, 0x6C000000},
-	{EPIMCR0 + EPIMCR_STRIDE * 23, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 24, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 25, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 26, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 27, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 28, 0x76000000},
-	{EPIMCR0 + EPIMCR_STRIDE * 29, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 30, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 31, 0x76000000},
-	/* EPXTRIGCR (Event Processor Crosstrigger Control Register) */
-	{EPXTRIGCR, 0x0000FFDF},
-	/* end */
-	{FSM_END_FLAG, 0},
-};
-
-/**
- * fsl_epu_setup - Setup EPU registers to default values
- */
-void fsl_epu_setup(void *epu_base)
-{
-	struct fsm_reg_vals *data = epu_default_val;
-
-	if (!epu_base || !data)
-		return;
-
-	while (data->offset != FSM_END_FLAG) {
-		out_be32(epu_base + data->offset, data->value);
-		data++;
-	}
-}
-
 /**
  * fsl_epu_clean - Clear EPU registers
  */

arch/arm/cpu/armv7/ls102xa/fsl_epu.h

@@ -63,14 +63,6 @@
 #define EPCTR31		0xA7C
 #define EPCTR_STRIDE	FSL_STRIDE_4B
 
-#define FSM_END_FLAG	0xFFFFFFFFUL
-
-struct fsm_reg_vals {
-	u32 offset;
-	u32 value;
-};
-
-void fsl_epu_setup(void *epu_base);
 void fsl_epu_clean(void *epu_base);
 
 #endif

arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c

@@ -7,7 +7,7 @@
 #include <common.h>
 #include <asm/arch/fsl_serdes.h>
 #include <asm/arch/immap_ls102xa.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/io.h>
 #include "fsl_ls1_serdes.h"
 
@@ -23,15 +23,9 @@ int is_serdes_configured(enum srds_prtcl device)
 	u64 ret = 0;
 
 #ifdef CONFIG_SYS_FSL_SRDS_1
-	if (!(serdes1_prtcl_map & (1ULL << NONE)))
-		fsl_serdes_init();
-
 	ret |= (1ULL << device) & serdes1_prtcl_map;
 #endif
 #ifdef CONFIG_SYS_FSL_SRDS_2
-	if (!(serdes2_prtcl_map & (1ULL << NONE)))
-		fsl_serdes_init();
-
 	ret |= (1ULL << device) & serdes2_prtcl_map;
 #endif
 
@@ -93,24 +87,19 @@ u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift)
 		serdes_prtcl_map |= (1ULL << lane_prtcl);
 	}
 
-	/* Set the first bit to indicate serdes has been initialized */
-	serdes_prtcl_map |= (1ULL << NONE);
-
 	return serdes_prtcl_map;
 }
 
 void fsl_serdes_init(void)
 {
 #ifdef CONFIG_SYS_FSL_SRDS_1
-	if (!(serdes1_prtcl_map & (1ULL << NONE)))
-		serdes1_prtcl_map = serdes_init(FSL_SRDS_1,
+	serdes1_prtcl_map = serdes_init(FSL_SRDS_1,
 					CONFIG_SYS_FSL_SERDES_ADDR,
 					RCWSR4_SRDS1_PRTCL_MASK,
 					RCWSR4_SRDS1_PRTCL_SHIFT);
 #endif
 #ifdef CONFIG_SYS_FSL_SRDS_2
-	if (!(serdes2_prtcl_map & (1ULL << NONE)))
-		serdes2_prtcl_map = serdes_init(FSL_SRDS_2,
+	serdes2_prtcl_map = serdes_init(FSL_SRDS_2,
 					CONFIG_SYS_FSL_SERDES_ADDR +
 					FSL_SRDS_2 * 0x1000,
 					RCWSR4_SRDS2_PRTCL_MASK,

arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c

@@ -1,236 +0,0 @@
-/*
- * Copyright 2016 Freescale Semiconductor, Inc.
- * Author: Hongbo Zhang <hongbo.zhang@nxp.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- * This file implements LS102X platform PSCI SYSTEM-SUSPEND function
- */
-
-#include <config.h>
-#include <asm/io.h>
-#include <asm/psci.h>
-#include <asm/arch/immap_ls102xa.h>
-#include <fsl_immap.h>
-#include "fsl_epu.h"
-
-#define __secure __attribute__((section("._secure.text")))
-
-#define CCSR_GICD_CTLR			0x1000
-#define CCSR_GICC_CTLR			0x2000
-#define DCSR_RCPM_CG1CR0		0x31c
-#define DCSR_RCPM_CSTTACR0		0xb00
-#define DCFG_CRSTSR_WDRFR		0x8
-#define DDR_RESV_LEN			128
-
-#ifdef CONFIG_LS1_DEEP_SLEEP
-/*
- * DDR controller initialization training breaks the first 128 bytes of DDR,
- * save them so that the bootloader can restore them while resuming.
- */
-static void __secure ls1_save_ddr_head(void)
-{
-	const char *src = (const char *)CONFIG_SYS_SDRAM_BASE;
-	char *dest = (char *)(OCRAM_BASE_S_ADDR + OCRAM_S_SIZE - DDR_RESV_LEN);
-	struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
-	int i;
-
-	out_le32(&scfg->sparecr[2], dest);
-
-	for (i = 0; i < DDR_RESV_LEN; i++)
-		*dest++ = *src++;
-}
-
-static void __secure ls1_fsm_setup(void)
-{
-	void *dcsr_epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
-	void *dcsr_rcpm_base = (void *)SYS_FSL_DCSR_RCPM_ADDR;
-
-	out_be32(dcsr_rcpm_base + DCSR_RCPM_CSTTACR0, 0x00001001);
-	out_be32(dcsr_rcpm_base + DCSR_RCPM_CG1CR0, 0x00000001);
-
-	fsl_epu_setup((void *)dcsr_epu_base);
-
-	/* Pull MCKE signal low before enabling deep sleep signal in FPGA */
-	out_be32(dcsr_epu_base + EPECR0, 0x5);
-	out_be32(dcsr_epu_base + EPSMCR15, 0x76300000);
-}
-
-static void __secure ls1_deepsleep_irq_cfg(void)
-{
-	struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
-	struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR;
-	u32 ippdexpcr0, ippdexpcr1, pmcintecr = 0;
-
-	/* Mask interrupts from GIC */
-	out_be32(&rcpm->nfiqoutr, 0x0ffffffff);
-	out_be32(&rcpm->nirqoutr, 0x0ffffffff);
-	/* Mask deep sleep wake-up interrupts while entering deep sleep */
-	out_be32(&rcpm->dsimskr, 0x0ffffffff);
-
-	ippdexpcr0 = in_be32(&rcpm->ippdexpcr0);
-	/*
-	 * Workaround: There is bug of register ippdexpcr1, when read it always
-	 * returns zero, so its value is saved to a scrachpad register to be
-	 * read, that is why we don't read it from register ippdexpcr1 itself.
-	 */
-	ippdexpcr1 = in_le32(&scfg->sparecr[7]);
-
-	if (ippdexpcr0 & RCPM_IPPDEXPCR0_ETSEC)
-		pmcintecr |= SCFG_PMCINTECR_ETSECRXG0 |
-			     SCFG_PMCINTECR_ETSECRXG1 |
-			     SCFG_PMCINTECR_ETSECERRG0 |
-			     SCFG_PMCINTECR_ETSECERRG1;
-
-	if (ippdexpcr0 & RCPM_IPPDEXPCR0_GPIO)
-		pmcintecr |= SCFG_PMCINTECR_GPIO;
-
-	if (ippdexpcr1 & RCPM_IPPDEXPCR1_LPUART)
-		pmcintecr |= SCFG_PMCINTECR_LPUART;
-
-	if (ippdexpcr1 & RCPM_IPPDEXPCR1_FLEXTIMER)
-		pmcintecr |= SCFG_PMCINTECR_FTM;
-
-	/* Always set external IRQ pins as wakeup source */
-	pmcintecr |= SCFG_PMCINTECR_IRQ0 | SCFG_PMCINTECR_IRQ1;
-
-	out_be32(&scfg->pmcintlecr, 0);
-	/* Clear PMC interrupt status */
-	out_be32(&scfg->pmcintsr, 0xffffffff);
-	/* Enable wakeup interrupt during deep sleep */
-	out_be32(&scfg->pmcintecr, pmcintecr);
-}
-
-static void __secure ls1_delay(unsigned int loop)
-{
-	while (loop--) {
-		int i = 1000;
-		while (i--)
-			;
-	}
-}
-
-static void __secure ls1_start_fsm(void)
-{
-	void *dcsr_epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
-	void *ccsr_gic_base = (void *)SYS_FSL_GIC_ADDR;
-	struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
-	struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
-
-	/* Set HRSTCR */
-	setbits_be32(&scfg->hrstcr, 0x80000000);
-
-	/* Place DDR controller in self refresh mode */
-	setbits_be32(&ddr->sdram_cfg_2, 0x80000000);
-
-	ls1_delay(2000);
-
-	/* Set EVT4_B to lock the signal MCKE down */
-	out_be32(dcsr_epu_base + EPECR0, 0x0);
-
-	ls1_delay(2000);
-
-	out_be32(ccsr_gic_base + CCSR_GICD_CTLR, 0x0);
-	out_be32(ccsr_gic_base + CCSR_GICC_CTLR, 0x0);
-
-	/* Enable all EPU Counters */
-	setbits_be32(dcsr_epu_base + EPGCR, 0x80000000);
-
-	/* Enable SCU15 */
-	setbits_be32(dcsr_epu_base + EPECR15, 0x90000004);
-
-	/* Enter WFI mode, and EPU FSM will start */
-	__asm__ __volatile__ ("wfi" : : : "memory");
-
-	/* NEVER ENTER HERE */
-	while (1)
-		;
-}
-
-static void __secure ls1_deep_sleep(u32 entry_point)
-{
-	struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
-	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
-	struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR;
-#ifdef QIXIS_BASE
-	u32 tmp;
-	void *qixis_base = (void *)QIXIS_BASE;
-#endif
-
-	/* Enable cluster to enter the PCL10 state */
-	out_be32(&scfg->clusterpmcr, SCFG_CLUSTERPMCR_WFIL2EN);
-
-	/* Save the first 128 bytes of DDR data */
-	ls1_save_ddr_head();
-
-	/* Save the kernel resume entry */
-	out_le32(&scfg->sparecr[3], entry_point);
-
-	/* Request to put cluster 0 in PCL10 state */
-	setbits_be32(&rcpm->clpcl10setr, RCPM_CLPCL10SETR_C0);
-
-	/* Setup the registers of the EPU FSM for deep sleep */
-	ls1_fsm_setup();
-
-#ifdef QIXIS_BASE
-	/* Connect the EVENT button to IRQ in FPGA */
-	tmp = in_8(qixis_base + QIXIS_CTL_SYS);
-	tmp &= ~QIXIS_CTL_SYS_EVTSW_MASK;
-	tmp |= QIXIS_CTL_SYS_EVTSW_IRQ;
-	out_8(qixis_base + QIXIS_CTL_SYS, tmp);
-
-	/* Enable deep sleep signals in FPGA */
-	tmp = in_8(qixis_base + QIXIS_PWR_CTL2);
-	tmp |= QIXIS_PWR_CTL2_PCTL;
-	out_8(qixis_base + QIXIS_PWR_CTL2, tmp);
-
-	/* Pull down PCIe RST# */
-	tmp = in_8(qixis_base + QIXIS_RST_FORCE_3);
-	tmp |= QIXIS_RST_FORCE_3_PCIESLOT1;
-	out_8(qixis_base + QIXIS_RST_FORCE_3, tmp);
-#endif
-
-	/* Enable Warm Device Reset */
-	setbits_be32(&scfg->dpslpcr, SCFG_DPSLPCR_WDRR_EN);
-	setbits_be32(&gur->crstsr, DCFG_CRSTSR_WDRFR);
-
-	ls1_deepsleep_irq_cfg();
-
-	psci_v7_flush_dcache_all();
-
-	ls1_start_fsm();
-}
-
-#else
-static void __secure ls1_sleep(void)
-{
-	struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
-	struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR;
-
-#ifdef QIXIS_BASE
-	u32 tmp;
-	void *qixis_base = (void *)QIXIS_BASE;
-
-	/* Connect the EVENT button to IRQ in FPGA */
-	tmp = in_8(qixis_base + QIXIS_CTL_SYS);
-	tmp &= ~QIXIS_CTL_SYS_EVTSW_MASK;
-	tmp |= QIXIS_CTL_SYS_EVTSW_IRQ;
-	out_8(qixis_base + QIXIS_CTL_SYS, tmp);
-#endif
-
-	/* Enable cluster to enter the PCL10 state */
-	out_be32(&scfg->clusterpmcr, SCFG_CLUSTERPMCR_WFIL2EN);
-
-	setbits_be32(&rcpm->powmgtcsr, RCPM_POWMGTCSR_LPM20_REQ);
-
-	__asm__ __volatile__ ("wfi" : : : "memory");
-}
-#endif
-
-void __secure ls1_system_suspend(u32 fn, u32 entry_point, u32 context_id)
-{
-#ifdef CONFIG_LS1_DEEP_SLEEP
-	ls1_deep_sleep(entry_point);
-#else
-	ls1_sleep();
-#endif
-}

arch/arm/cpu/armv7/ls102xa/psci.S

@@ -29,7 +29,6 @@
 #define PSCI_FN_AFFINITY_INFO_FEATURE_MASK	0x0
 #define PSCI_FN_SYSTEM_OFF_FEATURE_MASK		0x0
 #define PSCI_FN_SYSTEM_RESET_FEATURE_MASK	0x0
-#define PSCI_FN_SYSTEM_SUSPEND_FEATURE_MASK	0x0
 
 	.pushsection ._secure.text, "ax"
 
@@ -62,8 +61,6 @@ _ls102x_psci_supported_table:
 	.word	PSCI_FN_SYSTEM_OFF_FEATURE_MASK
 	.word	ARM_PSCI_0_2_FN_SYSTEM_RESET
 	.word	PSCI_FN_SYSTEM_RESET_FEATURE_MASK
-	.word	ARM_PSCI_1_0_FN_SYSTEM_SUSPEND
-	.word	PSCI_FN_SYSTEM_SUSPEND_FEATURE_MASK
 	.word	0
 	.word	ARM_PSCI_RET_NI
 
@@ -246,12 +243,4 @@ psci_system_reset:
 1:	wfi
 	b	1b
 
-.globl	psci_system_suspend
-psci_system_suspend:
-	push	{lr}
-
-	bl	ls1_system_suspend
-
-	pop	{pc}
-
 	.popsection

arch/arm/cpu/armv7/ls102xa/soc.c

@@ -7,11 +7,9 @@
 #include <common.h>
 #include <asm/arch/clock.h>
 #include <asm/io.h>
-#include <asm/arch/fsl_serdes.h>
 #include <asm/arch/immap_ls102xa.h>
 #include <asm/arch/ls102xa_soc.h>
 #include <asm/arch/ls102xa_stream_id.h>
-#include <fsl_csu.h>
 
 struct liodn_id_table sec_liodn_tbl[] = {
 	SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10),
@@ -60,29 +58,12 @@ unsigned int get_soc_major_rev(void)
 	return major;
 }
 
-#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
-void erratum_a010315(void)
-{
-	int i;
-
-	for (i = PCIE1; i <= PCIE2; i++)
-		if (!is_serdes_configured(i)) {
-			debug("PCIe%d: disabled all R/W permission!\n", i);
-			set_pcie_ns_access(i, 0);
-		}
-}
-#endif
-
 int arch_soc_init(void)
 {
 	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
 	unsigned int major;
 
-#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
-	enable_layerscape_ns_access();
-#endif
-
 #ifdef CONFIG_FSL_QSPI
 	out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
 #endif

arch/arm/cpu/armv7/mx5/clock.c

@@ -9,7 +9,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/clock.h>

arch/arm/cpu/armv7/mx5/soc.c

@@ -12,7 +12,7 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/sys_proto.h>
 
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/io.h>
 #include <asm/imx-common/boot_mode.h>
 

arch/arm/cpu/armv7/mx6/clock.c

@@ -7,7 +7,7 @@
 #include <common.h>
 #include <div64.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/clock.h>

arch/arm/cpu/armv7/mx6/mp.c

@@ -9,7 +9,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/imx-regs.h>
 

arch/arm/cpu/armv7/mx6/soc.c

@@ -8,7 +8,7 @@
  */
 
 #include <common.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/clock.h>

arch/arm/cpu/armv7/mx7/clock.c

@@ -10,7 +10,7 @@
 #include <common.h>
 #include <div64.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/clock.h>

arch/arm/cpu/armv7/mx7/clock_slice.c

@@ -10,7 +10,7 @@
 #include <common.h>
 #include <div64.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/clock.h>

arch/arm/cpu/armv7/omap-common/Kconfig

@@ -1,6 +1,6 @@
 config TI_SECURE_DEVICE
 	bool "HS Device Type Support"
-	depends on OMAP54XX || AM43XX || AM33XX
+	depends on OMAP54XX || AM43XX
 	help
 	  If a high secure (HS) device type is being used, this config
 	  must be set. This option impacts various aspects of the

arch/arm/cpu/armv7/omap-common/boot-common.c

@@ -90,11 +90,6 @@ void save_omap_boot_params(void)
 		case BOOT_DEVICE_CPGMAC:
 			sys_boot_device = 1;
 			break;
-#endif
-#if defined(BOOT_DEVICE_DFU) && !defined(CONFIG_SPL_DFU_SUPPORT)
-		case BOOT_DEVICE_DFU:
-			sys_boot_device = 1;
-			break;
 #endif
 	}
 

arch/arm/cpu/armv7/omap-common/emif-common.c

@@ -14,7 +14,6 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/omap_common.h>
-#include <asm/omap_sec_common.h>
 #include <asm/utils.h>
 #include <linux/compiler.h>
 
@@ -1478,20 +1477,6 @@ void sdram_init(void)
 			debug("get_ram_size() successful");
 	}
 
-#if defined(CONFIG_TI_SECURE_DEVICE)
-	/*
-	 * On HS devices, do static EMIF firewall configuration
-	 * but only do it if not already running in SDRAM
-	 */
-	if (!in_sdram)
-		if (0 != secure_emif_reserve())
-			hang();
-
-	/* On HS devices, ensure static EMIF firewall APIs are locked */
-	if (0 != secure_emif_firewall_lock())
-		hang();
-#endif
-
 	if (sdram_type == EMIF_SDRAM_TYPE_DDR3 &&
 	    (!in_sdram && !warm_reset()) && (!is_dra7xx())) {
 		if (emif1_enabled)

arch/arm/cpu/armv7/omap-common/pipe3-phy.c

@@ -12,7 +12,7 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include "pipe3-phy.h"
 
 /* PLLCTRL Registers */

arch/arm/cpu/armv7/omap3/Kconfig

@@ -1,38 +1,5 @@
 if OMAP34XX
 
-config SPL_EXT_SUPPORT
-	default y
-
-config SPL_FAT_SUPPORT
-	default y
-
-config SPL_GPIO_SUPPORT
-	default y
-
-config SPL_I2C_SUPPORT
-	default y
-
-config SPL_LIBCOMMON_SUPPORT
-	default y
-
-config SPL_LIBDISK_SUPPORT
-	default y
-
-config SPL_LIBGENERIC_SUPPORT
-	default y
-
-config SPL_MMC_SUPPORT
-	default y
-
-config SPL_NAND_SUPPORT
-	default y
-
-config SPL_POWER_SUPPORT
-	default y
-
-config SPL_SERIAL_SUPPORT
-	default y
-
 choice
 	prompt "OMAP3 board select"
 	optional

arch/arm/cpu/armv7/omap4/Kconfig

@@ -1,38 +1,5 @@
 if OMAP44XX
 
-config SPL_EXT_SUPPORT
-	default y
-
-config SPL_FAT_SUPPORT
-	default y
-
-config SPL_GPIO_SUPPORT
-	default y
-
-config SPL_I2C_SUPPORT
-	default y
-
-config SPL_LIBCOMMON_SUPPORT
-	default y
-
-config SPL_LIBDISK_SUPPORT
-	default y
-
-config SPL_LIBGENERIC_SUPPORT
-	default y
-
-config SPL_MMC_SUPPORT
-	default y
-
-config SPL_NAND_SUPPORT
-	default y
-
-config SPL_POWER_SUPPORT
-	default y
-
-config SPL_SERIAL_SUPPORT
-	default y
-
 choice
 	prompt "OMAP4 board select"
 	optional

arch/arm/cpu/armv7/omap5/Kconfig

@@ -1,38 +1,5 @@
 if OMAP54XX
 
-config SPL_EXT_SUPPORT
-	default y
-
-config SPL_FAT_SUPPORT
-	default y
-
-config SPL_GPIO_SUPPORT
-	default y
-
-config SPL_I2C_SUPPORT
-	default y
-
-config SPL_LIBCOMMON_SUPPORT
-	default y
-
-config SPL_LIBDISK_SUPPORT
-	default y
-
-config SPL_LIBGENERIC_SUPPORT
-	default y
-
-config SPL_MMC_SUPPORT
-	default y
-
-config SPL_NAND_SUPPORT
-	default y
-
-config SPL_POWER_SUPPORT
-	default y
-
-config SPL_SERIAL_SUPPORT
-	default y
-
 choice
 	prompt "OMAP5 board select"
 	optional
@@ -57,32 +24,6 @@ endchoice
 config SYS_SOC
 	default "omap5"
 
-config TI_SECURE_EMIF_REGION_START
-	hex "Reserved EMIF region start address"
-	depends on TI_SECURE_DEVICE
-	default 0x0
-	help
-	  Reserved EMIF region start address. Set to "0" to auto-select
-	  to be at the end of the external memory region.
-
-config TI_SECURE_EMIF_TOTAL_REGION_SIZE
-	hex "Reserved EMIF region size"
-	depends on TI_SECURE_DEVICE
-	default 0x0
-	help
-	  Total reserved EMIF region size. Default is 0, which means no reserved EMIF
-	  region on secure devices.
-
-config TI_SECURE_EMIF_PROTECTED_REGION_SIZE
-	hex "Size of protected region within reserved EMIF region"
-	depends on TI_SECURE_DEVICE
-	default 0x0
-	help
-	  This config option is used to specify the size of the portion of the total
-	  reserved EMIF region set aside for secure OS needs that will  be protected
-	  using hardware memory firewalls. This value must be smaller than the
-	  TI_SECURE_EMIF_TOTAL_REGION_SIZE value.
-
 source "board/compulab/cm_t54/Kconfig"
 source "board/ti/omap5_uevm/Kconfig"
 source "board/ti/dra7xx/Kconfig"

arch/arm/cpu/armv7/omap5/Makefile

@@ -14,4 +14,3 @@ obj-y	+= hw_data.o
 obj-y	+= abb.o
 obj-y	+= fdt.o
 obj-$(CONFIG_IODELAY_RECALIBRATION) += dra7xx_iodelay.o
-obj-$(CONFIG_TI_SECURE_DEVICE) += sec-fxns.o

arch/arm/cpu/armv7/omap5/fdt.c

@@ -153,73 +153,13 @@ static int ft_hs_fixup_sram(void *fdt, bd_t *bd)
 static int ft_hs_fixup_sram(void *fdt, bd_t *bd) { return 0; }
 #endif
 
-#if (CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE != 0)
-static int ft_hs_fixup_dram(void *fdt, bd_t *bd)
-{
-	const char *path, *subpath;
-	int offs;
-	u32 sec_mem_start = CONFIG_TI_SECURE_EMIF_REGION_START;
-	u32 sec_mem_size = CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE;
-	fdt64_t temp[2];
-
-	/* If start address is zero, place at end of DRAM */
-	if (0 == sec_mem_start)
-		sec_mem_start =
-			(CONFIG_SYS_SDRAM_BASE +
-			(omap_sdram_size() - sec_mem_size));
-
-	/* Delete any original secure_reserved node */
-	path = "/reserved-memory/secure_reserved";
-	offs = fdt_path_offset(fdt, path);
-	if (offs >= 0)
-		fdt_del_node(fdt, offs);
-
-	/* Add new secure_reserved node */
-	path = "/reserved-memory";
-	offs = fdt_path_offset(fdt, path);
-	if (offs < 0) {
-		debug("Node %s not found\n", path);
-		path = "/";
-		subpath = "reserved-memory";
-		fdt_path_offset(fdt, path);
-		offs = fdt_add_subnode(fdt, offs, subpath);
-		if (offs < 0) {
-			printf("Could not create %s%s node.\n", path, subpath);
-			return 1;
-		}
-		path = "/reserved-memory";
-		offs = fdt_path_offset(fdt, path);
-	}
-
-	subpath = "secure_reserved";
-	offs = fdt_add_subnode(fdt, offs, subpath);
-	if (offs < 0) {
-		printf("Could not create %s%s node.\n", path, subpath);
-		return 1;
-	}
-
-	temp[0] = cpu_to_fdt64(((u64)sec_mem_start));
-	temp[1] = cpu_to_fdt64(((u64)sec_mem_size));
-	fdt_setprop_string(fdt, offs, "compatible",
-			   "ti,dra7-secure-memory");
-	fdt_setprop_string(fdt, offs, "status", "okay");
-	fdt_setprop(fdt, offs, "no-map", NULL, 0);
-	fdt_setprop(fdt, offs, "reg", temp, sizeof(temp));
-
-	return 0;
-}
-#else
-static int ft_hs_fixup_dram(void *fdt, bd_t *bd) { return 0; }
-#endif
-
 static void ft_hs_fixups(void *fdt, bd_t *bd)
 {
 	/* Check we are running on an HS/EMU device type */
 	if (GP_DEVICE != get_device_type()) {
 		if ((ft_hs_fixup_crossbar(fdt, bd) == 0) &&
 		    (ft_hs_disable_rng(fdt, bd) == 0) &&
-		    (ft_hs_fixup_sram(fdt, bd) == 0) &&
-		    (ft_hs_fixup_dram(fdt, bd) == 0))
+		    (ft_hs_fixup_sram(fdt, bd) == 0))
 			return;
 	} else {
 		printf("ERROR: Incorrect device type (GP) detected!");
@@ -231,7 +171,7 @@ static void ft_hs_fixups(void *fdt, bd_t *bd)
 static void ft_hs_fixups(void *fdt, bd_t *bd)
 {
 }
-#endif /* #ifdef CONFIG_TI_SECURE_DEVICE */
+#endif
 
 /*
  * Place for general cpu/SoC FDT fixups. Board specific

arch/arm/cpu/armv7/omap5/sec-fxns.c

@@ -1,126 +0,0 @@
-/*
- *
- * Security related functions for OMAP5 class devices
- *
- * (C) Copyright 2016
- * Texas Instruments, <www.ti.com>
- *
- * Daniel Allred <d-allred@ti.com>
- * Harinarayan Bhatta <harinarayan@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <stdarg.h>
-
-#include <asm/arch/sys_proto.h>
-#include <asm/omap_common.h>
-#include <asm/omap_sec_common.h>
-#include <asm/spl.h>
-#include <spl.h>
-
-/* Index for signature PPA-based TI HAL APIs */
-#define PPA_HAL_SERVICES_START_INDEX        (0x200)
-#define PPA_SERV_HAL_SETUP_SEC_RESVD_REGION (PPA_HAL_SERVICES_START_INDEX + 25)
-#define PPA_SERV_HAL_SETUP_EMIF_FW_REGION   (PPA_HAL_SERVICES_START_INDEX + 26)
-#define PPA_SERV_HAL_LOCK_EMIF_FW           (PPA_HAL_SERVICES_START_INDEX + 27)
-
-static u32 get_sec_mem_start(void)
-{
-	u32 sec_mem_start = CONFIG_TI_SECURE_EMIF_REGION_START;
-	u32 sec_mem_size = CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE;
-	/*
-	 * Total reserved region is all contiguous with protected
-	 * region coming first, followed by the non-secure region.
-	 * If 0x0 start address is given, we simply put the reserved
-	 * region at the end of the external DRAM.
-	 */
-	if (sec_mem_start == 0)
-		sec_mem_start =
-			(CONFIG_SYS_SDRAM_BASE +
-			(omap_sdram_size() - sec_mem_size));
-	return sec_mem_start;
-}
-
-int secure_emif_firewall_setup(uint8_t region_num, uint32_t start_addr,
-			       uint32_t size, uint32_t access_perm,
-			       uint32_t initiator_perm)
-{
-	int result = 1;
-
-	/*
-	 * Call PPA HAL API to do any other general firewall
-	 * configuration for regions 1-6 of the EMIF firewall.
-	 */
-	debug("%s: regionNum = %x, startAddr = %x, size = %x", __func__,
-	      region_num, start_addr, size);
-
-	result = secure_rom_call(
-			PPA_SERV_HAL_SETUP_EMIF_FW_REGION, 0, 0, 4,
-			(start_addr & 0xFFFFFFF0) | (region_num & 0x0F),
-			size, access_perm, initiator_perm);
-
-	if (result != 0) {
-		puts("Secure EMIF Firewall Setup failed!\n");
-		debug("Return Value = %x\n", result);
-	}
-
-	return result;
-}
-
-#if	(CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE <  \
-	CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE)
-#error	"TI Secure EMIF: Protected size cannot be larger than total size."
-#endif
-int secure_emif_reserve(void)
-{
-	int result = 1;
-	u32 sec_mem_start = get_sec_mem_start();
-	u32 sec_prot_size = CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE;
-
-	/* If there is no protected region, there is no reservation to make */
-	if (sec_prot_size == 0)
-		return 0;
-
-	/*
-	 * Call PPA HAL API to reserve a chunk of EMIF SDRAM
-	 * for secure world use. This region should be carved out
-	 * from use by any public code. EMIF firewall region 7
-	 * will be used to protect this block of memory.
-	 */
-	result = secure_rom_call(
-			PPA_SERV_HAL_SETUP_SEC_RESVD_REGION,
-			0, 0, 2, sec_mem_start, sec_prot_size);
-
-	if (result != 0) {
-		puts("SDRAM Firewall: Secure memory reservation failed!\n");
-		debug("Return Value = %x\n", result);
-	}
-
-	return result;
-}
-
-int secure_emif_firewall_lock(void)
-{
-	int result = 1;
-
-	/*
-	 * Call PPA HAL API to lock the EMIF firewall configurations.
-	 * After this API is called, none of the PPA HAL APIs for
-	 * configuring the EMIF firewalls will be usable again (that
-	 * is, calls to those APIs will return failure and have no
-	 * effect).
-	 */
-
-	result = secure_rom_call(
-			PPA_SERV_HAL_LOCK_EMIF_FW,
-			0, 0, 0);
-
-	if (result != 0) {
-		puts("Secure EMIF Firewall Lock failed!\n");
-		debug("Return Value = %x\n", result);
-	}
-
-	return result;
-}

arch/arm/cpu/armv7/psci.S

@@ -187,7 +187,7 @@ ENDPROC(psci_get_cpu_id)
 .weak psci_get_cpu_id
 
 /* Imported from Linux kernel */
-ENTRY(psci_v7_flush_dcache_all)
+LENTRY(v7_flush_dcache_all)
 	stmfd	sp!, {r4-r5, r7, r9-r11, lr}
 	dmb					@ ensure ordering with previous memory accesses
 	mrc	p15, 1, r0, c0, c0, 1		@ read clidr
@@ -234,7 +234,7 @@ finished:
 	isb
 	ldmfd	sp!, {r4-r5, r7, r9-r11, lr}
 	bx	lr
-ENDPROC(psci_v7_flush_dcache_all)
+ENDPROC(v7_flush_dcache_all)
 
 ENTRY(psci_disable_smp)
 	mrc	p15, 0, r0, c1, c0, 1		@ ACTLR
@@ -264,7 +264,7 @@ ENTRY(psci_cpu_off_common)
 	isb
 	dsb
 
-	bl	psci_v7_flush_dcache_all
+	bl	v7_flush_dcache_all
 
 	clrex					@ Why???
 

arch/arm/cpu/armv8/fsl-layerscape/Kconfig

@@ -1,17 +0,0 @@
-config ARCH_LS1012A
-	bool "Freescale Layerscape LS1012A SoC"
-	select SYS_FSL_MMDC
-	select SYS_FSL_ERRATUM_A010315
-
-config ARCH_LS1043A
-	bool "Freescale Layerscape LS1043A SoC"
-	select SYS_FSL_ERRATUM_A010315
-
-config ARCH_LS1046A
-	bool "Freescale Layerscape LS1046A SoC"
-
-config SYS_FSL_MMDC
-	bool "Freescale Multi Mode DDR Controller"
-
-config SYS_FSL_ERRATUM_A010315
-	bool "Workaround for PCIe erratum A010315"

arch/arm/cpu/armv8/fsl-layerscape/Makefile

@@ -30,10 +30,10 @@ ifneq ($(CONFIG_LS1043A),)
 obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o
 endif
 
-ifneq ($(CONFIG_ARCH_LS1012A),)
+ifneq ($(CONFIG_LS1012A),)
 obj-$(CONFIG_SYS_HAS_SERDES) += ls1012a_serdes.o
 endif
 
-ifneq ($(CONFIG_ARCH_LS1046A),)
+ifneq ($(CONFIG_LS1046A),)
 obj-$(CONFIG_SYS_HAS_SERDES) += ls1046a_serdes.o
 endif

arch/arm/cpu/armv8/fsl-layerscape/cpu.c

@@ -6,7 +6,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/system.h>
 #include <asm/armv8/mmu.h>
 #include <asm/io.h>
@@ -18,6 +18,7 @@
 #include <asm/arch/mp.h>
 #endif
 #include <fm_eth.h>
+#include <fsl_debug_server.h>
 #include <fsl-mc/fsl_mc.h>
 #ifdef CONFIG_FSL_ESDHC
 #include <fsl_esdhc.h>
@@ -456,6 +457,10 @@ phys_size_t board_reserve_ram_top(phys_size_t ram_size)
 #ifdef CONFIG_SYS_MEM_TOP_HIDE
 #error CONFIG_SYS_MEM_TOP_HIDE not to be used together with this function
 #endif
+/* Carve the Debug Server private DRAM block from the end of DRAM */
+#ifdef CONFIG_FSL_DEBUG_SERVER
+	ram_top -= debug_server_get_dram_block_size();
+#endif
 
 /* Carve the MC private DRAM block from the end of DRAM */
 #ifdef CONFIG_FSL_MC_ENET

arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c

@@ -6,7 +6,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/fsl_serdes.h>
 #include <asm/arch/soc.h>
 
@@ -22,15 +22,9 @@ int is_serdes_configured(enum srds_prtcl device)
 	int ret = 0;
 
 #ifdef CONFIG_SYS_FSL_SRDS_1
-	if (!serdes1_prtcl_map[NONE])
-		fsl_serdes_init();
-
 	ret |= serdes1_prtcl_map[device];
 #endif
 #ifdef CONFIG_SYS_FSL_SRDS_2
-	if (!serdes2_prtcl_map[NONE])
-		fsl_serdes_init();
-
 	ret |= serdes2_prtcl_map[device];
 #endif
 
@@ -104,9 +98,6 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
 	u32 cfg;
 	int lane;
 
-	if (serdes_prtcl_map[NONE])
-		return;
-
 	memset(serdes_prtcl_map, 0, sizeof(u8) * SERDES_PRCTL_COUNT);
 
 	cfg = gur_in32(&gur->rcwsr[4]) & sd_prctl_mask;
@@ -124,9 +115,6 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
 		else
 			serdes_prtcl_map[lane_prtcl] = 1;
 	}
-
-	/* Set the first element to indicate serdes has been initialized */
-	serdes_prtcl_map[NONE] = 1;
 }
 
 void fsl_serdes_init(void)

arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c

@@ -60,7 +60,7 @@ void get_sys_info(struct sys_info *sys_info)
 	sys_info->freq_ddrbus = sysclk;
 #endif
 
-#ifdef CONFIG_ARCH_LS1012A
+#ifdef CONFIG_LS1012A
 	sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
 			FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
 			FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
@@ -91,7 +91,7 @@ void get_sys_info(struct sys_info *sys_info)
 			freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
 	}
 
-#ifdef CONFIG_ARCH_LS1012A
+#ifdef CONFIG_LS1012A
 	sys_info->freq_systembus = sys_info->freq_ddrbus / 2;
 	sys_info->freq_ddrbus *= 2;
 #endif

arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c

@@ -6,7 +6,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/fsl_serdes.h>
 #include <asm/arch/soc.h>
 #include <fsl-mc/ldpaa_wriop.h>
@@ -28,15 +28,9 @@ int is_serdes_configured(enum srds_prtcl device)
 	int ret = 0;
 
 #ifdef CONFIG_SYS_FSL_SRDS_1
-	if (!serdes1_prtcl_map[NONE])
-		fsl_serdes_init();
-
 	ret |= serdes1_prtcl_map[device];
 #endif
 #ifdef CONFIG_SYS_FSL_SRDS_2
-	if (!serdes2_prtcl_map[NONE])
-		fsl_serdes_init();
-
 	ret |= serdes2_prtcl_map[device];
 #endif
 
@@ -85,9 +79,6 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
 	u32 cfg;
 	int lane;
 
-	if (serdes_prtcl_map[NONE])
-		return;
-
 	memset(serdes_prtcl_map, 0, sizeof(u8) * SERDES_PRCTL_COUNT);
 
 	cfg = gur_in32(&gur->rcwsr[28]) & sd_prctl_mask;
@@ -145,9 +136,6 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
 #endif
 		}
 	}
-
-	/* Set the first element to indicate serdes has been initialized */
-	serdes_prtcl_map[NONE] = 1;
 }
 
 void fsl_serdes_init(void)

arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S

@@ -179,21 +179,6 @@ ENTRY(lowlevel_init)
 	isb
 	dsb	sy
 #endif
-
-#ifdef CONFIG_ARCH_LS1046A
-	/* Initialize the L2 RAM latency */
-	mrs   x1, S3_1_c11_c0_2
-	mov   x0, #0x1C7
-	/* Clear L2 Tag RAM latency and L2 Data RAM latency */
-	bic   x1, x1, x0
-	/* Set L2 data ram latency bits [2:0] */
-	orr   x1, x1, #0x2
-	/* set L2 tag ram latency bits [8:6] */
-	orr   x1,  x1, #0x80
-	msr   S3_1_c11_c0_2, x1
-	isb
-#endif
-
 	mov	lr, x29			/* Restore LR */
 	ret
 ENDPROC(lowlevel_init)

arch/arm/cpu/armv8/fsl-layerscape/ppa.c

@@ -17,9 +17,6 @@
 #ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
 #include <asm/armv8/sec_firmware.h>
 #endif
-#ifdef CONFIG_CHAIN_OF_TRUST
-#include <fsl_validate.h>
-#endif
 
 int ppa_init(void)
 {
@@ -27,30 +24,12 @@ int ppa_init(void)
 	u32 *boot_loc_ptr_l, *boot_loc_ptr_h;
 	int ret;
 
-#ifdef CONFIG_CHAIN_OF_TRUST
-	uintptr_t ppa_esbc_hdr = CONFIG_SYS_LS_PPA_ESBC_ADDR;
-	uintptr_t ppa_img_addr = 0;
-#endif
-
 #ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP
 	ppa_fit_addr = (void *)CONFIG_SYS_LS_PPA_FW_ADDR;
 #else
 #error "No CONFIG_SYS_LS_PPA_FW_IN_xxx defined"
 #endif
 
-#ifdef CONFIG_CHAIN_OF_TRUST
-	ppa_img_addr = (uintptr_t)ppa_fit_addr;
-	if (fsl_check_boot_mode_secure() != 0) {
-		ret = fsl_secboot_validate(ppa_esbc_hdr,
-					   CONFIG_PPA_KEY_HASH,
-					   &ppa_img_addr);
-		if (ret != 0)
-			printf("PPA validation failed\n");
-		else
-			printf("PPA validation Successful\n");
-	}
-#endif
-
 #ifdef CONFIG_FSL_LSCH3
 	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 	boot_loc_ptr_l = &gur->bootlocptrl;

arch/arm/cpu/armv8/fsl-layerscape/soc.c

@@ -8,14 +8,10 @@
 #include <fsl_ifc.h>
 #include <ahci.h>
 #include <scsi.h>
-#include <asm/arch/fsl_serdes.h>
 #include <asm/arch/soc.h>
 #include <asm/io.h>
 #include <asm/global_data.h>
 #include <asm/arch-fsl-layerscape/config.h>
-#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
-#include <fsl_csu.h>
-#endif
 #ifdef CONFIG_SYS_FSL_DDR
 #include <fsl_ddr_sdram.h>
 #include <fsl_ddr.h>
@@ -62,13 +58,11 @@ static void erratum_a008336(void)
 #ifdef CONFIG_SYS_FSL_ERRATUM_A008336
 #ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR
 	eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
-	if (fsl_ddr_get_version(0) == 0x50200)
-		out_le32(eddrtqcr1, 0x63b30002);
+	out_le32(eddrtqcr1, 0x63b30002);
 #endif
 #ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR
 	eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
-	if (fsl_ddr_get_version(0) == 0x50200)
-		out_le32(eddrtqcr1, 0x63b30002);
+	out_le32(eddrtqcr1, 0x63b30002);
 #endif
 #endif
 }
@@ -228,10 +222,6 @@ int sata_init(void)
 {
 	struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA;
 
-#ifdef CONFIG_ARCH_LS1046A
-	/* Disable SATA ECC */
-	out_le32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + 0x520, 0x80000000);
-#endif
 	out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
 	out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY_2_CFG);
 	out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY_3_CFG);
@@ -308,28 +298,11 @@ void erratum_a008850_post(void)
 #endif
 }
 
-#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
-void erratum_a010315(void)
-{
-	int i;
-
-	for (i = PCIE1; i <= PCIE4; i++)
-		if (!is_serdes_configured(i)) {
-			debug("PCIe%d: disabled all R/W permission!\n", i);
-			set_pcie_ns_access(i, 0);
-		}
-}
-#endif
-
 void fsl_lsch2_early_init_f(void)
 {
 	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
 	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 
-#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
-	enable_layerscape_ns_access();
-#endif
-
 #ifdef CONFIG_FSL_IFC
 	init_early_memctl_regs();	/* tighten IFC timing */
 #endif

arch/arm/cpu/armv8/fsl-layerscape/spl.c

@@ -8,6 +8,7 @@
 #include <spl.h>
 #include <asm/io.h>
 #include <fsl_ifc.h>
+#include <fsl_csu.h>
 #include <i2c.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -61,5 +62,13 @@ void board_init_f(ulong dummy)
 	i2c_init_all();
 #endif
 	dram_init();
+
+	/* Clear the BSS */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+	enable_layerscape_ns_access();
+#endif
+	board_init_r(NULL, 0);
 }
 #endif

arch/arm/cpu/armv8/zynqmp/Kconfig

@@ -1,29 +1,5 @@
 if ARCH_ZYNQMP
 
-config SPL_FAT_SUPPORT
-	default y
-
-config SPL_LIBCOMMON_SUPPORT
-	default y
-
-config SPL_LIBDISK_SUPPORT
-	default y
-
-config SPL_LIBGENERIC_SUPPORT
-	default y
-
-config SPL_MMC_SUPPORT
-	default y
-
-config SPL_SERIAL_SUPPORT
-	default y
-
-config SPL_SPI_FLASH_SUPPORT
-	default y if ZYNQ_QSPI
-
-config SPL_SPI_SUPPORT
-	default y if ZYNQ_QSPI
-
 config SYS_BOARD
 	default "zynqmp"
 
@@ -47,53 +23,5 @@ config ZYNQMP_USB
 config SYS_MALLOC_F_LEN
 	default 0x600
 
-config SPL_ZYNQMP_ALT_BOOTMODE_ENABLED
-	bool "Overwrite SPL bootmode"
-	depends on SPL
-	help
-	  Overwrite bootmode selected via boot mode pins to tell SPL what should
-	  be the next boot device.
-
-config SPL_ZYNQMP_ALT_BOOTMODE
-	hex
-	default 0x0 if JTAG_MODE
-	default 0x1 if QSPI_MODE_24BIT
-	default 0x2 if QSPI_MODE_32BIT
-	default 0x3 if SD_MODE
-	default 0x4 if NAND_MODE
-	default 0x5 if SD_MODE1
-	default 0x6 if EMMC_MODE
-	default 0x7 if USB_MODE
-
-choice
-	prompt "Boot mode"
-	depends on ZYNQMP_ALT_BOOTMODE_ENABLED
-	default JTAG
-
-config JTAG_MODE
-	bool "JTAG_MODE"
-
-config QSPI_MODE_24BIT
-	bool "QSPI_MODE_24BIT"
-
-config QSPI_MODE_32BIT
-	bool "QSPI_MODE_32BIT"
-
-config SD_MODE
-	bool "SD_MODE"
-
-config SD_MODE1
-	bool "SD_MODE1"
-
-config NAND_MODE
-	bool "NAND_MODE"
-
-config EMMC_MODE
-	bool "EMMC_MODE"
-
-config USB_MODE
-	bool "USB"
-
-endchoice
 
 endif

arch/arm/cpu/armv8/zynqmp/spl.c

@@ -35,29 +35,10 @@ void board_init_f(ulong dummy)
 	board_init_r(NULL, 0);
 }
 
-static void ps_mode_reset(ulong mode)
-{
-	writel(mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT,
-	       &crlapb_base->boot_pin_ctrl);
-	udelay(5);
-	writel(mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT |
-	       mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT,
-	       &crlapb_base->boot_pin_ctrl);
-}
-
-/*
- * Set default PS_MODE1 which is used for USB ULPI phy reset
- * Also other resets can be connected to this certain pin
- */
-#ifndef MODE_RESET
-# define MODE_RESET	PS_MODE1
-#endif
-
 #ifdef CONFIG_SPL_BOARD_INIT
 void spl_board_init(void)
 {
 	preloader_console_init();
-	ps_mode_reset(MODE_RESET);
 	board_init();
 }
 #endif
@@ -67,13 +48,6 @@ u32 spl_boot_device(void)
 	u32 reg = 0;
 	u8 bootmode;
 
-#if defined(CONFIG_SPL_ZYNQMP_ALT_BOOTMODE_ENABLED)
-	/* Change default boot mode at run-time */
-	writel(BOOT_MODE_USE_ALT |
-	       CONFIG_SPL_ZYNQMP_ALT_BOOTMODE << BOOT_MODE_ALT_SHIFT,
-	       &crlapb_base->boot_mode);
-#endif
-
 	reg = readl(&crlapb_base->boot_mode);
 	bootmode = reg & BOOT_MODES_MASK;
 
@@ -85,10 +59,6 @@ u32 spl_boot_device(void)
 	case SD_MODE:
 	case SD_MODE1:
 		return BOOT_DEVICE_MMC1;
-#endif
-#ifdef CONFIG_SPL_DFU_SUPPORT
-	case USB_MODE:
-		return BOOT_DEVICE_DFU;
 #endif
 	default:
 		printf("Invalid Boot Mode:0x%x\n", bootmode);

arch/arm/cpu/sa1100/timer.c

@@ -66,5 +66,8 @@ unsigned long long get_ticks(void)
  */
 ulong get_tbclk (void)
 {
-	return CONFIG_SYS_HZ;
+	ulong tbclk;
+
+	tbclk = CONFIG_SYS_HZ;
+	return tbclk;
 }

arch/arm/dts/Makefile

@@ -67,12 +67,9 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
 	tegra210-p2571.dtb
 
 dtb-$(CONFIG_ARCH_MVEBU) +=			\
-	armada-3720-db.dtb			\
 	armada-375-db.dtb			\
 	armada-388-clearfog.dtb			\
 	armada-388-gp.dtb			\
-	armada-385-amc.dtb			\
-	armada-7040-db.dtb			\
 	armada-xp-gp.dtb			\
 	armada-xp-maxbcm.dtb			\
 	armada-xp-synology-ds414.dtb		\
@@ -146,8 +143,6 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
 dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
 	fsl-ls1043a-qds-lpuart.dtb \
 	fsl-ls1043a-rdb.dtb \
-	fsl-ls1046a-qds-duart.dtb \
-	fsl-ls1046a-rdb.dtb \
 	fsl-ls1012a-qds.dtb \
 	fsl-ls1012a-rdb.dtb \
 	fsl-ls1012a-frdm.dtb
@@ -266,8 +261,7 @@ dtb-$(CONFIG_MACH_SUN8I_H3) += \
 	sun8i-h3-orangepi-pc.dtb \
 	sun8i-h3-orangepi-pc-plus.dtb \
 	sun8i-h3-orangepi-plus.dtb \
-	sun8i-h3-orangepi-plus2e.dtb \
-	sun8i-h3-nanopi-neo.dtb
+	sun8i-h3-orangepi-plus2e.dtb
 dtb-$(CONFIG_MACH_SUN50I) += \
 	sun50i-a64-pine64-plus.dtb \
 	sun50i-a64-pine64.dtb

arch/arm/dts/armada-371x.dtsi

@@ -1,53 +0,0 @@
-/*
- * Device Tree Include file for Marvell Armada 371x family of SoCs
- * (also named 88F3710)
- *
- * Copyright (C) 2016 Marvell
- *
- * Gregory CLEMENT <gregory.clement@free-electrons.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This file is distributed in the hope that it will be useful
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include "armada-37xx.dtsi"
-
-/ {
-	model = "Marvell Armada 3710 SoC";
-	compatible = "marvell,armada3710", "marvell,armada3700";
-};

arch/arm/dts/armada-3720-db.dts

@@ -1,123 +0,0 @@
-/*
- * Device Tree file for Marvell Armada 3720 development board
- * (DB-88F3720-DDR3)
- * Copyright (C) 2016 Marvell
- *
- * Gregory CLEMENT <gregory.clement@free-electrons.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This file is distributed in the hope that it will be useful
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/dts-v1/;
-
-#include "armada-372x.dtsi"
-
-/ {
-	model = "Marvell Armada 3720 Development Board DB-88F3720-DDR3";
-	compatible = "marvell,armada-3720-db", "marvell,armada3720", "marvell,armada3710";
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	aliases {
-		ethernet0 = &eth0;
-		i2c0 = &i2c0;
-		spi0 = &spi0;
-	};
-
-	memory {
-		device_type = "memory";
-		reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
-	};
-};
-
-&comphy {
-	phy0 {
-		phy-type = <PHY_TYPE_PEX0>;
-		phy-speed = <PHY_SPEED_2_5G>;
-	};
-
-	phy1 {
-		phy-type = <PHY_TYPE_USB3_HOST0>;
-		phy-speed = <PHY_SPEED_5G>;
-	};
-};
-
-&eth0 {
-	status = "okay";
-	phy-mode = "rgmii";
-};
-
-&i2c0 {
-	status = "okay";
-};
-
-/* CON3 */
-&sata {
-	status = "okay";
-};
-
-&spi0 {
-	status = "okay";
-
-	spi-flash@0 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "st,m25p128", "spi-flash";
-		reg = <0>; /* Chip select 0 */
-		spi-max-frequency = <50000000>;
-		m25p,fast-read;
-	};
-};
-
-/* Exported on the micro USB connector CON32 through an FTDI */
-&uart0 {
-	status = "okay";
-};
-
-/* CON29 */
-&usb2 {
-	status = "okay";
-};
-
-/* CON31 */
-&usb3 {
-	status = "okay";
-};

arch/arm/dts/armada-372x.dtsi

@@ -1,62 +0,0 @@
-/*
- * Device Tree Include file for Marvell Armada 372x family of SoCs
- * (also named 88F3720)
- *
- * Copyright (C) 2016 Marvell
- *
- * Gregory CLEMENT <gregory.clement@free-electrons.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This file is distributed in the hope that it will be useful
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include "armada-37xx.dtsi"
-
-/ {
-	model = "Marvell Armada 3720 SoC";
-	compatible = "marvell,armada3720", "marvell,armada3710";
-
-	cpus {
-		cpu@1 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a53","arm,armv8";
-			reg = <0x1>;
-			enable-method = "psci";
-		};
-	};
-};

arch/arm/dts/armada-37xx.dtsi

@@ -1,189 +0,0 @@
-/*
- * Device Tree Include file for Marvell Armada 37xx family of SoCs.
- *
- * Copyright (C) 2016 Marvell
- *
- * Gregory CLEMENT <gregory.clement@free-electrons.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This file is distributed in the hope that it will be useful
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/comphy/comphy_data.h>
-
-/ {
-	model = "Marvell Armada 37xx SoC";
-	compatible = "marvell,armada3700";
-	interrupt-parent = <&gic>;
-	#address-cells = <2>;
-	#size-cells = <2>;
-
-	aliases {
-		serial0 = &uart0;
-	};
-
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		cpu@0 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a53", "arm,armv8";
-			reg = <0>;
-			enable-method = "psci";
-		};
-	};
-
-	psci {
-		compatible = "arm,psci-0.2";
-		method = "smc";
-	};
-
-	timer {
-		compatible = "arm,armv8-timer";
-		interrupts = <GIC_PPI 13
-			(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
-			     <GIC_PPI 14
-			(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
-			     <GIC_PPI 11
-			(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
-			     <GIC_PPI 10
-			(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
-	};
-
-	soc {
-		compatible = "simple-bus";
-		#address-cells = <2>;
-		#size-cells = <2>;
-		ranges;
-
-		internal-regs {
-			#address-cells = <1>;
-			#size-cells = <1>;
-			compatible = "simple-bus";
-			/* 32M internal register @ 0xd000_0000 */
-			ranges = <0x0 0x0 0xd0000000 0x2000000>;
-
-			uart0: serial@12000 {
-				compatible = "marvell,armada-3700-uart";
-				reg = <0x12000 0x400>;
-				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
-				status = "disabled";
-			};
-
-			usb3: usb@58000 {
-				compatible = "marvell,armada3700-xhci",
-				"generic-xhci";
-				reg = <0x58000 0x4000>;
-				interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
-				status = "disabled";
-			};
-
-			usb2: usb@5e000 {
-				compatible = "marvell,armada3700-ehci";
-				reg = <0x5e000 0x450>;
-				status = "disabled";
-			};
-
-			xor@60900 {
-				compatible = "marvell,armada-3700-xor";
-				reg = <0x60900 0x100
-				       0x60b00 0x100>;
-
-				xor10 {
-					interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
-				};
-				xor11 {
-					interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
-				};
-			};
-
-			sata: sata@e0000 {
-				compatible = "marvell,armada-3700-ahci";
-				reg = <0xe0000 0x2000>;
-				interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
-				status = "disabled";
-			};
-
-			gic: interrupt-controller@1d00000 {
-				compatible = "arm,gic-v3";
-				#interrupt-cells = <3>;
-				interrupt-controller;
-				reg = <0x1d00000 0x10000>, /* GICD */
-				      <0x1d40000 0x40000>; /* GICR */
-			};
-
-			eth0: neta@30000 {
-				compatible = "marvell,armada-3700-neta";
-				reg = <0x30000 0x20>;
-				status = "disabled";
-			};
-
-			eth1: neta@40000 {
-				compatible = "marvell,armada-3700-neta";
-				reg = <0x40000 0x20>;
-				status = "disabled";
-			};
-
-			i2c0: i2c@11000 {
-				compatible = "marvell,armada-3700-i2c";
-				reg = <0x11000 0x100>;
-				status = "disabled";
-			};
-
-			spi0: spi@10600 {
-				compatible = "marvell,armada-3700-spi";
-				reg = <0x10600 0x50>;
-				#address-cells = <1>;
-				#size-cells = <0>;
-				#clock-cells = <0>;
-				clock-frequency = <160000>;
-				spi-max-frequency = <40000>;
-				status = "disabled";
-			};
-
-			comphy: comphy@18300 {
-				compatible = "marvell,mvebu-comphy", "marvell,comphy-armada-3700";
-				reg = <0x18300 0x28>,
-				      <0x1f300 0x3d000>;
-				mux-bitcount = <1>;
-				max-lanes = <2>;
-			};
-		};
-	};
-};

arch/arm/dts/armada-385-amc.dts

@@ -1,163 +0,0 @@
-/*
- * Device Tree file for Marvell Armada 385 development board
- * (DB-88F6820-AMC)
- *
- * Copyright (C) 2014 Marvell
- *
- * Gregory CLEMENT <gregory.clement@free-electrons.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is licensed under the terms of the GNU General Public
- *     License version 2.  This program is licensed "as is" without
- *     any warranty of any kind, whether express or implied.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/dts-v1/;
-#include "armada-385.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-	model = "Marvell Armada 385 AMC";
-	compatible = "marvell,a385-amc", "marvell,armada385", "marvell,armada380";
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	aliases {
-		ethernet0 = &eth0;
-		ethernet1 = &eth1;
-		spi1 = &spi1;
-	};
-
-	memory {
-		device_type = "memory";
-		reg = <0x00000000 0x80000000>; /* 2 GB */
-	};
-
-	soc {
-		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
-			  MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
-
-		internal-regs {
-			i2c@11000 {
-				pinctrl-names = "default";
-				pinctrl-0 = <&i2c0_pins>;
-				status = "okay";
-			};
-
-			serial@12000 {
-				/*
-				 * Exported on the micro USB connector CON16
-				 * through an FTDI
-				 */
-
-				pinctrl-names = "default";
-				pinctrl-0 = <&uart0_pins>;
-				status = "okay";
-				u-boot,dm-pre-reloc;
-			};
-
-			ethernet@34000 {
-				status = "okay";
-				phy = <&phy1>;
-				phy-mode = "sgmii";
-			};
-
-			usb@58000 {
-				status = "okay";
-			};
-
-			ethernet@70000 {
-				pinctrl-names = "default";
-				/*
-				 * The Reference Clock 0 is used to provide a
-				 * clock to the PHY
-				 */
-				pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>;
-				status = "okay";
-				phy = <&phy0>;
-				phy-mode = "rgmii-id";
-			};
-
-
-			mdio@72004 {
-				pinctrl-names = "default";
-				pinctrl-0 = <&mdio_pins>;
-
-				phy0: ethernet-phy@1 {
-					reg = <1>;
-				};
-
-				phy1: ethernet-phy@0 {
-					reg = <0>;
-				};
-			};
-
-			flash@d0000 {
-				status = "okay";
-				num-cs = <1>;
-				marvell,nand-keep-config;
-				marvell,nand-enable-arbiter;
-				nand-on-flash-bbt;
-			};
-		};
-
-		pcie-controller {
-			status = "okay";
-			pcie@1,0 {
-				/* Port 0, Lane 0 */
-				status = "okay";
-			};
-
-		};
-	};
-};
-
-&spi1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&spi1_pins>;
-	status = "okay";
-	u-boot,dm-pre-reloc;
-
-	spi-flash@0 {
-		u-boot,dm-pre-reloc;
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "st,m25p128", "jedec,spi-nor";
-		reg = <0>; /* Chip select 0 */
-		spi-max-frequency = <50000000>;
-		m25p,fast-read;
-	};
-};
-
-&refclk {
-	clock-frequency = <20000000>;
-};

arch/arm/dts/armada-7040-db.dts

@@ -1,193 +0,0 @@
-/*
- * Copyright (C) 2016 Marvell Technology Group Ltd.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPLv2 or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This library is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This library is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Device Tree file for Marvell Armada 7040 Development board platform
- */
-
-#include "armada-7040.dtsi"
-
-/ {
-	model = "Marvell Armada 7040 DB board";
-	compatible = "marvell,armada7040-db", "marvell,armada7040",
-		     "marvell,armada-ap806-quad", "marvell,armada-ap806";
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	aliases {
-		i2c0 = &cpm_i2c0;
-		spi0 = &cpm_spi1;
-	};
-
-	memory@00000000 {
-		device_type = "memory";
-		reg = <0x0 0x0 0x0 0x80000000>;
-	};
-};
-
-&i2c0 {
-	status = "okay";
-	clock-frequency = <100000>;
-};
-
-&spi0 {
-	status = "okay";
-
-	spi-flash@0 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <10000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "U-Boot";
-				reg = <0 0x200000>;
-			};
-			partition@400000 {
-				label = "Filesystem";
-				reg = <0x200000 0xce0000>;
-			};
-		};
-	};
-};
-
-&uart0 {
-	status = "okay";
-};
-
-
-&cpm_pcie2 {
-	status = "okay";
-};
-
-&cpm_i2c0 {
-	status = "okay";
-	clock-frequency = <100000>;
-};
-
-&cpm_spi1 {
-	status = "okay";
-
-	spi-flash@0 {
-		#address-cells = <0x1>;
-		#size-cells = <0x1>;
-		compatible = "jedec,spi-nor";
-		reg = <0x0>;
-		spi-max-frequency = <20000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "U-Boot";
-				reg = <0x0 0x200000>;
-			};
-
-			partition@400000 {
-				label = "Filesystem";
-				reg = <0x200000 0xe00000>;
-			};
-		};
-	};
-};
-
-&cpm_sata0 {
-	status = "okay";
-};
-
-&cpm_usb3_0 {
-	status = "okay";
-};
-
-&cpm_usb3_1 {
-	status = "okay";
-};
-
-&comphy_cp110 {
-	phy0 {
-		phy-type = <PHY_TYPE_SGMII2>;
-		phy-speed = <PHY_SPEED_3_125G>;
-	};
-
-	phy1 {
-		phy-type = <PHY_TYPE_USB3_HOST0>;
-		phy-speed = <PHY_SPEED_5G>;
-	};
-
-	phy2 {
-		phy-type = <PHY_TYPE_SGMII0>;
-		phy-speed = <PHY_SPEED_1_25G>;
-	};
-
-	phy3 {
-		phy-type = <PHY_TYPE_SATA1>;
-		phy-speed = <PHY_SPEED_5G>;
-	};
-
-	phy4 {
-		phy-type = <PHY_TYPE_USB3_HOST1>;
-		phy-speed = <PHY_SPEED_5G>;
-	};
-
-	phy5 {
-		phy-type = <PHY_TYPE_PEX2>;
-		phy-speed = <PHY_SPEED_5G>;
-	};
-};
-
-&utmi0 {
-	status = "okay";
-};
-
-&utmi1 {
-	status = "okay";
-};

arch/arm/dts/armada-7040.dtsi

@@ -1,55 +0,0 @@
-/*
- * Copyright (C) 2016 Marvell Technology Group Ltd.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPLv2 or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This library is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This library is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Device Tree file for the Armada 7040 SoC, made of an AP806 Quad and
- * one CP110.
- */
-
-#include "armada-ap806-quad.dtsi"
-#include "armada-cp110-master.dtsi"
-
-/ {
-	model = "Marvell Armada 7040";
-	compatible = "marvell,armada7040", "marvell,armada-ap806-quad",
-		     "marvell,armada-ap806";
-};

arch/arm/dts/armada-ap806-quad.dtsi

@@ -1,82 +0,0 @@
-/*
- * Copyright (C) 2016 Marvell Technology Group Ltd.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPLv2 or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This library is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This library is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Device Tree file for Marvell Armada AP806.
- */
-
-#include "armada-ap806.dtsi"
-
-/ {
-	model = "Marvell Armada AP806 Quad";
-	compatible = "marvell,armada-ap806-quad", "marvell,armada-ap806";
-
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		cpu@000 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a72", "arm,armv8";
-			reg = <0x000>;
-			enable-method = "psci";
-		};
-		cpu@001 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a72", "arm,armv8";
-			reg = <0x001>;
-			enable-method = "psci";
-		};
-		cpu@100 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a72", "arm,armv8";
-			reg = <0x100>;
-			enable-method = "psci";
-		};
-		cpu@101 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a72", "arm,armv8";
-			reg = <0x101>;
-			enable-method = "psci";
-		};
-	};
-};

arch/arm/dts/armada-ap806.dtsi

@@ -1,230 +0,0 @@
-/*
- * Copyright (C) 2016 Marvell Technology Group Ltd.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPLv2 or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This library is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This library is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Device Tree file for Marvell Armada AP806.
- */
-
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-
-/dts-v1/;
-
-/ {
-	model = "Marvell Armada AP806";
-	compatible = "marvell,armada-ap806";
-	#address-cells = <2>;
-	#size-cells = <2>;
-
-	aliases {
-		serial0 = &uart0;
-		serial1 = &uart1;
-	};
-
-	psci {
-		compatible = "arm,psci-0.2";
-		method = "smc";
-	};
-
-	ap806 {
-		#address-cells = <2>;
-		#size-cells = <2>;
-		compatible = "simple-bus";
-		interrupt-parent = <&gic>;
-		ranges;
-
-		config-space {
-			#address-cells = <1>;
-			#size-cells = <1>;
-			compatible = "simple-bus";
-			ranges = <0x0 0x0 0xf0000000 0x1000000>;
-
-			gic: interrupt-controller@210000 {
-				compatible = "arm,gic-400";
-				#interrupt-cells = <3>;
-				#address-cells = <1>;
-				#size-cells = <1>;
-				ranges;
-				interrupt-controller;
-				interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
-				reg = <0x210000 0x10000>,
-				      <0x220000 0x20000>,
-				      <0x240000 0x20000>,
-				      <0x260000 0x20000>;
-
-				gic_v2m0: v2m@280000 {
-					compatible = "arm,gic-v2m-frame";
-					msi-controller;
-					reg = <0x280000 0x1000>;
-					arm,msi-base-spi = <160>;
-					arm,msi-num-spis = <32>;
-				};
-				gic_v2m1: v2m@290000 {
-					compatible = "arm,gic-v2m-frame";
-					msi-controller;
-					reg = <0x290000 0x1000>;
-					arm,msi-base-spi = <192>;
-					arm,msi-num-spis = <32>;
-				};
-				gic_v2m2: v2m@2a0000 {
-					compatible = "arm,gic-v2m-frame";
-					msi-controller;
-					reg = <0x2a0000 0x1000>;
-					arm,msi-base-spi = <224>;
-					arm,msi-num-spis = <32>;
-				};
-				gic_v2m3: v2m@2b0000 {
-					compatible = "arm,gic-v2m-frame";
-					msi-controller;
-					reg = <0x2b0000 0x1000>;
-					arm,msi-base-spi = <256>;
-					arm,msi-num-spis = <32>;
-				};
-			};
-
-			timer {
-				compatible = "arm,armv8-timer";
-				interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>,
-					     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>,
-					     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>,
-					     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
-			};
-
-			odmi: odmi@300000 {
-				compatible = "marvell,odmi-controller";
-				interrupt-controller;
-				msi-controller;
-				marvell,odmi-frames = <4>;
-				reg = <0x300000 0x4000>,
-				      <0x304000 0x4000>,
-				      <0x308000 0x4000>,
-				      <0x30C000 0x4000>;
-				marvell,spi-base = <128>, <136>, <144>, <152>;
-			};
-
-			xor@400000 {
-				compatible = "marvell,mv-xor-v2";
-				reg = <0x400000 0x1000>,
-				      <0x410000 0x1000>;
-				msi-parent = <&gic_v2m0>;
-				dma-coherent;
-			};
-
-			xor@420000 {
-				compatible = "marvell,mv-xor-v2";
-				reg = <0x420000 0x1000>,
-				      <0x430000 0x1000>;
-				msi-parent = <&gic_v2m0>;
-				dma-coherent;
-			};
-
-			xor@440000 {
-				compatible = "marvell,mv-xor-v2";
-				reg = <0x440000 0x1000>,
-				      <0x450000 0x1000>;
-				msi-parent = <&gic_v2m0>;
-				dma-coherent;
-			};
-
-			xor@460000 {
-				compatible = "marvell,mv-xor-v2";
-				reg = <0x460000 0x1000>,
-				      <0x470000 0x1000>;
-				msi-parent = <&gic_v2m0>;
-				dma-coherent;
-			};
-
-			spi0: spi@510600 {
-				compatible = "marvell,armada-380-spi";
-				reg = <0x510600 0x50>;
-				#address-cells = <1>;
-				#size-cells = <0>;
-				cell-index = <0>;
-				interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&ap_syscon 3>;
-				status = "disabled";
-			};
-
-			i2c0: i2c@511000 {
-				compatible = "marvell,mv78230-i2c";
-				reg = <0x511000 0x20>;
-				#address-cells = <1>;
-				#size-cells = <0>;
-				interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
-				timeout-ms = <1000>;
-				clocks = <&ap_syscon 3>;
-				status = "disabled";
-			};
-
-			uart0: serial@512000 {
-				compatible = "snps,dw-apb-uart";
-				reg = <0x512000 0x100>;
-				reg-shift = <2>;
-				interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
-				reg-io-width = <1>;
-				clocks = <&ap_syscon 3>;
-				status = "disabled";
-				clock-frequency = <200000000>;
-			};
-
-			uart1: serial@512100 {
-				compatible = "snps,dw-apb-uart";
-				reg = <0x512100 0x100>;
-				reg-shift = <2>;
-				interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
-				reg-io-width = <1>;
-				clocks = <&ap_syscon 3>;
-				status = "disabled";
-
-			};
-
-			ap_syscon: system-controller@6f4000 {
-				compatible = "marvell,ap806-system-controller",
-					     "syscon";
-				#clock-cells = <1>;
-				clock-output-names = "ap-cpu-cluster-0",
-						     "ap-cpu-cluster-1",
-						     "ap-fixed", "ap-mss";
-				reg = <0x6f4000 0x1000>;
-			};
-		};
-	};
-};

arch/arm/dts/armada-cp110-master.dtsi

@@ -1,256 +0,0 @@
-/*
- * Copyright (C) 2016 Marvell Technology Group Ltd.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPLv2 or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This library is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This library is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Device Tree file for Marvell Armada CP110 Master.
- */
-
-#include <dt-bindings/comphy/comphy_data.h>
-
-/ {
-	cp110-master {
-		#address-cells = <2>;
-		#size-cells = <2>;
-		compatible = "simple-bus";
-		interrupt-parent = <&gic>;
-		ranges;
-
-		config-space {
-			#address-cells = <1>;
-			#size-cells = <1>;
-			compatible = "simple-bus";
-			interrupt-parent = <&gic>;
-			ranges = <0x0 0x0 0xf2000000 0x2000000>;
-
-			cpm_syscon0: system-controller@440000 {
-				compatible = "marvell,cp110-system-controller0",
-					     "syscon";
-				reg = <0x440000 0x1000>;
-				#clock-cells = <2>;
-				core-clock-output-names =
-					"cpm-apll", "cpm-ppv2-core", "cpm-eip",
-					"cpm-core", "cpm-nand-core";
-				gate-clock-output-names =
-					"cpm-audio", "cpm-communit", "cpm-nand",
-					"cpm-ppv2", "cpm-sdio", "cpm-mg-domain",
-					"cpm-mg-core", "cpm-xor1", "cpm-xor0",
-					"cpm-gop-dp", "none", "cpm-pcie_x10",
-					"cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor",
-					"cpm-sata", "cpm-sata-usb", "cpm-main",
-					"cpm-sd-mmc", "none", "none",
-					"cpm-slow-io", "cpm-usb3h0", "cpm-usb3h1",
-					"cpm-usb3dev", "cpm-eip150", "cpm-eip197";
-			};
-
-			cpm_sata0: sata@540000 {
-				compatible = "marvell,armada-8k-ahci";
-				reg = <0x540000 0x30000>;
-				interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&cpm_syscon0 1 15>;
-				status = "disabled";
-			};
-
-			cpm_usb3_0: usb3@500000 {
-				compatible = "marvell,armada-8k-xhci",
-					     "generic-xhci";
-				reg = <0x500000 0x4000>;
-				dma-coherent;
-				interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&cpm_syscon0 1 22>;
-				status = "disabled";
-			};
-
-			cpm_usb3_1: usb3@510000 {
-				compatible = "marvell,armada-8k-xhci",
-					     "generic-xhci";
-				reg = <0x510000 0x4000>;
-				dma-coherent;
-				interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&cpm_syscon0 1 23>;
-				status = "disabled";
-			};
-
-			cpm_spi0: spi@700600 {
-				compatible = "marvell,armada-380-spi";
-				reg = <0x700600 0x50>;
-				#address-cells = <0x1>;
-				#size-cells = <0x0>;
-				cell-index = <1>;
-				clocks = <&cpm_syscon0 0 3>;
-				status = "disabled";
-			};
-
-			cpm_spi1: spi@700680 {
-				compatible = "marvell,armada-380-spi";
-				reg = <0x700680 0x50>;
-				#address-cells = <1>;
-				#size-cells = <0>;
-				cell-index = <2>;
-				clocks = <&cpm_syscon0 1 21>;
-				status = "disabled";
-			};
-
-			cpm_i2c0: i2c@701000 {
-				compatible = "marvell,mv78230-i2c";
-				reg = <0x701000 0x20>;
-				#address-cells = <1>;
-				#size-cells = <0>;
-				interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&cpm_syscon0 1 21>;
-				status = "disabled";
-			};
-
-			cpm_i2c1: i2c@701100 {
-				compatible = "marvell,mv78230-i2c";
-				reg = <0x701100 0x20>;
-				#address-cells = <1>;
-				#size-cells = <0>;
-				interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&cpm_syscon0 1 21>;
-				status = "disabled";
-			};
-
-			comphy_cp110: comphy@441000 {
-				compatible = "marvell,mvebu-comphy", "marvell,comphy-cp110";
-				reg = <0x441000 0x8>,
-				      <0x120000 0x8>;
-				mux-bitcount = <4>;
-				max-lanes = <6>;
-			};
-
-			utmi0: utmi@580000 {
-				compatible = "marvell,mvebu-utmi-2.6.0";
-				reg = <0x580000 0x1000>,	/* utmi-unit */
-				      <0x440420 0x4>,		/* usb-cfg */
-				      <0x440440 0x4>;		/* utmi-cfg */
-				utmi-port = <UTMI_PHY_TO_USB_HOST0>;
-				status = "disabled";
-			};
-
-			utmi1: utmi@581000 {
-				compatible = "marvell,mvebu-utmi-2.6.0";
-				reg = <0x581000 0x1000>,	/* utmi-unit */
-				      <0x440420 0x4>,		/* usb-cfg */
-				      <0x440444 0x4>;		/* utmi-cfg */
-				utmi-port = <UTMI_PHY_TO_USB_HOST1>;
-				status = "disabled";
-			};
-		};
-
-		cpm_pcie0: pcie@f2600000 {
-			compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
-			reg = <0 0xf2600000 0 0x10000>,
-			      <0 0xf6f00000 0 0x80000>;
-			reg-names = "ctrl", "config";
-			#address-cells = <3>;
-			#size-cells = <2>;
-			#interrupt-cells = <1>;
-			device_type = "pci";
-			dma-coherent;
-
-			bus-range = <0 0xff>;
-			ranges =
-				/* downstream I/O */
-				<0x81000000 0 0xf9000000 0  0xf9000000 0 0x10000
-				/* non-prefetchable memory */
-				0x82000000 0 0xf6000000 0  0xf6000000 0 0xf00000>;
-			interrupt-map-mask = <0 0 0 0>;
-			interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
-			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
-			num-lanes = <1>;
-			clocks = <&cpm_syscon0 1 13>;
-			status = "disabled";
-		};
-
-		cpm_pcie1: pcie@f2620000 {
-			compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
-			reg = <0 0xf2620000 0 0x10000>,
-			      <0 0xf7f00000 0 0x80000>;
-			reg-names = "ctrl", "config";
-			#address-cells = <3>;
-			#size-cells = <2>;
-			#interrupt-cells = <1>;
-			device_type = "pci";
-			dma-coherent;
-
-			bus-range = <0 0xff>;
-			ranges =
-				/* downstream I/O */
-				<0x81000000 0 0xf9010000 0  0xf9010000 0 0x10000
-				/* non-prefetchable memory */
-				0x82000000 0 0xf7000000 0  0xf7000000 0 0xf00000>;
-			interrupt-map-mask = <0 0 0 0>;
-			interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
-			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
-
-			num-lanes = <1>;
-			clocks = <&cpm_syscon0 1 11>;
-			status = "disabled";
-		};
-
-		cpm_pcie2: pcie@f2640000 {
-			compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
-			reg = <0 0xf2640000 0 0x10000>,
-			      <0 0xf8f00000 0 0x80000>;
-			reg-names = "ctrl", "config";
-			#address-cells = <3>;
-			#size-cells = <2>;
-			#interrupt-cells = <1>;
-			device_type = "pci";
-			dma-coherent;
-
-			bus-range = <0 0xff>;
-			ranges =
-				/* downstream I/O */
-				<0x81000000 0 0xf9020000 0  0xf9020000 0 0x10000
-				/* non-prefetchable memory */
-				0x82000000 0 0xf8000000 0  0xf8000000 0 0xf00000>;
-			interrupt-map-mask = <0 0 0 0>;
-			interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
-			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
-
-			num-lanes = <1>;
-			clocks = <&cpm_syscon0 1 12>;
-			status = "disabled";
-		};
-	};
-};

arch/arm/dts/fsl-ls1046a-qds-duart.dts

@@ -1,16 +0,0 @@
-/*
- * Device Tree file for Freescale Layerscape-1046A family SoC.
- *
- * Copyright (C) 2016, Freescale Semiconductor
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/dts-v1/;
-#include "fsl-ls1046a-qds.dtsi"
-
-/ {
-       chosen {
-               stdout-path = &duart0;
-       };
-};

arch/arm/dts/fsl-ls1046a-qds.dtsi

@@ -1,77 +0,0 @@
-/*
- * Device Tree Include file for Freescale Layerscape-1046A family SoC.
- *
- * Copyright (C) 2016, Freescale Semiconductor
- *
- * Mingkai Hu <Mingkai.hu@nxp.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-/include/ "fsl-ls1046a.dtsi"
-
-/ {
-	model = "LS1046A QDS Board";
-	aliases {
-		spi0 = &qspi;
-		spi1 = &dspi0;
-	};
-};
-
-&dspi0 {
-	bus-num = <0>;
-	status = "okay";
-
-	dflash0: n25q128a {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "spi-flash";
-		spi-max-frequency = <1000000>; /* input clock */
-		spi-cpol;
-		spi-cpha;
-		reg = <0>;
-	};
-
-	dflash1: sst25wf040b {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "spi-flash";
-		spi-max-frequency = <3500000>;
-		spi-cpol;
-		spi-cpha;
-		reg = <1>;
-	};
-
-	dflash2: en25s64 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "spi-flash";
-		spi-max-frequency = <3500000>;
-		spi-cpol;
-		spi-cpha;
-		reg = <2>;
-	};
-};
-
-&qspi {
-	bus-num = <0>;
-	status = "okay";
-
-	qflash0: s25fl128s@0 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "spi-flash";
-		spi-max-frequency = <20000000>;
-		reg = <0>;
-	};
-};
-
-&duart0 {
-	status = "okay";
-};
-
-&duart1 {
-	status = "okay";
-};

arch/arm/dts/fsl-ls1046a-rdb.dts

@@ -1,44 +0,0 @@
-/*
- * Device Tree Include file for Freescale Layerscape-1046A family SoC.
- *
- * Copyright 2016, Freescale Semiconductor
- *
- * Mingkai Hu <Mingkai.hu@freescale.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-/dts-v1/;
-/include/ "fsl-ls1046a.dtsi"
-
-/ {
-	model = "LS1046A RDB Board";
-
-	aliases {
-		spi0 = &qspi;
-	};
-
-};
-
-&qspi {
-	bus-num = <0>;
-	status = "okay";
-
-	qflash0: s25fs512s@0 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "spi-flash";
-		spi-max-frequency = <50000000>;
-		reg = <0>;
-	};
-
-	qflash1: s25fs512s@1 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "spi-flash";
-		spi-max-frequency = <50000000>;
-		reg = <1>;
-	 };
-};

arch/arm/dts/fsl-ls1046a.dtsi

@@ -1,166 +0,0 @@
-/*
- * Device Tree Include file for Freescale Layerscape-1046A family SoC.
- *
- * Copyright (C) 2016, Freescale Semiconductor
- *
- * Mingkai Hu <mingkai.hu@nxp.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-/include/ "skeleton64.dtsi"
-
-/ {
-	compatible = "fsl,ls1046a";
-	interrupt-parent = <&gic>;
-
-	sysclk: sysclk {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <100000000>;
-		clock-output-names = "sysclk";
-	};
-
-	gic: interrupt-controller@1400000 {
-		compatible = "arm,gic-400";
-		#interrupt-cells = <3>;
-		interrupt-controller;
-		reg = <0x0 0x1410000 0 0x10000>, /* GICD */
-		      <0x0 0x1420000 0 0x10000>, /* GICC */
-		      <0x0 0x1440000 0 0x20000>, /* GICH */
-		      <0x0 0x1460000 0 0x20000>; /* GICV */
-		interrupts = <1 9 0xf08>;
-	};
-
-	soc {
-		compatible = "simple-bus";
-		#address-cells = <2>;
-		#size-cells = <2>;
-		ranges;
-
-		clockgen: clocking@1ee1000 {
-			compatible = "fsl,ls1046a-clockgen";
-			reg = <0x0 0x1ee1000 0x0 0x1000>;
-			#clock-cells = <2>;
-			clocks = <&sysclk>;
-		};
-
-		dspi0: dspi@2100000 {
-			compatible = "fsl,vf610-dspi";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <0x0 0x2100000 0x0 0x10000>;
-			interrupts = <0 64 0x4>;
-			clock-names = "dspi";
-			clocks = <&clockgen 4 0>;
-			num-cs = <6>;
-			big-endian;
-			status = "disabled";
-		};
-
-		dspi1: dspi@2110000 {
-			compatible = "fsl,vf610-dspi";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <0x0 0x2110000 0x0 0x10000>;
-			interrupts = <0 65 0x4>;
-			clock-names = "dspi";
-			clocks = <&clockgen 4 0>;
-			num-cs = <6>;
-			big-endian;
-			status = "disabled";
-		};
-
-		ifc: ifc@1530000 {
-			compatible = "fsl,ifc", "simple-bus";
-			reg = <0x0 0x1530000 0x0 0x10000>;
-			interrupts = <0 43 0x4>;
-		};
-
-		i2c0: i2c@2180000 {
-			compatible = "fsl,vf610-i2c";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <0x0 0x2180000 0x0 0x10000>;
-			interrupts = <0 56 0x4>;
-			clock-names = "i2c";
-			clocks = <&clockgen 4 0>;
-			status = "disabled";
-		};
-
-		i2c1: i2c@2190000 {
-			compatible = "fsl,vf610-i2c";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <0x0 0x2190000 0x0 0x10000>;
-			interrupts = <0 57 0x4>;
-			clock-names = "i2c";
-			clocks = <&clockgen 4 0>;
-			status = "disabled";
-		};
-
-		i2c2: i2c@21a0000 {
-			compatible = "fsl,vf610-i2c";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <0x0 0x21a0000 0x0 0x10000>;
-			interrupts = <0 58 0x4>;
-			clock-names = "i2c";
-			clocks = <&clockgen 4 0>;
-			status = "disabled";
-		};
-
-		i2c3: i2c@21b0000 {
-			compatible = "fsl,vf610-i2c";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <0x0 0x21b0000 0x0 0x10000>;
-			interrupts = <0 59 0x4>;
-			clock-names = "i2c";
-			clocks = <&clockgen 4 0>;
-			status = "disabled";
-		};
-
-		duart0: serial@21c0500 {
-			compatible = "fsl,ns16550", "ns16550a";
-			reg = <0x00 0x21c0500 0x0 0x100>;
-			interrupts = <0 54 0x4>;
-			clocks = <&clockgen 4 0>;
-		};
-
-		duart1: serial@21c0600 {
-			compatible = "fsl,ns16550", "ns16550a";
-			reg = <0x00 0x21c0600 0x0 0x100>;
-			interrupts = <0 54 0x4>;
-			clocks = <&clockgen 4 0>;
-		};
-
-		duart2: serial@21d0500 {
-			compatible = "fsl,ns16550", "ns16550a";
-			reg = <0x0 0x21d0500 0x0 0x100>;
-			interrupts = <0 55 0x4>;
-			clocks = <&clockgen 4 0>;
-		};
-
-		duart3: serial@21d0600 {
-			compatible = "fsl,ns16550", "ns16550a";
-			reg = <0x0 0x21d0600 0x0 0x100>;
-			interrupts = <0 55 0x4>;
-			clocks = <&clockgen 4 0>;
-		};
-
-		qspi: quadspi@1550000 {
-			compatible = "fsl,vf610-qspi";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <0x0 0x1550000 0x0 0x10000>,
-				<0x0 0x40000000 0x0 0x10000000>;
-			reg-names = "QuadSPI", "QuadSPI-memory";
-			num-cs = <4>;
-			big-endian;
-			status = "disabled";
-		};
-	};
-};

arch/arm/dts/rk3288-miniarm.dtsi

@@ -116,6 +116,18 @@
 	cpu0-supply = <&vdd_cpu>;
 };
 
+&emmc {
+	broken-cd;
+	bus-width = <8>;
+	cap-mmc-highspeed;
+	disable-wp;
+	non-removable;
+	num-slots = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>;
+	status = "okay";
+};
+
 &sdmmc {
 	bus-width = <4>;
 	cap-mmc-highspeed;

arch/arm/dts/rk3399-evb.dts

@@ -23,7 +23,6 @@
 		regulator-name = "vdd_center";
 		regulator-min-microvolt = <800000>;
 		regulator-max-microvolt = <1400000>;
-		regulator-init-microvolt = <950000>;
 		regulator-always-on;
 		regulator-boot-on;
 		status = "okay";
@@ -44,12 +43,6 @@
 		regulator-always-on;
 		regulator-boot-on;
 	};
-
-	vcc5v0_host: vcc5v0-host-en {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc5v0_host";
-		gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>;
-	};
 };
 
 &emmc_phy {
@@ -92,10 +85,6 @@
 	status = "okay";
 };
 
-&dwc3_typec0 {
-	status = "okay";
-};
-
 &usb_host1_ehci {
 	status = "okay";
 };
@@ -104,10 +93,6 @@
 	status = "okay";
 };
 
-&dwc3_typec1 {
-	status = "okay";
-};
-
 &pinctrl {
 	pmic {
 		pmic_int_l: pmic-int-l {

arch/arm/dts/rk3399.dtsi

@@ -9,7 +9,6 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/pinctrl/rockchip.h>
-#define USB_CLASS_HUB			9
 
 / {
 	compatible = "rockchip,rk3399";
@@ -176,8 +175,6 @@
 		clocks = <&cru SCLK_SDMMC>, <&cru HCLK_SDMMC>,
 			 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 		clock-names = "ciu", "biu", "ciu-drive", "ciu-sample";
-		pinctrl-names = "default";
-		pinctrl-0 = <&sdmmc_clk>;
 		fifo-depth = <0x100>;
 		status = "disabled";
 	};
@@ -231,50 +228,6 @@
 		status = "disabled";
 	};
 
-	dwc3_typec0: usb@fe800000 {
-		compatible = "rockchip,rk3399-xhci";
-		reg = <0x0 0xfe800000 0x0 0x100000>;
-		status = "disabled";
-		rockchip,vbus-gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>;
-		snps,dis-enblslpm-quirk;
-		snps,phyif-utmi-bits = <16>;
-		snps,dis-u2-freeclk-exists-quirk;
-		snps,dis-u2-susphy-quirk;
-
-		#address-cells = <2>;
-		#size-cells = <2>;
-		hub {
-			compatible = "usb-hub";
-			usb,device-class = <USB_CLASS_HUB>;
-		};
-		typec_phy0 {
-			compatible = "rockchip,rk3399-usb3-phy";
-			reg = <0x0 0xff7c0000 0x0 0x40000>;
-		};
-	};
-
-	dwc3_typec1: usb@fe900000 {
-		compatible = "rockchip,rk3399-xhci";
-		reg = <0x0 0xfe900000 0x0 0x100000>;
-		status = "disabled";
-		rockchip,vbus-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
-		snps,dis-enblslpm-quirk;
-		snps,phyif-utmi-bits = <16>;
-		snps,dis-u2-freeclk-exists-quirk;
-		snps,dis-u2-susphy-quirk;
-
-		#address-cells = <2>;
-		#size-cells = <2>;
-		hub {
-			compatible = "usb-hub";
-			usb,device-class = <USB_CLASS_HUB>;
-		};
-		typec_phy1 {
-			compatible = "rockchip,rk3399-usb3-phy";
-			reg = <0x0 0xff800000 0x0 0x40000>;
-		};
-	};
-
 	gic: interrupt-controller@fee00000 {
 		compatible = "arm,gic-v3";
 		#interrupt-cells = <3>;
@@ -818,41 +771,6 @@
 			};
 		};
 
-		sdmmc {
-			sdmmc_bus1: sdmmc-bus1 {
-				rockchip,pins =
-					<4 8 RK_FUNC_1 &pcfg_pull_up>;
-			};
-
-			sdmmc_bus4: sdmmc-bus4 {
-				rockchip,pins =
-					<4 8 RK_FUNC_1 &pcfg_pull_up>,
-					<4 9 RK_FUNC_1 &pcfg_pull_up>,
-					<4 10 RK_FUNC_1 &pcfg_pull_up>,
-					<4 11 RK_FUNC_1 &pcfg_pull_up>;
-			};
-
-			sdmmc_clk: sdmmc-clk {
-				rockchip,pins =
-					<4 12 RK_FUNC_1 &pcfg_pull_none>;
-			};
-
-			sdmmc_cmd: sdmmc-cmd {
-				rockchip,pins =
-					<4 13 RK_FUNC_1 &pcfg_pull_up>;
-			};
-
-			sdmmc_cd: sdmcc-cd {
-				rockchip,pins =
-					<0 7 RK_FUNC_1 &pcfg_pull_up>;
-			};
-
-			sdmmc_wp: sdmmc-wp {
-				rockchip,pins =
-					<0 8 RK_FUNC_1 &pcfg_pull_up>;
-			};
-		};
-
 		spdif {
 			spdif_bus: spdif-bus {
 				rockchip,pins =

arch/arm/dts/sun8i-h3-nanopi-neo.dts

@@ -1,125 +0,0 @@
-/*
- * Copyright (C) 2016 James Pettigrew <james@innovum.com.au>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/dts-v1/;
-#include "sun8i-h3.dtsi"
-#include "sunxi-common-regulators.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
-
-/ {
-	model = "FriendlyARM NanoPi NEO";
-	compatible = "friendlyarm,nanopi-neo", "allwinner,sun8i-h3";
-
-	aliases {
-		serial0 = &uart0;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	leds {
-		compatible = "gpio-leds";
-		pinctrl-names = "default";
-		pinctrl-0 = <&leds_opc>, <&leds_r_opc>;
-
-		pwr {
-			label = "nanopi:green:pwr";
-			gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */
-			default-state = "on";
-		};
-
-		status {
-			label = "nanopi:blue:status";
-			gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; /* PA10 */
-		};
-	};
-};
-
-&ehci3 {
-	status = "okay";
-};
-
-&mmc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
-	vmmc-supply = <&reg_vcc3v3>;
-	bus-width = <4>;
-	cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
-	cd-inverted;
-	status = "okay";
-};
-
-&ohci3 {
-	status = "okay";
-};
-
-&pio {
-	leds_opc: led-pins {
-		allwinner,pins = "PA10";
-		allwinner,function = "gpio_out";
-		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
-	};
-};
-
-&r_pio {
-	leds_r_opc: led-pins {
-		allwinner,pins = "PL10";
-		allwinner,function = "gpio_out";
-		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
-	};
-};
-
-&uart0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart0_pins_a>;
-	status = "okay";
-};
-
-&usbphy {
-	/* USB VBUS is always on */
-	status = "okay";
-};

arch/arm/dts/tegra114-dalmore.dts

@@ -16,8 +16,8 @@
 		i2c2 = "/i2c@7000c400";
 		i2c3 = "/i2c@7000c500";
 		i2c4 = "/i2c@7000c700";
-		mmc0 = "/sdhci@78000600";
-		mmc1 = "/sdhci@78000400";
+		sdhci0 = "/sdhci@78000600";
+		sdhci1 = "/sdhci@78000400";
 		usb0 = "/usb@7d000000";
 		usb1 = "/usb@7d008000";
 	};
@@ -66,7 +66,6 @@
 	sdhci@78000600 {
 		bus-width = <8>;
 		status = "okay";
-		non-removable;
 	};
 
 	usb@7d000000 {
@@ -79,17 +78,4 @@
 		nvidia,vbus-gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
 		status = "okay";
 	};
-
-	clocks {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		clk32k_in: clock@0 {
-			compatible = "fixed-clock";
-			reg=<0>;
-			#clock-cells = <0>;
-			clock-frequency = <32768>;
-		};
-	};
 };

arch/arm/dts/tegra114.dtsi

@@ -1,222 +1,53 @@
 #include <dt-bindings/clock/tegra114-car.h>
 #include <dt-bindings/gpio/tegra-gpio.h>
-#include <dt-bindings/memory/tegra114-mc.h>
-#include <dt-bindings/pinctrl/pinctrl-tegra.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 
 #include "skeleton.dtsi"
 
 / {
 	compatible = "nvidia,tegra114";
-	interrupt-parent = <&lic>;
 
-	host1x@50000000 {
-		compatible = "nvidia,tegra114-host1x", "simple-bus";
-		reg = <0x50000000 0x00028000>;
-		interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
-			     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
-		clocks = <&tegra_car TEGRA114_CLK_HOST1X>;
-		resets = <&tegra_car 28>;
-		reset-names = "host1x";
-
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-		ranges = <0x54000000 0x54000000 0x01000000>;
-
-		gr2d@54140000 {
-			compatible = "nvidia,tegra114-gr2d", "nvidia,tegra20-gr2d";
-			reg = <0x54140000 0x00040000>;
-			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&tegra_car TEGRA114_CLK_GR2D>;
-			resets = <&tegra_car 21>;
-			reset-names = "2d";
-		};
-
-		gr3d@54180000 {
-			compatible = "nvidia,tegra114-gr3d", "nvidia,tegra20-gr3d";
-			reg = <0x54180000 0x00040000>;
-			clocks = <&tegra_car TEGRA114_CLK_GR3D>;
-			resets = <&tegra_car 24>;
-			reset-names = "3d";
-		};
-
-		dc@54200000 {
-			compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc";
-			reg = <0x54200000 0x00040000>;
-			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&tegra_car TEGRA114_CLK_DISP1>,
-				 <&tegra_car TEGRA114_CLK_PLL_P>;
-			clock-names = "dc", "parent";
-			resets = <&tegra_car 27>;
-			reset-names = "dc";
-
-			iommus = <&mc TEGRA_SWGROUP_DC>;
-
-			nvidia,head = <0>;
-
-			rgb {
-				status = "disabled";
-			};
-		};
-
-		dc@54240000 {
-			compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc";
-			reg = <0x54240000 0x00040000>;
-			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&tegra_car TEGRA114_CLK_DISP2>,
-				 <&tegra_car TEGRA114_CLK_PLL_P>;
-			clock-names = "dc", "parent";
-			resets = <&tegra_car 26>;
-			reset-names = "dc";
-
-			iommus = <&mc TEGRA_SWGROUP_DCB>;
-
-			nvidia,head = <1>;
-
-			rgb {
-				status = "disabled";
-			};
-		};
-
-		hdmi@54280000 {
-			compatible = "nvidia,tegra114-hdmi";
-			reg = <0x54280000 0x00040000>;
-			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&tegra_car TEGRA114_CLK_HDMI>,
-				 <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>;
-			clock-names = "hdmi", "parent";
-			resets = <&tegra_car 51>;
-			reset-names = "hdmi";
-			status = "disabled";
-		};
-
-		dsi@54300000 {
-			compatible = "nvidia,tegra114-dsi";
-			reg = <0x54300000 0x00040000>;
-			clocks = <&tegra_car TEGRA114_CLK_DSIA>,
-				 <&tegra_car TEGRA114_CLK_DSIALP>,
-				 <&tegra_car TEGRA114_CLK_PLL_D_OUT0>;
-			clock-names = "dsi", "lp", "parent";
-			resets = <&tegra_car 48>;
-			reset-names = "dsi";
-			nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */
-			status = "disabled";
-
-			#address-cells = <1>;
-			#size-cells = <0>;
-		};
-
-		dsi@54400000 {
-			compatible = "nvidia,tegra114-dsi";
-			reg = <0x54400000 0x00040000>;
-			clocks = <&tegra_car TEGRA114_CLK_DSIB>,
-				 <&tegra_car TEGRA114_CLK_DSIBLP>,
-				 <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>;
-			clock-names = "dsi", "lp", "parent";
-			resets = <&tegra_car 82>;
-			reset-names = "dsi";
-			nvidia,mipi-calibrate = <&mipi 0x180>; /* DSIC & DSID pads */
-			status = "disabled";
-
-			#address-cells = <1>;
-			#size-cells = <0>;
-		};
-	};
-
-	gic: interrupt-controller@50041000 {
-		compatible = "arm,cortex-a15-gic";
-		#interrupt-cells = <3>;
-		interrupt-controller;
-		reg = <0x50041000 0x1000>,
-		      <0x50042000 0x1000>,
-		      <0x50044000 0x2000>,
-		      <0x50046000 0x2000>;
-		interrupts = <GIC_PPI 9
-			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
-		interrupt-parent = <&gic>;
-	};
-
-	lic: interrupt-controller@60004000 {
-		compatible = "nvidia,tegra114-ictlr", "nvidia,tegra30-ictlr";
-		reg = <0x60004000 0x100>,
-		      <0x60004100 0x50>,
-		      <0x60004200 0x50>,
-		      <0x60004300 0x50>,
-		      <0x60004400 0x50>;
-		interrupt-controller;
-		#interrupt-cells = <3>;
-		interrupt-parent = <&gic>;
-	};
-
-	timer@60005000 {
-		compatible = "nvidia,tegra114-timer", "nvidia,tegra30-timer", "nvidia,tegra20-timer";
-		reg = <0x60005000 0x400>;
-		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car TEGRA114_CLK_TIMER>;
-	};
-
-	tegra_car: clock@60006000 {
+	tegra_car: clock {
 		compatible = "nvidia,tegra114-car";
 		reg = <0x60006000 0x1000>;
 		#clock-cells = <1>;
-		#reset-cells = <1>;
 	};
 
-	flow-controller@60007000 {
-		compatible = "nvidia,tegra114-flowctrl";
-		reg = <0x60007000 0x1000>;
-	};
-
-	apbdma: dma@6000a000 {
-		compatible = "nvidia,tegra114-apbdma";
+	apbdma: dma {
+		compatible = "nvidia,tegra114-apbdma", "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
 		reg = <0x6000a000 0x1400>;
-		interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car TEGRA114_CLK_APBDMA>;
-		resets = <&tegra_car 34>;
-		reset-names = "dma";
-		#dma-cells = <1>;
-	};
-
-	ahb: ahb@6000c000 {
-		compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb";
-		reg = <0x6000c000 0x150>;
+		interrupts = <0 104 0x04
+			      0 105 0x04
+			      0 106 0x04
+			      0 107 0x04
+			      0 108 0x04
+			      0 109 0x04
+			      0 110 0x04
+			      0 111 0x04
+			      0 112 0x04
+			      0 113 0x04
+			      0 114 0x04
+			      0 115 0x04
+			      0 116 0x04
+			      0 117 0x04
+			      0 118 0x04
+			      0 119 0x04
+			      0 128 0x04
+			      0 129 0x04
+			      0 130 0x04
+			      0 131 0x04
+			      0 132 0x04
+			      0 133 0x04
+			      0 134 0x04
+			      0 135 0x04
+			      0 136 0x04
+			      0 137 0x04
+			      0 138 0x04
+			      0 139 0x04
+			      0 140 0x04
+			      0 141 0x04
+			      0 142 0x04
+			      0 143 0x04>;
 	};
 
 	gpio: gpio@6000d000 {
@@ -234,31 +65,58 @@
 		gpio-controller;
 		#interrupt-cells = <2>;
 		interrupt-controller;
-		/*
-		gpio-ranges = <&pinmux 0 0 246>;
-		*/
 	};
 
-	apbmisc@70000800 {
-		compatible = "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc";
-		reg = <0x70000800 0x64   /* Chip revision */
-		       0x70000008 0x04>; /* Strapping options */
+	i2c@7000c000 {
+		compatible = "nvidia,tegra114-i2c";
+		reg = <0x7000c000 0x100>;
+		interrupts = <0 38 0x04>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car 12>;
+		status = "disabled";
 	};
 
-	pinmux: pinmux@70000868 {
-		compatible = "nvidia,tegra114-pinmux";
-		reg = <0x70000868 0x148		/* Pad control registers */
-		       0x70003000 0x40c>;	/* Mux registers */
+	i2c@7000c400 {
+		compatible = "nvidia,tegra114-i2c";
+		reg = <0x7000c400 0x100>;
+		interrupts = <0 84 0x04>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car 54>;
+		status = "disabled";
+	};
+
+	i2c@7000c500 {
+		compatible = "nvidia,tegra114-i2c";
+		reg = <0x7000c500 0x100>;
+		interrupts = <0 92 0x04>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car 67>;
+		status = "disabled";
+	};
+
+	i2c@7000c700 {
+		compatible = "nvidia,tegra114-i2c";
+		reg = <0x7000c700 0x100>;
+		interrupts = <0 120 0x04>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car 103>;
+		status = "disabled";
+	};
+
+	i2c@7000d000 {
+		compatible = "nvidia,tegra114-i2c";
+		reg = <0x7000d000 0x100>;
+		interrupts = <0 53 0x04>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car 47>;
+		status = "disabled";
 	};
 
-	/*
-	 * There are two serial driver i.e. 8250 based simple serial
-	 * driver and APB DMA based serial driver for higher baudrate
-	 * and performace. To enable the 8250 based driver, the compatible
-	 * is "nvidia,tegra114-uart", "nvidia,tegra20-uart" and to enable
-	 * the APB DMA based serial driver, the compatible is
-	 * "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart".
-	 */
 	uarta: serial@70006000 {
 		compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
 		reg = <0x70006000 0x40>;
@@ -311,477 +169,134 @@
 		status = "disabled";
 	};
 
-	pwm: pwm@7000a000 {
-		compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm";
-		reg = <0x7000a000 0x100>;
-		#pwm-cells = <2>;
-		clocks = <&tegra_car TEGRA114_CLK_PWM>;
-		resets = <&tegra_car 17>;
-		reset-names = "pwm";
-		status = "disabled";
-	};
-
-	i2c@7000c000 {
-		compatible = "nvidia,tegra114-i2c";
-		reg = <0x7000c000 0x100>;
-		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		clocks = <&tegra_car TEGRA114_CLK_I2C1>;
-		clock-names = "div-clk";
-		resets = <&tegra_car 12>;
-		reset-names = "i2c";
-		dmas = <&apbdma 21>, <&apbdma 21>;
-		dma-names = "rx", "tx";
-		status = "disabled";
-	};
-
-	i2c@7000c400 {
-		compatible = "nvidia,tegra114-i2c";
-		reg = <0x7000c400 0x100>;
-		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		clocks = <&tegra_car TEGRA114_CLK_I2C2>;
-		clock-names = "div-clk";
-		resets = <&tegra_car 54>;
-		reset-names = "i2c";
-		dmas = <&apbdma 22>, <&apbdma 22>;
-		dma-names = "rx", "tx";
-		status = "disabled";
-	};
-
-	i2c@7000c500 {
-		compatible = "nvidia,tegra114-i2c";
-		reg = <0x7000c500 0x100>;
-		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		clocks = <&tegra_car TEGRA114_CLK_I2C3>;
-		clock-names = "div-clk";
-		resets = <&tegra_car 67>;
-		reset-names = "i2c";
-		dmas = <&apbdma 23>, <&apbdma 23>;
-		dma-names = "rx", "tx";
-		status = "disabled";
-	};
-
-	i2c@7000c700 {
-		compatible = "nvidia,tegra114-i2c";
-		reg = <0x7000c700 0x100>;
-		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		clocks = <&tegra_car TEGRA114_CLK_I2C4>;
-		clock-names = "div-clk";
-		resets = <&tegra_car 103>;
-		reset-names = "i2c";
-		dmas = <&apbdma 26>, <&apbdma 26>;
-		dma-names = "rx", "tx";
-		status = "disabled";
-	};
-
-	i2c@7000d000 {
-		compatible = "nvidia,tegra114-i2c";
-		reg = <0x7000d000 0x100>;
-		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		clocks = <&tegra_car TEGRA114_CLK_I2C5>;
-		clock-names = "div-clk";
-		resets = <&tegra_car 47>;
-		reset-names = "i2c";
-		dmas = <&apbdma 24>, <&apbdma 24>;
-		dma-names = "rx", "tx";
-		status = "disabled";
-	};
-
 	spi@7000d400 {
 		compatible = "nvidia,tegra114-spi";
 		reg = <0x7000d400 0x200>;
-		interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <0 59 0x04>;
+		nvidia,dma-request-selector = <&apbdma 15>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car TEGRA114_CLK_SBC1>;
-		clock-names = "spi";
-		resets = <&tegra_car 41>;
-		reset-names = "spi";
-		dmas = <&apbdma 15>, <&apbdma 15>;
-		dma-names = "rx", "tx";
 		status = "disabled";
+		/* PERIPH_ID_SBC1, PLLP_OUT0 */
+		clocks = <&tegra_car 41>;
 	};
 
 	spi@7000d600 {
 		compatible = "nvidia,tegra114-spi";
 		reg = <0x7000d600 0x200>;
-		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <0 82 0x04>;
+		nvidia,dma-request-selector = <&apbdma 16>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car TEGRA114_CLK_SBC2>;
-		clock-names = "spi";
-		resets = <&tegra_car 44>;
-		reset-names = "spi";
-		dmas = <&apbdma 16>, <&apbdma 16>;
-		dma-names = "rx", "tx";
 		status = "disabled";
+		/* PERIPH_ID_SBC2, PLLP_OUT0 */
+		clocks = <&tegra_car 44>;
 	};
 
 	spi@7000d800 {
 		compatible = "nvidia,tegra114-spi";
 		reg = <0x7000d800 0x200>;
-		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <0 83 0x04>;
+		nvidia,dma-request-selector = <&apbdma 17>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car TEGRA114_CLK_SBC3>;
-		clock-names = "spi";
-		resets = <&tegra_car 46>;
-		reset-names = "spi";
-		dmas = <&apbdma 17>, <&apbdma 17>;
-		dma-names = "rx", "tx";
 		status = "disabled";
+		/* PERIPH_ID_SBC3, PLLP_OUT0 */
+		clocks = <&tegra_car 46>;
 	};
 
 	spi@7000da00 {
 		compatible = "nvidia,tegra114-spi";
 		reg = <0x7000da00 0x200>;
-		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <0 93 0x04>;
+		nvidia,dma-request-selector = <&apbdma 18>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car TEGRA114_CLK_SBC4>;
-		clock-names = "spi";
-		resets = <&tegra_car 68>;
-		reset-names = "spi";
-		dmas = <&apbdma 18>, <&apbdma 18>;
-		dma-names = "rx", "tx";
 		status = "disabled";
+		/* PERIPH_ID_SBC4, PLLP_OUT0 */
+		clocks = <&tegra_car 68>;
 	};
 
 	spi@7000dc00 {
 		compatible = "nvidia,tegra114-spi";
 		reg = <0x7000dc00 0x200>;
-		interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <0 94 0x04>;
+		nvidia,dma-request-selector = <&apbdma 27>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car TEGRA114_CLK_SBC5>;
-		clock-names = "spi";
-		resets = <&tegra_car 104>;
-		reset-names = "spi";
-		dmas = <&apbdma 27>, <&apbdma 27>;
-		dma-names = "rx", "tx";
 		status = "disabled";
+		/* PERIPH_ID_SBC5, PLLP_OUT0 */
+		clocks = <&tegra_car 104>;
 	};
 
 	spi@7000de00 {
 		compatible = "nvidia,tegra114-spi";
 		reg = <0x7000de00 0x200>;
-		interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <0 79 0x04>;
+		nvidia,dma-request-selector = <&apbdma 28>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car TEGRA114_CLK_SBC6>;
-		clock-names = "spi";
-		resets = <&tegra_car 105>;
-		reset-names = "spi";
-		dmas = <&apbdma 28>, <&apbdma 28>;
-		dma-names = "rx", "tx";
 		status = "disabled";
-	};
-
-	rtc@7000e000 {
-		compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
-		reg = <0x7000e000 0x100>;
-		interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car TEGRA114_CLK_RTC>;
-	};
-
-	kbc@7000e200 {
-		compatible = "nvidia,tegra114-kbc";
-		reg = <0x7000e200 0x100>;
-		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car TEGRA114_CLK_KBC>;
-		resets = <&tegra_car 36>;
-		reset-names = "kbc";
-		status = "disabled";
-	};
-
-	pmc@7000e400 {
-		compatible = "nvidia,tegra114-pmc";
-		reg = <0x7000e400 0x400>;
-		clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>;
-		clock-names = "pclk", "clk32k_in";
-	};
-
-	fuse@7000f800 {
-		compatible = "nvidia,tegra114-efuse";
-		reg = <0x7000f800 0x400>;
-		clocks = <&tegra_car TEGRA114_CLK_FUSE>;
-		clock-names = "fuse";
-		resets = <&tegra_car 39>;
-		reset-names = "fuse";
-	};
-
-	mc: memory-controller@70019000 {
-		compatible = "nvidia,tegra114-mc";
-		reg = <0x70019000 0x1000>;
-		clocks = <&tegra_car TEGRA114_CLK_MC>;
-		clock-names = "mc";
-
-		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
-
-		#iommu-cells = <1>;
-	};
-
-	ahub@70080000 {
-		compatible = "nvidia,tegra114-ahub";
-		reg = <0x70080000 0x200>,
-		      <0x70080200 0x100>,
-		      <0x70081000 0x200>;
-		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car TEGRA114_CLK_D_AUDIO>,
-			 <&tegra_car TEGRA114_CLK_APBIF>;
-		clock-names = "d_audio", "apbif";
-		resets = <&tegra_car 106>, /* d_audio */
-			 <&tegra_car 107>, /* apbif */
-			 <&tegra_car 30>,  /* i2s0 */
-			 <&tegra_car 11>,  /* i2s1 */
-			 <&tegra_car 18>,  /* i2s2 */
-			 <&tegra_car 101>, /* i2s3 */
-			 <&tegra_car 102>, /* i2s4 */
-			 <&tegra_car 108>, /* dam0 */
-			 <&tegra_car 109>, /* dam1 */
-			 <&tegra_car 110>, /* dam2 */
-			 <&tegra_car 10>,  /* spdif */
-			 <&tegra_car 153>, /* amx */
-			 <&tegra_car 154>; /* adx */
-		reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
-			      "i2s3", "i2s4", "dam0", "dam1", "dam2",
-			      "spdif", "amx", "adx";
-		dmas = <&apbdma 1>, <&apbdma 1>,
-		       <&apbdma 2>, <&apbdma 2>,
-		       <&apbdma 3>, <&apbdma 3>,
-		       <&apbdma 4>, <&apbdma 4>,
-		       <&apbdma 6>, <&apbdma 6>,
-		       <&apbdma 7>, <&apbdma 7>,
-		       <&apbdma 12>, <&apbdma 12>,
-		       <&apbdma 13>, <&apbdma 13>,
-		       <&apbdma 14>, <&apbdma 14>,
-		       <&apbdma 29>, <&apbdma 29>;
-		dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
-			    "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
-			    "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
-			    "rx9", "tx9";
-		ranges;
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-		tegra_i2s0: i2s@70080300 {
-			compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
-			reg = <0x70080300 0x100>;
-			nvidia,ahub-cif-ids = <4 4>;
-			clocks = <&tegra_car TEGRA114_CLK_I2S0>;
-			resets = <&tegra_car 30>;
-			reset-names = "i2s";
-			status = "disabled";
-		};
-
-		tegra_i2s1: i2s@70080400 {
-			compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
-			reg = <0x70080400 0x100>;
-			nvidia,ahub-cif-ids = <5 5>;
-			clocks = <&tegra_car TEGRA114_CLK_I2S1>;
-			resets = <&tegra_car 11>;
-			reset-names = "i2s";
-			status = "disabled";
-		};
-
-		tegra_i2s2: i2s@70080500 {
-			compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
-			reg = <0x70080500 0x100>;
-			nvidia,ahub-cif-ids = <6 6>;
-			clocks = <&tegra_car TEGRA114_CLK_I2S2>;
-			resets = <&tegra_car 18>;
-			reset-names = "i2s";
-			status = "disabled";
-		};
-
-		tegra_i2s3: i2s@70080600 {
-			compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
-			reg = <0x70080600 0x100>;
-			nvidia,ahub-cif-ids = <7 7>;
-			clocks = <&tegra_car TEGRA114_CLK_I2S3>;
-			resets = <&tegra_car 101>;
-			reset-names = "i2s";
-			status = "disabled";
-		};
-
-		tegra_i2s4: i2s@70080700 {
-			compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
-			reg = <0x70080700 0x100>;
-			nvidia,ahub-cif-ids = <8 8>;
-			clocks = <&tegra_car TEGRA114_CLK_I2S4>;
-			resets = <&tegra_car 102>;
-			reset-names = "i2s";
-			status = "disabled";
-		};
-	};
-
-	mipi: mipi@700e3000 {
-		compatible = "nvidia,tegra114-mipi";
-		reg = <0x700e3000 0x100>;
-		clocks = <&tegra_car TEGRA114_CLK_MIPI_CAL>;
-		#nvidia,mipi-calibrate-cells = <1>;
+		/* PERIPH_ID_SBC6, PLLP_OUT0 */
+		clocks = <&tegra_car 105>;
 	};
 
 	sdhci@78000000 {
 		compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
 		reg = <0x78000000 0x200>;
-		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car TEGRA114_CLK_SDMMC1>;
-		resets = <&tegra_car 14>;
-		reset-names = "sdhci";
-		status = "disabled";
+		interrupts = <0 14 0x04>;
+		clocks = <&tegra_car 14>;
+		status = "disable";
 	};
 
 	sdhci@78000200 {
 		compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
 		reg = <0x78000200 0x200>;
-		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car TEGRA114_CLK_SDMMC2>;
-		resets = <&tegra_car 9>;
-		reset-names = "sdhci";
-		status = "disabled";
+		interrupts = <0 15 0x04>;
+		clocks = <&tegra_car 9>;
+		status = "disable";
 	};
 
 	sdhci@78000400 {
 		compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
 		reg = <0x78000400 0x200>;
-		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car TEGRA114_CLK_SDMMC3>;
-		resets = <&tegra_car 69>;
-		reset-names = "sdhci";
-		status = "disabled";
+		interrupts = <0 19 0x04>;
+		clocks = <&tegra_car 69>;
+		status = "disable";
 	};
 
 	sdhci@78000600 {
 		compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
 		reg = <0x78000600 0x200>;
-		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&tegra_car TEGRA114_CLK_SDMMC4>;
-		resets = <&tegra_car 15>;
-		reset-names = "sdhci";
-		status = "disabled";
+		interrupts = <0 31 0x04>;
+		clocks = <&tegra_car 15>;
+		status = "disable";
 	};
 
 	usb@7d000000 {
-		compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci", "usb-ehci";
+		compatible = "nvidia,tegra114-ehci";
 		reg = <0x7d000000 0x4000>;
-		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <52>;
 		phy_type = "utmi";
-		clocks = <&tegra_car TEGRA114_CLK_USBD>;
-		resets = <&tegra_car 22>;
-		reset-names = "usb";
-		nvidia,phy = <&phy1>;
+		clocks = <&tegra_car 22>;	/* PERIPH_ID_USBD */
 		status = "disabled";
 	};
 
-	phy1: usb-phy@7d000000 {
-		compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy";
-		reg = <0x7d000000 0x4000 0x7d000000 0x4000>;
-		phy_type = "utmi";
-		clocks = <&tegra_car TEGRA114_CLK_USBD>,
-			 <&tegra_car TEGRA114_CLK_PLL_U>,
-			 <&tegra_car TEGRA114_CLK_USBD>;
-		clock-names = "reg", "pll_u", "utmi-pads";
-		resets = <&tegra_car 22>, <&tegra_car 22>;
-		reset-names = "usb", "utmi-pads";
-		nvidia,hssync-start-delay = <0>;
-		nvidia,idle-wait-delay = <17>;
-		nvidia,elastic-limit = <16>;
-		nvidia,term-range-adj = <6>;
-		nvidia,xcvr-setup = <9>;
-		nvidia,xcvr-lsfslew = <0>;
-		nvidia,xcvr-lsrslew = <3>;
-		nvidia,hssquelch-level = <2>;
-		nvidia,hsdiscon-level = <5>;
-		nvidia,xcvr-hsslew = <12>;
-		nvidia,has-utmi-pad-registers;
+	usb@7d004000 {
+		compatible = "nvidia,tegra114-ehci";
+		reg = <0x7d004000 0x4000>;
+		interrupts = <53>;
+		phy_type = "hsic";
+		clocks = <&tegra_car 58>;	/* PERIPH_ID_USB2 */
 		status = "disabled";
 	};
 
 	usb@7d008000 {
-		compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci", "usb-ehci";
+		compatible = "nvidia,tegra114-ehci";
 		reg = <0x7d008000 0x4000>;
-		interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <129>;
 		phy_type = "utmi";
-		clocks = <&tegra_car TEGRA114_CLK_USB3>;
-		resets = <&tegra_car 59>;
-		reset-names = "usb";
-		nvidia,phy = <&phy3>;
+		clocks = <&tegra_car 59>;	/* PERIPH_ID_USB3 */
 		status = "disabled";
 	};
-
-	phy3: usb-phy@7d008000 {
-		compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy";
-		reg = <0x7d008000 0x4000 0x7d000000 0x4000>;
-		phy_type = "utmi";
-		clocks = <&tegra_car TEGRA114_CLK_USB3>,
-			 <&tegra_car TEGRA114_CLK_PLL_U>,
-			 <&tegra_car TEGRA114_CLK_USBD>;
-		clock-names = "reg", "pll_u", "utmi-pads";
-		resets = <&tegra_car 59>, <&tegra_car 22>;
-		reset-names = "usb", "utmi-pads";
-		nvidia,hssync-start-delay = <0>;
-		nvidia,idle-wait-delay = <17>;
-		nvidia,elastic-limit = <16>;
-		nvidia,term-range-adj = <6>;
-		nvidia,xcvr-setup = <9>;
-		nvidia,xcvr-lsfslew = <0>;
-		nvidia,xcvr-lsrslew = <3>;
-		nvidia,hssquelch-level = <2>;
-		nvidia,hsdiscon-level = <5>;
-		nvidia,xcvr-hsslew = <12>;
-		status = "disabled";
-	};
-
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		cpu@0 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a15";
-			reg = <0>;
-		};
-
-		cpu@1 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a15";
-			reg = <1>;
-		};
-
-		cpu@2 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a15";
-			reg = <2>;
-		};
-
-		cpu@3 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a15";
-			reg = <3>;
-		};
-	};
-
-	timer {
-		compatible = "arm,armv7-timer";
-		interrupts =
-			<GIC_PPI 13
-				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 14
-				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 11
-				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 10
-				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
-		interrupt-parent = <&gic>;
-	};
 };

arch/arm/dts/tegra124-cei-tk1-som.dts

@@ -16,8 +16,8 @@
 		i2c2 = "/i2c@7000c400";
 		i2c3 = "/i2c@7000c500";
 		i2c4 = "/i2c@7000c700";
-		mmc0 = "/sdhci@700b0600";
-		mmc1 = "/sdhci@700b0400";
+		sdhci0 = "/sdhci@700b0600";
+		sdhci1 = "/sdhci@700b0400";
 		spi0 = "/spi@7000d400";
 		spi1 = "/spi@7000da00";
 		usb0 = "/usb@7d000000";

arch/arm/dts/tegra124-jetson-tk1.dts

@@ -16,8 +16,8 @@
 		i2c2 = "/i2c@7000c400";
 		i2c3 = "/i2c@7000c500";
 		i2c4 = "/i2c@7000c700";
-		mmc0 = "/sdhci@700b0600";
-		mmc1 = "/sdhci@700b0400";
+		sdhci0 = "/sdhci@700b0600";
+		sdhci1 = "/sdhci@700b0400";
 		spi0 = "/spi@7000d400";
 		spi1 = "/spi@7000da00";
 		usb0 = "/usb@7d000000";
@@ -312,7 +312,6 @@
 	sdhci@700b0600 {
 		status = "okay";
 		bus-width = <8>;
-		non-removable;
 	};
 
 	usb@7d000000 {

arch/arm/dts/tegra124-nyan-big.dts

@@ -15,10 +15,10 @@
 		i2c3 = "/i2c@7000c500";
 		i2c4 = "/i2c@7000c700";
 		i2c5 = "/i2c@7000d100";
-		rtc0 = "/i2c@7000d000/pmic@40";
-		rtc1 = "/rtc@7000e000";
-		mmc0 = "/sdhci@700b0600";
-		mmc1 = "/sdhci@700b0400";
+		rtc0 = "/i2c@0,7000d000/pmic@40";
+		rtc1 = "/rtc@0,7000e000";
+		sdhci0 = "/sdhci@700b0600";
+		sdhci1 = "/sdhci@700b0400";
 		spi0 = "/spi@7000d400";
 		spi1 = "/spi@7000da00";
 		usb0 = "/usb@7d000000";
@@ -58,7 +58,7 @@
 		ddc-i2c-bus = <&dpaux>;
 	};
 
-	sdhci@700b0400 { /* SD Card on this bus */
+	sdhci@0,700b0400 { /* SD Card on this bus */
 		wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
 	};
 
@@ -69,7 +69,7 @@
 		nvidia,model = "GoogleNyanBig";
 	};
 
-	pinmux@70000868 {
+	pinmux@0,70000868 {
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinmux_default>;
 

arch/arm/dts/tegra124-nyan.dtsi

@@ -3,8 +3,8 @@
 
 / {
 	aliases {
-		rtc0 = "/i2c@7000d000/pmic@40";
-		rtc1 = "/rtc@7000e000";
+		rtc0 = "/i2c@0,7000d000/pmic@40";
+		rtc1 = "/rtc@0,7000e000";
 		serial0 = &uarta;
 	};
 
@@ -424,12 +424,10 @@
 
 	usb@7d004000 { /* Internal webcam. */
 		status = "okay";
-		phy_type = "hsic";
 	};
 
 	usb-phy@7d004000 {
 		status = "okay";
-		phy_type = "hsic";
 		vbus-supply = <&vdd_run_cam>;
 	};
 

arch/arm/dts/tegra124-venice2.dts

@@ -17,8 +17,8 @@
 		i2c3 = "/i2c@7000c500";
 		i2c4 = "/i2c@7000c700";
 		i2c5 = "/i2c@7000d100";
-		mmc0 = "/sdhci@700b0600";
-		mmc1 = "/sdhci@700b0400";
+		sdhci0 = "/sdhci@700b0600";
+		sdhci1 = "/sdhci@700b0400";
 		spi0 = "/spi@7000d400";
 		spi1 = "/spi@7000da00";
 		usb0 = "/usb@7d000000";
@@ -81,7 +81,6 @@
 	sdhci@700b0600 {
 		status = "okay";
 		bus-width = <8>;
-		non-removable;
 	};
 
 	usb@7d000000 {

arch/arm/dts/tegra124.dtsi

@@ -196,18 +196,13 @@
 
 	lic: interrupt-controller@60004000 {
 		compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr";
-		reg = <0x0 0x60004000 0x0 0x100>,
-		      <0x0 0x60004100 0x0 0x100>,
-		      <0x0 0x60004200 0x0 0x100>,
-		      <0x0 0x60004300 0x0 0x100>,
-		      <0x0 0x60004400 0x0 0x100>;
 		interrupt-controller;
 		#interrupt-cells = <3>;
 		interrupt-parent = <&gic>;
 	};
 
 	timer@60005000 {
-		compatible = "nvidia,tegra124-timer", "nvidia,tegra30-timer", "nvidia,tegra20-timer";
+		compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer";
 		reg = <0x60005000 0x400>;
 		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
@@ -321,7 +316,7 @@
 	 * driver and APB DMA based serial driver for higher baudrate
 	 * and performace. To enable the 8250 based driver, the compatible
 	 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
-	 * the APB DMA based serial driver, the compatible is
+	 * the APB DMA based serial driver, the comptible is
 	 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
 	 */
 	uarta: serial@70006000 {
@@ -404,15 +399,10 @@
 	i2c@7000c400 {
 		compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 		reg = <0x7000c400 0x100>;
-		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <0 84 0x04>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&tegra_car TEGRA124_CLK_I2C2>;
-		clock-names = "div-clk";
-		resets = <&tegra_car 54>;
-		reset-names = "i2c";
-		dmas = <&apbdma 22>, <&apbdma 22>;
-		dma-names = "rx", "tx";
+		clocks = <&tegra_car 54>;
 		status = "disabled";
 	};
 
@@ -641,41 +631,6 @@
 		status = "disabled";
 	};
 
-	usb@70090000 {
-		compatible = "nvidia,tegra124-xusb";
-		reg = <0x70090000 0x8000>,
-		      <0x70098000 0x1000>,
-		      <0x70099000 0x1000>;
-		reg-names = "hcd", "fpci", "ipfs";
-
-		interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
-
-		clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>,
-			 <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>,
-			 <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>,
-			 <&tegra_car TEGRA124_CLK_XUSB_SS>,
-			 <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>,
-			 <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>,
-			 <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>,
-			 <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>,
-			 <&tegra_car TEGRA124_CLK_PLL_U_480M>,
-			 <&tegra_car TEGRA124_CLK_CLK_M>,
-			 <&tegra_car TEGRA124_CLK_PLL_E>;
-		clock-names = "xusb_host", "xusb_host_src",
-			      "xusb_falcon_src", "xusb_ss",
-			      "xusb_ss_div2", "xusb_ss_src",
-			      "xusb_hs_src", "xusb_fs_src",
-			      "pll_u_480m", "clk_m", "pll_e";
-		resets = <&tegra_car 89>, <&tegra_car 156>,
-			 <&tegra_car 143>;
-		reset-names = "xusb_host", "xusb_ss", "xusb_src";
-
-		nvidia,xusb-padctl = <&padctl>;
-
-		status = "disabled";
-	};
-
 	padctl: padctl@7009f000 {
 		compatible = "nvidia,tegra124-xusb-padctl";
 		reg = <0x7009f000 0x1000>;
@@ -865,7 +820,7 @@
 	};
 
 	usb@7d000000 {
-		compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
+		compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
 		reg = <0x7d000000 0x4000>;
 		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 		phy_type = "utmi";
@@ -902,10 +857,10 @@
 	};
 
 	usb@7d004000 {
-		compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
+		compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
 		reg = <0x7d004000 0x4000>;
 		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
-		phy_type = "utmi";
+		phy_type = "hsic";
 		clocks = <&tegra_car TEGRA124_CLK_USB2>;
 		resets = <&tegra_car 58>;
 		reset-names = "usb";

arch/arm/dts/tegra186-p2771-0000.dtsi

@@ -9,8 +9,8 @@
 	};
 
 	aliases {
-		mmc0 = "/sdhci@3460000";
-		mmc1 = "/sdhci@3400000";
+		sdhci0 = "/sdhci@3460000";
+		sdhci1 = "/sdhci@3400000";
 		i2c0 = "/bpmp/i2c";
 		i2c1 = "/i2c@3160000";
 		i2c2 = "/i2c@c240000";
@@ -50,7 +50,6 @@
 	sdhci@3460000 {
 		status = "okay";
 		bus-width = <8>;
-		non-removable;
 	};
 
 	i2c@c240000 {

arch/arm/dts/tegra20-colibri.dts

@@ -17,7 +17,7 @@
 		usb0 = "/usb@c5008000";
 		usb1 = "/usb@c5000000";
 		usb2 = "/usb@c5004000";
-		mmc0 = "/sdhci@c8000600";
+		sdhci0 = "/sdhci@c8000600";
 	};
 
 	host1x@50000000 {
@@ -39,8 +39,7 @@
 	usb@c5004000 {
 		statuc = "okay";
 		/* VBUS_LAN */
-		nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
-			GPIO_ACTIVE_LOW>;
+		nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
 		nvidia,vbus-gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>;
 	};
 

arch/arm/dts/tegra20-harmony.dts

@@ -15,11 +15,10 @@
 		rtc0 = "/i2c@7000d000/tps6586x@34";
 		rtc1 = "/rtc@7000e000";
 		serial0 = &uartd;
-		usb0 = "/usb@c5000000";
+		usb0 = "/usb@c5008000";
 		usb1 = "/usb@c5004000";
-		usb2 = "/usb@c5008000";
-		mmc0 = "/sdhci@c8000600";
-		mmc1 = "/sdhci@c8000200";
+		sdhci0 = "/sdhci@c8000600";
+		sdhci1 = "/sdhci@c8000200";
 	};
 
 	memory {
@@ -627,8 +626,7 @@
 
 	usb@c5004000 {
 		status = "okay";
-		nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
-			GPIO_ACTIVE_LOW>;
+		nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) 0>;
 	};
 
 	usb-phy@c5004000 {

arch/arm/dts/tegra20-medcom-wide.dts

@@ -12,7 +12,7 @@
 
 	aliases {
 		usb0 = "/usb@c5008000";
-		mmc0 = "/sdhci@c8000600";
+		sdhci0 = "/sdhci@c8000600";
 	};
 
 	memory {