Prepare v2016.09.01

Signed-off-by: Tom Rini <trini@konsulko.com>
Revert "image-fit: switch ENOLINK to ENOENT"
2026-06-03 02:06:44 +03:00 · 2016-09-19 10:45:12 -04:00 · 2016-09-19 10:43:12 -04:00 · 2016-09-19 10:42:32 -04:00
9460 changed files with 447733 additions and 542194 deletions
--- a/.gitignore
+++ b/.gitignore
@@ -30,9 +30,8 @@
 #
 # Top-level generic files
 #
-fit-dtb.blob
 /MLO*
-/SPL*
+/SPL
 /System.map
 /u-boot*
 /boards.cfg
--- a/.mailmap
+++ b/.mailmap
@@ -20,7 +20,6 @@ Jagan Teki <jaganna@xilinx.com>
 Jagan Teki <jagannadh.teki@gmail.com>
 Jagan Teki <jagannadha.sutradharudu-teki@xilinx.com>
 Markus Klotzbuecher <mk@denx.de>
-Paul Burton <paul.burton@mips.com> <paul.burton@imgtec.com>
 Prabhakar Kushwaha <prabhakar@freescale.com>
 Rajeshwari Shinde <rajeshwari.s@samsung.com>
 Ricardo Ribalda <ricardo.ribalda@uam.es>
--- a/.travis.yml
+++ b/.travis.yml
@@ -3,8 +3,7 @@

 # build U-Boot on Travis CI - https://travis-ci.org/

-sudo: required
-dist: trusty
+sudo: true

 language: c

@@ -19,100 +18,58 @@ addons:
    - libsdl1.2-dev
    - python
    - python-virtualenv
-    - swig
-    - libpython-dev
-    - gcc-powerpc-linux-gnu
-    - iasl
-    - grub-efi-ia32-bin
-    - rpm2cpio
-    - wget
-    - device-tree-compiler
+
+cache:
+ - apt

 install:
- # Clone uboot-test-hooks
- - git clone --depth=1 git://github.com/swarren/uboot-test-hooks.git /tmp/uboot-test-hooks
- - ln -s travis-ci /tmp/uboot-test-hooks/bin/`hostname`
- - ln -s travis-ci /tmp/uboot-test-hooks/py/`hostname`
+ # install latest device tree compiler
+ - git clone --depth=1 https://git.kernel.org/pub/scm/utils/dtc/dtc.git /tmp/dtc
+ - make -j4 -C /tmp/dtc
 # prepare buildman environment
- - echo -e "[toolchain]\nroot = /usr" > ~/.buildman
- - echo -e "aarch64 = /tmp/gcc-linaro-6.3.1-2017.02-x86_64_aarch64-linux-gnu" >> ~/.buildman
- - echo -e "arm = /tmp/gcc-linaro-6.3.1-2017.02-x86_64_arm-linux-gnueabihf" >> ~/.buildman
- - echo -e "arc = /tmp/arc_gnu_2016.09_prebuilt_uclibc_le_archs_linux_install" >> ~/.buildman
- - echo -e "\n[toolchain-alias]\nsh = sh4\nopenrisc = or32" >> ~/.buildman
+ - export BUILDMAN_ROOT="root:"
+ - export BUILDMAN_PPC="ppc:"
+ - export BUILDMAN_ARM="arm:"
+ - export BUILDMAN_SANDBOX="sandbox:"
+ - echo -e "[toolchain]\n${BUILDMAN_ROOT} /\n" > ~/.buildman
+ - echo -e "${BUILDMAN_PPC} /opt/eldk-5.4/powerpc/sysroots/i686-eldk-linux/usr/bin/powerpc-linux/\n" >> ~/.buildman
+ - echo -e "${BUILDMAN_ARM} /opt/eldk-5.4/armv5te/sysroots/i686-eldk-linux/usr/bin/armv5te-linux-gnueabi/\n" >> ~/.buildman
+ - echo -e "${BUILDMAN_SANDBOX} /usr/bin/gcc\n" >> ~/.buildman
+ - export BUILDMAN_ALIAS="x86:"
+ - export BUILDMAN_ALIAS_ARM="arm:"
+ - echo -e "\n\n[toolchain-alias]\n${BUILDMAN_ALIAS} i386\n" >> ~/.buildman
+ - echo -e "${BUILDMAN_ALIAS_ARM} armv5te\n" >> ~/.buildman
 - cat ~/.buildman
 - virtualenv /tmp/venv
 - . /tmp/venv/bin/activate
 - pip install pytest
- - grub-mkimage -o ~/grub_x86.efi -O i386-efi normal  echo lsefimmap lsefi lsefisystab efinet tftp minicmd
- - mkdir ~/grub2-arm
- - ( cd ~/grub2-arm; wget -O - http://download.opensuse.org/ports/armv7hl/distribution/leap/42.2/repo/oss/suse/armv7hl/grub2-arm-efi-2.02~beta2-87.1.armv7hl.rpm | rpm2cpio | cpio -di )

 env:
  global:
-    - PATH=/tmp/qemu-install/bin:/tmp/uboot-test-hooks/bin:/usr/bin:/bin
-    - PYTHONPATH=/tmp/uboot-test-hooks/py/travis-ci
+    - PATH=/tmp/dtc:$PATH
    - BUILD_DIR=build
    - HOSTCC="cc"
    - HOSTCXX="c++"

 before_script:
  # install toolchains based on TOOLCHAIN} variable
+  - if [[ "${TOOLCHAIN}" == *aarch64* ]]; then ./tools/buildman/buildman --fetch-arch aarch64 ; fi
+  - if [[ "${TOOLCHAIN}" == *arm* ]]; then wget ftp://ftp.denx.de/pub/eldk/5.4/targets/armv5te/eldk-eglibc-i686-arm-toolchain-gmae-5.4.sh ; fi
+  - if [[ "${TOOLCHAIN}" == *arm* ]]; then sh eldk-eglibc-i686-arm-toolchain-gmae-5.4.sh -y ; fi
+  - if [[ "${TOOLCHAIN}" == *avr32* ]]; then ./tools/buildman/buildman --fetch-arch avr32 ; fi
+  - if [[ "${TOOLCHAIN}" == *i386* ]]; then ./tools/buildman/buildman sandbox --fetch-arch i386 ; fi
  - if [[ "${TOOLCHAIN}" == *m68k* ]]; then ./tools/buildman/buildman --fetch-arch m68k ; fi
-  - if [[ "${TOOLCHAIN}" == *microblaze* ]]; then ./tools/buildman/buildman --fetch-arch microblaze ; fi
  - if [[ "${TOOLCHAIN}" == *mips* ]]; then ./tools/buildman/buildman --fetch-arch mips ; fi
-  - if [[ "${TOOLCHAIN}" == *or32* ]]; then ./tools/buildman/buildman --fetch-arch or32 ; fi
-  - if [[ "${TOOLCHAIN}" == *sh4* ]]; then ./tools/buildman/buildman --fetch-arch sh4 ; fi
-  - if [[ "${TOOLCHAIN}" == *x86_64* ]]; then
-      ./tools/buildman/buildman --fetch-arch x86_64;
-      echo -e "\n[toolchain-prefix]\nx86 = ${HOME}/.buildman-toolchains/gcc-4.9.0-nolibc/x86_64-linux/bin/x86_64-linux-" >> ~/.buildman;
-    fi
-  - if [[ "${TOOLCHAIN}" == arc ]]; then
-       wget https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/releases/download/arc-2016.09-release/arc_gnu_2016.09_prebuilt_uclibc_le_archs_linux_install.tar.gz &&
-       tar -C /tmp -xf arc_gnu_2016.09_prebuilt_uclibc_le_archs_linux_install.tar.gz;
-    fi
-  - if [[ "${TOOLCHAIN}" == *xtensa* ]]; then ./tools/buildman/buildman --fetch-arch xtensa ; fi
-  # If TOOLCHAIN is unset, we're on some flavour of ARM.
-  - if [[ "${TOOLCHAIN}" == "" ]]; then
-       wget http://releases.linaro.org/components/toolchain/binaries/6.3-2017.02/aarch64-linux-gnu/gcc-linaro-6.3.1-2017.02-x86_64_aarch64-linux-gnu.tar.xz &&
-       wget http://releases.linaro.org/components/toolchain/binaries/6.3-2017.02/arm-linux-gnueabihf/gcc-linaro-6.3.1-2017.02-x86_64_arm-linux-gnueabihf.tar.xz &&
-       tar -C /tmp -xf gcc-linaro-6.3.1-2017.02-x86_64_aarch64-linux-gnu.tar.xz &&
-       tar -C /tmp -xf gcc-linaro-6.3.1-2017.02-x86_64_arm-linux-gnueabihf.tar.xz;
-    fi
-  - if [[ "${QEMU_TARGET}" != "" ]]; then
-       git clone git://git.qemu.org/qemu.git /tmp/qemu;
-       pushd /tmp/qemu;
-       git submodule update --init dtc &&
-       git checkout v2.8.0-rc3 &&
-       ./configure --prefix=/tmp/qemu-install --target-list=${QEMU_TARGET} &&
-       make -j4 all install;
-       popd;
-    fi
+  - if [[ "${TOOLCHAIN}" == *ppc* ]]; then wget ftp://ftp.denx.de/pub/eldk/5.4/targets/powerpc/eldk-eglibc-i686-powerpc-toolchain-gmae-5.4.sh ; fi
+  - if [[ "${TOOLCHAIN}" == *ppc* ]]; then sh eldk-eglibc-i686-powerpc-toolchain-gmae-5.4.sh -y ; fi

 script:
- # Comments must be outside the command strings below, or the Travis parser
- # will get confused.
- #
- # Exit code 129 means warnings only.
- - if [[ "${BUILDMAN}" != "" ]]; then
-     set +e;
-     tools/buildman/buildman -P ${BUILDMAN};
-     ret=$?;
-     if [[ $ret -ne 0 && $ret -ne 129 ]]; then
-       tools/buildman/buildman -sdeP ${BUILDMAN};
-       exit $ret;
-     fi;
+ # the execution sequence for each test
+ - if [[ "${TEST_CMD}" != "" ]]; then
+     ${TEST_CMD};
   fi
- # "not a_test_which_does_not_exist" is a dummy -k parameter which will
- # never prevent any test from running. That way, we can always pass
- # "-k something" even when $TEST_PY_TEST_SPEC doesnt need a custom
- # value.
- - export UBOOT_TRAVIS_BUILD_DIR=`cd .. && pwd`/.bm-work/${TEST_PY_BD};
-   cp ~/grub_x86.efi $UBOOT_TRAVIS_BUILD_DIR/;
-   cp ~/grub2-arm/usr/lib/grub2/arm-efi/grub.efi $UBOOT_TRAVIS_BUILD_DIR/grub_arm.efi;
-   if [[ "${TEST_PY_BD}" != "" ]]; then
-     ./test/py/test.py --bd ${TEST_PY_BD} ${TEST_PY_ID}
-       -k "${TEST_PY_TEST_SPEC:-not a_test_which_does_not_exist}"
-       --build-dir "$UBOOT_TRAVIS_BUILD_DIR";
+ - if [[ "${BUILDMAN}" != "" ]]; then
+     tools/buildman/buildman ${BUILDMAN};
   fi

 matrix:
@@ -120,235 +77,113 @@ matrix:
  # we need to build by vendor due to 50min time limit for builds
  # each env setting here is a dedicated build
    - env:
-        - BUILDMAN="arc"
-          TOOLCHAIN="arc"
+        - BUILDMAN="arm1136"
+          TOOLCHAIN="arm"
    - env:
-        - BUILDMAN="arm11"
+        - BUILDMAN="arm1136"
+          TOOLCHAIN="arm"
    - env:
-        - BUILDMAN="arm7"
+        - BUILDMAN="arm1176"
+          TOOLCHAIN="arm"
+    - env:
+        - BUILDMAN="arm720t"
+          TOOLCHAIN="arm"
    - env:
        - BUILDMAN="arm920t"
+          TOOLCHAIN="arm"
    - env:
-        - JOB="arm926ejs"
-          BUILDMAN="arm926ejs -x mx,siemens,atmel"
+        - BUILDMAN="atmel -x avr32"
+          TOOLCHAIN="arm"
    - env:
-        - BUILDMAN="arm946es"
+        - BUILDMAN="avr32"
+          TOOLCHAIN="avr32"
    - env:
-        - BUILDMAN="atmel"
+        - BUILDMAN="davinci"
+          TOOLCHAIN="arm"
    - env:
-        - BUILDMAN="aries"
+        - BUILDMAN="denx"
+          TOOLCHAIN="arm"
    - env:
-        - JOB="Boundary Devices"
-          BUILDMAN="boundary"
-    - env:
-        - JOB="engicam"
-          BUILDMAN="engicam"
-    - env:
-        - JOB="Freescale ARM32"
-          BUILDMAN="freescale -x powerpc,m68k,aarch64"
-    - env:
-        - JOB="Freescale AArch64"
-          BUILDMAN="freescale&aarch64"
-    - env:
-        - JOB="i.MX6 (non-Freescale)"
-          BUILDMAN="mx6 -x freescale,toradex,boundary,engicam"
-    - env:
-        - JOB="i.MX (non-Freescale, non-i.MX6)"
-          BUILDMAN="mx -x freescale,mx6,toradex"
-    - env:
-        - BUILDMAN="k2"
-    - env:
-        - BUILDMAN="samsung"
-    - env:
-        - BUILDMAN="socfpga"
-    - env:
-        - BUILDMAN="sun4i"
-    - env:
-        - BUILDMAN="sun5i"
-    - env:
-        - BUILDMAN="sun6i"
-    - env:
-        - BUILDMAN="sun7i"
-    - env:
-        - BUILDMAN="sun8i"
-    - env:
-        - BUILDMAN="sun9i"
-    - env:
-        - BUILDMAN="sun50i"
-    - env:
-        - JOB="Catch-all ARM"
-          BUILDMAN="arm -x arm11,arm7,arm9,aarch64,atmel,aries,freescale,kirkwood,mvebu,siemens,tegra,uniphier,mx,samsung,sunxi,am33xx,omap3,omap4,omap5,pxa,rockchip,toradex,socfpga,k2,xilinx"
+        - BUILDMAN="freescale -x powerpc,m68k,aarch64"
+          TOOLCHAIN="arm"
    - env:
        - BUILDMAN="sandbox x86"
-          TOOLCHAIN="x86_64"
-    - env:
-        - BUILDMAN="toradex"
+          TOOLCHAIN="i386"
    - env:
        - BUILDMAN="kirkwood"
-    - env:
-        - BUILDMAN="mvebu"
-    - env:
-        - JOB="PXA"
-        - BUILDMAN="pxa -x toradex"
+          TOOLCHAIN="arm"
    - env:
        - BUILDMAN="m68k"
          TOOLCHAIN="m68k"
-    - env:
-        - BUILDMAN="microblaze"
-          TOOLCHAIN="microblaze"
    - env:
        - BUILDMAN="mips"
          TOOLCHAIN="mips"
+    - env:
+        - BUILDMAN="mpc512x"
+          TOOLCHAIN="ppc"
+    - env:
+        - BUILDMAN="mpc5xx"
+          TOOLCHAIN="ppc"
+    - env:
+        - BUILDMAN="mpc5xxx"
+          TOOLCHAIN="ppc"
+    - env:
+        - BUILDMAN="mpc8260"
+          TOOLCHAIN="ppc"
    - env:
        - BUILDMAN="mpc83xx"
+          TOOLCHAIN="ppc"
    - env:
        - BUILDMAN="mpc85xx -x freescale"
+          TOOLCHAIN="ppc"
    - env:
        - BUILDMAN="mpc85xx -x t208xrdb -x t4qds -x t102* -x p1_p2_rdb_pc -x p1010rdb -x corenet_ds -x b4860qds -x sbc8548 -x bsc91*"
+          TOOLCHAIN="ppc"
    - env:
        - BUILDMAN="t208xrdb t4qds t102*"
+          TOOLCHAIN="ppc"
    - env:
-        - BUILDMAN="p1_p2_rdb_pc"
-    - env:
-        - BUILDMAN="p1010rdb"
+        - BUILDMAN="p1_p2_rdb_pc p1010rdb"
+          TOOLCHAIN="ppc"
    - env:
        - BUILDMAN="corenet_ds b4860qds sbc8548 bsc91*"
+          TOOLCHAIN="ppc"
    - env:
        - BUILDMAN="mpc86xx"
+          TOOLCHAIN="ppc"
    - env:
        - BUILDMAN="mpc8xx"
+          TOOLCHAIN="ppc"
    - env:
        - BUILDMAN="siemens"
+          TOOLCHAIN="arm"
    - env:
-        - JOB="tegra"
-          BUILDMAN="tegra -x toradex"
+        - BUILDMAN="ti"
+          TOOLCHAIN="arm"
    - env:
-        - JOB="am33xx"
-          BUILDMAN="am33xx -x siemens"
-    - env:
-        - BUILDMAN="omap3"
-    - env:
-        - BUILDMAN="omap4"
-    - env:
-        - BUILDMAN="omap5"
-    - env:
-        - BUILDMAN="uniphier"
-    - env:
-        - JOB="aarch64"
-          BUILDMAN="aarch64 -x tegra,freescale,mvebu,uniphier,sunxi,samsung,rockchip"
-    - env:
-        - BUILDMAN="rockchip"
-    - env:
-        - BUILDMAN="sh4"
-          TOOLCHAIN="sh4"
-    - env:
-        - JOB="Xilinx (ARM)"
-          BUILDMAN="xilinx -x microblaze"
-    - env:
-        - BUILDMAN="xtensa"
-          TOOLCHAIN="xtensa"
+        - BUILDMAN="aarch64"
+          TOOLCHAIN="aarch64"

    # QA jobs for code analytics
    # static code analysis with cppcheck (we can add --enable=all later)
    - env:
-        - JOB="cppcheck"
-      script:
-        - cppcheck --force --quiet --inline-suppr .
+        - TEST_CMD="cppcheck --force --quiet --inline-suppr ."
    # search for TODO within source tree
    - env:
-        - JOB="grep TODO"
-      script:
-        - grep -r TODO .
+        - TEST_CMD="grep -r TODO ."
    # search for FIXME within source tree
    - env:
-        - JOB="grep FIXME HACK"
-      script:
-        - grep -r FIXME .
+        - TEST_CMD="grep -r FIXME ."
    # search for HACK within source tree and ignore HACKKIT board
+    - env:
+        - TEST_CMD="grep -r HACK . | grep -v HACKKIT"
      script:
        - grep -r HACK . | grep -v HACKKIT
    # some statistics about the code base
    - env:
-        - JOB="sloccount"
-      script:
-        - sloccount .
-
+        - TEST_CMD="sloccount ."
    # test/py
    - env:
-        - TEST_PY_BD="sandbox"
-          BUILDMAN="^sandbox$"
-          TOOLCHAIN="x86_64"
-    - env:
-        - TEST_PY_BD="sandbox_spl"
-          TEST_PY_TEST_SPEC="test_ofplatdata"
-          BUILDMAN="^sandbox$"
-          TOOLCHAIN="x86_64"
-    - env:
-        - TEST_PY_BD="sandbox_flattree"
-          BUILDMAN="^sandbox_flattree$"
-          TOOLCHAIN="x86_64"
-    - env:
-        - TEST_PY_BD="vexpress_ca15_tc2"
-          TEST_PY_ID="--id qemu"
-          QEMU_TARGET="arm-softmmu"
-          BUILDMAN="^vexpress_ca15_tc2$"
-    - env:
-        - TEST_PY_BD="vexpress_ca9x4"
-          TEST_PY_ID="--id qemu"
-          QEMU_TARGET="arm-softmmu"
-          BUILDMAN="^vexpress_ca9x4$"
-    - env:
-        - TEST_PY_BD="integratorcp_cm926ejs"
-          TEST_PY_TEST_SPEC="not sleep"
-          TEST_PY_ID="--id qemu"
-          QEMU_TARGET="arm-softmmu"
-          BUILDMAN="^integratorcp_cm926ejs$"
-    - env:
-        - TEST_PY_BD="qemu_arm"
-          TEST_PY_TEST_SPEC="not sleep"
-          QEMU_TARGET="arm-softmmu"
-          BUILDMAN="^qemu_arm$"
-    - env:
-        - TEST_PY_BD="qemu_mips"
-          TEST_PY_TEST_SPEC="not sleep"
-          QEMU_TARGET="mips-softmmu"
-          BUILDMAN="^qemu_mips$"
-          TOOLCHAIN="mips"
-    - env:
-        - TEST_PY_BD="qemu_mipsel"
-          TEST_PY_TEST_SPEC="not sleep"
-          QEMU_TARGET="mipsel-softmmu"
-          BUILDMAN="^qemu_mipsel$"
-          TOOLCHAIN="mips"
-    - env:
-        - TEST_PY_BD="qemu_mips64"
-          TEST_PY_TEST_SPEC="not sleep"
-          QEMU_TARGET="mips64-softmmu"
-          BUILDMAN="^qemu_mips64$"
-          TOOLCHAIN="mips"
-    - env:
-        - TEST_PY_BD="qemu_mips64el"
-          TEST_PY_TEST_SPEC="not sleep"
-          QEMU_TARGET="mips64el-softmmu"
-          BUILDMAN="^qemu_mips64el$"
-          TOOLCHAIN="mips"
-    - env:
-        - TEST_PY_BD="qemu-ppce500"
-          TEST_PY_TEST_SPEC="not sleep"
-          QEMU_TARGET="ppc-softmmu"
-          BUILDMAN="^qemu-ppce500$"
-    - env:
-        - TEST_PY_BD="qemu-x86"
-          TEST_PY_TEST_SPEC="not sleep"
-          QEMU_TARGET="i386-softmmu"
-          BUILDMAN="^qemu-x86$"
-          TOOLCHAIN="x86_64"
-          BUILD_ROM="yes"
-    - env:
-        - TEST_PY_BD="zynq_zc702"
-          TEST_PY_TEST_SPEC="not sleep"
-          QEMU_TARGET="arm-softmmu"
-          TEST_PY_ID="--id qemu"
-          BUILDMAN="^zynq_zc702$"
+        - TEST_CMD="./test/py/test.py --bd sandbox --build"

 # TODO make it perfect ;-r
--- a/Documentation/devicetree/bindings/phy/no-op.txt
+++ b/Documentation/devicetree/bindings/phy/no-op.txt
@@ -1,16 +0,0 @@
-NOP PHY driver
-
-This driver is used to stub PHY operations in a driver (USB, SATA).
-This is useful when the 'client' driver (USB, SATA, ...) uses the PHY framework
-and there is no actual PHY harwdare to drive.
-
-Required properties:
- compatible     : must contain "nop-phy"
- #phy-cells     : must contain <0>
-
-Example:
-
-nop_phy {
-	compatible = "nop-phy";
-	#phy-cells = <0>;
-};
--- a/Documentation/devicetree/bindings/rtc/brcm,brcmstb-waketimer.txt
+++ b/Documentation/devicetree/bindings/rtc/brcm,brcmstb-waketimer.txt
@@ -1,22 +0,0 @@
-Broadcom STB wake-up Timer
-
-The Broadcom STB wake-up timer provides a 27Mhz resolution timer, with the
-ability to wake up the system from low-power suspend/standby modes.
-
-Required properties:
- compatible     : should contain "brcm,brcmstb-waketimer"
- reg            : the register start and length for the WKTMR block
- interrupts     : The TIMER interrupt
- interrupt-parent: The phandle to the Always-On (AON) Power Management (PM) L2
-                    interrupt controller node
- clocks	 : The phandle to the UPG fixed clock (27Mhz domain)
-
-Example:
-
-waketimer@f0411580 {
-	compatible = "brcm,brcmstb-waketimer";
-	reg = <0xf0411580 0x14>;
-	interrupts = <0x3>;
-	interrupt-parent = <&aon_pm_l2_intc>;
-	clocks = <&upg_fixed>;
-};
--- a/293
+++ b/293
@@ -14,12 +14,6 @@ source "arch/Kconfig"

 menu "General setup"

-config BROKEN
-	bool
-	help
-	  This option cannot be enabled. It is used as dependency
-	  for broken and incomplete features.
-
 config LOCALVERSION
 	string "Local version - append to U-Boot release"
 	help
@@ -61,23 +55,17 @@ config CC_OPTIMIZE_FOR_SIZE

 config DISTRO_DEFAULTS
 	bool "Select defaults suitable for booting general purpose Linux distributions"
-	default y if ARCH_SUNXI || TEGRA
-	default y if ARCH_LS2080A
-	default y if ARCH_MESON
-	default y if ARCH_ROCKCHIP
+	default y if ARCH_SUNXI
 	default n
-	imply USE_BOOTCOMMAND
 	select CMD_BOOTZ if ARM && !ARM64
 	select CMD_BOOTI if ARM64
 	select CMD_DHCP
-	select CMD_PXE
 	select CMD_EXT2
 	select CMD_EXT4
 	select CMD_FAT
 	select CMD_FS_GENERIC
 	select CMD_MII
 	select CMD_PING
-	select CMD_PART
 	select HUSH_PARSER
 	help
 	  Select this to enable various options and commands which are suitable
@@ -102,26 +90,6 @@ config SYS_MALLOC_F_LEN
 	  particular needs this to operate, so that it can allocate the
 	  initial serial device and any others that are needed.

-config SPL_SYS_MALLOC_F_LEN
-        hex "Size of malloc() pool in SPL before relocation"
-        depends on SYS_MALLOC_F
-        default SYS_MALLOC_F_LEN
-        help
-          Before relocation, memory is very limited on many platforms. Still,
-          we can provide a small malloc() pool if needed. Driver model in
-          particular needs this to operate, so that it can allocate the
-          initial serial device and any others that are needed.
-
-config TPL_SYS_MALLOC_F_LEN
-        hex "Size of malloc() pool in TPL before relocation"
-        depends on SYS_MALLOC_F
-        default SYS_MALLOC_F_LEN
-        help
-          Before relocation, memory is very limited on many platforms. Still,
-          we can provide a small malloc() pool if needed. Driver model in
-          particular needs this to operate, so that it can allocate the
-          initial serial device and any others that are needed.
-
 menuconfig EXPERT
 	bool "Configure standard U-Boot features (expert users)"
 	default y
@@ -156,7 +124,7 @@ config TOOLS_DEBUG
 	  it is possible to set breakpoints on particular lines, single-step
 	  debug through the source code, etc.

-endif # EXPERT
+endif

 config PHYS_64BIT
 	bool "64bit physical address support"
@@ -165,65 +133,110 @@ config PHYS_64BIT
 	  This can be used not only for 64bit SoCs, but also for
 	  large physical address extention on 32bit SoCs.

-config BUILD_ROM
-	bool "Build U-Boot as BIOS replacement"
-	depends on X86
-	help
-	  This option allows to build a ROM version of U-Boot.
-	  The build process generally requires several binary blobs
-	  which are not shipped in the U-Boot source tree.
-	  Please, see doc/README.x86 for details.
-
 endmenu		# General setup

 menu "Boot images"

-config ANDROID_BOOT_IMAGE
-	bool "Enable support for Android Boot Images"
-	default y if FASTBOOT
+config SUPPORT_SPL
+	bool
+
+config SUPPORT_TPL
+	bool
+
+config SPL
+	bool
+	depends on SUPPORT_SPL
+	prompt "Enable SPL"
 	help
-	  This enables support for booting images which use the Android
-	  image format header.
+	  If you want to build SPL as well as the normal image, say Y.
+
+config SPL_SYS_MALLOC_SIMPLE
+	bool
+	depends on SPL
+	prompt "Only use malloc_simple functions in the SPL"
+	help
+	  Say Y here to only use the *_simple malloc functions from
+	  malloc_simple.c, rather then using the versions from dlmalloc.c;
+	  this will make the SPL binary smaller at the cost of more heap
+	  usage as the *_simple malloc functions do not re-use free-ed mem.
+
+config SPL_STACK_R
+	depends on SPL
+	bool "Enable SDRAM location for SPL stack"
+	help
+	  SPL starts off execution in SRAM and thus typically has only a small
+	  stack available. Since SPL sets up DRAM while in its board_init_f()
+	  function, it is possible for the stack to move there before
+	  board_init_r() is reached. This option enables a special SDRAM
+	  location for the SPL stack. U-Boot SPL switches to this after
+	  board_init_f() completes, and before board_init_r() starts.
+
+config SPL_STACK_R_ADDR
+	depends on SPL_STACK_R
+	hex "SDRAM location for SPL stack"
+	help
+	  Specify the address in SDRAM for the SPL stack. This will be set up
+	  before board_init_r() is called.
+
+config SPL_STACK_R_MALLOC_SIMPLE_LEN
+	depends on SPL_STACK_R && SPL_SYS_MALLOC_SIMPLE
+	hex "Size of malloc_simple heap after switching to DRAM SPL stack"
+	default 0x100000
+	help
+	  Specify the amount of the stack to use as memory pool for
+	  malloc_simple after switching the stack to DRAM. This may be set
+	  to give board_init_r() a larger heap then the initial heap in
+	  SRAM which is limited to SYS_MALLOC_F_LEN bytes.
+
+config SPL_SEPARATE_BSS
+	depends on SPL
+	bool "BSS section is in a different memory region from text"
+	help
+	  Some platforms need a large BSS region in SPL and can provide this
+	  because RAM is already set up. In this case BSS can be moved to RAM.
+	  This option should then be enabled so that the correct device tree
+	  location is used. Normally we put the device tree at the end of BSS
+	  but with this option enabled, it goes at _image_binary_end.
+
+config TPL
+	bool
+	depends on SPL && SUPPORT_TPL
+	prompt "Enable TPL"
+	help
+	  If you want to build TPL as well as the normal image and SPL, say Y.

 config FIT
 	bool "Support Flattened Image Tree"
-	select MD5
-	select SHA1
 	help
-	  This option allows you to boot the new uImage structure,
+	  This option allows to boot the new uImage structrure,
 	  Flattened Image Tree.  FIT is formally a FDT, which can include
 	  images of various types (kernel, FDT blob, ramdisk, etc.)
 	  in a single blob.  To boot this new uImage structure,
 	  pass the address of the blob to the "bootm" command.
 	  FIT is very flexible, supporting compression, multiple images,
 	  multiple configurations, verification through hashing and also
-	  verified boot (secure boot using RSA).
+	  verified boot (secure boot using RSA). This option enables that
+	  feature.

-if FIT
+config SPL_FIT
+	bool "Support Flattened Image Tree within SPL"
+	depends on FIT
+	depends on SPL

-config FIT_ENABLE_SHA256_SUPPORT
-	bool "Support SHA256 checksum of FIT image contents"
-	select SHA256
-	default y
-	help
-	  Enable this to support SHA256 checksum of FIT image contents. A
-	  SHA256 checksum is a 256-bit (32-byte) hash value used to check that
-	  the image contents have not been corrupted. SHA256 is recommended
-	  for use in secure applications since (as at 2016) there is no known
-	  feasible attack that could produce a 'collision' with differing
-	  input data. Use this for the highest security. Note that only the
-	  SHA256 variant is supported: SHA512 and others are not currently
-	  supported in U-Boot.
+config FIT_VERBOSE
+	bool "Display verbose messages on FIT boot"
+	depends on FIT

 config FIT_SIGNATURE
 	bool "Enable signature verification of FIT uImages"
+	depends on FIT
 	depends on DM
 	select RSA
 	help
 	  This option enables signature verification of FIT uImages,
 	  using a hash signed and verified using RSA. If
 	  CONFIG_SHA_PROG_HW_ACCEL is defined, i.e support for progressive
-	  hashing is available using hardware, then the RSA library will use
+	  hashing is available using hardware, then then RSA library will use
 	  it. See doc/uImage.FIT/signature.txt for more details.

 	  WARNING: When relying on signed FIT images with a required signature
@@ -232,16 +245,15 @@ config FIT_SIGNATURE
 	  format support in this case, enable it using
 	  CONFIG_IMAGE_FORMAT_LEGACY.

-config FIT_VERBOSE
-	bool "Show verbose messages when FIT images fail"
-	help
-	  Generally a system will have valid FIT images so debug messages
-	  are a waste of code space. If you are debugging your images then
-	  you can enable this option to get more verbose information about
-	  failures.
+config SPL_FIT_SIGNATURE
+	bool "Enable signature verification of FIT firmware within SPL"
+	depends on SPL_FIT
+	depends on SPL_DM
+	select SPL_RSA

 config FIT_BEST_MATCH
 	bool "Select the best match for the kernel device tree"
+	depends on FIT
 	help
 	  When no configuration is explicitly selected, default to the
 	  one whose fdt's compatibility field best matches that of
@@ -249,79 +261,14 @@ config FIT_BEST_MATCH
 	  most specific compatibility entry of U-Boot's fdt's root node.
 	  The order of entries in the configuration's fdt is ignored.

-config FIT_IMAGE_POST_PROCESS
-	bool "Enable post-processing of FIT artifacts after loading by U-Boot"
-	depends on TI_SECURE_DEVICE
+config FIT_VERBOSE
+	bool "Show verbose messages when FIT images fails"
+	depends on FIT
 	help
-	  Allows doing any sort of manipulation to blobs after they got extracted
-	  from FIT images like stripping off headers or modifying the size of the
-	  blob, verification, authentication, decryption etc. in a platform or
-	  board specific way. In order to use this feature a platform or board-
-	  specific implementation of board_fit_image_post_process() must be
-	  provided. Also, anything done during this post-processing step would
-	  need to be comprehended in how the images were prepared before being
-	  injected into the FIT creation (i.e. the blobs would have been pre-
-	  processed before being added to the FIT image).
-
-if SPL
-
-config SPL_FIT
-	bool "Support Flattened Image Tree within SPL"
-	depends on SPL
-	select SPL_OF_LIBFDT
-
-config SPL_FIT_SIGNATURE
-	bool "Enable signature verification of FIT firmware within SPL"
-	depends on SPL_DM
-	select SPL_FIT
-	select SPL_RSA
-
-config SPL_LOAD_FIT
-	bool "Enable SPL loading U-Boot as a FIT"
-	select SPL_FIT
-	help
-	  Normally with the SPL framework a legacy image is generated as part
-	  of the build. This contains U-Boot along with information as to
-	  where it should be loaded. This option instead enables generation
-	  of a FIT (Flat Image Tree) which provides more flexibility. In
-	  particular it can handle selecting from multiple device tree
-	  and passing the correct one to U-Boot.
-
-config SPL_FIT_IMAGE_POST_PROCESS
-	bool "Enable post-processing of FIT artifacts after loading by the SPL"
-	depends on SPL_LOAD_FIT
-	help
-	  Allows doing any sort of manipulation to blobs after they got extracted
-	  from the U-Boot FIT image like stripping off headers or modifying the
-	  size of the blob, verification, authentication, decryption etc. in a
-	  platform or board specific way. In order to use this feature a platform
-	  or board-specific implementation of board_fit_image_post_process() must
-	  be provided. Also, anything done during this post-processing step would
-	  need to be comprehended in how the images were prepared before being
-	  injected into the FIT creation (i.e. the blobs would have been pre-
-	  processed before being added to the FIT image).
-
-config SPL_FIT_SOURCE
-	string ".its source file for U-Boot FIT image"
-	depends on SPL_FIT
-	help
-	  Specifies a (platform specific) FIT source file to generate the
-	  U-Boot FIT image. This could specify further image to load and/or
-	  execute.
-
-config SPL_FIT_GENERATOR
-	string ".its file generator script for U-Boot FIT image"
-	depends on SPL_FIT
-	default "board/sunxi/mksunxi_fit_atf.sh" if SPL_LOAD_FIT && ARCH_SUNXI
-	help
-	  Specifies a (platform specific) script file to generate the FIT
-	  source file used to build the U-Boot FIT image file. This gets
-	  passed a list of supported device tree file stub names to
-	  include in the generated image.
-
-endif # SPL
-
-endif # FIT
+	  Generally a system will have valid FIT images so debug messages
+	  are a waste of code space. If you are debugging your images then
+	  you can enable this option to get more verbose information about
+	  failures.

 config OF_BOARD_SETUP
 	bool "Set up board-specific details in device tree before boot"
@@ -366,16 +313,51 @@ config SYS_EXTRA_OPTIONS
 	  new boards should not use this option.

 config SYS_TEXT_BASE
-	depends on ARC || X86 || ARCH_UNIPHIER || ARCH_ZYNQMP || \
-		(M68K && !TARGET_ASTRO_MCF5373L) || MICROBLAZE || MIPS || \
-		ARCH_ZYNQ || ARCH_KEYSTONE || ARCH_OMAP2PLUS
+	depends on SPARC || ARC || X86 || ARCH_UNIPHIER || ARCH_ZYNQMP || \
+		(M68K && !TARGET_ASTRO_MCF5373L) || MICROBLAZE || MIPS
 	depends on !EFI_APP
 	hex "Text Base"
 	help
 	  TODO: Move CONFIG_SYS_TEXT_BASE for all the architecture

-	default 0x80800000 if ARCH_OMAP2PLUS
+config SPL_LOAD_FIT
+	bool "Enable SPL loading U-Boot as a FIT"
+	depends on FIT
+	help
+	  Normally with the SPL framework a legacy image is generated as part
+	  of the build. This contains U-Boot along with information as to
+	  where it should be loaded. This option instead enables generation
+	  of a FIT (Flat Image Tree) which provides more flexibility. In
+	  particular it can handle selecting from multiple device tree
+	  and passing the correct one to U-Boot.

+config SPL_FIT_IMAGE_POST_PROCESS
+	bool "Enable post-processing of FIT artifacts after loading by the SPL"
+	depends on SPL_LOAD_FIT && TI_SECURE_DEVICE
+	help
+	  Allows doing any sort of manipulation to blobs after they got extracted
+	  from the U-Boot FIT image like stripping off headers or modifying the
+	  size of the blob, verification, authentication, decryption etc. in a
+	  platform or board specific way. In order to use this feature a platform
+	  or board-specific implementation of board_fit_image_post_process() must
+	  be provided. Also, anything done during this post-processing step would
+	  need to be comprehended in how the images were prepared before being
+	  injected into the FIT creation (i.e. the blobs would have been pre-
+	  processed before being added to the FIT image).
+
+config FIT_IMAGE_POST_PROCESS
+	bool "Enable post-processing of FIT artifacts after loading by U-Boot"
+	depends on FIT && TI_SECURE_DEVICE
+	help
+	  Allows doing any sort of manipulation to blobs after they got extracted
+	  from FIT images like stripping off headers or modifying the size of the
+	  blob, verification, authentication, decryption etc. in a platform or
+	  board specific way. In order to use this feature a platform or board-
+	  specific implementation of board_fit_image_post_process() must be
+	  provided. Also, anything done during this post-processing step would
+	  need to be comprehended in how the images were prepared before being
+	  injected into the FIT creation (i.e. the blobs would have been pre-
+	  processed before being added to the FIT image).

 config SYS_CLK_FREQ
 	depends on ARC || ARCH_SUNXI
@@ -383,8 +365,9 @@ config SYS_CLK_FREQ
 	help
 	  TODO: Move CONFIG_SYS_CLK_FREQ for all the architecture

-config ARCH_FIXUP_FDT_MEMORY
-	bool "Enable arch_fixup_memory_banks() call"
+config ARCH_FIXUP_FDT
+	bool "Enable arch_fixup_fdt() call"
+	depends on ARM || MIPS
 	default y
 	help
 	  Enable FDT memory map syncup before OS boot. This feature can be
@@ -393,18 +376,12 @@ config ARCH_FIXUP_FDT_MEMORY

 endmenu		# Boot images

-source "api/Kconfig"
-
 source "common/Kconfig"

 source "cmd/Kconfig"

-source "disk/Kconfig"
-
 source "dts/Kconfig"

-source "env/Kconfig"
-
 source "net/Kconfig"

 source "drivers/Kconfig"
--- a/Licenses/r8a779x_usb3.txt
+++ b/Licenses/r8a779x_usb3.txt
@@ -1,26 +0,0 @@
-Copyright (c) 2014, Renesas Electronics Corporation
-All rights reserved.
-
-Redistribution and use in binary form, without modification, are permitted
-provided that the following conditions are met:
-
-1. Redistribution in binary form must reproduce the above copyright notice,
-   this list of conditions and the following disclaimer in the documentation
-   and/or other materials provided with the distribution.
-2. The name of Renesas Electronics Corporation may not be used to endorse or
-   promote products derived from this software without specific prior written
-   permission.
-3. Reverse engineering, decompilation, or disassembly of this software is
-   not permitted.
-
-THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS ELECTRONICS CORPORATION DISCLAIMS
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, AND
-NONINFRINGEMENT OF THIRD PARTY RIGHTS. IN NO EVENT SHALL RENESAS ELECTRONICS
-CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-POSSIBILITY OF SUCH DAMAGE.
--- a/151
+++ b/151
@@ -59,20 +59,6 @@ S:	Maintained
 T:	git git://git.denx.de/u-boot-arc.git
 F:	arch/arc/

-ARC HSDK CREG GPIO
-M:	Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
-S:	Maintained
-L:	uboot-snps-arc@synopsys.com
-F:	drivers/gpio/hsdk-creg-gpio.c
-
-ARC HSDK CGU CLOCK
-M:	Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
-S:	Maintained
-L:	uboot-snps-arc@synopsys.com
-F:	drivers/clk/clk-hsdk-cgu.c
-F:	include/dt-bindings/clock/snps,hsdk-cgu.h
-F:	doc/device-tree-bindings/clock/snps,hsdk-cgu.txt
-
 ARM
 M:	Albert Aribaud <albert.u.boot@aribaud.net>
 S:	Maintained
@@ -83,7 +69,8 @@ ARM ALTERA SOCFPGA
 M:	Marek Vasut <marex@denx.de>
 S:	Maintainted
 T:	git git://git.denx.de/u-boot-socfpga.git
-F:	arch/arm/mach-socfpga/
+F:	arch/arm/cpu/armv7/socfpga/
+F:	board/altera/socfpga/

 ARM ATMEL AT91
 M:	Andreas Bießmann <andreas@biessmann.org>
@@ -92,8 +79,8 @@ T:	git git://git.denx.de/u-boot-atmel.git
 F:	arch/arm/mach-at91/

 ARM BROADCOM BCM283X
-#M:	Stephen Warren <swarren@wwwdotorg.org>
-S:	Orphaned (Since 2017-07)
+M:	Stephen Warren <swarren@wwwdotorg.org>
+S:	Maintained
 F:	arch/arm/mach-bcm283x/
 F:	drivers/gpio/bcm2835_gpio.c
 F:	drivers/mmc/bcm2835_sdhci.c
@@ -103,18 +90,18 @@ F:	include/dm/platform_data/serial_bcm283x_mu.h

 ARM FREESCALE IMX
 M:	Stefano Babic <sbabic@denx.de>
-M:	Fabio Estevam <fabio.estevam@nxp.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-imx.git
 F:	arch/arm/cpu/arm1136/mx*/
 F:	arch/arm/cpu/arm926ejs/mx*/
+F:	arch/arm/cpu/arm926ejs/imx/
 F:	arch/arm/cpu/armv7/mx*/
 F:	arch/arm/cpu/armv7/vf610/
-F:	arch/arm/mach-imx/
+F:	arch/arm/cpu/imx-common/
 F:	arch/arm/include/asm/arch-imx/
 F:	arch/arm/include/asm/arch-mx*/
 F:	arch/arm/include/asm/arch-vf610/
-F:	arch/arm/include/asm/mach-imx/
+F:	arch/arm/include/asm/imx-common/
 F:	board/freescale/*mx*/

 ARM HISILICON
@@ -141,30 +128,15 @@ F:	arch/arm/include/asm/arch-pxa/

 ARM RENESAS RMOBILE/R-CAR
 M:	Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
-M:	Marek Vasut <marek.vasut+renesas@gmail.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-sh.git
 F:	arch/arm/mach-rmobile/

 ARM ROCKCHIP
 M:	Simon Glass <sjg@chromium.org>
-M:	Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-rockchip.git
-F:	arch/arm/include/asm/arch-rockchip/
 F:	arch/arm/mach-rockchip/
-F:	board/rockchip/
-F:	drivers/clk/rockchip/
-F:	drivers/gpio/rk_gpio.c
-F:	drivers/misc/rockchip-efuse.c
-F:	drivers/pinctrl/rockchip/
-F:	drivers/ram/rockchip/
-F:	drivers/sysreset/sysreset_rockchip.c
-F:	tools/rkcommon.c
-F:	tools/rkcommon.h
-F:	tools/rkimage.c
-F:	tools/rksd.c
-F:	tools/rkspi.c

 ARM SAMSUNG
 M:	Minkyu Kang <mk7.kang@samsung.com>
@@ -194,21 +166,13 @@ S:	Maintained
 F:	arch/arm/cpu/armv7/stv0991/
 F:	arch/arm/include/asm/arch-stv0991/

-ARM STI
-M:	Patrice Chotard <patrice.chotard@st.com>
-S:	Maintained
-F:	arch/arm/mach-sti/
-F:	arch/arm/include/asm/arch-sti*/
-
 ARM SUNXI
-M:	Jagan Teki <jagan@openedev.com>
-M:	Maxime Ripard <maxime.ripard@free-electrons.com>
+M:	Ian Campbell <ijc@hellion.org.uk>
+M:	Hans De Goede <hdegoede@redhat.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-sunxi.git
 F:	arch/arm/cpu/armv7/sunxi/
 F:	arch/arm/include/asm/arch-sunxi/
-F:	arch/arm/mach-sunxi/
-F:	board/sunxi/

 ARM TEGRA
 M:	Tom Warren <twarren@nvidia.com>
@@ -248,6 +212,18 @@ S:	Maintained
 F:	arch/arm/cpu/armv8/zynqmp/
 F:	arch/arm/include/asm/arch-zynqmp/

+AVR32
+M:	Andreas Bießmann <andreas@biessmann.org>
+S:	Maintained
+T:	git git://git.denx.de/u-boot-avr32.git
+F:	arch/avr32/
+
+BLACKFIN
+M:	Sonic Zhang <sonic.adi@gmail.com>
+S:	Maintained
+T:	git git://git.denx.de/u-boot-blackfin.git
+F:	arch/blackfin/
+
 BUILDMAN
 M:	Simon Glass <sjg@chromium.org>
 S:	Maintained
@@ -268,7 +244,7 @@ T:	git git://git.denx.de/u-boot-coldfire.git
 F:	arch/m68k/

 DFU
-M:	Lukasz Majewski <lukma@denx.de>
+M:	Lukasz Majewski <l.majewski@samsung.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-dfu.git
 F:	drivers/dfu/
@@ -285,10 +261,8 @@ F:	test/dm/
 EFI PAYLOAD
 M:	Alexander Graf <agraf@suse.de>
 S:	Maintained
-T:	git git://github.com/agraf/u-boot.git
-F:	include/efi*
-F:	lib/efi*
-F:	test/py/tests/test_efi*
+F:	include/efi_loader.h
+F:	lib/efi_loader/
 F:	cmd/bootefi.c

 FLATTENED DEVICE TREE
@@ -299,7 +273,7 @@ F:	lib/fdtdec*
 F:	lib/libfdt/
 F:	include/fdt*
 F:	include/libfdt*
-F:	cmd/fdt.c
+F.	common/cmd_fdt.c
 F:	common/fdt_support.c

 FREEBSD
@@ -318,15 +292,6 @@ S:	Maintained
 T:	git git://git.denx.de/u-boot-i2c.git
 F:	drivers/i2c/

-LOGGING
-M:	Simon Glass <sjg@chromium.org>
-S:	Maintained
-T:	git git://git.denx.de/u-boot.git
-F:	common/log.c
-F:	cmd/log.c
-F:	test/log/log_test.c
-F:	test/py/tests/test_log.py
-
 MICROBLAZE
 M:	Michal Simek <monstr@monstr.eu>
 S:	Maintained
@@ -345,6 +310,11 @@ S:	Maintained
 T:	git git://git.denx.de/u-boot-mmc.git
 F:	drivers/mmc/

+OPENRISC
+M:	Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
+S:	Maintained
+F:	arch/openrisc/
+
 PATMAN
 M:	Simon Glass <sjg@chromium.org>
 S:	Maintained
@@ -355,15 +325,27 @@ M:	Wolfgang Denk <wd@denx.de>
 S:	Maintained
 F:	arch/powerpc/

+POWERPC MPC5XXX
+M:	Wolfgang Denk <wd@denx.de>
+S:	Maintained
+T:	git git://git.denx.de/u-boot-mpc5xxx.git
+F:	arch/powerpc/cpu/mpc5*/
+
 POWERPC MPC8XX
-M:	Christophe Leroy <christophe.leroy@c-s.fr>
+M:	Wolfgang Denk <wd@denx.de>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-mpc8xx.git
 F:	arch/powerpc/cpu/mpc8xx/

-POWERPC MPC83XX
-M:	Mario Six <mario.six@gdsys.cc>
+POWERPC MPC82XX
+M:	Wolfgang Denk <wd@denx.de>
 S:	Maintained
+T:	git git://git.denx.de/u-boot-mpc82xx.git
+F:	arch/powerpc/cpu/mpc82*/
+
+POWERPC MPC83XX
+#M:	Kim Phillips <kim.phillips@freescale.com>
+S:	Orphaned (Since 2016-02)
 T:	git git://git.denx.de/u-boot-mpc83xx.git
 F:	arch/powerpc/cpu/mpc83xx/
 F:	arch/powerpc/include/asm/arch-mpc83xx/
@@ -386,12 +368,6 @@ S:	Maintained
 T:	git git://git.denx.de/u-boot-ppc4xx.git
 F:	arch/powerpc/cpu/ppc4xx/

-POWER
-M:	Jaehoon Chung <jh80.chung@samsung.com>
-S:	Maintained
-T:	git git://git.denx.de/u-boot-pmic.git
-F:	drivers/power/
-
 NETWORK
 M:	Joe Hershberger <joe.hershberger@ni.com>
 S:	Maintained
@@ -418,8 +394,8 @@ T:	git git://git.denx.de/u-boot-nios.git
 F:	arch/nios2/

 ONENAND
-#M:	Lukasz Majewski <l.majewski@majess.pl>
-S:	Orphaned (Since 2017-01)
+M:	Lukasz Majewski <l.majewski@samsung.com>
+S:	Maintained
 T:	git git://git.denx.de/u-boot-onenand.git
 F:	drivers/mtd/onenand/

@@ -434,8 +410,14 @@ S:	Maintained
 T:	git git://git.denx.de/u-boot-sh.git
 F:	arch/sh/

+SPARC
+#M:	Francois Retief <fgretief@spaceteq.co.za>
+S:	Orphaned (Since 2016-02)
+T:	git git://git.denx.de/u-boot-sparc.git
+F:	arch/sparc/
+
 SPI
-M:	Jagan Teki <jagan@openedev.com>
+M:	Jagan Teki <jteki@openedev.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-spi.git
 F:	drivers/mtd/spi/
@@ -448,22 +430,6 @@ S:	Maintained
 F:	drivers/spmi/
 F:	include/spmi/

-TI SYSTEM SECURITY
-M:	Andrew F. Davis <afd@ti.com>
-S:	Supported
-F:	arch/arm/mach-omap2/omap5/sec_entry_cpu1.S
-F:	arch/arm/mach-omap2/omap5/sec-fxns.c
-F:	arch/arm/mach-omap2/sec-common.c
-F:	arch/arm/mach-omap2/config_secure.mk
-F:	configs/am335x_hs_evm_defconfig
-F:	configs/am335x_hs_evm_uart_defconfig
-F:	configs/am43xx_hs_evm_defconfig
-F:	configs/am57xx_hs_evm_defconfig
-F:	configs/dra7xx_hs_evm_defconfig
-F:	configs/k2hk_hs_evm_defconfig
-F:	configs/k2e_hs_evm_defconfig
-F:	configs/k2g_hs_evm_defconfig
-
 TQ GROUP
 #M:	Martin Krause <martin.krause@tq-systems.de>
 S:	Orphaned (Since 2016-02)
@@ -482,23 +448,14 @@ S:	Maintained
 T:	git git://git.denx.de/u-boot-usb.git
 F:	drivers/usb/

-USB xHCI
-M:	Bin Meng <bmeng.cn@gmail.com>
-S:	Maintained
-T:	git git://git.denx.de/u-boot-usb.git topic-xhci
-F:	drivers/usb/host/xhci*
-
 VIDEO
 M:	Anatolij Gustschin <agust@denx.de>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-video.git
 F:	drivers/video/
-F:	common/lcd*.c
-F:	include/lcd*.h

 X86
 M:	Simon Glass <sjg@chromium.org>
-M:	Bin Meng <bmeng.cn@gmail.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-x86.git
 F:	arch/x86/
--- a/278
+++ b/278
@@ -2,9 +2,9 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #

-VERSION = 2018
-PATCHLEVEL = 01
-SUBLEVEL =
+VERSION = 2016
+PATCHLEVEL = 09
+SUBLEVEL = 01
 EXTRAVERSION =
 NAME =

@@ -348,8 +348,8 @@ OBJCOPY		= $(CROSS_COMPILE)objcopy
 OBJDUMP		= $(CROSS_COMPILE)objdump
 AWK		= awk
 PERL		= perl
-PYTHON		?= python
-DTC		?= $(objtree)/scripts/dtc/dtc
+PYTHON		= python
+DTC		= dtc
 CHECK		= sparse

 CHECKFLAGS     := -D__linux__ -Dlinux -D__STDC__ -Dunix -D__unix__ \
@@ -360,7 +360,6 @@ KBUILD_CPPFLAGS := -D__KERNEL__ -D__UBOOT__
 KBUILD_CFLAGS   := -Wall -Wstrict-prototypes \
 		   -Wno-format-security \
 		   -fno-builtin -ffreestanding
-KBUILD_CFLAGS	+= -fshort-wchar
 KBUILD_AFLAGS   := -D__ASSEMBLY__

 # Read UBOOTRELEASE from include/config/uboot.release (if it exists)
@@ -372,7 +371,7 @@ export ARCH CPU BOARD VENDOR SOC CPUDIR BOARDDIR
 export CONFIG_SHELL HOSTCC HOSTCFLAGS HOSTLDFLAGS CROSS_COMPILE AS LD CC
 export CPP AR NM LDR STRIP OBJCOPY OBJDUMP
 export MAKE AWK PERL PYTHON
-export HOSTCXX HOSTCXXFLAGS CHECK CHECKFLAGS DTC DTC_FLAGS
+export HOSTCXX HOSTCXXFLAGS DTC CHECK CHECKFLAGS

 export KBUILD_CPPFLAGS NOSTDINC_FLAGS UBOOTINCLUDE OBJCOPYFLAGS LDFLAGS
 export KBUILD_CFLAGS KBUILD_AFLAGS
@@ -483,13 +482,6 @@ else
 # Build targets only - this includes vmlinux, arch specific targets, clean
 # targets and others. In general all targets except *config targets.

-# Additional helpers built in scripts/
-# Carefully list dependencies so we do not try to build scripts twice
-# in parallel
-PHONY += scripts
-scripts: scripts_basic include/config/auto.conf
-	$(Q)$(MAKE) $(build)=$(@)
-
 ifeq ($(dot-config),1)
 # Read in config
 -include include/config/auto.conf
@@ -517,9 +509,6 @@ include/config/%.conf: $(KCONFIG_CONFIG) include/config/auto.conf.cmd
 	@# Otherwise, 'make silentoldconfig' would be invoked twice.
 	$(Q)touch include/config/auto.conf

-u-boot.cfg spl/u-boot.cfg tpl/u-boot.cfg: include/config.h FORCE
-	$(Q)$(MAKE) -f $(srctree)/scripts/Makefile.autoconf $(@)
-
 -include include/autoconf.mk
 -include include/autoconf.mk.dep

@@ -538,15 +527,6 @@ endif
 endif
 endif

-# These are set by the arch-specific config.mk. Make sure they are exported
-# so they can be used when building an EFI application.
-export EFI_LDS		# Filename of EFI link script in arch/$(ARCH)/lib
-export EFI_CRT0		# Filename of EFI CRT0 in arch/$(ARCH)/lib
-export EFI_RELOC	# Filename of EFU relocation code in arch/$(ARCH)/lib
-export CFLAGS_EFI	# Compiler flags to add when building EFI app
-export CFLAGS_NON_EFI	# Compiler flags to remove when building EFI app
-export EFI_TARGET	# binutils target if EFI is natively supported
-
 # If board code explicitly specified LDSCRIPT or CONFIG_SYS_LDSCRIPT, use
 # that (or fail if absent).  Otherwise, search for a linker script in a
 # standard location.
@@ -628,9 +608,8 @@ KBUILD_CFLAGS += $(KCFLAGS)
 UBOOTINCLUDE    := \
 		-Iinclude \
 		$(if $(KBUILD_SRC), -I$(srctree)/include) \
-		$(if $(CONFIG_$(SPL_)SYS_THUMB_BUILD), \
-			$(if $(CONFIG_HAS_THUMB2),, \
-				-I$(srctree)/arch/$(ARCH)/thumb1/include),) \
+		$(if $(CONFIG_SYS_THUMB_BUILD), $(if $(CONFIG_HAS_THUMB2),, \
+			-I$(srctree)/arch/$(ARCH)/thumb1/include),) \
 		-I$(srctree)/arch/$(ARCH)/include \
 		-include $(srctree)/include/linux/kconfig.h

@@ -657,6 +636,7 @@ libs-y += drivers/
 libs-y += drivers/dma/
 libs-y += drivers/gpio/
 libs-y += drivers/i2c/
+libs-y += drivers/mmc/
 libs-y += drivers/mtd/
 libs-$(CONFIG_CMD_NAND) += drivers/mtd/nand/
 libs-y += drivers/mtd/onenand/
@@ -675,7 +655,6 @@ libs-y += drivers/power/ \
 libs-y += drivers/spi/
 libs-$(CONFIG_FMAN_ENET) += drivers/net/fm/
 libs-$(CONFIG_SYS_FSL_DDR) += drivers/ddr/fsl/
-libs-$(CONFIG_SYS_FSL_MMDC) += drivers/ddr/fsl/
 libs-$(CONFIG_ALTERA_SDRAM) += drivers/ddr/altera/
 libs-y += drivers/serial/
 libs-y += drivers/usb/dwc3/
@@ -691,7 +670,6 @@ libs-y += drivers/usb/phy/
 libs-y += drivers/usb/ulpi/
 libs-y += cmd/
 libs-y += common/
-libs-y += env/
 libs-$(CONFIG_API) += api/
 libs-$(CONFIG_HAS_POST) += post/
 libs-y += test/
@@ -751,9 +729,6 @@ BOARD_SIZE_CHECK =
 endif

 # Statically apply RELA-style relocations (currently arm64 only)
-# This is useful for arm64 where static relocation needs to be performed on
-# the raw binary, but certain simulators only accept an ELF file (but don't
-# do the relocation).
 ifneq ($(CONFIG_STATIC_RELA),)
 # $(1) is u-boot ELF, $(2) is u-boot bin, $(3) is text base
 DO_STATIC_RELA = \
@@ -765,7 +740,7 @@ DO_STATIC_RELA =
 endif

 # Always append ALL so that arch config.mk's can add custom ones
-ALL-y += u-boot.srec u-boot.bin u-boot.sym System.map binary_size_check
+ALL-y += u-boot.srec u-boot.bin u-boot.sym System.map u-boot.cfg binary_size_check

 ALL-$(CONFIG_ONENAND_U_BOOT) += u-boot-onenand.bin
 ifeq ($(CONFIG_SPL_FSL_PBL),y)
@@ -778,11 +753,7 @@ ALL-$(CONFIG_RAMBOOT_PBL) += u-boot.pbl
 endif
 endif
 ALL-$(CONFIG_SPL) += spl/u-boot-spl.bin
-ifeq ($(CONFIG_MX6)$(CONFIG_SECURE_BOOT), yy)
-ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot-ivt.img
-else
 ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot.img
-endif
 ALL-$(CONFIG_TPL) += tpl/u-boot-tpl.bin
 ALL-$(CONFIG_OF_SEPARATE) += u-boot.dtb
 ifeq ($(CONFIG_SPL_FRAMEWORK),y)
@@ -796,7 +767,7 @@ ALL-$(CONFIG_REMAKE_ELF) += u-boot.elf
 ALL-$(CONFIG_EFI_APP) += u-boot-app.efi
 ALL-$(CONFIG_EFI_STUB) += u-boot-payload.efi

-ifneq ($(BUILD_ROM)$(CONFIG_BUILD_ROM),)
+ifneq ($(BUILD_ROM),)
 ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom
 endif

@@ -812,10 +783,6 @@ ALL-y += $(CONFIG_BUILD_TARGET:"%"=%)
 endif

 LDFLAGS_u-boot += $(LDFLAGS_FINAL)
-
-# Avoid 'Not enough room for program headers' error on binutils 2.28 onwards.
-LDFLAGS_u-boot += $(call ld-option, --no-dynamic-linker)
-
 ifneq ($(CONFIG_SYS_TEXT_BASE),)
 LDFLAGS_u-boot += -Ttext $(CONFIG_SYS_TEXT_BASE)
 endif
@@ -832,15 +799,9 @@ cmd_zobjcopy = $(OBJCOPY) $(OBJCOPYFLAGS) $(OBJCOPYFLAGS_$(@F)) $< $@
 quiet_cmd_efipayload = OBJCOPY $@
 cmd_efipayload = $(OBJCOPY) -I binary -O $(EFIPAYLOAD_BFDTARGET) -B $(EFIPAYLOAD_BFDARCH) $< $@

-MKIMAGEOUTPUT ?= /dev/null
-
 quiet_cmd_mkimage = MKIMAGE $@
 cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \
-	$(if $(KBUILD_VERBOSE:1=), >$(MKIMAGEOUTPUT))
-
-quiet_cmd_mkfitimage = MKIMAGE $@
-cmd_mkfitimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -f $(U_BOOT_ITS) -E $@ \
-	$(if $(KBUILD_VERBOSE:1=), >$(MKIMAGEOUTPUT))
+	$(if $(KBUILD_VERBOSE:1=), >/dev/null)

 quiet_cmd_cat = CAT     $@
 cmd_cat = cat $(filter-out $(PHONY), $^) > $@
@@ -850,13 +811,7 @@ append = cat $(filter-out $< $(PHONY), $^) >> $@
 quiet_cmd_pad_cat = CAT     $@
 cmd_pad_cat = $(cmd_objcopy) && $(append) || rm -f $@

-cfg: u-boot.cfg
-
-quiet_cmd_cfgcheck = CFGCHK  $2
-cmd_cfgcheck = $(srctree)/scripts/check-config.sh $2 \
-		$(srctree)/scripts/config_whitelist.txt $(srctree)
-
-all:		$(ALL-y) cfg
+all:		$(ALL-y)
 ifeq ($(CONFIG_DM_I2C_COMPAT)$(CONFIG_SANDBOX),y)
 	@echo "===================== WARNING ======================"
 	@echo "This board uses CONFIG_DM_I2C_COMPAT. Please remove"
@@ -864,35 +819,17 @@ ifeq ($(CONFIG_DM_I2C_COMPAT)$(CONFIG_SANDBOX),y)
 	@echo "before sending patches to the mailing list."
 	@echo "===================================================="
 endif
-	@# Check that this build does not use CONFIG options that we do not
-	@# know about unless they are in Kconfig. All the existing CONFIG
-	@# options are whitelisted, so new ones should not be added.
-	$(call cmd,cfgcheck,u-boot.cfg)

 PHONY += dtbs
 dtbs: dts/dt.dtb
 	@:
-dts/dt.dtb: u-boot
+dts/dt.dtb: checkdtc u-boot
 	$(Q)$(MAKE) $(build)=dts dtbs

 quiet_cmd_copy = COPY    $@
      cmd_copy = cp $< $@

-ifeq ($(CONFIG_MULTI_DTB_FIT),y)
-
-fit-dtb.blob: dts/dt.dtb FORCE
-	$(call if_changed,mkimage)
-
-MKIMAGEFLAGS_fit-dtb.blob = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
-	-a 0 -e 0 -E \
-	$(patsubst %,-b arch/$(ARCH)/dts/%.dtb,$(subst ",,$(CONFIG_OF_LIST))) -d /dev/null
-
-u-boot-fit-dtb.bin: u-boot-nodtb.bin fit-dtb.blob
-	$(call if_changed,cat)
-
-u-boot.bin: u-boot-fit-dtb.bin FORCE
-	$(call if_changed,copy)
-else ifeq ($(CONFIG_OF_SEPARATE),y)
+ifeq ($(CONFIG_OF_SEPARATE),y)
 u-boot-dtb.bin: u-boot-nodtb.bin dts/dt.dtb FORCE
 	$(call if_changed,cat)

@@ -904,13 +841,7 @@ u-boot.bin: u-boot-nodtb.bin FORCE
 endif

 %.imx: %.bin
-	$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
-
-%.vyb: %.imx
-	$(Q)$(MAKE) $(build)=arch/arm/cpu/armv7/vf610 $@
-
-quiet_cmd_copy = COPY    $@
-      cmd_copy = cp $< $@
+	$(Q)$(MAKE) $(build)=arch/arm/imx-common $@

 u-boot.dtb: dts/dt.dtb
 	$(call cmd,copy)
@@ -923,7 +854,7 @@ u-boot.hex u-boot.srec: u-boot FORCE
 	$(call if_changed,objcopy)

 OBJCOPYFLAGS_u-boot-nodtb.bin := -O binary \
-		$(if $(CONFIG_X86_16BIT_INIT),-R .start16 -R .resetvec)
+		$(if $(CONFIG_X86_RESET_VECTOR),-R .start16 -R .resetvec)

 binary_size_check: u-boot-nodtb.bin FORCE
 	@file_size=$(shell wc -c u-boot-nodtb.bin | awk '{print $$1}') ; \
@@ -949,12 +880,6 @@ u-boot.ldr:	u-boot
 		$(LDR) -T $(CONFIG_CPU) -c $@ $< $(LDR_FLAGS)
 		$(BOARD_SIZE_CHECK)

-# binman
-# ---------------------------------------------------------------------------
-quiet_cmd_binman = BINMAN  $@
-cmd_binman = $(srctree)/tools/binman/binman -d u-boot.dtb -O . \
-		-I . -I $(srctree)/board/$(BOARDDIR) $<
-
 OBJCOPYFLAGS_u-boot.ldr.hex := -I binary -O ihex

 OBJCOPYFLAGS_u-boot.ldr.srec := -I binary -O srec
@@ -975,19 +900,6 @@ quiet_cmd_cpp_cfg = CFG     $@
 cmd_cpp_cfg = $(CPP) -Wp,-MD,$(depfile) $(cpp_flags) $(LDPPFLAGS) -ansi \
 	-DDO_DEPS_ONLY -D__ASSEMBLY__ -x assembler-with-cpp -P -dM -E -o $@ $<

-# Boards with more complex image requirments can provide an .its source file
-# or a generator script
-ifneq ($(CONFIG_SPL_FIT_SOURCE),"")
-U_BOOT_ITS = $(subst ",,$(CONFIG_SPL_FIT_SOURCE))
-else
-ifneq ($(CONFIG_SPL_FIT_GENERATOR),"")
-U_BOOT_ITS := u-boot.its
-$(U_BOOT_ITS): FORCE
-	$(srctree)/$(CONFIG_SPL_FIT_GENERATOR) \
-	$(patsubst %,arch/$(ARCH)/dts/%.dtb,$(subst ",,$(CONFIG_OF_LIST))) > $@
-endif
-endif
-
 ifdef CONFIG_SPL_LOAD_FIT
 MKIMAGEFLAGS_u-boot.img = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
 	-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
@@ -997,11 +909,6 @@ else
 MKIMAGEFLAGS_u-boot.img = -A $(ARCH) -T firmware -C none -O u-boot \
 	-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
 	-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board"
-MKIMAGEFLAGS_u-boot-ivt.img = -A $(ARCH) -T firmware_ivt -C none -O u-boot \
-	-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
-	-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board"
-u-boot-ivt.img: MKIMAGEOUTPUT = u-boot-ivt.img.log
-CLEAN_FILES += u-boot-ivt.img.log u-boot-dtb.imx.log SPL.log u-boot.imx.log
 endif

 MKIMAGEFLAGS_u-boot-dtb.img = $(MKIMAGEFLAGS_u-boot.img)
@@ -1010,19 +917,15 @@ MKIMAGEFLAGS_u-boot.kwb = -n $(srctree)/$(CONFIG_SYS_KWD_CONFIG:"%"=%) \
 	-T kwbimage -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE)

 MKIMAGEFLAGS_u-boot-spl.kwb = -n $(srctree)/$(CONFIG_SYS_KWD_CONFIG:"%"=%) \
-	-T kwbimage -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) \
-	$(if $(KEYDIR),-k $(KEYDIR))
+	-T kwbimage -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE)

 MKIMAGEFLAGS_u-boot.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \
 		-R $(srctree)/$(CONFIG_SYS_FSL_PBL_PBI:"%"=%) -T pblimage

-u-boot-dtb.img u-boot.img u-boot.kwb u-boot.pbl u-boot-ivt.img: \
+u-boot-dtb.img u-boot.img u-boot.kwb u-boot.pbl: \
 		$(if $(CONFIG_SPL_LOAD_FIT),u-boot-nodtb.bin dts/dt.dtb,u-boot.bin) FORCE
 	$(call if_changed,mkimage)

-u-boot.itb: u-boot-nodtb.bin dts/dt.dtb $(U_BOOT_ITS) FORCE
-	$(call if_changed,mkfitimage)
-
 u-boot-spl.kwb: u-boot.img spl/u-boot-spl.bin FORCE
 	$(call if_changed,mkimage)

@@ -1032,6 +935,9 @@ u-boot.sha1:	u-boot.bin
 u-boot.dis:	u-boot
 		$(OBJDUMP) -d $< > $@

+u-boot.cfg:	include/config.h FORCE
+	$(call if_changed,cpp_cfg)
+
 ifdef CONFIG_TPL
 SPL_PAYLOAD := tpl/u-boot-with-tpl.bin
 else
@@ -1069,10 +975,10 @@ tpl/u-boot-with-tpl.bin: tpl/u-boot-tpl.bin u-boot.bin FORCE
 	$(call if_changed,pad_cat)

 SPL: spl/u-boot-spl.bin FORCE
-	$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
+	$(Q)$(MAKE) $(build)=arch/arm/imx-common $@

 u-boot-with-spl.imx u-boot-with-nand-spl.imx: SPL u-boot.bin FORCE
-	$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
+	$(Q)$(MAKE) $(build)=arch/arm/imx-common $@

 MKIMAGEFLAGS_u-boot.ubl = -n $(UBL_CONFIG) -T ublimage -e $(CONFIG_SYS_TEXT_BASE)

@@ -1121,11 +1027,50 @@ endif

 # x86 uses a large ROM. We fill it with 0xff, put the 16-bit stuff (including
 # reset vector) at the top, Intel ME descriptor at the bottom, and U-Boot in
-# the middle. This is handled by binman based on an image description in the
-# board's device tree.
+# the middle.
 ifneq ($(CONFIG_X86_RESET_VECTOR),)
 rom: u-boot.rom FORCE

+IFDTOOL=$(objtree)/tools/ifdtool
+IFDTOOL_FLAGS  = -f 0:$(objtree)/u-boot.dtb
+IFDTOOL_FLAGS += -m 0x$(shell $(NM) u-boot |grep _dt_ucode_base_size |cut -d' ' -f1)
+IFDTOOL_FLAGS += -U $(CONFIG_SYS_TEXT_BASE):$(objtree)/u-boot-nodtb.bin
+IFDTOOL_FLAGS += -w $(CONFIG_SYS_X86_START16):$(objtree)/u-boot-x86-16bit.bin
+IFDTOOL_FLAGS += -C
+
+ifneq ($(CONFIG_HAVE_INTEL_ME),)
+IFDTOOL_ME_FLAGS  = -D $(srctree)/board/$(BOARDDIR)/descriptor.bin
+IFDTOOL_ME_FLAGS += -i ME:$(srctree)/board/$(BOARDDIR)/me.bin
+endif
+
+ifneq ($(CONFIG_HAVE_MRC),)
+IFDTOOL_FLAGS += -w $(CONFIG_X86_MRC_ADDR):$(srctree)/board/$(BOARDDIR)/mrc.bin
+endif
+
+ifneq ($(CONFIG_HAVE_FSP),)
+IFDTOOL_FLAGS += -w $(CONFIG_FSP_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_FSP_FILE)
+endif
+
+ifneq ($(CONFIG_HAVE_CMC),)
+IFDTOOL_FLAGS += -w $(CONFIG_CMC_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_CMC_FILE)
+endif
+
+ifneq ($(CONFIG_HAVE_VGA_BIOS),)
+IFDTOOL_FLAGS += -w $(CONFIG_VGA_BIOS_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_VGA_BIOS_FILE)
+endif
+
+ifneq ($(CONFIG_HAVE_REFCODE),)
+IFDTOOL_FLAGS += -w $(CONFIG_X86_REFCODE_ADDR):refcode.bin
+endif
+
+quiet_cmd_ifdtool = IFDTOOL $@
+cmd_ifdtool  = $(IFDTOOL) -c -r $(CONFIG_ROM_SIZE) u-boot.tmp;
+ifneq ($(CONFIG_HAVE_INTEL_ME),)
+cmd_ifdtool += $(IFDTOOL) $(IFDTOOL_ME_FLAGS) u-boot.tmp;
+endif
+cmd_ifdtool += $(IFDTOOL) $(IFDTOOL_FLAGS) u-boot.tmp;
+cmd_ifdtool += mv u-boot.tmp $@
+
 refcode.bin: $(srctree)/board/$(BOARDDIR)/refcode.bin FORCE
 	$(call if_changed,copy)

@@ -1133,27 +1078,23 @@ quiet_cmd_ldr = LD      $@
 cmd_ldr = $(LD) $(LDFLAGS_$(@F)) \
 	       $(filter-out FORCE,$^) -o $@

-u-boot.rom: u-boot-x86-16bit.bin u-boot.bin \
-		$(if $(CONFIG_SPL_X86_16BIT_INIT),spl/u-boot-spl.bin) \
-		$(if $(CONFIG_HAVE_REFCODE),refcode.bin) FORCE
-	$(call if_changed,binman)
+u-boot.rom: u-boot-x86-16bit.bin u-boot.bin FORCE \
+		$(if $(CONFIG_HAVE_REFCODE),refcode.bin)
+	$(call if_changed,ifdtool)

 OBJCOPYFLAGS_u-boot-x86-16bit.bin := -O binary -j .start16 -j .resetvec
 u-boot-x86-16bit.bin: u-boot FORCE
 	$(call if_changed,objcopy)
 endif

-ifneq ($(CONFIG_ARCH_SUNXI),)
-u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin u-boot.img u-boot.dtb FORCE
-	$(call if_changed,binman)
+ifneq ($(CONFIG_SUNXI),)
+OBJCOPYFLAGS_u-boot-sunxi-with-spl.bin = -I binary -O binary \
+				   --pad-to=$(CONFIG_SPL_PAD_TO) --gap-fill=0xff
+u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin u-boot.img FORCE
+	$(call if_changed,pad_cat)
 endif

 ifneq ($(CONFIG_TEGRA),)
-ifneq ($(CONFIG_BINMAN),)
-u-boot-dtb-tegra.bin u-boot-tegra.bin u-boot-nodtb-tegra.bin: \
-		spl/u-boot-spl u-boot.bin FORCE
-	$(call if_changed,binman)
-else
 OBJCOPYFLAGS_u-boot-nodtb-tegra.bin = -O binary --pad-to=$(CONFIG_SYS_TEXT_BASE)
 u-boot-nodtb-tegra.bin: spl/u-boot-spl u-boot-nodtb.bin FORCE
 	$(call if_changed,pad_cat)
@@ -1164,7 +1105,6 @@ u-boot-tegra.bin: spl/u-boot-spl u-boot.bin FORCE

 u-boot-dtb-tegra.bin: u-boot-tegra.bin FORCE
 	$(call if_changed,copy)
-endif  # binman
 endif

 OBJCOPYFLAGS_u-boot-app.efi := $(OBJCOPYFLAGS_EFI)
@@ -1182,7 +1122,7 @@ quiet_cmd_u-boot_payload ?= LD      $@
      cmd_u-boot_payload ?= $(LD) $(LDFLAGS_EFI_PAYLOAD) -o $@ \
      -T u-boot-payload.lds arch/x86/cpu/call32.o \
      lib/efi/efi.o lib/efi/efi_stub.o u-boot.bin.o \
-      $(addprefix arch/$(ARCH)/lib/,$(EFISTUB))
+      $(addprefix arch/$(ARCH)/lib/efi/,$(EFISTUB))

 u-boot-payload: u-boot.bin.o u-boot-payload.lds FORCE
 	$(call if_changed,u-boot_payload)
@@ -1227,19 +1167,17 @@ OBJCOPYFLAGS_u-boot-img-spl-at-end.bin := -I binary -O binary \
 u-boot-img-spl-at-end.bin: u-boot.img spl/u-boot-spl.bin FORCE
 	$(call if_changed,pad_cat)

-# Create a new ELF from a raw binary file.
-ifndef PLATFORM_ELFENTRY
-  PLATFORM_ELFENTRY = "_start"
-endif
-quiet_cmd_u-boot-elf ?= LD      $@
-	cmd_u-boot-elf ?= $(LD) u-boot-elf.o -o $@ \
-	--defsym=$(PLATFORM_ELFENTRY)=$(CONFIG_SYS_TEXT_BASE) \
-	-Ttext=$(CONFIG_SYS_TEXT_BASE)
+# Create a new ELF from a raw binary file.  This is useful for arm64
+# where static relocation needs to be performed on the raw binary,
+# but certain simulators only accept an ELF file (but don't do the
+# relocation).
+# FIXME refactor dts/Makefile to share target/arch detection
 u-boot.elf: u-boot.bin
-	$(Q)$(OBJCOPY) -I binary $(PLATFORM_ELFFLAGS) $< u-boot-elf.o
-	$(call if_changed,u-boot-elf)
-
-ARCH_POSTLINK := $(wildcard $(srctree)/arch/$(ARCH)/Makefile.postlink)
+	@$(OBJCOPY)  -B aarch64 -I binary -O elf64-littleaarch64 \
+		$< u-boot-elf.o
+	@$(LD) u-boot-elf.o -o $@ \
+		--defsym=_start=$(CONFIG_SYS_TEXT_BASE) \
+		-Ttext=$(CONFIG_SYS_TEXT_BASE)

 # Rule to link u-boot
 # May be overridden by arch/$(ARCH)/config.mk
@@ -1247,8 +1185,7 @@ quiet_cmd_u-boot__ ?= LD      $@
      cmd_u-boot__ ?= $(LD) $(LDFLAGS) $(LDFLAGS_u-boot) -o $@ \
      -T u-boot.lds $(u-boot-init)                             \
      --start-group $(u-boot-main) --end-group                 \
-      $(PLATFORM_LIBS) -Map u-boot.map;                        \
-      $(if $(ARCH_POSTLINK), $(MAKE) -f $(ARCH_POSTLINK) $@, true)
+      $(PLATFORM_LIBS) -Map u-boot.map

 quiet_cmd_smap = GEN     common/system_map.o
 cmd_smap = \
@@ -1258,7 +1195,7 @@ cmd_smap = \
 		-c $(srctree)/common/system_map.c -o common/system_map.o

 u-boot:	$(u-boot-init) $(u-boot-main) u-boot.lds FORCE
-	+$(call if_changed,u-boot__)
+	$(call if_changed,u-boot__)
 ifeq ($(CONFIG_KALLSYMS),y)
 	$(call cmd,smap)
 	$(call cmd,u-boot__) common/system_map.o
@@ -1365,7 +1302,6 @@ define filechk_timestamp.h
 			LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_TIME "%T"'; \
 			LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_TZ "%z"'; \
 			LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_DMI_DATE "%m/%d/%Y"'; \
-			LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_BUILD_DATE 0x%Y%m%d'; \
 		else \
 			return 42; \
 		fi; \
@@ -1374,7 +1310,6 @@ define filechk_timestamp.h
 		LC_ALL=C date +'#define U_BOOT_TIME "%T"'; \
 		LC_ALL=C date +'#define U_BOOT_TZ "%z"'; \
 		LC_ALL=C date +'#define U_BOOT_DMI_DATE "%m/%d/%Y"'; \
-		LC_ALL=C date +'#define U_BOOT_BUILD_DATE 0x%Y%m%d'; \
 	fi)
 endef

@@ -1395,24 +1330,19 @@ u-boot.lds: $(LDSCRIPT) prepare FORCE
 spl/u-boot-spl.bin: spl/u-boot-spl
 	@:
 spl/u-boot-spl: tools prepare \
-		$(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_SPL_OF_PLATDATA),dts/dt.dtb) \
-		$(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_TPL_OF_PLATDATA),dts/dt.dtb)
+		$(if $(CONFIG_OF_SEPARATE)$(CONFIG_SPL_OF_PLATDATA),dts/dt.dtb)
 	$(Q)$(MAKE) obj=spl -f $(srctree)/scripts/Makefile.spl all

 spl/sunxi-spl.bin: spl/u-boot-spl
 	@:

-spl/sunxi-spl-with-ecc.bin: spl/sunxi-spl.bin
-	@:
-
 spl/u-boot-spl.sfp: spl/u-boot-spl
 	@:

 spl/boot.bin: spl/u-boot-spl
 	@:

-tpl/u-boot-tpl.bin: tools prepare \
-		$(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_SPL_OF_PLATDATA),dts/dt.dtb)
+tpl/u-boot-tpl.bin: tools prepare
 	$(Q)$(MAKE) obj=tpl -f $(srctree)/scripts/Makefile.spl all

 TAG_SUBDIRS := $(patsubst %,$(srctree)/%,$(u-boot-dirs) include)
@@ -1440,6 +1370,12 @@ SYSTEM_MAP = \
 System.map:	u-boot
 		@$(call SYSTEM_MAP,$<) > $@

+checkdtc:
+	@if test $(call dtc-version) -lt 0104; then \
+		echo '*** Your dtc is too old, please upgrade to dtc 1.4 or newer'; \
+		false; \
+	fi
+
 #########################################################################

 # ARM relocations should all be R_ARM_RELATIVE (32-bit) or
@@ -1453,14 +1389,14 @@ checkarmreloc: u-boot
 		false; \
 	fi

-envtools: scripts_basic $(version_h) $(timestamp_h)
-	$(Q)$(MAKE) $(build)=tools/env
+env: scripts_basic
+	$(Q)$(MAKE) $(build)=tools/$@

 tools-only: scripts_basic $(version_h) $(timestamp_h)
 	$(Q)$(MAKE) $(build)=tools

 tools-all: export HOST_TOOLS_ALL=y
-tools-all: envtools tools ;
+tools-all: env tools ;

 cross_tools: export CROSS_BUILD_TOOLS=y
 cross_tools: tools ;
@@ -1484,8 +1420,8 @@ CLEAN_DIRS  += $(MODVERDIR) \
 	       $(foreach d, spl tpl, $(patsubst %,$d/%, \
 			$(filter-out include, $(shell ls -1 $d 2>/dev/null))))

-CLEAN_FILES += include/bmp_logo.h include/bmp_logo_data.h \
-	       boot* u-boot* MLO* SPL System.map fit-dtb.blob
+CLEAN_FILES += include/bmp_logo.h include/bmp_logo_data.h include/license.h \
+	       boot* u-boot* MLO* SPL System.map

 # Directories & files removed with 'make mrproper'
 MRPROPER_DIRS  += include/config include/generated spl tpl \
@@ -1573,12 +1509,9 @@ help:
 	@echo  '  cscope	  - Generate cscope index'
 	@echo  '  ubootrelease	  - Output the release version string (use with make -s)'
 	@echo  '  ubootversion	  - Output the version stored in Makefile (use with make -s)'
-	@echo  "  cfg		  - Don't build, just create the .cfg files"
-	@echo  "  envtools	  - Build only the target-side environment tools"
 	@echo  ''
 	@echo  'Static analysers'
 	@echo  '  checkstack      - Generate a list of stack hogs'
-	@echo  '  coccicheck      - Execute static code analysis with Coccinelle'
 	@echo  ''
 	@echo  'Documentation targets:'
 	@$(MAKE) -f $(srctree)/doc/DocBook/Makefile dochelp
@@ -1607,6 +1540,11 @@ tests:
 	$(Q)$(MAKE) $(build)=scripts build_docproc
 	$(Q)$(MAKE) $(build)=doc/DocBook $@

+# Dummies...
+PHONY += prepare scripts
+prepare: ;
+scripts: ;
+
 endif #ifeq ($(config-targets),1)
 endif #ifeq ($(mixed-targets),1)

@@ -1671,14 +1609,6 @@ endif
 	$(build)=$(build-dir) $(@:.ko=.o)
 	$(Q)$(MAKE) -f $(srctree)/scripts/Makefile.modpost

-# Consistency checks
-# ---------------------------------------------------------------------------
-
-PHONY += coccicheck
-
-coccicheck:
-	$(Q)$(CONFIG_SHELL) $(srctree)/scripts/$@
-
 # FIXME Should go into a make.lib or something
 # ===========================================================================

--- a/1486
+++ b/1486
--- a/api/Kconfig
+++ b/api/Kconfig
@@ -1,9 +0,0 @@
-menu "API"
-
-config API
-	bool "Enable U-Boot API"
-	default n
-	help
-	  This option enables the U-Boot API. See api/README for more information.
-
-endmenu
--- a/api/api.c
+++ b/api/api.c
@@ -458,7 +458,7 @@ static int API_env_get(va_list ap)
 	if ((value = (char **)va_arg(ap, uintptr_t)) == NULL)
 		return API_EINVAL;

-	*value = env_get(name);
+	*value = getenv(name);

 	return 0;
 }
@@ -481,7 +481,7 @@ static int API_env_set(va_list ap)
 	if ((value = (char *)va_arg(ap, uintptr_t)) == NULL)
 		return API_EINVAL;

-	env_set(name, value);
+	setenv(name, value);

 	return 0;
 }
@@ -495,47 +495,45 @@ static int API_env_set(va_list ap)
 */
 static int API_env_enum(va_list ap)
 {
-	int i, buflen;
-	char *last, **next, *s;
-	ENTRY *match, search;
-	static char *var;
+	int i, n;
+	char *last, **next;

 	last = (char *)va_arg(ap, unsigned long);

 	if ((next = (char **)va_arg(ap, uintptr_t)) == NULL)
 		return API_EINVAL;

-	if (last == NULL) {
-		var = NULL;
-		i = 0;
-	} else {
-		var = strdup(last);
-		s = strchr(var, '=');
-		if (s != NULL)
-			*s = 0;
-		search.key = var;
-		i = hsearch_r(search, FIND, &match, &env_htab, 0);
-		if (i == 0) {
-			i = API_EINVAL;
-			goto done;
+	if (last == NULL)
+		/* start over */
+		*next = ((char *)env_get_addr(0));
+	else {
+		*next = last;
+
+		for (i = 0; env_get_char(i) != '\0'; i = n + 1) {
+			for (n = i; env_get_char(n) != '\0'; ++n) {
+				if (n >= CONFIG_ENV_SIZE) {
+					/* XXX shouldn't we set *next = NULL?? */
+					return 0;
+				}
+			}
+
+			if (envmatch((uchar *)last, i) < 0)
+				continue;
+
+			/* try to get next name */
+			i = n + 1;
+			if (env_get_char(i) == '\0') {
+				/* no more left */
+				*next = NULL;
+				return 0;
+			}
+
+			*next = ((char *)env_get_addr(i));
+			return 0;
 		}
 	}

-	/* match the next entry after i */
-	i = hmatch_r("", i, &match, &env_htab);
-	if (i == 0)
-		goto done;
-	buflen = strlen(match->key) + strlen(match->data) + 2;
-	var = realloc(var, buflen);
-	snprintf(var, buflen, "%s=%s", match->key, match->data);
-	*next = var;
 	return 0;
-
-done:
-	free(var);
-	var = NULL;
-	*next = NULL;
-	return i;
 }

 /*
@@ -625,7 +623,7 @@ int syscall(int call, int *retval, ...)

 void api_init(void)
 {
-	struct api_signature *sig;
+	struct api_signature *sig = NULL;

 	/* TODO put this into linker set one day... */
 	calls_table[API_RSVD] = NULL;
@@ -663,7 +661,7 @@ void api_init(void)
 		return;
 	}

-	env_set_hex("api_address", (unsigned long)sig);
+	setenv_hex("api_address", (unsigned long)sig);
 	debugf("API sig @ 0x%lX\n", (unsigned long)sig);
 	memcpy(sig->magic, API_SIG_MAGIC, 8);
 	sig->version = API_SIG_VERSION;
--- a/api/api_platform-powerpc.c
+++ b/api/api_platform-powerpc.c
@@ -30,8 +30,11 @@ int platform_sys_info(struct sys_info *si)
 	si->clk_bus = gd->bus_clk;
 	si->clk_cpu = gd->cpu_clk;

-#if defined(CONFIG_8xx) || defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
+#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_MPC8260) || \
+    defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
 #define bi_bar	bi_immr_base
+#elif defined(CONFIG_MPC5xxx)
+#define bi_bar	bi_mbar_base
 #elif defined(CONFIG_MPC83xx)
 #define bi_bar	bi_immrbar
 #endif
--- a/api/api_storage.c
+++ b/api/api_storage.c
@@ -37,19 +37,16 @@ struct stor_spec {
 	int		max_dev;
 	int		enum_started;
 	int		enum_ended;
-	int		type;	/* "external" type: DT_STOR_{IDE,USB,etc} */
+	int		type;		/* "external" type: DT_STOR_{IDE,USB,etc} */
 	char		*name;
 };

-static struct stor_spec specs[ENUM_MAX] = { { 0, 0, 0, 0, NULL }, };
+static struct stor_spec specs[ENUM_MAX] = { { 0, 0, 0, 0, "" }, };

-#ifndef CONFIG_SYS_MMC_MAX_DEVICE
-#define CONFIG_SYS_MMC_MAX_DEVICE	1
-#endif

 void dev_stor_init(void)
 {
-#if defined(CONFIG_IDE)
+#if defined(CONFIG_CMD_IDE)
 	specs[ENUM_IDE].max_dev = CONFIG_SYS_IDE_MAXDEVICE;
 	specs[ENUM_IDE].enum_started = 0;
 	specs[ENUM_IDE].enum_ended = 0;
@@ -63,7 +60,7 @@ void dev_stor_init(void)
 	specs[ENUM_MMC].type = DEV_TYP_STOR | DT_STOR_MMC;
 	specs[ENUM_MMC].name = "mmc";
 #endif
-#if defined(CONFIG_SATA)
+#if defined(CONFIG_CMD_SATA)
 	specs[ENUM_SATA].max_dev = CONFIG_SYS_SATA_MAX_DEVICE;
 	specs[ENUM_SATA].enum_started = 0;
 	specs[ENUM_SATA].enum_ended = 0;
@@ -91,67 +88,88 @@ void dev_stor_init(void)
 *
 * type:	storage group type - ENUM_IDE, ENUM_SCSI etc.
 *
+ * first:	if 1 the first device in the storage group is returned (if
+ *              exists), if 0 the next available device is searched
+ *
 * more:	returns 0/1 depending if there are more devices in this group
 *		available (for future iterations)
 *
 * returns:	0/1 depending if device found in this iteration
 */
-static int dev_stor_get(int type, int *more, struct device_info *di)
+static int dev_stor_get(int type, int first, int *more, struct device_info *di)
 {
-	struct blk_desc *dd;
 	int found = 0;
-	int i = 0;
+	*more = 0;

-	/* Wasn't configured for this type, return 0 directly */
-	if (specs[type].name == NULL)
-		return 0;
+	int i;

-	if (di->cookie != NULL) {
-		/* Find the last device we've returned  */
-		for (i = 0; i < specs[type].max_dev; i++) {
+	struct blk_desc *dd;
+
+	if (first) {
+		di->cookie = (void *)blk_get_dev(specs[type].name, 0);
+		if (di->cookie == NULL)
+			return 0;
+		else
+			found = 1;
+
+		/* provide hint if there are more devices in
+		 * this group to enumerate */
+		if (1 < specs[type].max_dev)
+			*more = 1;
+
+	} else {
+		for (i = 0; i < specs[type].max_dev; i++)
 			if (di->cookie ==
 			    (void *)blk_get_dev(specs[type].name, i)) {
-				i += 1;
+				/* previous cookie found -- advance to the
+				 * next device, if possible */
+
+				if (++i >= specs[type].max_dev) {
+					/* out of range, no more to enum */
+					di->cookie = NULL;
+					break;
+				}
+
+				di->cookie = (void *)blk_get_dev(
+							specs[type].name, i);
+				if (di->cookie == NULL)
+					return 0;
+				else
+					found = 1;
+
+				/* provide hint if there are more devices in
+				 * this group to enumerate */
+				if ((i + 1) < specs[type].max_dev)
+					*more = 1;
+
 				break;
 			}
-		}
 	}

-	for (; i < specs[type].max_dev; i++) {
-		di->cookie = (void *)blk_get_dev(specs[type].name, i);
-
-		if (di->cookie != NULL) {
-			found = 1;
-			break;
-		}
-	}
-
-	if (i == specs[type].max_dev)
-		*more = 0;
-	else
-		*more = 1;
-
 	if (found) {
 		di->type = specs[type].type;

-		dd = (struct blk_desc *)di->cookie;
-		if (dd->type == DEV_TYPE_UNKNOWN) {
-			debugf("device instance exists, but is not active..");
-			found = 0;
-		} else {
-			di->di_stor.block_count = dd->lba;
-			di->di_stor.block_size = dd->blksz;
+		if (di->cookie != NULL) {
+			dd = (struct blk_desc *)di->cookie;
+			if (dd->type == DEV_TYPE_UNKNOWN) {
+				debugf("device instance exists, but is not active..");
+				found = 0;
+			} else {
+				di->di_stor.block_count = dd->lba;
+				di->di_stor.block_size = dd->blksz;
+			}
 		}
-	} else {
+
+	} else
 		di->cookie = NULL;
-	}

 	return found;
 }


-/* returns: ENUM_IDE, ENUM_USB etc. based on struct blk_desc */
-
+/*
+ * returns:	ENUM_IDE, ENUM_USB etc. based on struct blk_desc
+ */
 static int dev_stor_type(struct blk_desc *dd)
 {
 	int i, j;
@@ -165,8 +183,9 @@ static int dev_stor_type(struct blk_desc *dd)
 }


-/* returns: 0/1 whether cookie points to some device in this group */
-
+/*
+ * returns:	0/1 whether cookie points to some device in this group
+ */
 static int dev_is_stor(int type, struct device_info *di)
 {
 	return (dev_stor_type(di->cookie) == type) ? 1 : 0;
@@ -197,16 +216,18 @@ static int dev_enum_stor(int type, struct device_info *di)
 	 */

 	if (di->cookie == NULL) {
+
 		debugf("group%d - enum restart\n", type);

 		/*
 		 * 1. Enumeration (re-)started: take the first available
 		 * device, if exists
 		 */
-		found = dev_stor_get(type, &more, di);
+		found = dev_stor_get(type, 1, &more, di);
 		specs[type].enum_started = 1;

 	} else if (dev_is_stor(type, di)) {
+
 		debugf("group%d - enum continued for the next device\n", type);

 		if (specs[type].enum_ended) {
@@ -215,9 +236,10 @@ static int dev_enum_stor(int type, struct device_info *di)
 		}

 		/* 2a. Attempt to take a next available device in the group */
-		found = dev_stor_get(type, &more, di);
+		found = dev_stor_get(type, 0, &more, di);

 	} else {
+
 		if (specs[type].enum_ended) {
 			debugf("group %d - already enumerated, skipping\n", type);
 			return 0;
@@ -229,7 +251,7 @@ static int dev_enum_stor(int type, struct device_info *di)
 			/*
 			 * 2b.  If enumerating devices in this group did not
 			 * happen before, it means the cookie pointed to a
-			 * device from some other group (another storage
+			 * device frome some other group (another storage
 			 * group, or network); in this case try to take the
 			 * first available device from our group
 			 */
@@ -239,7 +261,7 @@ static int dev_enum_stor(int type, struct device_info *di)
 			 * Attempt to take the first device in this group:
 			 *'first element' flag is set
 			 */
-			found = dev_stor_get(type, &more, di);
+			found = dev_stor_get(type, 1, &more, di);

 		} else {
 			errf("group%d - out of order iteration\n", type);
@@ -256,7 +278,7 @@ static int dev_enum_stor(int type, struct device_info *di)

 	if (found)
 		debugf("device found, returning cookie 0x%08x\n",
-		       (u_int32_t)di->cookie);
+			(u_int32_t)di->cookie);
 	else
 		debugf("no device found\n");

@@ -277,7 +299,9 @@ int dev_enum_storage(struct device_info *di)
 {
 	int i;

-	/* check: ide, usb, scsi, mmc */
+	/*
+	 * check: ide, usb, scsi, mmc
+	 */
 	for (i = ENUM_IDE; i < ENUM_MAX; i ++) {
 		if (dev_enum_stor(i, di))
 			return 1;
@@ -334,14 +358,10 @@ lbasize_t dev_read_stor(void *cookie, void *buf, lbasize_t len, lbastart_t start
 	if (!dev_stor_is_valid(type, dd))
 		return 0;

-#ifdef CONFIG_BLK
-	return blk_dread(dd, start, len, buf);
-#else
 	if ((dd->block_read) == NULL) {
 		debugf("no block_read() for device 0x%08x\n", cookie);
 		return 0;
 	}

 	return dd->block_read(dd, start, len, buf);
-#endif	/* defined(CONFIG_BLK) */
 }
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -12,10 +12,6 @@ config ARC
 	bool "ARC architecture"
 	select HAVE_PRIVATE_LIBGCC
 	select SUPPORT_OF_CONTROL
-	select ARCH_EARLY_INIT_R
-	select CLK
-	select TIMER
-	select ARC_TIMER

 config ARM
 	bool "ARM architecture"
@@ -23,6 +19,13 @@ config ARM
 	select HAVE_PRIVATE_LIBGCC if !ARM64
 	select SUPPORT_OF_CONTROL

+config AVR32
+	bool "AVR32 architecture"
+	select CREATE_ARCH_SYMLINK
+
+config BLACKFIN
+	bool "Blackfin architecture"
+
 config M68K
 	bool "M68000 architecture"
 	select HAVE_PRIVATE_LIBGCC
@@ -30,7 +33,6 @@ config M68K
 config MICROBLAZE
 	bool "MicroBlaze architecture"
 	select SUPPORT_OF_CONTROL
-	imply CMD_IRQ

 config MIPS
 	bool "MIPS architecture"
@@ -40,7 +42,6 @@ config MIPS

 config NDS32
 	bool "NDS32 architecture"
-	select SUPPORT_OF_CONTROL

 config NIOS2
 	bool "Nios II architecture"
@@ -49,6 +50,9 @@ config NIOS2
 	select DM
 	select CPU

+config OPENRISC
+	bool "OpenRISC architecture"
+
 config PPC
 	bool "PowerPC architecture"
 	select HAVE_PRIVATE_LIBGCC
@@ -56,68 +60,33 @@ config PPC

 config SANDBOX
 	bool "Sandbox"
-	select BOARD_LATE_INIT
 	select SUPPORT_OF_CONTROL
 	select DM
-	select DM_KEYBOARD
 	select DM_SPI_FLASH
 	select DM_SERIAL
 	select DM_I2C
 	select DM_SPI
 	select DM_GPIO
 	select DM_MMC
-	select LZO
-	imply CMD_GETTIME
-	imply CMD_HASH
-	imply CMD_IO
-	imply CMD_IOTRACE
-	imply CMD_LZMADEC
-	imply CRC32_VERIFY
-	imply FAT_WRITE
-	imply HASH_VERIFY
-	imply LZMA
-	imply SCSI
-	imply CMD_SATA
-	imply CMD_SF_TEST

 config SH
 	bool "SuperH architecture"
 	select HAVE_PRIVATE_LIBGCC

+config SPARC
+	bool "SPARC architecture"
+	select CREATE_ARCH_SYMLINK
+
 config X86
 	bool "x86 architecture"
 	select CREATE_ARCH_SYMLINK
 	select HAVE_PRIVATE_LIBGCC
-	select USE_PRIVATE_LIBGCC
 	select SUPPORT_OF_CONTROL
-	select OF_CONTROL
 	select DM
-	select DM_PCI
-	select PCI
-	select TIMER
-	select X86_TSC_TIMER
-	imply BLK
-	imply DM_ETH
-	imply DM_GPIO
-	imply DM_KEYBOARD
-	imply DM_MMC
-	imply DM_RTC
-	imply DM_SERIAL
-	imply DM_SCSI
-	imply DM_SPI
-	imply DM_SPI_FLASH
-	imply DM_USB
-	imply DM_VIDEO
-	imply CMD_FPGA_LOADMK
-	imply CMD_GETTIME
-	imply CMD_IO
-	imply CMD_IRQ
-	imply CMD_PCI
-	imply CMD_SF_TEST
-	imply CMD_ZBOOT
-	imply USB_HOST_ETHER
-	imply USB_ETHER_ASIX
-	imply USB_ETHER_SMSC95XX
+	select DM_SERIAL
+	select DM_GPIO
+	select DM_SPI
+	select DM_SPI_FLASH

 config XTENSA
 	bool "Xtensa architecture"
@@ -184,13 +153,17 @@ config SYS_CONFIG_NAME

 source "arch/arc/Kconfig"
 source "arch/arm/Kconfig"
+source "arch/avr32/Kconfig"
+source "arch/blackfin/Kconfig"
 source "arch/m68k/Kconfig"
 source "arch/microblaze/Kconfig"
 source "arch/mips/Kconfig"
 source "arch/nds32/Kconfig"
 source "arch/nios2/Kconfig"
+source "arch/openrisc/Kconfig"
 source "arch/powerpc/Kconfig"
 source "arch/sandbox/Kconfig"
 source "arch/sh/Kconfig"
+source "arch/sparc/Kconfig"
 source "arch/x86/Kconfig"
 source "arch/xtensa/Kconfig"
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -118,7 +118,7 @@ config SYS_DCACHE_OFF

 choice
 	prompt "Target select"
-	default TARGET_AXS103
+	default TARGET_AXS10X

 config TARGET_TB100
 	bool "Support tb100"
@@ -126,20 +126,13 @@ config TARGET_TB100
 config TARGET_NSIM
 	bool "Support standalone nSIM & Free nSIM"

-config TARGET_AXS101
-	bool "Support Synopsys Designware SDP board AXS101"
-
-config TARGET_AXS103
-	bool "Support Synopsys Designware SDP board AXS103"
-
-config TARGET_HSDK
-	bool "Support Synpsys HS DevelopmentKit board"
+config TARGET_AXS10X
+	bool "Support Synopsys Designware SDP board (AXS101 & AXS103)"

 endchoice

 source "board/abilis/tb100/Kconfig"
 source "board/synopsys/Kconfig"
 source "board/synopsys/axs10x/Kconfig"
-source "board/synopsys/hsdk/Kconfig"

 endmenu
--- a/arch/arc/config.mk
+++ b/arch/arc/config.mk
@@ -31,15 +31,15 @@ CONFIG_MMU = 1
 endif

 ifdef CONFIG_CPU_ARC750D
-PLATFORM_CPPFLAGS += -mcpu=arc700
+PLATFORM_CPPFLAGS += -marc700
 endif

 ifdef CONFIG_CPU_ARC770D
-PLATFORM_CPPFLAGS += -mcpu=arc700 -mlock -mswape
+PLATFORM_CPPFLAGS += -marc700 -mlock -mswape
 endif

 ifdef CONFIG_CPU_ARCEM6
-PLATFORM_CPPFLAGS += -mcpu=arcem
+PLATFORM_CPPFLAGS += -marcem
 endif

 ifdef CONFIG_CPU_ARCHS34
--- a/arch/arc/dts/Makefile
+++ b/arch/arc/dts/Makefile
@@ -2,11 +2,9 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #

-dtb-$(CONFIG_TARGET_AXS101) +=  axs101.dtb
-dtb-$(CONFIG_TARGET_AXS103) +=  axs103.dtb
+dtb-$(CONFIG_TARGET_AXS10X) +=  axs10x.dtb
 dtb-$(CONFIG_TARGET_NSIM) +=  nsim.dtb
 dtb-$(CONFIG_TARGET_TB100) +=  abilis_tb100.dtb
-dtb-$(CONFIG_TARGET_HSDK) +=  hsdk.dtb

 targets += $(dtb-y)

--- a/arch/arc/dts/abilis_tb100.dts
+++ b/arch/arc/dts/abilis_tb100.dts
@@ -8,19 +8,13 @@
 #include "skeleton.dtsi"

 / {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
 	aliases {
 		console = &uart0;
 	};

-	cpu_card {
-		core_clk: core_clk {
-			#clock-cells = <0>;
-			compatible = "fixed-clock";
-			clock-frequency = <500000000>;
-			u-boot,dm-pre-reloc;
-		};
-	};
-
 	uart0: serial@ff100000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0xff100000 0x1000>;
--- a/arch/arc/dts/axc001.dtsi
+++ b/arch/arc/dts/axc001.dtsi
@@ -1,19 +0,0 @@
-/*
- * Copyright (C) 2017 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/include/ "skeleton.dtsi"
-
-/ {
-	cpu_card {
-		core_clk: core_clk {
-			#clock-cells = <0>;
-			compatible = "fixed-clock";
-			clock-frequency = <750000000>;
-			u-boot,dm-pre-reloc;
-		};
-	};
-};
-
--- a/arch/arc/dts/axc003.dtsi
+++ b/arch/arc/dts/axc003.dtsi
@@ -1,19 +0,0 @@
-/*
- * Copyright (C) 2017 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/include/ "skeleton.dtsi"
-
-/ {
-	cpu_card {
-		core_clk: core_clk {
-			#clock-cells = <0>;
-			compatible = "fixed-clock";
-			clock-frequency = <100000000>;
-			u-boot,dm-pre-reloc;
-		};
-	};
-};
-
--- a/arch/arc/dts/axs101.dts
+++ b/arch/arc/dts/axs101.dts
@@ -1,17 +0,0 @@
-/*
- * Copyright (C) 2017 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-/dts-v1/;
-
-/include/ "axc001.dtsi"
-/include/ "axs10x_mb.dtsi"
-
-
-/ {
-	chosen {
-		stdout-path = &uart0;
-	};
-};
-
--- a/arch/arc/dts/axs103.dts
+++ b/arch/arc/dts/axs103.dts
@@ -1,17 +0,0 @@
-/*
- * Copyright (C) 2017 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-/dts-v1/;
-
-/include/ "axc003.dtsi"
-/include/ "axs10x_mb.dtsi"
-
-
-/ {
-	chosen {
-		stdout-path = &uart0;
-	};
-};
-
--- a/arch/arc/dts/axs10x.dts
+++ b/arch/arc/dts/axs10x.dts
@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2015 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+/dts-v1/;
+
+#include "skeleton.dtsi"
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	aliases {
+		console = &uart0;
+	};
+
+	clocks {
+		apbclk: apbclk {
+			compatible = "fixed-clock";
+			clock-frequency = <50000000>;
+			#clock-cells = <0>;
+		};
+	};
+
+	uart0: serial0@e0022000 {
+		compatible = "snps,dw-apb-uart";
+		reg = <0xe0022000 0x1000>;
+		reg-shift = <2>;
+		reg-io-width = <4>;
+	};
+
+	ethernet@e0018000 {
+		#interrupt-cells = <1>;
+		compatible = "altr,socfpga-stmmac";
+		reg = < 0xe0018000 0x2000 >;
+		interrupts = < 25 >;
+		interrupt-names = "macirq";
+		phy-mode = "gmii";
+		snps,pbl = < 32 >;
+		clocks = <&apbclk>;
+		clock-names = "stmmaceth";
+		max-speed = <100>;
+	};
+
+	ehci@0xe0040000 {
+		compatible = "generic-ehci";
+		reg = < 0xe0040000 0x100 >;
+		interrupts = < 8 >;
+	};
+
+	ohci@0xe0060000 {
+		compatible = "generic-ohci";
+		reg = < 0xe0060000 0x100 >;
+		interrupts = < 8 >;
+	};
+};
--- a/arch/arc/dts/axs10x_mb.dtsi
+++ b/arch/arc/dts/axs10x_mb.dtsi
@@ -1,66 +0,0 @@
-/*
- * Copyright (C) 2017 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/ {
-	axs10x_mb@e0000000 {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0x00000000 0xe0000000 0x10000000>;
-		u-boot,dm-pre-reloc;
-
-		clocks {
-			compatible = "simple-bus";
-			u-boot,dm-pre-reloc;
-
-			apbclk: apbclk {
-				compatible = "fixed-clock";
-				clock-frequency = <50000000>;
-				#clock-cells = <0>;
-			};
-
-			uartclk: uartclk {
-				compatible = "fixed-clock";
-				clock-frequency = <33333333>;
-				#clock-cells = <0>;
-				u-boot,dm-pre-reloc;
-			};
-		};
-
-		ethernet@18000 {
-			#interrupt-cells = <1>;
-			compatible = "altr,socfpga-stmmac";
-			reg = < 0x18000 0x2000 >;
-			interrupts = < 25 >;
-			interrupt-names = "macirq";
-			phy-mode = "gmii";
-			snps,pbl = < 32 >;
-			clocks = <&apbclk>;
-			clock-names = "stmmaceth";
-			max-speed = <100>;
-		};
-
-		ehci@0x40000 {
-			compatible = "generic-ehci";
-			reg = < 0x40000 0x100 >;
-			interrupts = < 8 >;
-		};
-
-		ohci@0x60000 {
-			compatible = "generic-ohci";
-			reg = < 0x60000 0x100 >;
-			interrupts = < 8 >;
-		};
-
-		uart0: serial0@22000 {
-			compatible = "snps,dw-apb-uart";
-			reg = <0x22000 0x100>;
-			clocks = <&uartclk>;
-			reg-shift = <2>;
-			reg-io-width = <4>;
-		};
-	};
-};
--- a/arch/arc/dts/hsdk.dts
+++ b/arch/arc/dts/hsdk.dts
@@ -1,50 +0,0 @@
-/*
- * Copyright (C) 2017 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-/dts-v1/;
-
-#include "skeleton.dtsi"
-
-/ {
-	#address-cells = <1>;
-	#size-cells = <1>;
-
-	aliases {
-		console = &uart0;
-	};
-
-	cpu_card {
-		core_clk: core_clk {
-			#clock-cells = <0>;
-			compatible = "fixed-clock";
-			clock-frequency = <1000000000>;
-			u-boot,dm-pre-reloc;
-		};
-	};
-
-	uart0: serial0@f0005000 {
-		compatible = "snps,dw-apb-uart";
-		reg = <0xf0005000 0x1000>;
-		reg-shift = <2>;
-		reg-io-width = <4>;
-	};
-
-	ethernet@f0008000 {
-		#interrupt-cells = <1>;
-		compatible = "altr,socfpga-stmmac";
-		reg = <0xf0008000 0x2000>;
-		phy-mode = "gmii";
-	};
-
-	ehci@0xf0040000 {
-		compatible = "generic-ehci";
-		reg = <0xf0040000 0x100>;
-	};
-
-	ohci@0xf0060000 {
-		compatible = "generic-ohci";
-		reg = <0xf0060000 0x100>;
-	};
-};
--- a/arch/arc/dts/nsim.dts
+++ b/arch/arc/dts/nsim.dts
@@ -8,23 +8,17 @@
 #include "skeleton.dtsi"

 / {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
 	aliases {
 		console = &arcuart0;
 	};

-	cpu_card {
-		core_clk: core_clk {
-			#clock-cells = <0>;
-			compatible = "fixed-clock";
-			clock-frequency = <70000000>;
-			u-boot,dm-pre-reloc;
-		};
-	};
-
 	arcuart0: serial@0xc0fc1000 {
 		compatible = "snps,arc-uart";
 		reg = <0xc0fc1000 0x100>;
-		clock-frequency = <70000000>;
+		clock-frequency = <80000000>;
 	};

 };
--- a/arch/arc/dts/skeleton.dtsi
+++ b/arch/arc/dts/skeleton.dtsi
@@ -9,22 +9,5 @@
 	#size-cells = <1>;
 	chosen { };
 	aliases { };
-
-	cpu_card {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		u-boot,dm-pre-reloc;
-
-		timer@0 {
-			compatible = "snps,arc-timer";
-			clocks = <&core_clk>;
-			reg = <0 1>;
-		};
-	};
-
-	memory@80000000 {
-		device_type = "memory";
-		reg = <0x80000000 0x10000000>; /* 256M */
-	};
+	memory { device_type = "memory"; reg = <0 0>; };
 };
--- a/arch/arc/include/asm/arcregs.h
+++ b/arch/arc/include/asm/arcregs.h
@@ -27,22 +27,12 @@
 #define ARC_AUX_IC_PTAG		0x1E
 #endif
 #define ARC_BCR_IC_BUILD	0x77
-#define AUX_AUX_CACHE_LIMIT		0x5D
-#define ARC_AUX_NON_VOLATILE_LIMIT	0x5E
-
-/* ICCM and DCCM auxiliary registers */
-#define ARC_AUX_DCCM_BASE	0x18	/* DCCM Base Addr ARCv2 */
-#define ARC_AUX_ICCM_BASE	0x208	/* ICCM Base Addr ARCv2 */

 /* Timer related auxiliary registers */
 #define ARC_AUX_TIMER0_CNT	0x21	/* Timer 0 count */
 #define ARC_AUX_TIMER0_CTRL	0x22	/* Timer 0 control */
 #define ARC_AUX_TIMER0_LIMIT	0x23	/* Timer 0 limit */

-#define ARC_AUX_TIMER1_CNT	0x100	/* Timer 1 count */
-#define ARC_AUX_TIMER1_CTRL	0x101	/* Timer 1 control */
-#define ARC_AUX_TIMER1_LIMIT	0x102	/* Timer 1 limit */
-
 #define ARC_AUX_INTR_VEC_BASE	0x25

 /* Data cache related auxiliary registers */
@@ -78,9 +68,6 @@
 /* gcc builtin sr needs reg param to be long immediate */
 #define write_aux_reg(reg_immed, val)		\
 		__builtin_arc_sr((unsigned int)val, reg_immed)
-
-/* ARCNUM [15:8] - field to identify each core in a multi-core system */
-#define CPU_ID_GET()	((read_aux_reg(ARC_AUX_IDENTITY) & 0xFF00) >> 8)
 #endif /* __ASSEMBLY__ */

 #endif /* _ASM_ARC_ARCREGS_H */
--- a/arch/arc/include/asm/config.h
+++ b/arch/arc/include/asm/config.h
@@ -8,6 +8,7 @@
 #define __ASM_ARC_CONFIG_H_

 #define CONFIG_SYS_BOOT_RAMDISK_HIGH
+#define CONFIG_ARCH_EARLY_INIT_R

 #define CONFIG_LMB

--- a/arch/arc/include/asm/errno.h
+++ b/arch/arc/include/asm/errno.h
@@ -0,0 +1 @@
+#include <asm-generic/errno.h>
--- a/arch/arc/include/asm/gpio.h
+++ b/arch/arc/include/asm/gpio.h
@@ -1 +0,0 @@
-#include <asm-generic/gpio.h>
--- a/arch/arc/include/asm/init_helpers.h
+++ b/arch/arc/include/asm/init_helpers.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (C) 2013-2015 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ASM_ARC_INIT_HELPERS_H
+#define _ASM_ARC_INIT_HELPERS_H
+
+int init_cache_f_r(void);
+
+#endif	/* _ASM_ARC_INIT_HELPERS_H */
--- a/arch/arc/include/asm/io.h
+++ b/arch/arc/include/asm/io.h
@@ -50,6 +50,30 @@
 #define __iowmb()		do { } while (0)
 #endif

+/*
+ * Given a physical address and a length, return a virtual address
+ * that can be used to access the memory range with the caching
+ * properties specified by "flags".
+ */
+#define MAP_NOCACHE	(0)
+#define MAP_WRCOMBINE	(0)
+#define MAP_WRBACK	(0)
+#define MAP_WRTHROUGH	(0)
+
+static inline void *
+map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
+{
+	return (void *)((unsigned long)paddr);
+}
+
+/*
+ * Take down a mapping set up by map_physmem().
+ */
+static inline void unmap_physmem(void *vaddr, unsigned long flags)
+{
+
+}
+
 static inline void sync(void)
 {
 	/* Not yet implemented */
@@ -278,6 +302,9 @@ static inline int __raw_writesl(unsigned int addr, void *data, int longlen)
 #define setbits_8(addr, set) setbits(8, addr, set)
 #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)

-#include <asm-generic/io.h>
+static inline phys_addr_t virt_to_phys(void *vaddr)
+{
+	return (phys_addr_t)((unsigned long)vaddr);
+}

 #endif	/* __ASM_ARC_IO_H */
--- a/arch/arc/include/asm/relocate.h
+++ b/arch/arc/include/asm/relocate.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) 2013-2015 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ASM_ARC_RELOCATE_H
+#define _ASM_ARC_RELOCATE_H
+
+#include <common.h>
+
+int copy_uboot_to_ram(void);
+int clear_bss(void);
+int do_elf_reloc_fixups(void);
+
+#endif	/* _ASM_ARC_RELOCATE_H */
--- a/arch/arc/include/asm/u-boot.h
+++ b/arch/arc/include/asm/u-boot.h
@@ -8,7 +8,6 @@
 #define __ASM_ARC_U_BOOT_H__

 #include <asm-generic/u-boot.h>
-#include <asm/u-boot-arc.h>

 /* For image.h:image_check_target_arch() */
 #define IH_ARCH_DEFAULT IH_ARCH_ARC
--- a/arch/arc/lib/Makefile
+++ b/arch/arc/lib/Makefile
@@ -18,6 +18,7 @@ obj-y += memcmp.o
 obj-y += memcpy-700.o
 obj-y += memset.o
 obj-y += reset.o
+obj-y += timer.o
 obj-y += ints_low.o
 obj-y += init_helpers.o

--- a/arch/arc/lib/bootm.c
+++ b/arch/arc/lib/bootm.c
@@ -37,11 +37,6 @@ void arch_lmb_reserve(struct lmb *lmb)
 	lmb_reserve(lmb, sp, (CONFIG_SYS_SDRAM_BASE + gd->ram_size - sp));
 }

-int arch_fixup_fdt(void *blob)
-{
-	return 0;
-}
-
 static int cleanup_before_linux(void)
 {
 	disable_interrupts();
@@ -85,14 +80,14 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
 		r2 = (unsigned int)images->ft_addr;
 	} else {
 		r0 = 1;
-		r2 = (unsigned int)env_get("bootargs");
+		r2 = (unsigned int)getenv("bootargs");
 	}

-	if (!fake) {
-		smp_set_core_boot_addr((unsigned long)kernel_entry, -1);
-		smp_kick_all_cpus();
+	smp_set_core_boot_addr((unsigned long)kernel_entry, -1);
+	smp_kick_all_cpus();
+
+	if (!fake)
 		kernel_entry(r0, 0, r2);
-	}
 }

 int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
--- a/arch/arc/lib/cache.c
+++ b/arch/arc/lib/cache.c
@@ -8,7 +8,6 @@
 #include <common.h>
 #include <linux/compiler.h>
 #include <linux/kernel.h>
-#include <linux/log2.h>
 #include <asm/arcregs.h>
 #include <asm/cache.h>

@@ -32,15 +31,15 @@
 * relocation but will be used after being zeroed.
 */
 int l1_line_sz __section(".data");
-bool dcache_exists __section(".data") = false;
-bool icache_exists __section(".data") = false;
+int dcache_exists __section(".data");
+int icache_exists __section(".data");

 #define CACHE_LINE_MASK		(~(l1_line_sz - 1))

 #ifdef CONFIG_ISA_ARCV2
 int slc_line_sz __section(".data");
-bool slc_exists __section(".data") = false;
-bool ioc_exists __section(".data") = false;
+int slc_exists __section(".data");
+int ioc_exists __section(".data");

 static unsigned int __before_slc_op(const int op)
 {
@@ -60,16 +59,10 @@ static unsigned int __before_slc_op(const int op)

 static void __after_slc_op(const int op, unsigned int reg)
 {
-	if (op & OP_FLUSH) {	/* flush / flush-n-inv both wait */
-		/*
-		 * Make sure "busy" bit reports correct status,
-		 * see STAR 9001165532
-		 */
-		read_aux_reg(ARC_AUX_SLC_CTRL);
+	if (op & OP_FLUSH)	/* flush / flush-n-inv both wait */
 		while (read_aux_reg(ARC_AUX_SLC_CTRL) &
 		       DC_CTRL_FLUSH_STATUS)
 			;
-	}

 	/* Switch back to default Invalidate mode */
 	if (op == OP_INV)
@@ -152,7 +145,7 @@ static void read_decode_cache_bcr_arcv2(void)
 	sbcr.word = read_aux_reg(ARC_BCR_SLC);
 	if (sbcr.fields.ver) {
 		slc_cfg.word = read_aux_reg(ARC_AUX_SLC_CONFIG);
-		slc_exists = true;
+		slc_exists = 1;
 		slc_line_sz = (slc_cfg.fields.lsz == 0) ? 128 : 64;
 	}

@@ -169,7 +162,7 @@ static void read_decode_cache_bcr_arcv2(void)

 	cbcr.word = read_aux_reg(ARC_BCR_CLUSTER);
 	if (cbcr.fields.c)
-		ioc_exists = true;
+		ioc_exists = 1;
 }
 #endif

@@ -190,7 +183,7 @@ void read_decode_cache_bcr(void)

 	ibcr.word = read_aux_reg(ARC_BCR_IC_BUILD);
 	if (ibcr.fields.ver) {
-		icache_exists = true;
+		icache_exists = 1;
 		l1_line_sz = ic_line_sz = 8 << ibcr.fields.line_len;
 		if (!ic_line_sz)
 			panic("Instruction exists but line length is 0\n");
@@ -198,7 +191,7 @@ void read_decode_cache_bcr(void)

 	dbcr.word = read_aux_reg(ARC_BCR_DC_BUILD);
 	if (dbcr.fields.ver){
-		dcache_exists = true;
+		dcache_exists = 1;
 		l1_line_sz = dc_line_sz = 16 << dbcr.fields.line_len;
 		if (!dc_line_sz)
 			panic("Data cache exists but line length is 0\n");
@@ -216,33 +209,17 @@ void cache_init(void)
 	read_decode_cache_bcr_arcv2();

 	if (ioc_exists) {
-		/* IOC Aperture start is equal to DDR start */
-		unsigned int ap_base = CONFIG_SYS_SDRAM_BASE;
-		/* IOC Aperture size is equal to DDR size */
-		long ap_size = CONFIG_SYS_SDRAM_SIZE;
-
 		flush_dcache_all();
 		invalidate_dcache_all();

-		if (!is_power_of_2(ap_size) || ap_size < 4096)
-			panic("IOC Aperture size must be power of 2 and bigger 4Kib");
-
-		/*
-		 * IOC Aperture size decoded as 2 ^ (SIZE + 2) KB,
-		 * so setting 0x11 implies 512M, 0x12 implies 1G...
-		 */
-		write_aux_reg(ARC_AUX_IO_COH_AP0_SIZE,
-			      order_base_2(ap_size/1024) - 2);
-
-
-		/* IOC Aperture start must be aligned to the size of the aperture */
-		if (ap_base % ap_size != 0)
-			panic("IOC Aperture start must be aligned to the size of the aperture");
-
-		write_aux_reg(ARC_AUX_IO_COH_AP0_BASE, ap_base >> 12);
+		/* IO coherency base - 0x8z */
+		write_aux_reg(ARC_AUX_IO_COH_AP0_BASE, 0x80000);
+		/* IO coherency aperture size - 512Mb: 0x8z-0xAz */
+		write_aux_reg(ARC_AUX_IO_COH_AP0_SIZE, 0x11);
+		/* Enable partial writes */
 		write_aux_reg(ARC_AUX_IO_COH_PARTIAL, 1);
+		/* Enable IO coherency */
 		write_aux_reg(ARC_AUX_IO_COH_ENABLE, 1);
-
 	}
 #endif
 }
@@ -278,13 +255,6 @@ void invalidate_icache_all(void)
 	/* Any write to IC_IVIC register triggers invalidation of entire I$ */
 	if (icache_status()) {
 		write_aux_reg(ARC_AUX_IC_IVIC, 1);
-		/*
-		 * As per ARC HS databook (see chapter 5.3.3.2)
-		 * it is required to add 3 NOPs after each write to IC_IVIC.
-		 */
-		__builtin_arc_nop();
-		__builtin_arc_nop();
-		__builtin_arc_nop();
 		read_aux_reg(ARC_AUX_IC_CTRL);	/* blocks */
 	}
 }
--- a/arch/arc/lib/cpu.c
+++ b/arch/arc/lib/cpu.c
@@ -28,9 +28,3 @@ int arch_early_init_r(void)
 	gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
 	return 0;
 }
-
-/* This is a dummy function on arc */
-int dram_init(void)
-{
-	return 0;
-}
--- a/arch/arc/lib/start.S
+++ b/arch/arc/lib/start.S
@@ -10,26 +10,6 @@
 #include <asm/arcregs.h>

 ENTRY(_start)
-; ARCompact devices are not supposed to be SMP so master/slave check
-; makes no sense.
-#ifdef CONFIG_ISA_ARCV2
-	; Non-masters will be halted immediately, they might be kicked later
-	; by platform code right before passing control to the Linux kernel
-	; in bootm.c:boot_jump_linux().
-	lr 	r5, [identity]
-	lsr	r5, r5, 8
-	bmsk	r5, r5, 7
-	cmp	r5, 0
-	mov.nz	r0, r5
-	bz	.Lmaster_proceed
-	flag	1
-	nop
-	nop
-	nop
-
-.Lmaster_proceed:
-#endif
-
 	/* Setup interrupt vector base that matches "__text_start" */
 	sr	__ivt_start, [ARC_AUX_INTR_VEC_BASE]

--- a/arch/arc/lib/timer.c
+++ b/arch/arc/lib/timer.c
@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/arcregs.h>
+
+#define NH_MODE	(1 << 1)	/* Disable timer if CPU is halted */
+
+int timer_init(void)
+{
+	write_aux_reg(ARC_AUX_TIMER0_CTRL, NH_MODE);
+	/* Set max value for counter/timer */
+	write_aux_reg(ARC_AUX_TIMER0_LIMIT, 0xffffffff);
+	/* Set initial count value and restart counter/timer */
+	write_aux_reg(ARC_AUX_TIMER0_CNT, 0);
+	return 0;
+}
+
+unsigned long timer_read_counter(void)
+{
+	return read_aux_reg(ARC_AUX_TIMER0_CNT);
+}
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -50,7 +50,6 @@ PLATFORM_CPPFLAGS += $(arch-y) $(tune-y)

 # Machine directory name.  This list is sorted alphanumerically
 # by CONFIG_* macro name.
-machine-$(CONFIG_ARCH_ASPEED)		+= aspeed
 machine-$(CONFIG_ARCH_AT91)		+= at91
 machine-$(CONFIG_ARCH_BCM283X)		+= bcm283x
 machine-$(CONFIG_ARCH_DAVINCI)		+= davinci
@@ -64,7 +63,6 @@ machine-$(CONFIG_ARCH_MVEBU)		+= mvebu
 # TODO: rename CONFIG_TEGRA -> CONFIG_ARCH_TEGRA
 # TODO: rename CONFIG_ORION5X -> CONFIG_ARCH_ORION5X
 machine-$(CONFIG_ORION5X)		+= orion5x
-machine-$(CONFIG_ARCH_OMAP2PLUS)	+= omap2
 machine-$(CONFIG_ARCH_S5PC1XX)		+= s5pc1xx
 machine-$(CONFIG_ARCH_SUNXI)		+= sunxi
 machine-$(CONFIG_ARCH_SNAPDRAGON)	+= snapdragon
@@ -95,12 +93,12 @@ libs-y += arch/arm/cpu/
 libs-y += arch/arm/lib/

 ifeq ($(CONFIG_SPL_BUILD),y)
-ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35))
-libs-y += arch/arm/mach-imx/
+ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx31 mx35))
+libs-y += arch/arm/imx-common/
 endif
 else
-ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs vf610))
-libs-y += arch/arm/mach-imx/
+ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx31 mx35 mxs vf610))
+libs-y += arch/arm/imx-common/
 endif
 endif

--- a/arch/arm/config.mk
+++ b/arch/arm/config.mk
@@ -6,16 +6,13 @@
 #

 ifndef CONFIG_STANDALONE_LOAD_ADDR
-ifneq ($(CONFIG_ARCH_OMAP2PLUS),)
+ifneq ($(CONFIG_OMAP_COMMON),)
 CONFIG_STANDALONE_LOAD_ADDR = 0x80300000
 else
 CONFIG_STANDALONE_LOAD_ADDR = 0xc100000
 endif
 endif

-CFLAGS_NON_EFI := -fno-pic -ffixed-r9 -ffunction-sections -fdata-sections
-CFLAGS_EFI := -fpic -fshort-wchar
-
 LDFLAGS_FINAL += --gc-sections
 PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections \
 		     -fno-common -ffixed-r9
@@ -30,14 +27,8 @@ PLATFORM_RELFLAGS	+= $(LLVM_RELFLAGS)

 PLATFORM_CPPFLAGS += -D__ARM__

-ifdef CONFIG_ARM64
-PLATFORM_ELFFLAGS += -B aarch64 -O elf64-littleaarch64
-else
-PLATFORM_ELFFLAGS += -B arm -O elf32-littlearm
-endif
-
 # Choose between ARM/Thumb instruction sets
-ifeq ($(CONFIG_$(SPL_)SYS_THUMB_BUILD),y)
+ifeq ($(CONFIG_SYS_THUMB_BUILD),y)
 AFLAGS_IMPLICIT_IT	:= $(call as-option,-Wa$(comma)-mimplicit-it=always)
 PF_CPPFLAGS_ARM		:= $(AFLAGS_IMPLICIT_IT) \
 			$(call cc-option, -mthumb -mthumb-interwork,\
@@ -50,8 +41,9 @@ PF_CPPFLAGS_ARM := $(call cc-option,-marm,) \
 endif

 # Only test once
-ifeq ($(CONFIG_$(SPL_)SYS_THUMB_BUILD),y)
-archprepare: checkthumb checkgcc6
+ifneq ($(CONFIG_SPL_BUILD),y)
+ifeq ($(CONFIG_SYS_THUMB_BUILD),y)
+archprepare: checkthumb

 checkthumb:
 	@if test "$(call cc-name)" = "gcc" -a \
@@ -61,17 +53,8 @@ checkthumb:
 		echo '*** Your board is configured for THUMB mode.'; \
 		false; \
 	fi
-else
-archprepare: checkgcc6
 endif
-
-checkgcc6:
-	@if test "$(call cc-name)" = "gcc" -a \
-			"$(call cc-version)" -lt "0600"; then \
-		echo '*** Your GCC is older than 6.0 and is not supported'; \
-		false; \
-	fi
-
+endif

 # Try if EABI is supported, else fall back to old API,
 # i. e. for example:
@@ -113,7 +96,7 @@ LDFLAGS_u-boot += -pie
 #
 # http://sourceware.org/bugzilla/show_bug.cgi?id=12532
 #
-ifeq ($(CONFIG_$(SPL_)SYS_THUMB_BUILD),y)
+ifeq ($(CONFIG_SYS_THUMB_BUILD),y)
 ifeq ($(GAS_BUG_12532),)
 export GAS_BUG_12532:=$(shell if [ $(call binutils-version) -lt 0222 ] ; \
 	then echo y; else echo n; fi)
@@ -135,20 +118,15 @@ endif

 # limit ourselves to the sections we want in the .bin.
 ifdef CONFIG_ARM64
-OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .data \
-		-j .u_boot_list -j .rela.dyn -j .got -j .got.plt \
-		-j .binman_sym_table
+OBJCOPYFLAGS += -j .text -j .rodata -j .data -j .u_boot_list -j .rela.dyn
 else
 OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .hash \
-		-j .data -j .got -j .got.plt -j .u_boot_list -j .rel.dyn \
-		-j .binman_sym_table
+		-j .data -j .got -j .got.plt -j .u_boot_list -j .rel.dyn
 endif

-# if a dtb section exists we always have to include it
-# there are only two cases where it is generated
-# 1) OF_EMBEDED is turned on
-# 2) unit tests include device tree blobs
+ifdef CONFIG_OF_EMBED
 OBJCOPYFLAGS += -j .dtb.init.rodata
+endif

 ifdef CONFIG_EFI_LOADER
 OBJCOPYFLAGS += -j .efi_runtime -j .efi_runtime_rel
@@ -166,11 +144,4 @@ else
 ALL-y += u-boot.imx
 endif
 endif
-ifneq ($(CONFIG_VF610),)
-ALL-y += u-boot.vyb
 endif
-endif
-
-EFI_LDS := elf_arm_efi.lds
-EFI_CRT0 := crt0_arm_efi.o
-EFI_RELOC := reloc_arm_efi.o
--- a/arch/arm/cpu/arm1136/mx35/generic.c
+++ b/arch/arm/cpu/arm1136/mx35/generic.c
@@ -10,7 +10,7 @@
 #include <common.h>
 #include <div64.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/clock.h>
--- a/arch/arm/cpu/arm1136/mx35/mx35_sdram.c
+++ b/arch/arm/cpu/arm1136/mx35/mx35_sdram.c
@@ -5,7 +5,7 @@
 */

 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/imx-regs.h>
 #include <linux/types.h>
 #include <asm/arch/sys_proto.h>
--- a/arch/arm/cpu/arm1176/start.S
+++ b/arch/arm/cpu/arm1176/start.S
@@ -16,7 +16,6 @@

 #include <asm-offsets.h>
 #include <config.h>
-#include <linux/linkage.h>

 #ifndef CONFIG_SYS_PHY_UBOOT_BASE
 #define CONFIG_SYS_PHY_UBOOT_BASE	CONFIG_SYS_UBOOT_BASE
@@ -38,11 +37,6 @@
 	.globl reset

 reset:
-	/* Allow the board to save important registers */
-	b	save_boot_params
-.globl	save_boot_params_ret
-save_boot_params_ret:
-
 	/*
 	 * set the cpu to SVC32 mode
 	 */
@@ -116,7 +110,3 @@ mmu_disable_phys:
 c_runtime_cpu_setup:

 	mov	pc, lr
-
-WEAK(save_boot_params)
-	b	save_boot_params_ret	/* back to my caller */
-ENDPROC(save_boot_params)
--- a/arch/arm/cpu/arm720t/interrupts.c
+++ b/arch/arm/cpu/arm720t/interrupts.c
@@ -12,6 +12,12 @@

 #include <common.h>

+#ifdef CONFIG_USE_IRQ
+void do_irq (struct pt_regs *pt_regs)
+{
+}
+#endif
+
 #if defined(CONFIG_TEGRA)
 static ulong timestamp;
 static ulong lastdec;
--- a/arch/arm/cpu/arm720t/start.S
+++ b/arch/arm/cpu/arm720t/start.S
@@ -38,8 +38,7 @@ reset:
 	 * we do sys-critical inits only at reboot,
 	 * not when booting from ram!
 	 */
-#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
-		!defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
 	bl	cpu_init_crit
 #endif

@@ -63,8 +62,7 @@ c_runtime_cpu_setup:
 *************************************************************************
 */

-#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
-		!defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
 cpu_init_crit:

 	mov	ip, lr
--- a/arch/arm/cpu/arm920t/Makefile
+++ b/arch/arm/cpu/arm920t/Makefile
@@ -8,12 +8,14 @@
 extra-y	= start.o

 obj-y	+= cpu.o
+obj-$(CONFIG_USE_IRQ)	+= interrupts.o

 obj-$(CONFIG_EP93XX) += ep93xx/
 obj-$(CONFIG_IMX) += imx/
+obj-$(CONFIG_S3C24X0) += s3c24x0/

 # some files can only build in ARM mode

-ifdef CONFIG_$(SPL_)SYS_THUMB_BUILD
+ifdef CONFIG_SYS_THUMB_BUILD
 CFLAGS_cpu.o := -marm
 endif
--- a/arch/arm/cpu/arm920t/ep93xx/led.c
+++ b/arch/arm/cpu/arm920t/ep93xx/led.c
@@ -9,16 +9,16 @@
 #include <config.h>
 #include <status_led.h>

-static uint8_t saved_state[2] = {CONFIG_LED_STATUS_OFF, CONFIG_LED_STATUS_OFF};
-static uint32_t gpio_pin[2] = {1 << CONFIG_LED_STATUS_GREEN,
-			       1 << CONFIG_LED_STATUS_RED};
+static uint8_t saved_state[2] = {STATUS_LED_OFF, STATUS_LED_OFF};
+static uint32_t gpio_pin[2] = {1 << STATUS_LED_GREEN,
+			       1 << STATUS_LED_RED};

 static inline void switch_LED_on(uint8_t led)
 {
 	register struct gpio_regs *gpio = (struct gpio_regs *)GPIO_BASE;

 	writel(readl(&gpio->pedr) | gpio_pin[led], &gpio->pedr);
-	saved_state[led] = CONFIG_LED_STATUS_ON;
+	saved_state[led] = STATUS_LED_ON;
 }

 static inline void switch_LED_off(uint8_t led)
@@ -26,27 +26,27 @@ static inline void switch_LED_off(uint8_t led)
 	register struct gpio_regs *gpio = (struct gpio_regs *)GPIO_BASE;

 	writel(readl(&gpio->pedr) & ~gpio_pin[led], &gpio->pedr);
-	saved_state[led] = CONFIG_LED_STATUS_OFF;
+	saved_state[led] = STATUS_LED_OFF;
 }

 void red_led_on(void)
 {
-	switch_LED_on(CONFIG_LED_STATUS_RED);
+	switch_LED_on(STATUS_LED_RED);
 }

 void red_led_off(void)
 {
-	switch_LED_off(CONFIG_LED_STATUS_RED);
+	switch_LED_off(STATUS_LED_RED);
 }

 void green_led_on(void)
 {
-	switch_LED_on(CONFIG_LED_STATUS_GREEN);
+	switch_LED_on(STATUS_LED_GREEN);
 }

 void green_led_off(void)
 {
-	switch_LED_off(CONFIG_LED_STATUS_GREEN);
+	switch_LED_off(STATUS_LED_GREEN);
 }

 void __led_init(led_id_t mask, int state)
@@ -56,14 +56,13 @@ void __led_init(led_id_t mask, int state)

 void __led_toggle(led_id_t mask)
 {
-	if (CONFIG_LED_STATUS_RED == mask) {
-		if (CONFIG_LED_STATUS_ON == saved_state[CONFIG_LED_STATUS_RED])
+	if (STATUS_LED_RED == mask) {
+		if (STATUS_LED_ON == saved_state[STATUS_LED_RED])
 			red_led_off();
 		else
 			red_led_on();
-	} else if (CONFIG_LED_STATUS_GREEN == mask) {
-		if (CONFIG_LED_STATUS_ON ==
-		    saved_state[CONFIG_LED_STATUS_GREEN])
+	} else if (STATUS_LED_GREEN == mask) {
+		if (STATUS_LED_ON == saved_state[STATUS_LED_GREEN])
 			green_led_off();
 		else
 			green_led_on();
@@ -72,13 +71,13 @@ void __led_toggle(led_id_t mask)

 void __led_set(led_id_t mask, int state)
 {
-	if (CONFIG_LED_STATUS_RED == mask) {
-		if (CONFIG_LED_STATUS_ON == state)
+	if (STATUS_LED_RED == mask) {
+		if (STATUS_LED_ON == state)
 			red_led_on();
 		else
 			red_led_off();
-	} else if (CONFIG_LED_STATUS_GREEN == mask) {
-		if (CONFIG_LED_STATUS_ON == state)
+	} else if (STATUS_LED_GREEN == mask) {
+		if (STATUS_LED_ON == state)
 			green_led_on();
 		else
 			green_led_off();
--- a/arch/arm/cpu/arm920t/ep93xx/speed.c
+++ b/arch/arm/cpu/arm920t/ep93xx/speed.c
@@ -39,7 +39,7 @@ static ulong get_PLLCLK(uint32_t *pllreg)
 }

 /* return FCLK frequency */
-ulong get_FCLK(void)
+ulong get_FCLK()
 {
 	const uint8_t fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 };
 	struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
--- a/arch/arm/cpu/arm920t/imx/timer.c
+++ b/arch/arm/cpu/arm920t/imx/timer.c
@@ -78,7 +78,11 @@ unsigned long long get_ticks(void)
 */
 ulong get_tbclk (void)
 {
-	return CONFIG_SYS_HZ;
+	ulong tbclk;
+
+	tbclk = CONFIG_SYS_HZ;
+
+	return tbclk;
 }

 /*
--- a/arch/arm/cpu/arm920t/interrupts.c
+++ b/arch/arm/cpu/arm920t/interrupts.c
@@ -0,0 +1,27 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/proc-armv/ptrace.h>
+
+#if defined (CONFIG_ARCH_INTEGRATOR)
+void do_irq (struct pt_regs *pt_regs)
+{
+	/* ASSUMED to be a timer interrupt  */
+	/* Just clear it - count handled in */
+	/* integratorap.c                   */
+	*(volatile ulong *)(CONFIG_SYS_TIMERBASE + 0x0C) = 0;
+}
+#endif
--- a/arch/arm/cpu/arm920t/s3c24x0/Makefile
+++ b/arch/arm/cpu/arm920t/s3c24x0/Makefile
@@ -0,0 +1,11 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-$(CONFIG_USE_IRQ) += interrupts.o
+obj-$(CONFIG_DISPLAY_CPUINFO)	+= cpu_info.o
+obj-y	+= speed.o
+obj-y	+= timer.o
--- a/arch/arm/cpu/arm920t/s3c24x0/cpu_info.c
+++ b/arch/arm/cpu/arm920t/s3c24x0/cpu_info.c
@@ -0,0 +1,38 @@
+/*
+ * (C) Copyright 2010
+ * David Mueller <d.mueller@elsoft.ch>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/s3c24x0_cpu.h>
+
+typedef ulong (*getfreq)(void);
+
+static const getfreq freq_f[] = {
+	get_FCLK,
+	get_HCLK,
+	get_PCLK,
+};
+
+static const char freq_c[] = { 'F', 'H', 'P' };
+
+int print_cpuinfo(void)
+{
+	int i;
+	char buf[32];
+/* the S3C2400 seems to be lacking a CHIP ID register */
+#ifndef CONFIG_S3C2400
+	ulong cpuid;
+	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
+
+	cpuid = readl(&gpio->gstatus1);
+	printf("CPUID: %8lX\n", cpuid);
+#endif
+	for (i = 0; i < ARRAY_SIZE(freq_f); i++)
+		printf("%cCLK: %8s MHz\n", freq_c[i], strmhz(buf, freq_f[i]()));
+
+	return 0;
+}
--- a/arch/arm/cpu/arm920t/s3c24x0/interrupts.c
+++ b/arch/arm/cpu/arm920t/s3c24x0/interrupts.c
@@ -0,0 +1,26 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+
+#include <asm/arch/s3c24x0_cpu.h>
+#include <asm/proc-armv/ptrace.h>
+
+void do_irq (struct pt_regs *pt_regs)
+{
+	struct s3c24x0_interrupt *irq = s3c24x0_get_base_interrupt();
+	u_int32_t intpnd = readl(&irq->INTPND);
+
+}
--- a/arch/arm/cpu/arm920t/s3c24x0/speed.c
+++ b/arch/arm/cpu/arm920t/s3c24x0/speed.c
@@ -0,0 +1,102 @@
+/*
+ * (C) Copyright 2001-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* This code should work for both the S3C2400 and the S3C2410
+ * as they seem to have the same PLL and clock machinery inside.
+ * The different address mapping is handled by the s3c24xx.h files below.
+ */
+
+#include <common.h>
+#ifdef CONFIG_S3C24X0
+
+#include <asm/io.h>
+#include <asm/arch/s3c24x0_cpu.h>
+
+#define MPLL 0
+#define UPLL 1
+
+/* ------------------------------------------------------------------------- */
+/* NOTE: This describes the proper use of this file.
+ *
+ * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
+ *
+ * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
+ * the specified bus in HZ.
+ */
+/* ------------------------------------------------------------------------- */
+
+static ulong get_PLLCLK(int pllreg)
+{
+	struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
+	ulong r, m, p, s;
+
+	if (pllreg == MPLL)
+		r = readl(&clk_power->mpllcon);
+	else if (pllreg == UPLL)
+		r = readl(&clk_power->upllcon);
+	else
+		hang();
+
+	m = ((r & 0xFF000) >> 12) + 8;
+	p = ((r & 0x003F0) >> 4) + 2;
+	s = r & 0x3;
+
+#if defined(CONFIG_S3C2440)
+	if (pllreg == MPLL)
+		return 2 * m * (CONFIG_SYS_CLK_FREQ / (p << s));
+#endif
+	return (CONFIG_SYS_CLK_FREQ * m) / (p << s);
+
+}
+
+/* return FCLK frequency */
+ulong get_FCLK(void)
+{
+	return get_PLLCLK(MPLL);
+}
+
+/* return HCLK frequency */
+ulong get_HCLK(void)
+{
+	struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
+#ifdef CONFIG_S3C2440
+	switch (readl(&clk_power->clkdivn) & 0x6) {
+	default:
+	case 0:
+		return get_FCLK();
+	case 2:
+		return get_FCLK() / 2;
+	case 4:
+		return (readl(&clk_power->camdivn) & (1 << 9)) ?
+			get_FCLK() / 8 : get_FCLK() / 4;
+	case 6:
+		return (readl(&clk_power->camdivn) & (1 << 8)) ?
+			get_FCLK() / 6 : get_FCLK() / 3;
+	}
+#else
+	return (readl(&clk_power->clkdivn) & 2) ? get_FCLK() / 2 : get_FCLK();
+#endif
+}
+
+/* return PCLK frequency */
+ulong get_PCLK(void)
+{
+	struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
+
+	return (readl(&clk_power->clkdivn) & 1) ? get_HCLK() / 2 : get_HCLK();
+}
+
+/* return UCLK frequency */
+ulong get_UCLK(void)
+{
+	return get_PLLCLK(UPLL);
+}
+
+#endif /* CONFIG_S3C24X0 */
--- a/arch/arm/cpu/arm920t/s3c24x0/timer.c
+++ b/arch/arm/cpu/arm920t/s3c24x0/timer.c
@@ -0,0 +1,160 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#ifdef CONFIG_S3C24X0
+
+#include <asm/io.h>
+#include <asm/arch/s3c24x0_cpu.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int timer_init(void)
+{
+	struct s3c24x0_timers *timers = s3c24x0_get_base_timers();
+	ulong tmr;
+
+	/* use PWM Timer 4 because it has no output */
+	/* prescaler for Timer 4 is 16 */
+	writel(0x0f00, &timers->tcfg0);
+	if (gd->arch.tbu == 0) {
+		/*
+		 * for 10 ms clock period @ PCLK with 4 bit divider = 1/2
+		 * (default) and prescaler = 16. Should be 10390
+		 * @33.25MHz and 15625 @ 50 MHz
+		 */
+		gd->arch.tbu = get_PCLK() / (2 * 16 * 100);
+		gd->arch.timer_rate_hz = get_PCLK() / (2 * 16);
+	}
+	/* load value for 10 ms timeout */
+	writel(gd->arch.tbu, &timers->tcntb4);
+	/* auto load, manual update of timer 4 */
+	tmr = (readl(&timers->tcon) & ~0x0700000) | 0x0600000;
+	writel(tmr, &timers->tcon);
+	/* auto load, start timer 4 */
+	tmr = (tmr & ~0x0700000) | 0x0500000;
+	writel(tmr, &timers->tcon);
+	gd->arch.lastinc = 0;
+	gd->arch.tbl = 0;
+
+	return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+ulong get_timer(ulong base)
+{
+	return get_timer_masked() - base;
+}
+
+void __udelay (unsigned long usec)
+{
+	ulong tmo;
+	ulong start = get_ticks();
+
+	tmo = usec / 1000;
+	tmo *= (gd->arch.tbu * 100);
+	tmo /= 1000;
+
+	while ((ulong) (get_ticks() - start) < tmo)
+		/*NOP*/;
+}
+
+ulong get_timer_masked(void)
+{
+	ulong tmr = get_ticks();
+
+	return tmr / (gd->arch.timer_rate_hz / CONFIG_SYS_HZ);
+}
+
+void udelay_masked(unsigned long usec)
+{
+	ulong tmo;
+	ulong endtime;
+	signed long diff;
+
+	if (usec >= 1000) {
+		tmo = usec / 1000;
+		tmo *= (gd->arch.tbu * 100);
+		tmo /= 1000;
+	} else {
+		tmo = usec * (gd->arch.tbu * 100);
+		tmo /= (1000 * 1000);
+	}
+
+	endtime = get_ticks() + tmo;
+
+	do {
+		ulong now = get_ticks();
+		diff = endtime - now;
+	} while (diff >= 0);
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	struct s3c24x0_timers *timers = s3c24x0_get_base_timers();
+	ulong now = readl(&timers->tcnto4) & 0xffff;
+
+	if (gd->arch.lastinc >= now) {
+		/* normal mode */
+		gd->arch.tbl += gd->arch.lastinc - now;
+	} else {
+		/* we have an overflow ... */
+		gd->arch.tbl += gd->arch.lastinc + gd->arch.tbu - now;
+	}
+	gd->arch.lastinc = now;
+
+	return gd->arch.tbl;
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	return CONFIG_SYS_HZ;
+}
+
+/*
+ * reset the cpu by setting up the watchdog timer and let him time out
+ */
+void reset_cpu(ulong ignored)
+{
+	struct s3c24x0_watchdog *watchdog;
+
+	watchdog = s3c24x0_get_base_watchdog();
+
+	/* Disable watchdog */
+	writel(0x0000, &watchdog->wtcon);
+
+	/* Initialize watchdog timer count register */
+	writel(0x0001, &watchdog->wtcnt);
+
+	/* Enable watchdog timer; assert reset at timer timeout */
+	writel(0x0021, &watchdog->wtcon);
+
+	while (1)
+		/* loop forever and wait for reset to happen */;
+
+	/*NOTREACHED*/
+}
+
+#endif /* CONFIG_S3C24X0 */
--- a/arch/arm/cpu/arm920t/start.S
+++ b/arch/arm/cpu/arm920t/start.S
@@ -50,6 +50,43 @@ copyex:
 	bne	copyex
 #endif

+#ifdef CONFIG_S3C24X0
+	/* turn off the watchdog */
+
+# if defined(CONFIG_S3C2400)
+#  define pWTCON	0x15300000
+#  define INTMSK	0x14400008	/* Interrupt-Controller base addresses */
+#  define CLKDIVN	0x14800014	/* clock divisor register */
+#else
+#  define pWTCON	0x53000000
+#  define INTMSK	0x4A000008	/* Interrupt-Controller base addresses */
+#  define INTSUBMSK	0x4A00001C
+#  define CLKDIVN	0x4C000014	/* clock divisor register */
+# endif
+
+	ldr	r0, =pWTCON
+	mov	r1, #0x0
+	str	r1, [r0]
+
+	/*
+	 * mask all IRQs by setting all bits in the INTMR - default
+	 */
+	mov	r1, #0xffffffff
+	ldr	r0, =INTMSK
+	str	r1, [r0]
+# if defined(CONFIG_S3C2410)
+	ldr	r1, =0x3ff
+	ldr	r0, =INTSUBMSK
+	str	r1, [r0]
+# endif
+
+	/* FCLK:HCLK:PCLK = 1:2:4 */
+	/* default FCLK is 120 MHz ! */
+	ldr	r0, =CLKDIVN
+	mov	r1, #3
+	str	r1, [r0]
+#endif	/* CONFIG_S3C24X0 */
+
 	/*
 	 * we do sys-critical inits only at reboot,
 	 * not when booting from ram!
--- a/arch/arm/cpu/arm926ejs/Makefile
+++ b/arch/arm/cpu/arm926ejs/Makefile
@@ -23,7 +23,7 @@ obj-$(if $(filter spear,$(SOC)),y) += spear/

 # some files can only build in ARM or THUMB2, not THUMB1

-ifdef CONFIG_$(SPL_)SYS_THUMB_BUILD
+ifdef CONFIG_SYS_THUMB_BUILD
 ifndef CONFIG_HAS_THUMB2

 CFLAGS_cpu.o := -marm
--- a/arch/arm/cpu/arm926ejs/armada100/dram.c
+++ b/arch/arm/cpu/arm926ejs/armada100/dram.c
@@ -108,9 +108,7 @@ int dram_init(void)
 * If this function is not defined here,
 * board.c alters dram bank zero configuration defined above.
 */
-int dram_init_banksize(void)
+void dram_init_banksize(void)
 {
 	dram_init();
-
-	return 0;
 }
--- a/arch/arm/cpu/arm926ejs/cache.c
+++ b/arch/arm/cpu/arm926ejs/cache.c
@@ -63,6 +63,6 @@ void flush_dcache_all(void)

 __weak void l2_cache_disable(void) {}

-#if CONFIG_IS_ENABLED(SYS_THUMB_BUILD)
+#if defined CONFIG_SYS_THUMB_BUILD
 __weak void invalidate_l2_cache(void) {}
 #endif
--- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
@@ -45,14 +45,10 @@ void lpc32xx_uart_init(unsigned int uart_id)

 #if !CONFIG_IS_ENABLED(OF_CONTROL)
 static const struct ns16550_platdata lpc32xx_uart[] = {
-	{ .base = UART3_BASE, .reg_shift = 2,
-	  .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
-	{ .base = UART4_BASE, .reg_shift = 2,
-	  .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
-	{ .base = UART5_BASE, .reg_shift = 2,
-	  .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
-	{ .base = UART6_BASE, .reg_shift = 2,
-	  .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
+	{ .base = UART3_BASE, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
+	{ .base = UART4_BASE, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
+	{ .base = UART5_BASE, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
+	{ .base = UART6_BASE, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
 };

 #if defined(CONFIG_LPC32XX_HSUART)
--- a/arch/arm/cpu/arm926ejs/mx25/generic.c
+++ b/arch/arm/cpu/arm926ejs/mx25/generic.c
@@ -58,14 +58,6 @@ static ulong imx_get_mpllclk(void)
 	return imx_decode_pll(readl(&ccm->mpctl), fref);
 }

-static ulong imx_get_upllclk(void)
-{
-	struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
-	ulong fref = MXC_HCLK;
-
-	return imx_decode_pll(readl(&ccm->upctl), fref);
-}
-
 static ulong imx_get_armclk(void)
 {
 	struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
@@ -103,8 +95,7 @@ static ulong imx_get_ipgclk(void)
 static ulong imx_get_perclk(int clk)
 {
 	struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
-	ulong fref = readl(&ccm->mcr) & (1 << clk) ? imx_get_upllclk() :
-						     imx_get_ahbclk();
+	ulong fref = imx_get_ahbclk();
 	ulong div;

 	div = readl(&ccm->pcdr[CCM_PERCLK_REG(clk)]);
@@ -113,25 +104,6 @@ static ulong imx_get_perclk(int clk)
 	return fref / div;
 }

-int imx_set_perclk(enum mxc_clock clk, bool from_upll, unsigned int freq)
-{
-	struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
-	ulong fref = from_upll ? imx_get_upllclk() : imx_get_ahbclk();
-	ulong div = (fref + freq - 1) / freq;
-
-	if (clk > MXC_UART_CLK || !div || --div > CCM_PERCLK_MASK)
-		return -EINVAL;
-
-	clrsetbits_le32(&ccm->pcdr[CCM_PERCLK_REG(clk)],
-			CCM_PERCLK_MASK << CCM_PERCLK_SHIFT(clk),
-			div << CCM_PERCLK_SHIFT(clk));
-	if (from_upll)
-		setbits_le32(&ccm->mcr, 1 << clk);
-	else
-		clrbits_le32(&ccm->mcr, 1 << clk);
-	return 0;
-}
-
 unsigned int mxc_get_clock(enum mxc_clock clk)
 {
 	if (clk >= MXC_CLK_NUM)
--- a/arch/arm/cpu/arm926ejs/mx27/generic.c
+++ b/arch/arm/cpu/arm926ejs/mx27/generic.c
@@ -12,8 +12,8 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/gpio.h>
-#include <asm/mach-imx/sys_proto.h>
-#ifdef CONFIG_MMC_MXC
+#include <asm/imx-common/sys_proto.h>
+#ifdef CONFIG_MXC_MMC
 #include <asm/arch/mxcmmc.h>
 #endif

@@ -196,7 +196,7 @@ int cpu_eth_init(bd_t *bis)
 */
 int cpu_mmc_init(bd_t *bis)
 {
-#ifdef CONFIG_MMC_MXC
+#ifdef CONFIG_MXC_MMC
 	return mxc_mmc_init(bis);
 #else
 	return 0;
@@ -340,7 +340,7 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 }
 #endif /* CONFIG_FEC_MXC */

-#ifdef CONFIG_MMC_MXC
+#ifdef CONFIG_MXC_MMC
 void mx27_sd1_init_pins(void)
 {
 	int i;
@@ -374,7 +374,7 @@ void mx27_sd2_init_pins(void)
 		imx_gpio_mode(mode[i]);

 }
-#endif /* CONFIG_MMC_MXC */
+#endif /* CONFIG_MXC_MMC */

 #ifndef CONFIG_SYS_DCACHE_OFF
 void enable_caches(void)
--- a/arch/arm/cpu/arm926ejs/mxs/clock.c
+++ b/arch/arm/cpu/arm926ejs/mxs/clock.c
@@ -11,7 +11,7 @@
 */

 #include <common.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/imx-regs.h>
--- a/arch/arm/cpu/arm926ejs/mxs/iomux.c
+++ b/arch/arm/cpu/arm926ejs/mxs/iomux.c
@@ -8,7 +8,7 @@
 */

 #include <common.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/iomux.h>
--- a/arch/arm/cpu/arm926ejs/mxs/mxs.c
+++ b/arch/arm/cpu/arm926ejs/mxs/mxs.c
@@ -11,10 +11,10 @@
 */

 #include <common.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
-#include <asm/mach-imx/dma.h>
+#include <asm/imx-common/dma.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/iomux.h>
 #include <asm/arch/imx-regs.h>
--- a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
@@ -40,17 +40,17 @@ void early_delay(int delay)
 		;
 }

-#if defined(CONFIG_MX23)
 #define	MUX_CONFIG_BOOTMODE_PAD	(MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
 static const iomux_cfg_t iomux_boot[] = {
+#if defined(CONFIG_MX23)
 	MX23_PAD_LCD_D00__GPIO_1_0 | MUX_CONFIG_BOOTMODE_PAD,
 	MX23_PAD_LCD_D01__GPIO_1_1 | MUX_CONFIG_BOOTMODE_PAD,
 	MX23_PAD_LCD_D02__GPIO_1_2 | MUX_CONFIG_BOOTMODE_PAD,
 	MX23_PAD_LCD_D03__GPIO_1_3 | MUX_CONFIG_BOOTMODE_PAD,
 	MX23_PAD_LCD_D04__GPIO_1_4 | MUX_CONFIG_BOOTMODE_PAD,
 	MX23_PAD_LCD_D05__GPIO_1_5 | MUX_CONFIG_BOOTMODE_PAD,
-};
 #endif
+};

 static uint8_t mxs_get_bootmode_index(void)
 {
--- a/arch/arm/cpu/arm926ejs/omap/Makefile
+++ b/arch/arm/cpu/arm926ejs/omap/Makefile
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	= timer.o
+obj-$(CONFIG_DISPLAY_CPUINFO) += cpuinfo.o
+obj-y	+= reset.o
--- a/arch/arm/cpu/arm926ejs/omap/cpuinfo.c
+++ b/arch/arm/cpu/arm926ejs/omap/cpuinfo.c
@@ -0,0 +1,242 @@
+/*
+ * OMAP1 CPU identification code
+ *
+ * Copyright (C) 2004 Nokia Corporation
+ * Written by Tony Lindgren <tony@atomide.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <linux/compiler.h>
+
+#if defined(CONFIG_OMAP)
+
+#define omap_readw(x)		*(volatile unsigned short *)(x)
+#define omap_readl(x)		*(volatile unsigned long *)(x)
+
+#define OMAP_DIE_ID_0		0xfffe1800
+#define OMAP_DIE_ID_1		0xfffe1804
+#define OMAP_PRODUCTION_ID_0	0xfffe2000
+#define OMAP_PRODUCTION_ID_1	0xfffe2004
+#define OMAP32_ID_0		0xfffed400
+#define OMAP32_ID_1		0xfffed404
+
+struct omap_id {
+	u16	jtag_id;	/* Used to determine OMAP type */
+	u8	die_rev;	/* Processor revision */
+	u32	omap_id;	/* OMAP revision */
+	u32	type;		/* Cpu id bits [31:08], cpu class bits [07:00] */
+};
+
+/* Register values to detect the OMAP version */
+static struct omap_id omap_ids[] = {
+	{ .jtag_id = 0xb574, .die_rev = 0x2, .omap_id = 0x03310315, .type = 0x03100000},
+	{ .jtag_id = 0x355f, .die_rev = 0x0, .omap_id = 0x03320000, .type = 0x07300100},
+	{ .jtag_id = 0xb55f, .die_rev = 0x0, .omap_id = 0x03320000, .type = 0x07300300},
+	{ .jtag_id = 0xb470, .die_rev = 0x0, .omap_id = 0x03310100, .type = 0x15100000},
+	{ .jtag_id = 0xb576, .die_rev = 0x0, .omap_id = 0x03320000, .type = 0x16100000},
+	{ .jtag_id = 0xb576, .die_rev = 0x2, .omap_id = 0x03320100, .type = 0x16110000},
+	{ .jtag_id = 0xb576, .die_rev = 0x3, .omap_id = 0x03320100, .type = 0x16100c00},
+	{ .jtag_id = 0xb576, .die_rev = 0x0, .omap_id = 0x03320200, .type = 0x16100d00},
+	{ .jtag_id = 0xb613, .die_rev = 0x0, .omap_id = 0x03320300, .type = 0x1610ef00},
+	{ .jtag_id = 0xb613, .die_rev = 0x0, .omap_id = 0x03320300, .type = 0x1610ef00},
+	{ .jtag_id = 0xb576, .die_rev = 0x1, .omap_id = 0x03320100, .type = 0x16110000},
+	{ .jtag_id = 0xb58c, .die_rev = 0x2, .omap_id = 0x03320200, .type = 0x16110b00},
+	{ .jtag_id = 0xb58c, .die_rev = 0x3, .omap_id = 0x03320200, .type = 0x16110c00},
+	{ .jtag_id = 0xb65f, .die_rev = 0x0, .omap_id = 0x03320400, .type = 0x16212300},
+	{ .jtag_id = 0xb65f, .die_rev = 0x1, .omap_id = 0x03320400, .type = 0x16212300},
+	{ .jtag_id = 0xb65f, .die_rev = 0x1, .omap_id = 0x03320500, .type = 0x16212300},
+	{ .jtag_id = 0xb5f7, .die_rev = 0x0, .omap_id = 0x03330000, .type = 0x17100000},
+	{ .jtag_id = 0xb5f7, .die_rev = 0x1, .omap_id = 0x03330100, .type = 0x17100000},
+	{ .jtag_id = 0xb5f7, .die_rev = 0x2, .omap_id = 0x03330100, .type = 0x17100000},
+};
+
+/*
+ * Get OMAP type from PROD_ID.
+ * 1710 has the PROD_ID in bits 15:00, not in 16:01 as documented in TRM.
+ * 1510 PROD_ID is empty, and 1610 PROD_ID does not make sense.
+ * Undocumented register in TEST BLOCK is used as fallback; This seems to
+ * work on 1510, 1610 & 1710. The official way hopefully will work in future
+ * processors.
+ */
+static u16 omap_get_jtag_id(void)
+{
+	u32 prod_id, omap_id;
+
+	prod_id = omap_readl(OMAP_PRODUCTION_ID_1);
+	omap_id = omap_readl(OMAP32_ID_1);
+
+	/* Check for unusable OMAP_PRODUCTION_ID_1 on 1611B/5912 and 730 */
+	if (((prod_id >> 20) == 0) || (prod_id == omap_id))
+		prod_id = 0;
+	else
+		prod_id &= 0xffff;
+
+	if (prod_id)
+		return prod_id;
+
+	/* Use OMAP32_ID_1 as fallback */
+	prod_id = ((omap_id >> 12) & 0xffff);
+
+	return prod_id;
+}
+
+/*
+ * Get OMAP revision from DIE_REV.
+ * Early 1710 processors may have broken OMAP_DIE_ID, it contains PROD_ID.
+ * Undocumented register in the TEST BLOCK is used as fallback.
+ * REVISIT: This does not seem to work on 1510
+ */
+static u8 omap_get_die_rev(void)
+{
+	u32 die_rev;
+
+	die_rev = omap_readl(OMAP_DIE_ID_1);
+
+	/* Check for broken OMAP_DIE_ID on early 1710 */
+	if (((die_rev >> 12) & 0xffff) == omap_get_jtag_id())
+		die_rev = 0;
+
+	die_rev = (die_rev >> 17) & 0xf;
+	if (die_rev)
+		return die_rev;
+
+	die_rev = (omap_readl(OMAP32_ID_1) >> 28) & 0xf;
+
+	return die_rev;
+}
+
+static unsigned long dpll1(void)
+{
+	unsigned short pll_ctl_val = omap_readw(DPLL_CTL_REG);
+	unsigned long rate;
+
+	rate = CONFIG_SYS_CLK_FREQ; /* Base xtal rate */
+	if (pll_ctl_val & 0x10) {
+		/* PLL enabled, apply multiplier and divisor */
+		if (pll_ctl_val & 0xf80)
+			rate *= (pll_ctl_val & 0xf80) >> 7;
+		rate /= ((pll_ctl_val & 0x60) >> 5) + 1;
+	} else {
+		/* PLL disabled, apply bypass divisor */
+		switch (pll_ctl_val & 0xc) {
+		case 0:
+			break;
+		case 0x4:
+			rate /= 2;
+			break;
+		default:
+			rate /= 4;
+			break;
+		}
+	}
+
+	return rate;
+}
+
+static unsigned long armcore(void)
+{
+	unsigned short arm_ckctl = omap_readw(ARM_CKCTL);
+
+	return (dpll1() >> ((arm_ckctl & 0x0030) >> 4));
+}
+
+int print_cpuinfo (void)
+{
+	int i;
+	u16 jtag_id;
+	u8 die_rev;
+	u32 omap_id;
+	u8 cpu_type;
+	__maybe_unused u32 system_serial_high;
+	__maybe_unused u32 system_serial_low;
+	u32 system_rev = 0;
+
+	jtag_id = omap_get_jtag_id();
+	die_rev = omap_get_die_rev();
+	omap_id = omap_readl(OMAP32_ID_0);
+
+#ifdef DEBUG
+	printf("OMAP_DIE_ID_0: 0x%08x\n", omap_readl(OMAP_DIE_ID_0));
+	printf("OMAP_DIE_ID_1: 0x%08x DIE_REV: %i\n",
+	       omap_readl(OMAP_DIE_ID_1),
+	       (omap_readl(OMAP_DIE_ID_1) >> 17) & 0xf);
+	printf("OMAP_PRODUCTION_ID_0: 0x%08x\n", omap_readl(OMAP_PRODUCTION_ID_0));
+	printf("OMAP_PRODUCTION_ID_1: 0x%08x JTAG_ID: 0x%04x\n",
+	       omap_readl(OMAP_PRODUCTION_ID_1),
+	       omap_readl(OMAP_PRODUCTION_ID_1) & 0xffff);
+	printf("OMAP32_ID_0: 0x%08x\n", omap_readl(OMAP32_ID_0));
+	printf("OMAP32_ID_1: 0x%08x\n", omap_readl(OMAP32_ID_1));
+	printf("JTAG_ID: 0x%04x DIE_REV: %i\n", jtag_id, die_rev);
+#endif
+
+	system_serial_high = omap_readl(OMAP_DIE_ID_0);
+	system_serial_low = omap_readl(OMAP_DIE_ID_1);
+
+	/* First check only the major version in a safe way */
+	for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
+		if (jtag_id == (omap_ids[i].jtag_id)) {
+			system_rev = omap_ids[i].type;
+			break;
+		}
+	}
+
+	/* Check if we can find the die revision */
+	for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
+		if (jtag_id == omap_ids[i].jtag_id && die_rev == omap_ids[i].die_rev) {
+			system_rev = omap_ids[i].type;
+			break;
+		}
+	}
+
+	/* Finally check also the omap_id */
+	for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
+		if (jtag_id == omap_ids[i].jtag_id
+		    && die_rev == omap_ids[i].die_rev
+		    && omap_id == omap_ids[i].omap_id) {
+			system_rev = omap_ids[i].type;
+			break;
+		}
+	}
+
+	/* Add the cpu class info (7xx, 15xx, 16xx, 24xx) */
+	cpu_type = system_rev >> 24;
+
+	switch (cpu_type) {
+	case 0x07:
+		system_rev |= 0x07;
+		break;
+	case 0x03:
+	case 0x15:
+		system_rev |= 0x15;
+		break;
+	case 0x16:
+	case 0x17:
+		system_rev |= 0x16;
+		break;
+	case 0x24:
+		system_rev |= 0x24;
+		break;
+	default:
+		printf("Unknown OMAP cpu type: 0x%02x\n", cpu_type);
+	}
+
+	printf("CPU:   OMAP%04x", system_rev >> 16);
+	if ((system_rev >> 8) & 0xff)
+		printf("%x", (system_rev >> 8) & 0xff);
+#ifdef DEBUG
+	printf(" revision %i handled as %02xxx id: %08x%08x",
+	       die_rev, system_rev & 0xff, system_serial_low, system_serial_high);
+#endif
+	printf(" at %ld.%01ld MHz (DPLL1=%ld.%01ld MHz)\n",
+	       armcore() / 1000000, (armcore() / 100000) % 10,
+	       dpll1() / 1000000, (dpll1() / 100000) % 10);
+
+	return 0;
+}
+
+#endif /* #if defined(CONFIG_OMAP) */
--- a/arch/arm/cpu/arm926ejs/omap/reset.S
+++ b/arch/arm/cpu/arm926ejs/omap/reset.S
@@ -0,0 +1,29 @@
+/*
+ *  armboot - Startup Code for ARM926EJS CPU-core
+ *
+ *  Copyright (c) 2003  Texas Instruments
+ *
+ *  ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
+ *
+ *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
+ *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
+ *  Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
+ *  Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
+ *  Copyright (c) 2003	Kshitij <kshitij@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+	.align	5
+.globl reset_cpu
+reset_cpu:
+	ldr	r1, rstctl1	/* get clkm1 reset ctl */
+	mov	r3, #0x0
+	strh	r3, [r1]	/* clear it */
+	mov	r3, #0x8
+	strh	r3, [r1]	/* force dsp+arm reset */
+_loop_forever:
+	b	_loop_forever
+
+rstctl1:
+	.word	0xfffece10
--- a/arch/arm/cpu/arm926ejs/omap/timer.c
+++ b/arch/arm/cpu/arm926ejs/omap/timer.c
@@ -0,0 +1,152 @@
+/*
+ * (C) Copyright 2003
+ * Texas Instruments <www.ti.com>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002-2004
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * (C) Copyright 2004
+ * Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+#define TIMER_CLOCK	(CONFIG_SYS_CLK_FREQ / (2 << CONFIG_SYS_PTV))
+#define TIMER_LOAD_VAL	0xffffffff
+
+/* macro to read the 32 bit timer */
+#define READ_TIMER	readl(CONFIG_SYS_TIMERBASE+8) \
+			/ (TIMER_CLOCK / CONFIG_SYS_HZ)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define timestamp gd->arch.tbl
+#define lastdec gd->arch.lastinc
+
+int timer_init (void)
+{
+	int32_t val;
+
+	/* Start the decrementer ticking down from 0xffffffff */
+	*((int32_t *) (CONFIG_SYS_TIMERBASE + LOAD_TIM)) = TIMER_LOAD_VAL;
+	val = MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE | (CONFIG_SYS_PTV << MPUTIM_PTV_BIT);
+	*((int32_t *) (CONFIG_SYS_TIMERBASE + CNTL_TIMER)) = val;
+
+	/* init the timestamp and lastdec value */
+	reset_timer_masked();
+
+	return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+ulong get_timer (ulong base)
+{
+	return get_timer_masked () - base;
+}
+
+/* delay x useconds AND preserve advance timestamp value */
+void __udelay (unsigned long usec)
+{
+	ulong tmo, tmp;
+
+	if(usec >= 1000){		/* if "big" number, spread normalization to seconds */
+		tmo = usec / 1000;	/* start to normalize for usec to ticks per sec */
+		tmo *= CONFIG_SYS_HZ;	/* find number of "ticks" to wait to achieve target */
+		tmo /= 1000;		/* finish normalize. */
+	}else{				/* else small number, don't kill it prior to HZ multiply */
+		tmo = usec * CONFIG_SYS_HZ;
+		tmo /= (1000*1000);
+	}
+
+	tmp = get_timer (0);		/* get current timestamp */
+	if( (tmo + tmp + 1) < tmp )	/* if setting this fordward will roll time stamp */
+		reset_timer_masked ();	/* reset "advancing" timestamp to 0, set lastdec value */
+	else
+		tmo += tmp;		/* else, set advancing stamp wake up time */
+
+	while (get_timer_masked () < tmo)/* loop till event */
+		/*NOP*/;
+}
+
+void reset_timer_masked (void)
+{
+	/* reset time */
+	lastdec = READ_TIMER;  /* capure current decrementer value time */
+	timestamp = 0;	       /* start "advancing" time stamp from 0 */
+}
+
+ulong get_timer_masked (void)
+{
+	ulong now = READ_TIMER;		/* current tick value */
+
+	if (lastdec >= now) {		/* normal mode (non roll) */
+		/* normal mode */
+		timestamp += lastdec - now; /* move stamp fordward with absoulte diff ticks */
+	} else {			/* we have overflow of the count down timer */
+		/* nts = ts + ld + (TLV - now)
+		 * ts=old stamp, ld=time that passed before passing through -1
+		 * (TLV-now) amount of time after passing though -1
+		 * nts = new "advancing time stamp"...it could also roll and cause problems.
+		 */
+		timestamp += lastdec + (TIMER_LOAD_VAL / (TIMER_CLOCK /
+					CONFIG_SYS_HZ)) - now;
+	}
+	lastdec = now;
+
+	return timestamp;
+}
+
+/* waits specified delay value and resets timestamp */
+void udelay_masked (unsigned long usec)
+{
+	ulong tmo;
+	ulong endtime;
+	signed long diff;
+
+	if (usec >= 1000) {		/* if "big" number, spread normalization to seconds */
+		tmo = usec / 1000;	/* start to normalize for usec to ticks per sec */
+		tmo *= CONFIG_SYS_HZ;		/* find number of "ticks" to wait to achieve target */
+		tmo /= 1000;		/* finish normalize. */
+	} else {			/* else small number, don't kill it prior to HZ multiply */
+		tmo = usec * CONFIG_SYS_HZ;
+		tmo /= (1000*1000);
+	}
+
+	endtime = get_timer_masked () + tmo;
+
+	do {
+		ulong now = get_timer_masked ();
+		diff = endtime - now;
+	} while (diff >= 0);
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk (void)
+{
+	return CONFIG_SYS_HZ;
+}
--- a/arch/arm/cpu/arm926ejs/spear/Makefile
+++ b/arch/arm/cpu/arm926ejs/spear/Makefile
@@ -16,8 +16,6 @@ obj-$(CONFIG_DDR_MT47H64M16) += spr600_mt47h64m16_3_333_cl5_psync.o
 obj-$(CONFIG_DDR_MT47H32M16) += spr600_mt47h32m16_333_cl5_psync.o
 obj-$(CONFIG_DDR_MT47H32M16) += spr600_mt47h32m16_37e_166_cl4_sync.o
 obj-$(CONFIG_DDR_MT47H128M8) += spr600_mt47h128m8_3_266_cl5_async.o
-else
-obj-y += spr_misc.o spr_lowlevel_init.o
 endif

 extra-$(CONFIG_SPL_BUILD) := start.o
--- a/arch/arm/cpu/arm926ejs/spear/cpu.c
+++ b/arch/arm/cpu/arm926ejs/spear/cpu.c
@@ -84,7 +84,7 @@ int print_cpuinfo(void)
 }
 #endif

-#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_ECC_BCH) && defined(CONFIG_NAND_FSMC)
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_ECC_BCH)
 static int do_switch_ecc(cmd_tbl_t *cmdtp, int flag, int argc,
 			 char *const argv[])
 {
--- a/arch/arm/cpu/arm926ejs/spear/spl.c
+++ b/arch/arm/cpu/arm926ejs/spear/spl.c
@@ -222,7 +222,7 @@ static void snor_init(void)

 u32 spl_boot_device(void)
 {
-	u32 mode = 0;
+	u32 mode;

 	/* Currently only SNOR is supported as the only */
 	if (snor_boot_selected()) {
--- a/arch/arm/cpu/arm926ejs/spear/timer.c
+++ b/arch/arm/cpu/arm926ejs/spear/timer.c
@@ -37,7 +37,7 @@ int timer_init(void)
 	writel(MISC_PRSC_CFG, &misc_regs_p->prsc1_clk_cfg);
 	synth = MISC_GPT3SYNTH;
 #else
-# error Incorrect config. Can only be SPEAR{600|300|310|320}
+# error Incorrect config. Can only be spear{600|300|310|320}
 #endif

 	writel(readl(&misc_regs_p->periph_clk_cfg) | synth,
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -12,27 +12,36 @@ obj-y	+= cache_v7.o cache_v7_asm.o
 obj-y	+= cpu.o cp15.o
 obj-y	+= syslib.o

+ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_MX7)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_SUNXI)$(CONFIG_ARCH_SOCFPGA),)
 ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y)
 obj-y	+= lowlevel_init.o
 endif
+endif

-obj-$(CONFIG_ARM_SMCCC)		+= smccc-call.o
 obj-$(CONFIG_ARMV7_NONSEC)	+= nonsec_virt.o virt-v7.o virt-dt.o
 obj-$(CONFIG_ARMV7_PSCI)	+= psci.o psci-common.o

 obj-$(CONFIG_IPROC) += iproc-common/
 obj-$(CONFIG_KONA) += kona-common/
+obj-$(CONFIG_OMAP_COMMON) += omap-common/
 obj-$(CONFIG_SYS_ARCH_TIMER) += arch_timer.o

 ifneq (,$(filter s5pc1xx exynos,$(SOC)))
 obj-y += s5p-common/
 endif

+obj-$(if $(filter am33xx,$(SOC)),y) += am33xx/
 obj-$(if $(filter bcm235xx,$(SOC)),y) += bcm235xx/
 obj-$(if $(filter bcm281xx,$(SOC)),y) += bcm281xx/
 obj-$(if $(filter bcmcygnus,$(SOC)),y) += bcmcygnus/
 obj-$(if $(filter bcmnsp,$(SOC)),y) += bcmnsp/
 obj-$(if $(filter ls102xa,$(SOC)),y) += ls102xa/
+obj-$(if $(filter mx5,$(SOC)),y) += mx5/
+obj-$(CONFIG_MX6) += mx6/
+obj-$(CONFIG_MX7) += mx7/
+obj-$(CONFIG_OMAP34XX) += omap3/
+obj-$(CONFIG_OMAP44XX) += omap4/
+obj-$(CONFIG_OMAP54XX) += omap5/
 obj-$(CONFIG_RMOBILE) += rmobile/
 obj-$(if $(filter stv0991,$(SOC)),y) += stv0991/
 obj-$(CONFIG_ARCH_SUNXI) += sunxi/
--- a/arch/arm/cpu/armv7/am33xx/Kconfig
+++ b/arch/arm/cpu/armv7/am33xx/Kconfig
@@ -0,0 +1,40 @@
+if AM43XX
+config TARGET_AM43XX_EVM
+	bool "Support am43xx_evm"
+	select TI_I2C_BOARD_DETECT
+	help
+	  This option specifies support for the AM43xx
+	  GP and HS EVM development platforms.The AM437x
+	  GP EVM is a standalone test, development, and
+	  evaluation module system that enables developers
+	  to write software and develop hardware around
+	  an AM43xx processor subsystem.
+
+config ISW_ENTRY_ADDR
+	hex "Address in memory or XIP flash of bootloader entry point"
+	help
+	  After any reset, the boot ROM on the AM43XX SOC
+	  searches the boot media for a valid boot image.
+	  For non-XIP devices, the ROM then copies the
+	  image into internal memory.
+	  For all boot modes, after the ROM processes the
+	  boot image it eventually computes the entry
+	  point address depending on the device type
+	  (secure/non-secure), boot media (xip/non-xip) and
+	  image headers.
+	default 0x402F4000
+
+config PUB_ROM_DATA_SIZE
+	hex "Size in bytes of the L3 SRAM reserved by ROM to store data"
+	help
+	  During the device boot, the public ROM uses the top of
+	  the public L3 OCMC RAM to store r/w data like stack,
+	  heap, globals etc. When the ROM is copying the boot
+	  image from the boot media into memory, the image must
+	  not spill over into this area. This value can be used
+	  during compile time to determine the maximum size of a
+	  boot image. Once the ROM transfers control to the boot
+	  image, this area is no longer used, and can be reclaimed
+	  for run time use by the boot image.
+	default 0x8400
+endif
--- a/arch/arm/cpu/armv7/am33xx/Makefile
+++ b/arch/arm/cpu/armv7/am33xx/Makefile
@@ -0,0 +1,22 @@
+#
+# Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-$(CONFIG_AM33XX)	+= clock_am33xx.o
+obj-$(CONFIG_TI814X)	+= clock_ti814x.o
+obj-$(CONFIG_AM43XX)	+= clock_am43xx.o
+
+ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX),)
+obj-y	+= clock.o
+endif
+
+obj-$(CONFIG_TI816X)	+= clock_ti816x.o
+obj-y	+= sys_info.o
+obj-y	+= ddr.o
+obj-y	+= emif4.o
+obj-y	+= board.o
+obj-y	+= mux.o
+
+obj-$(CONFIG_CLOCK_SYNTHESIZER)	+= clk_synthesizer.o
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -0,0 +1,300 @@
+/*
+ * board.c
+ *
+ * Common board functions for AM33XX based boards
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <ns16550.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <cpsw.h>
+#include <asm/errno.h>
+#include <linux/compiler.h>
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+#include <linux/usb/musb.h>
+#include <asm/omap_musb.h>
+#include <asm/davinci_rtc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if !CONFIG_IS_ENABLED(OF_CONTROL)
+static const struct ns16550_platdata am33xx_serial[] = {
+	{ .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
+# ifdef CONFIG_SYS_NS16550_COM2
+	{ .base = CONFIG_SYS_NS16550_COM2, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
+#  ifdef CONFIG_SYS_NS16550_COM3
+	{ .base = CONFIG_SYS_NS16550_COM3, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
+	{ .base = CONFIG_SYS_NS16550_COM4, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
+	{ .base = CONFIG_SYS_NS16550_COM5, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
+	{ .base = CONFIG_SYS_NS16550_COM6, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
+#  endif
+# endif
+};
+
+U_BOOT_DEVICES(am33xx_uarts) = {
+	{ "ns16550_serial", &am33xx_serial[0] },
+#  ifdef CONFIG_SYS_NS16550_COM2
+	{ "ns16550_serial", &am33xx_serial[1] },
+#   ifdef CONFIG_SYS_NS16550_COM3
+	{ "ns16550_serial", &am33xx_serial[2] },
+	{ "ns16550_serial", &am33xx_serial[3] },
+	{ "ns16550_serial", &am33xx_serial[4] },
+	{ "ns16550_serial", &am33xx_serial[5] },
+#   endif
+#  endif
+};
+
+#ifdef CONFIG_DM_GPIO
+static const struct omap_gpio_platdata am33xx_gpio[] = {
+	{ 0, AM33XX_GPIO0_BASE },
+	{ 1, AM33XX_GPIO1_BASE },
+	{ 2, AM33XX_GPIO2_BASE },
+	{ 3, AM33XX_GPIO3_BASE },
+#ifdef CONFIG_AM43XX
+	{ 4, AM33XX_GPIO4_BASE },
+	{ 5, AM33XX_GPIO5_BASE },
+#endif
+};
+
+U_BOOT_DEVICES(am33xx_gpios) = {
+	{ "gpio_omap", &am33xx_gpio[0] },
+	{ "gpio_omap", &am33xx_gpio[1] },
+	{ "gpio_omap", &am33xx_gpio[2] },
+	{ "gpio_omap", &am33xx_gpio[3] },
+#ifdef CONFIG_AM43XX
+	{ "gpio_omap", &am33xx_gpio[4] },
+	{ "gpio_omap", &am33xx_gpio[5] },
+#endif
+};
+#endif
+#endif
+
+#ifndef CONFIG_DM_GPIO
+static const struct gpio_bank gpio_bank_am33xx[] = {
+	{ (void *)AM33XX_GPIO0_BASE },
+	{ (void *)AM33XX_GPIO1_BASE },
+	{ (void *)AM33XX_GPIO2_BASE },
+	{ (void *)AM33XX_GPIO3_BASE },
+#ifdef CONFIG_AM43XX
+	{ (void *)AM33XX_GPIO4_BASE },
+	{ (void *)AM33XX_GPIO5_BASE },
+#endif
+};
+
+const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
+#endif
+
+#if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
+int cpu_mmc_init(bd_t *bis)
+{
+	int ret;
+
+	ret = omap_mmc_init(0, 0, 0, -1, -1);
+	if (ret)
+		return ret;
+
+	return omap_mmc_init(1, 0, 0, -1, -1);
+}
+#endif
+
+/* AM33XX has two MUSB controllers which can be host or gadget */
+#if (defined(CONFIG_USB_MUSB_GADGET) || defined(CONFIG_USB_MUSB_HOST)) && \
+	(defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1))
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+/* USB 2.0 PHY Control */
+#define CM_PHY_PWRDN			(1 << 0)
+#define CM_PHY_OTG_PWRDN		(1 << 1)
+#define OTGVDET_EN			(1 << 19)
+#define OTGSESSENDEN			(1 << 20)
+
+static void am33xx_usb_set_phy_power(u8 on, u32 *reg_addr)
+{
+	if (on) {
+		clrsetbits_le32(reg_addr, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN,
+				OTGVDET_EN | OTGSESSENDEN);
+	} else {
+		clrsetbits_le32(reg_addr, 0, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN);
+	}
+}
+
+static struct musb_hdrc_config musb_config = {
+	.multipoint     = 1,
+	.dyn_fifo       = 1,
+	.num_eps        = 16,
+	.ram_bits       = 12,
+};
+
+#ifdef CONFIG_AM335X_USB0
+static void am33xx_otg0_set_phy_power(u8 on)
+{
+	am33xx_usb_set_phy_power(on, &cdev->usb_ctrl0);
+}
+
+struct omap_musb_board_data otg0_board_data = {
+	.set_phy_power = am33xx_otg0_set_phy_power,
+};
+
+static struct musb_hdrc_platform_data otg0_plat = {
+	.mode           = CONFIG_AM335X_USB0_MODE,
+	.config         = &musb_config,
+	.power          = 50,
+	.platform_ops	= &musb_dsps_ops,
+	.board_data	= &otg0_board_data,
+};
+#endif
+
+#ifdef CONFIG_AM335X_USB1
+static void am33xx_otg1_set_phy_power(u8 on)
+{
+	am33xx_usb_set_phy_power(on, &cdev->usb_ctrl1);
+}
+
+struct omap_musb_board_data otg1_board_data = {
+	.set_phy_power = am33xx_otg1_set_phy_power,
+};
+
+static struct musb_hdrc_platform_data otg1_plat = {
+	.mode           = CONFIG_AM335X_USB1_MODE,
+	.config         = &musb_config,
+	.power          = 50,
+	.platform_ops	= &musb_dsps_ops,
+	.board_data	= &otg1_board_data,
+};
+#endif
+#endif
+
+int arch_misc_init(void)
+{
+#ifdef CONFIG_AM335X_USB0
+	musb_register(&otg0_plat, &otg0_board_data,
+		(void *)USB0_OTG_BASE);
+#endif
+#ifdef CONFIG_AM335X_USB1
+	musb_register(&otg1_plat, &otg1_board_data,
+		(void *)USB1_OTG_BASE);
+#endif
+	return 0;
+}
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+/*
+ * In the case of non-SPL based booting we'll want to call these
+ * functions a tiny bit later as it will require gd to be set and cleared
+ * and that's not true in s_init in this case so we cannot do it there.
+ */
+int board_early_init_f(void)
+{
+	prcm_init();
+	set_mux_conf_regs();
+
+	return 0;
+}
+
+/*
+ * This function is the place to do per-board things such as ramp up the
+ * MPU clock frequency.
+ */
+__weak void am33xx_spl_board_init(void)
+{
+	do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
+	do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
+}
+
+#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
+static void rtc32k_enable(void)
+{
+	struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
+
+	/*
+	 * Unlock the RTC's registers.  For more details please see the
+	 * RTC_SS section of the TRM.  In order to unlock we need to
+	 * write these specific values (keys) in this order.
+	 */
+	writel(RTC_KICK0R_WE, &rtc->kick0r);
+	writel(RTC_KICK1R_WE, &rtc->kick1r);
+
+	/* Enable the RTC 32K OSC by setting bits 3 and 6. */
+	writel((1 << 3) | (1 << 6), &rtc->osc);
+}
+#endif
+
+static void uart_soft_reset(void)
+{
+	struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
+	u32 regval;
+
+	regval = readl(&uart_base->uartsyscfg);
+	regval |= UART_RESET;
+	writel(regval, &uart_base->uartsyscfg);
+	while ((readl(&uart_base->uartsyssts) &
+		UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
+		;
+
+	/* Disable smart idle */
+	regval = readl(&uart_base->uartsyscfg);
+	regval |= UART_SMART_IDLE_EN;
+	writel(regval, &uart_base->uartsyscfg);
+}
+
+static void watchdog_disable(void)
+{
+	struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
+
+	writel(0xAAAA, &wdtimer->wdtwspr);
+	while (readl(&wdtimer->wdtwwps) != 0x0)
+		;
+	writel(0x5555, &wdtimer->wdtwspr);
+	while (readl(&wdtimer->wdtwwps) != 0x0)
+		;
+}
+
+#ifdef CONFIG_SPL_BUILD
+void board_init_f(ulong dummy)
+{
+	board_early_init_f();
+	sdram_init();
+}
+#endif
+
+void s_init(void)
+{
+	/*
+	 * The ROM will only have set up sufficient pinmux to allow for the
+	 * first 4KiB NOR to be read, we must finish doing what we know of
+	 * the NOR mux in this space in order to continue.
+	 */
+#ifdef CONFIG_NOR_BOOT
+	enable_norboot_pin_mux();
+#endif
+	watchdog_disable();
+	set_uart_mux_conf();
+	setup_clocks_for_console();
+	uart_soft_reset();
+#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
+	/* Enable RTC32K clock */
+	rtc32k_enable();
+#endif
+}
+#endif
--- a/arch/arm/mach-omap2/am33xx/clk_synthesizer.c
+++ b/arch/arm/mach-omap2/am33xx/clk_synthesizer.c
--- a/arch/arm/cpu/armv7/am33xx/clock.c
+++ b/arch/arm/cpu/armv7/am33xx/clock.c
@@ -0,0 +1,241 @@
+/*
+ * clock.c
+ *
+ * Clock initialization for AM33XX boards.
+ * Derived from OMAP4 boards
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+
+static void setup_post_dividers(const struct dpll_regs *dpll_regs,
+			 const struct dpll_params *params)
+{
+	/* Setup post-dividers */
+	if (params->m2 >= 0)
+		writel(params->m2, dpll_regs->cm_div_m2_dpll);
+	if (params->m3 >= 0)
+		writel(params->m3, dpll_regs->cm_div_m3_dpll);
+	if (params->m4 >= 0)
+		writel(params->m4, dpll_regs->cm_div_m4_dpll);
+	if (params->m5 >= 0)
+		writel(params->m5, dpll_regs->cm_div_m5_dpll);
+	if (params->m6 >= 0)
+		writel(params->m6, dpll_regs->cm_div_m6_dpll);
+}
+
+static inline void do_lock_dpll(const struct dpll_regs *dpll_regs)
+{
+	clrsetbits_le32(dpll_regs->cm_clkmode_dpll,
+			CM_CLKMODE_DPLL_DPLL_EN_MASK,
+			DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT);
+}
+
+static inline void wait_for_lock(const struct dpll_regs *dpll_regs)
+{
+	if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK,
+			   (void *)dpll_regs->cm_idlest_dpll, LDELAY)) {
+		printf("DPLL locking failed for 0x%x\n",
+		       dpll_regs->cm_clkmode_dpll);
+		hang();
+	}
+}
+
+static inline void do_bypass_dpll(const struct dpll_regs *dpll_regs)
+{
+	clrsetbits_le32(dpll_regs->cm_clkmode_dpll,
+			CM_CLKMODE_DPLL_DPLL_EN_MASK,
+			DPLL_EN_MN_BYPASS << CM_CLKMODE_DPLL_EN_SHIFT);
+}
+
+static inline void wait_for_bypass(const struct dpll_regs *dpll_regs)
+{
+	if (!wait_on_value(ST_DPLL_CLK_MASK, 0,
+			   (void *)dpll_regs->cm_idlest_dpll, LDELAY)) {
+		printf("Bypassing DPLL failed 0x%x\n",
+		       dpll_regs->cm_clkmode_dpll);
+	}
+}
+
+static void bypass_dpll(const struct dpll_regs *dpll_regs)
+{
+	do_bypass_dpll(dpll_regs);
+	wait_for_bypass(dpll_regs);
+}
+
+void do_setup_dpll(const struct dpll_regs *dpll_regs,
+		   const struct dpll_params *params)
+{
+	u32 temp;
+
+	if (!params)
+		return;
+
+	temp = readl(dpll_regs->cm_clksel_dpll);
+
+	bypass_dpll(dpll_regs);
+
+	/* Set M & N */
+	temp &= ~CM_CLKSEL_DPLL_M_MASK;
+	temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK;
+
+	temp &= ~CM_CLKSEL_DPLL_N_MASK;
+	temp |= (params->n << CM_CLKSEL_DPLL_N_SHIFT) & CM_CLKSEL_DPLL_N_MASK;
+
+	writel(temp, dpll_regs->cm_clksel_dpll);
+
+	setup_post_dividers(dpll_regs, params);
+
+	/* Wait till the DPLL locks */
+	do_lock_dpll(dpll_regs);
+	wait_for_lock(dpll_regs);
+}
+
+static void setup_dplls(void)
+{
+	const struct dpll_params *params;
+
+	params = get_dpll_core_params();
+	do_setup_dpll(&dpll_core_regs, params);
+
+	params = get_dpll_mpu_params();
+	do_setup_dpll(&dpll_mpu_regs, params);
+
+	params = get_dpll_per_params();
+	do_setup_dpll(&dpll_per_regs, params);
+	writel(0x300, &cmwkup->clkdcoldodpllper);
+
+	params = get_dpll_ddr_params();
+	do_setup_dpll(&dpll_ddr_regs, params);
+}
+
+static inline void wait_for_clk_enable(u32 *clkctrl_addr)
+{
+	u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
+	u32 bound = LDELAY;
+
+	while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
+		(idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
+		clkctrl = readl(clkctrl_addr);
+		idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
+			 MODULE_CLKCTRL_IDLEST_SHIFT;
+		if (--bound == 0) {
+			printf("Clock enable failed for 0x%p idlest 0x%x\n",
+			       clkctrl_addr, clkctrl);
+			return;
+		}
+	}
+}
+
+static inline void enable_clock_module(u32 *const clkctrl_addr, u32 enable_mode,
+				       u32 wait_for_enable)
+{
+	clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
+			enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT);
+	debug("Enable clock module - %p\n", clkctrl_addr);
+	if (wait_for_enable)
+		wait_for_clk_enable(clkctrl_addr);
+}
+
+static inline void wait_for_clk_disable(u32 *clkctrl_addr)
+{
+	u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL;
+	u32 bound = LDELAY;
+
+	while ((idlest != MODULE_CLKCTRL_IDLEST_DISABLED)) {
+		clkctrl = readl(clkctrl_addr);
+		idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
+			  MODULE_CLKCTRL_IDLEST_SHIFT;
+		if (--bound == 0) {
+			printf("Clock disable failed for 0x%p idlest 0x%x\n",
+			       clkctrl_addr, clkctrl);
+			 return;
+		}
+	}
+}
+static inline void disable_clock_module(u32 *const clkctrl_addr,
+					u32 wait_for_disable)
+{
+	clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
+			MODULE_CLKCTRL_MODULEMODE_SW_DISABLE <<
+			MODULE_CLKCTRL_MODULEMODE_SHIFT);
+	debug("Disable clock module - %p\n", clkctrl_addr);
+	if (wait_for_disable)
+		wait_for_clk_disable(clkctrl_addr);
+}
+
+static inline void enable_clock_domain(u32 *const clkctrl_reg, u32 enable_mode)
+{
+	clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
+			enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT);
+	debug("Enable clock domain - %p\n", clkctrl_reg);
+}
+
+static inline void disable_clock_domain(u32 *const clkctrl_reg)
+{
+	clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
+			CD_CLKCTRL_CLKTRCTRL_SW_SLEEP <<
+			CD_CLKCTRL_CLKTRCTRL_SHIFT);
+	debug("Disable clock domain - %p\n", clkctrl_reg);
+}
+
+void do_enable_clocks(u32 *const *clk_domains,
+		      u32 *const *clk_modules_explicit_en, u8 wait_for_enable)
+{
+	u32 i, max = 100;
+
+	/* Put the clock domains in SW_WKUP mode */
+	for (i = 0; (i < max) && clk_domains[i]; i++) {
+		enable_clock_domain(clk_domains[i],
+				    CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
+	}
+
+	/* Clock modules that need to be put in SW_EXPLICIT_EN mode */
+	for (i = 0; (i < max) && clk_modules_explicit_en[i]; i++) {
+		enable_clock_module(clk_modules_explicit_en[i],
+				    MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
+				    wait_for_enable);
+	};
+}
+
+void do_disable_clocks(u32 *const *clk_domains,
+			u32 *const *clk_modules_disable,
+			u8 wait_for_disable)
+{
+	u32 i, max = 100;
+
+
+	/* Clock modules that need to be put in SW_DISABLE */
+	for (i = 0; (i < max) && clk_modules_disable[i]; i++)
+		disable_clock_module(clk_modules_disable[i],
+				     wait_for_disable);
+
+	/* Put the clock domains in SW_SLEEP mode */
+	for (i = 0; (i < max) && clk_domains[i]; i++)
+		disable_clock_domain(clk_domains[i]);
+}
+
+/*
+ * Before scaling up the clocks we need to have the PMIC scale up the
+ * voltages first.  This will be dependent on which PMIC is in use
+ * and in some cases we may not be scaling things up at all and thus not
+ * need to do anything here.
+ */
+__weak void scale_vcores(void)
+{
+}
+
+void prcm_init()
+{
+	enable_basic_clocks();
+	scale_vcores();
+	setup_dplls();
+	timer_init();
+}
--- a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
@@ -0,0 +1,234 @@
+/*
+ * clock_am33xx.c
+ *
+ * clocks for AM33XX based boards
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+
+#define OSC	(V_OSCK/1000000)
+
+struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
+struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
+struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL;
+struct cm_rtc *const cmrtc = (struct cm_rtc *)CM_RTC;
+
+const struct dpll_regs dpll_mpu_regs = {
+	.cm_clkmode_dpll	= CM_WKUP + 0x88,
+	.cm_idlest_dpll		= CM_WKUP + 0x20,
+	.cm_clksel_dpll		= CM_WKUP + 0x2C,
+	.cm_div_m2_dpll		= CM_WKUP + 0xA8,
+};
+
+const struct dpll_regs dpll_core_regs = {
+	.cm_clkmode_dpll	= CM_WKUP + 0x90,
+	.cm_idlest_dpll		= CM_WKUP + 0x5C,
+	.cm_clksel_dpll		= CM_WKUP + 0x68,
+	.cm_div_m4_dpll		= CM_WKUP + 0x80,
+	.cm_div_m5_dpll		= CM_WKUP + 0x84,
+	.cm_div_m6_dpll		= CM_WKUP + 0xD8,
+};
+
+const struct dpll_regs dpll_per_regs = {
+	.cm_clkmode_dpll	= CM_WKUP + 0x8C,
+	.cm_idlest_dpll		= CM_WKUP + 0x70,
+	.cm_clksel_dpll		= CM_WKUP + 0x9C,
+	.cm_div_m2_dpll		= CM_WKUP + 0xAC,
+};
+
+const struct dpll_regs dpll_ddr_regs = {
+	.cm_clkmode_dpll	= CM_WKUP + 0x94,
+	.cm_idlest_dpll		= CM_WKUP + 0x34,
+	.cm_clksel_dpll		= CM_WKUP + 0x40,
+	.cm_div_m2_dpll		= CM_WKUP + 0xA0,
+};
+
+struct dpll_params dpll_mpu_opp100 = {
+		CONFIG_SYS_MPUCLK, OSC-1, 1, -1, -1, -1, -1};
+const struct dpll_params dpll_core_opp100 = {
+		1000, OSC-1, -1, -1, 10, 8, 4};
+const struct dpll_params dpll_mpu = {
+		MPUPLL_M_300, OSC-1, 1, -1, -1, -1, -1};
+const struct dpll_params dpll_core = {
+		50, OSC-1, -1, -1, 1, 1, 1};
+const struct dpll_params dpll_per = {
+		960, OSC-1, 5, -1, -1, -1, -1};
+
+const struct dpll_params *get_dpll_mpu_params(void)
+{
+	return &dpll_mpu;
+}
+
+const struct dpll_params *get_dpll_core_params(void)
+{
+	return &dpll_core;
+}
+
+const struct dpll_params *get_dpll_per_params(void)
+{
+	return &dpll_per;
+}
+
+void setup_clocks_for_console(void)
+{
+	clrsetbits_le32(&cmwkup->wkclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
+			CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
+			CD_CLKCTRL_CLKTRCTRL_SHIFT);
+
+	clrsetbits_le32(&cmper->l4hsclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
+			CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
+			CD_CLKCTRL_CLKTRCTRL_SHIFT);
+
+	clrsetbits_le32(&cmwkup->wkup_uart0ctrl,
+			MODULE_CLKCTRL_MODULEMODE_MASK,
+			MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
+			MODULE_CLKCTRL_MODULEMODE_SHIFT);
+	clrsetbits_le32(&cmper->uart1clkctrl,
+			MODULE_CLKCTRL_MODULEMODE_MASK,
+			MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
+			MODULE_CLKCTRL_MODULEMODE_SHIFT);
+	clrsetbits_le32(&cmper->uart2clkctrl,
+			MODULE_CLKCTRL_MODULEMODE_MASK,
+			MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
+			MODULE_CLKCTRL_MODULEMODE_SHIFT);
+	clrsetbits_le32(&cmper->uart3clkctrl,
+			MODULE_CLKCTRL_MODULEMODE_MASK,
+			MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
+			MODULE_CLKCTRL_MODULEMODE_SHIFT);
+	clrsetbits_le32(&cmper->uart4clkctrl,
+			MODULE_CLKCTRL_MODULEMODE_MASK,
+			MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
+			MODULE_CLKCTRL_MODULEMODE_SHIFT);
+	clrsetbits_le32(&cmper->uart5clkctrl,
+			MODULE_CLKCTRL_MODULEMODE_MASK,
+			MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
+			MODULE_CLKCTRL_MODULEMODE_SHIFT);
+}
+
+void enable_basic_clocks(void)
+{
+	u32 *const clk_domains[] = {
+		&cmper->l3clkstctrl,
+		&cmper->l4fwclkstctrl,
+		&cmper->l3sclkstctrl,
+		&cmper->l4lsclkstctrl,
+		&cmwkup->wkclkstctrl,
+		&cmper->emiffwclkctrl,
+		&cmrtc->clkstctrl,
+		0
+	};
+
+	u32 *const clk_modules_explicit_en[] = {
+		&cmper->l3clkctrl,
+		&cmper->l4lsclkctrl,
+		&cmper->l4fwclkctrl,
+		&cmwkup->wkl4wkclkctrl,
+		&cmper->l3instrclkctrl,
+		&cmper->l4hsclkctrl,
+		&cmwkup->wkgpio0clkctrl,
+		&cmwkup->wkctrlclkctrl,
+		&cmper->timer2clkctrl,
+		&cmper->gpmcclkctrl,
+		&cmper->elmclkctrl,
+		&cmper->mmc0clkctrl,
+		&cmper->mmc1clkctrl,
+		&cmwkup->wkup_i2c0ctrl,
+		&cmper->gpio1clkctrl,
+		&cmper->gpio2clkctrl,
+		&cmper->gpio3clkctrl,
+		&cmper->i2c1clkctrl,
+		&cmper->cpgmac0clkctrl,
+		&cmper->spi0clkctrl,
+		&cmrtc->rtcclkctrl,
+		&cmper->usb0clkctrl,
+		&cmper->emiffwclkctrl,
+		&cmper->emifclkctrl,
+		0
+	};
+
+	do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
+
+	/* Select the Master osc 24 MHZ as Timer2 clock source */
+	writel(0x1, &cmdpll->clktimer2clk);
+}
+
+/*
+ * Enable Spread Spectrum for the MPU by calculating the required
+ * values and setting the registers accordingly.
+ * @param permille The spreading in permille (10th of a percent)
+ */
+void set_mpu_spreadspectrum(int permille)
+{
+	u32 multiplier_m;
+	u32 predivider_n;
+	u32 cm_clksel_dpll_mpu;
+	u32 cm_clkmode_dpll_mpu;
+	u32 ref_clock;
+	u32 pll_bandwidth;
+	u32 mod_freq_divider;
+	u32 exponent;
+	u32 mantissa;
+	u32 delta_m_step;
+
+	printf("Enabling Spread Spectrum of %d permille for MPU\n",
+	       permille);
+
+	/* Read PLL parameter m and n */
+	cm_clksel_dpll_mpu = readl(&cmwkup->clkseldpllmpu);
+	multiplier_m = (cm_clksel_dpll_mpu >> 8) & 0x3FF;
+	predivider_n = cm_clksel_dpll_mpu & 0x7F;
+
+	/*
+	 * Calculate reference clock (clock after pre-divider),
+	 * its max. PLL bandwidth,
+	 * and resulting mod_freq_divider
+	 */
+	ref_clock = V_OSCK / (predivider_n + 1);
+	pll_bandwidth = ref_clock / 70;
+	mod_freq_divider = ref_clock / (4 * pll_bandwidth);
+
+	/* Calculate Mantissa/Exponent */
+	exponent = 0;
+	mantissa = mod_freq_divider;
+	while ((mantissa > 127) && (exponent < 7)) {
+		exponent++;
+		mantissa /= 2;
+	}
+	if (mantissa > 127)
+		mantissa = 127;
+
+	mod_freq_divider = mantissa << exponent;
+
+	/*
+	 * Calculate Modulation steps
+	 * As we use Downspread only, the spread is twice the value of
+	 * permille, so Div2!
+	 * As it takes the value in percent, divide by ten!
+	 */
+	delta_m_step = ((u32)((multiplier_m * permille) / 10 / 2)) << 18;
+	delta_m_step /= 100;
+	delta_m_step /= mod_freq_divider;
+	if (delta_m_step > 0xFFFFF)
+		delta_m_step = 0xFFFFF;
+
+	/* Setup Spread Spectrum */
+	writel(delta_m_step, &cmwkup->sscdeltamstepdllmpu);
+	writel((exponent << 8) | mantissa, &cmwkup->sscmodfreqdivdpllmpu);
+	cm_clkmode_dpll_mpu = readl(&cmwkup->clkmoddpllmpu);
+	/* clear all SSC flags */
+	cm_clkmode_dpll_mpu &= ~(0xF << CM_CLKMODE_DPLL_SSC_EN_SHIFT);
+	/* enable SSC with Downspread only */
+	cm_clkmode_dpll_mpu |=  CM_CLKMODE_DPLL_SSC_EN_MASK |
+				CM_CLKMODE_DPLL_SSC_DOWNSPREAD_MASK;
+	writel(cm_clkmode_dpll_mpu, &cmwkup->clkmoddpllmpu);
+	while (!(readl(&cmwkup->clkmoddpllmpu) & 0x2000))
+		;
+}
--- a/arch/arm/mach-omap2/am33xx/clock_am43xx.c
+++ b/arch/arm/mach-omap2/am33xx/clock_am43xx.c
--- a/arch/arm/mach-omap2/am33xx/clock_ti814x.c
+++ b/arch/arm/mach-omap2/am33xx/clock_ti814x.c
@@ -386,12 +386,6 @@ void setup_clocks_for_console(void)
 	while (readl(&cmalwon->uart0clkctrl) != PRCM_MOD_EN)
 		;
 }
-
-void setup_early_clocks(void)
-{
-	setup_clocks_for_console();
-}
-
 /*
 * Configure the PLL/PRCM for necessary peripherals
 */
--- a/arch/arm/mach-omap2/am33xx/clock_ti816x.c
+++ b/arch/arm/mach-omap2/am33xx/clock_ti816x.c
@@ -54,6 +54,55 @@
 #define MAIN_MDIV7		0x4

 /* DDR PLL */
+#if defined(CONFIG_TI816X_DDR_PLL_400) /* 400 MHz */
+#define DDR_N			59
+#define DDR_P			0x1
+#define DDR_MDIV1		0x4
+#define DDR_INTFREQ2		0x8
+#define DDR_FRACFREQ2		0xD99999
+#define DDR_MDIV2		0x1E
+#define DDR_INTFREQ3		0x8
+#define DDR_FRACFREQ3		0x0
+#define DDR_MDIV3		0x4
+#define DDR_INTFREQ4		0xE /* Expansion DDR clk */
+#define DDR_FRACFREQ4		0x0
+#define DDR_MDIV4		0x4
+#define DDR_INTFREQ5		0xE /* Expansion DDR clk */
+#define DDR_FRACFREQ5		0x0
+#define DDR_MDIV5		0x4
+#elif defined(CONFIG_TI816X_DDR_PLL_531) /* 531 MHz */
+#define DDR_N			59
+#define DDR_P			0x1
+#define DDR_MDIV1		0x3
+#define DDR_INTFREQ2		0x8
+#define DDR_FRACFREQ2		0xD99999
+#define DDR_MDIV2		0x1E
+#define DDR_INTFREQ3		0x8
+#define DDR_FRACFREQ3		0x0
+#define DDR_MDIV3		0x4
+#define DDR_INTFREQ4		0xE /* Expansion DDR clk */
+#define DDR_FRACFREQ4		0x0
+#define DDR_MDIV4		0x4
+#define DDR_INTFREQ5		0xE /* Expansion DDR clk */
+#define DDR_FRACFREQ5		0x0
+#define DDR_MDIV5		0x4
+#elif defined(CONFIG_TI816X_DDR_PLL_675) /* 675 MHz */
+#define DDR_N			50
+#define DDR_P			0x1
+#define DDR_MDIV1		0x2
+#define DDR_INTFREQ2		0x9
+#define DDR_FRACFREQ2		0x0
+#define DDR_MDIV2		0x19
+#define DDR_INTFREQ3		0x13
+#define DDR_FRACFREQ3		0x800000
+#define DDR_MDIV3		0x2
+#define DDR_INTFREQ4		0xE /* Expansion DDR clk */
+#define DDR_FRACFREQ4		0x0
+#define DDR_MDIV4		0x4
+#define DDR_INTFREQ5		0xE /* Expansion DDR clk */
+#define DDR_FRACFREQ5		0x0
+#define DDR_MDIV5		0x4
+#elif defined(CONFIG_TI816X_DDR_PLL_796) /* 796 MHz */
 #define DDR_N			59
 #define DDR_P			0x1
 #define DDR_MDIV1		0x2
@@ -69,10 +118,12 @@
 #define DDR_INTFREQ5		0xE /* Expansion DDR clk */
 #define DDR_FRACFREQ5		0x0
 #define DDR_MDIV5		0x4
+#endif

 #define CONTROL_STATUS			(CTRL_BASE + 0x40)
 #define DDR_RCD				(CTRL_BASE + 0x070C)
 #define CM_TIMER1_CLKSEL		(PRCM_BASE + 0x390)
+#define DMM_PAT_BASE_ADDR		(DMM_BASE + 0x420)
 #define CM_ALWON_CUST_EFUSE_CLKCTRL	(PRCM_BASE + 0x1628)

 #define INTCPS_SYSCONFIG	0x48200010
@@ -136,15 +187,6 @@ const struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;

 void enable_dmm_clocks(void)
 {
-	writel(PRCM_MOD_EN, &cmdef->dmmclkctrl);
-	/* Wait for dmm to be fully functional, including OCP */
-	while (((readl(&cmdef->dmmclkctrl) >> 17) & 0x3) != 0)
-		;
-}
-
-void enable_emif_clocks(void)
-{
-	writel(PRCM_MOD_EN, &cmdef->fwclkctrl);
 	writel(PRCM_MOD_EN, &cmdef->l3fastclkstctrl);
 	writel(PRCM_MOD_EN, &cmdef->emif0clkctrl);
 	writel(PRCM_MOD_EN, &cmdef->emif1clkctrl);
@@ -158,6 +200,14 @@ void enable_emif_clocks(void)
 	/* Wait for emif1 to be fully functional, including OCP */
 	while (((readl(&cmdef->emif1clkctrl) >> 17) & 0x3) != 0)
 		;
+
+	writel(PRCM_MOD_EN, &cmdef->dmmclkctrl);
+	/* Wait for dmm to be fully functional, including OCP */
+	while (((readl(&cmdef->dmmclkctrl) >> 17) & 0x3) != 0)
+		;
+
+	/* Enable Tiled Access */
+	writel(0x80000000, DMM_PAT_BASE_ADDR);
 }

 /* assume delay is aprox at least 1us */
@@ -335,13 +385,7 @@ static void peripheral_enable(void)
 	writel(PRCM_MOD_EN, &cmalwon->gpio0clkctrl);
 	while (readl(&cmalwon->gpio0clkctrl) != PRCM_MOD_EN)
 		;
-	writel((BIT(1) | BIT(8)), &cmalwon->gpio0clkctrl);
-
-	/* Enable gpio1 */
-	writel(PRCM_MOD_EN, &cmalwon->gpio1clkctrl);
-	while (readl(&cmalwon->gpio1clkctrl) != PRCM_MOD_EN)
-		;
-	writel((BIT(1) | BIT(8)), &cmalwon->gpio1clkctrl);
+	writel((BIT(8)), &cmalwon->gpio0clkctrl);

 	/* Enable spi */
 	writel(PRCM_MOD_EN, &cmalwon->spiclkctrl);
@@ -385,11 +429,6 @@ void setup_clocks_for_console(void)
 		;
 }

-void setup_early_clocks(void)
-{
-	setup_clocks_for_console();
-}
-
 void prcm_init(void)
 {
 	/* Enable the control */
--- a/arch/arm/cpu/armv7/am33xx/config.mk
+++ b/arch/arm/cpu/armv7/am33xx/config.mk
@@ -0,0 +1,32 @@
+#
+# Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+include  $(srctree)/$(CPUDIR)/omap-common/config_secure.mk
+
+ifdef CONFIG_SPL_BUILD
+ifeq ($(CONFIG_TI_SECURE_DEVICE),y)
+#
+# For booting from SPI use
+# u-boot-spl_HS_SPI_X-LOADER to program flash
+#
+# For booting spl from all other  media
+# use u-boot-spl_HS_ISSW
+#
+# Refer to README.ti-secure for more info
+#
+ALL-y	+= u-boot-spl_HS_ISSW
+ALL-$(CONFIG_SPL_SPI_SUPPORT) += u-boot-spl_HS_SPI_X-LOADER
+else
+ALL-y	+= MLO
+ALL-$(CONFIG_SPL_SPI_SUPPORT) += MLO.byteswap
+endif
+else
+ifeq ($(CONFIG_TI_SECURE_DEVICE),y)
+ALL-$(CONFIG_QSPI_BOOT) += u-boot_HS_XIP_X-LOADER
+ALL-$(CONFIG_SPL_LOAD_FIT) += u-boot_HS.img
+endif
+ALL-y	+= u-boot.img
+endif
--- a/arch/arm/cpu/armv7/am33xx/ddr.c
+++ b/arch/arm/cpu/armv7/am33xx/ddr.c
@@ -0,0 +1,377 @@
+/*
+ * DDR Configuration for AM33xx devices.
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/arch/cpu.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+
+/**
+ * Base address for EMIF instances
+ */
+static struct emif_reg_struct *emif_reg[2] = {
+				(struct emif_reg_struct *)EMIF4_0_CFG_BASE,
+				(struct emif_reg_struct *)EMIF4_1_CFG_BASE};
+
+/**
+ * Base addresses for DDR PHY cmd/data regs
+ */
+static struct ddr_cmd_regs *ddr_cmd_reg[2] = {
+				(struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR,
+				(struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR2};
+
+static struct ddr_data_regs *ddr_data_reg[2] = {
+				(struct ddr_data_regs *)DDR_PHY_DATA_ADDR,
+				(struct ddr_data_regs *)DDR_PHY_DATA_ADDR2};
+
+/**
+ * Base address for ddr io control instances
+ */
+static struct ddr_cmdtctrl *ioctrl_reg = {
+			(struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR};
+
+static inline u32 get_mr(int nr, u32 cs, u32 mr_addr)
+{
+	u32 mr;
+
+	mr_addr |= cs << EMIF_REG_CS_SHIFT;
+	writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg);
+
+	mr = readl(&emif_reg[nr]->emif_lpddr2_mode_reg_data);
+	debug("get_mr: EMIF1 cs %d mr %08x val 0x%x\n", cs, mr_addr, mr);
+	if (((mr & 0x0000ff00) >>  8) == (mr & 0xff) &&
+	    ((mr & 0x00ff0000) >> 16) == (mr & 0xff) &&
+	    ((mr & 0xff000000) >> 24) == (mr & 0xff))
+		return mr & 0xff;
+	else
+		return mr;
+}
+
+static inline void set_mr(int nr, u32 cs, u32 mr_addr, u32 mr_val)
+{
+	mr_addr |= cs << EMIF_REG_CS_SHIFT;
+	writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg);
+	writel(mr_val, &emif_reg[nr]->emif_lpddr2_mode_reg_data);
+}
+
+static void configure_mr(int nr, u32 cs)
+{
+	u32 mr_addr;
+
+	while (get_mr(nr, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
+		;
+	set_mr(nr, cs, LPDDR2_MR10, 0x56);
+
+	set_mr(nr, cs, LPDDR2_MR1, 0x43);
+	set_mr(nr, cs, LPDDR2_MR2, 0x2);
+
+	mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK;
+	set_mr(nr, cs, mr_addr, 0x2);
+}
+
+/*
+ * Configure EMIF4D5 registers and MR registers For details about these magic
+ * values please see the EMIF registers section of the TRM.
+ */
+void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
+{
+	writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl);
+	writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw);
+	writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
+
+	writel(regs->temp_alert_config, &emif_reg[nr]->emif_temp_alert_config);
+	writel(regs->emif_rd_wr_lvl_rmp_win,
+	       &emif_reg[nr]->emif_rd_wr_lvl_rmp_win);
+	writel(regs->emif_rd_wr_lvl_rmp_ctl,
+	       &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl);
+	writel(regs->emif_rd_wr_lvl_ctl, &emif_reg[nr]->emif_rd_wr_lvl_ctl);
+	writel(regs->emif_rd_wr_exec_thresh,
+	       &emif_reg[nr]->emif_rd_wr_exec_thresh);
+
+	/*
+	 * for most SOCs these registers won't need to be changed so only
+	 * write to these registers if someone explicitly has set the
+	 * register's value.
+	 */
+	if(regs->emif_cos_config) {
+		writel(regs->emif_prio_class_serv_map, &emif_reg[nr]->emif_prio_class_serv_map);
+		writel(regs->emif_connect_id_serv_1_map, &emif_reg[nr]->emif_connect_id_serv_1_map);
+		writel(regs->emif_connect_id_serv_2_map, &emif_reg[nr]->emif_connect_id_serv_2_map);
+		writel(regs->emif_cos_config, &emif_reg[nr]->emif_cos_config);
+	}
+
+	/*
+	 * Sequence to ensure that the PHY is in a known state prior to
+	 * startting hardware leveling.  Also acts as to latch some state from
+	 * the EMIF into the PHY.
+	 */
+	writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
+	writel(0x2411, &emif_reg[nr]->emif_iodft_tlgc);
+	writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
+
+	clrbits_le32(&emif_reg[nr]->emif_sdram_ref_ctrl,
+			EMIF_REG_INITREF_DIS_MASK);
+
+	writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
+	writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
+
+	/* Wait 1ms because of L3 timeout error */
+	udelay(1000);
+
+	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
+	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
+
+	/* Perform hardware leveling for DDR3 */
+	if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3) {
+		writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36) |
+		       0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36);
+		writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw) |
+		       0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw);
+
+		writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl);
+
+		/* Enable read leveling */
+		writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_ctl);
+
+		/*
+		 * Enable full read and write leveling.  Wait for read and write
+		 * leveling bit to clear RDWRLVLFULL_START bit 31
+		 */
+		while ((readl(&emif_reg[nr]->emif_rd_wr_lvl_ctl) & 0x80000000)
+		      != 0)
+			;
+
+		/* Check the timeout register to see if leveling is complete */
+		if ((readl(&emif_reg[nr]->emif_status) & 0x70) != 0)
+			puts("DDR3 H/W leveling incomplete with errors\n");
+
+	} else {
+		/* DDR2 */
+		configure_mr(nr, 0);
+		configure_mr(nr, 1);
+	}
+}
+
+/**
+ * Configure SDRAM
+ */
+void config_sdram(const struct emif_regs *regs, int nr)
+{
+	if (regs->zq_config) {
+		writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
+		writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
+		writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
+
+		/* Trigger initialization */
+		writel(0x00003100, &emif_reg[nr]->emif_sdram_ref_ctrl);
+		/* Wait 1ms because of L3 timeout error */
+		udelay(1000);
+
+		/* Write proper sdram_ref_cref_ctrl value */
+		writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
+		writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
+	}
+	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
+	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
+	writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
+}
+
+/**
+ * Set SDRAM timings
+ */
+void set_sdram_timings(const struct emif_regs *regs, int nr)
+{
+	writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1);
+	writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1_shdw);
+	writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2);
+	writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2_shdw);
+	writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3);
+	writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3_shdw);
+}
+
+/*
+ * Configure EXT PHY registers for software leveling
+ */
+static void ext_phy_settings_swlvl(const struct emif_regs *regs, int nr)
+{
+	u32 *ext_phy_ctrl_base = 0;
+	u32 *emif_ext_phy_ctrl_base = 0;
+	__maybe_unused const u32 *ext_phy_ctrl_const_regs;
+	u32 i = 0;
+	__maybe_unused u32 size;
+
+	ext_phy_ctrl_base = (u32 *)&(regs->emif_ddr_ext_phy_ctrl_1);
+	emif_ext_phy_ctrl_base =
+			(u32 *)&(emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
+
+	/* Configure external phy control timing registers */
+	for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
+		writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
+		/* Update shadow registers */
+		writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
+	}
+
+#ifdef CONFIG_AM43XX
+	/*
+	 * External phy 6-24 registers do not change with ddr frequency.
+	 * These only need to be set on DDR2 on AM43xx.
+	 */
+	emif_get_ext_phy_ctrl_const_regs(&ext_phy_ctrl_const_regs, &size);
+
+	if (!size)
+		return;
+
+	for (i = 0; i < size; i++) {
+		writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++);
+		/* Update shadow registers */
+		writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++);
+	}
+#endif
+}
+
+/*
+ * Configure EXT PHY registers for hardware leveling
+ */
+static void ext_phy_settings_hwlvl(const struct emif_regs *regs, int nr)
+{
+	/*
+	 * Enable hardware leveling on the EMIF.  For details about these
+	 * magic values please see the EMIF registers section of the TRM.
+	 */
+	writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
+	writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1_shdw);
+	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_22);
+	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_22_shdw);
+	writel(0x00600020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_23);
+	writel(0x00600020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_23_shdw);
+	writel(0x40010080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_24);
+	writel(0x40010080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_24_shdw);
+	writel(0x08102040, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_25);
+	writel(0x08102040, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_25_shdw);
+	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_26);
+	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_26_shdw);
+	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_27);
+	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_27_shdw);
+	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_28);
+	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_28_shdw);
+	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_29);
+	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_29_shdw);
+	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_30);
+	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_30_shdw);
+	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_31);
+	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_31_shdw);
+	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_32);
+	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_32_shdw);
+	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_33);
+	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_33_shdw);
+	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_34);
+	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_34_shdw);
+	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35);
+	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35_shdw);
+	writel(0x000000FF, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36);
+	writel(0x000000FF, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw);
+
+	/*
+	 * Sequence to ensure that the PHY is again in a known state after
+	 * hardware leveling.
+	 */
+	writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
+	writel(0x2411, &emif_reg[nr]->emif_iodft_tlgc);
+	writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
+}
+
+/**
+ * Configure DDR PHY
+ */
+void config_ddr_phy(const struct emif_regs *regs, int nr)
+{
+	/*
+	 * Disable initialization and refreshes for now until we finish
+	 * programming EMIF regs and set time between rising edge of
+	 * DDR_RESET to rising edge of DDR_CKE to > 500us per memory spec.
+	 * We currently hardcode a value based on a max expected frequency
+	 * of 400MHz.
+	 */
+	writel(EMIF_REG_INITREF_DIS_MASK | 0x3100,
+		&emif_reg[nr]->emif_sdram_ref_ctrl);
+
+	writel(regs->emif_ddr_phy_ctlr_1,
+		&emif_reg[nr]->emif_ddr_phy_ctrl_1);
+	writel(regs->emif_ddr_phy_ctlr_1,
+		&emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw);
+
+	if (get_emif_rev((u32)emif_reg[nr]) == EMIF_4D5) {
+		if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3)
+			ext_phy_settings_hwlvl(regs, nr);
+		else
+			ext_phy_settings_swlvl(regs, nr);
+	}
+}
+
+/**
+ * Configure DDR CMD control registers
+ */
+void config_cmd_ctrl(const struct cmd_control *cmd, int nr)
+{
+	if (!cmd)
+		return;
+
+	writel(cmd->cmd0csratio, &ddr_cmd_reg[nr]->cm0csratio);
+	writel(cmd->cmd0iclkout, &ddr_cmd_reg[nr]->cm0iclkout);
+
+	writel(cmd->cmd1csratio, &ddr_cmd_reg[nr]->cm1csratio);
+	writel(cmd->cmd1iclkout, &ddr_cmd_reg[nr]->cm1iclkout);
+
+	writel(cmd->cmd2csratio, &ddr_cmd_reg[nr]->cm2csratio);
+	writel(cmd->cmd2iclkout, &ddr_cmd_reg[nr]->cm2iclkout);
+}
+
+/**
+ * Configure DDR DATA registers
+ */
+void config_ddr_data(const struct ddr_data *data, int nr)
+{
+	int i;
+
+	if (!data)
+		return;
+
+	for (i = 0; i < DDR_DATA_REGS_NR; i++) {
+		writel(data->datardsratio0,
+			&(ddr_data_reg[nr]+i)->dt0rdsratio0);
+		writel(data->datawdsratio0,
+			&(ddr_data_reg[nr]+i)->dt0wdsratio0);
+		writel(data->datawiratio0,
+			&(ddr_data_reg[nr]+i)->dt0wiratio0);
+		writel(data->datagiratio0,
+			&(ddr_data_reg[nr]+i)->dt0giratio0);
+		writel(data->datafwsratio0,
+			&(ddr_data_reg[nr]+i)->dt0fwsratio0);
+		writel(data->datawrsratio0,
+			&(ddr_data_reg[nr]+i)->dt0wrsratio0);
+	}
+}
+
+void config_io_ctrl(const struct ctrl_ioregs *ioregs)
+{
+	if (!ioregs)
+		return;
+
+	writel(ioregs->cm0ioctl, &ioctrl_reg->cm0ioctl);
+	writel(ioregs->cm1ioctl, &ioctrl_reg->cm1ioctl);
+	writel(ioregs->cm2ioctl, &ioctrl_reg->cm2ioctl);
+	writel(ioregs->dt0ioctl, &ioctrl_reg->dt0ioctl);
+	writel(ioregs->dt1ioctl, &ioctrl_reg->dt1ioctl);
+#ifdef CONFIG_AM43XX
+	writel(ioregs->dt2ioctrl, &ioctrl_reg->dt2ioctrl);
+	writel(ioregs->dt3ioctrl, &ioctrl_reg->dt3ioctrl);
+	writel(ioregs->emif_sdram_config_ext,
+	       &ioctrl_reg->emif_sdram_config_ext);
+#endif
+}
--- a/arch/arm/cpu/armv7/am33xx/emif4.c
+++ b/arch/arm/cpu/armv7/am33xx/emif4.c
@@ -0,0 +1,140 @@
+/*
+ * emif4.c
+ *
+ * AM33XX emif4 configuration file
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+	sdram_init();
+#endif
+
+	/* dram_init must store complete ramsize in gd->ram_size */
+	gd->ram_size = get_ram_size(
+			(void *)CONFIG_SYS_SDRAM_BASE,
+			CONFIG_MAX_RAM_BANK_SIZE);
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].size = gd->ram_size;
+}
+
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#ifdef CONFIG_TI81XX
+static struct dmm_lisa_map_regs *hw_lisa_map_regs =
+				(struct dmm_lisa_map_regs *)DMM_BASE;
+#endif
+#ifndef CONFIG_TI816X
+static struct vtp_reg *vtpreg[2] = {
+				(struct vtp_reg *)VTP0_CTRL_ADDR,
+				(struct vtp_reg *)VTP1_CTRL_ADDR};
+#endif
+#ifdef CONFIG_AM33XX
+static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
+#endif
+#ifdef CONFIG_AM43XX
+static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
+static struct cm_device_inst *cm_device =
+				(struct cm_device_inst *)CM_DEVICE_INST;
+#endif
+
+#ifdef CONFIG_TI81XX
+void config_dmm(const struct dmm_lisa_map_regs *regs)
+{
+	enable_dmm_clocks();
+
+	writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
+	writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
+	writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
+	writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
+
+	writel(regs->dmm_lisa_map_3, &hw_lisa_map_regs->dmm_lisa_map_3);
+	writel(regs->dmm_lisa_map_2, &hw_lisa_map_regs->dmm_lisa_map_2);
+	writel(regs->dmm_lisa_map_1, &hw_lisa_map_regs->dmm_lisa_map_1);
+	writel(regs->dmm_lisa_map_0, &hw_lisa_map_regs->dmm_lisa_map_0);
+}
+#endif
+
+#ifndef CONFIG_TI816X
+static void config_vtp(int nr)
+{
+	writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_ENABLE,
+			&vtpreg[nr]->vtp0ctrlreg);
+	writel(readl(&vtpreg[nr]->vtp0ctrlreg) & (~VTP_CTRL_START_EN),
+			&vtpreg[nr]->vtp0ctrlreg);
+	writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_START_EN,
+			&vtpreg[nr]->vtp0ctrlreg);
+
+	/* Poll for READY */
+	while ((readl(&vtpreg[nr]->vtp0ctrlreg) & VTP_CTRL_READY) !=
+			VTP_CTRL_READY)
+		;
+}
+#endif
+
+void __weak ddr_pll_config(unsigned int ddrpll_m)
+{
+}
+
+void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
+		const struct ddr_data *data, const struct cmd_control *ctrl,
+		const struct emif_regs *regs, int nr)
+{
+	ddr_pll_config(pll);
+#ifndef CONFIG_TI816X
+	config_vtp(nr);
+#endif
+	config_cmd_ctrl(ctrl, nr);
+
+	config_ddr_data(data, nr);
+#ifdef CONFIG_AM33XX
+	config_io_ctrl(ioregs);
+
+	/* Set CKE to be controlled by EMIF/DDR PHY */
+	writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
+
+#endif
+#ifdef CONFIG_AM43XX
+	writel(readl(&cm_device->cm_dll_ctrl) & ~0x1, &cm_device->cm_dll_ctrl);
+	while ((readl(&cm_device->cm_dll_ctrl) & CM_DLL_READYST) == 0)
+		;
+
+	config_io_ctrl(ioregs);
+
+	/* Set CKE to be controlled by EMIF/DDR PHY */
+	writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
+
+	if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3)
+		/* Allow EMIF to control DDR_RESET */
+		writel(0x00000000, &ddrctrl->ddrioctrl);
+#endif
+
+	/* Program EMIF instance */
+	config_ddr_phy(regs, nr);
+	set_sdram_timings(regs, nr);
+	if (get_emif_rev(EMIF1_BASE) == EMIF_4D5)
+		config_sdram_emif4d5(regs, nr);
+	else
+		config_sdram(regs, nr);
+}
+#endif
--- a/arch/arm/cpu/armv7/am33xx/mux.c
+++ b/arch/arm/cpu/armv7/am33xx/mux.c
@@ -0,0 +1,33 @@
+/*
+ * mux.c
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+
+/*
+ * Configure the pin mux for the module
+ */
+void configure_module_pin_mux(struct module_pin_mux *mod_pin_mux)
+{
+	int i;
+
+	if (!mod_pin_mux)
+		return;
+
+	for (i = 0; mod_pin_mux[i].reg_offset != -1; i++)
+		MUX_CFG(mod_pin_mux[i].val, mod_pin_mux[i].reg_offset);
+}
--- a/arch/arm/cpu/armv7/am33xx/sys_info.c
+++ b/arch/arm/cpu/armv7/am33xx/sys_info.c
@@ -0,0 +1,175 @@
+/*
+ * sys_info.c
+ *
+ * System information functions
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * Derived from Beagle Board and 3430 SDP code by
+ *      Richard Woodruff <r-woodruff2@ti.com>
+ *      Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clock.h>
+#include <power/tps65910.h>
+#include <linux/compiler.h>
+
+struct ctrl_stat *cstat = (struct ctrl_stat *)CTRL_BASE;
+
+/**
+ * get_cpu_rev(void) - extract rev info
+ */
+u32 get_cpu_rev(void)
+{
+	u32 id;
+	u32 rev;
+
+	id = readl(DEVICE_ID);
+	rev = (id >> 28) & 0xff;
+
+	return rev;
+}
+
+/**
+ * get_cpu_type(void) - extract cpu info
+ */
+u32 get_cpu_type(void)
+{
+	u32 id = 0;
+	u32 partnum;
+
+	id = readl(DEVICE_ID);
+	partnum = (id >> 12) & 0xffff;
+
+	return partnum;
+}
+
+/**
+ * get_device_type(): tell if GP/HS/EMU/TST
+ */
+u32 get_device_type(void)
+{
+	int mode;
+	mode = readl(&cstat->statusreg) & (DEVICE_MASK);
+	return mode >>= 8;
+}
+
+/**
+ * get_sysboot_value(void) - return SYS_BOOT[4:0]
+ */
+u32 get_sysboot_value(void)
+{
+	int mode;
+	mode = readl(&cstat->statusreg) & (SYSBOOT_MASK);
+	return mode;
+}
+
+#ifdef CONFIG_DISPLAY_CPUINFO
+static char *cpu_revs[] = {
+		"1.0",
+		"2.0",
+		"2.1"};
+
+
+static char *dev_types[] = {
+		"TST",
+		"EMU",
+		"HS",
+		"GP"};
+
+/**
+ * Print CPU information
+ */
+int print_cpuinfo(void)
+{
+	char *cpu_s, *sec_s, *rev_s;
+
+	switch (get_cpu_type()) {
+	case AM335X:
+		cpu_s = "AM335X";
+		break;
+	case TI81XX:
+		cpu_s = "TI81XX";
+		break;
+	default:
+		cpu_s = "Unknown CPU type";
+		break;
+	}
+
+	if (get_cpu_rev() < ARRAY_SIZE(cpu_revs))
+		rev_s = cpu_revs[get_cpu_rev()];
+	else
+		rev_s = "?";
+
+	if (get_device_type() < ARRAY_SIZE(dev_types))
+		sec_s = dev_types[get_device_type()];
+	else
+		sec_s = "?";
+
+	printf("%s-%s rev %s\n", cpu_s, sec_s, rev_s);
+
+	return 0;
+}
+#endif	/* CONFIG_DISPLAY_CPUINFO */
+
+#ifdef CONFIG_AM33XX
+int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev)
+{
+	int sil_rev;
+
+	sil_rev = readl(&cdev->deviceid) >> 28;
+
+	if (sil_rev == 1)
+		/* PG 2.0, efuse may not be set. */
+		return MPUPLL_M_800;
+	else if (sil_rev >= 2) {
+		/* Check what the efuse says our max speed is. */
+		int efuse_arm_mpu_max_freq;
+		efuse_arm_mpu_max_freq = readl(&cdev->efuse_sma);
+		switch ((efuse_arm_mpu_max_freq & DEVICE_ID_MASK)) {
+		case AM335X_ZCZ_1000:
+			return MPUPLL_M_1000;
+		case AM335X_ZCZ_800:
+			return MPUPLL_M_800;
+		case AM335X_ZCZ_720:
+			return MPUPLL_M_720;
+		case AM335X_ZCZ_600:
+		case AM335X_ZCE_600:
+			return MPUPLL_M_600;
+		case AM335X_ZCZ_300:
+		case AM335X_ZCE_300:
+			return MPUPLL_M_300;
+		}
+	}
+
+	/* PG 1.0 or otherwise unknown, use the PG1.0 max */
+	return MPUPLL_M_720;
+}
+
+int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency)
+{
+	/* For PG2.1 and later, we have one set of values. */
+	if (sil_rev >= 2) {
+		switch (frequency) {
+		case MPUPLL_M_1000:
+			return TPS65910_OP_REG_SEL_1_3_2_5;
+		case MPUPLL_M_800:
+			return TPS65910_OP_REG_SEL_1_2_6;
+		case MPUPLL_M_720:
+			return TPS65910_OP_REG_SEL_1_2_0;
+		case MPUPLL_M_600:
+		case MPUPLL_M_300:
+			return TPS65910_OP_REG_SEL_1_1_3;
+		}
+	}
+
+	/* Default to PG1.0/PG2.0 values. */
+	return TPS65910_OP_REG_SEL_1_1_3;
+}
+#endif
--- a/arch/arm/cpu/armv7/am33xx/u-boot-spl.lds
+++ b/arch/arm/cpu/armv7/am33xx/u-boot-spl.lds
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *	Aneesh V <aneesh@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
+		LENGTH = CONFIG_SPL_MAX_SIZE }
+MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
+		LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	.text      :
+	{
+		__start = .;
+		*(.vectors)
+		arch/arm/cpu/armv7/start.o	(.text)
+		*(.text*)
+	} >.sram
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
+
+	. = ALIGN(4);
+	.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
+
+	.u_boot_list : {
+		KEEP(*(SORT(.u_boot_list*)));
+	} >.sram
+
+	. = ALIGN(4);
+	__image_copy_end = .;
+
+	.end :
+	{
+		*(.__end)
+	} >.sram
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start = .;
+		*(.bss*)
+		. = ALIGN(4);
+		__bss_end = .;
+	} >.sdram
+}
--- a/arch/arm/cpu/armv7/arch_timer.c
+++ b/arch/arm/cpu/armv7/arch_timer.c
@@ -8,7 +8,6 @@
 #include <common.h>
 #include <asm/io.h>
 #include <div64.h>
-#include <bootstage.h>

 DECLARE_GLOBAL_DATA_PTR;

@@ -18,6 +17,7 @@ int timer_init(void)
 	gd->arch.tbu = 0;

 	gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ;
+
 	return 0;
 }

@@ -39,11 +39,6 @@ ulong get_timer(ulong base)
 	return lldiv(get_ticks(), gd->arch.timer_rate_hz) - base;
 }

-ulong timer_get_boot_us(void)
-{
-	return lldiv(get_ticks(), CONFIG_SYS_HZ_CLOCK / (CONFIG_SYS_HZ * 1000));
-}
-
 void __udelay(unsigned long usec)
 {
 	unsigned long long endtime;
--- a/arch/arm/cpu/armv7/bcm235xx/clk-bcm235xx.c
+++ b/arch/arm/cpu/armv7/bcm235xx/clk-bcm235xx.c
@@ -12,7 +12,7 @@

 #include <common.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/sysmap.h>
 #include <asm/kona-common/clk.h>
 #include "clk-core.h"
--- a/arch/arm/cpu/armv7/bcm235xx/clk-bsc.c
+++ b/arch/arm/cpu/armv7/bcm235xx/clk-bsc.c
@@ -6,7 +6,7 @@

 #include <common.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/sysmap.h>
 #include <asm/kona-common/clk.h>
 #include "clk-core.h"
--- a/arch/arm/cpu/armv7/bcm235xx/clk-core.c
+++ b/arch/arm/cpu/armv7/bcm235xx/clk-core.c
@@ -12,7 +12,7 @@

 #include <common.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <bitfield.h>
 #include <asm/arch/sysmap.h>
 #include <asm/kona-common/clk.h>
@@ -479,9 +479,9 @@ unsigned long clk_get_rate(struct clk *c)
 {
 	unsigned long rate;

+	debug("%s: %s\n", __func__, c->name);
 	if (!c || !c->ops || !c->ops->get_rate)
 		return 0;
-	debug("%s: %s\n", __func__, c->name);

 	rate = c->ops->get_rate(c);
 	debug("%s: rate = %ld\n", __func__, rate);
@@ -493,9 +493,9 @@ int clk_set_rate(struct clk *c, unsigned long rate)
 {
 	int ret;

+	debug("%s: %s rate=%ld\n", __func__, c->name, rate);
 	if (!c || !c->ops || !c->ops->set_rate)
 		return -EINVAL;
-	debug("%s: %s rate=%ld\n", __func__, c->name, rate);

 	if (c->use_cnt)
 		return -EINVAL;
--- a/arch/arm/cpu/armv7/bcm235xx/clk-eth.c
+++ b/arch/arm/cpu/armv7/bcm235xx/clk-eth.c
@@ -6,7 +6,7 @@

 #include <common.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/sysmap.h>
 #include <asm/kona-common/clk.h>
 #include "clk-core.h"
--- a/Show More
+++ b/Show More