Prepare v2020.10

Signed-off-by: Tom Rini <trini@konsulko.com>

Makefile

@@ -3,7 +3,7 @@
 VERSION = 2020
 PATCHLEVEL = 10
 SUBLEVEL =
-EXTRAVERSION = -rc5
+EXTRAVERSION =
 NAME =
 
 # *DOCUMENTATION*

README

@@ -266,7 +266,7 @@ board_init_f():
 		version as needed.
 	- preloader_console_init() can be called here in extremis
 	- should set up SDRAM, and anything needed to make the UART work
-	- these is no need to clear BSS, it will be done by crt0.S
+	- there is no need to clear BSS, it will be done by crt0.S
 	- for specific scenarios on certain architectures an early BSS *can*
 	  be made available (via CONFIG_SPL_EARLY_BSS by moving the clearing
 	  of BSS prior to entering board_init_f()) but doing so is discouraged.

arch/arm/cpu/armv8/fsl-layerscape/cpu.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2017-2019 NXP
+ * Copyright 2017-2020 NXP
  * Copyright 2014-2015 Freescale Semiconductor, Inc.
  */
 
@@ -1229,13 +1229,15 @@ __efi_runtime_data u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR;
 
 void __efi_runtime reset_cpu(ulong addr)
 {
+#ifdef CONFIG_ARCH_LX2160A
+	/* clear the RST_REQ_MSK and SW_RST_REQ */
+	out_le32(rstcr, 0x0);
+
+	/* initiate the sw reset request */
+	out_le32(rstcr, 0x1);
+#else
 	u32 val;
 
-#ifdef CONFIG_ARCH_LX2160A
-	val = in_le32(rstcr);
-	val |= 0x01;
-	out_le32(rstcr, val);
-#else
 	/* Raise RESET_REQ_B */
 	val = scfg_in32(rstcr);
 	val |= 0x02;

arch/arm/cpu/armv8/fsl-layerscape/soc.c

@@ -36,6 +36,8 @@
 #ifdef CONFIG_TFABOOT
 #include <env_internal.h>
 #endif
+#include <dm.h>
+#include <linux/err.h>
 #if defined(CONFIG_TFABOOT) || defined(CONFIG_GIC_V3_ITS)
 DECLARE_GLOBAL_DATA_PTR;
 #endif
@@ -43,7 +45,22 @@ DECLARE_GLOBAL_DATA_PTR;
 #ifdef CONFIG_GIC_V3_ITS
 int ls_gic_rd_tables_init(void *blob)
 {
-	int ret;
+	struct fdt_memory lpi_base;
+	fdt_addr_t addr;
+	fdt_size_t size;
+	int offset, ret;
+
+	offset = fdt_path_offset(gd->fdt_blob, "/syscon@0x80000000");
+	addr = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, offset, "reg",
+						  0, &size, false);
+
+	lpi_base.start = addr;
+	lpi_base.end = addr + size - 1;
+	ret = fdtdec_add_reserved_memory(blob, "lpi_rd_table", &lpi_base, NULL);
+	if (ret) {
+		debug("%s: failed to add reserved memory\n", __func__);
+		return ret;
+	}
 
 	ret = gic_lpi_tables_init();
 	if (ret)
@@ -897,6 +914,38 @@ __weak int fsl_board_late_init(void)
 	return 0;
 }
 
+#define DWC3_GSBUSCFG0			0xc100
+#define DWC3_GSBUSCFG0_CACHETYPE_SHIFT	16
+#define DWC3_GSBUSCFG0_CACHETYPE(n)        (((n) & 0xffff)            \
+	<< DWC3_GSBUSCFG0_CACHETYPE_SHIFT)
+
+void enable_dwc3_snooping(void)
+{
+	int ret;
+	u32 val;
+	struct udevice *bus;
+	struct uclass *uc;
+	fdt_addr_t dwc3_base;
+
+	ret = uclass_get(UCLASS_USB, &uc);
+	if (ret)
+		return;
+
+	uclass_foreach_dev(bus, uc) {
+		if (!strcmp(bus->driver->of_match->compatible, "fsl,layerscape-dwc3")) {
+			dwc3_base = devfdt_get_addr(bus);
+			if (dwc3_base == FDT_ADDR_T_NONE) {
+				dev_err(bus, "dwc3 regs missing\n");
+				continue;
+			}
+			val = in_le32(dwc3_base + DWC3_GSBUSCFG0);
+			val &= ~DWC3_GSBUSCFG0_CACHETYPE(~0);
+			val |= DWC3_GSBUSCFG0_CACHETYPE(0x2222);
+			writel(val, dwc3_base + DWC3_GSBUSCFG0);
+		}
+	}
+}
+
 int board_late_init(void)
 {
 #ifdef CONFIG_CHAIN_OF_TRUST
@@ -934,6 +983,9 @@ int board_late_init(void)
 	fspi_ahb_init();
 #endif
 
+	if (IS_ENABLED(CONFIG_DM))
+		enable_dwc3_snooping();
+
 	return fsl_board_late_init();
 }
 #endif

arch/arm/dts/fsl-ls1028a.dtsi

@@ -44,6 +44,12 @@
 					 IRQ_TYPE_LEVEL_LOW)>;
 	};
 
+	gic_lpi_base: syscon@0x80000000 {
+		compatible = "gic-lpi-base";
+		reg = <0x0 0x80000000 0x0 0x100000>;
+		max-gic-redistributors = <2>;
+	};
+
 	timer {
 		compatible = "arm,armv8-timer";
 		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |

arch/arm/dts/fsl-ls1088a.dtsi

@@ -26,6 +26,12 @@
 		interrupts = <1 9 0x4>;
 	};
 
+	gic_lpi_base: syscon@0x80000000 {
+		compatible = "gic-lpi-base";
+		reg = <0x0 0x80000000 0x0 0x100000>;
+		max-gic-redistributors = <8>;
+	};
+
 	timer {
 		compatible = "arm,armv8-timer";
 		interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */

arch/arm/dts/fsl-ls2080a.dtsi

@@ -26,6 +26,12 @@
 		interrupts = <1 9 0x4>;
 	};
 
+	gic_lpi_base: syscon@0x80000000 {
+		compatible = "gic-lpi-base";
+		reg = <0x0 0x80000000 0x0 0x100000>;
+		max-gic-redistributors = <8>;
+	};
+
 	timer {
 		compatible = "arm,armv8-timer";
 		interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */

arch/arm/dts/fsl-lx2160a.dtsi

@@ -43,6 +43,12 @@
 		interrupts = <1 9 0x4>;
 	};
 
+	gic_lpi_base: syscon@0x80000000 {
+		compatible = "gic-lpi-base";
+		reg = <0x0 0x80000000 0x0 0x200000>;
+		max-gic-redistributors = <16>;
+	};
+
 	timer {
 		compatible = "arm,armv8-timer";
 		interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
@@ -193,6 +199,28 @@
 		num-cs = <6>;
 	};
 
+	gpio0: gpio@2300000 {
+		compatible = "fsl,qoriq-gpio";
+		reg = <0x0 0x2300000 0x0 0x10000>;
+		interrupts = <0 36 4>;
+		gpio-controller;
+		little-endian;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpio1: gpio@2310000 {
+		compatible = "fsl,qoriq-gpio";
+		reg = <0x0 0x2310000 0x0 0x10000>;
+		interrupts = <0 36 4>;
+		gpio-controller;
+		little-endian;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
 	gpio2: gpio@2320000 {
 		compatible = "fsl,qoriq-gpio";
 		reg = <0x0 0x2320000 0x0 0x10000>;
@@ -204,6 +232,17 @@
 		#interrupt-cells = <2>;
 	};
 
+	gpio3: gpio@2330000 {
+		compatible = "fsl,qoriq-gpio";
+		reg = <0x0 0x2330000 0x0 0x10000>;
+		interrupts = <0 37 4>;
+		gpio-controller;
+		little-endian;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
 	watchdog@23a0000 {
 		compatible = "arm,sbsa-gwdt";
 		reg = <0x0 0x23a0000 0 0x1000>,
@@ -297,7 +336,8 @@
 		#size-cells = <2>;
 		device_type = "pci";
 		bus-range = <0x0 0xff>;
-		ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>;
+		ranges = <0x81000000 0x0 0x00000000 0x80 0x00020000 0x0 0x00010000   /* downstream I/O */
+			  0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 	};
 
 	pcie@3500000 {
@@ -312,7 +352,8 @@
 		device_type = "pci";
 		num-lanes = <2>;
 		bus-range = <0x0 0xff>;
-		ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>;
+		ranges = <0x81000000 0x0 0x00000000 0x88 0x00020000 0x0 0x00010000   /* downstream I/O */
+			  0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 	};
 
 	pcie@3600000 {
@@ -326,7 +367,8 @@
 		#size-cells = <2>;
 		device_type = "pci";
 		bus-range = <0x0 0xff>;
-		ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>;
+		ranges = <0x81000000 0x0 0x00000000 0x90 0x00020000 0x0 0x00010000   /* downstream I/O */
+			  0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 	};
 
 	pcie@3700000 {
@@ -340,7 +382,8 @@
 		#size-cells = <2>;
 		device_type = "pci";
 		bus-range = <0x0 0xff>;
-		ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>;
+		ranges = <0x81000000 0x0 0x00000000 0x98 0x00020000 0x0 0x00010000   /* downstream I/O */
+			  0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 	};
 
 	pcie@3800000 {
@@ -354,7 +397,8 @@
 		#size-cells = <2>;
 		device_type = "pci";
 		bus-range = <0x0 0xff>;
-		ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>;
+		ranges = <0x81000000 0x0 0x00000000 0xa0 0x00020000 0x0 0x00010000   /* downstream I/O */
+			  0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 	};
 
 	pcie@3900000 {
@@ -368,7 +412,8 @@
 		#size-cells = <2>;
 		device_type = "pci";
 		bus-range = <0x0 0xff>;
-		ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>;
+		ranges = <0x81000000 0x0 0x00000000 0xa8 0x00020000 0x0 0x00010000   /* downstream I/O */
+			  0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 	};
 
 	fsl_mc: fsl-mc@80c000000 {

arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi

@@ -21,6 +21,10 @@
 	};
 };
 
+&flash0 {
+	u-boot,dm-spl;
+};
+
 &gpiof {
 	snor-nwp {
 		gpio-hog;
@@ -49,6 +53,23 @@
 	u-boot,dm-spl;
 };
 
+&qspi_clk_pins_a {
+	u-boot,dm-spl;
+	pins {
+		u-boot,dm-spl;
+	};
+};
+
+&qspi_bk1_pins_a {
+	u-boot,dm-spl;
+	pins1 {
+		u-boot,dm-spl;
+	};
+	pins2 {
+		u-boot,dm-spl;
+	};
+};
+
 &rcc {
 	st,clksrc = <
 		CLK_MPU_PLL1P

arch/mips/dts/pic32mzda.dtsi

@@ -26,8 +26,13 @@
 	};
 
 	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
 		cpu@0 {
 			compatible = "mips,mips14kc";
+			device-type = "cpu";
+			reg = <0>;
 		};
 	};
 
@@ -40,6 +45,7 @@
 	uart1: serial@1f822000 {
 		compatible = "microchip,pic32mzda-uart";
 		reg = <0x1f822000 0x50>;
+		interrupt-parent = <&evic>;
 		interrupts = <112 IRQ_TYPE_LEVEL_HIGH>;
 		status = "disabled";
 		clocks = <&clock PB2CLK>;
@@ -48,6 +54,7 @@
 	uart2: serial@1f822200 {
 		compatible = "microchip,pic32mzda-uart";
 		reg = <0x1f822200 0x50>;
+		interrupt-parent = <&evic>;
 		interrupts = <145 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&clock PB2CLK>;
 		status = "disabled";
@@ -56,6 +63,7 @@
 	uart6: serial@1f822a00 {
 		compatible = "microchip,pic32mzda-uart";
 		reg = <0x1f822a00 0x50>;
+		interrupt-parent = <&evic>;
 		interrupts = <188 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&clock PB2CLK>;
 		status = "disabled";
@@ -69,6 +77,8 @@
 	};
 
 	pinctrl: pinctrl@1f801400 {
+		#address-cells = <1>;
+		#size-cells = <1>;
 		compatible = "microchip,pic32mzda-pinctrl";
 		reg = <0x1f801400 0x100>, /* in  */
 		      <0x1f801500 0x200>, /* out */
@@ -76,75 +86,72 @@
 		reg-names = "ppsin","ppsout","port";
 		status = "disabled";
 
-		ranges = <0 0x1f860000 0xa00>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-		gpioA: gpio0@0 {
+		gpioA: gpio0@1f860000 {
 			compatible = "microchip,pic32mzda-gpio";
-			reg = <0x000 0x48>;
+			reg = <0x1f860000 0xe0>;
 			gpio-controller;
 			#gpio-cells = <2>;
 		};
 
-		gpioB: gpio1@100 {
+		gpioB: gpio1@1f860100 {
 			compatible = "microchip,pic32mzda-gpio";
-			reg = <0x100 0x48>;
+			reg = <0x1f860100 0xe0>;
 			gpio-controller;
 			#gpio-cells = <2>;
 		};
 
-		gpioC: gpio2@200 {
+		gpioC: gpio2@1f860200 {
 			compatible = "microchip,pic32mzda-gpio";
-			reg = <0x200 0x48>;
+			reg = <0x1f860200 0xe0>;
 			gpio-controller;
 			#gpio-cells = <2>;
 		};
 
-		gpioD: gpio3@300 {
+		gpioD: gpio3@1f860300 {
 			compatible = "microchip,pic32mzda-gpio";
-			reg = <0x300 0x48>;
+			reg = <0x1f860300 0xe0>;
 			gpio-controller;
 			#gpio-cells = <2>;
 		};
 
-		gpioE: gpio4@400 {
+		gpioE: gpio4@1f860400 {
 			compatible = "microchip,pic32mzda-gpio";
-			reg = <0x400 0x48>;
+			reg = <0x1f860400 0xe0>;
 			gpio-controller;
 			#gpio-cells = <2>;
 		};
 
-		gpioF: gpio5@500 {
+		gpioF: gpio5@1f860500 {
 			compatible = "microchip,pic32mzda-gpio";
-			reg = <0x500 0x48>;
+			reg = <0x1f860500 0xe0>;
 			gpio-controller;
 			#gpio-cells = <2>;
 		};
 
-		gpioG: gpio6@600 {
+		gpioG: gpio6@1f860600 {
 			compatible = "microchip,pic32mzda-gpio";
-			reg = <0x600 0x48>;
+			reg = <0x1f860600 0xe0>;
 			gpio-controller;
 			#gpio-cells = <2>;
 		};
 
-		gpioH: gpio7@700 {
+		gpioH: gpio7@1f860700 {
 			compatible = "microchip,pic32mzda-gpio";
-			reg = <0x700 0x48>;
+			reg = <0x1f860700 0xe0>;
 			gpio-controller;
 			#gpio-cells = <2>;
 		};
 
-		gpioJ: gpio8@800 {
+		gpioJ: gpio9@1f860800 {
 			compatible = "microchip,pic32mzda-gpio";
-			reg = <0x800 0x48>;
+			reg = <0x1f860800 0xe0>;
 			gpio-controller;
 			#gpio-cells = <2>;
 		};
 
-		gpioK: gpio9@900 {
+		gpioK: gpio10@1f860900 {
 			compatible = "microchip,pic32mzda-gpio";
-			reg = <0x900 0x48>;
+			reg = <0x1f860900 0xe0>;
 			gpio-controller;
 			#gpio-cells = <2>;
 		};
@@ -153,6 +160,7 @@
 	sdhci: sdhci@1f8ec000 {
 		compatible = "microchip,pic32mzda-sdhci";
 		reg = <0x1f8ec000 0x100>;
+		interrupt-parent = <&evic>;
 		interrupts = <191 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&clock REF4CLK>, <&clock PB5CLK>;
 		clock-names = "base_clk", "sys_clk";
@@ -164,6 +172,7 @@
 	ethernet: ethernet@1f882000 {
 		compatible = "microchip,pic32mzda-eth";
 		reg = <0x1f882000 0x1000>;
+		interrupt-parent = <&evic>;
 		interrupts = <153 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&clock PB5CLK>;
 		status = "disabled";
@@ -176,6 +185,7 @@
 		reg = <0x1f8e3000 0x1000>,
 		      <0x1f884000 0x1000>;
 		reg-names = "mc", "control";
+		interrupt-parent = <&evic>;
 		interrupts = <132 IRQ_TYPE_EDGE_RISING>,
 			     <133 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&clock PB5CLK>;

arch/mips/dts/pic32mzda_sk.dts

@@ -40,6 +40,7 @@
 };
 
 &sdhci {
+	microchip,use-sdcd;
 	status = "okay";
 };
 

arch/mips/dts/vocore_vocore2.dts

@@ -59,7 +59,7 @@
 		#address-cells = <1>;
 		#size-cells = <1>;
 		compatible = "jedec,spi-nor";
-		spi-max-frequency = <25000000>;
+		spi-max-frequency = <40000000>;
 		reg = <0>;
 	};
 };

arch/riscv/lib/interrupts.c

@@ -111,6 +111,9 @@ ulong handle_trap(ulong cause, ulong epc, ulong tval, struct pt_regs *regs)
 {
 	ulong is_irq, irq;
 
+	/* An UEFI application may have changed gd. Restore U-Boot's gd. */
+	efi_restore_gd();
+
 	is_irq = (cause & MCAUSE_INT);
 	irq = (cause & ~MCAUSE_INT);
 

board/Marvell/mvebu_armada-37xx/board.c

@@ -5,6 +5,7 @@
 
 #include <common.h>
 #include <dm.h>
+#include <env.h>
 #include <i2c.h>
 #include <init.h>
 #include <phy.h>
@@ -50,6 +51,22 @@ DECLARE_GLOBAL_DATA_PTR;
 #define MVEBU_G2_SMI_PHY_CMD_REG	(24)
 #define MVEBU_G2_SMI_PHY_DATA_REG	(25)
 
+/*
+ * Memory Controller Registers
+ *
+ * Assembled based on public information:
+ * https://gitlab.nic.cz/turris/mox-boot-builder/-/blob/master/wtmi/main.c#L332-336
+ * https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/blob/mv_ddr-armada-18.12/drivers/mv_ddr_mc6.h#L309-L332
+ *
+ * And checked against the written register values for the various topologies:
+ * https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/blob/mv_ddr-armada-atf-mainline/a3700/mv_ddr_tim.h
+ */
+#define A3700_CH0_MC_CTRL2_REG		MVEBU_REGISTER(0x002c4)
+#define A3700_MC_CTRL2_SDRAM_TYPE_MASK	0xf
+#define A3700_MC_CTRL2_SDRAM_TYPE_OFFS	4
+#define A3700_MC_CTRL2_SDRAM_TYPE_DDR3	2
+#define A3700_MC_CTRL2_SDRAM_TYPE_DDR4	3
+
 int board_early_init_f(void)
 {
 	return 0;
@@ -63,6 +80,36 @@ int board_init(void)
 	return 0;
 }
 
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+	bool ddr4, emmc;
+
+	if (env_get("fdtfile"))
+		return 0;
+
+	if (!of_machine_is_compatible("marvell,armada-3720-espressobin"))
+		return 0;
+
+	/* If the memory controller has been configured for DDR4, we're running on v7 */
+	ddr4 = ((readl(A3700_CH0_MC_CTRL2_REG) >> A3700_MC_CTRL2_SDRAM_TYPE_OFFS)
+		& A3700_MC_CTRL2_SDRAM_TYPE_MASK) == A3700_MC_CTRL2_SDRAM_TYPE_DDR4;
+
+	emmc = of_machine_is_compatible("marvell,armada-3720-espressobin-emmc");
+
+	if (ddr4 && emmc)
+		env_set("fdtfile", "marvell/armada-3720-espressobin-v7-emmc.dtb");
+	else if (ddr4)
+		env_set("fdtfile", "marvell/armada-3720-espressobin-v7.dtb");
+	else if (emmc)
+		env_set("fdtfile", "marvell/armada-3720-espressobin-emmc.dtb");
+	else
+		env_set("fdtfile", "marvell/armada-3720-espressobin.dtb");
+
+	return 0;
+}
+#endif
+
 /* Board specific AHCI / SATA enable code */
 int board_ahci_enable(void)
 {

board/freescale/common/emc2305.c

@@ -1,8 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2018 NXP.
+ * Copyright 2018-2020 NXP.
  *
- * SPDX-License-Identifier:     GPL-2.0+
  */
 
 #include <common.h>
@@ -14,7 +13,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-void set_fan_speed(u8 data)
+void set_fan_speed(u8 data, int chip_addr)
 {
 	u8 index;
 	u8 Fan[NUM_OF_FANS] = {I2C_EMC2305_FAN1,
@@ -25,14 +24,14 @@ void set_fan_speed(u8 data)
 
 	for (index = 0; index < NUM_OF_FANS; index++) {
 #ifndef CONFIG_DM_I2C
-		if (i2c_write(I2C_EMC2305_ADDR, Fan[index], 1, &data, 1) != 0) {
+		if (i2c_write(chip_addr, Fan[index], 1, &data, 1) != 0) {
 			printf("Error: failed to change fan speed @%x\n",
 			       Fan[index]);
 		}
 #else
 		struct udevice *dev;
 
-		if (i2c_get_chip_for_busnum(0, I2C_EMC2305_ADDR, 1, &dev))
+		if (i2c_get_chip_for_busnum(0, chip_addr, 1, &dev))
 			continue;
 
 		if (dm_i2c_write(dev, Fan[index], &data, 1) != 0) {
@@ -43,18 +42,18 @@ void set_fan_speed(u8 data)
 	}
 }
 
-void emc2305_init(void)
+void emc2305_init(int chip_addr)
 {
 	u8 data;
 
 	data = I2C_EMC2305_CMD;
 #ifndef CONFIG_DM_I2C
-	if (i2c_write(I2C_EMC2305_ADDR, I2C_EMC2305_CONF, 1, &data, 1) != 0)
+	if (i2c_write(chip_addr, I2C_EMC2305_CONF, 1, &data, 1) != 0)
 		printf("Error: failed to configure EMC2305\n");
 #else
 	struct udevice *dev;
 
-	if (!i2c_get_chip_for_busnum(0, I2C_EMC2305_ADDR, 1, &dev))
+	if (!i2c_get_chip_for_busnum(0, chip_addr, 1, &dev))
 		if (dm_i2c_write(dev, I2C_EMC2305_CONF, &data, 1))
 			printf("Error: failed to configure EMC2305\n");
 #endif

board/freescale/common/emc2305.h

@@ -1,8 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Copyright 2018 NXP
+ * Copyright 2018-2020 NXP
  *
- * SPDX-License-Identifier:     GPL-2.0+
  */
 
 #ifndef __EMC2305_H_
@@ -17,7 +16,7 @@
 
 #define NUM_OF_FANS			5
 
-void emc2305_init(void);
-void set_fan_speed(u8 data);
+void emc2305_init(int chip_addr);
+void set_fan_speed(u8 data, int chip_addr);
 
 #endif  /* __EMC2305_H_ */

board/freescale/common/vid.c

@@ -533,14 +533,14 @@ int adjust_vdd(ulong vdd_override)
 		0,      /* reserved */
 		0,      /* reserved */
 		0,      /* reserved */
-		0,      /* reserved */
-		0,      /* reserved */
-		0,      /* reserved */
 		9000,      /* reserved */
 		0,      /* reserved */
 		0,      /* reserved */
 		0,      /* reserved */
 		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
 		10000,  /* 1.0000V */
 		0,      /* reserved */
 		10250,

board/freescale/lx2160a/lx2160a.c

@@ -114,8 +114,8 @@ int board_early_init_f(void)
 
 #ifdef CONFIG_EMC2305
 	select_i2c_ch_pca9547(I2C_MUX_CH_EMC2305);
-	emc2305_init();
-	set_fan_speed(I2C_EMC2305_PWM);
+	emc2305_init(I2C_EMC2305_ADDR);
+	set_fan_speed(I2C_EMC2305_PWM, I2C_EMC2305_ADDR);
 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 #endif
 

board/renesas/ebisu/ebisu.c

@@ -47,23 +47,10 @@ int board_init(void)
 }
 
 #define RST_BASE	0xE6160000
-#define RST_CA57RESCNT	(RST_BASE + 0x40)
 #define RST_CA53RESCNT	(RST_BASE + 0x44)
-#define RST_RSTOUTCR	(RST_BASE + 0x58)
-#define RST_CA57_CODE	0xA5A5000F
 #define RST_CA53_CODE	0x5A5A000F
 
 void reset_cpu(ulong addr)
 {
-	unsigned long midr, cputype;
-
-	asm volatile("mrs %0, midr_el1" : "=r" (midr));
-	cputype = (midr >> 4) & 0xfff;
-
-	if (cputype == 0xd03)
-		writel(RST_CA53_CODE, RST_CA53RESCNT);
-	else if (cputype == 0xd07)
-		writel(RST_CA57_CODE, RST_CA57RESCNT);
-	else
-		hang();
+	writel(RST_CA53_CODE, RST_CA53RESCNT);
 }

board/solidrun/clearfog/clearfog.c

@@ -240,6 +240,9 @@ int board_eth_init(struct bd_info *bis)
 
 int board_late_init(void)
 {
+	if (env_get("fdtfile"))
+		return 0;
+
 	cf_read_tlv_data();
 
 	if (sr_product_is(&cf_tlv_data, "Clearfog Base"))

cmd/efidebug.c

@@ -9,6 +9,7 @@
 #include <common.h>
 #include <command.h>
 #include <efi_loader.h>
+#include <efi_rng.h>
 #include <exports.h>
 #include <hexdump.h>
 #include <log.h>
@@ -248,6 +249,10 @@ static const struct {
 		"Load File2",
 		EFI_LOAD_FILE2_PROTOCOL_GUID,
 	},
+	{
+		"Random Number Generator",
+		EFI_RNG_PROTOCOL_GUID,
+	},
 	{
 		"Simple Network",
 		EFI_SIMPLE_NETWORK_PROTOCOL_GUID,

common/Kconfig

@@ -403,7 +403,6 @@ config BOOTCOMMAND
 
 config USE_PREBOOT
 	bool "Enable preboot"
-	default "usb start" if USB_KEYBOARD
 	help
 	  When this option is enabled, the existence of the environment
 	  variable "preboot" will be checked immediately before starting the
@@ -417,6 +416,7 @@ config USE_PREBOOT
 config PREBOOT
 	string "preboot default value"
 	depends on USE_PREBOOT && !USE_DEFAULT_ENV_FILE
+	default "usb start" if USB_KEYBOARD || USB_STORAGE
 	default ""
 	help
 	  This is the default of "preboot" environment variable.

common/image-fdt.c

@@ -557,6 +557,14 @@ int image_setup_libfdt(bootm_headers_t *images, void *blob,
 		printf("ERROR: arch-specific fdt fixup failed\n");
 		goto err;
 	}
+
+	fdt_ret = optee_copy_fdt_nodes(gd->fdt_blob, blob);
+	if (fdt_ret) {
+		printf("ERROR: transfer of optee nodes to new fdt failed: %s\n",
+		       fdt_strerror(fdt_ret));
+		goto err;
+	}
+
 	/* Update ethernet nodes */
 	fdt_fixup_ethernet(blob);
 	if (IMAGE_OF_BOARD_SETUP) {
@@ -576,13 +584,6 @@ int image_setup_libfdt(bootm_headers_t *images, void *blob,
 		}
 	}
 
-	fdt_ret = optee_copy_fdt_nodes(gd->fdt_blob, blob);
-	if (fdt_ret) {
-		printf("ERROR: transfer of optee nodes to new fdt failed: %s\n",
-		       fdt_strerror(fdt_ret));
-		goto err;
-	}
-
 	/* Delete the old LMB reservation */
 	if (lmb)
 		lmb_free(lmb, (phys_addr_t)(u32)(uintptr_t)blob,

configs/T1023RDB_SPIFLASH_defconfig

@@ -50,7 +50,6 @@ CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000
 CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_ADDR=0xFFFC9000
 CONFIG_FSL_CAAM=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y

configs/T1024RDB_SPIFLASH_defconfig

@@ -53,7 +53,6 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),9
 CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_ADDR=0xFFFC9000
 CONFIG_DM=y
 CONFIG_FSL_CAAM=y
 CONFIG_SYS_FSL_DDR3=y

configs/T1040D4RDB_SPIFLASH_defconfig

@@ -47,7 +47,6 @@ CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000
 CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_ADDR=0xFFFC9000
 CONFIG_FSL_CAAM=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y

configs/T1040RDB_SPIFLASH_defconfig

@@ -47,7 +47,6 @@ CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000
 CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_ADDR=0xFFFC9000
 CONFIG_FSL_CAAM=y
 CONFIG_SYS_FSL_DDR3=y
 CONFIG_FSL_ESDHC=y

configs/T1042D4RDB_SPIFLASH_defconfig

@@ -50,7 +50,6 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),9
 CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_ADDR=0xFFFC9000
 CONFIG_DM=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y

configs/T1042RDB_PI_SPIFLASH_defconfig

@@ -49,7 +49,6 @@ CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000
 CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_ADDR=0xFFFC9000
 CONFIG_FSL_CAAM=y
 CONFIG_SYS_FSL_DDR3=y
 CONFIG_FSL_ESDHC=y

configs/T2080QDS_SPIFLASH_defconfig

@@ -46,7 +46,6 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),9
 CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_ADDR=0xFFFC9000
 CONFIG_DM=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y

configs/T2080RDB_SPIFLASH_defconfig

@@ -50,7 +50,6 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),9
 CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_ADDR=0xFFFC9000
 CONFIG_DM=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y

configs/T2081QDS_SPIFLASH_defconfig

@@ -44,7 +44,6 @@ CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000
 CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_ADDR=0xFFFC9000
 CONFIG_FSL_CAAM=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y

configs/dns325_defconfig

@@ -3,7 +3,7 @@ CONFIG_SYS_DCACHE_OFF=y
 CONFIG_ARCH_CPU_INIT=y
 CONFIG_ARCH_KIRKWOOD=y
 CONFIG_SYS_TEXT_BASE=0x600000
-CONFIG_NR_DRAM_BANKS=2
+CONFIG_NR_DRAM_BANKS=1
 CONFIG_TARGET_DNS325=y
 CONFIG_ENV_SIZE=0x20000
 CONFIG_ENV_OFFSET=0xE0000

configs/ls1012a2g5rdb_qspi_defconfig

@@ -34,6 +34,7 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_CACHE=y
 CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_NET_RANDOM_ETHADDR=y

configs/ls1012a2g5rdb_tfa_defconfig

@@ -34,6 +34,7 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_CACHE=y
 CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_NET_RANDOM_ETHADDR=y

configs/ls1012afrdm_qspi_defconfig

@@ -32,6 +32,7 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_CACHE=y
 CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_NET_RANDOM_ETHADDR=y

configs/ls1012afrdm_tfa_defconfig

@@ -32,6 +32,7 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_CACHE=y
 CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_NET_RANDOM_ETHADDR=y

configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig

@@ -32,6 +32,7 @@ CONFIG_CMD_PCI=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_CACHE=y
 CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM=y
 CONFIG_SATA_CEVA=y

configs/ls1012afrwy_qspi_defconfig

@@ -34,6 +34,7 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_CACHE=y
 CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_ENV_ADDR=0x401D0000
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y

configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig

@@ -32,6 +32,7 @@ CONFIG_CMD_PCI=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_CACHE=y
 CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM=y
 CONFIG_SATA_CEVA=y

configs/ls1012afrwy_tfa_defconfig

@@ -34,6 +34,7 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_CACHE=y
 CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_NET_RANDOM_ETHADDR=y

configs/ls1012aqds_qspi_defconfig

@@ -40,6 +40,7 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_CACHE=y
 CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_USE_ENV_SPI_BUS=y
 CONFIG_ENV_SPI_BUS=0

configs/ls1012aqds_tfa_SECURE_BOOT_defconfig

@@ -37,6 +37,7 @@ CONFIG_DEFAULT_SPI_BUS=1
 CONFIG_CMD_USB=y
 CONFIG_CMD_CACHE=y
 CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM=y

configs/ls1012aqds_tfa_defconfig

@@ -40,6 +40,7 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_CACHE=y
 CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_USE_ENV_SPI_BUS=y
 CONFIG_ENV_SPI_BUS=0

configs/ls1012ardb_qspi_SECURE_BOOT_defconfig

@@ -35,6 +35,7 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_CACHE=y
 CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM=y

configs/ls1012ardb_qspi_defconfig

@@ -35,6 +35,7 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_CACHE=y
 CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_ENV_ADDR=0x40300000
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y

configs/ls1012ardb_tfa_SECURE_BOOT_defconfig

@@ -34,6 +34,7 @@ CONFIG_CMD_PCI=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_CACHE=y
 CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM=y

configs/ls1012ardb_tfa_defconfig

@@ -35,6 +35,7 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_CACHE=y
 CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_NET_RANDOM_ETHADDR=y

configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig

@@ -26,6 +26,7 @@ CONFIG_CMD_CACHE=y
 CONFIG_MP=y
 CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.spi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
 CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
 CONFIG_SATA_CEVA=y

configs/ls1046afrwy_tfa_defconfig

@@ -29,6 +29,7 @@ CONFIG_CMD_CACHE=y
 CONFIG_MP=y
 CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.spi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
 CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_ENV_ADDR=0x40500000

configs/ls1046aqds_SECURE_BOOT_defconfig

@@ -33,6 +33,7 @@ CONFIG_CMD_CACHE=y
 CONFIG_MP=y
 CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)"
 CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
 CONFIG_DM=y
 CONFIG_SATA_CEVA=y
 CONFIG_DM_I2C=y

configs/ls1046aqds_defconfig

@@ -33,6 +33,7 @@ CONFIG_CMD_CACHE=y
 CONFIG_MP=y
 CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)"
 CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_ADDR=0x60300000
 CONFIG_DM=y

configs/ls1046aqds_lpuart_defconfig

@@ -34,6 +34,7 @@ CONFIG_CMD_CACHE=y
 CONFIG_MP=y
 CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)"
 CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_ADDR=0x60300000
 CONFIG_DM=y

configs/ls1046aqds_nand_defconfig

@@ -42,6 +42,7 @@ CONFIG_CMD_CACHE=y
 CONFIG_MP=y
 CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)"
 CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y

configs/ls1046aqds_qspi_defconfig

@@ -33,6 +33,7 @@ CONFIG_CMD_CACHE=y
 CONFIG_MP=y
 CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.spi-0:2m(uboot),14m(free)"
 CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_ENV_ADDR=0x40300000
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y

configs/ls1046aqds_sdcard_ifc_defconfig

@@ -51,6 +51,7 @@ CONFIG_MP=y
 CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)"
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y

configs/ls1046aqds_sdcard_qspi_defconfig

@@ -49,6 +49,7 @@ CONFIG_MP=y
 CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.spi-0:2m(uboot),14m(free)"
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y

configs/ls1046aqds_tfa_SECURE_BOOT_defconfig

@@ -35,6 +35,7 @@ CONFIG_CMD_CACHE=y
 CONFIG_MP=y
 CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)"
 CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
 CONFIG_DM=y
 CONFIG_SATA_CEVA=y
 CONFIG_DM_I2C=y

configs/ls1046aqds_tfa_defconfig

@@ -36,6 +36,7 @@ CONFIG_CMD_CACHE=y
 CONFIG_MP=y
 CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)"
 CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_ENV_IS_IN_NAND=y

configs/ls1046ardb_emmc_defconfig

@@ -45,6 +45,7 @@ CONFIG_MP=y
 CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y

configs/ls1046ardb_qspi_SECURE_BOOT_defconfig

@@ -28,6 +28,7 @@ CONFIG_CMD_CACHE=y
 CONFIG_MP=y
 CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
 CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
 CONFIG_SATA_CEVA=y

configs/ls1046ardb_qspi_defconfig

@@ -29,6 +29,7 @@ CONFIG_CMD_CACHE=y
 CONFIG_MP=y
 CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
 CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_ENV_ADDR=0x40300000
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y

configs/ls1046ardb_qspi_spl_defconfig

@@ -48,6 +48,7 @@ CONFIG_MP=y
 CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_SPL_ENV_IS_NOWHERE=y

configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig

@@ -44,6 +44,7 @@ CONFIG_MP=y
 CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
 CONFIG_SPL_DM=y

configs/ls1046ardb_sdcard_defconfig

@@ -44,6 +44,7 @@ CONFIG_MP=y
 CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y

configs/ls1046ardb_tfa_SECURE_BOOT_defconfig

@@ -29,6 +29,7 @@ CONFIG_CMD_CACHE=y
 CONFIG_MP=y
 CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
 CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
 CONFIG_DM=y
 CONFIG_SATA_CEVA=y
 CONFIG_DM_I2C=y

configs/ls1046ardb_tfa_defconfig

@@ -30,6 +30,7 @@ CONFIG_CMD_CACHE=y
 CONFIG_MP=y
 CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
 CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_ENV_ADDR=0x40500000

configs/mvebu_espressobin-88f3720_defconfig

@@ -84,3 +84,5 @@ CONFIG_USB_ETHER_RTL8152=y
 CONFIG_USB_ETHER_SMSC95XX=y
 CONFIG_SHA1=y
 CONFIG_SHA256=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_BOARD_LATE_INIT=y

configs/pic32mzdask_defconfig

@@ -27,7 +27,6 @@ CONFIG_CMD_EXT4_WRITE=y
 # CONFIG_EFI_PARTITION is not set
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_NET_RANDOM_ETHADDR=y
-# CONFIG_BLK is not set
 CONFIG_CLK=y
 CONFIG_MMC=y
 CONFIG_DM_MMC=y

configs/vocore2_defconfig

@@ -6,7 +6,7 @@ CONFIG_ENV_SIZE=0x1000
 CONFIG_ENV_OFFSET=0x04e000
 CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_SYS_BOOTCOUNT_ADDR=0xb000006c
-CONFIG_SPL_SYS_MALLOC_F_LEN=0x20000
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x40000
 CONFIG_SPL=y
 CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
 CONFIG_ARCH_MTMIPS=y

disk/part_efi.c

@@ -7,7 +7,7 @@
 /*
  * NOTE:
  *   when CONFIG_SYS_64BIT_LBA is not defined, lbaint_t is 32 bits; this
- *   limits the maximum size of addressable storage to < 2 Terra Bytes
+ *   limits the maximum size of addressable storage to < 2 tebibytes
  */
 #include <common.h>
 #include <blk.h>

doc/README.marvell

@@ -27,7 +27,7 @@ Build Procedure
 	- For the Armada-70x0/80x0 DB board use "mvebu_db_armada8k_defconfig"
 	- For the Armada-80x0 MacchiatoBin use "make mvebu_mcbin-88f8040_defconfig"
 	- For the Armada-3700 DB board use "make mvebu_db-88f3720_defconfig"
-	- For the Armada-3700 EsspressoBin use "make mvebu_espressobin-88f3720_defconfig"
+	- For the Armada-3700 EspressoBin use "make mvebu_espressobin-88f3720_defconfig"
 
 5. Configure the device-tree and build the U-Boot image:
 
@@ -62,11 +62,15 @@ Configuration update
 Permanent ethernet MAC address
 -------------------------------
 	Prior flashing new U-Boot version (as part of ATF image) it is suggested to backup
-	permanent ethernet MAC address as it is stored only in U-Boot env storage (SPI or eMMC).
-	Some boards like EspressoBin have MAC address printed on sticker. To print current MAC
-	address run:
+	permanent ethernet MAC addresses as they are stored only in U-Boot env storage (SPI or eMMC).
+	Some boards like EspressoBin have MAC addresses printed on sticker. Some boards got assigned
+	only one address other may also more than one. To print current MAC addresses run:
 
 		# echo $ethaddr
+		# echo $eth1addr
+		# echo $eth2addr
+		# echo $eth3addr
+		# ...
 
 	MAC addresses 00:51:82:11:22:00, 00:51:82:11:22:01, 00:51:82:11:22:02, 00:51:82:11:22:03
 	and F0:AD:4E:03:64:7F are default hardcoded values found in Marvell's and Armbian U-Boot
@@ -75,13 +79,20 @@ Permanent ethernet MAC address
 	suggested to generate new random one.
 
 	After flashing new U-Boot version it is suggested to reset U-Boot env variables to default
-	and then set correct permanent ethernet MAC address.
+	and then set correct permanent ethernet MAC addresses.
 
 		# env default -a
 		# setenv ethaddr XX:XX:XX:XX:XX:XX
+		# setenv eth1addr XX:XX:XX:XX:XX:XX
+		# setenv eth2addr YY:YY:YY:YY:YY:YY
+		# setenv eth3addr ZZ:ZZ:ZZ:ZZ:ZZ:ZZ
+		# ...
 		# saveenv
 
-	Where XX:XX:XX:XX:XX:XX is permanent ethernet MAC address.
+	Where value for ethaddr is required permanent ethernet MAC address and values for ethNaddr
+	are optional per-port MAC addresses. When optional ethNaddr variables are not defined then
+	they are inherited from required ethaddr variable. eth1addr contains MAC address for the
+	wan port, other for particular lan ports.
 
 	Recent Linux kernel versions use correct permanent ethernet MAC address from U-Boot env as
 	U-Boot will inject it into kernel's device-tree.

doc/build/gcc.rst

@@ -17,7 +17,7 @@ You could install GCC and the GCC cross compiler for the ARMv8 architecture with
 
 .. code-block:: bash
 
-    sudo apt-get gcc gcc-aarch64-linux-gnu
+    sudo apt-get install gcc gcc-aarch64-linux-gnu
 
 Depending on the build targets further packages maybe needed
 

drivers/gpio/mpc83xx_spisel_boot.c

@@ -6,6 +6,7 @@
  */
 
 #include <common.h>
+#include <log.h>
 #include <dm.h>
 #include <mapmem.h>
 #include <asm/gpio.h>

drivers/i2c/rcar_i2c.c

@@ -211,7 +211,7 @@ static int rcar_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs)
 	int ret;
 
 	for (; nmsgs > 0; nmsgs--, msg++) {
-		ret = rcar_i2c_set_addr(dev, msg->addr, 1);
+		ret = rcar_i2c_set_addr(dev, msg->addr, !!(msg->flags & I2C_M_RD));
 		if (ret)
 			return ret;
 

drivers/mmc/pic32_sdhci.c

@@ -6,65 +6,76 @@
  * Andrei Pistirica <andrei.pistirica@microchip.com>
  */
 
-#include <common.h>
 #include <dm.h>
 #include <sdhci.h>
-#include <linux/errno.h>
-#include <mach/pic32.h>
+#include <clk.h>
 
-DECLARE_GLOBAL_DATA_PTR;
-
-static int pic32_sdhci_get_cd(struct sdhci_host *host)
-{
-	/* PIC32 SDHCI CD errata:
-	 * - set CD_TEST and clear CD_TEST_INS bit
-	 */
-	sdhci_writeb(host, SDHCI_CTRL_CD_TEST, SDHCI_HOST_CONTROL);
-
-	return 0;
-}
-
-static const struct sdhci_ops pic32_sdhci_ops = {
-	.get_cd	= pic32_sdhci_get_cd,
+struct pic32_sdhci_plat {
+	struct mmc_config cfg;
+	struct mmc mmc;
 };
 
 static int pic32_sdhci_probe(struct udevice *dev)
 {
+	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+	struct pic32_sdhci_plat *plat = dev_get_platdata(dev);
 	struct sdhci_host *host = dev_get_priv(dev);
-	const void *fdt = gd->fdt_blob;
-	u32 f_min_max[2];
-	fdt_addr_t addr;
-	fdt_size_t size;
+
+	struct clk clk;
+	ulong clk_rate;
 	int ret;
 
-	addr = fdtdec_get_addr_size(fdt, dev_of_offset(dev), "reg", &size);
-	if (addr == FDT_ADDR_T_NONE)
-		return -EINVAL;
-
-	host->ioaddr	= ioremap(addr, size);
-	host->name	= dev->name;
-	host->quirks	= SDHCI_QUIRK_NO_HISPD_BIT;
-	host->bus_width	= fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
-					"bus-width", 4);
-	host->ops = &pic32_sdhci_ops;
-
-	ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev),
-				   "clock-freq-min-max", f_min_max, 2);
-	if (ret) {
-		printf("sdhci: clock-freq-min-max not found\n");
-		return ret;
-	}
-
-	host->max_clk   = f_min_max[1];
-
-	ret = add_sdhci(host, 0, f_min_max[0]);
+	ret = clk_get_by_name(dev, "base_clk", &clk);
 	if (ret)
 		return ret;
+
+	clk_rate = clk_get_rate(&clk);
+	clk_free(&clk);
+
+	if (IS_ERR_VALUE(clk_rate))
+		return clk_rate;
+
+	host->ioaddr = dev_remap_addr(dev);
+
+	if (!host->ioaddr)
+		return -EINVAL;
+
+	host->name	= dev->name;
+	host->quirks	= SDHCI_QUIRK_NO_HISPD_BIT;
+	host->bus_width	= dev_read_u32_default(dev, "bus-width", 4);
+	host->max_clk   = clk_rate;
+
+	host->mmc = &plat->mmc;
 	host->mmc->dev = dev;
 
+	ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0);
+	if (ret)
+		return ret;
+
+	host->mmc->priv = host;
+	upriv->mmc = host->mmc;
+
+	ret = sdhci_probe(dev);
+	if (ret)
+		return ret;
+
+	if (!dev_read_bool(dev, "microchip,use-sdcd")) {
+		// Use workaround 1 for erratum #15 by default
+		u8 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
+		ctrl = (ctrl & ~SDHCI_CTRL_CD_TEST_INS) | SDHCI_CTRL_CD_TEST;
+		sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
+	}
+
 	return 0;
 }
 
+static int pic32_sdhci_bind(struct udevice *dev)
+{
+	struct pic32_sdhci_plat *plat = dev_get_platdata(dev);
+
+	return sdhci_bind(dev, &plat->mmc, &plat->cfg);
+}
+
 static const struct udevice_id pic32_sdhci_ids[] = {
 	{ .compatible = "microchip,pic32mzda-sdhci" },
 	{ }
@@ -74,6 +85,9 @@ U_BOOT_DRIVER(pic32_sdhci_drv) = {
 	.name			= "pic32_sdhci",
 	.id			= UCLASS_MMC,
 	.of_match		= pic32_sdhci_ids,
+	.ops			= &sdhci_ops,
+	.bind			= pic32_sdhci_bind,
 	.probe			= pic32_sdhci_probe,
 	.priv_auto_alloc_size	= sizeof(struct sdhci_host),
+	.platdata_auto_alloc_size = sizeof(struct pic32_sdhci_plat)
 };

drivers/mtd/Kconfig

@@ -6,8 +6,8 @@ config MTD_PARTITIONS
 config MTD
 	bool "Enable MTD layer"
 	help
-	  Enable the MTD stack, necessary to interract with NAND, NOR,
-	  SPI-NOR, SPI-NAND, onenand, etc.
+	  Enable the MTD stack, necessary to interact with NAND, NOR,
+	  SPI-NOR, SPI-NAND, OneNAND, etc.
 
 config DM_MTD
 	bool "Enable Driver Model for MTD drivers"
@@ -95,10 +95,10 @@ config FLASH_PIC32
 	  chips through PIC32 Non-Volatile-Memory Controller.
 
 config RENESAS_RPC_HF
-	bool "Renesas RCar Gen3 RPC Hyperflash driver"
+	bool "Renesas RCar Gen3 RPC HyperFlash driver"
 	depends on RCAR_GEN3 && DM_MTD
 	help
-	  This enables access to Hyperflash memory through the Renesas
+	  This enables access to HyperFlash memory through the Renesas
 	  RCar Gen3 RPC controller.
 
 config HBMC_AM654

drivers/mtd/renesas_rpc_hf.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Renesas RCar Gen3 RPC Hyperflash driver
+ * Renesas RCar Gen3 RPC HyperFlash driver
  *
  * Copyright (C) 2016 Renesas Electronics Corporation
  * Copyright (C) 2016 Cogent Embedded, Inc.

drivers/mtd/spi/spi-nor-ids.c

@@ -151,6 +151,7 @@ const struct flash_info spi_nor_ids[] = {
 	{ INFO("mx25u3235f",  0xc22536, 0, 4 * 1024,  1024, SECT_4K) },
 	{ INFO("mx25u6435f",  0xc22537, 0, 64 * 1024, 128, SECT_4K) },
 	{ INFO("mx25l12805d", 0xc22018, 0, 64 * 1024, 256, 0) },
+	{ INFO("mx25u12835f", 0xc22538, 0, 64 * 1024, 256, SECT_4K) },
 	{ INFO("mx25l12855e", 0xc22618, 0, 64 * 1024, 256, 0) },
 	{ INFO("mx25l25635e", 0xc22019, 0, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 	{ INFO("mx25u25635f", 0xc22539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_4B_OPCODES) },

drivers/net/fm/memac.c

@@ -98,6 +98,7 @@ static void memac_set_interface_mode(struct fsl_enet_mac *mac,
 		if_mode &= ~IF_MODE_MASK;
 		if_mode |= (IF_MODE_GMII);
 		break;
+	case PHY_INTERFACE_MODE_XFI:
 	case PHY_INTERFACE_MODE_XGMII:
 		if_mode &= ~IF_MODE_MASK;
 		if_mode |= IF_MODE_XGMII;
@@ -106,7 +107,7 @@ static void memac_set_interface_mode(struct fsl_enet_mac *mac,
 		break;
 	}
 	/* Enable automatic speed selection for Non-XGMII */
-	if (type != PHY_INTERFACE_MODE_XGMII)
+	if (type != PHY_INTERFACE_MODE_XGMII && type != PHY_INTERFACE_MODE_XFI)
 		if_mode |= IF_MODE_EN_AUTO;
 
 	if (type == PHY_INTERFACE_MODE_RGMII ||

drivers/net/ldpaa_eth/lx2160a.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2018 NXP
+ * Copyright 2018, 2020 NXP
  */
 #include <common.h>
 #include <phy.h>
@@ -57,7 +57,7 @@ phy_interface_t wriop_dpmac_enet_if(int dpmac_id, int lane_prtcl)
 {
 	enum srds_prtcl;
 
-	if (is_device_disabled(dpmac_id + 1))
+	if (is_device_disabled(dpmac_id))
 		return PHY_INTERFACE_MODE_NONE;
 
 	if (lane_prtcl >= SGMII1 && lane_prtcl <= SGMII18)

drivers/net/pfe_eth/pfe_eth.c

@@ -176,9 +176,10 @@ static int pfe_eth_send(struct udevice *dev, void *packet, int length)
 
 		udelay(100);
 		i++;
-		if (i == 30000)
+		if (i == 30000) {
 			printf("Tx timeout, send failed\n");
-		break;
+			break;
+		}
 	}
 
 	return 0;
@@ -213,27 +214,22 @@ static int pfe_eth_recv(struct udevice *dev, int flags, uchar **packetp)
 static int pfe_eth_probe(struct udevice *dev)
 {
 	struct pfe_eth_dev *priv = dev_get_priv(dev);
-	struct pfe_ddr_address *pfe_addr;
+	struct pfe_ddr_address pfe_addr;
 	struct pfe_eth_pdata *pdata = dev_get_platdata(dev);
 	int ret = 0;
 	static int init_done;
 
 	if (!init_done) {
-		pfe_addr = (struct pfe_ddr_address *)malloc(sizeof
-						    (struct pfe_ddr_address));
-		if (!pfe_addr)
-			return -ENOMEM;
-
-		pfe_addr->ddr_pfe_baseaddr =
+		pfe_addr.ddr_pfe_baseaddr =
 				(void *)pdata->pfe_ddr_addr.ddr_pfe_baseaddr;
-		pfe_addr->ddr_pfe_phys_baseaddr =
+		pfe_addr.ddr_pfe_phys_baseaddr =
 		(unsigned long)pdata->pfe_ddr_addr.ddr_pfe_phys_baseaddr;
 
 		debug("ddr_pfe_baseaddr: %p, ddr_pfe_phys_baseaddr: %08x\n",
-		      pfe_addr->ddr_pfe_baseaddr,
-		      (u32)pfe_addr->ddr_pfe_phys_baseaddr);
+		      pfe_addr.ddr_pfe_baseaddr,
+		      (u32)pfe_addr.ddr_pfe_phys_baseaddr);
 
-		ret = pfe_drv_init(pfe_addr);
+		ret = pfe_drv_init(&pfe_addr);
 		if (ret)
 			return ret;
 

drivers/net/pfe_eth/pfe_firmware.c

@@ -167,25 +167,23 @@ static int pfe_fit_check(void)
 int pfe_spi_flash_init(void)
 {
 	struct spi_flash *pfe_flash;
+	struct udevice *new;
 	int ret = 0;
 	void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
 
-#ifdef CONFIG_DM_SPI_FLASH
-	struct udevice *new;
+	if (!addr)
+		return -ENOMEM;
 
-	/* speed and mode will be read from DT */
 	ret = spi_flash_probe_bus_cs(CONFIG_ENV_SPI_BUS,
-				     CONFIG_ENV_SPI_CS, 0, 0, &new);
+				     CONFIG_ENV_SPI_CS,
+				     CONFIG_ENV_SPI_MAX_HZ,
+				     CONFIG_ENV_SPI_MODE,
+				     &new);
 
 	pfe_flash = dev_get_uclass_priv(new);
-#else
-	pfe_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS,
-				    CONFIG_ENV_SPI_CS,
-				    CONFIG_ENV_SPI_MAX_HZ,
-				    CONFIG_ENV_SPI_MODE);
-#endif
 	if (!pfe_flash) {
 		printf("SF: probe for pfe failed\n");
+		free(addr);
 		return -ENODEV;
 	}
 

drivers/net/phy/aquantia.c

@@ -680,6 +680,20 @@ struct phy_driver aqr112_driver = {
 	.data = AQUANTIA_GEN3,
 };
 
+struct phy_driver aqr113c_driver = {
+	.name = "Aquantia AQR113C",
+	.uid = 0x31c31c12,
+	.mask = 0xfffffff0,
+	.features = PHY_10G_FEATURES,
+	.mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS |
+		 MDIO_MMD_PHYXS | MDIO_MMD_AN |
+		 MDIO_MMD_VEND1),
+	.config = &aquantia_config,
+	.startup = &aquantia_startup,
+	.shutdown = &gen10g_shutdown,
+	.data = AQUANTIA_GEN3,
+};
+
 struct phy_driver aqr405_driver = {
 	.name = "Aquantia AQR405",
 	.uid = 0x3a1b4b2,
@@ -716,6 +730,7 @@ int phy_aquantia_init(void)
 	phy_register(&aqr106_driver);
 	phy_register(&aqr107_driver);
 	phy_register(&aqr112_driver);
+	phy_register(&aqr113c_driver);
 	phy_register(&aqr405_driver);
 	phy_register(&aqr412_driver);
 

drivers/pci/pci-aardvark.c

@@ -647,10 +647,15 @@ static int pcie_advk_probe(struct udevice *dev)
 static int pcie_advk_remove(struct udevice *dev)
 {
 	struct pcie_advk *pcie = dev_get_priv(dev);
+	u32 reg;
 
 	if (dm_gpio_is_valid(&pcie->reset_gpio))
 		dm_gpio_set_value(&pcie->reset_gpio, 1);
 
+	reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
+	reg &= ~LINK_TRAINING_EN;
+	advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
+
 	return 0;
 }
 

drivers/pci/pcie_layerscape_fixup.c

@@ -188,6 +188,12 @@ static void fdt_fixup_pcie_ls(void *blob)
 	     pci_find_next_device(&dev)) {
 		for (bus = dev; device_is_on_pci_bus(bus);)
 			bus = bus->parent;
+
+		/* Only do the fixups for layerscape PCIe controllers */
+		if (!device_is_compatible(bus, "fsl,ls-pcie") &&
+		    !device_is_compatible(bus, CONFIG_FSL_PCIE_COMPAT))
+			continue;
+
 		pcie_rc = dev_get_priv(bus);
 
 		streamid = pcie_next_streamid(pcie_rc->stream_id_cur,

drivers/pci/pcie_layerscape_fixup_common.c

@@ -41,6 +41,8 @@ int lx2_board_fix_fdt(void *fdt)
 		{ "config_axi_slave", "config" }
 	};
 	int off = -1, i;
+	const fdt32_t *prop;
+	u32 ob_wins, ib_wins;
 
 	off = fdt_node_offset_by_compatible(fdt, -1, "fsl,lx2160a-pcie");
 	while (off != -FDT_ERR_NOTFOUND) {
@@ -86,6 +88,30 @@ int lx2_board_fix_fdt(void *fdt)
 		off = fdt_node_offset_by_compatible(fdt, off,
 						    "fsl,lx2160a-pcie");
 	}
+
+	/* Fixup PCIe EP nodes */
+	off = -1;
+	off = fdt_node_offset_by_compatible(fdt, off, "fsl,lx2160a-pcie-ep");
+	while (off != -FDT_ERR_NOTFOUND) {
+		fdt_setprop_string(fdt, off, "compatible",
+				   "fsl,lx2160ar2-pcie-ep");
+		prop = fdt_getprop(fdt, off, "apio-wins", NULL);
+		if (!prop) {
+			printf("%s: Failed to fixup PCIe EP node @0x%x\n",
+			       __func__, off);
+			continue;
+		}
+
+		ob_wins = fdt32_to_cpu(*prop);
+		ib_wins = (ob_wins == 256) ? 24 : 8;
+		fdt_setprop_u32(fdt, off, "num-ib-windows", ib_wins);
+		fdt_setprop_u32(fdt, off, "num-ob-windows", ob_wins);
+		fdt_delprop(fdt, off, "apio-wins");
+
+		off = fdt_node_offset_by_compatible(fdt, off,
+						    "fsl,lx2160a-pcie-ep");
+	}
+
 	return 0;
 }
 

drivers/pinctrl/pinctrl_pic32.c

@@ -222,6 +222,31 @@ static void pic32_eth_pin_config(struct udevice *dev)
 	pic32_pinconfig_set(priv, configs, ARRAY_SIZE(configs));
 }
 
+static void pic32_sdhci_pin_config(struct udevice *dev)
+{
+	struct pic32_pinctrl_priv *priv = dev_get_priv(dev);
+	const struct pic32_pin_config configs[] = {
+		/* SDWP - H2 */
+		PIN_CONFIG(PIC32_PORT_H, 2, PIN_CONFIG_PIC32_DIGITAL),
+		/* SDCD - A0 */
+		PIN_CONFIG(PIC32_PORT_A, 0, PIN_CONFIG_PIC32_DIGITAL),
+		/* SDCMD - D4 */
+		PIN_CONFIG(PIC32_PORT_D, 4, PIN_CONFIG_PIC32_DIGITAL),
+		/* SDCK - A6 */
+		PIN_CONFIG(PIC32_PORT_A, 6, PIN_CONFIG_PIC32_DIGITAL),
+		/* SDDATA0 - G13 */
+		PIN_CONFIG(PIC32_PORT_G, 13, PIN_CONFIG_PIC32_DIGITAL),
+		/* SDDATA1 - G12 */
+		PIN_CONFIG(PIC32_PORT_G, 12, PIN_CONFIG_PIC32_DIGITAL),
+		/* SDDATA2 - G14 */
+		PIN_CONFIG(PIC32_PORT_G, 14, PIN_CONFIG_PIC32_DIGITAL),
+		/* SDDATA3 - A7 */
+		PIN_CONFIG(PIC32_PORT_A, 7, PIN_CONFIG_PIC32_DIGITAL),
+	};
+
+	pic32_pinconfig_set(priv, configs, ARRAY_SIZE(configs));
+}
+
 static int pic32_pinctrl_request(struct udevice *dev, int func, int flags)
 {
 	struct pic32_pinctrl_priv *priv = dev_get_priv(dev);
@@ -240,6 +265,9 @@ static int pic32_pinctrl_request(struct udevice *dev, int func, int flags)
 	case PERIPH_ID_ETH:
 		pic32_eth_pin_config(dev);
 		break;
+	case PERIPH_ID_SDHCI:
+		pic32_sdhci_pin_config(dev);
+		break;
 	default:
 		debug("%s: unknown-unhandled case\n", __func__);
 		break;

drivers/rng/meson-rng.c

@@ -90,8 +90,9 @@ static int meson_rng_ofdata_to_platdata(struct udevice *dev)
 	if (!pdata->base)
 		return -ENODEV;
 
+	/* Get optional "core" clock */
 	err = clk_get_by_name(dev, "core", &pdata->clk);
-	if (err)
+	if (err && err != -ENODATA)
 		return err;
 
 	return 0;

drivers/spi/mpc8xxx_spi.c

@@ -109,8 +109,7 @@ static void mpc8xxx_spi_cs_activate(struct udevice *dev)
 	struct mpc8xxx_priv *priv = dev_get_priv(dev->parent);
 	struct dm_spi_slave_platdata *platdata = dev_get_parent_platdata(dev);
 
-	dm_gpio_set_dir_flags(&priv->gpios[platdata->cs], GPIOD_IS_OUT);
-	dm_gpio_set_value(&priv->gpios[platdata->cs], 0);
+	dm_gpio_set_value(&priv->gpios[platdata->cs], 1);
 }
 
 static void mpc8xxx_spi_cs_deactivate(struct udevice *dev)
@@ -118,8 +117,7 @@ static void mpc8xxx_spi_cs_deactivate(struct udevice *dev)
 	struct mpc8xxx_priv *priv = dev_get_priv(dev->parent);
 	struct dm_spi_slave_platdata *platdata = dev_get_parent_platdata(dev);
 
-	dm_gpio_set_dir_flags(&priv->gpios[platdata->cs], GPIOD_IS_OUT);
-	dm_gpio_set_value(&priv->gpios[platdata->cs], 1);
+	dm_gpio_set_value(&priv->gpios[platdata->cs], 0);
 }
 
 static int mpc8xxx_spi_xfer(struct udevice *dev, uint bitlen,

drivers/video/console_truetype.c

@@ -432,7 +432,7 @@ static int console_truetype_backspace(struct udevice *dev)
 	pos = &priv->pos[--priv->pos_ptr];
 
 	/*
-	 * Figure out the end position for clearing. Normlly it is the current
+	 * Figure out the end position for clearing. Normally it is the current
 	 * cursor position, but if we are clearing a character on the previous
 	 * line, we clear from the end of the line.
 	 */

fs/squashfs/sqfs_inode.c

@@ -141,9 +141,9 @@ int sqfs_read_metablock(unsigned char *file_mapping, int offset,
 	const unsigned char *data;
 	u16 header;
 
-	data = file_mapping + offset;
-	if (!data)
+	if (!file_mapping)
 		return -EFAULT;
+	data = file_mapping + offset;
 
 	header = get_unaligned((u16 *)data);
 	if (!header)

include/configs/ls1028aqds.h

@@ -129,13 +129,6 @@
 			"run scan_dev_for_boot; " \
 		  "fi; " \
 		"done\0" \
-	"scan_dev_for_boot=" \
-		"echo Scanning ${devtype} " \
-				"${devnum}:${distro_bootpart}...; " \
-		"for prefix in ${boot_prefixes}; do " \
-			"run scan_dev_for_scripts; " \
-		"done;" \
-		"\0" \
 	"boot_a_script=" \
 		"load ${devtype} ${devnum}:${distro_bootpart} " \
 			"${scriptaddr} ${prefix}${script}; " \

include/configs/ls1028ardb.h

@@ -112,13 +112,6 @@
 			"run scan_dev_for_boot; "            \
 		  "fi; "                                   \
 		"done\0"                                   \
-	"scan_dev_for_boot="				  \
-		"echo Scanning ${devtype} "		  \
-				"${devnum}:${distro_bootpart}...; "  \
-		"for prefix in ${boot_prefixes}; do "	  \
-			"run scan_dev_for_scripts; "	  \
-		"done;"					  \
-		"\0"					  \
 	"boot_a_script="				  \
 		"load ${devtype} ${devnum}:${distro_bootpart} "  \
 			"${scriptaddr} ${prefix}${script}; "    \

include/configs/lx2160aqds.h

@@ -131,7 +131,7 @@ u8 qixis_esdhc_detect_quirk(void);
 		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 		" bootm $load_addr#$BOARD\0"			\
 	"sd_bootcmd=echo Trying load from sd card..;"		\
-		"mmcinfo; mmc read $load_addr "			\
+		"mmc dev 0; mmcinfo; mmc read $load_addr "			\
 		"$kernel_addr_sd $kernel_size_sd ;"		\
 		"env exists secureboot && mmc read $kernelheader_addr_r "\
 		"$kernelhdr_addr_sd $kernelhdr_size_sd "	\

include/configs/lx2160ardb.h

@@ -101,7 +101,7 @@
 		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 		" bootm $load_addr#$BOARD\0"			\
 	"sd_bootcmd=echo Trying load from sd card..;"		\
-		"mmcinfo; mmc read $load_addr "			\
+		"mmc dev 0; mmcinfo; mmc read $load_addr "			\
 		"$kernel_addr_sd $kernel_size_sd ;"		\
 		"env exists secureboot && mmc read $kernelheader_addr_r "\
 		"$kernelhdr_addr_sd $kernelhdr_size_sd "	\

include/configs/mvebu_armada-37xx.h

@@ -6,6 +6,8 @@
 #ifndef _CONFIG_MVEBU_ARMADA_37XX_H
 #define _CONFIG_MVEBU_ARMADA_37XX_H
 
+#include <linux/sizes.h>
+
 /*
  * High Level Configuration Options (easy to change)
  */
@@ -13,6 +15,8 @@
 /* additions for new ARM relocation support */
 #define CONFIG_SYS_SDRAM_BASE	0x00000000
 
+#define CONFIG_SYS_BOOTM_LEN	SZ_64M /* Increase max gunzip size */
+
 /* auto boot */
 
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, \

include/configs/tbs2910.h

@@ -85,13 +85,12 @@
 			"bootm 0x10800000 0x10d00000\0" \
 	"console=ttymxc0\0" \
 	"fan=gpio set 92\0" \
-	"fdt_addr=0x13000000\0" \
-	"fdt_addr_r=0x13000000\0" \
+	"fdt_addr_r=0x18000000\0" \
 	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
-	"kernel_addr_r=0x10008000\0" \
-	"pxefile_addr_r=0x10008000\0" \
-	"ramdisk_addr_r=0x18000000\0" \
-	"scriptaddr=0x14000000\0" \
+	"kernel_addr_r=0x12000000\0" \
+	"pxefile_addr_r=0x10100000\0" \
+	"ramdisk_addr_r=0x18080000\0" \
+	"scriptaddr=0x10000000\0" \
 	"set_con_serial=setenv stdout serial; " \
 			"setenv stderr serial\0" \
 	"set_con_hdmi=setenv stdout serial,vidconsole; " \

include/configs/vocore2.h

@@ -25,6 +25,7 @@
 #define CONFIG_SPL_BSS_START_ADDR	0x80010000
 #define CONFIG_SPL_BSS_MAX_SIZE		0x10000
 #define CONFIG_SPL_MAX_SIZE		0x10000
+#define CONFIG_SPL_PAD_TO		0
 
 /* Dummy value */
 #define CONFIG_SYS_UBOOT_BASE		0
@@ -34,12 +35,13 @@
 #define CONFIG_SYS_NS16550_CLK		40000000
 #define CONFIG_SYS_NS16550_REG_SIZE	-4
 #define CONFIG_SYS_NS16550_COM3		0xb0000e00
+#define CONFIG_CONS_INDEX		3
 
 /* RAM */
 
 /* Memory usage */
 #define CONFIG_SYS_MAXARGS		64
-#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(16 * 1024 * 1024)
 #define CONFIG_SYS_BOOTPARAMS_LEN	(128 * 1024)
 #define CONFIG_SYS_CBSIZE		512
 

include/efi_loader.h

@@ -154,7 +154,6 @@ extern const struct efi_hii_config_routing_protocol efi_hii_config_routing;
 extern const struct efi_hii_config_access_protocol efi_hii_config_access;
 extern const struct efi_hii_database_protocol efi_hii_database;
 extern const struct efi_hii_string_protocol efi_hii_string;
-extern const struct efi_rng_protocol efi_rng_protocol;
 
 uint16_t *efi_dp_str(struct efi_device_path *dp);
 
@@ -404,6 +403,8 @@ efi_status_t EFIAPI efi_convert_pointer(efi_uintn_t debug_disposition,
 efi_status_t efi_console_register(void);
 /* Called by bootefi to make all disk storage accessible as EFI objects */
 efi_status_t efi_disk_register(void);
+/* Called by efi_init_obj_list() to install EFI_RNG_PROTOCOL */
+efi_status_t efi_rng_register(void);
 /* Create handles and protocols for the partitions of a block device */
 int efi_disk_create_partitions(efi_handle_t parent, struct blk_desc *desc,
 			       const char *if_typename, int diskid,