Commit Graph

103321 Commits

Author SHA1 Message Date
Tanmay Kathpalia
ed0e33cec0 mmc: sdhci-cadence6: Add DLL master control and improve tuning reliability
- Add support for configuring the PHY DLL master control register for all
  SD/eMMC timing modes (DS, HS, SDR, DDR, HS200, HS400) by extending the
  PHY configuration arrays and writing the value during PHY adjustment.
- Fix tuning reliability by toggling the DLL reset before and after
  updating the PHY_DLL_SLAVE_CTRL_REG_ADDR register.

Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@altera.com>
Reviewed-by: Balsundar Ponnusamy <balsundar.ponnusamy@altera.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-12-11 20:53:52 +08:00
Tanmay Kathpalia
7c2ba8a202 mmc: sdhci-cadence6: socfpga: Fix DT property naming convention
1. Replace underscores with hyphens in device tree property names to
follow the standard DT naming convention. This affects all
"lpbk_ctrl" properties which are now correctly named "lpbk-ctrl".

Changes:
- cdns,phy-gate-lpbk_ctrl-delay-* → cdns,phy-gate-lpbk-ctrl-delay-*
- cdns,ctrl-hrs10-lpbk_ctrl-delay-* → cdns,ctrl-hrs10-lpbk-ctrl-delay-*

2. Fix typo: semmc → emmc in eMMC SDR PHY property name

Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@altera.com>
Reviewed-by: Balsundar Ponnusamy <balsundar.ponnusamy@altera.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-12-11 20:53:52 +08:00
Tanmay Kathpalia
3dafdeface mmc: sdhci-cadence: Enable software tuning for both SD and eMMC interfaces
Remove interface type restrictions in sdhci_cdns_execute_tuning() to
enable software tuning for both SD and eMMC devices. The previous
assumption that SD timing should be handled by SDHCI core is incorrect
based on the actual function assignment logic.

The execute_tuning function is assigned based on MMC_SUPPORTS_TUNING
config, which is enabled by both MMC_UHS_SUPPORT and MMC_HS200_SUPPORT.

Changes:
Remove IS_MMC() check that restricted tuning to eMMC only
Remove opcode validation limited to MMC_CMD_SEND_TUNING_BLOCK_HS200

Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@altera.com>
Reviewed-by: Balsundar Ponnusamy <balsundar.ponnusamy@altera.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-12-11 20:53:52 +08:00
Tanmay Kathpalia
7d52b66b9b mmc: sdhci-cadence: Use hardware version field for Cadence SDHCI controller
Replace device tree compatible string checks with hardware version field
detection to determine SDHCI controller capabilities. This approach is
more robust and aligns with standard SDHCI specification practices.
Controllers with SDHCI version 4.2 and above will automatically use the
enhanced PHY adjustment, and tuning v6-specific procedures.

Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@altera.com>
Reviewed-by: Balsundar Ponnusamy <balsundar.ponnusamy@altera.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-12-11 20:53:52 +08:00
Tanmay Kathpalia
90f43c7edc mmc: sdhci: Add SDHCI_SPEC_400, _410, and _420 version defines
Add SDHCI_SPEC_400, SDHCI_SPEC_410, and SDHCI_SPEC_420 macros to sdhci.h
to support newer SDHCI specification versions. These defines are required
for compatibility with controllers implementing SDHCI 4.0 and above.

Reference:
https://lore.kernel.org/all/1535617305-16952-2-git-send-email-zhang.chunyan@linaro.org/

Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@altera.com>
Reviewed-by: Balsundar Ponnusamy <balsundar.ponnusamy@altera.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-12-11 20:53:51 +08:00
Tanmay Kathpalia
fa7e82127f mmc: sdhci-cadence: Set controller and PHY speed modes for SD and eMMC cards
Replace the legacy clock frequency-based timing mode selection with
proper MMC timing mode constants.

Changes to sdhci-cadence.c:
- Add sdhci_cdns_get_hrs06_mode() helper function for mode selection
- Replace clock frequency logic with mmc->selected_mode switch statement
- Use proper MMC timing constants (MMC_HS, UHS_SDR104, etc.)
- Add SD card specific handling with standard SDHCI control register setup

Changes to sdhci-cadence6.c:
- Add SD high speed PHY and control configuration arrays
- Update sdhci_cdns6_phy_adj() to use timing modes instead of HRS06 modes
- Support both SD and eMMC timing modes with appropriate PHY settings

Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@altera.com>
Reviewed-by: Balsundar Ponnusamy <balsundar.ponnusamy@altera.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-12-11 20:53:51 +08:00
Tanmay Kathpalia
1e40e419ae mmc: sdhci-cadence: Use max-frequency property from device tree
When f_max parameter is 0 in sdhci_setup_cfg(), the function defaults
to using the maximum frequency from host controller capabilities register
instead of the max-frequency property parsed from device tree.

The max-frequency property from device tree is parsed by mmc_of_parse()
and stored in plat->cfg.f_max, but sdhci_setup_cfg() was being called
with f_max=0, causing it to ignore the device tree value and use the
host capabilities register value instead.

Fix this by passing plat->cfg.f_max to sdhci_setup_cfg() to ensure
the device tree specified maximum frequency is respected over the
hardware default.

Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@altera.com>
Reviewed-by: Balsundar Ponnusamy <balsundar.ponnusamy@altera.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-12-11 20:53:50 +08:00
Tanmay Kathpalia
aebb523a23 mmc: mmc-uclass: Use max-frequency from device tree with default handling
When the max-frequency property is not specified in the device tree,
the function now explicitly defaults to 0 instead of leaving cfg->f_max
uninitialized. This allows sdhci_setup_cfg() to properly detect the
absence of a device tree specified frequency and fall back to using
the host controller's maximum base clock frequency from the capabilities
register.

Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@altera.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-12-11 20:53:50 +08:00
Tanmay Kathpalia
b033255a57 mmc: sdhci-cadence: Add reset control support
Add reset control functionality to the SDHCI Cadence driver to properly
handle hardware reset sequences during probe. This ensures the controller
is in a known state before initialization.

Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@altera.com>
Reviewed-by: Balsundar Ponnusamy <balsundar.ponnusamy@altera.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-12-11 20:53:50 +08:00
Jérémie Dautheribes
66be03b7ee binman: blob_dtb: improve error message when SPL is not found
When using binman with the '-a spl-dtb=y' flag, if the SPL blob is not
found, binman throws a cryptic error message:
binman: 'NoneType' object has no attribute 'startswith'

Let's improve the error message to explicitly state which SPL blob is
missing.
This is particularly useful when binman is used as a standalone tool
outside the U-Boot source tree.

Signed-off-by: Jérémie Dautheribes <jeremie.dautheribes@bootlin.com>
[trini: Add '# pragma: no cover' because coverage doesn't seem to like
the documentation about this error]
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-12-10 13:45:29 -06:00
Wadim Egorov
90dc6a8b10 arch: arm: dts: k3-am642-phyboard-electra: Drop bootph properties
Remove bootph properties no longer needed. These are now handled
in upstream Linux device trees.

While at it, drop the vtt-supply which is a leftover from the
very initial prototype of this board.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
2025-12-10 11:59:45 -06:00
Wadim Egorov
8c5166e9fe arch: arm: dts: k3-am625-phyboard-lyra: Drop bootph properties
Remove bootph properties no longer needed. These are now handled
in upstream Linux device trees.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
2025-12-10 11:59:45 -06:00
Markus Schneider-Pargmann (TI.com)
5425350bf5 configs: am335x_hs_evm_spi_defconfig: Remove duplicate symbols
Remove symbols already present in the included file.

Signed-off-by: Markus Schneider-Pargmann (TI.com) <msp@baylibre.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2025-12-10 11:59:41 -06:00
Tom Rini
57ff26c424 fs/jffs2: Make depend on !64BIT
Building this code on 64bit platforms leads to warnings (and so errors
in CI). Rather than rework the code, as this is a deprecated filesystem,
don't try and disallow building on 64bit hosts.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-12-10 11:59:38 -06:00
Tom Rini
e09d04dae5 Merge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-riscv into next
CI: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/28674

- riscv: Implement private GCC library
- mpfs: Add MPFS CPU Implementation
- andes: Stop disabling device tree relocation and some minor fixes
- sifive: Stop disabling device tree relocation
- starfive: Cleanup size types and typos
2025-12-08 15:10:53 -06:00
Tom Rini
59202e5ae7 Merge tag 'v2026.01-rc4' into next
Prepare v2026.01-rc4
2025-12-08 13:17:27 -06:00
Tom Rini
0e0a198a68 Prepare v2026.01-rc4
Signed-off-by: Tom Rini <trini@konsulko.com>
v2026.01-rc4
2025-12-08 12:54:47 -06:00
Yao Zi
543900ab53 MAINTAINERS: update my email address
My old mail address, ziyao@disroot.org, has stopped working. Switch to
my new address, me@ziyao.cc, and map it in .mailmap.

Signed-off-by: Yao Zi <me@ziyao.cc>
2025-12-08 12:53:25 -06:00
Pranav Tilak
f2c148e0df arm64: versal: Fix LTO for mini_ospi/mini_qspi
With LTO enabled, mini U-Boot was hanging during reloc_fdt().
The initial stack pointer was placed too low, and the FDT memcpy
destination was carved only 4KB above it. This left insufficient
margin, causing the FDT copy to overwrite the live early stack
and corrupt execution before relocation.

To fix this, increase the malloc heap from 8KB to 12KB and raise the
initial stack pointer by 4KB. Together these adjustments increase
the separation between the early stack and the FDT region during
the pre-relocation phase, eliminating the overlap and fixing the
hang on mini builds (QSPI/OSPI).

Signed-off-by: Pranav Tilak <pranav.vinaytilak@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
2025-12-08 09:05:15 -06:00
Tom Rini
ae184121e0 omap3_evm: Take over maintainership
After talking with Derald, take over the maintainership role for this
platform.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-12-08 08:48:10 -06:00
Tom Rini
976c1cb85f doc: Update urllib3 version for building
The GitHub dependabot tool has reported two "high" priority bugs,
CVE-2025-66418 and CVE-2025-66471, with this package. Update to the
patched version.

Reported-by: GitHub dependabot
Acked-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-12-08 08:44:36 -06:00
Tom Rini
f21a301147 configs: Resync with savedefconfig
Resync all defconfig files using qconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-12-08 08:37:35 -06:00
E Shattow
2da2c01cd1 configs: starfive: enable wget https
Enable WGET_HTTPS (no CA verification; also enables dependency MBEDTLS_LIB)

Signed-off-by: E Shattow <e@freeshell.de>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-12-08 12:11:06 +08:00
Heinrich Schuchardt
cf386262d5 test: provide unit tests for the RISC-V private GCC library
Add unit tests for the functions for counting leading and trailing zero
bits.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2025-12-08 12:11:01 +08:00
Heinrich Schuchardt
dd0ad45920 RISC-V: implement private GCC library
The following functions are provided:

Count leading zero bits

* int __clzsi2 (unsigned int a)
* int __clzdi2 (unsigned long a)
* int __clzti2 (unsigned long long a)

Count trailing zero bits

* int __ctzsi2 (unsigned int a)
* int __ctzdi2 (unsigned long a)
* int __ctzti2 (unsigned long long a)

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2025-12-08 12:10:55 +08:00
Tom Rini
7a12507e35 sifive-unleashed: Stop disabling device tree relocation
Remove setting of fdt_high to ~0, which disables device tree relocation,
from the default environment. Doing so prevents U-Boot from correcting
problems such as having an unaligned device tree and leads to various
failure modes in the OS.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-12-08 12:10:51 +08:00
Tom Rini
17ffa78ecf ae350: Stop disabling device tree relocation
Remove setting of fdt_high to ~0, which disables device tree relocation,
from the default environment. Doing so prevents U-Boot from correcting
problems such as having an unaligned device tree and leads to various
failure modes in the OS.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-12-08 12:10:47 +08:00
Conor Dooley
2f7420ccaa riscv: mpfs: move SoC level options to the CPU Kconfig
There are multiple boards that use the PolarFire SoC, so extract
the Kconfig sections that are determined at a CPU level from the board
Kconfigs now that we have a CPU Kconfig.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2025-12-08 12:10:43 +08:00
Conor Dooley
4d056a2037 riscv: create a custom CPU implementation for PolarFire SoC
PolarFire SoC needs a custom implementation of top_of_ram(), so stop
using the generic CPU & create a custom CPU instead.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-12-08 12:10:39 +08:00
E Shattow
87ecc2b6ca ram: starfive: fix typo for unsupported DDR size
Fix typo for "unsupport" size and improve description to Unknown DDR size.

Signed-off-by: E Shattow <e@freeshell.de>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2025-12-08 12:10:35 +08:00
E Shattow
e8874f361d ram: starfive: use SZ_8G for 8GB memory size
Replace numeric literal with SZ_8G consistent with other uses of types
from linux/types.h

Signed-off-by: E Shattow <e@freeshell.de>
Acked-by: Hal Feng <hal.feng@starfivetech.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2025-12-08 12:10:30 +08:00
E Shattow
bccbe56710 ram: starfive: drop references to 16GB memory size
16GB memory size is not addressable on StarFive JH-7110 SoC because the
DRAM uncached alias begins at +8GB offset from start of DRAM. The logic
for 16GB memory size is a fall-through to the default for an unknown size.
Let's drop this unnecessary 16GB memory size and rely on the case default.

Signed-off-by: E Shattow <e@freeshell.de>
2025-12-08 12:10:26 +08:00
Randolph
28261933c5 falcon: support booting linux from MMC/Parallel Flash
To support booting Linux from MMC, the file name should be
set up correctly. To support booting Linux from Parallel Flash,
the SPL_LOAD_FIT_ADDRESS should point to the Parallel Flash.

Signed-off-by: Randolph <randolph@andestech.com>
2025-12-08 12:10:21 +08:00
Che-Wei Chuang
281e6fa4e4 configs: Change default baud rate to 115200
Updated DTS and configuration files to set the default baud rate from 38400 to 115200.

Signed-off-by: Che-Wei Chuang <cnoize@andestech.com>
2025-12-08 12:10:17 +08:00
Leo Yu-Chi Liang
3b8a3df191 riscv: cpu: Beautify the warning message
Add '\n' to the end of the warning message.

Besides, if we enable console record utility,
missing the '\n' causes the console_record_readline
fail to recognize the end of string.

Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-12-08 12:10:10 +08:00
Tom Rini
8e12d6ccb3 Merge patch series "Azure: Rework world build to directly use the container"
This series from Tom Rini <trini@konsulko.com> makes some of our Azure
jobs easier to follow by removing the abstraction of calling docker from
the job we're running and instead following normal Azure Pipelines
conventions.

Link: https://lore.kernel.org/r/20251126234959.3909571-1-trini@konsulko.com
2025-12-07 12:53:09 -06:00
Tom Rini
57753073c1 Azure: Rework binman testsuite job to directly use the container
Similar to the changes made for the world build job, rework the binman
testsuite job as well. There's no functional changes, but makes our CI
clearer to others familiar with Azure pipelines.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-12-07 08:09:12 -06:00
Tom Rini
cf3d4da03f Azure: Rework world build to directly use the container
While we had problems historically using buildman inside of a container
when invoked directly via Azure, rather than calling docker in our
script, that is no longer the case. We can make the job a bit easier to
understand by running it more normally. The challenge here is that our
container normally runs with an unprivileged user that we have populated
tools for and Azure creates and uses a new unprivileged user. Copy what
we need over to the new user.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-12-07 08:09:12 -06:00
Tom Rini
9ecb7dc4b1 Merge patch series "board: phytec: phytec_som_detection: Add missing assignment"
This series from Daniel Schultz <d.schultz@phytec.de> lays the
groundwork for the phyFLEX SOMs from phytec.

Link: https://lore.kernel.org/r/20251124082506.3376876-1-d.schultz@phytec.de
2025-12-07 08:07:36 -06:00
Daniel Schultz
7bcf016090 board: phytec: phytec_som_detection: Add support for phyFLEX
phyFLEX are SoMs based on the FPSC standard.

Add additional "SOM types" for the phyFLEX modules base on the
FPSC Gamma specification. These modules come in four different
variants; prototypes (PT), standard product (SP), KSP (KP) and
KSM (KM).

Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Reviewed-by: Teresa Remmet <t.remmet@phytec.de>
Tested-by: Dominik Haller <d.haller@phytec.de>
2025-12-07 08:07:07 -06:00
Daniel Schultz
9ce3d264e3 board: phytec: phytec_som_detection: Add missing assignment
Assign the return value of snprintf (total length) to a variable to
properly check if the string has the correct length.

Currently, this variable is always zero and the length check after
snprintf will always fail.

Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
2025-12-07 08:07:07 -06:00
Tom Rini
06e1e2e271 Merge tag 'u-boot-imx-next-20251206' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx into next
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/28658

- Fix the i.MX9 USB instance number for revision B0.
- Add nxp-imx9image etype for binman node.
- Use default for SYS_MALLOC_F_LEN for apalis-imx8 and colibri-imx8x.
- Switch phycore-imx93 to standard boot.
- Update the nitrogen6x maintainer.
2025-12-07 08:05:09 -06:00
Primoz Fiser
76948dd22d board: phytec: phycore-imx93: env: Add required uuu variables
Add variable 'emmc_dev' and 'sd_dev' required for NXP uuu flash scripts.

Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
2025-12-06 15:26:07 -03:00
Primoz Fiser
8f4d74929d board: phytec: phycore-imx93: Set boot_targets dynamically
Set boot_targets environment variable dynamically, so that when booting
from SD-card, boot binaries are also preferably fetched from the SD-card
by default. If the user decides to set their own boot_targets, we should
not overwrite them.

Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
Reviewed-by: Wadim Egorov <w.egorov@phytec.de>
2025-12-06 15:26:07 -03:00
Primoz Fiser
2d964cb725 board: phytec: phycore-imx93: Switch to standard boot
Enable standard boot for the phyCORE-i.MX93 board and use it as a new
default. Add required standard boot variables to the environment, while
removing old boot scripts and now unnecessary environment variables.
Adjust variables according to the requirements of PHYTEC ampliphy-boot
distro-boot. Last but not least, order environment vars by alphabet and
run 'make savedefconfig' to resync defconfig.

Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
Reviewed-by: Wadim Egorov <w.egorov@phytec.de>
2025-12-06 15:26:07 -03:00
Simon Gaynor
3a686ef149 nitrogen6x: change maintainer
Simon Gaynor shall be the new maintainer

Signed-off-by: Simon Gaynor <simon.gaynor@ezurio.com>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
2025-12-06 15:25:47 -03:00
Max Krummenacher
3273fba5f2 configs: colibri-imx8x: use default for SYS_MALLOC_F_LEN
Drop setting an explicit value for SYS_MALLOC_F_LEN. This increases
the available space to 0x10000.

Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
2025-12-06 15:25:26 -03:00
Max Krummenacher
5656e5f059 configs: apalis-imx8: use default for SYS_MALLOC_F_LEN
Drop setting an explicit value for SYS_MALLOC_F_LEN. This increases
the available space to 0x10000.

Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
2025-12-06 15:25:26 -03:00
Fedor Ross
e2829b8cca imx9: scmi: soc: USB instance number change for silicon revision B0
For silicon revision A1, the USB instance number for USB1 is 3 and for
USB2 it is 4. This changed for revision B0 where the USB instance number
for USB1 is 0 and for USB2 it is 1, which is the intended instance
number. Select the correct numbering according to the selected SoC
(IMX95) and its revision.

This patch is based on the information provided by:
"AN14750 Migration Guide from i.MX 95 A1 to B0; Rev. 1.0" .

Reviewed-by: Alice Guo <alice.guo@nxp.com>
Signed-off-by: Fedor Ross <fedor.ross@ifm.com>
Reviewed-by: Marek Vasut <marek.vasut@mailbox.org>
2025-12-06 15:24:56 -03:00
Jérémie Dautheribes (Schneider Electric)
3ffae6c14a imx93-u-boot: use nxp-imx9image etype for binman node
Similar to the imx95, use the nxp-imx9image etype for the binman node to
facilitate further modifications.

Signed-off-by: Jérémie Dautheribes (Schneider Electric) <jeremie.dautheribes@bootlin.com>
2025-12-06 15:24:01 -03:00