Merge patch series "arm: am335x: Switch to upstream devicetree"

"Markus Schneider-Pargmann (TI)" <msp@baylibre.com> says:

The series is split into two logical groups:

- Patches 1-3: Fixes for am335x-evm to boot and support the LCD panel
  with the current u-boot devicetree.
- Patches 4-17: Make upstream devicetree working with uboot. This
  adds tick-timer, adds compatibility of the board code for different
  USB probing, makes SPL smaller and updates the defconfig.

The series has been tested on am335x-evm. Note that I don't have all
other boards built with the am335x_*evm_*defconfig, so tests are
appreciated. buildman reports builds are working.

Link: https://lore.kernel.org/r/20260601-topic-am33-evm-oftree-v2026-01-v8-0-2c33c98e7ce5@baylibre.com/

MAINTAINERS

@@ -50,7 +50,7 @@ so much easier [Ed]
 Maintainers List (try to look for most precise areas first)
 
 		-----------------------------------
-ACPI:
+ACPI
 M:	Simon Glass <sjg@chromium.org>
 S:	Maintained
 F:	board/emulation/configs/acpi.config
@@ -58,7 +58,13 @@ F:	cmd/acpi.c
 F:	include/acpi/
 F:	lib/acpi/
 
-ALIST:
+AIROHA PHY
+M:	Tommy Shih <tommy.shih@airoha.com>
+M:	Kevin-KW Huang <kevin-kw.huang@airoha.com>
+S:	Maintained
+F:	drivers/net/phy/airoha/
+
+ALIST
 M:	Simon Glass <sjg@chromium.org>
 S:	Maintained
 F:	include/alist.h
@@ -208,22 +214,22 @@ M:	Chia-Wei Wang <chiawei_wang@aspeedtech.com>
 R:	Aspeed BMC SW team <BMC-SW@aspeedtech.com>
 R:	Joel Stanley <joel@jms.id.au>
 S:	Maintained
-F:	arch/arm/mach-aspeed/
-F:	arch/arm/include/asm/arch-aspeed/
-F:	board/aspeed/
-F:	drivers/clk/aspeed/
-F:	drivers/crypto/aspeed/
-F:	drivers/gpio/gpio-aspeed.c
 F:	drivers/i2c/ast_i2c.[ch]
-F:	drivers/mmc/aspeed_sdhci.c
-F:	drivers/net/aspeed_mdio.c
 F:	drivers/net/ftgmac100.[ch]
-F:	drivers/pinctrl/aspeed/
-F:	drivers/pwm/pwm-aspeed.c
-F:	drivers/ram/aspeed/
-F:	drivers/reset/reset-ast2500.c
 F:	drivers/watchdog/ast_wdt.c
 N:	aspeed
+N:	ast2500
+
+ARM AXIADO AX3005 SCM3005
+M:	Siu Ming Tong <smtong@axiado.com>
+M:	Karthikeyan Mitran <kmitran@axiado.com>
+M:	Prasad Bolisetty <pbolisetty@axiado.com>
+S:	Maintained
+F:	arch/arm/dts/ax3005*
+F:	arch/arm/mach-axiado/
+F:	board/axiado/scm3005/
+F:	configs/ax3005_scm3005_defconfig
+F:	include/configs/ax3005-scm3005.h
 
 ARM BROADCOM BCM283X / BCM27XX
 M:	Matthias Brugger <mbrugger@suse.com>
@@ -430,6 +436,7 @@ F:	drivers/clk/mediatek/
 F:	drivers/cpu/mtk_cpu.c
 F:	drivers/i2c/mtk_i2c.c
 F:	drivers/mmc/mtk-sd.c
+F:	drivers/net/dwc_eth_qos_mtk.c
 F:	drivers/net/mtk_eth/
 F:	drivers/net/phy/mediatek/
 F:	drivers/phy/phy-mtk-*
@@ -1273,7 +1280,7 @@ S:	Maintained
 F:	drivers/timer/goldfish_timer.c
 F:	include/goldfish_timer.h
 
-INTERCONNECT:
+INTERCONNECT
 M:	Neil Armstrong <neil.armstrong@linaro.org>
 S:	Maintained
 T:	git https://source.denx.de/u-boot/u-boot.git
@@ -1297,6 +1304,11 @@ T:	git https://source.denx.de/u-boot/u-boot.git
 F:	cmd/i3c.c
 F:	drivers/i3c/
 
+JEDEC JC-42.4 / TSE2004av TEMPERATURE SENSOR
+M:	Vincent Jardin <vjardin@free.fr>
+S:	Maintained
+F:	drivers/thermal/jc42.c
+
 KWBIMAGE / KWBOOT TOOLS
 M:	Pali Rohár <pali@kernel.org>
 M:	Marek Behún <kabel@kernel.org>

Makefile

@@ -829,6 +829,21 @@ autoconf_is_old := $(shell find . -path ./$(KCONFIG_CONFIG) -newer \
 						include/config/auto.conf)
 ifeq ($(autoconf_is_old),)
 include $(srctree)/config.mk
+
+ifeq ($(CONFIG_OF_UPSTREAM),y)
+ifeq ($(CONFIG_CPU_V8M),y)
+dt_dir := dts/upstream/src/arm64
+else
+ifeq ($(CONFIG_ARM64),y)
+dt_dir := dts/upstream/src/arm64
+else
+dt_dir := dts/upstream/src/$(ARCH)
+endif
+endif
+else
+dt_dir := arch/$(ARCH)/dts
+endif
+
 include $(srctree)/arch/$(ARCH)/Makefile
 endif
 endif
@@ -1445,20 +1460,6 @@ dt_binding_check: scripts_dtc
 quiet_cmd_copy = COPY    $@
       cmd_copy = cp $< $@
 
-ifeq ($(CONFIG_OF_UPSTREAM),y)
-ifeq ($(CONFIG_CPU_V8M),y)
-dt_dir := dts/upstream/src/arm64
-else
-ifeq ($(CONFIG_ARM64),y)
-dt_dir := dts/upstream/src/arm64
-else
-dt_dir := dts/upstream/src/$(ARCH)
-endif
-endif
-else
-dt_dir := arch/$(ARCH)/dts
-endif
-
 ifeq ($(CONFIG_MULTI_DTB_FIT),y)
 
 ifeq ($(CONFIG_MULTI_DTB_FIT_LZO),y)

arch/arm/Kconfig

@@ -2153,6 +2153,13 @@ config ARCH_ASPEED
 	select OF_CONTROL
 	imply CMD_DM
 
+config ARCH_AXIADO
+	bool "Support Axiado SoCs"
+	select AXIADO_AX3005
+	help
+	  Support for Axiado AX-series SoCs such as the AX3005.
+	  These ARM64 SoCs are used in BMC and security applications.
+
 config TARGET_DURIAN
 	bool "Support Phytium Durian Platform"
 	select ARM64
@@ -2294,6 +2301,8 @@ source "arch/arm/mach-aspeed/Kconfig"
 
 source "arch/arm/mach-at91/Kconfig"
 
+source "arch/arm/mach-axiado/Kconfig"
+
 source "arch/arm/mach-bcm283x/Kconfig"
 
 source "arch/arm/mach-bcmbca/Kconfig"

arch/arm/cpu/armv8/fsl-layerscape/cpu.c

@@ -986,6 +986,27 @@ uint get_svr(void)
 }
 #endif
 
+/*
+ * Layerscape mirror of the i.MX get_cpu_temp_grade(). i.MX reads the
+ * OCOTP "CPU temp grade" fuses; Layerscape has no such fuse, so the
+ * limits come from the data sheet instead. LX2160A Reference Manual
+ * Rev. 1 (10/2021) section 1.12.1 specifies the maximum operating
+ * junction temperature at 105 degC for commercial / embedded parts;
+ * the lower bound is the standard -40 degC commercial low.
+ *
+ * The TMU itself is documented as accurate within +/- 3 degC (RM
+ * section 28.1), which the thermal driver clears by setting its
+ * alert threshold 10 degC below critical.
+ */
+u32 get_cpu_temp_grade(int *minc, int *maxc)
+{
+	if (minc)
+		*minc = -40;
+	if (maxc)
+		*maxc = 105;
+	return 0; /* commercial */
+}
+
 #ifdef CONFIG_DISPLAY_CPUINFO
 int print_cpuinfo(void)
 {

arch/arm/dts/Makefile

@@ -4,6 +4,7 @@ dtb-$(CONFIG_TARGET_SMARTWEB) += at91sam9260-smartweb.dtb
 dtb-$(CONFIG_TARGET_TAURUS) += at91sam9g20-taurus.dtb
 dtb-$(CONFIG_TARGET_CORVUS) += at91sam9g45-corvus.dtb
 dtb-$(CONFIG_TARGET_GURNARD) += at91sam9g45-gurnard.dtb
+dtb-$(CONFIG_TARGET_SCM3005) += ax3005-scm3005.dtb
 
 dtb-$(CONFIG_TARGET_SMDKC100) += s5pc1xx-smdkc100.dtb
 dtb-$(CONFIG_TARGET_S5P_GONI) += s5pc1xx-goni.dtb
@@ -137,6 +138,7 @@ dtb-$(CONFIG_ARCH_MVEBU) +=			\
 	armada-388-gp.dtb			\
 	armada-388-helios4.dtb			\
 	armada-38x-controlcenterdc.dtb		\
+	armada-xp-atl-x220.dtb			\
 	armada-xp-crs305-1g-4s.dtb		\
 	armada-xp-crs305-1g-4s-bit.dtb		\
 	armada-xp-crs326-24g-2s.dtb		\
@@ -162,6 +164,7 @@ dtb-$(CONFIG_ARCH_MVEBU) +=			\
 	armada-8040-clearfog-gt-8k.dtb		\
 	armada-8040-db.dtb			\
 	armada-8040-mcbin.dtb			\
+	armada-8040-nbx.dtb			\
 	armada-8040-puzzle-m801.dtb		\
 	cn9130-db-A.dtb				\
 	cn9130-db-B.dtb				\
@@ -396,26 +399,12 @@ dtb-$(CONFIG_ARCH_ZYNQMP_R5) += \
 	zynqmp-r5.dtb
 dtb-$(CONFIG_AM33XX) += \
 	am335x-baltos.dtb \
-	am335x-bone.dtb \
-	am335x-boneblack.dtb \
-	am335x-boneblack-wireless.dtb \
-	am335x-boneblue.dtb \
 	am335x-brppt1-mmc.dtb \
 	am335x-brxre1.dtb \
 	am335x-brsmarc1.dtb \
 	am335x-draco.dtb \
-	am335x-evm.dtb \
-	am335x-evmsk.dtb \
-	am335x-bonegreen.dtb \
-	am335x-bonegreen-eco.dtb \
-	am335x-bonegreen-wireless.dtb \
-	am335x-icev2.dtb \
-	am335x-pocketbeagle.dtb \
 	am335x-pxm50.dtb \
 	am335x-rut.dtb \
-	am335x-sancloud-bbe.dtb \
-	am335x-sancloud-bbe-lite.dtb \
-	am335x-sancloud-bbe-extended-wifi.dtb \
 	am335x-shc.dtb \
 	am335x-pdu001.dtb \
 	am335x-chiliboard.dtb \

arch/arm/dts/am335x-bone-common-u-boot.dtsi

@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * am335x-bone-common U-Boot Additions
+ *
+ * Common u-boot configuration for all BeagleBone variants
+ */
+
+#include "am33xx-u-boot.dtsi"
+
+/ {
+	chosen {
+		tick-timer = &timer2;
+	};
+};

arch/arm/dts/am335x-bone-u-boot.dtsi

@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * am335x-bone U-Boot Additions
+ */
+
+#include "am335x-bone-common-u-boot.dtsi"

arch/arm/dts/am335x-bone.dts

@@ -1,23 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
- */
-/dts-v1/;
-
-#include "am33xx.dtsi"
-#include "am335x-bone-common.dtsi"
-
-/ {
-	model = "TI AM335x BeagleBone";
-	compatible = "ti,am335x-bone", "ti,am33xx";
-};
-
-&ldo3_reg {
-	regulator-min-microvolt = <1800000>;
-	regulator-max-microvolt = <3300000>;
-	regulator-always-on;
-};
-
-&mmc1 {
-	vmmc-supply = <&ldo3_reg>;
-};

arch/arm/dts/am335x-boneblack-u-boot.dtsi

@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * am335x-boneblack U-Boot Additions
+ */
+
+#include "am335x-bone-common-u-boot.dtsi"
+
+&l4_per {
+	segment@300000 {
+		target-module@e000 {
+			bootph-all;
+			lcdc: lcdc@0 {
+				bootph-all;
+			};
+		};
+	};
+};

arch/arm/dts/am335x-boneblack-wireless-u-boot.dtsi

@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * am335x-boneblack-wireless U-Boot Additions
+ */
+
+#include "am335x-bone-common-u-boot.dtsi"

arch/arm/dts/am335x-boneblack-wireless.dts

@@ -1,111 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
- */
-/dts-v1/;
-
-#include "am33xx.dtsi"
-#include "am335x-bone-common.dtsi"
-#include "am335x-boneblack-common.dtsi"
-#include "am335x-boneblack-hdmi.dtsi"
-#include <dt-bindings/interrupt-controller/irq.h>
-
-/ {
-	model = "TI AM335x BeagleBone Black Wireless";
-	compatible = "ti,am335x-bone-black-wireless", "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx";
-
-	wlan_en_reg: fixedregulator@2 {
-		compatible = "regulator-fixed";
-		regulator-name = "wlan-en-regulator";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-		startup-delay-us = <70000>;
-
-		/* WL_EN */
-		gpio = <&gpio3 9 0>;
-		enable-active-high;
-	};
-};
-
-&am33xx_pinmux {
-	bt_pins: pinmux_bt_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLUP, MUX_MODE7)	/* gmii1_txd0.gpio0_28 - BT_EN */
-		>;
-	};
-
-	mmc3_pins: pinmux_mmc3_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE6 ) /* (L15) gmii1_rxd1.mmc2_clk */
-			AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLUP, MUX_MODE6 ) /* (J16) gmii1_txen.mmc2_cmd */
-			AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLUP, MUX_MODE5 ) /* (J17) gmii1_rxdv.mmc2_dat0 */
-			AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLUP, MUX_MODE5 ) /* (J18) gmii1_txd3.mmc2_dat1 */
-			AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLUP, MUX_MODE5 ) /* (K15) gmii1_txd2.mmc2_dat2 */
-			AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLUP, MUX_MODE5 ) /* (H16) gmii1_col.mmc2_dat3 */
-		>;
-	};
-
-	uart3_pins: pinmux_uart3_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE1)	/* gmii1_rxd3.uart3_rxd */
-			AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE1)	/* gmii1_rxd2.uart3_txd */
-			AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT, MUX_MODE3)		/* mdio_data.uart3_ctsn */
-			AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLDOWN, MUX_MODE3)	/* mdio_clk.uart3_rtsn */
-		>;
-	};
-
-	wl18xx_pins: pinmux_wl18xx_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE7)	/* gmii1_txclk.gpio3_9 WL_EN */
-			AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)	/* rmii1_refclk.gpio0_29 WL_IRQ */
-			AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_OUTPUT_PULLUP, MUX_MODE7)	/* gmii1_rxclk.gpio3_10 LS_BUF_EN */
-		>;
-	};
-};
-
-&mac {
-	status = "disabled";
-};
-
-&mmc3 {
-	dmas = <&edma_xbar 12 0 1
-		&edma_xbar 13 0 2>;
-	dma-names = "tx", "rx";
-	status = "okay";
-	vmmc-supply = <&wlan_en_reg>;
-	bus-width = <4>;
-	non-removable;
-	cap-power-off-card;
-	keep-power-in-suspend;
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc3_pins &wl18xx_pins>;
-
-	#address-cells = <1>;
-	#size-cells = <0>;
-	wlcore: wlcore@2 {
-		compatible = "ti,wl1835";
-		reg = <2>;
-		interrupt-parent = <&gpio0>;
-		interrupts = <29 IRQ_TYPE_EDGE_RISING>;
-	};
-};
-
-&uart3 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart3_pins &bt_pins>;
-	status = "okay";
-
-	bluetooth {
-		compatible = "ti,wl1835-st";
-		enable-gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>;
-	};
-};
-
-&gpio3 {
-	ls-buf-en-hog {
-		gpio-hog;
-		gpios = <10 GPIO_ACTIVE_HIGH>;
-		output-high;
-		line-name = "LS_BUF_EN";
-	};
-};

arch/arm/dts/am335x-boneblack.dts

@@ -1,174 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
- */
-/dts-v1/;
-
-#include "am33xx.dtsi"
-#include "am335x-bone-common.dtsi"
-#include "am335x-boneblack-common.dtsi"
-#include "am335x-boneblack-hdmi.dtsi"
-
-/ {
-	model = "TI AM335x BeagleBone Black";
-	compatible = "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx";
-};
-
-&cpu0_opp_table {
-	/*
-	 * All PG 2.0 silicon may not support 1GHz but some of the early
-	 * BeagleBone Blacks have PG 2.0 silicon which is guaranteed
-	 * to support 1GHz OPP so enable it for PG 2.0 on this board.
-	 */
-	oppnitro-1000000000 {
-		opp-supported-hw = <0x06 0x0100>;
-	};
-};
-
-&gpio0 {
-	gpio-line-names =
-		"[mdio_data]",
-		"[mdio_clk]",
-		"P9_22 [spi0_sclk]",
-		"P9_21 [spi0_d0]",
-		"P9_18 [spi0_d1]",
-		"P9_17 [spi0_cs0]",
-		"[mmc0_cd]",
-		"P8_42A [ecappwm0]",
-		"P8_35 [lcd d12]",
-		"P8_33 [lcd d13]",
-		"P8_31 [lcd d14]",
-		"P8_32 [lcd d15]",
-		"P9_20 [i2c2_sda]",
-		"P9_19 [i2c2_scl]",
-		"P9_26 [uart1_rxd]",
-		"P9_24 [uart1_txd]",
-		"[rmii1_txd3]",
-		"[rmii1_txd2]",
-		"[usb0_drvvbus]",
-		"[hdmi cec]",
-		"P9_41B",
-		"[rmii1_txd1]",
-		"P8_19 [ehrpwm2a]",
-		"P8_13 [ehrpwm2b]",
-		"NC",
-		"NC",
-		"P8_14",
-		"P8_17",
-		"[rmii1_txd0]",
-		"[rmii1_refclk]",
-		"P9_11 [uart4_rxd]",
-		"P9_13 [uart4_txd]";
-};
-
-&gpio1 {
-	gpio-line-names =
-		"P8_25 [mmc1_dat0]",
-		"[mmc1_dat1]",
-		"P8_5 [mmc1_dat2]",
-		"P8_6 [mmc1_dat3]",
-		"P8_23 [mmc1_dat4]",
-		"P8_22 [mmc1_dat5]",
-		"P8_3 [mmc1_dat6]",
-		"P8_4 [mmc1_dat7]",
-		"NC",
-		"NC",
-		"NC",
-		"NC",
-		"P8_12",
-		"P8_11",
-		"P8_16",
-		"P8_15",
-		"P9_15A",
-		"P9_23",
-		"P9_14 [ehrpwm1a]",
-		"P9_16 [ehrpwm1b]",
-		"[emmc rst]",
-		"[usr0 led]",
-		"[usr1 led]",
-		"[usr2 led]",
-		"[usr3 led]",
-		"[hdmi irq]",
-		"[usb vbus oc]",
-		"[hdmi audio]",
-		"P9_12",
-		"P8_26",
-		"P8_21 [emmc]",
-		"P8_20 [emmc]";
-};
-
-&gpio2 {
-	gpio-line-names =
-		"P9_15B",
-		"P8_18",
-		"P8_7",
-		"P8_8",
-		"P8_10",
-		"P8_9",
-		"P8_45 [hdmi]",
-		"P8_46 [hdmi]",
-		"P8_43 [hdmi]",
-		"P8_44 [hdmi]",
-		"P8_41 [hdmi]",
-		"P8_42 [hdmi]",
-		"P8_39 [hdmi]",
-		"P8_40 [hdmi]",
-		"P8_37 [hdmi]",
-		"P8_38 [hdmi]",
-		"P8_36 [hdmi]",
-		"P8_34 [hdmi]",
-		"[rmii1_rxd3]",
-		"[rmii1_rxd2]",
-		"[rmii1_rxd1]",
-		"[rmii1_rxd0]",
-		"P8_27 [hdmi]",
-		"P8_29 [hdmi]",
-		"P8_28 [hdmi]",
-		"P8_30 [hdmi]",
-		"[mmc0_dat3]",
-		"[mmc0_dat2]",
-		"[mmc0_dat1]",
-		"[mmc0_dat0]",
-		"[mmc0_clk]",
-		"[mmc0_cmd]";
-};
-
-&gpio3 {
-	gpio-line-names =
-		"[mii col]",
-		"[mii crs]",
-		"[mii rx err]",
-		"[mii tx en]",
-		"[mii rx dv]",
-		"[i2c0 sda]",
-		"[i2c0 scl]",
-		"[jtag emu0]",
-		"[jtag emu1]",
-		"[mii tx clk]",
-		"[mii rx clk]",
-		"NC",
-		"NC",
-		"[usb vbus en]",
-		"P9_31 [spi1_sclk]",
-		"P9_29 [spi1_d0]",
-		"P9_30 [spi1_d1]",
-		"P9_28 [spi1_cs0]",
-		"P9_42B [ecappwm0]",
-		"P9_27",
-		"P9_41A",
-		"P9_25",
-		"NC",
-		"NC",
-		"NC",
-		"NC",
-		"NC",
-		"NC",
-		"NC",
-		"NC",
-		"NC",
-		"NC";
-};
-
-&baseboard_eeprom {
-	vcc-supply = <&ldo4_reg>;
-};

arch/arm/dts/am335x-boneblue-u-boot.dtsi

@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * am335x-boneblue U-Boot Additions
+ */
+
+#include "am335x-bone-common-u-boot.dtsi"

arch/arm/dts/am335x-boneblue.dts

@@ -1,617 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
- */
-/dts-v1/;
-
-#include "am33xx.dtsi"
-#include "am335x-osd335x-common.dtsi"
-#include <dt-bindings/interrupt-controller/irq.h>
-
-/ {
-	model = "TI AM335x BeagleBone Blue";
-	compatible = "ti,am335x-bone-blue", "ti,am33xx";
-
-	chosen {
-		stdout-path = &uart0;
-		tick-timer = &timer2;
-	};
-
-	leds {
-		pinctrl-names = "default";
-		pinctrl-0 = <&user_leds_s0>;
-
-		compatible = "gpio-leds";
-
-		usr_0_led {
-			label = "beaglebone:green:usr0";
-			gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
-			linux,default-trigger = "heartbeat";
-			default-state = "off";
-		};
-
-		usr_1_led {
-			label = "beaglebone:green:usr1";
-			gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>;
-			linux,default-trigger = "mmc0";
-			default-state = "off";
-		};
-
-		usr_2_led {
-			label = "beaglebone:green:usr2";
-			gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
-			linux,default-trigger = "cpu0";
-			default-state = "off";
-		};
-
-		usr_3_led {
-			label = "beaglebone:green:usr3";
-			gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
-			linux,default-trigger = "mmc1";
-			default-state = "off";
-		};
-
-		wifi_led {
-			label = "wifi";
-			gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>;
-			default-state = "off";
-			linux,default-trigger = "phy0assoc";
-		};
-
-		red_led {
-			label = "red";
-			gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
-			default-state = "off";
-		};
-
-		green_led {
-			label = "green";
-			gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
-			default-state = "off";
-		};
-
-		batt_1_led {
-			label = "bat25";
-			gpios = <&gpio0 27 GPIO_ACTIVE_HIGH>;
-			default-state = "off";
-		};
-
-		batt_2_led {
-			label = "bat50";
-			gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;
-			default-state = "off";
-		};
-
-		batt_3_led {
-			label = "bat75";
-			gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
-			default-state = "off";
-		};
-
-		batt_4_led {
-			label = "bat100";
-			gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>;
-			default-state = "off";
-		};
-	};
-
-	vmmcsd_fixed: fixedregulator0 {
-		compatible = "regulator-fixed";
-		regulator-name = "vmmcsd_fixed";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-	};
-
-	wlan_en_reg: fixedregulator@2 {
-		compatible = "regulator-fixed";
-		regulator-name = "wlan-en-regulator";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-		startup-delay-us = <70000>;
-
-		/* WL_EN */
-		gpio = <&gpio3 9 0>;
-		enable-active-high;
-	};
-};
-
-&am33xx_pinmux {
-	user_leds_s0: user_leds_s0 {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE7) /* (V15) gpmc_a5.gpio1[21] - USR_LED_0 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT, MUX_MODE7) /* (U15) gpmc_a6.gpio1[22] - USR_LED_1 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT, MUX_MODE7) /* (T15) gpmc_a7.gpio1[23] - USR_LED_2 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT, MUX_MODE7) /* (V16) gpmc_a8.gpio1[24] - USR_LED_3 */
-			AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE7) /* (A15) xdma_event_intr0.gpio0[19] - WIFI_LED */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE7) /* (R7) gpmc_advn_ale.gpio2[2] - P8.7, LED_RED, GP1_PIN_5 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE7) /* (T7) gpmc_oen_ren.gpio2[3] - P8.8, LED_GREEN, GP1_PIN_6 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE7) /* (U12) gpmc_ad11.gpio0[27] - P8.17, BATT_LED_1 */
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE7) /* (T5) lcd_data15.gpio0[11] - P8.32, BATT_LED_2 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE7) /* (V6) gpmc_csn0.gpio1[29] - P8.26, BATT_LED_3 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE7) /* (T11) gpmc_ad10.gpio0[26] - P8.14, BATT_LED_4 */
-
-		>;
-	};
-
-	i2c2_pins: pinmux_i2c2_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3)	/* (D18) uart1_ctsn.I2C2_SDA */
-			AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3)	/* (D17) uart1_rtsn.I2C2_SCL */
-		>;
-	};
-
-	/* UT0 */
-	uart0_pins: pinmux_uart0_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
-		>;
-	};
-
-	/* UT1 */
-	uart1_pins: pinmux_uart1_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
-		>;
-	};
-
-	/* GPS */
-	uart2_pins: pinmux_uart2_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE1)	/* (A17) spi0_sclk.uart2_rxd */
-			AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT_PULLDOWN, MUX_MODE1)	/* (B17) spi0_d0.uart2_txd */
-		>;
-	};
-
-	/* DSM2 */
-	uart4_pins: pinmux_uart4_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE6)	/* (T17) gpmc_wait0.uart4_rxd */
-		>;
-	};
-
-	/* UT5 */
-	uart5_pins: pinmux_uart5_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_INPUT_PULLUP, MUX_MODE4)	/* (U2) lcd_data9.uart5_rxd */
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT_PULLDOWN, MUX_MODE4)	/* (U1) lcd_data8.uart5_txd */
-		>;
-	};
-
-	mmc1_pins: pinmux_mmc1_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7)		/* (C15) spi0_cs1.gpio0[6] */
-		>;
-	};
-
-	mmc2_pins: pinmux_mmc2_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2)	/* (U9) gpmc_csn1.mmc1_clk */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2)	/* (V9) gpmc_csn2.mmc1_cmd */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1)	/* (U7) gpmc_ad0.mmc1_dat0 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1)	/* (V7) gpmc_ad1.mmc1_dat1 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1)	/* (R8) gpmc_ad2.mmc1_dat2 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1)	/* (T8) gpmc_ad3.mmc1_dat3 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1)	/* (U8) gpmc_ad4.mmc1_dat4 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1)	/* (V8) gpmc_ad5.mmc1_dat5 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1)	/* (R9) gpmc_ad6.mmc1_dat6 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1)	/* (T9) gpmc_ad7.mmc1_dat7 */
-		>;
-	};
-
-	mmc3_pins: pinmux_mmc3_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE6)	/* (L15) gmii1_rxd1.mmc2_clk */
-			AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLUP, MUX_MODE6)	/* (J16) gmii1_txen.mmc2_cmd */
-			AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLUP, MUX_MODE5)	/* (J17) gmii1_rxdv.mmc2_dat0 */
-			AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLUP, MUX_MODE5)	/* (J18) gmii1_txd3.mmc2_dat1 */
-			AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLUP, MUX_MODE5)	/* (K15) gmii1_txd2.mmc2_dat2 */
-			AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLUP, MUX_MODE5)	/* (H16) gmii1_col.mmc2_dat3 */
-		>;
-	};
-
-	bt_pins: pinmux_bt_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLUP, MUX_MODE7)	/* (K17) gmii1_txd0.gpio0[28] - BT_EN */
-		>;
-	};
-
-	uart3_pins: pinmux_uart3_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE1)	/* (L17) gmii1_rxd3.uart3_rxd */
-			AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE1)	/* (L16) gmii1_rxd2.uart3_txd */
-			AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT, MUX_MODE3)		/* (M17) mdio_data.uart3_ctsn */
-			AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLDOWN, MUX_MODE3)	/* (M18) mdio_clk.uart3_rtsn */
-		>;
-	};
-
-	wl18xx_pins: pinmux_wl18xx_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE7)	/* (K18) gmii1_txclk.gpio3[9] - WL_EN */
-			AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)	/* (K16) gmii1_txd1.gpio0[21] - WL_IRQ */
-			AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_OUTPUT_PULLUP, MUX_MODE7)	/* (L18) gmii1_rxclk.gpio3[10] - LS_BUF_EN */
-		>;
-	};
-
-	/* DCAN */
-	dcan1_pins: pinmux_dcan1_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT, MUX_MODE2)		/* (E17) uart0_rtsn.dcan1_rx */
-			AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT, MUX_MODE2)		/* (E18) uart0_ctsn.dcan1_tx */
-			AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_OUTPUT, MUX_MODE7)		/* (M16) gmii1_rxd0.gpio2[21] */
-		>;
-	};
-
-	/* E1 */
-	eqep0_pins: pinmux_eqep0_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_INPUT, MUX_MODE1)		/* (B12) mcasp0_aclkr.eQEP0A_in */
-			AM33XX_PADCONF(AM335X_PIN_MCASP0_FSR, PIN_INPUT, MUX_MODE1)		/* (C13) mcasp0_fsr.eQEP0B_in */
-		>;
-	};
-
-	/* E2 */
-	eqep1_pins: pinmux_eqep1_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_INPUT, MUX_MODE2)		/* (V2) lcd_data12.eQEP1A_in */
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_INPUT, MUX_MODE2)		/* (V3) lcd_data13.eQEP1B_in */
-		>;
-	};
-
-	/* E3 */
-	eqep2_pins: pinmux_eqep2_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT, MUX_MODE4)		/* (T12) gpmc_ad12.eQEP2A_in */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT, MUX_MODE4)		/* (R12) gpmc_ad13.eQEP2B_in */
-		>;
-	};
-};
-
-&uart0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart0_pins>;
-
-	status = "okay";
-};
-
-&uart1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart1_pins>;
-
-	status = "okay";
-};
-
-&uart2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart2_pins>;
-
-	status = "okay";
-};
-
-&uart4 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart4_pins>;
-
-	status = "okay";
-};
-
-&uart5 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart5_pins>;
-
-	status = "okay";
-};
-
-&usb0 {
-	dr_mode = "peripheral";
-	interrupts-extended = <&intc 18 &tps 0>;
-	interrupt-names = "mc", "vbus";
-};
-
-&usb1 {
-	dr_mode = "host";
-};
-
-&i2c0 {
-	baseboard_eeprom: baseboard_eeprom@50 {
-		compatible = "atmel,24c256";
-		reg = <0x50>;
-
-		#address-cells = <1>;
-		#size-cells = <1>;
-		baseboard_data: baseboard_data@0 {
-			reg = <0 0x100>;
-		};
-	};
-};
-
-&i2c2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c2_pins>;
-
-	status = "okay";
-	clock-frequency = <400000>;
-
-	mpu9250@68 {
-		compatible = "invensense,mpu9250";
-		reg = <0x68>;
-		interrupt-parent = <&gpio3>;
-		interrupts = <21 IRQ_TYPE_EDGE_RISING>;
-		i2c-gate {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			ax8975@c {
-				compatible = "asahi-kasei,ak8975";
-				reg = <0x0c>;
-			};
-		};
-	};
-
-	pressure@76 {
-		compatible = "bosch,bmp280";
-		reg = <0x76>;
-	};
-};
-
-/include/ "tps65217.dtsi"
-
-&tps {
-	/delete-property/ ti,pmic-shutdown-controller;
-
-	charger {
-		interrupts = <0>, <1>;
-		interrupt-names = "USB", "AC";
-		status = "okay";
-	};
-};
-
-&mmc1 {
-	status = "okay";
-	vmmc-supply = <&vmmcsd_fixed>;
-	bus-width = <4>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc1_pins>;
-	cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
-};
-
-&mmc2 {
-	status = "okay";
-	vmmc-supply = <&vmmcsd_fixed>;
-	bus-width = <8>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc2_pins>;
-};
-
-&mmc3 {
-	dmas = <&edma_xbar 12 0 1
-		&edma_xbar 13 0 2>;
-	dma-names = "tx", "rx";
-	status = "okay";
-	vmmc-supply = <&wlan_en_reg>;
-	bus-width = <4>;
-	non-removable;
-	cap-power-off-card;
-	keep-power-in-suspend;
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc3_pins &wl18xx_pins>;
-
-	#address-cells = <1>;
-	#size-cells = <0>;
-	wlcore: wlcore@2 {
-		compatible = "ti,wl1835";
-		reg = <2>;
-		interrupt-parent = <&gpio0>;
-		interrupts = <21 IRQ_TYPE_EDGE_RISING>;
-	};
-};
-
-&tscadc {
-	status = "okay";
-	adc {
-		ti,adc-channels = <0 1 2 3 4 5 6 7>;
-	};
-};
-
-&uart3 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart3_pins &bt_pins>;
-	status = "okay";
-
-	bluetooth {
-		compatible = "ti,wl1835-st";
-		enable-gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>;
-	};
-};
-
-&rtc {
-	system-power-controller;
-	clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
-	clock-names = "ext-clk", "int-clk";
-};
-
-&dcan1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&dcan1_pins>;
-	status = "okay";
-};
-
-&gpio0 {
-	gpio-line-names =
-		"UART3_CTS", /* M17 */
-		"UART3_RTS", /* M18 */
-		"UART2_RX", /* A17 */
-		"UART2_TX", /* B17 */
-		"I2C1_SDA", /* B16 */
-		"I2C1_SCL", /* A16 */
-		"MMC0_CD", /* C15 */
-		"SPI1_SS2", /* C18 */
-		"EQEP_1A", /* V2 */
-		"EQEP_1B", /* V3 */
-		"MDIR_2B", /* V4 */
-		"BATT_LED_2", /* T5 */
-		"I2C2_SDA", /* D18 */
-		"I2C2_SCL", /* D17 */
-		"UART1_RX", /* D16 */
-		"UART1_TX", /* D15 */
-		"MMC2_DAT1", /* J18 */
-		"MMC2_DAT2", /* K15 */
-		"NC", /* F16 */
-		"WIFI_LED", /* A15 */
-		"MOT_STBY", /* D14 */
-		"WLAN_IRQ", /* K16 */
-		"PWM_2A", /* U10 */
-		"PWM_2B", /* T10 */
-		"",
-		"",
-		"BATT_LED_4", /* T11 */
-		"BATT_LED_1", /* U12 */
-		"BT_EN", /* K17 */
-		"SPI1_SS1", /* H18 */
-		"UART4_RX", /* T17 */
-		"MDIR_1B"; /* U17 */
-};
-
-&gpio1 {
-	gpio-line-names =
-		"MMC1_DAT0", /* U7 */
-		"MMC1_DAT1", /* V7 */
-		"MMC1_DAT2", /* R8 */
-		"MMC1_DAT3", /* T8 */
-		"MMC1_DAT4", /* U8 */
-		"MMC1_DAT5", /* V8 */
-		"MMC1_DAT6", /* R9 */
-		"MMC1_DAT7", /* T9 */
-		"DCAN1_TX", /* E18 */
-		"DCAN1_RX", /* E17 */
-		"UART0_RX", /* E15 */
-		"UART0_TX", /* E16 */
-		"EQEP_2A", /* T12 */
-		"EQEP_2B", /* R12 */
-		"PRU_E_A", /* V13 */
-		"PRU_E_B", /* U13 */
-		"MDIR_2A", /* R13 */
-		"GPIO1_17", /* V14 */
-		"PWM_1A", /* U14 */
-		"PWM_1B", /* T14 */
-		"EMMC_RST", /* R14 */
-		"USR_LED_0", /* V15 */
-		"USR_LED_1", /* U15 */
-		"USR_LED_2", /* T15 */
-		"USR_LED_3", /* V16 */
-		"GPIO1_25", /* U16 */
-		"MCASP0_AXR0", /* T16 */
-		"MCASP0_AXR1", /* V17 */
-		"MCASP0_ACLKR", /* U18 */
-		"BATT_LED_3", /* V6 */
-		"MMC1_CLK", /* U9 */
-		"MMC1_CMD"; /* V9 */
-};
-
-&gpio2 {
-	gpio-line-names =
-		"MDIR_1A", /* T13 */
-		"MCASP0_FSR", /* V12 */
-		"LED_RED", /* R7 */
-		"LED_GREEN", /* T7 */
-		"MODE_BTN", /* U6 */
-		"PAUSE_BTN", /* T6 */
-		"MDIR_4A", /* R1 */
-		"MDIR_4B", /* R2 */
-		"MDIR_3B", /* R3 */
-		"MDIR_3A", /* R4 */
-		"SVO7", /* T1 */
-		"SVO8", /* T2 */
-		"SVO5", /* T3 */
-		"SVO6", /* T4 */
-		"UART5_TX", /* U1 */
-		"UART5_RX", /* U2 */
-		"SERVO_EN", /* U3 */
-		"NC", /* U4 */
-		"UART3_RX", /* L17 */
-		"UART3_TX", /* L16 */
-		"MMC2_CLK", /* L15 */
-		"DCAN1_SILENT", /* M16 */
-		"SVO1", /* U5 */
-		"SVO3", /* R5 */
-		"SVO2", /* V5 */
-		"SVO4", /* R6 */
-		"MMC0_DAT3", /* F17 */
-		"MMC0_DAT2", /* F18 */
-		"MMC0_DAT1", /* G15 */
-		"MMC0_DAT0", /* G16 */
-		"MMC0_CLK", /* G17 */
-		"MMC0_CMD"; /* G18 */
-};
-
-&gpio3 {
-	gpio-line-names =
-		"MMC2_DAT3", /* H16 */
-		"GPIO3_1", /* H17 */
-		"GPIO3_2", /* J15 */
-		"MMC2_CMD", /* J16 */
-		"MMC2_DAT0", /* J17 */
-		"I2C0_SDA", /* C17 */
-		"I2C0_SCL", /* C16 */
-		"EMU1", /* C14 */
-		"EMU0", /* B14 */
-		"WL_EN", /* K18 */
-		"WL_BT_OE", /* L18 */
-		"",
-		"",
-		"NC", /* F15 */
-		"SPI1_SCK", /* A13 */
-		"SPI1_MISO", /* B13 */
-		"SPI1_MOSI", /* D12 */
-		"GPIO3_17", /* C12 */
-		"EQEP_0A", /* B12 */
-		"EQEP_0B", /* C13 */
-		"GPIO3_20", /* D13 */
-		"IMU_INT", /* A14 */
-		"",
-		"",
-		"",
-		"",
-		"",
-		"",
-		"",
-		"",
-		"",
-		"";
-
-	ls-buf-en-hog {
-		gpio-hog;
-		gpios = <10 GPIO_ACTIVE_HIGH>;
-		output-high;
-	};
-};
-
-&epwmss0 {
-	status = "okay";
-};
-
-&eqep0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&eqep0_pins>;
-	status = "okay";
-};
-
-&epwmss1 {
-	status = "okay";
-};
-
-&eqep1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&eqep1_pins>;
-	status = "okay";
-};
-
-&epwmss2 {
-	status = "okay";
-};
-
-&eqep2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&eqep2_pins>;
-	status = "okay";
-};

arch/arm/dts/am335x-bonegreen-eco-u-boot.dtsi

@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * am335x-bonegreen-eco U-Boot Additions
+ */
+
+#include "am335x-bone-common-u-boot.dtsi"

arch/arm/dts/am335x-bonegreen-eco.dts

@@ -1,53 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2025 Bootlin
- */
-/dts-v1/;
-
-#include "am33xx.dtsi"
-#include "am335x-bone-common.dtsi"
-#include "am335x-bonegreen-common.dtsi"
-#include <dt-bindings/net/ti-dp83867.h>
-
-/ {
-	model = "TI AM335x BeagleBone Green Eco";
-	compatible = "ti,am335x-bone-green-eco", "ti,am335x-bone-green",
-		     "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx";
-
-	cpus {
-		cpu@0 {
-			/delete-property/ cpu0-supply;
-		};
-	};
-};
-
-&usb0 {
-	interrupts-extended = <&intc 18>;
-	interrupt-names = "mc";
-};
-
-&cpsw_emac0 {
-	phy-mode = "rgmii-id";
-	phy-handle = <&dp83867_0>;
-};
-
-&davinci_mdio {
-	/delete-node/ ethernet-phy@0;
-
-	dp83867_0: ethernet-phy@0 {
-		reg = <0>;
-		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
-		ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
-		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
-		ti,min-output-impedance;
-		ti,dp83867-rxctrl-strap-quirk;
-	};
-};
-
-&baseboard_eeprom {
-	/delete-property/ vcc-supply;
-};
-
-&i2c0 {
-	/delete-node/ tps@24;
-};

arch/arm/dts/am335x-bonegreen-u-boot.dtsi

@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * am335x-bonegreen U-Boot Additions
+ */
+
+#include "am335x-bone-common-u-boot.dtsi"

arch/arm/dts/am335x-bonegreen-wireless-u-boot.dtsi

@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * am335x-bonegreen-wireless U-Boot Additions
+ */
+
+#include "am335x-bone-common-u-boot.dtsi"

arch/arm/dts/am335x-bonegreen-wireless.dts

@@ -1,127 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
- */
-/dts-v1/;
-
-#include "am33xx.dtsi"
-#include "am335x-bone-common.dtsi"
-#include "am335x-bonegreen-common.dtsi"
-#include <dt-bindings/interrupt-controller/irq.h>
-
-/ {
-	model = "TI AM335x BeagleBone Green Wireless";
-	compatible = "ti,am335x-bone-green-wireless", "ti,am335x-bone-green", "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx";
-
-	wlan_en_reg: fixedregulator@2 {
-		compatible = "regulator-fixed";
-		regulator-name = "wlan-en-regulator";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-		startup-delay-us = <70000>;
-
-		/* WL_EN */
-		gpio = <&gpio0 26 0>;
-		enable-active-high;
-	};
-};
-
-&am33xx_pinmux {
-	bt_pins: pinmux_bt_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_OUTPUT_PULLUP, MUX_MODE7)	/* gpmc_ad12.gpio1_28 BT_EN */
-		>;
-	};
-
-	mmc3_pins: pinmux_mmc3_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE3)	/* gpmc_ad12.mmc2_dat0 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE3)	/* gpmc_ad13.mmc2_dat1 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE3)	/* gpmc_ad14.mmc2_dat2 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE3)	/* gpmc_ad15.mmc2_dat3 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT_PULLUP, MUX_MODE3)	/* gpmc_csn3.mmc2_cmd */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE3)	/* gpmc_clk.mmc2_clk */
-		>;
-	};
-
-	uart3_pins: pinmux_uart3_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE1)	/* gmii1_rxd3.uart3_rxd */
-			AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE1)	/* gmii1_rxd2.uart3_txd */
-			AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT, MUX_MODE3)		/* mdio_data.uart3_ctsn */
-			AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLDOWN, MUX_MODE3)	/* mdio_clk.uart3_rtsn */
-		>;
-	};
-
-	wl18xx_pins: pinmux_wl18xx_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT_PULLDOWN, MUX_MODE7)	/* gpmc_ad10.gpio0_26 WL_EN */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLDOWN, MUX_MODE7)	/* gpmc_ad11.gpio0_27 WL_IRQ */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT_PULLUP, MUX_MODE7)	/* gpmc_csn0.gpio1_29 LS_BUF_EN */
-		>;
-	};
-};
-
-&mac {
-	status = "disabled";
-};
-
-&mmc3 {
-	dmas = <&edma_xbar 12 0 1
-		&edma_xbar 13 0 2>;
-	dma-names = "tx", "rx";
-	status = "okay";
-	vmmc-supply = <&wlan_en_reg>;
-	bus-width = <4>;
-	non-removable;
-	cap-power-off-card;
-	keep-power-in-suspend;
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc3_pins &wl18xx_pins>;
-
-	#address-cells = <1>;
-	#size-cells = <0>;
-	wlcore: wlcore@2 {
-		compatible = "ti,wl1835";
-		reg = <2>;
-		interrupt-parent = <&gpio0>;
-		interrupts = <27 IRQ_TYPE_EDGE_RISING>;
-	};
-};
-
-&uart3 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart3_pins &bt_pins>;
-	status = "okay";
-
-	bluetooth {
-		compatible = "ti,wl1835-st";
-		enable-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
-	};
-};
-
-&gpio1 {
-	ls-buf-en-hog {
-		gpio-hog;
-		gpios = <29 GPIO_ACTIVE_HIGH>;
-		output-high;
-		line-name = "LS_BUF_EN";
-	};
-};
-
-/* BT_AUD_OUT from wl1835 has to be pulled low when WL_EN is activated.*/
-/* in case it isn't, wilink8 ends up in one of the test modes that     */
-/* intruces various issues (elp wkaeup timeouts etc.)                  */
-/* On the BBGW this pin is routed through the level shifter (U21) that */
-/* introduces a pullup on the line and wilink8 ends up in a bad state. */
-/* use a gpio hog to force this pin low. An alternative may be adding  */
-/* an external pulldown on U21 pin 4.                                  */
-
-&gpio3 {
-	bt-aud-in-hog {
-		gpio-hog;
-		gpios = <16 GPIO_ACTIVE_HIGH>;
-		output-low;
-		line-name = "MCASP0_AHCLKR";
-	};
-};

arch/arm/dts/am335x-bonegreen.dts

@@ -1,14 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
- */
-/dts-v1/;
-
-#include "am33xx.dtsi"
-#include "am335x-bone-common.dtsi"
-#include "am335x-bonegreen-common.dtsi"
-
-/ {
-	model = "TI AM335x BeagleBone Green";
-	compatible = "ti,am335x-bone-green", "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx";
-};

arch/arm/dts/am335x-evm-u-boot.dtsi

@@ -5,6 +5,12 @@
 
 #include "am33xx-u-boot.dtsi"
 
+/ {
+	chosen {
+		tick-timer = &timer2;
+	};
+};
+
 &l4_per {
 	bootph-all;
 	segment@300000 {

arch/arm/dts/am335x-evm.dts

@@ -1,766 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
- */
-/dts-v1/;
-
-#include "am33xx.dtsi"
-#include <dt-bindings/interrupt-controller/irq.h>
-
-/ {
-	model = "TI AM335x EVM";
-	compatible = "ti,am335x-evm", "ti,am33xx";
-
-	chosen {
-		stdout-path = &uart0;
-		tick-timer = &timer2;
-	};
-
-	cpus {
-		cpu@0 {
-			cpu0-supply = <&vdd1_reg>;
-		};
-	};
-
-	memory@80000000 {
-		device_type = "memory";
-		reg = <0x80000000 0x10000000>; /* 256 MB */
-	};
-
-	vbat: fixedregulator0 {
-		compatible = "regulator-fixed";
-		regulator-name = "vbat";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		regulator-boot-on;
-	};
-
-	lis3_reg: fixedregulator1 {
-		compatible = "regulator-fixed";
-		regulator-name = "lis3_reg";
-		regulator-boot-on;
-	};
-
-	wlan_en_reg: fixedregulator2 {
-		compatible = "regulator-fixed";
-		regulator-name = "wlan-en-regulator";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-
-		/* WLAN_EN GPIO for this board - Bank1, pin16 */
-		gpio = <&gpio1 16 0>;
-
-		/* WLAN card specific delay */
-		startup-delay-us = <70000>;
-		enable-active-high;
-	};
-
-	matrix_keypad: matrix_keypad@0 {
-		compatible = "gpio-matrix-keypad";
-		debounce-delay-ms = <5>;
-		col-scan-delay-us = <2>;
-
-		row-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH		/* Bank1, pin25 */
-			     &gpio1 26 GPIO_ACTIVE_HIGH		/* Bank1, pin26 */
-			     &gpio1 27 GPIO_ACTIVE_HIGH>;	/* Bank1, pin27 */
-
-		col-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH		/* Bank1, pin21 */
-			     &gpio1 22 GPIO_ACTIVE_HIGH>;	/* Bank1, pin22 */
-
-		linux,keymap = <0x0000008b	/* MENU */
-				0x0100009e	/* BACK */
-				0x02000069	/* LEFT */
-				0x0001006a	/* RIGHT */
-				0x0101001c	/* ENTER */
-				0x0201006c>;	/* DOWN */
-	};
-
-	gpio_keys: volume-keys {
-		compatible = "gpio-keys";
-		autorepeat;
-
-		switch-9 {
-			label = "volume-up";
-			linux,code = <115>;
-			gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
-			gpio-key,wakeup;
-		};
-
-		switch-10 {
-			label = "volume-down";
-			linux,code = <114>;
-			gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
-			gpio-key,wakeup;
-		};
-	};
-
-	backlight {
-		compatible = "pwm-backlight";
-		pwms = <&ecap0 0 50000 0>;
-		brightness-levels = <0 51 53 56 62 75 101 152 255>;
-		default-brightness-level = <8>;
-	};
-
-	panel {
-		compatible = "ti,tilcdc,panel";
-		status = "okay";
-		pinctrl-names = "default";
-		pinctrl-0 = <&lcd_pins_s0>;
-		panel-info {
-			ac-bias           = <255>;
-			ac-bias-intrpt    = <0>;
-			dma-burst-sz      = <16>;
-			bpp               = <32>;
-			fdd               = <0x80>;
-			sync-edge         = <0>;
-			sync-ctrl         = <1>;
-			raster-order      = <0>;
-			fifo-th           = <0>;
-		};
-
-		display-timings {
-			800x480p62 {
-				clock-frequency = <30000000>;
-				hactive = <800>;
-				vactive = <480>;
-				hfront-porch = <39>;
-				hback-porch = <39>;
-				hsync-len = <47>;
-				vback-porch = <29>;
-				vfront-porch = <13>;
-				vsync-len = <2>;
-				hsync-active = <1>;
-				vsync-active = <1>;
-			};
-		};
-	};
-
-	sound {
-		compatible = "ti,da830-evm-audio";
-		ti,model = "AM335x-EVM";
-		ti,audio-codec = <&tlv320aic3106>;
-		ti,mcasp-controller = <&mcasp1>;
-		ti,codec-clock-rate = <12000000>;
-		ti,audio-routing =
-			"Headphone Jack",       "HPLOUT",
-			"Headphone Jack",       "HPROUT",
-			"LINE1L",               "Line In",
-			"LINE1R",               "Line In";
-	};
-};
-
-&am33xx_pinmux {
-	pinctrl-names = "default";
-	pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0 &clkout2_pin>;
-
-	matrix_keypad_s0: matrix_keypad_s0 {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7)	/* gpmc_a5.gpio1_21 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLDOWN, MUX_MODE7)	/* gpmc_a6.gpio1_22 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7)	/* gpmc_a9.gpio1_25 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7)	/* gpmc_a10.gpio1_26 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7)	/* gpmc_a11.gpio1_27 */
-		>;
-	};
-
-	volume_keys_s0: volume_keys_s0 {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLDOWN, MUX_MODE7)	/* spi0_sclk.gpio0_2 */
-			AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLDOWN, MUX_MODE7)	/* spi0_d0.gpio0_3 */
-		>;
-	};
-
-	i2c0_pins: pinmux_i2c0_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0)	/* i2c0_sda.i2c0_sda */
-			AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0)	/* i2c0_scl.i2c0_scl */
-		>;
-	};
-
-	i2c1_pins: pinmux_i2c1_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE2)	/* spi0_d1.i2c1_sda */
-			AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE2)	/* spi0_cs0.i2c1_scl */
-		>;
-	};
-
-	uart0_pins: pinmux_uart0_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
-		>;
-	};
-
-	uart1_pins: pinmux_uart1_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
-		>;
-	};
-
-	clkout2_pin: pinmux_clkout2_pin {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3)	/* xdma_event_intr1.clkout2 */
-		>;
-	};
-
-	nandflash_pins_s0: nandflash_pins_s0 {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7)	/* gpmc_wpn.gpio0_31 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0)
-		>;
-	};
-
-	ecap0_pins: backlight_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, 0x0, MUX_MODE0)
-		>;
-	};
-
-	cpsw_default: cpsw_default {
-		pinctrl-single,pins = <
-			/* Slave 1 */
-			AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* mii1_txen.rgmii1_tctl */
-			AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* mii1_rxdv.rgmii1_rctl */
-			AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* mii1_txd3.rgmii1_td3 */
-			AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* mii1_txd2.rgmii1_td2 */
-			AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* mii1_txd1.rgmii1_td1 */
-			AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* mii1_txd0.rgmii1_td0 */
-			AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* mii1_txclk.rgmii1_tclk */
-			AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* mii1_rxclk.rgmii1_rclk */
-			AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* mii1_rxd3.rgmii1_rd3 */
-			AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* mii1_rxd2.rgmii1_rd2 */
-			AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* mii1_rxd1.rgmii1_rd1 */
-			AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* mii1_rxd0.rgmii1_rd0 */
-		>;
-	};
-
-	cpsw_sleep: cpsw_sleep {
-		pinctrl-single,pins = <
-			/* Slave 1 reset value */
-			AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
-		>;
-	};
-
-	davinci_mdio_default: davinci_mdio_default {
-		pinctrl-single,pins = <
-			/* MDIO */
-			AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
-		>;
-	};
-
-	davinci_mdio_sleep: davinci_mdio_sleep {
-		pinctrl-single,pins = <
-			/* MDIO reset value */
-			AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)
-		>;
-	};
-
-	mmc1_pins: pinmux_mmc1_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7)		/* spi0_cs1.gpio0_6 */
-		>;
-	};
-
-	mmc3_pins: pinmux_mmc3_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLUP, MUX_MODE3)	/* gpmc_a1.mmc2_dat0, INPUT_PULLUP | MODE3 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLUP, MUX_MODE3)	/* gpmc_a2.mmc2_dat1, INPUT_PULLUP | MODE3 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_INPUT_PULLUP, MUX_MODE3)	/* gpmc_a3.mmc2_dat2, INPUT_PULLUP | MODE3 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLUP, MUX_MODE3)	/* gpmc_ben1.mmc2_dat3, INPUT_PULLUP | MODE3 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT_PULLUP, MUX_MODE3)	/* gpmc_csn3.mmc2_cmd, INPUT_PULLUP | MODE3 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE3)	/* gpmc_clk.mmc2_clk, INPUT_PULLUP | MODE3 */
-		>;
-	};
-
-	wlan_pins: pinmux_wlan_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE7)	/* gpmc_a0.gpio1_16 */
-			AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_INPUT, MUX_MODE7)		/* mcasp0_ahclkr.gpio3_17 */
-			AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE7)	/* mcasp0_ahclkx.gpio3_21 */
-		>;
-	};
-
-	lcd_pins_s0: lcd_pins_s0 {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE1)		/* gpmc_ad8.lcd_data23 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE1)		/* gpmc_ad9.lcd_data22 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE1)		/* gpmc_ad10.lcd_data21 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE1)		/* gpmc_ad11.lcd_data20 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE1)		/* gpmc_ad12.lcd_data19 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE1)		/* gpmc_ad13.lcd_data18 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE1)		/* gpmc_ad14.lcd_data17 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE1)		/* gpmc_ad15.lcd_data16 */
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0)
-		>;
-	};
-
-	mcasp1_pins: mcasp1_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
-			AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
-			AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_OUTPUT_PULLDOWN, MUX_MODE4) /* mii1_col.mcasp1_axr2 */
-			AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
-		>;
-	};
-
-	dcan1_pins_default: dcan1_pins_default {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT, MUX_MODE2) /* uart0_ctsn.d_can1_tx */
-			AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLDOWN, MUX_MODE2) /* uart0_rtsn.d_can1_rx */
-		>;
-	};
-};
-
-&uart0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart0_pins>;
-
-	status = "okay";
-};
-
-&uart1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart1_pins>;
-
-	status = "okay";
-};
-
-&i2c0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c0_pins>;
-
-	status = "okay";
-	clock-frequency = <400000>;
-
-	tps: tps@2d {
-		reg = <0x2d>;
-	};
-};
-
-&usb {
-	status = "okay";
-};
-
-&usb_ctrl_mod {
-	status = "okay";
-};
-
-&usb0_phy {
-	status = "okay";
-};
-
-&usb1_phy {
-	status = "okay";
-};
-
-&usb0 {
-	status = "okay";
-};
-
-&usb1 {
-	status = "okay";
-	dr_mode = "host";
-};
-
-&cppi41dma  {
-	status = "okay";
-};
-
-&i2c1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c1_pins>;
-
-	status = "okay";
-	clock-frequency = <100000>;
-
-	lis331dlh: lis331dlh@18 {
-		compatible = "st,lis331dlh", "st,lis3lv02d";
-		reg = <0x18>;
-		Vdd-supply = <&lis3_reg>;
-		Vdd_IO-supply = <&lis3_reg>;
-
-		st,click-single-x;
-		st,click-single-y;
-		st,click-single-z;
-		st,click-thresh-x = <10>;
-		st,click-thresh-y = <10>;
-		st,click-thresh-z = <10>;
-		st,irq1-click;
-		st,irq2-click;
-		st,wakeup-x-lo;
-		st,wakeup-x-hi;
-		st,wakeup-y-lo;
-		st,wakeup-y-hi;
-		st,wakeup-z-lo;
-		st,wakeup-z-hi;
-		st,min-limit-x = <120>;
-		st,min-limit-y = <120>;
-		st,min-limit-z = <140>;
-		st,max-limit-x = <550>;
-		st,max-limit-y = <550>;
-		st,max-limit-z = <750>;
-	};
-
-	tsl2550: tsl2550@39 {
-		compatible = "taos,tsl2550";
-		reg = <0x39>;
-	};
-
-	tmp275: tmp275@48 {
-		compatible = "ti,tmp275";
-		reg = <0x48>;
-	};
-
-	tlv320aic3106: tlv320aic3106@1b {
-		compatible = "ti,tlv320aic3106";
-		reg = <0x1b>;
-		status = "okay";
-
-		/* Regulators */
-		AVDD-supply = <&vaux2_reg>;
-		IOVDD-supply = <&vaux2_reg>;
-		DRVDD-supply = <&vaux2_reg>;
-		DVDD-supply = <&vbat>;
-	};
-};
-
-&lcdc {
-	status = "okay";
-};
-
-&elm {
-	status = "okay";
-};
-
-&epwmss0 {
-	status = "okay";
-
-	ecap0: pwm@100 {
-		status = "okay";
-		pinctrl-names = "default";
-		pinctrl-0 = <&ecap0_pins>;
-	};
-};
-
-&gpmc {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&nandflash_pins_s0>;
-	ranges = <0 0 0x08000000 0x1000000>;	/* CS0: 16MB for NAND */
-	nand@0,0 {
-		reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
-		ti,nand-ecc-opt = "bch8";
-		ti,elm-id = <&elm>;
-		nand-bus-width = <8>;
-		gpmc,device-width = <1>;
-		gpmc,sync-clk-ps = <0>;
-		gpmc,cs-on-ns = <0>;
-		gpmc,cs-rd-off-ns = <44>;
-		gpmc,cs-wr-off-ns = <44>;
-		gpmc,adv-on-ns = <6>;
-		gpmc,adv-rd-off-ns = <34>;
-		gpmc,adv-wr-off-ns = <44>;
-		gpmc,we-on-ns = <0>;
-		gpmc,we-off-ns = <40>;
-		gpmc,oe-on-ns = <0>;
-		gpmc,oe-off-ns = <54>;
-		gpmc,access-ns = <64>;
-		gpmc,rd-cycle-ns = <82>;
-		gpmc,wr-cycle-ns = <82>;
-		gpmc,wait-on-read = "true";
-		gpmc,wait-on-write = "true";
-		gpmc,bus-turnaround-ns = <0>;
-		gpmc,cycle2cycle-delay-ns = <0>;
-		gpmc,clk-activation-ns = <0>;
-		gpmc,wait-monitoring-ns = <0>;
-		gpmc,wr-access-ns = <40>;
-		gpmc,wr-data-mux-bus-ns = <0>;
-		/* MTD partition table */
-		/* All SPL-* partitions are sized to minimal length
-		 * which can be independently programmable. For
-		 * NAND flash this is equal to size of erase-block */
-		#address-cells = <1>;
-		#size-cells = <1>;
-		partition@0 {
-			label = "NAND.SPL";
-			reg = <0x00000000 0x00020000>;
-		};
-		partition@1 {
-			label = "NAND.SPL.backup1";
-			reg = <0x00020000 0x00020000>;
-		};
-		partition@2 {
-			label = "NAND.SPL.backup2";
-			reg = <0x00040000 0x00020000>;
-		};
-		partition@3 {
-			label = "NAND.SPL.backup3";
-			reg = <0x00060000 0x00020000>;
-		};
-		partition@4 {
-			label = "NAND.u-boot-spl-os";
-			reg = <0x00080000 0x00040000>;
-		};
-		partition@5 {
-			label = "NAND.u-boot";
-			reg = <0x000C0000 0x00100000>;
-		};
-		partition@6 {
-			label = "NAND.u-boot-env";
-			reg = <0x001C0000 0x00020000>;
-		};
-		partition@7 {
-			label = "NAND.u-boot-env.backup1";
-			reg = <0x001E0000 0x00020000>;
-		};
-		partition@8 {
-			label = "NAND.kernel";
-			reg = <0x00200000 0x00800000>;
-		};
-		partition@9 {
-			label = "NAND.file-system";
-			reg = <0x00A00000 0x0F600000>;
-		};
-	};
-};
-
-#include "tps65910.dtsi"
-
-&mcasp1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mcasp1_pins>;
-
-	status = "okay";
-
-	op-mode = <0>;          /* MCASP_IIS_MODE */
-	tdm-slots = <2>;
-	/* 4 serializers */
-	serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
-		0 0 1 2
-	>;
-	tx-num-evt = <32>;
-	rx-num-evt = <32>;
-};
-
-&tps {
-	vcc1-supply = <&vbat>;
-	vcc2-supply = <&vbat>;
-	vcc3-supply = <&vbat>;
-	vcc4-supply = <&vbat>;
-	vcc5-supply = <&vbat>;
-	vcc6-supply = <&vbat>;
-	vcc7-supply = <&vbat>;
-	vccio-supply = <&vbat>;
-
-	regulators {
-		vrtc_reg: regulator@0 {
-			regulator-always-on;
-		};
-
-		vio_reg: regulator@1 {
-			regulator-always-on;
-		};
-
-		vdd1_reg: regulator@2 {
-			/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
-			regulator-name = "vdd_mpu";
-			regulator-min-microvolt = <912500>;
-			regulator-max-microvolt = <1312500>;
-			regulator-boot-on;
-			regulator-always-on;
-		};
-
-		vdd2_reg: regulator@3 {
-			/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
-			regulator-name = "vdd_core";
-			regulator-min-microvolt = <912500>;
-			regulator-max-microvolt = <1150000>;
-			regulator-boot-on;
-			regulator-always-on;
-		};
-
-		vdd3_reg: regulator@4 {
-			regulator-always-on;
-		};
-
-		vdig1_reg: regulator@5 {
-			regulator-always-on;
-		};
-
-		vdig2_reg: regulator@6 {
-			regulator-always-on;
-		};
-
-		vpll_reg: regulator@7 {
-			regulator-always-on;
-		};
-
-		vdac_reg: regulator@8 {
-			regulator-always-on;
-		};
-
-		vaux1_reg: regulator@9 {
-			regulator-always-on;
-		};
-
-		vaux2_reg: regulator@10 {
-			regulator-always-on;
-		};
-
-		vaux33_reg: regulator@11 {
-			regulator-always-on;
-		};
-
-		vmmc_reg: regulator@12 {
-			regulator-min-microvolt = <1800000>;
-			regulator-max-microvolt = <3300000>;
-			regulator-always-on;
-		};
-	};
-};
-
-&mac {
-	pinctrl-names = "default", "sleep";
-	pinctrl-0 = <&cpsw_default>;
-	pinctrl-1 = <&cpsw_sleep>;
-	status = "okay";
-	slaves = <1>;
-};
-
-&davinci_mdio {
-	pinctrl-names = "default", "sleep";
-	pinctrl-0 = <&davinci_mdio_default>;
-	pinctrl-1 = <&davinci_mdio_sleep>;
-	status = "okay";
-
-	ethphy0: ethernet-phy@0 {
-		reg = <0>;
-	};
-};
-
-&cpsw_emac0 {
-	phy-handle = <&ethphy0>;
-	phy-mode = "rgmii-id";
-};
-
-&tscadc {
-	status = "okay";
-	tsc {
-		ti,wires = <4>;
-		ti,x-plate-resistance = <200>;
-		ti,coordinate-readouts = <5>;
-		ti,wire-config = <0x00 0x11 0x22 0x33>;
-		ti,charge-delay = <0x400>;
-	};
-
-	adc {
-		ti,adc-channels = <4 5 6 7>;
-	};
-};
-
-&mmc1 {
-	status = "okay";
-	vmmc-supply = <&vmmc_reg>;
-	bus-width = <4>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc1_pins>;
-	cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
-};
-
-&mmc3 {
-	/* these are on the crossbar and are outlined in the
-	   xbar-event-map element */
-	dmas = <&edma 12 0
-		&edma 13 0>;
-	dma-names = "tx", "rx";
-	status = "okay";
-	vmmc-supply = <&wlan_en_reg>;
-	bus-width = <4>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc3_pins &wlan_pins>;
-	ti,non-removable;
-	ti,needs-special-hs-handling;
-	cap-power-off-card;
-	keep-power-in-suspend;
-
-	#address-cells = <1>;
-	#size-cells = <0>;
-	wlcore: wlcore@0 {
-		compatible = "ti,wl1835";
-		reg = <2>;
-		interrupt-parent = <&gpio3>;
-		interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
-	};
-};
-
-&edma {
-	ti,edma-xbar-event-map = /bits/ 16 <1 12
-					    2 13>;
-};
-
-&sham {
-	status = "okay";
-};
-
-&aes {
-	status = "okay";
-};
-
-&dcan1 {
-	status = "disabled";	/* Enable only if Profile 1 is selected */
-	pinctrl-names = "default";
-	pinctrl-0 = <&dcan1_pins_default>;
-};
-
-&rtc {
-	clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
-	clock-names = "ext-clk", "int-clk";
-};

arch/arm/dts/am335x-evmsk-u-boot.dtsi

@@ -7,6 +7,12 @@
 
 #include "am33xx-u-boot.dtsi"
 
+/ {
+	chosen {
+		tick-timer = &timer2;
+	};
+};
+
 &l4_per {
 
 	segment@300000 {

arch/arm/dts/am335x-evmsk.dts

@@ -1,730 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-/*
- * AM335x Starter Kit
- * https://www.ti.com/tool/tmdssk3358
- */
-
-/dts-v1/;
-
-#include "am33xx.dtsi"
-#include <dt-bindings/pwm/pwm.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-
-/ {
-	model = "TI AM335x EVM-SK";
-	compatible = "ti,am335x-evmsk", "ti,am33xx";
-
-	chosen {
-		stdout-path = &uart0;
-		tick-timer = &timer2;
-	};
-
-	cpus {
-		cpu@0 {
-			cpu0-supply = <&vdd1_reg>;
-		};
-	};
-
-	memory@80000000 {
-		device_type = "memory";
-		reg = <0x80000000 0x10000000>; /* 256 MB */
-	};
-
-	vbat: fixedregulator0 {
-		compatible = "regulator-fixed";
-		regulator-name = "vbat";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		regulator-boot-on;
-	};
-
-	lis3_reg: fixedregulator1 {
-		compatible = "regulator-fixed";
-		regulator-name = "lis3_reg";
-		regulator-boot-on;
-	};
-
-	wl12xx_vmmc: fixedregulator2 {
-		pinctrl-names = "default";
-		pinctrl-0 = <&wl12xx_gpio>;
-		compatible = "regulator-fixed";
-		regulator-name = "vwl1271";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-		gpio = <&gpio1 29 0>;
-		startup-delay-us = <70000>;
-		enable-active-high;
-	};
-
-	vtt_fixed: fixedregulator3 {
-		compatible = "regulator-fixed";
-		regulator-name = "vtt";
-		regulator-min-microvolt = <1500000>;
-		regulator-max-microvolt = <1500000>;
-		gpio = <&gpio0 7 GPIO_ACTIVE_HIGH>;
-		regulator-always-on;
-		regulator-boot-on;
-		enable-active-high;
-	};
-
-	leds {
-		pinctrl-names = "default";
-		pinctrl-0 = <&user_leds_s0>;
-
-		compatible = "gpio-leds";
-
-		led1 {
-			label = "evmsk:green:usr0";
-			gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
-			default-state = "off";
-		};
-
-		led2 {
-			label = "evmsk:green:usr1";
-			gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
-			default-state = "off";
-		};
-
-		led3 {
-			label = "evmsk:green:mmc0";
-			gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
-			linux,default-trigger = "mmc0";
-			default-state = "off";
-		};
-
-		led4 {
-			label = "evmsk:green:heartbeat";
-			gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
-			linux,default-trigger = "heartbeat";
-			default-state = "off";
-		};
-	};
-
-	gpio_buttons: gpio_buttons0 {
-		compatible = "gpio-keys";
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		switch1 {
-			label = "button0";
-			linux,code = <0x100>;
-			gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
-		};
-
-		switch2 {
-			label = "button1";
-			linux,code = <0x101>;
-			gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
-		};
-
-		switch3 {
-			label = "button2";
-			linux,code = <0x102>;
-			gpios = <&gpio0 30 GPIO_ACTIVE_HIGH>;
-			wakeup-source;
-		};
-
-		switch4 {
-			label = "button3";
-			linux,code = <0x103>;
-			gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>;
-		};
-	};
-
-	lcd_bl: backlight {
-		compatible = "pwm-backlight";
-		pwms = <&ecap2 0 50000 PWM_POLARITY_INVERTED>;
-		brightness-levels = <0 58 61 66 75 90 125 170 255>;
-		default-brightness-level = <8>;
-	};
-
-	sound {
-		compatible = "simple-audio-card";
-		simple-audio-card,name = "AM335x-EVMSK";
-		simple-audio-card,widgets =
-			"Headphone", "Headphone Jack";
-		simple-audio-card,routing =
-			"Headphone Jack",	"HPLOUT",
-			"Headphone Jack",	"HPROUT";
-		simple-audio-card,format = "dsp_b";
-		simple-audio-card,bitclock-master = <&sound_master>;
-		simple-audio-card,frame-master = <&sound_master>;
-		simple-audio-card,bitclock-inversion;
-
-		simple-audio-card,cpu {
-			sound-dai = <&mcasp1>;
-		};
-
-		sound_master: simple-audio-card,codec {
-			sound-dai = <&tlv320aic3106>;
-			system-clock-frequency = <24000000>;
-		};
-	};
-
-	panel {
-		compatible = "ti,tilcdc,panel";
-		pinctrl-names = "default", "sleep";
-		pinctrl-0 = <&lcd_pins_default>;
-		pinctrl-1 = <&lcd_pins_sleep>;
-		status = "okay";
-		panel-info {
-			ac-bias           = <255>;
-			ac-bias-intrpt    = <0>;
-			dma-burst-sz      = <16>;
-			bpp               = <32>;
-			fdd               = <0x80>;
-			sync-edge         = <0>;
-			sync-ctrl         = <1>;
-			raster-order      = <0>;
-			fifo-th           = <0>;
-		};
-		display-timings {
-			480x272 {
-				hactive         = <480>;
-				vactive         = <272>;
-				hback-porch     = <43>;
-				hfront-porch    = <8>;
-				hsync-len       = <4>;
-				vback-porch     = <12>;
-				vfront-porch    = <4>;
-				vsync-len       = <10>;
-				clock-frequency = <9000000>;
-				hsync-active    = <0>;
-				vsync-active    = <0>;
-			};
-		};
-	};
-};
-
-&am33xx_pinmux {
-	pinctrl-names = "default";
-	pinctrl-0 = <&gpio_keys_s0 &clkout2_pin>;
-
-	lcd_pins_default: lcd_pins_default {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE1)	/* gpmc_ad8.lcd_data23 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE1)	/* gpmc_ad9.lcd_data22 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE1)	/* gpmc_ad10.lcd_data21 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE1)	/* gpmc_ad11.lcd_data20 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE1)	/* gpmc_ad12.lcd_data19 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE1)	/* gpmc_ad13.lcd_data18 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE1)	/* gpmc_ad14.lcd_data17 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE1)	/* gpmc_ad15.lcd_data16 */
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0)
-		>;
-	};
-
-	lcd_pins_sleep: lcd_pins_sleep {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLDOWN, MUX_MODE7)	/* gpmc_ad8.lcd_data23 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLDOWN, MUX_MODE7)	/* gpmc_ad9.lcd_data22 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLDOWN, MUX_MODE7)	/* gpmc_ad10.lcd_data21 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLDOWN, MUX_MODE7)	/* gpmc_ad11.lcd_data20 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLDOWN, MUX_MODE7)	/* gpmc_ad12.lcd_data19 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLDOWN, MUX_MODE7)	/* gpmc_ad13.lcd_data18 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLDOWN, MUX_MODE7)	/* gpmc_ad14.lcd_data17 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLDOWN, MUX_MODE7)	/* gpmc_ad15.lcd_data16 */
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PULL_DISABLE, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PULL_DISABLE, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PULL_DISABLE, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PULL_DISABLE, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PULL_DISABLE, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PULL_DISABLE, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PULL_DISABLE, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PULL_DISABLE, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PULL_DISABLE, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PULL_DISABLE, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PULL_DISABLE, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PULL_DISABLE, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PULL_DISABLE, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PULL_DISABLE, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PULL_DISABLE, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PULL_DISABLE, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
-		>;
-	};
-
-
-	user_leds_s0: user_leds_s0 {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_OUTPUT_PULLDOWN, MUX_MODE7)	/* gpmc_ad4.gpio1_4 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_OUTPUT_PULLDOWN, MUX_MODE7)	/* gpmc_ad5.gpio1_5 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_OUTPUT_PULLDOWN, MUX_MODE7)	/* gpmc_ad6.gpio1_6 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_OUTPUT_PULLDOWN, MUX_MODE7)	/* gpmc_ad7.gpio1_7 */
-		>;
-	};
-
-	gpio_keys_s0: gpio_keys_s0 {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_INPUT_PULLDOWN, MUX_MODE7)	/* gpmc_oen_ren.gpio2_3 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_INPUT_PULLDOWN, MUX_MODE7)	/* gpmc_advn_ale.gpio2_2 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE7)	/* gpmc_wait0.gpio0_30 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_INPUT_PULLDOWN, MUX_MODE7)	/* gpmc_ben0_cle.gpio2_5 */
-		>;
-	};
-
-	i2c0_pins: pinmux_i2c0_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0)
-		>;
-	};
-
-	uart0_pins: pinmux_uart0_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
-		>;
-	};
-
-	clkout2_pin: pinmux_clkout2_pin {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3)	/* xdma_event_intr1.clkout2 */
-		>;
-	};
-
-	ecap2_pins: backlight_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, 0x0, MUX_MODE4)	/* mcasp0_ahclkr.ecap2_in_pwm2_out */
-		>;
-	};
-
-	cpsw_default: cpsw_default {
-		pinctrl-single,pins = <
-			/* Slave 1 */
-			AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* mii1_txen.rgmii1_tctl */
-			AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* mii1_rxdv.rgmii1_rctl */
-			AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* mii1_txd3.rgmii1_td3 */
-			AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* mii1_txd2.rgmii1_td2 */
-			AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* mii1_txd1.rgmii1_td1 */
-			AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* mii1_txd0.rgmii1_td0 */
-			AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* mii1_txclk.rgmii1_tclk */
-			AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* mii1_rxclk.rgmii1_rclk */
-			AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* mii1_rxd3.rgmii1_rd3 */
-			AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* mii1_rxd2.rgmii1_rd2 */
-			AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* mii1_rxd1.rgmii1_rd1 */
-			AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* mii1_rxd0.rgmii1_rd0 */
-
-			/* Slave 2 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* gpmc_a0.rgmii2_tctl */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* gpmc_a1.rgmii2_rctl */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* gpmc_a2.rgmii2_td3 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* gpmc_a3.rgmii2_td2 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* gpmc_a4.rgmii2_td1 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* gpmc_a5.rgmii2_td0 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* gpmc_a6.rgmii2_tclk */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* gpmc_a7.rgmii2_rclk */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* gpmc_a8.rgmii2_rd3 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* gpmc_a9.rgmii2_rd2 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* gpmc_a10.rgmii2_rd1 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* gpmc_a11.rgmii2_rd0 */
-		>;
-	};
-
-	cpsw_sleep: cpsw_sleep {
-		pinctrl-single,pins = <
-			/* Slave 1 reset value */
-			AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
-
-			/* Slave 2 reset value*/
-			AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7)
-		>;
-	};
-
-	davinci_mdio_default: davinci_mdio_default {
-		pinctrl-single,pins = <
-			/* MDIO */
-			AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
-		>;
-	};
-
-	davinci_mdio_sleep: davinci_mdio_sleep {
-		pinctrl-single,pins = <
-			/* MDIO reset value */
-			AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)
-		>;
-	};
-
-	mmc1_pins: pinmux_mmc1_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) 		/* spi0_cs1.gpio0_6 */
-		>;
-	};
-
-	mcasp1_pins: mcasp1_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
-			AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
-			AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_OUTPUT_PULLDOWN, MUX_MODE4) /* mii1_col.mcasp1_axr2 */
-			AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
-		>;
-	};
-
-	mcasp1_pins_sleep: mcasp1_pins_sleep {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
-		>;
-	};
-
-	mmc2_pins: pinmux_mmc2_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_31 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
-		>;
-	};
-
-	wl12xx_gpio: pinmux_wl12xx_gpio {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_csn0.gpio1_29 */
-		>;
-	};
-};
-
-&uart0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart0_pins>;
-
-	status = "okay";
-};
-
-&i2c0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c0_pins>;
-
-	status = "okay";
-	clock-frequency = <400000>;
-
-	tps: tps@2d {
-		reg = <0x2d>;
-	};
-
-	lis331dlh: lis331dlh@18 {
-		compatible = "st,lis331dlh", "st,lis3lv02d";
-		reg = <0x18>;
-		Vdd-supply = <&lis3_reg>;
-		Vdd_IO-supply = <&lis3_reg>;
-
-		st,click-single-x;
-		st,click-single-y;
-		st,click-single-z;
-		st,click-thresh-x = <10>;
-		st,click-thresh-y = <10>;
-		st,click-thresh-z = <10>;
-		st,irq1-click;
-		st,irq2-click;
-		st,wakeup-x-lo;
-		st,wakeup-x-hi;
-		st,wakeup-y-lo;
-		st,wakeup-y-hi;
-		st,wakeup-z-lo;
-		st,wakeup-z-hi;
-		st,min-limit-x = <120>;
-		st,min-limit-y = <120>;
-		st,min-limit-z = <140>;
-		st,max-limit-x = <550>;
-		st,max-limit-y = <550>;
-		st,max-limit-z = <750>;
-	};
-
-	tlv320aic3106: tlv320aic3106@1b {
-		#sound-dai-cells = <0>;
-		compatible = "ti,tlv320aic3106";
-		reg = <0x1b>;
-		status = "okay";
-
-		/* Regulators */
-		AVDD-supply = <&vaux2_reg>;
-		IOVDD-supply = <&vaux2_reg>;
-		DRVDD-supply = <&vaux2_reg>;
-		DVDD-supply = <&vbat>;
-	};
-};
-
-&usb {
-	status = "okay";
-};
-
-&usb_ctrl_mod {
-	status = "okay";
-};
-
-&usb0_phy {
-	status = "okay";
-};
-
-&usb1_phy {
-	status = "okay";
-};
-
-&usb0 {
-	status = "okay";
-};
-
-&usb1 {
-	status = "okay";
-	dr_mode = "host";
-};
-
-&cppi41dma  {
-	status = "okay";
-};
-
-&epwmss2 {
-	status = "okay";
-
-	ecap2: pwm@100 {
-		status = "okay";
-		pinctrl-names = "default";
-		pinctrl-0 = <&ecap2_pins>;
-	};
-};
-
-#include "tps65910.dtsi"
-
-&tps {
-	vcc1-supply = <&vbat>;
-	vcc2-supply = <&vbat>;
-	vcc3-supply = <&vbat>;
-	vcc4-supply = <&vbat>;
-	vcc5-supply = <&vbat>;
-	vcc6-supply = <&vbat>;
-	vcc7-supply = <&vbat>;
-	vccio-supply = <&vbat>;
-
-	regulators {
-		vrtc_reg: regulator@0 {
-			regulator-always-on;
-		};
-
-		vio_reg: regulator@1 {
-			regulator-always-on;
-		};
-
-		vdd1_reg: regulator@2 {
-			/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
-			regulator-name = "vdd_mpu";
-			regulator-min-microvolt = <912500>;
-			regulator-max-microvolt = <1312500>;
-			regulator-boot-on;
-			regulator-always-on;
-		};
-
-		vdd2_reg: regulator@3 {
-			/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
-			regulator-name = "vdd_core";
-			regulator-min-microvolt = <912500>;
-			regulator-max-microvolt = <1150000>;
-			regulator-boot-on;
-			regulator-always-on;
-		};
-
-		vdd3_reg: regulator@4 {
-			regulator-always-on;
-		};
-
-		vdig1_reg: regulator@5 {
-			regulator-always-on;
-		};
-
-		vdig2_reg: regulator@6 {
-			regulator-always-on;
-		};
-
-		vpll_reg: regulator@7 {
-			regulator-always-on;
-		};
-
-		vdac_reg: regulator@8 {
-			regulator-always-on;
-		};
-
-		vaux1_reg: regulator@9 {
-			regulator-always-on;
-		};
-
-		vaux2_reg: regulator@10 {
-			regulator-always-on;
-		};
-
-		vaux33_reg: regulator@11 {
-			regulator-always-on;
-		};
-
-		vmmc_reg: regulator@12 {
-			regulator-min-microvolt = <1800000>;
-			regulator-max-microvolt = <3300000>;
-			regulator-always-on;
-		};
-	};
-};
-
-&mac {
-	pinctrl-names = "default", "sleep";
-	pinctrl-0 = <&cpsw_default>;
-	pinctrl-1 = <&cpsw_sleep>;
-	dual_emac = <1>;
-	status = "okay";
-};
-
-&davinci_mdio {
-	pinctrl-names = "default", "sleep";
-	pinctrl-0 = <&davinci_mdio_default>;
-	pinctrl-1 = <&davinci_mdio_sleep>;
-	status = "okay";
-
-	ethphy0: ethernet-phy@0 {
-		reg = <0>;
-	};
-
-	ethphy1: ethernet-phy@1 {
-		reg = <1>;
-	};
-};
-
-&cpsw_emac0 {
-	phy-handle = <&ethphy0>;
-	phy-mode = "rgmii-id";
-	dual_emac_res_vlan = <1>;
-};
-
-&cpsw_emac1 {
-	phy-handle = <&ethphy1>;
-	phy-mode = "rgmii-id";
-	dual_emac_res_vlan = <2>;
-};
-
-&mmc1 {
-	status = "okay";
-	vmmc-supply = <&vmmc_reg>;
-	bus-width = <4>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc1_pins>;
-	cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
-};
-
-&sham {
-	status = "okay";
-};
-
-&aes {
-	status = "okay";
-};
-
-&gpio0 {
-	ti,no-reset-on-init;
-};
-
-&mmc2 {
-	status = "okay";
-	vmmc-supply = <&wl12xx_vmmc>;
-	ti,non-removable;
-	bus-width = <4>;
-	cap-power-off-card;
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc2_pins>;
-
-	#address-cells = <1>;
-	#size-cells = <0>;
-	wlcore: wlcore@2 {
-		compatible = "ti,wl1271";
-		reg = <2>;
-		interrupt-parent = <&gpio0>;
-		interrupts = <31 IRQ_TYPE_LEVEL_HIGH>; /* gpio 31 */
-		ref-clock-frequency = <38400000>;
-	};
-};
-
-&mcasp1 {
-	#sound-dai-cells = <0>;
-	pinctrl-names = "default", "sleep";
-	pinctrl-0 = <&mcasp1_pins>;
-	pinctrl-1 = <&mcasp1_pins_sleep>;
-
-	status = "okay";
-
-	op-mode = <0>;          /* MCASP_IIS_MODE */
-	tdm-slots = <2>;
-	/* 4 serializers */
-	serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
-		0 0 1 2
-	>;
-	tx-num-evt = <32>;
-	rx-num-evt = <32>;
-};
-
-&tscadc {
-	status = "okay";
-	tsc {
-		ti,wires = <4>;
-		ti,x-plate-resistance = <200>;
-		ti,coordinate-readouts = <5>;
-		ti,wire-config = <0x00 0x11 0x22 0x33>;
-	};
-};
-
-&lcdc {
-	status = "okay";
-};
-
-&rtc {
-	clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
-	clock-names = "ext-clk", "int-clk";
-};

arch/arm/dts/am335x-icev2-u-boot.dtsi

@@ -6,6 +6,10 @@
 #include "am33xx-u-boot.dtsi"
 
 / {
+	chosen {
+		tick-timer = &timer2;
+	};
+
 	xtal25mhz: xtal25mhz {
 		compatible = "fixed-clock";
 		#clock-cells = <0>;

arch/arm/dts/am335x-icev2.dts

@@ -1,486 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-/*
- * AM335x ICE V2 board
- * https://www.ti.com/tool/tmdsice3359
- */
-
-/dts-v1/;
-
-#include "am33xx.dtsi"
-
-/ {
-	model = "TI AM3359 ICE-V2";
-	compatible = "ti,am3359-icev2", "ti,am33xx";
-
-	chosen {
-		stdout-path = &uart3;
-		tick-timer = &timer2;
-	};
-
-	memory@80000000 {
-		device_type = "memory";
-		reg = <0x80000000 0x10000000>; /* 256 MB */
-	};
-
-	vbat: fixedregulator0 {
-		compatible = "regulator-fixed";
-		regulator-name = "vbat";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		regulator-boot-on;
-	};
-
-	vtt_fixed: fixedregulator1 {
-		compatible = "regulator-fixed";
-		regulator-name = "vtt";
-		regulator-min-microvolt = <1500000>;
-		regulator-max-microvolt = <1500000>;
-		gpio = <&gpio0 18 GPIO_ACTIVE_HIGH>;
-		regulator-always-on;
-		regulator-boot-on;
-		enable-active-high;
-	};
-
-	leds-iio {
-		compatible = "gpio-leds";
-		led-out0 {
-			label = "out0";
-			gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>;
-			default-state = "off";
-		};
-
-		led-out1 {
-			label = "out1";
-			gpios = <&tpic2810 1 GPIO_ACTIVE_HIGH>;
-			default-state = "off";
-		};
-
-		led-out2 {
-			label = "out2";
-			gpios = <&tpic2810 2 GPIO_ACTIVE_HIGH>;
-			default-state = "off";
-		};
-
-		led-out3 {
-			label = "out3";
-			gpios = <&tpic2810 3 GPIO_ACTIVE_HIGH>;
-			default-state = "off";
-		};
-
-		led-out4 {
-			label = "out4";
-			gpios = <&tpic2810 4 GPIO_ACTIVE_HIGH>;
-			default-state = "off";
-		};
-
-		led-out5 {
-			label = "out5";
-			gpios = <&tpic2810 5 GPIO_ACTIVE_HIGH>;
-			default-state = "off";
-		};
-
-		led-out6 {
-			label = "out6";
-			gpios = <&tpic2810 6 GPIO_ACTIVE_HIGH>;
-			default-state = "off";
-		};
-
-		led-out7 {
-			label = "out7";
-			gpios = <&tpic2810 7 GPIO_ACTIVE_HIGH>;
-			default-state = "off";
-		};
-	};
-
-	/* Tricolor status LEDs */
-	leds1 {
-		compatible = "gpio-leds";
-		pinctrl-names = "default";
-		pinctrl-0 = <&user_leds>;
-
-		led0 {
-			label = "status0:red:cpu0";
-			gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>;
-			default-state = "off";
-			linux,default-trigger = "cpu0";
-		};
-
-		led1 {
-			label = "status0:green:usr";
-			gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
-			default-state = "off";
-		};
-
-		led2 {
-			label = "status0:yellow:usr";
-			gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>;
-			default-state = "off";
-		};
-
-		led3 {
-			label = "status1:red:mmc0";
-			gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
-			default-state = "off";
-			linux,default-trigger = "mmc0";
-		};
-
-		led4 {
-			label = "status1:green:usr";
-			gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
-			default-state = "off";
-		};
-
-		led5 {
-			label = "status1:yellow:usr";
-			gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>;
-			default-state = "off";
-		};
-	};
-};
-
-&am33xx_pinmux {
-	user_leds: user_leds {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT, MUX_MODE7) /* (J18) gmii1_txd3.gpio0[16] */
-			AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT, MUX_MODE7) /* (K15) gmii1_txd2.gpio0[17] */
-			AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE7) /* (A15) xdma_event_intr0.gpio0[19] */
-			AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT, MUX_MODE7) /* (D14) xdma_event_intr1.gpio0[20] */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_OUTPUT, MUX_MODE7) /* (U9) gpmc_csn1.gpio1[30] */
-			AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT, MUX_MODE7) /* (K18) gmii1_txclk.gpio3[9] */
-		>;
-	};
-
-	mmc0_pins_default: mmc0_pins_default {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)
-			AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE5) /* (C15) spi0_cs1.mmc0_sdcd */
-		>;
-	};
-
-	i2c0_pins_default: i2c0_pins_default {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0)
-		>;
-	};
-
-	spi0_pins_default: spi0_pins_default {
-		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE0) /* (A17) spi0_sclk.spi0_sclk */
-			AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE0) /* (B17) spi0_d0.spi0_d0 */
-			AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) /* (B16) spi0_d1.spi0_d1 */
-			AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE0) /* (A16) spi0_cs0.spi0_cs0 */
-		>;
-	};
-
-	uart3_pins_default: uart3_pins_default {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE1) /* (L17) gmii1_rxd3.uart3_rxd */
-			AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLUP, MUX_MODE1) /* (L16) gmii1_rxd2.uart3_txd */
-		>;
-	};
-
-	cpsw_default: cpsw_default {
-		pinctrl-single,pins = <
-			/* Slave 1, RMII mode */
-			AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLUP, MUX_MODE1)	/* mii1_crs.rmii1_crs_dv */
-			AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE1)
-			AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE1)
-			AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE1)	/* mii1_rxerr.rmii1_rxerr */
-			AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1)	/* mii1_txd0.rmii1_txd0 */
-			AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1)	/* mii1_txd1.rmii1_txd1 */
-			AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1)	/* mii1_txen.rmii1_txen */
-			/* Slave 2, RMII mode */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE3)	/* gpmc_wait0.rmii2_crs_dv */
-			AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLUP, MUX_MODE1)	/* mii1_col.rmii2_refclk */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLUP, MUX_MODE3)	/* gpmc_a11.rmii2_rxd0 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLUP, MUX_MODE3)	/* gpmc_a10.rmii2_rxd1 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE3)	/* gpmc_wpn.rmii2_rxerr */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE3)	/* gpmc_a5.rmii2_txd0 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE3)	/* gpmc_a4.rmii2_txd1 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE3)	/* gpmc_a0.rmii2_txen */
-		>;
-	};
-
-	cpsw_sleep: cpsw_sleep {
-		pinctrl-single,pins = <
-			/* Slave 1 reset value */
-			AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
-
-			/* Slave 2 reset value */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7)
-		>;
-	};
-
-	davinci_mdio_default: davinci_mdio_default {
-		pinctrl-single,pins = <
-			/* MDIO */
-			AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
-		>;
-	};
-
-	davinci_mdio_sleep: davinci_mdio_sleep {
-		pinctrl-single,pins = <
-			/* MDIO reset value */
-			AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)
-		>;
-	};
-};
-
-&i2c0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c0_pins_default>;
-
-	status = "okay";
-	clock-frequency = <400000>;
-
-	tps: power-controller@2d {
-		reg = <0x2d>;
-	};
-
-	tpic2810: gpio@60 {
-		compatible = "ti,tpic2810";
-		reg = <0x60>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
-};
-
-&spi0 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&spi0_pins_default>;
-
-	sn65hvs882@1 {
-		compatible = "pisosr-gpio";
-		gpio-controller;
-		#gpio-cells = <2>;
-
-		load-gpios = <&gpio3 18 GPIO_ACTIVE_LOW>;
-
-		reg = <1>;
-		spi-max-frequency = <1000000>;
-		spi-cpol;
-	};
-
-	spi_nor: flash@0 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "winbond,w25q64", "jedec,spi-nor";
-		spi-max-frequency = <80000000>;
-		m25p,fast-read;
-		reg = <0>;
-
-		partition@0 {
-			label = "u-boot-spl";
-			reg = <0x0 0x80000>;
-			read-only;
-		};
-
-		partition@1 {
-			label = "u-boot";
-			reg = <0x80000 0x100000>;
-			read-only;
-		};
-
-		partition@2 {
-			label = "u-boot-env";
-			reg = <0x180000 0x20000>;
-			read-only;
-		};
-
-		partition@3 {
-			label = "misc";
-			reg = <0x1A0000 0x660000>;
-		};
-	};
-};
-
-#include "tps65910.dtsi"
-
-&tps {
-	vcc1-supply = <&vbat>;
-	vcc2-supply = <&vbat>;
-	vcc3-supply = <&vbat>;
-	vcc4-supply = <&vbat>;
-	vcc5-supply = <&vbat>;
-	vcc6-supply = <&vbat>;
-	vcc7-supply = <&vbat>;
-	vccio-supply = <&vbat>;
-
-	regulators {
-		vrtc_reg: regulator@0 {
-			regulator-always-on;
-		};
-
-		vio_reg: regulator@1 {
-			regulator-always-on;
-		};
-
-		vdd1_reg: regulator@2 {
-			regulator-name = "vdd_mpu";
-			regulator-min-microvolt = <912500>;
-			regulator-max-microvolt = <1326000>;
-			regulator-boot-on;
-			regulator-always-on;
-		};
-
-		vdd2_reg: regulator@3 {
-			regulator-name = "vdd_core";
-			regulator-min-microvolt = <912500>;
-			regulator-max-microvolt = <1144000>;
-			regulator-boot-on;
-			regulator-always-on;
-		};
-
-		vdd3_reg: regulator@4 {
-			regulator-always-on;
-		};
-
-		vdig1_reg: regulator@5 {
-			regulator-always-on;
-		};
-
-		vdig2_reg: regulator@6 {
-			regulator-always-on;
-		};
-
-		vpll_reg: regulator@7 {
-			regulator-always-on;
-		};
-
-		vdac_reg: regulator@8 {
-			regulator-always-on;
-		};
-
-		vaux1_reg: regulator@9 {
-			regulator-always-on;
-		};
-
-		vaux2_reg: regulator@10 {
-			regulator-always-on;
-		};
-
-		vaux33_reg: regulator@11 {
-			regulator-always-on;
-		};
-
-		vmmc_reg: regulator@12 {
-			regulator-min-microvolt = <1800000>;
-			regulator-max-microvolt = <3300000>;
-			regulator-always-on;
-		};
-	};
-};
-
-&mmc1 {
-	status = "okay";
-	vmmc-supply = <&vmmc_reg>;
-	bus-width = <4>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins_default>;
-};
-
-&gpio0 {
-	/* Do not idle the GPIO used for holding the VTT regulator */
-	ti,no-reset-on-init;
-	ti,no-idle-on-init;
-
-	p7 {
-		gpio-hog;
-		gpios = <7 GPIO_ACTIVE_HIGH>;
-		output-high;
-		line-name = "FET_SWITCH_CTRL";
-	};
-};
-
-&uart3 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart3_pins_default>;
-	status = "okay";
-};
-
-&gpio3 {
-	pr1-mii-ctl-hog {
-		gpio-hog;
-		gpios = <4 GPIO_ACTIVE_HIGH>;
-		output-high;
-		line-name = "PR1_MII_CTRL";
-	};
-
-	mux-mii-hog {
-		gpio-hog;
-		gpios = <10 GPIO_ACTIVE_HIGH>;
-		/* ETH1 mux: Low for MII-PRU, high for RMII-CPSW */
-		output-high;
-		line-name = "MUX_MII_CTRL";
-	};
-};
-
-&cpsw_emac0 {
-	phy-handle = <&ethphy0>;
-	phy-mode = "rmii";
-	dual_emac_res_vlan = <1>;
-};
-
-&cpsw_emac1 {
-	phy-handle = <&ethphy1>;
-	phy-mode = "rmii";
-	dual_emac_res_vlan = <2>;
-};
-
-&mac {
-	pinctrl-names = "default", "sleep";
-	pinctrl-0 = <&cpsw_default>;
-	pinctrl-1 = <&cpsw_sleep>;
-	status = "okay";
-	dual_emac;
-};
-
-&phy_sel {
-	rmii-clock-ext;
-};
-
-&davinci_mdio {
-	pinctrl-names = "default", "sleep";
-	pinctrl-0 = <&davinci_mdio_default>;
-	pinctrl-1 = <&davinci_mdio_sleep>;
-	status = "okay";
-	reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
-	reset-delay-us = <2>;   /* PHY datasheet states 1uS min */
-
-	ethphy0: ethernet-phy@1 {
-		reg = <1>;
-	};
-
-	ethphy1: ethernet-phy@3 {
-		reg = <3>;
-	};
-};
-

arch/arm/dts/am335x-pocketbeagle-u-boot.dtsi

@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * am335x-pocketbeagle U-Boot Additions
+ */
+
+#include "am335x-bone-common-u-boot.dtsi"

arch/arm/dts/am335x-pocketbeagle.dts

@@ -1,237 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
- *
- * Author: Robert Nelson <robertcnelson@gmail.com>
- */
-/dts-v1/;
-
-#include "am33xx.dtsi"
-#include "am335x-osd335x-common.dtsi"
-
-/ {
-	model = "TI AM335x PocketBeagle";
-	compatible = "ti,am335x-pocketbeagle", "ti,am335x-bone", "ti,am33xx";
-
-	chosen {
-		stdout-path = &uart0;
-	};
-
-	leds {
-		pinctrl-names = "default";
-		pinctrl-0 = <&usr_leds_pins>;
-
-		compatible = "gpio-leds";
-
-		led-usr0 {
-			label = "beaglebone:green:usr0";
-			gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
-			linux,default-trigger = "heartbeat";
-			default-state = "off";
-		};
-
-		led-usr1 {
-			label = "beaglebone:green:usr1";
-			gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>;
-			linux,default-trigger = "mmc0";
-			default-state = "off";
-		};
-
-		led-usr2 {
-			label = "beaglebone:green:usr2";
-			gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
-			linux,default-trigger = "cpu0";
-			default-state = "off";
-		};
-
-		led-usr3 {
-			label = "beaglebone:green:usr3";
-			gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
-			default-state = "off";
-		};
-	};
-
-	vmmcsd_fixed: fixedregulator0 {
-		compatible = "regulator-fixed";
-		regulator-name = "vmmcsd_fixed";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-	};
-};
-
-&am33xx_pinmux {
-	i2c2_pins: pinmux-i2c2-pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3)	/* (D17) uart1_rtsn.I2C2_SCL */
-			AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3)	/* (D18) uart1_ctsn.I2C2_SDA */
-		>;
-	};
-
-	ehrpwm0_pins: pinmux-ehrpwm0-pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE1)	/* (A13) mcasp0_aclkx.ehrpwm0A */
-		>;
-	};
-
-	ehrpwm1_pins: pinmux-ehrpwm1-pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT_PULLDOWN, MUX_MODE6)	/* (U14) gpmc_a2.ehrpwm1A */
-		>;
-	};
-
-	mmc0_pins: pinmux-mmc0-pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7)		/* (C15) spi0_cs1.gpio0[6] */
-			AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
-			AM33XX_IOPAD(0x9a0, PIN_INPUT | MUX_MODE4)		/* (B12) mcasp0_aclkr.mmc0_sdwp */
-		>;
-	};
-
-	spi0_pins: pinmux-spi0-pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0)
-		>;
-	};
-
-	spi1_pins: pinmux-spi1-pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_INPUT_PULLUP, MUX_MODE4)	/* (C18) eCAP0_in_PWM0_out.spi1_sclk */
-			AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLUP, MUX_MODE4)	/* (E18) uart0_ctsn.spi1_d0 */
-			AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE4)	/* (E17) uart0_rtsn.spi1_d1 */
-			AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_INPUT_PULLUP, MUX_MODE4)	/* (A15) xdma_event_intr0.spi1_cs1 */
-		>;
-	};
-
-	usr_leds_pins: pinmux-usr-leds-pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE7)		/* (V15) gpmc_a5.gpio1[21] - USR_LED_0 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT, MUX_MODE7)		/* (U15) gpmc_a6.gpio1[22] - USR_LED_1 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT, MUX_MODE7)		/* (T15) gpmc_a7.gpio1[23] - USR_LED_2 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT, MUX_MODE7)		/* (V16) gpmc_a8.gpio1[24] - USR_LED_3 */
-		>;
-	};
-
-	uart0_pins: pinmux-uart0-pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
-		>;
-	};
-
-	uart4_pins: pinmux-uart4-pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE6)	/* (T17) gpmc_wait0.uart4_rxd */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_OUTPUT_PULLDOWN, MUX_MODE6)	/* (U17) gpmc_wpn.uart4_txd */
-		>;
-	};
-};
-
-&epwmss0 {
-	status = "okay";
-};
-
-&ehrpwm0 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&ehrpwm0_pins>;
-};
-
-&epwmss1 {
-	status = "okay";
-};
-
-&ehrpwm1 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&ehrpwm1_pins>;
-};
-
-&i2c0 {
-	eeprom: eeprom@50 {
-		compatible = "atmel,24c256";
-		reg = <0x50>;
-	};
-};
-
-&i2c2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c2_pins>;
-
-	status = "okay";
-	clock-frequency = <400000>;
-};
-
-&mmc1 {
-	status = "okay";
-	vmmc-supply = <&vmmcsd_fixed>;
-	bus-width = <4>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins>;
-	cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
-};
-
-&rtc {
-	system-power-controller;
-};
-
-&tscadc {
-	status = "okay";
-	adc {
-		ti,adc-channels = <0 1 2 3 4 5 6 7>;
-		ti,chan-step-avg = <16 16 16 16 16 16 16 16>;
-		ti,chan-step-opendelay = <0x98 0x98 0x98 0x98 0x98 0x98 0x98 0x98>;
-		ti,chan-step-sampledelay = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
-	};
-};
-
-&uart0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart0_pins>;
-
-	status = "okay";
-};
-
-&uart4 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart4_pins>;
-
-	status = "okay";
-};
-
-&usb {
-	status = "okay";
-};
-
-&usb_ctrl_mod {
-	status = "okay";
-};
-
-&usb0_phy {
-	status = "okay";
-};
-
-&usb0 {
-	status = "okay";
-	dr_mode = "otg";
-};
-
-&usb1_phy {
-	status = "okay";
-};
-
-&usb1 {
-	status = "okay";
-	dr_mode = "host";
-};
-
-&cppi41dma  {
-	status = "okay";
-};

arch/arm/dts/am335x-sancloud-bbe-common.dtsi

@@ -1,67 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-&am33xx_pinmux {
-	cpsw_default: cpsw_default {
-		pinctrl-single,pins = <
-			/* Slave 1 */
-			AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* mii1_txen.rgmii1_tctl */
-			AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* mii1_rxdv.rgmii1_rctl */
-			AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* mii1_txd3.rgmii1_td3 */
-			AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* mii1_txd2.rgmii1_td2 */
-			AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* mii1_txd1.rgmii1_td1 */
-			AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* mii1_txd0.rgmii1_td0 */
-			AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* mii1_txclk.rgmii1_tclk */
-			AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* mii1_rxclk.rgmii1_rclk */
-			AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* mii1_rxd3.rgmii1_rd3 */
-			AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* mii1_rxd2.rgmii1_rd2 */
-			AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* mii1_rxd1.rgmii1_rd1 */
-			AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* mii1_rxd0.rgmii1_rd0 */
-		>;
-	};
-
-	cpsw_sleep: cpsw_sleep {
-		pinctrl-single,pins = <
-			/* Slave 1 reset value */
-			AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
-		>;
-	};
-
-	usb_hub_ctrl: usb_hub_ctrl {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_OUTPUT_PULLUP, MUX_MODE7)     /* rmii1_refclk.gpio0_29 */
-		>;
-	};
-};
-
-&mac {
-	pinctrl-0 = <&cpsw_default>;
-	pinctrl-1 = <&cpsw_sleep>;
-};
-
-&cpsw_emac0 {
-	phy-mode = "rgmii-id";
-};
-
-&i2c0 {
-	usb2512b: usb-hub@2c {
-		pinctrl-names = "default";
-		pinctrl-0 = <&usb_hub_ctrl>;
-		compatible = "microchip,usb2512b";
-		reg = <0x2c>;
-		reset-gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
-	};
-};

arch/arm/dts/am335x-sancloud-bbe-extended-wifi-u-boot.dtsi

@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * am335x-sancloud-bbe-extended-wifi U-Boot Additions
+ */
+
+#include "am335x-sancloud-bbe-u-boot.dtsi"

arch/arm/dts/am335x-sancloud-bbe-extended-wifi.dts

@@ -1,113 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2021 Sancloud Ltd
- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
- */
-/dts-v1/;
-
-#include "am33xx.dtsi"
-#include "am335x-bone-common.dtsi"
-#include "am335x-boneblack-common.dtsi"
-#include "am335x-sancloud-bbe-common.dtsi"
-#include <dt-bindings/interrupt-controller/irq.h>
-
-/ {
-	model = "SanCloud BeagleBone Enhanced Extended WiFi";
-	compatible = "sancloud,am335x-boneenhanced",
-		     "ti,am335x-bone-black",
-		     "ti,am335x-bone",
-		     "ti,am33xx";
-
-	wlan_en_reg: fixedregulator@2 {
-		compatible = "regulator-fixed";
-		regulator-name = "wlan-en-regulator";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		startup-delay-us = <100000>;
-	};
-};
-
-&am33xx_pinmux {
-	mmc3_pins: pinmux_mmc3_pins {
-		pinctrl-single,pins = <
-			/* gpmc_a9.gpio1_25: RADIO_EN */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_OUTPUT_PULLUP, MUX_MODE7)
-
-			/* gpmc_ad12.mmc2_dat0 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE3)
-
-			/* gpmc_ad13.mmc2_dat1 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE3)
-
-			/* gpmc_ad14.mmc2_dat2 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE3)
-
-			/* gpmc_ad15.mmc2_dat3 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE3)
-
-			/* gpmc_csn3.mmc2_cmd */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT_PULLUP, MUX_MODE3)
-
-			/* gpmc_clk.mmc2_clk */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE3)
-		>;
-	};
-
-	bluetooth_pins: pinmux_bluetooth_pins {
-		pinctrl-single,pins = <
-			/* event_intr0.gpio0_19 */
-			AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_INPUT_PULLUP, MUX_MODE7)
-		>;
-	};
-
-	uart1_pins: pinmux_uart1_pins {
-		pinctrl-single,pins = <
-			/* uart1_rxd */
-			AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0)
-
-			/* uart1_txd */
-			AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT, MUX_MODE0)
-
-			/* uart1_ctsn */
-			AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0)
-
-			/* uart1_rtsn */
-			AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
-		>;
-	};
-};
-
-&i2c2 {
-	status = "disabled";
-};
-
-&mmc3 {
-	status = "okay";
-	vmmc-supply = <&wlan_en_reg>;
-	bus-width = <4>;
-	non-removable;
-	cap-power-off-card;
-	ti,needs-special-hs-handling;
-	keep-power-in-suspend;
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc3_pins>;
-	dmas = <&edma_xbar 12 0 1
-		&edma_xbar 13 0 2>;
-	dma-names = "tx", "rx";
-	clock-frequency = <50000000>;
-	max-frequency = <50000000>;
-};
-
-&uart1 {
-	status = "okay";
-
-	bluetooth {
-		pinctrl-names = "default";
-		pinctrl-0 = <&uart1_pins &bluetooth_pins>;
-		compatible = "qcom,qca6174-bt";
-		enable-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>;
-		clocks = <&l4ls_clkctrl AM3_L4LS_UART2_CLKCTRL 0>;
-		interrupt-parent = <&gpio0>;
-		interrupts = <19 IRQ_TYPE_EDGE_RISING>;
-	};
-};

arch/arm/dts/am335x-sancloud-bbe-lite.dts

@@ -1,50 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
- * Copyright (C) 2021 SanCloud Ltd
- */
-/dts-v1/;
-
-#include "am33xx.dtsi"
-#include "am335x-bone-common.dtsi"
-#include "am335x-boneblack-common.dtsi"
-#include "am335x-sancloud-bbe-common.dtsi"
-
-/ {
-	model = "SanCloud BeagleBone Enhanced Lite";
-	compatible = "sancloud,am335x-boneenhanced",
-		     "ti,am335x-bone-black",
-		     "ti,am335x-bone",
-		     "ti,am33xx";
-};
-
-&am33xx_pinmux {
-	bb_spi0_pins: pinmux_bb_spi0_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT, MUX_MODE0)
-		>;
-	};
-};
-
-&spi0 {
-	#address-cells = <1>;
-	#size-cells = <0>;
-
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&bb_spi0_pins>;
-
-	channel@0 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		compatible = "micron,spi-authenta", "jedec,spi-nor";
-
-		reg = <0>;
-		spi-max-frequency = <16000000>;
-		spi-cpha;
-	};
-};

arch/arm/dts/am335x-sancloud-bbe.dts

@@ -1,53 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
- */
-/dts-v1/;
-
-#include "am33xx.dtsi"
-#include "am335x-bone-common.dtsi"
-#include "am335x-boneblack-common.dtsi"
-#include "am335x-boneblack-hdmi.dtsi"
-#include "am335x-sancloud-bbe-common.dtsi"
-#include <dt-bindings/interrupt-controller/irq.h>
-
-/ {
-	model = "SanCloud BeagleBone Enhanced";
-	compatible = "sancloud,am335x-boneenhanced", "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx";
-};
-
-&am33xx_pinmux {
-	mpu6050_pins: pinmux_mpu6050_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT, MUX_MODE7)    /* uart0_ctsn.gpio1_8 */
-		>;
-	};
-
-	lps3331ap_pins: pinmux_lps3331ap_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT, MUX_MODE7)     /* gpmc_a10.gpio1_26 */
-		>;
-	};
-};
-
-&i2c0 {
-	lps331ap: barometer@5c {
-		pinctrl-names = "default";
-		pinctrl-0 = <&lps3331ap_pins>;
-		compatible = "st,lps331ap-press";
-		st,drdy-int-pin = <1>;
-		reg = <0x5c>;
-		interrupt-parent = <&gpio1>;
-		interrupts = <26 IRQ_TYPE_EDGE_RISING>;
-	};
-
-	mpu6050: accelerometer@68 {
-		pinctrl-names = "default";
-		pinctrl-0 = <&mpu6050_pins>;
-		compatible = "invensense,mpu6050";
-		reg = <0x68>;
-		interrupt-parent = <&gpio0>;
-		interrupts = <2 IRQ_TYPE_EDGE_RISING>;
-		orientation = <0xff 0 0 0 1 0 0 0 0xff>;
-	};
-};

arch/arm/dts/armada-8040-nbx-u-boot.dtsi

@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2026 Free Mobile, Vincent Jardin
+ */
+
+#ifdef CONFIG_OPTEE
+/ {
+	firmware {
+		optee {
+			compatible = "linaro,optee-tz";
+			method = "smc";
+		};
+	};
+};
+#endif

arch/arm/dts/armada-8040-nbx.dts

@@ -0,0 +1,259 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Device Tree file for NBX board (Freebox Nodebox10G)
+ * Based on Marvell Armada 8040 SoC
+ *
+ * Copyright (C) 2024
+ */
+
+#include "armada-8040.dtsi"
+
+/ {
+	model = "NBX Armada 8040";
+	compatible = "nbx,armada8040", "marvell,armada8040";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	aliases {
+		i2c0 = &cp0_i2c0;
+		i2c1 = &cp0_i2c1;
+		gpio0 = &ap_gpio0;
+		gpio1 = &cp0_gpio0;
+		gpio2 = &cp0_gpio1;
+	};
+
+	memory@00000000 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x80000000>;  /* 2GB */
+	};
+};
+
+/* AP806 UART - active */
+&uart0 {
+	status = "okay";
+};
+
+/* AP806 pinctrl */
+&ap_pinctl {
+	/*
+	 * MPP Bus:
+	 * eMMC  [0-10]
+	 * UART0 [11,19]
+	 */
+		  /* 0 1 2 3 4 5 6 7 8 9 */
+	pin-func = < 1 1 1 1 1 1 1 1 1 1
+		     1 3 0 0 0 0 0 0 0 3 >;
+};
+
+/* AP806 on-board eMMC */
+&ap_sdhci0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&ap_emmc_pins>;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+
+/* CP0 pinctrl */
+&cp0_pinctl {
+	/*
+	 * MPP Bus:
+	 * [0-31]  = 0xff: Keep default CP0_shared_pins
+	 * [32,34] GE_MDIO/MDC
+	 * [35-36] I2C1
+	 * [37-38] I2C0
+	 * [57-58] MSS I2C
+	 */
+		/*   0    1    2    3    4    5    6    7    8    9 */
+	pin-func = < 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
+		     0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
+		     0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
+		     0xff 0xff 7    0    7    2    2    2    2    0
+		     0    0    0    0    0    0    0    0    0    0
+		     0    0    0    0    0    0    0    2    2    0
+		     0    0    0 >;
+
+	cp0_smi_pins: cp0-smi-pins {
+		marvell,pins = <32 34>;
+		marvell,function = <7>;
+	};
+};
+
+/* CP0 I2C0 */
+&cp0_i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&cp0_i2c0_pins>;
+	status = "okay";
+	clock-frequency = <100000>;
+};
+
+/* CP0 I2C1 */
+&cp0_i2c1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&cp0_i2c1_pins>;
+	status = "okay";
+	clock-frequency = <100000>;
+};
+
+/* CP0 MSS I2C0 - Management SubSystem I2C (pins 57-58, func 2) */
+&cp0_mss_i2c0 {
+	status = "okay";
+};
+
+/* CP0 MDIO for PHY */
+&cp0_mdio {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&cp0_smi_pins>;
+
+	nbx_phy0: ethernet-phy@0 {
+		reg = <0>;
+	};
+};
+
+/* CP0 ComPhy - SerDes configuration */
+&cp0_comphy {
+	/*
+	 * CP0 Serdes Configuration:
+	 * Lane 0-3: Unconnected
+	 * Lane 4:   SFI (10G Ethernet)
+	 * Lane 5:   SGMII2 (1G Ethernet)
+	 */
+	phy0 {
+		phy-type = <COMPHY_TYPE_UNCONNECTED>;
+	};
+	phy1 {
+		phy-type = <COMPHY_TYPE_UNCONNECTED>;
+	};
+	phy2 {
+		phy-type = <COMPHY_TYPE_UNCONNECTED>;
+	};
+	phy3 {
+		phy-type = <COMPHY_TYPE_UNCONNECTED>;
+	};
+	phy4 {
+		phy-type = <COMPHY_TYPE_SFI0>;
+		phy-speed = <COMPHY_SPEED_10_3125G>;
+	};
+	phy5 {
+		phy-type = <COMPHY_TYPE_SGMII2>;
+		phy-speed = <COMPHY_SPEED_1_25G>;
+	};
+};
+
+/* CP0 Ethernet - only eth2 (MAC3) is active via SGMII */
+&cp0_ethernet {
+	status = "okay";
+};
+
+&cp0_eth2 {
+	status = "okay";
+	phy = <&nbx_phy0>;
+	phy-mode = "sgmii";
+};
+
+/* CP0 UTMI PHY for USB */
+&cp0_utmi {
+	status = "okay";
+};
+
+&cp0_utmi0 {
+	status = "okay";
+};
+
+&cp0_utmi1 {
+	status = "okay";
+};
+
+/* CP0 USB3 Host controllers */
+&cp0_usb3_0 {
+	status = "okay";
+};
+
+&cp0_usb3_1 {
+	status = "okay";
+};
+
+/* CP1 pinctrl */
+&cp1_pinctl {
+	/*
+	 * MPP Bus:
+	 * [0-26]  = Unconfigured
+	 * [27-28] GE_MDIO/MDC
+	 * [29-30] MSS I2C
+	 * [31]    = Unconfigured
+	 * [32-62] = 0xff: Keep default CP1_shared_pins
+	 */
+		/*   0    1    2    3    4    5    6    7    8    9 */
+	pin-func = < 0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x0
+		     0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x0
+		     0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x8  0x8  0x8
+		     0x8  0x0  0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
+		     0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
+		     0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
+		     0xff 0xff 0xff>;
+
+	cp1_mss_i2c_pins: cp1-mss-i2c-pins {
+		marvell,pins = <29 30>;
+		marvell,function = <8>;
+	};
+};
+
+/* CP1 MSS I2C0 - Management SubSystem I2C (pins 29-30, func 8) */
+&cp1_mss_i2c0 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&cp1_mss_i2c_pins>;
+};
+
+/* CP1 ComPhy - SerDes configuration */
+&cp1_comphy {
+	/*
+	 * CP1 Serdes Configuration:
+	 * Lane 0:   PCIe x1
+	 * Lane 1:   USB3 Host
+	 * Lane 2-3: Unconnected
+	 * Lane 4:   SFI (10G Ethernet)
+	 * Lane 5:   Unconnected
+	 */
+	phy0 {
+		phy-type = <COMPHY_TYPE_PEX0>;
+	};
+	phy1 {
+		phy-type = <COMPHY_TYPE_USB3_HOST0>;
+	};
+	phy2 {
+		phy-type = <COMPHY_TYPE_UNCONNECTED>;
+	};
+	phy3 {
+		phy-type = <COMPHY_TYPE_UNCONNECTED>;
+	};
+	phy4 {
+		phy-type = <COMPHY_TYPE_SFI0>;
+		phy-speed = <COMPHY_SPEED_10_3125G>;
+	};
+	phy5 {
+		phy-type = <COMPHY_TYPE_UNCONNECTED>;
+	};
+};
+
+/* CP1 PCIe x1 on lane 0 */
+&cp1_pcie0 {
+	status = "okay";
+};
+
+/* CP1 USB3 Host on lane 1 */
+&cp1_usb3_0 {
+	status = "okay";
+};
+
+/* CP1 UTMI PHY for USB */
+&cp1_utmi {
+	status = "okay";
+};
+
+&cp1_utmi0 {
+	status = "okay";
+};

arch/arm/dts/armada-xp-atl-x220.dts

@@ -0,0 +1,162 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree file for x220 board
+ *
+ * Copyright (C) 2025 Allied Telesis Labs
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include "armada-xp-98dx3236.dtsi"
+#include "mvebu-u-boot.dtsi"
+
+/ {
+	model = "x220";
+	compatible = "marvell,armadaxp-98dx3236", "marvell,armadaxp-mv78260",
+		     "marvell,armadaxp", "marvell,armada-370-xp";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+		bootargs = "console=ttyS0,115200";
+	};
+
+	aliases {
+		i2c0 = &i2c0;
+		spi0 = &spi0;
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
+	};
+};
+
+&L2 {
+	arm,parity-enable;
+	marvell,ecc-enable;
+};
+
+&devbus_bootcs {
+	status = "okay";
+
+	/* Device Bus parameters are required */
+
+	/* Read parameters */
+	devbus,bus-width    = <16>;
+	devbus,turn-off-ps  = <60000>;
+	devbus,badr-skew-ps = <0>;
+	devbus,acc-first-ps = <124000>;
+	devbus,acc-next-ps  = <248000>;
+	devbus,rd-setup-ps  = <0>;
+	devbus,rd-hold-ps   = <0>;
+
+	/* Write parameters */
+	devbus,sync-enable = <0>;
+	devbus,wr-high-ps  = <60000>;
+	devbus,wr-low-ps   = <60000>;
+	devbus,ale-wr-ps   = <60000>;
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&i2c0 {
+	clock-frequency = <100000>;
+	status = "okay";
+
+	rtc@68 {
+		compatible = "dallas,ds1340";
+		reg = <0x68>;
+	};
+
+	adt7476a@2e {
+		compatible = "adi,adt7476";
+		reg = <0x2e>;
+	};
+
+	sfpgpio: gpio@27 {
+		#address-cells = <2>;
+		#size-cells = <0>;
+		compatible = "nxp,pca9555";
+		reg = <0x27>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	systemgpio: gpio@25 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "nxp,pca9555";
+		reg = <0x25>;
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		nand-protect {
+			gpio-hog;
+			gpios = <6 GPIO_ACTIVE_HIGH>;
+			output-high;
+			line-name = "nand-protect";
+		};
+
+		usb-enable {
+			gpio-hog;
+			gpios = <9 GPIO_ACTIVE_HIGH>;
+			output-high;
+			line-name = "usb-enable";
+		};
+
+		phy-reset {
+			gpio-hog;
+			gpios = <5 GPIO_ACTIVE_LOW>;
+			output-high;
+			line-name = "phy-reset";
+		};
+
+		led-enable {
+			gpio-hog;
+			gpios = <13 GPIO_ACTIVE_HIGH>;
+			output-low;
+			line-name = "led-enable";
+		};
+	};
+};
+
+&watchdog {
+	status = "okay";
+};
+
+&usb0 {
+	status = "okay";
+};
+
+&spi0 {
+	status = "okay";
+
+	spi-flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-flash", "jedec,spi-nor";
+		reg = <0>; /* Chip select 0 */
+		spi-max-frequency = <20000000>;
+	};
+};
+
+&nand_controller {
+	compatible = "marvell,armada370-nand-controller";
+	label = "pxa3xx_nand-0";
+	status = "okay";
+	nand-rb = <0>;
+	nand-on-flash-bbt;
+	nand-ecc-strength = <4>;
+	nand-ecc-step-size = <512>;
+};
+
+&{/} {
+	boot-board {
+		compatible = "atl,boot-board";
+		present-gpio = <&systemgpio 12 GPIO_ACTIVE_HIGH>;
+		override-gpio = <&gpio0 31 GPIO_ACTIVE_HIGH>;
+	};
+};
+

arch/arm/dts/armada-xp-db-xc3-24g4xg-u-boot.dtsi

@@ -5,7 +5,6 @@
 	status = "okay";
 	label = "pxa3xx_nand-0";
 	nand-rb = <0>;
-	marvell,nand-keep-config;
 	nand-on-flash-bbt;
 	nand-ecc-strength = <4>;
 	nand-ecc-step-size = <512>;

arch/arm/dts/ax3005-scm3005.dts

@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2021-2026 Axiado Corporation (or its affiliates).
+ */
+
+/dts-v1/;
+
+#include "ax3005.dtsi"
+
+/ {
+	model = "Axiado AX3005 SCM3005";
+	compatible = "axiado,ax3005-scm3005", "axiado,ax3005";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	chosen {
+		stdout-path = "serial3:115200";
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x00 0x80000000 0x00 0x80000000>;
+	};
+};
+
+&uart3 {
+	status = "okay";
+};

arch/arm/dts/ax3005.dtsi

@@ -0,0 +1,100 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2021-2026 Axiado Corporation (or its affiliates).
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/memreserve/ 0x80002fa0 0x00000008;
+
+/ {
+	aliases {
+		serial3 = &uart3;
+	};
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			compatible = "arm,cortex-a53";
+			device_type = "cpu";
+			reg = <0x0 0x0>;
+			enable-method = "spin-table";
+			cpu-release-addr = <0x0 0x80002fa0>;
+		};
+		cpu1: cpu@1 {
+			compatible = "arm,cortex-a53";
+			device_type = "cpu";
+			reg = <0x0 0x1>;
+			enable-method = "spin-table";
+			cpu-release-addr = <0x0 0x80002fa0>;
+		};
+		cpu2: cpu@2 {
+			compatible = "arm,cortex-a53";
+			device_type = "cpu";
+			reg = <0x0 0x2>;
+			enable-method = "spin-table";
+			cpu-release-addr = <0x0 0x80002fa0>;
+		};
+		cpu3: cpu@3 {
+			compatible = "arm,cortex-a53";
+			device_type = "cpu";
+			reg = <0x0 0x3>;
+			enable-method = "spin-table";
+			cpu-release-addr = <0x0 0x80002fa0>;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupt-parent = <&gic500>;
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+		clock-frequency = <1000000000>;
+	};
+
+	clocks {
+		refclk: refclk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <125000000>;
+			bootph-pre-reloc;
+		};
+	};
+
+	soc: soc {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		interrupt-parent = <&gic500>;
+		ranges;
+
+		gic500: interrupt-controller@40400000 {
+			compatible = "arm,gic-v3";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+			#interrupt-cells = <3>;
+			interrupt-controller;
+			#redistributor-regions = <1>;
+			reg = <0x00 0x40400000 0x00 0x10000>,
+			      <0x00 0x40500000 0x00 0xc0000>;
+			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		uart3: serial@33020800 {
+			compatible = "cdns,uart-r1p12", "xlnx,xuartps";
+			interrupt-parent = <&gic500>;
+			interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0x00 0x33020800 0x00 0x100>;
+			clock-names = "uart_clk", "pclk";
+			clocks = <&refclk &refclk>;
+			bootph-pre-reloc;
+			status = "disabled";
+		};
+	};
+};

arch/arm/dts/fsl-lx2160a.dtsi

@@ -292,7 +292,7 @@
 		#interrupt-cells = <2>;
 	};
 
-	watchdog@23a0000 {
+	wdt0: watchdog@23a0000 {
 		compatible = "arm,sbsa-gwdt";
 		reg = <0x0 0x23a0000 0 0x1000>,
 		      <0x0 0x2390000 0 0x1000>;
@@ -594,6 +594,64 @@
 		};
 	};
 
+	/* LX2160ARM Chapter 28 ("Thermal Monitoring Unit") */
+	tmu: tmu@1f80000 {
+		compatible = "fsl,qoriq-tmu";
+		reg = <0x0 0x1f80000 0x0 0x10000>;
+		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+		fsl,tmu-range = <0x800000e6 0x8001017d>;
+		fsl,tmu-calibration = <0x00000000 0x00000035
+				       0x00000001 0x00000154>;
+		little-endian;
+		#thermal-sensor-cells = <1>;
+		label = "lx2160a-tmu"; /* explicit naming */
+	};
+
+	/* explicit thermal-zones names per LX2160ARM Table 323 */
+	thermal-zones {
+		cluster67-thermal {
+			polling-delay-passive = <1000>;
+			polling-delay = <5000>;
+			thermal-sensors = <&tmu 0>;
+		};
+
+		ddr1-cluster5-thermal {
+			polling-delay-passive = <1000>;
+			polling-delay = <5000>;
+			thermal-sensors = <&tmu 1>;
+		};
+
+		wriop-thermal {
+			polling-delay-passive = <1000>;
+			polling-delay = <5000>;
+			thermal-sensors = <&tmu 2>;
+		};
+
+		dce-qbman-hsio2-thermal {
+			polling-delay-passive = <1000>;
+			polling-delay = <5000>;
+			thermal-sensors = <&tmu 3>;
+		};
+
+		ccn-dpaa-tbu-thermal {
+			polling-delay-passive = <1000>;
+			polling-delay = <5000>;
+			thermal-sensors = <&tmu 4>;
+		};
+
+		cluster4-hsio3-thermal {
+			polling-delay-passive = <1000>;
+			polling-delay = <5000>;
+			thermal-sensors = <&tmu 5>;
+		};
+
+		cluster23-thermal {
+			polling-delay-passive = <1000>;
+			polling-delay = <5000>;
+			thermal-sensors = <&tmu 6>;
+		};
+	};
+
 	/* WRIOP0: 0x8b8_0000, E-MDIO1: 0x1_6000 */
 	emdio1: mdio@8b96000 {
 		compatible = "fsl,ls-mdio";

arch/arm/dts/fsl-lx2162a-qds.dts

@@ -37,105 +37,6 @@
 	status = "disabled";
 };
 
-&dspi0 {
-	bus-num = <0>;
-	status = "okay";
-
-	dflash0: n25q128a@0 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "jedec,spi-nor";
-		spi-max-frequency = <3000000>;
-		spi-cpol;
-		spi-cpha;
-		reg = <0>;
-	};
-	dflash1: sst25wf040b@1 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "jedec,spi-nor";
-		spi-max-frequency = <3000000>;
-		spi-cpol;
-		spi-cpha;
-		reg = <1>;
-	};
-	dflash2: en25s64@2 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "jedec,spi-nor";
-		spi-max-frequency = <3000000>;
-		spi-cpol;
-		spi-cpha;
-		reg = <2>;
-	};
-};
-
-&dspi1 {
-	bus-num = <0>;
-	status = "okay";
-
-	dflash3: n25q128a@0 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "jedec,spi-nor";
-		spi-max-frequency = <3000000>;
-		spi-cpol;
-		spi-cpha;
-		reg = <0>;
-	};
-	dflash4: sst25wf040b@1 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "jedec,spi-nor";
-		spi-max-frequency = <3000000>;
-		spi-cpol;
-		spi-cpha;
-		reg = <1>;
-	};
-	dflash5: en25s64@2 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "jedec,spi-nor";
-		spi-max-frequency = <3000000>;
-		spi-cpol;
-		spi-cpha;
-		reg = <2>;
-	};
-};
-
-&dspi2 {
-	bus-num = <0>;
-	status = "okay";
-
-	dflash6: n25q128a@0 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "jedec,spi-nor";
-		spi-max-frequency = <3000000>;
-		spi-cpol;
-		spi-cpha;
-		reg = <0>;
-	};
-	dflash7: sst25wf040b@1 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "jedec,spi-nor";
-		spi-max-frequency = <3000000>;
-		spi-cpol;
-		spi-cpha;
-		reg = <1>;
-	};
-	dflash8: en25s64@2 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "jedec,spi-nor";
-		spi-max-frequency = <3000000>;
-		spi-cpol;
-		spi-cpha;
-		reg = <2>;
-	};
-};
-
 &esdhc1 {
 	mmc-hs200-1_8v;
 	mmc-hs400-1_8v;

arch/arm/dts/mt8189.dtsi

@@ -381,6 +381,83 @@
 			#reset-cells = <1>;
 		};
 
+		eth: ethernet@1101a000 {
+			compatible = "mediatek,mt8189-gmac", "snps,dwmac-5.10a";
+			reg = <0 0x1101a000 0 0x4000>;
+			interrupts = <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH 0>;
+			interrupt-names = "macirq";
+			clock-names = "mac_main",
+				      "ptp_ref";
+			clocks = <&topckgen_clk CLK_TOP_ETH_250M_SEL>,
+				 <&topckgen_clk CLK_TOP_ETH_62P4M_PTP_SEL>;
+			assigned-clocks = <&topckgen_clk CLK_TOP_ETH_250M_SEL>,
+					  <&topckgen_clk CLK_TOP_ETH_62P4M_PTP_SEL>,
+					  <&topckgen_clk CLK_TOP_ETH_50M_RMII_SEL>;
+			assigned-clock-parents = <&topckgen_clk CLK_TOP_ETHPLL_D2>,
+						 <&topckgen_clk CLK_TOP_ETHPLL_D8>,
+						 <&topckgen_clk CLK_TOP_ETHPLL_D10>;
+			mediatek,pericfg = <&pericfg_ao_clk>;
+			snps,axi-config = <&stmmac_axi_setup>;
+			snps,mtl-rx-config = <&mtl_rx_setup>;
+			snps,mtl-tx-config = <&mtl_tx_setup>;
+			snps,txpbl = <16>;
+			snps,rxpbl = <16>;
+			clk-csr = <4>;
+			status = "disabled";
+
+			stmmac_axi_setup: stmmac-axi-config {
+				snps,wr-osr-lmt = <0x7>;
+				snps,rd-osr-lmt = <0x7>;
+				snps,blen = <0 0 0 0 16 8 4>;
+			};
+
+			mtl_rx_setup: rx-queues-config {
+				snps,rx-queues-to-use = <4>;
+				snps,rx-sched-sp;
+				queue0 {
+					snps,dcb-algorithm;
+					snps,map-to-dma-channel = <0x0>;
+				};
+				queue1 {
+					snps,dcb-algorithm;
+					snps,map-to-dma-channel = <0x0>;
+				};
+				queue2 {
+					snps,dcb-algorithm;
+					snps,map-to-dma-channel = <0x0>;
+				};
+				queue3 {
+					snps,dcb-algorithm;
+					snps,map-to-dma-channel = <0x0>;
+				};
+			};
+
+			mtl_tx_setup: tx-queues-config {
+				snps,tx-queues-to-use = <4>;
+				snps,tx-sched-wrr;
+				queue0 {
+					snps,weight = <0x10>;
+					snps,dcb-algorithm;
+					snps,priority = <0x0>;
+				};
+				queue1 {
+					snps,weight = <0x11>;
+					snps,dcb-algorithm;
+					snps,priority = <0x1>;
+				};
+				queue2 {
+					snps,weight = <0x12>;
+					snps,dcb-algorithm;
+					snps,priority = <0x2>;
+				};
+				queue3 {
+					snps,weight = <0x13>;
+					snps,dcb-algorithm;
+					snps,priority = <0x3>;
+				};
+			};
+		};
+
 		topckgen_clk: clock-controller@10000000 {
 			compatible = "mediatek,mt8189-topckgen", "syscon";
 			reg = <0 0x10000000 0 0x1000>;

arch/arm/dts/mt8371-genio-common.dtsi

@@ -312,6 +312,68 @@
 			bias-pull-up;
 		};
 	};
+
+	eth_default_pins: eth-default-pins {
+		txd-pins {
+			pinmux = <PINMUX_GPIO119__FUNC_GBE_TXD3>,
+				 <PINMUX_GPIO120__FUNC_GBE_TXD2>,
+				 <PINMUX_GPIO121__FUNC_GBE_TXD1>,
+				 <PINMUX_GPIO122__FUNC_GBE_TXD0>;
+			drive-strength = <MTK_DRIVE_8mA>;
+		};
+		cc-pins {
+			pinmux = <PINMUX_GPIO127__FUNC_GBE_TXC>,
+				 <PINMUX_GPIO130__FUNC_GBE_TXEN>,
+				 <PINMUX_GPIO129__FUNC_GBE_RXDV>,
+				 <PINMUX_GPIO128__FUNC_GBE_RXC>;
+			drive-strength = <MTK_DRIVE_8mA>;
+		};
+		rxd-pins {
+			pinmux = <PINMUX_GPIO123__FUNC_GBE_RXD3>,
+				 <PINMUX_GPIO124__FUNC_GBE_RXD2>,
+				 <PINMUX_GPIO125__FUNC_GBE_RXD1>,
+				 <PINMUX_GPIO126__FUNC_GBE_RXD0>;
+			drive-strength = <MTK_DRIVE_8mA>;
+		};
+		mdio-pins {
+			pinmux = <PINMUX_GPIO131__FUNC_GBE_MDC>,
+				 <PINMUX_GPIO132__FUNC_GBE_MDIO>;
+			drive-strength = <MTK_DRIVE_8mA>;
+			input-enable;
+		};
+		power-pins {
+			pinmux = <PINMUX_GPIO133__FUNC_GPIO133>,
+				 <PINMUX_GPIO134__FUNC_GPIO134>;
+			output-high;
+		};
+	};
+
+	eth_sleep_pins: eth-sleep-pins {
+		txd-pins {
+			pinmux = <PINMUX_GPIO119__FUNC_GPIO119>,
+				 <PINMUX_GPIO120__FUNC_GPIO120>,
+				 <PINMUX_GPIO121__FUNC_GPIO121>,
+				 <PINMUX_GPIO122__FUNC_GPIO122>;
+		};
+		cc-pins {
+			pinmux = <PINMUX_GPIO127__FUNC_GPIO127>,
+				 <PINMUX_GPIO130__FUNC_GPIO130>,
+				 <PINMUX_GPIO129__FUNC_GPIO129>,
+				 <PINMUX_GPIO128__FUNC_GPIO128>;
+		};
+		rxd-pins {
+			pinmux = <PINMUX_GPIO123__FUNC_GPIO123>,
+				 <PINMUX_GPIO124__FUNC_GPIO124>,
+				 <PINMUX_GPIO125__FUNC_GPIO125>,
+				 <PINMUX_GPIO126__FUNC_GPIO126>;
+		};
+		mdio-pins {
+			pinmux = <PINMUX_GPIO131__FUNC_GPIO131>,
+				 <PINMUX_GPIO132__FUNC_GPIO132>;
+			input-disable;
+			bias-disable;
+		};
+	};
 };
 
 &pmic {
@@ -342,3 +404,24 @@
 	vbus-supply = <&usb_p4_vbus>;
 	status = "okay";
 };
+
+&eth {
+	/*
+	 * TX clock is provided by MAC
+	 */
+	phy-mode = "rgmii-rxid";
+	phy-handle = <&phy>;
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&eth_default_pins>;
+	pinctrl-1 = <&eth_sleep_pins>;
+	status = "okay";
+	mdio {
+		compatible = "snps,dwmac-mdio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		phy: phy@0 {
+			compatible = "ethernet-phy-idc0ff.0421";
+			reg = <0>;
+		};
+	};
+};

arch/arm/dts/sc573-ezlite.dts

@@ -14,6 +14,8 @@
 };
 
 &i2c0 {
+	status = "okay";
+
 	gpio_expander0: mcp23017@21 {
 		compatible = "microchip,mcp23017";
 		reg = <0x21>;

arch/arm/dts/sc584-ezkit.dts

@@ -13,6 +13,8 @@
 };
 
 &i2c2 {
+	status = "okay";
+
 	gpio_expander0: mcp23017@21 {
 		compatible = "microchip,mcp23017";
 		reg = <0x21>;

arch/arm/dts/sc589-ezkit.dts

@@ -17,6 +17,8 @@
 &i2c0 {
 	#address-cells = <1>;
 	#size-cells = <0>;
+	status = "okay";
+
 	gpio_expander0: mcp23017@21 {
 		compatible = "microchip,mcp23017";
 		reg = <0x21>;

arch/arm/dts/sc594-som.dtsi

@@ -79,6 +79,7 @@
 
 &i2c2 {
 	clocks = <&clk ADSP_SC594_CLK_CGU0_SCLK0>;
+	status = "okay";
 
 	som_gpio_expander: mcp23017@21 {
 		compatible = "microchip,mcp23017";
@@ -153,6 +154,18 @@
 	};
 };
 
+&i2c3 {
+	clocks = <&clk ADSP_SC594_CLK_CGU0_SCLK0>;
+};
+
+&i2c4 {
+	clocks = <&clk ADSP_SC594_CLK_CGU0_SCLK0>;
+};
+
+&i2c5 {
+	clocks = <&clk ADSP_SC594_CLK_CGU0_SCLK0>;
+};
+
 &ospi {
 	status = "okay";
 

arch/arm/dts/sc598-som-revD.dtsi

@@ -8,6 +8,8 @@
 #include "sc598-som.dtsi"
 
 &i2c2 {
+	status = "okay";
+
 	som_gpio_expander: mcp23018@20 {
 		compatible = "microchip,mcp23018";
 		reg = <0x20>;

arch/arm/dts/sc598-som-revE.dtsi

@@ -8,6 +8,8 @@
 #include "sc598-som.dtsi"
 
 &i2c2 {
+	status = "okay";
+
 	som_gpio_expander: adp5587@34 {
 		compatible = "adi,adp5587";
 		reg = <0x34>;

arch/arm/dts/sc598-som.dtsi

@@ -138,6 +138,18 @@
 	clocks = <&clk ADSP_SC598_CLK_CGU0_SCLK0>;
 };
 
+&i2c3 {
+	clocks = <&clk ADSP_SC598_CLK_CGU0_SCLK0>;
+};
+
+&i2c4 {
+	clocks = <&clk ADSP_SC598_CLK_CGU0_SCLK0>;
+};
+
+&i2c5 {
+	clocks = <&clk ADSP_SC598_CLK_CGU0_SCLK0>;
+};
+
 &spi2 {
 	clocks = <&clk ADSP_SC598_CLK_SPI>;
 };

arch/arm/dts/sc59x.dtsi

@@ -86,6 +86,36 @@
 			pinctrl-0 = <&usb0_default>;
 			status = "disabled";
 		};
+
+		i2c3: i2c3@31001000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "adi-i2c";
+			reg = <0x31001000 0x100>;
+			clock-names = "i2c";
+			status = "disabled";
+			bootph-pre-ram;
+		};
+
+		i2c4: i2c4@31001100 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "adi-i2c";
+			reg = <0x31001100 0x100>;
+			clock-names = "i2c";
+			status = "disabled";
+			bootph-pre-ram;
+		};
+
+		i2c5: i2c5@31001200 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "adi-i2c";
+			reg = <0x31001200 0x100>;
+			clock-names = "i2c";
+			status = "disabled";
+			bootph-pre-ram;
+		};
 	};
 };
 

arch/arm/dts/sc5xx.dtsi

@@ -140,9 +140,9 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			compatible = "adi-i2c";
-			reg = <0x31001400 0x1000>;
+			reg = <0x31001400 0x100>;
 			clock-names = "i2c";
-			status = "okay";
+			status = "disabled";
 			bootph-pre-ram;
 		};
 
@@ -150,9 +150,9 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			compatible = "adi-i2c";
-			reg = <0x31001500 0x1000>;
+			reg = <0x31001500 0x100>;
 			clock-names = "i2c";
-			status = "okay";
+			status = "disabled";
 			bootph-pre-ram;
 		};
 
@@ -160,9 +160,9 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			compatible = "adi-i2c";
-			reg = <0x31001600 0x1000>;
+			reg = <0x31001600 0x100>;
 			clock-names = "i2c";
-			status = "okay";
+			status = "disabled";
 			bootph-pre-ram;
 		};
 	};

arch/arm/include/asm/arch-fsl-layerscape/sys_proto.h

@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2026 Free Mobile - Vincent Jardin
+ *
+ * Layerscape mirror of the i.MX <asm/mach-imx/sys_proto.h>: declares
+ * the SoC-personality helpers consumed by generic drivers that work on
+ * both i.MX and QorIQ/Layerscape parts (e.g. drivers/thermal/imx_tmu.c
+ * for the QorIQ TMU variant).
+ */
+
+#ifndef _ASM_ARCH_FSL_LAYERSCAPE_SYS_PROTO_H
+#define _ASM_ARCH_FSL_LAYERSCAPE_SYS_PROTO_H
+
+#include <linux/types.h>
+
+/*
+ * Per LX2160A Reference Manual, Rev. 1 (10/2021):
+ *  - section 1.12.1: "NXP specs max power at 105 degC junction" for
+ *    commercial / embedded operating conditions.
+ *  - section 28.1:   TMU "Accuracy within +/- 3 degC".
+ *
+ * Layerscape SoCs do not expose an OCOTP-style "CPU temp grade" fuse,
+ * so the implementation returns the documented junction-temperature
+ * limit from the data sheet (-40 .. 105 degC commercial range). The
+ * thermal driver subtracts 10 degC for its alert threshold, which
+ * comfortably clears the +/- 3 degC TMU accuracy in both directions.
+ */
+u32 get_cpu_temp_grade(int *minc, int *maxc);
+
+#endif /* _ASM_ARCH_FSL_LAYERSCAPE_SYS_PROTO_H */

arch/arm/include/asm/arch-imx9/sys_proto.h

@@ -22,6 +22,7 @@ int low_drive_freq_update(void *blob);
 
 enum imx9_soc_voltage_mode soc_target_voltage_mode(void);
 int get_reset_reason(bool sys, bool lm);
+int imx9_uboot_fixup_by_fuse(void *fdt);
 
 int scmi_get_boot_device_offset(unsigned long *img_off);
 int scmi_get_boot_stage(u8 *stage);

arch/arm/mach-axiado/Kconfig

@@ -0,0 +1,22 @@
+if ARCH_AXIADO
+
+config SYS_ARCH
+	default "arm"
+
+config SYS_SOC
+	default "axiado"
+
+config AXIADO_AX3005
+	bool
+	select ARM64
+	select ARMV8_SWITCH_TO_EL1
+	select DM
+	select DM_SERIAL
+	select GICV3
+	select ZYNQ_SERIAL
+	select MMC_SDHCI_AXIADO
+	select PHY_AXIADO_EMMC
+
+source "arch/arm/mach-axiado/scm3005/Kconfig"
+
+endif

arch/arm/mach-axiado/Makefile

@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2021-2026 Axiado Corporation (or its affiliates).
+#
+
+obj-$(CONFIG_AXIADO_AX3005) += scm3005/

arch/arm/mach-axiado/scm3005/Kconfig

@@ -0,0 +1,11 @@
+if AXIADO_AX3005
+
+config TARGET_SCM3005
+	bool "Support Axiado AX3005 SCM3005"
+	help
+	  Support for the Axiado AX3005 SCM3005 board.
+	  Based on the Axiado AX3005 quad-core ARMv8 Cortex-A53 SoC.
+
+source "board/axiado/scm3005/Kconfig"
+
+endif

arch/arm/mach-imx/imx9/Kconfig

@@ -150,6 +150,7 @@ config TARGET_PHYCORE_IMX93
 
 config TARGET_IMX95_19X19_EVK
 	bool "imx95_19x19_evk"
+	select OF_BOARD_FIXUP
 	select IMX95
 	imply BOOTSTD_BOOTCOMMAND
 	imply BOOTSTD_FULL
@@ -157,6 +158,7 @@ config TARGET_IMX95_19X19_EVK
 
 config TARGET_IMX95_15X15_EVK
 	bool "imx95_15x15_evk"
+	select OF_BOARD_FIXUP
 	select IMX95
 	imply BOOTSTD_BOOTCOMMAND
 	imply BOOTSTD_FULL
@@ -164,6 +166,7 @@ config TARGET_IMX95_15X15_EVK
 
 config TARGET_IMX943_EVK
 	bool "imx943_evk"
+	select OF_BOARD_FIXUP
 	select IMX94
 	imply BOOTSTD_BOOTCOMMAND
 	imply BOOTSTD_FULL
@@ -180,6 +183,7 @@ config TARGET_VERDIN_IMX95
 
 config TARGET_IMX952_EVK
 	bool "imx952_evk"
+	select OF_BOARD_FIXUP
 	select IMX_SM_CPU
 	select IMX_SM_LMM
 	select IMX952

arch/arm/mach-imx/imx9/scmi/Makefile

@@ -5,5 +5,5 @@
 # Add include path for NXP device tree header files from Linux.
 ccflags-y += -I$(srctree)/dts/upstream/src/arm64/freescale/
 
-obj-y += soc.o
+obj-y += soc.o fdt.o
 obj-y += clock_scmi.o clock.o

arch/arm/mach-imx/imx9/scmi/fdt.c

@@ -0,0 +1,644 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2026 NXP
+ *
+ */
+
+#include <asm/arch/sys_proto.h>
+#include <linux/bitfield.h>
+#include <fuse.h>
+#include <fdt_support.h>
+#include <fdtdec.h>
+
+struct periph_fuse_info {
+	u32 bit_mask;
+	u32 soc_type; /* 0 means for all */
+	bool of_board_fix;
+	int (*disable_func)(void *blob, u32 fuse_val);
+};
+
+int num_a55_cores_disabled;
+int gpu_disabled;
+
+static int delete_fdt_nodes(void *blob, const char *const nodes_path[], int size_array)
+{
+	int i = 0;
+	int rc;
+	int nodeoff;
+
+	for (i = 0; i < size_array; i++) {
+		nodeoff = fdt_path_offset(blob, nodes_path[i]);
+		if (nodeoff < 0)
+			continue; /* Not found, skip it */
+
+		debug("Found %s node\n", nodes_path[i]);
+
+		rc = fdt_del_node(blob, nodeoff);
+		if (rc < 0) {
+			printf("Unable to delete node %s, err=%s\n",
+			       nodes_path[i], fdt_strerror(rc));
+		} else {
+			printf("Delete node %s\n", nodes_path[i]);
+		}
+	}
+
+	return 0;
+}
+
+static int disable_fdt_nodes(void *blob, const char *const nodes_path[],
+			     int size_array, const char *prop, const char *value)
+{
+	int i = 0;
+	int rc;
+	int nodeoff;
+	const char *status = "disabled";
+	const char *prop_str;
+
+	for (i = 0; i < size_array; i++) {
+		nodeoff = fdt_path_offset(blob, nodes_path[i]);
+		if (nodeoff < 0)
+			continue; /* Not found, skip it */
+
+		debug("Found %s node\n", nodes_path[i]);
+
+		if (prop && value) {
+			prop_str = fdt_stringlist_get(blob, nodeoff, prop, 0, NULL);
+
+			if (!prop_str || strcmp(prop_str, value))
+				continue;
+		}
+
+add_status:
+		rc = fdt_setprop(blob, nodeoff, "status", status, strlen(status) + 1);
+		if (rc) {
+			if (rc == -FDT_ERR_NOSPACE) {
+				rc = fdt_increase_size(blob, 512);
+				if (!rc)
+					goto add_status;
+			}
+			printf("Unable to update property %s:%s, err=%s\n",
+			       nodes_path[i], "status", fdt_strerror(rc));
+		} else {
+			debug("Modify %s:%s disabled\n", nodes_path[i], "status");
+		}
+	}
+
+	return 0;
+}
+
+static int get_cooling_device_list(void *blob, u32 nodeoff,
+				   const char *const path, u32 *cooling_dev, int max_cnt)
+{
+		int cnt, j;
+
+		cnt = fdtdec_get_int_array_count(blob, nodeoff, "cooling-device",
+						 cooling_dev, max_cnt);
+		if (cnt < 0) {
+			printf("cnt incorrect, path %s, cnt = %d\n", path, cnt);
+			return cnt;
+		}
+		if (cnt != max_cnt)
+			printf("Warning: %s, cooling-device count %d\n", path, cnt);
+
+		for (j = 0; j < cnt; j++)
+			cooling_dev[j] = cpu_to_fdt32(cooling_dev[j]);
+
+		return cnt;
+}
+
+static void disable_thermal_vpu_node(void *blob, u32 disabled_cores, u32 gpu_disabled)
+{
+	static const char * const thermal_path[] = {
+		"/thermal-zones/ana/cooling-maps/map0",
+		"/thermal-zones/ana-thermal/cooling-maps/map0",
+	};
+	int num_cpus = (is_imx94() || is_imx952()) ? 4 : 6;
+	u32 array_cnt = (num_cpus + 2) * 3 - (disabled_cores * 3) - (gpu_disabled * 3);
+	u32 cooling_dev[array_cnt];
+
+	int nodeoff, ret, i, cnt;
+
+	for (i = 0; i < ARRAY_SIZE(thermal_path); i++) {
+		nodeoff = fdt_path_offset(blob, thermal_path[i]);
+		if (nodeoff < 0) {
+			printf("path not found %s\n", thermal_path[i]);
+			continue; /* Not found, skip it */
+		}
+
+		cnt = get_cooling_device_list(blob, nodeoff,
+					      thermal_path[i], cooling_dev, array_cnt);
+		/* VPU map does not exist in cooling dev*/
+		if (cnt <= ((num_cpus - disabled_cores) * 3 + (gpu_disabled ? 0 : 3)))
+			continue;
+
+		/* Remove  VPU it the last two nodes in the fdt ana blob */
+		ret = fdt_setprop(blob, nodeoff, "cooling-device", &cooling_dev,
+				  sizeof(u32) * (array_cnt - 3));
+
+		if (ret < 0) {
+			printf("Warning: %s, cooling-device setprop failed %d\n",
+			       thermal_path[i], ret);
+			continue;
+		}
+
+		printf("Update node %s, cooling-device prop\n", thermal_path[i]);
+	}
+}
+
+static void disable_thermal_gpu_node(void *blob, u32 disabled_cores)
+{
+	static const char * const thermal_path[] = {
+		"/thermal-zones/ana/cooling-maps/map0",
+		"/thermal-zones/ana-thermal/cooling-maps/map0",
+	};
+	int num_cpus = (is_imx94() || is_imx952()) ? 4 : 6;
+	u32 array_cnt = (num_cpus + 2) * 3 - (disabled_cores * 3);
+	u32 cooling_dev[array_cnt];
+	int nodeoff, ret, i, cnt;
+
+	for (i = 0; i < ARRAY_SIZE(thermal_path); i++) {
+		nodeoff = fdt_path_offset(blob, thermal_path[i]);
+		if (nodeoff < 0) {
+			printf("path not found %s\n", thermal_path[i]);
+			continue; /* Not found, skip it */
+		}
+
+		cnt = get_cooling_device_list(blob, nodeoff, thermal_path[i],
+					      cooling_dev, array_cnt);
+		if (cnt <= (num_cpus - disabled_cores) * 3)
+			continue; /* GPU map does not exist in cooling dev*/
+
+		/* Remove GPU and VPU as these are the last two nodes in the fdt ana blob */
+		ret = fdt_setprop(blob, nodeoff, "cooling-device", &cooling_dev,
+				  sizeof(u32) * (array_cnt - 6));
+		if (ret < 0) {
+			printf("Warning: %s, cooling-device setprop failed %d\n",
+			       thermal_path[i], ret);
+			continue;
+		}
+
+		if (cnt == array_cnt) {
+			/* Add VPU node back to ana thermal-zone. */
+			ret = fdt_appendprop(blob, nodeoff, "cooling-device",
+					     &cooling_dev[array_cnt - 3], sizeof(u32) * 3);
+			if (ret < 0) {
+				printf("Warning: %s, cooling-device appendprop failed %d\n",
+				       thermal_path[i], ret);
+				continue;
+			}
+		}
+
+		printf("Update node %s, cooling-device prop\n", thermal_path[i]);
+	}
+}
+
+static void disable_thermal_cpu_nodes(void *blob, u32 disabled_cores)
+{
+	static const char * const thermal_path[] = {
+		"/thermal-zones/pf53_arm/cooling-maps/map0",
+		"/thermal-zones/ana/cooling-maps/map0",
+		"/thermal-zones/a55/cooling-maps/map0",
+		"/thermal-zones/a55-thermal/cooling-maps/map0",
+		"/thermal-zones/ana-thermal/cooling-maps/map0",
+	};
+	u32 cooling_dev[24];
+	int nodeoff, ret, i, cnt;
+	int prop_size = 3 * ((is_imx94() || is_imx952()) ? 4 : 6);
+
+	for (i = 0; i < ARRAY_SIZE(thermal_path); i++) {
+		nodeoff = fdt_path_offset(blob, thermal_path[i]);
+		if (nodeoff < 0) {
+			printf("path not found %s\n", thermal_path[i]);
+			continue; /* Not found, skip it */
+		}
+		cnt = get_cooling_device_list(blob, nodeoff, thermal_path[i], cooling_dev, 24);
+
+		ret = fdt_setprop(blob, nodeoff, "cooling-device", &cooling_dev,
+				  sizeof(u32) * (prop_size - disabled_cores * 3));
+
+		if (ret < 0) {
+			printf("Warning: %s, cooling-device setprop failed %d\n",
+			       thermal_path[i], ret);
+			continue;
+		}
+
+		/* Add GPU and VPU nodes back to ana thermal-zone. */
+		if (cnt > prop_size) {
+			ret = fdt_appendprop(blob, nodeoff, "cooling-device",
+					     &cooling_dev[prop_size],
+					     sizeof(u32) * (cnt - prop_size));
+			if (ret < 0) {
+				printf("Warning: %s, cooling-device appendprop failed %d\n",
+				       thermal_path[i], ret);
+				continue;
+			}
+		}
+
+		printf("Update node %s, cooling-device prop\n", thermal_path[i]);
+	}
+}
+
+static int disable_ld_node(void *blob, u32 fuse_val)
+{
+	static const char * const nodes_path_ld[] = {
+		"/remoteproc",
+		"/disp-mu",
+		"/soc/syscon@4b070000",
+		"/soc/mailbox@4b080000",
+		"/soc/mailbox@4b090000",
+	};
+
+	return delete_fdt_nodes(blob, nodes_path_ld, ARRAY_SIZE(nodes_path_ld));
+}
+
+static int disable_npu_node(void *blob, u32 fuse_val)
+{
+	static const char * const nodes_path_npu[] = {
+		"/soc/imx95-neutron-remoteproc@4ab00000",
+		"/soc/imx95-neutron@4ab00004",
+		"/soc/neutron-remoteproc@4ab00000",
+		"/soc/neutron@4ab00004",
+	};
+
+	return delete_fdt_nodes(blob, nodes_path_npu, ARRAY_SIZE(nodes_path_npu));
+}
+
+static int disable_arm_cpu_nodes(void *blob, u32 fuse_val)
+{
+	u32 i = 0;
+	int rc;
+	int nodeoff;
+	char nodes_path[32];
+	int num_cpus = (is_imx94() || is_imx952()) ? 4 : 6;
+
+	num_a55_cores_disabled = 0;
+
+	if (fuse_val & BIT(2)) /* A55C2 */
+		num_a55_cores_disabled++;
+
+	if (fuse_val & BIT(3)) /* A55C2 */
+		num_a55_cores_disabled++;
+
+	if (fuse_val & BIT(4)) /* A55C3 */
+		num_a55_cores_disabled++;
+
+	if (fuse_val & BIT(5)) /* A55C4 */
+		num_a55_cores_disabled++;
+
+	if (fuse_val & BIT(6)) /* A55C5 */
+		num_a55_cores_disabled++;
+
+	for (i = num_cpus; i > (num_cpus - num_a55_cores_disabled); i--) {
+		sprintf(nodes_path, "/cpus/cpu@%u00", i - 1);
+
+		nodeoff = fdt_path_offset(blob, nodes_path);
+		if (nodeoff < 0)
+			continue; /* Not found, skip it */
+
+		debug("Found %s node\n", nodes_path);
+
+		rc = fdt_del_node(blob, nodeoff);
+		if (rc < 0) {
+			printf("Unable to delete node %s, err=%s\n",
+			       nodes_path, fdt_strerror(rc));
+		} else {
+			printf("Delete node %s\n", nodes_path);
+
+			/* Remove node from cpu-map/cluster0 */
+			sprintf(nodes_path, "/cpus/cpu-map/cluster0/core%u", i - 1);
+			nodeoff = fdt_path_offset(blob, nodes_path);
+			if (nodeoff < 0)
+				continue; /* Not found, skip it */
+
+			rc = fdt_del_node(blob, nodeoff);
+			if (rc < 0)
+				printf("Unable to delete node %s, err=%s\n",
+				       nodes_path, fdt_strerror(rc));
+		}
+	}
+
+	disable_thermal_cpu_nodes(blob, num_a55_cores_disabled);
+
+	return 0;
+}
+
+static int disable_jpegdec_node(void *blob, u32 fuse_val)
+{
+	static const char * const nodes_path_jpegdec[] = {
+		"/soc/jpegdec@4c500000",
+	};
+
+	return delete_fdt_nodes(blob, nodes_path_jpegdec, ARRAY_SIZE(nodes_path_jpegdec));
+}
+
+static int disable_jpegenc_node(void *blob, u32 fuse_val)
+{
+	static const char * const nodes_path_jpegenc[] = {
+		"/soc/jpegenc@4c550000",
+	};
+
+	return delete_fdt_nodes(blob, nodes_path_jpegenc, ARRAY_SIZE(nodes_path_jpegenc));
+}
+
+static int disable_mipicsi0_node(void *blob, u32 fuse_val)
+{
+	static const char * const nodes_path_mipicsi0[] = {
+		"/soc/csi@4ad30000",
+	};
+
+	return delete_fdt_nodes(blob, nodes_path_mipicsi0, ARRAY_SIZE(nodes_path_mipicsi0));
+}
+
+static int disable_mipicsi1_node(void *blob, u32 fuse_val)
+{
+	static const char * const nodes_path_mipicsi1[] = {
+		"/soc/csi@4ad40000",
+	};
+
+	return delete_fdt_nodes(blob, nodes_path_mipicsi1, ARRAY_SIZE(nodes_path_mipicsi1));
+}
+
+static int disable_isp_node(void *blob, u32 fuse_val)
+{
+	static const char * const nodes_path_isp[] = {
+		"/soc@0/isp@4ae00000",
+		"/soc/isp@4ae00000",
+	};
+
+	return delete_fdt_nodes(blob, nodes_path_isp, ARRAY_SIZE(nodes_path_isp));
+}
+
+static int disable_vpu_node(void *blob, u32 fuse_val)
+{
+	int ret = 0;
+
+	static const char * const nodes_path_vpu[] = {
+		"/soc/vpu-ctrl@4c4c0000",
+		"/soc/vpu-ctrl@4c4f0000",
+		"/soc/vpu@4c480000",
+		"/soc/vpu@4c490000",
+		"/soc/vpu@4c4a0000",
+		"/soc/vpu@4c4b0000",
+		"/soc/vpu@4c4c0000",
+		"/soc/vpu@4c4d0000",
+		"/soc/vpu@4c4e0000",
+		"/soc/jpegdec@4c500000",
+		"/soc/jpegenc@4c550000",
+		"/soc/vpuenc@4c460000",
+		"/soc/syscon@4c410000"
+	};
+
+	ret = delete_fdt_nodes(blob, nodes_path_vpu, ARRAY_SIZE(nodes_path_vpu));
+	if (!ret)
+		disable_thermal_vpu_node(blob, num_a55_cores_disabled, gpu_disabled);
+
+	return ret;
+}
+
+static int disable_vpuenc_node(void *blob, u32 fuse_val)
+{
+	static const char * const nodes_path_vpuenc[] = {
+		"/soc/vpuenc@4c460000",
+	};
+
+	return delete_fdt_nodes(blob, nodes_path_vpuenc, ARRAY_SIZE(nodes_path_vpuenc));
+}
+
+static int disable_vpuwave511_node(void *blob, u32 fuse_val)
+{
+	static const char * const nodes_path_vpu511[] = {
+		"/soc/vpu-ctrl@4c4f0000",
+		"/soc/vpu@4c4b0000",
+		"/soc/vpu@4c4c0000",
+		"/soc/vpu@4c4d0000",
+		"/soc/vpu@4c4e0000",
+	};
+
+	return delete_fdt_nodes(blob, nodes_path_vpu511, ARRAY_SIZE(nodes_path_vpu511));
+}
+
+static int disable_gpu_node(void *blob, u32 fuse_val)
+{
+	int ret = 0;
+
+	static const char * const nodes_path_gpu[] = {
+		"/soc/gpu@4d900000",
+		"/thermal-zones@1/ana/cooling-maps/map1/cooling-device/gpu@4d900000",
+		"/thermal-zones/ana/cooling-maps/map1/cooling-device/gpu@4d900000",
+		"/thermal-zones@1/ana/cooling-maps/map1/cooling-device",
+		"/thermal-zones/ana/cooling-maps/map1/cooling-device",
+		"/thermal-zones@1/ana/cooling-maps/map1",
+		"/thermal-zones/ana/cooling-maps/map1",
+	};
+
+	ret = delete_fdt_nodes(blob, nodes_path_gpu, ARRAY_SIZE(nodes_path_gpu));
+	if (!ret) {
+		disable_thermal_gpu_node(blob, num_a55_cores_disabled);
+		gpu_disabled = 1;
+	}
+	return ret;
+}
+
+static int disable_pciea_node(void *blob, u32 fuse_val)
+{
+	static const char * const nodes_path_pciea[] = {
+		"/soc/pcie@4c300000",
+		"/soc/pcie-ep@4c300000"
+	};
+
+	return delete_fdt_nodes(blob, nodes_path_pciea, ARRAY_SIZE(nodes_path_pciea));
+}
+
+static int disable_pcieb_node(void *blob, u32 fuse_val)
+{
+	static const char * const nodes_path_pcieb[] = {
+		"/soc/pcie@4c380000",
+		"/soc/pcie-ep@4c380000"
+	};
+
+	return delete_fdt_nodes(blob, nodes_path_pcieb, ARRAY_SIZE(nodes_path_pcieb));
+}
+
+int disable_enet10g_node(void *blob, u32 fuse_val)
+{
+	static const char * const nodes_path_enet10g[] = {
+		"/pcie@4ca00000/ethernet@10,0",
+		"/soc/pcie@4ca00000/ethernet@10,0",
+		"/soc/syscon@4ca00000/ethernet@10,0",
+		"/soc/netc-blk-ctrl@4cde0000/pcie@4ca00000/ethernet@10,0",
+	};
+
+	return disable_fdt_nodes(blob, nodes_path_enet10g, ARRAY_SIZE(nodes_path_enet10g),
+		NULL, NULL);
+}
+
+int disable_enet25g_node(void *blob, u32 fuse_val)
+{
+	static const char * const nodes_path_enet25g[] = {
+		"/soc/system-controller@4ceb0000/pcie@4ca00000/ethernet-switch@0,2/ports/port@0",
+		"/soc/system-controller@4ceb0000/pcie@4ca00000/ethernet-switch@0,2/ports/port@1",
+	};
+
+	return disable_fdt_nodes(blob, nodes_path_enet25g, ARRAY_SIZE(nodes_path_enet25g),
+		"phy-mode", "sgmii");
+}
+
+int disable_mipidsi_node(void *blob, u32 fuse_val)
+{
+	static const char * const nodes_path_mipidsi[] = {
+		"/soc/dsi@4acf0000",
+		"/soc/syscon@4acf0000",
+		"/soc/dsi@4b060000",
+		"/soc/phy@4b110000",
+	};
+
+	return delete_fdt_nodes(blob, nodes_path_mipidsi, ARRAY_SIZE(nodes_path_mipidsi));
+}
+
+int disable_dpu_node(void *blob, u32 fuse_val)
+{
+	static const char * const nodes_path_dpu[] = {
+		"/soc/bridge@4b0d0000/channel@0/port@0/endpoint",
+		"/soc/bridge@4b0d0000/channel@0/port@1/endpoint",
+		"/soc/bridge@4b0d0000/channel@1/port@0/endpoint",
+		"/soc/bridge@4b0d0000/channel@1/port@1/endpoint",
+		"/soc/display-controller@4b400000/ports/port@0/endpoint",
+		"/soc/display-controller@4b400000/ports/port@1/endpoint",
+		"/soc/display-controller@4b400000",
+		"/soc/syscon@4b010000/bridge@8/ports/port@0/endpoint",
+		"/soc/syscon@4b010000/bridge@8/ports/port@1/endpoint",
+		"/soc/syscon@4b010000/bridge@8/ports/port@2/endpoint@0",
+		"/soc/syscon@4b010000/bridge@8/ports/port@2/endpoint@1",
+		"/soc/syscon@4b010000/bridge@8/ports/port@3/endpoint@0",
+		"/soc/syscon@4b010000/bridge@8/ports/port@3/endpoint@1",
+		"/soc/syscon@4b010000/bridge@8",
+		"/soc/syscon@4b010000",
+		"/soc/syscon@4b0a0000",
+		"/soc/interrupt-controller@4b0b0000",
+		"/soc/bridge@4b0d0000"
+	};
+
+	return delete_fdt_nodes(blob, nodes_path_dpu, ARRAY_SIZE(nodes_path_dpu));
+}
+
+int disable_lvds_node(void *blob, u32 fuse_val)
+{
+	static const char * const nodes_path_lvds[] = {
+		"/soc/syscon@4b0c0000/ldb@4/channel@0",
+		"/soc/syscon@4b0c0000/phy@8",
+		"/soc/syscon@4b0c0000/ldb@4/channel@1",
+		"/soc/syscon@4b0c0000/phy@c",
+		"/soc/syscon@4b0c0000"
+	};
+
+	return delete_fdt_nodes(blob, nodes_path_lvds, ARRAY_SIZE(nodes_path_lvds));
+}
+
+int disable_cm70_node(void *blob, u32 fuse_val)
+{
+	static const char * const nodes_path_cm70[] = {
+		"/reserved-memory/vdev0vring0@82000000",
+		"/reserved-memory/vdev0vring1@82008000",
+		"/reserved-memory/vdev1vring0@82010000",
+		"/reserved-memory/vdev1vring1@82018000",
+		"/reserved-memory/rsc-table@82220000",
+		"/reserved-memory/vdevbuffer@82020000",
+		"/imx943-cm70",
+	};
+
+	return delete_fdt_nodes(blob, nodes_path_cm70, ARRAY_SIZE(nodes_path_cm70));
+}
+
+int disable_cm71_node(void *blob, u32 fuse_val)
+{
+	static const char * const nodes_path_cm71[] = {
+		"/reserved-memory/vdev0vring0@84000000",
+		"/reserved-memory/vdev0vring1@84008000",
+		"/reserved-memory/vdev1vring0@84010000",
+		"/reserved-memory/vdev1vring1@84018000",
+		"/reserved-memory/rsc-table@84220000",
+		"/reserved-memory/vdevbuffer@84020000",
+		"/imx943-cm71",
+	};
+
+	return delete_fdt_nodes(blob, nodes_path_cm71, ARRAY_SIZE(nodes_path_cm71));
+}
+
+/* There is order dependency between cpu->gpu->vpu */
+struct periph_fuse_info f17_grp[] = {
+	{ BIT(30), MXC_CPU_IMX952, false, disable_ld_node },
+};
+
+struct periph_fuse_info f18_grp[] = {
+	{ BIT(0), 0, false, disable_npu_node },
+	{ GENMASK(6, 2), 0, false, disable_arm_cpu_nodes },
+	{ BIT(9), 0, true, disable_cm70_node },
+	{ BIT(17), MXC_CPU_IMX94, true, disable_cm71_node },
+	{ BIT(22), 0, true, disable_dpu_node },
+	{ BIT(27), 0, true, disable_lvds_node },
+	{ BIT(29), 0, false, disable_isp_node },
+};
+
+struct periph_fuse_info f19_grp[] = {
+	{ BIT(6), 0, true, disable_pciea_node },
+	{ BIT(7), 0, true, disable_pcieb_node },
+	{ BIT(17), 0, false, disable_gpu_node },
+	{ BIT(18), 0, false, disable_vpu_node },
+	{ BIT(19), 0, false, disable_jpegenc_node },
+	{ BIT(20), 0, false, disable_jpegdec_node },
+	{ BIT(22), 0, false, disable_mipicsi0_node },
+	{ BIT(23), 0, false, disable_mipicsi1_node },
+	{ BIT(24), 0, true, disable_mipidsi_node },
+	{ BIT(26), 0, false, disable_vpuenc_node },
+	{ BIT(27), 0, false, disable_vpuwave511_node },
+};
+
+struct periph_fuse_info f20_grp[] = {
+	{ BIT(12), MXC_CPU_IMX95, true, disable_enet10g_node },
+	{ BIT(12), MXC_CPU_IMX94, true, disable_enet25g_node },
+};
+
+static void ft_disable_periph(void *blob, u32 fuse_bank, u32 fuse_word,
+			      struct periph_fuse_info *info, u32 info_num,
+			      bool board_fix_fdt)
+{
+	int i, ret;
+	u32 val = 0;
+
+	ret = fuse_read(fuse_bank, fuse_word, &val);
+	if (ret)
+		return;
+
+	for (i = 0; i < info_num; i++) {
+		if (val & info[i].bit_mask) {
+			if (board_fix_fdt && !info[i].of_board_fix)
+				continue;
+
+			if (!info[i].soc_type || is_cpu_type(info[i].soc_type))
+				info[i].disable_func(blob, val);
+		}
+	}
+}
+
+int ft_system_setup(void *blob, struct bd_info *bd)
+{
+	/* Common peripheral disable fuse process */
+	ft_disable_periph(blob, 2, 1, f17_grp, ARRAY_SIZE(f17_grp), false);
+	ft_disable_periph(blob, 2, 2, f18_grp, ARRAY_SIZE(f18_grp), false);
+	ft_disable_periph(blob, 2, 3, f19_grp, ARRAY_SIZE(f19_grp), false);
+	ft_disable_periph(blob, 2, 4, f20_grp, ARRAY_SIZE(f20_grp), false);
+
+	return 0;
+}
+
+/* Fix uboot dtb based on fuses. */
+#if IS_ENABLED(CONFIG_OF_BOARD_FIXUP) && !IS_ENABLED(CONFIG_XPL_BUILD)
+int imx9_uboot_fixup_by_fuse(void *fdt)
+{
+	ft_disable_periph(fdt, 2, 2, f18_grp, ARRAY_SIZE(f18_grp), true);
+	ft_disable_periph(fdt, 2, 3, f19_grp, ARRAY_SIZE(f19_grp), true);
+	ft_disable_periph(fdt, 2, 4, f20_grp, ARRAY_SIZE(f20_grp), true);
+
+	return 0;
+}
+#endif

arch/arm/mach-imx/imx9/scmi/soc.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2025 NXP
+ * Copyright 2025-2026 NXP
  *
  * Peng Fan <peng.fan@nxp.com>
  */
@@ -186,8 +186,9 @@ u32 get_cpu_temp_grade(int *minc, int *maxc)
 			*minc = -40;
 			*maxc = 105;
 		} else if (val == TEMP_EXTCOMMERCIAL) {
-			*minc = -20;
-			*maxc = 105;
+			/* Map to Ext industrial */
+			*minc = -40;
+			*maxc = 125;
 		} else {
 			*minc = 0;
 			*maxc = 95;
@@ -715,14 +716,88 @@ int get_reset_reason(bool sys, bool lm)
 	return 0;
 }
 
-const char *get_imx_type(u32 imxtype)
+const char *get_cpu_variant_type_name(u32 type)
 {
-	switch (imxtype) {
-	case SCMI_CPU:
-		return IMX_PLAT_STR;
-	default:
-		return "??";
+	u32 val, core_num, part_num;
+	int ret;
+
+	ret = fuse_read(2, 1, &val);
+	if (ret)
+		return NULL;
+
+	/* Get part num */
+	part_num = (val >> 4) & 0xff;
+	if (!part_num)
+		return NULL;
+
+	if (type == MXC_CPU_IMX95 || type == MXC_CPU_IMX952) {
+		u32 segment;
+		static char name[8] = "95294";
+		char pn[2];
+
+		core_num = part_num & 0x3;
+		segment = (part_num >> 2) & 0xf;
+
+		switch (segment) {
+		case 0xa:
+			pn[0] = 'T';
+			break;
+		case 0xb:
+			pn[0] = 'V';
+			break;
+		case 0xc:
+			pn[0] = 'C';
+			break;
+		case 0xd:
+			pn[0] = 'G';
+			break;
+		case 0xe:
+			pn[0] = 'I';
+			break;
+		case 0xf:
+			pn[0] = 'N';
+			break;
+		default:
+			pn[0] = segment + '0';
+			break;
+		}
+
+		pn[1] = core_num * 2 + '0';
+
+		if (type == MXC_CPU_IMX95)
+			sprintf(name, "95%c%c", pn[0], pn[1]);
+		else
+			sprintf(name, "952%c%c", pn[0], pn[1]);
+
+		return name;
+	} else if (type == MXC_CPU_IMX94) {
+		static char *name = "94398";
+
+		core_num = 8;
+
+		ret = fuse_read(2, 2, &val);
+		if (ret)
+			return NULL;
+
+		if (part_num > 30) { /* 943 */
+			/* A55 2 & 3 disabled */
+			if ((val & 0x18) == 0x18)
+				core_num = 6;
+		} else if (part_num > 20) { /* 942 */
+			core_num = 5;
+
+			/* m7_0 disabled */
+			if ((val & 0x200) == 0x200)
+				core_num = 4;
+		} else if (part_num > 10) { /* 941 */
+			core_num = 5;
+		}
+		sprintf(name, "94%u%u", part_num, core_num);
+
+		return name;
 	}
+
+	return NULL;
 }
 
 void build_info(void)
@@ -798,18 +873,6 @@ int arch_misc_init(void)
 	return 0;
 }
 
-#if defined(CONFIG_OF_BOARD_FIXUP) && !defined(CONFIG_SPL_BUILD)
-int board_fix_fdt(void *fdt)
-{
-	return 0;
-}
-#endif
-
-int ft_system_setup(void *blob, struct bd_info *bd)
-{
-	return 0;
-}
-
 #if IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
 void get_board_serial(struct tag_serialnr *serialnr)
 {

arch/arm/mach-kirkwood/cpu.c

@@ -99,16 +99,16 @@ static void kw_sysrst_action(void)
 
 	if (!s) {
 		debug("Error.. %s failed, check sysrstcmd\n",
-			__FUNCTION__);
+			__func__);
 		return;
 	}
 
-	debug("Starting %s process...\n", __FUNCTION__);
+	debug("Starting %s process...\n", __func__);
 	ret = run_command(s, 0);
 	if (ret != 0)
-		debug("Error.. %s failed\n", __FUNCTION__);
+		debug("Error.. %s failed\n", __func__);
 	else
-		debug("%s process finished\n", __FUNCTION__);
+		debug("%s process finished\n", __func__);
 }
 
 static void kw_sysrst_check(void)
@@ -152,7 +152,7 @@ int print_cpuinfo(void)
 	u8 revid = readl(KW_REG_PCIE_REVID) & 0xff;
 
 	if ((readl(KW_REG_DEVICE_ID) & 0x03) > 2) {
-		printf("Error.. %s:Unsupported Kirkwood SoC 88F%04x\n", __FUNCTION__, devid);
+		printf("Error.. %s:Unsupported Kirkwood SoC 88F%04x\n", __func__, devid);
 		return -1;
 	}
 

arch/arm/mach-mvebu/Kconfig

@@ -166,6 +166,14 @@ config TARGET_MVEBU_ARMADA_8K
 	select BOARD_LATE_INIT
 	imply SCSI
 
+config TARGET_NBX10G
+	bool "Support Freebox Nodebox 10G"
+	select ARMADA_8K
+	select BOARD_LATE_INIT
+	help
+	  Enable support for the Freebox Nodebox 10G board based on the
+	  Marvell Armada 8040 SoC with dual CP110 companion chips.
+
 config TARGET_MVEBU_ALLEYCAT5
 	bool "Support AlleyCat 5 platforms"
 	select ALLEYCAT_5
@@ -226,6 +234,10 @@ config TARGET_X240
 	select ALLEYCAT_5
 	imply BOOTSTD_DEFAULTS
 
+config TARGET_X220
+	bool "Support Allied Telesis x220"
+	select 98DX3336
+
 config TARGET_DB_XC3_24G4XG
 	bool "Support DB-XC3-24G4XG"
 	select 98DX3336
@@ -310,6 +322,7 @@ config SYS_BOARD
 	default "x530" if TARGET_X530
 	default "x250" if TARGET_X250
 	default "x240" if TARGET_X240
+	default "x220" if TARGET_X220
 	default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG
 	default "crs3xx-98dx3236" if TARGET_CRS3XX_98DX3236
 	default "mvebu_alleycat-5" if TARGET_MVEBU_ALLEYCAT5
@@ -335,6 +348,7 @@ config SYS_CONFIG_NAME
 	default "x530" if TARGET_X530
 	default "x250" if TARGET_X250
 	default "x240" if TARGET_X240
+	default "x220" if TARGET_X220
 	default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG
 	default "crs3xx-98dx3236" if TARGET_CRS3XX_98DX3236
 	default "mvebu_alleycat-5" if TARGET_MVEBU_ALLEYCAT5
@@ -360,6 +374,7 @@ config SYS_VENDOR
 	default "alliedtelesis" if TARGET_X530
 	default "alliedtelesis" if TARGET_X250
 	default "alliedtelesis" if TARGET_X240
+	default "alliedtelesis" if TARGET_X220
 	default "mikrotik" if TARGET_CRS3XX_98DX3236
 	default "Marvell" if TARGET_MVEBU_ALLEYCAT5
 
@@ -508,5 +523,6 @@ config ARMADA_32BIT_SYSCON_SYSRESET
 
 source "board/solidrun/clearfog/Kconfig"
 source "board/kobol/helios4/Kconfig"
+source "board/freebox/nbx10g/Kconfig"
 
 endif

arch/arm/mach-mvebu/armada8k/Makefile

@@ -2,4 +2,4 @@
 #
 # Copyright (C) 2016 Stefan Roese <sr@denx.de>
 
-obj-y = cpu.o cache_llc.o dram.o
+obj-y = cpu.o cache_llc.o dram.o soc_info.o

arch/arm/mach-mvebu/armada8k/cpu.c

@@ -15,6 +15,8 @@
 #include <asm/armv8/mmu.h>
 #include <mach/fw_info.h>
 
+#include "soc_info.h"
+
 /* Armada 7k/8k */
 #define MVEBU_RFU_BASE			(MVEBU_REGISTER(0x6f0000))
 #define RFU_GLOBAL_SW_RST		(MVEBU_RFU_BASE + 0x84)
@@ -111,3 +113,13 @@ int mmc_get_env_dev(void)
 
 	return CONFIG_ENV_MMC_DEVICE_INDEX;
 }
+
+int print_cpuinfo(void)
+{
+	if (!IS_ENABLED(CONFIG_DISPLAY_CPUINFO))
+		return 0;
+
+	soc_print_clock_info();
+	soc_print_soc_info();
+	return 0;
+}

arch/arm/mach-mvebu/armada8k/soc_info.c

@@ -0,0 +1,194 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015 Marvell International Ltd.
+ *
+ * Marvell Armada 8K SoC info: SAR, Clock frequencies, LLC status
+ * Ported from Marvell U-Boot 2015.01 to mainline U-Boot.
+ */
+
+#include <config.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <stdio.h>
+#include <asm/io.h>
+#include <asm/arch/soc.h>
+
+/* Clock frequency units */
+#define KHz			1000
+#define MHz			1000000
+#define GHz			1000000000
+
+/* AP806 SAR (Sample-At-Reset) register */
+#define AP806_SAR_REG_BASE		(SOC_REGS_PHY_BASE + 0x6F4400)
+#define SAR_CLOCK_FREQ_MODE_OFFSET	0
+#define SAR_CLOCK_FREQ_MODE_MASK	(0x1f << SAR_CLOCK_FREQ_MODE_OFFSET)
+
+/* LLC (Last Level Cache) registers */
+#define LLC_BASE			(SOC_REGS_PHY_BASE + 0x8000)
+#define LLC_CTRL			0x100
+#define LLC_CTRL_EN			0x1
+#define LLC_EXCLUSIVE_EN		0x100
+
+/* MSS clock is fixed at 200MHz on AP806 */
+#define AP806_MSS_CLOCK			(200 * MHz)
+
+/* Clock ID indices in PLL frequency table */
+#define CPU_CLOCK_ID	0
+#define DDR_CLOCK_ID	1
+#define RING_CLOCK_ID	2
+
+/* Clocking options (SAR field values) */
+enum clocking_options {
+	CPU_2000_DDR_1200_RCLK_1200 = 0x0,
+	CPU_2000_DDR_1050_RCLK_1050 = 0x1,
+	CPU_1600_DDR_800_RCLK_800 = 0x4,
+	CPU_1800_DDR_1200_RCLK_1200 = 0x6,
+	CPU_1800_DDR_1050_RCLK_1050 = 0x7,
+	CPU_1600_DDR_900_RCLK_900 = 0x0b,
+	CPU_1600_DDR_1050_RCLK_1050 = 0x0d,
+	CPU_1600_DDR_900_RCLK_900_2 = 0x0e,
+	CPU_1000_DDR_650_RCLK_650 = 0x13,
+	CPU_1300_DDR_800_RCLK_800 = 0x14,
+	CPU_1300_DDR_650_RCLK_650 = 0x17,
+	CPU_1200_DDR_800_RCLK_800 = 0x19,
+	CPU_1400_DDR_800_RCLK_800 = 0x1a,
+	CPU_600_DDR_800_RCLK_800 = 0x1b,
+	CPU_800_DDR_800_RCLK_800 = 0x1c,
+	CPU_1000_DDR_800_RCLK_800 = 0x1d,
+};
+
+/*
+ * PLL frequency table: maps SAR clock mode to actual frequencies.
+ * Format: { CPU_freq, DDR_freq, RING_freq, SAR_value }
+ */
+static const u32 pll_freq_tbl[16][4] = {
+	/* CPU */	/* DDR */	/* Ring */
+	{2000 * MHz,	1200 * MHz,	1200 * MHz,	CPU_2000_DDR_1200_RCLK_1200},
+	{2000 * MHz,	1050 * MHz,	1050 * MHz,	CPU_2000_DDR_1050_RCLK_1050},
+	{1800 * MHz,	1200 * MHz,	1200 * MHz,	CPU_1800_DDR_1200_RCLK_1200},
+	{1800 * MHz,	1050 * MHz,	1050 * MHz,	CPU_1800_DDR_1050_RCLK_1050},
+	{1600 * MHz,	1050 * MHz,	1050 * MHz,	CPU_1600_DDR_1050_RCLK_1050},
+	{1600 * MHz,	900 * MHz,	900 * MHz,	CPU_1600_DDR_900_RCLK_900_2},
+	{1300 * MHz,	800 * MHz,	800 * MHz,	CPU_1300_DDR_800_RCLK_800},
+	{1300 * MHz,	650 * MHz,	650 * MHz,	CPU_1300_DDR_650_RCLK_650},
+	{1600 * MHz,	800 * MHz,	800 * MHz,	CPU_1600_DDR_800_RCLK_800},
+	{1600 * MHz,	900 * MHz,	900 * MHz,	CPU_1600_DDR_900_RCLK_900},
+	{1000 * MHz,	650 * MHz,	650 * MHz,	CPU_1000_DDR_650_RCLK_650},
+	{1200 * MHz,	800 * MHz,	800 * MHz,	CPU_1200_DDR_800_RCLK_800},
+	{1400 * MHz,	800 * MHz,	800 * MHz,	CPU_1400_DDR_800_RCLK_800},
+	{600 * MHz,	800 * MHz,	800 * MHz,	CPU_600_DDR_800_RCLK_800},
+	{800 * MHz,	800 * MHz,	800 * MHz,	CPU_800_DDR_800_RCLK_800},
+	{1000 * MHz,	800 * MHz,	800 * MHz,	CPU_1000_DDR_800_RCLK_800}
+};
+
+/*
+ * Get the clock frequency mode index from SAR register.
+ * Returns index into pll_freq_tbl, or -1 if not found.
+ */
+static int sar_get_clock_freq_mode(void)
+{
+	u32 i;
+	u32 clock_freq;
+
+	clock_freq = (readl(AP806_SAR_REG_BASE) & SAR_CLOCK_FREQ_MODE_MASK)
+			>> SAR_CLOCK_FREQ_MODE_OFFSET;
+
+	for (i = 0; i < ARRAY_SIZE(pll_freq_tbl); i++) {
+		if (pll_freq_tbl[i][3] == clock_freq)
+			return i;
+	}
+
+	pr_err("SAR: unsupported clock freq mode %d\n", clock_freq);
+	return -1;
+}
+
+/*
+ * Get CPU clock frequency in Hz.
+ */
+static u32 soc_cpu_clk_get(void)
+{
+	int mode = sar_get_clock_freq_mode();
+
+	if (mode < 0)
+		return 0;
+	return pll_freq_tbl[mode][CPU_CLOCK_ID];
+}
+
+/*
+ * Get DDR clock frequency in Hz.
+ */
+static u32 soc_ddr_clk_get(void)
+{
+	int mode = sar_get_clock_freq_mode();
+
+	if (mode < 0)
+		return 0;
+	return pll_freq_tbl[mode][DDR_CLOCK_ID];
+}
+
+/*
+ * Get Ring (Fabric) clock frequency in Hz.
+ */
+static u32 soc_ring_clk_get(void)
+{
+	int mode = sar_get_clock_freq_mode();
+
+	if (mode < 0)
+		return 0;
+	return pll_freq_tbl[mode][RING_CLOCK_ID];
+}
+
+/*
+ * Get MSS clock frequency in Hz.
+ */
+static u32 soc_mss_clk_get(void)
+{
+	return AP806_MSS_CLOCK;
+}
+
+/*
+ * Get LLC status and mode.
+ * Returns 1 if LLC is enabled, 0 otherwise.
+ * If excl_mode is not NULL, sets it to 1 if exclusive mode is enabled.
+ */
+static int llc_mode_get(int *excl_mode)
+{
+	u32 val;
+	int ret = 0, excl = 0;
+
+	val = readl(LLC_BASE + LLC_CTRL);
+	if (val & LLC_CTRL_EN) {
+		ret = 1;
+		if (val & LLC_EXCLUSIVE_EN)
+			excl = 1;
+	}
+	if (excl_mode)
+		*excl_mode = excl;
+
+	return ret;
+}
+
+/*
+ * Print SoC clock information.
+ */
+void soc_print_clock_info(void)
+{
+	printf("Clock:  CPU     %-4d [MHz]\n", soc_cpu_clk_get() / MHz);
+	printf("\tDDR     %-4d [MHz]\n", soc_ddr_clk_get() / MHz);
+	printf("\tFABRIC  %-4d [MHz]\n", soc_ring_clk_get() / MHz);
+	printf("\tMSS     %-4d [MHz]\n", soc_mss_clk_get() / MHz);
+}
+
+/*
+ * Print SoC-specific information: DDR width and LLC status.
+ */
+void soc_print_soc_info(void)
+{
+	int llc_en, llc_excl_mode;
+
+	printf("\tDDR 64 Bit width\n");
+
+	llc_en = llc_mode_get(&llc_excl_mode);
+	printf("\tLLC %s%s\n", llc_en ? "Enabled" : "Disabled",
+	       llc_excl_mode ? " (Exclusive Mode)" : "");
+}

arch/arm/mach-mvebu/armada8k/soc_info.h

@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015 Marvell International Ltd.
+ *
+ * Marvell Armada 8K SoC info functions
+ */
+
+#ifndef _ARMADA8K_SOC_INFO_H_
+#define _ARMADA8K_SOC_INFO_H_
+
+void soc_print_clock_info(void);
+void soc_print_soc_info(void);
+
+#endif /* _ARMADA8K_SOC_INFO_H_ */

arch/arm/mach-omap2/am33xx/board.c

@@ -259,31 +259,34 @@ int arch_misc_init(void)
 {
 	return 0;
 }
-#else	/* CONFIG_USB_MUSB_* && CONFIG_AM335X_USB* && !CONFIG_DM_USB */
+#else /* CONFIG_AM335X_USB* && CONFIG_XPL_BUILD */
 
 int arch_misc_init(void)
 {
 	struct udevice *dev;
-	int ret;
+	int ret = 0;
 
-	/*
-	 * The MUSB wrapper driver is bound as a MISC device, so probe here
-	 * to register the musb device early.
-	 */
-	if (IS_ENABLED(CONFIG_USB_MUSB_TI)) {
+	if (IS_ENABLED(CONFIG_USB_MUSB_TI) && !IS_ENABLED(CONFIG_OF_UPSTREAM)) {
+		/*
+		 * Trigger probe of the UCLASS_MISC device which is a USB
+		 * wrapper driver ti-musb-wrapper that handles all usb host and
+		 * gadget devices. Note that with OF_UPSTREAM the devices are
+		 * bound directly, no wrapper necessary.
+		 */
 		ret = uclass_first_device_err(UCLASS_MISC, &dev);
 		if (ret)
-			return ret;
+			printf("Failed probing USB %d, continue without USB\n", ret);
 	}
 
 #if defined(CONFIG_DM_ETH) && defined(CONFIG_USB_ETHER)
-	usb_ether_init();
+	if (!ret)
+		usb_ether_init();
 #endif
 
 	return 0;
 }
 
-#endif /* CONFIG_USB_MUSB_* && CONFIG_AM335X_USB* && !CONFIG_DM_USB */
+#endif /* CONFIG_AM335X_USB* && CONFIG_XPL_BUILD */
 
 #if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
 

arch/arm/mach-omap2/config_secure.mk

@@ -104,9 +104,9 @@ ifdef CONFIG_SPL_LOAD_FIT
 MKIMAGEFLAGS_u-boot_HS.img = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
 	-a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
 	-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" -E \
-	$(patsubst %,-b arch/$(ARCH)/dts/%.dtb_HS,$(subst ",,$(CONFIG_OF_LIST)))
+	$(patsubst %,-b $(dt_dir)/%.dtb_HS,$(subst ",,$(CONFIG_OF_LIST)))
 
-OF_LIST_TARGETS = $(patsubst %,arch/$(ARCH)/dts/%.dtb,$(subst ",,$(CONFIG_OF_LIST)))
+OF_LIST_TARGETS = $(patsubst %,$(dt_dir)/%.dtb,$(subst ",,$(CONFIG_OF_LIST)))
 $(OF_LIST_TARGETS): dtbs
 
 %.dtb_HS: %.dtb FORCE

arch/mips/include/asm/system.h

@@ -259,9 +259,9 @@ extern void __die_if_kernel(const char *, struct pt_regs *, const char *where,
 	unsigned long line);
 
 #define die(msg, regs)							\
-	__die(msg, regs, __FILE__ ":"__FUNCTION__, __LINE__)
+	__die(msg, regs, __FILE__ ":" __func__, __LINE__)
 #define die_if_kernel(msg, regs)					\
-	__die_if_kernel(msg, regs, __FILE__ ":"__FUNCTION__, __LINE__)
+	__die_if_kernel(msg, regs, __FILE__ ":" __func__, __LINE__)
 
 static inline void execution_hazard_barrier(void)
 {

arch/powerpc/cpu/mpc85xx/liodn.c

@@ -110,7 +110,7 @@ static void setup_fman_liodn_base(enum fsl_dpaa_dev dev,
 		break;
 #endif
 	default:
-		printf("Error: Invalid device type to %s\n", __FUNCTION__);
+		printf("Error: Invalid device type to %s\n", __func__);
 		return;
 	}
 

arch/sandbox/dts/sandbox-boot.sh

@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+echo "* default script"

arch/sandbox/dts/sandbox-inner.sh

@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+# Some comment.
+echo "* inner"

arch/sandbox/dts/sandbox-outer.sh

@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+echo "* outer 1"
+source ${fdtcontroladdr}:inner
+echo "* outer 2"

arch/sandbox/dts/sandbox_scripts.dtsi

@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/ {
+	images {
+		default = "boot";
+		boot {
+			description = "Test boot script";
+			data = /incbin/("sandbox-boot.sh");
+			type = "script";
+			compression = "none";
+		};
+		outer {
+			description = "Script testing recursion";
+			data = /incbin/("sandbox-outer.sh");
+			type = "script";
+			compression = "none";
+		};
+		inner {
+			description = "Another test script";
+			data = /incbin/("sandbox-inner.sh");
+			type = "script";
+			compression = "none";
+		};
+	};
+};

board/Marvell/guruplug/guruplug.c

@@ -111,7 +111,7 @@ void mv_phy_88e1121_init(char *name)
 	/* command to read PHY dev address */
 	if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
 		printf("Err..%s could not read PHY dev address\n",
-			__FUNCTION__);
+			__func__);
 		return;
 	}
 

board/Marvell/mvebu_armada-37xx/board.c

@@ -102,11 +102,6 @@ static bool is_edpu_plus(void)
 		return false;
 }
 
-int board_early_init_f(void)
-{
-	return 0;
-}
-
 int board_init(void)
 {
 	/* adress of boot parameters */

board/Synology/common/Makefile

@@ -2,4 +2,4 @@
 #
 # Copyright (C) 2021 Phil Sutter <phil@nwl.cc>
 
-obj-$(SUPPORT_PASSING_ATAGS)	+= legacy.o
+obj-$(CONFIG_SUPPORT_PASSING_ATAGS)	+= legacy.o

board/Synology/common/legacy.c

@@ -10,6 +10,7 @@
 #include <vsprintf.h>
 #include <env.h>
 #include <net.h>
+#include <asm/io.h>
 #include <asm/setup.h>
 
 #include "legacy.h"

board/alliedtelesis/x220/.gitattributes

@@ -0,0 +1 @@
+binary.0 binary

board/alliedtelesis/x220/.gitignore

@@ -0,0 +1 @@
+kwbimage.cfg

board/alliedtelesis/x220/MAINTAINERS

@@ -0,0 +1,8 @@
+x220 BOARD
+M:	Chris Packham <chris.packham@alliedtelesis.co.nz>
+S:	Maintained
+F:	board/alliedtelesis/x220
+F:	include/configs/x220.h
+F:	configs/x220_defconfig
+F:	arch/arm/dts/armada-xp-atl-x220.dts
+F:	doc/board/alliedtelesis/x220.rst

board/alliedtelesis/x220/Makefile

@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2025 Allied Telesis Labs
+
+obj-y	:= x220.o
+extra-y	:= kwbimage.cfg
+
+quiet_cmd_sed = SED     $@
+      cmd_sed = sed $(SEDFLAGS_$(@F)) $< >$(dir $@)$(@F)
+
+SEDFLAGS_kwbimage.cfg =-e "s|^BINARY.*|BINARY $(srctree)/$(@D)/binary.0 0000005b 00000068|"
+$(obj)/kwbimage.cfg: $(src)/kwbimage.cfg.in include/autoconf.mk \
+		include/config/auto.conf
+	  $(call if_changed,sed)

board/alliedtelesis/x220/binary.0

@@ -0,0 +1,11 @@
+--------
+WARNING:
+--------
+This file should contain the bin_hdr generated by the original Marvell
+U-Boot implementation. As this is currently not included in this
+U-Boot version, we have added this placeholder, so that the U-Boot
+image can be generated without errors.
+
+If you have a known to be working bin_hdr for your board, then you
+just need to replace this text file here with the binary header
+and recompile U-Boot.

board/alliedtelesis/x220/kwbimage.cfg.in

@@ -0,0 +1,12 @@
+#
+# Copyright (C) 2025 Allied Telesis Labs
+#
+
+# Armada XP uses version 1 image format
+VERSION		1
+
+# Boot Media configurations
+BOOT_FROM	spi
+
+# Binary Header (bin_hdr) with DDR3 training code
+BINARY board/alliedtelesis/x220/binary.0 0000005b 00000068

board/alliedtelesis/x220/x220.c

@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2025 Allied Telesis Labs
+ */
+
+#include <i2c.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/gpio.h>
+#include <linux/bitops.h>
+#include <linux/mbus.h>
+#include <linux/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define X220_GPP_OUT_ENA_LOW	(~(BIT(12) | BIT(17) | BIT(18) | BIT(31)))
+#define X220_GPP_OUT_ENA_MID	(~(0))
+#define X220_GPP_OUT_VAL_LOW	(BIT(12) | BIT(18))
+#define X220_GPP_OUT_VAL_MID	0x0
+#define X220_GPP_POL_LOW	0x0
+#define X220_GPP_POL_MID	0x0
+
+int board_early_init_f(void)
+{
+	/* Configure MPP */
+	writel(0x44042222, MVEBU_MPP_BASE + 0x00);
+	writel(0x11000004, MVEBU_MPP_BASE + 0x04);
+	writel(0x44444004, MVEBU_MPP_BASE + 0x08);
+	writel(0x04444444, MVEBU_MPP_BASE + 0x0c);
+	writel(0x00000004, MVEBU_MPP_BASE + 0x10);
+
+	/* Set GPP Out value */
+	writel(X220_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
+	writel(X220_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
+
+	/* Set GPP Polarity */
+	writel(X220_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
+	writel(X220_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
+
+	/* Set GPP Out Enable */
+	writel(X220_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
+	writel(X220_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+	/* Disable MBUS Err Prop - in order to avoid data aborts */
+	clrbits_le32(MVEBU_CPU_WIN_BASE + 0x200, (1 << 8));
+
+	return 0;
+}
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
+{
+	puts("Board: Allied Telesis x220\n");
+
+	return 0;
+}
+#endif

board/axiado/scm3005/Kconfig

@@ -0,0 +1,15 @@
+if TARGET_SCM3005
+
+config SYS_BOARD
+	string
+	default "scm3005"
+
+config SYS_VENDOR
+	string
+	default "axiado"
+
+config SYS_CONFIG_NAME
+	string
+	default "ax3005-scm3005"
+
+endif

board/axiado/scm3005/Makefile

@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2021-2026 Axiado Corporation (or its affiliates).
+
+obj-y := scm3005.o

board/axiado/scm3005/scm3005.c

@@ -0,0 +1,128 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2021-2026 Axiado Corporation (or its affiliates).
+ */
+
+#include <config.h>
+#include <dm.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/armv8/mmu.h>
+#include <asm/io.h>
+#include <asm/spin_table.h>
+#include <asm/system.h>
+#include <fdt_support.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct mm_region axiado_ax3005_mem_map[] = {
+	{ /* Peripherals including UART */
+	  .virt = 0x00000000UL,
+	  .phys = 0x00000000UL,
+	  .size = 0x4A000000UL, /* 0 to 0x4A000000: peripherals */
+	  .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE |
+		   PTE_BLOCK_PXN | PTE_BLOCK_UXN },
+	{ .virt = 0x80000000UL,
+	  .phys = 0x80000000UL,
+	  .size = 0x80000000UL,
+	  .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE },
+	{
+		0,
+	}
+};
+
+struct mm_region *mem_map = axiado_ax3005_mem_map;
+
+/*
+ * Accept any FIT configuration name - the board loads a single FIT image
+ * and the first matching config is used.
+ */
+int board_fit_config_name_match(const char *name)
+{
+	return 0;
+}
+
+/*
+ * ft_board_setup - restore cpu-release-addr after relocation
+ *
+ * arch_fixup_fdt() / spin_table_update_dt() overwrites cpu-release-addr
+ * with U-Boot's relocated address.  Restore the pre-relocation physical
+ * address so secondary cores spin on the correct location.
+ */
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	int cpus_offset, offset;
+	const char *prop;
+	int ret;
+	u64 cpu_release_addr = (u64)&spin_table_cpu_release_addr - gd->reloc_off;
+
+	cpus_offset = fdt_path_offset(blob, "/cpus");
+	if (cpus_offset < 0)
+		return 0;
+
+	for (offset = fdt_first_subnode(blob, cpus_offset); offset >= 0;
+	     offset = fdt_next_subnode(blob, offset)) {
+		prop = fdt_getprop(blob, offset, "device_type", NULL);
+		if (!prop || strcmp(prop, "cpu"))
+			continue;
+
+		prop = fdt_getprop(blob, offset, "enable-method", NULL);
+		if (!prop || strcmp(prop, "spin-table"))
+			continue;
+
+		ret = fdt_setprop_u64(blob, offset, "cpu-release-addr",
+				      cpu_release_addr);
+		if (ret) {
+			printf("WARNING: Failed to restore cpu-release-addr\n");
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+/*
+ * dram_init - DDR is initialized by firmware, just setting size
+ */
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+				    CFG_SYS_SDRAM_SIZE);
+	return 0;
+}
+
+/*
+ * the SOC uses single bank, non-interleaving
+ */
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].size = CFG_SYS_SDRAM_SIZE;
+	return 0;
+}
+
+/*
+ * timer_init - enable the AX3005 platform system timer
+ *
+ * CNTFRQ_EL0 is already set by arch/arm/cpu/armv8/start.S using
+ * CONFIG_COUNTER_FREQUENCY from the defconfig.
+ *
+ * SYS_TIMER_CTRL (0x48016000) is the AX3005 system timer control
+ * register — writing SYS_TIMER_ENABLE starts the counter that feeds
+ * the ARM generic timer.
+ */
+int timer_init(void)
+{
+	writel(SYS_TIMER_ENABLE, SYS_TIMER_CTRL);
+	return 0;
+}
+
+int board_init(void)
+{
+	return 0;
+}
+
+void reset_cpu(void)
+{
+	/* For later ARM_PSCI_FW or watchdog reset */
+}

board/freebox/nbx10g/Kconfig

@@ -0,0 +1,94 @@
+if TARGET_NBX10G
+
+config SYS_BOARD
+	default "nbx10g"
+
+config SYS_VENDOR
+	default "freebox"
+
+config SYS_CONFIG_NAME
+	default "nbx10g"
+
+config CMD_NBX_EMMCBOOT
+	bool "emmcboot command"
+	depends on MMC_SDHCI_XENON
+	help
+	  Enable the emmcboot command for dual-bank boot from eMMC.
+	  This is a legacy boot format used on this board for many years.
+	  It implements a boot system with two image banks and automatic
+	  fallback on boot failures. The boot order depends on a reboot
+	  tracking counter (nrboot):
+	  - If healthy: try Bank1 (newer) first, then Bank0 (stable)
+	  - If degraded (>= 4 failures): try Bank0 first, then Bank1
+
+	  Requires image_addr and fdt_addr environment variables to be set.
+
+if CMD_NBX_EMMCBOOT
+
+config NBX_MMC_PART_NRBOOT_OFFSET
+	hex "NRBoot counter offset in eMMC"
+	default 0x802000
+	help
+	  Byte offset in eMMC where the reboot tracking counter is stored.
+	  Default: 0x802000 (8MB + 8KB)
+
+config NBX_MMC_PART_BANK0_OFFSET
+	hex "Bank0 image offset in eMMC"
+	default 0x804000
+	help
+	  Byte offset in eMMC where the stable (Bank0) boot image starts.
+	  Default: 0x804000 (8MB + 16KB)
+
+config NBX_MMC_PART_BANK0_SIZE
+	hex "Bank0 image maximum size"
+	default 0x10000000
+	help
+	  Maximum size of the Bank0 boot image.
+	  Default: 0x10000000 (256MB)
+
+config NBX_MMC_PART_BANK1_OFFSET
+	hex "Bank1 image offset in eMMC"
+	default 0x10804000
+	help
+	  Byte offset in eMMC where the newer (Bank1) boot image starts.
+	  Default: 0x10804000 (264MB + 16KB)
+
+config NBX_MMC_PART_BANK1_SIZE
+	hex "Bank1 image maximum size"
+	default 0x10000000
+	help
+	  Maximum size of the Bank1 boot image.
+	  Default: 0x10000000 (256MB)
+
+endif
+
+config CMD_NBX_FBXSERIAL
+	bool "fbxserial command"
+	depends on MMC_SDHCI_XENON
+	help
+	  Enable the fbxserial command to read and display device
+	  serial information from eMMC. This includes:
+	  - Device serial number (type, version, manufacturer, date, number)
+	  - MAC address (used to set ethaddr environment variables)
+	  - Bundle information (if present)
+
+	  The serial info is stored at a fixed offset in the eMMC user area.
+
+	  Subcommands:
+	  - fbxserial show: display serial info (default)
+	  - fbxserial init: initialize ethaddr from serial info
+
+	  Use CONFIG_PREBOOT="fbxserial init" to auto-initialize at boot.
+
+if CMD_NBX_FBXSERIAL
+
+config NBX_MMC_PART_SERIAL_OFFSET
+	hex "Serial info offset in eMMC"
+	default 0x800000
+	help
+	  Byte offset in eMMC where the serial info structure is stored.
+	  Default: 0x800000 (8MB)
+
+endif
+
+endif

board/freebox/nbx10g/MAINTAINERS

@@ -0,0 +1,6 @@
+NBX10G BOARD
+M:	Vincent Jardin <vjardin@free.fr>
+S:	Maintained
+F:	board/freebox/nbx10g/
+F:	configs/mvebu_nbx_88f8040_defconfig
+F:	arch/arm/dts/armada-8040-nbx*

board/freebox/nbx10g/Makefile

@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y	:= board.o
+obj-$(CONFIG_CMD_NBX_EMMCBOOT)	+= nbx_emmcboot.o
+obj-$(CONFIG_CMD_NBX_FBXSERIAL)	+= nbx_fbxserial.o

board/freebox/nbx10g/board.c

@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017-2018 Freebox SA
+ * Copyright (C) 2026 Free Mobile, Vincent Jardin <vjardin@free.fr>
+ *
+ * Freebox Nodebox 10G board support
+ */
+
+#include <init.h>
+#include <asm/gpio.h>
+#include <linux/delay.h>
+
+/* Management PHY reset GPIO */
+#define NBX_PHY_RESET_GPIO	83
+
+/* Nodebox 10G ASCII art logo */
+static const char * const nbx_logo =
+	"  _   _           _      _                 __  ___   _____\n"
+	" | \\ | |         | |    | |               /_ |/ _ \\ / ____|\n"
+	" |  \\| | ___   __| | ___| |__   _____  __  | | | | | |  __\n"
+	" | . ` |/ _ \\ / _` |/ _ \\ '_ \\ / _ \\ \\/ /  | | | | | | |_ |\n"
+	" | |\\  | (_) | (_| |  __/ |_) | (_) >  <   | | |_| | |__| |\n"
+	" |_| \\_|\\___/ \\__,_|\\___|_.__/ \\___/_/\\_\\  |_|\\___/ \\_____|\n";
+
+int checkboard(void)
+{
+	printf("%s\n", nbx_logo);
+	return 0;
+}
+
+int board_init(void)
+{
+	return 0;
+}
+
+int board_late_init(void)
+{
+	int ret;
+
+	/* Reset the management PHY */
+	ret = gpio_request(NBX_PHY_RESET_GPIO, "phy-reset");
+	if (ret) {
+		printf("Failed to request PHY reset GPIO: %d\n", ret);
+		return 0;
+	}
+
+	gpio_direction_output(NBX_PHY_RESET_GPIO, 0);
+	mdelay(100);
+	gpio_set_value(NBX_PHY_RESET_GPIO, 1);
+	mdelay(100);
+
+	return 0;
+}

board/freebox/nbx10g/nbx_emmcboot.c

@@ -0,0 +1,357 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Nodebox 10G dual-bank eMMC boot command with automatic fallback
+ *
+ * Copyright (C) 2026 Free Mobile, Freebox
+ *
+ * This implements a dual-bank boot system with automatic fallback:
+ * - Bank0: Stable/fallback boot image
+ * - Bank1: Newer/test boot image
+ *
+ * The boot order depends on the reboot tracking counter (nrboot):
+ * - If healthy: try Bank1 first, then Bank0
+ * - If degraded (>= 4 failures): try Bank0 first, then Bank1
+ */
+
+#include <command.h>
+#include <env.h>
+#include <mmc.h>
+#include <malloc.h>
+#include <memalign.h>
+#include <vsprintf.h>
+#include <u-boot/crc.h>
+#include <u-boot/schedule.h>
+#include <asm/byteorder.h>
+#include <linux/errno.h>
+#include "nbx_imagetag.h"
+#include "nbx_nrboot.h"
+
+/* Partition offsets defined in Kconfig (CONFIG_NBX_MMC_PART_*) */
+
+/* Image Tag Functions */
+
+static int mvebu_imagetag_check(struct mvebu_image_tag *tag,
+				unsigned long maxsize, const char *name)
+{
+	if (be32_to_cpu(tag->magic) != MVEBU_IMAGE_TAG_MAGIC) {
+		if (name)
+			printf("%s: invalid TAG magic: %.8x\n", name,
+			       be32_to_cpu(tag->magic));
+		return -EINVAL;
+	}
+
+	if (be32_to_cpu(tag->version) != MVEBU_IMAGE_TAG_VERSION) {
+		if (name)
+			printf("%s: invalid TAG version: %.8x\n", name,
+			       be32_to_cpu(tag->version));
+		return -EINVAL;
+	}
+
+	if (be32_to_cpu(tag->total_size) < sizeof(*tag)) {
+		if (name)
+			printf("%s: tag size is too small!\n", name);
+		return -EINVAL;
+	}
+
+	if (be32_to_cpu(tag->total_size) > maxsize) {
+		if (name)
+			printf("%s: tag size is too big!\n", name);
+		return -EINVAL;
+	}
+
+	if (be32_to_cpu(tag->device_tree_offset) < sizeof(*tag) ||
+	    be32_to_cpu(tag->device_tree_offset) +
+	    be32_to_cpu(tag->device_tree_size) > maxsize) {
+		if (name)
+			printf("%s: bogus device tree offset/size!\n", name);
+		return -EINVAL;
+	}
+
+	if (be32_to_cpu(tag->kernel_offset) < sizeof(*tag) ||
+	    be32_to_cpu(tag->kernel_offset) +
+	    be32_to_cpu(tag->kernel_size) > maxsize) {
+		if (name)
+			printf("%s: bogus kernel offset/size!\n", name);
+		return -EINVAL;
+	}
+
+	if (be32_to_cpu(tag->rootfs_offset) < sizeof(*tag) ||
+	    be32_to_cpu(tag->rootfs_offset) +
+	    be32_to_cpu(tag->rootfs_size) > maxsize) {
+		if (name)
+			printf("%s: bogus rootfs offset/size!\n", name);
+		return -EINVAL;
+	}
+
+	if (name) {
+		/*
+		 * Ensure null-termination within the 32-byte fields
+		 * before printing to avoid displaying garbage.
+		 */
+		tag->image_name[sizeof(tag->image_name) - 1] = '\0';
+		tag->build_date[sizeof(tag->build_date) - 1] = '\0';
+		tag->build_user[sizeof(tag->build_user) - 1] = '\0';
+
+		printf("%s: Found valid tag: %s / %s / %s\n", name,
+		       tag->image_name, tag->build_date, tag->build_user);
+	}
+
+	return 0;
+}
+
+static int mvebu_imagetag_crc(struct mvebu_image_tag *tag, const char *name)
+{
+	u32 crc = ~0;
+
+	crc = crc32(crc, ((unsigned char *)tag) + 4,
+		    be32_to_cpu(tag->total_size) - 4);
+
+	if (be32_to_cpu(tag->crc) != crc) {
+		if (name)
+			printf("%s: invalid tag CRC!\n", name);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+/* NRBoot (Reboot Tracking) Functions */
+
+struct mvebu_nrboot {
+	u16 nrboot;
+	u16 nrsuccess;
+};
+
+#define MVEBU_MAX_FAILURE	4
+
+static int mvebu_count_bits(u16 val)
+{
+	int i, found = 0;
+
+	for (i = 0; i < 16; i++) {
+		if (val & (1 << i))
+			found++;
+	}
+	return found;
+}
+
+int mvebu_check_nrboot(struct mmc *mmc, unsigned long offset)
+{
+	struct blk_desc *bd = mmc_get_blk_desc(mmc);
+	struct mvebu_nrboot *nr;
+	uint blk_start = ALIGN(offset, bd->blksz) / bd->blksz;
+	uint blk_cnt = ALIGN(sizeof(*nr), bd->blksz) / bd->blksz;
+	uint n;
+
+	ALLOC_CACHE_ALIGN_BUFFER(char, buf, blk_cnt * bd->blksz);
+	nr = (void *)buf;
+
+	n = blk_dread(bd, blk_start, blk_cnt, buf);
+	if (n != blk_cnt)
+		return 0;
+
+	printf(" - nr.nrboot = %04x\n", nr->nrboot);
+	printf(" - nr.nrsuccess = %04x\n", nr->nrsuccess);
+
+	/* Sanity check on values */
+	if (mvebu_count_bits(~nr->nrboot + 1) <= 1 &&
+	    mvebu_count_bits(~nr->nrsuccess + 1) <= 1) {
+		int boot, success;
+
+		boot = 16 - mvebu_count_bits(nr->nrboot);
+		success = 16 - mvebu_count_bits(nr->nrsuccess);
+
+		printf(" - Nrboot: %d / Nrsuccess: %d\n", boot, success);
+
+		if (boot == 16 || boot < success ||
+		    boot - success >= MVEBU_MAX_FAILURE) {
+			printf(" - Nrboot exceeded\n");
+			return 0;
+		}
+
+		/* Increment boot attempt counter */
+		boot++;
+		nr->nrboot = ~((1 << boot) - 1);
+
+		printf(" - Setting Nrboot to %d\n", boot);
+
+		n = blk_dwrite(bd, blk_start, blk_cnt, buf);
+		if (n != blk_cnt)
+			return 0;
+
+		return 1;
+	}
+
+	printf(" - Invalid NR values\n");
+
+	return 0;
+}
+
+/* emmcboot Command */
+
+static void mvebu_try_emmcboot(struct mmc *mmc, unsigned long offset,
+			       unsigned long maxsize, const char *bank)
+{
+	struct blk_desc *bd = mmc_get_blk_desc(mmc);
+	struct mvebu_image_tag *tag;
+	ulong image_addr = 0;
+	ulong fdt_addr = 0;
+	ulong tag_addr;
+	uint tag_blk_start = ALIGN(offset, bd->blksz) / bd->blksz;
+	uint tag_blk_cnt = ALIGN(sizeof(*tag), bd->blksz) / bd->blksz;
+	uint n;
+
+	ALLOC_CACHE_ALIGN_BUFFER(char, tag_buf, tag_blk_cnt * bd->blksz);
+	tag = (void *)tag_buf;
+
+	schedule();
+
+	printf("## Trying %s boot...\n", bank);
+
+	/* Load tag header */
+	n = blk_dread(bd, tag_blk_start, tag_blk_cnt, tag_buf);
+	if (n != tag_blk_cnt) {
+		printf("%s: failed to read tag header\n", bank);
+		return;
+	}
+
+	if (mvebu_imagetag_check(tag, maxsize, bank) != 0)
+		return;
+
+	if (tag->rootfs_size != 0) {
+		printf("%s: rootfs in tag not supported\n", bank);
+		return;
+	}
+
+	/* Get image and device tree load addresses from environment */
+	image_addr = env_get_ulong("image_addr", 16, 0);
+	if (!image_addr) {
+		puts("emmcboot needs image_addr\n");
+		return;
+	}
+
+	fdt_addr = env_get_ulong("fdt_addr", 16, 0);
+	if (!fdt_addr) {
+		puts("emmcboot needs fdt_addr\n");
+		return;
+	}
+
+	tag_addr = image_addr;
+
+	/* Load full image, temporarily reuse image_addr for this */
+	{
+		uint data_blk_start = ALIGN(offset, bd->blksz) / bd->blksz;
+		uint data_blk_cnt = ALIGN(mvebu_imagetag_total_size(tag),
+					  bd->blksz) / bd->blksz;
+
+		n = blk_dread(bd, data_blk_start, data_blk_cnt, (void *)tag_addr);
+		if (n != data_blk_cnt) {
+			printf("%s: failed to read full image\n", bank);
+			return;
+		}
+
+		if (mvebu_imagetag_crc((void *)tag_addr, bank) != 0)
+			return;
+	}
+
+	schedule();
+
+	/* Copy image and device tree to the right addresses */
+	/* We assume that image_addr + tag_size < fdt_addr */
+	{
+		tag = (void *)tag_addr;
+		memcpy((void *)fdt_addr,
+		       ((void *)tag_addr) + mvebu_imagetag_device_tree_offset(tag),
+		       mvebu_imagetag_device_tree_size(tag));
+		memmove((void *)image_addr,
+			((void *)tag_addr) + mvebu_imagetag_kernel_offset(tag),
+			mvebu_imagetag_kernel_size(tag));
+	}
+
+	schedule();
+
+	/* Set bootargs and boot */
+	{
+		char bootargs[256];
+		char *console_env;
+
+		console_env = env_get("console");
+		if (console_env)
+			snprintf(bootargs, sizeof(bootargs), "%s bank=%s",
+				 console_env, bank);
+		else
+			snprintf(bootargs, sizeof(bootargs), "bank=%s", bank);
+
+		env_set("bootargs", bootargs);
+
+		printf("## Booting kernel from %s...\n", bank);
+		printf("   Image addr: 0x%lx\n", image_addr);
+		printf("   FDT addr:   0x%lx\n", fdt_addr);
+
+		/* Build and run booti command */
+		{
+			char cmd[128];
+
+			snprintf(cmd, sizeof(cmd), "booti 0x%lx - 0x%lx",
+				 image_addr, fdt_addr);
+			run_command(cmd, 0);
+		}
+	}
+
+	printf("## %s boot failed\n", bank);
+}
+
+static int do_emmcboot(struct cmd_tbl *cmdtp, int flag, int argc,
+		       char *const argv[])
+{
+	int dev;
+	struct mmc *mmc;
+
+	dev = 0;
+	if (argc >= 2)
+		dev = dectoul(argv[1], NULL);
+
+	mmc = find_mmc_device(dev);
+	if (!mmc) {
+		printf("No MMC device %d found\n", dev);
+		return CMD_RET_FAILURE;
+	}
+
+	if (mmc_init(mmc)) {
+		puts("MMC init failed\n");
+		return CMD_RET_FAILURE;
+	}
+
+	/* Switch to partition 0 (user data area) */
+	if (blk_select_hwpart_devnum(UCLASS_MMC, dev, 0)) {
+		puts("MMC partition switch failed\n");
+		return CMD_RET_FAILURE;
+	}
+
+	if (mvebu_check_nrboot(mmc, CONFIG_NBX_MMC_PART_NRBOOT_OFFSET)) {
+		/* System is healthy: try newer bank first */
+		mvebu_try_emmcboot(mmc, CONFIG_NBX_MMC_PART_BANK1_OFFSET,
+				   CONFIG_NBX_MMC_PART_BANK1_SIZE, "bank1");
+		mvebu_try_emmcboot(mmc, CONFIG_NBX_MMC_PART_BANK0_OFFSET,
+				   CONFIG_NBX_MMC_PART_BANK0_SIZE, "bank0");
+	} else {
+		/* System is degraded: use stable bank first */
+		mvebu_try_emmcboot(mmc, CONFIG_NBX_MMC_PART_BANK0_OFFSET,
+				   CONFIG_NBX_MMC_PART_BANK0_SIZE, "bank0");
+		mvebu_try_emmcboot(mmc, CONFIG_NBX_MMC_PART_BANK1_OFFSET,
+				   CONFIG_NBX_MMC_PART_BANK1_SIZE, "bank1");
+	}
+
+	puts("emmcboot: all boot attempts failed\n");
+	return CMD_RET_FAILURE;
+}
+
+U_BOOT_CMD(
+	emmcboot, 2, 0, do_emmcboot,
+	"boot from MVEBU eMMC image banks",
+	"[dev]\n"
+	"    - Boot from eMMC device <dev> (default 0)\n"
+	"    - Requires image_addr and fdt_addr environment variables\n"
+	"    - Uses dual-bank boot with automatic fallback\n"
+	"    - Bank selection based on reboot tracking (nrboot)"
+);

board/freebox/nbx10g/nbx_fbxserial.c

@@ -0,0 +1,286 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * NBX Freebox Serial Info Support
+ *
+ * Copyright (C) 2025 Free Mobile, Freebox
+ *
+ * Reads device serial number and MAC address from eMMC.
+ * The serial info is stored at a fixed offset in the eMMC user area.
+ *
+ * Serial format: TTTT-VV-M-(YY)WW-NN-NNNNN / FLAGS
+ * Where:
+ *   TTTT  = Device type (e.g., 9018)
+ *   VV    = Board version
+ *   M     = Manufacturer code (ASCII)
+ *   YY    = Year (BCD)
+ *   WW    = Week (1-53)
+ *   NNNNN = Serial number
+ *   FLAGS = Feature flags
+ */
+
+#include <command.h>
+#include <dm/device.h>
+#include <env.h>
+#include <event.h>
+#include <mmc.h>
+#include <malloc.h>
+#include <memalign.h>
+#include <vsprintf.h>
+#include <u-boot/crc.h>
+#include <asm/byteorder.h>
+#include <linux/ctype.h>
+#include <linux/errno.h>
+#include "nbx_fbxserial.h"
+
+/* Partition offset defined in Kconfig (CONFIG_NBX_MMC_PART_SERIAL_OFFSET) */
+
+/*
+ * Validate serial info structure
+ */
+static int nbx_fbx_check_serial(struct nbx_fbx_serial *fs)
+{
+	unsigned int sum, len;
+
+	/* Check magic first */
+	if (be32_to_cpu(fs->magic) != NBX_FBXSERIAL_MAGIC) {
+		printf("Invalid magic for serial info (%08x != %08x)!\n",
+		       be32_to_cpu(fs->magic), NBX_FBXSERIAL_MAGIC);
+		return -EINVAL;
+	}
+
+	/* Check struct version */
+	if (be32_to_cpu(fs->struct_version) > NBX_FBXSERIAL_VERSION) {
+		printf("Version too big for fbxserial info (0x%08x)!\n",
+		       be32_to_cpu(fs->struct_version));
+		return -EINVAL;
+	}
+
+	/* Check for silly len */
+	len = be32_to_cpu(fs->len);
+	if (len > NBX_FBXSERIAL_MAX_SIZE) {
+		printf("Silly len for serial info (%d)\n", len);
+		return -EINVAL;
+	}
+
+	/* Validate CRC (crc32_no_comp: no one's complement) */
+	sum = crc32_no_comp(0, (void *)fs + 4, len - 4);
+	if (be32_to_cpu(fs->crc32) != sum) {
+		printf("Invalid checksum for serial info (%08x != %08x)\n",
+		       sum, be32_to_cpu(fs->crc32));
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+int nbx_fbx_read_serial(int dev_num, unsigned long offset,
+			struct nbx_fbx_serial *fs)
+{
+	struct mmc *mmc;
+	struct blk_desc *bd;
+	uint blk_start, blk_cnt;
+	uint n;
+
+	ALLOC_CACHE_ALIGN_BUFFER(char, buf, ALIGN(sizeof(*fs), 512));
+	mmc = find_mmc_device(dev_num);
+	if (!mmc) {
+		printf("No MMC device %d found\n", dev_num);
+		nbx_fbxserial_set_default(fs);
+		return -ENODEV;
+	}
+
+	if (mmc_init(mmc)) {
+		puts("MMC init failed\n");
+		nbx_fbxserial_set_default(fs);
+		return -EIO;
+	}
+
+	/* Switch to partition 0 (user data area) */
+	if (blk_select_hwpart_devnum(UCLASS_MMC, dev_num, 0)) {
+		puts("MMC partition switch failed\n");
+		nbx_fbxserial_set_default(fs);
+		return -EIO;
+	}
+
+	bd = mmc_get_blk_desc(mmc);
+	if (!bd) {
+		puts("Failed to get MMC block descriptor\n");
+		nbx_fbxserial_set_default(fs);
+		return -EIO;
+	}
+
+	blk_start = ALIGN(offset, bd->blksz) / bd->blksz;
+	blk_cnt = ALIGN(sizeof(*fs), bd->blksz) / bd->blksz;
+
+	memset(fs, 0x42, sizeof(*fs));
+
+	n = blk_dread(bd, blk_start, blk_cnt, buf);
+	if (n != blk_cnt) {
+		printf("Failed to read serial info from MMC\n");
+		nbx_fbxserial_set_default(fs);
+		return -EIO;
+	}
+
+	memcpy(fs, buf, sizeof(*fs));
+
+	if (nbx_fbx_check_serial(fs) != 0) {
+		nbx_fbxserial_set_default(fs);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+void nbx_fbx_dump_serial(struct nbx_fbx_serial *fs)
+{
+	int i;
+
+	printf("Serial: %04u-%02u-%c-(%02u)%02u-%02u-%05u / %08x\n",
+	       ntohs(fs->type),
+	       fs->version,
+	       isprint(fs->manufacturer) ? fs->manufacturer : '?',
+	       ntohs(fs->year) / 100,
+	       ntohs(fs->year) % 100,
+	       fs->week,
+	       ntohl(fs->number),
+	       ntohl(fs->flags));
+
+	printf("Mac:    %02X:%02X:%02X:%02X:%02X:%02X\n",
+	       fs->mac_addr_base[0],
+	       fs->mac_addr_base[1],
+	       fs->mac_addr_base[2],
+	       fs->mac_addr_base[3],
+	       fs->mac_addr_base[4],
+	       fs->mac_addr_base[5]);
+
+	/* Show bundle info */
+	for (i = 0; i < be32_to_cpu(fs->extinfo_count); i++) {
+		struct nbx_serial_extinfo *p;
+
+		if (i >= NBX_EXTINFO_MAX_COUNT)
+			break;
+
+		p = &fs->extinfos[i];
+		if (be32_to_cpu(p->type) == NBX_EXTINFO_TYPE_EXTDEV &&
+		    be32_to_cpu(p->u.extdev.type) == NBX_EXTDEV_TYPE_BUNDLE) {
+			/* Ensure null termination */
+			p->u.extdev.serial[sizeof(p->u.extdev.serial) - 1] = 0;
+			printf("Bundle: %s\n", p->u.extdev.serial);
+		}
+	}
+
+	printf("\n");
+}
+
+int nbx_fbx_init_ethaddr(int dev_num, unsigned long offset)
+{
+	struct nbx_fbx_serial fs;
+	char mac[32];
+	int ret;
+
+	ret = nbx_fbx_read_serial(dev_num, offset, &fs);
+
+	/* Even on error, fs has default values set */
+	snprintf(mac, sizeof(mac), "%02x:%02x:%02x:%02x:%02x:%02x",
+		 fs.mac_addr_base[0], fs.mac_addr_base[1],
+		 fs.mac_addr_base[2], fs.mac_addr_base[3],
+		 fs.mac_addr_base[4], fs.mac_addr_base[5]);
+
+	nbx_fbx_dump_serial(&fs);
+
+	env_set("ethaddr", mac);
+	env_set("eth1addr", mac);
+	env_set("eth2addr", mac);
+
+	return ret;
+}
+
+/*
+ * fbxserial show - display serial info from eMMC
+ */
+static int do_fbxserial_show(struct cmd_tbl *cmdtp, int flag, int argc,
+			     char *const argv[])
+{
+	struct nbx_fbx_serial fs;
+	int dev = 0;
+	unsigned long offset = CONFIG_NBX_MMC_PART_SERIAL_OFFSET;
+
+	if (argc >= 1)
+		dev = dectoul(argv[0], NULL);
+
+	if (argc >= 2)
+		offset = hextoul(argv[1], NULL);
+
+	if (nbx_fbx_read_serial(dev, offset, &fs) != 0)
+		printf("Warning: Using default serial info\n");
+
+	nbx_fbx_dump_serial(&fs);
+
+	return CMD_RET_SUCCESS;
+}
+
+/*
+ * fbxserial init - initialize ethaddr from serial info
+ */
+static int do_fbxserial_init(struct cmd_tbl *cmdtp, int flag, int argc,
+			     char *const argv[])
+{
+	int dev = 0;
+	unsigned long offset = CONFIG_NBX_MMC_PART_SERIAL_OFFSET;
+
+	if (argc >= 1)
+		dev = dectoul(argv[0], NULL);
+
+	if (argc >= 2)
+		offset = hextoul(argv[1], NULL);
+
+	return nbx_fbx_init_ethaddr(dev, offset);
+}
+
+static struct cmd_tbl cmd_fbxserial_sub[] = {
+	U_BOOT_CMD_MKENT(show, 3, 0, do_fbxserial_show, "", ""),
+	U_BOOT_CMD_MKENT(init, 3, 0, do_fbxserial_init, "", ""),
+};
+
+static int do_fbxserial(struct cmd_tbl *cmdtp, int flag, int argc,
+			char *const argv[])
+{
+	struct cmd_tbl *cp;
+
+	/* Default to 'show' if no subcommand */
+	if (argc < 2)
+		return do_fbxserial_show(cmdtp, flag, 0, NULL);
+
+	cp = find_cmd_tbl(argv[1], cmd_fbxserial_sub,
+			  ARRAY_SIZE(cmd_fbxserial_sub));
+
+	if (!cp)
+		return CMD_RET_USAGE;
+
+	return cp->cmd(cmdtp, flag, argc - 2, argv + 2);
+}
+
+U_BOOT_CMD(
+	fbxserial, 5, 0, do_fbxserial,
+	"NBX serial info and MAC address initialization",
+	"show [dev] [offset] - display serial info from eMMC\n"
+	"fbxserial init [dev] [offset] - initialize ethaddr from serial info\n"
+	"    dev    - MMC device number (default 0)\n"
+	"    offset - offset in eMMC in hex (default from Kconfig)"
+);
+
+/*
+ * Early init hook: Set MAC address from eMMC serial info before
+ * network driver probes. EVT_SETTINGS_R is triggered after MMC
+ * is available but before initr_net().
+ */
+static int nbx_fbx_settings_r(void)
+{
+	if (!of_machine_is_compatible("nbx,armada8040"))
+		return 0;
+
+	nbx_fbx_init_ethaddr(0, CONFIG_NBX_MMC_PART_SERIAL_OFFSET);
+	return 0;
+}
+
+EVENT_SPY_SIMPLE(EVT_SETTINGS_R, nbx_fbx_settings_r);

board/freebox/nbx10g/nbx_fbxserial.h

@@ -0,0 +1,156 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * NBX Freebox Serial Info Support
+ *
+ * Copyright (C) 2025 Free Mobile, Freebox
+ *
+ * Reads device serial number and MAC address from eMMC.
+ * Used to identify the board and set network MAC addresses.
+ */
+
+#ifndef NBX_FBXSERIAL_H
+#define NBX_FBXSERIAL_H
+
+#include <linux/types.h>
+
+/*
+ * Extended info structure - variable data depending on type
+ */
+#define NBX_EXTINFO_SIZE		128
+#define NBX_EXTINFO_MAX_COUNT		16
+
+/* Extended info types */
+#define NBX_EXTINFO_TYPE_EXTDEV		1
+
+/* Extended device types */
+#define NBX_EXTDEV_TYPE_BUNDLE		1
+#define NBX_EXTDEV_TYPE_MAX		2
+
+struct nbx_serial_extinfo {
+	u32 type;
+
+	union {
+		/* extdev */
+		struct {
+			u32 type;
+			u32 model;
+			char serial[64];
+		} extdev;
+
+		/* raw access */
+		unsigned char data[NBX_EXTINFO_SIZE];
+	} u;
+} __packed;
+
+/*
+ * Master serial structure
+ */
+#define NBX_FBXSERIAL_VERSION		1
+#define NBX_FBXSERIAL_MAGIC		0x2d9521ab
+
+#define NBX_MAC_ADDR_SIZE		6
+#define NBX_RANDOM_DATA_SIZE		32
+
+/* Maximum size for CRC validation */
+#define NBX_FBXSERIAL_MAX_SIZE		8192
+
+struct nbx_fbx_serial {
+	u32 crc32;
+	u32 magic;
+	u32 struct_version;
+	u32 len;
+
+	/* Board serial */
+	u16 type;
+	u8 version;
+	u8 manufacturer;
+	u16 year;
+	u8 week;
+	u32 number;
+	u32 flags;
+
+	/* MAC address base */
+	u8 mac_addr_base[NBX_MAC_ADDR_SIZE];
+
+	/* MAC address count */
+	u8 mac_count;
+
+	/* Random data used to derive keys */
+	u8 random_data[NBX_RANDOM_DATA_SIZE];
+
+	/* Last update of data (seconds since epoch) */
+	u32 last_modified;
+
+	/* Count of following extinfo tags */
+	u32 extinfo_count;
+
+	/* Beginning of extended info */
+	struct nbx_serial_extinfo extinfos[NBX_EXTINFO_MAX_COUNT];
+} __packed;
+
+/**
+ * nbx_fbxserial_set_default() - Initialize serial structure with defaults
+ * @serial: Pointer to serial structure to initialize
+ *
+ * Sets the serial structure to default values (Freebox OUI, type 9018).
+ * Used as fallback when serial info cannot be read from eMMC.
+ */
+static inline void nbx_fbxserial_set_default(struct nbx_fbx_serial *serial)
+{
+	static const struct nbx_fbx_serial def = {
+		.crc32		= 0,
+		.magic		= NBX_FBXSERIAL_MAGIC,
+		.struct_version	= NBX_FBXSERIAL_VERSION,
+		.len		= sizeof(struct nbx_fbx_serial),
+		.type		= 9018,
+		.version	= 0,
+		.manufacturer	= '_',
+		.year		= 0,
+		.week		= 0,
+		.number		= 0,
+		.flags		= 0,
+		.mac_addr_base	= { 0x00, 0x07, 0xCB, 0x00, 0x00, 0xFD },
+		.mac_count	= 1,
+		.random_data	= { 0 },
+		.last_modified	= 0,
+		.extinfo_count	= 0,
+	};
+
+	memcpy(serial, &def, sizeof(def));
+}
+
+/**
+ * nbx_fbx_read_serial() - Read serial info from eMMC
+ * @dev_num: MMC device number
+ * @offset: Byte offset in eMMC where serial info is stored
+ * @fs: Pointer to serial structure to fill
+ *
+ * Reads and validates the serial info from eMMC. On failure,
+ * the structure is filled with default values.
+ *
+ * Return: 0 on success, negative on error (defaults still set)
+ */
+int nbx_fbx_read_serial(int dev_num, unsigned long offset,
+			struct nbx_fbx_serial *fs);
+
+/**
+ * nbx_fbx_dump_serial() - Print serial info to console
+ * @fs: Pointer to serial structure to display
+ *
+ * Prints the serial number, MAC address, and bundle info (if present).
+ */
+void nbx_fbx_dump_serial(struct nbx_fbx_serial *fs);
+
+/**
+ * nbx_fbx_init_ethaddr() - Initialize Ethernet addresses from serial info
+ * @dev_num: MMC device number
+ * @offset: Byte offset in eMMC where serial info is stored
+ *
+ * Reads serial info and sets ethaddr, eth1addr, eth2addr environment
+ * variables from the MAC address in the serial structure.
+ *
+ * Return: 0 on success, negative on error
+ */
+int nbx_fbx_init_ethaddr(int dev_num, unsigned long offset);
+
+#endif /* NBX_FBXSERIAL_H */

board/freebox/nbx10g/nbx_imagetag.h

@@ -0,0 +1,78 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * MVEBU Image Tag header
+ *
+ * Copyright (C) 2026 Free Mobile, Freebox
+ */
+
+#ifndef __MVEBU_IMAGETAG_H
+#define __MVEBU_IMAGETAG_H
+
+#include <linux/types.h>
+
+#define MVEBU_IMAGE_TAG_MAGIC	0x8d7c90bc
+#define MVEBU_IMAGE_TAG_VERSION	1
+
+/**
+ * struct mvebu_image_tag - MVEBU boot image tag structure
+ *
+ * All multi-byte fields are stored in big-endian format.
+ */
+struct mvebu_image_tag {
+	u32 crc;			/* CRC32-LE checksum (from offset 4) */
+	u32 magic;			/* Magic: 0x8d7c90bc */
+	u32 version;			/* Version: 1 */
+	u32 total_size;			/* Total image size including tag */
+	u32 flags;			/* Feature flags (reserved) */
+
+	u32 device_tree_offset;		/* Offset from tag start to DTB */
+	u32 device_tree_size;		/* DTB size in bytes */
+
+	u32 kernel_offset;		/* Offset from tag start to kernel */
+	u32 kernel_size;		/* Kernel size in bytes */
+
+	u32 rootfs_offset;		/* Offset from tag start to rootfs */
+	u32 rootfs_size;		/* Rootfs size (must be 0) */
+
+	char image_name[32];		/* Image name (null-terminated) */
+	char build_user[32];		/* Build user info */
+	char build_date[32];		/* Build date info */
+};
+
+/* Accessor functions for big-endian fields */
+static inline u32 mvebu_imagetag_device_tree_offset(struct mvebu_image_tag *tag)
+{
+	return be32_to_cpu(tag->device_tree_offset);
+}
+
+static inline u32 mvebu_imagetag_device_tree_size(struct mvebu_image_tag *tag)
+{
+	return be32_to_cpu(tag->device_tree_size);
+}
+
+static inline u32 mvebu_imagetag_kernel_offset(struct mvebu_image_tag *tag)
+{
+	return be32_to_cpu(tag->kernel_offset);
+}
+
+static inline u32 mvebu_imagetag_kernel_size(struct mvebu_image_tag *tag)
+{
+	return be32_to_cpu(tag->kernel_size);
+}
+
+static inline u32 mvebu_imagetag_rootfs_offset(struct mvebu_image_tag *tag)
+{
+	return be32_to_cpu(tag->rootfs_offset);
+}
+
+static inline u32 mvebu_imagetag_rootfs_size(struct mvebu_image_tag *tag)
+{
+	return be32_to_cpu(tag->rootfs_size);
+}
+
+static inline u32 mvebu_imagetag_total_size(struct mvebu_image_tag *tag)
+{
+	return be32_to_cpu(tag->total_size);
+}
+
+#endif /* __MVEBU_IMAGETAG_H */

board/freebox/nbx10g/nbx_nrboot.h

@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * MVEBU NRBoot (Number of Reboots) tracking header
+ *
+ * Copyright (C) 2026 Free Mobile, Freebox
+ */
+
+#ifndef __MVEBU_NRBOOT_H
+#define __MVEBU_NRBOOT_H
+
+#include <mmc.h>
+
+/**
+ * mvebu_check_nrboot() - Check and update reboot tracking counter
+ * @mmc: MMC device
+ * @offset: Byte offset in MMC where nrboot data is stored
+ *
+ * This function reads the reboot tracking counter, checks if we've
+ * exceeded the maximum number of failed boots (4), and updates the
+ * counter for the current boot attempt.
+ *
+ * The counter uses a bit-field encoding:
+ * - nrboot: Running count of boot attempts
+ * - nrsuccess: Count of successful boots
+ *
+ * If boot - success >= MAX_FAILURE (4), the system is considered
+ * degraded and should use the fallback boot bank.
+ *
+ * Return: 1 if system is healthy (try newer bank first),
+ *         0 if system is degraded (use stable bank first)
+ */
+int mvebu_check_nrboot(struct mmc *mmc, unsigned long offset);
+
+#endif /* __MVEBU_NRBOOT_H */

board/nxp/imx94_evk/imx94_evk.c

@@ -7,7 +7,7 @@
 #include <fdt_support.h>
 #include <asm/gpio.h>
 #include <asm/arch/clock.h>
-#include <asm/mach-imx/sys_proto.h>
+#include <asm/arch/sys_proto.h>
 
 int board_init(void)
 {
@@ -26,3 +26,11 @@ int board_late_init(void)
 
 	return 0;
 }
+
+#if IS_ENABLED(CONFIG_OF_BOARD_FIXUP)
+int board_fix_fdt(void *fdt)
+{
+	/* Remove nodes based on fuses. */
+	return imx9_uboot_fixup_by_fuse(fdt);
+}
+#endif

board/nxp/imx952_evk/imx952_evk.c

@@ -24,3 +24,11 @@ int board_late_init(void)
 
 	return 0;
 }
+
+#if IS_ENABLED(CONFIG_OF_BOARD_FIXUP)
+int board_fix_fdt(void *fdt)
+{
+	/* Remove nodes based on fuses. */
+	return imx9_uboot_fixup_by_fuse(fdt);
+}
+#endif