Prepare v2009.11.1

Update CHANGELOG Signed-off-by: Wolfgang Denk <wd@denx.de>
ppc4xx: Kilauea: Add CPLD version detection and EBC reconfiguration
2026-06-04 02:36:38 +03:00 · 2010-01-25 09:35:12 +01:00 · 2010-01-23 17:54:03 +01:00 · 2010-01-23 17:53:55 +01:00 · 2010-01-23 17:53:22 +01:00 · 2010-01-23 17:53:11 +01:00
3212 changed files with 94702 additions and 92033 deletions
--- a/11395
+++ b/11395
--- a/7
+++ b/7
@@ -437,7 +437,7 @@ D: FADS823 configuration, MPC823 video support, I2C, wireless keyboard, lots mor

 N: Andre Schwarz
 E: andre.schwarz@matrix-vision.de
-D: Support for Matrix Vision boards (MVBLM7/MVBC_P/MVSMR)
+D: Support for Matrix Vision boards (MVBLM7/MVBC_P)

 N: Robert Schwebel
 E: r.schwebel@pengutronix.de
@@ -511,11 +511,6 @@ N: Martin Winistoerfer
 E: martinwinistoerfer@gmx.ch
 D: Port to MPC555/556 microcontrollers and support for cmi board

-N: David Wu
-E: support@arcturusnetworks.com
-D: Mercury Security EP2500
-W: http://www.arcturusnetworks.com
-
 N: Ming-Len Wu
 E: minglen_wu@techware.com.tw
 D: Motorola MX1ADS board support
--- a/145
+++ b/145
@@ -36,7 +36,6 @@ Reinhard Arlt <reinhard.arlt@esd-electronics.com>
 	mecp5200	MPC5200
 	pf5200		MPC5200

-	caddy2		MPC8349
 	vme8349		MPC8349

 	CPCI750		PPC750FX/GX
@@ -62,10 +61,6 @@ Oliver Brown <obrown@adventnetworks.com>

 	gw8260		MPC8260

-Cyril Chemparathy <cyril@ti.com>
-
-	tnetv107x_evm	tnetv107x
-
 Conn Clark <clark@esteem.com>

 	ESTEEM192E	MPC8xx
@@ -84,6 +79,7 @@ Torsten Demke <torsten.demke@fci.com>

 Wolfgang Denk <wd@denx.de>

+	IceCube_5100	MGT5100
 	IceCube_5200	MPC5200

 	ARIA		MPC5121e
@@ -121,6 +117,7 @@ Wolfgang Denk <wd@denx.de>

 	CU824		MPC8240
 	Sandpoint8240	MPC8240
+	SL8245		MPC8245

 	ATC		MPC8250
 	PM825		MPC8250
@@ -136,6 +133,8 @@ Wolfgang Denk <wd@denx.de>
 	PCIPPC2		MPC750
 	PCIPPC6		MPC750

+	EXBITGEN	PPC405GP
+
 Jon Diekema <jon.diekema@smiths-aerospace.com>

 	sbc8260		MPC8260
@@ -152,10 +151,6 @@ Dave Ellis <DGE@sixnetio.com>

 	SXNI855T	MPC8xx

-Fred Fan <fanyefeng@gmail.com>
-
-	mx51evk		i.MX51
-
 Thomas Frieden <ThomasF@hyperion-entertainment.com>

 	AmigaOneG3SE	MPC7xx
@@ -198,10 +193,6 @@ Niklaus Giger <niklaus.giger@netstal.com>
 	MCU25		PPC405GPr
 	HCU5		PPC440EPx

-Siddarth Gore <gores@marvell.com>
-
-	guruplug	ARM926EJS (Kirkwood SoC)
-
 Frank Gottschling <fgottschling@eltec.de>

 	MHPC		MPC8xx
@@ -210,8 +201,6 @@ Frank Gottschling <fgottschling@eltec.de>

 Wolfgang Grandegger <wg@denx.de>

-	ipek01		MPC5200
-
 	CCM		MPC855

 	PN62		MPC8240
@@ -232,7 +221,6 @@ Ilko Iliev <iliev@ronetix.at>

 	PM9261		AT91SAM9261
 	PM9263		AT91SAM9263
-	PM9G45		ARM926EJS (AT91SAM9G45 SoC)

 Gary Jennejohn <garyj@denx.de>

@@ -354,10 +342,6 @@ Daniel Poirot <dan.poirot@windriver.com>
 	sbc8240		MPC8240
 	sbc405		PPC405GP

-Sudhakar Rajashekhara <sudhakar.raj@ti.com>
-
-	da850evm	ARM926EJS (DA850/OMAP-L138)
-
 Ricardo Ribalda <ricardo.ribalda@uam.es>

 	ml507 		PPC440x5
@@ -381,7 +365,6 @@ Stefan Roese <sr@denx.de>
 	ebony		PPC440GP
 	glacier		PPC460GT
 	haleakala	PPC405EXr
-	icon		PPC440SPe
 	katmai		PPC440SPe
 	kilauea		PPC405EX
 	lwmon5		PPC440EPx
@@ -425,9 +408,9 @@ Heiko Schocher <hs@denx.de>
 	muas3001	MPC8270
 	municse		MPC5200
 	sc3		PPC405GP
-	suen3		ARM926EJS (Kirkwood SoC)
 	uc101		MPC5200

+
 Peter De Schrijver <p2@mind.be>

 	ML2		PPC4xx
@@ -436,7 +419,6 @@ Andre Schwarz <andre.schwarz@matrix-vision.de>

 	mvbc_p		MPC5200
 	mvblm7		MPC8343
-	mvsmr		MPC5200

 Jon Smirl <jonsmirl@gmail.com>

@@ -481,10 +463,6 @@ Josef Wagner <Wagner@Microsys.de>
 	CPC45		MPC8245
 	PM520		MPC5200

-Michael Weiss <michael.weiss@ifm.com>
-
-	PDM360NG	MPC5121e
-
 Stephen Williams <steve@icarus.com>

 	JSE		PPC405GPr
@@ -534,10 +512,6 @@ Unknown / orphaned boards:
 #	Board		CPU						#
 #########################################################################

-Albert ARIBAUD <albert.aribaud@free.fr>
-
-	edminiv2	ARM926EJS (Orion5x SoC)
-
 Rowel Atienza <rowel@diwalabs.com>

 	armadillo	ARM720T
@@ -569,10 +543,6 @@ Rick Bronson <rick@efn.org>

 	AT91RM9200DK	at91rm9200

-Po-Yu Chuang <ratbert@faraday-tech.com>
-
-	a320evb		FA526 (ARM920T-like) (a320 SoC)
-
 George G. Davis <gdavis@mvista.com>

 	assabet		SA1100
@@ -597,7 +567,6 @@ Peter Figuli <peposh@etc.sk>
 Daniel Gorsulowski <daniel.gorsulowski@esd.eu>

 	meesc		ARM926EJS (AT91SAM9263 SoC)
-	otc570		ARM926EJS (AT91SAM9263 SoC)

 Sedji Gaouaou<sedji.gaouaou@atmel.com>
 	at91sam9g10ek		ARM926EJS (AT91SAM9G10 SoC)
@@ -613,10 +582,6 @@ Kshitij Gupta <kshitij@ti.com>
 	omap1510inn	ARM925T
 	omap1610inn	ARM926EJS

-Vaibhav Hiremath <hvaibhav@ti.com>
-
-	am3517_evm	ARM CORTEX-A8 (AM35x SoC)
-
 Grazvydas Ignotas <notasas@gmail.com>

 	omap3_pandora	ARM CORTEX-A8 (OMAP3xx SoC)
@@ -626,16 +591,6 @@ Gary Jennejohn <garyj@denx.de>
 	smdk2400	ARM920T
 	trab		ARM920T

-Matthias Kaehlcke <matthias@kaehlcke.net>
-	edb9301			ARM920T (EP9301)
-	edb9302			ARM920T (EP9302)
-	edb9302a		ARM920T (EP9302)
-	edb9307			ARM920T (EP9307)
-	edb9307a		ARM920T (EP9307)
-	edb9312			ARM920T (EP9312)
-	edb9315			ARM920T (EP9315)
-	edb9315a		ARM920T (EP9315)
-
 Konstantin Kletschke <kletschke@synertronixx.de>
 	scb9328		ARM920T

@@ -647,11 +602,6 @@ Nishant Kamat <nskamat@ti.com>

 	omap1610h2	ARM926EJS

-Minkyu Kang <mk7.kang@samsung.com>
-
-	s5p_goni	ARM CORTEX-A8 (S5PC110 SoC)
-	SMDKC100	ARM CORTEX-A8 (S5PC100 SoC)
-
 Frederik Kriewitz <frederik@kriewitz.eu>

 	devkit8000	ARM CORTEX-A8 (OMAP3530 SoC)
@@ -662,21 +612,27 @@ Sergey Kubushyn <ksi@koi8.net>
 	SONATA		ARM926EJS
 	SCHMOOGIE	ARM926EJS

+Sandeep Paulraj <s-paulraj@ti.com>
+
+	davinci_dm355evm	ARM926EJS
+	davinci_dm355leopard	ARM926EJS
+	davinci_dm365evm	ARM926EJS
+	davinci_dm6467evm	ARM926EJS
+
 Prakash Kumar <prakash@embedx.com>

 	cerf250		xscale

-Vipin Kumar <vipin.kumar@st.com>
-
-	spear300	ARM926EJS (spear300 Soc)
-	spear310	ARM926EJS (spear310 Soc)
-	spear320	ARM926EJS (spear320 Soc)
-	spear600	ARM926EJS (spear600 Soc)
-
 Sergey Lapin <slapin@ossfans.org>

 	afeb9260	ARM926EJS (AT91SAM9260 SoC)

+Guennadi Liakhovetski <g.liakhovetski@gmx.de>
+
+	imx31_phycore_eet	i.MX31
+	mx31ads			i.MX31
+	SMDK6400		S3C6400
+
 Nishanth Menon <nm@ti.com>

 	omap3_sdp3430	ARM CORTEX-A8 (OMAP3xx SoC)
@@ -699,13 +655,6 @@ Kyungmin Park <kyungmin.park@samsung.com>

 	apollon		ARM1136EJS

-Sandeep Paulraj <s-paulraj@ti.com>
-
-	davinci_dm355evm	ARM926EJS
-	davinci_dm355leopard	ARM926EJS
-	davinci_dm365evm	ARM926EJS
-	davinci_dm6467evm	ARM926EJS
-
 Peter Pearse <peter.pearse@arm.com>
 	integratorcp	All current ARM supplied & supported core modules
 			-see http://www.arm.com/products/DevTools/Hardware_Platforms.html
@@ -732,10 +681,6 @@ Tom Rix <Tom.Rix@windriver.com>

 	omap3_zoom2	ARM CORTEX-A8 (OMAP3xx SoC)

-John Rigby <jcrigby@gmail.com>
-
-	tx25		i.MX25
-
 Stefan Roese <sr@denx.de>

 	ixdpg425	xscale
@@ -745,20 +690,12 @@ Stefan Roese <sr@denx.de>
 Alessandro Rubini <rubini@unipv.it>
 Nomadik Linux Team <STN_WMM_nomadik_linux@list.st.com>

-	nhk8815		ARM926EJS (Nomadik 8815 Soc)
+	nmdk8815	ARM926EJS (Nomadik 8815 Soc)

 Steve Sakoman <sakoman@gmail.com>

 	omap3_overo	ARM CORTEX-A8 (OMAP3xx SoC)

-Jens Scharsig <esw@bus-elektronik.de>
-
-	eb_cpux9k2	ARM920T (AT91RM9200 SoC)
-
-Heiko Schocher <hs@denx.de>
-
-	magnesium	i.MX27
-
 Robert Schwebel <r.schwebel@pengutronix.de>

 	csb226		xscale
@@ -775,10 +712,6 @@ Andrea Scian <andrea.scian@dave-tech.it>

 	B2		ARM7TDMI (S3C44B0X)

-Nick Thompson <nick.thompson@gefanuc.com>
-
-	da830evm	ARM926EJS (DA830/OMAP-L137)
-
 Albin Tonnerre <albin.tonnerre@free-electrons.com>

 	sbc35_a9g20	ARM926EJS (AT91SAM9G20 SoC)
@@ -810,6 +743,10 @@ Alex Z
 	lart		SA1100
 	dnp1110		SA1110

+Minkyu Kang <mk7.kang@samsung.com>
+
+	SMDKC100	ARM CORTEX-A8 (S5PC100 SoC)
+
 -------------------------------------------------------------------------

 Unknown / orphaned boards:
@@ -819,10 +756,6 @@ Unknown / orphaned boards:
 	ixdp425		xscale	Kyle Harris <kharris@nexus-tech.net> / dead address
 	lubbock		xscale	Kyle Harris <kharris@nexus-tech.net> / dead address

-	imx31_phycore_eet i.MX31  Guennadi Liakhovetski <g.liakhovetski@gmx.de> / resigned
-	mx31ads		  i.MX31  Guennadi Liakhovetski <g.liakhovetski@gmx.de> / resigned
-	SMDK6400	  S3C6400 Guennadi Liakhovetski <g.liakhovetski@gmx.de> / resigned
-
 #########################################################################
 # x86 Systems:								#
 #									#
@@ -857,6 +790,22 @@ Stefan Roese <sr@denx.de>

 	vct_xxx		MIPS32 4Kc

+#########################################################################
+# Nios-32 Systems:							#
+#									#
+# Maintainer Name, Email Address					#
+#	Board		CPU						#
+#########################################################################
+
+Stephan Linz <linz@li-pro.net>
+
+	DK1S10		Nios-32
+	ADNPESC1	Nios-32
+
+Scott McNutt <smcnutt@psyent.com>
+
+	DK1C20		Nios-32
+
 #########################################################################
 # Nios-II Systems:							#
 #									#
@@ -871,7 +820,6 @@ Scott McNutt <smcnutt@psyent.com>
 	EP1C20		Nios-II
 	EP1S10		Nios-II
 	EP1S40		Nios-II
-	nios2-generic	Nios-II

 #########################################################################
 # MicroBlaze Systems:							#
@@ -911,10 +859,6 @@ TsiChung Liew <Tsi-Chung.Liew@freescale.com>
 	M5475EVB	mcf547x_8x
 	M5485EVB	mcf547x_8x

-Wolfgang Wegner <w.wegner@astro-kom.de>
-
-	astro_mcf5373l	MCF5373L
-
 #########################################################################
 # AVR32 Systems:							#
 #									#
@@ -988,7 +932,6 @@ Blackfin Team <u-boot-devel@blackfin.uclinux.org>
 	BF518F-EZBRD	BF518
 	BF526-EZBRD	BF526
 	BF527-EZKIT	BF527
-	BF527-EZKIT-V2	BF527
 	BF533-EZKIT	BF533
 	BF533-STAMP	BF533
 	BF537-PNAV	BF537
@@ -1006,7 +949,6 @@ Blackfin Team <u-boot-devel@blackfin.uclinux.org>
 	CM-BF537U	BF537
 	CM-BF548	BF548
 	CM-BF561	BF561
-	TCM-BF518	BF518
 	TCM-BF537	BF537

 Martin Strubel <strubel@section5.ch>
@@ -1025,15 +967,6 @@ Blackfin Team <u-boot-devel@blackfin.uclinux.org>

 	IBF-DSP561	BF561

-Valentin Yakovenkov <yakovenkov@niistt.ru>
-Anton Shurpin <shurpin.aa@niistt.ru>
-
-	BF561-ACVILON	BF561
-
-Brent Kandetzki <brentk@teleco.com>
-
-	IP04		BF532
-
 #########################################################################
 # End of MAINTAINERS list						#
 #########################################################################
--- a/80
+++ b/80
@@ -61,21 +61,21 @@ LIST_5xxx="		\
 	EVAL5200	\
 	fo300		\
 	galaxy5200	\
+	icecube_5100	\
 	icecube_5200	\
 	inka4x0		\
-	ipek01		\
 	lite5200b	\
 	mcc200		\
 	mecp5200	\
 	motionpro	\
 	munices		\
 	MVBC_P		\
-	MVSMR		\
 	o2dnt		\
 	pcm030		\
 	pf5200		\
 	PM520		\
 	TB5200		\
+	Total5100	\
 	Total5200	\
 	Total5200_Rev2	\
 	TQM5200		\
@@ -92,7 +92,6 @@ LIST_512x="		\
 	aria		\
 	mecp5123	\
 	mpc5121ads	\
-	pdm360ng	\
 "

 #########################################################################
@@ -186,7 +185,6 @@ LIST_4xx="		\
 	ADCIOP		\
 	alpr		\
 	AP1000		\
-	APC405		\
 	AR405		\
 	arches		\
 	ASH405		\
@@ -214,6 +212,7 @@ LIST_4xx="		\
 	DU440		\
 	ebony		\
 	ERIC		\
+	EXBITGEN	\
 	fx12mm		\
 	G2000		\
 	gdppc440etx	\
@@ -224,7 +223,6 @@ LIST_4xx="		\
 	hcu5		\
 	HH405		\
 	HUB405		\
-	icon		\
 	intip		\
 	JSE		\
 	KAREF		\
@@ -240,6 +238,7 @@ LIST_4xx="		\
 	MIP405		\
 	MIP405T		\
 	ML2		\
+	ml300		\
 	ml507		\
 	ml507_flash	\
 	neo		\
@@ -313,6 +312,7 @@ LIST_824x="		\
 	Sandpoint8240	\
 	Sandpoint8245	\
 	sbc8240		\
+	SL8245		\
 	utx8245		\
 "

@@ -357,12 +357,10 @@ LIST_8260="		\
 #########################################################################

 LIST_83xx="		\
-	caddy2		\
 	kmeter1		\
 	MPC8313ERDB_33	\
 	MPC8313ERDB_NAND_66	\
 	MPC8315ERDB	\
-	MPC8315ERDB_NAND	\
 	MPC8323ERDB	\
 	MPC832XEMDS	\
 	MPC832XEMDS_ATM	\
@@ -393,7 +391,6 @@ LIST_85xx="		\
 	MPC8536DS_NAND	\
 	MPC8536DS_SDCARD	\
 	MPC8536DS_SPIFLASH	\
-	MPC8536DS_36BIT	\
 	MPC8540ADS	\
 	MPC8540EVAL	\
 	MPC8541CDS	\
@@ -403,8 +400,6 @@ LIST_85xx="		\
 	MPC8560ADS	\
 	MPC8568MDS	\
 	MPC8569MDS	\
-	MPC8569MDS_ATM	\
-	MPC8569MDS_NAND \
 	MPC8572DS	\
 	MPC8572DS_36BIT	\
 	P2020DS		\
@@ -454,7 +449,6 @@ LIST_85xx="		\

 LIST_86xx="		\
 	MPC8610HPCD	\
-	MPC8641HPCN_36BIT \
 	MPC8641HPCN	\
 	sbc8641d	\
 	XPEDITE5170	\
@@ -494,7 +488,7 @@ LIST_TSEC="		\
 	${LIST_86xx}	\
 "

-LIST_powerpc="		\
+LIST_ppc="		\
 	${LIST_5xx}	\
 	${LIST_512x}	\
 	${LIST_5xxx}	\
@@ -510,12 +504,6 @@ LIST_powerpc="		\
 	${LIST_7xx}	\
 "

-# Alias "ppc" -> "powerpc" to not break compatibility with older scripts
-# still using "ppc" instead of "powerpc"
-LIST_ppc="		\
-	${LIST_powerpc}	\
-"
-
 #########################################################################
 ## StrongARM Systems
 #########################################################################
@@ -551,7 +539,6 @@ LIST_ARM7="		\
 #########################################################################

 LIST_ARM9="			\
-	a320evb			\
 	ap920t			\
 	ap922_XA10		\
 	ap926ejs		\
@@ -562,21 +549,8 @@ LIST_ARM9="			\
 	cp926ejs		\
 	cp946es			\
 	cp966			\
-	da830evm		\
-	da850evm		\
-	edb9301			\
-	edb9302			\
-	edb9302a		\
-	edb9307			\
-	edb9307a		\
-	edb9312			\
-	edb9315			\
-	edb9315a		\
-	edminiv2		\
-	guruplug		\
 	imx27lite		\
 	lpd7a400		\
-	magnesium		\
 	mv88f6281gtw_ge		\
 	mx1ads			\
 	mx1fs2			\
@@ -595,11 +569,6 @@ LIST_ARM9="			\
 	sheevaplug		\
 	smdk2400		\
 	smdk2410		\
-	spear300		\
-	spear310		\
-	spear320		\
-	spear600		\
-	suen3			\
 	trab			\
 	VCMA9			\
 	versatile		\
@@ -612,7 +581,6 @@ LIST_ARM9="			\
 	davinci_sonata		\
 	davinci_dm355evm	\
 	davinci_dm355leopard	\
-	davinci_dm365evm	\
 	davinci_dm6467evm	\
 "

@@ -639,16 +607,13 @@ LIST_ARM11="			\
 	mx31pdk_nand		\
 	qong			\
 	smdk6400		\
-	tnetv107x_evm		\
 "

 #########################################################################
 ## ARM Cortex-A8 Systems
 #########################################################################
 LIST_ARM_CORTEX_A8="		\
-	am3517_evm		\
 	devkit8000		\
-	mx51evk			\
 	omap3_beagle		\
 	omap3_overo		\
 	omap3_evm		\
@@ -656,7 +621,6 @@ LIST_ARM_CORTEX_A8="		\
 	omap3_sdp3430		\
 	omap3_zoom1		\
 	omap3_zoom2		\
-	s5p_goni		\
 	smdkc100		\
 "

@@ -681,15 +645,12 @@ LIST_at91="			\
 	CPU9260			\
 	CPU9G20			\
 	csb637			\
-	eb_cpux9k2		\
 	kb9202			\
 	meesc			\
 	mp2usb			\
 	m501sk			\
-	otc570			\
 	pm9261			\
 	pm9263			\
-	pm9g45			\
 	SBC35_A9G20		\
 	TNY_A9260		\
 	TNY_A9G20		\
@@ -818,6 +779,21 @@ LIST_x86="		\
 	${LIST_I486}	\
 "

+#########################################################################
+## NIOS Systems
+#########################################################################
+
+LIST_nios="			\
+	ADNPESC1		\
+	ADNPESC1_base_32	\
+	ADNPESC1_DNPEVA2_base_32\
+	DK1C20			\
+	DK1C20_standard_32	\
+	DK1S10			\
+	DK1S10_standard_32	\
+	DK1S10_mtx_ldk_20	\
+"
+
 #########################################################################
 ## Nios-II Systems
 #########################################################################
@@ -828,7 +804,6 @@ LIST_nios2="		\
 	EP1S40		\
 	PCI5441		\
 	PK1C20		\
-	nios2-generic	\
 "

 #########################################################################
@@ -844,7 +819,6 @@ LIST_microblaze="			\
 #########################################################################

 LIST_coldfire="			\
-	astro_mcf5373l		\
 	cobra5272		\
 	EB+MCF-EV123		\
 	EB+MCF-EV123_internal	\
@@ -892,7 +866,6 @@ LIST_blackfin="		\
 	bf518f-ezbrd	\
 	bf526-ezbrd	\
 	bf527-ezkit	\
-	bf527-ezkit-v2	\
 	bf533-ezkit	\
 	bf533-stamp	\
 	bf537-minotaur	\
@@ -901,7 +874,6 @@ LIST_blackfin="		\
 	bf537-stamp	\
 	bf538f-ezkit	\
 	bf548-ezkit	\
-	bf561-acvilon	\
 	bf561-ezkit	\
 	blackstamp	\
 	cm-bf527	\
@@ -911,8 +883,6 @@ LIST_blackfin="		\
 	cm-bf548	\
 	cm-bf561	\
 	ibf-dsp561	\
-	ip04		\
-	tcm-bf518	\
 	tcm-bf537	\
 "

@@ -954,8 +924,8 @@ LIST_sparc="gr_xc3s_1500	gr_cpci_ax2000	gr_ep2s60	grsim	grsim_leon2"

 #-----------------------------------------------------------------------

-#----- for now, just run PowerPC by default -----
-[ $# = 0 ] && set $LIST_powerpc
+#----- for now, just run PPC by default -----
+[ $# = 0 ] && set $LIST_ppc

 #-----------------------------------------------------------------------

@@ -1010,8 +980,8 @@ do
 	|coldfire \
 	|microblaze \
 	|mips|mips_el \
-	|nios2 \
-	|ppc|powerpc|5xx|5xxx|512x|8xx|8220|824x|8260|83xx|85xx|86xx|4xx|7xx|74xx|TSEC \
+	|nios|nios2 \
+	|ppc|5xx|5xxx|512x|8xx|8220|824x|8260|83xx|85xx|86xx|4xx|7xx|74xx|TSEC \
 	|sh|sh2|sh3|sh4 \
 	|sparc \
 	|x86|I486 \
--- a/925
+++ b/925
--- a/256
+++ b/256
@@ -138,88 +138,68 @@ U-Boot will always have a patchlevel of "0".
 Directory Hierarchy:
 ====================

-/arch			Architecture specific files
-  /arm			Files generic to ARM architecture
-    /cpu		CPU specific files
-      /arm720t		Files specific to ARM 720 CPUs
-      /arm920t		Files specific to ARM 920 CPUs
-	/at91rm9200	Files specific to Atmel AT91RM9200 CPU
-	/imx		Files specific to Freescale MC9328 i.MX CPUs
-	/s3c24x0	Files specific to Samsung S3C24X0 CPUs
-      /arm925t		Files specific to ARM 925 CPUs
-      /arm926ejs	Files specific to ARM 926 CPUs
-      /arm1136		Files specific to ARM 1136 CPUs
-      /ixp		Files specific to Intel XScale IXP CPUs
-      /pxa		Files specific to Intel XScale PXA CPUs
-      /s3c44b0		Files specific to Samsung S3C44B0 CPUs
-      /sa1100		Files specific to Intel StrongARM SA1100 CPUs
-    /lib		Architecture specific library files
-  /avr32		Files generic to AVR32 architecture
-    /cpu		CPU specific files
-    /lib		Architecture specific library files
-  /blackfin		Files generic to Analog Devices Blackfin architecture
-    /cpu		CPU specific files
-    /lib		Architecture specific library files
-  /i386			Files generic to i386 architecture
-    /cpu		CPU specific files
-    /lib		Architecture specific library files
-  /m68k			Files generic to m68k architecture
-    /cpu		CPU specific files
-      /mcf52x2		Files specific to Freescale ColdFire MCF52x2 CPUs
-      /mcf5227x		Files specific to Freescale ColdFire MCF5227x CPUs
-      /mcf532x		Files specific to Freescale ColdFire MCF5329 CPUs
-      /mcf5445x		Files specific to Freescale ColdFire MCF5445x CPUs
-      /mcf547x_8x	Files specific to Freescale ColdFire MCF547x_8x CPUs
-    /lib		Architecture specific library files
-  /microblaze		Files generic to microblaze architecture
-    /cpu		CPU specific files
-    /lib		Architecture specific library files
-  /mips			Files generic to MIPS architecture
-    /cpu		CPU specific files
-    /lib		Architecture specific library files
-  /nios2		Files generic to Altera NIOS2 architecture
-    /cpu		CPU specific files
-    /lib		Architecture specific library files
-  /powerpc		Files generic to PowerPC architecture
-    /cpu		CPU specific files
-      /74xx_7xx		Files specific to Freescale MPC74xx and 7xx CPUs
-      /mpc5xx		Files specific to Freescale MPC5xx CPUs
-      /mpc5xxx		Files specific to Freescale MPC5xxx CPUs
-      /mpc8xx		Files specific to Freescale MPC8xx CPUs
-      /mpc8220		Files specific to Freescale MPC8220 CPUs
-      /mpc824x		Files specific to Freescale MPC824x CPUs
-      /mpc8260		Files specific to Freescale MPC8260 CPUs
-      /mpc85xx		Files specific to Freescale MPC85xx CPUs
-      /ppc4xx		Files specific to AMCC PowerPC 4xx CPUs
-    /lib		Architecture specific library files
-  /sh			Files generic to SH architecture
-    /cpu		CPU specific files
-      /sh2		Files specific to sh2 CPUs
-      /sh3		Files specific to sh3 CPUs
-      /sh4		Files specific to sh4 CPUs
-    /lib		Architecture specific library files
-  /sparc		Files generic to SPARC architecture
-    /cpu		CPU specific files
-      /leon2		Files specific to Gaisler LEON2 SPARC CPU
-      /leon3		Files specific to Gaisler LEON3 SPARC CPU
-    /lib		Architecture specific library files
-/api			Machine/arch independent API for external apps
-/board			Board dependent files
-/common			Misc architecture independent functions
-/disk			Code for disk drive partition handling
-/doc			Documentation (don't expect too much)
-/drivers		Commonly used device drivers
-/examples		Example code for standalone applications, etc.
-/fs			Filesystem code (cramfs, ext2, jffs2, etc.)
-/include		Header Files
-/lib			Files generic to all architectures
-  /libfdt		Library files to support flattened device trees
-  /lzma			Library files to support LZMA decompression
-  /lzo			Library files to support LZO decompression
-/net			Networking code
-/post			Power On Self Test
-/rtc			Real Time Clock drivers
-/tools			Tools to build S-Record or U-Boot images, etc.
+- api		Machine/arch independent API for external apps
+- board		Board dependent files
+- common	Misc architecture independent functions
+- cpu		CPU specific files
+  - 74xx_7xx	Files specific to Freescale MPC74xx and 7xx CPUs
+  - arm720t	Files specific to ARM 720 CPUs
+  - arm920t	Files specific to ARM 920 CPUs
+    - at91rm9200 Files specific to Atmel AT91RM9200 CPU
+    - imx	Files specific to Freescale MC9328 i.MX CPUs
+    - s3c24x0	Files specific to Samsung S3C24X0 CPUs
+  - arm925t	Files specific to ARM 925 CPUs
+  - arm926ejs	Files specific to ARM 926 CPUs
+  - arm1136	Files specific to ARM 1136 CPUs
+  - at32ap	Files specific to Atmel AVR32 AP CPUs
+  - blackfin	Files specific to Analog Devices Blackfin CPUs
+  - i386	Files specific to i386 CPUs
+  - ixp		Files specific to Intel XScale IXP CPUs
+  - leon2	Files specific to Gaisler LEON2 SPARC CPU
+  - leon3	Files specific to Gaisler LEON3 SPARC CPU
+  - mcf52x2	Files specific to Freescale ColdFire MCF52x2 CPUs
+  - mcf5227x	Files specific to Freescale ColdFire MCF5227x CPUs
+  - mcf532x	Files specific to Freescale ColdFire MCF5329 CPUs
+  - mcf5445x	Files specific to Freescale ColdFire MCF5445x CPUs
+  - mcf547x_8x	Files specific to Freescale ColdFire MCF547x_8x CPUs
+  - mips	Files specific to MIPS CPUs
+  - mpc5xx	Files specific to Freescale MPC5xx  CPUs
+  - mpc5xxx	Files specific to Freescale MPC5xxx CPUs
+  - mpc8xx	Files specific to Freescale MPC8xx  CPUs
+  - mpc8220	Files specific to Freescale MPC8220 CPUs
+  - mpc824x	Files specific to Freescale MPC824x CPUs
+  - mpc8260	Files specific to Freescale MPC8260 CPUs
+  - mpc85xx	Files specific to Freescale MPC85xx CPUs
+  - nios	Files specific to Altera NIOS CPUs
+  - nios2	Files specific to Altera Nios-II CPUs
+  - ppc4xx	Files specific to AMCC PowerPC 4xx CPUs
+  - pxa		Files specific to Intel XScale PXA CPUs
+  - s3c44b0	Files specific to Samsung S3C44B0 CPUs
+  - sa1100	Files specific to Intel StrongARM SA1100 CPUs
+- disk		Code for disk drive partition handling
+- doc		Documentation (don't expect too much)
+- drivers	Commonly used device drivers
+- examples	Example code for standalone applications, etc.
+- fs		Filesystem code (cramfs, ext2, jffs2, etc.)
+- include	Header Files
+- lib_arm	Files generic to ARM	 architecture
+- lib_avr32	Files generic to AVR32	 architecture
+- lib_blackfin	Files generic to Blackfin architecture
+- lib_generic	Files generic to all	 architectures
+- lib_i386	Files generic to i386	 architecture
+- lib_m68k	Files generic to m68k	 architecture
+- lib_microblaze Files generic to microblaze architecture
+- lib_mips	Files generic to MIPS	 architecture
+- lib_nios	Files generic to NIOS	 architecture
+- lib_nios2	Files generic to NIOS2	 architecture
+- lib_ppc	Files generic to PowerPC architecture
+- lib_sh	Files generic to SH	 architecture
+- lib_sparc	Files generic to SPARC	 architecture
+- libfdt	Library files to support flattened device trees
+- net		Networking code
+- post		Power On Self Test
+- rtc		Real Time Clock drivers
+- tools		Tools to build S-Record or U-Boot images, etc.

 Software Configuration:
 =======================
@@ -797,7 +777,7 @@ The following options need to be configured:
 		CONFIG_LBA48

 		Set this to enable support for disks larger than 137GB
-		Also look at CONFIG_SYS_64BIT_LBA.
+		Also look at CONFIG_SYS_64BIT_LBA ,CONFIG_SYS_64BIT_VSPRINTF and CONFIG_SYS_64BIT_STRTOUL
 		Whithout these , LBA48 support uses 32bit variables and will 'only'
 		support disks up to 2.1TB.

@@ -842,16 +822,6 @@ The following options need to be configured:

 - NETWORK Support (other):

-		CONFIG_DRIVER_AT91EMAC
-		Support for AT91RM9200 EMAC.
-
-			CONFIG_RMII
-			Define this to use reduced MII inteface
-
-			CONFIG_DRIVER_AT91EMAC_QUIET
-			If this defined, the driver is quiet.
-			The driver doen't show link status messages.
-
 		CONFIG_DRIVER_LAN91C96
 		Support for SMSC's LAN91C96 chips.

@@ -1153,12 +1123,6 @@ The following options need to be configured:
 		images, gzipped BMP images can be displayed via the
 		splashscreen support or the bmp command.

- Run length encoded BMP image (RLE8) support: CONFIG_VIDEO_BMP_RLE8
-
-		If this option is set, 8-bit RLE compressed BMP images
-		can be displayed via the splashscreen support or the
-		bmp command.
-
 - Compression support:
 		CONFIG_BZIP2

@@ -1413,11 +1377,10 @@ The following options need to be configured:
 		to run and CONFIG_SYS_I2C_SLAVE to be the address of this node (ie
 		the CPU's i2c node address).

-		Now, the u-boot i2c code for the mpc8xx
-		(arch/powerpc/cpu/mpc8xx/i2c.c) sets the CPU up as a master node
-		and so its address should therefore be cleared to 0 (See,
-		eg, MPC823e User's Manual p.16-473). So, set
-		CONFIG_SYS_I2C_SLAVE to 0.
+		Now, the u-boot i2c code for the mpc8xx (cpu/mpc8xx/i2c.c)
+		sets the CPU up as a master node and so its address should
+		therefore be cleared to 0 (See, eg, MPC823e User's Manual
+		p.16-473). So, set CONFIG_SYS_I2C_SLAVE to 0.

 		CONFIG_SYS_I2C_INIT_MPC5XXX

@@ -1506,17 +1469,6 @@ The following options need to be configured:
 		custom i2c_init_board() routine in boards/xxx/board.c
 		is run early in the boot sequence.

-		CONFIG_SYS_I2C_BOARD_LATE_INIT
-
-		An alternative to CONFIG_SYS_I2C_INIT_BOARD. If this option is
-		defined a custom i2c_board_late_init() routine in
-		boards/xxx/board.c is run AFTER the operations in i2c_init()
-		is completed. This callpoint can be used to unreset i2c bus
-		using CPU i2c controller register accesses for CPUs whose i2c
-		controller provide such a method. It is called at the end of
-		i2c_init() to allow i2c_init operations to setup the i2c bus
-		controller on the CPU (e.g. setting bus speed & slave address).
-
 		CONFIG_I2CFAST (PPC405GP|PPC405EP only)

 		This option enables configuration of bi_iic_fast[] flags
@@ -1972,9 +1924,9 @@ Legacy uImage format:
   13	common/image.c		Start multifile image verification
   14	common/image.c		No initial ramdisk, no multifile, continue.

-   15	arch/<arch>/lib/bootm.c	All preparation done, transferring control to OS
+   15	lib_<arch>/bootm.c	All preparation done, transferring control to OS

-  -30	arch/powerpc/lib/board.c	Fatal error, hang the system
+  -30	lib_ppc/board.c		Fatal error, hang the system
  -31	post/post.c		POST test failed, detected by post_output_backlog()
  -32	post/post.c		POST test failed, detected by post_run_single()

@@ -2495,19 +2447,6 @@ to save the current settings.
 	- CONFIG_SYS_EEPROM_SIZE:
 	  The size in bytes of the EEPROM device.

-	- CONFIG_ENV_EEPROM_IS_ON_I2C
-	  define this, if you have I2C and SPI activated, and your
-	  EEPROM, which holds the environment, is on the I2C bus.
-
-	- CONFIG_I2C_ENV_EEPROM_BUS
-	  if you have an Environment on an EEPROM reached over
-	  I2C muxes, you can define here, how to reach this
-	  EEPROM. For example:
-
-	  #define CONFIG_I2C_ENV_EEPROM_BUS	  "pca9547:70:d\0"
-
-	  EEPROM which holds the environment, is reached over
-	  a pca9547 i2c mux with address 0x70, channel 3.

 - CONFIG_ENV_IS_IN_DATAFLASH:

@@ -2585,6 +2524,13 @@ use the "saveenv" command to store a valid environment.
 - CONFIG_SYS_FAULT_MII_ADDR:
 		MII address of the PHY to check for the Ethernet link state.

+- CONFIG_SYS_64BIT_VSPRINTF:
+		Makes vsprintf (and all *printf functions) support printing
+		of 64bit values by using the L quantifier
+
+- CONFIG_SYS_64BIT_STRTOUL:
+		Adds simple_strtoull that returns a 64bit value
+
 - CONFIG_NS16550_MIN_FUNCTIONS:
 		Define this if you desire to only have use of the NS16550_init
 		and NS16550_putc functions for the serial driver located at
@@ -2735,7 +2681,7 @@ Low Level (hardware related) configuration options:
  CONFIG_SYS_PCI_MSTR_MEMIO_SIZE, CONFIG_SYS_POCMR1_MASK_ATTRIB, CONFIG_SYS_PCI_MSTR_IO_LOCAL,
  CONFIG_SYS_PCI_MSTR_IO_BUS, CONFIG_SYS_CPU_PCI_IO_START, CONFIG_SYS_PCI_MSTR_IO_SIZE,
  CONFIG_SYS_POCMR2_MASK_ATTRIB: (MPC826x only)
-		Overrides the default PCI memory map in arch/powerpc/cpu/mpc8260/pci.c if set.
+		Overrides the default PCI memory map in cpu/mpc8260/pci.c if set.

 - CONFIG_PCI_DISABLE_PCIE:
 		Disable PCI-Express on systems where it is supported but not
@@ -3043,9 +2989,7 @@ environment. As long as you don't save the environment you are
 working with an in-memory copy. In case the Flash area containing the
 environment is erased by accident, a default environment is provided.

-Some configuration options can be set using Environment Variables.
-
-List of environment variables (most likely not complete):
+Some configuration options can be set using Environment Variables:

  baudrate	- see CONFIG_BAUDRATE

@@ -3157,7 +3101,7 @@ List of environment variables (most likely not complete):
 		  available network interfaces.
 		  It just stays at the currently selected interface.

-  netretry	- When set to "no" each network operation will
+   netretry	- When set to "no" each network operation will
 		  either succeed or fail without retrying.
 		  When set to "once" the network operation will
 		  fail when all the available network interfaces
@@ -3173,18 +3117,7 @@ List of environment variables (most likely not complete):
  tftpdstport	- If this is set, the value is used for TFTP's UDP
 		  destination port instead of the Well Know Port 69.

-  tftpblocksize - Block size to use for TFTP transfers; if not set,
-		  we use the TFTP server's default block size
-
-  tftptimeout	- Retransmission timeout for TFTP packets (in milli-
-		  seconds, minimum value is 1000 = 1 second). Defines
-		  when a packet is considered to be lost so it has to
-		  be retransmitted. The default is 5000 = 5 seconds.
-		  Lowering this value may make downloads succeed
-		  faster in networks with high packet loss rates or
-		  with unreliable TFTP servers.
-
-  vlan		- When set to a value < 4095 the traffic over
+   vlan		- When set to a value < 4095 the traffic over
 		  Ethernet is encapsulated/received over 802.1q
 		  VLAN tagged frames.

@@ -3300,11 +3233,6 @@ o If both the SROM and the environment contain a MAC address, and the
 o If neither SROM nor the environment contain a MAC address, an error
  is raised.

-If Ethernet drivers implement the 'write_hwaddr' function, valid MAC addresses
-will be programmed into hardware as part of the initialization process.  This
-may be skipped by setting the appropriate 'ethmacskip' environment variable.
-The naming convention is as follows:
-"ethmacskip" (=>eth0), "eth1macskip" (=>eth1) etc.

 Image Formats:
 ==============
@@ -3334,8 +3262,8 @@ details; basically, the header defines the following image properties:
  Currently supported: Linux, NetBSD, VxWorks, QNX, RTEMS, LynxOS,
  INTEGRITY).
 * Target CPU Architecture (Provisions for Alpha, ARM, AVR32, Intel x86,
-  IA64, MIPS, Nios II, PowerPC, IBM S390, SuperH, Sparc, Sparc 64 Bit;
-  Currently supported: ARM, AVR32, Intel x86, MIPS, Nios II, PowerPC).
+  IA64, MIPS, NIOS, PowerPC, IBM S390, SuperH, Sparc, Sparc 64 Bit;
+  Currently supported: ARM, AVR32, Intel x86, MIPS, NIOS, PowerPC).
 * Compression Type (uncompressed, gzip, bzip2)
 * Load Address
 * Entry Point
@@ -3386,7 +3314,7 @@ configure the Linux device drivers for use with your target hardware
 (no, we don't intend to provide a full virtual machine interface to
 Linux :-).

-But now you can ignore ALL boot loader code (in arch/powerpc/mbxboot).
+But now you can ignore ALL boot loader code (in arch/ppc/mbxboot).

 Just make sure your machine specific header file (for instance
 include/asm-ppc/tqm8xx.h) includes the same definition of the Board
@@ -3484,7 +3412,7 @@ So a typical call to build a U-Boot image would read:

 	-> tools/mkimage -n '2.4.4 kernel for TQM850L' \
 	> -A ppc -O linux -T kernel -C gzip -a 0 -e 0 \
-	> -d /opt/elsk/ppc_8xx/usr/src/linux-2.4.4/arch/powerpc/coffboot/vmlinux.gz \
+	> -d /opt/elsk/ppc_8xx/usr/src/linux-2.4.4/arch/ppc/coffboot/vmlinux.gz \
 	> examples/uImage.TQM850L
 	Image Name:   2.4.4 kernel for TQM850L
 	Created:      Wed Jul 19 02:34:59 2000
@@ -3508,10 +3436,10 @@ speed for memory and install an UNCOMPRESSED image instead: this
 needs more space in Flash, but boots much faster since it does not
 need to be uncompressed:

-	-> gunzip /opt/elsk/ppc_8xx/usr/src/linux-2.4.4/arch/powerpc/coffboot/vmlinux.gz
+	-> gunzip /opt/elsk/ppc_8xx/usr/src/linux-2.4.4/arch/ppc/coffboot/vmlinux.gz
 	-> tools/mkimage -n '2.4.4 kernel for TQM850L' \
 	> -A ppc -O linux -T kernel -C none -a 0 -e 0 \
-	> -d /opt/elsk/ppc_8xx/usr/src/linux-2.4.4/arch/powerpc/coffboot/vmlinux \
+	> -d /opt/elsk/ppc_8xx/usr/src/linux-2.4.4/arch/ppc/coffboot/vmlinux \
 	> examples/uImage.TQM850L-uncompressed
 	Image Name:   2.4.4 kernel for TQM850L
 	Created:      Wed Jul 19 02:34:59 2000
@@ -3988,9 +3916,7 @@ For PowerPC, the following registers have specific use:
 	R30:	GOT pointer
 	R31:	frame pointer

-	(U-Boot also uses R12 as internal GOT pointer. r12
-	is a volatile register so r12 needs to be reset when
-	going back and forth between asm and C)
+	(U-Boot also uses R14 as internal GOT pointer.)

    ==> U-Boot will use R2 to hold a pointer to the global data

@@ -4020,14 +3946,6 @@ On ARM, the following registers are used:

    ==> U-Boot will use R8 to hold a pointer to the global data

-On Nios II, the ABI is documented here:
-	http://www.altera.com/literature/hb/nios2/n2cpu_nii51016.pdf
-
-    ==> U-Boot will use gp to hold a pointer to the global data
-
-    Note: on Nios II, we give "-G0" option to gcc and don't use gp
-    to access small data sections, so gp is free.
-
 NOTE: DECLARE_GLOBAL_DATA_PTR must be used with file-global scope,
 or current versions of GCC may "optimize" the code too much.

--- a/api/api_platform-powerpc.c
+++ b/api/api_platform-powerpc.c
--- a/arch/.gitignore
+++ b/arch/.gitignore
@@ -1,2 +0,0 @@
-/*/include/asm/arch
-/*/include/asm/proc
--- a/arch/arm/cpu/arm1176/tnetv107x/Makefile
+++ b/arch/arm/cpu/arm1176/tnetv107x/Makefile
@@ -1,44 +0,0 @@
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).a
-
-COBJS	+= aemif.o clock.o init.o mux.o timer.o wdt.o
-SOBJS	+= lowlevel_init.o
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-
-OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS)
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
--- a/arch/arm/cpu/arm1176/tnetv107x/aemif.c
+++ b/arch/arm/cpu/arm1176/tnetv107x/aemif.c
@@ -1,93 +0,0 @@
-/*
- * TNETV107X: Asynchronous EMIF Configuration
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/mux.h>
-
-#define ASYNC_EMIF_BASE			TNETV107X_ASYNC_EMIF_CNTRL_BASE
-#define ASYNC_EMIF_CONFIG(cs)		(ASYNC_EMIF_BASE+0x10+(cs)*4)
-#define ASYNC_EMIF_ONENAND_CONTROL	(ASYNC_EMIF_BASE+0x5c)
-#define ASYNC_EMIF_NAND_CONTROL		(ASYNC_EMIF_BASE+0x60)
-#define ASYNC_EMIF_WAITCYCLE_CONFIG	(ASYNC_EMIF_BASE+0x4)
-
-#define CONFIG_SELECT_STROBE(v)		((v) ? 1 << 31 : 0)
-#define CONFIG_EXTEND_WAIT(v)		((v) ? 1 << 30 : 0)
-#define CONFIG_WR_SETUP(v)		(((v) & 0x0f) << 26)
-#define CONFIG_WR_STROBE(v)		(((v) & 0x3f) << 20)
-#define CONFIG_WR_HOLD(v)		(((v) & 0x07) << 17)
-#define CONFIG_RD_SETUP(v)		(((v) & 0x0f) << 13)
-#define CONFIG_RD_STROBE(v)		(((v) & 0x3f) << 7)
-#define CONFIG_RD_HOLD(v)		(((v) & 0x07) << 4)
-#define CONFIG_TURN_AROUND(v)		(((v) & 0x03) << 2)
-#define CONFIG_WIDTH(v)			(((v) & 0x03) << 0)
-
-#define NUM_CS				4
-
-#define set_config_field(reg, field, val)			\
-	do {							\
-		if (val != -1) {				\
-			reg &= ~CONFIG_##field(0xffffffff);	\
-			reg |=	CONFIG_##field(val);		\
-		}						\
-	} while (0)
-
-void configure_async_emif(int cs, struct async_emif_config *cfg)
-{
-	unsigned long tmp;
-
-	if (cfg->mode == ASYNC_EMIF_MODE_NAND) {
-		tmp = __raw_readl(ASYNC_EMIF_NAND_CONTROL);
-		tmp |= (1 << cs);
-		__raw_writel(tmp, ASYNC_EMIF_NAND_CONTROL);
-
-	} else if (cfg->mode == ASYNC_EMIF_MODE_ONENAND) {
-		tmp = __raw_readl(ASYNC_EMIF_ONENAND_CONTROL);
-		tmp |= (1 << cs);
-		__raw_writel(tmp, ASYNC_EMIF_ONENAND_CONTROL);
-	}
-
-	tmp = __raw_readl(ASYNC_EMIF_CONFIG(cs));
-
-	set_config_field(tmp, SELECT_STROBE,	cfg->select_strobe);
-	set_config_field(tmp, EXTEND_WAIT,	cfg->extend_wait);
-	set_config_field(tmp, WR_SETUP,		cfg->wr_setup);
-	set_config_field(tmp, WR_STROBE,	cfg->wr_strobe);
-	set_config_field(tmp, WR_HOLD,		cfg->wr_hold);
-	set_config_field(tmp, RD_SETUP,		cfg->rd_setup);
-	set_config_field(tmp, RD_STROBE,	cfg->rd_strobe);
-	set_config_field(tmp, RD_HOLD,		cfg->rd_hold);
-	set_config_field(tmp, TURN_AROUND,	cfg->turn_around);
-	set_config_field(tmp, WIDTH,		cfg->width);
-
-	__raw_writel(tmp, ASYNC_EMIF_CONFIG(cs));
-}
-
-void init_async_emif(int num_cs, struct async_emif_config *config)
-{
-	int cs;
-
-	clk_enable(TNETV107X_LPSC_AEMIF);
-
-	for (cs = 0; cs < num_cs; cs++)
-		configure_async_emif(cs, config + cs);
-}
--- a/arch/arm/cpu/arm1176/tnetv107x/clock.c
+++ b/arch/arm/cpu/arm1176/tnetv107x/clock.c
@@ -1,451 +0,0 @@
-/*
- * TNETV107X: Clock management APIs
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <common.h>
-#include <asm-generic/errno.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-#include <asm/arch/clock.h>
-
-#define CLOCK_BASE		TNETV107X_CLOCK_CONTROL_BASE
-#define PSC_BASE		TNETV107X_PSC_BASE
-
-#define BIT(x)			(1 << (x))
-
-#define MAX_PREDIV		64
-#define MAX_POSTDIV		8
-#define MAX_MULT		512
-#define MAX_DIV			(MAX_PREDIV * MAX_POSTDIV)
-
-/* LPSC registers */
-#define PSC_PTCMD		0x120
-#define PSC_PTSTAT		0x128
-#define PSC_MDSTAT(n)		(0x800 + (n) * 4)
-#define PSC_MDCTL(n)		(0xA00 + (n) * 4)
-
-#define PSC_MDCTL_LRSTZ		BIT(8)
-
-#define psc_reg_read(reg)	__raw_readl((u32 *)(PSC_BASE + (reg)))
-#define psc_reg_write(reg, val)	__raw_writel(val, (u32 *)(PSC_BASE + (reg)))
-
-/* SSPLL registers */
-struct sspll_regs {
-	u32	modes;
-	u32	postdiv;
-	u32	prediv;
-	u32	mult_factor;
-	u32	divider_range;
-	u32	bw_divider;
-	u32	spr_amount;
-	u32	spr_rate_div;
-	u32	diag;
-};
-
-/* SSPLL base addresses */
-static struct sspll_regs *sspll_regs[] = {
-	(struct sspll_regs *)(CLOCK_BASE + 0x040),
-	(struct sspll_regs *)(CLOCK_BASE + 0x080),
-	(struct sspll_regs *)(CLOCK_BASE + 0x0c0),
-};
-
-#define sspll_reg(pll, reg)		(&(sspll_regs[pll]->reg))
-#define sspll_reg_read(pll, reg)	__raw_readl(sspll_reg(pll, reg))
-#define sspll_reg_write(pll, reg, val)	__raw_writel(val, sspll_reg(pll, reg))
-
-
-/* PLL Control Registers */
-struct pllctl_regs {
-	u32	ctl;		/* 00 */
-	u32	ocsel;		/* 04 */
-	u32	secctl;		/* 08 */
-	u32	__pad0;
-	u32	mult;		/* 10 */
-	u32	prediv;		/* 14 */
-	u32	div1;		/* 18 */
-	u32	div2;		/* 1c */
-	u32	div3;		/* 20 */
-	u32	oscdiv1;	/* 24 */
-	u32	postdiv;	/* 28 */
-	u32	bpdiv;		/* 2c */
-	u32	wakeup;		/* 30 */
-	u32	__pad1;
-	u32	cmd;		/* 38 */
-	u32	stat;		/* 3c */
-	u32	alnctl;		/* 40 */
-	u32	dchange;	/* 44 */
-	u32	cken;		/* 48 */
-	u32	ckstat;		/* 4c */
-	u32	systat;		/* 50 */
-	u32	ckctl;		/* 54 */
-	u32	__pad2[2];
-	u32	div4;		/* 60 */
-	u32	div5;		/* 64 */
-	u32	div6;		/* 68 */
-	u32	div7;		/* 6c */
-	u32	div8;		/* 70 */
-};
-
-struct lpsc_map {
-	int	pll, div;
-};
-
-static struct pllctl_regs *pllctl_regs[] = {
-	(struct pllctl_regs *)(CLOCK_BASE + 0x700),
-	(struct pllctl_regs *)(CLOCK_BASE + 0x300),
-	(struct pllctl_regs *)(CLOCK_BASE + 0x500),
-};
-
-#define pllctl_reg(pll, reg)		(&(pllctl_regs[pll]->reg))
-#define pllctl_reg_read(pll, reg)	__raw_readl(pllctl_reg(pll, reg))
-#define pllctl_reg_write(pll, reg, val)	__raw_writel(val, pllctl_reg(pll, reg))
-
-#define pllctl_reg_rmw(pll, reg, mask, val)			\
-	pllctl_reg_write(pll, reg,				\
-		(pllctl_reg_read(pll, reg) & ~(mask)) | val)
-
-#define pllctl_reg_setbits(pll, reg, mask)			\
-	pllctl_reg_rmw(pll, reg, 0, mask)
-
-#define pllctl_reg_clrbits(pll, reg, mask)			\
-	pllctl_reg_rmw(pll, reg, mask, 0)
-
-/* PLLCTL Bits */
-#define PLLCTL_CLKMODE		BIT(8)
-#define PLLCTL_PLLSELB		BIT(7)
-#define PLLCTL_PLLENSRC		BIT(5)
-#define PLLCTL_PLLDIS		BIT(4)
-#define PLLCTL_PLLRST		BIT(3)
-#define PLLCTL_PLLPWRDN		BIT(1)
-#define PLLCTL_PLLEN		BIT(0)
-
-#define PLLDIV_ENABLE		BIT(15)
-
-static int pll_div_offset[] = {
-#define div_offset(reg)	offsetof(struct pllctl_regs, reg)
-	div_offset(div1), div_offset(div2), div_offset(div3),
-	div_offset(div4), div_offset(div5), div_offset(div6),
-	div_offset(div7), div_offset(div8),
-};
-
-static unsigned long pll_bypass_mask[] = { 1, 4, 2 };
-static unsigned long pll_div_mask[] = { 0x01ff, 0x00ff, 0x00ff };
-
-/* Mappings from PLL+DIV to subsystem clocks */
-#define sys_arm1176_clk		{SYS_PLL, 0}
-#define sys_dsp_clk		{SYS_PLL, 1}
-#define sys_ddr_clk		{SYS_PLL, 2}
-#define sys_full_clk		{SYS_PLL, 3}
-#define sys_lcd_clk		{SYS_PLL, 4}
-#define sys_vlynq_ref_clk	{SYS_PLL, 5}
-#define sys_tsc_clk		{SYS_PLL, 6}
-#define sys_half_clk		{SYS_PLL, 7}
-
-#define eth_clk_5		{ETH_PLL, 0}
-#define eth_clk_50		{ETH_PLL, 1}
-#define eth_clk_125		{ETH_PLL, 2}
-#define eth_clk_250		{ETH_PLL, 3}
-#define eth_clk_25		{ETH_PLL, 4}
-
-#define tdm_clk			{TDM_PLL, 0}
-#define tdm_extra_clk		{TDM_PLL, 1}
-#define tdm1_clk		{TDM_PLL, 2}
-
-/* Optimization barrier */
-#define barrier()	\
-	__asm__ __volatile__("mov r0, r0\n" : : : "memory");
-
-static const struct lpsc_map lpsc_clk_map[] = {
-	[TNETV107X_LPSC_ARM]			= sys_arm1176_clk,
-	[TNETV107X_LPSC_GEM]			= sys_dsp_clk,
-	[TNETV107X_LPSC_DDR2_PHY]		= sys_ddr_clk,
-	[TNETV107X_LPSC_TPCC]			= sys_full_clk,
-	[TNETV107X_LPSC_TPTC0]			= sys_full_clk,
-	[TNETV107X_LPSC_TPTC1]			= sys_full_clk,
-	[TNETV107X_LPSC_RAM]			= sys_full_clk,
-	[TNETV107X_LPSC_MBX_LITE]		= sys_arm1176_clk,
-	[TNETV107X_LPSC_LCD]			= sys_lcd_clk,
-	[TNETV107X_LPSC_ETHSS]			= eth_clk_125,
-	[TNETV107X_LPSC_AEMIF]			= sys_full_clk,
-	[TNETV107X_LPSC_CHIP_CFG]		= sys_half_clk,
-	[TNETV107X_LPSC_TSC]			= sys_tsc_clk,
-	[TNETV107X_LPSC_ROM]			= sys_half_clk,
-	[TNETV107X_LPSC_UART2]			= sys_half_clk,
-	[TNETV107X_LPSC_PKTSEC]			= sys_half_clk,
-	[TNETV107X_LPSC_SECCTL]			= sys_half_clk,
-	[TNETV107X_LPSC_KEYMGR]			= sys_half_clk,
-	[TNETV107X_LPSC_KEYPAD]			= sys_half_clk,
-	[TNETV107X_LPSC_GPIO]			= sys_half_clk,
-	[TNETV107X_LPSC_MDIO]			= sys_half_clk,
-	[TNETV107X_LPSC_SDIO0]			= sys_half_clk,
-	[TNETV107X_LPSC_UART0]			= sys_half_clk,
-	[TNETV107X_LPSC_UART1]			= sys_half_clk,
-	[TNETV107X_LPSC_TIMER0]			= sys_half_clk,
-	[TNETV107X_LPSC_TIMER1]			= sys_half_clk,
-	[TNETV107X_LPSC_WDT_ARM]		= sys_half_clk,
-	[TNETV107X_LPSC_WDT_DSP]		= sys_half_clk,
-	[TNETV107X_LPSC_SSP]			= sys_half_clk,
-	[TNETV107X_LPSC_TDM0]			= tdm_clk,
-	[TNETV107X_LPSC_VLYNQ]			= sys_vlynq_ref_clk,
-	[TNETV107X_LPSC_MCDMA]			= sys_half_clk,
-	[TNETV107X_LPSC_USB0]			= sys_half_clk,
-	[TNETV107X_LPSC_TDM1]			= tdm1_clk,
-	[TNETV107X_LPSC_DEBUGSS]		= sys_half_clk,
-	[TNETV107X_LPSC_ETHSS_RGMII]		= eth_clk_250,
-	[TNETV107X_LPSC_SYSTEM]			= sys_half_clk,
-	[TNETV107X_LPSC_IMCOP]			= sys_dsp_clk,
-	[TNETV107X_LPSC_SPARE]			= sys_half_clk,
-	[TNETV107X_LPSC_SDIO1]			= sys_half_clk,
-	[TNETV107X_LPSC_USB1]			= sys_half_clk,
-	[TNETV107X_LPSC_USBSS]			= sys_half_clk,
-	[TNETV107X_LPSC_DDR2_EMIF1_VRST]	= sys_ddr_clk,
-	[TNETV107X_LPSC_DDR2_EMIF2_VCTL_RST]	= sys_ddr_clk,
-};
-
-static const unsigned long pll_ext_freq[] = {
-	[SYS_PLL] = CONFIG_PLL_SYS_EXT_FREQ,
-	[ETH_PLL] = CONFIG_PLL_ETH_EXT_FREQ,
-	[TDM_PLL] = CONFIG_PLL_TDM_EXT_FREQ,
-};
-
-static unsigned long pll_freq_get(int pll)
-{
-	unsigned long mult = 1, prediv = 1, postdiv = 1;
-	unsigned long ref = CONFIG_SYS_INT_OSC_FREQ;
-	unsigned long ret;
-	u32 bypass;
-
-	bypass = __raw_readl((u32 *)(CLOCK_BASE));
-	if (!(bypass & pll_bypass_mask[pll])) {
-		mult	= sspll_reg_read(pll, mult_factor);
-		prediv	= sspll_reg_read(pll, prediv) + 1;
-		postdiv	= sspll_reg_read(pll, postdiv) + 1;
-	}
-
-	if (pllctl_reg_read(pll, ctl) & PLLCTL_CLKMODE)
-		ref = pll_ext_freq[pll];
-
-	if (!(pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN))
-		return ref;
-
-	ret = (unsigned long)(ref + ((unsigned long long)ref * mult) / 256);
-	ret /= (prediv * postdiv);
-
-	return ret;
-}
-
-static unsigned long __pll_div_freq_get(int pll, unsigned int fpll,
-					int div)
-{
-	int divider = 1;
-	unsigned long divreg;
-
-	divreg = __raw_readl((void *)pllctl_regs[pll] + pll_div_offset[div]);
-
-	if (divreg & PLLDIV_ENABLE)
-		divider = (divreg & pll_div_mask[pll]) + 1;
-
-	return fpll / divider;
-}
-
-static unsigned long pll_div_freq_get(int pll, int div)
-{
-	unsigned int fpll = pll_freq_get(pll);
-
-	return __pll_div_freq_get(pll, fpll, div);
-}
-
-static void __pll_div_freq_set(int pll, unsigned int fpll, int div,
-			       unsigned long hz)
-{
-	int divider = (fpll / hz - 1);
-
-	divider &= pll_div_mask[pll];
-	divider |= PLLDIV_ENABLE;
-
-	__raw_writel(divider, (void *)pllctl_regs[pll] + pll_div_offset[div]);
-	pllctl_reg_setbits(pll, alnctl, (1 << div));
-	pllctl_reg_setbits(pll, dchange, (1 << div));
-}
-
-static unsigned long pll_div_freq_set(int pll, int div, unsigned long hz)
-{
-	unsigned int fpll = pll_freq_get(pll);
-
-	__pll_div_freq_set(pll, fpll, div, hz);
-
-	pllctl_reg_write(pll, cmd, 1);
-
-	/* Wait until new divider takes effect */
-	while (pllctl_reg_read(pll, stat) & 0x01);
-
-	return __pll_div_freq_get(pll, fpll, div);
-}
-
-unsigned long clk_get_rate(unsigned int clk)
-{
-	return pll_div_freq_get(lpsc_clk_map[clk].pll, lpsc_clk_map[clk].div);
-}
-
-unsigned long clk_round_rate(unsigned int clk, unsigned long hz)
-{
-	unsigned long fpll, divider, pll;
-
-	pll = lpsc_clk_map[clk].pll;
-	fpll = pll_freq_get(pll);
-	divider = (fpll / hz - 1);
-	divider &= pll_div_mask[pll];
-
-	return fpll / (divider + 1);
-}
-
-int clk_set_rate(unsigned int clk, unsigned long _hz)
-{
-	unsigned long hz;
-
-	hz = clk_round_rate(clk, _hz);
-	if (hz != _hz)
-		return -EINVAL;	/* Cannot set to target freq */
-
-	pll_div_freq_set(lpsc_clk_map[clk].pll, lpsc_clk_map[clk].div, hz);
-	return 0;
-}
-
-void lpsc_control(int mod, unsigned long state, int lrstz)
-{
-	u32 mdctl;
-
-	mdctl = psc_reg_read(PSC_MDCTL(mod));
-	mdctl &= ~0x1f;
-	mdctl |= state;
-
-	if (lrstz == 0)
-		mdctl &= ~PSC_MDCTL_LRSTZ;
-	else if (lrstz == 1)
-		mdctl |= PSC_MDCTL_LRSTZ;
-
-	psc_reg_write(PSC_MDCTL(mod), mdctl);
-
-	psc_reg_write(PSC_PTCMD, 1);
-
-	/* wait for power domain transition to end */
-	while (psc_reg_read(PSC_PTSTAT) & 1);
-
-	/* Wait for module state change */
-	while ((psc_reg_read(PSC_MDSTAT(mod)) & 0x1f) != state);
-}
-
-int lpsc_status(unsigned int id)
-{
-	return psc_reg_read(PSC_MDSTAT(id)) & 0x1f;
-}
-
-static void init_pll(const struct pll_init_data *data)
-{
-	unsigned long fpll;
-	unsigned long best_pre = 0, best_post = 0, best_mult = 0;
-	unsigned long div, prediv, postdiv, mult;
-	unsigned long delta, actual;
-	long best_delta = -1;
-	int i;
-	u32 tmp;
-
-	if (data->pll == SYS_PLL)
-		return; /* cannot reconfigure system pll on the fly */
-
-	tmp = pllctl_reg_read(data->pll, ctl);
-	if (data->internal_osc) {
-		tmp &= ~PLLCTL_CLKMODE;
-		fpll = CONFIG_SYS_INT_OSC_FREQ;
-	} else {
-		tmp |= PLLCTL_CLKMODE;
-		fpll = pll_ext_freq[data->pll];
-	}
-	pllctl_reg_write(data->pll, ctl, tmp);
-
-	mult = data->pll_freq / fpll;
-	for (mult = MAX(mult, 1); mult <= MAX_MULT; mult++) {
-		div = (fpll * mult) / data->pll_freq;
-		if (div < 1 || div > MAX_DIV)
-			continue;
-
-		for (postdiv = 1; postdiv <= min(div, MAX_POSTDIV); postdiv++) {
-			prediv = div / postdiv;
-			if (prediv < 1 || prediv > MAX_PREDIV)
-				continue;
-
-			actual = (fpll / prediv) * (mult / postdiv);
-			delta = (actual - data->pll_freq);
-			if (delta < 0)
-				delta = -delta;
-			if ((delta < best_delta) || (best_delta == -1)) {
-				best_delta = delta;
-				best_mult = mult;
-				best_pre = prediv;
-				best_post = postdiv;
-				if (delta == 0)
-					goto done;
-			}
-		}
-	}
-done:
-
-	if (best_delta == -1) {
-		printf("pll cannot derive %lu from %lu\n",
-				data->pll_freq, fpll);
-		return;
-	}
-
-	fpll = fpll * best_mult;
-	fpll /= best_pre * best_post;
-
-	pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLENSRC);
-	pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN);
-
-	pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLRST);
-
-	pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLPWRDN);
-	pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLDIS);
-
-	sspll_reg_write(data->pll, mult_factor,	(best_mult - 1) << 8);
-	sspll_reg_write(data->pll, prediv,	best_pre - 1);
-	sspll_reg_write(data->pll, postdiv,	best_post - 1);
-
-	for (i = 0; i < 10; i++)
-		if (data->div_freq[i])
-			__pll_div_freq_set(data->pll, fpll, i,
-					   data->div_freq[i]);
-
-	pllctl_reg_write(data->pll, cmd, 1);
-
-	/* Wait until pll "go" operation completes */
-	while (pllctl_reg_read(data->pll, stat) & 0x01);
-
-	pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLRST);
-	pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN);
-}
-
-void init_plls(int num_pll, struct pll_init_data *config)
-{
-	int i;
-
-	for (i = 0; i < num_pll; i++)
-		init_pll(&config[i]);
-}
--- a/arch/arm/cpu/arm1176/tnetv107x/init.c
+++ b/arch/arm/cpu/arm1176/tnetv107x/init.c
@@ -1,37 +0,0 @@
-/*
- * TNETV107X: Architecture initialization
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <common.h>
-#include <asm/io.h>
-
-void chip_configuration_unlock(void)
-{
-       __raw_writel(TNETV107X_KICK0_MAGIC, TNETV107X_KICK0);
-       __raw_writel(TNETV107X_KICK1_MAGIC, TNETV107X_KICK1);
-}
-
-int arch_cpu_init(void)
-{
-       icache_enable();
-       chip_configuration_unlock();
-
-       return 0;
-}
--- a/arch/arm/cpu/arm1176/tnetv107x/lowlevel_init.S
+++ b/arch/arm/cpu/arm1176/tnetv107x/lowlevel_init.S
@@ -1,25 +0,0 @@
-/*
- * TNETV107X: Low-level pre-relocation initialization
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-.globl lowlevel_init
-lowlevel_init:
-	/* nothing for now, maybe needed for more exotic boot modes */
-	mov	pc, lr
--- a/arch/arm/cpu/arm1176/tnetv107x/mux.c
+++ b/arch/arm/cpu/arm1176/tnetv107x/mux.c
@@ -1,334 +0,0 @@
-/*
- * TNETV107X: Pinmux configuration
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/mux.h>
-
-#define MUX_MODE_1		0x00
-#define MUX_MODE_2		0x04
-#define MUX_MODE_3		0x0c
-#define MUX_MODE_4		0x1c
-
-#define MUX_DEBUG		0
-
-static const struct pin_config pin_table[] = {
-	/*		  reg	shift	mode	*/
-	TNETV107X_MUX_CFG(0,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(0,	0,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(0,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(0,	5,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(0,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(0,	10,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(0,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(0,	15,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(0,	20,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(0,	20,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(0,	25,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(0,	25,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(1,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(1,	0,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(1,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(1,	5,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(1,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(1,	10,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(1,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(1,	15,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(1,	20,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(1,	20,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(1,	25,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(1,	25,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(2,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(2,	0,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(2,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(2,	5,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(2,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(2,	10,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(2,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(2,	15,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(2,	20,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(2,	20,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(2,	25,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(2,	25,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(3,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(3,	0,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(3,	0,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(3,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(3,	5,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(3,	5,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(3,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(3,	10,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(3,	10,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(3,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(3,	15,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(3,	15,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(3,	20,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(3,	20,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(3,	20,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(3,	25,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(3,	25,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(3,	25,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(4,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(4,	0,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(4,	0,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(4,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(4,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(4,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(4,	15,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(4,	20,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(4,	20,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(4,	25,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(4,	25,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(5,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(5,	0,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(5,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(5,	5,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(5,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(5,	10,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(5,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(5,	15,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(5,	20,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(5,	20,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(5,	25,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(5,	25,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(6,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(6,	0,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(6,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(6,	5,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(6,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(6,	10,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(6,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(6,	15,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(6,	20,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(6,	20,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(6,	25,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(6,	25,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(7,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(7,	0,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(7,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(7,	5,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(7,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(7,	10,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(7,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(7,	15,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(7,	20,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(7,	20,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(7,	25,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(7,	25,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(8,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(8,	0,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(8,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(8,	5,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(8,	5,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(8,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(8,	10,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(9,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(9,	0,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(9,	0,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(9,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(9,	5,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(9,	5,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(9,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(9,	10,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(9,	10,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(9,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(9,	15,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(9,	15,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(9,	20,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(9,	20,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(9,	20,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(10,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(10,	0,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(10,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(10,	5,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(10,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(10,	10,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(10,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(10,	15,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(10,	20,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(10,	20,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(10,	25,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(10,	25,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(11,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(11,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(12,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(12,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(12,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(12,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(12,	20,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(12,	25,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(13,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(13,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(13,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(13,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(14,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(14,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(14,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(14,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(14,	20,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(14,	25,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(15,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(15,	0,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(15,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(15,	5,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(15,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(15,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(15,	20,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(15,	25,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(16,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(16,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(16,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(16,	10,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(16,	10,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(16,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(16,	15,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(17,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(17,	0,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(17,	0,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(17,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(17,	5,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(17,	5,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(17,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(17,	10,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(17,	10,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(17,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(17,	15,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(17,	15,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(18,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(18,	0,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(18,	0,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(18,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(18,	5,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(18,	5,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(18,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(18,	10,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(18,	10,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(18,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(18,	15,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(18,	15,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(19,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(19,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(19,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(19,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(19,	20,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(19,	25,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(20,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(20,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(20,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(20,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(20,	15,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(20,	20,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(20,	25,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(21,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(21,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(21,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(21,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(21,	20,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(21,	25,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(22,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(22,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(22,	5,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(22,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(22,	10,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(22,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(22,	15,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(22,	15,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(22,	20,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(22,	20,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(22,	25,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(22,	25,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(23,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(23,	0,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(23,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(23,	5,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(23,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(23,	10,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(24,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(24,	0,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(24,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(24,	5,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(24,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(24,	10,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(24,	10,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(24,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(24,	15,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(24,	15,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(24,	20,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(24,	20,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(24,	25,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(24,	25,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(25,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(25,	0,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(25,	0,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(25,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(25,	5,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(25,	5,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(25,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(25,	10,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(25,	10,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(25,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(25,	15,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(25,	15,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(25,	15,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(26,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(26,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(26,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(26,	10,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(26,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(26,	15,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(26,	20,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(26,	20,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(26,	25,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(26,	25,	MUX_MODE_2),
-};
-
-const int pin_table_size = sizeof(pin_table) / sizeof(pin_table[0]);
-
-int mux_select_pin(short index)
-{
-	const struct pin_config *cfg;
-	unsigned long mask, mode, reg;
-
-	if (index >= pin_table_size)
-		return 0;
-
-	cfg = &pin_table[index];
-
-	mask = 0x1f << cfg->mask_offset;
-	mode = cfg->mode << cfg->mask_offset;
-
-	reg = __raw_readl(TNETV107X_PINMUX(cfg->reg_index));
-	reg = (reg & ~mask) | mode;
-	__raw_writel(reg, TNETV107X_PINMUX(cfg->reg_index));
-
-	return 1;
-}
-
-int mux_select_pins(const short *pins)
-{
-	int i, ret = 1;
-
-	for (i = 0; pins[i] >= 0; i++)
-		ret &= mux_select_pin(pins[i]);
-
-	return ret;
-}
--- a/arch/arm/cpu/arm1176/tnetv107x/timer.c
+++ b/arch/arm/cpu/arm1176/tnetv107x/timer.c
@@ -1,122 +0,0 @@
-/*
- * TNETV107X: Timer implementation
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-
-struct timer_regs {
-	u_int32_t pid12;
-	u_int32_t pad[3];
-	u_int32_t tim12;
-	u_int32_t tim34;
-	u_int32_t prd12;
-	u_int32_t prd34;
-	u_int32_t tcr;
-	u_int32_t tgcr;
-	u_int32_t wdtcr;
-};
-
-#define regs ((struct timer_regs *)CONFIG_SYS_TIMERBASE)
-
-#define TIMER_LOAD_VAL	(CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ)
-#define TIM_CLK_DIV	16
-
-static ulong timestamp;
-static ulong lastinc;
-
-int timer_init(void)
-{
-	clk_enable(TNETV107X_LPSC_TIMER0);
-
-	lastinc = timestamp = 0;
-
-	/* We are using timer34 in unchained 32-bit mode, full speed */
-	__raw_writel(0x0, &regs->tcr);
-	__raw_writel(0x0, &regs->tgcr);
-	__raw_writel(0x06 | ((TIM_CLK_DIV - 1) << 8), &regs->tgcr);
-	__raw_writel(0x0, &regs->tim34);
-	__raw_writel(TIMER_LOAD_VAL, &regs->prd34);
-	__raw_writel(2 << 22, &regs->tcr);
-
-	return 0;
-}
-
-void reset_timer(void)
-{
-	lastinc = timestamp = 0;
-
-	__raw_writel(0,		&regs->tcr);
-	__raw_writel(0,		&regs->tim34);
-	__raw_writel(2 << 22,	&regs->tcr);
-}
-
-static ulong get_timer_raw(void)
-{
-	ulong now = __raw_readl(&regs->tim34);
-
-	if (now >= lastinc)
-		timestamp += now - lastinc;
-	else
-		timestamp += now + TIMER_LOAD_VAL - lastinc;
-
-	lastinc = now;
-
-	return timestamp;
-}
-
-ulong get_timer(ulong base)
-{
-	return (get_timer_raw() / (TIMER_LOAD_VAL / TIM_CLK_DIV)) - base;
-}
-
-void set_timer(ulong t)
-{
-	timestamp = t;
-}
-
-unsigned long long get_ticks(void)
-{
-	return get_timer(0);
-}
-
-void __udelay(unsigned long usec)
-{
-	ulong tmo;
-	ulong endtime;
-	signed long diff;
-
-	tmo = CONFIG_SYS_HZ_CLOCK / 1000;
-	tmo *= usec;
-	tmo /= (1000 * TIM_CLK_DIV);
-
-	endtime = get_timer_raw() + tmo;
-
-	do {
-		ulong now = get_timer_raw();
-		diff = endtime - now;
-	} while (diff >= 0);
-}
-
-ulong get_tbclk(void)
-{
-	return CONFIG_SYS_HZ;
-}
--- a/arch/arm/cpu/arm1176/tnetv107x/wdt.c
+++ b/arch/arm/cpu/arm1176/tnetv107x/wdt.c
@@ -1,180 +0,0 @@
-/*
- * TNETV107X: Watchdog timer implementation (for reset)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-
-#define MAX_DIV		0xFFFE0001
-
-struct wdt_regs {
-	u32 kick_lock;
-#define KICK_LOCK_1	0x5555
-#define KICK_LOCK_2	0xaaaa
-	u32 kick;
-
-	u32 change_lock;
-#define CHANGE_LOCK_1	0x6666
-#define CHANGE_LOCK_2	0xbbbb
-	u32 change;
-
-	u32 disable_lock;
-#define DISABLE_LOCK_1	0x7777
-#define DISABLE_LOCK_2	0xcccc
-#define DISABLE_LOCK_3	0xdddd
-	u32 disable;
-
-	u32 prescale_lock;
-#define PRESCALE_LOCK_1	0x5a5a
-#define PRESCALE_LOCK_2	0xa5a5
-	u32 prescale;
-};
-
-static struct wdt_regs* regs = (struct wdt_regs *)TNETV107X_WDT0_ARM_BASE;
-
-#define wdt_reg_read(reg)	__raw_readl(&regs->reg)
-#define wdt_reg_write(reg, val)	__raw_writel((val), &regs->reg)
-
-static int write_prescale_reg(unsigned long prescale_value)
-{
-	wdt_reg_write(prescale_lock, PRESCALE_LOCK_1);
-	if ((wdt_reg_read(prescale_lock) & 0x3) != 0x1)
-		return -1;
-
-	wdt_reg_write(prescale_lock, PRESCALE_LOCK_2);
-	if ((wdt_reg_read(prescale_lock) & 0x3) != 0x3)
-		return -1;
-
-	wdt_reg_write(prescale, prescale_value);
-
-	return 0;
-}
-
-static int write_change_reg(unsigned long initial_timer_value)
-{
-	wdt_reg_write(change_lock, CHANGE_LOCK_1);
-	if ((wdt_reg_read(change_lock) & 0x3) != 0x1)
-		return -1;
-
-	wdt_reg_write(change_lock, CHANGE_LOCK_2);
-	if ((wdt_reg_read(change_lock) & 0x3) != 0x3)
-		return -1;
-
-	wdt_reg_write(change, initial_timer_value);
-
-	return 0;
-}
-
-static int wdt_control(unsigned long disable_value)
-{
-	wdt_reg_write(disable_lock, DISABLE_LOCK_1);
-	if ((wdt_reg_read(disable_lock) & 0x3) != 0x1)
-		return -1;
-
-	wdt_reg_write(disable_lock, DISABLE_LOCK_2);
-	if ((wdt_reg_read(disable_lock) & 0x3) != 0x2)
-		return -1;
-
-	wdt_reg_write(disable_lock, DISABLE_LOCK_3);
-	if ((wdt_reg_read(disable_lock) & 0x3) != 0x3)
-		return -1;
-
-	wdt_reg_write(disable, disable_value);
-	return 0;
-}
-
-static int wdt_set_period(unsigned long msec)
-{
-	unsigned long change_value, count_value;
-	unsigned long prescale_value = 1;
-	unsigned long refclk_khz, maxdiv;
-	int ret;
-
-	refclk_khz = clk_get_rate(TNETV107X_LPSC_WDT_ARM);
-	maxdiv = (MAX_DIV / refclk_khz);
-
-	if ((!msec) || (msec > maxdiv))
-		return -1;
-
-	count_value = refclk_khz * msec;
-	if (count_value > 0xffff) {
-		change_value = count_value / 0xffff + 1;
-		prescale_value = count_value / change_value;
-	} else {
-		change_value = count_value;
-	}
-
-	ret = write_prescale_reg(prescale_value - 1);
-	if (ret)
-		return ret;
-
-	ret = write_change_reg(change_value);
-	if (ret)
-		return ret;
-
-	return 0;
-}
-
-unsigned long last_wdt = -1;
-
-int wdt_start(unsigned long msecs)
-{
-	int ret;
-	ret = wdt_control(0);
-	if (ret)
-		return ret;
-	ret = wdt_set_period(msecs);
-	if (ret)
-		return ret;
-	ret = wdt_control(1);
-	if (ret)
-		return ret;
-	ret = wdt_kick();
-	last_wdt = msecs;
-	return ret;
-}
-
-int wdt_stop(void)
-{
-	last_wdt = -1;
-	return wdt_control(0);
-}
-
-int wdt_kick(void)
-{
-	wdt_reg_write(kick_lock, KICK_LOCK_1);
-	if ((wdt_reg_read(kick_lock) & 0x3) != 0x1)
-		return -1;
-
-	wdt_reg_write(kick_lock, KICK_LOCK_2);
-	if ((wdt_reg_read(kick_lock) & 0x3) != 0x3)
-		return -1;
-
-	wdt_reg_write(kick, 1);
-	return 0;
-}
-
-void reset_cpu(ulong addr)
-{
-	clk_enable(TNETV107X_LPSC_WDT_ARM);
-	wdt_start(1);
-	wdt_kick();
-}
--- a/arch/arm/cpu/arm920t/a320/ftsmc020.c
+++ b/arch/arm/cpu/arm920t/a320/ftsmc020.c
@@ -1,51 +0,0 @@
-/*
- * (C) Copyright 2009 Faraday Technology
- * Po-Yu Chuang <ratbert@faraday-tech.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <config.h>
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/ftsmc020.h>
-
-struct ftsmc020_config {
-	unsigned int	config;
-	unsigned int	timing;
-};
-
-static struct ftsmc020_config config[] = CONFIG_SYS_FTSMC020_CONFIGS;
-
-static struct ftsmc020 *smc = (struct ftsmc020 *)CONFIG_FTSMC020_BASE;
-
-static void ftsmc020_setup_bank(unsigned int bank, struct ftsmc020_config *cfg)
-{
-	if (bank > 3) {
-		printf("bank # %u invalid\n", bank);
-		return;
-	}
-
-	writel(cfg->config, &smc->bank[bank].cr);
-	writel(cfg->timing, &smc->bank[bank].tpr);
-}
-
-void ftsmc020_init(void)
-{
-	int i;
-
-	for (i = 0; i < ARRAY_SIZE(config); i++)
-		ftsmc020_setup_bank(i, &config[i]);
-}
--- a/arch/arm/cpu/arm920t/a320/reset.S
+++ b/arch/arm/cpu/arm920t/a320/reset.S
@@ -1,22 +0,0 @@
-/*
- * (C) Copyright 2009 Faraday Technology
- * Po-Yu Chuang <ratbert@faraday-tech.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-.global reset_cpu
-reset_cpu:
-	b	reset_cpu
--- a/arch/arm/cpu/arm920t/a320/timer.c
+++ b/arch/arm/cpu/arm920t/a320/timer.c
@@ -1,193 +0,0 @@
-/*
- * (C) Copyright 2009 Faraday Technology
- * Po-Yu Chuang <ratbert@faraday-tech.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/ftpmu010.h>
-#include <asm/arch/fttmr010.h>
-
-static ulong timestamp;
-static ulong lastdec;
-
-static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
-static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE;
-
-#define TIMER_CLOCK	32768
-#define TIMER_LOAD_VAL	0xffffffff
-
-int timer_init(void)
-{
-	unsigned int oscc;
-	unsigned int cr;
-
-	debug("%s()\n", __func__);
-
-	/* disable timers */
-	writel(0, &tmr->cr);
-
-	/*
-	 * use 32768Hz oscillator for RTC, WDT, TIMER
-	 */
-
-	/* enable the 32768Hz oscillator */
-	oscc = readl(&pmu->OSCC);
-	oscc &= ~(FTPMU010_OSCC_OSCL_OFF | FTPMU010_OSCC_OSCL_TRI);
-	writel(oscc, &pmu->OSCC);
-
-	/* wait until ready */
-	while (!(readl(&pmu->OSCC) & FTPMU010_OSCC_OSCL_STABLE))
-		;
-
-	/* select 32768Hz oscillator */
-	oscc = readl(&pmu->OSCC);
-	oscc |= FTPMU010_OSCC_OSCL_RTCLSEL;
-	writel(oscc, &pmu->OSCC);
-
-	/* setup timer */
-	writel(TIMER_LOAD_VAL, &tmr->timer3_load);
-	writel(TIMER_LOAD_VAL, &tmr->timer3_counter);
-	writel(0, &tmr->timer3_match1);
-	writel(0, &tmr->timer3_match2);
-
-	/* we don't want timer to issue interrupts */
-	writel(FTTMR010_TM3_MATCH1 |
-	       FTTMR010_TM3_MATCH2 |
-	       FTTMR010_TM3_OVERFLOW,
-	       &tmr->interrupt_mask);
-
-	cr = readl(&tmr->cr);
-	cr |= FTTMR010_TM3_CLOCK;	/* use external clock */
-	cr |= FTTMR010_TM3_ENABLE;
-	writel(cr, &tmr->cr);
-
-	/* init the timestamp and lastdec value */
-	reset_timer_masked();
-
-	return 0;
-}
-
-/*
- * timer without interrupts
- */
-
-/*
- * reset time
- */
-void reset_timer_masked(void)
-{
-	/* capure current decrementer value time */
-	lastdec = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ);
-	timestamp = 0;		/* start "advancing" time stamp from 0 */
-
-	debug("%s(): lastdec = %lx\n", __func__, lastdec);
-}
-
-void reset_timer(void)
-{
-	debug("%s()\n", __func__);
-	reset_timer_masked();
-}
-
-/*
- * return timer ticks
- */
-ulong get_timer_masked(void)
-{
-	/* current tick value */
-	ulong now = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ);
-
-	debug("%s(): now = %lx, lastdec = %lx\n", __func__, now, lastdec);
-
-	if (lastdec >= now) {
-		/*
-		 * normal mode (non roll)
-		 * move stamp fordward with absoulte diff ticks
-		 */
-		timestamp += lastdec - now;
-	} else {
-		/*
-		 * we have overflow of the count down timer
-		 *
-		 * nts = ts + ld + (TLV - now)
-		 * ts=old stamp, ld=time that passed before passing through -1
-		 * (TLV-now) amount of time after passing though -1
-		 * nts = new "advancing time stamp"...it could also roll and
-		 * cause problems.
-		 */
-		timestamp += lastdec + TIMER_LOAD_VAL - now;
-	}
-
-	lastdec = now;
-
-	debug("%s() returns %lx\n", __func__, timestamp);
-
-	return timestamp;
-}
-
-/*
- * return difference between timer ticks and base
- */
-ulong get_timer(ulong base)
-{
-	debug("%s(%lx)\n", __func__, base);
-	return get_timer_masked() - base;
-}
-
-void set_timer(ulong t)
-{
-	debug("%s(%lx)\n", __func__, t);
-	timestamp = t;
-}
-
-/* delay x useconds AND preserve advance timestamp value */
-void __udelay(unsigned long usec)
-{
-	long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
-	unsigned long now, last = readl(&tmr->timer3_counter);
-
-	debug("%s(%lu)\n", __func__, usec);
-	while (tmo > 0) {
-		now = readl(&tmr->timer3_counter);
-		if (now > last) /* count down timer overflow */
-			tmo -= TIMER_LOAD_VAL + last - now;
-		else
-			tmo -= last - now;
-		last = now;
-	}
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-	debug("%s()\n", __func__);
-	return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
-	debug("%s()\n", __func__);
-	return CONFIG_SYS_HZ;
-}
--- a/arch/arm/cpu/arm920t/at91/Makefile
+++ b/arch/arm/cpu/arm920t/at91/Makefile
@@ -1,47 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).a
-
-SOBJS	+= lowlevel_init.o
-COBJS	+= reset.o
-COBJS	+= timer.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS)
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
--- a/arch/arm/cpu/arm920t/at91/lowlevel_init.S
+++ b/arch/arm/cpu/arm920t/at91/lowlevel_init.S
@@ -1,164 +0,0 @@
-/*
- * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
- *		       Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
- *
- * Modified for the at91rm9200dk board by
- * (C) Copyright 2004
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_mc.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_pio.h>
-
-#define ARM920T_CONTROL	0xC0000000	/* @ set bit 31 (iA) and 30 (nF) */
-
-_MTEXT_BASE:
-#undef START_FROM_MEM
-#ifdef START_FROM_MEM
-	.word	TEXT_BASE-PHYS_FLASH_1
-#else
-	.word	TEXT_BASE
-#endif
-
-.globl lowlevel_init
-lowlevel_init:
-	ldr     r1, =AT91_ASM_PMC_MOR
-	/* Main oscillator Enable register */
-#ifdef CONFIG_SYS_USE_MAIN_OSCILLATOR
-	ldr     r0, =0x0000FF01		/* Enable main oscillator */
-#else
-	ldr     r0, =0x0000FF00		/* Disable main oscillator */
-#endif
-	str     r0, [r1] /*AT91C_CKGR_MOR] */
-	/* Add loop to compensate Main Oscillator startup time */
-	ldr     r0, =0x00000010
-LoopOsc:
-	subs    r0, r0, #1
-	bhi     LoopOsc
-
-	/* memory control configuration */
-	/* this isn't very elegant, but	 what the heck */
-	ldr	r0, =SMRDATA
-	ldr	r1, _MTEXT_BASE
-	sub	r0, r0, r1
-	add	r2, r0, #80
-pllloop:
-	/* the address */
-	ldr	r1, [r0], #4
-	/* the value */
-	ldr	r3, [r0], #4
-	str	r3, [r1]
-	cmp	r2, r0
-	bne	pllloop
-	/* delay - this is all done by guess */
-	ldr	r0, =0x00010000
-	/* (vs reading PMC_SR for LOCKA, LOCKB ... or MOSCS earlier) */
-lock:
-	subs	r0, r0, #1
-	bhi	lock
-	ldr	r0, =SMRDATA1
-	ldr	r1, _MTEXT_BASE
-	sub	r0, r0, r1
-	add	r2, r0, #176
-sdinit:
-	/* the address */
-	ldr	r1, [r0], #4
-	/* the value */
-	ldr	r3, [r0], #4
-	str	r3, [r1]
-	cmp	r2, r0
-	bne	sdinit
-
-	/* switch from FastBus to Asynchronous clock mode */
-	mrc	p15, 0, r0, c1, c0, 0
-	orr	r0, r0, #ARM920T_CONTROL
-	mcr	p15, 0, r0, c1, c0, 0
-
-	/* everything is fine now */
-	mov	pc, lr
-
-	.ltorg
-
-SMRDATA:
-	.word AT91_ASM_MC_EBI_CFG
-	.word CONFIG_SYS_EBI_CFGR_VAL
-	.word AT91_ASM_MC_SMC_CSR0
-	.word CONFIG_SYS_SMC_CSR0_VAL
-	.word AT91_ASM_PMC_PLLAR
-	.word CONFIG_SYS_PLLAR_VAL
-	.word AT91_ASM_PMC_PLLBR
-	.word CONFIG_SYS_PLLBR_VAL
-	.word AT91_ASM_PMC_MCKR
-	.word CONFIG_SYS_MCKR_VAL
-	/* here there's a delay */
-SMRDATA1:
-	.word AT91_ASM_PIOC_ASR
-	.word CONFIG_SYS_PIOC_ASR_VAL
-	.word AT91_ASM_PIOC_BSR
-	.word CONFIG_SYS_PIOC_BSR_VAL
-	.word AT91_ASM_PIOC_PDR
-	.word CONFIG_SYS_PIOC_PDR_VAL
-	.word AT91_ASM_MC_EBI_CSA
-	.word CONFIG_SYS_EBI_CSA_VAL
-	.word AT91_ASM_MC_SDRAMC_CR
-	.word CONFIG_SYS_SDRC_CR_VAL
-	.word AT91_ASM_MC_SDRAMC_MR
-	.word CONFIG_SYS_SDRC_MR_VAL
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
-	.word AT91_ASM_MC_SDRAMC_MR
-	.word CONFIG_SYS_SDRC_MR_VAL1
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
-	.word AT91_ASM_MC_SDRAMC_MR
-	.word CONFIG_SYS_SDRC_MR_VAL2
-	.word CONFIG_SYS_SDRAM1
-	.word CONFIG_SYS_SDRAM_VAL
-	.word AT91_ASM_MC_SDRAMC_TR
-	.word CONFIG_SYS_SDRC_TR_VAL
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
-	.word AT91_ASM_MC_SDRAMC_MR
-	.word CONFIG_SYS_SDRC_MR_VAL3
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
-	/* SMRDATA1 is 176 bytes long */
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
--- a/arch/arm/cpu/arm920t/at91/reset.c
+++ b/arch/arm/cpu/arm920t/at91/reset.c
@@ -1,59 +0,0 @@
-/*
- * (C) Copyright 2002
- * Lineo, Inc. <www.lineo.com>
- * Bernhard Kuhn <bkuhn@lineo.com>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_st.h>
-
-void board_reset(void) __attribute__((__weak__));
-
-void reset_cpu(ulong ignored)
-{
-	at91_st_t *st = (at91_st_t *) AT91_ST_BASE;
-#if defined(CONFIG_AT91RM9200_USART)
-	/*shutdown the console to avoid strange chars during reset */
-	serial_exit();
-#endif
-
-	if (board_reset)
-		board_reset();
-
-	/* Reset the cpu by setting up the watchdog timer */
-	writel(AT91_ST_WDMR_RSTEN | AT91_ST_WDMR_EXTEN | AT91_ST_WDMR_WDV(2),
-		&st->wdmr);
-	writel(AT91_ST_CR_WDRST, &st->cr);
-	/* and let it timeout */
-	while (1)
-		;
-	/* Never reached */
-}
--- a/arch/arm/cpu/arm920t/at91/timer.c
+++ b/arch/arm/cpu/arm920t/at91/timer.c
@@ -1,163 +0,0 @@
-/*
- * (C) Copyright 2002
- * Lineo, Inc. <www.lineo.com>
- * Bernhard Kuhn <bkuhn@lineo.com>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-
-#include <asm/io.h>
-#include <asm/hardware.h>
-#include <asm/arch/at91_tc.h>
-#include <asm/arch/at91_pmc.h>
-
-/* the number of clocks per CONFIG_SYS_HZ */
-#define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK/CONFIG_SYS_HZ)
-
-static u32 timestamp;
-static u32 lastinc;
-
-int timer_init(void)
-{
-	at91_tc_t *tc = (at91_tc_t *) AT91_TC_BASE;
-	at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
-
-	/* enables TC1.0 clock */
-	writel(1 << AT91_ID_TC0, &pmc->pcer);	/* enable clock */
-
-	writel(0, &tc->bcr);
-	writel(AT91_TC_BMR_TC0XC0S_NONE | AT91_TC_BMR_TC1XC1S_NONE |
-		AT91_TC_BMR_TC2XC2S_NONE , &tc->bmr);
-
-	writel(AT91_TC_CCR_CLKDIS, &tc->tc[0].ccr);
-	/* set to MCLK/2 and restart the timer
-	when the value in TC_RC is reached */
-	writel(AT91_TC_CMR_TCCLKS_CLOCK1 | AT91_TC_CMR_CPCTRG, &tc->tc[0].cmr);
-
-	writel(0xFFFFFFFF, &tc->tc[0].idr); /* disable interupts */
-	writel(TIMER_LOAD_VAL, &tc->tc[0].rc);
-
-	writel(AT91_TC_CCR_SWTRG | AT91_TC_CCR_CLKEN, &tc->tc[0].ccr);
-	lastinc = 0;
-	timestamp = 0;
-
-	return 0;
-}
-
-/*
- * timer without interrupts
- */
-
-void reset_timer(void)
-{
-	reset_timer_masked();
-}
-
-ulong get_timer(ulong base)
-{
-	return get_timer_masked() - base;
-}
-
-void set_timer(ulong t)
-{
-	timestamp = t;
-}
-
-void __udelay(unsigned long usec)
-{
-	udelay_masked(usec);
-}
-
-void reset_timer_masked(void)
-{
-	/* reset time */
-	at91_tc_t *tc = (at91_tc_t *) AT91_TC_BASE;
-	lastinc = readl(&tc->tc[0].cv) & 0x0000ffff;
-	timestamp = 0;
-}
-
-ulong get_timer_raw(void)
-{
-	at91_tc_t *tc = (at91_tc_t *) AT91_TC_BASE;
-	u32 now;
-
-	now = readl(&tc->tc[0].cv) & 0x0000ffff;
-
-	if (now >= lastinc) {
-		/* normal mode */
-		timestamp += now - lastinc;
-	} else {
-		/* we have an overflow ... */
-		timestamp += now + TIMER_LOAD_VAL - lastinc;
-	}
-	lastinc = now;
-
-	return timestamp;
-}
-
-ulong get_timer_masked(void)
-{
-	return get_timer_raw()/TIMER_LOAD_VAL;
-}
-
-void udelay_masked(unsigned long usec)
-{
-	u32 tmo;
-	u32 endtime;
-	signed long diff;
-
-	tmo = CONFIG_SYS_HZ_CLOCK / 1000;
-	tmo *= usec;
-	tmo /= 1000;
-
-	endtime = get_timer_raw() + tmo;
-
-	do {
-		u32 now = get_timer_raw();
-		diff = endtime - now;
-	} while (diff >= 0);
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-	return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
-	return CONFIG_SYS_HZ;
-}
--- a/arch/arm/cpu/arm920t/ep93xx/Makefile
+++ b/arch/arm/cpu/arm920t/ep93xx/Makefile
@@ -1,55 +0,0 @@
-#
-# Cirrus Logic EP93xx CPU-specific Makefile
-#
-# Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
-#
-# Copyright (C) 2004, 2005
-# Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
-#
-# Copyright (C) 2006
-# Dominic Rath <Dominic.Rath@gmx.de>
-#
-# Based on an original Makefile, which is
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this project.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful, but
-# WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-# or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
-# for more details.
-#
-# You should have received a copy of the GNU General Public License along
-# with this program; if not, write to the Free Software Foundation, Inc.,
-# 675 Mass Ave, Cambridge, MA 02139, USA.
-#
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)lib$(SOC).a
-
-COBJS   = cpu.o led.o speed.o timer.o
-SOBJS   = lowlevel_init.o
-
-SRCS    := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS    := $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-all:    $(obj).depend $(LIB)
-
-$(LIB): $(OBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS)
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
--- a/arch/arm/cpu/arm920t/ep93xx/cpu.c
+++ b/arch/arm/cpu/arm920t/ep93xx/cpu.c
@@ -1,51 +0,0 @@
-/*
- * Cirrus Logic EP93xx CPU-specific support.
- *
- * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
- *
- * Copyright (C) 2004, 2005
- * Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
- *
- * See file CREDITS for list of people who contributed to this project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- * or FITNESS FOR A PARTICULAR PURPOSE.	See the GNU General Public License
- * for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <common.h>
-#include <asm/arch/ep93xx.h>
-#include <asm/io.h>
-
-/* We reset the CPU by generating a 1-->0 transition on DeviceCfg bit 31. */
-extern void reset_cpu(ulong addr)
-{
-	struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
-	uint32_t value;
-
-	/* Unlock DeviceCfg and set SWRST */
-	writel(0xAA, &syscon->sysswlock);
-	value = readl(&syscon->devicecfg);
-	value |= SYSCON_DEVICECFG_SWRST;
-	writel(value, &syscon->devicecfg);
-
-	/* Unlock DeviceCfg and clear SWRST */
-	writel(0xAA, &syscon->sysswlock);
-	value = readl(&syscon->devicecfg);
-	value &= ~SYSCON_DEVICECFG_SWRST;
-	writel(value, &syscon->devicecfg);
-
-	/* Dying... */
-	while (1)
-		; /* noop */
-}
--- a/arch/arm/cpu/arm920t/ep93xx/led.c
+++ b/arch/arm/cpu/arm920t/ep93xx/led.c
@@ -1,101 +0,0 @@
-/*
- * Copyright (C) 2010, 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <asm/io.h>
-#include <asm/arch/ep93xx.h>
-#include <config.h>
-#include <status_led.h>
-
-static uint8_t saved_state[2] = {STATUS_LED_OFF, STATUS_LED_OFF};
-static uint32_t gpio_pin[2] = {1 << STATUS_LED_GREEN,
-			       1 << STATUS_LED_RED};
-
-inline void switch_LED_on(uint8_t led)
-{
-	register struct gpio_regs *gpio = (struct gpio_regs *)GPIO_BASE;
-
-	writel(readl(&gpio->pedr) | gpio_pin[led], &gpio->pedr);
-	saved_state[led] = STATUS_LED_ON;
-}
-
-inline void switch_LED_off(uint8_t led)
-{
-	register struct gpio_regs *gpio = (struct gpio_regs *)GPIO_BASE;
-
-	writel(readl(&gpio->pedr) & ~gpio_pin[led], &gpio->pedr);
-	saved_state[led] = STATUS_LED_OFF;
-}
-
-void red_LED_on(void)
-{
-	switch_LED_on(STATUS_LED_RED);
-}
-
-void red_LED_off(void)
-{
-	switch_LED_off(STATUS_LED_RED);
-}
-
-void green_LED_on(void)
-{
-	switch_LED_on(STATUS_LED_GREEN);
-}
-
-void green_LED_off(void)
-{
-	switch_LED_off(STATUS_LED_GREEN);
-}
-
-void __led_init(led_id_t mask, int state)
-{
-	__led_set(mask, state);
-}
-
-void __led_toggle(led_id_t mask)
-{
-	if (STATUS_LED_RED == mask) {
-		if (STATUS_LED_ON == saved_state[STATUS_LED_RED])
-			red_LED_off();
-		else
-			red_LED_on();
-	} else if (STATUS_LED_GREEN == mask) {
-		if (STATUS_LED_ON == saved_state[STATUS_LED_GREEN])
-			green_LED_off();
-		else
-			green_LED_on();
-	}
-}
-
-void __led_set(led_id_t mask, int state)
-{
-	if (STATUS_LED_RED == mask) {
-		if (STATUS_LED_ON == state)
-			red_LED_on();
-		else
-			red_LED_off();
-	} else if (STATUS_LED_GREEN == mask) {
-		if (STATUS_LED_ON == state)
-			green_LED_on();
-		else
-			green_LED_off();
-	}
-}
--- a/arch/arm/cpu/arm920t/ep93xx/lowlevel_init.S
+++ b/arch/arm/cpu/arm920t/ep93xx/lowlevel_init.S
@@ -1,65 +0,0 @@
-/*
- * Low-level initialization for EP93xx
- *
- * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
- *
- * Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <version.h>
-#include <asm/arch/ep93xx.h>
-
-.globl lowlevel_init
-lowlevel_init:
-	/* backup return address */
-	ldr r1, =SYSCON_SCRATCH0
-	str lr, [r1]
-
-	/* Turn on both LEDs */
-	bl red_LED_on
-	bl green_LED_on
-
-	/* Configure flash wait states before we switch to the PLL */
-	bl flash_cfg
-
-	/* Set up PLL */
-	bl pll_cfg
-
-	/* Turn off the Green LED and leave the Red LED on */
-	bl green_LED_off
-
-	/* Setup SDRAM */
-	bl sdram_cfg
-
-	/* Turn on Green LED, Turn off the Red LED */
-	bl green_LED_on
-	bl red_LED_off
-
-	/* FIXME: we use async mode for now */
-	mrc p15, 0, r0, c1, c0, 0
-	orr r0, r0, #0xc0000000
-	mcr p15, 0, r0, c1, c0, 0
-
-	/* restore return address */
-	ldr r1, =SYSCON_SCRATCH0
-	ldr lr, [r1]
-
-	mov pc, lr
--- a/arch/arm/cpu/arm920t/ep93xx/speed.c
+++ b/arch/arm/cpu/arm920t/ep93xx/speed.c
@@ -1,110 +0,0 @@
-/*
- * Cirrus Logic EP93xx PLL support.
- *
- * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
- *
- * See file CREDITS for list of people who contributed to this project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- * for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <common.h>
-#include <asm/arch/ep93xx.h>
-#include <asm/io.h>
-#include <div64.h>
-
-/*
- * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
- *
- * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
- * the specified bus in HZ.
- */
-
-/*
- * return the PLL output frequency
- *
- * PLL rate = CONFIG_SYS_CLK_FREQ * (X1FBD + 1) * (X2FBD + 1)
- * / (X2IPD + 1) / 2^PS
- */
-static ulong get_PLLCLK(uint32_t *pllreg)
-{
-	uint8_t i;
-	const uint32_t clkset = readl(pllreg);
-	uint64_t rate = CONFIG_SYS_CLK_FREQ;
-	rate *= ((clkset >> SYSCON_CLKSET_PLL_X1FBD1_SHIFT) & 0x1f) + 1;
-	rate *= ((clkset >> SYSCON_CLKSET_PLL_X2FBD2_SHIFT) & 0x3f) + 1;
-	do_div(rate, (clkset  & 0x1f) + 1);			/* X2IPD */
-	for (i = 0; i < ((clkset >> SYSCON_CLKSET_PLL_PS_SHIFT) & 3); i++)
-		rate >>= 1;
-
-	return (ulong)rate;
-}
-
-/* return FCLK frequency */
-ulong get_FCLK()
-{
-	const uint8_t fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 };
-	struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
-
-	const uint32_t clkset1 = readl(&syscon->clkset1);
-	const uint8_t fclk_div =
-		fclk_divisors[(clkset1 >> SYSCON_CLKSET1_FCLK_DIV_SHIFT) & 7];
-	const ulong fclk_rate = get_PLLCLK(&syscon->clkset1) / fclk_div;
-
-	return fclk_rate;
-}
-
-/* return HCLK frequency */
-ulong get_HCLK(void)
-{
-	const uint8_t hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 };
-	struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
-
-	const uint32_t clkset1 = readl(&syscon->clkset1);
-	const uint8_t hclk_div =
-		hclk_divisors[(clkset1 >> SYSCON_CLKSET1_HCLK_DIV_SHIFT) & 7];
-	const ulong hclk_rate = get_PLLCLK(&syscon->clkset1) / hclk_div;
-
-	return hclk_rate;
-}
-
-/* return PCLK frequency */
-ulong get_PCLK(void)
-{
-	const uint8_t pclk_divisors[] = { 1, 2, 4, 8 };
-	struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
-
-	const uint32_t clkset1 = readl(&syscon->clkset1);
-	const uint8_t pclk_div =
-		pclk_divisors[(clkset1 >> SYSCON_CLKSET1_PCLK_DIV_SHIFT) & 3];
-	const ulong pclk_rate = get_HCLK() / pclk_div;
-
-	return pclk_rate;
-}
-
-/* return UCLK frequency */
-ulong get_UCLK(void)
-{
-	struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
-	ulong uclk_rate;
-
-	const uint32_t value = readl(&syscon->pwrcnt);
-	if (value & SYSCON_PWRCNT_UART_BAUD)
-		uclk_rate = CONFIG_SYS_CLK_FREQ;
-	else
-		uclk_rate = CONFIG_SYS_CLK_FREQ / 2;
-
-	return uclk_rate;
-}
--- a/arch/arm/cpu/arm920t/ep93xx/timer.c
+++ b/arch/arm/cpu/arm920t/ep93xx/timer.c
@@ -1,143 +0,0 @@
-/*
- * Cirrus Logic EP93xx timer support.
- *
- * Copyright (C) 2009, 2010 Matthias Kaehlcke <matthias@kaehlcke.net>
- *
- * Copyright (C) 2004, 2005
- * Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
- *
- * Based on the original intr.c Cirrus Logic EP93xx Rev D. interrupt support,
- * author unknown.
- *
- * See file CREDITS for list of people who contributed to this project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- * for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <common.h>
-#include <linux/types.h>
-#include <asm/arch/ep93xx.h>
-#include <asm/io.h>
-#include <div64.h>
-
-#define TIMER_CLKSEL	(1 << 3)
-#define TIMER_ENABLE	(1 << 7)
-
-#define TIMER_FREQ			508469		/* ticks / second */
-#define TIMER_MAX_VAL			0xFFFFFFFF
-
-static struct ep93xx_timer
-{
-	unsigned long long ticks;
-	unsigned long last_read;
-} timer;
-
-static inline unsigned long long usecs_to_ticks(unsigned long usecs)
-{
-	unsigned long long ticks = (unsigned long long)usecs * TIMER_FREQ;
-	do_div(ticks, 1000 * 1000);
-
-	return ticks;
-}
-
-static inline void read_timer(void)
-{
-	struct timer_regs *timer_regs = (struct timer_regs *)TIMER_BASE;
-	const unsigned long now = TIMER_MAX_VAL - readl(&timer_regs->timer3.value);
-
-	if (now >= timer.last_read)
-		timer.ticks += now - timer.last_read;
-	else
-		/* an overflow occurred */
-		timer.ticks += TIMER_MAX_VAL - timer.last_read + now;
-
-	timer.last_read = now;
-}
-
-/*
- * Get the number of ticks (in CONFIG_SYS_HZ resolution)
- */
-unsigned long long get_ticks(void)
-{
-	unsigned long long sys_ticks;
-
-	read_timer();
-
-	sys_ticks = timer.ticks * CONFIG_SYS_HZ;
-	do_div(sys_ticks, TIMER_FREQ);
-
-	return sys_ticks;
-}
-
-unsigned long get_timer_masked(void)
-{
-	return get_ticks();
-}
-
-unsigned long get_timer(unsigned long base)
-{
-	return get_timer_masked() - base;
-}
-
-void reset_timer_masked(void)
-{
-	read_timer();
-	timer.ticks = 0;
-}
-
-void reset_timer(void)
-{
-	reset_timer_masked();
-}
-
-void __udelay(unsigned long usec)
-{
-	unsigned long long target;
-
-	read_timer();
-
-	target = timer.ticks + usecs_to_ticks(usec);
-
-	while (timer.ticks < target)
-		read_timer();
-}
-
-int timer_init(void)
-{
-	struct timer_regs *timer_regs = (struct timer_regs *)TIMER_BASE;
-
-	/* use timer 3 with 508KHz and free running, not enabled now */
-	writel(TIMER_CLKSEL, &timer_regs->timer3.control);
-
-	/* set initial timer value */
-	writel(TIMER_MAX_VAL, &timer_regs->timer3.load);
-
-	/* Enable the timer */
-	writel(TIMER_ENABLE | TIMER_CLKSEL,
-		&timer_regs->timer3.control);
-
-	reset_timer_masked();
-
-	return 0;
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-unsigned long get_tbclk(void)
-{
-	return CONFIG_SYS_HZ;
-}
--- a/arch/arm/cpu/arm920t/ep93xx/u-boot.lds
+++ b/arch/arm/cpu/arm920t/ep93xx/u-boot.lds
@@ -1,59 +0,0 @@
-/*
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN(4);
-	.text      :
-	{
-	  arch/arm/cpu/arm920t/start.o	(.text)
-		/* the EP93xx expects to find the pattern 'CRUS' at 0x1000 */
-	  . = 0x1000;
-	  LONG(0x53555243)
-	  *(.text)
-	}
-
-	. = ALIGN(4);
-	.rodata : { *(.rodata) }
-
-	. = ALIGN(4);
-	.data : { *(.data) }
-
-	. = ALIGN(4);
-	.got : { *(.got) }
-
-	. = .;
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
-	__u_boot_cmd_end = .;
-
-	. = ALIGN(4);
-	__bss_start = .;
-	.bss : { *(.bss) }
-	_end = .;
-}
--- a/arch/arm/cpu/arm926ejs/at91/at91cap9_devices.c
+++ b/arch/arm/cpu/arm926ejs/at91/at91cap9_devices.c
@@ -1,205 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian.pop@leadtechdesign.com>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * (C) Copyright 2009
- * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
- * esd electronic system design gmbh <www.esd.eu>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/io.h>
-
-void at91_serial0_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTA, 22, 1);		/* TXD0 */
-	at91_set_a_periph(AT91_PIO_PORTA, 23, 0);		/* RXD0 */
-	writel(1 << AT91CAP9_ID_US0, &pmc->pcer);
-}
-
-void at91_serial1_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTD, 0, 1);		/* TXD1 */
-	at91_set_a_periph(AT91_PIO_PORTD, 1, 0);		/* RXD1 */
-	writel(1 << AT91CAP9_ID_US1, &pmc->pcer);
-}
-
-void at91_serial2_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTD, 2, 1);		/* TXD2 */
-	at91_set_a_periph(AT91_PIO_PORTD, 3, 0);		/* RXD2 */
-	writel(1 << AT91CAP9_ID_US2, &pmc->pcer);
-}
-
-void at91_serial3_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTC, 30, 0);		/* DRXD */
-	at91_set_a_periph(AT91_PIO_PORTC, 31, 1);		/* DTXD */
-	writel(1 << AT91_ID_SYS, &pmc->pcer);
-}
-
-void at91_serial_hw_init(void)
-{
-#ifdef CONFIG_USART0
-	at91_serial0_hw_init();
-#endif
-
-#ifdef CONFIG_USART1
-	at91_serial1_hw_init();
-#endif
-
-#ifdef CONFIG_USART2
-	at91_serial2_hw_init();
-#endif
-
-#ifdef CONFIG_USART3	/* DBGU */
-	at91_serial3_hw_init();
-#endif
-}
-
-#ifdef CONFIG_HAS_DATAFLASH
-void at91_spi0_hw_init(unsigned long cs_mask)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_b_periph(AT91_PIO_PORTA, 0, 0);	/* SPI0_MISO */
-	at91_set_b_periph(AT91_PIO_PORTA, 1, 0);	/* SPI0_MOSI */
-	at91_set_b_periph(AT91_PIO_PORTA, 2, 0);	/* SPI0_SPCK */
-
-	/* Enable clock */
-	writel(1 << AT91CAP9_ID_SPI0, &pmc->pcer);
-
-	if (cs_mask & (1 << 0)) {
-		at91_set_b_periph(AT91_PIO_PORTA, 5, 1);
-	}
-	if (cs_mask & (1 << 1)) {
-		at91_set_b_periph(AT91_PIO_PORTA, 3, 1);
-	}
-	if (cs_mask & (1 << 2)) {
-		at91_set_b_periph(AT91_PIO_PORTD, 0, 1);
-	}
-	if (cs_mask & (1 << 3)) {
-		at91_set_b_periph(AT91_PIO_PORTD, 1, 1);
-	}
-	if (cs_mask & (1 << 4)) {
-		at91_set_pio_output(AT91_PIO_PORTA, 5, 1);
-	}
-	if (cs_mask & (1 << 5)) {
-		at91_set_pio_output(AT91_PIO_PORTA, 3, 1);
-	}
-	if (cs_mask & (1 << 6)) {
-		at91_set_pio_output(AT91_PIO_PORTD, 0, 1);
-	}
-	if (cs_mask & (1 << 7)) {
-		at91_set_pio_output(AT91_PIO_PORTD, 1, 1);
-	}
-}
-
-void at91_spi1_hw_init(unsigned long cs_mask)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTB, 12, 0);	/* SPI1_MISO */
-	at91_set_a_periph(AT91_PIO_PORTB, 13, 0);	/* SPI1_MOSI */
-	at91_set_a_periph(AT91_PIO_PORTB, 14, 0);	/* SPI1_SPCK */
-
-	/* Enable clock */
-	writel(1 << AT91CAP9_ID_SPI1, &pmc->pcer);
-
-	if (cs_mask & (1 << 0)) {
-		at91_set_a_periph(AT91_PIO_PORTB, 15, 1);
-	}
-	if (cs_mask & (1 << 1)) {
-		at91_set_a_periph(AT91_PIO_PORTB, 16, 1);
-	}
-	if (cs_mask & (1 << 2)) {
-		at91_set_a_periph(AT91_PIO_PORTB, 17, 1);
-	}
-	if (cs_mask & (1 << 3)) {
-		at91_set_a_periph(AT91_PIO_PORTB, 18, 1);
-	}
-	if (cs_mask & (1 << 4)) {
-		at91_set_pio_output(AT91_PIO_PORTB, 15, 1);
-	}
-	if (cs_mask & (1 << 5)) {
-		at91_set_pio_output(AT91_PIO_PORTB, 16, 1);
-	}
-	if (cs_mask & (1 << 6)) {
-		at91_set_pio_output(AT91_PIO_PORTB, 17, 1);
-	}
-	if (cs_mask & (1 << 7)) {
-		at91_set_pio_output(AT91_PIO_PORTB, 18, 1);
-	}
-
-}
-#endif
-
-#ifdef CONFIG_MACB
-void at91_macb_hw_init(void)
-{
-	at91_set_a_periph(AT91_PIO_PORTB, 21, 0);	/* ETXCK_EREFCK */
-	at91_set_a_periph(AT91_PIO_PORTB, 22, 0);	/* ERXDV */
-	at91_set_a_periph(AT91_PIO_PORTB, 25, 0);	/* ERX0 */
-	at91_set_a_periph(AT91_PIO_PORTB, 26, 0);	/* ERX1 */
-	at91_set_a_periph(AT91_PIO_PORTB, 27, 0);	/* ERXER */
-	at91_set_a_periph(AT91_PIO_PORTB, 28, 0);	/* ETXEN */
-	at91_set_a_periph(AT91_PIO_PORTB, 23, 0);	/* ETX0 */
-	at91_set_a_periph(AT91_PIO_PORTB, 24, 0);	/* ETX1 */
-	at91_set_a_periph(AT91_PIO_PORTB, 30, 0);	/* EMDIO */
-	at91_set_a_periph(AT91_PIO_PORTB, 29, 0);	/* EMDC */
-
-#ifndef CONFIG_RMII
-	at91_set_b_periph(AT91_PIO_PORTC, 25, 0);	/* ECRS */
-	at91_set_b_periph(AT91_PIO_PORTC, 26, 0);	/* ECOL */
-	at91_set_b_periph(AT91_PIO_PORTC, 22, 0);	/* ERX2 */
-	at91_set_b_periph(AT91_PIO_PORTC, 23, 0);	/* ERX3 */
-	at91_set_b_periph(AT91_PIO_PORTC, 27, 0);	/* ERXCK */
-	at91_set_b_periph(AT91_PIO_PORTC, 20, 0);	/* ETX2 */
-	at91_set_b_periph(AT91_PIO_PORTC, 21, 0);	/* ETX3 */
-	at91_set_b_periph(AT91_PIO_PORTC, 24, 0);	/* ETXER */
-#endif
-}
-#endif
-
-#ifdef CONFIG_AT91_CAN
-void at91_can_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTA, 12, 0);	/* CAN_TX */
-	at91_set_a_periph(AT91_PIO_PORTA, 13, 1);	/* CAN_RX */
-
-	/* Enable clock */
-	writel(1 << AT91CAP9_ID_CAN, &pmc->pcer);
-}
-#endif
--- a/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c
+++ b/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c
@@ -1,196 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian.pop@leadtechdesign.com>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/io.h>
-
-void at91_serial0_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTB, 4, 1);		/* TXD0 */
-	at91_set_a_periph(AT91_PIO_PORTB, 5, 0);		/* RXD0 */
-	writel(1 << AT91SAM9260_ID_US0, &pmc->pcer);
-}
-
-void at91_serial1_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTB, 6, 1);		/* TXD1 */
-	at91_set_a_periph(AT91_PIO_PORTB, 7, 0);		/* RXD1 */
-	writel(1 << AT91SAM9260_ID_US1, &pmc->pcer);
-}
-
-void at91_serial2_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTB, 8, 1);		/* TXD2 */
-	at91_set_a_periph(AT91_PIO_PORTB, 9, 0);		/* RXD2 */
-	writel(1 << AT91SAM9260_ID_US2, &pmc->pcer);
-}
-
-void at91_serial3_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTB, 14, 0);		/* DRXD */
-	at91_set_a_periph(AT91_PIO_PORTB, 15, 1);		/* DTXD */
-	writel(1 << AT91_ID_SYS, &pmc->pcer);
-}
-
-void at91_serial_hw_init(void)
-{
-#ifdef CONFIG_USART0
-	at91_serial0_hw_init();
-#endif
-
-#ifdef CONFIG_USART1
-	at91_serial1_hw_init();
-#endif
-
-#ifdef CONFIG_USART2
-	at91_serial2_hw_init();
-#endif
-
-#ifdef CONFIG_USART3	/* DBGU */
-	at91_serial3_hw_init();
-#endif
-}
-
-#if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI)
-void at91_spi0_hw_init(unsigned long cs_mask)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTA, 0, 0);	/* SPI0_MISO */
-	at91_set_a_periph(AT91_PIO_PORTA, 1, 0);	/* SPI0_MOSI */
-	at91_set_a_periph(AT91_PIO_PORTA, 2, 0);	/* SPI0_SPCK */
-
-	/* Enable clock */
-	writel(1 << AT91SAM9260_ID_SPI0, &pmc->pcer);
-
-	if (cs_mask & (1 << 0)) {
-		at91_set_a_periph(AT91_PIO_PORTA, 3, 1);
-	}
-	if (cs_mask & (1 << 1)) {
-		at91_set_b_periph(AT91_PIO_PORTC, 11, 1);
-	}
-	if (cs_mask & (1 << 2)) {
-		at91_set_b_periph(AT91_PIO_PORTC, 16, 1);
-	}
-	if (cs_mask & (1 << 3)) {
-		at91_set_b_periph(AT91_PIO_PORTC, 17, 1);
-	}
-	if (cs_mask & (1 << 4)) {
-		at91_set_pio_output(AT91_PIO_PORTA, 3, 1);
-	}
-	if (cs_mask & (1 << 5)) {
-		at91_set_pio_output(AT91_PIO_PORTC, 11, 1);
-	}
-	if (cs_mask & (1 << 6)) {
-		at91_set_pio_output(AT91_PIO_PORTC, 16, 1);
-	}
-	if (cs_mask & (1 << 7)) {
-		at91_set_pio_output(AT91_PIO_PORTC, 17, 1);
-	}
-}
-
-void at91_spi1_hw_init(unsigned long cs_mask)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTB, 0, 0);	/* SPI1_MISO */
-	at91_set_a_periph(AT91_PIO_PORTB, 1, 0);	/* SPI1_MOSI */
-	at91_set_a_periph(AT91_PIO_PORTB, 2, 0);	/* SPI1_SPCK */
-
-	/* Enable clock */
-	writel(1 << AT91SAM9260_ID_SPI1, &pmc->pcer);
-
-	if (cs_mask & (1 << 0)) {
-		at91_set_a_periph(AT91_PIO_PORTB, 3, 1);
-	}
-	if (cs_mask & (1 << 1)) {
-		at91_set_b_periph(AT91_PIO_PORTC, 5, 1);
-	}
-	if (cs_mask & (1 << 2)) {
-		at91_set_b_periph(AT91_PIO_PORTC, 4, 1);
-	}
-	if (cs_mask & (1 << 3)) {
-		at91_set_pio_output(AT91_PIO_PORTC, 3, 1);
-	}
-	if (cs_mask & (1 << 4)) {
-		at91_set_pio_output(AT91_PIO_PORTB, 3, 1);
-	}
-	if (cs_mask & (1 << 5)) {
-		at91_set_pio_output(AT91_PIO_PORTC, 5, 1);
-	}
-	if (cs_mask & (1 << 6)) {
-		at91_set_pio_output(AT91_PIO_PORTC, 4, 1);
-	}
-	if (cs_mask & (1 << 7)) {
-		at91_set_pio_output(AT91_PIO_PORTC, 3, 1);
-	}
-}
-#endif
-
-#ifdef CONFIG_MACB
-void at91_macb_hw_init(void)
-{
-	at91_set_a_periph(AT91_PIO_PORTA, 19, 0);	/* ETXCK_EREFCK */
-	at91_set_a_periph(AT91_PIO_PORTA, 17, 0);	/* ERXDV */
-	at91_set_a_periph(AT91_PIO_PORTA, 14, 0);	/* ERX0 */
-	at91_set_a_periph(AT91_PIO_PORTA, 15, 0);	/* ERX1 */
-	at91_set_a_periph(AT91_PIO_PORTA, 18, 0);	/* ERXER */
-	at91_set_a_periph(AT91_PIO_PORTA, 16, 0);	/* ETXEN */
-	at91_set_a_periph(AT91_PIO_PORTA, 12, 0);	/* ETX0 */
-	at91_set_a_periph(AT91_PIO_PORTA, 13, 0);	/* ETX1 */
-	at91_set_a_periph(AT91_PIO_PORTA, 21, 0);	/* EMDIO */
-	at91_set_a_periph(AT91_PIO_PORTA, 20, 0);	/* EMDC */
-
-#ifndef CONFIG_RMII
-	at91_set_b_periph(AT91_PIO_PORTA, 28, 0);	/* ECRS */
-	at91_set_b_periph(AT91_PIO_PORTA, 29, 0);	/* ECOL */
-	at91_set_b_periph(AT91_PIO_PORTA, 25, 0);	/* ERX2 */
-	at91_set_b_periph(AT91_PIO_PORTA, 26, 0);	/* ERX3 */
-	at91_set_b_periph(AT91_PIO_PORTA, 27, 0);	/* ERXCK */
-#if defined(CONFIG_AT91SAM9260EK) || defined(CONFIG_AFEB9260)
-	/*
-	 * use PA10, PA11 for ETX2, ETX3.
-	 * PA23 and PA24 are for TWI EEPROM
-	 */
-	at91_set_b_periph(AT91_PIO_PORTA, 10, 0);	/* ETX2 */
-	at91_set_b_periph(AT91_PIO_PORTA, 11, 0);	/* ETX3 */
-#else
-	at91_set_b_periph(AT91_PIO_PORTA, 23, 0);	/* ETX2 */
-	at91_set_b_periph(AT91_PIO_PORTA, 24, 0);	/* ETX3 */
-#endif
-	at91_set_b_periph(AT91_PIO_PORTA, 22, 0);	/* ETXER */
-#endif
-}
-#endif
--- a/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c
+++ b/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c
@@ -1,214 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian.pop@leadtechdesign.com>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * (C) Copyright 2009
- * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
- * esd electronic system design gmbh <www.esd.eu>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/io.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_pio.h>
-
-void at91_serial0_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTA, 26, 1);		/* TXD0 */
-	at91_set_a_periph(AT91_PIO_PORTA, 27, 0);		/* RXD0 */
-	writel(1 << AT91SAM9263_ID_US0, &pmc->pcer);
-}
-
-void at91_serial1_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTD, 0, 1);		/* TXD1 */
-	at91_set_a_periph(AT91_PIO_PORTD, 1, 0);		/* RXD1 */
-	writel(1 << AT91SAM9263_ID_US1, &pmc->pcer);
-}
-
-void at91_serial2_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTD, 2, 1);		/* TXD2 */
-	at91_set_a_periph(AT91_PIO_PORTD, 3, 0);		/* RXD2 */
-	writel(1 << AT91SAM9263_ID_US2, &pmc->pcer);
-}
-
-void at91_serial3_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTC, 30, 0);		/* DRXD */
-	at91_set_a_periph(AT91_PIO_PORTC, 31, 1);		/* DTXD */
-	writel(1 << AT91_ID_SYS, &pmc->pcer);
-}
-
-void at91_serial_hw_init(void)
-{
-#ifdef CONFIG_USART0
-	at91_serial0_hw_init();
-#endif
-
-#ifdef CONFIG_USART1
-	at91_serial1_hw_init();
-#endif
-
-#ifdef CONFIG_USART2
-	at91_serial2_hw_init();
-#endif
-
-#ifdef CONFIG_USART3	/* DBGU */
-	at91_serial3_hw_init();
-#endif
-}
-
-#ifdef CONFIG_HAS_DATAFLASH
-void at91_spi0_hw_init(unsigned long cs_mask)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_b_periph(AT91_PIO_PORTA, 0, 0);	/* SPI0_MISO */
-	at91_set_b_periph(AT91_PIO_PORTA, 1, 0);	/* SPI0_MOSI */
-	at91_set_b_periph(AT91_PIO_PORTA, 2, 0);	/* SPI0_SPCK */
-
-	/* Enable clock */
-	writel(1 << AT91SAM9263_ID_SPI0, &pmc->pcer);
-
-	if (cs_mask & (1 << 0)) {
-		at91_set_b_periph(AT91_PIO_PORTA, 5, 1);
-	}
-	if (cs_mask & (1 << 1)) {
-		at91_set_b_periph(AT91_PIO_PORTA, 3, 1);
-	}
-	if (cs_mask & (1 << 2)) {
-		at91_set_b_periph(AT91_PIO_PORTA, 4, 1);
-	}
-	if (cs_mask & (1 << 3)) {
-		at91_set_b_periph(AT91_PIO_PORTB, 11, 1);
-	}
-	if (cs_mask & (1 << 4)) {
-		at91_set_pio_output(AT91_PIO_PORTA, 5, 1);
-	}
-	if (cs_mask & (1 << 5)) {
-		at91_set_pio_output(AT91_PIO_PORTA, 3, 1);
-	}
-	if (cs_mask & (1 << 6)) {
-		at91_set_pio_output(AT91_PIO_PORTA, 4, 1);
-	}
-	if (cs_mask & (1 << 7)) {
-		at91_set_pio_output(AT91_PIO_PORTB, 11, 1);
-	}
-}
-
-void at91_spi1_hw_init(unsigned long cs_mask)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTB, 12, 0);	/* SPI1_MISO */
-	at91_set_a_periph(AT91_PIO_PORTB, 13, 0);	/* SPI1_MOSI */
-	at91_set_a_periph(AT91_PIO_PORTB, 14, 0);	/* SPI1_SPCK */
-
-	/* Enable clock */
-	writel(1 << AT91SAM9263_ID_SPI1, &pmc->pcer);
-
-	if (cs_mask & (1 << 0)) {
-		at91_set_a_periph(AT91_PIO_PORTB, 15, 1);
-	}
-	if (cs_mask & (1 << 1)) {
-		at91_set_a_periph(AT91_PIO_PORTB, 16, 1);
-	}
-	if (cs_mask & (1 << 2)) {
-		at91_set_a_periph(AT91_PIO_PORTB, 17, 1);
-	}
-	if (cs_mask & (1 << 3)) {
-		at91_set_a_periph(AT91_PIO_PORTB, 18, 1);
-	}
-	if (cs_mask & (1 << 4)) {
-		at91_set_pio_output(AT91_PIO_PORTB, 15, 1);
-	}
-	if (cs_mask & (1 << 5)) {
-		at91_set_pio_output(AT91_PIO_PORTB, 16, 1);
-	}
-	if (cs_mask & (1 << 6)) {
-		at91_set_pio_output(AT91_PIO_PORTB, 17, 1);
-	}
-	if (cs_mask & (1 << 7)) {
-		at91_set_pio_output(AT91_PIO_PORTB, 18, 1);
-	}
-}
-#endif
-
-#ifdef CONFIG_MACB
-void at91_macb_hw_init(void)
-{
-	at91_set_a_periph(AT91_PIO_PORTE, 21, 0);	/* ETXCK_EREFCK */
-	at91_set_b_periph(AT91_PIO_PORTC, 25, 0);	/* ERXDV */
-	at91_set_a_periph(AT91_PIO_PORTE, 25, 0);	/* ERX0 */
-	at91_set_a_periph(AT91_PIO_PORTE, 26, 0);	/* ERX1 */
-	at91_set_a_periph(AT91_PIO_PORTE, 27, 0);	/* ERXER */
-	at91_set_a_periph(AT91_PIO_PORTE, 28, 0);	/* ETXEN */
-	at91_set_a_periph(AT91_PIO_PORTE, 23, 0);	/* ETX0 */
-	at91_set_a_periph(AT91_PIO_PORTE, 24, 0);	/* ETX1 */
-	at91_set_a_periph(AT91_PIO_PORTE, 30, 0);	/* EMDIO */
-	at91_set_a_periph(AT91_PIO_PORTE, 29, 0);	/* EMDC */
-
-#ifndef CONFIG_RMII
-	at91_set_a_periph(AT91_PIO_PORTE, 22, 0);	/* ECRS */
-	at91_set_b_periph(AT91_PIO_PORTC, 26, 0);	/* ECOL */
-	at91_set_b_periph(AT91_PIO_PORTC, 22, 0);	/* ERX2 */
-	at91_set_b_periph(AT91_PIO_PORTC, 23, 0);	/* ERX3 */
-	at91_set_b_periph(AT91_PIO_PORTC, 27, 0);	/* ERXCK */
-	at91_set_b_periph(AT91_PIO_PORTC, 20, 0);	/* ETX2 */
-	at91_set_b_periph(AT91_PIO_PORTC, 21, 0);	/* ETX3 */
-	at91_set_b_periph(AT91_PIO_PORTC, 24, 0);	/* ETXER */
-#endif
-}
-#endif
-
-#ifdef CONFIG_USB_OHCI_NEW
-void at91_uhp_hw_init(void)
-{
-	/* Enable VBus on UHP ports */
-	at91_set_pio_output(AT91_PIO_PORTA, 21, 0);
-	at91_set_pio_output(AT91_PIO_PORTA, 24, 0);
-}
-#endif
-
-#ifdef CONFIG_AT91_CAN
-void at91_can_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTA, 13, 0);	/* CAN_TX */
-	at91_set_a_periph(AT91_PIO_PORTA, 14, 1);	/* CAN_RX */
-
-	/* Enable clock */
-	writel(1 << AT91SAM9263_ID_CAN, &pmc->pcer);
-}
-#endif
--- a/arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c
+++ b/arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c
@@ -1,187 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian.pop@leadtechdesign.com>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/io.h>
-
-void at91_serial0_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTB, 19, 1);	/* TXD0 */
-	at91_set_a_periph(AT91_PIO_PORTB, 18, 0);	/* RXD0 */
-	writel(1 << AT91SAM9G45_ID_US0, &pmc->pcer);
-}
-
-void at91_serial1_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTB, 4, 1);		/* TXD1 */
-	at91_set_a_periph(AT91_PIO_PORTB, 5, 0);		/* RXD1 */
-	writel(1 << AT91SAM9G45_ID_US1, &pmc->pcer);
-}
-
-void at91_serial2_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTD, 6, 1);		/* TXD2 */
-	at91_set_a_periph(AT91_PIO_PORTD, 7, 0);		/* RXD2 */
-	writel(1 << AT91SAM9G45_ID_US2, &pmc->pcer);
-}
-
-void at91_serial3_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTB, 12, 0);	/* DRXD */
-	at91_set_a_periph(AT91_PIO_PORTB, 13, 1);	/* DTXD */
-	writel(1 << AT91_ID_SYS, &pmc->pcer);
-}
-
-void at91_serial_hw_init(void)
-{
-#ifdef CONFIG_USART0
-	at91_serial0_hw_init();
-#endif
-
-#ifdef CONFIG_USART1
-	at91_serial1_hw_init();
-#endif
-
-#ifdef CONFIG_USART2
-	at91_serial2_hw_init();
-#endif
-
-#ifdef CONFIG_USART3	/* DBGU */
-	at91_serial3_hw_init();
-#endif
-}
-
-#ifdef CONFIG_ATMEL_SPI
-void at91_spi0_hw_init(unsigned long cs_mask)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTB, 0, 0);	/* SPI0_MISO */
-	at91_set_a_periph(AT91_PIO_PORTB, 1, 0);	/* SPI0_MOSI */
-	at91_set_a_periph(AT91_PIO_PORTB, 2, 0);	/* SPI0_SPCK */
-
-	/* Enable clock */
-	writel(1 << AT91SAM9G45_ID_SPI0, &pmc->pcer);
-
-	if (cs_mask & (1 << 0)) {
-		at91_set_a_periph(AT91_PIO_PORTB, 3, 0);
-	}
-	if (cs_mask & (1 << 1)) {
-		at91_set_b_periph(AT91_PIO_PORTB, 18, 0);
-	}
-	if (cs_mask & (1 << 2)) {
-		at91_set_b_periph(AT91_PIO_PORTB, 19, 0);
-	}
-	if (cs_mask & (1 << 3)) {
-		at91_set_b_periph(AT91_PIO_PORTD, 27, 0);
-	}
-	if (cs_mask & (1 << 4)) {
-		at91_set_pio_output(AT91_PIO_PORTB, 3, 0);
-	}
-	if (cs_mask & (1 << 5)) {
-		at91_set_pio_output(AT91_PIO_PORTB, 18, 0);
-	}
-	if (cs_mask & (1 << 6)) {
-		at91_set_pio_output(AT91_PIO_PORTB, 19, 0);
-	}
-	if (cs_mask & (1 << 7)) {
-		at91_set_pio_output(AT91_PIO_PORTD, 27, 0);
-	}
-}
-
-void at91_spi1_hw_init(unsigned long cs_mask)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTB, 14, 0);	/* SPI1_MISO */
-	at91_set_a_periph(AT91_PIO_PORTB, 15, 0);	/* SPI1_MOSI */
-	at91_set_a_periph(AT91_PIO_PORTB, 16, 0);	/* SPI1_SPCK */
-
-	/* Enable clock */
-	writel(1 << AT91SAM9G45_ID_SPI1, &pmc->pcer);
-
-	if (cs_mask & (1 << 0)) {
-		at91_set_a_periph(AT91_PIO_PORTB, 17, 0);
-	}
-	if (cs_mask & (1 << 1)) {
-		at91_set_b_periph(AT91_PIO_PORTD, 28, 0);
-	}
-	if (cs_mask & (1 << 2)) {
-		at91_set_a_periph(AT91_PIO_PORTD, 18, 0);
-	}
-	if (cs_mask & (1 << 3)) {
-		at91_set_a_periph(AT91_PIO_PORTD, 19, 0);
-	}
-	if (cs_mask & (1 << 4)) {
-		at91_set_pio_output(AT91_PIO_PORTB, 17, 0);
-	}
-	if (cs_mask & (1 << 5)) {
-		at91_set_pio_output(AT91_PIO_PORTD, 28, 0);
-	}
-	if (cs_mask & (1 << 6)) {
-		at91_set_pio_output(AT91_PIO_PORTD, 18, 0);
-	}
-	if (cs_mask & (1 << 7)) {
-		at91_set_pio_output(AT91_PIO_PORTD, 19, 0);
-	}
-
-}
-#endif
-
-#ifdef CONFIG_MACB
-void at91_macb_hw_init(void)
-{
-	at91_set_a_periph(AT91_PIO_PORTA, 17, 0);	/* ETXCK_EREFCK */
-	at91_set_a_periph(AT91_PIO_PORTA, 15, 0);	/* ERXDV */
-	at91_set_a_periph(AT91_PIO_PORTA, 12, 0);	/* ERX0 */
-	at91_set_a_periph(AT91_PIO_PORTA, 13, 0);	/* ERX1 */
-	at91_set_a_periph(AT91_PIO_PORTA, 16, 0);	/* ERXER */
-	at91_set_a_periph(AT91_PIO_PORTA, 14, 0);	/* ETXEN */
-	at91_set_a_periph(AT91_PIO_PORTA, 10, 0);	/* ETX0 */
-	at91_set_a_periph(AT91_PIO_PORTA, 11, 0);	/* ETX1 */
-	at91_set_a_periph(AT91_PIO_PORTA, 19, 0);	/* EMDIO */
-	at91_set_a_periph(AT91_PIO_PORTA, 18, 0);	/* EMDC */
-#ifndef CONFIG_RMII
-	at91_set_b_periph(AT91_PIO_PORTA, 29, 0);	/* ECRS */
-	at91_set_b_periph(AT91_PIO_PORTA, 30, 0);	/* ECOL */
-	at91_set_b_periph(AT91_PIO_PORTA, 8,  0);	/* ERX2 */
-	at91_set_b_periph(AT91_PIO_PORTA, 9,  0);	/* ERX3 */
-	at91_set_b_periph(AT91_PIO_PORTA, 28, 0);	/* ERXCK */
-	at91_set_b_periph(AT91_PIO_PORTA, 6,  0);	/* ETX2 */
-	at91_set_b_periph(AT91_PIO_PORTA, 7,  0);	/* ETX3 */
-	at91_set_b_periph(AT91_PIO_PORTA, 27, 0);	/* ETXER */
-#endif
-}
-#endif
--- a/arch/arm/cpu/arm926ejs/at91/cpu.c
+++ b/arch/arm/cpu/arm926ejs/at91/cpu.c
@@ -1,92 +0,0 @@
-/*
- * (C) Copyright 2009
- * Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#ifdef CONFIG_AT91_LEGACY
-#warning Your board is using legacy SoC access. Please update!
-#endif
-
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/io.h>
-
-#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
-#define CONFIG_SYS_AT91_MAIN_CLOCK 0
-#endif
-
-/*
- * The at91sam9260 has 4 GPBR (0-3), we'll use the last one, nr 3,
- * to keep track of the bootcount.
- */
-#define AT91_GPBR_BOOTCOUNT_REGISTER 3
-#define AT91_BOOTCOUNT_ADDRESS (AT91_GPBR + 4*AT91_GPBR_BOOTCOUNT_REGISTER)
-
-int arch_cpu_init(void)
-{
-	return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
-}
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo(void)
-{
-	char buf[32];
-
-	printf("CPU: %s\n", CONFIG_SYS_AT91_CPU_NAME);
-	printf("Crystal frequency: %8s MHz\n",
-					strmhz(buf, get_main_clk_rate()));
-	printf("CPU clock        : %8s MHz\n",
-					strmhz(buf, get_cpu_clk_rate()));
-	printf("Master clock     : %8s MHz\n",
-					strmhz(buf, get_mck_clk_rate()));
-
-	return 0;
-}
-#endif
-
-#ifdef CONFIG_BOOTCOUNT_LIMIT
-/*
- * Just as the mpc5xxx, we combine the BOOTCOUNT_MAGIC and boocount
- * in one 32-bit register. This is done, as the AT91SAM9260 only has
- * 4 GPBR.
- */
-void bootcount_store (ulong a)
-{
-	volatile ulong *save_addr =
-		(volatile ulong *)(AT91_BASE_SYS + AT91_BOOTCOUNT_ADDRESS);
-
-	*save_addr = (BOOTCOUNT_MAGIC & 0xffff0000) | (a & 0x0000ffff);
-}
-
-ulong bootcount_load (void)
-{
-	volatile ulong *save_addr =
-		(volatile ulong *)(AT91_BASE_SYS + AT91_BOOTCOUNT_ADDRESS);
-
-	if ((*save_addr & 0xffff0000) != (BOOTCOUNT_MAGIC & 0xffff0000))
-		return 0;
-	else
-		return (*save_addr & 0x0000ffff);
-}
-
-#endif /* CONFIG_BOOTCOUNT_LIMIT */
--- a/arch/arm/cpu/arm926ejs/mx25/Makefile
+++ b/arch/arm/cpu/arm926ejs/mx25/Makefile
@@ -1,46 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).a
-
-COBJS	= generic.o timer.o
-MX27OBJS = reset.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-SRCS	+= $(addprefix $(SRCTREE)/arch/arm/cpu/arm926ejs/mx27/,$(MX27OBJS:.o=.c))
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS) $(MX27OBJS))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS)
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
--- a/arch/arm/cpu/arm926ejs/mx25/generic.c
+++ b/arch/arm/cpu/arm926ejs/mx25/generic.c
@@ -1,263 +0,0 @@
-/*
- * (C) Copyright 2009 DENX Software Engineering
- * Author: John Rigby <jrigby@gmail.com>
- *
- * Based on mx27/generic.c:
- *  Copyright (c) 2008 Eric Jarrige <eric.jarrige@armadeus.org>
- *  Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <div64.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/imx25-pinmux.h>
-#ifdef CONFIG_MXC_MMC
-#include <asm/arch/mxcmmc.h>
-#endif
-
-/*
- *  get the system pll clock in Hz
- *
- *                  mfi + mfn / (mfd +1)
- *  f = 2 * f_ref * --------------------
- *                        pd + 1
- */
-static unsigned int imx_decode_pll (unsigned int pll, unsigned int f_ref)
-{
-	unsigned int mfi = (pll >> CCM_PLL_MFI_SHIFT)
-	    & CCM_PLL_MFI_MASK;
-	unsigned int mfn = (pll >> CCM_PLL_MFN_SHIFT)
-	    & CCM_PLL_MFN_MASK;
-	unsigned int mfd = (pll >> CCM_PLL_MFD_SHIFT)
-	    & CCM_PLL_MFD_MASK;
-	unsigned int pd = (pll >> CCM_PLL_PD_SHIFT)
-	    & CCM_PLL_PD_MASK;
-
-	mfi = mfi <= 5 ? 5 : mfi;
-
-	return lldiv (2 * (u64) f_ref * (mfi * (mfd + 1) + mfn),
-		      (mfd + 1) * (pd + 1));
-}
-
-static ulong imx_get_mpllclk (void)
-{
-	struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
-	ulong fref = 24000000;
-
-	return imx_decode_pll (readl (&ccm->mpctl), fref);
-}
-
-ulong imx_get_armclk (void)
-{
-	struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
-	ulong cctl = readl (&ccm->cctl);
-	ulong fref = imx_get_mpllclk ();
-	ulong div;
-
-	if (cctl & CCM_CCTL_ARM_SRC)
-		fref = lldiv ((fref * 3), 4);
-
-	div = ((cctl >> CCM_CCTL_ARM_DIV_SHIFT)
-	       & CCM_CCTL_ARM_DIV_MASK) + 1;
-
-	return lldiv (fref, div);
-}
-
-ulong imx_get_ahbclk (void)
-{
-	struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
-	ulong cctl = readl (&ccm->cctl);
-	ulong fref = imx_get_armclk ();
-	ulong div;
-
-	div = ((cctl >> CCM_CCTL_AHB_DIV_SHIFT)
-	       & CCM_CCTL_AHB_DIV_MASK) + 1;
-
-	return lldiv (fref, div);
-}
-
-ulong imx_get_perclk (int clk)
-{
-	struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
-	ulong fref = imx_get_ahbclk ();
-	ulong div;
-
-	div = readl (&ccm->pcdr[CCM_PERCLK_REG (clk)]);
-	div = ((div >> CCM_PERCLK_SHIFT (clk)) & CCM_PERCLK_MASK) + 1;
-
-	return lldiv (fref, div);
-}
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo (void)
-{
-	char buf[32];
-
-	printf ("CPU:   Freescale i.MX25 at %s MHz\n\n",
-		strmhz (buf, imx_get_armclk ()));
-	return 0;
-}
-#endif
-
-int cpu_eth_init (bd_t * bis)
-{
-#if defined(CONFIG_FEC_MXC)
-	struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
-	ulong val;
-
-	val = readl (&ccm->cgr0);
-	val |= (1 << 23);
-	writel (val, &ccm->cgr0);
-	return fecmxc_initialize (bis);
-#else
-	return 0;
-#endif
-}
-
-/*
- * Initializes on-chip MMC controllers.
- * to override, implement board_mmc_init()
- */
-int cpu_mmc_init (bd_t * bis)
-{
-#ifdef CONFIG_MXC_MMC
-	return mxc_mmc_init (bis);
-#else
-	return 0;
-#endif
-}
-
-#ifdef CONFIG_MXC_UART
-void mx25_uart_init_pins (void)
-{
-	struct iomuxc_mux_ctl *muxctl;
-	struct iomuxc_pad_ctl *padctl;
-	u32 inpadctl;
-	u32 outpadctl;
-	u32 muxmode0;
-
-	muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
-	padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
-	muxmode0 = MX25_PIN_MUX_MODE (0);
-	/*
-	 * set up input pins with hysteresis and 100K pull-ups
-	 */
-	inpadctl = MX25_PIN_PAD_CTL_HYS
-	    | MX25_PIN_PAD_CTL_PKE
-	    | MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PU;
-
-	/*
-	 * set up output pins with 100K pull-downs
-	 * FIXME: need to revisit this
-	 *      PUE is ignored if PKE is not set
-	 *      so the right value here is likely
-	 *        0x0 for no pull up/down
-	 *      or
-	 *        0xc0 for 100k pull down
-	 */
-	outpadctl = MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD;
-
-	/* UART1 */
-	/* rxd */
-	writel (muxmode0, &muxctl->pad_uart1_rxd);
-	writel (inpadctl, &padctl->pad_uart1_rxd);
-
-	/* txd */
-	writel (muxmode0, &muxctl->pad_uart1_txd);
-	writel (outpadctl, &padctl->pad_uart1_txd);
-
-	/* rts */
-	writel (muxmode0, &muxctl->pad_uart1_rts);
-	writel (outpadctl, &padctl->pad_uart1_rts);
-
-	/* cts */
-	writel (muxmode0, &muxctl->pad_uart1_cts);
-	writel (inpadctl, &padctl->pad_uart1_cts);
-}
-#endif /* CONFIG_MXC_UART */
-
-#ifdef CONFIG_FEC_MXC
-void mx25_fec_init_pins (void)
-{
-	struct iomuxc_mux_ctl *muxctl;
-	struct iomuxc_pad_ctl *padctl;
-	u32 inpadctl_100kpd;
-	u32 inpadctl_22kpu;
-	u32 outpadctl;
-	u32 muxmode0;
-
-	muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
-	padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
-	muxmode0 = MX25_PIN_MUX_MODE (0);
-	inpadctl_100kpd = MX25_PIN_PAD_CTL_HYS
-	    | MX25_PIN_PAD_CTL_PKE
-	    | MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD;
-	inpadctl_22kpu = MX25_PIN_PAD_CTL_HYS
-	    | MX25_PIN_PAD_CTL_PKE
-	    | MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_22K_PU;
-	/*
-	 * set up output pins with 100K pull-downs
-	 * FIXME: need to revisit this
-	 *      PUE is ignored if PKE is not set
-	 *      so the right value here is likely
-	 *        0x0 for no pull
-	 *      or
-	 *        0xc0 for 100k pull down
-	 */
-	outpadctl = MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD;
-
-	/* FEC_TX_CLK */
-	writel (muxmode0, &muxctl->pad_fec_tx_clk);
-	writel (inpadctl_100kpd, &padctl->pad_fec_tx_clk);
-
-	/* FEC_RX_DV */
-	writel (muxmode0, &muxctl->pad_fec_rx_dv);
-	writel (inpadctl_100kpd, &padctl->pad_fec_rx_dv);
-
-	/* FEC_RDATA0 */
-	writel (muxmode0, &muxctl->pad_fec_rdata0);
-	writel (inpadctl_100kpd, &padctl->pad_fec_rdata0);
-
-	/* FEC_TDATA0 */
-	writel (muxmode0, &muxctl->pad_fec_tdata0);
-	writel (outpadctl, &padctl->pad_fec_tdata0);
-
-	/* FEC_TX_EN */
-	writel (muxmode0, &muxctl->pad_fec_tx_en);
-	writel (outpadctl, &padctl->pad_fec_tx_en);
-
-	/* FEC_MDC */
-	writel (muxmode0, &muxctl->pad_fec_mdc);
-	writel (outpadctl, &padctl->pad_fec_mdc);
-
-	/* FEC_MDIO */
-	writel (muxmode0, &muxctl->pad_fec_mdio);
-	writel (inpadctl_22kpu, &padctl->pad_fec_mdio);
-
-	/* FEC_RDATA1 */
-	writel (muxmode0, &muxctl->pad_fec_rdata1);
-	writel (inpadctl_100kpd, &padctl->pad_fec_rdata1);
-
-	/* FEC_TDATA1 */
-	writel (muxmode0, &muxctl->pad_fec_tdata1);
-	writel (outpadctl, &padctl->pad_fec_tdata1);
-
-}
-#endif /* CONFIG_FEC_MXC */
--- a/arch/arm/cpu/arm926ejs/mx25/reset.c
+++ b/arch/arm/cpu/arm926ejs/mx25/reset.c
@@ -1,56 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * (C) Copyright 2009
- * Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-
-/*
- * Reset the cpu by setting up the watchdog timer and let it time out
- */
-void reset_cpu (ulong ignored)
-{
-	struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE;
-	/* Disable watchdog and set Time-Out field to 0 */
-	writel (0x00000000, &regs->wcr);
-
-	/* Write Service Sequence */
-	writel (0x00005555, &regs->wsr);
-	writel (0x0000AAAA, &regs->wsr);
-
-	/* Enable watchdog */
-	writel (WCR_WDE, &regs->wcr);
-
-	while (1) ;
-}
--- a/arch/arm/cpu/arm926ejs/mx25/timer.c
+++ b/arch/arm/cpu/arm926ejs/mx25/timer.c
@@ -1,187 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * (C) Copyright 2009
- * Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
- *
- * (C) Copyright 2009 DENX Software Engineering
- * Author: John Rigby <jrigby@gmail.com>
- * 	Add support for MX25
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <div64.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-
-static ulong timestamp;
-static ulong lastinc;
-
-/*
- * "time" is measured in 1 / CONFIG_SYS_HZ seconds,
- * "tick" is internal timer period
- */
-#ifdef CONFIG_MX25_TIMER_HIGH_PRECISION
-/* ~0.4% error - measured with stop-watch on 100s boot-delay */
-static inline unsigned long long tick_to_time(unsigned long long tick)
-{
-	tick *= CONFIG_SYS_HZ;
-	do_div(tick, CONFIG_MX25_CLK32);
-	return tick;
-}
-
-static inline unsigned long long time_to_tick(unsigned long long time)
-{
-	time *= CONFIG_MX25_CLK32;
-	do_div(time, CONFIG_SYS_HZ);
-	return time;
-}
-
-static inline unsigned long long us_to_tick(unsigned long long us)
-{
-	us = us * CONFIG_MX25_CLK32 + 999999;
-	do_div(us, 1000000);
-	return us;
-}
-#else
-/* ~2% error */
-#define TICK_PER_TIME	((CONFIG_MX25_CLK32 + CONFIG_SYS_HZ / 2) / \
-		CONFIG_SYS_HZ)
-#define US_PER_TICK	(1000000 / CONFIG_MX25_CLK32)
-
-static inline unsigned long long tick_to_time(unsigned long long tick)
-{
-	do_div(tick, TICK_PER_TIME);
-	return tick;
-}
-
-static inline unsigned long long time_to_tick(unsigned long long time)
-{
-	return time * TICK_PER_TIME;
-}
-
-static inline unsigned long long us_to_tick(unsigned long long us)
-{
-	us += US_PER_TICK - 1;
-	do_div(us, US_PER_TICK);
-	return us;
-}
-#endif
-
-/* nothing really to do with interrupts, just starts up a counter. */
-/* The 32KHz 32-bit timer overruns in 134217 seconds */
-int timer_init(void)
-{
-	int i;
-	struct gpt_regs *gpt = (struct gpt_regs *)IMX_GPT1_BASE;
-	struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
-
-	/* setup GP Timer 1 */
-	writel(GPT_CTRL_SWR, &gpt->ctrl);
-
-	writel(readl(&ccm->cgr1) | CCM_CGR1_GPT1, &ccm->cgr1);
-
-	for (i = 0; i < 100; i++)
-		writel(0, &gpt->ctrl); /* We have no udelay by now */
-	writel(0, &gpt->pre); /* prescaler = 1 */
-	/* Freerun Mode, 32KHz input */
-	writel(readl(&gpt->ctrl) | GPT_CTRL_CLKSOURCE_32 | GPT_CTRL_FRR,
-			&gpt->ctrl);
-	writel(readl(&gpt->ctrl) | GPT_CTRL_TEN, &gpt->ctrl);
-
-	return 0;
-}
-
-void reset_timer_masked(void)
-{
-	struct gpt_regs *gpt = (struct gpt_regs *)IMX_GPT1_BASE;
-	/* reset time */
-	/* capture current incrementer value time */
-	lastinc = readl(&gpt->counter);
-	timestamp = 0; /* start "advancing" time stamp from 0 */
-}
-
-void reset_timer(void)
-{
-	reset_timer_masked();
-}
-
-unsigned long long get_ticks (void)
-{
-	struct gpt_regs *gpt = (struct gpt_regs *)IMX_GPT1_BASE;
-	ulong now = readl(&gpt->counter); /* current tick value */
-
-	if (now >= lastinc) {
-		/*
-		 * normal mode (non roll)
-		 * move stamp forward with absolut diff ticks
-		 */
-		timestamp += (now - lastinc);
-	} else {
-		/* we have rollover of incrementer */
-		timestamp += (0xFFFFFFFF - lastinc) + now;
-	}
-	lastinc = now;
-	return timestamp;
-}
-
-ulong get_timer_masked (void)
-{
-	/*
-	 * get_ticks() returns a long long (64 bit), it wraps in
-	 * 2^64 / CONFIG_MX25_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
-	 * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
-	 * 5 * 10^6 days - long enough.
-	 */
-	return tick_to_time(get_ticks());
-}
-
-ulong get_timer (ulong base)
-{
-	return get_timer_masked () - base;
-}
-
-void set_timer (ulong t)
-{
-	timestamp = time_to_tick(t);
-}
-
-/* delay x useconds AND preserve advance timstamp value */
-void __udelay (unsigned long usec)
-{
-	unsigned long long tmp;
-	ulong tmo;
-
-	tmo = us_to_tick(usec);
-	tmp = get_ticks() + tmo;	/* get current timestamp */
-
-	while (get_ticks() < tmp)	/* loop till event */
-		 /*NOP*/;
-}
--- a/arch/arm/cpu/arm926ejs/orion5x/Makefile
+++ b/arch/arm/cpu/arm926ejs/orion5x/Makefile
@@ -1,55 +0,0 @@
-#
-# Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
-#
-# Based on original Kirkwood support which is
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
-# MA 02110-1301 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).a
-
-COBJS-y	= cpu.o
-COBJS-y	+= dram.o
-COBJS-y	+= timer.o
-
-ifndef CONFIG_SKIP_LOWLEVEL_INIT
-SOBJS	:= lowlevel_init.o
-endif
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS-y))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS)
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
--- a/arch/arm/cpu/arm926ejs/orion5x/cpu.c
+++ b/arch/arm/cpu/arm926ejs/orion5x/cpu.c
@@ -1,270 +0,0 @@
-/*
- * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
- *
- * Based on original Kirkwood support which is
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/cache.h>
-#include <u-boot/md5.h>
-#include <asm/arch/orion5x.h>
-#include <hush.h>
-
-#define BUFLEN	16
-
-void reset_cpu(unsigned long ignored)
-{
-	struct orion5x_cpu_registers *cpureg =
-	    (struct orion5x_cpu_registers *)ORION5X_CPU_REG_BASE;
-
-	writel(readl(&cpureg->rstoutn_mask) | (1 << 2),
-		&cpureg->rstoutn_mask);
-	writel(readl(&cpureg->sys_soft_rst) | 1,
-		&cpureg->sys_soft_rst);
-	while (1)
-		;
-}
-
-/*
- * Window Size
- * Used with the Base register to set the address window size and location.
- * Must be programmed from LSB to MSB as sequence of ones followed by
- * sequence of zeros. The number of ones specifies the size of the window in
- * 64 KByte granularity (e.g., a value of 0x00FF specifies 256 = 16 MByte).
- * NOTE: A value of 0x0 specifies 64-KByte size.
- */
-unsigned int orion5x_winctrl_calcsize(unsigned int sizeval)
-{
-	int i;
-	unsigned int j = 0;
-	u32 val = sizeval >> 1;
-
-	for (i = 0; val > 0x10000; i++) {
-		j |= (1 << i);
-		val = val >> 1;
-	}
-	return 0x0000ffff & j;
-}
-
-/*
- * orion5x_config_adr_windows - Configure address Windows
- *
- * There are 8 address windows supported by Orion5x Soc to addess different
- * devices. Each window can be configured for size, BAR and remap addr
- * Below configuration is standard for most of the cases
- *
- * If remap function not used, remap_lo must be set as base
- *
- * Reference Documentation:
- * Mbus-L to Mbus Bridge Registers Configuration.
- * (Sec 25.1 and 25.3 of Datasheet)
- */
-int orion5x_config_adr_windows(void)
-{
-	struct orion5x_win_registers *winregs =
-		(struct orion5x_win_registers *)ORION5X_CPU_WIN_BASE;
-
-	/* Window 0: PCIE MEM address space */
-	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCIE_MEM,
-		ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_MEM,
-		ORION5X_WIN_ENABLE), &winregs[0].ctrl);
-	writel(ORION5X_DEFADR_PCIE_MEM, &winregs[0].base);
-	writel(ORION5X_DEFADR_PCIE_MEM_REMAP_LO, &winregs[0].remap_lo);
-	writel(ORION5X_DEFADR_PCIE_MEM_REMAP_HI, &winregs[0].remap_hi);
-
-	/* Window 1: PCIE IO address space */
-	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCIE_IO,
-		ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_IO,
-		ORION5X_WIN_ENABLE), &winregs[1].ctrl);
-	writel(ORION5X_DEFADR_PCIE_IO, &winregs[1].base);
-	writel(ORION5X_DEFADR_PCIE_IO_REMAP_LO, &winregs[1].remap_lo);
-	writel(ORION5X_DEFADR_PCIE_IO_REMAP_HI, &winregs[1].remap_hi);
-
-	/* Window 2: PCI MEM address space */
-	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCI_MEM,
-		ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_MEM,
-		ORION5X_WIN_ENABLE), &winregs[2].ctrl);
-	writel(ORION5X_DEFADR_PCI_MEM, &winregs[2].base);
-
-	/* Window 3: PCI IO address space */
-	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCI_IO,
-		ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_IO,
-		ORION5X_WIN_ENABLE), &winregs[3].ctrl);
-	writel(ORION5X_DEFADR_PCI_IO, &winregs[3].base);
-
-	/* Window 4: DEV_CS0 address space */
-	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_DEV_CS0,
-		ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS0,
-		ORION5X_WIN_ENABLE), &winregs[4].ctrl);
-	writel(ORION5X_DEFADR_DEV_CS0, &winregs[4].base);
-
-	/* Window 5: DEV_CS1 address space */
-	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_DEV_CS1,
-		ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS1,
-		ORION5X_WIN_ENABLE), &winregs[5].ctrl);
-	writel(ORION5X_DEFADR_DEV_CS1, &winregs[5].base);
-
-	/* Window 6: DEV_CS2 address space */
-	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_DEV_CS2,
-		ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS2,
-		ORION5X_WIN_ENABLE), &winregs[6].ctrl);
-	writel(ORION5X_DEFADR_DEV_CS2, &winregs[6].base);
-
-	/* Window 7: BOOT Memory address space */
-	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_BOOTROM,
-		ORION5X_TARGET_DEVICE, ORION5X_ATTR_BOOTROM,
-		ORION5X_WIN_ENABLE), &winregs[7].ctrl);
-	writel(ORION5X_DEFADR_BOOTROM, &winregs[7].base);
-
-	return 0;
-}
-
-/*
- * Orion5x identification is done through PCIE space.
- */
-
-u32 orion5x_device_id(void)
-{
-	return readl(PCIE_DEV_ID_OFF) >> 16;
-}
-
-u32 orion5x_device_rev(void)
-{
-	return readl(PCIE_DEV_REV_OFF) & 0xff;
-}
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-
-/* Display device and revision IDs.
- * This function must cover all known device/revision
- * combinations, not only the one for which u-boot is
- * compiled; this way, one can identify actual HW in
- * case of a mismatch.
- */
-int print_cpuinfo(void)
-{
-	char dev_str[] = "0x0000";
-	char rev_str[] = "0x00";
-	char *dev_name = NULL;
-	char *rev_name = NULL;
-
-	u32 dev = orion5x_device_id();
-	u32 rev = orion5x_device_rev();
-
-	if (dev == MV88F5181_DEV_ID) {
-		dev_name = "MV88F5181";
-		if (rev == MV88F5181_REV_B1)
-			rev_name = "B1";
-		else if (rev == MV88F5181L_REV_A1) {
-			dev_name = "MV88F5181L";
-			rev_name = "A1";
-		} else if (rev == MV88F5181L_REV_A0) {
-			dev_name = "MV88F5181L";
-			rev_name = "A0";
-		}
-	} else if (dev == MV88F5182_DEV_ID) {
-		dev_name = "MV88F5182";
-		if (rev == MV88F5182_REV_A2)
-			rev_name = "A2";
-	} else if (dev == MV88F5281_DEV_ID) {
-		dev_name = "MV88F5281";
-		if (rev == MV88F5281_REV_D2)
-			rev_name = "D2";
-		else if (rev == MV88F5281_REV_D1)
-			rev_name = "D1";
-		else if (rev == MV88F5281_REV_D0)
-			rev_name = "D0";
-	} else if (dev == MV88F6183_DEV_ID) {
-		dev_name = "MV88F6183";
-		if (rev == MV88F6183_REV_B0)
-			rev_name = "B0";
-	}
-	if (dev_name == NULL) {
-		sprintf(dev_str, "0x%04x", dev);
-		dev_name = dev_str;
-	}
-	if (rev_name == NULL) {
-		sprintf(rev_str, "0x%02x", rev);
-		rev_name = rev_str;
-	}
-
-	printf("SoC:   Orion5x %s-%s\n", dev_name, rev_name);
-
-	return 0;
-}
-#endif /* CONFIG_DISPLAY_CPUINFO */
-
-#ifdef CONFIG_ARCH_CPU_INIT
-int arch_cpu_init(void)
-{
-	/* Enable and invalidate L2 cache in write through mode */
-	invalidate_l2_cache();
-
-	orion5x_config_adr_windows();
-
-	return 0;
-}
-#endif /* CONFIG_ARCH_CPU_INIT */
-
-/*
- * SOC specific misc init
- */
-#if defined(CONFIG_ARCH_MISC_INIT)
-int arch_misc_init(void)
-{
-	u32 temp;
-
-	/*CPU streaming & write allocate */
-	temp = readfr_extra_feature_reg();
-	temp &= ~(1 << 28);	/* disable wr alloc */
-	writefr_extra_feature_reg(temp);
-
-	temp = readfr_extra_feature_reg();
-	temp &= ~(1 << 29);	/* streaming disabled */
-	writefr_extra_feature_reg(temp);
-
-	/* L2Cache settings */
-	temp = readfr_extra_feature_reg();
-	/* Disable L2C pre fetch - Set bit 24 */
-	temp |= (1 << 24);
-	/* enable L2C - Set bit 22 */
-	temp |= (1 << 22);
-	writefr_extra_feature_reg(temp);
-
-	icache_enable();
-	/* Change reset vector to address 0x0 */
-	temp = get_cr();
-	set_cr(temp & ~CR_V);
-
-	/* Set CPIOs and MPPs - values provided by board
-	   include file */
-	writel(ORION5X_MPP0_7, ORION5X_MPP_BASE+0x00);
-	writel(ORION5X_MPP8_15, ORION5X_MPP_BASE+0x04);
-	writel(ORION5X_MPP16_23, ORION5X_MPP_BASE+0x50);
-	writel(ORION5X_GPIO_OUT_ENABLE, ORION5X_GPIO_BASE+0x04);
-
-	return 0;
-}
-#endif /* CONFIG_ARCH_MISC_INIT */
--- a/arch/arm/cpu/arm926ejs/orion5x/dram.c
+++ b/arch/arm/cpu/arm926ejs/orion5x/dram.c
@@ -1,64 +0,0 @@
-/*
- * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
- *
- * Based on original Kirkwood support which is
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <common.h>
-#include <config.h>
-#include <asm/arch/orion5x.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * orion5x_sdram_bar - reads SDRAM Base Address Register
- */
-u32 orion5x_sdram_bar(enum memory_bank bank)
-{
-	struct orion5x_ddr_addr_decode_registers *winregs =
-		(struct orion5x_ddr_addr_decode_registers *)
-		ORION5X_CPU_WIN_BASE;
-
-	u32 result = 0;
-	u32 enable = 0x01 & winregs[bank].size;
-
-	if ((!enable) || (bank > BANK3))
-		return 0;
-
-	result = winregs[bank].base;
-	return result;
-}
-
-int dram_init(void)
-{
-	int i;
-
-	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
-		gd->bd->bi_dram[i].start = orion5x_sdram_bar(i);
-		gd->bd->bi_dram[i].size = get_ram_size(
-			(volatile long *) (gd->bd->bi_dram[i].start),
-			CONFIG_MAX_RAM_BANK_SIZE);
-	}
-	return 0;
-}
--- a/arch/arm/cpu/arm926ejs/orion5x/lowlevel_init.S
+++ b/arch/arm/cpu/arm926ejs/orion5x/lowlevel_init.S
@@ -1,293 +0,0 @@
-/*
- * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
- *
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <config.h>
-#include "asm/arch/orion5x.h"
-
-/*
- * Configuration values for SDRAM access setup
- */
-
-#define SDRAM_CONFIG			0x3148400
-#define SDRAM_MODE			0x62
-#define SDRAM_CONTROL			0x4041000
-#define SDRAM_TIME_CTRL_LOW		0x11602220
-#define SDRAM_TIME_CTRL_HI		0x40c
-#define SDRAM_OPEN_PAGE_EN		0x0
-/* DDR 1 2x 32M NANYA NT5DS16M16CS-6K ==> 64MB */
-#define SDRAM_BANK0_SIZE		0x3ff0001
-#define SDRAM_ADDR_CTRL			0x10
-
-#define SDRAM_OP_NOP			0x05
-#define SDRAM_OP_SETMODE		0x03
-
-#define SDRAM_PAD_CTRL_WR_EN		0x80000000
-#define SDRAM_PAD_CTRL_TUNE_EN		0x00010000
-#define SDRAM_PAD_CTRL_DRVN_MASK	0x0000003f
-#define SDRAM_PAD_CTRL_DRVP_MASK	0x00000fc0
-
-/*
- * For Guideline MEM-3 - Drive Strength value
- */
-
-#define DDR1_PAD_STRENGTH_DEFAULT	0x00001000
-#define SDRAM_PAD_CTRL_DRV_STR_MASK	0x00003000
-
-/*
- * For Guideline MEM-4 - DQS Reference Delay Tuning
- */
-
-#define MSAR_ARMDDRCLCK_MASK		0x000000f0
-#define MSAR_ARMDDRCLCK_H_MASK		0x00000100
-
-#define MSAR_ARMDDRCLCK_333_167		0x00000000
-#define MSAR_ARMDDRCLCK_500_167		0x00000030
-#define MSAR_ARMDDRCLCK_667_167		0x00000060
-#define MSAR_ARMDDRCLCK_400_200_1	0x000001E0
-#define MSAR_ARMDDRCLCK_400_200		0x00000010
-#define MSAR_ARMDDRCLCK_600_200		0x00000050
-#define MSAR_ARMDDRCLCK_800_200		0x00000070
-
-#define FTDLL_DDR1_166MHZ		0x0047F001
-
-#define FTDLL_DDR1_200MHZ		0x0044D001
-
-/*
- * Low-level init happens right after start.S has switched to SVC32,
- * flushed and disabled caches and disabled MMU. We're still running
- * from the boot chip select, so the first thing we should do is set
- * up RAM for us to relocate into.
- */
-
-.globl lowlevel_init
-
-lowlevel_init:
-
-	/* Use 'r4 as the base for internal register accesses */
-	ldr	r4, =ORION5X_REGS_PHY_BASE
-
-	/* move internal registers from the default 0xD0000000
-	 * to their intended location, defined by SoC */
-	ldr	r3, =0xD0000000
-	add	r3, r3, #0x20000
-	str	r4, [r3, #0x80]
-
-	/* Use R3 as the base for DRAM registers */
-	add	r3, r4, #0x01000
-
-	/*DDR SDRAM Initialization Control */
-	ldr	r6, =0x00000001
-	str	r6, [r3, #0x480]
-
-	/* Use R3 as the base for PCI registers */
-	add	r3, r4, #0x31000
-
-	/* Disable arbiter */
-	ldr	r6, =0x00000030
-	str	r6, [r3, #0xd00]
-
-	/* Use R3 as the base for DRAM registers */
-	add	r3, r4, #0x01000
-
-	/* set all dram windows to 0 */
-	mov	r6, #0
-	str	r6, [r3, #0x504]
-	str	r6, [r3, #0x50C]
-	str	r6, [r3, #0x514]
-	str	r6, [r3, #0x51C]
-
-	/* 1) Configure SDRAM  */
-	ldr	r6, =SDRAM_CONFIG
-	str	r6, [r3, #0x400]
-
-	/* 2) Set SDRAM Control reg */
-	ldr	r6, =SDRAM_CONTROL
-	str	r6, [r3, #0x404]
-
-	/* 3) Write SDRAM address control register */
-	ldr	r6, =SDRAM_ADDR_CTRL
-	str	r6, [r3, #0x410]
-
-	/* 4) Write SDRAM bank 0 size register */
-	ldr	r6, =SDRAM_BANK0_SIZE
-	str	r6, [r3, #0x504]
-	/* keep other banks disabled */
-
-	/* 5) Write SDRAM open pages control register */
-	ldr	r6, =SDRAM_OPEN_PAGE_EN
-	str	r6, [r3, #0x414]
-
-	/* 6) Write SDRAM timing Low register */
-	ldr	r6, =SDRAM_TIME_CTRL_LOW
-	str	r6, [r3, #0x408]
-
-	/* 7) Write SDRAM timing High register */
-	ldr	r6, =SDRAM_TIME_CTRL_HI
-	str	r6, [r3, #0x40C]
-
-	/* 8) Write SDRAM mode register */
-	/* The CPU must not attempt to change the SDRAM Mode register setting */
-	/* prior to DRAM controller completion of the DRAM initialization     */
-	/* sequence. To guarantee this restriction, it is recommended that    */
-	/* the CPU sets the SDRAM Operation register to NOP command, performs */
-	/* read polling until the register is back in Normal operation value, */
-	/* and then sets SDRAM Mode register to its new value.		      */
-
-	/* 8.1 write 'nop' to SDRAM operation */
-	ldr	r6, =SDRAM_OP_NOP
-	str	r6, [r3, #0x418]
-
-	/* 8.2 poll SDRAM operation until back in 'normal' mode.  */
-1:
-	ldr	r6, [r3, #0x418]
-	cmp	r6, #0
-	bne	1b
-
-	/* 8.3 Now its safe to write new value to SDRAM Mode register	      */
-	ldr	r6, =SDRAM_MODE
-	str	r6, [r3, #0x41C]
-
-	/* 8.4 Set new mode */
-	ldr	r6, =SDRAM_OP_SETMODE
-	str	r6, [r3, #0x418]
-
-	/* 8.5 poll SDRAM operation until back in 'normal' mode.  */
-2:
-	ldr	r6, [r3, #0x418]
-	cmp	r6, #0
-	bne	2b
-
-	/* DDR SDRAM Address/Control Pads Calibration */
-	ldr	r6, [r3, #0x4C0]
-
-	/* Set Bit [31] to make the register writable			*/
-	orr	r6, r6, #SDRAM_PAD_CTRL_WR_EN
-	str	r6, [r3, #0x4C0]
-
-	bic	r6, r6, #SDRAM_PAD_CTRL_WR_EN
-	bic	r6, r6, #SDRAM_PAD_CTRL_TUNE_EN
-	bic	r6, r6, #SDRAM_PAD_CTRL_DRVN_MASK
-	bic	r6, r6, #SDRAM_PAD_CTRL_DRVP_MASK
-
-	/* Get the final N locked value of driving strength [22:17]	*/
-	mov	r1, r6
-	mov	r1, r1, LSL #9
-	mov	r1, r1, LSR #26	 /* r1[5:0]<DrvN>  = r3[22:17]<LockN>	*/
-	orr	r1, r1, r1, LSL #6 /* r1[11:6]<DrvP> = r1[5:0]<DrvN>	*/
-
-	/* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6]	*/
-	orr	r6, r6, r1
-	str	r6, [r3, #0x4C0]
-
-	/* DDR SDRAM Data Pads Calibration				*/
-	ldr	r6, [r3, #0x4C4]
-
-	/* Set Bit [31] to make the register writable			*/
-	orr	r6, r6, #SDRAM_PAD_CTRL_WR_EN
-	str	r6, [r3, #0x4C4]
-
-	bic	r6, r6, #SDRAM_PAD_CTRL_WR_EN
-	bic	r6, r6, #SDRAM_PAD_CTRL_TUNE_EN
-	bic	r6, r6, #SDRAM_PAD_CTRL_DRVN_MASK
-	bic	r6, r6, #SDRAM_PAD_CTRL_DRVP_MASK
-
-	/* Get the final N locked value of driving strength [22:17]	*/
-	mov	r1, r6
-	mov	r1, r1, LSL #9
-	mov	r1, r1, LSR #26
-	orr	r1, r1, r1, LSL #6 /* r1[5:0] = r3[22:17]<LockN>	*/
-
-	/* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6]	*/
-	orr	r6, r6, r1
-
-	str	r6, [r3, #0x4C4]
-
-	/* Implement Guideline (GL# MEM-3) Drive Strength Value		*/
-	/* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0		*/
-
-	ldr	r1, =DDR1_PAD_STRENGTH_DEFAULT
-
-	/* Enable writes to DDR SDRAM Addr/Ctrl Pads Calibration register */
-	ldr	r6, [r3, #0x4C0]
-	orr	r6, r6, #SDRAM_PAD_CTRL_WR_EN
-	str	r6, [r3, #0x4C0]
-
-	/* Correct strength and disable writes again */
-	bic	r6, r6, #SDRAM_PAD_CTRL_WR_EN
-	bic	r6, r6, #SDRAM_PAD_CTRL_DRV_STR_MASK
-	orr	r6, r6, r1
-	str	r6, [r3, #0x4C0]
-
-	/* Enable writes to DDR SDRAM Data Pads Calibration register */
-	ldr	r6, [r3, #0x4C4]
-	orr	r6, r6, #SDRAM_PAD_CTRL_WR_EN
-	str	r6, [r3, #0x4C4]
-
-	/* Correct strength and disable writes again */
-	bic	r6, r6, #SDRAM_PAD_CTRL_DRV_STR_MASK
-	bic	r6, r6, #SDRAM_PAD_CTRL_WR_EN
-	orr	r6, r6, r1
-	str	r6, [r3, #0x4C4]
-
-	/* Implement Guideline (GL# MEM-4) DQS Reference Delay Tuning	*/
-	/* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0		*/
-
-	/* Get the "sample on reset" register for the DDR frequancy	*/
-	ldr	r3, =0x10000
-	ldr	r6, [r3, #0x010]
-	ldr	r1, =MSAR_ARMDDRCLCK_MASK
-	and	r1, r6, r1
-
-	ldr	r6, =FTDLL_DDR1_166MHZ
-	cmp	r1, #MSAR_ARMDDRCLCK_333_167
-	beq	3f
-	cmp	r1, #MSAR_ARMDDRCLCK_500_167
-	beq	3f
-	cmp	r1, #MSAR_ARMDDRCLCK_667_167
-	beq	3f
-
-	ldr	r6, =FTDLL_DDR1_200MHZ
-	cmp	r1, #MSAR_ARMDDRCLCK_400_200_1
-	beq	3f
-	cmp	r1, #MSAR_ARMDDRCLCK_400_200
-	beq	3f
-	cmp	r1, #MSAR_ARMDDRCLCK_600_200
-	beq	3f
-	cmp	r1, #MSAR_ARMDDRCLCK_800_200
-	beq	3f
-
-	ldr	r6, =0
-
-3:
-	/* Use R3 as the base for DRAM registers */
-	add	r3, r4, #0x01000
-
-	ldr	r2, [r3, #0x484]
-	orr	r2, r2, r6
-	str	r2, [r3, #0x484]
-
-	/* Return to U-boot via saved link register */
-	mov	pc, lr
--- a/arch/arm/cpu/arm926ejs/orion5x/timer.c
+++ b/arch/arm/cpu/arm926ejs/orion5x/timer.c
@@ -1,181 +0,0 @@
-/*
-  * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
- *
- * Based on original Kirkwood support which is
- * Copyright (C) Marvell International Ltd. and its affiliates
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <common.h>
-#include <asm/arch/orion5x.h>
-
-#define UBOOT_CNTR	0	/* counter to use for uboot timer */
-
-/* Timer reload and current value registers */
-struct orion5x_tmr_val {
-	u32 reload;	/* Timer reload reg */
-	u32 val;	/* Timer value reg */
-};
-
-/* Timer registers */
-struct orion5x_tmr_registers {
-	u32 ctrl;	/* Timer control reg */
-	u32 pad[3];
-	struct orion5x_tmr_val tmr[2];
-	u32 wdt_reload;
-	u32 wdt_val;
-};
-
-struct orion5x_tmr_registers *orion5x_tmr_regs =
-	(struct orion5x_tmr_registers *)ORION5X_TIMER_BASE;
-
-/*
- * ARM Timers Registers Map
- */
-#define CNTMR_CTRL_REG			(&orion5x_tmr_regs->ctrl)
-#define CNTMR_RELOAD_REG(tmrnum)	(&orion5x_tmr_regs->tmr[tmrnum].reload)
-#define CNTMR_VAL_REG(tmrnum)		(&orion5x_tmr_regs->tmr[tmrnum].val)
-
-/*
- * ARM Timers Control Register
- * CPU_TIMERS_CTRL_REG (CTCR)
- */
-#define CTCR_ARM_TIMER_EN_OFFS(cntr)	(cntr * 2)
-#define CTCR_ARM_TIMER_EN_MASK(cntr)	(1 << CTCR_ARM_TIMER_EN_OFFS)
-#define CTCR_ARM_TIMER_EN(cntr)		(1 << CTCR_ARM_TIMER_EN_OFFS(cntr))
-#define CTCR_ARM_TIMER_DIS(cntr)	(0 << CTCR_ARM_TIMER_EN_OFFS(cntr))
-
-#define CTCR_ARM_TIMER_AUTO_OFFS(cntr)	((cntr * 2) + 1)
-#define CTCR_ARM_TIMER_AUTO_MASK(cntr)	(1 << 1)
-#define CTCR_ARM_TIMER_AUTO_EN(cntr)	(1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
-#define CTCR_ARM_TIMER_AUTO_DIS(cntr)	(0 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
-
-/*
- * ARM Timer\Watchdog Reload Register
- * CNTMR_RELOAD_REG (TRR)
- */
-#define TRG_ARM_TIMER_REL_OFFS		0
-#define TRG_ARM_TIMER_REL_MASK		0xffffffff
-
-/*
- * ARM Timer\Watchdog Register
- * CNTMR_VAL_REG (TVRG)
- */
-#define TVR_ARM_TIMER_OFFS		0
-#define TVR_ARM_TIMER_MASK		0xffffffff
-#define TVR_ARM_TIMER_MAX		0xffffffff
-#define TIMER_LOAD_VAL 			0xffffffff
-
-static inline ulong read_timer(void)
-{
-	return readl(CNTMR_VAL_REG(UBOOT_CNTR))
-	      / (CONFIG_SYS_TCLK / 1000);
-}
-
-static ulong timestamp;
-static ulong lastdec;
-
-void reset_timer_masked(void)
-{
-	/* reset time */
-	lastdec = read_timer();
-	timestamp = 0;
-}
-
-ulong get_timer_masked(void)
-{
-	ulong now = read_timer();
-
-	if (lastdec >= now) {
-		/* normal mode */
-		timestamp += lastdec - now;
-	} else {
-		/* we have an overflow ... */
-		timestamp += lastdec +
-			(TIMER_LOAD_VAL / (CONFIG_SYS_TCLK / 1000)) - now;
-	}
-	lastdec = now;
-
-	return timestamp;
-}
-
-void reset_timer(void)
-{
-	reset_timer_masked();
-}
-
-ulong get_timer(ulong base)
-{
-	return get_timer_masked() - base;
-}
-
-void set_timer(ulong t)
-{
-	timestamp = t;
-}
-
-static inline ulong uboot_cntr_val(void)
-{
-	return readl(CNTMR_VAL_REG(UBOOT_CNTR));
-}
-
-void __udelay(unsigned long usec)
-{
-	uint current;
-	ulong delayticks;
-
-	current = uboot_cntr_val();
-	delayticks = (usec * (CONFIG_SYS_TCLK / 1000000));
-
-	if (current < delayticks) {
-		delayticks -= current;
-		while (uboot_cntr_val() < current)
-			;
-		while ((TIMER_LOAD_VAL - delayticks) < uboot_cntr_val())
-			;
-	} else {
-		while (uboot_cntr_val() > (current - delayticks))
-			;
-	}
-}
-
-/*
- * init the counter
- */
-int timer_init(void)
-{
-	unsigned int cntmrctrl;
-
-	/* load value into timer */
-	writel(TIMER_LOAD_VAL, CNTMR_RELOAD_REG(UBOOT_CNTR));
-	writel(TIMER_LOAD_VAL, CNTMR_VAL_REG(UBOOT_CNTR));
-
-	/* enable timer in auto reload mode */
-	cntmrctrl = readl(CNTMR_CTRL_REG);
-	cntmrctrl |= CTCR_ARM_TIMER_EN(UBOOT_CNTR);
-	cntmrctrl |= CTCR_ARM_TIMER_AUTO_EN(UBOOT_CNTR);
-	writel(cntmrctrl, CNTMR_CTRL_REG);
-
-	/* init the timestamp and lastdec value */
-	reset_timer_masked();
-
-	return 0;
-}
--- a/arch/arm/cpu/arm926ejs/spear/Makefile
+++ b/arch/arm/cpu/arm926ejs/spear/Makefile
@@ -1,52 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).a
-
-COBJS	:= reset.o \
-	   timer.o
-SOBJS	:=
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
-
-clean:
-	rm -f $(SOBJS) $(OBJS)
-
-distclean:	clean
-	rm -f $(LIB) core *.bak $(obj).depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
--- a/arch/arm/cpu/arm926ejs/spear/reset.c
+++ b/arch/arm/cpu/arm926ejs/spear/reset.c
@@ -1,54 +0,0 @@
-/*
- * (C) Copyright 2009
- * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/spr_syscntl.h>
-
-void reset_cpu(ulong ignored)
-{
-	struct syscntl_regs *syscntl_regs_p =
-	    (struct syscntl_regs *)CONFIG_SPEAR_SYSCNTLBASE;
-
-	printf("System is going to reboot ...\n");
-
-	/*
-	 * This 1 second delay will allow the above message
-	 * to be printed before reset
-	 */
-	udelay((1000 * 1000));
-
-	/* Going into slow mode before resetting SOC */
-	writel(0x02, &syscntl_regs_p->scctrl);
-
-	/*
-	 * Writing any value to the system status register will
-	 * reset the SoC
-	 */
-	writel(0x00, &syscntl_regs_p->scsysstat);
-
-	/* system will restart */
-	while (1)
-		;
-}
--- a/arch/arm/cpu/arm926ejs/spear/timer.c
+++ b/arch/arm/cpu/arm926ejs/spear/timer.c
@@ -1,153 +0,0 @@
-/*
- * (C) Copyright 2009
- * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/spr_gpt.h>
-#include <asm/arch/spr_misc.h>
-
-#define GPT_RESOLUTION	(CONFIG_SPEAR_HZ_CLOCK / CONFIG_SPEAR_HZ)
-#define READ_TIMER()	(readl(&gpt_regs_p->count) & GPT_FREE_RUNNING)
-
-static struct gpt_regs *const gpt_regs_p =
-    (struct gpt_regs *)CONFIG_SPEAR_TIMERBASE;
-
-static struct misc_regs *const misc_regs_p =
-    (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
-
-static ulong timestamp;
-static ulong lastdec;
-
-int timer_init(void)
-{
-	u32 synth;
-
-	/* Prescaler setting */
-#if defined(CONFIG_SPEAR3XX)
-	writel(MISC_PRSC_CFG, &misc_regs_p->prsc2_clk_cfg);
-	synth = MISC_GPT4SYNTH;
-#elif defined(CONFIG_SPEAR600)
-	writel(MISC_PRSC_CFG, &misc_regs_p->prsc1_clk_cfg);
-	synth = MISC_GPT3SYNTH;
-#else
-# error Incorrect config. Can only be spear{600|300|310|320}
-#endif
-
-	writel(readl(&misc_regs_p->periph_clk_cfg) | synth,
-	       &misc_regs_p->periph_clk_cfg);
-
-	/* disable timers */
-	writel(GPT_PRESCALER_1 | GPT_MODE_AUTO_RELOAD, &gpt_regs_p->control);
-
-	/* load value for free running */
-	writel(GPT_FREE_RUNNING, &gpt_regs_p->compare);
-
-	/* auto reload, start timer */
-	writel(readl(&gpt_regs_p->control) | GPT_ENABLE, &gpt_regs_p->control);
-
-	reset_timer_masked();
-
-	return 0;
-}
-
-/*
- * timer without interrupts
- */
-
-void reset_timer(void)
-{
-	reset_timer_masked();
-}
-
-ulong get_timer(ulong base)
-{
-	return (get_timer_masked() / GPT_RESOLUTION) - base;
-}
-
-void set_timer(ulong t)
-{
-	timestamp = t;
-}
-
-void __udelay(unsigned long usec)
-{
-	ulong tmo;
-	ulong start = get_timer_masked();
-	ulong tenudelcnt = CONFIG_SPEAR_HZ_CLOCK / (1000 * 100);
-	ulong rndoff;
-
-	rndoff = (usec % 10) ? 1 : 0;
-
-	/* tenudelcnt timer tick gives 10 microsecconds delay */
-	tmo = ((usec / 10) + rndoff) * tenudelcnt;
-
-	while ((ulong) (get_timer_masked() - start) < tmo)
-		;
-}
-
-void reset_timer_masked(void)
-{
-	/* reset time */
-	lastdec = READ_TIMER();
-	timestamp = 0;
-}
-
-ulong get_timer_masked(void)
-{
-	ulong now = READ_TIMER();
-
-	if (now >= lastdec) {
-		/* normal mode */
-		timestamp += now - lastdec;
-	} else {
-		/* we have an overflow ... */
-		timestamp += now + GPT_FREE_RUNNING - lastdec;
-	}
-	lastdec = now;
-
-	return timestamp;
-}
-
-void udelay_masked(unsigned long usec)
-{
-	return udelay(usec);
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-	return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
-	return CONFIG_SPEAR_HZ;
-}
--- a/arch/arm/cpu/arm_cortexa8/mx51/Makefile
+++ b/arch/arm/cpu/arm_cortexa8/mx51/Makefile
@@ -1,48 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2009 Freescale Semiconductor, Inc.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).a
-
-COBJS	= soc.o clock.o iomux.o timer.o speed.o
-SOBJS = lowlevel_init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS)
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
--- a/arch/arm/cpu/arm_cortexa8/mx51/clock.c
+++ b/arch/arm/cpu/arm_cortexa8/mx51/clock.c
@@ -1,294 +0,0 @@
-/*
- * (C) Copyright 2007
- * Sascha Hauer, Pengutronix
- *
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/errno.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/clock.h>
-
-enum pll_clocks {
-	PLL1_CLOCK = 0,
-	PLL2_CLOCK,
-	PLL3_CLOCK,
-	PLL_CLOCKS,
-};
-
-struct mxc_pll_reg *mxc_plls[PLL_CLOCKS] = {
-	[PLL1_CLOCK] = (struct mxc_pll_reg *)PLL1_BASE_ADDR,
-	[PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR,
-	[PLL3_CLOCK] = (struct mxc_pll_reg *)PLL3_BASE_ADDR,
-};
-
-struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
-
-/*
- * Calculate the frequency of this pll.
- */
-static u32 decode_pll(struct mxc_pll_reg *pll, u32 infreq)
-{
-	u32 mfi, mfn, mfd, pd;
-
-	mfn = __raw_readl(&pll->mfn);
-	mfd = __raw_readl(&pll->mfd) + 1;
-	mfi = __raw_readl(&pll->op);
-	pd = (mfi  & 0xF) + 1;
-	mfi = (mfi >> 4) & 0xF;
-	mfi = (mfi >= 5) ? mfi : 5;
-
-	return ((4 * (infreq / 1000) * (mfi * mfd + mfn)) / (mfd * pd)) * 1000;
-}
-
-/*
- * Get mcu main rate
- */
-u32 get_mcu_main_clk(void)
-{
-	u32 reg, freq;
-
-	reg = (__raw_readl(&mxc_ccm->cacrr) & MXC_CCM_CACRR_ARM_PODF_MASK) >>
-		MXC_CCM_CACRR_ARM_PODF_OFFSET;
-	freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_MX51_HCLK_FREQ);
-	return freq / (reg + 1);
-}
-
-/*
- * Get the rate of peripheral's root clock.
- */
-static u32 get_periph_clk(void)
-{
-	u32 reg;
-
-	reg = __raw_readl(&mxc_ccm->cbcdr);
-	if (!(reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL))
-		return decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_MX51_HCLK_FREQ);
-	reg = __raw_readl(&mxc_ccm->cbcmr);
-	switch ((reg & MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >>
-		MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) {
-	case 0:
-		return decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_MX51_HCLK_FREQ);
-	case 1:
-		return decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_MX51_HCLK_FREQ);
-	default:
-		return 0;
-	}
-	/* NOTREACHED */
-}
-
-/*
- * Get the rate of ipg clock.
- */
-static u32 get_ipg_clk(void)
-{
-	u32 ahb_podf, ipg_podf;
-
-	ahb_podf = __raw_readl(&mxc_ccm->cbcdr);
-	ipg_podf = (ahb_podf & MXC_CCM_CBCDR_IPG_PODF_MASK) >>
-			MXC_CCM_CBCDR_IPG_PODF_OFFSET;
-	ahb_podf = (ahb_podf & MXC_CCM_CBCDR_AHB_PODF_MASK) >>
-			MXC_CCM_CBCDR_AHB_PODF_OFFSET;
-	return get_periph_clk() / ((ahb_podf + 1) * (ipg_podf + 1));
-}
-
-/*
- * Get the rate of ipg_per clock.
- */
-static u32 get_ipg_per_clk(void)
-{
-	u32 pred1, pred2, podf;
-
-	if (__raw_readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL)
-		return get_ipg_clk();
-	/* Fixme: not handle what about lpm*/
-	podf = __raw_readl(&mxc_ccm->cbcdr);
-	pred1 = (podf & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >>
-		MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET;
-	pred2 = (podf & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >>
-		MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET;
-	podf = (podf & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >>
-		MXC_CCM_CBCDR_PERCLK_PODF_OFFSET;
-
-	return get_periph_clk() / ((pred1 + 1) * (pred2 + 1) * (podf + 1));
-}
-
-/*
- * Get the rate of uart clk.
- */
-static u32 get_uart_clk(void)
-{
-	unsigned int freq, reg, pred, podf;
-
-	reg = __raw_readl(&mxc_ccm->cscmr1);
-	switch ((reg & MXC_CCM_CSCMR1_UART_CLK_SEL_MASK) >>
-		MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET) {
-	case 0x0:
-		freq = decode_pll(mxc_plls[PLL1_CLOCK],
-				    CONFIG_MX51_HCLK_FREQ);
-		break;
-	case 0x1:
-		freq = decode_pll(mxc_plls[PLL2_CLOCK],
-				    CONFIG_MX51_HCLK_FREQ);
-		break;
-	case 0x2:
-		freq = decode_pll(mxc_plls[PLL3_CLOCK],
-				    CONFIG_MX51_HCLK_FREQ);
-		break;
-	default:
-		return 66500000;
-	}
-
-	reg = __raw_readl(&mxc_ccm->cscdr1);
-
-	pred = (reg & MXC_CCM_CSCDR1_UART_CLK_PRED_MASK) >>
-		MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET;
-
-	podf = (reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >>
-		MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
-	freq /= (pred + 1) * (podf + 1);
-
-	return freq;
-}
-
-/*
- * This function returns the low power audio clock.
- */
-u32 get_lp_apm(void)
-{
-	u32 ret_val = 0;
-	u32 ccsr = __raw_readl(&mxc_ccm->ccsr);
-
-	if (((ccsr >> 9) & 1) == 0)
-		ret_val = CONFIG_MX51_HCLK_FREQ;
-	else
-		ret_val = ((32768 * 1024));
-
-	return ret_val;
-}
-
-/*
- * get cspi clock rate.
- */
-u32 imx_get_cspiclk(void)
-{
-	u32 ret_val = 0, pdf, pre_pdf, clk_sel;
-	u32 cscmr1 = __raw_readl(&mxc_ccm->cscmr1);
-	u32 cscdr2 = __raw_readl(&mxc_ccm->cscdr2);
-
-	pre_pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK) \
-			>> MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET;
-	pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK) \
-			>> MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET;
-	clk_sel = (cscmr1 & MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK) \
-			>> MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET;
-
-	switch (clk_sel) {
-	case 0:
-		ret_val = decode_pll(mxc_plls[PLL1_CLOCK],
-					CONFIG_MX51_HCLK_FREQ) /
-					((pre_pdf + 1) * (pdf + 1));
-		break;
-	case 1:
-		ret_val = decode_pll(mxc_plls[PLL2_CLOCK],
-					CONFIG_MX51_HCLK_FREQ) /
-					((pre_pdf + 1) * (pdf + 1));
-		break;
-	case 2:
-		ret_val = decode_pll(mxc_plls[PLL3_CLOCK],
-					CONFIG_MX51_HCLK_FREQ) /
-					((pre_pdf + 1) * (pdf + 1));
-		break;
-	default:
-		ret_val = get_lp_apm() / ((pre_pdf + 1) * (pdf + 1));
-		break;
-	}
-
-	return ret_val;
-}
-
-/*
- * The API of get mxc clockes.
- */
-unsigned int mxc_get_clock(enum mxc_clock clk)
-{
-	switch (clk) {
-	case MXC_ARM_CLK:
-		return get_mcu_main_clk();
-	case MXC_AHB_CLK:
-		break;
-	case MXC_IPG_CLK:
-		return get_ipg_clk();
-	case MXC_IPG_PERCLK:
-		return get_ipg_per_clk();
-	case MXC_UART_CLK:
-		return get_uart_clk();
-	case MXC_CSPI_CLK:
-		return imx_get_cspiclk();
-	case MXC_FEC_CLK:
-		return decode_pll(mxc_plls[PLL1_CLOCK],
-				    CONFIG_MX51_HCLK_FREQ);
-	default:
-		break;
-	}
-	return -1;
-}
-
-u32 imx_get_uartclk(void)
-{
-	return get_uart_clk();
-}
-
-
-u32 imx_get_fecclk(void)
-{
-	return mxc_get_clock(MXC_IPG_CLK);
-}
-
-/*
- * Dump some core clockes.
- */
-int do_mx51_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
-	u32 freq;
-
-	freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_MX51_HCLK_FREQ);
-	printf("mx51 pll1: %dMHz\n", freq / 1000000);
-	freq = decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_MX51_HCLK_FREQ);
-	printf("mx51 pll2: %dMHz\n", freq / 1000000);
-	freq = decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_MX51_HCLK_FREQ);
-	printf("mx51 pll3: %dMHz\n", freq / 1000000);
-	printf("ipg clock     : %dHz\n", mxc_get_clock(MXC_IPG_CLK));
-	printf("ipg per clock : %dHz\n", mxc_get_clock(MXC_IPG_PERCLK));
-
-	return 0;
-}
-
-/***************************************************/
-
-U_BOOT_CMD(
-	clockinfo,	CONFIG_SYS_MAXARGS,	1,	do_mx51_showclocks,
-	"display mx51 clocks\n",
-	""
-);
--- a/arch/arm/cpu/arm_cortexa8/mx51/iomux.c
+++ b/arch/arm/cpu/arm_cortexa8/mx51/iomux.c
@@ -1,166 +0,0 @@
-/*
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/mx51_pins.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/sys_proto.h>
-
-/* IOMUX register (base) addresses */
-enum iomux_reg_addr {
-	IOMUXGPR0 = IOMUXC_BASE_ADDR,
-	IOMUXGPR1 = IOMUXC_BASE_ADDR + 0x004,
-	IOMUXSW_MUX_CTL = IOMUXC_BASE_ADDR,
-	IOMUXSW_MUX_END = IOMUXC_BASE_ADDR + MUX_I_END,
-	IOMUXSW_PAD_CTL = IOMUXC_BASE_ADDR + PAD_I_START,
-	IOMUXSW_INPUT_CTL = IOMUXC_BASE_ADDR,
-};
-
-#define MUX_PIN_NUM_MAX (((MUX_I_END - MUX_I_START) >> 2) + 1)
-
-/* Get the iomux register address of this pin */
-static inline u32 get_mux_reg(iomux_pin_name_t pin)
-{
-	u32 mux_reg = PIN_TO_IOMUX_MUX(pin);
-
-	if (is_soc_rev(CHIP_REV_2_0) < 0) {
-		/*
-		 * Fixup register address:
-		 *	i.MX51 TO1 has offset with the register
-		 * 	which is define as TO2.
-		 */
-		if ((pin == MX51_PIN_NANDF_RB5) ||
-			(pin == MX51_PIN_NANDF_RB6) ||
-			(pin == MX51_PIN_NANDF_RB7))
-			; /* Do nothing */
-		else if (mux_reg >= 0x2FC)
-			mux_reg += 8;
-		else if (mux_reg >= 0x130)
-			mux_reg += 0xC;
-	}
-	mux_reg += IOMUXSW_MUX_CTL;
-	return mux_reg;
-}
-
-/* Get the pad register address of this pin */
-static inline u32 get_pad_reg(iomux_pin_name_t pin)
-{
-	u32 pad_reg = PIN_TO_IOMUX_PAD(pin);
-
-	if (is_soc_rev(CHIP_REV_2_0) < 0) {
-		/*
-		 * Fixup register address:
-		 *	i.MX51 TO1 has offset with the register
-		 * 	which is define as TO2.
-		 */
-		if ((pin == MX51_PIN_NANDF_RB5) ||
-			(pin == MX51_PIN_NANDF_RB6) ||
-			(pin == MX51_PIN_NANDF_RB7))
-			; /* Do nothing */
-		else if (pad_reg == 0x4D0 - PAD_I_START)
-			pad_reg += 0x4C;
-		else if (pad_reg == 0x860 - PAD_I_START)
-			pad_reg += 0x9C;
-		else if (pad_reg >= 0x804 - PAD_I_START)
-			pad_reg += 0xB0;
-		else if (pad_reg >= 0x7FC - PAD_I_START)
-			pad_reg += 0xB4;
-		else if (pad_reg >= 0x4E4 - PAD_I_START)
-			pad_reg += 0xCC;
-		else
-			pad_reg += 8;
-	}
-	pad_reg += IOMUXSW_PAD_CTL;
-	return pad_reg;
-}
-
-/* Get the last iomux register address */
-static inline u32 get_mux_end(void)
-{
-	if (is_soc_rev(CHIP_REV_2_0) < 0)
-		return IOMUXC_BASE_ADDR + (0x3F8 - 4);
-	else
-		return IOMUXC_BASE_ADDR + (0x3F0 - 4);
-}
-
-/*
- * This function is used to configure a pin through the IOMUX module.
- * @param  pin		a pin number as defined in iomux_pin_name_t
- * @param  cfg		an output function as defined in iomux_pin_cfg_t
- *
- * @return 		0 if successful; Non-zero otherwise
- */
-static void iomux_config_mux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
-{
-	u32 mux_reg = get_mux_reg(pin);
-
-	if ((mux_reg > get_mux_end()) || (mux_reg < IOMUXSW_MUX_CTL))
-		return ;
-	if (cfg == IOMUX_CONFIG_GPIO)
-		writel(PIN_TO_ALT_GPIO(pin), mux_reg);
-	else
-		writel(cfg, mux_reg);
-}
-
-/*
- * Request ownership for an IO pin. This function has to be the first one
- * being called before that pin is used. The caller has to check the
- * return value to make sure it returns 0.
- *
- * @param  pin		a name defined by iomux_pin_name_t
- * @param  cfg		an input function as defined in iomux_pin_cfg_t
- *
- */
-void mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
-{
-	iomux_config_mux(pin, cfg);
-}
-
-/*
- * Release ownership for an IO pin
- *
- * @param  pin		a name defined by iomux_pin_name_t
- * @param  cfg		an input function as defined in iomux_pin_cfg_t
- */
-void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
-{
-}
-
-/*
- * This function configures the pad value for a IOMUX pin.
- *
- * @param  pin     a pin number as defined in iomux_pin_name_t
- * @param  config  the ORed value of elements defined in iomux_pad_config_t
- */
-void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config)
-{
-	u32 pad_reg = get_pad_reg(pin);
-	writel(config, pad_reg);
-}
-
-unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin)
-{
-	u32 pad_reg = get_pad_reg(pin);
-	return readl(pad_reg);
-}
--- a/arch/arm/cpu/arm_cortexa8/mx51/lowlevel_init.S
+++ b/arch/arm/cpu/arm_cortexa8/mx51/lowlevel_init.S
@@ -1,291 +0,0 @@
-/*
- * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
- *
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/asm-offsets.h>
-
-/*
- * L2CC Cache setup/invalidation/disable
- */
-.macro init_l2cc
-	/* explicitly disable L2 cache */
-	mrc 15, 0, r0, c1, c0, 1
-	bic r0, r0, #0x2
-	mcr 15, 0, r0, c1, c0, 1
-
-	/* reconfigure L2 cache aux control reg */
-	mov r0, #0xC0			/* tag RAM */
-	add r0, r0, #0x4		/* data RAM */
-	orr r0, r0, #(1 << 24)		/* disable write allocate delay */
-	orr r0, r0, #(1 << 23)		/* disable write allocate combine */
-	orr r0, r0, #(1 << 22)		/* disable write allocate */
-
-	cmp r3, #0x10    /* r3 contains the silicon rev */
-
-	/* disable write combine for TO 2 and lower revs */
-	orrls r0, r0, #(1 << 25)
-
-	mcr 15, 1, r0, c9, c0, 2
-.endm /* init_l2cc */
-
-/* AIPS setup - Only setup MPROTx registers.
- * The PACR default values are good.*/
-.macro init_aips
-	/*
-	 * Set all MPROTx to be non-bufferable, trusted for R/W,
-	 * not forced to user-mode.
-	 */
-	ldr r0, =AIPS1_BASE_ADDR
-	ldr r1, =0x77777777
-	str r1, [r0, #0x0]
-	str r1, [r0, #0x4]
-	ldr r0, =AIPS2_BASE_ADDR
-	str r1, [r0, #0x0]
-	str r1, [r0, #0x4]
-	/*
-	 * Clear the on and off peripheral modules Supervisor Protect bit
-	 * for SDMA to access them. Did not change the AIPS control registers
-	 * (offset 0x20) access type
-	 */
-.endm /* init_aips */
-
-/* M4IF setup */
-.macro init_m4if
-	/* VPU and IPU given higher priority (0x4)
-	 * IPU accesses with ID=0x1 given highest priority (=0xA)
-	 */
-	ldr r0, =M4IF_BASE_ADDR
-
-	ldr r1, =0x00000203
-	str r1, [r0, #0x40]
-
-	ldr r1, =0x0
-	str r1, [r0, #0x44]
-
-	ldr r1, =0x00120125
-	str r1, [r0, #0x9C]
-
-	ldr r1, =0x001901A3
-	str r1, [r0, #0x48]
-
-.endm /* init_m4if */
-
-.macro setup_pll pll, freq
-	ldr r2, =\pll
-	ldr r1, =0x00001232
-	str r1, [r2, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
-	mov r1, #0x2
-	str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
-
-	str r3, [r2, #PLL_DP_OP]
-	str r3, [r2, #PLL_DP_HFS_OP]
-
-	str r4, [r2, #PLL_DP_MFD]
-	str r4, [r2, #PLL_DP_HFS_MFD]
-
-	str r5, [r2, #PLL_DP_MFN]
-	str r5, [r2, #PLL_DP_HFS_MFN]
-
-	ldr r1, =0x00001232
-	str r1, [r2, #PLL_DP_CTL]
-1:	ldr r1, [r2, #PLL_DP_CTL]
-	ands r1, r1, #0x1
-	beq 1b
-.endm
-
-.macro init_clock
-	ldr r0, =CCM_BASE_ADDR
-
-	/* Gate of clocks to the peripherals first */
-	ldr r1, =0x3FFFFFFF
-	str r1, [r0, #CLKCTL_CCGR0]
-	ldr r1, =0x0
-	str r1, [r0, #CLKCTL_CCGR1]
-	str r1, [r0, #CLKCTL_CCGR2]
-	str r1, [r0, #CLKCTL_CCGR3]
-
-	ldr r1, =0x00030000
-	str r1, [r0, #CLKCTL_CCGR4]
-	ldr r1, =0x00FFF030
-	str r1, [r0, #CLKCTL_CCGR5]
-	ldr r1, =0x00000300
-	str r1, [r0, #CLKCTL_CCGR6]
-
-	/* Disable IPU and HSC dividers */
-	mov r1, #0x60000
-	str r1, [r0, #CLKCTL_CCDR]
-
-	/* Make sure to switch the DDR away from PLL 1 */
-	ldr r1, =0x19239145
-	str r1, [r0, #CLKCTL_CBCDR]
-	/* make sure divider effective */
-1:	ldr r1, [r0, #CLKCTL_CDHIPR]
-	cmp r1, #0x0
-	bne 1b
-
-	/* Switch ARM to step clock */
-	mov r1, #0x4
-	str r1, [r0, #CLKCTL_CCSR]
-	mov r3, #DP_OP_800
-	mov r4, #DP_MFD_800
-	mov r5, #DP_MFN_800
-	setup_pll PLL1_BASE_ADDR
-
-	mov r3, #DP_OP_665
-	mov r4, #DP_MFD_665
-	mov r5, #DP_MFN_665
-	setup_pll PLL3_BASE_ADDR
-
-	/* Switch peripheral to PLL 3 */
-	ldr r0, =CCM_BASE_ADDR
-	ldr r1, =0x000010C0
-	orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
-	str r1, [r0, #CLKCTL_CBCMR]
-	ldr r1, =0x13239145
-	str r1, [r0, #CLKCTL_CBCDR]
-	mov r3, #DP_OP_665
-	mov r4, #DP_MFD_665
-	mov r5, #DP_MFN_665
-	setup_pll PLL2_BASE_ADDR
-
-	/* Switch peripheral to PLL2 */
-	ldr r0, =CCM_BASE_ADDR
-	ldr r1, =0x19239145
-	str r1, [r0, #CLKCTL_CBCDR]
-	ldr r1, =0x000020C0
-	orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
-	str r1, [r0, #CLKCTL_CBCMR]
-
-	mov r3, #DP_OP_216
-	mov r4, #DP_MFD_216
-	mov r5, #DP_MFN_216
-	setup_pll PLL3_BASE_ADDR
-
-
-	/* Set the platform clock dividers */
-	ldr r0, =ARM_BASE_ADDR
-	ldr r1, =0x00000725
-	str r1, [r0, #0x14]
-
-	ldr r0, =CCM_BASE_ADDR
-
-	/* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */
-	ldr r1, =0x0
-	ldr r3, [r1, #ROM_SI_REV]
-	cmp r3, #0x10
-	movls r1, #0x1
-	movhi r1, #0
-	str r1, [r0, #CLKCTL_CACRR]
-
-	/* Switch ARM back to PLL 1 */
-	mov r1, #0
-	str r1, [r0, #CLKCTL_CCSR]
-
-	/* setup the rest */
-	/* Use lp_apm (24MHz) source for perclk */
-	ldr r1, =0x000020C2
-	orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
-	str r1, [r0, #CLKCTL_CBCMR]
-	/* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
-	ldr r1, =CONFIG_SYS_CLKTL_CBCDR
-	str r1, [r0, #CLKCTL_CBCDR]
-
-	/* Restore the default values in the Gate registers */
-	ldr r1, =0xFFFFFFFF
-	str r1, [r0, #CLKCTL_CCGR0]
-	str r1, [r0, #CLKCTL_CCGR1]
-	str r1, [r0, #CLKCTL_CCGR2]
-	str r1, [r0, #CLKCTL_CCGR3]
-	str r1, [r0, #CLKCTL_CCGR4]
-	str r1, [r0, #CLKCTL_CCGR5]
-	str r1, [r0, #CLKCTL_CCGR6]
-
-	/* Use PLL 2 for UART's, get 66.5MHz from it */
-	ldr r1, =0xA5A2A020
-	str r1, [r0, #CLKCTL_CSCMR1]
-	ldr r1, =0x00C30321
-	str r1, [r0, #CLKCTL_CSCDR1]
-
-	/* make sure divider effective */
-1:	ldr r1, [r0, #CLKCTL_CDHIPR]
-	cmp r1, #0x0
-	bne 1b
-
-	mov r1, #0x0
-	str r1, [r0, #CLKCTL_CCDR]
-
-	/* for cko - for ARM div by 8 */
-	mov r1, #0x000A0000
-	add r1, r1, #0x00000F0
-	str r1, [r0, #CLKCTL_CCOSR]
-.endm
-
-.macro setup_wdog
-	ldr r0, =WDOG1_BASE_ADDR
-	mov r1, #0x30
-	strh r1, [r0]
-.endm
-
-.section ".text.init", "x"
-
-.globl lowlevel_init
-lowlevel_init:
-	ldr r0, =GPIO1_BASE_ADDR
-	ldr r1, [r0, #0x0]
-	orr r1, r1, #(1 << 23)
-	str r1, [r0, #0x0]
-	ldr r1, [r0, #0x4]
-	orr r1, r1, #(1 << 23)
-	str r1, [r0, #0x4]
-
-#ifdef ENABLE_IMPRECISE_ABORT
-	mrs r1, spsr		/* save old spsr */
-	mrs r0, cpsr		/* read out the cpsr */
-	bic r0, r0, #0x100	/* clear the A bit */
-	msr spsr, r0		/* update spsr */
-	add lr, pc, #0x8	/* update lr */
-	movs pc, lr		/* update cpsr */
-	nop
-	nop
-	nop
-	nop
-	msr spsr, r1		/* restore old spsr */
-#endif
-
-	init_l2cc
-
-	init_aips
-
-	init_m4if
-
-	init_clock
-
-	/* r12 saved upper lr*/
-	mov pc,lr
-
-/* Board level setting value */
-DDR_PERCHARGE_CMD:	.word 0x04008008
-DDR_REFRESH_CMD:	.word 0x00008010
-DDR_LMR1_W:		.word 0x00338018
-DDR_LMR_CMD:		.word 0xB2220000
-DDR_TIMING_W:		.word 0xB02567A9
-DDR_MISC_W:		.word 0x000A0104
--- a/arch/arm/cpu/arm_cortexa8/mx51/soc.c
+++ b/arch/arm/cpu/arm_cortexa8/mx51/soc.c
@@ -1,114 +0,0 @@
-/*
- * (C) Copyright 2007
- * Sascha Hauer, Pengutronix
- *
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/clock.h>
-#include <asm/errno.h>
-#include <asm/io.h>
-
-#ifdef CONFIG_FSL_ESDHC
-#include <fsl_esdhc.h>
-#endif
-
-u32 get_cpu_rev(void)
-{
-	int reg;
-	int system_rev;
-
-	reg = __raw_readl(ROM_SI_REV);
-	switch (reg) {
-	case 0x02:
-		system_rev = 0x51000 | CHIP_REV_1_1;
-		break;
-	case 0x10:
-		if ((__raw_readl(GPIO1_BASE_ADDR + 0x0) & (0x1 << 22)) == 0)
-			system_rev = 0x51000 | CHIP_REV_2_5;
-		else
-			system_rev = 0x51000 | CHIP_REV_2_0;
-		break;
-	case 0x20:
-		system_rev = 0x51000 | CHIP_REV_3_0;
-		break;
-	return system_rev;
-	default:
-		system_rev = 0x51000 | CHIP_REV_1_0;
-		break;
-	}
-	return system_rev;
-}
-
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo(void)
-{
-	u32 cpurev;
-
-	cpurev = get_cpu_rev();
-	printf("CPU:   Freescale i.MX51 family rev%d.%d at %d MHz\n",
-		(cpurev & 0xF0) >> 4,
-		(cpurev & 0x0F) >> 4,
-		mxc_get_clock(MXC_ARM_CLK) / 1000000);
-	return 0;
-}
-#endif
-
-/*
- * Initializes on-chip ethernet controllers.
- * to override, implement board_eth_init()
- */
-#if defined(CONFIG_FEC_MXC)
-extern int fecmxc_initialize(bd_t *bis);
-#endif
-
-int cpu_eth_init(bd_t *bis)
-{
-	int rc = -ENODEV;
-
-#if defined(CONFIG_FEC_MXC)
-	rc = fecmxc_initialize(bis);
-#endif
-
-	return rc;
-}
-
-/*
- * Initializes on-chip MMC controllers.
- * to override, implement board_mmc_init()
- */
-int cpu_mmc_init(bd_t *bis)
-{
-#ifdef CONFIG_FSL_ESDHC
-	return fsl_esdhc_mmc_init(bis);
-#else
-	return 0;
-#endif
-}
-
-
-void reset_cpu(ulong addr)
-{
-	__raw_writew(4, WDOG1_BASE_ADDR);
-}
--- a/arch/arm/cpu/arm_cortexa8/mx51/timer.c
+++ b/arch/arm/cpu/arm_cortexa8/mx51/timer.c
@@ -1,119 +0,0 @@
-/*
- * (C) Copyright 2007
- * Sascha Hauer, Pengutronix
- *
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-
-/* General purpose timers registers */
-struct mxc_gpt {
-	unsigned int control;
-	unsigned int prescaler;
-	unsigned int status;
-	unsigned int nouse[6];
-	unsigned int counter;
-};
-
-static struct mxc_gpt *cur_gpt = (struct mxc_gpt *)GPT1_BASE_ADDR;
-
-/* General purpose timers bitfields */
-#define GPTCR_SWR       (1<<15)	/* Software reset */
-#define GPTCR_FRR       (1<<9)	/* Freerun / restart */
-#define GPTCR_CLKSOURCE_32 (4<<6)	/* Clock source */
-#define GPTCR_TEN       (1)	/* Timer enable */
-
-static ulong timestamp;
-static ulong lastinc;
-
-int timer_init(void)
-{
-	int i;
-
-	/* setup GP Timer 1 */
-	__raw_writel(GPTCR_SWR, &cur_gpt->control);
-
-	/* We have no udelay by now */
-	for (i = 0; i < 100; i++)
-		__raw_writel(0, &cur_gpt->control);
-
-	__raw_writel(0, &cur_gpt->prescaler); /* 32Khz */
-
-	/* Freerun Mode, PERCLK1 input */
-	i = __raw_readl(&cur_gpt->control);
-	__raw_writel(i | GPTCR_CLKSOURCE_32 | GPTCR_TEN, &cur_gpt->control);
-	reset_timer_masked();
-	return 0;
-}
-
-void reset_timer(void)
-{
-	reset_timer_masked();
-}
-
-void reset_timer_masked(void)
-{
-	ulong val = __raw_readl(&cur_gpt->counter);
-	lastinc = val / (CONFIG_MX51_CLK32 / CONFIG_SYS_HZ);
-	timestamp = 0;
-}
-
-ulong get_timer_masked(void)
-{
-	ulong val = __raw_readl(&cur_gpt->counter);
-	val /= (CONFIG_MX51_CLK32 / CONFIG_SYS_HZ);
-	if (val >= lastinc)
-		timestamp += (val - lastinc);
-	else
-		timestamp += ((0xFFFFFFFF / (CONFIG_MX51_CLK32 / CONFIG_SYS_HZ))
-				- lastinc) + val;
-	lastinc = val;
-	return val;
-}
-
-ulong get_timer(ulong base)
-{
-	return get_timer_masked() - base;
-}
-
-void set_timer(ulong t)
-{
-	timestamp = t;
-}
-
-/* delay x useconds AND preserve advance timestamp value */
-void __udelay(unsigned long usec)
-{
-	unsigned long now, start, tmo;
-	tmo = usec * (CONFIG_MX51_CLK32 / 1000) / 1000;
-
-	if (!tmo)
-		tmo = 1;
-
-	now = start = readl(&cur_gpt->counter);
-
-	while ((now - start) < tmo)
-		now = readl(&cur_gpt->counter);
-
-}
--- a/arch/arm/cpu/arm_cortexa8/mx51/u-boot.lds
+++ b/arch/arm/cpu/arm_cortexa8/mx51/u-boot.lds
@@ -1,61 +0,0 @@
-/*
- * January 2004 - Changed to support H4 device
- * Copyright (c) 2004 Texas Instruments
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN(4);
-	.text	   :
-	{
-	  arch/arm/cpu/arm_cortexa8/start.o
-	  *(.text)
-	}
-
-	. = ALIGN(4);
-	.rodata : { *(.rodata) }
-
-	. = ALIGN(4);
-	.data : { *(.data) }
-
-	. = ALIGN(4);
-	.got : { *(.got) }
-
-	. = .;
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
-	__u_boot_cmd_end = .;
-
-	. = ALIGN(4);
-	__bss_start = .;
-	.bss : { *(.bss) }
-	_end = .;
-}
--- a/arch/arm/cpu/arm_cortexa8/omap3/emif4.c
+++ b/arch/arm/cpu/arm_cortexa8/omap3/emif4.c
@@ -1,168 +0,0 @@
-/*
- * Author :
- *     Vaibhav Hiremath <hvaibhav@ti.com>
- *
- * Based on mem.c and sdrc.c
- *
- * Copyright (C) 2010
- * Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/emif4.h>
-
-extern omap3_sysinfo sysinfo;
-
-static emif4_t *emif4_base = (emif4_t *)OMAP34XX_SDRC_BASE;
-
-/*
- * is_mem_sdr -
- *  - Return 1 if mem type in use is SDR
- */
-u32 is_mem_sdr(void)
-{
-	return 0;
-}
-
-/*
- * get_sdr_cs_size -
- *  - Get size of chip select 0/1
- */
-u32 get_sdr_cs_size(u32 cs)
-{
-	u32 size;
-
-	/* TODO: Calculate the size based on EMIF4 configuration */
-	size = CONFIG_SYS_CS0_SIZE;
-
-	return size;
-}
-
-/*
- * get_sdr_cs_offset -
- *  - Get offset of cs from cs0 start
- */
-u32 get_sdr_cs_offset(u32 cs)
-{
-	u32 offset = 0;
-
-	return offset;
-}
-
-/*
- * do_emif4_init -
- *  - Init the emif4 module for DDR access
- *  - Early init routines, called from flash or SRAM.
- */
-void do_emif4_init(void)
-{
-	unsigned int regval;
-	/* Set the DDR PHY parameters in PHY ctrl registers */
-	regval = (EMIF4_DDR1_READ_LAT | EMIF4_DDR1_PWRDN_DIS |
-		EMIF4_DDR1_EXT_STRB_DIS);
-	writel(regval, &emif4_base->ddr_phyctrl1);
-	writel(regval, &emif4_base->ddr_phyctrl1_shdw);
-	writel(0, &emif4_base->ddr_phyctrl2);
-
-	/* Reset the DDR PHY and wait till completed */
-	regval = readl(&emif4_base->sdram_iodft_tlgc);
-	regval |= (1<<10);
-	writel(regval, &emif4_base->sdram_iodft_tlgc);
-	/*Wait till that bit clears*/
-	while ((readl(&emif4_base->sdram_iodft_tlgc) & (1<<10)) == 0x1);
-	/*Re-verify the DDR PHY status*/
-	while ((readl(&emif4_base->sdram_sts) & (1<<2)) == 0x0);
-
-	regval |= (1<<0);
-	writel(regval, &emif4_base->sdram_iodft_tlgc);
-	/* Set SDR timing registers */
-	regval = (EMIF4_TIM1_T_WTR | EMIF4_TIM1_T_RRD |
-		EMIF4_TIM1_T_RC | EMIF4_TIM1_T_RAS |
-		EMIF4_TIM1_T_WR | EMIF4_TIM1_T_RCD |
-		EMIF4_TIM1_T_RP);
-	writel(regval, &emif4_base->sdram_time1);
-	writel(regval, &emif4_base->sdram_time1_shdw);
-
-	regval = (EMIF4_TIM2_T_CKE | EMIF4_TIM2_T_RTP |
-		EMIF4_TIM2_T_XSRD | EMIF4_TIM2_T_XSNR |
-		EMIF4_TIM2_T_ODT | EMIF4_TIM2_T_XP);
-	writel(regval, &emif4_base->sdram_time2);
-	writel(regval, &emif4_base->sdram_time2_shdw);
-
-	regval = (EMIF4_TIM3_T_RAS_MAX | EMIF4_TIM3_T_RFC);
-	writel(regval, &emif4_base->sdram_time3);
-	writel(regval, &emif4_base->sdram_time3_shdw);
-
-	/* Set the PWR control register */
-	regval = (EMIF4_PWR_PM_TIM | EMIF4_PWR_LP_MODE |
-		EMIF4_PWR_DPD_DIS | EMIF4_PWR_IDLE_MODE);
-	writel(regval, &emif4_base->sdram_pwr_mgmt);
-	writel(regval, &emif4_base->sdram_pwr_mgmt_shdw);
-
-	/* Set the DDR refresh rate control register */
-	regval = (EMIF4_REFRESH_RATE | EMIF4_INITREF_DIS);
-	writel(regval, &emif4_base->sdram_refresh_ctrl);
-	writel(regval, &emif4_base->sdram_refresh_ctrl_shdw);
-
-	/* set the SDRAM configuration register */
-	regval = (EMIF4_CFG_PGSIZE | EMIF4_CFG_EBANK |
-		EMIF4_CFG_IBANK | EMIF4_CFG_ROWSIZE |
-		EMIF4_CFG_CL | EMIF4_CFG_NARROW_MD |
-		EMIF4_CFG_SDR_DRV | EMIF4_CFG_DDR_DIS_DLL |
-		EMIF4_CFG_DDR2_DDQS | EMIF4_CFG_DDR_TERM |
-		EMIF4_CFG_IBANK_POS | EMIF4_CFG_SDRAM_TYP);
-	writel(regval, &emif4_base->sdram_config);
-}
-
-/*
- * dram_init -
- *  - Sets uboots idea of sdram size
- */
-int dram_init(void)
-{
-	DECLARE_GLOBAL_DATA_PTR;
-	unsigned int size0 = 0, size1 = 0;
-
-	size0 = get_sdr_cs_size(CS0);
-	/*
-	 * If a second bank of DDR is attached to CS1 this is
-	 * where it can be started.  Early init code will init
-	 * memory on CS0.
-	 */
-	if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED))
-		size1 = get_sdr_cs_size(CS1);
-
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = size0;
-	gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
-	gd->bd->bi_dram[1].size = size1;
-
-	return 0;
-}
-
-/*
- * mem_init() -
- *  - Initialize memory subsystem
- */
-void mem_init(void)
-{
-	do_emif4_init();
-}
--- a/arch/arm/cpu/arm_cortexa8/omap3/sdrc.c
+++ b/arch/arm/cpu/arm_cortexa8/omap3/sdrc.c
@@ -1,202 +0,0 @@
-/*
- * Functions related to OMAP3 SDRC.
- *
- * This file has been created after exctracting and consolidating
- * the SDRC related content from mem.c and board.c, also created
- * generic init function (mem_init).
- *
- * Copyright (C) 2004-2010
- * Texas Instruments Incorporated - http://www.ti.com/
- *
- * Author :
- *     Vaibhav Hiremath <hvaibhav@ti.com>
- *
- * Original implementation by (mem.c, board.c) :
- *      Sunil Kumar <sunilsaini05@gmail.com>
- *      Shashi Ranjan <shashiranjanmca05@gmail.com>
- *      Manikandan Pillai <mani.pillai@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/sys_proto.h>
-
-extern omap3_sysinfo sysinfo;
-
-static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE;
-
-/*
- * is_mem_sdr -
- *  - Return 1 if mem type in use is SDR
- */
-u32 is_mem_sdr(void)
-{
-	if (readl(&sdrc_base->cs[CS0].mr) == SDRC_MR_0_SDR)
-		return 1;
-	return 0;
-}
-
-/*
- * make_cs1_contiguous -
- *  - For es2 and above remap cs1 behind cs0 to allow command line
- *    mem=xyz use all memory with out discontinuous support compiled in.
- *    Could do it at the ATAG, but there really is two banks...
- *  - Called as part of 2nd phase DDR init.
- */
-void make_cs1_contiguous(void)
-{
-	u32 size, a_add_low, a_add_high;
-
-	size = get_sdr_cs_size(CS0);
-	size >>= 25;	/* divide by 32 MiB to find size to offset CS1 */
-	a_add_high = (size & 3) << 8;	/* set up low field */
-	a_add_low = (size & 0x3C) >> 2;	/* set up high field */
-	writel((a_add_high | a_add_low), &sdrc_base->cs_cfg);
-
-}
-
-
-/*
- * get_sdr_cs_size -
- *  - Get size of chip select 0/1
- */
-u32 get_sdr_cs_size(u32 cs)
-{
-	u32 size;
-
-	/* get ram size field */
-	size = readl(&sdrc_base->cs[cs].mcfg) >> 8;
-	size &= 0x3FF;		/* remove unwanted bits */
-	size <<= 21;		/* multiply by 2 MiB to find size in MB */
-	return size;
-}
-
-/*
- * get_sdr_cs_offset -
- *  - Get offset of cs from cs0 start
- */
-u32 get_sdr_cs_offset(u32 cs)
-{
-	u32 offset;
-
-	if (!cs)
-		return 0;
-
-	offset = readl(&sdrc_base->cs_cfg);
-	offset = (offset & 15) << 27 | (offset & 0x30) >> 17;
-
-	return offset;
-}
-
-/*
- * do_sdrc_init -
- *  - Initialize the SDRAM for use.
- *  - Sets up SDRC timings for CS0
- *  - code called once in C-Stack only context for CS0 and a possible 2nd
- *    time depending on memory configuration from stack+global context
- */
-void do_sdrc_init(u32 cs, u32 early)
-{
-	struct sdrc_actim *sdrc_actim_base;
-
-	if (cs)
-		sdrc_actim_base = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
-	else
-		sdrc_actim_base = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
-
-	if (early) {
-		/* reset sdrc controller */
-		writel(SOFTRESET, &sdrc_base->sysconfig);
-		wait_on_value(RESETDONE, RESETDONE, &sdrc_base->status,
-				12000000);
-		writel(0, &sdrc_base->sysconfig);
-
-		/* setup sdrc to ball mux */
-		writel(SDRC_SHARING, &sdrc_base->sharing);
-
-		/* Disable Power Down of CKE cuz of 1 CKE on combo part */
-		writel(WAKEUPPROC | SRFRONRESET | PAGEPOLICY_HIGH,
-				&sdrc_base->power);
-
-		writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl);
-		sdelay(0x20000);
-	}
-
-	writel(RASWIDTH_13BITS | CASWIDTH_10BITS | ADDRMUXLEGACY |
-			RAMSIZE_128 | BANKALLOCATION | B32NOT16 | B32NOT16 |
-			DEEPPD | DDR_SDRAM, &sdrc_base->cs[cs].mcfg);
-	writel(ARCV | ARE_ARCV_1, &sdrc_base->cs[cs].rfr_ctrl);
-	writel(V_ACTIMA_165, &sdrc_actim_base->ctrla);
-	writel(V_ACTIMB_165, &sdrc_actim_base->ctrlb);
-
-	writel(CMD_NOP, &sdrc_base->cs[cs].manual);
-	writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual);
-	writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
-	writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
-
-	/*
-	 * CAS latency 3, Write Burst = Read Burst, Serial Mode,
-	 * Burst length = 4
-	 */
-	writel(CASL3 | BURSTLENGTH4, &sdrc_base->cs[cs].mr);
-
-	if (!mem_ok(cs))
-		writel(0, &sdrc_base->cs[cs].mcfg);
-}
-
-/*
- * dram_init -
- *  - Sets uboots idea of sdram size
- */
-int dram_init(void)
-{
-	DECLARE_GLOBAL_DATA_PTR;
-	unsigned int size0 = 0, size1 = 0;
-
-	size0 = get_sdr_cs_size(CS0);
-	/*
-	 * If a second bank of DDR is attached to CS1 this is
-	 * where it can be started.  Early init code will init
-	 * memory on CS0.
-	 */
-	if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED)) {
-		do_sdrc_init(CS1, NOT_EARLY);
-		make_cs1_contiguous();
-
-		size1 = get_sdr_cs_size(CS1);
-	}
-
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = size0;
-	gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
-	gd->bd->bi_dram[1].size = size1;
-
-	return 0;
-}
-
-/*
- * mem_init -
- *  - Init the sdrc chip,
- *  - Selects CS0 and CS1,
- */
-void mem_init(void)
-{
-	/* only init up first bank here */
-	do_sdrc_init(CS0, EARLY_INIT);
-}
--- a/arch/arm/cpu/arm_cortexa8/s5pc1xx/cache.S
+++ b/arch/arm/cpu/arm_cortexa8/s5pc1xx/cache.S
@@ -1,120 +0,0 @@
-/*
- * Copyright (C) 2009 Samsung Electronics
- * Minkyu Kang <mk7.kang@samsung.com>
- *
- * based on arch/arm/cpu/arm_cortexa8/omap3/cache.S
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <asm/arch/cpu.h>
-
-.align 5
-.global invalidate_dcache
-.global l2_cache_enable
-.global l2_cache_disable
-
-/*
- * invalidate_dcache()
- * Invalidate the whole D-cache.
- *
- * Corrupted registers: r0-r5, r7, r9-r11
- */
-invalidate_dcache:
-	stmfd	r13!, {r0 - r5, r7, r9 - r12, r14}
-
-	cmp	r0, #0xC100			@ check if the cpu is s5pc100
-
-	beq	finished_inval			@ s5pc100 doesn't need this
-						@ routine
-	mrc	p15, 1, r0, c0, c0, 1		@ read clidr
-	ands	r3, r0, #0x7000000		@ extract loc from clidr
-	mov	r3, r3, lsr #23			@ left align loc bit field
-	beq	finished_inval			@ if loc is 0, then no need to
-						@ clean
-	mov	r10, #0				@ start clean at cache level 0
-inval_loop1:
-	add	r2, r10, r10, lsr #1		@ work out 3x current cache
-						@ level
-	mov	r1, r0, lsr r2			@ extract cache type bits from
-						@ clidr
-	and	r1, r1, #7			@ mask of the bits for current
-						@ cache only
-	cmp	r1, #2				@ see what cache we have at
-						@ this level
-	blt	skip_inval			@ skip if no cache, or just
-						@ i-cache
-	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level
-						@ in cssr
-	mov	r2, #0				@ operand for mcr SBZ
-	mcr	p15, 0, r2, c7, c5, 4		@ flush prefetch buffer to
-						@ sych the new cssr&csidr,
-						@ with armv7 this is 'isb',
-						@ but we compile with armv5
-	mrc	p15, 1, r1, c0, c0, 0		@ read the new csidr
-	and	r2, r1, #7			@ extract the length of the
-						@ cache lines
-	add	r2, r2, #4			@ add 4 (line length offset)
-	ldr	r4, =0x3ff
-	ands	r4, r4, r1, lsr #3		@ find maximum number on the
-						@ way size
-	clz	r5, r4				@ find bit position of way
-						@ size increment
-	ldr	r7, =0x7fff
-	ands	r7, r7, r1, lsr #13		@ extract max number of the
-						@ index size
-inval_loop2:
-	mov	r9, r4				@ create working copy of max
-						@ way size
-inval_loop3:
-	orr	r11, r10, r9, lsl r5		@ factor way and cache number
-						@ into r11
-	orr	r11, r11, r7, lsl r2		@ factor index number into r11
-	mcr	p15, 0, r11, c7, c6, 2		@ invalidate by set/way
-	subs	r9, r9, #1			@ decrement the way
-	bge	inval_loop3
-	subs	r7, r7, #1			@ decrement the index
-	bge	inval_loop2
-skip_inval:
-	add	r10, r10, #2			@ increment cache number
-	cmp	r3, r10
-	bgt	inval_loop1
-finished_inval:
-	mov	r10, #0				@ swith back to cache level 0
-	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level
-						@ in cssr
-	mcr	p15, 0, r10, c7, c5, 4		@ flush prefetch buffer,
-						@ with armv7 this is 'isb',
-						@ but we compile with armv5
-
-	ldmfd	r13!, {r0 - r5, r7, r9 - r12, pc}
-
-l2_cache_enable:
-	push	{r0, r1, r2, lr}
-	mrc	15, 0, r3, cr1, cr0, 1
-	orr	r3, r3, #2
-	mcr	15, 0, r3, cr1, cr0, 1
-	pop	{r1, r2, r3, pc}
-
-l2_cache_disable:
-	push	{r0, r1, r2, lr}
-	mrc	15, 0, r3, cr1, cr0, 1
-	bic	r3, r3, #2
-	mcr	15, 0, r3, cr1, cr0, 1
-	pop	{r1, r2, r3, pc}
--- a/arch/arm/cpu/arm_cortexa8/s5pc1xx/sromc.c
+++ b/arch/arm/cpu/arm_cortexa8/s5pc1xx/sromc.c
@@ -1,53 +0,0 @@
-/*
- * Copyright (C) 2010 Samsung Electronics
- * Naveen Krishna Ch <ch.naveen@samsung.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/smc.h>
-
-/*
- * s5pc1xx_config_sromc() - select the proper SROMC Bank and configure the
- * 		    band width control and bank control registers
- * srom_bank	- SROM Bank 0 to 5
- * smc_bw_conf  - SMC Band witdh reg configuration value
- * smc_bc_conf  - SMC Bank Control reg configuration value
- */
-void s5pc1xx_config_sromc(u32 srom_bank, u32 smc_bw_conf, u32 smc_bc_conf)
-{
-	u32 tmp;
-	struct s5pc1xx_smc *srom;
-
-	if (cpu_is_s5pc100())
-		srom = (struct s5pc1xx_smc *)S5PC100_SROMC_BASE;
-	else
-		srom = (struct s5pc1xx_smc *)S5PC110_SROMC_BASE;
-
-	/* Configure SMC_BW register to handle proper SROMC bank */
-	tmp = srom->bw;
-	tmp &= ~(0xF << (srom_bank * 4));
-	tmp |= smc_bw_conf;
-	srom->bw = tmp;
-
-	/* Configure SMC_BC register */
-	srom->bc[srom_bank] = smc_bc_conf;
-}
--- a/arch/arm/include/asm/arch-a320/a320.h
+++ b/arch/arm/include/asm/arch-a320/a320.h
@@ -1,34 +0,0 @@
-/*
- * (C) Copyright 2009 Faraday Technology
- * Po-Yu Chuang <ratbert@faraday-tech.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef __A320_H
-#define __A320_H
-
-/*
- * Hardware register bases
- */
-#define CONFIG_FTSMC020_BASE	0x90200000	/* Static Memory Controller */
-#define CONFIG_DEBUG_LED	0x902ffffc	/* Debug LED */
-#define CONFIG_FTSDMC020_BASE	0x90300000	/* SDRAM Controller */
-#define CONFIG_FTMAC100_BASE	0x90900000	/* Ethernet */
-#define CONFIG_FTPMU010_BASE	0x98100000	/* Power Management Unit */
-#define CONFIG_FTTMR010_BASE	0x98400000	/* Timer */
-#define CONFIG_FTRTC010_BASE	0x98600000	/* Real Time Clock*/
-
-#endif	/* __A320_H */
--- a/arch/arm/include/asm/arch-a320/ftpmu010.h
+++ b/arch/arm/include/asm/arch-a320/ftpmu010.h
@@ -1,146 +0,0 @@
-/*
- * (C) Copyright 2009 Faraday Technology
- * Po-Yu Chuang <ratbert@faraday-tech.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-/*
- * Power Management Unit
- */
-#ifndef __FTPMU010_H
-#define __FTPMU010_H
-
-struct ftpmu010 {
-	unsigned int	IDNMBR0;	/* 0x00 */
-	unsigned int	reserved0;	/* 0x04 */
-	unsigned int	OSCC;		/* 0x08 */
-	unsigned int	PMODE;		/* 0x0C */
-	unsigned int	PMCR;		/* 0x10 */
-	unsigned int	PED;		/* 0x14 */
-	unsigned int	PEDSR;		/* 0x18 */
-	unsigned int	reserved1;	/* 0x1C */
-	unsigned int	PMSR;		/* 0x20 */
-	unsigned int	PGSR;		/* 0x24 */
-	unsigned int	MFPSR;		/* 0x28 */
-	unsigned int	MISC;		/* 0x2C */
-	unsigned int	PDLLCR0;	/* 0x30 */
-	unsigned int	PDLLCR1;	/* 0x34 */
-	unsigned int	AHBMCLKOFF;	/* 0x38 */
-	unsigned int	APBMCLKOFF;	/* 0x3C */
-	unsigned int	DCSRCR0;	/* 0x40 */
-	unsigned int	DCSRCR1;	/* 0x44 */
-	unsigned int	DCSRCR2;	/* 0x48 */
-	unsigned int	SDRAMHTC;	/* 0x4C */
-	unsigned int	PSPR0;		/* 0x50 */
-	unsigned int	PSPR1;		/* 0x54 */
-	unsigned int	PSPR2;		/* 0x58 */
-	unsigned int	PSPR3;		/* 0x5C */
-	unsigned int	PSPR4;		/* 0x60 */
-	unsigned int	PSPR5;		/* 0x64 */
-	unsigned int	PSPR6;		/* 0x68 */
-	unsigned int	PSPR7;		/* 0x6C */
-	unsigned int	PSPR8;		/* 0x70 */
-	unsigned int	PSPR9;		/* 0x74 */
-	unsigned int	PSPR10;		/* 0x78 */
-	unsigned int	PSPR11;		/* 0x7C */
-	unsigned int	PSPR12;		/* 0x80 */
-	unsigned int	PSPR13;		/* 0x84 */
-	unsigned int	PSPR14;		/* 0x88 */
-	unsigned int	PSPR15;		/* 0x8C */
-	unsigned int	AHBDMA_RACCS;	/* 0x90 */
-	unsigned int	reserved2;	/* 0x94 */
-	unsigned int	reserved3;	/* 0x98 */
-	unsigned int	JSS;		/* 0x9C */
-	unsigned int	CFC_RACC;	/* 0xA0 */
-	unsigned int	SSP1_RACC;	/* 0xA4 */
-	unsigned int	UART1TX_RACC;	/* 0xA8 */
-	unsigned int	UART1RX_RACC;	/* 0xAC */
-	unsigned int	UART2TX_RACC;	/* 0xB0 */
-	unsigned int	UART2RX_RACC;	/* 0xB4 */
-	unsigned int	SDC_RACC;	/* 0xB8 */
-	unsigned int	I2SAC97_RACC;	/* 0xBC */
-	unsigned int	IRDATX_RACC;	/* 0xC0 */
-	unsigned int	reserved4;	/* 0xC4 */
-	unsigned int	USBD_RACC;	/* 0xC8 */
-	unsigned int	IRDARX_RACC;	/* 0xCC */
-	unsigned int	IRDA_RACC;	/* 0xD0 */
-	unsigned int	ED0_RACC;	/* 0xD4 */
-	unsigned int	ED1_RACC;	/* 0xD8 */
-};
-
-/*
- * ID Number 0 Register
- */
-#define FTPMU010_ID_A320A	0x03200000
-#define FTPMU010_ID_A320C	0x03200010
-#define FTPMU010_ID_A320D	0x03200030
-
-/*
- * OSC Control Register
- */
-#define FTPMU010_OSCC_OSCH_TRI		(1 << 11)
-#define FTPMU010_OSCC_OSCH_STABLE	(1 << 9)
-#define FTPMU010_OSCC_OSCH_OFF		(1 << 8)
-
-#define FTPMU010_OSCC_OSCL_TRI		(1 << 3)
-#define FTPMU010_OSCC_OSCL_RTCLSEL	(1 << 2)
-#define FTPMU010_OSCC_OSCL_STABLE	(1 << 1)
-#define FTPMU010_OSCC_OSCL_OFF		(1 << 0)
-
-/*
- * Power Mode Register
- */
-#define FTPMU010_PMODE_DIVAHBCLK_MASK	(0x7 << 4)
-#define FTPMU010_PMODE_DIVAHBCLK_2	(0x0 << 4)
-#define FTPMU010_PMODE_DIVAHBCLK_3	(0x1 << 4)
-#define FTPMU010_PMODE_DIVAHBCLK_4	(0x2 << 4)
-#define FTPMU010_PMODE_DIVAHBCLK_6	(0x3 << 4)
-#define FTPMU010_PMODE_DIVAHBCLK_8	(0x4 << 4)
-#define FTPMU010_PMODE_DIVAHBCLK(pmode)	(((pmode) >> 4) & 0x7)
-#define FTPMU010_PMODE_FCS		(1 << 2)
-#define FTPMU010_PMODE_TURBO		(1 << 1)
-#define FTPMU010_PMODE_SLEEP		(1 << 0)
-
-/*
- * Power Manager Status Register
- */
-#define FTPMU010_PMSR_SMR	(1 << 10)
-
-#define FTPMU010_PMSR_RDH	(1 << 2)
-#define FTPMU010_PMSR_PH	(1 << 1)
-#define FTPMU010_PMSR_CKEHLOW	(1 << 0)
-
-/*
- * Multi-Function Port Setting Register
- */
-#define FTPMU010_MFPSR_MODEMPINSEL	(1 << 14)
-#define FTPMU010_MFPSR_AC97CLKOUTSEL	(1 << 13)
-#define FTPMU010_MFPSR_AC97PINSEL	(1 << 3)
-
-/*
- * PLL/DLL Control Register 0
- */
-#define FTPMU010_PDLLCR0_HCLKOUTDIS(cr0)	(((cr0) >> 20) & 0xf)
-#define FTPMU010_PDLLCR0_DLLFRAG		(1 << 19)
-#define FTPMU010_PDLLCR0_DLLSTSEL		(1 << 18)
-#define FTPMU010_PDLLCR0_DLLSTABLE		(1 << 17)
-#define FTPMU010_PDLLCR0_DLLDIS			(1 << 16)
-#define FTPMU010_PDLLCR0_PLL1NS(cr0)		(((cr0) >> 3) & 0x1ff)
-#define FTPMU010_PDLLCR0_PLL1STSEL		(1 << 2)
-#define FTPMU010_PDLLCR0_PLL1STABLE		(1 << 1)
-#define FTPMU010_PDLLCR0_PLL1DIS		(1 << 0)
-
-#endif	/* __FTPMU010_H */
--- a/arch/arm/include/asm/arch-a320/ftsdmc020.h
+++ b/arch/arm/include/asm/arch-a320/ftsdmc020.h
@@ -1,103 +0,0 @@
-/*
- * (C) Copyright 2009 Faraday Technology
- * Po-Yu Chuang <ratbert@faraday-tech.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-/*
- * SDRAM Controller
- */
-#ifndef __FTSDMC020_H
-#define __FTSDMC020_H
-
-#define FTSDMC020_OFFSET_TP0		0x00
-#define FTSDMC020_OFFSET_TP1		0x04
-#define FTSDMC020_OFFSET_CR		0x08
-#define FTSDMC020_OFFSET_BANK0_BSR	0x0C
-#define FTSDMC020_OFFSET_BANK1_BSR	0x10
-#define FTSDMC020_OFFSET_BANK2_BSR	0x14
-#define FTSDMC020_OFFSET_BANK3_BSR	0x18
-#define FTSDMC020_OFFSET_BANK4_BSR	0x1C
-#define FTSDMC020_OFFSET_BANK5_BSR	0x20
-#define FTSDMC020_OFFSET_BANK6_BSR	0x24
-#define FTSDMC020_OFFSET_BANK7_BSR	0x28
-#define FTSDMC020_OFFSET_ACR		0x34
-
-/*
- * Timing Parametet 0 Register
- */
-#define FTSDMC020_TP0_TCL(x)	((x) & 0x3)
-#define FTSDMC020_TP0_TWR(x)	(((x) & 0x3) << 4)
-#define FTSDMC020_TP0_TRF(x)	(((x) & 0xf) << 8)
-#define FTSDMC020_TP0_TRCD(x)	(((x) & 0x7) << 12)
-#define FTSDMC020_TP0_TRP(x)	(((x) & 0xf) << 16)
-#define FTSDMC020_TP0_TRAS(x)	(((x) & 0xf) << 20)
-
-/*
- * Timing Parametet 1 Register
- */
-#define FTSDMC020_TP1_REF_INTV(x)	((x) & 0xffff)
-#define FTSDMC020_TP1_INI_REFT(x)	(((x) & 0xf) << 16)
-#define FTSDMC020_TP1_INI_PREC(x)	(((x) & 0xf) << 20)
-
-/*
- * Configuration Register
- */
-#define FTSDMC020_CR_SREF	(1 << 0)
-#define FTSDMC020_CR_PWDN	(1 << 1)
-#define FTSDMC020_CR_ISMR	(1 << 2)
-#define FTSDMC020_CR_IREF	(1 << 3)
-#define FTSDMC020_CR_IPREC	(1 << 4)
-#define FTSDMC020_CR_REFTYPE	(1 << 5)
-
-/*
- * SDRAM External Bank Base/Size Register
- */
-#define FTSDMC020_BANK_ENABLE		(1 << 28)
-
-#define FTSDMC020_BANK_BASE(addr)	(((addr) >> 20) << 16)
-
-#define FTSDMC020_BANK_DDW_X4		(0 << 12)
-#define FTSDMC020_BANK_DDW_X8		(1 << 12)
-#define FTSDMC020_BANK_DDW_X16		(2 << 12)
-#define FTSDMC020_BANK_DDW_X32		(3 << 12)
-
-#define FTSDMC020_BANK_DSZ_16M		(0 << 8)
-#define FTSDMC020_BANK_DSZ_64M		(1 << 8)
-#define FTSDMC020_BANK_DSZ_128M		(2 << 8)
-#define FTSDMC020_BANK_DSZ_256M		(3 << 8)
-
-#define FTSDMC020_BANK_MBW_8		(0 << 4)
-#define FTSDMC020_BANK_MBW_16		(1 << 4)
-#define FTSDMC020_BANK_MBW_32		(2 << 4)
-
-#define FTSDMC020_BANK_SIZE_1M		0x0
-#define FTSDMC020_BANK_SIZE_2M		0x1
-#define FTSDMC020_BANK_SIZE_4M		0x2
-#define FTSDMC020_BANK_SIZE_8M		0x3
-#define FTSDMC020_BANK_SIZE_16M		0x4
-#define FTSDMC020_BANK_SIZE_32M		0x5
-#define FTSDMC020_BANK_SIZE_64M		0x6
-#define FTSDMC020_BANK_SIZE_128M	0x7
-#define FTSDMC020_BANK_SIZE_256M	0x8
-
-/*
- * Arbiter Control Register
- */
-#define FTSDMC020_ACR_TOC(x)	((x) & 0x1f)
-#define FTSDMC020_ACR_TOE	(1 << 8)
-
-#endif	/* __FTSDMC020_H */
--- a/arch/arm/include/asm/arch-a320/ftsmc020.h
+++ b/arch/arm/include/asm/arch-a320/ftsmc020.h
@@ -1,79 +0,0 @@
-/*
- * (C) Copyright 2009 Faraday Technology
- * Po-Yu Chuang <ratbert@faraday-tech.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-/*
- * Static Memory Controller
- */
-#ifndef __FTSMC020_H
-#define __FTSMC020_H
-
-#ifndef __ASSEMBLY__
-
-struct ftsmc020 {
-	struct {
-		unsigned int	cr;	/* 0x00, 0x08, 0x10, 0x18 */
-		unsigned int	tpr;	/* 0x04, 0x0c, 0x14, 0x1c */
-	} bank[4];
-	unsigned int	pad[8];	/* 0x20 - 0x3c */
-	unsigned int	ssr;	/* 0x40 */
-};
-
-void ftsmc020_init(void);
-
-#endif /* __ASSEMBLY__ */
-
-/*
- * Memory Bank Configuration Register
- */
-#define FTSMC020_BANK_ENABLE	(1 << 28)
-#define FTSMC020_BANK_BASE(x)	((x) & 0x0fff1000)
-
-#define FTSMC020_BANK_WPROT	(1 << 11)
-
-#define FTSMC020_BANK_SIZE_32K	(0xb << 4)
-#define FTSMC020_BANK_SIZE_64K	(0xc << 4)
-#define FTSMC020_BANK_SIZE_128K	(0xd << 4)
-#define FTSMC020_BANK_SIZE_256K	(0xe << 4)
-#define FTSMC020_BANK_SIZE_512K	(0xf << 4)
-#define FTSMC020_BANK_SIZE_1M	(0x0 << 4)
-#define FTSMC020_BANK_SIZE_2M	(0x1 << 4)
-#define FTSMC020_BANK_SIZE_4M	(0x2 << 4)
-#define FTSMC020_BANK_SIZE_8M	(0x3 << 4)
-#define FTSMC020_BANK_SIZE_16M	(0x4 << 4)
-#define FTSMC020_BANK_SIZE_32M	(0x5 << 4)
-
-#define FTSMC020_BANK_MBW_8	(0x0 << 0)
-#define FTSMC020_BANK_MBW_16	(0x1 << 0)
-#define FTSMC020_BANK_MBW_32	(0x2 << 0)
-
-/*
- * Memory Bank Timing Parameter Register
- */
-#define FTSMC020_TPR_ETRNA(x)	(((x) & 0xf) << 28)
-#define FTSMC020_TPR_EATI(x)	(((x) & 0xf) << 24)
-#define FTSMC020_TPR_RBE	(1 << 20)
-#define FTSMC020_TPR_AST(x)	(((x) & 0x3) << 18)
-#define FTSMC020_TPR_CTW(x)	(((x) & 0x3) << 16)
-#define FTSMC020_TPR_ATI(x)	(((x) & 0xf) << 12)
-#define FTSMC020_TPR_AT2(x)	(((x) & 0x3) << 8)
-#define FTSMC020_TPR_WTC(x)	(((x) & 0x3) << 6)
-#define FTSMC020_TPR_AHT(x)	(((x) & 0x3) << 4)
-#define FTSMC020_TPR_TRNA(x)	(((x) & 0xf) << 0)
-
-#endif	/* __FTSMC020_H */
--- a/arch/arm/include/asm/arch-a320/fttmr010.h
+++ b/arch/arm/include/asm/arch-a320/fttmr010.h
@@ -1,73 +0,0 @@
-/*
- * (C) Copyright 2009 Faraday Technology
- * Po-Yu Chuang <ratbert@faraday-tech.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-/*
- * Timer
- */
-#ifndef __FTTMR010_H
-#define __FTTMR010_H
-
-struct fttmr010 {
-	unsigned int	timer1_counter;		/* 0x00 */
-	unsigned int	timer1_load;		/* 0x04 */
-	unsigned int	timer1_match1;		/* 0x08 */
-	unsigned int	timer1_match2;		/* 0x0c */
-	unsigned int	timer2_counter;		/* 0x10 */
-	unsigned int	timer2_load;		/* 0x14 */
-	unsigned int	timer2_match1;		/* 0x18 */
-	unsigned int	timer2_match2;		/* 0x1c */
-	unsigned int	timer3_counter;		/* 0x20 */
-	unsigned int	timer3_load;		/* 0x24 */
-	unsigned int	timer3_match1;		/* 0x28 */
-	unsigned int	timer3_match2;		/* 0x2c */
-	unsigned int	cr;			/* 0x30 */
-	unsigned int	interrupt_state;	/* 0x34 */
-	unsigned int	interrupt_mask;		/* 0x38 */
-};
-
-/*
- * Timer Control Register
- */
-#define FTTMR010_TM3_UPDOWN	(1 << 11)
-#define FTTMR010_TM2_UPDOWN	(1 << 10)
-#define FTTMR010_TM1_UPDOWN	(1 << 9)
-#define FTTMR010_TM3_OFENABLE	(1 << 8)
-#define FTTMR010_TM3_CLOCK	(1 << 7)
-#define FTTMR010_TM3_ENABLE	(1 << 6)
-#define FTTMR010_TM2_OFENABLE	(1 << 5)
-#define FTTMR010_TM2_CLOCK	(1 << 4)
-#define FTTMR010_TM2_ENABLE	(1 << 3)
-#define FTTMR010_TM1_OFENABLE	(1 << 2)
-#define FTTMR010_TM1_CLOCK	(1 << 1)
-#define FTTMR010_TM1_ENABLE	(1 << 0)
-
-/*
- * Timer Interrupt State & Mask Registers
- */
-#define FTTMR010_TM3_OVERFLOW	(1 << 8)
-#define FTTMR010_TM3_MATCH2	(1 << 7)
-#define FTTMR010_TM3_MATCH1	(1 << 6)
-#define FTTMR010_TM2_OVERFLOW	(1 << 5)
-#define FTTMR010_TM2_MATCH2	(1 << 4)
-#define FTTMR010_TM2_MATCH1	(1 << 3)
-#define FTTMR010_TM1_OVERFLOW	(1 << 2)
-#define FTTMR010_TM1_MATCH2	(1 << 1)
-#define FTTMR010_TM1_MATCH1	(1 << 0)
-
-#endif	/* __FTTMR010_H */
--- a/arch/arm/include/asm/arch-at91/at91_emac.h
+++ b/arch/arm/include/asm/arch-at91/at91_emac.h
@@ -1,143 +0,0 @@
-/*
- * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
- *
- * based on AT91RM9200 datasheet revision I (36. Ethernet MAC (EMAC))
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef AT91_H
-#define AT91_H
-
-typedef struct at91_emac {
-	u32	 ctl;
-	u32	 cfg;
-	u32	 sr;
-	u32	 tar;
-	u32	 tcr;
-	u32	 tsr;
-	u32	 rbqp;
-	u32	 reserved0;
-	u32	 rsr;
-	u32	 isr;
-	u32	 ier;
-	u32	 idr;
-	u32	 imr;
-	u32	 man;
-	u32	 reserved1[2];
-	u32	 fra;
-	u32	 scol;
-	u32	 mocl;
-	u32	 ok;
-	u32	 seqe;
-	u32	 ale;
-	u32	 dte;
-	u32	 lcol;
-	u32	 ecol;
-	u32	 cse;
-	u32	 tue;
-	u32	 cde;
-	u32	 elr;
-	u32	 rjb;
-	u32	 usf;
-	u32	 sqee;
-	u32	 drfc;
-	u32	 reserved2[3];
-	u32	 hsh;
-	u32	 hsl;
-	u32	 sh1l;
-	u32	 sa1h;
-	u32	 sa2l;
-	u32	 sa2h;
-	u32	 sa3l;
-	u32	 sa3h;
-	u32	 sa4l;
-	u32	 sa4h;
-} at91_emac_t;
-
-#define AT91_EMAC_CTL_LB	0x0001
-#define AT91_EMAC_CTL_LBL	0x0002
-#define AT91_EMAC_CTL_RE	0x0004
-#define AT91_EMAC_CTL_TE	0x0008
-#define AT91_EMAC_CTL_MPE	0x0010
-#define AT91_EMAC_CTL_CSR	0x0020
-#define AT91_EMAC_CTL_ISR	0x0040
-#define AT91_EMAC_CTL_WES	0x0080
-#define AT91_EMAC_CTL_BP	0x1000
-
-#define AT91_EMAC_CFG_SPD	0x0001
-#define AT91_EMAC_CFG_FD	0x0002
-#define AT91_EMAC_CFG_BR	0x0004
-#define AT91_EMAC_CFG_CAF	0x0010
-#define AT91_EMAC_CFG_NBC	0x0020
-#define AT91_EMAC_CFG_MTI	0x0040
-#define AT91_EMAC_CFG_UNI	0x0080
-#define AT91_EMAC_CFG_BIG	0x0100
-#define AT91_EMAC_CFG_EAE	0x0200
-#define AT91_EMAC_CFG_CLK_MASK	0xFFFFF3FF
-#define AT91_EMAC_CFG_MCLK_8	0x0000
-#define AT91_EMAC_CFG_MCLK_16	0x0400
-#define AT91_EMAC_CFG_MCLK_32	0x0800
-#define AT91_EMAC_CFG_MCLK_64	0x0C00
-#define AT91_EMAC_CFG_RTY	0x1000
-#define AT91_EMAC_CFG_RMII	0x2000
-
-#define AT91_EMAC_SR_LINK	0x0001
-#define AT91_EMAC_SR_MDIO	0x0002
-#define AT91_EMAC_SR_IDLE	0x0004
-
-#define AT91_EMAC_TCR_LEN(x)	(x & 0x7FF)
-#define AT91_EMAC_TCR_NCRC	0x8000
-
-#define AT91_EMAC_TSR_OVR	0x0001
-#define AT91_EMAC_TSR_COL	0x0002
-#define AT91_EMAC_TSR_RLE	0x0004
-#define AT91_EMAC_TSR_TXIDLE	0x0008
-#define AT91_EMAC_TSR_BNQ	0x0010
-#define AT91_EMAC_TSR_COMP	0x0020
-#define AT91_EMAC_TSR_UND	0x0040
-
-#define AT91_EMAC_RSR_BNA	0x0001
-#define AT91_EMAC_RSR_REC	0x0002
-#define AT91_EMAC_RSR_OVR	0x0004
-
-/*  ISR, IER, IDR, IMR use the same bits */
-#define AT91_EMAC_IxR_DONE	0x0001
-#define AT91_EMAC_IxR_RCOM	0x0002
-#define AT91_EMAC_IxR_RBNA	0x0004
-#define AT91_EMAC_IxR_TOVR	0x0008
-#define AT91_EMAC_IxR_TUND	0x0010
-#define AT91_EMAC_IxR_RTRY	0x0020
-#define AT91_EMAC_IxR_TBRE	0x0040
-#define AT91_EMAC_IxR_TCOM	0x0080
-#define AT91_EMAC_IxR_TIDLE	0x0100
-#define AT91_EMAC_IxR_LINK	0x0200
-#define AT91_EMAC_IxR_ROVR	0x0400
-#define AT91_EMAC_IxR_HRESP	0x0800
-
-#define AT91_EMAC_MAN_DATA_MASK		0xFFFF
-#define AT91_EMAC_MAN_CODE_802_3	0x00020000
-#define AT91_EMAC_MAN_REGA(reg)		((reg & 0x1F) << 18)
-#define AT91_EMAC_MAN_PHYA(phy)		((phy & 0x1F) << 23)
-#define AT91_EMAC_MAN_RW_R		0x20000000
-#define AT91_EMAC_MAN_RW_W		0x10000000
-#define AT91_EMAC_MAN_HIGH		0x40000000
-#define AT91_EMAC_MAN_LOW		0x80000000
-
-#endif
--- a/arch/arm/include/asm/arch-at91/at91_matrix.h
+++ b/arch/arm/include/asm/arch-at91/at91_matrix.h
@@ -1,254 +0,0 @@
-/*
- * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef AT91_MATRIX_H
-#define AT91_MATRIX_H
-
-#ifdef __ASSEMBLY__
-
-#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20)
-#define AT91_ASM_MATRIX_CSA0	(AT91_MATRIX_BASE + 0x11C)
-#elif defined(CONFIG_AT91SAM9261)
-#define AT91_ASM_MATRIX_CSA0	(AT91_MATRIX_BASE + 0x30)
-#elif defined(CONFIG_AT91SAM9263)
-#define AT91_ASM_MATRIX_CSA0	(AT91_MATRIX_BASE + 0x120)
-#elif defined(CONFIG_AT91SAM9G45)
-#define AT91_ASM_MATRIX_CSA0	(AT91_MATRIX_BASE + 0x128)
-#else
-#error AT91_ASM_MATRIX_CSA0 is not definied for current CPU
-#endif
-
-#define AT91_ASM_MATRIX_MCFG	AT91_MATRIX_BASE
-
-#else
-#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20)
-#define AT91_MATRIX_MASTERS	6
-#define AT91_MATRIX_SLAVES	5
-#elif defined(CONFIG_AT91SAM9261)
-#define AT91_MATRIX_MASTERS	1
-#define AT91_MATRIX_SLAVES	5
-#elif defined(CONFIG_AT91SAM9263)
-#define AT91_MATRIX_MASTERS	9
-#define AT91_MATRIX_SLAVES	7
-#elif defined(CONFIG_AT91SAM9G45)
-#define AT91_MATRIX_MASTERS	11
-#define AT91_MATRIX_SLAVES	8
-#else
-#error CPU not supported. Please update at91_matrix.h
-#endif
-
-typedef struct at91_priority {
-	u32	a;
-	u32	b;
-} at91_priority_t;
-
-typedef struct at91_matrix {
-	u32		mcfg[AT91_MATRIX_MASTERS];
-#if defined(CONFIG_AT91SAM9261)
-	u32		scfg[AT91_MATRIX_SLAVES];
-	u32		res61_1[3];
-	u32		tcr;
-	u32		res61_2[2];
-	u32		csa;
-	u32		pucr;
-	u32		res61_3[114];
-#else
-	u32		reserve1[16 - AT91_MATRIX_MASTERS];
-	u32		scfg[AT91_MATRIX_SLAVES];
-	u32		reserve2[16 - AT91_MATRIX_SLAVES];
-	at91_priority_t	pr[AT91_MATRIX_SLAVES];
-	u32		reserve3[32 - (2 * AT91_MATRIX_SLAVES)];
-	u32		mrcr;		/* 0x100 Master Remap Control */
-	u32		reserve4[3];
-#if	defined(CONFIG_AT91SAM9G45)
-	u32		ccr[52];	/* 0x110 - 0x1E0 Chip Configuration */
-	u32		womr;		/* 0x1E4 Write Protect Mode  */
-	u32		wpsr;		/* 0x1E8 Write Protect Status */
-	u32		resg45_1[10];
-#elif defined(CONFIG_AT91SAM9260)  || defined(CONFIG_AT91SAM9G20)
-	u32		res60_1[3];
-	u32		csa;
-	u32		res60_2[56];
-#elif defined(CONFIG_AT91SAM9263)
-	u32		res63_1;
-	u32		tcmr;
-	u32		res63_2[2];
-	u32		csa[2];
-	u32		res63_3[54];
-#else
-	u32		reserve5[60];
-#endif
-#endif
-} at91_matrix_t;
-
-#endif /* __ASSEMBLY__ */
-
-#define AT91_MATRIX_CSA_DBPUC		0x00000100
-#define AT91_MATRIX_CSA_VDDIOMSEL_1_8V	0x00000000
-#define AT91_MATRIX_CSA_VDDIOMSEL_3_3V	0x00010000
-
-#define AT91_MATRIX_CSA_EBI_CS1A	0x00000002
-#define AT91_MATRIX_CSA_EBI_CS3A	0x00000008
-#define AT91_MATRIX_CSA_EBI_CS4A	0x00000010
-#define AT91_MATRIX_CSA_EBI_CS5A	0x00000020
-
-#define AT91_MATRIX_CSA_EBI1_CS2A	0x00000008
-
-#if defined CONFIG_AT91SAM9261
-/* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
-#define	AT91_MATRIX_MCFG_RCB0	(1 << 0)
-/* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
-#define	AT91_MATRIX_MCFG_RCB1	(1 << 1)
-#endif
-
-/* Undefined Length Burst Type */
-#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263) || \
-	defined(CONFIG_AT91SAM9G45)
-#define AT91_MATRIX_MCFG_ULBT_INFINITE	0x00000000
-#define AT91_MATRIX_MCFG_ULBT_SINGLE	0x00000001
-#define AT91_MATRIX_MCFG_ULBT_FOUR	0x00000002
-#define AT91_MATRIX_MCFG_ULBT_EIGHT	0x00000003
-#define AT91_MATRIX_MCFG_ULBT_SIXTEEN	0x00000004
-#endif
-#if defined(CONFIG_AT91SAM9G45)
-#define AT91_MATRIX_MCFG_ULBT_THIRTYTWO	0x00000005
-#define AT91_MATRIX_MCFG_ULBT_SIXTYFOUR	0x00000006
-#define AT91_MATRIX_MCFG_ULBT_128	0x00000007
-#endif
-
-/* Default Master Type */
-#define AT91_MATRIX_SCFG_DEFMSTR_TYPE_NONE	0x00000000
-#define AT91_MATRIX_SCFG_DEFMSTR_TYPE_LAST	0x00010000
-#define AT91_MATRIX_SCFG_DEFMSTR_TYPE_FIXED	0x00020000
-
-/* Fixed Index of Default Master */
-#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9263)
-#define	AT91_MATRIX_SCFG_FIXED_DEFMSTR(x)	((x & 0xf) << 18)
-#elif defined(CONFIG_AT91SAM9261) || defined(CONFIG_AT91SAM9260)
-#define	AT91_MATRIX_SCFG_FIXED_DEFMSTR(x)	((x & 7) << 18)
-#endif
-
-/* Maximum Number of Allowed Cycles for a Burst */
-#if defined(CONFIG_AT91SAM9G45)
-#define	AT91_MATRIX_SCFG_SLOT_CYCLE(x)	((x & 0x1ff) << 0)
-#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) || \
-	defined(CONFIG_AT91SAM9263)
-#define	AT91_MATRIX_SCFG_SLOT_CYCLE(x)	((x & 0xff) << 0)
-#endif
-
-/* Arbitration Type */
-#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263)
-#define	AT91_MATRIX_SCFG_ARBT_ROUND_ROBIN	0x00000000
-#define	AT91_MATRIX_SCFG_ARBT_FIXED_PRIORITY	0x01000000
-#endif
-
-/* Master Remap Control Register */
-#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263) || \
-	defined(CONFIG_AT91SAM9G45)
-/* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
-#define	AT91_MATRIX_MRCR_RCB0	(1 << 0)
-/* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
-#define	AT91_MATRIX_MRCR_RCB1	(1 << 1)
-#endif
-#if defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G45)
-#define	AT91_MATRIX_MRCR_RCB2	0x00000004
-#define	AT91_MATRIX_MRCR_RCB3	0x00000008
-#define	AT91_MATRIX_MRCR_RCB4	0x00000010
-#define	AT91_MATRIX_MRCR_RCB5	0x00000020
-#define	AT91_MATRIX_MRCR_RCB6	0x00000040
-#define	AT91_MATRIX_MRCR_RCB7	0x00000080
-#define	AT91_MATRIX_MRCR_RCB8	0x00000100
-#endif
-#if defined(CONFIG_AT91SAM9G45)
-#define	AT91_MATRIX_MRCR_RCB9	0x00000200
-#define	AT91_MATRIX_MRCR_RCB10	0x00000400
-#define	AT91_MATRIX_MRCR_RCB11	0x00000800
-#endif
-
-/* TCM Configuration Register */
-#if defined(CONFIG_AT91SAM9G45)
-/* Size of ITCM enabled memory block */
-#define	AT91_MATRIX_TCMR_ITCM_0		0x00000000
-#define	AT91_MATRIX_TCMR_ITCM_32	0x00000040
-/* Size of DTCM enabled memory block */
-#define	AT91_MATRIX_TCMR_DTCM_0		0x00000000
-#define	AT91_MATRIX_TCMR_DTCM_32	0x00000060
-#define	AT91_MATRIX_TCMR_DTCM_64	0x00000070
-/* Wait state TCM register */
-#define	AT91_MATRIX_TCMR_TCM_NO_WS	0x00000000
-#define	AT91_MATRIX_TCMR_TCM_ONE_WS	0x00000800
-#endif
-#if defined(CONFIG_AT91SAM9263)
-/* Size of ITCM enabled memory block */
-#define	AT91_MATRIX_TCMR_ITCM_0		0x00000000
-#define	AT91_MATRIX_TCMR_ITCM_16	0x00000005
-#define	AT91_MATRIX_TCMR_ITCM_32	0x00000006
-/* Size of DTCM enabled memory block */
-#define	AT91_MATRIX_TCMR_DTCM_0		0x00000000
-#define	AT91_MATRIX_TCMR_DTCM_16	0x00000050
-#define	AT91_MATRIX_TCMR_DTCM_32	0x00000060
-#endif
-#if defined(CONFIG_AT91SAM9261)
-/* Size of ITCM enabled memory block */
-#define	AT91_MATRIX_TCMR_ITCM_0		0x00000000
-#define	AT91_MATRIX_TCMR_ITCM_16	0x00000005
-#define	AT91_MATRIX_TCMR_ITCM_32	0x00000006
-#define	AT91_MATRIX_TCMR_ITCM_64	0x00000007
-/* Size of DTCM enabled memory block */
-#define	AT91_MATRIX_TCMR_DTCM_0		0x00000000
-#define	AT91_MATRIX_TCMR_DTCM_16	0x00000050
-#define	AT91_MATRIX_TCMR_DTCM_32	0x00000060
-#define	AT91_MATRIX_TCMR_DTCM_64	0x00000070
-#endif
-
-#if defined(CONFIG_AT91SAM9G45)
-/* Video Mode Configuration Register */
-#define	AT91C_MATRIX_VDEC_SEL_OFF	0x00000000
-#define	AT91C_MATRIX_VDEC_SEL_ON	0x00000001
-/* Write Protect Mode Register */
-#define	AT91_MATRIX_WPMR_WP_WPDIS	0x00000000
-#define	AT91_MATRIX_WPMR_WP_WPEN	0x00000001
-#define	AT91_MATRIX_WPMR_WPKEY		0xFFFFFF00	/* Write Protect KEY */
-/* Write Protect Status Register */
-#define	AT91_MATRIX_WPSR_NO_WPV		0x00000000
-#define	AT91_MATRIX_WPSR_WPV		0x00000001
-#define	AT91_MATRIX_WPSR_WPVSRC		0x00FFFF00	/* Write Protect Violation Source */
-#endif
-
-/* USB Pad Pull-Up Control Register */
-#if defined(CONFIG_AT91SAM9261)
-#define	AT91_MATRIX_USBPUCR_PUON	0x40000000
-#endif
-
-#define AT91_MATRIX_PRA_M0(x)	((x & 3) << 0)	/* Master 0 Priority Reg. A*/
-#define AT91_MATRIX_PRA_M1(x)	((x & 3) << 4)	/* Master 1 Priority Reg. A*/
-#define AT91_MATRIX_PRA_M2(x)	((x & 3) << 8)	/* Master 2 Priority Reg. A*/
-#define AT91_MATRIX_PRA_M3(x)	((x & 3) << 12)	/* Master 3 Priority Reg. A*/
-#define AT91_MATRIX_PRA_M4(x)	((x & 3) << 16)	/* Master 4 Priority Reg. A*/
-#define AT91_MATRIX_PRA_M5(x)	((x & 3) << 20)	/* Master 5 Priority Reg. A*/
-#define AT91_MATRIX_PRA_M6(x)	((x & 3) << 24)	/* Master 6 Priority Reg. A*/
-#define AT91_MATRIX_PRA_M7(x)	((x & 3) << 28)	/* Master 7 Priority Reg. A*/
-#define AT91_MATRIX_PRB_M8(x)	((x & 3) << 0)	/* Master 8 Priority Reg. B) */
-#define AT91_MATRIX_PRB_M9(x)	((x & 3) << 4)	/* Master 9 Priority Reg. B) */
-#define AT91_MATRIX_PRB_M10(x)	((x & 3) << 8)	/* Master 10 Priority Reg. B) */
-
-#endif
--- a/arch/arm/include/asm/arch-at91/at91_mc.h
+++ b/arch/arm/include/asm/arch-at91/at91_mc.h
@@ -1,97 +0,0 @@
-/*
- * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef AT91_MC_H
-#define AT91_MC_H
-
-#define AT91_ASM_MC_EBI_CSA	(AT91_MC_BASE + 0x60)
-#define AT91_ASM_MC_EBI_CFG	(AT91_MC_BASE + 0x64)
-#define AT91_ASM_MC_SMC_CSR0	(AT91_MC_BASE + 0x70)
-#define AT91_ASM_MC_SDRAMC_MR	(AT91_MC_BASE + 0x90)
-#define AT91_ASM_MC_SDRAMC_TR	(AT91_MC_BASE + 0x94)
-#define AT91_ASM_MC_SDRAMC_CR	(AT91_MC_BASE + 0x98)
-
-#ifndef __ASSEMBLY__
-
-typedef struct at91_ebi {
-	u32 	csa;		/* 0x00 Chip Select Assignment Register */
-	u32	cfgr;		/* 0x04 Configuration Register */
-	u32	reserved[2];
-} __attribute__ ((packed)) at91_ebi_t;
-
-#define AT91_EBI_CSA_CS0A	0x0001
-#define AT91_EBI_CSA_CS1A	0x0002
-
-#define AT91_EBI_CSA_CS3A	0x0008
-#define AT91_EBI_CSA_CS4A	0x0010
-
-typedef struct at91_sdramc {
-	u32	mr; 	/* 0x00 SDRAMC Mode Register */
-	u32	tr; 	/* 0x04 SDRAMC Refresh Timer Register */
-	u32	cr; 	/* 0x08 SDRAMC Configuration Register */
-	u32	ssr; 	/* 0x0C SDRAMC Self Refresh Register */
-	u32	lpr; 	/* 0x10 SDRAMC Low Power Register */
-	u32	ier; 	/* 0x14 SDRAMC Interrupt Enable Register */
-	u32	idr; 	/* 0x18 SDRAMC Interrupt Disable Register */
-	u32	imr; 	/* 0x1C SDRAMC Interrupt Mask Register */
-	u32	icr; 	/* 0x20 SDRAMC Interrupt Status Register */
-	u32	reserved[3];
-} __attribute__ ((packed)) at91_sdramc_t;
-
-typedef struct at91_smc {
-	u32	csr[8]; 	/* 0x00 SDRAMC Mode Register */
-} __attribute__ ((packed)) at91_smc_t;
-
-#define AT91_SMC_CSR_RWHOLD(x)		((x & 0x7) << 28)
-#define AT91_SMC_CSR_RWSETUP(x)		((x & 0x7) << 24)
-#define AT91_SMC_CSR_ACSS_STANDARD	0x00000000
-#define AT91_SMC_CSR_ACSS_1CYCLE	0x00010000
-#define AT91_SMC_CSR_ACSS_2CYCLE	0x00020000
-#define AT91_SMC_CSR_ACSS_3CYCLE	0x00030000
-#define AT91_SMC_CSR_DRP		0x00008000
-#define AT91_SMC_CSR_DBW_8		0x00004000
-#define AT91_SMC_CSR_DBW_16		0x00002000
-#define AT91_SMC_CSR_BAT_8		0x00000000
-#define AT91_SMC_CSR_BAT_16		0x00001000
-#define AT91_SMC_CSR_TDF(x)		((x & 0xF) << 8)
-#define AT91_SMC_CSR_WSEN		0x00000080
-#define AT91_SMC_CSR_NWS(x)		(x & 0x7F)
-
-typedef struct at91_bfc {
-	u32	mr; 	/* 0x00 SDRAMC Mode Register */
-} __attribute__ ((packed)) at91_bfc_t;
-
-typedef struct at91_mc {
-	u32		rcr;		/* 0x00 MC Remap Control Register */
-	u32		asr;		/* 0x04 MC Abort Status Register */
-	u32		aasr;		/* 0x08 MC Abort Address Status Reg */
-	u32		mpr;		/* 0x0C MC Master Priority Register */
-	u32		reserved1[20];	/* 0x10-0x5C */
-	at91_ebi_t	ebi;		/* 0x60	- 0x6C EBI */
-	at91_smc_t	smc;		/* 0x70 - 0x8C SMC User Interface */
-	at91_sdramc_t	sdramc;		/* 0x90 - 0xBC SDRAMC User Interface */
-	at91_bfc_t	bfc;		/* 0xC0 BFC User Interface */
-	u32		reserved2[15];
-} __attribute__ ((packed)) at91_mc_t;
-
-#endif
-#endif
--- a/arch/arm/include/asm/arch-at91/at91_pdc.h
+++ b/arch/arm/include/asm/arch-at91/at91_pdc.h
@@ -1,39 +0,0 @@
-/*
- * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef AT91_PDC_H
-#define AT91_PDC_H
-
-typedef struct at91_pdc {
-	u32	rpr;		/* 0x100 Receive Pointer Register */
-	u32	rcr;		/* 0x104 Receive Counter Register */
-	u32	tpr;		/* 0x108 Transmit Pointer Register */
-	u32	tcr;		/* 0x10C Transmit Counter Register */
-	u32	pnpr;		/* 0x110 Receive Next Pointer Register */
-	u32	pncr;		/* 0x114 Receive Next Counter Register */
-	u32	tnpr;		/* 0x118 Transmit Next Pointer Register */
-	u32	tncr;		/* 0x11C Transmit Next Counter Register */
-	u32	ptcr;		/* 0x120 Transfer Control Register */
-	u32	ptsr;		/* 0x124 Transfer Status Register */
-} at91_pdc_t;
-
-#endif
--- a/arch/arm/include/asm/arch-at91/at91_pio.h
+++ b/arch/arm/include/asm/arch-at91/at91_pio.h
@@ -1,160 +0,0 @@
-/*
- * [origin: Linux kernel include/asm-arm/arch-at91/at91_pio.h]
- *
- * Copyright (C) 2005 Ivan Kokshaysky
- * Copyright (C) SAN People
- * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
- *
- * Parallel I/O Controller (PIO) - System peripherals registers.
- * Based on AT91RM9200 datasheet revision E.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91_PIO_H
-#define AT91_PIO_H
-
-
-#define AT91_ASM_PIO_RANGE	0x200
-#define AT91_ASM_PIOC_ASR	\
-	(AT91_PIO_BASE + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x70)
-#define AT91_ASM_PIOC_BSR	\
-	(AT91_PIO_BASE + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x74)
-#define AT91_ASM_PIOC_PDR	\
-	(AT91_PIO_BASE + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x04)
-#define AT91_ASM_PIOC_PUDR	\
-	(AT91_PIO_BASE + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x60)
-
-#define AT91_ASM_PIOD_PDR	\
-	(AT91_PIO_BASE + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x04)
-#define AT91_ASM_PIOD_PUDR	\
-	(AT91_PIO_BASE + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x60)
-#define AT91_ASM_PIOD_ASR	\
-	(AT91_PIO_BASE + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x70)
-
-#ifndef __ASSEMBLY__
-
-typedef struct at91_port {
-	u32	per;		/* 0x00 PIO Enable Register */
-	u32	pdr;		/* 0x04 PIO Disable Register */
-	u32	psr;		/* 0x08 PIO Status Register */
-	u32	reserved0;
-	u32	oer;		/* 0x10 Output Enable Register */
-	u32	odr;		/* 0x14 Output Disable Registerr */
-	u32	osr;		/* 0x18 Output Status Register */
-	u32	reserved1;
-	u32	ifer;		/* 0x20 Input Filter Enable Register */
-	u32	ifdr;		/* 0x24 Input Filter Disable Register */
-	u32	ifsr;		/* 0x28 Input Filter Status Register */
-	u32	reserved2;
-	u32	sodr;		/* 0x30 Set Output Data Register */
-	u32	codr;		/* 0x34 Clear Output Data Register */
-	u32	odsr;		/* 0x38 Output Data Status Register */
-	u32	pdsr;		/* 0x3C Pin Data Status Register */
-	u32	ier;		/* 0x40 Interrupt Enable Register */
-	u32	idr;		/* 0x44 Interrupt Disable Register */
-	u32	imr;		/* 0x48 Interrupt Mask Register */
-	u32	isr;		/* 0x4C Interrupt Status Register */
-	u32	mder;		/* 0x50 Multi-driver Enable Register */
-	u32	mddr;		/* 0x54 Multi-driver Disable Register */
-	u32	mdsr;		/* 0x58 Multi-driver Status Register */
-	u32	reserved3;
-	u32	pudr;		/* 0x60 Pull-up Disable Register */
-	u32	puer;		/* 0x64 Pull-up Enable Register */
-	u32	pusr;		/* 0x68 Pad Pull-up Status Register */
-	u32	reserved4;
-	u32	asr;		/* 0x70 Select A Register */
-	u32	bsr;		/* 0x74 Select B Register */
-	u32	absr;		/* 0x78 AB Select Status Register */
-	u32	reserved5[9];	/*  */
-	u32	ower;		/* 0xA0 Output Write Enable Register */
-	u32	owdr;		/* 0xA4 Output Write Disable Register */
-	u32	owsr;		/* OxA8 utput Write Status Register */
-	u32	reserved6[85];
-} at91_port_t;
-
-#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) || \
-	defined(CONFIG_AT91SAM9G10) || defined(CONFIG_AT91SAM9G20)
-#define AT91_PIO_PORTS	3
-#elif defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G45) || \
-	defined(CONFIG_AT91SAM9M10G45)
-#define AT91_PIO_PORTS	5
-#elif defined(CONFIG_AT91RM9200) || defined(CONFIG_AT91CAP9) || \
-	defined(CONFIG_AT91SAM9RL)
-#define AT91_PIO_PORTS	4
-#else
-#error "Unsupported cpu. Please update at91_pio.h"
-#endif
-
-typedef union at91_pio {
-	struct {
-		at91_port_t	pioa;
-		at91_port_t	piob;
-		at91_port_t	pioc;
-	#if (AT91_PIO_PORTS > 3)
-		at91_port_t	piod;
-	#endif
-	#if (AT91_PIO_PORTS > 4)
-		at91_port_t	pioe;
-	#endif
-	} ;
-	at91_port_t port[AT91_PIO_PORTS];
-} at91_pio_t;
-
-#ifdef CONFIG_AT91_GPIO
-int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup);
-int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup);
-int at91_set_pio_input(unsigned port, unsigned pin, int use_pullup);
-int at91_set_pio_multi_drive(unsigned port, unsigned pin, int is_on);
-int at91_set_pio_output(unsigned port, unsigned pin, int value);
-int at91_set_pio_periph(unsigned port, unsigned pin, int use_pullup);
-int at91_set_pio_pullup(unsigned port, unsigned pin, int use_pullup);
-int at91_set_pio_deglitch(unsigned port, unsigned pin, int is_on);
-int at91_set_pio_value(unsigned port, unsigned pin, int value);
-int at91_get_pio_value(unsigned port, unsigned pin);
-#endif
-#endif
-
-#define	AT91_PIO_PORTA		0x0
-#define	AT91_PIO_PORTB		0x1
-#define	AT91_PIO_PORTC		0x2
-#define	AT91_PIO_PORTD		0x3
-#define	AT91_PIO_PORTE		0x4
-
-#ifdef CONFIG_AT91_LEGACY
-
-#define PIO_PER		0x00	/* Enable Register */
-#define PIO_PDR		0x04	/* Disable Register */
-#define PIO_PSR		0x08	/* Status Register */
-#define PIO_OER		0x10	/* Output Enable Register */
-#define PIO_ODR		0x14	/* Output Disable Register */
-#define PIO_OSR		0x18	/* Output Status Register */
-#define PIO_IFER	0x20	/* Glitch Input Filter Enable */
-#define PIO_IFDR	0x24	/* Glitch Input Filter Disable */
-#define PIO_IFSR	0x28	/* Glitch Input Filter Status */
-#define PIO_SODR	0x30	/* Set Output Data Register */
-#define PIO_CODR	0x34	/* Clear Output Data Register */
-#define PIO_ODSR	0x38	/* Output Data Status Register */
-#define PIO_PDSR	0x3c	/* Pin Data Status Register */
-#define PIO_IER		0x40	/* Interrupt Enable Register */
-#define PIO_IDR		0x44	/* Interrupt Disable Register */
-#define PIO_IMR		0x48	/* Interrupt Mask Register */
-#define PIO_ISR		0x4c	/* Interrupt Status Register */
-#define PIO_MDER	0x50	/* Multi-driver Enable Register */
-#define PIO_MDDR	0x54	/* Multi-driver Disable Register */
-#define PIO_MDSR	0x58	/* Multi-driver Status Register */
-#define PIO_PUDR	0x60	/* Pull-up Disable Register */
-#define PIO_PUER	0x64	/* Pull-up Enable Register */
-#define PIO_PUSR	0x68	/* Pull-up Status Register */
-#define PIO_ASR		0x70	/* Peripheral A Select Register */
-#define PIO_BSR		0x74	/* Peripheral B Select Register */
-#define PIO_ABSR	0x78	/* AB Status Register */
-#define PIO_OWER	0xa0	/* Output Write Enable Register */
-#define PIO_OWDR	0xa4	/* Output Write Disable Register */
-#define PIO_OWSR	0xa8	/* Output Write Status Register */
-#endif
-
-#endif
--- a/arch/arm/include/asm/arch-at91/at91_st.h
+++ b/arch/arm/include/asm/arch-at91/at91_st.h
@@ -1,46 +0,0 @@
-/*
- * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef AT91_ST_H
-#define AT91_ST_H
-
-typedef struct at91_st {
-
-	u32	cr;
-	u32	pimr;
-	u32	wdmr;
-	u32	rtmr;
-	u32	sr;
-	u32	ier;
-	u32	idr;
-	u32	imr;
-	u32	rtar;
-	u32	crtr;
-} __attribute__ ((packed)) at91_st_t ;
-
-#define AT91_ST_CR_WDRST	1
-
-#define AT91_ST_WDMR_WDV(x)	(x & 0xFFFF)
-#define AT91_ST_WDMR_RSTEN	0x00010000
-#define AT91_ST_WDMR_EXTEN 	0x00020000
-
-#endif
--- a/arch/arm/include/asm/arch-at91/at91_tc.h
+++ b/arch/arm/include/asm/arch-at91/at91_tc.h
@@ -1,77 +0,0 @@
-/*
- * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef AT91_TC_H
-#define AT91_TC_H
-
-typedef struct at91_tcc {
-	u32		ccr;	/* 0x00 Channel Control Register */
-	u32		cmr;	/* 0x04 Channel Mode Register */
-	u32		reserved1[2];
-	u32		cv;	/* 0x10 Counter Value */
-	u32		ra;	/* 0x14 Register A */
-	u32		rb;	/* 0x18 Register B */
-	u32		rc;	/* 0x1C Register C */
-	u32		sr;	/* 0x20 Status Register */
-	u32		ier;	/* 0x24 Interrupt Enable Register */
-	u32		idr;	/* 0x28 Interrupt Disable Register */
-	u32		imr;	/* 0x2C Interrupt Mask Register */
-	u32		reserved3[4];
-} __attribute__ ((packed)) at91_tcc_t;
-
-#define AT91_TC_CCR_CLKEN		0x00000001
-#define AT91_TC_CCR_CLKDIS		0x00000002
-#define AT91_TC_CCR_SWTRG		0x00000004
-
-#define AT91_TC_CMR_CPCTRG		0x00004000
-
-#define AT91_TC_CMR_TCCLKS_CLOCK1	0x00000000
-#define AT91_TC_CMR_TCCLKS_CLOCK2	0x00000001
-#define AT91_TC_CMR_TCCLKS_CLOCK3	0x00000002
-#define AT91_TC_CMR_TCCLKS_CLOCK4	0x00000003
-#define AT91_TC_CMR_TCCLKS_CLOCK5	0x00000004
-#define AT91_TC_CMR_TCCLKS_XC0		0x00000005
-#define AT91_TC_CMR_TCCLKS_XC1		0x00000006
-#define AT91_TC_CMR_TCCLKS_XC2		0x00000007
-
-typedef struct at91_tc {
-	at91_tcc_t	tc[3];	/* 0x00 TC Channel 0-2 */
-	u32		bcr;	/* 0xC0 TC Block Control Register */
-	u32		bmr;	/* 0xC4 TC Block Mode Register */
-} __attribute__ ((packed)) at91_tc_t;
-
-#define AT91_TC_BMR_TC0XC0S_TCLK0	0x00000000
-#define AT91_TC_BMR_TC0XC0S_NONE	0x00000001
-#define AT91_TC_BMR_TC0XC0S_TIOA1	0x00000002
-#define AT91_TC_BMR_TC0XC0S_TIOA2	0x00000003
-
-#define AT91_TC_BMR_TC1XC1S_TCLK1	0x00000000
-#define AT91_TC_BMR_TC1XC1S_NONE	0x00000004
-#define AT91_TC_BMR_TC1XC1S_TIOA0	0x00000008
-#define AT91_TC_BMR_TC1XC1S_TIOA2	0x0000000C
-
-#define AT91_TC_BMR_TC2XC2S_TCLK2	0x00000000
-#define AT91_TC_BMR_TC2XC2S_NONE	0x00000010
-#define AT91_TC_BMR_TC2XC2S_TIOA0	0x00000020
-#define AT91_TC_BMR_TC2XC2S_TIOA1	0x00000030
-
-#endif
--- a/arch/arm/include/asm/arch-at91/at91rm9200.h
+++ b/arch/arm/include/asm/arch-at91/at91rm9200.h
@@ -1,135 +0,0 @@
-/*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __AT91RM9200_H__
-#define __AT91RM9200_H__
-
-/* Periperial Identifiers */
-
-#define AT91_ID_SYS	1	/* System Peripheral */
-#define AT91_ID_PIOA	2	/* PIO port A */
-#define AT91_ID_PIOB	3	/* PIO port B */
-#define AT91_ID_PIOC	4	/* PIO port C */
-#define AT91_ID_PIOD	5	/* PIO port D BGA only */
-#define AT91_ID_USART0	6	/* USART 0 */
-#define AT91_ID_USART1	7	/* USART 1 */
-#define AT91_ID_USART2	8	/* USART 2 */
-#define AT91_ID_USART3	9	/* USART 3 */
-#define AT91_ID_MCI	10	/* Multimedia Card Interface */
-#define AT91_ID_UDP	11	/* USB Device Port */
-#define AT91_ID_TWI	12	/* Two Wire Interface */
-#define AT91_ID_SPI	13	/* Serial Peripheral Interface */
-#define AT91_ID_SSC0	14	/* Synch. Serial Controller 0 */
-#define AT91_ID_SSC1	15	/* Synch. Serial Controller 1 */
-#define AT91_ID_SSC2	16	/* Synch. Serial Controller 2 */
-#define AT91_ID_TC0	17	/* Timer Counter 0 */
-#define AT91_ID_TC1	18	/* Timer Counter 1 */
-#define AT91_ID_TC2	19	/* Timer Counter 2 */
-#define AT91_ID_TC3	20	/* Timer Counter 3 */
-#define AT91_ID_TC4	21	/* Timer Counter 4 */
-#define AT91_ID_TC5	22	/* Timer Counter 5 */
-#define AT91_ID_UHP	23	/* OHCI USB Host Port */
-#define AT91_ID_EMAC	24	/* Ethernet MAC */
-#define AT91_ID_IRQ0	25	/* Advanced Interrupt Controller */
-#define AT91_ID_IRQ1	26	/* Advanced Interrupt Controller */
-#define AT91_ID_IRQ2	27	/* Advanced Interrupt Controller */
-#define AT91_ID_IRQ3	28	/* Advanced Interrupt Controller */
-#define AT91_ID_IRQ4	29	/* Advanced Interrupt Controller */
-#define AT91_ID_IRQ5	30	/* Advanced Interrupt Controller */
-#define AT91_ID_IRQ6	31	/* Advanced Interrupt Controller */
-
-#define AT91_USB_HOST_BASE	0x00300000
-
-#define AT91_TC_BASE		0xFFFA0000
-#define AT91_UDP_BASE		0xFFFB0000
-#define AT91_MCI_BASE		0xFFFB4000
-#define AT91_TWI_BASE		0xFFFB8000
-#define AT91_EMAC_BASE		0xFFFBC000
-#define AT91_USART_BASE		0xFFFC0000	/* 4x 0x4000 Offset */
-#define AT91_SCC_BASE		0xFFFD0000	/* 4x 0x4000 Offset */
-#define AT91_SPI_BASE		0xFFFE0000
-
-#define AT91_AIC_BASE		0xFFFFF000
-#define AT91_DBGU_BASE		0xFFFFF200
-#define AT91_PIO_BASE		0xFFFFF400	/* 4x 0x200 Offset */
-#define AT91_PMC_BASE		0xFFFFFC00
-#define AT91_ST_BASE		0xFFFFFD00
-#define AT91_ST_BASE		0xFFFFFD00
-#define AT91_RTC_BASE		0xFFFFFE00
-#define AT91_MC_BASE		0xFFFFFF00
-
-
-/* AT91RM9200 Periperial Multiplexing A */
-/* Port A */
-#define AT91_PMX_AA_EREFCK	0x00000080
-#define AT91_PMX_AA_ETXCK	0x00000080
-#define AT91_PMX_AA_ETXEN	0x00000100
-#define AT91_PMX_AA_ETX0	0x00000200
-#define AT91_PMX_AA_ETX1	0x00000400
-#define AT91_PMX_AA_ECRS	0x00000800
-#define AT91_PMX_AA_ECRSDV	0x00000800
-#define AT91_PMX_AA_ERX0	0x00001000
-#define AT91_PMX_AA_ERX1	0x00002000
-#define AT91_PMX_AA_ERXER	0x00004000
-#define AT91_PMX_AA_EMDC	0x00008000
-#define AT91_PMX_AA_EMDIO	0x00010000
-
-#define AT91_PMX_AA_TXD2	0x00810000
-
-#define AT91_PMX_AA_TWD		0x02000000
-#define AT91_PMX_AA_TWCK	0x04000000
-
-/* Port B */
-#define AT91_PMX_BA_ERXCK	0x00080000
-#define AT91_PMX_BA_ECOL	0x00040000
-#define AT91_PMX_BA_ERXDV	0x00020000
-#define AT91_PMX_BA_ERX3	0x00010000
-#define AT91_PMX_BA_ERX2 	0x00008000
-#define AT91_PMX_BA_ETXER	0x00004000
-#define AT91_PMX_BA_ETX3	0x00002000
-#define AT91_PMX_BA_ETX2	0x00001000
-
-/* Port B */
-
-#define AT91_PMX_CA_BFCK	0x00000001
-#define AT91_PMX_CA_BFRDY	0x00000002
-#define AT91_PMX_CA_SMOE	0x00000002
-#define AT91_PMX_CA_BFAVD	0x00000004
-#define AT91_PMX_CA_BFBAA	0x00000008
-#define AT91_PMX_CA_SMWE	0x00000008
-#define AT91_PMX_CA_BFOE	0x00000010
-#define AT91_PMX_CA_BFWE	0x00000020
-#define AT91_PMX_CA_NWAIT	0x00000040
-#define AT91_PMX_CA_A23		0x00000080
-#define AT91_PMX_CA_A24		0x00000100
-#define AT91_PMX_CA_A25		0x00000200
-#define AT91_PMX_CA_CFRNW	0x00000200
-#define AT91_PMX_CA_NCS4	0x00000400
-#define AT91_PMX_CA_CFCS	0x00000400
-#define AT91_PMX_CA_NCS5	0x00000800
-#define AT91_PMX_CA_CFCE1	0x00001000
-#define AT91_PMX_CA_NCS6	0x00001000
-#define AT91_PMX_CA_CFCE2	0x00002000
-#define AT91_PMX_CA_NCS7	0x00002000
-#define AT91_PMX_CA_D16_31	0xFFFF0000
-
-#define CONFIG_SYS_AT91_CPU_NAME	"AT91RM9200"
-
-#endif
--- a/arch/arm/include/asm/arch-davinci/emif_defs.h
+++ b/arch/arm/include/asm/arch-davinci/emif_defs.h
@@ -1,87 +0,0 @@
-/*
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#ifndef _EMIF_DEFS_H_
-#define _EMIF_DEFS_H_
-
-#include <asm/arch/hardware.h>
-
-struct davinci_emif_regs {
-	u_int32_t	ercsr;
-	u_int32_t	awccr;
-	u_int32_t	sdbcr;
-	u_int32_t	sdrcr;
-	u_int32_t	ab1cr;
-	u_int32_t	ab2cr;
-	u_int32_t	ab3cr;
-	u_int32_t	ab4cr;
-	u_int32_t	sdtimr;
-	u_int32_t	ddrsr;
-	u_int32_t	ddrphycr;
-	u_int32_t	ddrphysr;
-	u_int32_t	totar;
-	u_int32_t	totactr;
-	u_int32_t	ddrphyid_rev;
-	u_int32_t	sdsretr;
-	u_int32_t	eirr;
-	u_int32_t	eimr;
-	u_int32_t	eimsr;
-	u_int32_t	eimcr;
-	u_int32_t	ioctrlr;
-	u_int32_t	iostatr;
-	u_int8_t	rsvd0[8];
-	u_int32_t	nandfcr;
-	u_int32_t	nandfsr;
-	u_int8_t	rsvd1[8];
-	u_int32_t	nandfecc[4];
-	u_int8_t	rsvd2[60];
-	u_int32_t	nand4biteccload;
-	u_int32_t	nand4bitecc[4];
-	u_int32_t	nanderradd1;
-	u_int32_t	nanderradd2;
-	u_int32_t	nanderrval1;
-	u_int32_t	nanderrval2;
-};
-
-#define davinci_emif_regs \
-	((struct davinci_emif_regs *)DAVINCI_ASYNC_EMIF_CNTRL_BASE)
-
-#define DAVINCI_NANDFCR_NAND_ENABLE(n)			(1 << (n-2))
-#define DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK		(3 << 4)
-#define DAVINCI_NANDFCR_4BIT_ECC_SEL(n)			((n-2) << 4)
-#define DAVINCI_NANDFCR_1BIT_ECC_START(n)		(1 << (8 + (n-2)))
-#define DAVINCI_NANDFCR_4BIT_ECC_START			(1 << 12)
-#define DAVINCI_NANDFCR_4BIT_CALC_START			(1 << 13)
-
-/* Chip Select setup */
-#define DAVINCI_ABCR_STROBE_SELECT			(1 << 31)
-#define DAVINCI_ABCR_EXT_WAIT				(1 << 30)
-#define DAVINCI_ABCR_WSETUP(n)				(n << 26)
-#define DAVINCI_ABCR_WSTROBE(n)				(n << 20)
-#define DAVINCI_ABCR_WHOLD(n)				(n << 17)
-#define DAVINCI_ABCR_RSETUP(n)				(n << 13)
-#define DAVINCI_ABCR_RSTROBE(n)				(n << 7)
-#define DAVINCI_ABCR_RHOLD(n)				(n << 4)
-#define DAVINCI_ABCR_TA(n)				(n << 2)
-#define DAVINCI_ABCR_ASIZE_16BIT			1
-#define DAVINCI_ABCR_ASIZE_8BIT				0
-
-#endif
--- a/arch/arm/include/asm/arch-ep93xx/ep93xx.h
+++ b/arch/arm/include/asm/arch-ep93xx/ep93xx.h
@@ -1,596 +0,0 @@
-/*
- * Cirrus Logic EP93xx register definitions.
- *
- * Copyright (C) 2009
- * Matthias Kaehlcke <matthias@kaehlcke.net>
- *
- * Copyright (C) 2006
- * Dominic Rath <Dominic.Rath@gmx.de>
- *
- * Copyright (C) 2004, 2005
- * Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
- *
- * Based in large part on linux/include/asm-arm/arch-ep93xx/regmap.h, which is
- *
- * Copyright (C) 2004 Ray Lehtiniemi
- * Copyright (C) 2003 Cirrus Logic, Inc
- * Copyright (C) 1999 ARM Limited.
- *
- * See file CREDITS for list of people who contributed to this project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- * for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#define EP93XX_AHB_BASE			0x80000000
-#define EP93XX_APB_BASE			0x80800000
-
-/*
- * 0x80000000 - 0x8000FFFF: DMA
- */
-#define DMA_OFFSET			0x000000
-#define DMA_BASE			(EP93XX_AHB_BASE | DMA_OFFSET)
-
-#ifndef __ASSEMBLY__
-struct dma_channel {
-	uint32_t control;
-	uint32_t interrupt;
-	uint32_t ppalloc;
-	uint32_t status;
-	uint32_t reserved0;
-	uint32_t remain;
-	uint32_t reserved1[2];
-	uint32_t maxcnt0;
-	uint32_t base0;
-	uint32_t current0;
-	uint32_t reserved2;
-	uint32_t maxcnt1;
-	uint32_t base1;
-	uint32_t current1;
-	uint32_t reserved3;
-};
-
-struct dma_regs {
-	struct dma_channel m2p_channel_0;
-	struct dma_channel m2p_channel_1;
-	struct dma_channel m2p_channel_2;
-	struct dma_channel m2p_channel_3;
-	struct dma_channel m2m_channel_0;
-	struct dma_channel m2m_channel_1;
-	struct dma_channel reserved0[2];
-	struct dma_channel m2p_channel_5;
-	struct dma_channel m2p_channel_4;
-	struct dma_channel m2p_channel_7;
-	struct dma_channel m2p_channel_6;
-	struct dma_channel m2p_channel_9;
-	struct dma_channel m2p_channel_8;
-	uint32_t channel_arbitration;
-	uint32_t reserved[15];
-	uint32_t global_interrupt;
-};
-#endif
-
-/*
- * 0x80010000 - 0x8001FFFF: Ethernet MAC
- */
-#define MAC_OFFSET			0x010000
-#define MAC_BASE			(EP93XX_AHB_BASE | MAC_OFFSET)
-
-#ifndef __ASSEMBLY__
-struct mac_queue {
-	uint32_t badd;
-	union { /* deal with half-word aligned registers */
-		uint32_t blen;
-		union {
-			uint16_t filler;
-			uint16_t curlen;
-		};
-	};
-	uint32_t curadd;
-};
-
-struct mac_regs {
-	uint32_t rxctl;
-	uint32_t txctl;
-	uint32_t testctl;
-	uint32_t reserved0;
-	uint32_t miicmd;
-	uint32_t miidata;
-	uint32_t miists;
-	uint32_t reserved1;
-	uint32_t selfctl;
-	uint32_t inten;
-	uint32_t intstsp;
-	uint32_t intstsc;
-	uint32_t reserved2[2];
-	uint32_t diagad;
-	uint32_t diagdata;
-	uint32_t gt;
-	uint32_t fct;
-	uint32_t fcf;
-	uint32_t afp;
-	union {
-		struct {
-			uint32_t indad;
-			uint32_t indad_upper;
-		};
-		uint32_t hashtbl;
-	};
-	uint32_t reserved3[2];
-	uint32_t giintsts;
-	uint32_t giintmsk;
-	uint32_t giintrosts;
-	uint32_t giintfrc;
-	uint32_t txcollcnt;
-	uint32_t rxmissnct;
-	uint32_t rxruntcnt;
-	uint32_t reserved4;
-	uint32_t bmctl;
-	uint32_t bmsts;
-	uint32_t rxbca;
-	uint32_t reserved5;
-	struct mac_queue rxdq;
-	uint32_t rxdqenq;
-	struct mac_queue rxstsq;
-	uint32_t rxstsqenq;
-	struct mac_queue txdq;
-	uint32_t txdqenq;
-	struct mac_queue txstsq;
-	uint32_t reserved6;
-	uint32_t rxbufthrshld;
-	uint32_t txbufthrshld;
-	uint32_t rxststhrshld;
-	uint32_t txststhrshld;
-	uint32_t rxdthrshld;
-	uint32_t txdthrshld;
-	uint32_t maxfrmlen;
-	uint32_t maxhdrlen;
-};
-#endif
-
-#define SELFCTL_RWP		(1 << 7)
-#define SELFCTL_GPO0		(1 << 5)
-#define SELFCTL_PUWE		(1 << 4)
-#define SELFCTL_PDWE		(1 << 3)
-#define SELFCTL_MIIL		(1 << 2)
-#define SELFCTL_RESET		(1 << 0)
-
-#define INTSTS_RWI		(1 << 30)
-#define INTSTS_RXMI		(1 << 29)
-#define INTSTS_RXBI		(1 << 28)
-#define INTSTS_RXSQI		(1 << 27)
-#define INTSTS_TXLEI		(1 << 26)
-#define INTSTS_ECIE		(1 << 25)
-#define INTSTS_TXUHI		(1 << 24)
-#define INTSTS_MOI		(1 << 18)
-#define INTSTS_TXCOI		(1 << 17)
-#define INTSTS_RXROI		(1 << 16)
-#define INTSTS_MIII		(1 << 12)
-#define INTSTS_PHYI		(1 << 11)
-#define INTSTS_TI		(1 << 10)
-#define INTSTS_AHBE		(1 << 8)
-#define INTSTS_OTHER		(1 << 4)
-#define INTSTS_TXSQ		(1 << 3)
-#define INTSTS_RXSQ		(1 << 2)
-
-#define BMCTL_MT		(1 << 13)
-#define BMCTL_TT		(1 << 12)
-#define BMCTL_UNH		(1 << 11)
-#define BMCTL_TXCHR		(1 << 10)
-#define BMCTL_TXDIS		(1 << 9)
-#define BMCTL_TXEN		(1 << 8)
-#define BMCTL_EH2		(1 << 6)
-#define BMCTL_EH1		(1 << 5)
-#define BMCTL_EEOB		(1 << 4)
-#define BMCTL_RXCHR		(1 << 2)
-#define BMCTL_RXDIS		(1 << 1)
-#define BMCTL_RXEN		(1 << 0)
-
-#define BMSTS_TXACT		(1 << 7)
-#define BMSTS_TP		(1 << 4)
-#define BMSTS_RXACT		(1 << 3)
-#define BMSTS_QID_MASK		0x07
-#define BMSTS_QID_RXDATA	0x00
-#define BMSTS_QID_TXDATA	0x01
-#define BMSTS_QID_RXSTS		0x02
-#define BMSTS_QID_TXSTS		0x03
-#define BMSTS_QID_RXDESC	0x04
-#define BMSTS_QID_TXDESC	0x05
-
-#define AFP_MASK		0x07
-#define AFP_IAPRIMARY		0x00
-#define AFP_IASECONDARY1	0x01
-#define AFP_IASECONDARY2	0x02
-#define AFP_IASECONDARY3	0x03
-#define AFP_TX			0x06
-#define AFP_HASH		0x07
-
-#define RXCTL_PAUSEA		(1 << 20)
-#define RXCTL_RXFCE1		(1 << 19)
-#define RXCTL_RXFCE0		(1 << 18)
-#define RXCTL_BCRC		(1 << 17)
-#define RXCTL_SRXON		(1 << 16)
-#define RXCTL_RCRCA		(1 << 13)
-#define RXCTL_RA		(1 << 12)
-#define RXCTL_PA		(1 << 11)
-#define RXCTL_BA		(1 << 10)
-#define RXCTL_MA		(1 << 9)
-#define RXCTL_IAHA		(1 << 8)
-#define RXCTL_IA3		(1 << 3)
-#define RXCTL_IA2		(1 << 2)
-#define RXCTL_IA1		(1 << 1)
-#define RXCTL_IA0		(1 << 0)
-
-#define TXCTL_DEFDIS		(1 << 7)
-#define TXCTL_MBE		(1 << 6)
-#define TXCTL_ICRC		(1 << 5)
-#define TXCTL_TPD		(1 << 4)
-#define TXCTL_OCOLL		(1 << 3)
-#define TXCTL_SP		(1 << 2)
-#define TXCTL_PB		(1 << 1)
-#define TXCTL_STXON		(1 << 0)
-
-#define MIICMD_REGAD_MASK	(0x001F)
-#define MIICMD_PHYAD_MASK	(0x03E0)
-#define MIICMD_OPCODE_MASK	(0xC000)
-#define MIICMD_PHYAD_8950	(0x0000)
-#define MIICMD_OPCODE_READ	(0x8000)
-#define MIICMD_OPCODE_WRITE	(0x4000)
-
-#define MIISTS_BUSY		(1 << 0)
-
-/*
- * 0x80020000 - 0x8002FFFF: USB OHCI
- */
-#define USB_OFFSET			0x020000
-#define USB_BASE			(EP93XX_AHB_BASE | USB_OFFSET)
-
-/*
- * 0x80030000 - 0x8003FFFF: Raster engine
- */
-#if (defined(CONFIG_EP9307) || defined(CONFIG_EP9312) || defined(CONFIG_EP9315))
-#define RASTER_OFFSET			0x030000
-#define RASTER_BASE			(EP93XX_AHB_BASE | RASTER_OFFSET)
-#endif
-
-/*
- * 0x80040000 - 0x8004FFFF: Graphics accelerator
- */
-#if defined(CONFIG_EP9315)
-#define GFX_OFFSET			0x040000
-#define GFX_BASE			(EP93XX_AHB_BASE | GFX_OFFSET)
-#endif
-
-/*
- * 0x80050000 - 0x8005FFFF: Reserved
- */
-
-/*
- * 0x80060000 - 0x8006FFFF: SDRAM controller
- */
-#define SDRAM_OFFSET			0x060000
-#define SDRAM_BASE			(EP93XX_AHB_BASE | SDRAM_OFFSET)
-
-#ifndef __ASSEMBLY__
-struct sdram_regs {
-	uint32_t reserved;
-	uint32_t glconfig;
-	uint32_t refrshtimr;
-	uint32_t bootsts;
-	uint32_t devcfg0;
-	uint32_t devcfg1;
-	uint32_t devcfg2;
-	uint32_t devcfg3;
-};
-#endif
-
-#define SDRAM_DEVCFG_EXTBUSWIDTH	(1 << 2)
-#define SDRAM_DEVCFG_BANKCOUNT		(1 << 3)
-#define SDRAM_DEVCFG_SROMLL		(1 << 5)
-#define SDRAM_DEVCFG_CASLAT_2		0x00010000
-#define SDRAM_DEVCFG_RASTOCAS_2		0x00200000
-
-#define GLCONFIG_INIT			(1 << 0)
-#define GLCONFIG_MRS			(1 << 1)
-#define GLCONFIG_SMEMBUSY		(1 << 5)
-#define GLCONFIG_LCR			(1 << 6)
-#define GLCONFIG_REARBEN		(1 << 7)
-#define GLCONFIG_CLKSHUTDOWN		(1 << 30)
-#define GLCONFIG_CKE			(1 << 31)
-
-/*
- * 0x80070000 - 0x8007FFFF: Reserved
- */
-
-/*
- * 0x80080000 - 0x8008FFFF: SRAM controller & PCMCIA
- */
-#define SMC_OFFSET			0x080000
-#define SMC_BASE			(EP93XX_AHB_BASE | SMC_OFFSET)
-
-#ifndef __ASSEMBLY__
-struct smc_regs {
-	uint32_t bcr0;
-	uint32_t bcr1;
-	uint32_t bcr2;
-	uint32_t bcr3;
-	uint32_t reserved0[2];
-	uint32_t bcr6;
-	uint32_t bcr7;
-#if defined(CONFIG_EP9315)
-	uint32_t pcattribute;
-	uint32_t pccommon;
-	uint32_t pcio;
-	uint32_t reserved1[5];
-	uint32_t pcmciactrl;
-#endif
-};
-#endif
-
-#define SMC_BCR_IDCY_SHIFT	0
-#define SMC_BCR_WST1_SHIFT	5
-#define SMC_BCR_BLE		(1 << 10)
-#define SMC_BCR_WST2_SHIFT	11
-#define SMC_BCR_MW_SHIFT	28
-
-/*
- * 0x80090000 - 0x8009FFFF: Boot ROM
- */
-
-/*
- * 0x800A0000 - 0x800AFFFF: IDE interface
- */
-
-/*
- * 0x800B0000 - 0x800BFFFF: VIC1
- */
-
-/*
- * 0x800C0000 - 0x800CFFFF: VIC2
- */
-
-/*
- * 0x800D0000 - 0x800FFFFF: Reserved
- */
-
-/*
- * 0x80800000 - 0x8080FFFF: Reserved
- */
-
-/*
- * 0x80810000 - 0x8081FFFF: Timers
- */
-#define TIMER_OFFSET		0x010000
-#define TIMER_BASE		(EP93XX_APB_BASE | TIMER_OFFSET)
-
-#ifndef __ASSEMBLY__
-struct timer {
-	uint32_t load;
-	uint32_t value;
-	uint32_t control;
-	uint32_t clear;
-};
-
-struct timer4 {
-	uint32_t value_low;
-	uint32_t value_high;
-};
-
-struct timer_regs {
-	struct timer timer1;
-	uint32_t reserved0[4];
-	struct timer timer2;
-	uint32_t reserved1[12];
-	struct timer4 timer4;
-	uint32_t reserved2[6];
-	struct timer timer3;
-};
-#endif
-
-/*
- * 0x80820000 - 0x8082FFFF: I2S
- */
-#define I2S_OFFSET		0x020000
-#define I2S_BASE		(EP93XX_APB_BASE | I2S_OFFSET)
-
-/*
- * 0x80830000 - 0x8083FFFF: Security
- */
-#define SECURITY_OFFSET		0x030000
-#define SECURITY_BASE		(EP93XX_APB_BASE | SECURITY_OFFSET)
-
-#define EXTENSIONID		(SECURITY_BASE + 0x2714)
-
-/*
- * 0x80840000 - 0x8084FFFF: GPIO
- */
-#define GPIO_OFFSET		0x040000
-#define GPIO_BASE		(EP93XX_APB_BASE | GPIO_OFFSET)
-
-#ifndef __ASSEMBLY__
-struct gpio_int {
-	uint32_t inttype1;
-	uint32_t inttype2;
-	uint32_t eoi;
-	uint32_t inten;
-	uint32_t intsts;
-	uint32_t rawintsts;
-	uint32_t db;
-};
-
-struct gpio_regs {
-	uint32_t padr;
-	uint32_t pbdr;
-	uint32_t pcdr;
-	uint32_t pddr;
-	uint32_t paddr;
-	uint32_t pbddr;
-	uint32_t pcddr;
-	uint32_t pdddr;
-	uint32_t pedr;
-	uint32_t peddr;
-	uint32_t reserved0[2];
-	uint32_t pfdr;
-	uint32_t pfddr;
-	uint32_t pgdr;
-	uint32_t pgddr;
-	uint32_t phdr;
-	uint32_t phddr;
-	uint32_t reserved1;
-	uint32_t finttype1;
-	uint32_t finttype2;
-	uint32_t reserved2;
-	struct gpio_int pfint;
-	uint32_t reserved3[10];
-	struct gpio_int paint;
-	struct gpio_int pbint;
-	uint32_t eedrive;
-};
-#endif
-
-/*
- * 0x80850000 - 0x8087FFFF: Reserved
- */
-
-/*
- * 0x80880000 - 0x8088FFFF: AAC
- */
-#define AAC_OFFSET		0x080000
-#define AAC_BASE		(EP93XX_APB_BASE | AAC_OFFSET)
-
-/*
- * 0x80890000 - 0x8089FFFF: Reserved
- */
-
-/*
- * 0x808A0000 - 0x808AFFFF: SPI
- */
-#define SPI_OFFSET		0x0A0000
-#define SPI_BASE		(EP93XX_APB_BASE | SPI_OFFSET)
-
-/*
- * 0x808B0000 - 0x808BFFFF: IrDA
- */
-#define IRDA_OFFSET		0x0B0000
-#define IRDA_BASE		(EP93XX_APB_BASE | IRDA_OFFSET)
-
-/*
- * 0x808C0000 - 0x808CFFFF: UART1
- */
-#define UART1_OFFSET		0x0C0000
-#define UART1_BASE		(EP93XX_APB_BASE | UART1_OFFSET)
-
-/*
- * 0x808D0000 - 0x808DFFFF: UART2
- */
-#define UART2_OFFSET		0x0D0000
-#define UART2_BASE		(EP93XX_APB_BASE | UART2_OFFSET)
-
-/*
- * 0x808E0000 - 0x808EFFFF: UART3
- */
-#define UART3_OFFSET		0x0E0000
-#define UART3_BASE		(EP93XX_APB_BASE | UART3_OFFSET)
-
-/*
- * 0x808F0000 - 0x808FFFFF: Key Matrix
- */
-#define KEY_OFFSET		0x0F0000
-#define KEY_BASE		(EP93XX_APB_BASE | KEY_OFFSET)
-
-/*
- * 0x80900000 - 0x8090FFFF: Touchscreen
- */
-#define TOUCH_OFFSET		0x900000
-#define TOUCH_BASE		(EP93XX_APB_BASE | TOUCH_OFFSET)
-
-/*
- * 0x80910000 - 0x8091FFFF: Pulse Width Modulation
- */
-#define PWM_OFFSET		0x910000
-#define PWM_BASE		(EP93XX_APB_BASE | PWM_OFFSET)
-
-/*
- * 0x80920000 - 0x8092FFFF: Real time clock
- */
-#define RTC_OFFSET		0x920000
-#define RTC_BASE		(EP93XX_APB_BASE | RTC_OFFSET)
-
-/*
- * 0x80930000 - 0x8093FFFF: Syscon
- */
-#define SYSCON_OFFSET		0x930000
-#define SYSCON_BASE		(EP93XX_APB_BASE | SYSCON_OFFSET)
-
-#ifndef __ASSEMBLY__
-struct syscon_regs {
-	uint32_t pwrsts;
-	uint32_t pwrcnt;
-	uint32_t halt;
-	uint32_t stby;
-	uint32_t reserved0[2];
-	uint32_t teoi;
-	uint32_t stfclr;
-	uint32_t clkset1;
-	uint32_t clkset2;
-	uint32_t reserved1[6];
-	uint32_t scratch0;
-	uint32_t scratch1;
-	uint32_t reserved2[2];
-	uint32_t apbwait;
-	uint32_t bustmstrarb;
-	uint32_t bootmodeclr;
-	uint32_t reserved3[9];
-	uint32_t devicecfg;
-	uint32_t vidclkdiv;
-	uint32_t mirclkdiv;
-	uint32_t i2sclkdiv;
-	uint32_t keytchclkdiv;
-	uint32_t chipid;
-	uint32_t reserved4;
-	uint32_t syscfg;
-	uint32_t reserved5[8];
-	uint32_t sysswlock;
-};
-#else
-#define SYSCON_SCRATCH0		(SYSCON_BASE + 0x0040)
-#endif
-
-#define SYSCON_PWRCNT_UART_BAUD			(1 << 29)
-
-#define SYSCON_CLKSET_PLL_X2IPD_SHIFT		0
-#define SYSCON_CLKSET_PLL_X2FBD2_SHIFT		5
-#define SYSCON_CLKSET_PLL_X1FBD1_SHIFT		11
-#define SYSCON_CLKSET_PLL_PS_SHIFT		16
-#define SYSCON_CLKSET1_PCLK_DIV_SHIFT		18
-#define SYSCON_CLKSET1_HCLK_DIV_SHIFT		20
-#define SYSCON_CLKSET1_NBYP1			(1 << 23)
-#define SYSCON_CLKSET1_FCLK_DIV_SHIFT		25
-
-#define SYSCON_CLKSET2_PLL2_EN			(1 << 18)
-#define SYSCON_CLKSET2_NBYP2			(1 << 19)
-#define SYSCON_CLKSET2_USB_DIV_SHIFT		28
-
-#define SYSCON_CHIPID_REV_MASK			0xF0000000
-#define SYSCON_DEVICECFG_SWRST			(1 << 31)
-
-/*
- * 0x80930000 - 0x8093FFFF: Watchdog Timer
- */
-#define WATCHDOG_OFFSET		0x940000
-#define WATCHDOG_BASE		(EP93XX_APB_BASE | WATCHDOG_OFFSET)
-
-/*
- * 0x80950000 - 0x9000FFFF: Reserved
- */
--- a/arch/arm/include/asm/arch-mx25/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx25/imx-regs.h
@@ -1,316 +0,0 @@
-/*
- * Copyright (C) 2009, DENX Software Engineering
- * Author: John Rigby <jcrigby@gmail.com
- *
- *   Based on arch-mx31/mx31-regs.h
- *	Copyright (C) 2009 Ilya Yanok,
- *		Emcraft Systems <yanok@emcraft.com>
- *   and arch-mx27/imx-regs.h
- *	Copyright (C) 2007 Pengutronix,
- *		Sascha Hauer <s.hauer@pengutronix.de>
- *	Copyright (C) 2009 Ilya Yanok,
- *		Emcraft Systems <yanok@emcraft.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _IMX_REGS_H
-#define _IMX_REGS_H
-
-#ifndef __ASSEMBLY__
-#ifdef CONFIG_FEC_MXC
-extern void mx25_fec_init_pins(void);
-#endif
-
-/* Clock Control Module (CCM) registers */
-struct ccm_regs {
-	u32 mpctl;	/* Core PLL Control */
-	u32 upctl;	/* USB PLL Control */
-	u32 cctl;	/* Clock Control */
-	u32 cgr0;	/* Clock Gating Control 0 */
-	u32 cgr1;	/* Clock Gating Control 1 */
-	u32 cgr2;	/* Clock Gating Control 2 */
-	u32 pcdr[4];	/* PER Clock Dividers */
-	u32 rcsr;	/* CCM Status */
-	u32 crdr;	/* CCM Reset and Debug */
-	u32 dcvr0;	/* DPTC Comparator Value 0 */
-	u32 dcvr1;	/* DPTC Comparator Value 1 */
-	u32 dcvr2;	/* DPTC Comparator Value 2 */
-	u32 dcvr3;	/* DPTC Comparator Value 3 */
-	u32 ltr0;	/* Load Tracking 0 */
-	u32 ltr1;	/* Load Tracking 1 */
-	u32 ltr2;	/* Load Tracking 2 */
-	u32 ltr3;	/* Load Tracking 3 */
-	u32 ltbr0;	/* Load Tracking Buffer 0 */
-	u32 ltbr1;	/* Load Tracking Buffer 1 */
-	u32 pcmr0;	/* Power Management Control 0 */
-	u32 pcmr1;	/* Power Management Control 1 */
-	u32 pcmr2;	/* Power Management Control 2 */
-	u32 mcr;	/* Miscellaneous Control */
-	u32 lpimr0;	/* Low Power Interrupt Mask 0 */
-	u32 lpimr1;	/* Low Power Interrupt Mask 1 */
-};
-
-/* Enhanced SDRAM Controller (ESDRAMC) registers */
-struct esdramc_regs {
-	u32 ctl0; 	/* control 0 */
-	u32 cfg0; 	/* configuration 0 */
-	u32 ctl1; 	/* control 1 */
-	u32 cfg1; 	/* configuration 1 */
-	u32 misc; 	/* miscellaneous */
-	u32 pad[3];
-	u32 cdly1;	/* Delay Line 1 configuration debug */
-	u32 cdly2;	/* delay line 2 configuration debug */
-	u32 cdly3;	/* delay line 3 configuration debug */
-	u32 cdly4;	/* delay line 4 configuration debug */
-	u32 cdly5;	/* delay line 5 configuration debug */
-	u32 cdlyl;	/* delay line cycle length debug */
-};
-
-/* GPIO registers */
-struct gpio_regs {
-	u32 dr;		/* data */
-	u32 dir;	/* direction */
-	u32 psr;	/* pad satus */
-	u32 icr1;	/* interrupt config 1 */
-	u32 icr2;	/* interrupt config 2 */
-	u32 imr;	/* interrupt mask */
-	u32 isr;	/* interrupt status */
-	u32 edge_sel;	/* edge select */
-};
-
-/* General Purpose Timer (GPT) registers */
-struct gpt_regs {
-	u32 ctrl;   	/* control */
-	u32 pre;    	/* prescaler */
-	u32 stat;   	/* status */
-	u32 intr;   	/* interrupt */
-	u32 cmp[3]; 	/* output compare 1-3 */
-	u32 capt[2];	/* input capture 1-2 */
-	u32 counter;	/* counter */
-};
-
-/* Watchdog Timer (WDOG) registers */
-struct wdog_regs {
-	u32 wcr;	/* Control */
-	u32 wsr;	/* Service */
-	u32 wrsr;	/* Reset Status */
-	u32 wicr;	/* Interrupt Control */
-	u32 wmcr;	/* Misc Control */
-};
-
-/* IIM control registers */
-struct iim_regs {
-	u32 iim_stat;
-	u32 iim_statm;
-	u32 iim_err;
-	u32 iim_emask;
-	u32 iim_fctl;
-	u32 iim_ua;
-	u32 iim_la;
-	u32 iim_sdat;
-	u32 iim_prev;
-	u32 iim_srev;
-	u32 iim_prog_p;
-	u32 res1[0x1f5];
-	u32 iim_bank_area0[0x20];
-	u32 res2[0xe0];
-	u32 iim_bank_area1[0x20];
-	u32 res3[0xe0];
-	u32 iim_bank_area2[0x20];
-};
-#endif
-
-/* AIPS 1 */
-#define IMX_AIPS1_BASE		(0x43F00000)
-#define IMX_MAX_BASE		(0x43F04000)
-#define IMX_CLKCTL_BASE		(0x43F08000)
-#define IMX_ETB_SLOT4_BASE	(0x43F0C000)
-#define IMX_ETB_SLOT5_BASE	(0x43F10000)
-#define IMX_ECT_CTIO_BASE	(0x43F18000)
-#define IMX_I2C_BASE		(0x43F80000)
-#define IMX_I2C3_BASE		(0x43F84000)
-#define IMX_CAN1_BASE		(0x43F88000)
-#define IMX_CAN2_BASE		(0x43F8C000)
-#define IMX_UART1_BASE		(0x43F90000)
-#define IMX_UART2_BASE		(0x43F94000)
-#define IMX_I2C2_BASE		(0x43F98000)
-#define IMX_OWIRE_BASE		(0x43F9C000)
-#define IMX_CSPI1_BASE		(0x43FA4000)
-#define IMX_KPP_BASE		(0x43FA8000)
-#define IMX_IOPADMUX_BASE	(0x43FAC000)
-#define IMX_IOPADCTL_BASE	(0x43FAC22C)
-#define IMX_IOPADGRPCTL_BASE	(0x43FAC418)
-#define IMX_IOPADINPUTSEL_BASE	(0x43FAC460)
-#define IMX_AUDMUX_BASE		(0x43FB0000)
-#define IMX_ECT_IP1_BASE	(0x43FB8000)
-#define IMX_ECT_IP2_BASE	(0x43FBC000)
-
-/* SPBA */
-#define IMX_SPBA_BASE		(0x50000000)
-#define IMX_CSPI3_BASE		(0x50004000)
-#define IMX_UART4_BASE		(0x50008000)
-#define IMX_UART3_BASE		(0x5000C000)
-#define IMX_CSPI2_BASE		(0x50010000)
-#define IMX_SSI2_BASE		(0x50014000)
-#define IMX_ESAI_BASE		(0x50018000)
-#define IMX_ATA_DMA_BASE	(0x50020000)
-#define IMX_SIM1_BASE		(0x50024000)
-#define IMX_SIM2_BASE		(0x50028000)
-#define IMX_UART5_BASE		(0x5002C000)
-#define IMX_TSC_BASE		(0x50030000)
-#define IMX_SSI1_BASE		(0x50034000)
-#define IMX_FEC_BASE		(0x50038000)
-#define IMX_SPBA_CTRL_BASE	(0x5003C000)
-
-/* AIPS 2 */
-#define IMX_AIPS2_BASE		(0x53F00000)
-#define IMX_CCM_BASE		(0x53F80000)
-#define IMX_GPT4_BASE		(0x53F84000)
-#define IMX_GPT3_BASE		(0x53F88000)
-#define IMX_GPT2_BASE		(0x53F8C000)
-#define IMX_GPT1_BASE		(0x53F90000)
-#define IMX_EPIT1_BASE		(0x53F94000)
-#define IMX_EPIT2_BASE		(0x53F98000)
-#define IMX_GPIO4_BASE		(0x53F9C000)
-#define IMX_PWM2_BASE		(0x53FA0000)
-#define IMX_GPIO3_BASE		(0x53FA4000)
-#define IMX_PWM3_BASE		(0x53FA8000)
-#define IMX_SCC_BASE		(0x53FAC000)
-#define IMX_SCM_BASE		(0x53FAE000)
-#define IMX_SMN_BASE		(0x53FAF000)
-#define IMX_RNGD_BASE		(0x53FB0000)
-#define IMX_MMC_SDHC1_BASE	(0x53FB4000)
-#define IMX_MMC_SDHC2_BASE	(0x53FB8000)
-#define IMX_LCDC_BASE		(0x53FBC000)
-#define IMX_SLCDC_BASE		(0x53FC0000)
-#define IMX_PWM4_BASE		(0x53FC8000)
-#define IMX_GPIO1_BASE		(0x53FCC000)
-#define IMX_GPIO2_BASE		(0x53FD0000)
-#define IMX_SDMA_BASE		(0x53FD4000)
-#define IMX_WDT_BASE		(0x53FDC000)
-#define IMX_PWM1_BASE		(0x53FE0000)
-#define IMX_RTIC_BASE		(0x53FEC000)
-#define IMX_IIM_BASE		(0x53FF0000)
-#define IMX_USB_BASE		(0x53FF4000)
-#define IMX_CSI_BASE		(0x53FF8000)
-#define IMX_DRYICE_BASE		(0x53FFC000)
-
-#define IMX_ARM926_ROMPATCH	(0x60000000)
-#define IMX_ARM926_ASIC		(0x68000000)
-
-/* 128K Internal Static RAM */
-#define IMX_RAM_BASE		(0x78000000)
-
-/* SDRAM BANKS */
-#define IMX_SDRAM_BANK0_BASE	(0x80000000)
-#define IMX_SDRAM_BANK1_BASE	(0x90000000)
-
-#define IMX_WEIM_CS0		(0xA0000000)
-#define IMX_WEIM_CS1		(0xA8000000)
-#define IMX_WEIM_CS2		(0xB0000000)
-#define IMX_WEIM_CS3		(0xB2000000)
-#define IMX_WEIM_CS4		(0xB4000000)
-#define IMX_ESDRAMC_BASE	(0xB8001000)
-#define IMX_WEIM_CTRL_BASE	(0xB8002000)
-#define IMX_M3IF_CTRL_BASE	(0xB8003000)
-#define IMX_EMI_CTRL_BASE	(0xB8004000)
-
-/* NAND Flash Controller */
-#define IMX_NFC_BASE		(0xBB000000)
-#define NFC_BASE_ADDR		IMX_NFC_BASE
-
-/* CCM bitfields */
-#define CCM_PLL_MFI_SHIFT	10
-#define CCM_PLL_MFI_MASK	0xf
-#define CCM_PLL_MFN_SHIFT	0
-#define CCM_PLL_MFN_MASK	0x3ff
-#define CCM_PLL_MFD_SHIFT	16
-#define CCM_PLL_MFD_MASK	0x3ff
-#define CCM_PLL_PD_SHIFT	26
-#define CCM_PLL_PD_MASK		0xf
-#define CCM_CCTL_ARM_DIV_SHIFT	30
-#define CCM_CCTL_ARM_DIV_MASK	3
-#define CCM_CCTL_AHB_DIV_SHIFT	28
-#define CCM_CCTL_AHB_DIV_MASK	3
-#define CCM_CCTL_ARM_SRC	(1 << 14)
-#define CCM_CGR1_GPT1		(1 << 19)
-#define CCM_PERCLK_REG(clk)	(clk / 4)
-#define CCM_PERCLK_SHIFT(clk)	(8 * (clk % 4))
-#define CCM_PERCLK_MASK		0x3f
-#define CCM_RCSR_NF_16BIT_SEL	(1 << 14)
-#define CCM_RCSR_NF_PS(v)	((v >> 26) & 3)
-
-/* ESDRAM Controller register bitfields */
-#define ESDCTL_PRCT(x)		(((x) & 0x3f) << 0)
-#define ESDCTL_BL		(1 << 7)
-#define ESDCTL_FP		(1 << 8)
-#define ESDCTL_PWDT(x)		(((x) & 3) << 10)
-#define ESDCTL_SREFR(x)		(((x) & 7) << 13)
-#define ESDCTL_DSIZ_16_UPPER	(0 << 16)
-#define ESDCTL_DSIZ_16_LOWER	(1 << 16)
-#define ESDCTL_DSIZ_32		(2 << 16)
-#define ESDCTL_COL8		(0 << 20)
-#define ESDCTL_COL9		(1 << 20)
-#define ESDCTL_COL10		(2 << 20)
-#define ESDCTL_ROW11		(0 << 24)
-#define ESDCTL_ROW12		(1 << 24)
-#define ESDCTL_ROW13		(2 << 24)
-#define ESDCTL_ROW14		(3 << 24)
-#define ESDCTL_ROW15		(4 << 24)
-#define ESDCTL_SP		(1 << 27)
-#define ESDCTL_SMODE_NORMAL	(0 << 28)
-#define ESDCTL_SMODE_PRECHARGE	(1 << 28)
-#define ESDCTL_SMODE_AUTO_REF	(2 << 28)
-#define ESDCTL_SMODE_LOAD_MODE	(3 << 28)
-#define ESDCTL_SMODE_MAN_REF	(4 << 28)
-#define ESDCTL_SDE		(1 << 31)
-
-#define ESDCFG_TRC(x)		(((x) & 0xf) << 0)
-#define ESDCFG_TRCD(x)		(((x) & 0x7) << 4)
-#define ESDCFG_TCAS(x)		(((x) & 0x3) << 8)
-#define ESDCFG_TRRD(x)		(((x) & 0x3) << 10)
-#define ESDCFG_TRAS(x)		(((x) & 0x7) << 12)
-#define ESDCFG_TWR		(1 << 15)
-#define ESDCFG_TMRD(x)		(((x) & 0x3) << 16)
-#define ESDCFG_TRP(x)		(((x) & 0x3) << 18)
-#define ESDCFG_TWTR		(1 << 20)
-#define ESDCFG_TXP(x)		(((x) & 0x3) << 21)
-
-#define ESDMISC_RST		(1 << 1)
-#define ESDMISC_MDDREN		(1 << 2)
-#define ESDMISC_MDDR_DL_RST	(1 << 3)
-#define ESDMISC_MDDR_MDIS	(1 << 4)
-#define ESDMISC_LHD		(1 << 5)
-#define ESDMISC_MA10_SHARE	(1 << 6)
-#define ESDMISC_SDRAM_RDY	(1 << 31)
-
-/* GPT bits */
-#define GPT_CTRL_SWR		(1 << 15)	/* Software reset */
-#define GPT_CTRL_FRR		(1 << 9)	/* Freerun / restart */
-#define GPT_CTRL_CLKSOURCE_32	(4 << 6)	/* Clock source	*/
-#define GPT_CTRL_TEN		1		/* Timer enable	*/
-
-/* WDOG enable */
-#define WCR_WDE 0x04
-
-/* FUSE bank offsets */
-#define IIM0_MAC		0x1a
-
-#endif				/* _IMX_REGS_H */
--- a/arch/arm/include/asm/arch-mx25/imx25-pinmux.h
+++ b/arch/arm/include/asm/arch-mx25/imx25-pinmux.h
@@ -1,421 +0,0 @@
-/*
- * iopin settings are controlled by four different sets of registers
- *	iopad mux control
- *	individual iopad setup (voltage select, pull/keep, drive strength ...)
- *	group iopad setup (same as above but for groups of signals)
- *	input select when multiple inputs are possible
- */
-
-/*
- * software pad mux control
- */
-/* SW Input On (Loopback) */
-#define MX25_PIN_MUX_SION		(1 << 4)
-/* MUX Mode (0-7) */
-#define MX25_PIN_MUX_MODE(mode)		((mode & 0x7) << 0)
-struct iomuxc_mux_ctl {
-	u32 gpr1;
-	u32 observe_int_mux;
-	u32 pad_a10;
-	u32 pad_a13;
-	u32 pad_a14;
-	u32 pad_a15;
-	u32 pad_a16;
-	u32 pad_a17;
-	u32 pad_a18;
-	u32 pad_a19;
-	u32 pad_a20;
-	u32 pad_a21;
-	u32 pad_a22;
-	u32 pad_a23;
-	u32 pad_a24;
-	u32 pad_a25;
-	u32 pad_eb0;
-	u32 pad_eb1;
-	u32 pad_oe;
-	u32 pad_cs0;
-	u32 pad_cs1;
-	u32 pad_cs4;
-	u32 pad_cs5;
-	u32 pad_nf_ce0;
-	u32 pad_ecb;
-	u32 pad_lba;
-	u32 pad_bclk;
-	u32 pad_rw;
-	u32 pad_nfwe_b;
-	u32 pad_nfre_b;
-	u32 pad_nfale;
-	u32 pad_nfcle;
-	u32 pad_nfwp_b;
-	u32 pad_nfrb;
-	u32 pad_d15;
-	u32 pad_d14;
-	u32 pad_d13;
-	u32 pad_d12;
-	u32 pad_d11;
-	u32 pad_d10;
-	u32 pad_d9;
-	u32 pad_d8;
-	u32 pad_d7;
-	u32 pad_d6;
-	u32 pad_d5;
-	u32 pad_d4;
-	u32 pad_d3;
-	u32 pad_d2;
-	u32 pad_d1;
-	u32 pad_d0;
-	u32 pad_ld0;
-	u32 pad_ld1;
-	u32 pad_ld2;
-	u32 pad_ld3;
-	u32 pad_ld4;
-	u32 pad_ld5;
-	u32 pad_ld6;
-	u32 pad_ld7;
-	u32 pad_ld8;
-	u32 pad_ld9;
-	u32 pad_ld10;
-	u32 pad_ld11;
-	u32 pad_ld12;
-	u32 pad_ld13;
-	u32 pad_ld14;
-	u32 pad_ld15;
-	u32 pad_hsync;
-	u32 pad_vsync;
-	u32 pad_lsclk;
-	u32 pad_oe_acd;
-	u32 pad_contrast;
-	u32 pad_pwm;
-	u32 pad_csi_d2;
-	u32 pad_csi_d3;
-	u32 pad_csi_d4;
-	u32 pad_csi_d5;
-	u32 pad_csi_d6;
-	u32 pad_csi_d7;
-	u32 pad_csi_d8;
-	u32 pad_csi_d9;
-	u32 pad_csi_mclk;
-	u32 pad_csi_vsync;
-	u32 pad_csi_hsync;
-	u32 pad_csi_pixclk;
-	u32 pad_i2c1_clk;
-	u32 pad_i2c1_dat;
-	u32 pad_cspi1_mosi;
-	u32 pad_cspi1_miso;
-	u32 pad_cspi1_ss0;
-	u32 pad_cspi1_ss1;
-	u32 pad_cspi1_sclk;
-	u32 pad_cspi1_rdy;
-	u32 pad_uart1_rxd;
-	u32 pad_uart1_txd;
-	u32 pad_uart1_rts;
-	u32 pad_uart1_cts;
-	u32 pad_uart2_rxd;
-	u32 pad_uart2_txd;
-	u32 pad_uart2_rts;
-	u32 pad_uart2_cts;
-	u32 pad_sd1_cmd;
-	u32 pad_sd1_clk;
-	u32 pad_sd1_data0;
-	u32 pad_sd1_data1;
-	u32 pad_sd1_data2;
-	u32 pad_sd1_data3;
-	u32 pad_kpp_row0;
-	u32 pad_kpp_row1;
-	u32 pad_kpp_row2;
-	u32 pad_kpp_row3;
-	u32 pad_kpp_col0;
-	u32 pad_kpp_col1;
-	u32 pad_kpp_col2;
-	u32 pad_kpp_col3;
-	u32 pad_fec_mdc;
-	u32 pad_fec_mdio;
-	u32 pad_fec_tdata0;
-	u32 pad_fec_tdata1;
-	u32 pad_fec_tx_en;
-	u32 pad_fec_rdata0;
-	u32 pad_fec_rdata1;
-	u32 pad_fec_rx_dv;
-	u32 pad_fec_tx_clk;
-	u32 pad_rtck;
-	u32 pad_de_b;
-	u32 pad_gpio_a;
-	u32 pad_gpio_b;
-	u32 pad_gpio_c;
-	u32 pad_gpio_d;
-	u32 pad_gpio_e;
-	u32 pad_gpio_f;
-	u32 pad_ext_armclk;
-	u32 pad_upll_bypclk;
-	u32 pad_vstby_req;
-	u32 pad_vstby_ack;
-	u32 pad_power_fail;
-	u32 pad_clko;
-	u32 pad_boot_mode0;
-	u32 pad_boot_mode1;
-};
-
-/*
- * software pad control
- */
-/* Select 3.3 or 1.8 volts */
-#define MX25_PIN_PAD_CTL_DVS_33			(0 << 13)
-#define MX25_PIN_PAD_CTL_DVS_18			(1 << 13)
-/* Enable hysteresis */
-#define MX25_PIN_PAD_CTL_HYS			(1 << 8)
-/* Enable pull/keeper */
-#define MX25_PIN_PAD_CTL_PKE			(1 << 7)
-/* 0 - keeper / 1 - pull */
-#define MX25_PIN_PAD_CTL_PUE			(1 << 6)
-/* pull up/down strength */
-#define MX25_PIN_PAD_CTL_100K_PD		(0 << 4)
-#define MX25_PIN_PAD_CTL_47K_PU			(1 << 4)
-#define MX25_PIN_PAD_CTL_100K_PU		(2 << 4)
-#define MX25_PIN_PAD_CTL_22K_PU			(3 << 4)
-/* open drain control */
-#define MX25_PIN_PAD_CTL_OD			(1 << 3)
-/* drive strength */
-#define MX25_PIN_PAD_CTL_DS_NOM			(0 << 1)
-#define MX25_PIN_PAD_CTL_DS_HIGH		(1 << 1)
-#define MX25_PIN_PAD_CTL_DS_MAX			(2 << 1)
-#define MX25_PIN_PAD_CTL_DS_MAX11		(3 << 1)
-/* slew rate */
-#define MX25_PIN_PAD_CTL_SRE_SLOW		(0 << 0)
-#define MX25_PIN_PAD_CTL_SRE_FAST		(1 << 0)
-struct  iomuxc_pad_ctl {
-	u32 pad_a13;
-	u32 pad_a14;
-	u32 pad_a15;
-	u32 pad_a17;
-	u32 pad_a18;
-	u32 pad_a19;
-	u32 pad_a20;
-	u32 pad_a21;
-	u32 pad_a23;
-	u32 pad_a24;
-	u32 pad_a25;
-	u32 pad_eb0;
-	u32 pad_eb1;
-	u32 pad_oe;
-	u32 pad_cs4;
-	u32 pad_cs5;
-	u32 pad_nf_ce0;
-	u32 pad_ecb;
-	u32 pad_lba;
-	u32 pad_rw;
-	u32 pad_nfrb;
-	u32 pad_d15;
-	u32 pad_d14;
-	u32 pad_d13;
-	u32 pad_d12;
-	u32 pad_d11;
-	u32 pad_d10;
-	u32 pad_d9;
-	u32 pad_d8;
-	u32 pad_d7;
-	u32 pad_d6;
-	u32 pad_d5;
-	u32 pad_d4;
-	u32 pad_d3;
-	u32 pad_d2;
-	u32 pad_d1;
-	u32 pad_d0;
-	u32 pad_ld0;
-	u32 pad_ld1;
-	u32 pad_ld2;
-	u32 pad_ld3;
-	u32 pad_ld4;
-	u32 pad_ld5;
-	u32 pad_ld6;
-	u32 pad_ld7;
-	u32 pad_ld8;
-	u32 pad_ld9;
-	u32 pad_ld10;
-	u32 pad_ld11;
-	u32 pad_ld12;
-	u32 pad_ld13;
-	u32 pad_ld14;
-	u32 pad_ld15;
-	u32 pad_hsync;
-	u32 pad_vsync;
-	u32 pad_lsclk;
-	u32 pad_oe_acd;
-	u32 pad_contrast;
-	u32 pad_pwm;
-	u32 pad_csi_d2;
-	u32 pad_csi_d3;
-	u32 pad_csi_d4;
-	u32 pad_csi_d5;
-	u32 pad_csi_d6;
-	u32 pad_csi_d7;
-	u32 pad_csi_d8;
-	u32 pad_csi_d9;
-	u32 pad_csi_mclk;
-	u32 pad_csi_vsync;
-	u32 pad_csi_hsync;
-	u32 pad_csi_pixclk;
-	u32 pad_i2c1_clk;
-	u32 pad_i2c1_dat;
-	u32 pad_cspi1_mosi;
-	u32 pad_cspi1_miso;
-	u32 pad_cspi1_ss0;
-	u32 pad_cspi1_ss1;
-	u32 pad_cspi1_sclk;
-	u32 pad_cspi1_rdy;
-	u32 pad_uart1_rxd;
-	u32 pad_uart1_txd;
-	u32 pad_uart1_rts;
-	u32 pad_uart1_cts;
-	u32 pad_uart2_rxd;
-	u32 pad_uart2_txd;
-	u32 pad_uart2_rts;
-	u32 pad_uart2_cts;
-	u32 pad_sd1_cmd;
-	u32 pad_sd1_clk;
-	u32 pad_sd1_data0;
-	u32 pad_sd1_data1;
-	u32 pad_sd1_data2;
-	u32 pad_sd1_data3;
-	u32 pad_kpp_row0;
-	u32 pad_kpp_row1;
-	u32 pad_kpp_row2;
-	u32 pad_kpp_row3;
-	u32 pad_kpp_col0;
-	u32 pad_kpp_col1;
-	u32 pad_kpp_col2;
-	u32 pad_kpp_col3;
-	u32 pad_fec_mdc;
-	u32 pad_fec_mdio;
-	u32 pad_fec_tdata0;
-	u32 pad_fec_tdata1;
-	u32 pad_fec_tx_en;
-	u32 pad_fec_rdata0;
-	u32 pad_fec_rdata1;
-	u32 pad_fec_rx_dv;
-	u32 pad_fec_tx_clk;
-	u32 pad_rtck;
-	u32 pad_tdo;
-	u32 pad_de_b;
-	u32 pad_gpio_a;
-	u32 pad_gpio_b;
-	u32 pad_gpio_c;
-	u32 pad_gpio_d;
-	u32 pad_gpio_e;
-	u32 pad_gpio_f;
-	u32 pad_vstby_req;
-	u32 pad_vstby_ack;
-	u32 pad_power_fail;
-	u32 pad_clko;
-};
-
-
-/*
- * Pad group drive strength and voltage select
- * Same fields as iomuxc_pad_ctl plus ddr type
- */
-/* Select DDR type */
-#define MX25_PIN_PAD_CTL_DDR_18			(0 << 11)
-#define MX25_PIN_PAD_CTL_DDR_33			(1 << 11)
-#define MX25_PIN_PAD_CTL_DDR_MAX		(2 << 11)
-struct iomuxc_pad_grp_ctl {
-	u32 grp_dvs_misc;
-	u32 grp_dse_fec;
-	u32 grp_dvs_jtag;
-	u32 grp_dse_nfc;
-	u32 grp_dse_csi;
-	u32 grp_dse_weim;
-	u32 grp_dse_ddr;
-	u32 grp_dvs_crm;
-	u32 grp_dse_kpp;
-	u32 grp_dse_sdhc1;
-	u32 grp_dse_lcd;
-	u32 grp_dse_uart;
-	u32 grp_dvs_nfc;
-	u32 grp_dvs_csi;
-	u32 grp_dse_cspi1;
-	u32 grp_ddrtype;
-	u32 grp_dvs_sdhc1;
-	u32 grp_dvs_lcd;
-};
-
-/*
- * Pad input select control
- * Select which pad to connect to an input port
- * where multiple pads can function as given input
- */
-#define MX25_PAD_INPUT_SELECT_DAISY(in)		((in & 0x7) << 0)
-struct iomuxc_pad_input_select {
-	u32 audmux_p4_input_da_amx;
-	u32 audmux_p4_input_db_amx;
-	u32 audmux_p4_input_rxclk_amx;
-	u32 audmux_p4_input_rxfs_amx;
-	u32 audmux_p4_input_txclk_amx;
-	u32 audmux_p4_input_txfs_amx;
-	u32 audmux_p7_input_da_amx;
-	u32 audmux_p7_input_txfs_amx;
-	u32 can1_ipp_ind_canrx;
-	u32 can2_ipp_ind_canrx;
-	u32 csi_ipp_csi_d_0;
-	u32 csi_ipp_csi_d_1;
-	u32 cspi1_ipp_ind_ss3_b;
-	u32 cspi2_ipp_cspi_clk_in;
-	u32 cspi2_ipp_ind_dataready_b;
-	u32 cspi2_ipp_ind_miso;
-	u32 cspi2_ipp_ind_mosi;
-	u32 cspi2_ipp_ind_ss0_b;
-	u32 cspi2_ipp_ind_ss1_b;
-	u32 cspi3_ipp_cspi_clk_in;
-	u32 cspi3_ipp_ind_dataready_b;
-	u32 cspi3_ipp_ind_miso;
-	u32 cspi3_ipp_ind_mosi;
-	u32 cspi3_ipp_ind_ss0_b;
-	u32 cspi3_ipp_ind_ss1_b;
-	u32 cspi3_ipp_ind_ss2_b;
-	u32 cspi3_ipp_ind_ss3_b;
-	u32 esdhc1_ipp_dat4_in;
-	u32 esdhc1_ipp_dat5_in;
-	u32 esdhc1_ipp_dat6_in;
-	u32 esdhc1_ipp_dat7_in;
-	u32 esdhc2_ipp_card_clk_in;
-	u32 esdhc2_ipp_cmd_in;
-	u32 esdhc2_ipp_dat0_in;
-	u32 esdhc2_ipp_dat1_in;
-	u32 esdhc2_ipp_dat2_in;
-	u32 esdhc2_ipp_dat3_in;
-	u32 esdhc2_ipp_dat4_in;
-	u32 esdhc2_ipp_dat5_in;
-	u32 esdhc2_ipp_dat6_in;
-	u32 esdhc2_ipp_dat7_in;
-	u32 fec_fec_col;
-	u32 fec_fec_crs;
-	u32 fec_fec_rdata_2;
-	u32 fec_fec_rdata_3;
-	u32 fec_fec_rx_clk;
-	u32 fec_fec_rx_er;
-	u32 i2c2_ipp_scl_in;
-	u32 i2c2_ipp_sda_in;
-	u32 i2c3_ipp_scl_in;
-	u32 i2c3_ipp_sda_in;
-	u32 kpp_ipp_ind_col_4;
-	u32 kpp_ipp_ind_col_5;
-	u32 kpp_ipp_ind_col_6;
-	u32 kpp_ipp_ind_col_7;
-	u32 kpp_ipp_ind_row_4;
-	u32 kpp_ipp_ind_row_5;
-	u32 kpp_ipp_ind_row_6;
-	u32 kpp_ipp_ind_row_7;
-	u32 sim1_pin_sim_rcvd1_in;
-	u32 sim1_pin_sim_simpd1;
-	u32 sim1_sim_rcvd1_io;
-	u32 sim2_pin_sim_rcvd1_in;
-	u32 sim2_pin_sim_simpd1;
-	u32 sim2_sim_rcvd1_io;
-	u32 uart3_ipp_uart_rts_b;
-	u32 uart3_ipp_uart_rxd_mux;
-	u32 uart4_ipp_uart_rts_b;
-	u32 uart4_ipp_uart_rxd_mux;
-	u32 uart5_ipp_uart_rts_b;
-	u32 uart5_ipp_uart_rxd_mux;
-	u32 usb_top_ipp_ind_otg_usb_oc;
-	u32 usb_top_ipp_ind_uh2_usb_oc;
-};
--- a/arch/arm/include/asm/arch-mx51/asm-offsets.h
+++ b/arch/arm/include/asm/arch-mx51/asm-offsets.h
@@ -1,50 +0,0 @@
-/*
- * needed for arch/arm/cpu/arm_cortexa8/mx51/lowlevel_init.S
- *
- * These should be auto-generated
- */
-/* CCM */
-#define CLKCTL_CCR              0x00
-#define CLKCTL_CCDR             0x04
-#define CLKCTL_CSR              0x08
-#define CLKCTL_CCSR             0x0C
-#define CLKCTL_CACRR            0x10
-#define CLKCTL_CBCDR            0x14
-#define CLKCTL_CBCMR            0x18
-#define CLKCTL_CSCMR1           0x1C
-#define CLKCTL_CSCMR2           0x20
-#define CLKCTL_CSCDR1           0x24
-#define CLKCTL_CS1CDR           0x28
-#define CLKCTL_CS2CDR           0x2C
-#define CLKCTL_CDCDR            0x30
-#define CLKCTL_CHSCCDR          0x34
-#define CLKCTL_CSCDR2           0x38
-#define CLKCTL_CSCDR3           0x3C
-#define CLKCTL_CSCDR4           0x40
-#define CLKCTL_CWDR             0x44
-#define CLKCTL_CDHIPR           0x48
-#define CLKCTL_CDCR             0x4C
-#define CLKCTL_CTOR             0x50
-#define CLKCTL_CLPCR            0x54
-#define CLKCTL_CISR             0x58
-#define CLKCTL_CIMR             0x5C
-#define CLKCTL_CCOSR            0x60
-#define CLKCTL_CGPR             0x64
-#define CLKCTL_CCGR0            0x68
-#define CLKCTL_CCGR1            0x6C
-#define CLKCTL_CCGR2            0x70
-#define CLKCTL_CCGR3            0x74
-#define CLKCTL_CCGR4            0x78
-#define CLKCTL_CCGR5            0x7C
-#define CLKCTL_CCGR6            0x80
-#define CLKCTL_CMEOR            0x84
-
-/* DPLL */
-#define PLL_DP_CTL	0x00
-#define PLL_DP_CONFIG	0x04
-#define PLL_DP_OP	0x08
-#define PLL_DP_MFD	0x0C
-#define PLL_DP_MFN	0x10
-#define PLL_DP_HFS_OP	0x1C
-#define PLL_DP_HFS_MFD	0x20
-#define PLL_DP_HFS_MFN	0x24
--- a/arch/arm/include/asm/arch-mx51/clock.h
+++ b/arch/arm/include/asm/arch-mx51/clock.h
@@ -1,43 +0,0 @@
-/*
- * (C) Copyright 2009
- * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARCH_CLOCK_H
-#define __ASM_ARCH_CLOCK_H
-
-enum mxc_clock {
-	MXC_ARM_CLK = 0,
-	MXC_AHB_CLK,
-	MXC_IPG_CLK,
-	MXC_IPG_PERCLK,
-	MXC_UART_CLK,
-	MXC_CSPI_CLK,
-	MXC_FEC_CLK,
-};
-
-unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref);
-
-u32 imx_get_uartclk(void);
-u32 imx_get_fecclk(void);
-unsigned int mxc_get_clock(enum mxc_clock clk);
-
-#endif /* __ASM_ARCH_CLOCK_H */
--- a/arch/arm/include/asm/arch-mx51/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx51/crm_regs.h
@@ -1,192 +0,0 @@
-/*
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__
-#define __ARCH_ARM_MACH_MX51_CRM_REGS_H__
-
-#define MXC_CCM_BASE	CCM_BASE_ADDR
-
-/* DPLL register mapping structure */
-struct mxc_pll_reg {
-	u32 ctrl;
-	u32 config;
-	u32 op;
-	u32 mfd;
-	u32 mfn;
-	u32 mfn_minus;
-	u32 mfn_plus;
-	u32 hfs_op;
-	u32 hfs_mfd;
-	u32 hfs_mfn;
-	u32 mfn_togc;
-	u32 destat;
-};
-
-/* Register maping of CCM*/
-struct mxc_ccm_reg {
-	u32 ccr;	/* 0x0000 */
-	u32 ccdr;
-	u32 csr;
-	u32 ccsr;
-	u32 cacrr;	/* 0x0010*/
-	u32 cbcdr;
-	u32 cbcmr;
-	u32 cscmr1;
-	u32 cscmr2;	/* 0x0020 */
-	u32 cscdr1;
-	u32 cs1cdr;
-	u32 cs2cdr;
-	u32 cdcdr;	/* 0x0030 */
-	u32 chscdr;
-	u32 cscdr2;
-	u32 cscdr3;
-	u32 cscdr4;	/* 0x0040 */
-	u32 cwdr;
-	u32 cdhipr;
-	u32 cdcr;
-	u32 ctor;	/* 0x0050 */
-	u32 clpcr;
-	u32 cisr;
-	u32 cimr;
-	u32 ccosr;	/* 0x0060 */
-	u32 cgpr;
-	u32 CCGR0;
-	u32 CCGR1;
-	u32 CCGR2;	/* 0x0070 */
-	u32 CCGR3;
-	u32 CCGR4;
-	u32 CCGR5;
-	u32 CCGR6;	/* 0x0080 */
-	u32 cmeor;
-};
-
-/* Define the bits in register CACRR */
-#define MXC_CCM_CACRR_ARM_PODF_OFFSET		0
-#define MXC_CCM_CACRR_ARM_PODF_MASK		0x7
-
-/* Define the bits in register CBCDR */
-#define MXC_CCM_CBCDR_EMI_CLK_SEL		(0x1 << 26)
-#define MXC_CCM_CBCDR_PERIPH_CLK_SEL		(0x1 << 25)
-#define MXC_CCM_CBCDR_EMI_PODF_OFFSET		22
-#define MXC_CCM_CBCDR_EMI_PODF_MASK		(0x7 << 22)
-#define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET		19
-#define MXC_CCM_CBCDR_AXI_B_PODF_MASK		(0x7 << 19)
-#define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET		16
-#define MXC_CCM_CBCDR_AXI_A_PODF_MASK		(0x7 << 16)
-#define MXC_CCM_CBCDR_NFC_PODF_OFFSET		13
-#define MXC_CCM_CBCDR_NFC_PODF_MASK		(0x7 << 13)
-#define MXC_CCM_CBCDR_AHB_PODF_OFFSET		10
-#define MXC_CCM_CBCDR_AHB_PODF_MASK		(0x7 << 10)
-#define MXC_CCM_CBCDR_IPG_PODF_OFFSET		8
-#define MXC_CCM_CBCDR_IPG_PODF_MASK		(0x3 << 8)
-#define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET	6
-#define MXC_CCM_CBCDR_PERCLK_PRED1_MASK		(0x3 << 6)
-#define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET	3
-#define MXC_CCM_CBCDR_PERCLK_PRED2_MASK		(0x7 << 3)
-#define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET	0
-#define MXC_CCM_CBCDR_PERCLK_PODF_MASK		0x7
-
-/* Define the bits in register CSCMR1 */
-#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET		30
-#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK		(0x3 << 30)
-#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET		28
-#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK		(0x3 << 28)
-#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET		26
-#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL			(0x1 << 26)
-#define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET		24
-#define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK		(0x3 << 24)
-#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET		22
-#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK		(0x3 << 22)
-#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET	20
-#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK	(0x3 << 20)
-#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL			(0x1 << 19)
-#define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL			(0x1 << 18)
-#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET	16
-#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK	(0x3 << 16)
-#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET		14
-#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK		(0x3 << 14)
-#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET		12
-#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK		(0x3 << 12)
-#define MXC_CCM_CSCMR1_SSI3_CLK_SEL			(0x1 << 11)
-#define MXC_CCM_CSCMR1_VPU_RCLK_SEL			(0x1 << 10)
-#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET		8
-#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK		(0x3 << 8)
-#define MXC_CCM_CSCMR1_TVE_CLK_SEL			(0x1 << 7)
-#define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL			(0x1 << 6)
-#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET		4
-#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK		(0x3 << 4)
-#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET		2
-#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK		(0x3 << 2)
-#define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL		(0x1 << 1)
-#define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL		0x1
-
-/* Define the bits in register CSCDR2 */
-#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET		25
-#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK		(0x7 << 25)
-#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET		19
-#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK		(0x3F << 19)
-#define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET		16
-#define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK		(0x7 << 16)
-#define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET		9
-#define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK		(0x3F << 9)
-#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET		6
-#define MXC_CCM_CSCDR2_SLIMBUS_PRED_MASK		(0x7 << 6)
-#define MXC_CCM_CSCDR2_SLIMBUS_PODF_OFFSET		0
-#define MXC_CCM_CSCDR2_SLIMBUS_PODF_MASK		0x3F
-
-/* Define the bits in register CBCMR */
-#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET		14
-#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK		(0x3 << 14)
-#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET		12
-#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK		(0x3 << 12)
-#define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET		10
-#define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK			(0x3 << 10)
-#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET		8
-#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK		(0x3 << 8)
-#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET		6
-#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK		(0x3 << 6)
-#define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET		4
-#define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK			(0x3 << 4)
-#define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL		(0x1 << 1)
-#define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL		(0x1 << 0)
-
-/* Define the bits in register CSCDR1 */
-#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET	22
-#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK	(0x7 << 22)
-#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET	19
-#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK	(0x7 << 19)
-#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET	16
-#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK	(0x7 << 16)
-#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET		14
-#define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK		(0x3 << 14)
-#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET	11
-#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK	(0x7 << 11)
-#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET		8
-#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK		(0x7 << 8)
-#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET		6
-#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK		(0x3 << 6)
-#define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET		3
-#define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK		(0x7 << 3)
-#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET		0
-#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK		0x7
-
-#endif				/* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */
--- a/arch/arm/include/asm/arch-mx51/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx51/imx-regs.h
@@ -1,261 +0,0 @@
-/*
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARCH_MXC_MX51_H__
-#define __ASM_ARCH_MXC_MX51_H__
-
-#define __REG(x)	(*((volatile u32 *)(x)))
-#define __REG16(x)	(*((volatile u16 *)(x)))
-#define __REG8(x)	(*((volatile u8 *)(x)))
-/*
- * IRAM
- */
-#define IRAM_BASE_ADDR		0x1FFE8000	/* internal ram */
-/*
- * Graphics Memory of GPU
- */
-#define GPU_BASE_ADDR		0x20000000
-#define GPU_CTRL_BASE_ADDR	0x30000000
-#define IPU_CTRL_BASE_ADDR	0x40000000
-/*
- * Debug
- */
-#define DEBUG_BASE_ADDR		0x60000000
-#define ETB_BASE_ADDR		(DEBUG_BASE_ADDR + 0x00001000)
-#define ETM_BASE_ADDR		(DEBUG_BASE_ADDR + 0x00002000)
-#define TPIU_BASE_ADDR		(DEBUG_BASE_ADDR + 0x00003000)
-#define CTI0_BASE_ADDR		(DEBUG_BASE_ADDR + 0x00004000)
-#define CTI1_BASE_ADDR		(DEBUG_BASE_ADDR + 0x00005000)
-#define CTI2_BASE_ADDR		(DEBUG_BASE_ADDR + 0x00006000)
-#define CTI3_BASE_ADDR		(DEBUG_BASE_ADDR + 0x00007000)
-#define CORTEX_DBG_BASE_ADDR	(DEBUG_BASE_ADDR + 0x00008000)
-
-/*
- * SPBA global module enabled #0
- */
-#define SPBA0_BASE_ADDR 	0x70000000
-
-#define MMC_SDHC1_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00004000)
-#define MMC_SDHC2_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00008000)
-#define UART3_BASE_ADDR 	(SPBA0_BASE_ADDR + 0x0000C000)
-#define CSPI1_BASE_ADDR 	(SPBA0_BASE_ADDR + 0x00010000)
-#define SSI2_BASE_ADDR		(SPBA0_BASE_ADDR + 0x00014000)
-#define MMC_SDHC3_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00020000)
-#define MMC_SDHC4_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00024000)
-#define SPDIF_BASE_ADDR		(SPBA0_BASE_ADDR + 0x00028000)
-#define ATA_DMA_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00030000)
-#define SLIM_DMA_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00034000)
-#define HSI2C_DMA_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00038000)
-#define SPBA_CTRL_BASE_ADDR	(SPBA0_BASE_ADDR + 0x0003C000)
-
-/*
- * AIPS 1
- */
-#define AIPS1_BASE_ADDR 	0x73F00000
-
-#define OTG_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00080000)
-#define GPIO1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00084000)
-#define GPIO2_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00088000)
-#define GPIO3_BASE_ADDR		(AIPS1_BASE_ADDR + 0x0008C000)
-#define GPIO4_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00090000)
-#define KPP_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00094000)
-#define WDOG1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00098000)
-#define WDOG2_BASE_ADDR		(AIPS1_BASE_ADDR + 0x0009C000)
-#define GPT1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000A0000)
-#define SRTC_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000A4000)
-#define IOMUXC_BASE_ADDR	(AIPS1_BASE_ADDR + 0x000A8000)
-#define EPIT1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000AC000)
-#define EPIT2_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000B0000)
-#define PWM1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000B4000)
-#define PWM2_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000B8000)
-#define UART1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000BC000)
-#define UART2_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000C0000)
-#define SRC_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000D0000)
-#define CCM_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000D4000)
-#define GPC_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000D8000)
-
-/*
- * AIPS 2
- */
-#define AIPS2_BASE_ADDR	0x83F00000
-
-#define PLL1_BASE_ADDR		(AIPS2_BASE_ADDR + 0x00080000)
-#define PLL2_BASE_ADDR		(AIPS2_BASE_ADDR + 0x00084000)
-#define PLL3_BASE_ADDR		(AIPS2_BASE_ADDR + 0x00088000)
-#define AHBMAX_BASE_ADDR	(AIPS2_BASE_ADDR + 0x00094000)
-#define IIM_BASE_ADDR		(AIPS2_BASE_ADDR + 0x00098000)
-#define CSU_BASE_ADDR		(AIPS2_BASE_ADDR + 0x0009C000)
-#define ARM_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000A0000)
-#define OWIRE_BASE_ADDR 	(AIPS2_BASE_ADDR + 0x000A4000)
-#define FIRI_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000A8000)
-#define CSPI2_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000AC000)
-#define SDMA_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000B0000)
-#define SCC_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000B4000)
-#define ROMCP_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000B8000)
-#define RTIC_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000BC000)
-#define CSPI3_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000C0000)
-#define I2C2_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000C4000)
-#define I2C1_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000C8000)
-#define SSI1_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000CC000)
-#define AUDMUX_BASE_ADDR	(AIPS2_BASE_ADDR + 0x000D0000)
-#define M4IF_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000D8000)
-#define ESDCTL_BASE_ADDR	(AIPS2_BASE_ADDR + 0x000D9000)
-#define WEIM_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000DA000)
-#define NFC_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000DB000)
-#define EMI_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000DBF00)
-#define MIPI_HSC_BASE_ADDR	(AIPS2_BASE_ADDR + 0x000DC000)
-#define ATA_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000E0000)
-#define SIM_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000E4000)
-#define SSI3BASE_ADDR		(AIPS2_BASE_ADDR + 0x000E8000)
-#define FEC_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000EC000)
-#define TVE_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000F0000)
-#define VPU_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000F4000)
-#define SAHARA_BASE_ADDR	(AIPS2_BASE_ADDR + 0x000F8000)
-
-#define TZIC_BASE_ADDR		0x8FFFC000
-
-/*
- * Memory regions and CS
- */
-#define CSD0_BASE_ADDR		0x90000000
-#define CSD1_BASE_ADDR		0xA0000000
-#define CS0_BASE_ADDR		0xB0000000
-#define CS1_BASE_ADDR		0xB8000000
-#define CS2_BASE_ADDR		0xC0000000
-#define CS3_BASE_ADDR		0xC8000000
-#define CS4_BASE_ADDR		0xCC000000
-#define CS5_BASE_ADDR		0xCE000000
-
-/*
- * NFC
- */
-#define NFC_BASE_ADDR_AXI	0xCFFF0000	/* NAND flash AXI */
-
-/*!
- * Number of GPIO port as defined in the IC Spec
- */
-#define GPIO_PORT_NUM		4
-/*!
- * Number of GPIO pins per port
- */
-#define GPIO_NUM_PIN            32
-
-#define IIM_SREV	0x24
-#define ROM_SI_REV	0x48
-
-#define NFC_BUF_SIZE	0x1000
-
-/* M4IF */
-#define M4IF_FBPM0	0x40
-#define M4IF_FIDBP	0x48
-
-/* Assuming 24MHz input clock with doubler ON */
-/*                            MFI         PDF */
-#define DP_OP_850	((8 << 4) + ((1 - 1)  << 0))
-#define DP_MFD_850	(48 - 1)
-#define DP_MFN_850	41
-
-#define DP_OP_800	((8 << 4) + ((1 - 1)  << 0))
-#define DP_MFD_800	(3 - 1)
-#define DP_MFN_800	1
-
-#define DP_OP_700	((7 << 4) + ((1 - 1)  << 0))
-#define DP_MFD_700	(24 - 1)
-#define DP_MFN_700	7
-
-#define DP_OP_665	((6 << 4) + ((1 - 1)  << 0))
-#define DP_MFD_665	(96 - 1)
-#define DP_MFN_665	89
-
-#define DP_OP_532	((5 << 4) + ((1 - 1)  << 0))
-#define DP_MFD_532	(24 - 1)
-#define DP_MFN_532	13
-
-#define DP_OP_400	((8 << 4) + ((2 - 1)  << 0))
-#define DP_MFD_400	(3 - 1)
-#define DP_MFN_400	1
-
-#define DP_OP_216	((6 << 4) + ((3 - 1)  << 0))
-#define DP_MFD_216	(4 - 1)
-#define DP_MFN_216	3
-
-#define CHIP_REV_1_0            0x10
-#define CHIP_REV_1_1            0x11
-#define CHIP_REV_2_0            0x20
-#define CHIP_REV_2_5		0x25
-#define CHIP_REV_3_0            0x30
-
-#define BOARD_REV_1_0           0x0
-#define BOARD_REV_2_0           0x1
-
-#ifndef __ASSEMBLY__
-
-struct clkctl {
-	u32	ccr;
-	u32	ccdr;
-	u32	csr;
-	u32	ccsr;
-	u32	cacrr;
-	u32	cbcdr;
-	u32	cbcmr;
-	u32	cscmr1;
-	u32	cscmr2;
-	u32	cscdr1;
-	u32	cs1cdr;
-	u32	cs2cdr;
-	u32	cdcdr;
-	u32	chsccdr;
-	u32	cscdr2;
-	u32	cscdr3;
-	u32	cscdr4;
-	u32	cwdr;
-	u32	cdhipr;
-	u32	cdcr;
-	u32	ctor;
-	u32	clpcr;
-	u32	cisr;
-	u32	cimr;
-	u32	ccosr;
-	u32	cgpr;
-	u32	ccgr0;
-	u32	ccgr1;
-	u32	ccgr2;
-	u32	ccgr3;
-	u32	ccgr4;
-	u32	ccgr5;
-	u32	ccgr6;
-	u32	cmeor;
-};
-
-/* WEIM registers */
-struct weim {
-	u32	csgcr1;
-	u32	csgcr2;
-	u32	csrcr1;
-	u32	csrcr2;
-	u32	cswcr1;
-	u32	cswcr2;
-};
-
-#endif /* __ASSEMBLER__*/
-
-#endif				/*  __ASM_ARCH_MXC_MX51_H__ */
--- a/arch/arm/include/asm/arch-mx51/iomux.h
+++ b/arch/arm/include/asm/arch-mx51/iomux.h
@@ -1,193 +0,0 @@
-/*
- * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __MACH_MX51_IOMUX_H__
-#define __MACH_MX51_IOMUX_H__
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/mx51_pins.h>
-
-typedef unsigned int iomux_pin_name_t;
-
-/* various IOMUX output functions */
-typedef enum iomux_config {
-	IOMUX_CONFIG_ALT0,	/*!< used as alternate function 0 */
-	IOMUX_CONFIG_ALT1,	/*!< used as alternate function 1 */
-	IOMUX_CONFIG_ALT2,	/*!< used as alternate function 2 */
-	IOMUX_CONFIG_ALT3,	/*!< used as alternate function 3 */
-	IOMUX_CONFIG_ALT4,	/*!< used as alternate function 4 */
-	IOMUX_CONFIG_ALT5,	/*!< used as alternate function 5 */
-	IOMUX_CONFIG_ALT6,	/*!< used as alternate function 6 */
-	IOMUX_CONFIG_ALT7,	/*!< used as alternate function 7 */
-	IOMUX_CONFIG_GPIO,	/*!< added to help user use GPIO mode */
-	IOMUX_CONFIG_SION = 0x1 << 4,	/*!< used as LOOPBACK:MUX SION bit */
-} iomux_pin_cfg_t;
-
-/* various IOMUX pad functions */
-typedef enum iomux_pad_config {
-	PAD_CTL_SRE_SLOW = 0x0 << 0,	/* Slow slew rate */
-	PAD_CTL_SRE_FAST = 0x1 << 0,	/* Fast slew rate */
-	PAD_CTL_DRV_LOW = 0x0 << 1,	/* Low drive strength */
-	PAD_CTL_DRV_MEDIUM = 0x1 << 1,	/* Medium drive strength */
-	PAD_CTL_DRV_HIGH = 0x2 << 1,	/* High drive strength */
-	PAD_CTL_DRV_MAX = 0x3 << 1,	/* Max drive strength */
-	PAD_CTL_ODE_OPENDRAIN_NONE = 0x0 << 3,	/* Opendrain disable */
-	PAD_CTL_ODE_OPENDRAIN_ENABLE = 0x1 << 3,/* Opendrain enable */
-	PAD_CTL_100K_PD = 0x0 << 4,	/* 100Kohm pulldown */
-	PAD_CTL_47K_PU = 0x1 << 4,	/* 47Kohm pullup */
-	PAD_CTL_100K_PU = 0x2 << 4,	/* 100Kohm pullup */
-	PAD_CTL_22K_PU = 0x3 << 4,	/* 22Kohm pullup */
-	PAD_CTL_PUE_KEEPER = 0x0 << 6,	/* enable pulldown */
-	PAD_CTL_PUE_PULL = 0x1 << 6,	/* enable pullup */
-	PAD_CTL_PKE_NONE = 0x0 << 7,	/* Disable pullup/pulldown */
-	PAD_CTL_PKE_ENABLE = 0x1 << 7,	/* Enable pullup/pulldown */
-	PAD_CTL_HYS_NONE = 0x0 << 8,	/* Hysteresis disabled */
-	PAD_CTL_HYS_ENABLE = 0x1 << 8,	/* Hysteresis enabled */
-	PAD_CTL_DDR_INPUT_CMOS = 0x0 << 9,/* DDR input CMOS */
-	PAD_CTL_DDR_INPUT_DDR = 0x1 << 9,/* DDR input DDR */
-	PAD_CTL_DRV_VOT_LOW = 0x0 << 13, /* Low voltage mode */
-	PAD_CTL_DRV_VOT_HIGH = 0x1 << 13,/* High voltage mode */
-} iomux_pad_config_t;
-
-/* various IOMUX input select register index */
-typedef enum iomux_input_select {
-	MUX_IN_AUDMUX_P4_INPUT_DA_AMX_SELECT_I = 0,
-	MUX_IN_AUDMUX_P4_INPUT_DB_AMX_SELECT_I,
-	MUX_IN_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT,
-	MUX_IN_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT,
-	MUX_IN_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT,
-	MUX_IN_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT,
-	MUX_IN_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT,
-	MUX_IN_AUDMUX_P5_INPUT_RXFS_AMX_SELECT,
-	MUX_IN_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT,
-	MUX_IN_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT,
-	MUX_IN_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT,
-	MUX_IN_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT,
-	MUX_IN_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT,
-	MUX_IN_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT,
-	MUX_IN_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT,
-	MUX_IN_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT,
-	MUX_IN_CCM_IPP_DI_CLK_SELECT_INPUT,
-	/* TO2 */
-	MUX_IN_CCM_IPP_DI1_CLK_SELECT_INPUT,
-	MUX_IN_CCM_PLL1_BYPASS_CLK_SELECT_INPUT,
-	MUX_IN_CCM_PLL2_BYPASS_CLK_SELECT_INPUT,
-	MUX_IN_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT,
-	MUX_IN_CSPI_IPP_IND_MISO_SELECT_INPUT,
-	MUX_IN_CSPI_IPP_IND_MOSI_SELECT_INPUT,
-	MUX_IN_CSPI_IPP_IND_SS_B_1_SELECT_INPUT,
-	MUX_IN_CSPI_IPP_IND_SS_B_2_SELECT_INPUT,
-	MUX_IN_CSPI_IPP_IND_SS_B_3_SELECT_INPUT,
-	MUX_IN_DPLLIP1_L1T_TOG_EN_SELECT_INPUT,
-	/* TO2 */
-	MUX_IN_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT,
-	MUX_IN_ECSPI2_IPP_IND_SS_B_3_SELECT_INPUT,
-	MUX_IN_EMI_IPP_IND_RDY_INT_SELECT_INPUT,
-	MUX_IN_ESDHC3_IPP_DAT0_IN_SELECT_INPUT,
-	MUX_IN_ESDHC3_IPP_DAT1_IN_SELECT_INPUT,
-	MUX_IN_ESDHC3_IPP_DAT2_IN_SELECT_INPUT,
-	MUX_IN_ESDHC3_IPP_DAT3_IN_SELECT_INPUT,
-	MUX_IN_FEC_FEC_COL_SELECT_INPUT,
-	MUX_IN_FEC_FEC_CRS_SELECT_INPUT,
-	MUX_IN_FEC_FEC_MDI_SELECT_INPUT,
-	MUX_IN_FEC_FEC_RDATA_0_SELECT_INPUT,
-	MUX_IN_FEC_FEC_RDATA_1_SELECT_INPUT,
-	MUX_IN_FEC_FEC_RDATA_2_SELECT_INPUT,
-	MUX_IN_FEC_FEC_RDATA_3_SELECT_INPUT,
-	MUX_IN_FEC_FEC_RX_CLK_SELECT_INPUT,
-	MUX_IN_FEC_FEC_RX_DV_SELECT_INPUT,
-	MUX_IN_FEC_FEC_RX_ER_SELECT_INPUT,
-	MUX_IN_FEC_FEC_TX_CLK_SELECT_INPUT,
-	MUX_IN_GPIO3_IPP_IND_G_IN_1_SELECT_INPUT,
-	MUX_IN_GPIO3_IPP_IND_G_IN_2_SELECT_INPUT,
-	MUX_IN_GPIO3_IPP_IND_G_IN_3_SELECT_INPUT,
-	MUX_IN_GPIO3_IPP_IND_G_IN_4_SELECT_INPUT,
-	MUX_IN_GPIO3_IPP_IND_G_IN_5_SELECT_INPUT,
-	MUX_IN_GPIO3_IPP_IND_G_IN_6_SELECT_INPUT,
-	MUX_IN_GPIO3_IPP_IND_G_IN_7_SELECT_INPUT,
-	MUX_IN_GPIO3_IPP_IND_G_IN_8_SELECT_INPUT,
-	/* TO2 */
-	MUX_IN_GPIO3_IPP_IND_G_IN_12_SELECT_INPUT,
-	MUX_IN_HSC_MIPI_MIX_IPP_IND_SENS1_DATA_EN_SELECT_INPUT,
-	MUX_IN_HSC_MIPI_MIX_IPP_IND_SENS2_DATA_EN_SELECT_INPUT,
-	/* TO2 */
-	MUX_IN_HSC_MIPI_MIX_PAR_VSYNC_SELECT_INPUT,
-	/* TO2 */
-	MUX_IN_HSC_MIPI_MIX_PAR_DI_WAIT_SELECT_INPUT,
-	MUX_IN_HSC_MIPI_MIX_PAR_SISG_TRIG_SELECT_INPUT,
-	MUX_IN_I2C1_IPP_SCL_IN_SELECT_INPUT,
-	MUX_IN_I2C1_IPP_SDA_IN_SELECT_INPUT,
-	MUX_IN_I2C2_IPP_SCL_IN_SELECT_INPUT,
-	MUX_IN_I2C2_IPP_SDA_IN_SELECT_INPUT,
-
-	MUX_IN_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT,
-
-	MUX_IN_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT,
-
-	MUX_IN_KPP_IPP_IND_COL_6_SELECT_INPUT,
-	MUX_IN_KPP_IPP_IND_COL_7_SELECT_INPUT,
-	MUX_IN_KPP_IPP_IND_ROW_4_SELECT_INPUT,
-	MUX_IN_KPP_IPP_IND_ROW_5_SELECT_INPUT,
-	MUX_IN_KPP_IPP_IND_ROW_6_SELECT_INPUT,
-	MUX_IN_KPP_IPP_IND_ROW_7_SELECT_INPUT,
-	MUX_IN_UART1_IPP_UART_RTS_B_SELECT_INPUT,
-	MUX_IN_UART1_IPP_UART_RXD_MUX_SELECT_INPUT,
-	MUX_IN_UART2_IPP_UART_RTS_B_SELECT_INPUT,
-	MUX_IN_UART2_IPP_UART_RXD_MUX_SELECT_INPUT,
-	MUX_IN_UART3_IPP_UART_RTS_B_SELECT_INPUT,
-	MUX_IN_UART3_IPP_UART_RXD_MUX_SELECT_INPUT,
-	MUX_IN_USBOH3_IPP_IND_UH3_CLK_SELECT_INPUT,
-	MUX_IN_USBOH3_IPP_IND_UH3_DATA_0_SELECT_INPUT,
-	MUX_IN_USBOH3_IPP_IND_UH3_DATA_1_SELECT_INPUT,
-	MUX_IN_USBOH3_IPP_IND_UH3_DATA_2_SELECT_INPUT,
-	MUX_IN_USBOH3_IPP_IND_UH3_DATA_3_SELECT_INPUT,
-	MUX_IN_USBOH3_IPP_IND_UH3_DATA_4_SELECT_INPUT,
-	MUX_IN_USBOH3_IPP_IND_UH3_DATA_5_SELECT_INPUT,
-	MUX_IN_USBOH3_IPP_IND_UH3_DATA_6_SELECT_INPUT,
-	MUX_IN_USBOH3_IPP_IND_UH3_DATA_7_SELECT_INPUT,
-	MUX_IN_USBOH3_IPP_IND_UH3_DIR_SELECT_INPUT,
-	MUX_IN_USBOH3_IPP_IND_UH3_NXT_SELECT_INPUT,
-	MUX_IN_USBOH3_IPP_IND_UH3_STP_SELECT_INPUT,
-	MUX_INPUT_NUM_MUX,
-} iomux_input_select_t;
-
-/* various IOMUX input functions */
-typedef enum iomux_input_config {
-	INPUT_CTL_PATH0 = 0x0,
-	INPUT_CTL_PATH1,
-	INPUT_CTL_PATH2,
-	INPUT_CTL_PATH3,
-	INPUT_CTL_PATH4,
-	INPUT_CTL_PATH5,
-	INPUT_CTL_PATH6,
-	INPUT_CTL_PATH7,
-} iomux_input_config_t;
-
-void mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t config);
-void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t config);
-void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config);
-unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin);
-void mxc_iomux_set_input(iomux_input_select_t input, u32 config);
-
-#endif				/*  __MACH_MX51_IOMUX_H__ */
--- a/arch/arm/include/asm/arch-mx51/mx51_pins.h
+++ b/arch/arm/include/asm/arch-mx51/mx51_pins.h
@@ -1,374 +0,0 @@
-/*
- * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARCH_MXC_MX51_PINS_H__
-#define __ASM_ARCH_MXC_MX51_PINS_H__
-
-#ifndef __ASSEMBLY__
-
-/*
- * In order to identify pins more effectively, each mux-controlled pin's
- * enumerated value is constructed in the following way:
- *
- * -------------------------------------------------------------------
- * 31-29 | 28 - 24 |  23 - 21 | 20  - 10| 9 - 0
- * -------------------------------------------------------------------
- * IO_P  |  IO_I   | GPIO_I   | PAD_I   | MUX_I
- * -------------------------------------------------------------------
- *
- * Bit 0 to 9 contains MUX_I used to identify the register
- * offset (0-based. base is IOMUX_module_base) defined in the Section
- * "sw_pad_ctl & sw_mux_ctl details" of the IC Spec. The
- * similar field definitions are used for the pad control register.
- * The IOMUX controller can be split in two parts. At the begeinning,
- * there is the register definitions for the multiplexing each pin.
- * Then there is a set of registers (PAD_I) to configure each pin
- * (pullup, pulldown, etc).
- * PAD_I defines the offset of the pad register for each pin.
- * GPIO_I defines, if available, the number of gpio that can be
- * connected to that pad
- * IO_I defines the multiplexer mode required to set the pad in gpio mode
- * IO_P defines the gpio structure (gpio1..gpio4) the pad belongs
- *
- * For example, the MX51_PIN_ETM_D0 is defined in the enumeration:
- *    ( (0x28 - MUX_I_START) << MUX_I)|( (0x250 - PAD_I_START) << PAD_I)
- * It means the mux control register is at register offset 0x28. The pad control
- * register offset is: 0x250 and also occupy the least significant bits
- * within the register.
- */
-
-/*!
- * Starting bit position within each entry of \b iomux_pins to represent the
- * MUX control register offset
- */
-#define MUX_I			0
-/*!
- * Starting bit position within each entry of \b iomux_pins to represent the
- * PAD control register offset
- */
-#define PAD_I			10
-/*!
- * Starting bit position within each entry of \b iomux_pins to represent which
- * mux mode is for GPIO (0-based)
- */
-#define GPIO_I			21
-
-#define MUX_IO_P                29
-#define MUX_IO_I                24
-#define IOMUX_TO_GPIO(pin)      ((((unsigned int)pin >> MUX_IO_P) * \
-					GPIO_NUM_PIN) + ((pin >> MUX_IO_I) &\
-					((1 << (MUX_IO_P - MUX_IO_I)) - 1)))
-#define IOMUX_TO_IRQ(pin)       (MXC_GPIO_INT_BASE + IOMUX_TO_GPIO(pin))
-#define GPIO_TO_PORT(n)         (n / GPIO_NUM_PIN)
-#define GPIO_TO_INDEX(n)        (n % GPIO_NUM_PIN)
-
-#define NON_GPIO_PORT		0x7
-#define PIN_TO_MUX_MASK		((1 << (PAD_I - MUX_I)) - 1)
-#define PIN_TO_PAD_MASK		((1 << (GPIO_I - PAD_I)) - 1)
-#define PIN_TO_ALT_GPIO_MASK		((1 << (MUX_IO_I - GPIO_I)) - 1)
-
-#define NON_MUX_I		PIN_TO_MUX_MASK
-#define MUX_I_START		0x001C
-#define PAD_I_START		0x3F0
-#define INPUT_CTL_START		0x8C4
-#define INPUT_CTL_START_TO1	0x928
-#define MUX_I_END		(PAD_I_START - 4)
-
-#define _MXC_BUILD_PIN(gp, gi, ga, mi, pi) \
-	(((gp) << MUX_IO_P) | ((gi) << MUX_IO_I) | \
-	((mi) << MUX_I) | \
-	((pi - PAD_I_START) << PAD_I) | \
-	((ga) << GPIO_I))
-
-#define _MXC_BUILD_GPIO_PIN(gp, gi, ga, mi, pi) \
-	_MXC_BUILD_PIN(gp, gi, ga, mi, pi)
-
-#define _MXC_BUILD_NON_GPIO_PIN(mi, pi) \
-	_MXC_BUILD_PIN(NON_GPIO_PORT, 0, 0, mi, pi)
-
-#define PIN_TO_IOMUX_MUX(pin)	((pin >> MUX_I) & PIN_TO_MUX_MASK)
-#define PIN_TO_IOMUX_PAD(pin)	((pin >> PAD_I) & PIN_TO_PAD_MASK)
-#define PIN_TO_ALT_GPIO(pin)	((pin >> GPIO_I) & PIN_TO_ALT_GPIO_MASK)
-#define PIN_TO_IOMUX_INDEX(pin)	(PIN_TO_IOMUX_MUX(pin) >> 2)
-
-/*
- * This enumeration is constructed based on the Section
- * "sw_pad_ctl & sw_mux_ctl details" of the MX51 IC Spec. Each enumerated
- * value is constructed based on the rules described above.
- */
-enum iomux_pins {
-	MX51_PIN_EIM_DA0 = _MXC_BUILD_NON_GPIO_PIN(0x1C, 0x7A8),
-	MX51_PIN_EIM_DA1 = _MXC_BUILD_NON_GPIO_PIN(0x20, 0x7A8),
-	MX51_PIN_EIM_DA2 = _MXC_BUILD_NON_GPIO_PIN(0x24, 0x7A8),
-	MX51_PIN_EIM_DA3 = _MXC_BUILD_NON_GPIO_PIN(0x28, 0x7A8),
-	MX51_PIN_EIM_DA4 = _MXC_BUILD_NON_GPIO_PIN(0x2C, 0x7AC),
-	MX51_PIN_EIM_DA5 = _MXC_BUILD_NON_GPIO_PIN(0x30, 0x7AC),
-	MX51_PIN_EIM_DA6 = _MXC_BUILD_NON_GPIO_PIN(0x34, 0x7AC),
-	MX51_PIN_EIM_DA7 = _MXC_BUILD_NON_GPIO_PIN(0x38, 0x7AC),
-	MX51_PIN_EIM_DA8 = _MXC_BUILD_NON_GPIO_PIN(0x3C, 0x7B0),
-	MX51_PIN_EIM_DA9 = _MXC_BUILD_NON_GPIO_PIN(0x40, 0x7B0),
-	MX51_PIN_EIM_DA10 = _MXC_BUILD_NON_GPIO_PIN(0x44, 0x7B0),
-	MX51_PIN_EIM_DA11 = _MXC_BUILD_NON_GPIO_PIN(0x48, 0x7B0),
-	MX51_PIN_EIM_DA12 = _MXC_BUILD_NON_GPIO_PIN(0x4C, 0x7BC),
-	MX51_PIN_EIM_DA13 = _MXC_BUILD_NON_GPIO_PIN(0x50, 0x7BC),
-	MX51_PIN_EIM_DA14 = _MXC_BUILD_NON_GPIO_PIN(0x54, 0x7BC),
-	MX51_PIN_EIM_DA15 = _MXC_BUILD_NON_GPIO_PIN(0x58, 0x7BC),
-	MX51_PIN_EIM_D16 = _MXC_BUILD_GPIO_PIN(1, 0, 1, 0x5C, 0x3F0),
-	MX51_PIN_EIM_D17 = _MXC_BUILD_GPIO_PIN(1, 1, 1, 0x60, 0x3F4),
-	MX51_PIN_EIM_D18 = _MXC_BUILD_GPIO_PIN(1, 2, 1, 0x64, 0x3F8),
-	MX51_PIN_EIM_D19 = _MXC_BUILD_GPIO_PIN(1, 3, 1, 0x68, 0x3FC),
-	MX51_PIN_EIM_D20 = _MXC_BUILD_GPIO_PIN(1, 4, 1, 0x6C, 0x400),
-	MX51_PIN_EIM_D21 = _MXC_BUILD_GPIO_PIN(1, 5, 1, 0x70, 0x404),
-	MX51_PIN_EIM_D22 = _MXC_BUILD_GPIO_PIN(1, 6, 1, 0x74, 0x408),
-	MX51_PIN_EIM_D23 = _MXC_BUILD_GPIO_PIN(1, 7, 1, 0x78, 0x40C),
-	MX51_PIN_EIM_D24 = _MXC_BUILD_GPIO_PIN(1, 8, 1, 0x7C, 0x410),
-	MX51_PIN_EIM_D25 = _MXC_BUILD_NON_GPIO_PIN(0x80, 0x414),
-	MX51_PIN_EIM_D26 = _MXC_BUILD_NON_GPIO_PIN(0x84, 0x418),
-	MX51_PIN_EIM_D27 = _MXC_BUILD_GPIO_PIN(1, 9, 1, 0x88, 0x41C),
-	MX51_PIN_EIM_D28 = _MXC_BUILD_NON_GPIO_PIN(0x8C, 0x420),
-	MX51_PIN_EIM_D29 = _MXC_BUILD_NON_GPIO_PIN(0x90, 0x424),
-	MX51_PIN_EIM_D30 = _MXC_BUILD_NON_GPIO_PIN(0x94, 0x428),
-	MX51_PIN_EIM_D31 = _MXC_BUILD_NON_GPIO_PIN(0x98, 0x42C),
-	MX51_PIN_EIM_A16 = _MXC_BUILD_GPIO_PIN(1, 10, 1, 0x9C, 0x430),
-	MX51_PIN_EIM_A17 = _MXC_BUILD_GPIO_PIN(1, 11, 1, 0xA0, 0x434),
-	MX51_PIN_EIM_A18 = _MXC_BUILD_GPIO_PIN(1, 12, 1, 0xA4, 0x438),
-	MX51_PIN_EIM_A19 = _MXC_BUILD_GPIO_PIN(1, 13, 1, 0xA8, 0x43C),
-	MX51_PIN_EIM_A20 = _MXC_BUILD_GPIO_PIN(1, 14, 1, 0xAC, 0x440),
-	MX51_PIN_EIM_A21 = _MXC_BUILD_GPIO_PIN(1, 15, 1, 0xB0, 0x444),
-	MX51_PIN_EIM_A22 = _MXC_BUILD_GPIO_PIN(1, 16, 1, 0xB4, 0x448),
-	MX51_PIN_EIM_A23 = _MXC_BUILD_GPIO_PIN(1, 17, 1, 0xB8, 0x44C),
-	MX51_PIN_EIM_A24 = _MXC_BUILD_GPIO_PIN(1, 18, 1, 0xBC, 0x450),
-	MX51_PIN_EIM_A25 = _MXC_BUILD_GPIO_PIN(1, 19, 1, 0xC0, 0x454),
-	MX51_PIN_EIM_A26 = _MXC_BUILD_GPIO_PIN(1, 20, 1, 0xC4, 0x458),
-	MX51_PIN_EIM_A27 = _MXC_BUILD_GPIO_PIN(1, 21, 1, 0xC8, 0x45C),
-	MX51_PIN_EIM_EB0 = _MXC_BUILD_NON_GPIO_PIN(0xCC, 0x460),
-	MX51_PIN_EIM_EB1 = _MXC_BUILD_NON_GPIO_PIN(0xD0, 0x464),
-	MX51_PIN_EIM_EB2 = _MXC_BUILD_GPIO_PIN(1, 22, 1, 0xD4, 0x468),
-	MX51_PIN_EIM_EB3 = _MXC_BUILD_GPIO_PIN(1, 23, 1, 0xD8, 0x46C),
-	MX51_PIN_EIM_OE = _MXC_BUILD_GPIO_PIN(1, 24, 1, 0xDC, 0x470),
-	MX51_PIN_EIM_CS0 = _MXC_BUILD_GPIO_PIN(1, 25, 1, 0xE0, 0x474),
-	MX51_PIN_EIM_CS1 = _MXC_BUILD_GPIO_PIN(1, 26, 1, 0xE4, 0x478),
-	MX51_PIN_EIM_CS2 = _MXC_BUILD_GPIO_PIN(1, 27, 1, 0xE8, 0x47C),
-	MX51_PIN_EIM_CS3 = _MXC_BUILD_GPIO_PIN(1, 28, 1, 0xEC, 0x480),
-	MX51_PIN_EIM_CS4 = _MXC_BUILD_GPIO_PIN(1, 29, 1, 0xF0, 0x484),
-	MX51_PIN_EIM_CS5 = _MXC_BUILD_GPIO_PIN(1, 30, 1, 0xF4, 0x488),
-	MX51_PIN_EIM_DTACK = _MXC_BUILD_GPIO_PIN(1, 31, 1, 0xF8, 0x48C),
-	MX51_PIN_EIM_LBA = _MXC_BUILD_GPIO_PIN(2, 1, 1, 0xFC, 0x494),
-	MX51_PIN_EIM_CRE = _MXC_BUILD_GPIO_PIN(2, 2, 1, 0x100, 0x4A0),
-	MX51_PIN_DRAM_CS1 = _MXC_BUILD_NON_GPIO_PIN(0x104, 0x4D0),
-	MX51_PIN_NANDF_WE_B = _MXC_BUILD_GPIO_PIN(2, 3, 3, 0x108, 0x4E4),
-	MX51_PIN_NANDF_RE_B = _MXC_BUILD_GPIO_PIN(2, 4, 3, 0x10C, 0x4E8),
-	MX51_PIN_NANDF_ALE = _MXC_BUILD_GPIO_PIN(2, 5, 3, 0x110, 0x4EC),
-	MX51_PIN_NANDF_CLE = _MXC_BUILD_GPIO_PIN(2, 6, 3, 0x114, 0x4F0),
-	MX51_PIN_NANDF_WP_B = _MXC_BUILD_GPIO_PIN(2, 7, 3, 0x118, 0x4F4),
-	MX51_PIN_NANDF_RB0 = _MXC_BUILD_GPIO_PIN(2, 8, 3, 0x11C, 0x4F8),
-	MX51_PIN_NANDF_RB1 = _MXC_BUILD_GPIO_PIN(2, 9, 3, 0x120, 0x4FC),
-	MX51_PIN_NANDF_RB2 = _MXC_BUILD_GPIO_PIN(2, 10, 3, 0x124, 0x500),
-	MX51_PIN_NANDF_RB3 = _MXC_BUILD_GPIO_PIN(2, 11, 3, 0x128, 0x504),
-	MX51_PIN_GPIO_NAND = _MXC_BUILD_GPIO_PIN(2, 12, 3, 0x12C, 0x514),
-	MX51_PIN_NANDF_RB4 = MX51_PIN_GPIO_NAND,
-	MX51_PIN_NANDF_RB5 = _MXC_BUILD_GPIO_PIN(2, 13, 3, 0x130, 0x5D8),
-	MX51_PIN_NANDF_RB6 = _MXC_BUILD_GPIO_PIN(2, 14, 3, 0x134, 0x5DC),
-	MX51_PIN_NANDF_RB7 = _MXC_BUILD_GPIO_PIN(2, 15, 3, 0x138, 0x5E0),
-	MX51_PIN_NANDF_CS0 = _MXC_BUILD_GPIO_PIN(2, 16, 3, 0x130, 0x518),
-	MX51_PIN_NANDF_CS1 = _MXC_BUILD_GPIO_PIN(2, 17, 3, 0x134, 0x51C),
-	MX51_PIN_NANDF_CS2 = _MXC_BUILD_GPIO_PIN(2, 18, 3, 0x138, 0x520),
-	MX51_PIN_NANDF_CS3 = _MXC_BUILD_GPIO_PIN(2, 19, 3, 0x13C, 0x524),
-	MX51_PIN_NANDF_CS4 = _MXC_BUILD_GPIO_PIN(2, 20, 3, 0x140, 0x528),
-	MX51_PIN_NANDF_CS5 = _MXC_BUILD_GPIO_PIN(2, 21, 3, 0x144, 0x52C),
-	MX51_PIN_NANDF_CS6 = _MXC_BUILD_GPIO_PIN(2, 22, 3, 0x148, 0x530),
-	MX51_PIN_NANDF_CS7 = _MXC_BUILD_GPIO_PIN(2, 23, 3, 0x14C, 0x534),
-	MX51_PIN_NANDF_RDY_INT = _MXC_BUILD_GPIO_PIN(2, 24, 3, 0x150, 0x538),
-	MX51_PIN_NANDF_D15 = _MXC_BUILD_GPIO_PIN(2, 25, 3, 0x154, 0x53C),
-	MX51_PIN_NANDF_D14 = _MXC_BUILD_GPIO_PIN(2, 26, 3, 0x158, 0x540),
-	MX51_PIN_NANDF_D13 = _MXC_BUILD_GPIO_PIN(2, 27, 3, 0x15C, 0x544),
-	MX51_PIN_NANDF_D12 = _MXC_BUILD_GPIO_PIN(2, 28, 3, 0x160, 0x548),
-	MX51_PIN_NANDF_D11 = _MXC_BUILD_GPIO_PIN(2, 29, 3, 0x164, 0x54C),
-	MX51_PIN_NANDF_D10 = _MXC_BUILD_GPIO_PIN(2, 30, 3, 0x168, 0x550),
-	MX51_PIN_NANDF_D9 = _MXC_BUILD_GPIO_PIN(2, 31, 3, 0x16C, 0x554),
-	MX51_PIN_NANDF_D8 = _MXC_BUILD_GPIO_PIN(3, 0, 3, 0x170, 0x558),
-	MX51_PIN_NANDF_D7 = _MXC_BUILD_GPIO_PIN(3, 1, 3, 0x174, 0x55C),
-	MX51_PIN_NANDF_D6 = _MXC_BUILD_GPIO_PIN(3, 2, 3, 0x178, 0x560),
-	MX51_PIN_NANDF_D5 = _MXC_BUILD_GPIO_PIN(3, 3, 3, 0x17C, 0x564),
-	MX51_PIN_NANDF_D4 = _MXC_BUILD_GPIO_PIN(3, 4, 3, 0x180, 0x568),
-	MX51_PIN_NANDF_D3 = _MXC_BUILD_GPIO_PIN(3, 5, 3, 0x184, 0x56C),
-	MX51_PIN_NANDF_D2 = _MXC_BUILD_GPIO_PIN(3, 6, 3, 0x188, 0x570),
-	MX51_PIN_NANDF_D1 = _MXC_BUILD_GPIO_PIN(3, 7, 3, 0x18C, 0x574),
-	MX51_PIN_NANDF_D0 = _MXC_BUILD_GPIO_PIN(3, 8, 3, 0x190, 0x578),
-	MX51_PIN_CSI1_D8 = _MXC_BUILD_GPIO_PIN(2, 12, 3, 0x194, 0x57C),
-	MX51_PIN_CSI1_D9 = _MXC_BUILD_GPIO_PIN(2, 13, 3, 0x198, 0x580),
-	MX51_PIN_CSI1_D10 = _MXC_BUILD_NON_GPIO_PIN(0x19C, 0x584),
-	MX51_PIN_CSI1_D11 = _MXC_BUILD_NON_GPIO_PIN(0x1A0, 0x588),
-	MX51_PIN_CSI1_D12 = _MXC_BUILD_NON_GPIO_PIN(0x1A4, 0x58C),
-	MX51_PIN_CSI1_D13 = _MXC_BUILD_NON_GPIO_PIN(0x1A8, 0x590),
-	MX51_PIN_CSI1_D14 = _MXC_BUILD_NON_GPIO_PIN(0x1AC, 0x594),
-	MX51_PIN_CSI1_D15 = _MXC_BUILD_NON_GPIO_PIN(0x1B0, 0x598),
-	MX51_PIN_CSI1_D16 = _MXC_BUILD_NON_GPIO_PIN(0x1B4, 0x59C),
-	MX51_PIN_CSI1_D17 = _MXC_BUILD_NON_GPIO_PIN(0x1B8, 0x5A0),
-	MX51_PIN_CSI1_D18 = _MXC_BUILD_NON_GPIO_PIN(0x1BC, 0x5A4),
-	MX51_PIN_CSI1_D19 = _MXC_BUILD_NON_GPIO_PIN(0x1C0, 0x5A8),
-	MX51_PIN_CSI1_VSYNC = _MXC_BUILD_NON_GPIO_PIN(0x1C4, 0x5AC),
-	MX51_PIN_CSI1_HSYNC = _MXC_BUILD_NON_GPIO_PIN(0x1C8, 0x5B0),
-	MX51_PIN_CSI1_PIXCLK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5B4),
-	MX51_PIN_CSI1_MCLK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5B8),
-	MX51_PIN_CSI1_PKE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x860),
-	MX51_PIN_CSI2_D12 = _MXC_BUILD_GPIO_PIN(3, 9, 3, 0x1CC, 0x5BC),
-	MX51_PIN_CSI2_D13 = _MXC_BUILD_GPIO_PIN(3, 10, 3, 0x1D0, 0x5C0),
-	MX51_PIN_CSI2_D14 = _MXC_BUILD_GPIO_PIN(3, 11, 3, 0x1D4, 0x5C4),
-	MX51_PIN_CSI2_D15 = _MXC_BUILD_GPIO_PIN(3, 12, 3, 0x1D8, 0x5C8),
-	MX51_PIN_CSI2_D16 = _MXC_BUILD_GPIO_PIN(3, 11, 3, 0x1DC, 0x5CC),
-	MX51_PIN_CSI2_D17 = _MXC_BUILD_GPIO_PIN(3, 12, 3, 0x1E0, 0x5D0),
-	MX51_PIN_CSI2_D18 = _MXC_BUILD_GPIO_PIN(3, 11, 3, 0x1E4, 0x5D4),
-	MX51_PIN_CSI2_D19 = _MXC_BUILD_GPIO_PIN(3, 12, 3, 0x1E8, 0x5D8),
-	MX51_PIN_CSI2_VSYNC = _MXC_BUILD_GPIO_PIN(3, 13, 3, 0x1EC, 0x5DC),
-	MX51_PIN_CSI2_HSYNC = _MXC_BUILD_GPIO_PIN(3, 14, 3, 0x1F0, 0x5E0),
-	MX51_PIN_CSI2_PIXCLK = _MXC_BUILD_GPIO_PIN(3, 15, 3, 0x1F4, 0x5E4),
-	MX51_PIN_CSI2_PKE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x81C),
-	MX51_PIN_I2C1_CLK = _MXC_BUILD_GPIO_PIN(3, 16, 3, 0x1F8, 0x5E8),
-	MX51_PIN_I2C1_DAT = _MXC_BUILD_GPIO_PIN(3, 17, 3, 0x1FC, 0x5EC),
-	MX51_PIN_AUD3_BB_TXD = _MXC_BUILD_GPIO_PIN(3, 18, 3, 0x200, 0x5F0),
-	MX51_PIN_AUD3_BB_RXD = _MXC_BUILD_GPIO_PIN(3, 19, 3, 0x204, 0x5F4),
-	MX51_PIN_AUD3_BB_CK = _MXC_BUILD_GPIO_PIN(3, 20, 3, 0x208, 0x5F8),
-	MX51_PIN_AUD3_BB_FS = _MXC_BUILD_GPIO_PIN(3, 21, 3, 0x20C, 0x5FC),
-	MX51_PIN_CSPI1_MOSI = _MXC_BUILD_GPIO_PIN(3, 22, 3, 0x210, 0x600),
-	MX51_PIN_CSPI1_MISO = _MXC_BUILD_GPIO_PIN(3, 23, 3, 0x214, 0x604),
-	MX51_PIN_CSPI1_SS0 = _MXC_BUILD_GPIO_PIN(3, 24, 3, 0x218, 0x608),
-	MX51_PIN_CSPI1_SS1 = _MXC_BUILD_GPIO_PIN(3, 25, 3, 0x21C, 0x60C),
-	MX51_PIN_CSPI1_RDY = _MXC_BUILD_GPIO_PIN(3, 26, 3, 0x220, 0x610),
-	MX51_PIN_CSPI1_SCLK = _MXC_BUILD_GPIO_PIN(3, 27, 3, 0x224, 0x614),
-	MX51_PIN_UART1_RXD = _MXC_BUILD_GPIO_PIN(3, 28, 3, 0x228, 0x618),
-	MX51_PIN_UART1_TXD = _MXC_BUILD_GPIO_PIN(3, 29, 3, 0x22C, 0x61C),
-	MX51_PIN_UART1_RTS = _MXC_BUILD_GPIO_PIN(3, 30, 3, 0x230, 0x620),
-	MX51_PIN_UART1_CTS = _MXC_BUILD_GPIO_PIN(3, 31, 3, 0x234, 0x624),
-	MX51_PIN_UART2_RXD = _MXC_BUILD_GPIO_PIN(0, 20, 3, 0x238, 0x628),
-	MX51_PIN_UART2_TXD = _MXC_BUILD_GPIO_PIN(0, 21, 3, 0x23C, 0x62C),
-	MX51_PIN_UART3_RXD = _MXC_BUILD_GPIO_PIN(0, 22, 3, 0x240, 0x630),
-	MX51_PIN_UART3_TXD = _MXC_BUILD_GPIO_PIN(0, 23, 3, 0x244, 0x634),
-	MX51_PIN_OWIRE_LINE = _MXC_BUILD_GPIO_PIN(0, 24, 3, 0x248, 0x638),
-	MX51_PIN_KEY_ROW0 = _MXC_BUILD_NON_GPIO_PIN(0x24C, 0x63C),
-	MX51_PIN_KEY_ROW1 = _MXC_BUILD_NON_GPIO_PIN(0x250, 0x640),
-	MX51_PIN_KEY_ROW2 = _MXC_BUILD_NON_GPIO_PIN(0x254, 0x644),
-	MX51_PIN_KEY_ROW3 = _MXC_BUILD_NON_GPIO_PIN(0x258, 0x648),
-	MX51_PIN_KEY_COL0 = _MXC_BUILD_NON_GPIO_PIN(0x25C, 0x64C),
-	MX51_PIN_KEY_COL1 = _MXC_BUILD_NON_GPIO_PIN(0x260, 0x650),
-	MX51_PIN_KEY_COL2 = _MXC_BUILD_NON_GPIO_PIN(0x264, 0x654),
-	MX51_PIN_KEY_COL3 = _MXC_BUILD_NON_GPIO_PIN(0x268, 0x658),
-	MX51_PIN_KEY_COL4 = _MXC_BUILD_NON_GPIO_PIN(0x26C, 0x65C),
-	MX51_PIN_KEY_COL5 = _MXC_BUILD_NON_GPIO_PIN(0x270, 0x660),
-	MX51_PIN_USBH1_CLK = _MXC_BUILD_GPIO_PIN(0, 25, 2, 0x278, 0x678),
-	MX51_PIN_USBH1_DIR = _MXC_BUILD_GPIO_PIN(0, 26, 2, 0x27C, 0x67C),
-	MX51_PIN_USBH1_STP = _MXC_BUILD_GPIO_PIN(0, 27, 2, 0x280, 0x680),
-	MX51_PIN_USBH1_NXT = _MXC_BUILD_GPIO_PIN(0, 28, 2, 0x284, 0x684),
-	MX51_PIN_USBH1_DATA0 = _MXC_BUILD_GPIO_PIN(0, 11, 2, 0x288, 0x688),
-	MX51_PIN_USBH1_DATA1 = _MXC_BUILD_GPIO_PIN(0, 12, 2, 0x28C, 0x68C),
-	MX51_PIN_USBH1_DATA2 = _MXC_BUILD_GPIO_PIN(0, 13, 2, 0x290, 0x690),
-	MX51_PIN_USBH1_DATA3 = _MXC_BUILD_GPIO_PIN(0, 14, 2, 0x294, 0x694),
-	MX51_PIN_USBH1_DATA4 = _MXC_BUILD_GPIO_PIN(0, 15, 2, 0x298, 0x698),
-	MX51_PIN_USBH1_DATA5 = _MXC_BUILD_GPIO_PIN(0, 16, 2, 0x29C, 0x69C),
-	MX51_PIN_USBH1_DATA6 = _MXC_BUILD_GPIO_PIN(0, 17, 2, 0x2A0, 0x6A0),
-	MX51_PIN_USBH1_DATA7 = _MXC_BUILD_GPIO_PIN(0, 18, 2, 0x2A4, 0x6A4),
-	MX51_PIN_DI1_PIN11 = _MXC_BUILD_GPIO_PIN(2, 0, 4, 0x2A8, 0x6A8),
-	MX51_PIN_DI1_PIN12 = _MXC_BUILD_GPIO_PIN(2, 1, 4, 0x2AC, 0x6AC),
-	MX51_PIN_DI1_PIN13 = _MXC_BUILD_GPIO_PIN(2, 2, 4, 0x2B0, 0x6B0),
-	MX51_PIN_DI1_D0_CS = _MXC_BUILD_GPIO_PIN(2, 3, 4, 0x2B4, 0x6B4),
-	MX51_PIN_DI1_D1_CS = _MXC_BUILD_GPIO_PIN(2, 4, 4, 0x2B8, 0x6B8),
-	MX51_PIN_DISPB2_SER_DIN = _MXC_BUILD_GPIO_PIN(2, 5, 4, 0x2BC, 0x6BC),
-	MX51_PIN_DISPB2_SER_DIO = _MXC_BUILD_GPIO_PIN(2, 6, 4, 0x2C0, 0x6C0),
-	MX51_PIN_DISPB2_SER_CLK = _MXC_BUILD_GPIO_PIN(2, 7, 4, 0x2C4, 0x6C4),
-	MX51_PIN_DISPB2_SER_RS = _MXC_BUILD_GPIO_PIN(2, 8, 4, 0x2C8, 0x6C8),
-	MX51_PIN_DISP1_DAT0 = _MXC_BUILD_NON_GPIO_PIN(0x2CC, 0x6CC),
-	MX51_PIN_DISP1_DAT1 = _MXC_BUILD_NON_GPIO_PIN(0x2D0, 0x6D0),
-	MX51_PIN_DISP1_DAT2 = _MXC_BUILD_NON_GPIO_PIN(0x2D4, 0x6D4),
-	MX51_PIN_DISP1_DAT3 = _MXC_BUILD_NON_GPIO_PIN(0x2D8, 0x6D8),
-	MX51_PIN_DISP1_DAT4 = _MXC_BUILD_NON_GPIO_PIN(0x2DC, 0x6DC),
-	MX51_PIN_DISP1_DAT5 = _MXC_BUILD_NON_GPIO_PIN(0x2E0, 0x6E0),
-	MX51_PIN_DISP1_DAT6 = _MXC_BUILD_NON_GPIO_PIN(0x2E4, 0x6E4),
-	MX51_PIN_DISP1_DAT7 = _MXC_BUILD_NON_GPIO_PIN(0x2E8, 0x6E8),
-	MX51_PIN_DISP1_DAT8 = _MXC_BUILD_NON_GPIO_PIN(0x2EC, 0x6EC),
-	MX51_PIN_DISP1_DAT9 = _MXC_BUILD_NON_GPIO_PIN(0x2F0, 0x6F0),
-	MX51_PIN_DISP1_DAT10 = _MXC_BUILD_NON_GPIO_PIN(0x2F4, 0x6F4),
-	MX51_PIN_DISP1_DAT11 = _MXC_BUILD_NON_GPIO_PIN(0x2F8, 0x6F8),
-	MX51_PIN_DISP1_DAT12 = _MXC_BUILD_NON_GPIO_PIN(0x2FC, 0x6FC),
-	MX51_PIN_DISP1_DAT13 = _MXC_BUILD_NON_GPIO_PIN(0x300, 0x700),
-	MX51_PIN_DISP1_DAT14 = _MXC_BUILD_NON_GPIO_PIN(0x304, 0x704),
-	MX51_PIN_DISP1_DAT15 = _MXC_BUILD_NON_GPIO_PIN(0x308, 0x708),
-	MX51_PIN_DISP1_DAT16 = _MXC_BUILD_NON_GPIO_PIN(0x30C, 0x70C),
-	MX51_PIN_DISP1_DAT17 = _MXC_BUILD_NON_GPIO_PIN(0x310, 0x710),
-	MX51_PIN_DISP1_DAT18 = _MXC_BUILD_NON_GPIO_PIN(0x314, 0x714),
-	MX51_PIN_DISP1_DAT19 = _MXC_BUILD_NON_GPIO_PIN(0x318, 0x718),
-	MX51_PIN_DISP1_DAT20 = _MXC_BUILD_NON_GPIO_PIN(0x31C, 0x71C),
-	MX51_PIN_DISP1_DAT21 = _MXC_BUILD_NON_GPIO_PIN(0x320, 0x720),
-	MX51_PIN_DISP1_DAT22 = _MXC_BUILD_NON_GPIO_PIN(0x324, 0x724),
-	MX51_PIN_DISP1_DAT23 = _MXC_BUILD_NON_GPIO_PIN(0x328, 0x728),
-	MX51_PIN_DI1_PIN3 = _MXC_BUILD_NON_GPIO_PIN(0x32C, 0x72C),
-	MX51_PIN_DI1_PIN2 = _MXC_BUILD_NON_GPIO_PIN(0x330, 0x734),
-	MX51_PIN_DI_GP1 = _MXC_BUILD_NON_GPIO_PIN(0x334, 0x73C),
-	MX51_PIN_DI_GP2 = _MXC_BUILD_NON_GPIO_PIN(0x338, 0x740),
-	MX51_PIN_DI_GP3 = _MXC_BUILD_NON_GPIO_PIN(0x33C, 0x744),
-	MX51_PIN_DI2_PIN4 = _MXC_BUILD_NON_GPIO_PIN(0x340, 0x748),
-	MX51_PIN_DI2_PIN2 = _MXC_BUILD_NON_GPIO_PIN(0x344, 0x74C),
-	MX51_PIN_DI2_PIN3 = _MXC_BUILD_NON_GPIO_PIN(0x348, 0x750),
-	MX51_PIN_DI2_DISP_CLK = _MXC_BUILD_NON_GPIO_PIN(0x34C, 0x754),
-	MX51_PIN_DI_GP4 = _MXC_BUILD_NON_GPIO_PIN(0x350, 0x758),
-	MX51_PIN_DISP2_DAT0 = _MXC_BUILD_NON_GPIO_PIN(0x354, 0x75C),
-	MX51_PIN_DISP2_DAT1 = _MXC_BUILD_NON_GPIO_PIN(0x358, 0x760),
-	MX51_PIN_DISP2_DAT2 = _MXC_BUILD_NON_GPIO_PIN(0x35C, 0x764),
-	MX51_PIN_DISP2_DAT3 = _MXC_BUILD_NON_GPIO_PIN(0x360, 0x768),
-	MX51_PIN_DISP2_DAT4 = _MXC_BUILD_NON_GPIO_PIN(0x364, 0x76C),
-	MX51_PIN_DISP2_DAT5 = _MXC_BUILD_NON_GPIO_PIN(0x368, 0x770),
-	MX51_PIN_DISP2_DAT6 = _MXC_BUILD_GPIO_PIN(0, 19, 5, 0x36C, 0x774),
-	MX51_PIN_DISP2_DAT7 = _MXC_BUILD_GPIO_PIN(0, 29, 5, 0x370, 0x778),
-	MX51_PIN_DISP2_DAT8 = _MXC_BUILD_GPIO_PIN(0, 30, 5, 0x374, 0x77C),
-	MX51_PIN_DISP2_DAT9 = _MXC_BUILD_GPIO_PIN(0, 31, 5, 0x378, 0x780),
-	MX51_PIN_DISP2_DAT10 = _MXC_BUILD_NON_GPIO_PIN(0x37C, 0x784),
-	MX51_PIN_DISP2_DAT11 = _MXC_BUILD_NON_GPIO_PIN(0x380, 0x788),
-	MX51_PIN_DISP2_DAT12 = _MXC_BUILD_NON_GPIO_PIN(0x384, 0x78C),
-	MX51_PIN_DISP2_DAT13 = _MXC_BUILD_NON_GPIO_PIN(0x388, 0x790),
-	MX51_PIN_DISP2_DAT14 = _MXC_BUILD_NON_GPIO_PIN(0x38C, 0x794),
-	MX51_PIN_DISP2_DAT15 = _MXC_BUILD_NON_GPIO_PIN(0x390, 0x798),
-	MX51_PIN_SD1_CMD = _MXC_BUILD_NON_GPIO_PIN(0x394, 0x79C),
-	MX51_PIN_SD1_CLK = _MXC_BUILD_NON_GPIO_PIN(0x398, 0x7A0),
-	MX51_PIN_SD1_DATA0 = _MXC_BUILD_NON_GPIO_PIN(0x39C, 0x7A4),
-	MX51_PIN_SD1_DATA1 = _MXC_BUILD_NON_GPIO_PIN(0x3A0, 0x7A8),
-	MX51_PIN_SD1_DATA2 = _MXC_BUILD_NON_GPIO_PIN(0x3A4, 0x7AC),
-	MX51_PIN_SD1_DATA3 = _MXC_BUILD_NON_GPIO_PIN(0x3A8, 0x7B0),
-	MX51_PIN_GPIO1_0 = _MXC_BUILD_GPIO_PIN(0, 0, 1, 0x3AC, 0x7B4),
-	MX51_PIN_GPIO1_1 = _MXC_BUILD_GPIO_PIN(0, 1, 1, 0x3B0, 0x7B8),
-	MX51_PIN_SD2_CMD = _MXC_BUILD_NON_GPIO_PIN(0x3B4, 0x7BC),
-	MX51_PIN_SD2_CLK = _MXC_BUILD_NON_GPIO_PIN(0x3B8, 0x7C0),
-	MX51_PIN_SD2_DATA0 = _MXC_BUILD_NON_GPIO_PIN(0x3BC, 0x7C4),
-	MX51_PIN_SD2_DATA1 = _MXC_BUILD_NON_GPIO_PIN(0x3C0, 0x7C8),
-	MX51_PIN_SD2_DATA2 = _MXC_BUILD_NON_GPIO_PIN(0x3C4, 0x7CC),
-	MX51_PIN_SD2_DATA3 = _MXC_BUILD_NON_GPIO_PIN(0x3C8, 0x7D0),
-	MX51_PIN_GPIO1_2 = _MXC_BUILD_GPIO_PIN(0, 2, 0, 0x3CC, 0x7D4),
-	MX51_PIN_GPIO1_3 = _MXC_BUILD_GPIO_PIN(0, 3, 0, 0x3D0, 0x7D8),
-	MX51_PIN_PMIC_INT_REQ = _MXC_BUILD_NON_GPIO_PIN(0x3D4, 0x7FC),
-	MX51_PIN_GPIO1_4 = _MXC_BUILD_GPIO_PIN(0, 4, 0, 0x3D8, 0x804),
-	MX51_PIN_GPIO1_5 = _MXC_BUILD_GPIO_PIN(0, 5, 0, 0x3DC, 0x808),
-	MX51_PIN_GPIO1_6 = _MXC_BUILD_GPIO_PIN(0, 6, 0, 0x3E0, 0x80C),
-	MX51_PIN_GPIO1_7 = _MXC_BUILD_GPIO_PIN(0, 7, 0, 0x3E4, 0x810),
-	MX51_PIN_GPIO1_8 = _MXC_BUILD_GPIO_PIN(0, 8, 0, 0x3E8, 0x814),
-	MX51_PIN_GPIO1_9 = _MXC_BUILD_GPIO_PIN(0, 9, 0, 0x3EC, 0x818),
-};
-
-#endif				/* __ASSEMBLY__ */
-#endif				/* __ASM_ARCH_MXC_MX51_PINS_H__ */
--- a/arch/arm/include/asm/arch-omap3/emif4.h
+++ b/arch/arm/include/asm/arch-omap3/emif4.h
@@ -1,79 +0,0 @@
-/*
- * Auther:
- *       Vaibhav Hiremath <hvaibhav@ti.com>
- *
- * Copyright (C) 2010
- * Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _EMIF_H_
-#define _EMIF_H_
-
-/*
- * Configuration values
- */
-#define EMIF4_TIM1_T_RP		(0x3 << 25)
-#define EMIF4_TIM1_T_RCD	(0x3 << 21)
-#define EMIF4_TIM1_T_WR		(0x3 << 17)
-#define EMIF4_TIM1_T_RAS	(0x8 << 12)
-#define EMIF4_TIM1_T_RC		(0xA << 6)
-#define EMIF4_TIM1_T_RRD	(0x2 << 3)
-#define EMIF4_TIM1_T_WTR	(0x2)
-
-#define EMIF4_TIM2_T_XP		(0x2 << 28)
-#define EMIF4_TIM2_T_ODT	(0x0 << 25)
-#define EMIF4_TIM2_T_XSNR	(0x1C << 16)
-#define EMIF4_TIM2_T_XSRD	(0xC8 << 6)
-#define EMIF4_TIM2_T_RTP	(0x1 << 3)
-#define EMIF4_TIM2_T_CKE	(0x2)
-
-#define EMIF4_TIM3_T_RFC	(0x25 << 4)
-#define EMIF4_TIM3_T_RAS_MAX	(0x7)
-
-#define EMIF4_PWR_IDLE_MODE	(0x2 << 30)
-#define EMIF4_PWR_DPD_DIS	(0x0 << 10)
-#define EMIF4_PWR_DPD_EN	(0x1 << 10)
-#define EMIF4_PWR_LP_MODE	(0x0 << 8)
-#define EMIF4_PWR_PM_TIM	(0x0)
-
-#define EMIF4_INITREF_DIS	(0x0 << 31)
-#define EMIF4_REFRESH_RATE	(0x50F)
-
-#define EMIF4_CFG_SDRAM_TYP	(0x2 << 29)
-#define EMIF4_CFG_IBANK_POS	(0x0 << 27)
-#define EMIF4_CFG_DDR_TERM	(0x0 << 24)
-#define EMIF4_CFG_DDR2_DDQS	(0x1 << 23)
-#define EMIF4_CFG_DDR_DIS_DLL	(0x0 << 20)
-#define EMIF4_CFG_SDR_DRV	(0x0 << 18)
-#define EMIF4_CFG_NARROW_MD	(0x0 << 14)
-#define EMIF4_CFG_CL		(0x5 << 10)
-#define EMIF4_CFG_ROWSIZE	(0x0 << 7)
-#define EMIF4_CFG_IBANK		(0x3 << 4)
-#define EMIF4_CFG_EBANK		(0x0 << 3)
-#define EMIF4_CFG_PGSIZE	(0x2)
-
-/*
- * EMIF4 PHY Control 1 register configuration
- */
-#define EMIF4_DDR1_EXT_STRB_EN	(0x1 << 7)
-#define EMIF4_DDR1_EXT_STRB_DIS	(0x0 << 7)
-#define EMIF4_DDR1_PWRDN_DIS	(0x0 << 6)
-#define EMIF4_DDR1_PWRDN_EN	(0x1 << 6)
-#define EMIF4_DDR1_READ_LAT	(0x6 << 0)
-
-#endif /* endif _EMIF_H_ */
--- a/arch/arm/include/asm/arch-orion5x/cpu.h
+++ b/arch/arm/include/asm/arch-orion5x/cpu.h
@@ -1,203 +0,0 @@
-/*
- * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
- *
- * Based on original Kirorion5x_ood support which is
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#ifndef _ORION5X_CPU_H
-#define _ORION5X_CPU_H
-
-#include <asm/system.h>
-
-#ifndef __ASSEMBLY__
-
-#define ORION5X_CPU_WIN_CTRL_DATA(size, target, attr, en) (en | (target << 4) \
-			| (attr << 8) | (orion5x_winctrl_calcsize(size) << 16))
-
-#define ORION5XGBE_PORT_SERIAL_CONTROL1_REG(_x)	\
-		((_x ? ORION5X_EGIGA0_BASE : ORION5X_EGIGA1_BASE) + 0x44c)
-
-enum memory_bank {
-	BANK0,
-	BANK1,
-	BANK2,
-	BANK3
-};
-
-enum orion5x_cpu_winen {
-	ORION5X_WIN_DISABLE,
-	ORION5X_WIN_ENABLE
-};
-
-enum orion5x_cpu_target {
-	ORION5X_TARGET_DRAM = 0,
-	ORION5X_TARGET_DEVICE = 1,
-	ORION5X_TARGET_PCI = 3,
-	ORION5X_TARGET_PCIE = 4,
-	ORION5X_TARGET_SASRAM = 9
-};
-
-enum orion5x_cpu_attrib {
-	ORION5X_ATTR_DRAM_CS0 = 0x0e,
-	ORION5X_ATTR_DRAM_CS1 = 0x0d,
-	ORION5X_ATTR_DRAM_CS2 = 0x0b,
-	ORION5X_ATTR_DRAM_CS3 = 0x07,
-	ORION5X_ATTR_PCI_MEM = 0x59,
-	ORION5X_ATTR_PCI_IO = 0x51,
-	ORION5X_ATTR_PCIE_MEM = 0x59,
-	ORION5X_ATTR_PCIE_IO = 0x51,
-	ORION5X_ATTR_SASRAM = 0x00,
-	ORION5X_ATTR_DEV_CS0 = 0x1e,
-	ORION5X_ATTR_DEV_CS1 = 0x1d,
-	ORION5X_ATTR_DEV_CS2 = 0x1b,
-	ORION5X_ATTR_BOOTROM = 0x0f
-};
-
-/*
- * Default Device Address MAP BAR values
- */
-#define ORION5X_DEFADR_PCIE_MEM	0x90000000
-#define ORION5X_DEFADR_PCIE_MEM_REMAP_LO	0x90000000
-#define ORION5X_DEFADR_PCIE_MEM_REMAP_HI	0
-#define ORION5X_DEFSZ_PCIE_MEM	(128*1024*1024)
-
-#define ORION5X_DEFADR_PCIE_IO	0xf0000000
-#define ORION5X_DEFADR_PCIE_IO_REMAP_LO	0x90000000
-#define ORION5X_DEFADR_PCIE_IO_REMAP_HI	0
-#define ORION5X_DEFSZ_PCIE_IO	(64*1024)
-
-#define ORION5X_DEFADR_PCI_MEM	0x98000000
-#define ORION5X_DEFSZ_PCI_MEM	(128*1024*1024)
-
-#define ORION5X_DEFADR_PCI_IO	0xf0100000
-#define ORION5X_DEFSZ_PCI_IO	(64*1024)
-
-#define ORION5X_DEFADR_DEV_CS0	0xfa000000
-#define ORION5X_DEFSZ_DEV_CS0	(2*1024*1024)
-
-#define ORION5X_DEFADR_DEV_CS1	0xf8000000
-#define ORION5X_DEFSZ_DEV_CS1	(32*1024*1024)
-
-#define ORION5X_DEFADR_DEV_CS2	0xfa800000
-#define ORION5X_DEFSZ_DEV_CS2	(1*1024*1024)
-
-#define ORION5X_DEFADR_BOOTROM	0xFFF80000
-#define ORION5X_DEFSZ_BOOTROM	(512*1024)
-
-/*
- * PCIE registers are used for SoC device ID and revision
- */
-#define PCIE_DEV_ID_OFF         (ORION5X_REG_PCIE_BASE + 0x0000)
-#define PCIE_DEV_REV_OFF        (ORION5X_REG_PCIE_BASE + 0x0008)
-
-/*
- * The following definitions are intended for identifying
- * the real device and revision on which u-boot is running
- * even if it was compiled only for a specific one. Thus,
- * these constants must not be considered chip-specific.
- */
-
-/* Orion-1 (88F5181) and Orion-VoIP (88F5181L) */
-#define MV88F5181_DEV_ID        0x5181
-#define MV88F5181_REV_B1        3
-#define MV88F5181L_REV_A0       8
-#define MV88F5181L_REV_A1       9
-/* Orion-NAS (88F5182) */
-#define MV88F5182_DEV_ID        0x5182
-#define MV88F5182_REV_A2        2
-/* Orion-2 (88F5281) */
-#define MV88F5281_DEV_ID        0x5281
-#define MV88F5281_REV_D0        4
-#define MV88F5281_REV_D1        5
-#define MV88F5281_REV_D2        6
-/* Orion-1-90 (88F6183) */
-#define MV88F6183_DEV_ID        0x6183
-#define MV88F6183_REV_B0        3
-
-/*
- * read feroceon core extra feature register
- * using co-proc instruction
- */
-static inline unsigned int readfr_extra_feature_reg(void)
-{
-	unsigned int val;
-	asm volatile ("mrc p15, 1, %0, c15, c1, 0 @ readfr exfr" : "=r"
-			(val) : : "cc");
-	return val;
-}
-
-/*
- * write feroceon core extra feature register
- * using co-proc instruction
- */
-static inline void writefr_extra_feature_reg(unsigned int val)
-{
-	asm volatile ("mcr p15, 1, %0, c15, c1, 0 @ writefr exfr" : : "r"
-			(val) : "cc");
-	isb();
-}
-
-/*
- * AHB to Mbus Bridge Registers
- * Source: 88F5182 User Manual, Appendix A, section A.4
- * Note: only windows 0 and 1 have remap capability.
- */
-struct orion5x_win_registers {
-	u32 ctrl;
-	u32 base;
-	u32 remap_lo;
-	u32 remap_hi;
-};
-
-/*
- * CPU control and status Registers
- * Source: 88F5182 User Manual, Appendix A, section A.4
- */
-struct orion5x_cpu_registers {
-	u32 config;	/*0x20100 */
-	u32 ctrl_stat;	/*0x20104 */
-	u32 rstoutn_mask; /* 0x20108 */
-	u32 sys_soft_rst; /* 0x2010C */
-	u32 ahb_mbus_cause_irq; /* 0x20110 */
-	u32 ahb_mbus_mask_irq; /* 0x20114 */
-};
-
-/*
- * DDR SDRAM Controller Address Decode Registers
- * Source: 88F5182 User Manual, Appendix A, section A.5.1
- */
-struct orion5x_ddr_addr_decode_registers {
-	u32 base;
-	u32 size;
-};
-
-/*
- * functions
- */
-void reset_cpu(unsigned long ignored);
-u32 orion5x_device_id(void);
-u32 orion5x_device_rev(void);
-unsigned int orion5x_winctrl_calcsize(unsigned int sizeval);
-#endif /* __ASSEMBLY__ */
-#endif /* _ORION5X_CPU_H */
--- a/arch/arm/include/asm/arch-orion5x/mv88f5182.h
+++ b/arch/arm/include/asm/arch-orion5x/mv88f5182.h
@@ -1,40 +0,0 @@
-/*
- * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
- *
- * Based on original Kirkwood 88F6182 support which is
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * Header file for Feroceon CPU core 88F5182 SOC.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#ifndef _CONFIG_88F5182_H
-#define _CONFIG_88F5182_H
-
-/* SOC specific definitions */
-#define F88F5182_REGS_PHYS_BASE		0xf1000000
-#define ORION5X_REGS_PHY_BASE		F88F5182_REGS_PHYS_BASE
-
-/* TCLK Core Clock defination */
-#define CONFIG_SYS_TCLK			166000000 /* 166MHz */
-
-#endif /* _CONFIG_88F5182_H */
--- a/arch/arm/include/asm/arch-orion5x/orion5x.h
+++ b/arch/arm/include/asm/arch-orion5x/orion5x.h
@@ -1,69 +0,0 @@
-/*
- * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
- *
- * Based on original Kirkwood support which is
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * Header file for Marvell's Orion SoC with Feroceon CPU core.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#ifndef _ASM_ARCH_ORION5X_H
-#define _ASM_ARCH_ORION5X_H
-
-#ifndef __ASSEMBLY__
-#include <asm/types.h>
-#include <asm/io.h>
-#endif /* __ASSEMBLY__ */
-
-#if defined(CONFIG_FEROCEON)
-#include <asm/arch/cpu.h>
-
-/* SOC specific definations */
-#define ORION5X_REGISTER(x)			(ORION5X_REGS_PHY_BASE + x)
-
-/* Documented registers */
-#define ORION5X_TWSI_BASE			(ORION5X_REGISTER(0x11000))
-#define ORION5X_UART0_BASE			(ORION5X_REGISTER(0x12000))
-#define ORION5X_UART1_BASE			(ORION5X_REGISTER(0x12100))
-#define ORION5X_MPP_BASE			(ORION5X_REGISTER(0x10000))
-#define ORION5X_GPIO_BASE			(ORION5X_REGISTER(0x10100))
-#define ORION5X_CPU_WIN_BASE			(ORION5X_REGISTER(0x20000))
-#define ORION5X_CPU_REG_BASE			(ORION5X_REGISTER(0x20100))
-#define ORION5X_TIMER_BASE			(ORION5X_REGISTER(0x20300))
-#define ORION5X_REG_PCI_BASE			(ORION5X_REGISTER(0x30000))
-#define ORION5X_REG_PCIE_BASE			(ORION5X_REGISTER(0x40000))
-#define ORION5X_USB20_PORT0_BASE		(ORION5X_REGISTER(0x50000))
-#define ORION5X_USB20_PORT1_BASE		(ORION5X_REGISTER(0xA0000))
-#define ORION5X_EGIGA_BASE			(ORION5X_REGISTER(0x72000))
-
-#define CONFIG_MAX_RAM_BANK_SIZE		(64*1024*1024)
-
-/* include here SoC variants. 5181, 5281, 6183 should go here when
-   adding support for them, and this comment should then be updated. */
-#if defined(CONFIG_88F5182)
-#include <asm/arch/mv88f5182.h>
-#else
-#error "SOC Name not defined"
-#endif
-#endif /* CONFIG_FEROCEON */
-#endif /* _ASM_ARCH_ORION5X_H */
--- a/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h
+++ b/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h
@@ -1,652 +0,0 @@
-/*
- * (C) Copyright 2003
- * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/************************************************
- * NAME	    : s3c24x0.h
- * Version  : 31.3.2003
- *
- * common stuff for SAMSUNG S3C24X0 SoC
- ************************************************/
-
-#ifndef __S3C24X0_H__
-#define __S3C24X0_H__
-
-/* Memory controller (see manual chapter 5) */
-struct s3c24x0_memctl {
-	u32	BWSCON;
-	u32	BANKCON[8];
-	u32	REFRESH;
-	u32	BANKSIZE;
-	u32	MRSRB6;
-	u32	MRSRB7;
-};
-
-
-/* USB HOST (see manual chapter 12) */
-struct s3c24x0_usb_host {
-	u32	HcRevision;
-	u32	HcControl;
-	u32	HcCommonStatus;
-	u32	HcInterruptStatus;
-	u32	HcInterruptEnable;
-	u32	HcInterruptDisable;
-	u32	HcHCCA;
-	u32	HcPeriodCuttendED;
-	u32	HcControlHeadED;
-	u32	HcControlCurrentED;
-	u32	HcBulkHeadED;
-	u32	HcBuldCurrentED;
-	u32	HcDoneHead;
-	u32	HcRmInterval;
-	u32	HcFmRemaining;
-	u32	HcFmNumber;
-	u32	HcPeriodicStart;
-	u32	HcLSThreshold;
-	u32	HcRhDescriptorA;
-	u32	HcRhDescriptorB;
-	u32	HcRhStatus;
-	u32	HcRhPortStatus1;
-	u32	HcRhPortStatus2;
-};
-
-
-/* INTERRUPT (see manual chapter 14) */
-struct s3c24x0_interrupt {
-	u32	SRCPND;
-	u32	INTMOD;
-	u32	INTMSK;
-	u32	PRIORITY;
-	u32	INTPND;
-	u32	INTOFFSET;
-#ifdef CONFIG_S3C2410
-	u32	SUBSRCPND;
-	u32	INTSUBMSK;
-#endif
-};
-
-
-/* DMAS (see manual chapter 8) */
-struct s3c24x0_dma {
-	u32	DISRC;
-#ifdef CONFIG_S3C2410
-	u32	DISRCC;
-#endif
-	u32	DIDST;
-#ifdef CONFIG_S3C2410
-	u32	DIDSTC;
-#endif
-	u32	DCON;
-	u32	DSTAT;
-	u32	DCSRC;
-	u32	DCDST;
-	u32	DMASKTRIG;
-#ifdef CONFIG_S3C2400
-	u32	res[1];
-#endif
-#ifdef CONFIG_S3C2410
-	u32	res[7];
-#endif
-};
-
-struct s3c24x0_dmas {
-	struct s3c24x0_dma	dma[4];
-};
-
-
-/* CLOCK & POWER MANAGEMENT (see S3C2400 manual chapter 6) */
-/*                          (see S3C2410 manual chapter 7) */
-struct s3c24x0_clock_power {
-	u32	LOCKTIME;
-	u32	MPLLCON;
-	u32	UPLLCON;
-	u32	CLKCON;
-	u32	CLKSLOW;
-	u32	CLKDIVN;
-};
-
-
-/* LCD CONTROLLER (see manual chapter 15) */
-struct s3c24x0_lcd {
-	u32	LCDCON1;
-	u32	LCDCON2;
-	u32	LCDCON3;
-	u32	LCDCON4;
-	u32	LCDCON5;
-	u32	LCDSADDR1;
-	u32	LCDSADDR2;
-	u32	LCDSADDR3;
-	u32	REDLUT;
-	u32	GREENLUT;
-	u32	BLUELUT;
-	u32	res[8];
-	u32	DITHMODE;
-	u32	TPAL;
-#ifdef CONFIG_S3C2410
-	u32	LCDINTPND;
-	u32	LCDSRCPND;
-	u32	LCDINTMSK;
-	u32	LPCSEL;
-#endif
-};
-
-
-/* NAND FLASH (see S3C2410 manual chapter 6) */
-struct s3c2410_nand {
-	u32	NFCONF;
-	u32	NFCMD;
-	u32	NFADDR;
-	u32	NFDATA;
-	u32	NFSTAT;
-	u32	NFECC;
-};
-
-
-/* UART (see manual chapter 11) */
-struct s3c24x0_uart {
-	u32	ULCON;
-	u32	UCON;
-	u32	UFCON;
-	u32	UMCON;
-	u32	UTRSTAT;
-	u32	UERSTAT;
-	u32	UFSTAT;
-	u32	UMSTAT;
-#ifdef __BIG_ENDIAN
-	u8	res1[3];
-	u8	UTXH;
-	u8	res2[3];
-	u8	URXH;
-#else /* Little Endian */
-	u8	UTXH;
-	u8	res1[3];
-	u8	URXH;
-	u8	res2[3];
-#endif
-	u32	UBRDIV;
-};
-
-
-/* PWM TIMER (see manual chapter 10) */
-struct s3c24x0_timer {
-	u32	TCNTB;
-	u32	TCMPB;
-	u32	TCNTO;
-};
-
-struct s3c24x0_timers {
-	u32	TCFG0;
-	u32	TCFG1;
-	u32	TCON;
-	struct s3c24x0_timer	ch[4];
-	u32	TCNTB4;
-	u32	TCNTO4;
-};
-
-
-/* USB DEVICE (see manual chapter 13) */
-struct s3c24x0_usb_dev_fifos {
-#ifdef __BIG_ENDIAN
-	u8	res[3];
-	u8	EP_FIFO_REG;
-#else /*  little endian */
-	u8	EP_FIFO_REG;
-	u8	res[3];
-#endif
-};
-
-struct s3c24x0_usb_dev_dmas {
-#ifdef __BIG_ENDIAN
-	u8	res1[3];
-	u8	EP_DMA_CON;
-	u8	res2[3];
-	u8	EP_DMA_UNIT;
-	u8	res3[3];
-	u8	EP_DMA_FIFO;
-	u8	res4[3];
-	u8	EP_DMA_TTC_L;
-	u8	res5[3];
-	u8	EP_DMA_TTC_M;
-	u8	res6[3];
-	u8	EP_DMA_TTC_H;
-#else /*  little endian */
-	u8	EP_DMA_CON;
-	u8	res1[3];
-	u8	EP_DMA_UNIT;
-	u8	res2[3];
-	u8	EP_DMA_FIFO;
-	u8	res3[3];
-	u8	EP_DMA_TTC_L;
-	u8	res4[3];
-	u8	EP_DMA_TTC_M;
-	u8	res5[3];
-	u8	EP_DMA_TTC_H;
-	u8	res6[3];
-#endif
-};
-
-struct s3c24x0_usb_device {
-#ifdef __BIG_ENDIAN
-	u8	res1[3];
-	u8	FUNC_ADDR_REG;
-	u8	res2[3];
-	u8	PWR_REG;
-	u8	res3[3];
-	u8	EP_INT_REG;
-	u8	res4[15];
-	u8	USB_INT_REG;
-	u8	res5[3];
-	u8	EP_INT_EN_REG;
-	u8	res6[15];
-	u8	USB_INT_EN_REG;
-	u8	res7[3];
-	u8	FRAME_NUM1_REG;
-	u8	res8[3];
-	u8	FRAME_NUM2_REG;
-	u8	res9[3];
-	u8	INDEX_REG;
-	u8	res10[7];
-	u8	MAXP_REG;
-	u8	res11[3];
-	u8	EP0_CSR_IN_CSR1_REG;
-	u8	res12[3];
-	u8	IN_CSR2_REG;
-	u8	res13[7];
-	u8	OUT_CSR1_REG;
-	u8	res14[3];
-	u8	OUT_CSR2_REG;
-	u8	res15[3];
-	u8	OUT_FIFO_CNT1_REG;
-	u8	res16[3];
-	u8	OUT_FIFO_CNT2_REG;
-#else /*  little endian */
-	u8	FUNC_ADDR_REG;
-	u8	res1[3];
-	u8	PWR_REG;
-	u8	res2[3];
-	u8	EP_INT_REG;
-	u8	res3[15];
-	u8	USB_INT_REG;
-	u8	res4[3];
-	u8	EP_INT_EN_REG;
-	u8	res5[15];
-	u8	USB_INT_EN_REG;
-	u8	res6[3];
-	u8	FRAME_NUM1_REG;
-	u8	res7[3];
-	u8	FRAME_NUM2_REG;
-	u8	res8[3];
-	u8	INDEX_REG;
-	u8	res9[7];
-	u8	MAXP_REG;
-	u8	res10[7];
-	u8	EP0_CSR_IN_CSR1_REG;
-	u8	res11[3];
-	u8	IN_CSR2_REG;
-	u8	res12[3];
-	u8	OUT_CSR1_REG;
-	u8	res13[7];
-	u8	OUT_CSR2_REG;
-	u8	res14[3];
-	u8	OUT_FIFO_CNT1_REG;
-	u8	res15[3];
-	u8	OUT_FIFO_CNT2_REG;
-	u8	res16[3];
-#endif /*  __BIG_ENDIAN */
-	struct s3c24x0_usb_dev_fifos	fifo[5];
-	struct s3c24x0_usb_dev_dmas	dma[5];
-};
-
-
-/* WATCH DOG TIMER (see manual chapter 18) */
-struct s3c24x0_watchdog {
-	u32	WTCON;
-	u32	WTDAT;
-	u32	WTCNT;
-};
-
-
-/* IIC (see manual chapter 20) */
-struct s3c24x0_i2c {
-	u32	IICCON;
-	u32	IICSTAT;
-	u32	IICADD;
-	u32	IICDS;
-};
-
-
-/* IIS (see manual chapter 21) */
-struct s3c24x0_i2s {
-#ifdef __BIG_ENDIAN
-	u16	res1;
-	u16	IISCON;
-	u16	res2;
-	u16	IISMOD;
-	u16	res3;
-	u16	IISPSR;
-	u16	res4;
-	u16	IISFCON;
-	u16	res5;
-	u16	IISFIFO;
-#else /*  little endian */
-	u16	IISCON;
-	u16	res1;
-	u16	IISMOD;
-	u16	res2;
-	u16	IISPSR;
-	u16	res3;
-	u16	IISFCON;
-	u16	res4;
-	u16	IISFIFO;
-	u16	res5;
-#endif
-};
-
-
-/* I/O PORT (see manual chapter 9) */
-struct s3c24x0_gpio {
-#ifdef CONFIG_S3C2400
-	u32	PACON;
-	u32	PADAT;
-
-	u32	PBCON;
-	u32	PBDAT;
-	u32	PBUP;
-
-	u32	PCCON;
-	u32	PCDAT;
-	u32	PCUP;
-
-	u32	PDCON;
-	u32	PDDAT;
-	u32	PDUP;
-
-	u32	PECON;
-	u32	PEDAT;
-	u32	PEUP;
-
-	u32	PFCON;
-	u32	PFDAT;
-	u32	PFUP;
-
-	u32	PGCON;
-	u32	PGDAT;
-	u32	PGUP;
-
-	u32	OPENCR;
-
-	u32	MISCCR;
-	u32	EXTINT;
-#endif
-#ifdef CONFIG_S3C2410
-	u32	GPACON;
-	u32	GPADAT;
-	u32	res1[2];
-	u32	GPBCON;
-	u32	GPBDAT;
-	u32	GPBUP;
-	u32	res2;
-	u32	GPCCON;
-	u32	GPCDAT;
-	u32	GPCUP;
-	u32	res3;
-	u32	GPDCON;
-	u32	GPDDAT;
-	u32	GPDUP;
-	u32	res4;
-	u32	GPECON;
-	u32	GPEDAT;
-	u32	GPEUP;
-	u32	res5;
-	u32	GPFCON;
-	u32	GPFDAT;
-	u32	GPFUP;
-	u32	res6;
-	u32	GPGCON;
-	u32	GPGDAT;
-	u32	GPGUP;
-	u32	res7;
-	u32	GPHCON;
-	u32	GPHDAT;
-	u32	GPHUP;
-	u32	res8;
-
-	u32	MISCCR;
-	u32	DCLKCON;
-	u32	EXTINT0;
-	u32	EXTINT1;
-	u32	EXTINT2;
-	u32	EINTFLT0;
-	u32	EINTFLT1;
-	u32	EINTFLT2;
-	u32	EINTFLT3;
-	u32	EINTMASK;
-	u32	EINTPEND;
-	u32	GSTATUS0;
-	u32	GSTATUS1;
-	u32	GSTATUS2;
-	u32	GSTATUS3;
-	u32	GSTATUS4;
-#endif
-};
-
-
-/* RTC (see manual chapter 17) */
-struct s3c24x0_rtc {
-#ifdef __BIG_ENDIAN
-	u8	res1[67];
-	u8	RTCCON;
-	u8	res2[3];
-	u8	TICNT;
-	u8	res3[11];
-	u8	RTCALM;
-	u8	res4[3];
-	u8	ALMSEC;
-	u8	res5[3];
-	u8	ALMMIN;
-	u8	res6[3];
-	u8	ALMHOUR;
-	u8	res7[3];
-	u8	ALMDATE;
-	u8	res8[3];
-	u8	ALMMON;
-	u8	res9[3];
-	u8	ALMYEAR;
-	u8	res10[3];
-	u8	RTCRST;
-	u8	res11[3];
-	u8	BCDSEC;
-	u8	res12[3];
-	u8	BCDMIN;
-	u8	res13[3];
-	u8	BCDHOUR;
-	u8	res14[3];
-	u8	BCDDATE;
-	u8	res15[3];
-	u8	BCDDAY;
-	u8	res16[3];
-	u8	BCDMON;
-	u8	res17[3];
-	u8	BCDYEAR;
-#else /*  little endian */
-	u8	res0[64];
-	u8	RTCCON;
-	u8	res1[3];
-	u8	TICNT;
-	u8	res2[11];
-	u8	RTCALM;
-	u8	res3[3];
-	u8	ALMSEC;
-	u8	res4[3];
-	u8	ALMMIN;
-	u8	res5[3];
-	u8	ALMHOUR;
-	u8	res6[3];
-	u8	ALMDATE;
-	u8	res7[3];
-	u8	ALMMON;
-	u8	res8[3];
-	u8	ALMYEAR;
-	u8	res9[3];
-	u8	RTCRST;
-	u8	res10[3];
-	u8	BCDSEC;
-	u8	res11[3];
-	u8	BCDMIN;
-	u8	res12[3];
-	u8	BCDHOUR;
-	u8	res13[3];
-	u8	BCDDATE;
-	u8	res14[3];
-	u8	BCDDAY;
-	u8	res15[3];
-	u8	BCDMON;
-	u8	res16[3];
-	u8	BCDYEAR;
-	u8	res17[3];
-#endif
-};
-
-
-/* ADC (see manual chapter 16) */
-struct s3c2400_adc {
-	u32	ADCCON;
-	u32	ADCDAT;
-};
-
-
-/* ADC (see manual chapter 16) */
-struct s3c2410_adc {
-	u32	ADCCON;
-	u32	ADCTSC;
-	u32	ADCDLY;
-	u32	ADCDAT0;
-	u32	ADCDAT1;
-};
-
-
-/* SPI (see manual chapter 22) */
-struct s3c24x0_spi_channel {
-	u8	SPCON;
-	u8	res1[3];
-	u8	SPSTA;
-	u8	res2[3];
-	u8	SPPIN;
-	u8	res3[3];
-	u8	SPPRE;
-	u8	res4[3];
-	u8	SPTDAT;
-	u8	res5[3];
-	u8	SPRDAT;
-	u8	res6[3];
-	u8	res7[16];
-};
-
-struct s3c24x0_spi {
-	struct s3c24x0_spi_channel	ch[S3C24X0_SPI_CHANNELS];
-};
-
-
-/* MMC INTERFACE (see S3C2400 manual chapter 19) */
-struct s3c2400_mmc {
-#ifdef __BIG_ENDIAN
-	u8	res1[3];
-	u8	MMCON;
-	u8	res2[3];
-	u8	MMCRR;
-	u8	res3[3];
-	u8	MMFCON;
-	u8	res4[3];
-	u8	MMSTA;
-	u16	res5;
-	u16	MMFSTA;
-	u8	res6[3];
-	u8	MMPRE;
-	u16	res7;
-	u16	MMLEN;
-	u8	res8[3];
-	u8	MMCR7;
-	u32	MMRSP[4];
-	u8	res9[3];
-	u8	MMCMD0;
-	u32	MMCMD1;
-	u16	res10;
-	u16	MMCR16;
-	u8	res11[3];
-	u8	MMDAT;
-#else
-	u8	MMCON;
-	u8	res1[3];
-	u8	MMCRR;
-	u8	res2[3];
-	u8	MMFCON;
-	u8	res3[3];
-	u8	MMSTA;
-	u8	res4[3];
-	u16	MMFSTA;
-	u16	res5;
-	u8	MMPRE;
-	u8	res6[3];
-	u16	MMLEN;
-	u16	res7;
-	u8	MMCR7;
-	u8	res8[3];
-	u32	MMRSP[4];
-	u8	MMCMD0;
-	u8	res9[3];
-	u32	MMCMD1;
-	u16	MMCR16;
-	u16	res10;
-	u8	MMDAT;
-	u8	res11[3];
-#endif
-};
-
-
-/* SD INTERFACE (see S3C2410 manual chapter 19) */
-struct s3c2410_sdi {
-	u32	SDICON;
-	u32	SDIPRE;
-	u32	SDICARG;
-	u32	SDICCON;
-	u32	SDICSTA;
-	u32	SDIRSP0;
-	u32	SDIRSP1;
-	u32	SDIRSP2;
-	u32	SDIRSP3;
-	u32	SDIDTIMER;
-	u32	SDIBSIZE;
-	u32	SDIDCON;
-	u32	SDIDCNT;
-	u32	SDIDSTA;
-	u32	SDIFSTA;
-#ifdef __BIG_ENDIAN
-	u8	res[3];
-	u8	SDIDAT;
-#else
-	u8	SDIDAT;
-	u8	res[3];
-#endif
-	u32	SDIIMSK;
-};
-
-#endif /*__S3C24X0_H__*/
--- a/arch/arm/include/asm/arch-s5pc1xx/gpio.h
+++ b/arch/arm/include/asm/arch-s5pc1xx/gpio.h
@@ -1,158 +0,0 @@
-/*
- * (C) Copyright 2009 Samsung Electronics
- * Minkyu Kang <mk7.kang@samsung.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARCH_GPIO_H
-#define __ASM_ARCH_GPIO_H
-
-#ifndef __ASSEMBLY__
-struct s5p_gpio_bank {
-	unsigned int	con;
-	unsigned int	dat;
-	unsigned int	pull;
-	unsigned int	drv;
-	unsigned int	pdn_con;
-	unsigned int	pdn_pull;
-	unsigned char	res1[8];
-};
-
-struct s5pc100_gpio {
-	struct s5p_gpio_bank gpio_a0;
-	struct s5p_gpio_bank gpio_a1;
-	struct s5p_gpio_bank gpio_b;
-	struct s5p_gpio_bank gpio_c;
-	struct s5p_gpio_bank gpio_d;
-	struct s5p_gpio_bank gpio_e0;
-	struct s5p_gpio_bank gpio_e1;
-	struct s5p_gpio_bank gpio_f0;
-	struct s5p_gpio_bank gpio_f1;
-	struct s5p_gpio_bank gpio_f2;
-	struct s5p_gpio_bank gpio_f3;
-	struct s5p_gpio_bank gpio_g0;
-	struct s5p_gpio_bank gpio_g1;
-	struct s5p_gpio_bank gpio_g2;
-	struct s5p_gpio_bank gpio_g3;
-	struct s5p_gpio_bank gpio_i;
-	struct s5p_gpio_bank gpio_j0;
-	struct s5p_gpio_bank gpio_j1;
-	struct s5p_gpio_bank gpio_j2;
-	struct s5p_gpio_bank gpio_j3;
-	struct s5p_gpio_bank gpio_j4;
-	struct s5p_gpio_bank gpio_k0;
-	struct s5p_gpio_bank gpio_k1;
-	struct s5p_gpio_bank gpio_k2;
-	struct s5p_gpio_bank gpio_k3;
-	struct s5p_gpio_bank gpio_l0;
-	struct s5p_gpio_bank gpio_l1;
-	struct s5p_gpio_bank gpio_l2;
-	struct s5p_gpio_bank gpio_l3;
-	struct s5p_gpio_bank gpio_l4;
-	struct s5p_gpio_bank gpio_h0;
-	struct s5p_gpio_bank gpio_h1;
-	struct s5p_gpio_bank gpio_h2;
-	struct s5p_gpio_bank gpio_h3;
-};
-
-struct s5pc110_gpio {
-	struct s5p_gpio_bank gpio_a0;
-	struct s5p_gpio_bank gpio_a1;
-	struct s5p_gpio_bank gpio_b;
-	struct s5p_gpio_bank gpio_c0;
-	struct s5p_gpio_bank gpio_c1;
-	struct s5p_gpio_bank gpio_d0;
-	struct s5p_gpio_bank gpio_d1;
-	struct s5p_gpio_bank gpio_e0;
-	struct s5p_gpio_bank gpio_e1;
-	struct s5p_gpio_bank gpio_f0;
-	struct s5p_gpio_bank gpio_f1;
-	struct s5p_gpio_bank gpio_f2;
-	struct s5p_gpio_bank gpio_f3;
-	struct s5p_gpio_bank gpio_g0;
-	struct s5p_gpio_bank gpio_g1;
-	struct s5p_gpio_bank gpio_g2;
-	struct s5p_gpio_bank gpio_g3;
-	struct s5p_gpio_bank gpio_i;
-	struct s5p_gpio_bank gpio_j0;
-	struct s5p_gpio_bank gpio_j1;
-	struct s5p_gpio_bank gpio_j2;
-	struct s5p_gpio_bank gpio_j3;
-	struct s5p_gpio_bank gpio_j4;
-	struct s5p_gpio_bank gpio_mp0_1;
-	struct s5p_gpio_bank gpio_mp0_2;
-	struct s5p_gpio_bank gpio_mp0_3;
-	struct s5p_gpio_bank gpio_mp0_4;
-	struct s5p_gpio_bank gpio_mp0_5;
-	struct s5p_gpio_bank gpio_mp0_6;
-	struct s5p_gpio_bank gpio_mp0_7;
-	struct s5p_gpio_bank gpio_mp1_0;
-	struct s5p_gpio_bank gpio_mp1_1;
-	struct s5p_gpio_bank gpio_mp1_2;
-	struct s5p_gpio_bank gpio_mp1_3;
-	struct s5p_gpio_bank gpio_mp1_4;
-	struct s5p_gpio_bank gpio_mp1_5;
-	struct s5p_gpio_bank gpio_mp1_6;
-	struct s5p_gpio_bank gpio_mp1_7;
-	struct s5p_gpio_bank gpio_mp1_8;
-	struct s5p_gpio_bank gpio_mp2_0;
-	struct s5p_gpio_bank gpio_mp2_1;
-	struct s5p_gpio_bank gpio_mp2_2;
-	struct s5p_gpio_bank gpio_mp2_3;
-	struct s5p_gpio_bank gpio_mp2_4;
-	struct s5p_gpio_bank gpio_mp2_5;
-	struct s5p_gpio_bank gpio_mp2_6;
-	struct s5p_gpio_bank gpio_mp2_7;
-	struct s5p_gpio_bank gpio_mp2_8;
-	struct s5p_gpio_bank res1[48];
-	struct s5p_gpio_bank gpio_h0;
-	struct s5p_gpio_bank gpio_h1;
-	struct s5p_gpio_bank gpio_h2;
-	struct s5p_gpio_bank gpio_h3;
-};
-
-/* functions */
-void gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg);
-void gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en);
-void gpio_direction_input(struct s5p_gpio_bank *bank, int gpio);
-void gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en);
-unsigned int gpio_get_value(struct s5p_gpio_bank *bank, int gpio);
-void gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode);
-void gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode);
-void gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode);
-#endif
-
-/* Pin configurations */
-#define GPIO_INPUT	0x0
-#define GPIO_OUTPUT	0x1
-#define GPIO_IRQ	0xf
-#define GPIO_FUNC(x)	(x)
-
-/* Pull mode */
-#define GPIO_PULL_NONE	0x0
-#define GPIO_PULL_DOWN	0x1
-#define GPIO_PULL_UP	0x2
-
-/* Drive Strength level */
-#define GPIO_DRV_1X	0x0
-#define GPIO_DRV_2X	0x1
-#define GPIO_DRV_3X	0x2
-#define GPIO_DRV_4X	0x3
-#define GPIO_DRV_FAST	0x0
-#define GPIO_DRV_SLOW	0x1
-
-#endif
--- a/arch/arm/include/asm/arch-s5pc1xx/smc.h
+++ b/arch/arm/include/asm/arch-s5pc1xx/smc.h
@@ -1,53 +0,0 @@
-/*
- * (C) Copyright 2010 Samsung Electronics
- * Naveen Krishna Ch <ch.naveen@samsung.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- * Note: This file contains the register description for Memory subsystem
- * 	 (SROM, NAND Flash, OneNand, DDR, OneDRAM) on S5PC1XX.
- *
- * 	 Only SROMC is defined as of now
- */
-
-#ifndef __ASM_ARCH_SMC_H_
-#define __ASM_ARCH_SMC_H_
-
-#define SMC_DATA16_WIDTH(x)    (1<<((x*4)+0))
-#define SMC_BYTE_ADDR_MODE(x)  (1<<((x*4)+1))  /* 0-> Half-word base address*/
-						/* 1-> Byte base address*/
-#define SMC_WAIT_ENABLE(x)     (1<<((x*4)+2))
-#define SMC_BYTE_ENABLE(x)     (1<<((x*4)+3))
-
-#define SMC_BC_TACS(x) (x << 28) /* 0clk     address set-up */
-#define SMC_BC_TCOS(x) (x << 24) /* 4clk     chip selection set-up */
-#define SMC_BC_TACC(x) (x << 16) /* 14clk    access cycle */
-#define SMC_BC_TCOH(x) (x << 12) /* 1clk     chip selection hold */
-#define SMC_BC_TAH(x)  (x << 8)  /* 4clk     address holding time */
-#define SMC_BC_TACP(x) (x << 4)  /* 6clk     page mode access cycle */
-#define SMC_BC_PMC(x)  (x << 0)  /* normal(1data)page mode configuration */
-
-#ifndef __ASSEMBLY__
-struct s5pc1xx_smc {
-	unsigned int	bw;
-	unsigned int	bc[6];
-};
-#endif	/* __ASSEMBLY__ */
-
-/* Configure the Band Width and Bank Control Regs for required SROMC Bank */
-void s5pc1xx_config_sromc(u32 srom_bank, u32 smc_bw_conf, u32 smc_bc_conf);
-
-#endif /* __ASM_ARCH_SMC_H_ */
--- a/arch/arm/include/asm/arch-spear/hardware.h
+++ b/arch/arm/include/asm/arch-spear/hardware.h
@@ -1,66 +0,0 @@
-/*
- * (C) Copyright 2009
- * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _ASM_ARCH_HARDWARE_H
-#define _ASM_ARCH_HARDWARE_H
-
-#define CONFIG_SYS_USBD_BASE			(0xE1100000)
-#define CONFIG_SYS_PLUG_BASE			(0xE1200000)
-#define CONFIG_SYS_FIFO_BASE			(0xE1000800)
-#define CONFIG_SYS_SMI_BASE			(0xFC000000)
-#define CONFIG_SPEAR_SYSCNTLBASE		(0xFCA00000)
-#define CONFIG_SPEAR_TIMERBASE			(0xFC800000)
-#define CONFIG_SPEAR_MISCBASE			(0xFCA80000)
-
-#define CONFIG_SYS_NAND_CLE			(1 << 16)
-#define CONFIG_SYS_NAND_ALE			(1 << 17)
-
-#if defined(CONFIG_SPEAR600)
-#define CONFIG_SYS_I2C_BASE			(0xD0200000)
-#define CONFIG_SPEAR_FSMCBASE			(0xD1800000)
-
-#elif defined(CONFIG_SPEAR300)
-#define CONFIG_SYS_I2C_BASE			(0xD0180000)
-#define CONFIG_SPEAR_FSMCBASE			(0x94000000)
-
-#elif defined(CONFIG_SPEAR310)
-#define CONFIG_SYS_I2C_BASE			(0xD0180000)
-#define CONFIG_SPEAR_FSMCBASE			(0x44000000)
-
-#undef CONFIG_SYS_NAND_CLE
-#undef CONFIG_SYS_NAND_ALE
-#define CONFIG_SYS_NAND_CLE			(1 << 17)
-#define CONFIG_SYS_NAND_ALE			(1 << 16)
-
-#define CONFIG_SPEAR_EMIBASE			(0x4F000000)
-#define CONFIG_SPEAR_RASBASE			(0xB4000000)
-
-#elif defined(CONFIG_SPEAR320)
-#define CONFIG_SYS_I2C_BASE			(0xD0180000)
-#define CONFIG_SPEAR_FSMCBASE			(0x4C000000)
-
-#define CONFIG_SPEAR_EMIBASE			(0x40000000)
-#define CONFIG_SPEAR_RASBASE			(0xB3000000)
-
-#endif
-#endif /* _ASM_ARCH_HARDWARE_H */
--- a/arch/arm/include/asm/arch-spear/spr_defs.h
+++ b/arch/arm/include/asm/arch-spear/spr_defs.h
@@ -1,46 +0,0 @@
-/*
- * (C) Copyright 2009
- * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __SPR_DEFS_H__
-#define __SPR_DEFS_H__
-
-extern int spear_board_init(ulong);
-extern void setfreq(unsigned int, unsigned int);
-extern unsigned int setfreq_sz;
-
-struct chip_data {
-	int cpufreq;
-	int dramfreq;
-	int dramtype;
-	uchar version[32];
-};
-
-/* HW mac id in i2c memory definitions */
-#define MAGIC_OFF	0x0
-#define MAGIC_LEN	0x2
-#define MAGIC_BYTE0	0x55
-#define MAGIC_BYTE1	0xAA
-#define MAC_OFF		0x2
-#define MAC_LEN		0x6
-
-#endif
--- a/arch/arm/include/asm/arch-spear/spr_emi.h
+++ b/arch/arm/include/asm/arch-spear/spr_emi.h
@@ -1,54 +0,0 @@
-/*
- * (C) Copyright 2009
- * Ryan CHEN, ST Micoelectronics, ryan.chen@st.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __SPEAR_EMI_H__
-#define __SPEAR_EMI_H__
-
-#ifdef CONFIG_SPEAR_EMI
-
-struct emi_bank_regs {
-	u32 tap;
-	u32 tsdp;
-	u32 tdpw;
-	u32 tdpr;
-	u32 tdcs;
-	u32 control;
-};
-
-struct emi_regs {
-	struct emi_bank_regs bank_regs[CONFIG_SYS_MAX_FLASH_BANKS];
-	u32 tout;
-	u32 ack;
-	u32 irq;
-};
-
-#define EMI_ACKMSK		0x40
-
-/* control register definitions */
-#define EMI_CNTL_ENBBYTEW	(1 << 2)
-#define EMI_CNTL_ENBBYTER	(1 << 3)
-#define EMI_CNTL_ENBBYTERW	(EMI_CNTL_ENBBYTER | EMI_CNTL_ENBBYTEW)
-
-#endif
-
-#endif
--- a/arch/arm/include/asm/arch-spear/spr_gpt.h
+++ b/arch/arm/include/asm/arch-spear/spr_gpt.h
@@ -1,85 +0,0 @@
-/*
- * (C) Copyright 2009
- * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _SPR_GPT_H
-#define _SPR_GPT_H
-
-struct gpt_regs {
-	u8 reserved[0x80];
-	u32 control;
-	u32 status;
-	u32 compare;
-	u32 count;
-	u32 capture_re;
-	u32 capture_fe;
-};
-
-/*
- * TIMER_CONTROL register settings
- */
-
-#define GPT_PRESCALER_MASK		0x000F
-#define GPT_PRESCALER_1			0x0000
-#define GPT_PRESCALER_2 		0x0001
-#define GPT_PRESCALER_4 		0x0002
-#define GPT_PRESCALER_8 		0x0003
-#define GPT_PRESCALER_16		0x0004
-#define GPT_PRESCALER_32		0x0005
-#define GPT_PRESCALER_64		0x0006
-#define GPT_PRESCALER_128		0x0007
-#define GPT_PRESCALER_256		0x0008
-
-#define GPT_MODE_SINGLE_SHOT		0x0010
-#define GPT_MODE_AUTO_RELOAD		0x0000
-
-#define GPT_ENABLE			0x0020
-
-#define GPT_CAPT_MODE_MASK		0x00C0
-#define GPT_CAPT_MODE_NONE		0x0000
-#define GPT_CAPT_MODE_RE		0x0040
-#define GPT_CAPT_MODE_FE		0x0080
-#define GPT_CAPT_MODE_BOTH		0x00C0
-
-#define GPT_INT_MATCH			0x0100
-#define GPT_INT_FE			0x0200
-#define GPT_INT_RE			0x0400
-
-/*
- * TIMER_STATUS register settings
- */
-
-#define GPT_STS_MATCH			0x0001
-#define GPT_STS_FE			0x0002
-#define GPT_STS_RE			0x0004
-
-/*
- * TIMER_COMPARE register settings
- */
-
-#define GPT_FREE_RUNNING		0xFFFF
-
-/* Timer, HZ specific defines */
-#define CONFIG_SPEAR_HZ			(1000)
-#define CONFIG_SPEAR_HZ_CLOCK		(8300000)
-
-#endif
--- a/arch/arm/include/asm/arch-spear/spr_i2c.h
+++ b/arch/arm/include/asm/arch-spear/spr_i2c.h
@@ -1,146 +0,0 @@
-/*
- * (C) Copyright 2009
- * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __SPR_I2C_H_
-#define __SPR_I2C_H_
-
-struct i2c_regs {
-	u32 ic_con;
-	u32 ic_tar;
-	u32 ic_sar;
-	u32 ic_hs_maddr;
-	u32 ic_cmd_data;
-	u32 ic_ss_scl_hcnt;
-	u32 ic_ss_scl_lcnt;
-	u32 ic_fs_scl_hcnt;
-	u32 ic_fs_scl_lcnt;
-	u32 ic_hs_scl_hcnt;
-	u32 ic_hs_scl_lcnt;
-	u32 ic_intr_stat;
-	u32 ic_intr_mask;
-	u32 ic_raw_intr_stat;
-	u32 ic_rx_tl;
-	u32 ic_tx_tl;
-	u32 ic_clr_intr;
-	u32 ic_clr_rx_under;
-	u32 ic_clr_rx_over;
-	u32 ic_clr_tx_over;
-	u32 ic_clr_rd_req;
-	u32 ic_clr_tx_abrt;
-	u32 ic_clr_rx_done;
-	u32 ic_clr_activity;
-	u32 ic_clr_stop_det;
-	u32 ic_clr_start_det;
-	u32 ic_clr_gen_call;
-	u32 ic_enable;
-	u32 ic_status;
-	u32 ic_txflr;
-	u32 ix_rxflr;
-	u32 reserved_1;
-	u32 ic_tx_abrt_source;
-};
-
-#define IC_CLK			166
-#define NANO_TO_MICRO		1000
-
-/* High and low times in different speed modes (in ns) */
-#define MIN_SS_SCL_HIGHTIME	4000
-#define MIN_SS_SCL_LOWTIME	5000
-#define MIN_FS_SCL_HIGHTIME	800
-#define MIN_FS_SCL_LOWTIME	1700
-#define MIN_HS_SCL_HIGHTIME	60
-#define MIN_HS_SCL_LOWTIME	160
-
-/* Worst case timeout for 1 byte is kept as 2ms */
-#define I2C_BYTE_TO		(CONFIG_SYS_HZ/500)
-#define I2C_STOPDET_TO		(CONFIG_SYS_HZ/500)
-#define I2C_BYTE_TO_BB		(I2C_BYTE_TO * 16)
-
-/* i2c control register definitions */
-#define IC_CON_SD		0x0040
-#define IC_CON_RE		0x0020
-#define IC_CON_10BITADDRMASTER	0x0010
-#define IC_CON_10BITADDR_SLAVE	0x0008
-#define IC_CON_SPD_MSK		0x0006
-#define IC_CON_SPD_SS		0x0002
-#define IC_CON_SPD_FS		0x0004
-#define IC_CON_SPD_HS		0x0006
-#define IC_CON_MM		0x0001
-
-/* i2c target address register definitions */
-#define TAR_ADDR		0x0050
-
-/* i2c slave address register definitions */
-#define IC_SLAVE_ADDR		0x0002
-
-/* i2c data buffer and command register definitions */
-#define IC_CMD			0x0100
-
-/* i2c interrupt status register definitions */
-#define IC_GEN_CALL		0x0800
-#define IC_START_DET		0x0400
-#define IC_STOP_DET		0x0200
-#define IC_ACTIVITY		0x0100
-#define IC_RX_DONE		0x0080
-#define IC_TX_ABRT		0x0040
-#define IC_RD_REQ		0x0020
-#define IC_TX_EMPTY		0x0010
-#define IC_TX_OVER		0x0008
-#define IC_RX_FULL		0x0004
-#define IC_RX_OVER 		0x0002
-#define IC_RX_UNDER		0x0001
-
-/* fifo threshold register definitions */
-#define IC_TL0			0x00
-#define IC_TL1			0x01
-#define IC_TL2			0x02
-#define IC_TL3			0x03
-#define IC_TL4			0x04
-#define IC_TL5			0x05
-#define IC_TL6			0x06
-#define IC_TL7			0x07
-#define IC_RX_TL		IC_TL0
-#define IC_TX_TL		IC_TL0
-
-/* i2c enable register definitions */
-#define IC_ENABLE_0B		0x0001
-
-/* i2c status register  definitions */
-#define IC_STATUS_SA		0x0040
-#define IC_STATUS_MA		0x0020
-#define IC_STATUS_RFF		0x0010
-#define IC_STATUS_RFNE		0x0008
-#define IC_STATUS_TFE		0x0004
-#define IC_STATUS_TFNF		0x0002
-#define IC_STATUS_ACT		0x0001
-
-/* Speed Selection */
-#define IC_SPEED_MODE_STANDARD	1
-#define IC_SPEED_MODE_FAST	2
-#define IC_SPEED_MODE_MAX	3
-
-#define I2C_MAX_SPEED		3400000
-#define I2C_FAST_SPEED		400000
-#define I2C_STANDARD_SPEED	100000
-
-#endif /* __SPR_I2C_H_ */
--- a/arch/arm/include/asm/arch-spear/spr_misc.h
+++ b/arch/arm/include/asm/arch-spear/spr_misc.h
@@ -1,130 +0,0 @@
-/*
- * (C) Copyright 2009
- * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _SPR_MISC_H
-#define _SPR_MISC_H
-
-struct misc_regs {
-	u32 auto_cfg_reg;	/* 0x0 */
-	u32 armdbg_ctr_reg;	/* 0x4 */
-	u32 pll1_cntl;		/* 0x8 */
-	u32 pll1_frq;		/* 0xc */
-	u32 pll1_mod;		/* 0x10 */
-	u32 pll2_cntl;		/* 0x14 */
-	u32 pll2_frq;		/* 0x18 */
-	u32 pll2_mod;		/* 0x1C */
-	u32 pll_ctr_reg;	/* 0x20 */
-	u32 amba_clk_cfg;	/* 0x24 */
-	u32 periph_clk_cfg;	/* 0x28 */
-	u32 periph1_clken;	/* 0x2C */
-	u32 periph2_clken;	/* 0x30 */
-	u32 ras_clken;		/* 0x34 */
-	u32 periph1_rst;	/* 0x38 */
-	u32 periph2_rst;	/* 0x3C */
-	u32 ras_rst;		/* 0x40 */
-	u32 prsc1_clk_cfg;	/* 0x44 */
-	u32 prsc2_clk_cfg;	/* 0x48 */
-	u32 prsc3_clk_cfg;	/* 0x4C */
-	u32 amem_cfg_ctrl;	/* 0x50 */
-	u32 port_cfg_ctrl;	/* 0x54 */
-	u32 reserved_1;		/* 0x58 */
-	u32 clcd_synth_clk;	/* 0x5C */
-	u32 irda_synth_clk;	/* 0x60 */
-	u32 uart_synth_clk;	/* 0x64 */
-	u32 gmac_synth_clk;	/* 0x68 */
-	u32 ras_synth1_clk;	/* 0x6C */
-	u32 ras_synth2_clk;	/* 0x70 */
-	u32 ras_synth3_clk;	/* 0x74 */
-	u32 ras_synth4_clk;	/* 0x78 */
-	u32 arb_icm_ml1;	/* 0x7C */
-	u32 arb_icm_ml2;	/* 0x80 */
-	u32 arb_icm_ml3;	/* 0x84 */
-	u32 arb_icm_ml4;	/* 0x88 */
-	u32 arb_icm_ml5;	/* 0x8C */
-	u32 arb_icm_ml6;	/* 0x90 */
-	u32 arb_icm_ml7;	/* 0x94 */
-	u32 arb_icm_ml8;	/* 0x98 */
-	u32 arb_icm_ml9;	/* 0x9C */
-	u32 dma_src_sel;	/* 0xA0 */
-	u32 uphy_ctr_reg;	/* 0xA4 */
-	u32 gmac_ctr_reg;	/* 0xA8 */
-	u32 port_bridge_ctrl;	/* 0xAC */
-	u32 reserved_2[4];	/* 0xB0--0xBC */
-	u32 prc1_ilck_ctrl_reg;	/* 0xC0 */
-	u32 prc2_ilck_ctrl_reg;	/* 0xC4 */
-	u32 prc3_ilck_ctrl_reg;	/* 0xC8 */
-	u32 prc4_ilck_ctrl_reg;	/* 0xCC */
-	u32 prc1_intr_ctrl_reg;	/* 0xD0 */
-	u32 prc2_intr_ctrl_reg;	/* 0xD4 */
-	u32 prc3_intr_ctrl_reg;	/* 0xD8 */
-	u32 prc4_intr_ctrl_reg;	/* 0xDC */
-	u32 powerdown_cfg_reg;	/* 0xE0 */
-	u32 ddr_1v8_compensation;	/* 0xE4  */
-	u32 ddr_2v5_compensation;	/* 0xE8 */
-	u32 core_3v3_compensation;	/* 0xEC */
-	u32 ddr_pad;		/* 0xF0 */
-	u32 bist1_ctr_reg;	/* 0xF4 */
-	u32 bist2_ctr_reg;	/* 0xF8 */
-	u32 bist3_ctr_reg;	/* 0xFC */
-	u32 bist4_ctr_reg;	/* 0x100 */
-	u32 bist5_ctr_reg;	/* 0x104 */
-	u32 bist1_rslt_reg;	/* 0x108 */
-	u32 bist2_rslt_reg;	/* 0x10C */
-	u32 bist3_rslt_reg;	/* 0x110 */
-	u32 bist4_rslt_reg;	/* 0x114 */
-	u32 bist5_rslt_reg;	/* 0x118 */
-	u32 syst_error_reg;	/* 0x11C */
-	u32 reserved_3[0x1FB8];	/* 0x120--0x7FFC */
-	u32 ras_gpp1_in;	/* 0x8000 */
-	u32 ras_gpp2_in;	/* 0x8004 */
-	u32 ras_gpp1_out;	/* 0x8008 */
-	u32 ras_gpp2_out;	/* 0x800C */
-};
-
-/* AUTO_CFG_REG value */
-#define MISC_SOCCFGMSK                  0x0000003F
-#define MISC_SOCCFG30                   0x0000000C
-#define MISC_SOCCFG31                   0x0000000D
-#define MISC_NANDDIS			0x00020000
-
-/* PERIPH_CLK_CFG value */
-#define MISC_GPT3SYNTH			0x00000400
-#define MISC_GPT4SYNTH			0x00000800
-
-/* PRSC_CLK_CFG value */
-/*
- * Fout = Fin / (2^(N+1) * (M + 1))
- */
-#define MISC_PRSC_N_1			0x00001000
-#define MISC_PRSC_M_9			0x00000009
-#define MISC_PRSC_N_4			0x00004000
-#define MISC_PRSC_M_399			0x0000018F
-#define MISC_PRSC_N_6			0x00006000
-#define MISC_PRSC_M_2593		0x00000A21
-#define MISC_PRSC_M_124			0x0000007C
-#define MISC_PRSC_CFG			(MISC_PRSC_N_1 | MISC_PRSC_M_9)
-
-/* PERIPH1_CLKEN, PERIPH1_RST value */
-#define MISC_USBDENB			0x01000000
-
-#endif
--- a/arch/arm/include/asm/arch-spear/spr_nand.h
+++ b/arch/arm/include/asm/arch-spear/spr_nand.h
@@ -1,57 +0,0 @@
-/*
- * (C) Copyright 2009
- * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __SPR_NAND_H__
-#define __SPR_NAND_H__
-
-struct fsmc_regs {
-	u32 reserved_1[0x10];
-	u32 genmemctrl_pc;
-	u32 reserved_2;
-	u32 genmemctrl_comm;
-	u32 genmemctrl_attrib;
-	u32 reserved_3;
-	u32 genmemctrl_ecc;
-};
-
-/* genmemctrl_pc register definitions */
-#define FSMC_RESET		(1 << 0)
-#define FSMC_WAITON		(1 << 1)
-#define FSMC_ENABLE		(1 << 2)
-#define FSMC_DEVTYPE_NAND	(1 << 3)
-#define FSMC_DEVWID_8		(0 << 4)
-#define FSMC_DEVWID_16		(1 << 4)
-#define FSMC_ECCEN		(1 << 6)
-#define FSMC_ECCPLEN_512	(0 << 7)
-#define FSMC_ECCPLEN_256	(1 << 7)
-#define FSMC_TCLR_1		(1 << 9)
-#define FSMC_TAR_1		(1 << 13)
-
-/* genmemctrl_comm register definitions */
-#define FSMC_TSET_0		(0 << 0)
-#define FSMC_TWAIT_6		(6 << 8)
-#define FSMC_THOLD_4		(4 << 16)
-#define FSMC_THIZ_1		(1 << 24)
-
-extern int spear_nand_init(struct nand_chip *nand);
-#endif
--- a/arch/arm/include/asm/arch-spear/spr_smi.h
+++ b/arch/arm/include/asm/arch-spear/spr_smi.h
@@ -1,115 +0,0 @@
-/*
- * (C) Copyright 2009
- * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef SPR_SMI_H
-#define SPR_SMI_H
-
-/* 0xF800.0000 . 0xFBFF.FFFF	64MB	SMI (Serial Flash Mem) */
-/* 0xFC00.0000 . 0xFC1F.FFFF	2MB	SMI (Serial Flash Reg.) */
-
-#define FLASH_START_ADDRESS	CONFIG_SYS_FLASH_BASE
-#define FLASH_BANK_SIZE		CONFIG_SYS_FLASH_BANK_SIZE
-
-#define SMIBANK0_BASE		(FLASH_START_ADDRESS)
-#define SMIBANK1_BASE		(SMIBANK0_BASE + FLASH_BANK_SIZE)
-#define SMIBANK2_BASE		(SMIBANK1_BASE + FLASH_BANK_SIZE)
-#define SMIBANK3_BASE		(SMIBANK2_BASE + FLASH_BANK_SIZE)
-
-#define BANK0			0
-#define BANK1			1
-#define BANK2			2
-#define BANK3			3
-
-struct smi_regs {
-	u32 smi_cr1;
-	u32 smi_cr2;
-	u32 smi_sr;
-	u32 smi_tr;
-	u32 smi_rr;
-};
-
-/* CONTROL REG 1 */
-#define BANK_EN			0x0000000F	/* enables all banks */
-#define DSEL_TIME		0x00000060	/* Deselect time */
-#define PRESCAL5		0x00000500	/* AHB_CK prescaling value */
-#define PRESCALA		0x00000A00	/* AHB_CK prescaling value */
-#define PRESCAL3		0x00000300	/* AHB_CK prescaling value */
-#define PRESCAL4		0x00000400	/* AHB_CK prescaling value */
-#define SW_MODE			0x10000000	/* enables SW Mode */
-#define WB_MODE			0x20000000	/* Write Burst Mode */
-#define FAST_MODE		0x00008000	/* Fast Mode */
-#define HOLD1			0x00010000
-
-/* CONTROL REG 2 */
-#define RD_STATUS_REG		0x00000400	/* reads status reg */
-#define WE			0x00000800	/* Write Enable */
-#define BANK0_SEL		0x00000000	/* Select Banck0 */
-#define BANK1_SEL		0x00001000	/* Select Banck1 */
-#define BANK2_SEL		0x00002000	/* Select Banck2 */
-#define BANK3_SEL		0x00003000	/* Select Banck3 */
-#define BANKSEL_SHIFT		12
-#define SEND			0x00000080	/* Send data */
-#define TX_LEN_1		0x00000001	/* data length = 1 byte */
-#define TX_LEN_2		0x00000002	/* data length = 2 byte */
-#define TX_LEN_3		0x00000003	/* data length = 3 byte */
-#define TX_LEN_4		0x00000004	/* data length = 4 byte */
-#define RX_LEN_1		0x00000010	/* data length = 1 byte */
-#define RX_LEN_2		0x00000020	/* data length = 2 byte */
-#define RX_LEN_3		0x00000030	/* data length = 3 byte */
-#define RX_LEN_4		0x00000040	/* data length = 4 byte */
-#define TFIE			0x00000100	/* Tx Flag Interrupt Enable */
-#define WCIE			0x00000200	/* WCF Interrupt Enable */
-
-/* STATUS_REG */
-#define INT_WCF_CLR		0xFFFFFDFF	/* clear: WCF clear */
-#define INT_TFF_CLR		0xFFFFFEFF	/* clear: TFF clear */
-#define WIP_BIT			0x00000001	/* WIP Bit of SPI SR */
-#define WEL_BIT			0x00000002	/* WEL Bit of SPI SR */
-#define RSR			0x00000005	/* Read Status regiser */
-#define TFF			0x00000100	/* Transfer Finished FLag */
-#define WCF			0x00000200	/* Transfer Finished FLag */
-#define ERF1			0x00000400	/* Error Flag 1 */
-#define ERF2			0x00000800	/* Error Flag 2 */
-#define WM0			0x00001000	/* WM Bank 0 */
-#define WM1			0x00002000	/* WM Bank 1 */
-#define WM2			0x00004000	/* WM Bank 2 */
-#define WM3			0x00008000	/* WM Bank 3 */
-#define WM_SHIFT		12
-
-/* TR REG */
-#define READ_ID			0x0000009F	/* Read Identification */
-#define BULK_ERASE		0x000000C7	/* BULK erase */
-#define SECTOR_ERASE		0x000000D8	/* SECTOR erase */
-#define WRITE_ENABLE		0x00000006	/* Wenable command to FLASH */
-
-struct flash_dev {
-	u32 density;
-	ulong size;
-	ushort sector_count;
-};
-
-#define SFLASH_PAGE_SIZE	0x100	/* flash page size */
-#define XFER_FINISH_TOUT	2	/* xfer finish timeout */
-#define WMODE_TOUT		2	/* write enable timeout */
-
-#endif
--- a/arch/arm/include/asm/arch-spear/spr_syscntl.h
+++ b/arch/arm/include/asm/arch-spear/spr_syscntl.h
@@ -1,38 +0,0 @@
-/*
- * (C) Copyright 2009
- * Ryan CHEN, ST Micoelectronics, ryan.chen@st.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-struct syscntl_regs {
-	u32 scctrl;
-	u32 scsysstat;
-	u32 scimctrl;
-	u32 scimsysstat;
-	u32 scxtalctrl;
-	u32 scpllctrl;
-	u32 scpllfctrl;
-	u32 scperctrl0;
-	u32 scperctrl1;
-	u32 scperen;
-	u32 scperdis;
-	const u32 scperclken;
-	const u32 scperstat;
-};
--- a/arch/arm/include/asm/arch-spear/spr_xloader_table.h
+++ b/arch/arm/include/asm/arch-spear/spr_xloader_table.h
@@ -1,67 +0,0 @@
-/*
- * (C) Copyright 2009
- * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _SPR_XLOADER_TABLE_H
-#define _SPR_XLOADER_TABLE_H
-
-#define XLOADER_TABLE_VERSION_1_1	2
-#define XLOADER_TABLE_VERSION_1_2	3
-
-#define XLOADER_TABLE_ADDRESS		0xD2801FF0
-
-#define DDRMOBILE	1
-#define DDR2		2
-
-#define REV_BA		1
-#define REV_AA		2
-#define REV_AB		3
-
-struct xloader_table_1_1 {
-	unsigned short ddrfreq;
-	unsigned char ddrsize;
-	unsigned char ddrtype;
-
-	unsigned char soc_rev;
-} __attribute__ ((packed));
-
-struct xloader_table_1_2 {
-	unsigned const char *version;
-
-	unsigned short ddrfreq;
-	unsigned char ddrsize;
-	unsigned char ddrtype;
-
-	unsigned char soc_rev;
-} __attribute__ ((packed));
-
-union table_contents {
-	struct xloader_table_1_1 table_1_1;
-	struct xloader_table_1_2 table_1_2;
-};
-
-struct xloader_table {
-	unsigned char table_version;
-	union table_contents table;
-} __attribute__ ((packed));
-
-#endif
--- a/arch/arm/include/asm/arch-tnetv107x/clock.h
+++ b/arch/arm/include/asm/arch-tnetv107x/clock.h
@@ -1,68 +0,0 @@
-/*
- * TNETV107X: Clock APIs
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef __ASM_ARCH_CLOCK_H
-#define __ASM_ARCH_CLOCK_H
-
-#define PSC_MDCTL_NEXT_SWRSTDISABLE	0x0
-#define PSC_MDCTL_NEXT_SYNCRST		0x1
-#define PSC_MDCTL_NEXT_DISABLE		0x2
-#define PSC_MDCTL_NEXT_ENABLE		0x3
-
-#define CONFIG_SYS_INT_OSC_FREQ		24000000
-
-#ifndef __ASSEMBLY__
-
-/* PLL identifiers */
-enum pll_type_e {
-	SYS_PLL,
-	TDM_PLL,
-	ETH_PLL
-};
-
-/* PLL configuration data */
-struct pll_init_data {
-	int pll;
-	int internal_osc;
-	unsigned long pll_freq;
-	unsigned long div_freq[10];
-};
-
-void init_plls(int num_pll, struct pll_init_data *config);
-int  lpsc_status(unsigned int mod);
-void lpsc_control(int mod, unsigned long state, int lrstz);
-unsigned long clk_get_rate(unsigned int clk);
-unsigned long clk_round_rate(unsigned int clk, unsigned long hz);
-int clk_set_rate(unsigned int clk, unsigned long hz);
-
-static inline void clk_enable(unsigned int mod)
-{
-	lpsc_control(mod, PSC_MDCTL_NEXT_ENABLE, -1);
-}
-
-static inline void clk_disable(unsigned int mod)
-{
-	lpsc_control(mod, PSC_MDCTL_NEXT_DISABLE, -1);
-}
-
-#endif
-
-#endif
--- a/arch/arm/include/asm/arch-tnetv107x/emif_defs.h
+++ b/arch/arm/include/asm/arch-tnetv107x/emif_defs.h
@@ -1 +0,0 @@
-#include <asm/arch-davinci/emif_defs.h>
--- a/Show More
+++ b/Show More
Author	SHA1	Message	Date
Wolfgang Denk	f20393c5e7	Prepare v2009.11.1 Update CHANGELOG Signed-off-by: Wolfgang Denk <wd@denx.de>	2010-01-25 09:35:12 +01:00
Stefan Roese	580ca3c2b1	ppc4xx: Kilauea: Add CPLD version detection and EBC reconfiguration A newer CPLD version on the 405EX evaluation board requires a different EBC controller setup for the CPLD register access. This patch adds a CPLD version detection for Kilauea and code to reconfigure the EBC controller (chip select 2) for the old CPLD if no new version is found. Additionally the CPLD version is printed upon bootup: Board: Kilauea - AMCC PPC405EX Evaluation Board (CPLD rev. 0) Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Wolfgang Denk <wd@denx.de> Cc: Zhang Bao Quan <bqzhang@udtech.com.cn>	2010-01-23 17:54:03 +01:00
Felix Radensky	eb20392ca9	ppc4xx: Fix sending type 1 PCI transactions The list of 4xx SoCs that should send type 1 PCI transactions is not defined correctly. As a result PCI-PCI bridges and devices behind them are not identified. The following 4xx variants should send type 1 transactions: 440GX, 440GP, 440SP, 440SPE, 460EX and 460GT. Signed-off-by: Felix Radensky <felix@embedded-sol.com> Signed-off-by: Stefan Roese <sr@denx.de>	2010-01-23 17:53:55 +01:00
Felix Radensky	57ab8a129d	ppc4xx: Allow setting a single SPD EEPROM address for DDR2 DIMMs On platforms where SPD EEPROM and another EEPROM have adjacent I2C addresses SPD_EEPROM_ADDRESS should be defined as a single element array, otherwise DDR2 setup code would fail with the following error: ERROR: Unknown DIMM detected in slot 1 However, fixing SPD_EEPROM_ADDRESS would result in another error: ERROR: DIMM's DDR1 and DDR2 type can not be mixed. This happens because initdram() routine does not explicitly initialize dimm_populated array. This patch fixes the problem. Signed-off-by: Felix Radensky <felix@embedded-sol.com> Signed-off-by: Stefan Roese <sr@denx.de>	2010-01-23 17:53:22 +01:00
Felix Radensky	17ab3057bd	ppc4xx: Fix reporting of bootstrap options G and F on 460EX/GT Bootstrap options G and F are reported incorrectly (G instead of F and vice versa). This patch fixes this. Signed-off-by: Felix Radensky <felix@embedded-sol.com> Signed-off-by: Stefan Roese <sr@denx.de>	2010-01-23 17:53:11 +01:00