Prepare v2009.11.1

Update CHANGELOG

Signed-off-by: Wolfgang Denk <wd@denx.de>

.checkpatch.conf

@@ -1,23 +0,0 @@
-# Not Linux, so don't expect a Linux tree.
---no-tree
-
-# Temporary for false positive in checkpatch
---ignore COMPLEX_MACRO
-
-# For CONFIG_SYS_I2C_NOPROBES
---ignore MULTISTATEMENT_MACRO_USE_DO_WHILE
-
-# For simple_strtoul
---ignore CONSIDER_KSTRTO
-
-# For min/max
---ignore MINMAX
-
-# enable more tests
---strict
-
-# Not Linux, so we don't recommend usleep_range() over udelay()
---ignore USLEEP_RANGE
-
-# Ignore networking block comment style
---ignore NETWORKING_BLOCK_COMMENT_STYLE

.gitignore

@@ -10,60 +10,36 @@
 *.orig
 *.a
 *.o
-*.su
 *~
 *.swp
 *.patch
-*.bin
-*.cfgtmp
-*.dts.tmp
-
-# Build tree
-/build-*
 
 #
 # Top-level generic files
 #
 
-/MLO*
-/SPL
 /System.map
 /u-boot
 /u-boot.hex
-/u-boot.imx
-/u-boot-with-spl.imx
-/u-boot-with-nand-spl.imx
 /u-boot.map
+/u-boot.bin
 /u-boot.srec
 /u-boot.ldr
 /u-boot.ldr.hex
 /u-boot.ldr.srec
-/u-boot.img
-/u-boot.kwb
-/u-boot.sha1
-/u-boot.dis
 /u-boot.lds
-/u-boot.ubl
-/u-boot.ais
-/u-boot.dtb
-/u-boot.sb
-/u-boot.bd
-/u-boot.geany
+/u-boot-onenand.bin
+/u-boot-flexonenand.bin
 
 #
 # Generated files
 #
 
-*.depend*
+*.depend
 /LOG
 /errlog
 /reloc_off
 
-/include/generated/
-/include/spl-autoconf.mk
-/include/tpl-autoconf.mk
-asm-offsets.s
-
 # stgit generated dirs
 patches-*
 .stgit-edit.txt
@@ -83,11 +59,7 @@ cscope.*
 /ctags
 /etags
 
-# gnu global files
-GPATH
-GRTAGS
-GSYMS
-GTAGS
-
-# spl ais files
-/spl/*.ais
+# OneNAND IPL files
+/onenand_ipl/onenand-ipl*
+/onenand_ipl/board/*/onenand*
+/onenand_ipl/board/*/*.S

COPYING

@@ -0,0 +1,298 @@
+  NOTE! This copyright does *not* cover the so-called "standalone"
+applications that use U-Boot services by means of the jump table
+provided by U-Boot exactly for this purpose - this is merely
+considered normal use of U-Boot, and does *not* fall under the
+heading of "derived work".
+
+  The header files "include/image.h" and "include/asm-*/u-boot.h"
+define interfaces to U-Boot. Including these (unmodified) header
+files in another file is considered normal use of U-Boot, and does
+*not* fall under the heading of "derived work".
+
+  Also note that the GPL below is copyrighted by the Free Software
+Foundation, but the instance of code that it refers to (the U-Boot
+source code) is copyrighted by me and others who actually wrote it.
+-- Wolfgang Denk
+
+=======================================================================
+
+		    GNU GENERAL PUBLIC LICENSE
+		       Version 2, June 1991
+
+ Copyright (C) 1989, 1991 Free Software Foundation, Inc.
+     59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ Everyone is permitted to copy and distribute verbatim copies
+ of this license document, but changing it is not allowed.
+
+			    Preamble
+
+  The licenses for most software are designed to take away your
+freedom to share and change it.  By contrast, the GNU General Public
+License is intended to guarantee your freedom to share and change free
+software--to make sure the software is free for all its users.  This
+General Public License applies to most of the Free Software
+Foundation's software and to any other program whose authors commit to
+using it.  (Some other Free Software Foundation software is covered by
+the GNU Library General Public License instead.)  You can apply it to
+your programs, too.
+
+  When we speak of free software, we are referring to freedom, not
+price.  Our General Public Licenses are designed to make sure that you
+have the freedom to distribute copies of free software (and charge for
+this service if you wish), that you receive source code or can get it
+if you want it, that you can change the software or use pieces of it
+in new free programs; and that you know you can do these things.
+
+  To protect your rights, we need to make restrictions that forbid
+anyone to deny you these rights or to ask you to surrender the rights.
+These restrictions translate to certain responsibilities for you if you
+distribute copies of the software, or if you modify it.
+
+  For example, if you distribute copies of such a program, whether
+gratis or for a fee, you must give the recipients all the rights that
+you have.  You must make sure that they, too, receive or can get the
+source code.  And you must show them these terms so they know their
+rights.
+
+  We protect your rights with two steps: (1) copyright the software, and
+(2) offer you this license which gives you legal permission to copy,
+distribute and/or modify the software.
+
+  Also, for each author's protection and ours, we want to make certain
+that everyone understands that there is no warranty for this free
+software.  If the software is modified by someone else and passed on, we
+want its recipients to know that what they have is not the original, so
+that any problems introduced by others will not reflect on the original
+authors' reputations.
+
+  Finally, any free program is threatened constantly by software
+patents.  We wish to avoid the danger that redistributors of a free
+program will individually obtain patent licenses, in effect making the
+program proprietary.  To prevent this, we have made it clear that any
+patent must be licensed for everyone's free use or not licensed at all.
+
+  The precise terms and conditions for copying, distribution and
+modification follow.
+
+		    GNU GENERAL PUBLIC LICENSE
+   TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
+
+  0. This License applies to any program or other work which contains
+a notice placed by the copyright holder saying it may be distributed
+under the terms of this General Public License.  The "Program", below,
+refers to any such program or work, and a "work based on the Program"
+means either the Program or any derivative work under copyright law:
+that is to say, a work containing the Program or a portion of it,
+either verbatim or with modifications and/or translated into another
+language.  (Hereinafter, translation is included without limitation in
+the term "modification".)  Each licensee is addressed as "you".
+
+Activities other than copying, distribution and modification are not
+covered by this License; they are outside its scope.  The act of
+running the Program is not restricted, and the output from the Program
+is covered only if its contents constitute a work based on the
+Program (independent of having been made by running the Program).
+Whether that is true depends on what the Program does.
+
+  1. You may copy and distribute verbatim copies of the Program's
+source code as you receive it, in any medium, provided that you
+conspicuously and appropriately publish on each copy an appropriate
+copyright notice and disclaimer of warranty; keep intact all the
+notices that refer to this License and to the absence of any warranty;
+and give any other recipients of the Program a copy of this License
+along with the Program.
+
+You may charge a fee for the physical act of transferring a copy, and
+you may at your option offer warranty protection in exchange for a fee.
+
+  2. You may modify your copy or copies of the Program or any portion
+of it, thus forming a work based on the Program, and copy and
+distribute such modifications or work under the terms of Section 1
+above, provided that you also meet all of these conditions:
+
+    a) You must cause the modified files to carry prominent notices
+    stating that you changed the files and the date of any change.
+
+    b) You must cause any work that you distribute or publish, that in
+    whole or in part contains or is derived from the Program or any
+    part thereof, to be licensed as a whole at no charge to all third
+    parties under the terms of this License.
+
+    c) If the modified program normally reads commands interactively
+    when run, you must cause it, when started running for such
+    interactive use in the most ordinary way, to print or display an
+    announcement including an appropriate copyright notice and a
+    notice that there is no warranty (or else, saying that you provide
+    a warranty) and that users may redistribute the program under
+    these conditions, and telling the user how to view a copy of this
+    License.  (Exception: if the Program itself is interactive but
+    does not normally print such an announcement, your work based on
+    the Program is not required to print an announcement.)
+
+These requirements apply to the modified work as a whole.  If
+identifiable sections of that work are not derived from the Program,
+and can be reasonably considered independent and separate works in
+themselves, then this License, and its terms, do not apply to those
+sections when you distribute them as separate works.  But when you
+distribute the same sections as part of a whole which is a work based
+on the Program, the distribution of the whole must be on the terms of
+this License, whose permissions for other licensees extend to the
+entire whole, and thus to each and every part regardless of who wrote it.
+
+Thus, it is not the intent of this section to claim rights or contest
+your rights to work written entirely by you; rather, the intent is to
+exercise the right to control the distribution of derivative or
+collective works based on the Program.
+
+In addition, mere aggregation of another work not based on the Program
+with the Program (or with a work based on the Program) on a volume of
+a storage or distribution medium does not bring the other work under
+the scope of this License.
+
+  3. You may copy and distribute the Program (or a work based on it,
+under Section 2) in object code or executable form under the terms of
+Sections 1 and 2 above provided that you also do one of the following:
+
+    a) Accompany it with the complete corresponding machine-readable
+    source code, which must be distributed under the terms of Sections
+    1 and 2 above on a medium customarily used for software interchange; or,
+
+    b) Accompany it with a written offer, valid for at least three
+    years, to give any third party, for a charge no more than your
+    cost of physically performing source distribution, a complete
+    machine-readable copy of the corresponding source code, to be
+    distributed under the terms of Sections 1 and 2 above on a medium
+    customarily used for software interchange; or,
+
+    c) Accompany it with the information you received as to the offer
+    to distribute corresponding source code.  (This alternative is
+    allowed only for noncommercial distribution and only if you
+    received the program in object code or executable form with such
+    an offer, in accord with Subsection b above.)
+
+The source code for a work means the preferred form of the work for
+making modifications to it.  For an executable work, complete source
+code means all the source code for all modules it contains, plus any
+associated interface definition files, plus the scripts used to
+control compilation and installation of the executable.  However, as a
+special exception, the source code distributed need not include
+anything that is normally distributed (in either source or binary
+form) with the major components (compiler, kernel, and so on) of the
+operating system on which the executable runs, unless that component
+itself accompanies the executable.
+
+If distribution of executable or object code is made by offering
+access to copy from a designated place, then offering equivalent
+access to copy the source code from the same place counts as
+distribution of the source code, even though third parties are not
+compelled to copy the source along with the object code.
+
+  4. You may not copy, modify, sublicense, or distribute the Program
+except as expressly provided under this License.  Any attempt
+otherwise to copy, modify, sublicense or distribute the Program is
+void, and will automatically terminate your rights under this License.
+However, parties who have received copies, or rights, from you under
+this License will not have their licenses terminated so long as such
+parties remain in full compliance.
+
+  5. You are not required to accept this License, since you have not
+signed it.  However, nothing else grants you permission to modify or
+distribute the Program or its derivative works.  These actions are
+prohibited by law if you do not accept this License.  Therefore, by
+modifying or distributing the Program (or any work based on the
+Program), you indicate your acceptance of this License to do so, and
+all its terms and conditions for copying, distributing or modifying
+the Program or works based on it.
+
+  6. Each time you redistribute the Program (or any work based on the
+Program), the recipient automatically receives a license from the
+original licensor to copy, distribute or modify the Program subject to
+these terms and conditions.  You may not impose any further
+restrictions on the recipients' exercise of the rights granted herein.
+You are not responsible for enforcing compliance by third parties to
+this License.
+
+  7. If, as a consequence of a court judgment or allegation of patent
+infringement or for any other reason (not limited to patent issues),
+conditions are imposed on you (whether by court order, agreement or
+otherwise) that contradict the conditions of this License, they do not
+excuse you from the conditions of this License.  If you cannot
+distribute so as to satisfy simultaneously your obligations under this
+License and any other pertinent obligations, then as a consequence you
+may not distribute the Program at all.  For example, if a patent
+license would not permit royalty-free redistribution of the Program by
+all those who receive copies directly or indirectly through you, then
+the only way you could satisfy both it and this License would be to
+refrain entirely from distribution of the Program.
+
+If any portion of this section is held invalid or unenforceable under
+any particular circumstance, the balance of the section is intended to
+apply and the section as a whole is intended to apply in other
+circumstances.
+
+It is not the purpose of this section to induce you to infringe any
+patents or other property right claims or to contest validity of any
+such claims; this section has the sole purpose of protecting the
+integrity of the free software distribution system, which is
+implemented by public license practices.  Many people have made
+generous contributions to the wide range of software distributed
+through that system in reliance on consistent application of that
+system; it is up to the author/donor to decide if he or she is willing
+to distribute software through any other system and a licensee cannot
+impose that choice.
+
+This section is intended to make thoroughly clear what is believed to
+be a consequence of the rest of this License.
+
+  8. If the distribution and/or use of the Program is restricted in
+certain countries either by patents or by copyrighted interfaces, the
+original copyright holder who places the Program under this License
+may add an explicit geographical distribution limitation excluding
+those countries, so that distribution is permitted only in or among
+countries not thus excluded.  In such case, this License incorporates
+the limitation as if written in the body of this License.
+
+  9. The Free Software Foundation may publish revised and/or new versions
+of the General Public License from time to time.  Such new versions will
+be similar in spirit to the present version, but may differ in detail to
+address new problems or concerns.
+
+Each version is given a distinguishing version number.  If the Program
+specifies a version number of this License which applies to it and "any
+later version", you have the option of following the terms and conditions
+either of that version or of any later version published by the Free
+Software Foundation.  If the Program does not specify a version number of
+this License, you may choose any version ever published by the Free Software
+Foundation.
+
+  10. If you wish to incorporate parts of the Program into other free
+programs whose distribution conditions are different, write to the author
+to ask for permission.  For software which is copyrighted by the Free
+Software Foundation, write to the Free Software Foundation; we sometimes
+make exceptions for this.  Our decision will be guided by the two goals
+of preserving the free status of all derivatives of our free software and
+of promoting the sharing and reuse of software generally.
+
+			    NO WARRANTY
+
+  11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY
+FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW.  EXCEPT WHEN
+OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES
+PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED
+OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.  THE ENTIRE RISK AS
+TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU.  SHOULD THE
+PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING,
+REPAIR OR CORRECTION.
+
+  12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
+WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR
+REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES,
+INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING
+OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED
+TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY
+YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER
+PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGES.
+
+		     END OF TERMS AND CONDITIONS

CREDITS

@@ -22,6 +22,10 @@ N: Guillaume Alexandre
 E: guillaume.alexandre@gespac.ch
 D: Add PCIPPC6 configuration
 
+N: Swen Anderson
+E: sand@peppercon.de
+D: ERIC Support
+
 N: Pantelis Antoniou
 E: panto@intracom.gr
 D: NETVIA & NETPHONE board support, ARTOS support.
@@ -79,6 +83,12 @@ N: Oliver Brown
 E: obrown@adventnetworks.com
 D: Port to the gw8260 board
 
+N: Curt Brune
+E: curt@cucy.com
+D: Added support for Samsung S3C4510B CPU (ARM7tdmi based SoC)
+D: Added support for ESPD-Inc. EVB4510 Board
+W: http://www.cucy.com
+
 N: Jonathan De Bruyne
 E: jonathan.debruyne@siemens.atea.be
 D: Port to Siemens IAD210 board
@@ -124,14 +134,15 @@ N: James F. Dougherty
 E: jfd@GigabitNetworks.COM
 D: Port to the MOUSSE board
 
-N: Mike Dunn
-E: mikedunn@newsguy.com
-D: Palmtreo680 board, docg4 nand flash driver
-
 N: Dave Ellis
 E: DGE@sixnetio.com
 D: EEPROM Speedup, SXNI855T port
 
+N: Thomas Elste
+E: info@elste.org
+D: Port for the ModNET50 Board, NET+50 CPU Port
+W: http://www.imms.de
+
 N: Daniel Engstr?m
 E: daniel@omicron.se
 D: x86 port, Support for sc520_cdp board
@@ -154,13 +165,18 @@ N: Thomas Frieden
 E: ThomasF@hyperion-entertainment.com
 D: Support for AmigaOne
 
+N: Niklaus Giger
+E: niklaus.giger@netstal.com
+D: Support for HCU(x) boards
+W: www.netstal.com
+
 N: Paul Gortmaker
 E: paul.gortmaker@windriver.com
 D: Support for WRS SBC8347/8349 boards
 
 N: Frank Gottschling
 E: fgottschling@eltec.de
-D: Support for ELTEC MHPC/ELPPC boards, cfb-console, i8042, SMI LynxEM
+D: Support for ELTEC MHPC/BAB7xx/ELPPC boards, cfb-console, i8042, SMI LynxEM
 W: www.eltec.de
 
 N: Marius Groeger
@@ -182,7 +198,11 @@ D: Port to Walnut405 board
 
 N: Andreas Heppel
 E: aheppel@sysgo.de
-D: CPU Support for MPC 75x
+D: CPU Support for MPC 75x; board support for Eltec BAB750 [obsolete!]
+
+N: August Hoeraendl
+E: august.hoerandl@gmx.at
+D: Support for the logodl board (PXA2xx)
 
 N: Josh Huber
 E: huber@alum.wpi.edu
@@ -266,6 +286,11 @@ N: Thomas Lange
 E: thomas@corelatus.se
 D: Support for GTH, GTH2 and dbau1x00 boards; lots of PCMCIA fixes
 
+N: Marc Leeman
+E: marc.leeman@barco.com
+D: Support for Barco Streaming Video Card (SVC) and Sample Compress Network (SCN)
+W: www.barco.com
+
 N: The LEOX team
 E: team@leox.org
 D: Support for LEOX boards, DS164x RTC
@@ -375,7 +400,7 @@ D: Support for the Wind River sbc405, sbc8240 board
 W: http://www.windriver.com
 
 N: Stelian Pop
-E: stelian@popies.net
+E: stelian.pop@leadtechdesign.com
 D: Atmel AT91CAP9ADK support
 
 N: Ricardo Ribalda Delgado
@@ -412,11 +437,11 @@ D: FADS823 configuration, MPC823 video support, I2C, wireless keyboard, lots mor
 
 N: Andre Schwarz
 E: andre.schwarz@matrix-vision.de
-D: Support for Matrix Vision boards (MVBLM7/MVBC_P/MVSMR)
+D: Support for Matrix Vision boards (MVBLM7/MVBC_P)
 
 N: Robert Schwebel
 E: r.schwebel@pengutronix.de
-D: Support for csb226 and innokom boards (PXA2xx)
+D: Support for csb226, logodl and innokom boards (PXA2xx)
 
 N: Aaron Sells
 E: sellsa@embeddedplanet.com
@@ -427,11 +452,6 @@ E: art@videon-central.com
 D: Support for NetSilicon NS7520
 D: Support for ColdFire MCF5275
 
-N: Jeremy C. Andrus
-E: jeremy@jeremya.com
-D: ColdFire MCF5249 initialization code
-W: jeremya.com
-
 N: Michal Simek
 E: monstr@monstr.eu
 D: Support for Microblaze, ML401, XUPV2P board
@@ -491,11 +511,6 @@ N: Martin Winistoerfer
 E: martinwinistoerfer@gmx.ch
 D: Port to MPC555/556 microcontrollers and support for cmi board
 
-N: David Wu
-E: support@arcturusnetworks.com
-D: Mercury Security EP2500
-W: http://www.arcturusnetworks.com
-
 N: Ming-Len Wu
 E: minglen_wu@techware.com.tw
 D: Motorola MX1ADS board support

Licenses/Exceptions

@@ -1,15 +0,0 @@
-
-GPL License Exception:
-
-Even though U-Boot in general is covered by the GPL-2.0/GPL-2.0+,
-this does *not* cover the so-called "standalone" applications that
-use U-Boot services by means of the jump table provided by U-Boot
-exactly for this purpose - this is merely considered normal use of
-U-Boot, and does *not* fall under the heading of "derived work".
-
-  The header files "include/image.h" and "arch/*/include/asm/u-boot.h"
-define interfaces to U-Boot.  Including these (unmodified) header
-files in another file is considered normal use of U-Boot, and does
-*not* fall under the heading of "derived work".
--- Wolfgang Denk
-

Licenses/README

@@ -1,68 +0,0 @@
-  U-Boot is Free Software.  It is copyrighted by Wolfgang Denk and
-many others who contributed code (see the actual source code and the
-git commit messages for details).  You can redistribute U-Boot and/or
-modify it under the terms of version 2 of the GNU General Public
-License as published by the Free Software Foundation.  Most of it can
-also be distributed, at your option, under any later version of the
-GNU General Public License -- see individual files for exceptions.
-
-  NOTE! This license does *not* cover the so-called "standalone"
-applications that use U-Boot services by means of the jump table
-provided by U-Boot exactly for this purpose - this is merely
-considered normal use of U-Boot, and does *not* fall under the
-heading of "derived work" -- see file  Licenses/Exceptions  for
-details.
-
-  Also note that the GPL and the other licenses are copyrighted by
-the Free Software Foundation and other organizations, but the
-instance of code that they refer to (the U-Boot source code) is
-copyrighted by me and others who actually wrote it.
--- Wolfgang Denk
-
-
-Like many other projects, U-Boot has a tradition of including big
-blocks of License headers in all files.  This not only blows up the
-source code with mostly redundant information, but also makes it very
-difficult to generate License Clearing Reports.  An additional problem
-is that even the same licenses are referred to by a number of
-slightly varying text blocks (full, abbreviated, different
-indentation, line wrapping and/or white space, with obsolete address
-information, ...) which makes automatic processing a nightmare.
-
-To make this easier, such license headers in the source files will be
-replaced with a single line reference to Unique License Identifiers
-as defined by the Linux Foundation's SPDX project [1].  For example,
-in a source file the full "GPL v2.0 or later" header text will be
-replaced by a single line:
-
-	SPDX-License-Identifier:	GPL-2.0+
-
-Ideally, the license terms of all files in the source tree should be
-defined by such License Identifiers; in no case a file can contain
-more than one such License Identifier list.
-
-If a "SPDX-License-Identifier:" line references more than one Unique
-License Identifier, then this means that the respective file can be
-used under the terms of either of these licenses, i. e. with
-
-	SPDX-License-Identifier:	GPL-2.0+	BSD-3-Clause
-
-you can chose between GPL-2.0+ and BSD-3-Clause licensing.
-
-We use the SPDX Unique License Identifiers here; these are available
-at [2].
-
-[1] http://spdx.org/
-[2] http://spdx.org/licenses/
-
-Full name					SPDX Identifier	OSI Approved	File name		URI
-=======================================================================================================================================
-GNU General Public License v2.0 only		GPL-2.0		Y		gpl-2.0.txt		http://www.gnu.org/licenses/gpl-2.0.txt
-GNU General Public License v2.0 or later	GPL-2.0+	Y		gpl-2.0.txt		http://www.gnu.org/licenses/gpl-2.0.txt
-GNU Library General Public License v2 or later	LGPL-2.0+	Y		lgpl-2.0.txt		http://www.gnu.org/licenses/old-licenses/lgpl-2.0.txt
-GNU Lesser General Public License v2.1 or later	LGPL-2.1+	Y		lgpl-2.1.txt		http://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt
-eCos license version 2.0			eCos-2.0			eCos-2.0.txt		http://www.gnu.org/licenses/ecos-license.html
-BSD 2-Clause License				BSD-2-Clause	Y		bsd-2-clause.txt	http://spdx.org/licenses/BSD-2-Clause
-BSD 3-clause "New" or "Revised" License		BSD-3-Clause	Y		bsd-3-clause.txt	http://spdx.org/licenses/BSD-3-Clause#licenseText
-IBM PIBS (PowerPC Initialization and		IBM-pibs			ibm-pibs.txt
-	Boot Software) license

Licenses/bsd-2-clause.txt

@@ -1,25 +0,0 @@
-Redistribution and use in source and binary forms, with or
-without modification, are permitted provided that the following
-conditions are met:
-
-1. Redistributions of source code must retain the above
-   copyright notice, this list of conditions and the following
-   disclaimer.
-2. Redistributions in binary form must reproduce the above
-   copyright notice, this list of conditions and the following
-   disclaimer in the documentation and/or other materials
-   provided with the distribution.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
-CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Licenses/bsd-3-clause.txt

@@ -1,24 +0,0 @@
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions
-are met:
-1. Redistributions of source code must retain the above copyright
-   notice, this list of conditions, and the following disclaimer,
-   without modification.
-2. Redistributions in binary form must reproduce the above copyright
-   notice, this list of conditions and the following disclaimer in the
-   documentation and/or other materials provided with the distribution.
-3. The names of the above-listed copyright holders may not be used
-   to endorse or promote products derived from this software without
-   specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Licenses/eCos-2.0.txt

@@ -1,43 +0,0 @@
-   Note that this license is not endorsed by the Free Software Foundation.
-   It is available here as a convenience to readers of [1]the license
-   list.
-
-The eCos license version 2.0
-
-   This file is part of eCos, the Embedded Configurable Operating System.
-   Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
-
-   eCos is free software; you can redistribute it and/or modify it under
-   the terms of the GNU General Public License as published by the Free
-   Software Foundation; either version 2 or (at your option) any later
-   version.
-
-   eCos is distributed in the hope that it will be useful, but WITHOUT ANY
-   WARRANTY; without even the implied warranty of MERCHANTABILITY or
-   FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-   for more details.
-
-   You should have received a copy of the GNU General Public License along
-   with eCos; if not, write to the Free Software Foundation, Inc., 51
-   Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
-
-   As a special exception, if other files instantiate templates or use
-   macros or inline functions from this file, or you compile this file and
-   link it with other works to produce a work based on this file, this
-   file does not by itself cause the resulting work to be covered by the
-   GNU General Public License. However the source code for this file must
-   still be made available in accordance with section (3) of the GNU
-   General Public License.
-
-   This exception does not invalidate any other reasons why a work based
-   on this file might be covered by the GNU General Public License.
-
-   Alternative licenses for eCos may be arranged by contacting Red Hat,
-   Inc. at http://sources.redhat.com/ecos/ecos-license/
-   -------------------------------------------
-
-   ####ECOSGPLCOPYRIGHTEND####
-
-References
-
-   1. http://www.gnu.org/licenses/license-list.html

Licenses/gpl-2.0.txt

@@ -1,339 +0,0 @@
-                    GNU GENERAL PUBLIC LICENSE
-                       Version 2, June 1991
-
- Copyright (C) 1989, 1991 Free Software Foundation, Inc.,
- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
- Everyone is permitted to copy and distribute verbatim copies
- of this license document, but changing it is not allowed.
-
-                            Preamble
-
-  The licenses for most software are designed to take away your
-freedom to share and change it.  By contrast, the GNU General Public
-License is intended to guarantee your freedom to share and change free
-software--to make sure the software is free for all its users.  This
-General Public License applies to most of the Free Software
-Foundation's software and to any other program whose authors commit to
-using it.  (Some other Free Software Foundation software is covered by
-the GNU Lesser General Public License instead.)  You can apply it to
-your programs, too.
-
-  When we speak of free software, we are referring to freedom, not
-price.  Our General Public Licenses are designed to make sure that you
-have the freedom to distribute copies of free software (and charge for
-this service if you wish), that you receive source code or can get it
-if you want it, that you can change the software or use pieces of it
-in new free programs; and that you know you can do these things.
-
-  To protect your rights, we need to make restrictions that forbid
-anyone to deny you these rights or to ask you to surrender the rights.
-These restrictions translate to certain responsibilities for you if you
-distribute copies of the software, or if you modify it.
-
-  For example, if you distribute copies of such a program, whether
-gratis or for a fee, you must give the recipients all the rights that
-you have.  You must make sure that they, too, receive or can get the
-source code.  And you must show them these terms so they know their
-rights.
-
-  We protect your rights with two steps: (1) copyright the software, and
-(2) offer you this license which gives you legal permission to copy,
-distribute and/or modify the software.
-
-  Also, for each author's protection and ours, we want to make certain
-that everyone understands that there is no warranty for this free
-software.  If the software is modified by someone else and passed on, we
-want its recipients to know that what they have is not the original, so
-that any problems introduced by others will not reflect on the original
-authors' reputations.
-
-  Finally, any free program is threatened constantly by software
-patents.  We wish to avoid the danger that redistributors of a free
-program will individually obtain patent licenses, in effect making the
-program proprietary.  To prevent this, we have made it clear that any
-patent must be licensed for everyone's free use or not licensed at all.
-
-  The precise terms and conditions for copying, distribution and
-modification follow.
-
-                    GNU GENERAL PUBLIC LICENSE
-   TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
-
-  0. This License applies to any program or other work which contains
-a notice placed by the copyright holder saying it may be distributed
-under the terms of this General Public License.  The "Program", below,
-refers to any such program or work, and a "work based on the Program"
-means either the Program or any derivative work under copyright law:
-that is to say, a work containing the Program or a portion of it,
-either verbatim or with modifications and/or translated into another
-language.  (Hereinafter, translation is included without limitation in
-the term "modification".)  Each licensee is addressed as "you".
-
-Activities other than copying, distribution and modification are not
-covered by this License; they are outside its scope.  The act of
-running the Program is not restricted, and the output from the Program
-is covered only if its contents constitute a work based on the
-Program (independent of having been made by running the Program).
-Whether that is true depends on what the Program does.
-
-  1. You may copy and distribute verbatim copies of the Program's
-source code as you receive it, in any medium, provided that you
-conspicuously and appropriately publish on each copy an appropriate
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-notices that refer to this License and to the absence of any warranty;
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-along with the Program.
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-You may charge a fee for the physical act of transferring a copy, and
-you may at your option offer warranty protection in exchange for a fee.
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-this License, whose permissions for other licensees extend to the
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-with the Program (or with a work based on the Program) on a volume of
-a storage or distribution medium does not bring the other work under
-the scope of this License.
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-under Section 2) in object code or executable form under the terms of
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-    an offer, in accord with Subsection b above.)
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-  4. You may not copy, modify, sublicense, or distribute the Program
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-  5. You are not required to accept this License, since you have not
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-modifying or distributing the Program (or any work based on the
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-  6. Each time you redistribute the Program (or any work based on the
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-You are not responsible for enforcing compliance by third parties to
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-  7. If, as a consequence of a court judgment or allegation of patent
-infringement or for any other reason (not limited to patent issues),
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-the only way you could satisfy both it and this License would be to
-refrain entirely from distribution of the Program.
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-This section is intended to make thoroughly clear what is believed to
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-  8. If the distribution and/or use of the Program is restricted in
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-original copyright holder who places the Program under this License
-may add an explicit geographical distribution limitation excluding
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-the limitation as if written in the body of this License.
-
-  9. The Free Software Foundation may publish revised and/or new versions
-of the General Public License from time to time.  Such new versions will
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-Each version is given a distinguishing version number.  If the Program
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-
-  10. If you wish to incorporate parts of the Program into other free
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-
-                            NO WARRANTY
-
-  11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY
-FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW.  EXCEPT WHEN
-OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES
-PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED
-OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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-TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU.  SHOULD THE
-PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING,
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-  12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
-WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR
-REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES,
-INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING
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-PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE
-POSSIBILITY OF SUCH DAMAGES.
-
-                     END OF TERMS AND CONDITIONS
-
-            How to Apply These Terms to Your New Programs
-
-  If you develop a new program, and you want it to be of the greatest
-possible use to the public, the best way to achieve this is to make it
-free software which everyone can redistribute and change under these terms.
-
-  To do so, attach the following notices to the program.  It is safest
-to attach them to the start of each source file to most effectively
-convey the exclusion of warranty; and each file should have at least
-the "copyright" line and a pointer to where the full notice is found.
-
-    <one line to give the program's name and a brief idea of what it does.>
-    Copyright (C) <year>  <name of author>
-
-    This program is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 2 of the License, or
-    (at your option) any later version.
-
-    This program is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License along
-    with this program; if not, write to the Free Software Foundation, Inc.,
-    51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
-
-Also add information on how to contact you by electronic and paper mail.
-
-If the program is interactive, make it output a short notice like this
-when it starts in an interactive mode:
-
-    Gnomovision version 69, Copyright (C) year name of author
-    Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
-    This is free software, and you are welcome to redistribute it
-    under certain conditions; type `show c' for details.
-
-The hypothetical commands `show w' and `show c' should show the appropriate
-parts of the General Public License.  Of course, the commands you use may
-be called something other than `show w' and `show c'; they could even be
-mouse-clicks or menu items--whatever suits your program.
-
-You should also get your employer (if you work as a programmer) or your
-school, if any, to sign a "copyright disclaimer" for the program, if
-necessary.  Here is a sample; alter the names:
-
-  Yoyodyne, Inc., hereby disclaims all copyright interest in the program
-  `Gnomovision' (which makes passes at compilers) written by James Hacker.
-
-  <signature of Ty Coon>, 1 April 1989
-  Ty Coon, President of Vice
-
-This General Public License does not permit incorporating your program into
-proprietary programs.  If your program is a subroutine library, you may
-consider it more useful to permit linking proprietary applications with the
-library.  If this is what you want to do, use the GNU Lesser General
-Public License instead of this License.

Licenses/ibm-pibs.txt

@@ -1,17 +0,0 @@
-This source code has been made available to you by IBM on an AS-IS
-basis.	 Anyone receiving this source is licensed under IBM
-copyrights to use it in any way he or she deems fit, including
-copying it, modifying it, compiling it, and redistributing it either
-with or without modifications.	 No license under IBM patents or
-patent applications is to be implied by the copyright license.
-
-Any user of this software should understand that IBM cannot provide
-technical support for this software and will not be responsible for
-any consequences resulting from the use of this software.
-
-Any person who transfers this source code or any derivative work
-must include the IBM copyright notice, this paragraph, and the
-preceding two paragraphs in the transferred software.
-
-COPYRIGHT   I B M   CORPORATION 1995
-LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M

Licenses/lgpl-2.0.txt

@@ -1,481 +0,0 @@
-                  GNU LIBRARY GENERAL PUBLIC LICENSE
-                       Version 2, June 1991
-
- Copyright (C) 1991 Free Software Foundation, Inc.
- 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
- Everyone is permitted to copy and distribute verbatim copies
- of this license document, but changing it is not allowed.
-
-[This is the first released version of the library GPL.  It is
- numbered 2 because it goes with version 2 of the ordinary GPL.]
-
-                            Preamble
-
-  The licenses for most software are designed to take away your
-freedom to share and change it.  By contrast, the GNU General Public
-Licenses are intended to guarantee your freedom to share and change
-free software--to make sure the software is free for all its users.
-
-  This license, the Library General Public License, applies to some
-specially designated Free Software Foundation software, and to any
-other libraries whose authors decide to use it.  You can use it for
-your libraries, too.
-
-  When we speak of free software, we are referring to freedom, not
-price.  Our General Public Licenses are designed to make sure that you
-have the freedom to distribute copies of free software (and charge for
-this service if you wish), that you receive source code or can get it
-if you want it, that you can change the software or use pieces of it
-in new free programs; and that you know you can do these things.
-
-  To protect your rights, we need to make restrictions that forbid
-anyone to deny you these rights or to ask you to surrender the rights.
-These restrictions translate to certain responsibilities for you if
-you distribute copies of the library, or if you modify it.
-
-  For example, if you distribute copies of the library, whether gratis
-or for a fee, you must give the recipients all the rights that we gave
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-it.  And you must show them these terms so they know their rights.
-
-  Our method of protecting your rights has two steps: (1) copyright
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-
-  Finally, any free program is threatened constantly by software
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-
-                  GNU LIBRARY GENERAL PUBLIC LICENSE
-   TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
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-  0. This License Agreement applies to any software library which
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-
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-
-  <signature of Ty Coon>, 1 April 1990
-  Ty Coon, President of Vice
-
-That's all there is to it!

MAINTAINERS

@@ -0,0 +1,972 @@
+#########################################################################
+#									#
+# Regular Maintainers for U-Boot board support:				#
+#									#
+# For any board without permanent maintainer, please contact		#
+#	Wolfgang Denk <wd@denx.de>					#
+# and Cc: the <u-boot@lists.denx.de> mailing list.			#
+#									#
+# Note: lists sorted by Maintainer Name					#
+#########################################################################
+
+
+#########################################################################
+# PowerPC Systems:							#
+#									#
+# Maintainer Name, Email Address					#
+#	Board		CPU						#
+#########################################################################
+
+Poonam Aggrwal <poonam.aggrwal@freescale.com>
+
+	P2020RDB	P2020
+
+Greg Allen <gallen@arlut.utexas.edu>
+
+	UTX8245		MPC8245
+
+Pantelis Antoniou <panto@intracom.gr>
+
+	NETVIA		MPC8xx
+
+Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+
+	cpci5200	MPC5200
+	mecp5123	MPC5121
+	mecp5200	MPC5200
+	pf5200		MPC5200
+
+	vme8349		MPC8349
+
+	CPCI750		PPC750FX/GX
+
+Yuli Barcohen <yuli@arabellasw.com>
+
+	Adder		MPC87x/MPC852T
+	ep8248		MPC8248
+	ISPAN		MPC8260
+	MPC8260ADS	MPC826x/MPC827x/MPC8280
+	Rattler		MPC8248
+	ZPC1900		MPC8265
+
+Michael Barkowski <michael.barkowski@freescale.com>
+
+	MPC8323ERDB	MPC8323
+
+Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com>
+
+	sacsng		MPC8260
+
+Oliver Brown <obrown@adventnetworks.com>
+
+	gw8260		MPC8260
+
+Conn Clark <clark@esteem.com>
+
+	ESTEEM192E	MPC8xx
+
+Joe D'Abbraccio <ljd015@freescale.com>
+
+	MPC837xERDB	MPC837x
+
+Kári Davíðsson <kd@flaga.is>
+
+	FLAGADM		MPC823
+
+Torsten Demke <torsten.demke@fci.com>
+
+	eXalion		MPC824x
+
+Wolfgang Denk <wd@denx.de>
+
+	IceCube_5100	MGT5100
+	IceCube_5200	MPC5200
+
+	ARIA		MPC5121e
+
+	AMX860		MPC860
+	ETX094		MPC850
+	FPS850L		MPC850
+	FPS860L		MPC860
+	ICU862		MPC862
+	IP860		MPC860
+	IVML24		MPC860
+	IVML24_128	MPC860
+	IVML24_256	MPC860
+	IVMS8		MPC860
+	IVMS8_128	MPC860
+	IVMS8_256	MPC860
+	LANTEC		MPC850
+	LWMON		MPC823
+	NC650		MPC852
+	R360MPI		MPC823
+	RMU		MPC850
+	RRvision	MPC823
+	SM850		MPC850
+	SPD823TS	MPC823
+	TQM823L		MPC823
+	TQM823L_LCD	MPC823
+	TQM850L		MPC850
+	TQM855L		MPC855
+	TQM860L		MPC860
+	TQM860L_FEC	MPC860
+	c2mon		MPC855
+	hermes		MPC860
+	lwmon		MPC823
+	pcu_e		MPC855
+
+	CU824		MPC8240
+	Sandpoint8240	MPC8240
+	SL8245		MPC8245
+
+	ATC		MPC8250
+	PM825		MPC8250
+
+	TQM8255		MPC8255
+
+	CPU86		MPC8260
+	PM826		MPC8260
+	TQM8260		MPC8260
+
+	P3G4		MPC7410
+
+	PCIPPC2		MPC750
+	PCIPPC6		MPC750
+
+	EXBITGEN	PPC405GP
+
+Jon Diekema <jon.diekema@smiths-aerospace.com>
+
+	sbc8260		MPC8260
+
+Dirk Eibach <eibach@gdsys.de>
+
+	devconcenter	PPC460EX
+	dlvision        PPC405EP
+	gdppc440etx	PPC440EP/GR
+	intip		PPC460EX
+	neo		PPC405EP
+
+Dave Ellis <DGE@sixnetio.com>
+
+	SXNI855T	MPC8xx
+
+Thomas Frieden <ThomasF@hyperion-entertainment.com>
+
+	AmigaOneG3SE	MPC7xx
+
+Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+
+	ADCIOP		IOP480 (PPC401)
+	APC405		PPC405GP
+	AR405		PPC405GP
+	ASH405		PPC405EP
+	CANBT		PPC405CR
+	CPCI2DP		PPC405GP
+	CPCI405		PPC405GP
+	CPCI4052	PPC405GP
+	CPCI405AB	PPC405GP
+	CPCI405DT	PPC405GP
+	CPCIISER4	PPC405GP
+	DASA_SIM	IOP480 (PPC401)
+	DP405		PPC405EP
+	DU405		PPC405GP
+	DU440		PPC440EPx
+	G2000		PPC405EP
+	HH405		PPC405EP
+	HUB405		PPC405EP
+	OCRTC		PPC405GP
+	ORSG		PPC405GP
+	PCI405		PPC405GP
+	PLU405		PPC405EP
+	PMC405		PPC405GP
+	PMC405DE	PPC405EP
+	PMC440		PPC440EPx
+	VOH405		PPC405EP
+	VOM405		PPC405EP
+	WUH405		PPC405EP
+	CMS700		PPC405EP
+
+Niklaus Giger <niklaus.giger@netstal.com>
+
+	HCU4		PPC405GPr
+	MCU25		PPC405GPr
+	HCU5		PPC440EPx
+
+Frank Gottschling <fgottschling@eltec.de>
+
+	MHPC		MPC8xx
+
+	BAB7xx		MPC740/MPC750
+
+Wolfgang Grandegger <wg@denx.de>
+
+	CCM		MPC855
+
+	PN62		MPC8240
+	IPHASE4539	MPC8260
+	SCM		MPC8260
+
+Joe Hamman <joe.hamman@embeddedspecialties.com>
+
+	sbc8548		MPC8548
+	sbc8641d	MPC8641D
+
+Klaus Heydeck <heydeck@kieback-peter.de>
+
+	KUP4K		MPC855
+	KUP4X		MPC859
+
+Ilko Iliev <iliev@ronetix.at>
+
+	PM9261		AT91SAM9261
+	PM9263		AT91SAM9263
+
+Gary Jennejohn <garyj@denx.de>
+
+	quad100hd	PPC405EP
+
+Murray Jensen <Murray.Jensen@csiro.au>
+
+	cogent_mpc8xx	MPC8xx
+
+	cogent_mpc8260	MPC8260
+	hymod		MPC8260
+
+Larry Johnson <lrj@acm.org>
+
+	korat		PPC440EPx
+
+Feng Kan <fkan@amcc.com>
+
+	redwood			PPC4xx
+
+Brad Kemp <Brad.Kemp@seranoa.com>
+
+	ppmc8260	MPC8260
+
+Sangmoon Kim <dogoil@etinsys.com>
+
+	debris		MPC8245
+	KVME080		MPC8245
+
+Thomas Lange <thomas@corelatus.se>
+
+	GTH		MPC860
+
+Robert Lazarski <robertlazarski@gmail.com>
+
+	ATUM8548	MPC8548
+
+The LEOX team <team@leox.org>
+
+	ELPT860		MPC860T
+
+Guennadi Liakhovetski <g.liakhovetski@gmx.de>
+
+	linkstation	MPC8241
+
+Dave Liu <daveliu@freescale.com>
+
+	MPC8315ERDB	MPC8315
+	MPC832XEMDS	MPC832x
+	MPC8360EMDS	MPC8360
+	MPC837XEMDS	MPC837x
+
+Nye Liu <nyet@zumanetworks.com>
+
+	ZUMA		MPC7xx_74xx
+
+Kumar Gala <kumar.gala@freescale.com>
+
+	MPC8540ADS	MPC8540
+	MPC8560ADS	MPC8560
+	MPC8541CDS	MPC8541
+	MPC8555CDS	MPC8555
+
+	MPC8641HPCN	MPC8641D
+
+Ron Madrid <info@sheldoninst.com>
+
+	SIMPC8313	MPC8313
+
+Dan Malek <dan@embeddedalley.com>
+
+	stxgp3		MPC85xx
+	stxssa		MPC85xx
+	stxxtc		MPC8xx
+
+Eran Man <eran@nbase.co.il>
+
+	EVB64260_750CX	MPC750CX
+
+Andrea "llandre" Marson <andrea.marson@dave-tech.it>
+
+	PPChameleonEVB	PPC405EP
+
+Reinhard Meyer <r.meyer@emk-elektronik.de>
+
+	TOP860		MPC860T
+	TOP5200		MPC5200
+
+Tolunay Orkun <torkun@nextio.com>
+
+	csb272		PPC405GP
+	csb472		PPC405GP
+
+John Otken <jotken@softadvances.com>
+
+	luan		PPC440SP
+	taihu		PPC405EP
+
+Keith Outwater <Keith_Outwater@mvis.com>
+
+	GEN860T		MPC860T
+	GEN860T_SC	MPC860T
+
+Frank Panno <fpanno@delphintech.com>
+
+	ep8260		MPC8260
+
+Denis Peter <d.peter@mpl.ch>
+
+	MIP405		PPC4xx
+	PIP405		PPC4xx
+
+Kim Phillips <kim.phillips@freescale.com>
+
+	MPC8349EMDS	MPC8349
+
+Daniel Poirot <dan.poirot@windriver.com>
+
+	sbc8240		MPC8240
+	sbc405		PPC405GP
+
+Ricardo Ribalda <ricardo.ribalda@uam.es>
+
+	ml507 		PPC440x5
+	v5fx30teval	PPC440x5
+	xilinx-ppc405-generic	PPC405
+	xilinx-ppc440-generic	PPC440x5
+
+Stefan Roese <sr@denx.de>
+
+	P3M7448		MPC7448
+
+	uc100		MPC857
+
+	TQM85xx		MPC8540/8541/8555/8560
+
+	acadia		PPC405EZ
+	alpr		PPC440GX
+	bamboo		PPC440EP
+	bunbinga	PPC405EP
+	canyonlands	PPC460EX
+	ebony		PPC440GP
+	glacier		PPC460GT
+	haleakala	PPC405EXr
+	katmai		PPC440SPe
+	kilauea		PPC405EX
+	lwmon5		PPC440EPx
+	makalu		PPC405EX
+	ocotea		PPC440GX
+	p3p440		PPC440GP
+	pcs440ep	PPC440EP
+	rainier		PPC440GRx
+	sequoia		PPC440EPx
+	sycamore	PPC405GPr
+	taishan		PPC440GX
+	walnut		PPC405GP
+	yellowstone	PPC440GR
+	yosemite	PPC440EP
+	zeus		PPC405EP
+
+	P3M750		PPC750FX/GX/GL
+
+Yusdi Santoso <yusdi_santoso@adaptec.com>
+
+	HIDDEN_DRAGON	MPC8241/MPC8245
+
+Travis Sawyer (travis.sawyer@sandburst.com>
+
+	KAREF		PPC440GX
+	METROBOX	PPC440GX
+
+Georg Schardt <schardt@team-ctech.de>
+
+	fx12mm		PPC405
+
+Heiko Schocher <hs@denx.de>
+
+	ids8247		MPC8247
+	jupiter		MPC5200
+	kmeter1		MPC8360
+	kmsupx4		MPC852T
+	mgcoge		MPC8247
+	mgsuvd		MPC852
+	mucmc52		MPC5200
+	muas3001	MPC8270
+	municse		MPC5200
+	sc3		PPC405GP
+	uc101		MPC5200
+
+
+Peter De Schrijver <p2@mind.be>
+
+	ML2		PPC4xx
+
+Andre Schwarz <andre.schwarz@matrix-vision.de>
+
+	mvbc_p		MPC5200
+	mvblm7		MPC8343
+
+Jon Smirl <jonsmirl@gmail.com>
+
+	pcm030		MPC5200
+
+Timur Tabi <timur@freescale.com>
+
+	MPC8349E-mITX	MPC8349
+	MPC8349E-mITX-GP MPC8349
+
+Erik Theisen <etheisen@mindspring.com>
+
+	W7OLMC		PPC4xx
+	W7OLMG		PPC4xx
+
+Jim Thompson <jim@musenki.com>
+
+	MUSENKI		MPC8245/8241
+	Sandpoint8245	MPC8245
+
+Rune Torgersen <runet@innovsys.com>
+
+	MPC8266ADS	MPC8266
+
+Peter Tyser <ptyser@xes-inc.com>
+
+	XPEDITE1000	PPC440GX
+	XPEDITE5170	MPC8640
+	XPEDITE5200	MPC8548
+	XPEDITE5370	MPC8572
+
+David Updegraff <dave@cray.com>
+
+	CRAYL1		PPC4xx
+
+Anton Vorontsov <avorontsov@ru.mvista.com>
+
+	MPC8360ERDK	MPC8360
+
+Josef Wagner <Wagner@Microsys.de>
+
+	CPC45		MPC8245
+	PM520		MPC5200
+
+Stephen Williams <steve@icarus.com>
+
+	JSE		PPC405GPr
+
+Roy Zang <tie-fei.zang@freescale.com>
+
+	mpc7448hpc2	MPC7448
+
+John Zhan <zhanz@sinovee.com>
+
+	svm_sc8xx	MPC8xx
+
+Detlev Zundel <dzu@denx.de>
+
+	inka4x0		MPC5200
+
+-------------------------------------------------------------------------
+
+Unknown / orphaned boards:
+
+	ADS860		MPC8xx
+	FADS823		MPC8xx
+	FADS850SAR	MPC8xx
+	FADS860T	MPC8xx
+	GENIETV		MPC8xx
+	IAD210		MPC8xx
+	MBX		MPC8xx
+	MBX860T		MPC8xx
+	NX823		MPC8xx
+	RPXClassic	MPC8xx
+	RPXlite		MPC8xx
+
+	ERIC		PPC4xx
+
+	MOUSSE		MPC824x
+
+	RPXsuper	MPC8260
+	rsdproto	MPC8260
+
+	EVB64260	MPC7xx_74xx
+
+
+#########################################################################
+# ARM Systems:								#
+#									#
+# Maintainer Name, Email Address					#
+#	Board		CPU						#
+#########################################################################
+
+Rowel Atienza <rowel@diwalabs.com>
+
+	armadillo	ARM720T
+
+Stefano Babic <sbabic@denx.de>
+
+	polaris		xscale
+	trizepsiv	xscale
+
+Dirk Behme <dirk.behme@gmail.com>
+
+	omap3_beagle	ARM CORTEX-A8 (OMAP3530 SoC)
+
+Eric Benard <eric@eukrea.com>
+
+	cpuat91		ARM920T
+	cpu9260		ARM926EJS (AT91SAM9260 SoC)
+	cpu9G20		ARM926EJS (AT91SAM9G20 SoC)
+
+Rishi Bhattacharya <rishi@ti.com>
+
+	omap5912osk	ARM926EJS
+
+Cliff Brake <cliff.brake@gmail.com>
+
+	pxa255_idp	xscale
+
+Rick Bronson <rick@efn.org>
+
+	AT91RM9200DK	at91rm9200
+
+George G. Davis <gdavis@mvista.com>
+
+	assabet		SA1100
+	gcplus		SA1100
+
+Wolfgang Denk <wd@denx.de>
+	imx27lite	i.MX27
+	qong		i.MX31
+
+Thomas Elste <info@elste.org>
+
+	modnet50	ARM720T (NET+50)
+
+Fabio Estevam <Fabio.Estevam@freescale.com>
+
+	mx31pdk		i.MX31
+
+Peter Figuli <peposh@etc.sk>
+
+	wepep250	xscale
+
+Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
+
+	meesc		ARM926EJS (AT91SAM9263 SoC)
+
+Sedji Gaouaou<sedji.gaouaou@atmel.com>
+	at91sam9g10ek		ARM926EJS (AT91SAM9G10 SoC)
+	at91sam9m10g45ek	ARM926EJS (AT91SAM9G45 SoC)
+
+Marius Gröger <mag@sysgo.de>
+
+	impa7		ARM720T (EP7211)
+	ep7312		ARM720T (EP7312)
+
+Kshitij Gupta <kshitij@ti.com>
+
+	omap1510inn	ARM925T
+	omap1610inn	ARM926EJS
+
+Grazvydas Ignotas <notasas@gmail.com>
+
+	omap3_pandora	ARM CORTEX-A8 (OMAP3xx SoC)
+
+Gary Jennejohn <garyj@denx.de>
+
+	smdk2400	ARM920T
+	trab		ARM920T
+
+Konstantin Kletschke <kletschke@synertronixx.de>
+	scb9328		ARM920T
+
+Simon Kagstrom <simon.kagstrom@netinsight.net>
+
+       openrd_base     ARM926EJS (Kirkwood SoC)
+
+Nishant Kamat <nskamat@ti.com>
+
+	omap1610h2	ARM926EJS
+
+Frederik Kriewitz <frederik@kriewitz.eu>
+
+	devkit8000	ARM CORTEX-A8 (OMAP3530 SoC)
+
+Sergey Kubushyn <ksi@koi8.net>
+
+	DV-EVM		ARM926EJS
+	SONATA		ARM926EJS
+	SCHMOOGIE	ARM926EJS
+
+Sandeep Paulraj <s-paulraj@ti.com>
+
+	davinci_dm355evm	ARM926EJS
+	davinci_dm355leopard	ARM926EJS
+	davinci_dm365evm	ARM926EJS
+	davinci_dm6467evm	ARM926EJS
+
+Prakash Kumar <prakash@embedx.com>
+
+	cerf250		xscale
+
+Sergey Lapin <slapin@ossfans.org>
+
+	afeb9260	ARM926EJS (AT91SAM9260 SoC)
+
+Guennadi Liakhovetski <g.liakhovetski@gmx.de>
+
+	imx31_phycore_eet	i.MX31
+	mx31ads			i.MX31
+	SMDK6400		S3C6400
+
+Nishanth Menon <nm@ti.com>
+
+	omap3_sdp3430	ARM CORTEX-A8 (OMAP3xx SoC)
+	omap3_zoom1	ARM CORTEX-A8 (OMAP3xx SoC)
+
+David Müller <d.mueller@elsoft.ch>
+
+	smdk2410	ARM920T
+	VCMA9		ARM920T
+
+Eric Millbrandt <emillbrandt@dekaresearch.com>
+
+	galaxy5200	mpc5200
+
+Rolf Offermanns <rof@sysgo.de>
+
+	shannon		SA1100
+
+Kyungmin Park <kyungmin.park@samsung.com>
+
+	apollon		ARM1136EJS
+
+Peter Pearse <peter.pearse@arm.com>
+	integratorcp	All current ARM supplied & supported core modules
+			-see http://www.arm.com/products/DevTools/Hardware_Platforms.html
+	versatile	ARM926EJ-S
+	versatile	ARM926EJ-S
+
+Dave Peverley <dpeverley@mpc-data.co.uk>
+
+	omap730p2	ARM926EJS
+
+Manikandan Pillai <mani.pillai@ti.com>
+
+	omap3_evm	ARM CORTEX-A8 (OMAP3xx SoC)
+
+Stelian Pop <stelian.pop@leadtechdesign.com>
+
+	at91cap9adk	ARM926EJS (AT91CAP9 SoC)
+	at91sam9260ek	ARM926EJS (AT91SAM9260 SoC)
+	at91sam9261ek	ARM926EJS (AT91SAM9261 SoC)
+	at91sam9263ek	ARM926EJS (AT91SAM9263 SoC)
+	at91sam9rlek	ARM926EJS (AT91SAM9RL SoC)
+
+Tom Rix <Tom.Rix@windriver.com>
+
+	omap3_zoom2	ARM CORTEX-A8 (OMAP3xx SoC)
+
+Stefan Roese <sr@denx.de>
+
+	ixdpg425	xscale
+	pdnb3		xscale
+	scpu		xscale
+
+Alessandro Rubini <rubini@unipv.it>
+Nomadik Linux Team <STN_WMM_nomadik_linux@list.st.com>
+
+	nmdk8815	ARM926EJS (Nomadik 8815 Soc)
+
+Steve Sakoman <sakoman@gmail.com>
+
+	omap3_overo	ARM CORTEX-A8 (OMAP3xx SoC)
+
+Robert Schwebel <r.schwebel@pengutronix.de>
+
+	csb226		xscale
+	innokom		xscale
+
+Michael Schwingen <michael@schwingen.org>
+
+	actux1		xscale
+	actux2		xscale
+	actux3		xscale
+	actux4		xscale
+
+Andrea Scian <andrea.scian@dave-tech.it>
+
+	B2		ARM7TDMI (S3C44B0X)
+
+Albin Tonnerre <albin.tonnerre@free-electrons.com>
+
+	sbc35_a9g20	ARM926EJS (AT91SAM9G20 SoC)
+	tny_a9260	ARM926EJS (AT91SAM9260 SoC)
+	tny_a9g20	ARM926EJS (AT91SAM9G20 SoC)
+
+Greg Ungerer <greg.ungerer@opengear.com>
+
+	cm4008		ks8695p
+	cm4116		ks8695p
+	cm4148		ks8695p
+
+Hugo Villeneuve <hugo.villeneuve@lyrtech.com>
+
+	SFFSDR		ARM926EJS
+
+Prafulla Wadaskar <prafulla@marvell.com>
+
+	mv88f6281gtw_ge	ARM926EJS (Kirkwood SoC)
+	rd6281a		ARM926EJS (Kirkwood SoC)
+	sheevaplug	ARM926EJS (Kirkwood SoC)
+
+Richard Woodruff <r-woodruff2@ti.com>
+
+	omap2420h4	ARM1136EJS
+
+Alex Züpke <azu@sysgo.de>
+
+	lart		SA1100
+	dnp1110		SA1110
+
+Minkyu Kang <mk7.kang@samsung.com>
+
+	SMDKC100	ARM CORTEX-A8 (S5PC100 SoC)
+
+-------------------------------------------------------------------------
+
+Unknown / orphaned boards:
+ 	Board		CPU	Last known maintainer / Comment
+.........................................................................
+	cradle		xscale	Kyle Harris <kharris@nexus-tech.net> / dead address
+	ixdp425		xscale	Kyle Harris <kharris@nexus-tech.net> / dead address
+	lubbock		xscale	Kyle Harris <kharris@nexus-tech.net> / dead address
+
+#########################################################################
+# x86 Systems:								#
+#									#
+# Maintainer Name, Email Address					#
+#	Board		CPU						#
+#########################################################################
+
+Daniel Engström <daniel@omicron.se>
+
+	sc520_cdp	x86
+
+#########################################################################
+# MIPS Systems:								#
+#									#
+# Maintainer Name, Email Address					#
+#	Board		CPU						#
+#########################################################################
+
+Wolfgang Denk <wd@denx.de>
+
+	incaip		MIPS32 4Kc
+	purple		MIPS64 5Kc
+
+Thomas Lange <thomas@corelatus.se>
+	dbau1x00	MIPS32 Au1000
+	gth2		MIPS32 Au1000
+
+Vlad Lungu <vlad.lungu@windriver.com>
+	qemu_mips	MIPS32
+
+Stefan Roese <sr@denx.de>
+
+	vct_xxx		MIPS32 4Kc
+
+#########################################################################
+# Nios-32 Systems:							#
+#									#
+# Maintainer Name, Email Address					#
+#	Board		CPU						#
+#########################################################################
+
+Stephan Linz <linz@li-pro.net>
+
+	DK1S10		Nios-32
+	ADNPESC1	Nios-32
+
+Scott McNutt <smcnutt@psyent.com>
+
+	DK1C20		Nios-32
+
+#########################################################################
+# Nios-II Systems:							#
+#									#
+# Maintainer Name, Email Address					#
+#	Board		CPU						#
+#########################################################################
+
+Scott McNutt <smcnutt@psyent.com>
+
+	PCI5441		Nios-II
+	PK1C20		Nios-II
+	EP1C20		Nios-II
+	EP1S10		Nios-II
+	EP1S40		Nios-II
+
+#########################################################################
+# MicroBlaze Systems:							#
+#									#
+# Maintainer Name, Email Address					#
+#	Board		CPU						#
+#########################################################################
+
+Michal Simek <monstr@monstr.eu>
+
+	microblaze-generic	MicroBlaze
+
+#########################################################################
+# Coldfire Systems:							#
+#									#
+# Maintainer Name, Email Address					#
+#	Board		CPU						#
+#########################################################################
+
+Hayden Fraser <Hayden.Fraser@freescale.com>
+
+	M5253EVBE	mcf52x2
+
+Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+
+	TASREG		MCF5249
+
+TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+
+	M52277EVB	mcf5227x
+	M5235EVB	mcf52x2
+	M5253DEMO	mcf52x2
+	M53017EVB	mcf532x
+	M5329EVB	mcf532x
+	M5373EVB	mcf532x
+	M54455EVB	mcf5445x
+	M5475EVB	mcf547x_8x
+	M5485EVB	mcf547x_8x
+
+#########################################################################
+# AVR32 Systems:							#
+#									#
+# Maintainer Name, Email Address					#
+#	Board		CPU						#
+#########################################################################
+
+Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com>
+
+	FAVR-32-EZKIT		AT32AP7000
+
+Mark Jackson <mpfj@mimc.co.uk>
+
+	MIMC200			AT32AP7000
+
+Alex Raimondi <alex.raimondi@miromico.ch>
+Julien May <julien.may@miromico.ch>
+
+	HAMMERHEAD		AT32AP7000
+
+Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
+
+	ATSTK1000	AT32AP7xxx
+	ATSTK1002	AT32AP7000
+	ATSTK1003	AT32AP7001
+	ATSTK1004	AT32AP7002
+	ATSTK1006	AT32AP7000
+	ATNGW100	AT32AP7000
+
+#########################################################################
+# SuperH Systems:							#
+#									#
+# Maintainer Name, Email Address					#
+#	Board		CPU						#
+#########################################################################
+
+Yusuke Goda <goda.yusuke@renesas.com>
+
+	MIGO-R		SH7722
+
+Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+		  <iwamatsu.nobuhiro@renesas.com>
+
+	MS7750SE	SH7750
+	MS7722SE	SH7722
+	R7780MP		SH7780
+	R2DPlus		SH7751R
+	SH7763RDP	SH7763
+	RSK7203		SH7203
+	AP325RXA	SH7723
+
+Mark Jonas <mark.jonas@de.bosch.com>
+
+	mpr2		SH7720
+
+Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+
+	MS7720SE	SH7720
+	R0P77850011RL	SH7785
+
+#########################################################################
+# Blackfin Systems:							#
+#									#
+# Maintainer Name, Email Address					#
+#	Board		CPU						#
+#########################################################################
+
+Mike Frysinger <vapier@gentoo.org>
+Blackfin Team <u-boot-devel@blackfin.uclinux.org>
+
+	BF518F-EZBRD	BF518
+	BF526-EZBRD	BF526
+	BF527-EZKIT	BF527
+	BF533-EZKIT	BF533
+	BF533-STAMP	BF533
+	BF537-PNAV	BF537
+	BF537-STAMP	BF537
+	BF538F-EZKIT	BF538
+	BF548-EZKIT	BF548
+	BF561-EZKIT	BF561
+
+Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
+Blackfin Team <u-boot-devel@blackfin.uclinux.org>
+
+	CM-BF527	BF527
+	CM-BF533	BF533
+	CM-BF537E	BF537
+	CM-BF537U	BF537
+	CM-BF548	BF548
+	CM-BF561	BF561
+	TCM-BF537	BF537
+
+Martin Strubel <strubel@section5.ch>
+Blackfin Team <u-boot-devel@blackfin.uclinux.org>
+
+	BF537-minotaur	BF537
+	BF537-srv1	BF537
+
+Wojtek Skulski <skulski@pas.rochester.edu>
+Benjamin Matthews <mben12@gmail.com>
+
+	BLACKSTAMP	BF532
+
+I-SYST Micromodule <support@i-syst.com>
+Blackfin Team <u-boot-devel@blackfin.uclinux.org>
+
+	IBF-DSP561	BF561
+
+#########################################################################
+# End of MAINTAINERS list						#
+#########################################################################

api/Makefile

@@ -1,22 +1,37 @@
 #
 # (C) Copyright 2007 Semihalf
 #
-# SPDX-License-Identifier:	GPL-2.0+
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundatio; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
 #
 
 include $(TOPDIR)/config.mk
 
-LIB	= $(obj)libapi.o
+LIB	= $(obj)libapi.a
 
-COBJS-$(CONFIG_API) += api.o api_display.o api_net.o api_storage.o \
-		       api_platform-$(ARCH).o
+COBJS-$(CONFIG_API) += api.o api_net.o api_storage.o api_platform-$(ARCH).o
 
 COBJS	:= $(COBJS-y)
 SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
 
 $(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
+	$(AR) $(ARFLAGS) $@ $(OBJS)
 
 # defines $(obj).depend target
 include $(SRCTREE)/rules.mk

api/api.c

@@ -3,7 +3,24 @@
  *
  * Written by: Rafal Jaworowski <raj@semihalf.com>
  *
- * SPDX-License-Identifier:	GPL-2.0+
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
  */
 
 #include <config.h>
@@ -19,6 +36,9 @@
 #define DEBUG
 #undef DEBUG
 
+/* U-Boot routines needed */
+extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+
 /*****************************************************************************
  *
  * This is the API core.
@@ -536,50 +556,6 @@ static int API_env_enum(va_list ap)
 	return 0;
 }
 
-/*
- * pseudo signature:
- *
- * int API_display_get_info(int type, struct display_info *di)
- */
-static int API_display_get_info(va_list ap)
-{
-	int type;
-	struct display_info *di;
-
-	type = va_arg(ap, int);
-	di = va_arg(ap, struct display_info *);
-
-	return display_get_info(type, di);
-}
-
-/*
- * pseudo signature:
- *
- * int API_display_draw_bitmap(ulong bitmap, int x, int y)
- */
-static int API_display_draw_bitmap(va_list ap)
-{
-	ulong bitmap;
-	int x, y;
-
-	bitmap = va_arg(ap, ulong);
-	x = va_arg(ap, int);
-	y = va_arg(ap, int);
-
-	return display_draw_bitmap(bitmap, x, y);
-}
-
-/*
- * pseudo signature:
- *
- * void API_display_clear(void)
- */
-static int API_display_clear(va_list ap)
-{
-	display_clear();
-	return 0;
-}
-
 static cfp_t calls_table[API_MAXCALL] = { NULL, };
 
 /*
@@ -643,9 +619,6 @@ void api_init(void)
 	calls_table[API_ENV_GET] = &API_env_get;
 	calls_table[API_ENV_SET] = &API_env_set;
 	calls_table[API_ENV_ENUM] = &API_env_enum;
-	calls_table[API_DISPLAY_GET_INFO] = &API_display_get_info;
-	calls_table[API_DISPLAY_DRAW_BITMAP] = &API_display_draw_bitmap;
-	calls_table[API_DISPLAY_CLEAR] = &API_display_clear;
 	calls_no = API_MAXCALL;
 
 	debugf("API initialized with %d calls\n", calls_no);

api/api_display.c

@@ -1,58 +0,0 @@
-/*
- * Copyright (c) 2011 The Chromium OS Authors.
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <api_public.h>
-#include <lcd.h>
-#include <video_font.h> /* Get font width and height */
-
-/* lcd.h needs BMP_LOGO_HEIGHT to calculate CONSOLE_ROWS */
-#if defined(CONFIG_LCD_LOGO) && !defined(CONFIG_LCD_INFO_BELOW_LOGO)
-#include <bmp_logo.h>
-#endif
-
-/* TODO(clchiou): add support of video device */
-
-int display_get_info(int type, struct display_info *di)
-{
-	if (!di)
-		return API_EINVAL;
-
-	switch (type) {
-	default:
-		debug("%s: unsupport display device type: %d\n",
-				__FILE__, type);
-		return API_ENODEV;
-#ifdef CONFIG_LCD
-	case DISPLAY_TYPE_LCD:
-		di->pixel_width  = panel_info.vl_col;
-		di->pixel_height = panel_info.vl_row;
-		di->screen_rows = lcd_get_screen_rows();
-		di->screen_cols = lcd_get_screen_columns();
-		break;
-#endif
-	}
-
-	di->type = type;
-	return 0;
-}
-
-int display_draw_bitmap(ulong bitmap, int x, int y)
-{
-	if (!bitmap)
-		return API_EINVAL;
-#ifdef CONFIG_LCD
-	return lcd_display_bitmap(bitmap, x, y);
-#else
-	return API_ENODEV;
-#endif
-}
-
-void display_clear(void)
-{
-#ifdef CONFIG_LCD
-	lcd_clear();
-#endif
-}

api/api_net.c

@@ -3,7 +3,24 @@
  *
  * Written by: Rafal Jaworowski <raj@semihalf.com>
  *
- * SPDX-License-Identifier:	GPL-2.0+
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
  */
 
 #include <config.h>
@@ -17,6 +34,10 @@ DECLARE_GLOBAL_DATA_PTR;
 #define DEBUG
 #undef DEBUG
 
+#if !defined(CONFIG_NET_MULTI)
+#error "API/net is currently only available for platforms with CONFIG_NET_MULTI"
+#endif
+
 #ifdef DEBUG
 #define debugf(fmt, args...) do { printf("%s(): ", __func__); printf(fmt, ##args); } while (0)
 #else

api/api_platform-arm.c

@@ -3,10 +3,28 @@
  *
  * Written by: Rafal Jaworowski <raj@semihalf.com>
  *
- * SPDX-License-Identifier:	GPL-2.0+
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
  *
  * This file contains routines that fetch data from ARM-dependent sources
  * (bd_info etc.)
+ *
  */
 
 #include <config.h>

api/api_platform-powerpc.c

@@ -1,54 +0,0 @@
-/*
- * (C) Copyright 2007 Semihalf
- *
- * Written by: Rafal Jaworowski <raj@semihalf.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * This file contains routines that fetch data from PowerPC-dependent sources
- * (bd_info etc.)
- */
-
-#include <config.h>
-#include <linux/types.h>
-#include <api_public.h>
-
-#include <asm/u-boot.h>
-#include <asm/global_data.h>
-
-#include "api_private.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Important notice: handling of individual fields MUST be kept in sync with
- * include/asm-ppc/u-boot.h and include/asm-ppc/global_data.h, so any changes
- * need to reflect their current state and layout of structures involved!
- */
-int platform_sys_info(struct sys_info *si)
-{
-	si->clk_bus = gd->bus_clk;
-	si->clk_cpu = gd->cpu_clk;
-
-#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260) || \
-    defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
-#define bi_bar	bi_immr_base
-#elif defined(CONFIG_MPC5xxx)
-#define bi_bar	bi_mbar_base
-#elif defined(CONFIG_MPC83xx)
-#define bi_bar	bi_immrbar
-#endif
-
-#if defined(bi_bar)
-	si->bar = gd->bd->bi_bar;
-#undef bi_bar
-#else
-	si->bar = 0;
-#endif
-
-	platform_set_mr(si, gd->bd->bi_memstart, gd->bd->bi_memsize, MR_ATTR_DRAM);
-	platform_set_mr(si, gd->bd->bi_flashstart, gd->bd->bi_flashsize, MR_ATTR_FLASH);
-	platform_set_mr(si, gd->bd->bi_sramstart, gd->bd->bi_sramsize, MR_ATTR_SRAM);
-
-	return 1;
-}

api/api_platform-ppc.c

@@ -0,0 +1,74 @@
+/*
+ * (C) Copyright 2007 Semihalf
+ *
+ * Written by: Rafal Jaworowski <raj@semihalf.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ *
+ * This file contains routines that fetch data from PowerPC-dependent sources
+ * (bd_info etc.)
+ *
+ */
+
+#include <config.h>
+#include <linux/types.h>
+#include <api_public.h>
+
+#include <asm/u-boot.h>
+#include <asm/global_data.h>
+
+#include "api_private.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Important notice: handling of individual fields MUST be kept in sync with
+ * include/asm-ppc/u-boot.h and include/asm-ppc/global_data.h, so any changes
+ * need to reflect their current state and layout of structures involved!
+ */
+int platform_sys_info(struct sys_info *si)
+{
+	si->clk_bus = gd->bus_clk;
+	si->clk_cpu = gd->cpu_clk;
+
+#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260) || \
+    defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
+#define bi_bar	bi_immr_base
+#elif defined(CONFIG_MPC5xxx)
+#define bi_bar	bi_mbar_base
+#elif defined(CONFIG_MPC83xx)
+#define bi_bar	bi_immrbar
+#elif defined(CONFIG_MPC8220)
+#define bi_bar	bi_mbar_base
+#endif
+
+#if defined(bi_bar)
+	si->bar = gd->bd->bi_bar;
+#undef bi_bar
+#else
+	si->bar = 0;
+#endif
+
+	platform_set_mr(si, gd->bd->bi_memstart, gd->bd->bi_memsize, MR_ATTR_DRAM);
+	platform_set_mr(si, gd->bd->bi_flashstart, gd->bd->bi_flashsize, MR_ATTR_FLASH);
+	platform_set_mr(si, gd->bd->bi_sramstart, gd->bd->bi_sramsize, MR_ATTR_SRAM);
+
+	return 1;
+}

api/api_private.h

@@ -3,7 +3,24 @@
  *
  * Written by: Rafal Jaworowski <raj@semihalf.com>
  *
- * SPDX-License-Identifier:	GPL-2.0+
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
  */
 
 #ifndef _API_PRIVATE_H_
@@ -28,8 +45,4 @@ int		dev_write_net(void *, void *, int);
 
 void dev_stor_init(void);
 
-int display_get_info(int type, struct display_info *di);
-int display_draw_bitmap(ulong bitmap, int x, int y);
-void display_clear(void);
-
 #endif /* _API_PRIVATE_H_ */

api/api_storage.c

@@ -3,7 +3,24 @@
  *
  * Written by: Rafal Jaworowski <raj@semihalf.com>
  *
- * SPDX-License-Identifier:	GPL-2.0+
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
  */
 
 #include <config.h>

arch/.gitignore

@@ -1,2 +0,0 @@
-/*/include/asm/arch
-/*/include/asm/proc

arch/arm/config.mk

@@ -1,105 +0,0 @@
-#
-# (C) Copyright 2000-2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-CROSS_COMPILE ?= arm-linux-
-
-ifndef CONFIG_STANDALONE_LOAD_ADDR
-ifneq ($(CONFIG_OMAP_COMMON),)
-CONFIG_STANDALONE_LOAD_ADDR = 0x80300000
-else
-CONFIG_STANDALONE_LOAD_ADDR = 0xc100000
-endif
-endif
-
-LDFLAGS_FINAL += --gc-sections
-PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections \
-		     -fno-common -ffixed-r9 -msoft-float
-
-# Support generic board on ARM
-__HAVE_ARCH_GENERIC_BOARD := y
-
-PLATFORM_CPPFLAGS += -DCONFIG_ARM -D__ARM__
-
-# Choose between ARM/Thumb instruction sets
-ifeq ($(CONFIG_SYS_THUMB_BUILD),y)
-PF_CPPFLAGS_ARM := $(call cc-option, -mthumb -mthumb-interwork,\
-			$(call cc-option,-marm,)\
-			$(call cc-option,-mno-thumb-interwork,)\
-		)
-else
-PF_CPPFLAGS_ARM := $(call cc-option,-marm,) \
-		$(call cc-option,-mno-thumb-interwork,)
-endif
-
-# Only test once
-ifneq ($(CONFIG_SPL_BUILD),y)
-ALL-$(CONFIG_SYS_THUMB_BUILD)	+= checkthumb
-endif
-
-# Try if EABI is supported, else fall back to old API,
-# i. e. for example:
-# - with ELDK 4.2 (EABI supported), use:
-#	-mabi=aapcs-linux
-# - with ELDK 4.1 (gcc 4.x, no EABI), use:
-#	-mabi=apcs-gnu
-# - with ELDK 3.1 (gcc 3.x), use:
-#	-mapcs-32
-PF_CPPFLAGS_ABI := $(call cc-option,\
-			-mabi=aapcs-linux,\
-			$(call cc-option,\
-				-mapcs-32,\
-				$(call cc-option,\
-					-mabi=apcs-gnu,\
-				)\
-			)\
-		)
-PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_ARM) $(PF_CPPFLAGS_ABI)
-
-# For EABI, make sure to provide raise()
-ifneq (,$(findstring -mabi=aapcs-linux,$(PLATFORM_CPPFLAGS)))
-# This file is parsed many times, so the string may get added multiple
-# times. Also, the prefix needs to be different based on whether
-# CONFIG_SPL_BUILD is defined or not. 'filter-out' the existing entry
-# before adding the correct one.
-ifdef CONFIG_SPL_BUILD
-PLATFORM_LIBS := $(SPLTREE)/arch/arm/lib/eabi_compat.o \
-	$(filter-out %/arch/arm/lib/eabi_compat.o, $(PLATFORM_LIBS))
-else
-PLATFORM_LIBS := $(OBJTREE)/arch/arm/lib/eabi_compat.o \
-	$(filter-out %/arch/arm/lib/eabi_compat.o, $(PLATFORM_LIBS))
-endif
-endif
-
-# needed for relocation
-LDFLAGS_u-boot += -pie
-
-#
-# FIXME: binutils versions < 2.22 have a bug in the assembler where
-# branches to weak symbols can be incorrectly optimized in thumb mode
-# to a short branch (b.n instruction) that won't reach when the symbol
-# gets preempted
-#
-# http://sourceware.org/bugzilla/show_bug.cgi?id=12532
-#
-ifeq ($(CONFIG_SYS_THUMB_BUILD),y)
-ifeq ($(GAS_BUG_12532),)
-export GAS_BUG_12532:=$(shell if [ $(call binutils-version) -lt 0222 ] ; \
-	then echo y; else echo n; fi)
-endif
-ifeq ($(GAS_BUG_12532),y)
-PLATFORM_RELFLAGS += -fno-optimize-sibling-calls
-endif
-endif
-
-ifneq ($(CONFIG_SPL_BUILD),y)
-# Check that only R_ARM_RELATIVE relocations are generated.
-ALL-y += checkarmreloc
-# The movt / movw can hardcode 16 bit parts of the addresses in the
-# instruction. Relocation is not supported for that case, so disable
-# such usage by requiring word relocations.
-PLATFORM_CPPFLAGS += $(call cc-option, -mword-relocations)
-endif

arch/arm/cpu/arm1136/Makefile

@@ -1,31 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(CPU).o
-
-START	= start.o
-COBJS	= cpu.o
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################

arch/arm/cpu/arm1136/config.mk

@@ -1,26 +0,0 @@
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-# Make ARMv5 to allow more compilers to work, even though its v6.
-PLATFORM_CPPFLAGS += -march=armv5
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# =========================================================================
-PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
-PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
-
-ifneq ($(CONFIG_IMX_CONFIG),)
-ifdef CONFIG_SPL
-ifdef CONFIG_SPL_BUILD
-ALL-y	+= $(OBJTREE)/SPL
-endif
-else
-ALL-y	+= $(obj)u-boot.imx
-endif
-endif

arch/arm/cpu/arm1136/cpu.c

@@ -1,160 +0,0 @@
-/*
- * (C) Copyright 2004 Texas Insturments
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * CPU specific code
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/system.h>
-
-static void cache_flush(void);
-
-int cleanup_before_linux (void)
-{
-	/*
-	 * this function is called just before we call linux
-	 * it prepares the processor for linux
-	 *
-	 * we turn off caches etc ...
-	 */
-
-	disable_interrupts ();
-
-#ifdef CONFIG_LCD
-	{
-		extern void lcd_disable(void);
-		extern void lcd_panel_disable(void);
-
-		lcd_disable(); /* proper disable of lcd & panel */
-		lcd_panel_disable();
-	}
-#endif
-
-	/* turn off I/D-cache */
-	icache_disable();
-	dcache_disable();
-	/* flush I/D-cache */
-	cache_flush();
-
-	return 0;
-}
-
-static void cache_flush(void)
-{
-	unsigned long i = 0;
-	/* clean entire data cache */
-	asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (i));
-	/* invalidate both caches and flush btb */
-	asm volatile("mcr p15, 0, %0, c7, c7, 0" : : "r" (i));
-	/* mem barrier to sync things */
-	asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (i));
-}
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-
-#ifndef CONFIG_SYS_CACHELINE_SIZE
-#define CONFIG_SYS_CACHELINE_SIZE	32
-#endif
-
-void invalidate_dcache_all(void)
-{
-	asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
-}
-
-void flush_dcache_all(void)
-{
-	asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (0));
-	asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
-}
-
-static int check_cache_range(unsigned long start, unsigned long stop)
-{
-	int ok = 1;
-
-	if (start & (CONFIG_SYS_CACHELINE_SIZE - 1))
-		ok = 0;
-
-	if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1))
-		ok = 0;
-
-	if (!ok)
-		debug("CACHE: Misaligned operation at range [%08lx, %08lx]\n",
-			start, stop);
-
-	return ok;
-}
-
-void invalidate_dcache_range(unsigned long start, unsigned long stop)
-{
-	if (!check_cache_range(start, stop))
-		return;
-
-	while (start < stop) {
-		asm volatile("mcr p15, 0, %0, c7, c6, 1" : : "r" (start));
-		start += CONFIG_SYS_CACHELINE_SIZE;
-	}
-}
-
-void flush_dcache_range(unsigned long start, unsigned long stop)
-{
-	if (!check_cache_range(start, stop))
-		return;
-
-	while (start < stop) {
-		asm volatile("mcr p15, 0, %0, c7, c14, 1" : : "r" (start));
-		start += CONFIG_SYS_CACHELINE_SIZE;
-	}
-
-	asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
-}
-
-void flush_cache(unsigned long start, unsigned long size)
-{
-	flush_dcache_range(start, start + size);
-}
-
-#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
-void invalidate_dcache_all(void)
-{
-}
-
-void flush_dcache_all(void)
-{
-}
-
-void invalidate_dcache_range(unsigned long start, unsigned long stop)
-{
-}
-
-void flush_dcache_range(unsigned long start, unsigned long stop)
-{
-}
-
-void flush_cache(unsigned long start, unsigned long size)
-{
-}
-#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
-
-#if !defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF)
-void enable_caches(void)
-{
-#ifndef CONFIG_SYS_ICACHE_OFF
-	icache_enable();
-#endif
-#ifndef CONFIG_SYS_DCACHE_OFF
-	dcache_enable();
-#endif
-}
-#endif

arch/arm/cpu/arm1136/mx31/Makefile

@@ -1,31 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS	+= generic.o
-COBJS	+= timer.o
-COBJS	+= devices.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################

arch/arm/cpu/arm1136/mx31/devices.c

@@ -1,51 +0,0 @@
-/*
- *
- * (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
- *
- * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/clock.h>
-
-void mx31_uart1_hw_init(void)
-{
-	/* setup pins for UART1 */
-	mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
-	mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
-	mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
-	mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
-}
-
-void mx31_uart2_hw_init(void)
-{
-	/* setup pins for UART2 */
-	mx31_gpio_mux(MUX_RXD2__UART2_RXD_MUX);
-	mx31_gpio_mux(MUX_TXD2__UART2_TXD_MUX);
-	mx31_gpio_mux(MUX_RTS2__UART2_RTS_B);
-	mx31_gpio_mux(MUX_CTS2__UART2_CTS_B);
-}
-
-#ifdef CONFIG_MXC_SPI
-/*
- * Note: putting several spi setups here makes no sense as they may differ
- * at board level (physical pin SS0 of CSPI2 may aswell be used as SS0 of CSPI3)
- */
-void mx31_spi2_hw_init(void)
-{
-	/* SPI2 */
-	mx31_gpio_mux(MUX_CSPI2_SS2__CSPI2_SS2_B);
-	mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK);
-	mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B);
-	mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI);
-	mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO);
-	mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B);
-	mx31_gpio_mux(MUX_CSPI2_SS1__CSPI2_SS1_B);
-
-	/* start SPI2 clock */
-	__REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 4);
-}
-#endif

arch/arm/cpu/arm1136/mx31/generic.c

@@ -1,219 +0,0 @@
-/*
- * (C) Copyright 2007
- * Sascha Hauer, Pengutronix
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <div64.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/clock.h>
-#include <asm/io.h>
-#include <asm/arch/sys_proto.h>
-
-static u32 mx31_decode_pll(u32 reg, u32 infreq)
-{
-	u32 mfi = GET_PLL_MFI(reg);
-	s32 mfn = GET_PLL_MFN(reg);
-	u32 mfd = GET_PLL_MFD(reg);
-	u32 pd =  GET_PLL_PD(reg);
-
-	mfi = mfi <= 5 ? 5 : mfi;
-	mfn = mfn >= 512 ? mfn - 1024 : mfn;
-	mfd += 1;
-	pd += 1;
-
-	return lldiv(2 * (u64)infreq * (mfi * mfd + mfn),
-		mfd * pd);
-}
-
-static u32 mx31_get_mpl_dpdgck_clk(void)
-{
-	u32 infreq;
-
-	if ((readl(CCM_CCMR) & CCMR_PRCS_MASK) == CCMR_FPM)
-		infreq = MXC_CLK32 * 1024;
-	else
-		infreq = MXC_HCLK;
-
-	return mx31_decode_pll(readl(CCM_MPCTL), infreq);
-}
-
-static u32 mx31_get_mcu_main_clk(void)
-{
-	/* For now we assume mpl_dpdgck_clk == mcu_main_clk
-	 * which should be correct for most boards
-	 */
-	return mx31_get_mpl_dpdgck_clk();
-}
-
-static u32 mx31_get_ipg_clk(void)
-{
-	u32 freq = mx31_get_mcu_main_clk();
-	u32 pdr0 = readl(CCM_PDR0);
-
-	freq /= GET_PDR0_MAX_PODF(pdr0) + 1;
-	freq /= GET_PDR0_IPG_PODF(pdr0) + 1;
-
-	return freq;
-}
-
-/* hsp is the clock for the ipu */
-static u32 mx31_get_hsp_clk(void)
-{
-	u32 freq = mx31_get_mcu_main_clk();
-	u32 pdr0 = readl(CCM_PDR0);
-
-	freq /= GET_PDR0_HSP_PODF(pdr0) + 1;
-
-	return freq;
-}
-
-void mx31_dump_clocks(void)
-{
-	u32 cpufreq = mx31_get_mcu_main_clk();
-	printf("mx31 cpu clock: %dMHz\n", cpufreq / 1000000);
-	printf("ipg clock     : %dHz\n", mx31_get_ipg_clk());
-	printf("hsp clock     : %dHz\n", mx31_get_hsp_clk());
-}
-
-unsigned int mxc_get_clock(enum mxc_clock clk)
-{
-	switch (clk) {
-	case MXC_ARM_CLK:
-		return mx31_get_mcu_main_clk();
-	case MXC_IPG_CLK:
-	case MXC_IPG_PERCLK:
-	case MXC_CSPI_CLK:
-	case MXC_UART_CLK:
-	case MXC_ESDHC_CLK:
-	case MXC_I2C_CLK:
-		return mx31_get_ipg_clk();
-	case MXC_IPU_CLK:
-		return mx31_get_hsp_clk();
-	}
-	return -1;
-}
-
-u32 imx_get_uartclk(void)
-{
-	return mxc_get_clock(MXC_UART_CLK);
-}
-
-void mx31_gpio_mux(unsigned long mode)
-{
-	unsigned long reg, shift, tmp;
-
-	reg = IOMUXC_BASE + (mode & 0x1fc);
-	shift = (~mode & 0x3) * 8;
-
-	tmp = readl(reg);
-	tmp &= ~(0xff << shift);
-	tmp |= ((mode >> IOMUX_MODE_POS) & 0xff) << shift;
-	writel(tmp, reg);
-}
-
-void mx31_set_pad(enum iomux_pins pin, u32 config)
-{
-	u32 field, l, reg;
-
-	pin &= IOMUX_PADNUM_MASK;
-	reg = (IOMUXC_BASE + 0x154) + (pin + 2) / 3 * 4;
-	field = (pin + 2) % 3;
-
-	l = readl(reg);
-	l &= ~(0x1ff << (field * 10));
-	l |= config << (field * 10);
-	writel(l, reg);
-
-}
-
-void mx31_set_gpr(enum iomux_gp_func gp, char en)
-{
-	u32 l;
-	struct iomuxc_regs *iomuxc = (struct iomuxc_regs *)IOMUXC_BASE;
-
-	l = readl(&iomuxc->gpr);
-	if (en)
-		l |= gp;
-	else
-		l &= ~gp;
-
-	writel(l, &iomuxc->gpr);
-}
-
-void mxc_setup_weimcs(int cs, const struct mxc_weimcs *weimcs)
-{
-	struct mx31_weim *weim = (struct mx31_weim *) WEIM_BASE;
-	struct mx31_weim_cscr *cscr = &weim->cscr[cs];
-
-	writel(weimcs->upper, &cscr->upper);
-	writel(weimcs->lower, &cscr->lower);
-	writel(weimcs->additional, &cscr->additional);
-}
-
-struct mx3_cpu_type mx31_cpu_type[] = {
-	{ .srev = 0x00, .v = 0x10 },
-	{ .srev = 0x10, .v = 0x11 },
-	{ .srev = 0x11, .v = 0x11 },
-	{ .srev = 0x12, .v = 0x1F },
-	{ .srev = 0x13, .v = 0x1F },
-	{ .srev = 0x14, .v = 0x12 },
-	{ .srev = 0x15, .v = 0x12 },
-	{ .srev = 0x28, .v = 0x20 },
-	{ .srev = 0x29, .v = 0x20 },
-};
-
-u32 get_cpu_rev(void)
-{
-	u32 i, srev;
-
-	/* read SREV register from IIM module */
-	struct iim_regs *iim = (struct iim_regs *)MX31_IIM_BASE_ADDR;
-	srev = readl(&iim->iim_srev);
-
-	for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++)
-		if (srev == mx31_cpu_type[i].srev)
-			return mx31_cpu_type[i].v;
-
-	return srev | 0x8000;
-}
-
-static char *get_reset_cause(void)
-{
-	/* read RCSR register from CCM module */
-	struct clock_control_regs *ccm =
-		(struct clock_control_regs *)CCM_BASE;
-
-	u32 cause = readl(&ccm->rcsr) & 0x07;
-
-	switch (cause) {
-	case 0x0000:
-		return "POR";
-	case 0x0001:
-		return "RST";
-	case 0x0002:
-		return "WDOG";
-	case 0x0006:
-		return "JTAG";
-	case 0x0007:
-		return "ARM11P power gating";
-	default:
-		return "unknown reset";
-	}
-}
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo(void)
-{
-	u32 srev = get_cpu_rev();
-
-	printf("CPU:   Freescale i.MX31 rev %d.%d%s at %d MHz.\n",
-			(srev & 0xF0) >> 4, (srev & 0x0F),
-			((srev & 0x8000) ? " unknown" : ""),
-			mx31_get_mcu_main_clk() / 1000000);
-	printf("Reset cause: %s\n", get_reset_cause());
-	return 0;
-}
-#endif

arch/arm/cpu/arm1136/mx31/timer.c

@@ -1,147 +0,0 @@
-/*
- * (C) Copyright 2007
- * Sascha Hauer, Pengutronix
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/clock.h>
-#include <div64.h>
-#include <watchdog.h>
-#include <asm/io.h>
-
-#define TIMER_BASE 0x53f90000 /* General purpose timer 1 */
-
-/* General purpose timers registers */
-#define GPTCR	__REG(TIMER_BASE)		/* Control register	*/
-#define GPTPR	__REG(TIMER_BASE + 0x4)		/* Prescaler register	*/
-#define GPTSR	__REG(TIMER_BASE + 0x8)		/* Status register	*/
-#define GPTCNT	__REG(TIMER_BASE + 0x24)	/* Counter register	*/
-
-/* General purpose timers bitfields */
-#define GPTCR_SWR		(1 << 15)	/* Software reset	*/
-#define GPTCR_FRR		(1 << 9)	/* Freerun / restart	*/
-#define GPTCR_CLKSOURCE_32	(4 << 6)	/* Clock source		*/
-#define GPTCR_TEN		1		/* Timer enable		*/
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * "time" is measured in 1 / CONFIG_SYS_HZ seconds,
- * "tick" is internal timer period
- */
-
-#ifdef CONFIG_MX31_TIMER_HIGH_PRECISION
-/* ~0.4% error - measured with stop-watch on 100s boot-delay */
-static inline unsigned long long tick_to_time(unsigned long long tick)
-{
-	tick *= CONFIG_SYS_HZ;
-	do_div(tick, MXC_CLK32);
-	return tick;
-}
-
-static inline unsigned long long time_to_tick(unsigned long long time)
-{
-	time *= MXC_CLK32;
-	do_div(time, CONFIG_SYS_HZ);
-	return time;
-}
-
-static inline unsigned long long us_to_tick(unsigned long long us)
-{
-	us = us * MXC_CLK32 + 999999;
-	do_div(us, 1000000);
-	return us;
-}
-#else
-/* ~2% error */
-#define TICK_PER_TIME	((MXC_CLK32 + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ)
-#define US_PER_TICK	(1000000 / MXC_CLK32)
-
-static inline unsigned long long tick_to_time(unsigned long long tick)
-{
-	do_div(tick, TICK_PER_TIME);
-	return tick;
-}
-
-static inline unsigned long long time_to_tick(unsigned long long time)
-{
-	return time * TICK_PER_TIME;
-}
-
-static inline unsigned long long us_to_tick(unsigned long long us)
-{
-	us += US_PER_TICK - 1;
-	do_div(us, US_PER_TICK);
-	return us;
-}
-#endif
-
-/* The 32768Hz 32-bit timer overruns in 131072 seconds */
-int timer_init(void)
-{
-	int i;
-
-	/* setup GP Timer 1 */
-	GPTCR = GPTCR_SWR;
-	for (i = 0; i < 100; i++)
-		GPTCR = 0; /* We have no udelay by now */
-	GPTPR = 0; /* 32Khz */
-	/* Freerun Mode, PERCLK1 input */
-	GPTCR |= GPTCR_CLKSOURCE_32 | GPTCR_TEN;
-
-	return 0;
-}
-
-unsigned long long get_ticks(void)
-{
-	ulong now = GPTCNT; /* current tick value */
-
-	if (now >= gd->arch.lastinc)	/* normal mode (non roll) */
-		/* move stamp forward with absolut diff ticks */
-		gd->arch.tbl += (now - gd->arch.lastinc);
-	else			/* we have rollover of incrementer */
-		gd->arch.tbl += (0xFFFFFFFF - gd->arch.lastinc) + now;
-	gd->arch.lastinc = now;
-	return gd->arch.tbl;
-}
-
-ulong get_timer_masked(void)
-{
-	/*
-	 * get_ticks() returns a long long (64 bit), it wraps in
-	 * 2^64 / MXC_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
-	 * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
-	 * 5 * 10^6 days - long enough.
-	 */
-	return tick_to_time(get_ticks());
-}
-
-ulong get_timer(ulong base)
-{
-	return get_timer_masked() - base;
-}
-
-/* delay x useconds AND preserve advance timestamp value */
-void __udelay(unsigned long usec)
-{
-	unsigned long long tmp;
-	ulong tmo;
-
-	tmo = us_to_tick(usec);
-	tmp = get_ticks() + tmo;	/* get current timestamp */
-
-	while (get_ticks() < tmp)	/* loop till event */
-		 /*NOP*/;
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
-	return MXC_CLK32;
-}

arch/arm/cpu/arm1136/mx35/Makefile

@@ -1,34 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS	+= generic.o
-COBJS	+= timer.o
-COBJS	+= mx35_sdram.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################

arch/arm/cpu/arm1136/mx35/asm-offsets.c

@@ -1,71 +0,0 @@
-/*
- * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
- *
- * This program is used to generate definitions needed by
- * assembly language modules.
- *
- * We use the technique used in the OSF Mach kernel code:
- * generate asm statements containing #defines,
- * compile this file to assembler, and then extract the
- * #defines from the assembly-language output.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/imx-regs.h>
-
-#include <linux/kbuild.h>
-
-int main(void)
-{
-	/* Round up to make sure size gives nice stack alignment */
-	DEFINE(CLKCTL_CCMR, offsetof(struct ccm_regs, ccmr));
-	DEFINE(CLKCTL_PDR0, offsetof(struct ccm_regs, pdr0));
-	DEFINE(CLKCTL_PDR1, offsetof(struct ccm_regs, pdr1));
-	DEFINE(CLKCTL_PDR2, offsetof(struct ccm_regs, pdr2));
-	DEFINE(CLKCTL_PDR3, offsetof(struct ccm_regs, pdr3));
-	DEFINE(CLKCTL_PDR4, offsetof(struct ccm_regs, pdr4));
-	DEFINE(CLKCTL_RCSR, offsetof(struct ccm_regs, rcsr));
-	DEFINE(CLKCTL_MPCTL, offsetof(struct ccm_regs, mpctl));
-	DEFINE(CLKCTL_PPCTL, offsetof(struct ccm_regs, ppctl));
-	DEFINE(CLKCTL_ACMR, offsetof(struct ccm_regs, acmr));
-	DEFINE(CLKCTL_COSR, offsetof(struct ccm_regs, cosr));
-	DEFINE(CLKCTL_CGR0, offsetof(struct ccm_regs, cgr0));
-	DEFINE(CLKCTL_CGR1, offsetof(struct ccm_regs, cgr1));
-	DEFINE(CLKCTL_CGR2, offsetof(struct ccm_regs, cgr2));
-	DEFINE(CLKCTL_CGR3, offsetof(struct ccm_regs, cgr3));
-
-	/* Multi-Layer AHB Crossbar Switch */
-	DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0));
-	DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0));
-	DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1));
-	DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1));
-	DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2));
-	DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2));
-	DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3));
-	DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3));
-	DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4));
-	DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4));
-	DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0));
-	DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1));
-	DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2));
-	DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3));
-	DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4));
-	DEFINE(MAX_MGPCR5, offsetof(struct max_regs, mgpcr5));
-
-	/* AHB <-> IP-Bus Interface */
-	DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7));
-	DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15));
-	DEFINE(AIPS_PACR_0_7, offsetof(struct aips_regs, pacr_0_7));
-	DEFINE(AIPS_PACR_8_15, offsetof(struct aips_regs, pacr_8_15));
-	DEFINE(AIPS_PACR_16_23, offsetof(struct aips_regs, pacr_16_23));
-	DEFINE(AIPS_PACR_24_31, offsetof(struct aips_regs, pacr_24_31));
-	DEFINE(AIPS_OPACR_0_7, offsetof(struct aips_regs, opacr_0_7));
-	DEFINE(AIPS_OPACR_8_15, offsetof(struct aips_regs, opacr_8_15));
-	DEFINE(AIPS_OPACR_16_23, offsetof(struct aips_regs, opacr_16_23));
-	DEFINE(AIPS_OPACR_24_31, offsetof(struct aips_regs, opacr_24_31));
-	DEFINE(AIPS_OPACR_32_39, offsetof(struct aips_regs, opacr_32_39));
-
-	return 0;
-}

arch/arm/cpu/arm1136/mx35/generic.c

@@ -1,547 +0,0 @@
-/*
- * (C) Copyright 2007
- * Sascha Hauer, Pengutronix
- *
- * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <div64.h>
-#include <asm/io.h>
-#include <asm/errno.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sys_proto.h>
-#ifdef CONFIG_FSL_ESDHC
-#include <fsl_esdhc.h>
-#endif
-#include <netdev.h>
-#include <spl.h>
-
-#define CLK_CODE(arm, ahb, sel) (((arm) << 16) + ((ahb) << 8) + (sel))
-#define CLK_CODE_ARM(c)		(((c) >> 16) & 0xFF)
-#define CLK_CODE_AHB(c)		(((c) >>  8) & 0xFF)
-#define CLK_CODE_PATH(c)	((c) & 0xFF)
-
-#define CCM_GET_DIVIDER(x, m, o) (((x) & (m)) >> (o))
-
-#ifdef CONFIG_FSL_ESDHC
-DECLARE_GLOBAL_DATA_PTR;
-#endif
-
-static int g_clk_mux_auto[8] = {
-	CLK_CODE(1, 3, 0), CLK_CODE(1, 2, 1), CLK_CODE(2, 1, 1), -1,
-	CLK_CODE(1, 6, 0), CLK_CODE(1, 4, 1), CLK_CODE(2, 2, 1), -1,
-};
-
-static int g_clk_mux_consumer[16] = {
-	CLK_CODE(1, 4, 0), CLK_CODE(1, 3, 1), CLK_CODE(1, 3, 1), -1,
-	-1, -1, CLK_CODE(4, 1, 0), CLK_CODE(1, 5, 0),
-	CLK_CODE(1, 8, 1), CLK_CODE(1, 6, 1), CLK_CODE(2, 4, 0), -1,
-	-1, -1, CLK_CODE(4, 2, 0), -1,
-};
-
-static int hsp_div_table[3][16] = {
-	{4, 3, 2, -1, -1, -1, 1, 5, 4, 3, 2, -1, -1, -1, 1, -1},
-	{-1, -1, -1, -1, -1, -1, -1, -1, 8, 6, 4, -1, -1, -1, 2, -1},
-	{3, -1, -1, -1, -1, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1},
-};
-
-u32 get_cpu_rev(void)
-{
-	int reg;
-	struct iim_regs *iim =
-		(struct iim_regs *)IIM_BASE_ADDR;
-	reg = readl(&iim->iim_srev);
-	if (!reg) {
-		reg = readw(ROMPATCH_REV);
-		reg <<= 4;
-	} else {
-		reg += CHIP_REV_1_0;
-	}
-
-	return 0x35000 + (reg & 0xFF);
-}
-
-static u32 get_arm_div(u32 pdr0, u32 *fi, u32 *fd)
-{
-	int *pclk_mux;
-	if (pdr0 & MXC_CCM_PDR0_AUTO_CON) {
-		pclk_mux = g_clk_mux_consumer +
-			((pdr0 & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >>
-			MXC_CCM_PDR0_CON_MUX_DIV_OFFSET);
-	} else {
-		pclk_mux = g_clk_mux_auto +
-			((pdr0 & MXC_CCM_PDR0_AUTO_MUX_DIV_MASK) >>
-			MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET);
-	}
-
-	if ((*pclk_mux) == -1)
-		return -1;
-
-	if (fi && fd) {
-		if (!CLK_CODE_PATH(*pclk_mux)) {
-			*fi = *fd = 1;
-			return CLK_CODE_ARM(*pclk_mux);
-		}
-		if (pdr0 & MXC_CCM_PDR0_AUTO_CON) {
-			*fi = 3;
-			*fd = 4;
-		} else {
-			*fi = 2;
-			*fd = 3;
-		}
-	}
-	return CLK_CODE_ARM(*pclk_mux);
-}
-
-static int get_ahb_div(u32 pdr0)
-{
-	int *pclk_mux;
-
-	pclk_mux = g_clk_mux_consumer +
-		((pdr0 & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >>
-		MXC_CCM_PDR0_CON_MUX_DIV_OFFSET);
-
-	if ((*pclk_mux) == -1)
-		return -1;
-
-	return CLK_CODE_AHB(*pclk_mux);
-}
-
-static u32 decode_pll(u32 reg, u32 infreq)
-{
-	u32 mfi = (reg >> 10) & 0xf;
-	s32 mfn = reg & 0x3ff;
-	u32 mfd = (reg >> 16) & 0x3ff;
-	u32 pd = (reg >> 26) & 0xf;
-
-	mfi = mfi <= 5 ? 5 : mfi;
-	mfn = mfn >= 512 ? mfn - 1024 : mfn;
-	mfd += 1;
-	pd += 1;
-
-	return lldiv(2 * (u64)infreq * (mfi * mfd + mfn),
-		mfd * pd);
-}
-
-static u32 get_mcu_main_clk(void)
-{
-	u32 arm_div = 0, fi = 0, fd = 0;
-	struct ccm_regs *ccm =
-		(struct ccm_regs *)IMX_CCM_BASE;
-	arm_div = get_arm_div(readl(&ccm->pdr0), &fi, &fd);
-	fi *= decode_pll(readl(&ccm->mpctl), MXC_HCLK);
-	return fi / (arm_div * fd);
-}
-
-static u32 get_ipg_clk(void)
-{
-	u32 freq = get_mcu_main_clk();
-	struct ccm_regs *ccm =
-		(struct ccm_regs *)IMX_CCM_BASE;
-	u32 pdr0 = readl(&ccm->pdr0);
-
-	return freq / (get_ahb_div(pdr0) * 2);
-}
-
-static u32 get_ipg_per_clk(void)
-{
-	u32 freq = get_mcu_main_clk();
-	struct ccm_regs *ccm =
-		(struct ccm_regs *)IMX_CCM_BASE;
-	u32 pdr0 = readl(&ccm->pdr0);
-	u32 pdr4 = readl(&ccm->pdr4);
-	u32 div;
-	if (pdr0 & MXC_CCM_PDR0_PER_SEL) {
-		div = CCM_GET_DIVIDER(pdr4,
-			MXC_CCM_PDR4_PER0_PODF_MASK,
-			MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1;
-	} else {
-		div = CCM_GET_DIVIDER(pdr0,
-			MXC_CCM_PDR0_PER_PODF_MASK,
-			MXC_CCM_PDR0_PER_PODF_OFFSET) + 1;
-		div *= get_ahb_div(pdr0);
-	}
-	return freq / div;
-}
-
-u32 imx_get_uartclk(void)
-{
-	u32 freq;
-	struct ccm_regs *ccm =
-		(struct ccm_regs *)IMX_CCM_BASE;
-	u32 pdr4 = readl(&ccm->pdr4);
-
-	if (readl(&ccm->pdr3) & MXC_CCM_PDR3_UART_M_U)
-		freq = get_mcu_main_clk();
-	else
-		freq = decode_pll(readl(&ccm->ppctl), MXC_HCLK);
-	freq /= CCM_GET_DIVIDER(pdr4,
-			MXC_CCM_PDR4_UART_PODF_MASK,
-			MXC_CCM_PDR4_UART_PODF_OFFSET) + 1;
-	return freq;
-}
-
-unsigned int mxc_get_main_clock(enum mxc_main_clock clk)
-{
-	u32 nfc_pdf, hsp_podf;
-	u32 pll, ret_val = 0, usb_podf;
-	struct ccm_regs *ccm =
-		(struct ccm_regs *)IMX_CCM_BASE;
-
-	u32 reg = readl(&ccm->pdr0);
-	u32 reg4 = readl(&ccm->pdr4);
-
-	reg |= 0x1;
-
-	switch (clk) {
-	case CPU_CLK:
-		ret_val = get_mcu_main_clk();
-		break;
-	case AHB_CLK:
-		ret_val = get_mcu_main_clk();
-		break;
-	case HSP_CLK:
-		if (reg & CLKMODE_CONSUMER) {
-			hsp_podf = (reg >> 20) & 0x3;
-			pll = get_mcu_main_clk();
-			hsp_podf = hsp_div_table[hsp_podf][(reg>>16)&0xF];
-			if (hsp_podf > 0) {
-				ret_val = pll / hsp_podf;
-			} else {
-				puts("mismatch HSP with ARM clock setting\n");
-				ret_val = 0;
-			}
-		} else {
-			ret_val = get_mcu_main_clk();
-		}
-		break;
-	case IPG_CLK:
-		ret_val = get_ipg_clk();
-		break;
-	case IPG_PER_CLK:
-		ret_val = get_ipg_per_clk();
-		break;
-	case NFC_CLK:
-		nfc_pdf = (reg4 >> 28) & 0xF;
-		pll = get_mcu_main_clk();
-		/* AHB/nfc_pdf */
-		ret_val = pll / (nfc_pdf + 1);
-		break;
-	case USB_CLK:
-		usb_podf = (reg4 >> 22) & 0x3F;
-		if (reg4 & 0x200)
-			pll = get_mcu_main_clk();
-		else
-			pll = decode_pll(readl(&ccm->ppctl), MXC_HCLK);
-
-		ret_val = pll / (usb_podf + 1);
-		break;
-	default:
-		printf("Unknown clock: %d\n", clk);
-		break;
-	}
-
-	return ret_val;
-}
-unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk)
-{
-	u32 ret_val = 0, pdf, pre_pdf, clk_sel;
-	struct ccm_regs *ccm =
-		(struct ccm_regs *)IMX_CCM_BASE;
-	u32 mpdr2 = readl(&ccm->pdr2);
-	u32 mpdr3 = readl(&ccm->pdr3);
-	u32 mpdr4 = readl(&ccm->pdr4);
-
-	switch (clk) {
-	case UART1_BAUD:
-	case UART2_BAUD:
-	case UART3_BAUD:
-		clk_sel = mpdr3 & (1 << 14);
-		pdf = (mpdr4 >> 10) & 0x3F;
-		ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
-			decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
-		break;
-	case SSI1_BAUD:
-		pre_pdf = (mpdr2 >> 24) & 0x7;
-		pdf = mpdr2 & 0x3F;
-		clk_sel = mpdr2 & (1 << 6);
-		ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
-			decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
-				((pre_pdf + 1) * (pdf + 1));
-		break;
-	case SSI2_BAUD:
-		pre_pdf = (mpdr2 >> 27) & 0x7;
-		pdf = (mpdr2 >> 8) & 0x3F;
-		clk_sel = mpdr2 & (1 << 6);
-		ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
-			decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
-				((pre_pdf + 1) * (pdf + 1));
-		break;
-	case CSI_BAUD:
-		clk_sel = mpdr2 & (1 << 7);
-		pdf = (mpdr2 >> 16) & 0x3F;
-		ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
-			decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
-		break;
-	case MSHC_CLK:
-		pre_pdf = readl(&ccm->pdr1);
-		clk_sel = (pre_pdf & 0x80);
-		pdf = (pre_pdf >> 22) & 0x3F;
-		pre_pdf = (pre_pdf >> 28) & 0x7;
-		ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
-			decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
-				((pre_pdf + 1) * (pdf + 1));
-		break;
-	case ESDHC1_CLK:
-		clk_sel = mpdr3 & 0x40;
-		pdf = mpdr3 & 0x3F;
-		ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
-			decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
-		break;
-	case ESDHC2_CLK:
-		clk_sel = mpdr3 & 0x40;
-		pdf = (mpdr3 >> 8) & 0x3F;
-		ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
-			decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
-		break;
-	case ESDHC3_CLK:
-		clk_sel = mpdr3 & 0x40;
-		pdf = (mpdr3 >> 16) & 0x3F;
-		ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
-			decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
-		break;
-	case SPDIF_CLK:
-		clk_sel = mpdr3 & 0x400000;
-		pre_pdf = (mpdr3 >> 29) & 0x7;
-		pdf = (mpdr3 >> 23) & 0x3F;
-		ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
-			decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
-				((pre_pdf + 1) * (pdf + 1));
-		break;
-	default:
-		printf("%s(): This clock: %d not supported yet\n",
-				__func__, clk);
-		break;
-	}
-
-	return ret_val;
-}
-
-unsigned int mxc_get_clock(enum mxc_clock clk)
-{
-	switch (clk) {
-	case MXC_ARM_CLK:
-		return get_mcu_main_clk();
-	case MXC_AHB_CLK:
-		break;
-	case MXC_IPG_CLK:
-		return get_ipg_clk();
-	case MXC_IPG_PERCLK:
-	case MXC_I2C_CLK:
-		return get_ipg_per_clk();
-	case MXC_UART_CLK:
-		return imx_get_uartclk();
-	case MXC_ESDHC1_CLK:
-		return mxc_get_peri_clock(ESDHC1_CLK);
-	case MXC_ESDHC2_CLK:
-		return mxc_get_peri_clock(ESDHC2_CLK);
-	case MXC_ESDHC3_CLK:
-		return mxc_get_peri_clock(ESDHC3_CLK);
-	case MXC_USB_CLK:
-		return mxc_get_main_clock(USB_CLK);
-	case MXC_FEC_CLK:
-		return get_ipg_clk();
-	case MXC_CSPI_CLK:
-		return get_ipg_clk();
-	}
-	return -1;
-}
-
-#ifdef CONFIG_FEC_MXC
-/*
- * The MX35 has no fuse for MAC, return a NULL MAC
- */
-void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
-{
-	memset(mac, 0, 6);
-}
-
-u32 imx_get_fecclk(void)
-{
-	return mxc_get_clock(MXC_IPG_CLK);
-}
-#endif
-
-int do_mx35_showclocks(cmd_tbl_t *cmdtp,
-	int flag, int argc, char * const argv[])
-{
-	u32 cpufreq = get_mcu_main_clk();
-	printf("mx35 cpu clock: %dMHz\n", cpufreq / 1000000);
-	printf("ipg clock     : %dHz\n", get_ipg_clk());
-	printf("ipg per clock : %dHz\n", get_ipg_per_clk());
-	printf("uart clock    : %dHz\n", mxc_get_clock(MXC_UART_CLK));
-
-	return 0;
-}
-
-U_BOOT_CMD(
-	clocks,	CONFIG_SYS_MAXARGS, 1, do_mx35_showclocks,
-	"display clocks",
-	""
-);
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-static char *get_reset_cause(void)
-{
-	/* read RCSR register from CCM module */
-	struct ccm_regs *ccm =
-		(struct ccm_regs *)IMX_CCM_BASE;
-
-	u32 cause = readl(&ccm->rcsr) & 0x0F;
-
-	switch (cause) {
-	case 0x0000:
-		return "POR";
-	case 0x0002:
-		return "JTAG";
-	case 0x0004:
-		return "RST";
-	case 0x0008:
-		return "WDOG";
-	default:
-		return "unknown reset";
-	}
-}
-
-int print_cpuinfo(void)
-{
-	u32 srev = get_cpu_rev();
-
-	printf("CPU:   Freescale i.MX35 rev %d.%d at %d MHz.\n",
-		(srev & 0xF0) >> 4, (srev & 0x0F),
-		get_mcu_main_clk() / 1000000);
-
-	printf("Reset cause: %s\n", get_reset_cause());
-
-	return 0;
-}
-#endif
-
-/*
- * Initializes on-chip ethernet controllers.
- * to override, implement board_eth_init()
- */
-int cpu_eth_init(bd_t *bis)
-{
-	int rc = -ENODEV;
-
-#if defined(CONFIG_FEC_MXC)
-	rc = fecmxc_initialize(bis);
-#endif
-
-	return rc;
-}
-
-#ifdef CONFIG_FSL_ESDHC
-/*
- * Initializes on-chip MMC controllers.
- * to override, implement board_mmc_init()
- */
-int cpu_mmc_init(bd_t *bis)
-{
-	return fsl_esdhc_mmc_init(bis);
-}
-#endif
-
-int get_clocks(void)
-{
-#ifdef CONFIG_FSL_ESDHC
-#if CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR
-	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
-#elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR
-	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
-#else
-	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
-#endif
-#endif
-	return 0;
-}
-
-#define RCSR_MEM_CTL_WEIM	0
-#define RCSR_MEM_CTL_NAND	1
-#define RCSR_MEM_CTL_ATA	2
-#define RCSR_MEM_CTL_EXPANSION	3
-#define RCSR_MEM_TYPE_NOR	0
-#define RCSR_MEM_TYPE_ONENAND	2
-#define RCSR_MEM_TYPE_SD	0
-#define RCSR_MEM_TYPE_I2C	2
-#define RCSR_MEM_TYPE_SPI	3
-
-u32 spl_boot_device(void)
-{
-	struct ccm_regs *ccm =
-		(struct ccm_regs *)IMX_CCM_BASE;
-
-	u32 rcsr = readl(&ccm->rcsr);
-	u32 mem_type, mem_ctl;
-
-	/* In external mode, no boot device is returned */
-	if ((rcsr >> 10) & 0x03)
-		return BOOT_DEVICE_NONE;
-
-	mem_ctl = (rcsr >> 25) & 0x03;
-	mem_type = (rcsr >> 23) & 0x03;
-
-	switch (mem_ctl) {
-	case RCSR_MEM_CTL_WEIM:
-		switch (mem_type) {
-		case RCSR_MEM_TYPE_NOR:
-			return BOOT_DEVICE_NOR;
-		case RCSR_MEM_TYPE_ONENAND:
-			return BOOT_DEVICE_ONENAND;
-		default:
-			return BOOT_DEVICE_NONE;
-		}
-	case RCSR_MEM_CTL_NAND:
-		return BOOT_DEVICE_NAND;
-	case RCSR_MEM_CTL_EXPANSION:
-		switch (mem_type) {
-		case RCSR_MEM_TYPE_SD:
-			return BOOT_DEVICE_MMC1;
-		case RCSR_MEM_TYPE_I2C:
-			return BOOT_DEVICE_I2C;
-		case RCSR_MEM_TYPE_SPI:
-			return BOOT_DEVICE_SPI;
-		default:
-			return BOOT_DEVICE_NONE;
-		}
-	}
-
-	return BOOT_DEVICE_NONE;
-}
-
-#ifdef CONFIG_SPL_BUILD
-u32 spl_boot_mode(void)
-{
-	switch (spl_boot_device()) {
-	case BOOT_DEVICE_MMC1:
-#ifdef CONFIG_SPL_FAT_SUPPORT
-		return MMCSD_MODE_FAT;
-#else
-		return MMCSD_MODE_RAW;
-#endif
-		break;
-	case BOOT_DEVICE_NAND:
-		return 0;
-		break;
-	default:
-		puts("spl: ERROR:  unsupported device\n");
-		hang();
-	}
-}
-#endif

arch/arm/cpu/arm1136/mx35/mx35_sdram.c

@@ -1,121 +0,0 @@
-/*
- * Copyright (C) 2012, Stefano Babic <sbabic@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <asm/io.h>
-#include <asm/errno.h>
-#include <asm/arch/imx-regs.h>
-#include <linux/types.h>
-#include <asm/arch/sys_proto.h>
-
-#define ESDCTL_DDR2_EMR2	0x04000000
-#define ESDCTL_DDR2_EMR3	0x06000000
-#define ESDCTL_PRECHARGE	0x00000400
-#define ESDCTL_DDR2_EN_DLL	0x02000400
-#define ESDCTL_DDR2_RESET_DLL	0x00000333
-#define ESDCTL_DDR2_MR		0x00000233
-#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780
-
-enum {
-	SMODE_NORMAL =	0,
-	SMODE_PRECHARGE,
-	SMODE_AUTO_REFRESH,
-	SMODE_LOAD_REG,
-	SMODE_MANUAL_REFRESH
-};
-
-#define set_mode(x, en, m)	(x | (en << 31) | (m << 28))
-
-static inline void dram_wait(unsigned int count)
-{
-	volatile unsigned int wait = count;
-
-	while (wait--)
-		;
-
-}
-
-void mx3_setup_sdram_bank(u32 start_address, u32 ddr2_config,
-	u32 row, u32 col, u32 dsize, u32 refresh)
-{
-	struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
-	u32 *cfg_reg, *ctl_reg;
-	u32 val;
-	u32 ctlval;
-
-	switch (start_address) {
-	case CSD0_BASE_ADDR:
-		cfg_reg = &esdc->esdcfg0;
-		ctl_reg = &esdc->esdctl0;
-		break;
-	case CSD1_BASE_ADDR:
-		cfg_reg = &esdc->esdcfg1;
-		ctl_reg = &esdc->esdctl1;
-		break;
-	default:
-		return;
-	}
-
-	/* The MX35 supports 11 up to 14 rows */
-	if (row < 11 || row > 14 || col < 8 || col > 10)
-		return;
-	ctlval = (row - 11) << 24 | (col - 8) << 20 | (dsize << 16);
-
-	/* Initialize MISC register for DDR2 */
-	val = ESDC_MISC_RST | ESDC_MISC_MDDR_EN | ESDC_MISC_MDDR_DL_RST |
-		ESDC_MISC_DDR_EN | ESDC_MISC_DDR2_EN;
-	writel(val, &esdc->esdmisc);
-	val &= ~(ESDC_MISC_RST | ESDC_MISC_MDDR_DL_RST);
-	writel(val, &esdc->esdmisc);
-
-	/*
-	 * according to DDR2 specs, wait a while before
-	 * the PRECHARGE_ALL command
-	 */
-	dram_wait(0x20000);
-
-	/* Load DDR2 config and timing */
-	writel(ddr2_config, cfg_reg);
-
-	/* Precharge ALL */
-	writel(set_mode(ctlval, 1, SMODE_PRECHARGE),
-		ctl_reg);
-	writel(0xda, start_address + ESDCTL_PRECHARGE);
-
-	/* Load mode */
-	writel(set_mode(ctlval, 1, SMODE_LOAD_REG),
-		ctl_reg);
-	writeb(0xda, start_address + ESDCTL_DDR2_EMR2); /* EMRS2 */
-	writeb(0xda, start_address + ESDCTL_DDR2_EMR3); /* EMRS3 */
-	writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
-	writeb(0xda, start_address + ESDCTL_DDR2_RESET_DLL); /* Reset DLL */
-
-	/* Precharge ALL */
-	writel(set_mode(ctlval, 1, SMODE_PRECHARGE),
-		ctl_reg);
-	writel(0xda, start_address + ESDCTL_PRECHARGE);
-
-	/* Set mode auto refresh : at least two refresh are required */
-	writel(set_mode(ctlval, 1, SMODE_AUTO_REFRESH),
-		ctl_reg);
-	writel(0xda, start_address);
-	writel(0xda, start_address);
-
-	writel(set_mode(ctlval, 1, SMODE_LOAD_REG),
-		ctl_reg);
-	writeb(0xda, start_address + ESDCTL_DDR2_MR);
-	writeb(0xda, start_address + ESDCTL_DDR2_OCD_DEFAULT);
-
-	/* OCD mode exit */
-	writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
-
-	/* Set normal mode */
-	writel(set_mode(ctlval, 1, SMODE_NORMAL) | refresh,
-		ctl_reg);
-
-	dram_wait(0x20000);
-
-	/* Do not set delay lines, only for MDDR */
-}

arch/arm/cpu/arm1136/mx35/timer.c

@@ -1,130 +0,0 @@
-/*
- * (C) Copyright 2007
- * Sascha Hauer, Pengutronix
- *
- * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <div64.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/clock.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define timestamp	(gd->arch.tbl)
-#define lastinc		(gd->arch.lastinc)
-
-/* General purpose timers bitfields */
-#define GPTCR_SWR       (1<<15)	/* Software reset */
-#define GPTCR_FRR       (1<<9)	/* Freerun / restart */
-#define GPTCR_CLKSOURCE_32   (4<<6)	/* Clock source */
-#define GPTCR_TEN       (1)	/* Timer enable */
-
-/*
- * "time" is measured in 1 / CONFIG_SYS_HZ seconds,
- * "tick" is internal timer period
- */
-/* ~0.4% error - measured with stop-watch on 100s boot-delay */
-static inline unsigned long long tick_to_time(unsigned long long tick)
-{
-	tick *= CONFIG_SYS_HZ;
-	do_div(tick, MXC_CLK32);
-
-	return tick;
-}
-
-static inline unsigned long long us_to_tick(unsigned long long us)
-{
-	us = us * MXC_CLK32 + 999999;
-	do_div(us, 1000000);
-
-	return us;
-}
-
-/*
- * nothing really to do with interrupts, just starts up a counter.
- * The 32KHz 32-bit timer overruns in 134217 seconds
- */
-int timer_init(void)
-{
-	int i;
-	struct gpt_regs *gpt = (struct gpt_regs *)GPT1_BASE_ADDR;
-	struct ccm_regs *ccm = (struct ccm_regs *)CCM_BASE_ADDR;
-
-	/* setup GP Timer 1 */
-	writel(GPTCR_SWR, &gpt->ctrl);
-
-	writel(readl(&ccm->cgr1) | 3 << MXC_CCM_CGR1_GPT_OFFSET, &ccm->cgr1);
-
-	for (i = 0; i < 100; i++)
-		writel(0, &gpt->ctrl); /* We have no udelay by now */
-	writel(0, &gpt->pre); /* prescaler = 1 */
-	/* Freerun Mode, 32KHz input */
-	writel(readl(&gpt->ctrl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR,
-			&gpt->ctrl);
-	writel(readl(&gpt->ctrl) | GPTCR_TEN, &gpt->ctrl);
-
-	return 0;
-}
-
-unsigned long long get_ticks(void)
-{
-	struct gpt_regs *gpt = (struct gpt_regs *)GPT1_BASE_ADDR;
-	ulong now = readl(&gpt->counter); /* current tick value */
-
-	if (now >= lastinc) {
-		/*
-		 * normal mode (non roll)
-		 * move stamp forward with absolut diff ticks
-		 */
-		timestamp += (now - lastinc);
-	} else {
-		/* we have rollover of incrementer */
-		timestamp += (0xFFFFFFFF - lastinc) + now;
-	}
-	lastinc = now;
-	return timestamp;
-}
-
-ulong get_timer_masked(void)
-{
-	/*
-	 * get_ticks() returns a long long (64 bit), it wraps in
-	 * 2^64 / MXC_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
-	 * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
-	 * 5 * 10^6 days - long enough.
-	 */
-	return tick_to_time(get_ticks());
-}
-
-ulong get_timer(ulong base)
-{
-	return get_timer_masked() - base;
-}
-
-/* delay x useconds AND preserve advance timstamp value */
-void __udelay(unsigned long usec)
-{
-	unsigned long long tmp;
-	ulong tmo;
-
-	tmo = us_to_tick(usec);
-	tmp = get_ticks() + tmo;	/* get current timestamp */
-
-	while (get_ticks() < tmp)	/* loop till event */
-		 /*NOP*/;
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
-	return MXC_CLK32;
-}

arch/arm/cpu/arm1136/start.S

@@ -1,373 +0,0 @@
-/*
- *  armboot - Startup Code for OMP2420/ARM1136 CPU-core
- *
- *  Copyright (c) 2004	Texas Instruments <r-woodruff2@ti.com>
- *
- *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
- *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
- *  Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
- *  Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
- *  Copyright (c) 2003	Kshitij <kshitij@ti.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <asm-offsets.h>
-#include <config.h>
-#include <version.h>
-.globl _start
-_start: b	reset
-#ifdef CONFIG_SPL_BUILD
-	ldr	pc, _hang
-	ldr	pc, _hang
-	ldr	pc, _hang
-	ldr	pc, _hang
-	ldr	pc, _hang
-	ldr	pc, _hang
-	ldr	pc, _hang
-
-_hang:
-	.word	do_hang
-	.word	0x12345678
-	.word	0x12345678
-	.word	0x12345678
-	.word	0x12345678
-	.word	0x12345678
-	.word	0x12345678
-	.word	0x12345678	/* now 16*4=64 */
-#else
-	ldr	pc, _undefined_instruction
-	ldr	pc, _software_interrupt
-	ldr	pc, _prefetch_abort
-	ldr	pc, _data_abort
-	ldr	pc, _not_used
-	ldr	pc, _irq
-	ldr	pc, _fiq
-
-_undefined_instruction: .word undefined_instruction
-_software_interrupt:	.word software_interrupt
-_prefetch_abort:	.word prefetch_abort
-_data_abort:		.word data_abort
-_not_used:		.word not_used
-_irq:			.word irq
-_fiq:			.word fiq
-_pad:			.word 0x12345678 /* now 16*4=64 */
-#endif	/* CONFIG_SPL_BUILD */
-.global _end_vect
-_end_vect:
-
-	.balignl 16,0xdeadbeef
-/*
- *************************************************************************
- *
- * Startup Code (reset vector)
- *
- * do important init only if we don't start from memory!
- * setup Memory and board specific bits prior to relocation.
- * relocate armboot to ram
- * setup stack
- *
- *************************************************************************
- */
-
-.globl _TEXT_BASE
-_TEXT_BASE:
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
-	.word	CONFIG_SPL_TEXT_BASE
-#else
-	.word	CONFIG_SYS_TEXT_BASE
-#endif
-
-/*
- * These are defined in the board-specific linker script.
- * Subtracting _start from them lets the linker put their
- * relative position in the executable instead of leaving
- * them null.
- */
-.globl _bss_start_ofs
-_bss_start_ofs:
-	.word __bss_start - _start
-
-.globl _bss_end_ofs
-_bss_end_ofs:
-	.word __bss_end - _start
-
-.globl _end_ofs
-_end_ofs:
-	.word _end - _start
-
-#ifdef CONFIG_USE_IRQ
-/* IRQ stack memory (calculated at run-time) */
-.globl IRQ_STACK_START
-IRQ_STACK_START:
-	.word	0x0badc0de
-
-/* IRQ stack memory (calculated at run-time) */
-.globl FIQ_STACK_START
-FIQ_STACK_START:
-	.word 0x0badc0de
-#endif
-
-/* IRQ stack memory (calculated at run-time) + 8 bytes */
-.globl IRQ_STACK_START_IN
-IRQ_STACK_START_IN:
-	.word	0x0badc0de
-
-/*
- * the actual reset code
- */
-
-reset:
-	/*
-	 * set the cpu to SVC32 mode
-	 */
-	mrs	r0,cpsr
-	bic	r0,r0,#0x1f
-	orr	r0,r0,#0xd3
-	msr	cpsr,r0
-
-	/* the mask ROM code should have PLL and others stable */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-	bl  cpu_init_crit
-#endif
-
-	bl	_main
-
-/*------------------------------------------------------------------------------*/
-
-	.globl	c_runtime_cpu_setup
-c_runtime_cpu_setup:
-
-	bx	lr
-
-/*
- *************************************************************************
- *
- * CPU_init_critical registers
- *
- * setup important registers
- * setup memory timing
- *
- *************************************************************************
- */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-cpu_init_crit:
-	/*
-	 * flush v4 I/D caches
-	 */
-	mov	r0, #0
-	mcr	p15, 0, r0, c7, c7, 0	/* Invalidate I+D+BTB caches */
-	mcr	p15, 0, r0, c8, c7, 0	/* Invalidate Unified TLB */
-
-	/*
-	 * disable MMU stuff and caches
-	 */
-	mrc	p15, 0, r0, c1, c0, 0
-	bic	r0, r0, #0x00002300	@ clear bits 13, 9:8 (--V- --RS)
-	bic	r0, r0, #0x00000087	@ clear bits 7, 2:0 (B--- -CAM)
-	orr	r0, r0, #0x00000002	@ set bit 2 (A) Align
-	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
-	mcr	p15, 0, r0, c1, c0, 0
-
-	/*
-	 * Jump to board specific initialization... The Mask ROM will have already initialized
-	 * basic memory.  Go here to bump up clock rate and handle wake up conditions.
-	 */
-	mov	ip, lr		/* persevere link reg across call */
-	bl	lowlevel_init	/* go setup pll,mux,memory */
-	mov	lr, ip		/* restore link */
-	mov	pc, lr		/* back to my caller */
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
-
-#ifndef CONFIG_SPL_BUILD
-/*
- *************************************************************************
- *
- * Interrupt handling
- *
- *************************************************************************
- */
-@
-@ IRQ stack frame.
-@
-#define S_FRAME_SIZE	72
-
-#define S_OLD_R0	68
-#define S_PSR		64
-#define S_PC		60
-#define S_LR		56
-#define S_SP		52
-
-#define S_IP		48
-#define S_FP		44
-#define S_R10		40
-#define S_R9		36
-#define S_R8		32
-#define S_R7		28
-#define S_R6		24
-#define S_R5		20
-#define S_R4		16
-#define S_R3		12
-#define S_R2		8
-#define S_R1		4
-#define S_R0		0
-
-#define MODE_SVC 0x13
-#define I_BIT	 0x80
-
-/*
- * use bad_save_user_regs for abort/prefetch/undef/swi ...
- * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
- */
-
-	.macro	bad_save_user_regs
-	sub	sp, sp, #S_FRAME_SIZE		@ carve out a frame on current user stack
-	stmia	sp, {r0 - r12}			@ Save user registers (now in svc mode) r0-r12
-
-	ldr	r2, IRQ_STACK_START_IN		@ set base 2 words into abort stack
-	ldmia	r2, {r2 - r3}			@ get values for "aborted" pc and cpsr (into parm regs)
-	add	r0, sp, #S_FRAME_SIZE		@ grab pointer to old stack
-
-	add	r5, sp, #S_SP
-	mov	r1, lr
-	stmia	r5, {r0 - r3}			@ save sp_SVC, lr_SVC, pc, cpsr
-	mov	r0, sp				@ save current stack into r0 (param register)
-	.endm
-
-	.macro	irq_save_user_regs
-	sub	sp, sp, #S_FRAME_SIZE
-	stmia	sp, {r0 - r12}			@ Calling r0-r12
-	add	r8, sp, #S_PC			@ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
-	stmdb	r8, {sp, lr}^			@ Calling SP, LR
-	str	lr, [r8, #0]			@ Save calling PC
-	mrs	r6, spsr
-	str	r6, [r8, #4]			@ Save CPSR
-	str	r0, [r8, #8]			@ Save OLD_R0
-	mov	r0, sp
-	.endm
-
-	.macro	irq_restore_user_regs
-	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
-	mov	r0, r0
-	ldr	lr, [sp, #S_PC]			@ Get PC
-	add	sp, sp, #S_FRAME_SIZE
-	subs	pc, lr, #4			@ return & move spsr_svc into cpsr
-	.endm
-
-	.macro get_bad_stack
-	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack (enter in banked mode)
-
-	str	lr, [r13]			@ save caller lr in position 0 of saved stack
-	mrs	lr, spsr			@ get the spsr
-	str	lr, [r13, #4]			@ save spsr in position 1 of saved stack
-
-	mov	r13, #MODE_SVC			@ prepare SVC-Mode
-	@ msr	spsr_c, r13
-	msr	spsr, r13			@ switch modes, make sure moves will execute
-	mov	lr, pc				@ capture return pc
-	movs	pc, lr				@ jump to next instruction & switch modes.
-	.endm
-
-	.macro get_bad_stack_swi
-	sub	r13, r13, #4			@ space on current stack for scratch reg.
-	str	r0, [r13]			@ save R0's value.
-	ldr	r0, IRQ_STACK_START_IN		@ get data regions start
-	str	lr, [r0]			@ save caller lr in position 0 of saved stack
-	mrs	lr, spsr			@ get the spsr
-	str	lr, [r0, #4]			@ save spsr in position 1 of saved stack
-	ldr	lr, [r0]			@ restore lr
-	ldr	r0, [r13]			@ restore r0
-	add	r13, r13, #4			@ pop stack entry
-	.endm
-
-	.macro get_irq_stack			@ setup IRQ stack
-	ldr	sp, IRQ_STACK_START
-	.endm
-
-	.macro get_fiq_stack			@ setup FIQ stack
-	ldr	sp, FIQ_STACK_START
-	.endm
-#endif	/* CONFIG_SPL_BUILD */
-
-/*
- * exception handlers
- */
-#ifdef CONFIG_SPL_BUILD
-	.align	5
-do_hang:
-	ldr	sp, _TEXT_BASE			/* use 32 words about stack */
-	bl	hang				/* hang and never return */
-#else	/* !CONFIG_SPL_BUILD */
-	.align	5
-undefined_instruction:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_undefined_instruction
-
-	.align	5
-software_interrupt:
-	get_bad_stack_swi
-	bad_save_user_regs
-	bl	do_software_interrupt
-
-	.align	5
-prefetch_abort:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_prefetch_abort
-
-	.align	5
-data_abort:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_data_abort
-
-	.align	5
-not_used:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_not_used
-
-#ifdef CONFIG_USE_IRQ
-
-	.align	5
-irq:
-	get_irq_stack
-	irq_save_user_regs
-	bl	do_irq
-	irq_restore_user_regs
-
-	.align	5
-fiq:
-	get_fiq_stack
-	/* someone ought to write a more effiction fiq_save_user_regs */
-	irq_save_user_regs
-	bl	do_fiq
-	irq_restore_user_regs
-
-#else
-
-	.align	5
-irq:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_irq
-
-	.align	5
-fiq:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_fiq
-
-#endif
-	.align 5
-.global arm1136_cache_flush
-arm1136_cache_flush:
-#if !defined(CONFIG_SYS_ICACHE_OFF)
-		mcr	p15, 0, r1, c7, c5, 0	@ invalidate I cache
-#endif
-#if !defined(CONFIG_SYS_DCACHE_OFF)
-		mcr	p15, 0, r1, c7, c14, 0	@ invalidate D cache
-#endif
-		mov	pc, lr			@ back to caller
-#endif	/* CONFIG_SPL_BUILD */

arch/arm/cpu/arm1136/u-boot-spl.lds

@@ -1,46 +0,0 @@
-/*
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * (C) Copyright 2010
- * Texas Instruments, <www.ti.com>
- *	Aneesh V <aneesh@ti.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
-		LENGTH = CONFIG_SPL_MAX_SIZE }
-MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
-		LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
-	.text      :
-	{
-	__start = .;
-	  arch/arm/cpu/arm1136/start.o	(.text*)
-	  *(.text*)
-	} >.sram
-
-	. = ALIGN(4);
-	.rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
-
-	. = ALIGN(4);
-	.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
-	. = ALIGN(4);
-	__image_copy_end = .;
-	_end = .;
-
-	.bss :
-	{
-		. = ALIGN(4);
-		__bss_start = .;
-		*(.bss*)
-		. = ALIGN(4);
-		__bss_end = .;
-	} >.sdram
-}

arch/arm/cpu/arm1176/Makefile

@@ -1,34 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2008
-# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(CPU).o
-
-START	= start.o
-COBJS	= cpu.o
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################

arch/arm/cpu/arm1176/bcm2835/Makefile

@@ -1,37 +0,0 @@
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License
-# version 2 as published by the Free Software Foundation.
-#
-# This program is distributed in the hope that it will be useful, but
-# WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-SOBJS	:= lowlevel_init.o
-COBJS	:= init.o reset.o timer.o mbox.o
-
-SRCS	:= $(SOBJS:.o=.c) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################

arch/arm/cpu/arm1176/bcm2835/config.mk

@@ -1,19 +0,0 @@
-#
-# (C) Copyright 2012 Stephen Warren
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License
-# version 2 as published by the Free Software Foundation.
-#
-# This program is distributed in the hope that it will be useful, but
-# WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-
-# Don't attempt to override the target CPU/ABI options;
-# the Raspberry Pi toolchain does the right thing by default.
-PLATFORM_RELFLAGS := $(filter-out -msoft-float,$(PLATFORM_RELFLAGS))
-PLATFORM_CPPFLAGS := $(filter-out -march=armv5t,$(PLATFORM_CPPFLAGS))

arch/arm/cpu/arm1176/bcm2835/init.c

@@ -1,24 +0,0 @@
-/*
- * (C) Copyright 2012 Stephen Warren
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <common.h>
-
-int arch_cpu_init(void)
-{
-	icache_enable();
-
-	return 0;
-}

arch/arm/cpu/arm1176/bcm2835/lowlevel_init.S

@@ -1,19 +0,0 @@
-/*
- * (C) Copyright 2012 Stephen Warren
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-.globl lowlevel_init
-lowlevel_init:
-	mov	pc, lr

arch/arm/cpu/arm1176/bcm2835/mbox.c

@@ -1,153 +0,0 @@
-/*
- * (C) Copyright 2012 Stephen Warren
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/mbox.h>
-
-#define TIMEOUT (100 * 1000) /* 100mS in uS */
-
-int bcm2835_mbox_call_raw(u32 chan, u32 send, u32 *recv)
-{
-	struct bcm2835_mbox_regs *regs =
-		(struct bcm2835_mbox_regs *)BCM2835_MBOX_PHYSADDR;
-	ulong endtime = get_timer(0) + TIMEOUT;
-	u32 val;
-
-	debug("time: %lu timeout: %lu\n", get_timer(0), endtime);
-
-	if (send & BCM2835_CHAN_MASK) {
-		printf("mbox: Illegal mbox data 0x%08x\n", send);
-		return -1;
-	}
-
-	/* Drain any stale responses */
-
-	for (;;) {
-		val = readl(&regs->status);
-		if (val & BCM2835_MBOX_STATUS_RD_EMPTY)
-			break;
-		if (get_timer(0) >= endtime) {
-			printf("mbox: Timeout draining stale responses\n");
-			return -1;
-		}
-		val = readl(&regs->read);
-	}
-
-	/* Wait for space to send */
-
-	for (;;) {
-		val = readl(&regs->status);
-		if (!(val & BCM2835_MBOX_STATUS_WR_FULL))
-			break;
-		if (get_timer(0) >= endtime) {
-			printf("mbox: Timeout waiting for send space\n");
-			return -1;
-		}
-	}
-
-	/* Send the request */
-
-	val = BCM2835_MBOX_PACK(chan, send);
-	debug("mbox: TX raw: 0x%08x\n", val);
-	writel(val, &regs->write);
-
-	/* Wait for the response */
-
-	for (;;) {
-		val = readl(&regs->status);
-		if (!(val & BCM2835_MBOX_STATUS_RD_EMPTY))
-			break;
-		if (get_timer(0) >= endtime) {
-			printf("mbox: Timeout waiting for response\n");
-			return -1;
-		}
-	}
-
-	/* Read the response */
-
-	val = readl(&regs->read);
-	debug("mbox: RX raw: 0x%08x\n", val);
-
-	/* Validate the response */
-
-	if (BCM2835_MBOX_UNPACK_CHAN(val) != chan) {
-		printf("mbox: Response channel mismatch\n");
-		return -1;
-	}
-
-	*recv = BCM2835_MBOX_UNPACK_DATA(val);
-
-	return 0;
-}
-
-#ifdef DEBUG
-void dump_buf(struct bcm2835_mbox_hdr *buffer)
-{
-	u32 *p;
-	u32 words;
-	int i;
-
-	p = (u32 *)buffer;
-	words = buffer->buf_size / 4;
-	for (i = 0; i < words; i++)
-		printf("    0x%04x: 0x%08x\n", i * 4, p[i]);
-}
-#endif
-
-int bcm2835_mbox_call_prop(u32 chan, struct bcm2835_mbox_hdr *buffer)
-{
-	int ret;
-	u32 rbuffer;
-	struct bcm2835_mbox_tag_hdr *tag;
-	int tag_index;
-
-#ifdef DEBUG
-	printf("mbox: TX buffer\n");
-	dump_buf(buffer);
-#endif
-
-	ret = bcm2835_mbox_call_raw(chan, (u32)buffer, &rbuffer);
-	if (ret)
-		return ret;
-	if (rbuffer != (u32)buffer) {
-		printf("mbox: Response buffer mismatch\n");
-		return -1;
-	}
-
-#ifdef DEBUG
-	printf("mbox: RX buffer\n");
-	dump_buf(buffer);
-#endif
-
-	/* Validate overall response status */
-
-	if (buffer->code != BCM2835_MBOX_RESP_CODE_SUCCESS) {
-		printf("mbox: Header response code invalid\n");
-		return -1;
-	}
-
-	/* Validate each tag's response status */
-
-	tag = (void *)(buffer + 1);
-	tag_index = 0;
-	while (tag->tag) {
-		if (!(tag->val_len & BCM2835_MBOX_TAG_VAL_LEN_RESPONSE)) {
-			printf("mbox: Tag %d missing val_len response bit\n",
-				tag_index);
-			return -1;
-		}
-		/*
-		 * Clear the reponse bit so clients can just look right at the
-		 * length field without extra processing
-		 */
-		tag->val_len &= ~BCM2835_MBOX_TAG_VAL_LEN_RESPONSE;
-		tag = (void *)(((u8 *)tag) + sizeof(*tag) + tag->val_buf_size);
-		tag_index++;
-	}
-
-	return 0;
-}

arch/arm/cpu/arm1176/bcm2835/reset.c

@@ -1,35 +0,0 @@
-/*
- * (C) Copyright 2012 Stephen Warren
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/wdog.h>
-
-#define RESET_TIMEOUT 10
-
-void reset_cpu(ulong addr)
-{
-	struct bcm2835_wdog_regs *regs =
-		(struct bcm2835_wdog_regs *)BCM2835_WDOG_PHYSADDR;
-	uint32_t rstc;
-
-	rstc = readl(&regs->rstc);
-	rstc &= ~BCM2835_WDOG_RSTC_WRCFG_MASK;
-	rstc |= BCM2835_WDOG_RSTC_WRCFG_FULL_RESET;
-
-	writel(BCM2835_WDOG_PASSWORD | RESET_TIMEOUT, &regs->wdog);
-	writel(BCM2835_WDOG_PASSWORD | rstc, &regs->rstc);
-}

arch/arm/cpu/arm1176/bcm2835/timer.c

@@ -1,63 +0,0 @@
-/*
- * (C) Copyright 2012 Stephen Warren
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/timer.h>
-
-int timer_init(void)
-{
-	return 0;
-}
-
-ulong get_timer_us(ulong base)
-{
-	struct bcm2835_timer_regs *regs =
-		(struct bcm2835_timer_regs *)BCM2835_TIMER_PHYSADDR;
-
-	return readl(&regs->clo) - base;
-}
-
-ulong get_timer(ulong base)
-{
-	ulong us = get_timer_us(0);
-	us /= (1000000 / CONFIG_SYS_HZ);
-	us -= base;
-	return us;
-}
-
-unsigned long long get_ticks(void)
-{
-	return get_timer(0);
-}
-
-ulong get_tbclk(void)
-{
-	return CONFIG_SYS_HZ;
-}
-
-void __udelay(unsigned long usec)
-{
-	ulong endtime;
-	signed long diff;
-
-	endtime = get_timer_us(0) + usec;
-
-	do {
-		ulong now = get_timer_us(0);
-		diff = endtime - now;
-	} while (diff >= 0);
-}

arch/arm/cpu/arm1176/config.mk

@@ -1,17 +0,0 @@
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-# Make ARMv5 to allow more compilers to work, even though its v6.
-PLATFORM_CPPFLAGS += -march=armv5t
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# =========================================================================
-PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,\
-			$(call cc-option,-malignment-traps,))
-PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)

arch/arm/cpu/arm1176/cpu.c

@@ -1,51 +0,0 @@
-/*
- * (C) Copyright 2004 Texas Insturments
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * CPU specific code
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/system.h>
-
-static void cache_flush (void);
-
-int cleanup_before_linux (void)
-{
-	/*
-	 * this function is called just before we call linux
-	 * it prepares the processor for linux
-	 *
-	 * we turn off caches etc ...
-	 */
-
-	disable_interrupts ();
-
-	/* turn off I/D-cache */
-	icache_disable();
-	dcache_disable();
-	/* flush I/D-cache */
-	cache_flush();
-
-	return 0;
-}
-
-/* flush I/D-cache */
-static void cache_flush (void)
-{
-	/* invalidate both caches and flush btb */
-	asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (0));
-	/* mem barrier to sync things */
-	asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (0));
-}

arch/arm/cpu/arm1176/start.S

@@ -1,358 +0,0 @@
-/*
- *  armboot - Startup Code for ARM1176 CPU-core
- *
- * Copyright (c) 2007	Samsung Electronics
- *
- * Copyright (C) 2008
- * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * 2007-09-21 - Restructured codes by jsgood (jsgood.yang@samsung.com)
- * 2007-09-21 - Added MoviNAND and OneNAND boot codes by
- * jsgood (jsgood.yang@samsung.com)
- * Base codes by scsuh (sc.suh)
- */
-
-#include <asm-offsets.h>
-#include <config.h>
-#include <version.h>
-
-#ifndef CONFIG_SYS_PHY_UBOOT_BASE
-#define CONFIG_SYS_PHY_UBOOT_BASE	CONFIG_SYS_UBOOT_BASE
-#endif
-
-/*
- *************************************************************************
- *
- * Jump vector table as in table 3.1 in [1]
- *
- *************************************************************************
- */
-
-.globl _start
-_start: b	reset
-#ifndef CONFIG_SPL_BUILD
-	ldr	pc, _undefined_instruction
-	ldr	pc, _software_interrupt
-	ldr	pc, _prefetch_abort
-	ldr	pc, _data_abort
-	ldr	pc, _not_used
-	ldr	pc, _irq
-	ldr	pc, _fiq
-
-_undefined_instruction:
-	.word undefined_instruction
-_software_interrupt:
-	.word software_interrupt
-_prefetch_abort:
-	.word prefetch_abort
-_data_abort:
-	.word data_abort
-_not_used:
-	.word not_used
-_irq:
-	.word irq
-_fiq:
-	.word fiq
-_pad:
-	.word 0x12345678 /* now 16*4=64 */
-#else
-	. = _start + 64
-#endif
-
-.global _end_vect
-_end_vect:
-	.balignl 16,0xdeadbeef
-/*
- *************************************************************************
- *
- * Startup Code (reset vector)
- *
- * do important init only if we don't start from memory!
- * setup Memory and board specific bits prior to relocation.
- * relocate armboot to ram
- * setup stack
- *
- *************************************************************************
- */
-
-.globl _TEXT_BASE
-_TEXT_BASE:
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
-	.word	CONFIG_SPL_TEXT_BASE
-#else
-	.word	CONFIG_SYS_TEXT_BASE
-#endif
-
-/*
- * These are defined in the board-specific linker script.
- * Subtracting _start from them lets the linker put their
- * relative position in the executable instead of leaving
- * them null.
- */
-
-.globl _bss_start_ofs
-_bss_start_ofs:
-	.word __bss_start - _start
-
-.globl _bss_end_ofs
-_bss_end_ofs:
-	.word __bss_end - _start
-
-.globl _end_ofs
-_end_ofs:
-	.word _end - _start
-
-/* IRQ stack memory (calculated at run-time) + 8 bytes */
-.globl IRQ_STACK_START_IN
-IRQ_STACK_START_IN:
-	.word	0x0badc0de
-
-/*
- * the actual reset code
- */
-
-reset:
-	/*
-	 * set the cpu to SVC32 mode
-	 */
-	mrs	r0, cpsr
-	bic	r0, r0, #0x3f
-	orr	r0, r0, #0xd3
-	msr	cpsr, r0
-
-/*
- *************************************************************************
- *
- * CPU_init_critical registers
- *
- * setup important registers
- * setup memory timing
- *
- *************************************************************************
- */
-	/*
-	 * we do sys-critical inits only at reboot,
-	 * not when booting from ram!
-	 */
-cpu_init_crit:
-	/*
-	 * When booting from NAND - it has definitely been a reset, so, no need
-	 * to flush caches and disable the MMU
-	 */
-#ifndef CONFIG_SPL_BUILD
-	/*
-	 * flush v4 I/D caches
-	 */
-	mov	r0, #0
-	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
-	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */
-
-	/*
-	 * disable MMU stuff and caches
-	 */
-	mrc	p15, 0, r0, c1, c0, 0
-	bic	r0, r0, #0x00002300	@ clear bits 13, 9:8 (--V- --RS)
-	bic	r0, r0, #0x00000087	@ clear bits 7, 2:0 (B--- -CAM)
-	orr	r0, r0, #0x00000002	@ set bit 2 (A) Align
-	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
-
-	/* Prepare to disable the MMU */
-	adr	r2, mmu_disable_phys
-	sub	r2, r2, #(CONFIG_SYS_PHY_UBOOT_BASE - CONFIG_SYS_TEXT_BASE)
-	b	mmu_disable
-
-	.align 5
-	/* Run in a single cache-line */
-mmu_disable:
-	mcr	p15, 0, r0, c1, c0, 0
-	nop
-	nop
-	mov	pc, r2
-mmu_disable_phys:
-
-#ifdef CONFIG_DISABLE_TCM
-	/*
-	 * Disable the TCMs
-	 */
-	mrc	p15, 0, r0, c0, c0, 2	/* Return TCM details */
-	cmp	r0, #0
-	beq	skip_tcmdisable
-	mov	r1, #0
-	mov	r2, #1
-	tst	r0, r2
-	mcrne	p15, 0, r1, c9, c1, 1	/* Disable Instruction TCM if present*/
-	tst	r0, r2, LSL #16
-	mcrne	p15, 0, r1, c9, c1, 0	/* Disable Data TCM if present*/
-skip_tcmdisable:
-#endif
-#endif
-
-#ifdef CONFIG_PERIPORT_REMAP
-	/* Peri port setup */
-	ldr	r0, =CONFIG_PERIPORT_BASE
-	orr	r0, r0, #CONFIG_PERIPORT_SIZE
-	mcr	p15,0,r0,c15,c2,4
-#endif
-
-	/*
-	 * Go setup Memory and board specific bits prior to relocation.
-	 */
-	bl	lowlevel_init		/* go setup pll,mux,memory */
-
-	bl	_main
-
-/*------------------------------------------------------------------------------*/
-
-	.globl	c_runtime_cpu_setup
-c_runtime_cpu_setup:
-
-	mov	pc, lr
-
-#ifndef CONFIG_SPL_BUILD
-/*
- *************************************************************************
- *
- * Interrupt handling
- *
- *************************************************************************
- */
-@
-@ IRQ stack frame.
-@
-#define S_FRAME_SIZE	72
-
-#define S_OLD_R0	68
-#define S_PSR		64
-#define S_PC		60
-#define S_LR		56
-#define S_SP		52
-
-#define S_IP		48
-#define S_FP		44
-#define S_R10		40
-#define S_R9		36
-#define S_R8		32
-#define S_R7		28
-#define S_R6		24
-#define S_R5		20
-#define S_R4		16
-#define S_R3		12
-#define S_R2		8
-#define S_R1		4
-#define S_R0		0
-
-#define MODE_SVC 0x13
-#define I_BIT	 0x80
-
-/*
- * use bad_save_user_regs for abort/prefetch/undef/swi ...
- */
-
-	.macro	bad_save_user_regs
-	/* carve out a frame on current user stack */
-	sub	sp, sp, #S_FRAME_SIZE
-	/* Save user registers (now in svc mode) r0-r12 */
-	stmia	sp, {r0 - r12}
-
-	ldr	r2, IRQ_STACK_START_IN
-	/* get values for "aborted" pc and cpsr (into parm regs) */
-	ldmia	r2, {r2 - r3}
-	/* grab pointer to old stack */
-	add	r0, sp, #S_FRAME_SIZE
-
-	add	r5, sp, #S_SP
-	mov	r1, lr
-	/* save sp_SVC, lr_SVC, pc, cpsr */
-	stmia	r5, {r0 - r3}
-	/* save current stack into r0 (param register) */
-	mov	r0, sp
-	.endm
-
-	.macro get_bad_stack
-	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack
-
-	/* save caller lr in position 0 of saved stack */
-	str	lr, [r13]
-	/* get the spsr */
-	mrs	lr, spsr
-	/* save spsr in position 1 of saved stack */
-	str	lr, [r13, #4]
-
-	/* prepare SVC-Mode */
-	mov	r13, #MODE_SVC
-	@ msr	spsr_c, r13
-	/* switch modes, make sure moves will execute */
-	msr	spsr, r13
-	/* capture return pc */
-	mov	lr, pc
-	/* jump to next instruction & switch modes. */
-	movs	pc, lr
-	.endm
-
-	.macro get_bad_stack_swi
-	/* space on current stack for scratch reg. */
-	sub	r13, r13, #4
-	/* save R0's value. */
-	str	r0, [r13]
-	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack
-	/* save caller lr in position 0 of saved stack */
-	str	lr, [r0]
-	/* get the spsr */
-	mrs	lr, spsr
-	/* save spsr in position 1 of saved stack */
-	str	lr, [r0, #4]
-	/* restore lr */
-	ldr	lr, [r0]
-	/* restore r0 */
-	ldr	r0, [r13]
-	/* pop stack entry */
-	add	r13, r13, #4
-	.endm
-
-/*
- * exception handlers
- */
-	.align	5
-undefined_instruction:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_undefined_instruction
-
-	.align	5
-software_interrupt:
-	get_bad_stack_swi
-	bad_save_user_regs
-	bl	do_software_interrupt
-
-	.align	5
-prefetch_abort:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_prefetch_abort
-
-	.align	5
-data_abort:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_data_abort
-
-	.align	5
-not_used:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_not_used
-
-	.align	5
-irq:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_irq
-
-	.align	5
-fiq:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_fiq
-#endif /* CONFIG_SPL_BUILD */

arch/arm/cpu/arm1176/tnetv107x/Makefile

@@ -1,29 +0,0 @@
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS	+= aemif.o clock.o init.o mux.o timer.o
-SOBJS	+= lowlevel_init.o
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-
-OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################

arch/arm/cpu/arm1176/tnetv107x/aemif.c

@@ -1,78 +0,0 @@
-/*
- * TNETV107X: Asynchronous EMIF Configuration
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/mux.h>
-
-#define ASYNC_EMIF_BASE			TNETV107X_ASYNC_EMIF_CNTRL_BASE
-#define ASYNC_EMIF_CONFIG(cs)		(ASYNC_EMIF_BASE+0x10+(cs)*4)
-#define ASYNC_EMIF_ONENAND_CONTROL	(ASYNC_EMIF_BASE+0x5c)
-#define ASYNC_EMIF_NAND_CONTROL		(ASYNC_EMIF_BASE+0x60)
-#define ASYNC_EMIF_WAITCYCLE_CONFIG	(ASYNC_EMIF_BASE+0x4)
-
-#define CONFIG_SELECT_STROBE(v)		((v) ? 1 << 31 : 0)
-#define CONFIG_EXTEND_WAIT(v)		((v) ? 1 << 30 : 0)
-#define CONFIG_WR_SETUP(v)		(((v) & 0x0f) << 26)
-#define CONFIG_WR_STROBE(v)		(((v) & 0x3f) << 20)
-#define CONFIG_WR_HOLD(v)		(((v) & 0x07) << 17)
-#define CONFIG_RD_SETUP(v)		(((v) & 0x0f) << 13)
-#define CONFIG_RD_STROBE(v)		(((v) & 0x3f) << 7)
-#define CONFIG_RD_HOLD(v)		(((v) & 0x07) << 4)
-#define CONFIG_TURN_AROUND(v)		(((v) & 0x03) << 2)
-#define CONFIG_WIDTH(v)			(((v) & 0x03) << 0)
-
-#define NUM_CS				4
-
-#define set_config_field(reg, field, val)			\
-	do {							\
-		if (val != -1) {				\
-			reg &= ~CONFIG_##field(0xffffffff);	\
-			reg |=	CONFIG_##field(val);		\
-		}						\
-	} while (0)
-
-void configure_async_emif(int cs, struct async_emif_config *cfg)
-{
-	unsigned long tmp;
-
-	if (cfg->mode == ASYNC_EMIF_MODE_NAND) {
-		tmp = __raw_readl(ASYNC_EMIF_NAND_CONTROL);
-		tmp |= (1 << cs);
-		__raw_writel(tmp, ASYNC_EMIF_NAND_CONTROL);
-
-	} else if (cfg->mode == ASYNC_EMIF_MODE_ONENAND) {
-		tmp = __raw_readl(ASYNC_EMIF_ONENAND_CONTROL);
-		tmp |= (1 << cs);
-		__raw_writel(tmp, ASYNC_EMIF_ONENAND_CONTROL);
-	}
-
-	tmp = __raw_readl(ASYNC_EMIF_CONFIG(cs));
-
-	set_config_field(tmp, SELECT_STROBE,	cfg->select_strobe);
-	set_config_field(tmp, EXTEND_WAIT,	cfg->extend_wait);
-	set_config_field(tmp, WR_SETUP,		cfg->wr_setup);
-	set_config_field(tmp, WR_STROBE,	cfg->wr_strobe);
-	set_config_field(tmp, WR_HOLD,		cfg->wr_hold);
-	set_config_field(tmp, RD_SETUP,		cfg->rd_setup);
-	set_config_field(tmp, RD_STROBE,	cfg->rd_strobe);
-	set_config_field(tmp, RD_HOLD,		cfg->rd_hold);
-	set_config_field(tmp, TURN_AROUND,	cfg->turn_around);
-	set_config_field(tmp, WIDTH,		cfg->width);
-
-	__raw_writel(tmp, ASYNC_EMIF_CONFIG(cs));
-}
-
-void init_async_emif(int num_cs, struct async_emif_config *config)
-{
-	int cs;
-
-	clk_enable(TNETV107X_LPSC_AEMIF);
-
-	for (cs = 0; cs < num_cs; cs++)
-		configure_async_emif(cs, config + cs);
-}

arch/arm/cpu/arm1176/tnetv107x/clock.c

@@ -1,432 +0,0 @@
-/*
- * TNETV107X: Clock management APIs
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm-generic/errno.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-#include <asm/arch/clock.h>
-
-#define CLOCK_BASE		TNETV107X_CLOCK_CONTROL_BASE
-#define PSC_BASE		TNETV107X_PSC_BASE
-
-#define BIT(x)			(1 << (x))
-
-#define MAX_PREDIV		64
-#define MAX_POSTDIV		8
-#define MAX_MULT		512
-#define MAX_DIV			(MAX_PREDIV * MAX_POSTDIV)
-
-/* LPSC registers */
-#define PSC_PTCMD		0x120
-#define PSC_PTSTAT		0x128
-#define PSC_MDSTAT(n)		(0x800 + (n) * 4)
-#define PSC_MDCTL(n)		(0xA00 + (n) * 4)
-
-#define PSC_MDCTL_LRSTZ		BIT(8)
-
-#define psc_reg_read(reg)	__raw_readl((u32 *)(PSC_BASE + (reg)))
-#define psc_reg_write(reg, val)	__raw_writel(val, (u32 *)(PSC_BASE + (reg)))
-
-/* SSPLL registers */
-struct sspll_regs {
-	u32	modes;
-	u32	postdiv;
-	u32	prediv;
-	u32	mult_factor;
-	u32	divider_range;
-	u32	bw_divider;
-	u32	spr_amount;
-	u32	spr_rate_div;
-	u32	diag;
-};
-
-/* SSPLL base addresses */
-static struct sspll_regs *sspll_regs[] = {
-	(struct sspll_regs *)(CLOCK_BASE + 0x040),
-	(struct sspll_regs *)(CLOCK_BASE + 0x080),
-	(struct sspll_regs *)(CLOCK_BASE + 0x0c0),
-};
-
-#define sspll_reg(pll, reg)		(&(sspll_regs[pll]->reg))
-#define sspll_reg_read(pll, reg)	__raw_readl(sspll_reg(pll, reg))
-#define sspll_reg_write(pll, reg, val)	__raw_writel(val, sspll_reg(pll, reg))
-
-
-/* PLL Control Registers */
-struct pllctl_regs {
-	u32	ctl;		/* 00 */
-	u32	ocsel;		/* 04 */
-	u32	secctl;		/* 08 */
-	u32	__pad0;
-	u32	mult;		/* 10 */
-	u32	prediv;		/* 14 */
-	u32	div1;		/* 18 */
-	u32	div2;		/* 1c */
-	u32	div3;		/* 20 */
-	u32	oscdiv1;	/* 24 */
-	u32	postdiv;	/* 28 */
-	u32	bpdiv;		/* 2c */
-	u32	wakeup;		/* 30 */
-	u32	__pad1;
-	u32	cmd;		/* 38 */
-	u32	stat;		/* 3c */
-	u32	alnctl;		/* 40 */
-	u32	dchange;	/* 44 */
-	u32	cken;		/* 48 */
-	u32	ckstat;		/* 4c */
-	u32	systat;		/* 50 */
-	u32	ckctl;		/* 54 */
-	u32	__pad2[2];
-	u32	div4;		/* 60 */
-	u32	div5;		/* 64 */
-	u32	div6;		/* 68 */
-	u32	div7;		/* 6c */
-	u32	div8;		/* 70 */
-};
-
-struct lpsc_map {
-	int	pll, div;
-};
-
-static struct pllctl_regs *pllctl_regs[] = {
-	(struct pllctl_regs *)(CLOCK_BASE + 0x700),
-	(struct pllctl_regs *)(CLOCK_BASE + 0x300),
-	(struct pllctl_regs *)(CLOCK_BASE + 0x500),
-};
-
-#define pllctl_reg(pll, reg)		(&(pllctl_regs[pll]->reg))
-#define pllctl_reg_read(pll, reg)	__raw_readl(pllctl_reg(pll, reg))
-#define pllctl_reg_write(pll, reg, val)	__raw_writel(val, pllctl_reg(pll, reg))
-
-#define pllctl_reg_rmw(pll, reg, mask, val)			\
-	pllctl_reg_write(pll, reg,				\
-		(pllctl_reg_read(pll, reg) & ~(mask)) | val)
-
-#define pllctl_reg_setbits(pll, reg, mask)			\
-	pllctl_reg_rmw(pll, reg, 0, mask)
-
-#define pllctl_reg_clrbits(pll, reg, mask)			\
-	pllctl_reg_rmw(pll, reg, mask, 0)
-
-/* PLLCTL Bits */
-#define PLLCTL_CLKMODE		BIT(8)
-#define PLLCTL_PLLSELB		BIT(7)
-#define PLLCTL_PLLENSRC		BIT(5)
-#define PLLCTL_PLLDIS		BIT(4)
-#define PLLCTL_PLLRST		BIT(3)
-#define PLLCTL_PLLPWRDN		BIT(1)
-#define PLLCTL_PLLEN		BIT(0)
-
-#define PLLDIV_ENABLE		BIT(15)
-
-static int pll_div_offset[] = {
-#define div_offset(reg)	offsetof(struct pllctl_regs, reg)
-	div_offset(div1), div_offset(div2), div_offset(div3),
-	div_offset(div4), div_offset(div5), div_offset(div6),
-	div_offset(div7), div_offset(div8),
-};
-
-static unsigned long pll_bypass_mask[] = { 1, 4, 2 };
-static unsigned long pll_div_mask[] = { 0x01ff, 0x00ff, 0x00ff };
-
-/* Mappings from PLL+DIV to subsystem clocks */
-#define sys_arm1176_clk		{SYS_PLL, 0}
-#define sys_dsp_clk		{SYS_PLL, 1}
-#define sys_ddr_clk		{SYS_PLL, 2}
-#define sys_full_clk		{SYS_PLL, 3}
-#define sys_lcd_clk		{SYS_PLL, 4}
-#define sys_vlynq_ref_clk	{SYS_PLL, 5}
-#define sys_tsc_clk		{SYS_PLL, 6}
-#define sys_half_clk		{SYS_PLL, 7}
-
-#define eth_clk_5		{ETH_PLL, 0}
-#define eth_clk_50		{ETH_PLL, 1}
-#define eth_clk_125		{ETH_PLL, 2}
-#define eth_clk_250		{ETH_PLL, 3}
-#define eth_clk_25		{ETH_PLL, 4}
-
-#define tdm_clk			{TDM_PLL, 0}
-#define tdm_extra_clk		{TDM_PLL, 1}
-#define tdm1_clk		{TDM_PLL, 2}
-
-static const struct lpsc_map lpsc_clk_map[] = {
-	[TNETV107X_LPSC_ARM]			= sys_arm1176_clk,
-	[TNETV107X_LPSC_GEM]			= sys_dsp_clk,
-	[TNETV107X_LPSC_DDR2_PHY]		= sys_ddr_clk,
-	[TNETV107X_LPSC_TPCC]			= sys_full_clk,
-	[TNETV107X_LPSC_TPTC0]			= sys_full_clk,
-	[TNETV107X_LPSC_TPTC1]			= sys_full_clk,
-	[TNETV107X_LPSC_RAM]			= sys_full_clk,
-	[TNETV107X_LPSC_MBX_LITE]		= sys_arm1176_clk,
-	[TNETV107X_LPSC_LCD]			= sys_lcd_clk,
-	[TNETV107X_LPSC_ETHSS]			= eth_clk_125,
-	[TNETV107X_LPSC_AEMIF]			= sys_full_clk,
-	[TNETV107X_LPSC_CHIP_CFG]		= sys_half_clk,
-	[TNETV107X_LPSC_TSC]			= sys_tsc_clk,
-	[TNETV107X_LPSC_ROM]			= sys_half_clk,
-	[TNETV107X_LPSC_UART2]			= sys_half_clk,
-	[TNETV107X_LPSC_PKTSEC]			= sys_half_clk,
-	[TNETV107X_LPSC_SECCTL]			= sys_half_clk,
-	[TNETV107X_LPSC_KEYMGR]			= sys_half_clk,
-	[TNETV107X_LPSC_KEYPAD]			= sys_half_clk,
-	[TNETV107X_LPSC_GPIO]			= sys_half_clk,
-	[TNETV107X_LPSC_MDIO]			= sys_half_clk,
-	[TNETV107X_LPSC_SDIO0]			= sys_half_clk,
-	[TNETV107X_LPSC_UART0]			= sys_half_clk,
-	[TNETV107X_LPSC_UART1]			= sys_half_clk,
-	[TNETV107X_LPSC_TIMER0]			= sys_half_clk,
-	[TNETV107X_LPSC_TIMER1]			= sys_half_clk,
-	[TNETV107X_LPSC_WDT_ARM]		= sys_half_clk,
-	[TNETV107X_LPSC_WDT_DSP]		= sys_half_clk,
-	[TNETV107X_LPSC_SSP]			= sys_half_clk,
-	[TNETV107X_LPSC_TDM0]			= tdm_clk,
-	[TNETV107X_LPSC_VLYNQ]			= sys_vlynq_ref_clk,
-	[TNETV107X_LPSC_MCDMA]			= sys_half_clk,
-	[TNETV107X_LPSC_USB0]			= sys_half_clk,
-	[TNETV107X_LPSC_TDM1]			= tdm1_clk,
-	[TNETV107X_LPSC_DEBUGSS]		= sys_half_clk,
-	[TNETV107X_LPSC_ETHSS_RGMII]		= eth_clk_250,
-	[TNETV107X_LPSC_SYSTEM]			= sys_half_clk,
-	[TNETV107X_LPSC_IMCOP]			= sys_dsp_clk,
-	[TNETV107X_LPSC_SPARE]			= sys_half_clk,
-	[TNETV107X_LPSC_SDIO1]			= sys_half_clk,
-	[TNETV107X_LPSC_USB1]			= sys_half_clk,
-	[TNETV107X_LPSC_USBSS]			= sys_half_clk,
-	[TNETV107X_LPSC_DDR2_EMIF1_VRST]	= sys_ddr_clk,
-	[TNETV107X_LPSC_DDR2_EMIF2_VCTL_RST]	= sys_ddr_clk,
-};
-
-static const unsigned long pll_ext_freq[] = {
-	[SYS_PLL] = CONFIG_PLL_SYS_EXT_FREQ,
-	[ETH_PLL] = CONFIG_PLL_ETH_EXT_FREQ,
-	[TDM_PLL] = CONFIG_PLL_TDM_EXT_FREQ,
-};
-
-static unsigned long pll_freq_get(int pll)
-{
-	unsigned long mult = 1, prediv = 1, postdiv = 1;
-	unsigned long ref = CONFIG_SYS_INT_OSC_FREQ;
-	unsigned long ret;
-	u32 bypass;
-
-	bypass = __raw_readl((u32 *)(CLOCK_BASE));
-	if (!(bypass & pll_bypass_mask[pll])) {
-		mult	= sspll_reg_read(pll, mult_factor);
-		prediv	= sspll_reg_read(pll, prediv) + 1;
-		postdiv	= sspll_reg_read(pll, postdiv) + 1;
-	}
-
-	if (pllctl_reg_read(pll, ctl) & PLLCTL_CLKMODE)
-		ref = pll_ext_freq[pll];
-
-	if (!(pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN))
-		return ref;
-
-	ret = (unsigned long)(ref + ((unsigned long long)ref * mult) / 256);
-	ret /= (prediv * postdiv);
-
-	return ret;
-}
-
-static unsigned long __pll_div_freq_get(int pll, unsigned int fpll,
-					int div)
-{
-	int divider = 1;
-	unsigned long divreg;
-
-	divreg = __raw_readl((void *)pllctl_regs[pll] + pll_div_offset[div]);
-
-	if (divreg & PLLDIV_ENABLE)
-		divider = (divreg & pll_div_mask[pll]) + 1;
-
-	return fpll / divider;
-}
-
-static unsigned long pll_div_freq_get(int pll, int div)
-{
-	unsigned int fpll = pll_freq_get(pll);
-
-	return __pll_div_freq_get(pll, fpll, div);
-}
-
-static void __pll_div_freq_set(int pll, unsigned int fpll, int div,
-			       unsigned long hz)
-{
-	int divider = (fpll / hz - 1);
-
-	divider &= pll_div_mask[pll];
-	divider |= PLLDIV_ENABLE;
-
-	__raw_writel(divider, (void *)pllctl_regs[pll] + pll_div_offset[div]);
-	pllctl_reg_setbits(pll, alnctl, (1 << div));
-	pllctl_reg_setbits(pll, dchange, (1 << div));
-}
-
-static unsigned long pll_div_freq_set(int pll, int div, unsigned long hz)
-{
-	unsigned int fpll = pll_freq_get(pll);
-
-	__pll_div_freq_set(pll, fpll, div, hz);
-
-	pllctl_reg_write(pll, cmd, 1);
-
-	/* Wait until new divider takes effect */
-	while (pllctl_reg_read(pll, stat) & 0x01);
-
-	return __pll_div_freq_get(pll, fpll, div);
-}
-
-unsigned long clk_get_rate(unsigned int clk)
-{
-	return pll_div_freq_get(lpsc_clk_map[clk].pll, lpsc_clk_map[clk].div);
-}
-
-unsigned long clk_round_rate(unsigned int clk, unsigned long hz)
-{
-	unsigned long fpll, divider, pll;
-
-	pll = lpsc_clk_map[clk].pll;
-	fpll = pll_freq_get(pll);
-	divider = (fpll / hz - 1);
-	divider &= pll_div_mask[pll];
-
-	return fpll / (divider + 1);
-}
-
-int clk_set_rate(unsigned int clk, unsigned long _hz)
-{
-	unsigned long hz;
-
-	hz = clk_round_rate(clk, _hz);
-	if (hz != _hz)
-		return -EINVAL;	/* Cannot set to target freq */
-
-	pll_div_freq_set(lpsc_clk_map[clk].pll, lpsc_clk_map[clk].div, hz);
-	return 0;
-}
-
-void lpsc_control(int mod, unsigned long state, int lrstz)
-{
-	u32 mdctl;
-
-	mdctl = psc_reg_read(PSC_MDCTL(mod));
-	mdctl &= ~0x1f;
-	mdctl |= state;
-
-	if (lrstz == 0)
-		mdctl &= ~PSC_MDCTL_LRSTZ;
-	else if (lrstz == 1)
-		mdctl |= PSC_MDCTL_LRSTZ;
-
-	psc_reg_write(PSC_MDCTL(mod), mdctl);
-
-	psc_reg_write(PSC_PTCMD, 1);
-
-	/* wait for power domain transition to end */
-	while (psc_reg_read(PSC_PTSTAT) & 1);
-
-	/* Wait for module state change */
-	while ((psc_reg_read(PSC_MDSTAT(mod)) & 0x1f) != state);
-}
-
-int lpsc_status(unsigned int id)
-{
-	return psc_reg_read(PSC_MDSTAT(id)) & 0x1f;
-}
-
-static void init_pll(const struct pll_init_data *data)
-{
-	unsigned long fpll;
-	unsigned long best_pre = 0, best_post = 0, best_mult = 0;
-	unsigned long div, prediv, postdiv, mult;
-	unsigned long delta, actual;
-	long best_delta = -1;
-	int i;
-	u32 tmp;
-
-	if (data->pll == SYS_PLL)
-		return; /* cannot reconfigure system pll on the fly */
-
-	tmp = pllctl_reg_read(data->pll, ctl);
-	if (data->internal_osc) {
-		tmp &= ~PLLCTL_CLKMODE;
-		fpll = CONFIG_SYS_INT_OSC_FREQ;
-	} else {
-		tmp |= PLLCTL_CLKMODE;
-		fpll = pll_ext_freq[data->pll];
-	}
-	pllctl_reg_write(data->pll, ctl, tmp);
-
-	mult = data->pll_freq / fpll;
-	for (mult = MAX(mult, 1); mult <= MAX_MULT; mult++) {
-		div = (fpll * mult) / data->pll_freq;
-		if (div < 1 || div > MAX_DIV)
-			continue;
-
-		for (postdiv = 1; postdiv <= min(div, MAX_POSTDIV); postdiv++) {
-			prediv = div / postdiv;
-			if (prediv < 1 || prediv > MAX_PREDIV)
-				continue;
-
-			actual = (fpll / prediv) * (mult / postdiv);
-			delta = (actual - data->pll_freq);
-			if (delta < 0)
-				delta = -delta;
-			if ((delta < best_delta) || (best_delta == -1)) {
-				best_delta = delta;
-				best_mult = mult;
-				best_pre = prediv;
-				best_post = postdiv;
-				if (delta == 0)
-					goto done;
-			}
-		}
-	}
-done:
-
-	if (best_delta == -1) {
-		printf("pll cannot derive %lu from %lu\n",
-				data->pll_freq, fpll);
-		return;
-	}
-
-	fpll = fpll * best_mult;
-	fpll /= best_pre * best_post;
-
-	pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLENSRC);
-	pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN);
-
-	pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLRST);
-
-	pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLPWRDN);
-	pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLDIS);
-
-	sspll_reg_write(data->pll, mult_factor,	(best_mult - 1) << 8);
-	sspll_reg_write(data->pll, prediv,	best_pre - 1);
-	sspll_reg_write(data->pll, postdiv,	best_post - 1);
-
-	for (i = 0; i < 10; i++)
-		if (data->div_freq[i])
-			__pll_div_freq_set(data->pll, fpll, i,
-					   data->div_freq[i]);
-
-	pllctl_reg_write(data->pll, cmd, 1);
-
-	/* Wait until pll "go" operation completes */
-	while (pllctl_reg_read(data->pll, stat) & 0x01);
-
-	pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLRST);
-	pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN);
-}
-
-void init_plls(int num_pll, struct pll_init_data *config)
-{
-	int i;
-
-	for (i = 0; i < num_pll; i++)
-		init_pll(&config[i]);
-}

arch/arm/cpu/arm1176/tnetv107x/init.c

@@ -1,22 +0,0 @@
-/*
- * TNETV107X: Architecture initialization
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-
-void chip_configuration_unlock(void)
-{
-       __raw_writel(TNETV107X_KICK0_MAGIC, TNETV107X_KICK0);
-       __raw_writel(TNETV107X_KICK1_MAGIC, TNETV107X_KICK1);
-}
-
-int arch_cpu_init(void)
-{
-       icache_enable();
-       chip_configuration_unlock();
-
-       return 0;
-}

arch/arm/cpu/arm1176/tnetv107x/lowlevel_init.S

@@ -1,10 +0,0 @@
-/*
- * TNETV107X: Low-level pre-relocation initialization
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-.globl lowlevel_init
-lowlevel_init:
-	/* nothing for now, maybe needed for more exotic boot modes */
-	mov	pc, lr

arch/arm/cpu/arm1176/tnetv107x/mux.c

@@ -1,319 +0,0 @@
-/*
- * TNETV107X: Pinmux configuration
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/mux.h>
-
-#define MUX_MODE_1		0x00
-#define MUX_MODE_2		0x04
-#define MUX_MODE_3		0x0c
-#define MUX_MODE_4		0x1c
-
-#define MUX_DEBUG		0
-
-static const struct pin_config pin_table[] = {
-	/*		  reg	shift	mode	*/
-	TNETV107X_MUX_CFG(0,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(0,	0,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(0,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(0,	5,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(0,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(0,	10,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(0,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(0,	15,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(0,	20,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(0,	20,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(0,	25,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(0,	25,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(1,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(1,	0,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(1,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(1,	5,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(1,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(1,	10,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(1,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(1,	15,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(1,	20,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(1,	20,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(1,	25,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(1,	25,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(2,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(2,	0,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(2,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(2,	5,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(2,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(2,	10,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(2,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(2,	15,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(2,	20,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(2,	20,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(2,	25,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(2,	25,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(3,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(3,	0,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(3,	0,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(3,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(3,	5,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(3,	5,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(3,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(3,	10,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(3,	10,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(3,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(3,	15,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(3,	15,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(3,	20,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(3,	20,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(3,	20,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(3,	25,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(3,	25,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(3,	25,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(4,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(4,	0,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(4,	0,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(4,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(4,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(4,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(4,	15,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(4,	20,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(4,	20,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(4,	25,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(4,	25,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(5,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(5,	0,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(5,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(5,	5,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(5,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(5,	10,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(5,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(5,	15,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(5,	20,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(5,	20,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(5,	25,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(5,	25,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(6,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(6,	0,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(6,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(6,	5,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(6,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(6,	10,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(6,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(6,	15,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(6,	20,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(6,	20,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(6,	25,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(6,	25,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(7,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(7,	0,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(7,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(7,	5,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(7,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(7,	10,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(7,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(7,	15,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(7,	20,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(7,	20,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(7,	25,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(7,	25,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(8,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(8,	0,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(8,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(8,	5,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(8,	5,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(8,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(8,	10,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(9,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(9,	0,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(9,	0,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(9,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(9,	5,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(9,	5,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(9,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(9,	10,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(9,	10,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(9,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(9,	15,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(9,	15,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(9,	20,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(9,	20,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(9,	20,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(10,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(10,	0,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(10,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(10,	5,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(10,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(10,	10,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(10,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(10,	15,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(10,	20,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(10,	20,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(10,	25,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(10,	25,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(11,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(11,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(12,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(12,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(12,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(12,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(12,	20,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(12,	25,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(13,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(13,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(13,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(13,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(14,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(14,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(14,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(14,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(14,	20,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(14,	25,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(15,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(15,	0,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(15,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(15,	5,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(15,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(15,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(15,	20,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(15,	25,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(16,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(16,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(16,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(16,	10,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(16,	10,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(16,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(16,	15,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(17,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(17,	0,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(17,	0,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(17,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(17,	5,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(17,	5,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(17,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(17,	10,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(17,	10,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(17,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(17,	15,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(17,	15,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(18,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(18,	0,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(18,	0,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(18,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(18,	5,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(18,	5,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(18,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(18,	10,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(18,	10,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(18,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(18,	15,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(18,	15,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(19,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(19,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(19,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(19,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(19,	20,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(19,	25,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(20,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(20,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(20,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(20,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(20,	15,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(20,	20,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(20,	25,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(21,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(21,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(21,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(21,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(21,	20,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(21,	25,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(22,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(22,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(22,	5,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(22,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(22,	10,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(22,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(22,	15,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(22,	15,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(22,	20,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(22,	20,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(22,	25,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(22,	25,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(23,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(23,	0,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(23,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(23,	5,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(23,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(23,	10,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(24,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(24,	0,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(24,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(24,	5,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(24,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(24,	10,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(24,	10,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(24,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(24,	15,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(24,	15,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(24,	20,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(24,	20,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(24,	25,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(24,	25,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(25,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(25,	0,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(25,	0,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(25,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(25,	5,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(25,	5,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(25,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(25,	10,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(25,	10,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(25,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(25,	15,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(25,	15,	MUX_MODE_3),
-	TNETV107X_MUX_CFG(25,	15,	MUX_MODE_4),
-	TNETV107X_MUX_CFG(26,	0,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(26,	5,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(26,	10,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(26,	10,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(26,	15,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(26,	15,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(26,	20,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(26,	20,	MUX_MODE_2),
-	TNETV107X_MUX_CFG(26,	25,	MUX_MODE_1),
-	TNETV107X_MUX_CFG(26,	25,	MUX_MODE_2),
-};
-
-const int pin_table_size = sizeof(pin_table) / sizeof(pin_table[0]);
-
-int mux_select_pin(short index)
-{
-	const struct pin_config *cfg;
-	unsigned long mask, mode, reg;
-
-	if (index >= pin_table_size)
-		return 0;
-
-	cfg = &pin_table[index];
-
-	mask = 0x1f << cfg->mask_offset;
-	mode = cfg->mode << cfg->mask_offset;
-
-	reg = __raw_readl(TNETV107X_PINMUX(cfg->reg_index));
-	reg = (reg & ~mask) | mode;
-	__raw_writel(reg, TNETV107X_PINMUX(cfg->reg_index));
-
-	return 1;
-}
-
-int mux_select_pins(const short *pins)
-{
-	int i, ret = 1;
-
-	for (i = 0; pins[i] >= 0; i++)
-		ret &= mux_select_pin(pins[i]);
-
-	return ret;
-}

arch/arm/cpu/arm1176/tnetv107x/timer.c

@@ -1,93 +0,0 @@
-/*
- * TNETV107X: Timer implementation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-
-struct timer_regs {
-	u_int32_t pid12;
-	u_int32_t pad[3];
-	u_int32_t tim12;
-	u_int32_t tim34;
-	u_int32_t prd12;
-	u_int32_t prd34;
-	u_int32_t tcr;
-	u_int32_t tgcr;
-	u_int32_t wdtcr;
-};
-
-#define regs ((struct timer_regs *)CONFIG_SYS_TIMERBASE)
-
-#define TIMER_LOAD_VAL	(CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ)
-#define TIM_CLK_DIV	16
-
-static ulong timestamp;
-static ulong lastinc;
-
-int timer_init(void)
-{
-	clk_enable(TNETV107X_LPSC_TIMER0);
-
-	lastinc = timestamp = 0;
-
-	/* We are using timer34 in unchained 32-bit mode, full speed */
-	__raw_writel(0x0, &regs->tcr);
-	__raw_writel(0x0, &regs->tgcr);
-	__raw_writel(0x06 | ((TIM_CLK_DIV - 1) << 8), &regs->tgcr);
-	__raw_writel(0x0, &regs->tim34);
-	__raw_writel(TIMER_LOAD_VAL, &regs->prd34);
-	__raw_writel(2 << 22, &regs->tcr);
-
-	return 0;
-}
-
-static ulong get_timer_raw(void)
-{
-	ulong now = __raw_readl(&regs->tim34);
-
-	if (now >= lastinc)
-		timestamp += now - lastinc;
-	else
-		timestamp += now + TIMER_LOAD_VAL - lastinc;
-
-	lastinc = now;
-
-	return timestamp;
-}
-
-ulong get_timer(ulong base)
-{
-	return (get_timer_raw() / (TIMER_LOAD_VAL / TIM_CLK_DIV)) - base;
-}
-
-unsigned long long get_ticks(void)
-{
-	return get_timer(0);
-}
-
-void __udelay(unsigned long usec)
-{
-	ulong tmo;
-	ulong endtime;
-	signed long diff;
-
-	tmo = CONFIG_SYS_HZ_CLOCK / 1000;
-	tmo *= usec;
-	tmo /= (1000 * TIM_CLK_DIV);
-
-	endtime = get_timer_raw() + tmo;
-
-	do {
-		ulong now = get_timer_raw();
-		diff = endtime - now;
-	} while (diff >= 0);
-}
-
-ulong get_tbclk(void)
-{
-	return CONFIG_SYS_HZ;
-}

arch/arm/cpu/arm720t/Makefile

@@ -1,31 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(CPU).o
-
-START	= start.o
-COBJS	= interrupts.o cpu.o
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################

arch/arm/cpu/arm720t/config.mk

@@ -1,17 +0,0 @@
-#
-# (C) Copyright 2002
-# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
-# Marius Groeger <mgroeger@sysgo.de>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-PLATFORM_CPPFLAGS += -march=armv4 -mtune=arm7tdmi
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# =========================================================================
-PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,\
-			$(call cc-option,-malignment-traps,))
-PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)

arch/arm/cpu/arm720t/cpu.c

@@ -1,22 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * cleanup_before_linux() - Prepare the CPU to jump to Linux
- *
- * This function is called just before we call Linux, it
- * prepares the processor for linux
- */
-int cleanup_before_linux(void)
-{
-	return 0;
-}

arch/arm/cpu/arm720t/interrupts.c

@@ -1,33 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-
-#ifdef CONFIG_USE_IRQ
-void do_irq (struct pt_regs *pt_regs)
-{
-}
-#endif
-
-#if defined(CONFIG_TEGRA)
-static ulong timestamp;
-static ulong lastdec;
-
-int timer_init (void)
-{
-	/* No timer routines for tegra as yet */
-	lastdec = 0;
-	timestamp = 0;
-
-	return 0;
-}
-#endif

arch/arm/cpu/arm720t/start.S

@@ -1,333 +0,0 @@
-/*
- *  armboot - Startup Code for ARM720 CPU-core
- *
- *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
- *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <asm-offsets.h>
-#include <config.h>
-#include <version.h>
-#include <asm/hardware.h>
-
-/*
- *************************************************************************
- *
- * Jump vector table as in table 3.1 in [1]
- *
- *************************************************************************
- */
-
-
-.globl _start
-_start: b	reset
-	ldr	pc, _undefined_instruction
-	ldr	pc, _software_interrupt
-	ldr	pc, _prefetch_abort
-	ldr	pc, _data_abort
-	ldr	pc, _not_used
-	ldr	pc, _irq
-	ldr	pc, _fiq
-
-#ifdef CONFIG_SPL_BUILD
-_undefined_instruction: .word _undefined_instruction
-_software_interrupt:	.word _software_interrupt
-_prefetch_abort:	.word _prefetch_abort
-_data_abort:		.word _data_abort
-_not_used:		.word _not_used
-_irq:			.word _irq
-_fiq:			.word _fiq
-_pad:			.word 0x12345678 /* now 16*4=64 */
-#else
-_undefined_instruction: .word undefined_instruction
-_software_interrupt:	.word software_interrupt
-_prefetch_abort:	.word prefetch_abort
-_data_abort:		.word data_abort
-_not_used:		.word not_used
-_irq:			.word irq
-_fiq:			.word fiq
-_pad:			.word 0x12345678 /* now 16*4=64 */
-#endif	/* CONFIG_SPL_BUILD */
-
-	.balignl 16,0xdeadbeef
-
-
-/*
- *************************************************************************
- *
- * Startup Code (reset vector)
- *
- * do important init only if we don't start from RAM!
- * relocate armboot to ram
- * setup stack
- * jump to second stage
- *
- *************************************************************************
- */
-
-.globl _TEXT_BASE
-_TEXT_BASE:
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
-	.word	CONFIG_SPL_TEXT_BASE
-#else
-	.word	CONFIG_SYS_TEXT_BASE
-#endif
-
-/*
- * These are defined in the board-specific linker script.
- * Subtracting _start from them lets the linker put their
- * relative position in the executable instead of leaving
- * them null.
- */
-.globl _bss_start_ofs
-_bss_start_ofs:
-	.word __bss_start - _start
-
-.globl _bss_end_ofs
-_bss_end_ofs:
-	.word __bss_end - _start
-
-.globl _end_ofs
-_end_ofs:
-	.word _end - _start
-
-#ifdef CONFIG_USE_IRQ
-/* IRQ stack memory (calculated at run-time) */
-.globl IRQ_STACK_START
-IRQ_STACK_START:
-	.word	0x0badc0de
-
-/* IRQ stack memory (calculated at run-time) */
-.globl FIQ_STACK_START
-FIQ_STACK_START:
-	.word 0x0badc0de
-#endif
-
-/* IRQ stack memory (calculated at run-time) + 8 bytes */
-.globl IRQ_STACK_START_IN
-IRQ_STACK_START_IN:
-	.word	0x0badc0de
-
-/*
- * the actual reset code
- */
-
-reset:
-	/*
-	 * set the cpu to SVC32 mode
-	 */
-	mrs	r0,cpsr
-	bic	r0,r0,#0x1f
-	orr	r0,r0,#0xd3
-	msr	cpsr,r0
-
-	/*
-	 * we do sys-critical inits only at reboot,
-	 * not when booting from ram!
-	 */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-	bl	cpu_init_crit
-#endif
-
-	bl	_main
-
-/*------------------------------------------------------------------------------*/
-
-	.globl	c_runtime_cpu_setup
-c_runtime_cpu_setup:
-
-	mov	pc, lr
-
-/*
- *************************************************************************
- *
- * CPU_init_critical registers
- *
- * setup important registers
- * setup memory timing
- *
- *************************************************************************
- */
-
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-cpu_init_crit:
-
-	mov	ip, lr
-	/*
-	 * before relocating, we have to setup RAM timing
-	 * because memory timing is board-dependent, you will
-	 * find a lowlevel_init.S in your board directory.
-	 */
-	bl	lowlevel_init
-	mov	lr, ip
-
-	mov	pc, lr
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
-
-
-#ifndef CONFIG_SPL_BUILD
-/*
- *************************************************************************
- *
- * Interrupt handling
- *
- *************************************************************************
- */
-
-@
-@ IRQ stack frame.
-@
-#define S_FRAME_SIZE	72
-
-#define S_OLD_R0	68
-#define S_PSR		64
-#define S_PC		60
-#define S_LR		56
-#define S_SP		52
-
-#define S_IP		48
-#define S_FP		44
-#define S_R10		40
-#define S_R9		36
-#define S_R8		32
-#define S_R7		28
-#define S_R6		24
-#define S_R5		20
-#define S_R4		16
-#define S_R3		12
-#define S_R2		8
-#define S_R1		4
-#define S_R0		0
-
-#define MODE_SVC 0x13
-#define I_BIT	 0x80
-
-/*
- * use bad_save_user_regs for abort/prefetch/undef/swi ...
- * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
- */
-
-	.macro	bad_save_user_regs
-	sub	sp, sp, #S_FRAME_SIZE
-	stmia	sp, {r0 - r12}			@ Calling r0-r12
-	add	r8, sp, #S_PC
-
-	ldr	r2, IRQ_STACK_START_IN
-	ldmia	r2, {r2 - r4}			@ get pc, cpsr, old_r0
-	add	r0, sp, #S_FRAME_SIZE		@ restore sp_SVC
-
-	add	r5, sp, #S_SP
-	mov	r1, lr
-	stmia	r5, {r0 - r4}			@ save sp_SVC, lr_SVC, pc, cpsr, old_r
-	mov	r0, sp
-	.endm
-
-	.macro	irq_save_user_regs
-	sub	sp, sp, #S_FRAME_SIZE
-	stmia	sp, {r0 - r12}			@ Calling r0-r12
-	add	r8, sp, #S_PC
-	stmdb	r8, {sp, lr}^			@ Calling SP, LR
-	str	lr, [r8, #0]			@ Save calling PC
-	mrs	r6, spsr
-	str	r6, [r8, #4]			@ Save CPSR
-	str	r0, [r8, #8]			@ Save OLD_R0
-	mov	r0, sp
-	.endm
-
-	.macro	irq_restore_user_regs
-	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
-	mov	r0, r0
-	ldr	lr, [sp, #S_PC]			@ Get PC
-	add	sp, sp, #S_FRAME_SIZE
-	subs	pc, lr, #4			@ return & move spsr_svc into cpsr
-	.endm
-
-	.macro get_bad_stack
-	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack
-
-	str	lr, [r13]			@ save caller lr / spsr
-	mrs	lr, spsr
-	str	lr, [r13, #4]
-
-	mov	r13, #MODE_SVC			@ prepare SVC-Mode
-	msr	spsr_c, r13
-	mov	lr, pc
-	movs	pc, lr
-	.endm
-
-	.macro get_irq_stack			@ setup IRQ stack
-	ldr	sp, IRQ_STACK_START
-	.endm
-
-	.macro get_fiq_stack			@ setup FIQ stack
-	ldr	sp, FIQ_STACK_START
-	.endm
-
-/*
- * exception handlers
- */
-	.align	5
-undefined_instruction:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_undefined_instruction
-
-	.align	5
-software_interrupt:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_software_interrupt
-
-	.align	5
-prefetch_abort:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_prefetch_abort
-
-	.align	5
-data_abort:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_data_abort
-
-	.align	5
-not_used:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_not_used
-
-#ifdef CONFIG_USE_IRQ
-
-	.align	5
-irq:
-	get_irq_stack
-	irq_save_user_regs
-	bl	do_irq
-	irq_restore_user_regs
-
-	.align	5
-fiq:
-	get_fiq_stack
-	/* someone ought to write a more effiction fiq_save_user_regs */
-	irq_save_user_regs
-	bl	do_fiq
-	irq_restore_user_regs
-
-#else
-
-	.align	5
-irq:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_irq
-
-	.align	5
-fiq:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_fiq
-
-#endif
-#endif /* CONFIG_SPL_BUILD */

arch/arm/cpu/arm720t/tegra-common/Makefile

@@ -1,32 +0,0 @@
-#
-# (C) Copyright 2010,2011 Nvidia Corporation.
-#
-# (C) Copyright 2000-2008
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)libtegra-common.o
-
-COBJS-$(CONFIG_SPL_BUILD) += spl.o
-COBJS-y	+= cpu.o
-
-SRCS	:= $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################

arch/arm/cpu/arm720t/tegra-common/cpu.c

@@ -1,341 +0,0 @@
-/*
- * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/gp_padctrl.h>
-#include <asm/arch/pinmux.h>
-#include <asm/arch/tegra.h>
-#include <asm/arch-tegra/clk_rst.h>
-#include <asm/arch-tegra/pmc.h>
-#include <asm/arch-tegra/scu.h>
-#include "cpu.h"
-
-int get_num_cpus(void)
-{
-	struct apb_misc_gp_ctlr *gp;
-	uint rev;
-
-	gp = (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
-	rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
-
-	switch (rev) {
-	case CHIPID_TEGRA20:
-		return 2;
-		break;
-	case CHIPID_TEGRA30:
-	case CHIPID_TEGRA114:
-	default:
-		return 4;
-		break;
-	}
-}
-
-/*
- * Timing tables for each SOC for all four oscillator options.
- */
-struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
-	/* T20: 1 GHz */
-	/*  n,  m, p, cpcon */
-	{{ 1000, 13, 0, 12},	/* OSC 13M */
-	 { 625,  12, 0, 8},	/* OSC 19.2M */
-	 { 1000, 12, 0, 12},	/* OSC 12M */
-	 { 1000, 26, 0, 12},	/* OSC 26M */
-	},
-
-	/* T25: 1.2 GHz */
-	{{ 923, 10, 0, 12},
-	 { 750, 12, 0, 8},
-	 { 600,  6, 0, 12},
-	 { 600, 13, 0, 12},
-	},
-
-	/* T30: 1.4 GHz */
-	{{ 862, 8, 0, 8},
-	 { 583, 8, 0, 4},
-	 { 700, 6, 0, 8},
-	 { 700, 13, 0, 8},
-	},
-
-	/* T114: 1.4 GHz */
-	{{ 862, 8, 0, 8},
-	 { 583, 8, 0, 4},
-	 { 696, 12, 0, 8},
-	 { 700, 13, 0, 8},
-	},
-};
-
-void adjust_pllp_out_freqs(void)
-{
-	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
-	struct clk_pll *pll = &clkrst->crc_pll[CLOCK_ID_PERIPH];
-	u32 reg;
-
-	/* Set T30 PLLP_OUT1, 2, 3 & 4 freqs to 9.6, 48, 102 & 204MHz */
-	reg = readl(&pll->pll_out[0]);	/* OUTA, contains OUT2 / OUT1 */
-	reg |= (IN_408_OUT_48_DIVISOR << PLLP_OUT2_RATIO) | PLLP_OUT2_OVR
-		| (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO) | PLLP_OUT1_OVR;
-	writel(reg, &pll->pll_out[0]);
-
-	reg = readl(&pll->pll_out[1]);   /* OUTB, contains OUT4 / OUT3 */
-	reg |= (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO) | PLLP_OUT4_OVR
-		| (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO) | PLLP_OUT3_OVR;
-	writel(reg, &pll->pll_out[1]);
-}
-
-int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
-		u32 divp, u32 cpcon)
-{
-	u32 reg;
-
-	/* If PLLX is already enabled, just return */
-	if (readl(&pll->pll_base) & PLL_ENABLE_MASK) {
-		debug("pllx_set_rate: PLLX already enabled, returning\n");
-		return 0;
-	}
-
-	debug(" pllx_set_rate entry\n");
-
-	/* Set BYPASS, m, n and p to PLLX_BASE */
-	reg = PLL_BYPASS_MASK | (divm << PLL_DIVM_SHIFT);
-	reg |= ((divn << PLL_DIVN_SHIFT) | (divp << PLL_DIVP_SHIFT));
-	writel(reg, &pll->pll_base);
-
-	/* Set cpcon to PLLX_MISC */
-	reg = (cpcon << PLL_CPCON_SHIFT);
-
-	/* Set dccon to PLLX_MISC if freq > 600MHz */
-	if (divn > 600)
-		reg |= (1 << PLL_DCCON_SHIFT);
-	writel(reg, &pll->pll_misc);
-
-	/* Enable PLLX */
-	reg = readl(&pll->pll_base);
-	reg |= PLL_ENABLE_MASK;
-
-	/* Disable BYPASS */
-	reg &= ~PLL_BYPASS_MASK;
-	writel(reg, &pll->pll_base);
-
-	/* Set lock_enable to PLLX_MISC */
-	reg = readl(&pll->pll_misc);
-	reg |= PLL_LOCK_ENABLE_MASK;
-	writel(reg, &pll->pll_misc);
-
-	return 0;
-}
-
-void init_pllx(void)
-{
-	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
-	struct clk_pll_simple *pll = &clkrst->crc_pll_simple[SIMPLE_PLLX];
-	int soc_type, sku_info, chip_sku;
-	enum clock_osc_freq osc;
-	struct clk_pll_table *sel;
-
-	debug("init_pllx entry\n");
-
-	/* get SOC (chip) type */
-	soc_type = tegra_get_chip();
-	debug(" init_pllx: SoC = 0x%02X\n", soc_type);
-
-	/* get SKU info */
-	sku_info = tegra_get_sku_info();
-	debug(" init_pllx: SKU info byte = 0x%02X\n", sku_info);
-
-	/* get chip SKU, combo of the above info */
-	chip_sku = tegra_get_chip_sku();
-	debug(" init_pllx: Chip SKU = %d\n", chip_sku);
-
-	/* get osc freq */
-	osc = clock_get_osc_freq();
-	debug(" init_pllx: osc = %d\n", osc);
-
-	/* set pllx */
-	sel = &tegra_pll_x_table[chip_sku][osc];
-	pllx_set_rate(pll, sel->n, sel->m, sel->p, sel->cpcon);
-
-	/* adjust PLLP_out1-4 on T3x/T114 */
-	if (soc_type >= CHIPID_TEGRA30) {
-		debug("  init_pllx: adjusting PLLP out freqs\n");
-		adjust_pllp_out_freqs();
-	}
-}
-
-void enable_cpu_clock(int enable)
-{
-	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
-	u32 clk;
-
-	/*
-	 * NOTE:
-	 * Regardless of whether the request is to enable or disable the CPU
-	 * clock, every processor in the CPU complex except the master (CPU 0)
-	 * will have it's clock stopped because the AVP only talks to the
-	 * master.
-	 */
-
-	if (enable) {
-		/* Initialize PLLX */
-		init_pllx();
-
-		/* Wait until all clocks are stable */
-		udelay(PLL_STABILIZATION_DELAY);
-
-		writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
-		writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
-	}
-
-	/*
-	 * Read the register containing the individual CPU clock enables and
-	 * always stop the clocks to CPUs > 0.
-	 */
-	clk = readl(&clkrst->crc_clk_cpu_cmplx);
-	clk |= 1 << CPU1_CLK_STP_SHIFT;
-	if (get_num_cpus() == 4)
-		clk |= (1 << CPU2_CLK_STP_SHIFT) + (1 << CPU3_CLK_STP_SHIFT);
-
-	/* Stop/Unstop the CPU clock */
-	clk &= ~CPU0_CLK_STP_MASK;
-	clk |= !enable << CPU0_CLK_STP_SHIFT;
-	writel(clk, &clkrst->crc_clk_cpu_cmplx);
-
-	clock_enable(PERIPH_ID_CPU);
-}
-
-static int is_cpu_powered(void)
-{
-	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
-
-	return (readl(&pmc->pmc_pwrgate_status) & CPU_PWRED) ? 1 : 0;
-}
-
-static void remove_cpu_io_clamps(void)
-{
-	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
-	u32 reg;
-
-	/* Remove the clamps on the CPU I/O signals */
-	reg = readl(&pmc->pmc_remove_clamping);
-	reg |= CPU_CLMP;
-	writel(reg, &pmc->pmc_remove_clamping);
-
-	/* Give I/O signals time to stabilize */
-	udelay(IO_STABILIZATION_DELAY);
-}
-
-void powerup_cpu(void)
-{
-	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
-	u32 reg;
-	int timeout = IO_STABILIZATION_DELAY;
-
-	if (!is_cpu_powered()) {
-		/* Toggle the CPU power state (OFF -> ON) */
-		reg = readl(&pmc->pmc_pwrgate_toggle);
-		reg &= PARTID_CP;
-		reg |= START_CP;
-		writel(reg, &pmc->pmc_pwrgate_toggle);
-
-		/* Wait for the power to come up */
-		while (!is_cpu_powered()) {
-			if (timeout-- == 0)
-				printf("CPU failed to power up!\n");
-			else
-				udelay(10);
-		}
-
-		/*
-		 * Remove the I/O clamps from CPU power partition.
-		 * Recommended only on a Warm boot, if the CPU partition gets
-		 * power gated. Shouldn't cause any harm when called after a
-		 * cold boot according to HW, probably just redundant.
-		 */
-		remove_cpu_io_clamps();
-	}
-}
-
-void reset_A9_cpu(int reset)
-{
-	/*
-	* NOTE:  Regardless of whether the request is to hold the CPU in reset
-	*        or take it out of reset, every processor in the CPU complex
-	*        except the master (CPU 0) will be held in reset because the
-	*        AVP only talks to the master. The AVP does not know that there
-	*        are multiple processors in the CPU complex.
-	*/
-	int mask = crc_rst_cpu | crc_rst_de | crc_rst_debug;
-	int num_cpus = get_num_cpus();
-	int cpu;
-
-	debug("reset_a9_cpu entry\n");
-	/* Hold CPUs 1 onwards in reset, and CPU 0 if asked */
-	for (cpu = 1; cpu < num_cpus; cpu++)
-		reset_cmplx_set_enable(cpu, mask, 1);
-	reset_cmplx_set_enable(0, mask, reset);
-
-	/* Enable/Disable master CPU reset */
-	reset_set_enable(PERIPH_ID_CPU, reset);
-}
-
-void clock_enable_coresight(int enable)
-{
-	u32 rst, src = 2;
-	int soc_type;
-
-	debug("clock_enable_coresight entry\n");
-	clock_set_enable(PERIPH_ID_CORESIGHT, enable);
-	reset_set_enable(PERIPH_ID_CORESIGHT, !enable);
-
-	if (enable) {
-		/*
-		 * Put CoreSight on PLLP_OUT0 and divide it down as per
-		 * PLLP base frequency based on SoC type (T20/T30/T114).
-		 * Clock divider request would setup CSITE clock as 144MHz
-		 * for PLLP base 216MHz and 204MHz for PLLP base 408MHz
-		 */
-
-		soc_type = tegra_get_chip();
-		if (soc_type == CHIPID_TEGRA30 || soc_type == CHIPID_TEGRA114)
-			src = CLK_DIVIDER(NVBL_PLLP_KHZ, 204000);
-		else if (soc_type == CHIPID_TEGRA20)
-			src = CLK_DIVIDER(NVBL_PLLP_KHZ, 144000);
-		else
-			printf("%s: Unknown SoC type %X!\n",
-				 __func__, soc_type);
-
-		clock_ll_set_source_divisor(PERIPH_ID_CSI, 0, src);
-
-		/* Unlock the CPU CoreSight interfaces */
-		rst = CORESIGHT_UNLOCK;
-		writel(rst, CSITE_CPU_DBG0_LAR);
-		writel(rst, CSITE_CPU_DBG1_LAR);
-		if (get_num_cpus() == 4) {
-			writel(rst, CSITE_CPU_DBG2_LAR);
-			writel(rst, CSITE_CPU_DBG3_LAR);
-		}
-	}
-}
-
-void halt_avp(void)
-{
-	for (;;) {
-		writel((HALT_COP_EVENT_JTAG | HALT_COP_EVENT_IRQ_1 \
-			| HALT_COP_EVENT_FIQ_1 | (FLOW_MODE_STOP<<29)),
-			FLOW_CTLR_HALT_COP_EVENTS);
-	}
-}

arch/arm/cpu/arm720t/tegra-common/cpu.h

@@ -1,70 +0,0 @@
-/*
- * (C) Copyright 2010-2011
- * NVIDIA Corporation <www.nvidia.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#include <asm/types.h>
-
-/* Stabilization delays, in usec */
-#define PLL_STABILIZATION_DELAY (300)
-#define IO_STABILIZATION_DELAY	(1000)
-
-#if defined(CONFIG_TEGRA20)
-#define NVBL_PLLP_KHZ	(216000)
-#elif defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114)
-#define NVBL_PLLP_KHZ	(408000)
-#else
-#error "Unknown Tegra chip!"
-#endif
-
-#define PLLX_ENABLED		(1 << 30)
-#define CCLK_BURST_POLICY	0x20008888
-#define SUPER_CCLK_DIVIDER	0x80000000
-
-/* Calculate clock fractional divider value from ref and target frequencies */
-#define CLK_DIVIDER(REF, FREQ)  ((((REF) * 2) / FREQ) - 2)
-
-/* Calculate clock frequency value from reference and clock divider value */
-#define CLK_FREQUENCY(REF, REG)  (((REF) * 2) / (REG + 2))
-
-/* AVP/CPU ID */
-#define PG_UP_TAG_0_PID_CPU	0x55555555	/* CPU aka "a9" aka "mpcore" */
-#define PG_UP_TAG_0             0x0
-
-#define CORESIGHT_UNLOCK	0xC5ACCE55;
-
-#define EXCEP_VECTOR_CPU_RESET_VECTOR	(NV_PA_EVP_BASE + 0x100)
-#define CSITE_CPU_DBG0_LAR		(NV_PA_CSITE_BASE + 0x10FB0)
-#define CSITE_CPU_DBG1_LAR		(NV_PA_CSITE_BASE + 0x12FB0)
-#define CSITE_CPU_DBG2_LAR		(NV_PA_CSITE_BASE + 0x14FB0)
-#define CSITE_CPU_DBG3_LAR		(NV_PA_CSITE_BASE + 0x16FB0)
-
-#define FLOW_CTLR_HALT_COP_EVENTS	(NV_PA_FLOW_BASE + 4)
-#define FLOW_MODE_STOP			2
-#define HALT_COP_EVENT_JTAG		(1 << 28)
-#define HALT_COP_EVENT_IRQ_1		(1 << 11)
-#define HALT_COP_EVENT_FIQ_1		(1 << 9)
-
-#define FLOW_MODE_NONE		0
-
-#define SIMPLE_PLLX     (CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE)
-
-struct clk_pll_table {
-	u16	n;
-	u16	m;
-	u8	p;
-	u8	cpcon;
-};
-
-void clock_enable_coresight(int enable);
-void enable_cpu_clock(int enable);
-void halt_avp(void)  __attribute__ ((noreturn));
-void init_pllx(void);
-void powerup_cpu(void);
-void reset_A9_cpu(int reset);
-void start_cpu(u32 reset_vector);
-int tegra_get_chip(void);
-int tegra_get_sku_info(void);
-int tegra_get_chip_sku(void);
-void adjust_pllp_out_freqs(void);

arch/arm/cpu/arm720t/tegra-common/spl.c

@@ -1,47 +0,0 @@
-/*
- * (C) Copyright 2012
- * NVIDIA Inc, <www.nvidia.com>
- *
- * Allen Martin <amartin@nvidia.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#include <common.h>
-#include <spl.h>
-
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/pinmux.h>
-#include <asm/arch/tegra.h>
-#include <asm/arch-tegra/board.h>
-#include <asm/arch/spl.h>
-#include "cpu.h"
-
-void spl_board_init(void)
-{
-	struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-
-	/* enable JTAG */
-	writel(0xC0, &pmt->pmt_cfg_ctl);
-
-	board_init_uart_f();
-
-	/* Initialize periph GPIOs */
-	gpio_early_init_uart();
-
-	clock_early_init();
-	preloader_console_init();
-}
-
-u32 spl_boot_device(void)
-{
-	return BOOT_DEVICE_RAM;
-}
-
-void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
-{
-	debug("image entry point: 0x%X\n", spl_image->entry_point);
-
-	start_cpu((u32)spl_image->entry_point);
-	halt_avp();
-}

arch/arm/cpu/arm720t/tegra114/Makefile

@@ -1,42 +0,0 @@
-#
-# Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
-#
-# (C) Copyright 2000-2008
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# This program is free software; you can redistribute it and/or modify it
-# under the terms and conditions of the GNU General Public License,
-# version 2, as published by the Free Software Foundation.
-#
-# This program is distributed in the hope it will be useful, but WITHOUT
-# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-# more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program.  If not, see <http://www.gnu.org/licenses/>.
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-#COBJS-y	+= cpu.o t11x.o
-COBJS-y	+= cpu.o
-
-SRCS	:= $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################

arch/arm/cpu/arm720t/tegra114/config.mk

@@ -1,19 +0,0 @@
-#
-# Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-#
-# This program is free software; you can redistribute it and/or modify it
-# under the terms and conditions of the GNU General Public License,
-# version 2, as published by the Free Software Foundation.
-#
-# This program is distributed in the hope it will be useful, but WITHOUT
-# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-# more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program.  If not, see <http://www.gnu.org/licenses/>.
-#
-USE_PRIVATE_LIBGCC = yes

arch/arm/cpu/arm720t/tegra114/cpu.c

@@ -1,324 +0,0 @@
-/*
- * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/flow.h>
-#include <asm/arch/pinmux.h>
-#include <asm/arch/tegra.h>
-#include <asm/arch-tegra/clk_rst.h>
-#include <asm/arch-tegra/pmc.h>
-#include "../tegra-common/cpu.h"
-
-/* Tegra114-specific CPU init code */
-static void enable_cpu_power_rail(void)
-{
-	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
-	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
-	u32 reg;
-
-	debug("enable_cpu_power_rail entry\n");
-
-	/* un-tristate PWR_I2C SCL/SDA, rest of the defaults are correct */
-	pinmux_tristate_disable(PINGRP_PWR_I2C_SCL);
-	pinmux_tristate_disable(PINGRP_PWR_I2C_SDA);
-
-	/*
-	 * Set CPUPWRGOOD_TIMER - APB clock is 1/2 of SCLK (102MHz),
-	 * set it for 25ms (102MHz * .025)
-	 */
-	reg = 0x26E8F0;
-	writel(reg, &pmc->pmc_cpupwrgood_timer);
-
-	/* Set polarity to 0 (normal) and enable CPUPWRREQ_OE */
-	clrbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_POL);
-	setbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_OE);
-
-	/*
-	 * Set CLK_RST_CONTROLLER_CPU_SOFTRST_CTRL2_0_CAR2PMC_CPU_ACK_WIDTH
-	 * to 408 to satisfy the requirement of having at least 16 CPU clock
-	 * cycles before clamp removal.
-	 */
-
-	clrbits_le32(&clkrst->crc_cpu_softrst_ctrl2, 0xFFF);
-	setbits_le32(&clkrst->crc_cpu_softrst_ctrl2, 408);
-}
-
-static void enable_cpu_clocks(void)
-{
-	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
-	u32 reg;
-
-	debug("enable_cpu_clocks entry\n");
-
-	/* Wait for PLL-X to lock */
-	do {
-		reg = readl(&clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base);
-	} while ((reg & (1 << 27)) == 0);
-
-	/* Wait until all clocks are stable */
-	udelay(PLL_STABILIZATION_DELAY);
-
-	writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
-	writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
-
-	/* Always enable the main CPU complex clocks */
-	clock_enable(PERIPH_ID_CPU);
-	clock_enable(PERIPH_ID_CPULP);
-	clock_enable(PERIPH_ID_CPUG);
-}
-
-static void remove_cpu_resets(void)
-{
-	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
-	u32 reg;
-
-	debug("remove_cpu_resets entry\n");
-	/* Take the slow non-CPU partition out of reset */
-	reg = readl(&clkrst->crc_rst_cpulp_cmplx_clr);
-	writel((reg | CLR_NONCPURESET), &clkrst->crc_rst_cpulp_cmplx_clr);
-
-	/* Take the fast non-CPU partition out of reset */
-	reg = readl(&clkrst->crc_rst_cpug_cmplx_clr);
-	writel((reg | CLR_NONCPURESET), &clkrst->crc_rst_cpug_cmplx_clr);
-
-	/* Clear the SW-controlled reset of the slow cluster */
-	reg = readl(&clkrst->crc_rst_cpulp_cmplx_clr);
-	reg |= (CLR_CPURESET0+CLR_DBGRESET0+CLR_CORERESET0+CLR_CXRESET0);
-	writel(reg, &clkrst->crc_rst_cpulp_cmplx_clr);
-
-	/* Clear the SW-controlled reset of the fast cluster */
-	reg = readl(&clkrst->crc_rst_cpug_cmplx_clr);
-	reg |= (CLR_CPURESET0+CLR_DBGRESET0+CLR_CORERESET0+CLR_CXRESET0);
-	reg |= (CLR_CPURESET1+CLR_DBGRESET1+CLR_CORERESET1+CLR_CXRESET1);
-	reg |= (CLR_CPURESET2+CLR_DBGRESET2+CLR_CORERESET2+CLR_CXRESET2);
-	reg |= (CLR_CPURESET3+CLR_DBGRESET3+CLR_CORERESET3+CLR_CXRESET3);
-	writel(reg, &clkrst->crc_rst_cpug_cmplx_clr);
-}
-
-/**
- * The T114 requires some special clock initialization, including setting up
- * the DVC I2C, turning on MSELECT and selecting the G CPU cluster
- */
-void t114_init_clocks(void)
-{
-	struct clk_rst_ctlr *clkrst =
-			(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
-	struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
-	u32 val;
-
-	debug("t114_init_clocks entry\n");
-
-	/* Set active CPU cluster to G */
-	clrbits_le32(&flow->cluster_control, 1);
-
-	/*
-	 * Switch system clock to PLLP_OUT4 (108 MHz), AVP will now run
-	 * at 108 MHz. This is glitch free as only the source is changed, no
-	 * special precaution needed.
-	 */
-	val = (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) |
-		(SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) |
-		(SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) |
-		(SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) |
-		(SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT);
-	writel(val, &clkrst->crc_sclk_brst_pol);
-
-	writel(SUPER_SCLK_ENB_MASK, &clkrst->crc_super_sclk_div);
-
-	debug("Setting up PLLX\n");
-	init_pllx();
-
-	val = (1 << CLK_SYS_RATE_AHB_RATE_SHIFT);
-	writel(val, &clkrst->crc_clk_sys_rate);
-
-	/* Enable clocks to required peripherals. TBD - minimize this list */
-	debug("Enabling clocks\n");
-
-	clock_set_enable(PERIPH_ID_CACHE2, 1);
-	clock_set_enable(PERIPH_ID_GPIO, 1);
-	clock_set_enable(PERIPH_ID_TMR, 1);
-	clock_set_enable(PERIPH_ID_RTC, 1);
-	clock_set_enable(PERIPH_ID_CPU, 1);
-	clock_set_enable(PERIPH_ID_EMC, 1);
-	clock_set_enable(PERIPH_ID_I2C5, 1);
-	clock_set_enable(PERIPH_ID_FUSE, 1);
-	clock_set_enable(PERIPH_ID_PMC, 1);
-	clock_set_enable(PERIPH_ID_APBDMA, 1);
-	clock_set_enable(PERIPH_ID_MEM, 1);
-	clock_set_enable(PERIPH_ID_IRAMA, 1);
-	clock_set_enable(PERIPH_ID_IRAMB, 1);
-	clock_set_enable(PERIPH_ID_IRAMC, 1);
-	clock_set_enable(PERIPH_ID_IRAMD, 1);
-	clock_set_enable(PERIPH_ID_CORESIGHT, 1);
-	clock_set_enable(PERIPH_ID_MSELECT, 1);
-	clock_set_enable(PERIPH_ID_EMC1, 1);
-	clock_set_enable(PERIPH_ID_MC1, 1);
-	clock_set_enable(PERIPH_ID_DVFS, 1);
-
-	/*
-	 * Set MSELECT clock source as PLLP (00), and ask for a clock
-	 * divider that would set the MSELECT clock at 102MHz for a
-	 * PLLP base of 408MHz.
-	 */
-	clock_ll_set_source_divisor(PERIPH_ID_MSELECT, 0,
-		CLK_DIVIDER(NVBL_PLLP_KHZ, 102000));
-
-	/* I2C5 (DVC) gets CLK_M and a divisor of 17 */
-	clock_ll_set_source_divisor(PERIPH_ID_I2C5, 3, 16);
-
-	/* Give clocks time to stabilize */
-	udelay(1000);
-
-	/* Take required peripherals out of reset */
-	debug("Taking periphs out of reset\n");
-	reset_set_enable(PERIPH_ID_CACHE2, 0);
-	reset_set_enable(PERIPH_ID_GPIO, 0);
-	reset_set_enable(PERIPH_ID_TMR, 0);
-	reset_set_enable(PERIPH_ID_COP, 0);
-	reset_set_enable(PERIPH_ID_EMC, 0);
-	reset_set_enable(PERIPH_ID_I2C5, 0);
-	reset_set_enable(PERIPH_ID_FUSE, 0);
-	reset_set_enable(PERIPH_ID_APBDMA, 0);
-	reset_set_enable(PERIPH_ID_MEM, 0);
-	reset_set_enable(PERIPH_ID_CORESIGHT, 0);
-	reset_set_enable(PERIPH_ID_MSELECT, 0);
-	reset_set_enable(PERIPH_ID_EMC1, 0);
-	reset_set_enable(PERIPH_ID_MC1, 0);
-	reset_set_enable(PERIPH_ID_DVFS, 0);
-
-	debug("t114_init_clocks exit\n");
-}
-
-static int is_partition_powered(u32 mask)
-{
-	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
-	u32 reg;
-
-	/* Get power gate status */
-	reg = readl(&pmc->pmc_pwrgate_status);
-	return (reg & mask) == mask;
-}
-
-static int is_clamp_enabled(u32 mask)
-{
-	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
-	u32 reg;
-
-	/* Get clamp status. TODO: Add pmc_clamp_status alias to pmc.h */
-	reg = readl(&pmc->pmc_pwrgate_timer_on);
-	return (reg & mask) == mask;
-}
-
-static void power_partition(u32 status, u32 partid)
-{
-	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
-
-	debug("%s: status = %08X, part ID = %08X\n", __func__, status, partid);
-	/* Is the partition already on? */
-	if (!is_partition_powered(status)) {
-		/* No, toggle the partition power state (OFF -> ON) */
-		debug("power_partition, toggling state\n");
-		clrbits_le32(&pmc->pmc_pwrgate_toggle, 0x1F);
-		setbits_le32(&pmc->pmc_pwrgate_toggle, partid);
-		setbits_le32(&pmc->pmc_pwrgate_toggle, START_CP);
-
-		/* Wait for the power to come up */
-		while (!is_partition_powered(status))
-			;
-
-		/* Wait for the clamp status to be cleared */
-		while (is_clamp_enabled(status))
-			;
-
-		/* Give I/O signals time to stabilize */
-		udelay(IO_STABILIZATION_DELAY);
-	}
-}
-
-void powerup_cpus(void)
-{
-	debug("powerup_cpus entry\n");
-
-	/* We boot to the fast cluster */
-	debug("powerup_cpus entry: G cluster\n");
-	/* Power up the fast cluster rail partition */
-	power_partition(CRAIL, CRAILID);
-
-	/* Power up the fast cluster non-CPU partition */
-	power_partition(C0NC, C0NCID);
-
-	/* Power up the fast cluster CPU0 partition */
-	power_partition(CE0, CE0ID);
-}
-
-void start_cpu(u32 reset_vector)
-{
-	u32 imme, inst;
-
-	debug("start_cpu entry, reset_vector = %x\n", reset_vector);
-
-	t114_init_clocks();
-
-	/* Enable VDD_CPU */
-	enable_cpu_power_rail();
-
-	/* Get the CPU(s) running */
-	enable_cpu_clocks();
-
-	/* Enable CoreSight */
-	clock_enable_coresight(1);
-
-	/* Take CPU(s) out of reset */
-	remove_cpu_resets();
-
-	/* Set the entry point for CPU execution from reset */
-
-	/*
-	 * A01P with patched boot ROM; vector hard-coded to 0x4003fffc.
-	 * See nvbug 1193357 for details.
-	 */
-
-	/* mov r0, #lsb(reset_vector) */
-	imme = reset_vector & 0xffff;
-	inst = imme & 0xfff;
-	inst |= ((imme >> 12) << 16);
-	inst |= 0xe3000000;
-	writel(inst, 0x4003fff0);
-
-	/* movt r0, #msb(reset_vector) */
-	imme = (reset_vector >> 16) & 0xffff;
-	inst = imme & 0xfff;
-	inst |= ((imme >> 12) << 16);
-	inst |= 0xe3400000;
-	writel(inst, 0x4003fff4);
-
-	/* bx r0 */
-	writel(0xe12fff10, 0x4003fff8);
-
-	/* b -12 */
-	imme = (u32)-20;
-	inst = (imme >> 2) & 0xffffff;
-	inst |= 0xea000000;
-	writel(inst, 0x4003fffc);
-
-	/* Write to orignal location for compatibility */
-	writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
-
-	/* If the CPU(s) don't already have power, power 'em up */
-	powerup_cpus();
-}

arch/arm/cpu/arm720t/tegra20/Makefile

@@ -1,31 +0,0 @@
-#
-# (C) Copyright 2010,2011 Nvidia Corporation.
-#
-# (C) Copyright 2000-2008
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS-y	+= cpu.o
-
-SRCS	:= $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################

arch/arm/cpu/arm720t/tegra20/config.mk

@@ -1,10 +0,0 @@
-#
-# (C) Copyright 2010,2011
-# NVIDIA Corporation <www.nvidia.com>
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-USE_PRIVATE_LIBGCC = yes

arch/arm/cpu/arm720t/tegra20/cpu.c

@@ -1,70 +0,0 @@
-/*
- * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/tegra.h>
-#include <asm/arch-tegra/pmc.h>
-#include "../tegra-common/cpu.h"
-
-static void enable_cpu_power_rail(void)
-{
-	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
-	u32 reg;
-
-	reg = readl(&pmc->pmc_cntrl);
-	reg |= CPUPWRREQ_OE;
-	writel(reg, &pmc->pmc_cntrl);
-
-	/*
-	 * The TI PMU65861C needs a 3.75ms delay between enabling
-	 * the power rail and enabling the CPU clock.  This delay
-	 * between SM1EN and SM1 is for switching time + the ramp
-	 * up of the voltage to the CPU (VDD_CPU from PMU).
-	 */
-	udelay(3750);
-}
-
-void start_cpu(u32 reset_vector)
-{
-	/* Enable VDD_CPU */
-	enable_cpu_power_rail();
-
-	/* Hold the CPUs in reset */
-	reset_A9_cpu(1);
-
-	/* Disable the CPU clock */
-	enable_cpu_clock(0);
-
-	/* Enable CoreSight */
-	clock_enable_coresight(1);
-
-	/*
-	 * Set the entry point for CPU execution from reset,
-	 *  if it's a non-zero value.
-	 */
-	if (reset_vector)
-		writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
-
-	/* Enable the CPU clock */
-	enable_cpu_clock(1);
-
-	/* If the CPU doesn't already have power, power it up */
-	powerup_cpu();
-
-	/* Take the CPU out of reset */
-	reset_A9_cpu(0);
-}

arch/arm/cpu/arm720t/tegra30/Makefile

@@ -1,41 +0,0 @@
-#
-# Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
-#
-# (C) Copyright 2000-2008
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# This program is free software; you can redistribute it and/or modify it
-# under the terms and conditions of the GNU General Public License,
-# version 2, as published by the Free Software Foundation.
-#
-# This program is distributed in the hope it will be useful, but WITHOUT
-# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-# more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program.  If not, see <http://www.gnu.org/licenses/>.
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS-y	+= cpu.o
-
-SRCS	:= $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################

arch/arm/cpu/arm720t/tegra30/config.mk

@@ -1,19 +0,0 @@
-#
-# Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-#
-# This program is free software; you can redistribute it and/or modify it
-# under the terms and conditions of the GNU General Public License,
-# version 2, as published by the Free Software Foundation.
-#
-# This program is distributed in the hope it will be useful, but WITHOUT
-# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-# more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program.  If not, see <http://www.gnu.org/licenses/>.
-#
-USE_PRIVATE_LIBGCC = yes

arch/arm/cpu/arm720t/tegra30/cpu.c

@@ -1,176 +0,0 @@
-/*
- * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/flow.h>
-#include <asm/arch/tegra.h>
-#include <asm/arch-tegra/clk_rst.h>
-#include <asm/arch-tegra/pmc.h>
-#include <asm/arch-tegra/tegra_i2c.h>
-#include "../tegra-common/cpu.h"
-
-/* Tegra30-specific CPU init code */
-void tegra_i2c_ll_write_addr(uint addr, uint config)
-{
-	struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
-
-	writel(addr, &reg->cmd_addr0);
-	writel(config, &reg->cnfg);
-}
-
-void tegra_i2c_ll_write_data(uint data, uint config)
-{
-	struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
-
-	writel(data, &reg->cmd_data1);
-	writel(config, &reg->cnfg);
-}
-
-#define TPS65911_I2C_ADDR		0x5A
-#define TPS65911_VDDCTRL_OP_REG		0x28
-#define TPS65911_VDDCTRL_SR_REG		0x27
-#define TPS65911_VDDCTRL_OP_DATA	(0x2300 | TPS65911_VDDCTRL_OP_REG)
-#define TPS65911_VDDCTRL_SR_DATA	(0x0100 | TPS65911_VDDCTRL_SR_REG)
-#define I2C_SEND_2_BYTES		0x0A02
-
-static void enable_cpu_power_rail(void)
-{
-	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
-	u32 reg;
-
-	debug("enable_cpu_power_rail entry\n");
-	reg = readl(&pmc->pmc_cntrl);
-	reg |= CPUPWRREQ_OE;
-	writel(reg, &pmc->pmc_cntrl);
-
-	/*
-	 * Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus.
-	 * First set VDD to 1.4V, then enable the VDD regulator.
-	 */
-	tegra_i2c_ll_write_addr(TPS65911_I2C_ADDR, 2);
-	tegra_i2c_ll_write_data(TPS65911_VDDCTRL_OP_DATA, I2C_SEND_2_BYTES);
-	udelay(1000);
-	tegra_i2c_ll_write_data(TPS65911_VDDCTRL_SR_DATA, I2C_SEND_2_BYTES);
-	udelay(10 * 1000);
-}
-
-/**
- * The T30 requires some special clock initialization, including setting up
- * the dvc i2c, turning on mselect and selecting the G CPU cluster
- */
-void t30_init_clocks(void)
-{
-	struct clk_rst_ctlr *clkrst =
-			(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
-	struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
-	u32 val;
-
-	debug("t30_init_clocks entry\n");
-	/* Set active CPU cluster to G */
-	clrbits_le32(flow->cluster_control, 1 << 0);
-
-	/*
-	 * Switch system clock to PLLP_OUT4 (108 MHz), AVP will now run
-	 * at 108 MHz. This is glitch free as only the source is changed, no
-	 * special precaution needed.
-	 */
-	val = (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) |
-		(SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) |
-		(SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) |
-		(SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) |
-		(SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT);
-	writel(val, &clkrst->crc_sclk_brst_pol);
-
-	writel(SUPER_SCLK_ENB_MASK, &clkrst->crc_super_sclk_div);
-
-	val = (0 << CLK_SYS_RATE_HCLK_DISABLE_SHIFT) |
-		(1 << CLK_SYS_RATE_AHB_RATE_SHIFT) |
-		(0 << CLK_SYS_RATE_PCLK_DISABLE_SHIFT) |
-		(0 << CLK_SYS_RATE_APB_RATE_SHIFT);
-	writel(val, &clkrst->crc_clk_sys_rate);
-
-	/* Put i2c, mselect in reset and enable clocks */
-	reset_set_enable(PERIPH_ID_DVC_I2C, 1);
-	clock_set_enable(PERIPH_ID_DVC_I2C, 1);
-	reset_set_enable(PERIPH_ID_MSELECT, 1);
-	clock_set_enable(PERIPH_ID_MSELECT, 1);
-
-	/* Switch MSELECT clock to PLLP (00) and use a divisor of 2 */
-	clock_ll_set_source_divisor(PERIPH_ID_MSELECT, 0, 2);
-
-	/*
-	 * Our high-level clock routines are not available prior to
-	 * relocation. We use the low-level functions which require a
-	 * hard-coded divisor. Use CLK_M with divide by (n + 1 = 17)
-	 */
-	clock_ll_set_source_divisor(PERIPH_ID_DVC_I2C, 3, 16);
-
-	/*
-	 * Give clocks time to stabilize, then take i2c and mselect out of
-	 * reset
-	 */
-	udelay(1000);
-	reset_set_enable(PERIPH_ID_DVC_I2C, 0);
-	reset_set_enable(PERIPH_ID_MSELECT, 0);
-}
-
-static void set_cpu_running(int run)
-{
-	struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
-
-	debug("set_cpu_running entry, run = %d\n", run);
-	writel(run ? FLOW_MODE_NONE : FLOW_MODE_STOP, &flow->halt_cpu_events);
-}
-
-void start_cpu(u32 reset_vector)
-{
-	debug("start_cpu entry, reset_vector = %x\n", reset_vector);
-	t30_init_clocks();
-
-	/* Enable VDD_CPU */
-	enable_cpu_power_rail();
-
-	set_cpu_running(0);
-
-	/* Hold the CPUs in reset */
-	reset_A9_cpu(1);
-
-	/* Disable the CPU clock */
-	enable_cpu_clock(0);
-
-	/* Enable CoreSight */
-	clock_enable_coresight(1);
-
-	/*
-	 * Set the entry point for CPU execution from reset,
-	 *  if it's a non-zero value.
-	 */
-	if (reset_vector)
-		writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
-
-	/* Enable the CPU clock */
-	enable_cpu_clock(1);
-
-	/* If the CPU doesn't already have power, power it up */
-	powerup_cpu();
-
-	/* Take the CPU out of reset */
-	reset_A9_cpu(0);
-
-	set_cpu_running(1);
-}

arch/arm/cpu/arm920t/Makefile

@@ -1,33 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(CPU).o
-
-START	= start.o
-
-COBJS-y	+= cpu.o
-COBJS-$(CONFIG_USE_IRQ)	+= interrupts.o
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y) $(SOBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################

arch/arm/cpu/arm920t/a320/Makefile

@@ -1,30 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-SOBJS	+= reset.o
-COBJS	+= timer.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################

arch/arm/cpu/arm920t/a320/reset.S

@@ -1,10 +0,0 @@
-/*
- * (C) Copyright 2009 Faraday Technology
- * Po-Yu Chuang <ratbert@faraday-tech.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-.global reset_cpu
-reset_cpu:
-	b	reset_cpu

arch/arm/cpu/arm920t/a320/timer.c

@@ -1,118 +0,0 @@
-/*
- * (C) Copyright 2009 Faraday Technology
- * Po-Yu Chuang <ratbert@faraday-tech.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <div64.h>
-#include <asm/io.h>
-#include <faraday/ftpmu010.h>
-#include <faraday/fttmr010.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define TIMER_CLOCK	32768
-#define TIMER_LOAD_VAL	0xffffffff
-
-static inline unsigned long long tick_to_time(unsigned long long tick)
-{
-	tick *= CONFIG_SYS_HZ;
-	do_div(tick, gd->arch.timer_rate_hz);
-
-	return tick;
-}
-
-static inline unsigned long long usec_to_tick(unsigned long long usec)
-{
-	usec *= gd->arch.timer_rate_hz;
-	do_div(usec, 1000000);
-
-	return usec;
-}
-
-int timer_init(void)
-{
-	struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
-	unsigned int cr;
-
-	debug("%s()\n", __func__);
-
-	/* disable timers */
-	writel(0, &tmr->cr);
-
-	/* use 32768Hz oscillator for RTC, WDT, TIMER */
-	ftpmu010_32768osc_enable();
-
-	/* setup timer */
-	writel(TIMER_LOAD_VAL, &tmr->timer3_load);
-	writel(TIMER_LOAD_VAL, &tmr->timer3_counter);
-	writel(0, &tmr->timer3_match1);
-	writel(0, &tmr->timer3_match2);
-
-	/* we don't want timer to issue interrupts */
-	writel(FTTMR010_TM3_MATCH1 |
-	       FTTMR010_TM3_MATCH2 |
-	       FTTMR010_TM3_OVERFLOW,
-	       &tmr->interrupt_mask);
-
-	cr = readl(&tmr->cr);
-	cr |= FTTMR010_TM3_CLOCK;	/* use external clock */
-	cr |= FTTMR010_TM3_ENABLE;
-	writel(cr, &tmr->cr);
-
-	gd->arch.timer_rate_hz = TIMER_CLOCK;
-	gd->arch.tbu = gd->arch.tbl = 0;
-
-	return 0;
-}
-
-/*
- * Get the current 64 bit timer tick count
- */
-unsigned long long get_ticks(void)
-{
-	struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
-	ulong now = TIMER_LOAD_VAL - readl(&tmr->timer3_counter);
-
-	/* increment tbu if tbl has rolled over */
-	if (now < gd->arch.tbl)
-		gd->arch.tbu++;
-	gd->arch.tbl = now;
-	return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
-}
-
-void __udelay(unsigned long usec)
-{
-	unsigned long long start;
-	ulong tmo;
-
-	start = get_ticks();		/* get current timestamp */
-	tmo = usec_to_tick(usec);	/* convert usecs to ticks */
-	while ((get_ticks() - start) < tmo)
-		;			/* loop till time has passed */
-}
-
-/*
- * get_timer(base) can be used to check for timeouts or
- * to measure elasped time relative to an event:
- *
- * ulong start_time = get_timer(0) sets start_time to the current
- * time value.
- * get_timer(start_time) returns the time elapsed since then.
- *
- * The time is used in CONFIG_SYS_HZ units!
- */
-ulong get_timer(ulong base)
-{
-	return tick_to_time(get_ticks()) - base;
-}
-
-/*
- * Return the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
-	return gd->arch.timer_rate_hz;
-}

arch/arm/cpu/arm920t/at91/Makefile

@@ -1,34 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-SOBJS	+= lowlevel_init.o
-COBJS	+= reset.o
-COBJS	+= timer.o
-COBJS	+= clock.o
-COBJS	+= cpu.o
-COBJS	+= at91rm9200_devices.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################

arch/arm/cpu/arm920t/at91/at91rm9200_devices.c

@@ -1,67 +0,0 @@
-/*
- * [partely copied from arch/arm/cpu/arm926ejs/at91/arm9260_devices.c]
- *
- * (C) Copyright 2011
- * Andreas Bießmann <andreas.devel@googlemail.com>
- *
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian@popies.net>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/gpio.h>
-
-/*
- * if CONFIG_AT91_GPIO_PULLUP ist set, keep pullups on on all
- * peripheral pins. Good to have if hardware is soldered optionally
- * or in case of SPI no slave is selected. Avoid lines to float
- * needlessly. Use a short local PUP define.
- *
- * Due to errata "TXD floats when CTS is inactive" pullups are always
- * on for TXD pins.
- */
-#ifdef CONFIG_AT91_GPIO_PULLUP
-# define PUP CONFIG_AT91_GPIO_PULLUP
-#else
-# define PUP 0
-#endif
-
-void at91_serial0_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *)ATMEL_BASE_PMC;
-
-	at91_set_a_periph(AT91_PIO_PORTA, 17, 1);		/* TXD0 */
-	at91_set_a_periph(AT91_PIO_PORTA, 18, PUP);		/* RXD0 */
-	writel(1 << ATMEL_ID_USART0, &pmc->pcer);
-}
-
-void at91_serial1_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *)ATMEL_BASE_PMC;
-
-	at91_set_a_periph(AT91_PIO_PORTB, 20, PUP);		/* RXD1 */
-	at91_set_a_periph(AT91_PIO_PORTB, 21, 1);		/* TXD1 */
-	writel(1 << ATMEL_ID_USART1, &pmc->pcer);
-}
-
-void at91_serial2_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *)ATMEL_BASE_PMC;
-
-	at91_set_a_periph(AT91_PIO_PORTA, 22, PUP);		/* RXD2 */
-	at91_set_a_periph(AT91_PIO_PORTA, 23, 1);		/* TXD2 */
-	writel(1 << ATMEL_ID_USART2, &pmc->pcer);
-}
-
-void at91_seriald_hw_init(void)
-{
-	at91_set_a_periph(AT91_PIO_PORTA, 30, PUP);		/* DRXD */
-	at91_set_a_periph(AT91_PIO_PORTA, 31, 1);		/* DTXD */
-	/* writing SYS to PCER has no effect on AT91RM9200 */
-}

arch/arm/cpu/arm920t/at91/clock.c

@@ -1,157 +0,0 @@
-/*
- * [origin: Linux kernel linux/arch/arm/mach-at91/clock.c]
- *
- * Copyright (C) 2011 Andreas Bießmann
- * Copyright (C) 2005 David Brownell
- * Copyright (C) 2005 Ivan Kokshaysky
- * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/clk.h>
-
-#if !defined(CONFIG_AT91FAMILY)
-# error You need to define CONFIG_AT91FAMILY in your board config!
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static unsigned long at91_css_to_rate(unsigned long css)
-{
-	switch (css) {
-	case AT91_PMC_MCKR_CSS_SLOW:
-		return CONFIG_SYS_AT91_SLOW_CLOCK;
-	case AT91_PMC_MCKR_CSS_MAIN:
-		return gd->arch.main_clk_rate_hz;
-	case AT91_PMC_MCKR_CSS_PLLA:
-		return gd->arch.plla_rate_hz;
-	case AT91_PMC_MCKR_CSS_PLLB:
-		return gd->arch.pllb_rate_hz;
-	}
-
-	return 0;
-}
-
-#ifdef CONFIG_USB_ATMEL
-static unsigned at91_pll_calc(unsigned main_freq, unsigned out_freq)
-{
-	unsigned i, div = 0, mul = 0, diff = 1 << 30;
-	unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
-
-	/* PLL output max 240 MHz (or 180 MHz per errata) */
-	if (out_freq > 240000000)
-		goto fail;
-
-	for (i = 1; i < 256; i++) {
-		int diff1;
-		unsigned input, mul1;
-
-		/*
-		 * PLL input between 1MHz and 32MHz per spec, but lower
-		 * frequences seem necessary in some cases so allow 100K.
-		 * Warning: some newer products need 2MHz min.
-		 */
-		input = main_freq / i;
-		if (input < 100000)
-			continue;
-		if (input > 32000000)
-			continue;
-
-		mul1 = out_freq / input;
-		if (mul1 > 2048)
-			continue;
-		if (mul1 < 2)
-			goto fail;
-
-		diff1 = out_freq - input * mul1;
-		if (diff1 < 0)
-			diff1 = -diff1;
-		if (diff > diff1) {
-			diff = diff1;
-			div = i;
-			mul = mul1;
-			if (diff == 0)
-				break;
-		}
-	}
-	if (i == 256 && diff > (out_freq >> 5))
-		goto fail;
-	return ret | ((mul - 1) << 16) | div;
-fail:
-	return 0;
-}
-#endif
-
-static u32 at91_pll_rate(u32 freq, u32 reg)
-{
-	unsigned mul, div;
-
-	div = reg & 0xff;
-	mul = (reg >> 16) & 0x7ff;
-	if (div && mul) {
-		freq /= div;
-		freq *= mul + 1;
-	} else
-		freq = 0;
-
-	return freq;
-}
-
-int at91_clock_init(unsigned long main_clock)
-{
-	unsigned freq, mckr;
-	at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
-	unsigned tmp;
-	/*
-	 * When the bootloader initialized the main oscillator correctly,
-	 * there's no problem using the cycle counter.  But if it didn't,
-	 * or when using oscillator bypass mode, we must be told the speed
-	 * of the main clock.
-	 */
-	if (!main_clock) {
-		do {
-			tmp = readl(&pmc->mcfr);
-		} while (!(tmp & AT91_PMC_MCFR_MAINRDY));
-		tmp &= AT91_PMC_MCFR_MAINF_MASK;
-		main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16);
-	}
-#endif
-	gd->arch.main_clk_rate_hz = main_clock;
-
-	/* report if PLLA is more than mildly overclocked */
-	gd->arch.plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
-
-#ifdef CONFIG_USB_ATMEL
-	/*
-	 * USB clock init:  choose 48 MHz PLLB value,
-	 * disable 48MHz clock during usb peripheral suspend.
-	 *
-	 * REVISIT:  assumes MCK doesn't derive from PLLB!
-	 */
-	gd->arch.at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) |
-			     AT91_PMC_PLLBR_USBDIV_2;
-	gd->arch.pllb_rate_hz = at91_pll_rate(main_clock,
-					      gd->arch.at91_pllb_usb_init);
-#endif
-
-	/*
-	 * MCK and CPU derive from one of those primary clocks.
-	 * For now, assume this parentage won't change.
-	 */
-	mckr = readl(&pmc->mckr);
-	gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
-	freq = gd->arch.mck_rate_hz;
-
-	freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2));	/* prescale */
-	/* mdiv */
-	gd->arch.mck_rate_hz = freq /
-			(1 + ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
-	gd->arch.cpu_clk_rate_hz = freq;
-
-	return 0;
-}

arch/arm/cpu/arm920t/at91/cpu.c

@@ -1,26 +0,0 @@
-/*
- * [origin: arch/arm/cpu/arm926ejs/at91/cpu.c]
- *
- * (C) Copyright 2011
- * Andreas Bießmann, andreas.devel@googlemail.com
- * (C) Copyright 2010
- * Reinhard Meyer, reinhard.meyer@emk-elektronik.de
- * (C) Copyright 2009
- * Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/clk.h>
-
-#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
-#define CONFIG_SYS_AT91_MAIN_CLOCK 0
-#endif
-
-int arch_cpu_init(void)
-{
-	return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
-}

arch/arm/cpu/arm920t/at91/lowlevel_init.S

@@ -1,152 +0,0 @@
-/*
- * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
- *		       Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
- *
- * Modified for the at91rm9200dk board by
- * (C) Copyright 2004
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <config.h>
-
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_mc.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_pio.h>
-
-#define ARM920T_CONTROL	0xC0000000	/* @ set bit 31 (iA) and 30 (nF) */
-
-_MTEXT_BASE:
-#undef START_FROM_MEM
-#ifdef START_FROM_MEM
-	.word	CONFIG_SYS_TEXT_BASE-PHYS_FLASH_1
-#else
-	.word	CONFIG_SYS_TEXT_BASE
-#endif
-
-.globl lowlevel_init
-lowlevel_init:
-	ldr     r1, =AT91_ASM_PMC_MOR
-	/* Main oscillator Enable register */
-#ifdef CONFIG_SYS_USE_MAIN_OSCILLATOR
-	ldr     r0, =0x0000FF01		/* Enable main oscillator */
-#else
-	ldr     r0, =0x0000FF00		/* Disable main oscillator */
-#endif
-	str     r0, [r1] /*AT91C_CKGR_MOR] */
-	/* Add loop to compensate Main Oscillator startup time */
-	ldr     r0, =0x00000010
-LoopOsc:
-	subs    r0, r0, #1
-	bhi     LoopOsc
-
-	/* memory control configuration */
-	/* this isn't very elegant, but	 what the heck */
-	ldr	r0, =SMRDATA
-	ldr	r1, _MTEXT_BASE
-	sub	r0, r0, r1
-	ldr	r2, =SMRDATAE
-	sub	r2, r2, r1
-pllloop:
-	/* the address */
-	ldr	r1, [r0], #4
-	/* the value */
-	ldr	r3, [r0], #4
-	str	r3, [r1]
-	cmp	r2, r0
-	bne	pllloop
-	/* delay - this is all done by guess */
-	ldr	r0, =0x00010000
-	/* (vs reading PMC_SR for LOCKA, LOCKB ... or MOSCS earlier) */
-lock:
-	subs	r0, r0, #1
-	bhi	lock
-	ldr	r0, =SMRDATA1
-	ldr	r1, _MTEXT_BASE
-	sub	r0, r0, r1
-	ldr	r2, =SMRDATA1E
-	sub	r2, r2, r1
-sdinit:
-	/* the address */
-	ldr	r1, [r0], #4
-	/* the value */
-	ldr	r3, [r0], #4
-	str	r3, [r1]
-	cmp	r2, r0
-	bne	sdinit
-
-	/* switch from FastBus to Asynchronous clock mode */
-	mrc	p15, 0, r0, c1, c0, 0
-	orr	r0, r0, #ARM920T_CONTROL
-	mcr	p15, 0, r0, c1, c0, 0
-
-	/* everything is fine now */
-	mov	pc, lr
-
-	.ltorg
-
-SMRDATA:
-	.word AT91_ASM_MC_EBI_CFG
-	.word CONFIG_SYS_EBI_CFGR_VAL
-	.word AT91_ASM_MC_SMC_CSR0
-	.word CONFIG_SYS_SMC_CSR0_VAL
-	.word AT91_ASM_PMC_PLLAR
-	.word CONFIG_SYS_PLLAR_VAL
-	.word AT91_ASM_PMC_PLLBR
-	.word CONFIG_SYS_PLLBR_VAL
-	.word AT91_ASM_PMC_MCKR
-	.word CONFIG_SYS_MCKR_VAL
-SMRDATAE:
-	/* here there's a delay */
-SMRDATA1:
-	.word AT91_ASM_PIOC_ASR
-	.word CONFIG_SYS_PIOC_ASR_VAL
-	.word AT91_ASM_PIOC_BSR
-	.word CONFIG_SYS_PIOC_BSR_VAL
-	.word AT91_ASM_PIOC_PDR
-	.word CONFIG_SYS_PIOC_PDR_VAL
-	.word AT91_ASM_MC_EBI_CSA
-	.word CONFIG_SYS_EBI_CSA_VAL
-	.word AT91_ASM_MC_SDRAMC_CR
-	.word CONFIG_SYS_SDRC_CR_VAL
-	.word AT91_ASM_MC_SDRAMC_MR
-	.word CONFIG_SYS_SDRC_MR_VAL
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
-	.word AT91_ASM_MC_SDRAMC_MR
-	.word CONFIG_SYS_SDRC_MR_VAL1
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
-	.word AT91_ASM_MC_SDRAMC_MR
-	.word CONFIG_SYS_SDRC_MR_VAL2
-	.word CONFIG_SYS_SDRAM1
-	.word CONFIG_SYS_SDRAM_VAL
-	.word AT91_ASM_MC_SDRAMC_TR
-	.word CONFIG_SYS_SDRC_TR_VAL
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
-	.word AT91_ASM_MC_SDRAMC_MR
-	.word CONFIG_SYS_SDRC_MR_VAL3
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
-SMRDATA1E:
-	/* SMRDATA1 is 176 bytes long */
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */

arch/arm/cpu/arm920t/at91/reset.c

@@ -1,41 +0,0 @@
-/*
- * (C) Copyright 2002
- * Lineo, Inc. <www.lineo.com>
- * Bernhard Kuhn <bkuhn@lineo.com>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_st.h>
-
-void  __attribute__((weak)) board_reset(void)
-{
-	/* true empty function for defining weak symbol */
-}
-
-void reset_cpu(ulong ignored)
-{
-	at91_st_t *st = (at91_st_t *) ATMEL_BASE_ST;
-
-	board_reset();
-
-	/* Reset the cpu by setting up the watchdog timer */
-	writel(AT91_ST_WDMR_RSTEN | AT91_ST_WDMR_EXTEN | AT91_ST_WDMR_WDV(2),
-		&st->wdmr);
-	writel(AT91_ST_CR_WDRST, &st->cr);
-	/* and let it timeout */
-	while (1)
-		;
-	/* Never reached */
-}

arch/arm/cpu/arm920t/at91/timer.c

@@ -1,127 +0,0 @@
-/*
- * (C) Copyright 2002
- * Lineo, Inc. <www.lineo.com>
- * Bernhard Kuhn <bkuhn@lineo.com>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_tc.h>
-#include <asm/arch/at91_pmc.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* the number of clocks per CONFIG_SYS_HZ */
-#define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK/CONFIG_SYS_HZ)
-
-int timer_init(void)
-{
-	at91_tc_t *tc = (at91_tc_t *) ATMEL_BASE_TC;
-	at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
-	/* enables TC1.0 clock */
-	writel(1 << ATMEL_ID_TC0, &pmc->pcer);	/* enable clock */
-
-	writel(0, &tc->bcr);
-	writel(AT91_TC_BMR_TC0XC0S_NONE | AT91_TC_BMR_TC1XC1S_NONE |
-		AT91_TC_BMR_TC2XC2S_NONE , &tc->bmr);
-
-	writel(AT91_TC_CCR_CLKDIS, &tc->tc[0].ccr);
-	/* set to MCLK/2 and restart the timer
-	when the value in TC_RC is reached */
-	writel(AT91_TC_CMR_TCCLKS_CLOCK1 | AT91_TC_CMR_CPCTRG, &tc->tc[0].cmr);
-
-	writel(0xFFFFFFFF, &tc->tc[0].idr); /* disable interrupts */
-	writel(TIMER_LOAD_VAL, &tc->tc[0].rc);
-
-	writel(AT91_TC_CCR_SWTRG | AT91_TC_CCR_CLKEN, &tc->tc[0].ccr);
-	gd->arch.lastinc = 0;
-	gd->arch.tbl = 0;
-
-	return 0;
-}
-
-/*
- * timer without interrupts
- */
-ulong get_timer(ulong base)
-{
-	return get_timer_masked() - base;
-}
-
-void __udelay(unsigned long usec)
-{
-	udelay_masked(usec);
-}
-
-ulong get_timer_raw(void)
-{
-	at91_tc_t *tc = (at91_tc_t *) ATMEL_BASE_TC;
-	u32 now;
-
-	now = readl(&tc->tc[0].cv) & 0x0000ffff;
-
-	if (now >= gd->arch.lastinc) {
-		/* normal mode */
-		gd->arch.tbl += now - gd->arch.lastinc;
-	} else {
-		/* we have an overflow ... */
-		gd->arch.tbl += now + TIMER_LOAD_VAL - gd->arch.lastinc;
-	}
-	gd->arch.lastinc = now;
-
-	return gd->arch.tbl;
-}
-
-ulong get_timer_masked(void)
-{
-	return get_timer_raw()/TIMER_LOAD_VAL;
-}
-
-void udelay_masked(unsigned long usec)
-{
-	u32 tmo;
-	u32 endtime;
-	signed long diff;
-
-	tmo = CONFIG_SYS_HZ_CLOCK / 1000;
-	tmo *= usec;
-	tmo /= 1000;
-
-	endtime = get_timer_raw() + tmo;
-
-	do {
-		u32 now = get_timer_raw();
-		diff = endtime - now;
-	} while (diff >= 0);
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-	return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
-	return CONFIG_SYS_HZ;
-}

arch/arm/cpu/arm920t/config.mk

@@ -1,15 +0,0 @@
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-PLATFORM_CPPFLAGS += -march=armv4
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# =========================================================================
-PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
-PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)

arch/arm/cpu/arm920t/cpu.c

@@ -1,48 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * CPU specific code
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/system.h>
-
-static void cache_flush(void);
-
-int cleanup_before_linux (void)
-{
-	/*
-	 * this function is called just before we call linux
-	 * it prepares the processor for linux
-	 *
-	 * we turn off caches etc ...
-	 */
-
-	disable_interrupts ();
-
-	/* turn off I/D-cache */
-	icache_disable();
-	dcache_disable();
-	/* flush I/D-cache */
-	cache_flush();
-
-	return 0;
-}
-
-/* flush I/D-cache */
-static void cache_flush (void)
-{
-	unsigned long i = 0;
-
-	asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));
-}

arch/arm/cpu/arm920t/ep93xx/Makefile

@@ -1,41 +0,0 @@
-#
-# Cirrus Logic EP93xx CPU-specific Makefile
-#
-# Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
-#
-# Copyright (C) 2004, 2005
-# Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
-#
-# Copyright (C) 2006
-# Dominic Rath <Dominic.Rath@gmx.de>
-#
-# Based on an original Makefile, which is
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)lib$(SOC).o
-
-COBJS   = cpu.o led.o speed.o timer.o
-SOBJS   = lowlevel_init.o
-
-SRCS    := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS    := $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-all:    $(obj).depend $(LIB)
-
-$(LIB): $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################

arch/arm/cpu/arm920t/ep93xx/cpu.c

@@ -1,37 +0,0 @@
-/*
- * Cirrus Logic EP93xx CPU-specific support.
- *
- * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
- *
- * Copyright (C) 2004, 2005
- * Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/ep93xx.h>
-#include <asm/io.h>
-
-/* We reset the CPU by generating a 1-->0 transition on DeviceCfg bit 31. */
-extern void reset_cpu(ulong addr)
-{
-	struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
-	uint32_t value;
-
-	/* Unlock DeviceCfg and set SWRST */
-	writel(0xAA, &syscon->sysswlock);
-	value = readl(&syscon->devicecfg);
-	value |= SYSCON_DEVICECFG_SWRST;
-	writel(value, &syscon->devicecfg);
-
-	/* Unlock DeviceCfg and clear SWRST */
-	writel(0xAA, &syscon->sysswlock);
-	value = readl(&syscon->devicecfg);
-	value &= ~SYSCON_DEVICECFG_SWRST;
-	writel(value, &syscon->devicecfg);
-
-	/* Dying... */
-	while (1)
-		; /* noop */
-}

arch/arm/cpu/arm920t/ep93xx/led.c

@@ -1,85 +0,0 @@
-/*
- * Copyright (C) 2010, 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <asm/io.h>
-#include <asm/arch/ep93xx.h>
-#include <config.h>
-#include <status_led.h>
-
-static uint8_t saved_state[2] = {STATUS_LED_OFF, STATUS_LED_OFF};
-static uint32_t gpio_pin[2] = {1 << STATUS_LED_GREEN,
-			       1 << STATUS_LED_RED};
-
-inline void switch_LED_on(uint8_t led)
-{
-	register struct gpio_regs *gpio = (struct gpio_regs *)GPIO_BASE;
-
-	writel(readl(&gpio->pedr) | gpio_pin[led], &gpio->pedr);
-	saved_state[led] = STATUS_LED_ON;
-}
-
-inline void switch_LED_off(uint8_t led)
-{
-	register struct gpio_regs *gpio = (struct gpio_regs *)GPIO_BASE;
-
-	writel(readl(&gpio->pedr) & ~gpio_pin[led], &gpio->pedr);
-	saved_state[led] = STATUS_LED_OFF;
-}
-
-void red_led_on(void)
-{
-	switch_LED_on(STATUS_LED_RED);
-}
-
-void red_led_off(void)
-{
-	switch_LED_off(STATUS_LED_RED);
-}
-
-void green_led_on(void)
-{
-	switch_LED_on(STATUS_LED_GREEN);
-}
-
-void green_led_off(void)
-{
-	switch_LED_off(STATUS_LED_GREEN);
-}
-
-void __led_init(led_id_t mask, int state)
-{
-	__led_set(mask, state);
-}
-
-void __led_toggle(led_id_t mask)
-{
-	if (STATUS_LED_RED == mask) {
-		if (STATUS_LED_ON == saved_state[STATUS_LED_RED])
-			red_led_off();
-		else
-			red_led_on();
-	} else if (STATUS_LED_GREEN == mask) {
-		if (STATUS_LED_ON == saved_state[STATUS_LED_GREEN])
-			green_led_off();
-		else
-			green_led_on();
-	}
-}
-
-void __led_set(led_id_t mask, int state)
-{
-	if (STATUS_LED_RED == mask) {
-		if (STATUS_LED_ON == state)
-			red_led_on();
-		else
-			red_led_off();
-	} else if (STATUS_LED_GREEN == mask) {
-		if (STATUS_LED_ON == state)
-			green_led_on();
-		else
-			green_led_off();
-	}
-}

arch/arm/cpu/arm920t/ep93xx/lowlevel_init.S

@@ -1,49 +0,0 @@
-/*
- * Low-level initialization for EP93xx
- *
- * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
- *
- * Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <version.h>
-#include <asm/arch/ep93xx.h>
-
-.globl lowlevel_init
-lowlevel_init:
-	/* backup return address */
-	ldr r1, =SYSCON_SCRATCH0
-	str lr, [r1]
-
-	/* Turn on both LEDs */
-	bl red_led_on
-	bl green_led_on
-
-	/* Configure flash wait states before we switch to the PLL */
-	bl flash_cfg
-
-	/* Set up PLL */
-	bl pll_cfg
-
-	/* Turn off the Green LED and leave the Red LED on */
-	bl green_led_off
-
-	/* Setup SDRAM */
-	bl sdram_cfg
-
-	/* Turn on Green LED, Turn off the Red LED */
-	bl green_led_on
-	bl red_led_off
-
-	/* FIXME: we use async mode for now */
-	mrc p15, 0, r0, c1, c0, 0
-	orr r0, r0, #0xc0000000
-	mcr p15, 0, r0, c1, c0, 0
-
-	/* restore return address */
-	ldr r1, =SYSCON_SCRATCH0
-	ldr lr, [r1]
-
-	mov pc, lr

arch/arm/cpu/arm920t/ep93xx/speed.c

@@ -1,96 +0,0 @@
-/*
- * Cirrus Logic EP93xx PLL support.
- *
- * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/ep93xx.h>
-#include <asm/io.h>
-#include <div64.h>
-
-/*
- * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
- *
- * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
- * the specified bus in HZ.
- */
-
-/*
- * return the PLL output frequency
- *
- * PLL rate = CONFIG_SYS_CLK_FREQ * (X1FBD + 1) * (X2FBD + 1)
- * / (X2IPD + 1) / 2^PS
- */
-static ulong get_PLLCLK(uint32_t *pllreg)
-{
-	uint8_t i;
-	const uint32_t clkset = readl(pllreg);
-	uint64_t rate = CONFIG_SYS_CLK_FREQ;
-	rate *= ((clkset >> SYSCON_CLKSET_PLL_X1FBD1_SHIFT) & 0x1f) + 1;
-	rate *= ((clkset >> SYSCON_CLKSET_PLL_X2FBD2_SHIFT) & 0x3f) + 1;
-	do_div(rate, (clkset  & 0x1f) + 1);			/* X2IPD */
-	for (i = 0; i < ((clkset >> SYSCON_CLKSET_PLL_PS_SHIFT) & 3); i++)
-		rate >>= 1;
-
-	return (ulong)rate;
-}
-
-/* return FCLK frequency */
-ulong get_FCLK()
-{
-	const uint8_t fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 };
-	struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
-
-	const uint32_t clkset1 = readl(&syscon->clkset1);
-	const uint8_t fclk_div =
-		fclk_divisors[(clkset1 >> SYSCON_CLKSET1_FCLK_DIV_SHIFT) & 7];
-	const ulong fclk_rate = get_PLLCLK(&syscon->clkset1) / fclk_div;
-
-	return fclk_rate;
-}
-
-/* return HCLK frequency */
-ulong get_HCLK(void)
-{
-	const uint8_t hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 };
-	struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
-
-	const uint32_t clkset1 = readl(&syscon->clkset1);
-	const uint8_t hclk_div =
-		hclk_divisors[(clkset1 >> SYSCON_CLKSET1_HCLK_DIV_SHIFT) & 7];
-	const ulong hclk_rate = get_PLLCLK(&syscon->clkset1) / hclk_div;
-
-	return hclk_rate;
-}
-
-/* return PCLK frequency */
-ulong get_PCLK(void)
-{
-	const uint8_t pclk_divisors[] = { 1, 2, 4, 8 };
-	struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
-
-	const uint32_t clkset1 = readl(&syscon->clkset1);
-	const uint8_t pclk_div =
-		pclk_divisors[(clkset1 >> SYSCON_CLKSET1_PCLK_DIV_SHIFT) & 3];
-	const ulong pclk_rate = get_HCLK() / pclk_div;
-
-	return pclk_rate;
-}
-
-/* return UCLK frequency */
-ulong get_UCLK(void)
-{
-	struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
-	ulong uclk_rate;
-
-	const uint32_t value = readl(&syscon->pwrcnt);
-	if (value & SYSCON_PWRCNT_UART_BAUD)
-		uclk_rate = CONFIG_SYS_CLK_FREQ;
-	else
-		uclk_rate = CONFIG_SYS_CLK_FREQ / 2;
-
-	return uclk_rate;
-}

arch/arm/cpu/arm920t/ep93xx/timer.c

@@ -1,120 +0,0 @@
-/*
- * Cirrus Logic EP93xx timer support.
- *
- * Copyright (C) 2009, 2010 Matthias Kaehlcke <matthias@kaehlcke.net>
- *
- * Copyright (C) 2004, 2005
- * Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
- *
- * Based on the original intr.c Cirrus Logic EP93xx Rev D. interrupt support,
- * author unknown.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/types.h>
-#include <asm/arch/ep93xx.h>
-#include <asm/io.h>
-#include <div64.h>
-
-#define TIMER_CLKSEL	(1 << 3)
-#define TIMER_ENABLE	(1 << 7)
-
-#define TIMER_FREQ			508469		/* ticks / second */
-#define TIMER_MAX_VAL			0xFFFFFFFF
-
-static struct ep93xx_timer
-{
-	unsigned long long ticks;
-	unsigned long last_read;
-} timer;
-
-static inline unsigned long long usecs_to_ticks(unsigned long usecs)
-{
-	unsigned long long ticks = (unsigned long long)usecs * TIMER_FREQ;
-	do_div(ticks, 1000 * 1000);
-
-	return ticks;
-}
-
-static inline void read_timer(void)
-{
-	struct timer_regs *timer_regs = (struct timer_regs *)TIMER_BASE;
-	const unsigned long now = TIMER_MAX_VAL - readl(&timer_regs->timer3.value);
-
-	if (now >= timer.last_read)
-		timer.ticks += now - timer.last_read;
-	else
-		/* an overflow occurred */
-		timer.ticks += TIMER_MAX_VAL - timer.last_read + now;
-
-	timer.last_read = now;
-}
-
-/*
- * Get the number of ticks (in CONFIG_SYS_HZ resolution)
- */
-unsigned long long get_ticks(void)
-{
-	unsigned long long sys_ticks;
-
-	read_timer();
-
-	sys_ticks = timer.ticks * CONFIG_SYS_HZ;
-	do_div(sys_ticks, TIMER_FREQ);
-
-	return sys_ticks;
-}
-
-unsigned long get_timer_masked(void)
-{
-	return get_ticks();
-}
-
-unsigned long get_timer(unsigned long base)
-{
-	return get_timer_masked() - base;
-}
-
-void __udelay(unsigned long usec)
-{
-	unsigned long long target;
-
-	read_timer();
-
-	target = timer.ticks + usecs_to_ticks(usec);
-
-	while (timer.ticks < target)
-		read_timer();
-}
-
-int timer_init(void)
-{
-	struct timer_regs *timer_regs = (struct timer_regs *)TIMER_BASE;
-
-	/* use timer 3 with 508KHz and free running, not enabled now */
-	writel(TIMER_CLKSEL, &timer_regs->timer3.control);
-
-	/* set initial timer value */
-	writel(TIMER_MAX_VAL, &timer_regs->timer3.load);
-
-	/* Enable the timer */
-	writel(TIMER_ENABLE | TIMER_CLKSEL,
-		&timer_regs->timer3.control);
-
-	/* Reset the timer */
-	read_timer();
-	timer.ticks = 0;
-
-	return 0;
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-unsigned long get_tbclk(void)
-{
-	return CONFIG_SYS_HZ;
-}

arch/arm/cpu/arm920t/ep93xx/u-boot.lds

@@ -1,54 +0,0 @@
-/*
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN(4);
-	.text      :
-	{
-		*(.__image_copy_start)
-	  arch/arm/cpu/arm920t/start.o	(.text*)
-		/* the EP93xx expects to find the pattern 'CRUS' at 0x1000 */
-	  . = 0x1000;
-	  LONG(0x53555243)
-	  *(.text*)
-	}
-
-	. = ALIGN(4);
-	.rodata : { *(.rodata*) }
-
-	. = ALIGN(4);
-	.data : { *(.data*) }
-
-	. = ALIGN(4);
-	.got : { *(.got) }
-
-	. = .;
-
-	. = ALIGN(4);
-	.u_boot_list : {
-		KEEP(*(SORT(.u_boot_list*)));
-	}
-
-	. = ALIGN(4);
-
-	.image_copy_end :
-	{
-		*(.__image_copy_end)
-	}
-
-	__bss_start = .;
-	.bss : { *(.bss*) }
-	__bss_end = .;
-
-	_end = .;
-}