Build from OPTEE commit in develop-next branch:
7ef2a818a5 rk3588: otp: set life cycle to provisioned when writing otp key3
Update features:
7ef2a818a5 rk3588: otp: set life cycle to provisioned when writing otp key3
91c4147e75 pta: crypto_service: change some return code to be accurate
3167e37331 drivers: rockchip: hal_crypto: mask lockstep interrupt
911282ad2b plat-rockchip: rk3588: add for init HDCP key by keylad
Signed-off-by: xb.wang <xb.wang@rock-chips.com>
Change-Id: Ieab9c39458c1986ccd0cf8633098f76dc43a4b7b
from commit:
f04a3d: platform: rk3588: pmu os reg change to pmu0.
update feature:
Support spiflash.
Change-Id: I396e408307061c059c32292c3264c35faf6169f6
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Build from ATF commit:
b5f843fe1 plat: rockchip: rk3588: Don't change clock source to gpll when use pvtpll
update feature:
b5f843fe1 plat: rockchip: rk3588: Don't change clock source to gpll when use pvtpll
3c0a51aa4 plat: rockchip: rk3588: scmi: Add pvtpll config for cpul and dsu
5cc577ea0 plat: rockchip: rk3588: Add support set intermediate rate for npu
a029dd681 plat: rockchip: rk3588: Add support set intermediate rate for gpu
fdaa54cbb plat: rockchip: rk3588: Add support set intermediate rate for cpub
90c6c51f7 plat: rockchip: rk3588: Set gpll source clock div to 0
5ac4bc169 plat: rk3588: support vpu reset
00ba5738d plat: rk3588: support stop cpu
Change-Id: I3cbf062958c3a78526de5a4cf6df4b94e5b5b9a3
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
from commit:
rk_boot_all: c7de69a673: rk3326s: add usb phy tuning
update feature:
support rk3326s.
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: Icc5fd6153df1f18d02a58b6f0862fb2c2b457918
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Build from OPTEE commit:
c1514b9e rockchip: rv1126: fastboot: update mmu map table
update feature:
c1514b9e rockchip: rv1126: fastboot: update mmu map table
3ff3b774 rv1126: fix build error without ta
bea79573
700bd12a
40f5fcb2 pta: uboot_storedata: check the value of size when read head
cef03957 otp_support: add func to get ta encryption key
994a45d4 BACKPORT: core: add framework to load REE-FS encrypted TAs
1276ad6e pta: add support for write TA encryption key
2f186b1c core: supply hash length for salt length in rockchip and oem verify
c8e0eeb3 core: arm: support Thumb entry point
416c89b5 rockchip: sip: add share mem page type define
61053b11 rv1126: monitor: don't panic if cpu_feature err
b500cf9c rv1126: monitor: motify some debug code
a53a7d99 rv1126: only register fiq_cpu_stop_handler one time
cab1372b plat-rockchip: only register fiq_debugger_irq_handler one time
9c3b5fd9 plat-rockchip: map TEE_PLAT_SHMEM as MEM_AREA_RAM_NSEC
8cd72983 rv1126: fix macro RG_MAP_SECURE
ef89b5c2 rockchip: fix err of parsing ddr_parameter
2c6573a7 rockchip: rv1126: fix error of parenthesis matching in sgrf_init
1e75c939 plat-rockchip: fiq-debugger: adjust the usage of fiq_debugger.tgt_cpu
9f935616 pta: unnecessary to free share memory when close session
7fcbc47e plat-rockchip: fix CFG_RK_STATIC_MEM_PARAM define err
d9140b1b rv1126: conf.mk: use atags to pass parameter
715df903 plat-rockchip: conf.mk: enable CFG_RK_RPMB_NO_DIRF_HASH
59d68db8 rv1126: modify otp size for oem
10ff881f scripts: modify supported platforms
ee120571 rv1126: conf.mk: enable CFG_VENDOR_PROPS
e4d16707 plat-rockchip: vendor_props: add needed head files
5da82304 rv1126: support get seed for vendor props
1e6e6afa rv1126: pta: support write toybrick seed
36e572e8 rv1126: pta: support R&W attribute hash and vbootkey hash
867c532c plat-rockchip: rv1126: dmc: add support lp4x
8fc0f55b plat-rockchip: rv1126: dmc: fix MR14 setting err for lp4
4a1a9c4d plat-rockchip: common: dram: add LP4x support
23f06a39 rockchip: rv1126: don't close usb powerdomain when suspend
36d1043e plat-rockchip: rv1126: dmc: remove dsmpd when pll setting
44c0c0f1 rockchip: rv1126: support suspend from uboot
6ae5d629
380b79bf
e3cdf903 rv1126: otp: oem ns-otp prog mask value rely on ns-otp[504-511]
d4636cc1 rv1126: pta: add support for R&W oem OTP
Change-Id: Ie6156f1cc81fc3cea0efe17e7e9dfcecf262b061
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
1.uploading sign_tool in c++
2.support to sign by key in the server
3.support to verify signed file in local
Signed-off-by: liuyi <liuyi@rock-chips.com>
Change-Id: I19456f8d2c4be1d0929ec022012d4b0e59f0d60c
1.delete rk_sign_tool and library in python
2.prepare for uploading sign_tool in c++
Signed-off-by: liuyi <liuyi@rock-chips.com>
Change-Id: I12766d6715e8f9bb647479690358ddec4ec032c5
1.add IDB_PATH in the OUTPUT section
2.add CREATE_IDB in the FLAG section
3.support to create idblock binary during packing loader
Signed-off-by: liuyi <liuyi@rock-chips.com>
Change-Id: Ic8b1f5eef0151e5813ec0493c6bc6ef6490768d0
Build from ATF commit:
bc02fdb23 plat: rk3588: support booting from the cpu according to atags.
Update feature:
bc02fdb23 plat: rk3588: support booting from the cpu according to atags.
3f58c537b rockchip: common: Add boot1 param for atags
a8b89552b plat: rockchip: rk3588: dmc: ddr_m0: fix the mistake about idle_ddrsch
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I98cebd043832600634aa37fcb55eedccd78256ff
build from:
bdb740d4da rockchip: board: update with new envf support
build command:
./make.sh rk3588
update feature:
clk: rockchip: rk3588: set b0pll b1pll to 1200M in SPL
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Iafdd118cb70d363d636803c06b25f90140a1d290
The WORD_2[4:0] is used to assign boot cpu hwid,
ie. 0, 1, 2 ... 31, etc.
This feature depends on:
(d7ff10e rk3588: ddr: update ddr bin to v1.06)
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I9675f6eae088dc2d55bf172774806648ba86e668
Build from OPTEE commit in develop-next branch:
9d22c1e96 rk3588: support R&W oem ns otp
Update features:
9d22c1e96 rk3588: support R&W oem ns otp
3f0f0b052 pta: support check oem otp key is written
Signed-off-by: Hisping Lin <hisping.lin@rock-chips.com>
Change-Id: I7fb445fb1202e32ddbbc37cde78ccac79b5e8c32
build from RK3326_DDR_Init_Simple:
c8ac34ce rk3326/rk3326-s: Update DDR bin to V2.04 20220121
update feature:
255e5ca0 rk3326/rk3326-s: Set dfi_lp_wakeup_sr/pd to 0x0
Signed-off-by: Wesley Yao <wesley.yao@rock-chips.com>
Change-Id: I267bf5c6c1389695112b665371d57fccadb9a5d4
build from RK3326_DDR_Init_Simple:
980d865192 rk3326/rk3326-s: Update DDR bin to V2.03 20220121
update feature:
da0ff2abaa rk3326-s: Set ca_odt(REG0x40[13:12]) of LPDDR4 according to bw
Signed-off-by: Wesley Yao <wesley.yao@rock-chips.com>
Change-Id: I3b8f9bcf96841815b88e3772d7a3a808eb2435d5
Build from ATF commit:
378cb8595 plat: rockchip: rk3588: dmc: support ddr frequency scan after dmc resume
The ATF code for this version is same with The ATF code for v1.12.
Change-Id: Ibdf3603321ed5155c7623bfcf9b2200a3af45a81
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
build from RK3326_DDR_Init_Simple:
d6f4cb05c9 rk3326/rk3326-s: Update DDR bin to V2.02 20220118
update feature:
6faa6a326a rk3326-s: Set VDD_logic to 1.0V
8e81392239 rk3326-s: Disable some low power functions to prevent sleep and resume
(level 2) fail
9590d94add px30s: can not support row = 17 of lp4
c699c118bb px30s: modify dfi_tlp_resp to 0xa
df3d5d15fc px30s: modify vdd_logic to 0.9v
0fa00910a4 px30s: clear ddr clk gate for soft reset
08f7c28847 rk3326/rk3326s: Optimize the size of ddr bin
153b747d5f rk3326-s: Fix get_uboot_params() when sdram_params->ch.row_3_4 == 1
3b83b56391 rk3326s: set logic to 1.0V
a8eced54fb rk3326/s: all dram bring up ok
b280140e97 rk3326/s: add debug info
c4b391e8b4 rk3326/rk3326s: modify dfi timing for lp3/2
cec9c2868b rk3326/rk3326s: diff dfi tctrl_delay setting
de967f4b65 rk3326/rk3326s: modify dfi timing
fa9c9e3f4f rk3326s: add fix drv odt config
c534fef2c6 rk3326s: add support lp4
69776fa864 rk3326: inc: add rk3326s phy reg
3a1078c07d RK3326S: modify to PHY_REG_3326S define
fc7426a9a7 rk3326/S: save and restore arm special reg
2651ce4f97 rk3326/S: add check return to smc code
Signed-off-by: Wesley Yao <wesley.yao@rock-chips.com>
Change-Id: Id91158b3d6decc57366dc3259e232f24da6b64ce
Build from OPTEE commit in develop-next branch:
631d7ed9a pta: modify secure boot enable flag for rk3568
Update features:
631d7ed9a pta: modify secure boot enable flag for rk3568
be93c3390 Revert "pta: modify secure boot enable flag length for rk3568"
3f0f0b052 pta: support check oem otp key is written
Signed-off-by: Hisping Lin <hisping.lin@rock-chips.com>
Change-Id: I3e8f84e6c20bf452ce486e61f3ac63f64e80239e
build from:
74cb20d2b7 rk3588: ddr: update ddr bin to v1.04
build command:
./make.sh rk3588
update feature:
9ff0a6b00f rk3588: ddr: phy preset assert time add to 10us
5b8bbbb17c rk3588: ddr: ddr useful address 1MB align for kernel
c573e8eee3 rk3588: ddr: set EN_LOW_POWER(0) to disable dfi lp cfg
39846fffa8 rk3588: ddr: enable change frequency for LPDDR4
363a13da91 rk3588: ddr: fix the code about test for DFS/SUSPEND/REBOOT
65dd9468d2 rk3588: ddr: set DFILPCFG0.dfi_lp_en_data to 0
574deae90a rk3588: ddr: add memset for sdram_params_fsp in ddr_set_rate
4872d02a4e rk3588: ddr: enable PHY VTC at any frequency
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Change-Id: Id4854bed49b79eae8947952f46892b8d10ef0f0c
