Build from OPTEE commit:
0d6fb9bf 48M mini mem
Change-Id: I48bb4de47e52d8e7469d28baece9cd7e702b479d
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
print info: DDR Version 1.18 20210602
from commit:
98b32cf rk322xh: update DDR Version 1.18 20210602
update feature:
add limit ddr max freq to 533MHz for bin1 chip.
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
Change-Id: Ia309ef21fbf406c9f487517960e03dd8e8dd30db
Build from OPTEE commit:
61053b11
update feature:
61053b11
b500cf9c
a53a7d99 rv1126: only register fiq_cpu_stop_handler one time
cab1372b plat-rockchip: only register fiq_debugger_irq_handler one time
9c3b5fd9 plat-rockchip: map TEE_PLAT_SHMEM as MEM_AREA_RAM_NSEC
Change-Id: I4ee2f50a1b5b80a629359190280210db352ea673
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
Build from ATF commit:
2f70923a2 plat: rk3568: clean all ipd before starting the transfer
update feature:
2f70923a2 plat: rk3568: clean all ipd before starting the transfer
53499c5e6 plat: rk3568: rk_i2c_uninit has been called by the next i2c operation
05988ebe1 plat: rockchip: common: add share mem page type define
4c2797c7e plat: rk3568: dmc: fix RX Vref calc err when updata drv odt
0f7c02de8 plat: rk3568: dump wakeup pin number
3493ed30b plat: rk3568: add clk_scmi_ddr
fbc892360 plat: rk3568: support virtual poweroff
23bfcc0d6 plat: rk3568: support uboot charge low power mode
7bc959925 plat: rk3568: dmc: update version to V1.01 and add ddr_get_freq_info
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ic730290cde7f9b230c88cf2461bb976b85f5c46c
build from:
d66fc41e9c rk356x: ddr: update ddr bin to v1.09
build command:
./make.sh rk3568
update feature:
74bdef59fd rk356x: ddr: add 3568s/m/j/b2 support
3220a096ba rk356x: ddr: adjust print info
7dc3ec451a rk356x: ddr: fix reg_*_*_rxen_lp4 bug
b16ddd2a97 rk356x: ddr: allow user program otp in the user area
de4ccf565f rk356x: ddr: fix lpddr4/4x WDQS bug
dd0befbb88 rk356x: ddr: disable cs1/cs3 ca odt
f8c5ebd50e rk356x: ddr: add lpddr4 byte mode support
18225d611d rk356x: ddr: modify trfc base on real capacity
7e7f62e1e7 rk356x: ddr: auto detect 4 ch lpddr4/4x.
db9aecc5ae rk356x: ddr: add more ddrconf support move to highest 256MB
5ee3419e72 rk356x: ddr: only support 4GB map to high 8GB-256MB
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
Change-Id: I0ecc0f69dd97598f45619d486fa732aab99544dc
build from:
d66fc41e9c rk356x: ddr: update ddr bin to v1.09
build command:
./make.sh rk3568
update feature:
74bdef59fd rk356x: ddr: add 3568s/m/j/b2 support
3220a096ba rk356x: ddr: adjust print info
7dc3ec451a rk356x: ddr: fix reg_*_*_rxen_lp4 bug
b16ddd2a97 rk356x: ddr: allow user program otp in the user area
de4ccf565f rk356x: ddr: fix lpddr4/4x WDQS bug
dd0befbb88 rk356x: ddr: disable cs1/cs3 ca odt
f8c5ebd50e rk356x: ddr: add lpddr4 byte mode support
18225d611d rk356x: ddr: modify trfc base on real capacity
7e7f62e1e7 rk356x: ddr: auto detect 4 ch lpddr4/4x.
db9aecc5ae rk356x: ddr: add more ddrconf support move to highest 256MB
5ee3419e72 rk356x: ddr: only support 4GB map to high 8GB-256MB
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
Change-Id: Ifc726aaf94150b9ce2841eb71ff388c7642a5e50
build from next-dev:
b1b9d7fba4 drivers: ram: common: fix ssmod define err
update feature:
b1b9d7fba4 drivers: ram: common: fix ssmod define err
d49e7c3403 drivers: ram: rv1126: fix the judgment of "set ctl address map fail"
06a17b4adf drivers: ram: rv1126: Turn on DQS_c 2k pull-up resistor to workaround WDQS control of LPDDR4/LPDDR4X
246ad23dbf drivers: ram: rk356x: fix read_mr() of LPDDR3
e90784abb2 rv1126: ddr: fix tx dqs bypass phase setting err
c2a03d5d81 drivers: ram: rv1126: add support lpddr4x
bf922fc800 drivers: ram: rv1126: fix calculating of MSCH_DeviceSize
e2dc1cc022 drivers: ram: rv1126: Modify tRFC and related timing based on DDR capacity
330cd12fc3 drivers: ram: rv1126: fix return value of read_mr()
3993b0c711 drivers: ram: rv1126: Set default value of die bus with to x16 when bus width is x16/x32 of DDR3
9050e1f82e drivers: ram: rv1126: fix tZQLAT of LPDDR4
build command:
CONFIG_SPL_KERNEL_BOOT=y
for lpddr3 bin, CONFIG_ROCKCHIP_TPL_INIT_DRAM_TYPE need set to 6.
for lpddr4 bin, CONFIG_ROCKCHIP_TPL_INIT_DRAM_TYPE need set to 7.
default CONFIG_ROCKCHIP_DRAM_EXTENDED_TEMP_SUPPORT=n, if you need
extended temperature bin, you need enable "CONFIG_ROCKCHIP_DRAM\
_EXTENDED_TEMP_SUPPORT", then rebuild uboot.
./make.sh rv1126 && ./make.sh tpl.
Note:
the pre-build 528MHz binary disable ODT.
Change-Id: Ibb384f60d714535822202330d2c3ae3cef75337c
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
build from u-boot-ddr:
78270c3ffa dram_init: rv1126: update to v1.06
update feature:
d49e7c3403 drivers: ram: rv1126: fix the judgment of "set ctl
address map fail"
06a17b4adf drivers: ram: rv1126: Turn on DQS_c 2k pull-up
resistor to workaround WDQS control of LPDDR4/LPDDR4X
246ad23dbf drivers: ram: rk356x: fix read_mr() of LPDDR3
e90784abb2 rv1126: ddr: fix tx dqs bypass phase setting err
c2a03d5d81 drivers: ram: rv1126: add support lpddr4x
bf922fc800 drivers: ram: rv1126: fix calculating of
MSCH_DeviceSize
e2dc1cc022 drivers: ram: rv1126: Modify tRFC and related timing based on
DDR capacity
330cd12fc3 drivers: ram: rv1126: fix return value of read_mr()
3993b0c711 drivers: ram: rv1126: Set default value of die bus
with to x16 when bus width is x16/x32 of DDR3
9050e1f82e drivers: ram: rv1126: fix tZQLAT of LPDDR4
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
Change-Id: I053cb27d5addb4bb85dd88a7780049b95b991029
from commit: 98d5681 src: slc_flash: Support S34ML08G2
Change-Id: Ib95aa44b04c1a8ce1927a9bab10b04dbfb734a22
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Build from next-dev with command ./make.sh rk3566-eink
on-commit:
(74b82d9635 tools: rockchip: bmp2gray16: support eink power off logo)
Signed-off-by: Zorro Liu <lyx@rock-chips.com>
Change-Id: Iedb3768cd55c253a311dfd3a6ef9351ade96cc47
from commit: b651e66 src: spinand: Support new devices
Change-Id: I089c9ad80fa357612fa42fd7e23f50fd818c997f
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Build from ATF commit:
7bc959925 plat: rk3568: dmc: update version to V1.01 and add ddr_get_freq_info
update feature:
7bc959925 plat: rk3568: dmc: update version to V1.01 and add ddr_get_freq_info
d2e0ef53d plat: rk3568: select the default suspend 32k clock from the PVTM
f8297ce88 rockchip_exceptions: adjust the usage of uartdbg_uart_info.tgt_cpu
d053a1087 rockchip: fiq debugger: don't disable fiq if fiq from el2
354236216 rockchip_exceptions: save/restore el2 register if fiq-debugger from el2
02bab0c8f BACKPORT: lib: el3_runtime: Fix SPE system registers in el2_sysregs_context
2c7c36d92 plat: rk3568: support cache ecc.
cda1658bc plat: rk3568: config the pmugrf_reset_hold bit
c2d509965 plat: rk3568: save and restore PMUCRU_PMUCLKSEL_CON00
9b05de3a1 plat: rk3568: dump the wakeup irq
270aa3847 plat: rk3568: dmc: rectiyf LPDDR4 MR14 value
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I3e00968594fae0ceed781dbc130157b6d114cf76
Build from ATF commit:
dfd73e4 commit_elf.sh: use make.sh to compile out
the release version
update feature:
3479aa9 plat: rk322xh: remove ssmod and dsmpd when pll setting
5cb729f plat: rk322xh: init: config hdcp key
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
Change-Id: If8b92c809debb7681a715e35cea76a978a404fe9
build from:
b9e7e0b79c dram init: rk1808: update ddr bin version to v1.05
update feature:
375b118e2d drivers: ram: rk1808: add ssmod support
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
Change-Id: Idb9bdedbf9e9fcaf3ed80a7d38738b407feaa36c
pack Input: ./RKBOOT/RK3568MINIALL_RAMBOOT.ini
Traceback (most recent call last):
File "boot_merger.py", line 1062, in <module>
File "boot_merger.py", line 515, in boot_merger_main
File "boot_merger.py", line 281, in create_new_idblock
File "genericpath.py", line 50, in getsize
FileNotFoundError: [Errno 2] No such file or directory: 'bin/rk35/rk3568_ddr_1560MHz_v1.06.bin'
[12559] Failed to execute script boot_merger
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I626ed1af2199bb5cab13f6d8ad2ebe7b8bc8ce9b
Build from ATF commit:
6b10c1bb5 plat: rk3568: put status info in ultra_info()
update feature:
6b10c1bb5 plat: rk3568: put status info in ultra_info()
b834819eb plat: rk3568: disable pclk_stimer clk when VD_LOGIC keep on
34585499d plat: rk3568: disable gpio2B input_enable for reduce power
dissipation
8104e1d0f plat: rk3568: keep osc 24M on lite sleep only
f191f5d49 plat: rk3568: keep vd_logic on lite sleep only
Signed-off-by: Weixin Zhou <zwx@rock-chips.com>
Change-Id: I7733f5e5b83e1f48b5010917ce7975fdf75e86a7
Build from:
6b10c1bb5 plat: rk3568: put status info in ultra_info()
Update features:
6b10c1bb5 plat: rk3568: put status info in ultra_info()
b834819eb plat: rk3568: disable pclk_stimer clk when VD_LOGIC keep on
34585499d plat: rk3568: disable gpio2B input_enable for reduce power dissipation
8104e1d0f plat: rk3568: keep osc 24M on lite sleep only
f191f5d49 plat: rk3568: keep vd_logic on lite sleep only
ae0d3958f plat: rk3568: adjust npu pvtpll config
b86e22653 plat: rk3568: dmc: set ddr clock in phase when suspend
4f2434ad5 plat: rk3568: save/restore the clock gate contol
5803d89e7 plat: rk3568: add core_dbgprcr_pwrdown_wfi() for common
d17c40da3 plat: rk3568: dmc: setting clk_msch_div base on DPLL
405a815fd plat: rk3568: dmc: ignore CRU_DPLL_CON1.dsmpd when dfs
a5f3cd0d1 plat: rk3568: add ddr ecc support
1e9739b4e plat: rk3568: fix typo
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I36c4f37e80520556eaf04dd105e971de8e1ab2d6
