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315 Commits

Author SHA1 Message Date
Tom Rini
4459ed60cb Prepare v2023.10
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-10-02 10:39:59 -04:00
Tom Rini
ba6d575ee0 configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-10-02 10:35:27 -04:00
Bhupesh Sharma
f75bd201bf MAINTAINERS: ufs: Change Bhupesh's email address
Set my current personal email in the MAINTAINERS file.

Signed-off-by: Bhupesh Sharma <bhupesh.linux@gmail.com>
2023-09-30 15:09:44 -04:00
Tom Rini
2173c4a990 Merge tag 'u-boot-at91-fixes-2023.10-b' of https://source.denx.de/u-boot/custodians/u-boot-at91
Second set of u-boot-atmel fixes for the 2023.10 cycle:

Two small fixes , one for an array not initialized and the second one
fixes an error case when a DT property is missing for the atmel NAND
driver.
2023-09-29 10:40:34 -04:00
Francois Berder
7b4ffe8c32 clk: at91: Fix initializing arrays
Arrays are not cleared entirely because ARRAY_SIZE
returns the number of elements in an array, not the size
in bytes.
This commit fixes the calls to memset by providing the
array size in bytes instead of the number of elements
in the array.

Signed-off-by: Francois Berder <fberder@outlook.fr>
2023-09-29 16:45:40 +03:00
Tom Rini
87ebb54b9c Merge tag 'doc-2023-10-rc5-3' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request doc-2023-10-rc5-3

Documentation:

* describe that partition numbers are hexadecimal in load command
* remove obsolete half sentence in tools/binman/binman.rst
2023-09-29 07:49:57 -04:00
Tom Rini
a574e05d39 Merge branch '2023-09-28-assorted-minor-fixes'
- Fixes for two board builds and a script fix for many TI platforms
2023-09-29 07:49:24 -04:00
Heinrich Schuchardt
c65beebfae binman: doc: Remove incomplete sentence
This is the difference between version 1 and 2 of Massimo's patch:

binman: doc: fix reference tag placement for Logging section
v2: https://lore.kernel.org/u-boot/20230913161633.999542-1-massimo.pegorer+oss@gmail.com/
v1: https://lore.kernel.org/u-boot/20230909135235.21242-1-massimo.pegorer+oss@gmail.com/

Fixes: 0f40e23fd2 ("binman: add documentation for binman sign option")
Signed-off-by: Massimo Pegorer <massimo.pegorer+oss@gmail.com>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Massimo Pegorer <massimo.pegorer+oss@gmail.com>
2023-09-29 12:56:49 +02:00
Mickaël Tansorier
5bb1d1f9da doc: usage: load: document part as hexadecimal
`part` option is in hexadecimal, so information is missing in usage
documentation.

Callgraph for `part` parsing is :
do_load -> fs_set_blk_dev -> part_get_info_by_dev_and_name_or_num ->
blk_get_device_part_str -> hextoul (This is why it is hexadecimal)

Signed-off-by: Mickaël Tansorier <mickael.tansorier@smile.fr>
Reviewed-by: Yoann Congal <yoann.congal@smile.fr>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-09-29 12:55:39 +02:00
Jan Kiszka
ec91a96970 configs: iot2050: Disable CONFIG_CONSOLE_MUX
We only have serial as console option, and leaving this on turns on
SYS_CONSOLE_IS_IN_ENV which is also not true for these devices, leaving
an ugly

In:    No input devices available!
Out:   No output devices available!
Err:   No error devices available!

behind.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
2023-09-28 16:31:43 -04:00
Eduard Strehlau
fa5bde3760 smegw01: Fix inverted CONFIG_SYS_BOOT_LOCKED logic
CONFIG_SYS_BOOT_LOCKED means that a restricted boot environment will
be used. In this case, hab_auth_img_or_fail should be called to prevent
U-Boot to continue running when the fitImage authentication fails.

Fix the logic accordingly.

Additionally, select CONFIG_SYS_BOOT_LOCKED by default.

Signed-off-by: Eduard Strehlau <eduard@lionizers.com>
Signed-off-by: Fabio Estevam <festevam@denx.de>
2023-09-28 16:31:43 -04:00
Manorit Chawdhry
7ebbce535c env: ti: ti_common.env: Fix get_overlaystring for FIT Image
After the refactor with conf- nodes in fitImage, overlaystring wasn't
didn't handle the new conf- nodes in FIT Booting. Fix get_overlaystring
to handle conf- nodes.

Fixes: 837833a724 ("environment: ti: Add get_fit_config command to get FIT config string")
Reported-by: Aniket Limaye <a-limaye@ti.com>
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Reviewed-by: Andrew Davis <afd@ti.com>
2023-09-28 16:31:43 -04:00
Alexander Dahl
d6b4359e50 mtd: nand: raw: atmel: Add error handling when rb-gpios missing
Adapt behaviour to Linux kernel driver.

The return value of gpio_request_by_name_nodev() was not checked before,
and thus in case 'rb-gpios' was missing in DT, rb.type was set to
ATMEL_NAND_GPIO_RB nevertheless, leading to output like this for
example (on sam9x60-curiosity with the line removed from dts):

    NAND:  Could not find valid ONFI parameter page; aborting
    device found, Manufacturer ID: 0xc2, Chip ID: 0xdc
    Macronix NAND 512MiB 3,3V 8-bit
    512 MiB, SLC, erase size: 256 KiB, page size: 4096, OOB size: 64
    atmel-nand-controller nand-controller: NAND scan failed: -22
    Failed to probe nand driver (err = -22)
    Failed to initialize NAND controller. (error -22)
    0 MiB

Note: not having that gpio assigned in dts is possible, the driver does
not override nand_chip->dev_ready() then and a generic solution is used.

Fixes: 6a8dfd5722 ("nand: atmel: Add DM based NAND driver")
Signed-off-by: Alexander Dahl <ada@thorsis.com>
Reviewed-by: Eugen Hristev <eugen.hristev@collabora.com>
Acked-by: Michael Trimarchi <michael@amarulasolutions.com>
2023-09-27 12:43:05 +03:00
Tom Rini
964aae1644 Merge https://source.denx.de/u-boot/custodians/u-boot-riscv
+ Fix VisionFive2 booting issue by providing the correct FDT.
2023-09-26 09:45:41 -04:00
Heinrich Schuchardt
16dbe3d9d4 riscv: set fdtfile on VisionFive 2
Multiple revisions of the StarFive VisionFive 2 board exist. They can be
identified by reading their EEPROM.

Linux uses two differently named device-tree files. To load the correct
device-tree we need to set $fdtfile to the device-tree file name that
matches the board revision.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Tested-by: Milan P. Stanić <mps@arvanta.net>
2023-09-26 10:43:02 +08:00
Tom Rini
15155ab0a3 Merge tag 'u-boot-imx-20230923' of https://source.denx.de/u-boot/custodians/u-boot-imx
Fixes for 2023.10
-----------------

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/17831
2023-09-24 17:15:31 -04:00
Tom Rini
729b0104bb Merge tag 'dm-pull-23sep23' of https://source.denx.de/u-boot/custodians/u-boot-dm
trace: correct format of flyrecord
minor bug fixes
2023-09-24 17:15:15 -04:00
Eduard Strehlau
62a3c66a7c smegw01: Use CONFIG_SYS_LOAD_ADDR for loading fitImage
Set CONFIG_SYS_LOAD_ADDR=0x88000000 and use this address for
loading fitImage.

Also pass the standard CONFIG_BOOTFILE option to indicate
the fitImage file.

Signed-off-by: Eduard Strehlau <eduard@lionizers.com>
Signed-off-by: Fabio Estevam <festevam@denx.de>
2023-09-23 18:45:34 +02:00
Fabio Estevam
45651a3d69 imx7: Disable CAAM Job Ring 0
Trying to boot a fitImage after a successful hab_auth_img operation
causes the following error:

 ## Loading kernel from FIT Image at 88000000 ...
   Using 'conf-imx7d-smegw01.dtb' configuration
   Trying 'kernel-1' kernel subimage
     Description:  Linux kernel
     Type:         Kernel Image
     Compression:  uncompressed
     Data Start:   0x8800010c
     Data Size:    9901752 Bytes = 9.4 MiB
     Architecture: ARM
     OS:           Linux
     Load Address: 0x80800000
     Entry Point:  0x80800000
     Hash algo:    sha256
     Hash value:   28f8779bbf010780f16dd3d84ecb9b604c44c5c2cf7acd098c264a2d3f68e969
   Verifying Hash Integrity ... sha256Error in SEC deq
   CAAM was not setup properly or it is faulty error!

The reason for this error is that the BootROM uses the CAAM Job Ring 0,
so disable its node in U-Boot to avoid the resource conflict.

imx8m dtsi files also have the Job Ring 0 disable since the following
kernel commit:

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/arch?h=v6.5&id=dc9c1ceb555ff661e6fc1081434600771f29657c

For a temporary solution, disable the Job Ring 0 in imx7s-u-boot.dtsi.

Reported-by: Eduard Strehlau <eduard@lionizers.com>
Signed-off-by: Fabio Estevam <festevam@denx.de>
2023-09-23 18:45:34 +02:00
Fabio Estevam
5ae4f74a1b imx: hab: Explain that ivt_offset is optional
The ivt_offset parameter is optional for both hab_auth_img_or_fail
and hab_auth_img commands.

Document it in their usage texts to make it clearer.

Signed-off-by: Fabio Estevam <festevam@denx.de>
2023-09-23 18:45:34 +02:00
Fabio Estevam
ade6e375c3 imx: hab: Improve the hab_auth_img_or_fail usage text
Split the hab_auth_img_or_fail usage text in two sentences to make it
clearer.

Signed-off-by: Fabio Estevam <festevam@denx.de>
2023-09-23 18:45:34 +02:00
Eduard Strehlau
2ec9ebc72a imx: hab: Allow hab_auth_img_or_fail to be called without ivt_offset
Since commit ea91031b22 ("imx: hab: extend hab_auth_img to calculate
ivt_offset"), it is possible to call the hab_auth_img command without the
last ivt_offset argument.

Currently, calling hab_auth_img_or_fail without the last
ivt_offset parameter causes a failure and the command usage text is shown.

Fix this problem by adjusting the argc logic to allow
calling hab_auth_img_or_fail with only the address and size parameters.

This way, both hab_auth_img and hab_auth_img_or_fail have the same
behavior with respect to the allowed number of command parameters.

Signed-off-by: Eduard Strehlau <eduard@lionizers.com>
Signed-off-by: Fabio Estevam <festevam@denx.de>
2023-09-23 18:45:33 +02:00
Oleksandr Suvorov
71dfe179cd mach-imx: bootaux: fix building with disabled bootelf
If CMD_ELF disabled and IMX_BOOTAUX enabled, the u-boot building ends
up with a linking error [1]. Select LIB_ELF to fix the building
issue.

[1]
ld: /tmp/ccaF1rpv.ltrans0.ltrans.o: in function `do_bootaux':
arch/arm/mach-imx/imx_bootaux.c:108: undefined reference to `valid_elf_image'

Fixes: c0f037f6a2 ("mach-imx: bootaux: elf firmware support")
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
2023-09-23 18:45:33 +02:00
Michal Simek
e278ad9a2e trace: Fix alignment logic in flyrecord header
Current alignment which is using 16 bytes is not correct in connection to
trace_clocks description and it's length.
That's why use start_addr variable and record proper size based on used
entries.

Fixes: be16fc81b2 ("trace: Update proftool to use new binary format").
Signed-off-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-09-23 09:00:37 -06:00
Michal Simek
5ae43b8706 trace: Move trace_clocks description above record offset calculation
Flyrecord tracing data are page aligned that's why it is necessary to
calculate alignment properly. Because trace_clocks description is the part
of record length it is necessary to have information about length earlier.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-09-23 09:00:37 -06:00
Michal Simek
83711374ee trace: Use 64bit variable for start and len
tputq() requires variables to have 64bit width that's why make them 64bit
to clean alignment requirement.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-09-23 09:00:37 -06:00
Fei Shao
ce8cb76c7c patman: Respect include directive on Git config lookup
People may put their user name and email in a local config file and
reference it by the include.* directives, however `git config --global`
doesn't look up the included configs by default.

Enable the --includes option explicitly to support such use cases.

Signed-off-by: Fei Shao <fshao@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-09-23 09:00:37 -06:00
Michal Simek
92271d6104 sandbox: test: Fix typo in test.dts
s/parititon/partition/

Signed-off-by: Michal Simek <michal.simek@amd.com>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-09-23 09:00:37 -06:00
Rong Tao
ba4034a504 binman: Fix SyntaxWarning: invalid escape sequence '\('
Reproduct warning:

    $ git clean -dfx
    $ make CROSS_COMPILE="" qemu-x86_64_defconfig
    $ make -j8
    ...
    u-boot/tools/binman/etype/section.py:25:
    SyntaxWarning: invalid escape sequence '\('
    """Entry that contains other entries

Signed-off-by: Rong Tao <rongtao@cestc.cn>
2023-09-23 09:00:37 -06:00
Simon Glass
305114eb83 buildman: Fix full help for Python 3.8
With Python versions older than 3.9 Buildman produces an error on
start-up. Fix this with a workaround for importlib.

There is already a workaround for v3.6 but I am not sure if that is still
functioning.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-09-23 09:00:37 -06:00
Maxim Cournoyer
8acdb70c10 tools: Fix patman launcher script.
There is no "run_patman" procedure in patman's __main__.py file, which
would cause the following error at execution:

  "AttributeError: module 'patman.__main__' has no attribute 'run_patman'"

Signed-off-by: Maxim Cournoyer <maxim.cournoyer@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-09-23 09:00:37 -06:00
Tom Rini
4cb31a9f35 Merge branch '2023-09-22-assorted-bugfixes'
- A few driver fixes and MAINTAINER updates
2023-09-22 18:25:37 -04:00
Kunihiko Hayashi
ff6156f030 MAINTAINERS: Step up as maintainers of UniPhier SoC platform
Update maintainers for UniPhier SoC platform.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
2023-09-22 15:54:39 -04:00
Fabio Estevam
ee9245853e pico-imx7d: Remove Vanessa from MAINTAINERS
Vanessa's NXP e-mail is no longer active.

Contacted her offline and she told me that she does not have
access to the board anymore and it is OK to remove her
from MAINTAINERS.

Signed-off-by: Fabio Estevam <festevam@denx.de>
2023-09-22 15:54:39 -04:00
Francois Berder
8cf61051ae drivers: mediatek: Fix error handling in mtk_i2c_do_transfer
Errors were handled only if an I2C transfer timed out
and received a NACK which is very unlikely. This commit
changes the condition such that errors are handled if
an I2C transfer times out or received a NACK.

Signed-off-by: Francois Berder <fberder@outlook.fr>
Reviewed-by: Heiko Schocher <hs@denx.de>
2023-09-22 15:54:39 -04:00
Ryosuke Saito
c5b42e3e9e net: sni_netsec: Add workaround for timeout error
The NETSEC GMAC occasionally falls into a weird state where
MAC_REG_DESC_SOFT_RST has never been cleared and shows errors like the
below when networking commands are issued:

    => ping 192.168.1.1
    ethernet@522d0000 Waiting for PHY auto negotiation to complete... done
    netsec_wait_while_busy: timeout
    Using ethernet@522d0000 device

    ARP Retry count exceeded; starting again
    ping failed; host 192.168.1.1 is not alive

It happens on not only 'ping' but also 'dhcp', 'tftp' and so on.

Luckily, restarting the NETSEC GMAC and trying again seems to fix the
problematic state. So first ensure that we haven't entered the state by
checking MAC_REG_DESC_SOFT_RST to be cleared; otherwise, restarting
NETSEC/PHY and trying again would work as a workaround.

Signed-off-by: Ryosuke Saito <ryosuke.saito@linaro.org>
Tested-by: Masahisa Kojima <masahisa.kojima@linaro.org>
2023-09-22 15:54:35 -04:00
Ravi Gunasekaran
65adf86f1a configs: am65x_evm_r5_usbmsc_defconfig: Enable DWC3 wrapper for SPL
commit 280f45d239 ("configs: get rid of build warnings due to
SPL_USB_DWC3_GENERIC") missed enabling DWC3 glue layer for
usbmsc_defconfig and this broke boot from USB mass storage.
Fix this by enabling DWC3 glue layer.

Fixes: 280f45d239 ("configs: get rid of build warnings due to SPL_USB_DWC3_GENERIC")
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
2023-09-22 13:58:51 -04:00
Richard Weinberger
a8bd5ec000 net: wget: Avoid packet queue overflow
Make sure to stay within bounds, as a misbehaving HTTP server
can trigger a buffer overflow if not properly handled.

Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Richard Weinberger <richard@nod.at>
2023-09-22 13:58:51 -04:00
Tom Rini
d01a8541d6 Merge https://source.denx.de/u-boot/custodians/u-boot-riscv
- Fixup memory size passed to kernel on visionfive2
2023-09-21 15:56:47 -04:00
Shengyu Qu
43177705ab board: visionfive2: Fixup memory size passed to kernel
Use fdt_fixup_memory to make the memory size data from dtb match
the actual size.

Signed-off-by: Shengyu Qu <wiagn233@outlook.com>
Tested-by: Milan P. Stanić <mps@arvanta.net>
2023-09-20 20:30:30 +08:00
Shengyu Qu
7d4810cac5 configs: visionfive2: Enable CONFIG_OF_BOARD_SETUP
Enable CONFIG_OF_BOARD_SETUP, so we could use ft_board_setup() to fixup
memory size passed to kernel.

Signed-off-by: Shengyu Qu <wiagn233@outlook.com>
Tested-by: Milan P. Stanić <mps@arvanta.net>
2023-09-20 20:26:23 +08:00
Tom Rini
b9b83a86f0 Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sh
- Fix PHY in some cases on some platforms via enabling DM_ETH_PHY.
2023-09-17 09:25:42 -04:00
Tom Rini
064f29e48d Merge tag 'doc-2023-10-rc5-2' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request doc-2023-10-rc5-2

Documentation:

* fix code comments referring to doc/develop/expo.rst
* remove unused values from Chromebook kernel command line
* correct reference tag placement in tools/binman/binman.rst

Others:

* test: fix build dependency for event unit tests
2023-09-17 09:24:42 -04:00
Marek Vasut
075e0b9050 ARM: renesas: Enable DM_ETH_PHY on 64-bit R-Car boards
Enable DM_ETH_PHY to correctly release the PHY on these boards from reset.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-09-17 13:56:34 +02:00
Marek Vasut
2d22cb3413 ARM: dts: renesas: Add compatible properties to KSZ9031 Ethernet PHYs on Salvator-X boards
Add compatible values to Ethernet PHY subnodes representing Micrel
KSZ9031 PHYs on R-Car Gen3 Salvator-X boards. This allows software
to identify the PHY model at any time, regardless of the state of
the PHY reset line.

This is a fix for missed addition of these properties on Salvator-X
boards.

Ported from Linux kernel commit 722d55f3a9bd810f3a1a31916cc74e2915a994ce .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-09-17 13:56:34 +02:00
Massimo Pegorer
8bd7d08407 binman: doc: fix reference tag placement for Logging section
Move BinmanLogging reference tag after section "Signing FIT container
with private key in an image" and just before section "Logging".

Fixes: 0f40e23fd2 ("binman: add documentation for binman sign option")
Signed-off-by: Massimo Pegorer <massimo.pegorer+oss@gmail.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-09-16 18:17:25 +02:00
Massimo Pegorer
a3a057f839 expo: Fix documentation reference
Fix typo: doc/develop/expo.rst instead of doc/developer/expo.rst

Signed-off-by: Massimo Pegorer <massimo.pegorer+oss@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-09-16 18:17:25 +02:00
Jaewon Jung
17d98f84e0 doc: delete unused values kernel command line
Delete "boot=local", "noswap" unused values in kernel command line

Signed-off-by: Jaewon Jung <jw.jung@navercorp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-09-16 18:17:25 +02:00
Heinrich Schuchardt
fdd6a7733f test: build dependency for event unit tests
The test_event_base and test_event_probe unit tests use function
event_register() which depends on CONFIG_EVENT_DYNAMIC=y.

Fixes: 7d02645fe4 ("event: Add a simple test")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-09-16 18:17:25 +02:00
Tom Rini
252592214f Merge tag 'doc-2023-10-rc5' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request doc-2023-10-rc5

Documentation:

* move more TI board documentation to HTML
* update TPM usage instructions for qemu-arm
* update the EFI app documentation

Other:

* tpm: Fix autostart for TPM1.2 devices
* spl: fix undefined return value in spl_blk_load_image
2023-09-09 09:33:02 -04:00
Neha Malcom Francis
7314ba2bf8 doc: board: ti: Move documentation from README to .rst
Make the conversion for all existing TI documentation from README to
.rst

Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
2023-09-09 06:12:47 +02:00
Joao Marcos Costa
129048a3b7 doc: Update path to source_file_format.rst
Previously, the file extension was .txt, and it referenced the uImage.FIT
directory, which no longer exists. This commit updates the path accordingly.

Signed-off-by: Joao Marcos Costa <jmcosta944@gmail.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-09-09 06:12:47 +02:00
Heinrich Schuchardt
c00b289b96 timer: document the unit of the timer rate
To avoid confusion document that timer_dev_priv.clock_rate and
timer_get_rate() yield the timer rate in hertz.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-09-09 06:12:47 +02:00
Simon Glass
063536a781 doc: efi: Update for the 64-bit app
The 64-bit app is supported now, so update the documentation.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-09-09 06:12:47 +02:00
Ilias Apalodimas
5d1fa6b6a6 doc: qemu: switch swtpm instruction to 'tpm autostart'
We don't have a documentation page for our TPM subsystem.  I plan
on sending one in the future,  but in the meantime document the
new 'tpm autostart' command in the QEMU instructions while using
a SWTPM

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-09-09 06:12:47 +02:00
Ilias Apalodimas
edce82c822 tpm: Fix autostart for TPM1.2 devices
On commit e663b2ff4ba2("tpm: Add 'tpm autostart' shell command") an
autostart function was added for both TPM1.2 and 2.0 devices.  Instead
of correctly wiring the autostart command for TPM1.2 devices that patch
mistakenly added it on 'tpm init'

Fixes: commit e663b2ff4ba2("tpm: Add 'tpm autostart' shell command")
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-09-09 06:12:47 +02:00
Heinrich Schuchardt
323e91a183 spl: undefined return value in spl_blk_load_image
spl_blk_load_image() should not return an uninitialized value if
blk_get_devnum_by_uclass_id() fails.

Fixes: 8ce6a2e175 ("spl: blk: Support loading images from fs")
Reported-by: Xavier Drudis Ferran <xdrudis@tinet.cat>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by:  Xavier Drudis Ferran <xdrudis@tinet.cat>
2023-09-09 06:12:47 +02:00
Tom Rini
c0c08be546 Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-usb
- DWC3 fix on Layerscape
2023-09-05 14:44:10 -04:00
Tom Rini
34056394ce Merge tag 'u-boot-imx-20230905' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
Fixes for release
-----------------

- imx9: fix DRAM calculation
- thermal: fixes
- fixed for DM, DH and Gateworks boards

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/17639
2023-09-05 09:05:16 -04:00
Tom Rini
e7b7dca28f Merge https://source.denx.de/u-boot/custodians/u-boot-riscv
+ Implement OpenSBI DBCN extension for early debug console
+ Fixes for VisionFive2 board
      + Fix timer missing
      + Fix L2 LIM issue
      + Enable PCIE auto enumeration to support USB and NVMe by default
+ Set eth0 mac address properly
+ Add __noreturn attribute to spl_invoke_opensbi
2023-09-05 09:04:49 -04:00
Heinrich Schuchardt
dfe0837494 risc-v: implement DBCN based debug console
Use the DBCN SBI extension to implement a debug console.
Make it the default for S-mode RISC-V.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-09-05 10:53:55 +08:00
Heinrich Schuchardt
d14222e7c1 risc-v: implement DBCN write byte
The DBCN extension provides a Console Write Byte call.
Implement function sbi_dbcn_write_byte to invoke it.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-09-05 10:53:55 +08:00
Chanho Park
ef08687ea0 spl: add __noreturn attribute to spl_invoke_opensbi function
spl_invoke_opensbi function is not returned to SPL. Thus, we need to
set __noreturn function attribute.

Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-09-05 10:53:51 +08:00
Shengyu Qu
f39e24496a configs: starfive: Disable SYS_MALLOC_CLEAR_ON_INIT by default
SPL_SYS_MALLOC_CLEAR_ON_INIT would enable SYS_MALLOC_CLEAR_ON_INIT by
default, but that's not need on JH7110, so disable that.

Signed-off-by: Shengyu Qu <wiagn233@outlook.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-09-05 10:53:46 +08:00
Shengyu Qu
64339bc1f2 riscv: cpu: jh7110: Imply SPL_SYS_MALLOC_CLEAR_ON_INIT
Starfive JH7110 needs to clear L2 LIM to zero before use or ECC error
would be triggered. Currently, we use DDR ram for SPL malloc arena on
Visionfive 2 board in defconfig, but it's also possible to use L2 LIM as
SPL malloc arena. To avoid triggering ECC error in this scenario, we
imply SPL_SYS_MALLOC_CLEAR_ON_INIT as default.

Signed-off-by: Bo Gan <ganboing@gmail.com>
Signed-off-by: Shengyu Qu <wiagn233@outlook.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-09-05 10:53:46 +08:00
Shengyu Qu
c9db9a2ef5 dlmalloc: Add support for SPL_SYS_MALLOC_CLEAR_ON_INIT
To support SPL_SYS_MALLOC_CLEAR_ON_INIT, we have to modify
#ifdef CONFIG_SYS_MALLOC_CLEAR_ON_INIT
to #if CONFIG_IS_ENABLED(SYS_MALLOC_CLEAR_ON_INIT)

Signed-off-by: Bo Gan <ganboing@gmail.com>
Signed-off-by: Shengyu Qu <wiagn233@outlook.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-09-05 10:53:46 +08:00
Shengyu Qu
dd1eb1af26 Kconfig: Add SPL_SYS_MALLOC_CLEAR_ON_INIT
Add SPL version of SYS_MALLOC_CLEAR_ON_INIT, this would help devices
that need to clear ram before use to work correctly.

Signed-off-by: Bo Gan <ganboing@gmail.com>
Signed-off-by: Shengyu Qu <wiagn233@outlook.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-09-05 10:53:46 +08:00
Shengyu Qu
f943417737 doc: board: starfive: Add more info about supported driver
Since PLDA PCIE driver is added and VL805 support is enabled in
defconfig for Starfive Visionfive 2, modify the document to keep
consistent.

Signed-off-by: Shengyu Qu <wiagn233@outlook.com>
Tested-by: Milan P. Stanić <mps@arvanta.net>
2023-09-05 10:53:41 +08:00
Shengyu Qu
dccf4a843a configs: starfive: Enable PCIE auto enum and NVME/USB stuff for Starfive Visionfive 2
Although PCIE driver already exists, board defconfig isn't configured to
enable PCIE enum on boot, thus USB storage device and NVME drive are not
supported by default. So modify defconfig to enable PCIE auto enum, then
start USB subsystem and scan nvme drive on boot.

Signed-off-by: Shengyu Qu <wiagn233@outlook.com>
Tested-by: Milan P. Stanić <mps@arvanta.net>
2023-09-05 10:53:41 +08:00
Torsten Duwe
6164d86984 riscv: jh7110: enable riscv,timer in the device tree
The JH7110 has the arhitectural CPU timer on all 5 rv64 cores.
Note that in the device tree.

Signed-off-by: Torsten Duwe <duwe@suse.de>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-09-05 10:53:36 +08:00
Torsten Duwe
f39f8f77a5 riscv: allow riscv timer to be instantiated via device tree
For the architectural timer on riscv, there already is a defined
device tree binding[1]. Allow timer instances to be created from
device tree matches, but for now retain the old mechanism, which
registers the timer biggy-back with the CPU.

[1] linux/Documentation/devicetree/bindings/timer/riscv,timer.yaml

Signed-off-by: Torsten Duwe <duwe@suse.de>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-09-05 10:53:36 +08:00
Seung-Woo Kim
71914337ef eeprom: starfive: set eth0 mac address properly
fdt_fixup_ethernet() sets eth0 mac address from ethaddr. Set
ethaddr to environment instead of eth0addr.

Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-09-05 10:53:29 +08:00
Tom Rini
493fd3363f nokia_rx51: Remove platform
This platform is behind on migrations (it is the sole user of the oldest
legacy version of the USB gadget stack and is long overdue for
migration) and with Pali no longer being a maintainer, we remove this
platform.

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-09-04 21:14:32 -04:00
Tom Rini
af7de99e0c MAINTAINERS: Drop Pali Rohár
Remove Pali from his listed maintainer entries due to his publicly
visible actions on the mailing list.

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-09-04 21:13:38 -04:00
Fabio Estevam
a79fca7b44 thermal: imx_tmu: Increase the polling interval
Polling every second to check whether the CPU has cooled down is
too frequent.

Allow more time for the CPU to cool down by increasing the polling
interval to 5 seconds by defaut.

This value is used in the absence of the 'polling-delay' devicetree
property.

Signed-off-by: Fabio Estevam <festevam@denx.de>
2023-09-04 17:26:44 +02:00
Fabio Estevam
f4898e4b0e thermal: imx_tmu: Fix the temperature unit
The temperature unit is millidegree Celsius, so divide by 1000 to correctly
print the temperature values in Celsius.

While at it, also change a typo: "has beyond" to "is beyond".

Signed-off-by: Fabio Estevam <festevam@denx.de>
2023-09-04 17:26:44 +02:00
Fabio Estevam
966480fe43 thermal: imx_tmu: Increase the log level for high temperatures
dev_info() message is not printed by default. Increase the log level
to dev_crit(). This allows the critical messages related to the temperature
getting beyong the alert threshold to be displayed.

Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-09-04 17:26:44 +02:00
Fabio Estevam
402b8106ec thermal: imx_tmu: Fix the polling default
When the 'polling-delay' property is not passed via devicetree,
pdata->polling_delay keeps at 0. This causes the imx_tmu driver to get
stuck inside the busy while() loop when the CPU temperature is above
the alert point.

Fix this problem by passing a one second polling interval, which provides
a proper delay to let the system to cool down and exit the while() loop
when the temperature is below the alert point.

Signed-off-by: Fabio Estevam <festevam@denx.de>
2023-09-04 17:26:44 +02:00
Fabio Estevam
282ff895c8 imx8mm_evk_defconfig: Select CONFIG_IMX_TMU
Select the i.MX8MM thermal driver as it is useful for displaying
the CPU temperature and its grading:

CPU:   Commercial temperature grade (0C to 95C) at 38C

It also prevents booting when the temperature is above the alert
point.

Signed-off-by: Fabio Estevam <festevam@denx.de>
2023-09-04 17:26:44 +02:00
Tom Rini
b27eeca112 Prepare v2023.10-rc4
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-09-04 10:39:43 -04:00
Tom Rini
164b86f26b Merge tag 'rpi-2023.10' of https://source.denx.de/u-boot/custodians/u-boot-raspberrypi
Updates for RPi for 2023.10:

- rpi: Disable DISTRO_DEFAULTS
- arm: rpi: Switch to standard boot
- arm: rpi: Switch to a text environment
2023-09-04 10:07:48 -04:00
Oleksandr Suvorov
7f4b73fe69 usb: dwc3: Fix enabling USB_DR_MODE_HOST
The original logic always enables USB_DR_MODE_HOST operation mode in
dwc3_layerscape_bind() in u-boot. Prevent choosing USB_DR_MODE_HOST
operation mode if USB_HOST is not enabled.

Fixes: 2b0b51d0be ("usb: dwc3: add layerscape support")
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
2023-09-04 15:51:38 +02:00
Oleksandr Suvorov
da93ea6a9a usb: dwc3: Fix renaming SPL_USB_HOST_SUPPORT to SPL_USB_HOST
In the usb/dwc3-layerscape driver the first option should be renamed
to the latter as well. Do it.

Fix original logic in dwc3_layerscape_bind() - do not enable

Fixes: 333e4a621d ("Rename SPL_USB_HOST_SUPPORT to SPL_USB_HOST")
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
2023-09-04 15:51:38 +02:00
Marek Vasut
2629b18ed4 ARM: imx: Use default SAVED_DRAM_TIMING_BASE on Data Modul i.MX8M Plus eDM SBC
Use default SAVED_DRAM_TIMING_BASE as that is what upstream TFA expects.
Without this change, the board will fail to suspend/resume e.g. in Linux.

Signed-off-by: Marek Vasut <marex@denx.de>
2023-09-04 10:21:20 +02:00
Marek Vasut
7e4e4ff6ec ARM: imx: Use default SAVED_DRAM_TIMING_BASE on Data Modul i.MX8M Mini eDM SBC
Use default SAVED_DRAM_TIMING_BASE as that is what upstream TFA expects.
Without this change, the board will fail to suspend/resume e.g. in Linux.

Signed-off-by: Marek Vasut <marex@denx.de>
2023-09-04 10:21:20 +02:00
Marek Vasut
bd7606d142 ARM: imx: Use default SAVED_DRAM_TIMING_BASE on DH i.MX8M Plus DHCOM
Use default SAVED_DRAM_TIMING_BASE as that is what upstream TFA expects.
Without this change, the board will fail to suspend/resume e.g. in Linux.

Signed-off-by: Marek Vasut <marex@denx.de>
2023-09-04 10:21:20 +02:00
Tim Harvey
99eb21cfcc board: gateworks: venice: fix gw7904
Add missing imx8mm-venice-gw7904 to CONFIG_OF_LIST

Fixes commit 61e7f97325 ("board: gateworks: venice: add imx8mm-gw7904 support")
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2023-09-04 10:21:20 +02:00
Elena Popa
07908bf5e5 arm: imx: imx8m: imx9: Fix DRAM size calculation due to rom_pointer
If dram_init_banksize() is called from SPL, the rom_pointer, at that
point, is not correctly initialized. This causes wrong calculation of
DRAM start and size in dram_init_banksize(). The issue became apparent
only in Falcon Mode. Added an extra condition to prevent using
rom_pointer in SPL.

Signed-off-by: Elena Popa <elena.popa@nxp.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2023-09-04 10:21:20 +02:00
Marek Vasut
f58b0c8534 ARM: imx: Select 2 DRAM banks on Data Modul i.MX8M Mini eDM SBC
U-Boot splits DRAM bank spanning addresses below and above the 32bit
boundary into two DRAM banks. Since this platform may come with 4GiB
of DRAM, increase the DRAM bank count to 2.

Signed-off-by: Marek Vasut <marex@denx.de>
2023-09-04 10:21:20 +02:00
Marek Vasut
e47cab0fa1 ARM: imx: Drop CONFIG_USE_BOOTCOMMAND=n on i.MX6 DHSOM
This board certainly does use default 'run distro_bootcmd' boot command,
make sure this is set in 'bootcmd' variable.

Fixes: 970bf8603b ("Convert CONFIG_USE_BOOTCOMMAND et al to Kconfig")
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-09-04 10:21:20 +02:00
Simon Glass
fc2af2d978 arm: rpi: Switch to a text environment
Use the new environment format so we can drop most of the config.h file.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-09-03 23:33:04 +01:00
Simon Glass
90f626a5d8 rpi: Disable DISTRO_DEFAULTS
Disable this option to reclaim some space, since bootstd requires less
functionality to operate (e.g. hush parser).

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-09-03 23:20:59 +01:00
Simon Glass
c771e5b8c2 arm: rpi: Switch to standard boot
Drop use of the distro scripts and use standard boot instead.

We don't need to specify the mmc devices individually, since they are
used in order from 0 to 2, and standard boot uses that order anyway.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-09-03 23:20:59 +01:00
Tom Rini
8999257f21 Merge tag 'doc-2023-10-rc4-2' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request doc-2023-10-rc4-2

* Man-page for gpt command
* Fix long text help of gpt command
* Add events to HTML documentation
* Update Toradex documentation
2023-09-02 09:08:54 -04:00
Joshua Watt
44c5d7764b doc: Add gpt command documentation
Adds initial documentation for the gpt command

Signed-off-by: Joshua Watt <JPEWhacker@gmail.com>
2023-09-02 09:44:04 +02:00
Joshua Watt
1fa11cdcfe cmd: gpt: Remove confusing help text
This help text appears to be a fragment of the text shown when
CONFIG_CMD_GPT_RENAME is enabled, but is confusing so remove it.

Signed-off-by: Joshua Watt <JPEWhacker@gmail.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-09-02 09:43:49 +02:00
Marcel Ziswiler
b4b7eed499 doc: board: toradex: verdin-am62: document update u-boot wrapper
Now with the update U-Boot wrappers having been sorted out, document
their usage.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2023-09-02 06:05:45 +02:00
Marcel Ziswiler
4d1fea9ad1 doc: board: toradex: minor documentation update
- Update SPDX-License-Identifier from obsolete GPL-2.0+ to
  GPL-2.0-or-later.
- Add links to product websites of SoM and carrier board where missing.
- Add information about update U-Boot wrapper where missing.
- Add sectionauthor where missing.
- Update information about imx-seco from version 3.7.4 to 3.8.1.
- Various minor grammatic and spelling fixes.
- Improve whitespace by adding or removing new lines.
- Change from code-block for output to just Output::.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2023-09-02 06:05:45 +02:00
Heinrich Schuchardt
0926de2362 video: fix typo in video_sync_all documentation
%s/there/their/

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-09-02 06:04:11 +02:00
Heinrich Schuchardt
91f19550d1 doc: add events.h to documentation
Add the events.h include to the API documentation.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-09-02 06:03:42 +02:00
Heinrich Schuchardt
6a407076b2 dm: event: document all events
Provide Sphinx documentation for all events.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-09-02 06:03:42 +02:00
Tom Rini
0fe0395922 Merge branch '2023-08-28-assorted-important-fixes'
- A few platform-specific config/dts updates to fix issues, drop a
  temporary change in binman, update the MAINTAINERS file to remove
  Wolfgang Denk, fix a typo, fix a corner case with bootstd, update
  Azure to not timeout so easily, and fix a case where we would omit
  some files in SPL.
2023-08-29 10:06:08 -04:00
Ricardo Salveti
c91feda87c Revert "arm: imx: mx7: Move CONFIG_OPTEE_TZDRAM_SIZE from lib/optee"
This reverts commit c5b68ef8af.

CONFIG_OPTEE_TZDRAM_SIZE is used by imx6-based SoCs as well. Move the
option back.

Signed-off-by: Ricardo Salveti <ricardo@foundries.io>
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
2023-08-28 15:59:22 -04:00
Simon Glass
bbbf04cc7d Revert "binman: Add a temporary hack for duplicate phandles"
The affected boards have been fixed, so drop this hack.

This reverts commit 288ae53cb7.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Tim Harvey <tharvey@gateworks.com>
2023-08-28 15:59:22 -04:00
Simon Glass
98244a8550 imx: Drop unneeded phandle in FIT template
Adding a phandle to a template node is not allowed, since when the node is
instantiated multiple times, we end up with duplicate phandles.

Drop this invalid constructs.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Tim Harvey <tharvey@gateworks.com>
2023-08-28 15:59:22 -04:00
Heinrich Schuchardt
fa140172cb MAINTAINERS: remove Wolfgang Denk
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-08-28 15:59:22 -04:00
Oleksandr Suvorov
70bd471984 spl: crypto: fix including SHA* object files in SPL
If one of SHA* algorithms is disabled in u-boot, its code is not
included in SPL even if a given SHA* option is enabled in SPL. Fix
this.

Fixes: 603d15a572 ("spl: cypto: Bring back SPL_ versions of SHA")
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-08-28 15:59:22 -04:00
Tom Rini
04f7e95385 Azure: Set the timeout for jobs to the maximum
As per current Azure Pipelines documentation we qualify for 3600 minutes
per job, if specified, as the timeout. The default unspecified timeout
is 60 minutes. Rework things to specify 0 as the timeout (and so maximum
allowed) so that we don't have failures due to running slightly past 60
minutes total.

Link: https://learn.microsoft.com/en-us/azure/devops/pipelines/process/phases?view=azure-devops&tabs=yaml#timeouts
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-08-28 15:59:22 -04:00
Daniel Golle
dcde1f95bf configs: set CONFIG_LMB_MAX_REGIONS=64 for MT7988 boards
Similar to MT7981 and MT7986 also MT7988 can have a high number of
reserved-memory regions used by the various hardware offloading
subsystems.

Raise CONFIG_LMB_MAX_REGIONS to 64 to avoid errors when trying to boot
Linux with more then 6 reserved regions:

ERROR: reserving fdt memory region failed (addr=4f700000 size=240000 flags=4)
ERROR: reserving fdt memory region failed (addr=15194000 size=1000 flags=4)
ERROR: reserving fdt memory region failed (addr=15294000 size=1000 flags=4)
ERROR: reserving fdt memory region failed (addr=15394000 size=1000 flags=4)
ERROR: Failed to allocate 0xb161 bytes below 0x80000000.
device tree - allocation error

Fixes: bc4adc97cf ("board: mediatek: add MT7988 reference boards")
Reported-by: Lorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
2023-08-28 15:59:22 -04:00
Andrew Davis
b982a850d0 configs: Enable CONFIG_DM_SCSI in am57xx_hs_evm_usb
This should have already been enabled but was missed when converting the
base platform defconfig, fix this here.

Fixes: 3c5aa6cacc ("configs: Enable CONFIG_BLK in am57xx_evm and am57xx_hs_evm")
Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-08-28 15:59:22 -04:00
Simon Glass
5986d46f8e bootstd: Adjust the default bootmeth order
The existing distro scripts check extlinux and scripts before EFI. Adjust
the default ordering to do the same, to avoid breaking existing flows.

Add some documentation, mentioning that this order will likely change in
future.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Da Xue <da@libre.computer>
2023-08-28 15:59:22 -04:00
Frank Wunderlich
d389efc448 arm: dts: mediatek: convert gmac link mode to 2500base-x for r3
Ethernet on Bananapi-r3 is broken after

commit bd70f3cea3 ("net: mediatek: add support for SGMII 1Gbps auto-negotiation mode")

because changes from this commit were not applied to bpi-r3 devicetree too:

commit aef54ea16c ("arm: dts: medaitek: convert gmac link mode to 2500base-x")

Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
2023-08-28 15:59:22 -04:00
Peter Robinson
d167062c48 boot: Fix reference to bootmenu doc
The Kconfig references a readme file that's moved and
converted to rst so update the reference.

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-08-28 15:59:22 -04:00
Tom Rini
6a1d3f64c2 Merge tag 'efi-2023-10-rc4' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request efi-2023-10-rc4

Documentation:

* describe TPL/VPL/SPL boot
* Add support for sphinx-prompt and convert TI K3 to use it
* board: sdm845: Explicitly add boot.img flashing command

EFI:

* remove handle from events when deleting it

Others:

* fix gpt sub-commands setenv and enumerate
* add a parameter check in hash_calculate()
2023-08-27 11:04:02 -04:00
Ilias Apalodimas
cc889bd075 efi_loader: delete handle from events when a protocol is uninstalled
When a notification event is registered for a protocol the handle of the
protocol is added in our event notification list.  When all the protocols
of the handle are uninstalled we delete the handle but we do not remove
it from the event notification list.

Clean up the protocol removal functions and add a wrapper which
- Removes the to-be deleted handle from any lists it participates
- Remove the handle if no more protocols are present

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-08-27 08:21:08 +02:00
Heinrich Schuchardt
143c9a7e9d doc: describe TPL/VPL/SPL boot
This is a stub describing how TPL, VPL, and SPL load the next boot stages
on a detail level for users.

For sure we will need a few patches on top to catch the whole complexity.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
2023-08-27 08:21:08 +02:00
Nishanth Menon
febc7f1009 doc: board: ti: k3: Convert to sphinx-prompt
Sphinx-prompt provides a handy scheme to provide documentation that
renders nicely and yet provides a scheme to copy paste for users without
having to hand-edit the copied text as is the result of code-block

[1] https://lore.kernel.org/all/87fs48rgto.fsf@baylibre.com/
Reported-by: Simon Glass <sjg@chromium.org>
Suggested-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-08-27 08:21:08 +02:00
Nishanth Menon
1cfcc2298f doc: sphinx: Add sphinx-prompt
Sphinx-prompt[1] helps bring-in '.. prompt::' option that allows a
better rendered documentation, yet be able to copy paste without
picking up the prompt from rendered documentation.

[1] https://lore.kernel.org/all/87fs48rgto.fsf@baylibre.com/
Suggested-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-08-27 08:21:08 +02:00
Sumit Garg
96c4fec701 doc: board: sdm845: Explicitly add boot.img flashing command
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>

Use code-block. Fix length of two heading underlines.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-08-27 08:21:08 +02:00
Heinrich Schuchardt
eeef584015 cmd: let gpt_partition_entry be hexadecimal
In commands like 'ls mmc 0:f' the partition number is hexadecimal.

In command 'gpt setenv' variable gpt_partition_entry needs to be set
to a hexadecimal value to allow its use as a parameter in a
subsequent command.

Fixes: 57f8cf1b9aea ("cmd: fix gpt enumerate")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-08-27 08:21:08 +02:00
Heinrich Schuchardt
41cd23b7be cmd: fix gpt enumerate
Do not assume that partitions are numbered continuously starting at 1.

Only a single partition table type can exist on a block device. If we found
a GPT partition table, we must not re-enumerate with the MBR partition
driver which would find the protective partition.

Fixes: 12fc1f3bb2 ("cmd: gpt: add eMMC and GPT support")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-08-27 08:21:07 +02:00
Heinrich Schuchardt
018346770b cmd: fix gpt setenv
Do not assume that partitions are continuously numbered starting at 1.

Having a partition table with a single partition 63 is valid.

Fixes: 12fc1f3bb2 ("cmd: gpt: add eMMC and GPT support")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-08-27 08:21:07 +02:00
Heinrich Schuchardt
eb48efce26 lib: parameter check in hash_calculate
If hash_calculate is invoked with region_count = 0, it will try to hash
INT_MAX regions. We should check this parameter.

* Avoid a comparison with different signedness.
* Check that region_count is at least 1.
* Avoid a superfluous assignment.

Fixes: b37b46f042 ("rsa: Use checksum algorithms from struct hash_algo")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-08-27 08:21:07 +02:00
Tom Rini
e508b93002 Merge https://source.denx.de/u-boot/custodians/u-boot-usb
- Two phy-imx8mq-usb fixes and one dwc3 fix
2023-08-25 10:52:39 -04:00
Tom Rini
6b7aff3628 Merge tag 'u-boot-stm32-20230825' of https://source.denx.de/u-boot/custodians/u-boot-stm
Remove scmi-optee shmem for STM32MP15 and STM32MP13
2023-08-25 10:52:13 -04:00
Patrick Delaunay
3fce6bf213 ARM: dts: stm32mp13: remove shmem for scmi-optee
CFG_STM32MP1_SCMI_SHM_SYSRAM will be disabled by default for STM32MP13x
SoCs in next OP-TEE version and the OP-TEE SMCI server uses the OP-TEE
native shared memory registered by clients.

To be compatible by default with this configuration this patch removes
the shared memory in the SCMI configuration and the associated reserved
memory in SRAM.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-08-25 09:29:18 +02:00
Patrick Delaunay
b2fb22396f ARM: dts: stm32mp15: remove shmem for scmi-optee
Since OP-TEE commit 89ba3422ee80 ("plat-stm32mp1: scmi_server: default
use OP-TEE shared memory"), integrated in OP-TEE 3.22.0-rc1
the default configuration for STM32MP15x SoCs changes,
CFG_STM32MP1_SCMI_SHM_SYSRAM is disabled by default and the OP-TEE SMCI
server uses ithe OP-TEE native shared memory registered by clients.

To be compatible by default with this configuration and the next OP-TEE
version, this patch removes the SHMEM in the SCMI configuration and the
associated reserved memory in the last 4KByte page of SRAM,
in the STM32MP15 device tree.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-08-25 09:29:05 +02:00
Tim Harvey
e3380e1c1a phy: phy-imx8mq-usb: clean up clock code
use CONFIG_IS_ENABLED for clock enable/disable and change printf's
to dev_err. Additionlly remove the comment that does not make sense.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2023-08-25 02:36:19 +02:00
Tim Harvey
c90729c463 phy: phy-imx8mq-usb: add vbus regulator support
Add support for enabling and disabling vbus-supply regulator found
on several imx8mp boards in the usb3_phy0 and usb3_phy1 nodes.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2023-08-25 02:36:19 +02:00
Venkatesh Yadav Abbarapu
9871b0e5d0 usb: dwc3: Fix remove function if there is no ulpi_reset gpio
As ulpi_reset gpio is now optional, we need to check it when doing
the 'dwc3_generic_remove' function. Check if it is declared before
accessing the ulpi_reset.

Fixes: 237d1f60b1 ("usb: dwc3: Use the devm_gpiod_get_optional()
		     API for reset gpio")

Reported-by: Thomas Nizan <tnizan@witekio.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
2023-08-25 02:35:40 +02:00
Tom Rini
291055efee Merge tag 'doc-2023-10-rc4' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request for doc-2023-10-rc4

Documentation:

* Fix documentation for TI boards
* Describe running on VirtualBox
* List build dependencies for building documenation
* Add references to U-Boot talks

Other:

* Fix error handling in the setexpr command (printf_str)
2023-08-23 11:03:46 -04:00
Paul Barker
4e73b0153c doc: Highlight the most relevant u-boot talks
The list of u-boot talks on elinux.org is quite long, so let's highlight
the talks which are likely most relevant for newcomers.

Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-08-23 08:03:00 +02:00
Paul Barker
2a3c0680e6 doc: Explicitly list build dependencies for docs
Highlight the packages which need to be installed in order to build the
docs.

Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
2023-08-23 08:03:00 +02:00
Thomas Mittelstaedt
d737e9efcf Documentation extended with specific information for VirtualBox
The configuration for EFI is enhanced to start U-Boot at VirtualBox (x86_64)
with all features like booting with help of boot scripts and extended linux.
This documentation describes how to use U-Boot at VirtualBox to boot
Linux systems with a some simple example.

Signed-off-by: Thomas Mittelstaedt <thomas.mittelstaedt@de.bosch.com>
2023-08-23 08:03:00 +02:00
Jonathan Humphreys
975103f1ac doc: board: ti: k3: Fix up OpenOCD references and debug info
Fix minor path and config macro name updates to sync with latest
OpenOCD and U-Boot configurations.

Fixes: effe50854a ("doc: board: ti: k3: Add a guide to debugging with OpenOCD")
Signed-off-by: Jonathan Humphreys <j-humphreys@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-08-23 08:03:00 +02:00
Nishanth Menon
4e4f344e7d doc: board: ti: k3: Elaborate on various firmware
Add elaboration text for the various firmware involved for system
management.

Signed-off-by: Nishanth Menon <nm@ti.com>
2023-08-23 08:03:00 +02:00
Nishanth Menon
f340a162fb doc: board: ti: j721e: Fix build step numbering
Fix up build step numbering.

Fixes: c727b81d65 ("doc: board: ti: k3: Reuse build instructions")
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-08-23 08:03:00 +02:00
Nishanth Menon
7af00a7957 doc: board: ti: j7200: Fix build step numbering
Fix up build step numbering.

Fixes: c727b81d65 ("doc: board: ti: k3: Reuse build instructions")
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-08-23 08:03:00 +02:00
Nishanth Menon
c8612e2f49 doc: board: ti: am65x: Fix build step numbering
Fix up build step numbering.

Fixes: c727b81d65 ("doc: board: ti: k3: Reuse build instructions")
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-08-23 08:03:00 +02:00
Nishanth Menon
bfffc81b4c doc: board: ti: am62x: Fix build step numbering
Fix up build step numbering.

Fixes: c727b81d65 ("doc: board: ti: k3: Reuse build instructions")
Signed-off-by: Nishanth Menon <nm@ti.com>
Revieed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-08-23 08:03:00 +02:00
Nishanth Menon
e21a2ed33f doc: board: ti: j721e: provide image alt text
Provide alternative text for image.

Fixes: 3b83dff183 ("doc: board: ti: j721e: Convert the image format to svg")
Reported-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2023-08-23 08:03:00 +02:00
Nishanth Menon
49509dfec8 doc: board: ti: j7200: provide image alt text
Provide alternative text for image.

Fixes: f4ade09a1e ("doc: board: ti: j7200: Convert the image format to svg")
Reported-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2023-08-23 08:03:00 +02:00
Heinrich Schuchardt
dfd299a696 doc: board: ti: am65x: provide image alt text
Provide alternative text for image.

Fixes: fd358121bd ("doc: board: ti: am65x: Update with boot flow diagram")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2023-08-23 08:02:59 +02:00
Heinrich Schuchardt
f5a578e77e doc: board: ti: am62x: provide image alt texts
Provide alternative texts for images.

Fixes: 34f76921d8 ("doc: board: ti: am62x: Convert the image format to svg")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2023-08-23 08:02:59 +02:00
Nishanth Menon
c6df52892e doc: board: ti: k3: Fixup alt text for openocd sequence
Fix up OpenOCD setup sequence

Fixes: effe50854a ("doc: board: ti: k3: Add a guide to debugging with OpenOCD")
Reported-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2023-08-23 08:02:59 +02:00
Heinrich Schuchardt
7f62928a89 doc: board: ti: k3: image alt texts
Provide alternative texts for images.

Fixes: 6e8fa0611f ("board: ti: k3: Convert boot flow ascii flow to svg")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2023-08-23 08:02:59 +02:00
Heinrich Schuchardt
175e4b01be cmd: setexpr: fix printf_str()
If vsnprintf() returns a negative number, (i >= remaining) will
possibly be true:

'i' is of type signed int and 'remaining' is of the unsigned type size_t.
The C language will convert i to an unsigned type before the comparison.

This can result in the wrong error type being indicated.

Checking for negative i should be done first.

Fixes: f4f8d8bb1a ("cmd: setexpr: add format string handling")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-08-23 08:02:59 +02:00
Tom Rini
58144e2839 Merge tag 'dm-pull-22aug23' of https://source.denx.de/u-boot/custodians/u-boot-dm
RISC-V fix for CPU init
2023-08-22 15:52:58 -04:00
Chanho Park
1c55d62fb9 riscv: cpu: make riscv_cpu_probe to EVT_DM_POST_INIT_R callback
Since the Patch 55171aedda, VisionFive2 booting has been broken [1].
VisionFive2 board requires to enable CONFIG_TIMER_EARLY but booting went
to panic from initr_dm_devices due to lack of a timer device.

- Error logs
initcall sequence 00000000fffd8d38 failed at call 00000000402185e4
(err=-19)

Thus, we need to move riscv_cpu_probe function in order to register
the timer earlier than initr_dm_devices.

Fixes: 7fe32b3442 ("event: Convert arch_cpu_init_dm() to use events")
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Tested-by: Milan P. Stanić <mps@arvanta.net>
Tested-by: Roland Ruckerbauer <mail@ruabmbua.dev>
Tested-by: Roland Ruckerbauer <mail@ruabmbua.dev>
2023-08-22 08:07:54 -06:00
Chanho Park
27c7a62986 dm: event: add EVT_DM_POST_INIT_R event type
This patch introduces EVT_DM_POST_INIT_R event type for handling hooks
after relocation.

Fixes: 55171aedda ("dm: Emit the arch_cpu_init_dm() even only before relocation")
Suggested-by: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Tested-by: Milan P. Stanić <mps@arvanta.net>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Roland Ruckerbauer <mail@ruabmbua.dev>
Tested-by: Roland Ruckerbauer <mail@ruabmbua.dev>
Fixed missing event name in event.c:
Signed-off-by: Simon Glass <sjg@chromium.org>
2023-08-22 08:07:43 -06:00
Tom Rini
976fb2ffa3 Prepare v2023.10-rc3
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-08-21 16:19:59 -04:00
Tom Rini
db72a5736f Merge tag 'dm-pull-20aug23' of https://source.denx.de/u-boot/custodians/u-boot-dm
sandbox64 fixes
2023-08-21 15:48:30 -04:00
Marek Vasut
25a9be71ec test: cpu: Handle both 32bit and 64bit CPUs
Handle both 32bit and 64bit systems, i.e. sandbox and sandbox64
the same way drivers/cpu/cpu_sandbox.c does, that is in case
CONFIG_PHYS_64BIT is enabled, assume 64bit address width, else
assume 32bit address width. This fixes ut_dm_dm_test_cpu test
failure on sandbox64.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-08-20 15:55:27 -06:00
Marek Vasut
ddfda552e7 configs: sandbox64: Enable PCI register multi-entry support
Align the sandbox64 defconfig with sandbox defconfig. Enable missing
PCI register multi-entry support. This fixes ut_dm_dm_test_pci_bus_to_phys
test .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-08-20 15:55:27 -06:00
Marek Vasut
eaa5b5d7d2 configs: sandbox64: Enable clock CCF driver
Align the sandbox64 defconfig with sandbox defconfig. Enable missing
CCF and Sandbox CCF drivers. This fixes ut_dm_dm_test_clk_ccf test .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-08-20 15:55:27 -06:00
Marek Vasut
5d5d7e225d configs: sandbox64: Enable video 12x22 font support
Align the sandbox64 defconfig with sandbox defconfig. Enable missing
12x22 font support. This fixes ut_dm_dm_test_video_text_12x22 test .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-08-20 15:55:27 -06:00
Marek Vasut
539485fd9e configs: sandbox64: Enable video 16bpp and 24bpp support
Align the sandbox64 defconfig with sandbox defconfig. Enable missing
16bpp and 24bpp video support. This fixes ut_dm_dm_test_video_bmp16
and ut_dm_dm_test_video_bmp24 tests .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-08-20 15:55:27 -06:00
Marek Vasut
d54c44b474 configs: sandbox64: Enable PINCTRL_SINGLE driver
Align the sandbox64 defconfig with sandbox defconfig. Enable missing
PINCTRL single driver. This fixes ut_dm_dm_test_pinctrl_single test .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-08-20 15:55:27 -06:00
Marek Vasut
2fff2881c8 test: dm: pinmux: Handle %pa in pinctrl-single mux output
The pinctrl-single driver uses %pa to print register value
in its single_get_pin_muxing() output. Handle this properly
in the test based on CONFIG_PHYS_64BIT .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-08-20 15:55:27 -06:00
Marek Vasut
09c0b2e712 configs: sandbox64: Enable BUTTON_ADC driver
Align the sandbox64 defconfig with sandbox defconfig. Enable missing
BUTTON ADC driver. This fixes ut_dm_dm_test_button_keys_adc test .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-08-20 15:55:27 -06:00
Marek Vasut
226ddc0dcc configs: sandbox64: Enable MC34708 driver
Align the sandbox64 defconfig with sandbox defconfig. Enable missing
MC34708 PMIC driver. This fixes ut_dm_dm_test_power_pmic_mc34708_get test .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-08-20 15:55:27 -06:00
Marek Vasut
49147a0b0d configs: sandbox64: Increase console record size to 0x6000
Align the sandbox64 defconfig with sandbox defconfig. Increase the
console record size. This fixes ut_bootstd_bootflow_cmd_scan_e .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-08-20 15:55:27 -06:00
Marek Vasut
ff547a6bc2 configs: sandbox64: Enable SF bootdev
Align the sandbox64 defconfig with sandbox defconfig. Enable missing
SPI NOT bootdev. This fixes ut_bootstd_bootdev_test_cmd_hunt test .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-08-20 15:55:26 -06:00
Tom Rini
17aad80355 Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sh 2023-08-20 11:09:11 -04:00
Paul Barker
dbada49554 arm: rmobile: Fix off-by-one error in cpuinfo
In rmobile_cpuinfo_idx() there is an off-by-one error in accessing the
rmobile_cpuinfo array.

At the end of the loop, i is equal to the array size, i.e.
rmobile_cpuinfo[i] accesses one entry past the end of the array. The
last entry in the array is a fallback value so the loop should count to
ARRAY_SIZE(rmobile_cpuinfo) - 1 instead, this will leave i equal to the
index of the fallback value if no match is found.

Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-08-19 16:34:41 +02:00
Tom Rini
406a5ddf9d Merge tag 'doc-2023-10-rc3-2' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request doc-2023-10-rc3-2

Documentation:

* csf_examples: csf.sh: Remove unneeded export ATF_LOAD_ADDR line
* printf() codes: correct format specifier for unsigned int
* Fix typos in clk.h, irq.h.
* Correct description of proftool

Other:

* Quieten test for erofs filesystem presence
* spl: don't assume NVMe partition 1 exists
2023-08-19 10:13:28 -04:00
Fabio Estevam
951d63000e doc: csf_examples: csf.sh: Remove unneeded export ATF_LOAD_ADDR line
Originally, exporting the ATF_LOAD_ADDR was required, but since binman has
been used to generate the flash.bin, it is no longer needed to do
such manual export.

The ATF address is now passed via binman.

Remove the unneeded export ATF_LOAD_ADDR line.

Signed-off-by: Fabio Estevam <festevam@denx.de>
2023-08-19 04:12:53 +02:00
Paul Barker
99a4e5865e irq: Fix typo in header comment
Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-08-19 04:12:53 +02:00
Paul Barker
52029b783b clk: Fix typo in header comment
Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-08-19 04:12:53 +02:00
Siddharth Vadapalli
68886a9941 doc: printf() codes: Fix format specifier for unsigned int
The format specifier for the "unsigned int" variable is documented as
"%d". However, it should be "%u". Thus, fix it.

Fixes: f5e9035043 ("doc: printf() codes")
Reported-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-08-19 04:12:52 +02:00
Puhan Zhou
aab60a5128 docs: fix wrong usage of proftool
The usage of proftool in docs is incorrect. If proftool is used without
'-o' argument, it will show the usage like following

$ ./sandbox/tools/proftool -m sandbox/System.map -t trace -f funcgraph dump-ftrace >trace.dat
Must provide trace data, System.map file and output file
Usage: proftool [-cmtv] <cmd> <profdata>

Change '>' to '-o' to fix it.

Signed-off-by: Puhan Zhou <puh4n.zhou@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-08-19 04:12:52 +02:00
Heinrich Schuchardt
4ad85a9fea spl: don't assume NVMe partition 1 exists
There is no requirement that a partition 1 exists in a partition table.
We should not try to retrieve information about it.

We should not even try reading with partition number
CONFIG_SYS_NVME_BOOT_PARTITION here as this is done in the fs_set_blk_dev()
call anyway.

Fixes: 8ce6a2e175 ("spl: blk: Support loading images from fs")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-08-19 04:12:52 +02:00
Simon Glass
97f4bc372f fs/erofs: Quieten test for filesystem presence
At present listing a partition produces lots of errors about this
filesystem:

   => part list mmc 4
   cannot find valid erofs superblock
   cannot find valid erofs superblock
   cannot read erofs superblock: -5
   [9 more similar lines]

Use debugging rather than errors when unable to find a signature, as is
done with other filesystems.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Gao Xiang <hsiangkao@linux.alibaba.com>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-08-19 04:12:52 +02:00
Jonas Karlman
e34efcf51d rockchip: rk3566-anbernic-rgxx3: Rename defconfig to include SoC name
Rename defconfig to include SoC name, use similar pattern as other
RK356x boards: <soc>-<name>.dts -> <name>-<soc>_defconfig

Suggested-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-18 10:25:03 -04:00
Tom Rini
2d8e7ac320 Merge tag 'tegra-for-2023.10-rc1' of https://source.denx.de/u-boot/custodians/u-boot-tegra
ARM: tegra: Changes for v2023.10-rc1

This adds support for various new Tegra30 boards (ASUS, LG and HTC) and
has some other minor enhancements, such as enabling the poweroff command
on several Tegra210 and Tegra186 boards.
2023-08-18 10:05:04 -04:00
Tom Rini
3a438c1dbc Merge branch '2023-08-17-assorted-minor-fixes'
- More MAINTAINERS updates, update CI to use a newer coreboot and make
  arm-ffa a bit less verbose by default.
2023-08-17 15:01:11 -04:00
Jonas Karlman
a5ce494596 board: rockchip: rk35xx: Add myself as reviewer to MAINTAINERS
Add myself as a reviewer for RK3566/RK3568/RK3588 boards that I have and
can help with review and testing of defconfig and device tree changes.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Acked-by: Eugen Hristev <eugen.hristev@collabora.com>
2023-08-17 15:01:05 -04:00
Jonas Karlman
d17e896d07 board: rockchip: rk35xx: Add device tree files to MAINTAINERS
Update MAINTAINERS files for RK3566/RK3568/RK3588 boards to include
related device tree files. Also replace space with tabs.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Acked-by: Eugen Hristev <eugen.hristev@collabora.com>
2023-08-17 15:01:05 -04:00
Jonas Karlman
11bb3c76bc doc: rockchip: Add supported RK3566/RK3568 boards
Update Rockchip documentation to include RK3566/RK3568 boards already
supported. Also list Pine64 boards under RK3566 and drop defconfig to
match other listed boards.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
2023-08-17 15:01:05 -04:00
Neha Malcom Francis
4901d2499c MAINTAINERS: Update UFS maintainer
Dropping Faiz Abbas from the UFS maintainer list as his e-mail ID is no
longer valid.

Adding Bhupesh Sharma who has been using this framework working on
Qualcomm Snapdragon SoCs as well as sending out fixes.

Adding myself as well to support in reviewing and testing patches.

Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Acked-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-08-17 15:00:59 -04:00
Simon Glass
c60e6a24dd CI: x86: coreboot: Update to latest coreboot
Use a recent coreboot build for this test.

The coreboot commit is:

   6f5ead14b4 mb/google/nissa/var/joxer: Update eMMC DLL settings

This is build with default settings, i.e. QEMU x86 i440fx/piix4

Add some documentation as to how to update it next time.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-08-17 12:29:21 -04:00
Abdellatif El Khlifi
0d9a1262bb corstone1000: update maintainers
Update MAINTAINERS of corstone1000 board.

Signed-off-by: Xueliang Zhong <xueliang.zhong@arm.com>
Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
2023-08-17 12:29:21 -04:00
Abdellatif El Khlifi
67969516b0 arm_ffa: use debug logs
replace info logs with debug logs

Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-08-17 12:29:21 -04:00
Tom Rini
6831a4be29 arm: Add arch/arm/dts/Makefile specifically to MAINTAINERS
In order to reduce the number of people that are cc'd on a patch for
simply touching arch/arm/dts/Makefile (which is a big common file) add
an entry specifically to MAINTAINERS under the ARM entry.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-08-17 11:13:46 -04:00
Tom Rini
375fea811d Merge tag 'u-boot-stm32-20230816' of https://source.denx.de/u-boot/custodians/u-boot-stm
DHSOM: Power cycle Buck3 in reset
DHCOM: Switch DWMAC RMII clock to MCO2
stm32f746: fix display pinmux
stm32mp: psci: Inhibit PDDS because CSTBYDIS is set
stm32mp1: DT alignment with v6.4
stm32mp1: add splashscreen with STMicroelectronics logo
stm32mp1: clk: remove error for disabled clock in stm32mp1_clk_get_parent
serial: stm32: Extend TC timeout
2023-08-16 11:23:58 -04:00
Valentin Caron
9e8cbea1a7 serial: stm32: extend TC timeout
Waiting 150us TC bit couldn't be enough.

If TFA lets 16 bits in USART fifo, we has to wait 16 times 87 us (time
of 10 bits (1 byte in most use cases) at a baud rate of 115200).

Fixes: b4dbc5d65a ("serial: stm32: Wait TC bit before performing initialization")

Signed-off-by: Valentin Caron <valentin.caron@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-08-16 15:38:23 +02:00
Marek Vasut
c9678850bd ARM: dts: stm32: Switch DWMAC RMII clock to MCO2 on DHCOM
The DHCOM SoM has two options for supplying ETHRX clock to the DWMAC
block and PHY. Either (1) ETHCK_K generates 50 MHz clock on ETH_CLK
pad for the PHY and the same 50 MHz clock are fed back to ETHRX via
internal eth_clk_fb clock connection OR (2) ETH_CLK is not used at
all, MCO2 generates 50 MHz clock on MCO2 output pad for the PHY and
the same MCO2 clock are fed back into ETHRX via ETH_RX_CLK input pad
using external pad-to-pad connection.

Option (1) has two downsides. ETHCK_K is supplied directly from either
PLL3_Q or PLL4_P, hence the PLL output is limited to exactly 50 MHz and
since the same PLL output is also used to supply SDMMC blocks, the
performance of SD and eMMC access is affected. The second downside is
that using this option, the EMI of the SoM is higher.

Option (2) solves both of those problems, so implement it here. In this
case, the PLL4_P is no longer limited and can be operated faster, at
100 MHz, which improves SDMMC performance (read performance is improved
from ~41 MiB/s to ~57 MiB/s with dd if=/dev/mmcblk1 of=/dev/null bs=64M
count=1). The EMI interference also decreases.

Ported from Linux kernel commit
73ab99aad50cd ("ARM: dts: stm32: Switch DWMAC RMII clock to MCO2 on DHCOM")

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-08-16 15:37:14 +02:00
Patrick Delaunay
284b08fb51 board: stm32mp1: add splash screen with stmicroelectronics logo
Display the STMicroelectronics logo with features VIDEO_LOGO and
SPLASH_SCREEN on STMicroelectronics boards.

With CONFIG_SYS_VENDOR = "st", the logo st.bmp is selected, loaded at the
address indicated by splashimage and centered with "splashpos=m,m".

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-08-16 15:35:55 +02:00
Patrick Delaunay
61ad1a527a ARM: dts: stm32mp: alignment with v6.4
Device tree alignment with Linux kernel v6.4.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-08-16 15:30:49 +02:00
Marek Vasut
b58ab56d14 ARM: stm32: Inhibit PDDS because CSTBYDIS is set
The PWR_MPUCR CSTBYDIS bit is set, therefore the CA cores can never
enter CStandby state and would always end up in CStop state. Clear
the PDDS bit, which indicates the CA cores can enter CStandby state
as it makes little sense to keep it set with CSTBYDIS also set.

This does however fix a problem too. When both PWR_MPUCR and PWR_MCUCR
PDDS bits are set, then the chip enters CStandby state even though the
PWR_MCUCR CSTBYDIS is set. Clearing the PWR_MPUCR PDDS prevents that
from happening.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2023-08-16 15:29:47 +02:00
Dario Binacchi
fc7bd99f6d ARM: dts: stm32: fix display pinmux for stm32f746-disco
As reported by the datasheet (DocID027590 Rev 4) for PG12:
- AF9  -> LCD_B4
- AF14 -> LCD_B1

So replace AF14 with AF9 for PG12 in the dts.

Fixes: fe63d3cfb7 ("ARM: dts: stm32: Sync DT with v4.20 kernel for stm32f7")
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-08-16 15:27:45 +02:00
Patrick Delaunay
141e232dbd clk: stm32mp1: remove error for disabled clock in stm32mp1_clk_get_parent
To disabled a clock in clock tree initialization for a mux of STM32MP15,
the selected clock source index is set with the latest possible index for
the number of bit used. Today this valid configuration cause a error
in U-Boot messages, for example with CLK_ETH_DISABLED, when this clock
is not needed for the used ETH PHY without crystal:

   no parents defined for clk id 123

This patch change the level of this message to avoid this trace for
valid clock tree.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-08-16 15:23:09 +02:00
Marek Vasut
b3d97f8ce3 ARM: stm32: Power cycle Buck3 in reset on DHSOM
In case the DHSOM is in suspend state and either reset button is pushed
or IWDG2 triggers a watchdog reset, then DRAM initialization could fail
as follows:

  "
  RAM: DDR3L 32bits 2x4Gb 533MHz
  DDR invalid size : 0x4, expected 0x40000000
  DRAM init failed: -22
  ### ERROR ### Please RESET the board ###
  "

Avoid this failure by not keeping any Buck regulators enabled during reset,
let the SoC and DRAMs power cycle fully. Since the change which keeps Buck3
VDD enabled during reset is ST specific, move this addition to ST specific
SPL board initialization so that it wouldn't affect the DHSOM .

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2023-08-16 15:19:57 +02:00
Tom Rini
9b54b0e37b Merge tag 'efi-2023-10-rc3' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request for efi-2023-10-rc3

Documentation:

* Correct description of board_get_usable_ram_top
* Add partition API to HTML documentation
* Describe  lmb_is_reserved
* doc/sphinx/requirements.txt: Bump certifi up

UEFI:

* Fix  efi_add_known_memory
* Make distro_efi_boot() static

Other:

* Correct return type board_get_usable_ram_top
2023-08-15 13:08:17 -04:00
Heinrich Schuchardt
d768dd8855 common: return type board_get_usable_ram_top
board_get_usable_ram_top() returns a physical address that is stored in
gd->ram_top. The return type of the function should be phys_addr_t like the
current type of gd->ram_top.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-08-15 18:21:17 +02:00
Heinrich Schuchardt
b571b3acda efi_loader: fix efi_add_known_memory()
In efi_add_known_memory() we currently call board_get_usable_ram_top() with
an incorrect value 0 of parameter total_size. This leads to an incorrect
value for ram_top depending on the code in board_get_usable_ram_top().

Use the value of gd->ram_top instead which is set before relocation by
calling board_get_usable_ram_top().

Fixes: 7b78d6438a ("efi_loader: Reserve unaccessible memory")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-08-15 18:21:17 +02:00
Bin Meng
6072703dc9 bootmeth: efi: Make distro_efi_boot() static
As it is only called in bootmeth_efi.c

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-08-15 18:21:17 +02:00
Heinrich Schuchardt
5aae021c30 doc: add partition API to HTML documentation
* Convert comments in part.h to Sphinx style.
* Create documentation page for the partition API.
* Add the partition API page to the API index page.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-08-15 18:21:17 +02:00
Heinrich Schuchardt
289bd72ea4 doc: description of board_get_usable_ram_top()
Improve the description of function board_get_usable_ram_top().

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-08-15 18:21:17 +02:00
Heinrich Schuchardt
78246baa8d lmb: description lmb_is_reserved, lmb_is_reserved_flags
* provide a description for function lmb_is_reserved()
* improve the description of funciton lmb_is_reserved_flags()

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-08-15 18:21:17 +02:00
Tom Rini
f26c54ddde doc/sphinx/requirements.txt: Bump certifi up
Upgrade certifi to the latest version, to remove e-Tugra from the root
store.

Link: https://groups.google.com/a/mozilla.org/g/dev-security-policy/c/C-HrP1SEq1A?pli=1
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-08-15 18:21:17 +02:00
Tom Rini
f0efecd27d Merge tag 'ubi-updates-for-v2023.10-rc3' of https://source.denx.de/u-boot/custodians/u-boot-ubi
ubi changes for v2023.10-rc3

Fix:
- Fix 'ubi list' command arguments parsing
  from Dmitry
2023-08-15 10:44:32 -04:00
Tom Rini
ae9de10d5f Merge tag 'i2c-updates-for-v2023.10-rc3' of https://source.denx.de/u-boot/custodians/u-boot-i2c
i2c updates for v2023.10-rc3

Bugfixes:
- mvtwsi driver fix stuck "bus error" state
  from Sam
2023-08-15 10:44:20 -04:00
Dmitry Dunaev
34031e9cce cmd: ubi: Fix 'ubi list' command arguments parsing
This fixes allowed argc variable value for arguments parsing

Fixes: 6de1daf64b ("cmd: ubi: Add 'ubi list' command")
Signed-off-by: Dmitry Dunaev <dunaev@tecon.ru>
2023-08-15 07:32:13 +02:00
Sam Edwards
250454c59b i2c: mvtwsi: reset controller if stuck in "bus error" state
The MVTWSI controller can act either as a master or slave device. When
acting as a master, the FSM is driven by the CPU. As a slave, the FSM is
driven by the bus directly. In what is (apparently) a safety mechanism,
if the bus transitions our FSM in any improper way, the FSM goes to a
"bus error" state (0x00). I could find no documented or experimental way
to get the FSM out of this state, except for a controller reset.

Since U-Boot only uses the MVTWSI controller as a bus master, this
feature only gets in the way: we do not care what happened on the bus
previously as long as the bus is ready for a new transaction. So, when
trying to start a new transaction, check for this state and reset the
controller if necessary.

Note that this should not be confused with the "deblocking" technique
(used by the `i2c reset` command), which involves pulsing SCL repeatedly
if SDA is found to be held low, in an attempt to force the bus back to
an idle state. This patch only resets the controller in case something
else had previously upset it, and (in principle) results in no
externally-observable change in behavior.

Signed-off-by: Sam Edwards <CFSworks@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Heiko Schocher <hs@denx.de>
2023-08-15 06:52:04 +02:00
Tom Rini
832148f675 Merge tag 'u-boot-rockchip-20230814' of https://source.denx.de/u-boot/custodians/u-boot-rockchip
- Add board: rk3568 EmbedFire Lubancat 2
- Fixes for rk3568 clock and pinctrl;
- Fixes for rk3308 clock and uart;
- rk3328 rock64 updates;
- Video fix on veyron board;
2023-08-14 09:11:09 -04:00
Tom Rini
70c45244d9 Merge tag 'video-20230814' of https://source.denx.de/u-boot/custodians/u-boot-video
- fix NULL dereference in vidconsole_measure()
 - fix simplefb format for raspberrypi-4b
 - fix typo in Kconfig
2023-08-14 09:09:23 -04:00
Jonas Karlman
d7009faa09 pinctrl: rockchip: Fix drive and input schmitt on RK3568
On RK3568 most pins have a configurable drive strength of level 0-5 and
some pins level 0-11. When rk3568_set_drive is called with a strength
value above 7 the drv value written to reg may overflow into the write
enable bits, resulting in a bad configuration.

This cause e.g. ethernet PHY on Radxa CM3-IO board not to work after
drive is configured according to the device tree.

  Could not get PHY for ethernet@fe010000: addr 0

Level 6-11 can be configured using a second reg for some pins, however
the drv value is reused resulting in lower 6 bits being written to reg.

Input schmitt is configured in 2-bit fields on RK3568 compared to
earlier generation and 2'b10 should be used to enable input schmitt.

Change to use regmap_update_bits with a rmask to fix the overflow issue
and closer match the linux driver. Bit shift the drv value used for the
second reg to configure drive strength level 6-11. Also write correct
values for input schmitt setting.

Fixes: 1977d746aa ("rockchip: rk3568: add rk3568 pinctrl driver")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-14 11:07:27 +08:00
Meng Li
04cc66c047 rpi: set the correct parameter for simple framebuffer node
When raspberrpi-4b platform  boots up, there are 2 sets of same bootup
log displayed on HDMI monitor screen, it looks like the screen is split
into 2 parts. The root cause is that video format of u-boot is different
from kernel. The fixing "a8r8g8b8" video format is used in u-boot, but
"r5g6b5" video format from framebuffer node is used in kernel image. In
order to avoid weird display status on screen, it needs to set the correct
parameter for simple framebuffer node even if it has existed.

Signed-off-by: Meng Li <Meng.Li@windriver.com>
2023-08-13 23:57:46 +02:00
Jason Wessel
28cd244e84 bcm2835: Add simiple-framebuffer for use with fkms
When the fkms dtb overlay is used only the simple-framebuffer is
presented as a usable video display. So, add "simple-framebuffer"
compatible to enable video driver bcm2835.

Signed-off-by: Jason Wessel <jason.wessel@windriver.com>
Signed-off-by: Meng Li <Meng.Li@windriver.com>
2023-08-13 23:55:57 +02:00
Bin Meng
aba6776a71 video: kconfig: Fix a typo in SPL_VIDEO_REMOVE
Add one space between 'before' and 'loading'.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-08-13 23:09:23 +02:00
Bin Meng
01c76f1a64 video: vidconsole: Fix null dereference of ops->measure
At present vidconsole_measure() tests ops->select_font before calling
ops->measure, which would result in a null dereference when the console
driver provides no ops for measure.

Fixes: b828ed7d79 ("console: Allow measuring the bounding box of text")
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-08-13 23:08:15 +02:00
Hai Pham
bb89d926fc ARM: rmobile: Update little‐endian byte order option in srec_cat command
Since srecord v1.60, option "-Little_Endian_CONSTant" is deprecated.
Fix the build warnings by updating little‐endian byte order option in
srec_cat command when generating loader header.

Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-08-13 00:05:38 +02:00
Marek Vasut
a2bd99549c clk: renesas: Tear clock controller down last before booting OS
Once all the other drivers got torn down in preparation for the OS
to start, tear down the clock controller last. The clock controller
must be torn down last as some of the clock which get turned off
might have still been needed during the teardown stage of the other
drivers.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Tam Nguyen <tam.nguyen.xa@renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
2023-08-13 00:03:36 +02:00
FUKAUMI Naoki
a73a28b329 rockchip: MAINTAINERS: fix board name for Radxa ROCK 4C+
align with other ROCK series.

Fixes: 2b506407c8 ("rockchip: Add MAINTAINERS entry for Radxa Rock 4C+")
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12 10:39:51 +08:00
Massimo Pegorer
c71321c7c6 dts: rockchip: rk3308: Avoid warning for serial probe on prereloc
Make device tree complete and consistent for pre relocation phase. Some
nodes are missing, causing warnings to be issued on serial port probing
during pre relocation phase (uclass_get_device_by_phandle_id fails when
called by pinctrl_select_state_full: none of these failures is fatal
nor causing issues). Add to *-u-boot.dtsi all required nodes with the
'bootph-some-ram' attribute.

Signed-off-by: Massimo Pegorer <massimo.pegorer+oss@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12 10:37:57 +08:00
Massimo Pegorer
0cd87aac5c clk: rockchip: rk3308: Support reading UART rate and clock registers
Add support to read RK3308 registers used to configure UART clocks, and
thus to get UART rate and baudrate. This fixes clock_get_rate returning
error on serial device probing. Moreover, there is no need anymore to
use 'clock-frequency' property for UART nodes in *-u-boot.dtsi files
for all cases where UART is not inited by U-Boot proper or by SPL o by
TPL code but by a preliminary external boot phase (for Rock PI S, UART
is inited by external TPL).

Signed-off-by: Massimo Pegorer <massimo.pegorer+oss@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12 10:37:57 +08:00
Massimo Pegorer
e4c6ccc687 clk: rockchip: rk3308: Fix ordering between masking and shifting
As per definitions of masks and shift offsets in cru_rk3308.h, values
read from registers must be first masked and then shifted. By the way,
this fix is binary invariant, because in all of fixed cases the shift
offset is zero.

Signed-off-by: Massimo Pegorer <massimo.pegorer+oss@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12 10:37:57 +08:00
Massimo Pegorer
36adce7372 rockchip: spl: Drop out of scope debug message related to uart init
Debug uart is no more inited in board_init_f function: remove this
debug message from board_init_f. If an earliest-as-possible message
after debug uart initialization is needed, enable DEBUG_UART_ANNOUNCE
Kconfig option, instead.

Signed-off-by: Massimo Pegorer <massimo.pegorer+oss@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12 10:37:32 +08:00
Massimo Pegorer
08e74ac3d9 rockchip: spl: Drop useless call to debug_uart_init
Since commit 0dba45864b ("arm: Init the debug UART") function
debug_uart_init is called in crt files _main before calling
board_init_f. Therefore, there is no need to call it again
inside board_init_f implementation in arm/mach-rockchip/spl.c.

Signed-off-by: Massimo Pegorer <massimo.pegorer+oss@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12 10:37:32 +08:00
Jonas Karlman
520fece4ca rockchip: rk356x-u-boot: Set max-frequency prop in sdhci node
Most board device trees for RK356x set max-frequency = <200000000> in
the sdhci node, some boards like Quartz64 do not. This result in an
error message due to sdhci driver trying to set a clock rate of 0
instead of the max-frequency value.

  rockchip_sdhci_probe clk set rate fail!

Fix this by setting a common max-frequency in rk356x-u-boot.dtsi. A
patch to set default max-frequency of sdhci node in linux is planned.

Also remove the forced status = "okay" for the sdhci and sdmmc0 nodes,
boards already set correct state for these nodes.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12 10:35:35 +08:00
Jonas Karlman
9296f9a8d7 clk: rockchip: rk3568: Add dummy support for GMAC speed clocks
Pine64 Quartz64 boards DT reference SCLK_GMAC1_RGMII_SPEED in the
assigned-clocks property of the gmac1 node. This result in a ENOENT
error when driver core tries to set a parent for this clock.

The clock speed in rgmii/rmii mode is changed using clk_set_rate of the
tx_rx clock and not using clk_set_parent of the speed clock.

Add dummy support for SCLK_GMAC1_RGMII_SPEED and similar clocks to clk
driver to allow a driver for gmac node to probe.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12 10:35:35 +08:00
Jonas Karlman
ff46cd5631 clk: rockchip: rk3568: Include UART clocks in SPL
The clock driver for RK3568 does not include support for UART clocks in
SPL. This result in the following message with high enough loglevel.

  ns16550_serial serial@fe660000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19

Fix this by including support for UART clocks in SPL.

Fixes: 4a262feba3 ("rockchip: rk3568: add clock driver")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12 10:35:35 +08:00
Jonas Karlman
6da8400d7a clk: rockchip: rk3568: Fix mask for clk_cpll_div_25m_div
The field for clk_cpll_div_25m_div in CRU_CLKSEL_CON81 is 6 bits wide,
not 5 bits wide as currently defined in CPLL_25M_DIV_MASK.

Fix this and the assert so that CPLL_25M can be assigned a 25 MHz rate.

Fixes: 4a262feba3 ("rockchip: rk3568: add clock driver")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12 10:35:35 +08:00
Damon Ding
acb9812034 clk: rockchip: rk3568: Fix clk selection in rk3568_pwm_get_clk
Fix use of wrong clk selection for CLK_PWM1 on RK3568.

Fixes: 4a262feba3 ("rockchip: rk3568: add clock driver")
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12 10:35:35 +08:00
Anton
6e710897aa rockchip: cru: Enable cpu info support for rk3568
Add cru structure definition in head file to support cpu_info driver.

Series-version: 2
Series-changes: 2
Format the patch header, add commit message and signature.

Signed-off-by: Anton <vao@asu-vei.ru>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12 10:28:30 +08:00
Alvaro Fernando García
8300cebcd6 video: avoid build failure on veyron board
533ad9dc avoided an overflow but causes compilation
failure on 32bit boards (eg. veyron speedy)

this commit uses div_u64 which has a fallback codepath
for 32bit platforms

Signed-off-by: Alvaro Fernando García <alvarofernandogarcia@gmail.com>
Tested-by: Simon Glass <sjg@chromium.org>  # chromebook_jerry
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12 10:18:12 +08:00
Andy Yan
bb38db086c rockchip: rk3568: Add EmbedFire Lubancat 2 support
LubanCat2 is a rk3568 based SBC from EmbedFire.

Specification:
- Rockchip rk3568
- LPDDR4/4X 1/2/4/8 GB
- TF scard slot
- eMMC 8/32/64/128 GB
- Gigabit ethernet x 2
- HDMI out
- USB 2.0 Host x 1
- USB 2.0 Type-C OTG x 1
- USB 3.0 Host x 1
- Mini PCIE interface for WIFI/BT module
- M.2 key for 2280 NVME
- 40 pin header

The dts file is sync from linux mainline.

Signed-off-by: Andy Yan <andyshrk@163.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12 10:17:59 +08:00
Jagan Teki
2fa09b455a rockchip: rv1126: Enable fdtoverlay support
Add fdtoverlay_addr_r and enable OF_LIBFDT_OVERLAY for the
use of DT overlay in RV1126.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12 10:14:51 +08:00
Peter Robinson
10e38327f0 rockchip: dts: rk3328: rock64: Align spi flash entry
Align the SPI flash entry with upstream. There's no need
to diverge here.

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12 10:13:44 +08:00
Peter Robinson
080030f276 rockchip: dts: rk3328: Add rng details to u-boot.dtsi
Add the rk3328 rng details to the u-boot.dtsi and
enable the RNG on the Rock64 to be able to provide
a random seed via UEFI.

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
(Fix typo message)
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12 10:13:14 +08:00
Peter Robinson
a13a7a0b45 config: rock64: enable efuse for stable mac addr
Enable the rockchip efuse driver on the Rock64 to
provide a stable ethernet address on the device.

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12 10:13:06 +08:00
Jonas Karlman
0e2474f550 pci: rockchip: Release resources on failing probe
The PCIe driver for RK3399 is affected by a similar issue that was fixed
for RK35xx in the commit e04b67a7f4 ("pci: pcie_dw_rockchip: release
resources on failing probe").

Resources are not released on failing probe, e.g. regulators may be left
enabled and the ep-gpio may be left in a requested state.

Change to use regulator_set_enable_if_allowed and disable regulators
after failure to keep regulator enable count balanced, ep-gpio is also
released on regulator failure.

Also add support for the vpcie12v-supply, remove unused include and
check return value from dev_read_addr_name.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12 09:59:18 +08:00
Quentin Schulz
e5422ea512 rockchip: rk3399: remove duplicate call to regulators_enable_boot_on
An earlier commit makes the common SPL code call
regulators_enable_boot_on and regulators_enable_boot_off before
iterating over possible boot media for U-Boot proper. There is therefore
no need to do this in the rk3399-specific code, so let's remove it.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Tested-by: Xavier Drudis Ferran <xdrudis@tinet.cat>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2023-08-12 09:58:55 +08:00
Tom Rini
a5899cc69a Merge https://source.denx.de/u-boot/custodians/u-boot-watchdog
- cmd: cyclic: Remove duplicate command name in help text (Alexander)
- ftwdt010: need to reset watchdog in ftwdt010_wdt_start() (Sergei)
2023-08-10 11:40:09 -04:00
Tom Rini
824f104422 Merge https://source.denx.de/u-boot/custodians/u-boot-riscv
+ Add USB host support on VisionFive2 board
+ Enable SPI flash support on VisionFive2 board
+ Enable Random Number Generator in RISC-V QEMU board
+ Display new SBI extension
+ Add SPL_ZERO_MEM_BEFORE_USE Kconfig for jh7110 L2 LIM
  (Loosely-Integrated Memory)
2023-08-10 10:36:43 -04:00
Sergei Antonov
160984ed3a watchdog: ftwdt010: need to reset watchdog in ftwdt010_wdt_start()
ftwdt010_wdt_start() has to call ftwdt010_wdt_reset() after setting-up
the timeout in the same fashion ftwdt010_wdt_expire_now() does it.

Without this patch the "wdt start <ms>" command does not actually start
the watchdog timer until the "wdt reset" command is executed.

Signed-off-by: Sergei Antonov <saproj@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2023-08-10 08:39:16 +02:00
Alexander Dahl
8ba4eae01d cmd: cyclic: Remove duplicate command name in help text
Function 'cmd_usage()' already prints one command in usage before
printing out the help text given to the U_BOOT_CMD_WITH_SUBCMDS macro.

Wrong previous output:

    Usage:
    cyclic cyclic demo <cycletime_ms> <delay_us> - register cyclic demo function
    cyclic list - list cyclic functions

Signed-off-by: Alexander Dahl <ada@thorsis.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2023-08-10 08:39:11 +02:00
Shengyu Qu
47ed15125c riscv: cpu: jh7110: Select SPL_ZERO_MEM_BEFORE_USE
Add Kconfig item for Starfive JH7110 to select SPL_ZERO_MEM_BEFORE_USE.

Signed-off-by: Bo Gan <ganboing@gmail.com>
Signed-off-by: Shengyu Qu <wiagn233@outlook.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-08-10 10:58:55 +08:00
Shengyu Qu
6419f8e9fd riscv: Add SPL_ZERO_MEM_BEFORE_USE implementation
Add the actual support code for SPL_ZERO_MEM_BEFORE_USE and remove
existing Starfive JH7110's L2 LIM clean code, since existing code has
following issues:
 1. Each hart (in the middle of a function call) overwriting its own
    stack and other harts' stacks.
    (data-race and data-corruption)
 2. Lottery winner hart can be doing "board_init_f_init_reserve",
    while other harts are in the middle of zeroing L2 LIM.
    (data-race)

Signed-off-by: Bo Gan <ganboing@gmail.com>
Signed-off-by: Shengyu Qu <wiagn233@outlook.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-08-10 10:58:12 +08:00
Shengyu Qu
d365f6646a riscv: Kconfig: Add SPL_ZERO_MEM_BEFORE_USE
Add a Kconfig item to allow SPL to clear stack/GD/malloc area before
using them.

Signed-off-by: Bo Gan <ganboing@gmail.com>
Signed-off-by: Shengyu Qu <wiagn233@outlook.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-08-10 10:58:12 +08:00
Shengyu Qu
7d79bed00c configs: starfive: Enable environment in SPI flash support
On Starfive Visionfive 2, the u-boot environment settings are saved to
on-board SPI flash. Enable relative configs by default and set offset
and size according to upstream linux dts.

Signed-off-by: Shengyu Qu <wiagn233@outlook.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-08-10 10:58:07 +08:00
Minda Chen
0665621386 configs: riscv: starfive: Add VF2 PCIe USB3 XHCI support
Add XHCI_PCI to enable usb3-host functions.
Also add usb command and keyboard config.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-08-10 10:58:01 +08:00
Minda Chen
eca2d41c68 riscv: starfive: Add SYS_CACHE_SHIFT_6 to enable SYS_CACHELINE_SIZE
Some device driver need SYS_CACHELINE_SIZE macro. Add StarFive
SYS_CACHE_SHIFT_6 to enable it.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-08-10 10:58:01 +08:00
Minda Chen
1037c5ba37 riscv: dts: starfive: Enable pcie0 dts node
In StarFive VF2 board. pcie0 connect to VTI usb controller.
Enable it to support usb host.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-08-10 10:58:01 +08:00
Minda Chen
8d184d4b65 pci: plda: Get correct ECAM offset in multiple PCIe RC case
Get the correct ECAM offset and record the secondary bus
number in Multiple RC case.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-08-10 10:58:01 +08:00
Heinrich Schuchardt
6982e6b046 cmd/sbi: display new extensions
The SBI specification v2.0-rc2 defines new extensions:

* Nested Acceleration Extension (NACL)
* Steal Time Accounting (STA)

Allow the sbi command to display these.

Add missing implementation IDs.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-08-10 10:57:56 +08:00
Heinrich Schuchardt
1b7de4f9ef riscv: qemu: imply CONFIG_DM_RNG
The EFI_RNG_PROTOCOL is needed for Linux' KASLR.

QEMU can provide a virtio-rng device to emulate a hardware random number
generator which is supported by our virtio_rng driver.

Enabling CONFIG_DM_RNG will enable CONFIG_VIRTIO_RNG and
CONFIG_EFI_RNG_PROTOCOL by default too.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-08-10 10:57:36 +08:00
Tom Rini
ec58228830 Merge tag 'x86-pull-20230809' of https://source.denx.de/u-boot/custodians/u-boot-x86
- x86: Fixes for distro booting
- x86: Move some boards to text environment
2023-08-09 13:17:34 -04:00
Simon Glass
9234b77b9d x86: qemu-x86: Convert to text environment
Use the common include.

Drop everything from the config.h file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> # Intel Edison
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-08-09 23:31:12 +08:00
Simon Glass
3cc4095362 x86: qemu: Add required linux/sizes.h include
These files rely on the config.h file provided this include. Add it
explictily so we can move to a text environment.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> # Intel Edison
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-08-09 23:31:12 +08:00
Simon Glass
17b2398534 x86: efi-x86_payload: Convert to text environment
Use the common include.

Drop everything from the config.h file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> # Intel Edison
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-08-09 23:31:12 +08:00
Simon Glass
6ed1cb3552 x86: efi-x86_app: Convert to text environment
Use the common include. Drop the unnecessary changes, since missing
stdio drivers will be ignored.

Drop everything from the config.h file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> # Intel Edison
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-08-09 23:31:12 +08:00
Simon Glass
2d6ebda756 x86: slimbootloader: Convert to text environment
Use the common include along with some additions.

Drop everything from the config.h file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> # Intel Edison
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[Drop common env from slimbootloader.env]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2023-08-09 23:31:12 +08:00
Simon Glass
d9e6318ce9 x86: minnowmax: Convert to text environment
Use the common include along with some additions.

Drop everything from the config.h file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> # Intel Edison
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-08-09 23:31:12 +08:00
Simon Glass
c166298ed2 x86: cougarcanyon2: Convert to text environment
Use the common include. The existing environment includes "vga" but that
is not valid anymore, so let it use vidconsole

Drop everything from the config.h file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> # Intel Edison
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-08-09 23:31:12 +08:00
Simon Glass
5ccb18a752 x86: cherryhill: Convert to text environment
Use the common include.

Drop everything from the config.h file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> # Intel Edison
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-08-09 23:31:12 +08:00
Simon Glass
a68a7abc3d x86: edison: Convert to text environment
Don't use the common include since Edison's environment is empty.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> # Intel Edison
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-08-09 23:31:12 +08:00
Simon Glass
b5948c5d39 x86: galileo: Convert to text environment
Use the common include.

Drop everything from the config.h file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> # Intel Edison
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-08-09 23:31:12 +08:00
Simon Glass
df827efecd x86: bayleybay: Convert to text environment
Use the common include.

Drop everything from the config.h file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> # Intel Edison
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-08-09 23:31:12 +08:00
Simon Glass
f1e7abf4b9 x86: crownbay: Convert to text environment
Use the common include.

Drop everything from the config.h file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> # Intel Edison
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-08-09 23:31:12 +08:00
Simon Glass
c49a767a6a x86: coreboot: Convert to text environment
Use the common include and add some options specific to this board.

Drop everything from the config.h file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> # Intel Edison
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-08-09 23:31:12 +08:00
Simon Glass
876bc404bd x86: Add a common include for environment settings
Create a text-file version of x86-common.h which can be used by x86
boards.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> # Intel Edison
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-08-09 23:31:12 +08:00
Simon Glass
f726545a62 x86: Drop unused distro settings
No x86 board uses distro boot, so drop these settings.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> # Intel Edison
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-08-09 23:31:12 +08:00
Simon Glass
8c0090b069 x86: Drop inclusion of ibmpc.h
This is not needed in this file anymore. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> # Intel Edison
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-08-09 23:31:12 +08:00
Simon Glass
c0def3207d x86: edison: Drop inclusion of ibmpc.h
This should be included by files that need it, not the config.h file.
Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> # Intel Edison
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-08-09 23:31:12 +08:00
Simon Glass
dbfb6c096e x86: i8254: Include required ibmpc.h header
This is needed for this file, so include it here explicitly.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> # Intel Edison
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-08-09 23:31:12 +08:00
Simon Glass
edd53bda53 x86: Drop CFG_SYS_STACK_SIZE
This is only used in one file and the value is the same for both boards
which define it. Use the fixed value of 32KB and drop the CFG. This will
allow removal of the config.h files.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> # Intel Edison
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-08-09 23:31:12 +08:00
Simon Glass
63af90e7f0 env: Explain how to use #include files in text environment
Provide documentation on how to share common settings among boards.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> # Intel Edison
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-08-09 23:31:12 +08:00
Simon Glass
5e541a05f7 env: Use include/env for text-environment includes
The 'environment' word is too long. We mostly use 'env' in U-Boot, so use
that as the name of the include directory too.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> # Intel Edison
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-08-09 23:31:12 +08:00
Simon Glass
f26a966b2e doc: Explain how to avoid the distro-boot scripts
Now that standard boot is available, mention this in the environment
documentation.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> # Intel Edison
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-08-09 23:31:12 +08:00
Simon Glass
b985760b7e x86: Update qemu documentation
Add some hints and observations related to booting distros on QEMU on x86.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-08-09 23:31:12 +08:00
Simon Glass
cfa5934979 x86: Enable useful options for qemu-86
This build can be used to boot 32-bit standard-distro builds. Enable some
more options, so that all possible EFI UUIDs are decoded, we can search
memory for tables, support the full set of standard-boot features, have
full logging along with debug UART and can boot from CDROM media.

This mirrors a similar patch for qemu-x86_64

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[Drop the unknown option from defconfig]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2023-08-09 23:31:12 +08:00
Simon Glass
b7080bfceb video: Add a Kconfig option for SPL video handoff
At present this feature is enabled in SPL if a bloblist is available.
Some platforms may not want to use this, so add an option to allow the
feature to be disabled.

Note that the feature unfortunately only fills in part of the
video-handoff information, so causes failures on x86 platforms. For now,
disable it there.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com> # qemu-x86_64
2023-08-09 23:31:11 +08:00
Simon Glass
4099df48a6 x86: Correct copying of BIOS mode information
This is copying beyond the end of the destination buffer. Correct the code
by using the size of the  vesa_mode_info struct. We don't need to copy the
rest of the bytes in the buffer.

This long-standing bug prevents virtio bootdevs working correctly on
qemu-x86 at present.

Fixes: 0ca2426bea ("x86: Add support for running option ROMs natively")
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com> # qemu-x86_64
2023-08-09 23:31:11 +08:00
Simon Glass
1fa64e155d Revert "x86: Switch QEMU over to use the bochs driver"
Unfortunately the bochs driver does not currently work with distros.
It causes a hang between grub menu selection and the OS displaying
something.

Preliminary investigation shows that GRUB does not jump to the kernel
at all.

This reproduces reliably.

This reverts commit b8956425d5.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com> # qemu-x86_64
[Slightly modify the commit message about preliminary investigation]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2023-08-09 23:31:11 +08:00
Simon Glass
ea6eef27ca x86: Run QEMU machine setup in SPL
Call the hardware-init function from QEMU from SPL. This allows the
video BIOS to operate correctly.

Create an x86-wide qemu.h header to avoid having to #ifdef the header
in spl.c

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com> # qemu-x86_64
2023-08-09 23:31:11 +08:00
Simon Glass
d5a3f14c23 video: Tidy up Makefile rule for video
Drop the duplication and add a single rule which can handle SPL as well.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Nikhil M Jain <n-jain1@ti.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-08-09 23:31:11 +08:00
Simon Glass
22080e05fc x86: spl: Drop unwanted debug()
This was left over from some previous debugging. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-08-09 23:31:11 +08:00
Simon Glass
d60fb7a958 x86: coreboot: Update doc for CBFS access
Add an example to show how cbfs is used.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[Removed CONFIG_CMD_CBFS from defconfig files]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2023-08-09 23:31:11 +08:00
Simon Glass
3500ae13c6 bootstd: Add some more debugging in the bootdev uclass
Add some more output to make it easier to see what is going wrong when
a bootdev hunter fails.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-08-09 23:31:11 +08:00
Simon Glass
2d5b5a9cdb bootstd: Correct creating of bootdev sibling
Use the correct function here, since there may be multiple IDE devices
available.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
2023-08-09 23:31:11 +08:00
Simon Glass
d7d78576bb bootstd: Rename bootdev_setup_sibling_blk()
This name is a little confusing since it suggests that it sets up the
sibling block device. In fact it sets up a bootdev for it. Rename the
function to make this clearer.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
2023-08-09 23:31:11 +08:00
Simon Glass
3a3543db51 lib: Suppress E when writing error-string output
When CONFIG_ERRNO_STR is not enabled this shows a spurious 'E' from the
format string. Fix this.

Fixes: 7f33194132 ("lib: Support printing an error string")
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-08-09 23:31:11 +08:00
Simon Glass
4c4ccc5a04 usb: Return -ENOENT when no devices are found
When USB finds no devices it currently returns -EPERM which bootstd does
not understand. This causes other bootdevs of the same priority to be
skipped.

Fix this by returning the correct error code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-08-09 23:31:11 +08:00
Tom Rini
f26eda936b Merge tag 'doc-2023-10-rc3' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request for doc-2023-10-rc3

Documentation:

* Update examples for imx8mp_evk
* OpenOCD debugging guide for TI K3 boards
* Explain using gadget devices on TI boards
* Describe best practices for board ports
2023-08-09 08:28:50 -04:00
Tom Rini
5852b1d2c3 Merge tag 'fsl-qoriq-2023-8-9' of https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq
- Drop one unused function for layerscape
2023-08-09 08:28:27 -04:00
Shenlin Liang
0f621ca9b9 arm64: fsl: layerscape: Remove unused functions
Function board_switch_core_volt has not been used since it was
defined

Signed-off-by: Shenlin Liang <liangshenlin@eswincomputing.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-08-09 16:17:53 +08:00
Tom Rini
fa43709b8d doc: Begin adding a best practices document for board ports
To help guide developers down the right path, begin a document that
lists some best practices to follow when creating a new board port.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-08-09 08:41:52 +02:00
Fabio Estevam
8134043dad doc: imx8mp_evk: Use in-tree build in the example
To make it consistent with the instructions from other NXP imx8m boards,
such as imx8mm-evk and imx8mn-evk, use U-Boot in-tree build in the
examples.

Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-08-09 08:41:52 +02:00
Fabio Estevam
961519b58d doc: imx8mp_evk: Remove unneeded export ATF_LOAD_ADDR line
Originally, exporting the ATF_LOAD_ADDR was required, but since binman has
been used to generate the flash.bin, it is no longer needed to do
such manual export.

The ATF address is now passed via binman in imx8mp-u-boot.dtsi:

	atf {
		description = "ARM Trusted Firmware";
		type = "firmware";
		arch = "arm64";
		compression = "none";
		load = <0x970000>;
		entry = <0x970000>;

		atf_blob: atf-blob {
			filename = "bl31.bin";
			type = "atf-bl31";
		};
	};

Remove the  unneeded export ATF_LOAD_ADDR line.

Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-08-09 08:41:52 +02:00
Miquel Raynal
c631cf84db doc: ti: Explain how the various gadget devices can be used
Describe the current situation wrt the handling of USB devices on AM33xx
based boards, taking the example of a common board (the Beagle Bone
Black) and explaining how the different USB gadgets can be used.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2023-08-09 08:41:52 +02:00
Marcel Ziswiler
636acb4022 doc: board: toradex: fix verdin module output
Fix the Verdin module output which was missing white space for correct
rendering.

While at it also leave product links, add section author also for the
Verdin iMX8M Mini and Plus, and add a missing CROSS_COMPILE export for
the Verdin iMX8M Mini.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Nishanth Menon <nm@ti.com> #verdin-am62
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-08-09 08:41:52 +02:00
Jit Loon Lim
b8531ac4d1 doc: Add the link for the documentation of the .its
Provide the link for the .its related documentation for Arria10.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
2023-08-09 08:41:52 +02:00
Jason Kacines
effe50854a doc: board: ti: k3: Add a guide to debugging with OpenOCD
Bootloader debug usually tends to be a bit dicey prior to DDR and
serial port getting active in the system. JTAG typically remains the
only practical debug option during the initial bringup.

OpenOCD is one of the most popular environment for providing debug
capability via a GDB compatible interface for developers to work with.

Debugging U-Boot and bootloaders on K3 platform does have a bit of
tribal knowledge that is better documented in our common platform
documentation.

Signed-off-by: Jason Kacines <j-kacines@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2023-08-09 08:41:52 +02:00
Tom Rini
ef8336e270 Merge branch '2023-08-08-introuce-Arm-FF-A-support'
To quote the author:
Adding support for Arm FF-A v1.0 (Arm Firmware Framework for Armv8-A) [A].

FF-A specifies interfaces that enable a pair of software execution
environments aka partitions to communicate with each other. A partition
could be a VM in the Normal or Secure world, an application in S-EL0, or
a Trusted OS in S-EL1.

FF-A is a discoverable bus and similar to architecture features.
FF-A bus is discovered using ARM_SMCCC_FEATURES mechanism performed by
the PSCI driver.

   => dm tree

    Class     Index  Probed  Driver                Name
   -----------------------------------------------------------
   ...
    firmware      0  [ + ]   psci                      |-- psci
    ffa                   0  [   ]   arm_ffa               |   `-- arm_ffa
   ...

Clients are able to probe then use the FF-A bus by calling the DM class
searching APIs (e.g: uclass_first_device).

This implementation of the specification provides support for Aarch64.

The FF-A driver uses the SMC ABIs defined by the FF-A specification to:

    - Discover the presence of secure partitions (SPs) of interest
    - Access an SP's service through communication protocols
      (e.g: EFI MM communication protocol)

The FF-A support provides the following features:

    - Being generic by design and can be used by any Arm 64-bit platform
    - FF-A support can be compiled and used without EFI
    - Support for SMCCCv1.2 x0-x17 registers
    - Support for SMC32 calling convention
    - Support for 32-bit and 64-bit FF-A direct messaging
    - Support for FF-A MM communication (compatible with EFI boot time)
    - Enabling FF-A and MM communication in Corstone1000 platform as a use case
    - A Uclass driver providing generic FF-A methods.
    - An Arm FF-A device driver providing Arm-specific methods and reusing the Uclass methods.
    - A sandbox emulator for Arm FF-A, emulates the FF-A side of the Secure World and provides
      FF-A ABIs inspection methods.
    - An FF-A sandbox device driver for FF-A communication with the emulated Secure World.
      The driver leverages the FF-A Uclass to establish FF-A communication.
    - Sandbox FF-A test cases.
    - A new command called armffa is provided as an example of how to access the
      FF-A bus

For more details about the FF-A support please refer to [B] and refer to [C] for
how to use the armffa command.

Please find at [D] an example of the expected boot logs when enabling
FF-A support for a platform. In this example the platform is
Corstone1000. But it can be any Arm 64-bit platform.

More details:

[A]: https://developer.arm.com/documentation/den0077/latest/
[B]: doc/arch/arm64.ffa.rst
[C]: doc/usage/cmd/armffa.rst
[D]: example of boot logs when enabling FF-A
2023-08-08 15:23:16 -04:00
Abdellatif El Khlifi
13f3470adc arm_ffa: efi: corstone1000: enable MM communication
turn on EFI MM communication

On Corstone-1000 platform MM communication between u-boot
and the secure world (Optee) is done using the FF-A bus.

Changes made are generated using savedefconfig.

Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Cc: Jens Wiklander <jens.wiklander@linaro.org>
2023-08-08 10:23:32 -04:00
Abdellatif El Khlifi
218b062e8f arm_ffa: efi: introduce FF-A MM communication
Add MM communication support using FF-A transport

This feature allows accessing MM partitions services through
EFI MM communication protocol. MM partitions such as StandAlonneMM
or smm-gateway secure partitions which reside in secure world.

An MM shared buffer and a door bell event are used to exchange
the data.

The data is used by EFI services such as GetVariable()/SetVariable()
and copied from the communication buffer to the MM shared buffer.

The secure partition is notified about availability of data in the
MM shared buffer by an FF-A message (door bell).

On such event, MM SP can read the data and updates the MM shared
buffer with the response data.

The response data is copied back to the communication buffer and
consumed by the EFI subsystem.

MM communication protocol supports FF-A 64-bit direct messaging.

We tested the FF-A MM communication on the Corstone-1000 platform.

We ran the UEFI SCT test suite containing EFI setVariable, getVariable and
getNextVariable tests which involve FF-A MM communication and all tests
are passing with the current changes.

We made the SCT test reports (part of the ACS results) public following the
latest Corstone-1000 platform software release. Please find the test
reports at [1].

[1]: https://gitlab.arm.com/arm-reference-solutions/arm-reference-solutions-test-report/-/tree/master/embedded-a/corstone1000/CORSTONE1000-2023.06/acs_results_fpga.zip

Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
Tested-by: Gowtham Suresh Kumar <gowtham.sureshkumar@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Cc: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Cc: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-08-08 10:22:03 -04:00
Abdellatif El Khlifi
f16a48fec9 arm_ffa: introduce armffa command
Provide armffa command showcasing the use of the U-Boot FF-A support

armffa is a command showcasing how to invoke FF-A operations.
This provides a guidance to the client developers on how to
call the FF-A bus interfaces. The command also allows to gather secure
partitions information and ping these  partitions. The command is also
helpful in testing the communication with secure partitions.

For more details please refer to the command documentation [1].

A Sandbox test is provided for the armffa command.

[1]: doc/usage/cmd/armffa.rst

Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Cc: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Cc: Jens Wiklander <jens.wiklander@linaro.org>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
2023-08-08 10:22:03 -04:00
Abdellatif El Khlifi
a2f5c91cda arm_ffa: introduce sandbox test cases for UCLASS_FFA
Add functional test cases for the FF-A support

These tests rely on the FF-A sandbox emulator and FF-A
sandbox driver which help in inspecting the FF-A communication.

Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Cc: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Cc: Jens Wiklander <jens.wiklander@linaro.org>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
2023-08-08 10:22:03 -04:00
Abdellatif El Khlifi
a09852d862 arm_ffa: introduce sandbox FF-A support
Emulate Secure World's FF-A ABIs and allow testing U-Boot FF-A support

Features of the sandbox FF-A support:

- Introduce an FF-A emulator
- Introduce an FF-A device driver for FF-A comms with emulated Secure World
- Provides test methods allowing to read the status of the inspected ABIs

The sandbox FF-A emulator supports only 64-bit direct messaging.

Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Cc: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Cc: Jens Wiklander <jens.wiklander@linaro.org>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
2023-08-08 10:22:03 -04:00
Abdellatif El Khlifi
39d383bdac arm_ffa: introduce Arm FF-A support
Add Arm FF-A support implementing Arm Firmware Framework for Armv8-A v1.0

The Firmware Framework for Arm A-profile processors (FF-A v1.0) [1]
describes interfaces (ABIs) that standardize communication
between the Secure World and Normal World leveraging TrustZone
technology.

This driver uses 64-bit registers as per SMCCCv1.2 spec and comes
on top of the SMCCC layer. The driver provides the FF-A ABIs needed for
querying the FF-A framework from the secure world.

The driver uses SMC32 calling convention which means using the first
32-bit data of the Xn registers.

All supported ABIs come with their 32-bit version except FFA_RXTX_MAP
which has 64-bit version supported.

Both 32-bit and 64-bit direct messaging are supported which allows both
32-bit and 64-bit clients to use the FF-A bus.

FF-A is a discoverable bus and similar to architecture features.
FF-A bus is discovered using ARM_SMCCC_FEATURES mechanism performed
by the PSCI driver.

Clients are able to probe then use the FF-A bus by calling the DM class
searching APIs (e.g: uclass_first_device).

The Secure World is considered as one entity to communicate with
using the FF-A bus. FF-A communication is handled by one device and
one instance (the bus). This FF-A driver takes care of all the
interactions between Normal world and Secure World.

The driver exports its operations to be used by upper layers.

Exported operations:

- ffa_partition_info_get
- ffa_sync_send_receive
- ffa_rxtx_unmap

Generic FF-A methods are implemented in the Uclass (arm-ffa-uclass.c).
Arm specific methods are implemented in the Arm driver (arm-ffa.c).

For more details please refer to the driver documentation [2].

[1]: https://developer.arm.com/documentation/den0077/latest/
[2]: doc/arch/arm64.ffa.rst

Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Cc: Tom Rini <trini@konsulko.com>
Cc: Jens Wiklander <jens.wiklander@linaro.org>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
2023-08-08 10:22:03 -04:00
Abdellatif El Khlifi
b83dc8df64 lib: uuid: introduce testcase for uuid_str_to_le_bin
provide a test case

Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
2023-08-08 10:22:03 -04:00
Abdellatif El Khlifi
7048f26ccb lib: uuid: introduce uuid_str_to_le_bin function
convert UUID string to little endian binary data

Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Cc: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Cc: Jens Wiklander <jens.wiklander@linaro.org>
2023-08-08 10:22:03 -04:00
Abdellatif El Khlifi
d998735179 arm64: smccc: add support for SMCCCv1.2 x0-x17 registers
add support for x0-x17 registers used by the SMC calls

In SMCCC v1.2 [1] arguments are passed in registers x1-x17.
Results are returned in x0-x17.

This work is inspired from the following kernel commit:

arm64: smccc: Add support for SMCCCv1.2 extended input/output registers

[1]: https://documentation-service.arm.com/static/5f8edaeff86e16515cdbe4c6?token=

Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
2023-08-08 10:22:03 -04:00
Svyatoslav Ryhel
bdf9dead86 board: htc: endeavoru: add One X support
The HTC One X is a touchscreen-based, slate-sized smartphone
designed and manufactured by HTC that runs the Android operating
system. The One X features a 4.7" display, an Nvidia Tegra 3
quad-core chip, 1 GB of RAM and non-extendable 32 GB of internal
storage. UART-A is default debug port.

Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com>
Tested-by: Ion Agorria <ion@agorria.com>
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-06-30 15:20:37 +02:00
Svyatoslav Ryhel
623a8c812e board: lg: x3: add Optimus 4X HD and Optimus Vu support
LG X3 is a development board based on Nvidia Tegra 3 SoC
on base of which Optimus 4X HD and Optimus Vu were created.
Both smartphones feature a 4.7" and 5" panels respectively,
an Nvidia Tegra 3 quad-core chip, 1 GB of RAM and 16/32 GB
of internal storage. Optimux 4X HD additionally has a micro
SD slot.

Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # LG P880 T30
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-06-30 15:20:37 +02:00
Svyatoslav Ryhel
855ffdfa65 board: asus: grouper: add Google Nexus 7 (2012) support
Nexus 7 is a mini tablet computer co-developed by Google and Asus
that runs the Android operating system. The Nexus 7 features a 7"
display, an Nvidia Tegra 3 quad-core chip, 1 GB of RAM and 8/16 GB
of internal storage.

This patch brings support for all 3 known ASUS/Google devices:
- Nexus 7 (2012) E1565
- Nexus 7 (2012) PM269
- Nexus 7 (2012) 3G - tilapia

Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS Grouper E1565
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # ASUS Grouper E1565
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-06-30 15:20:37 +02:00
Svyatoslav Ryhel
15be9a7b3b board: asus: transformer: add ASUS Transformer T30 family support
The ASUS Transformer T30 family are 2-in-1 detachable tablets
and AiO developed by ASUS that run the Android operating system
(TF600T runs Windows RT and P1801-T runs Android and Windows).
The T30 Transformers feature a 10.1-inch display (apart P1801-T),
an Nvidia Tegra 3 quad-core chip, 1/2 GB of RAM, and 16/32 GB of
storage. Transformers board derives from Nvidia Cardhu development
board.

This patch brings support for 7 known Transformer devices:
- ASUS Transformer Prime TF201
- ASUS Transformer Pad TF300T/TF300TG/TF300TL
- ASUS VivoTab RT TF600T (Windows RT based)
- ASUS Transformer Infinity TF700T
- ASUS Portable AiO P1801-T

Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # all devices
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-06-30 15:20:37 +02:00
Svyatoslav Ryhel
d83721f1d4 ARM: tegra: add SoC UID calculation function
This is a small tool for calculation of SoC UID based on the same
Linux function. It can be further used for generation of device
unique data like mac address or exposing it as serial number.

Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS Grouper E1565
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-06-30 15:20:37 +02:00
Jonas Schwöbel
c8cd4db6f1 configs: tegra-common-post: make PXE and DHCP boot targets optional
Disabling the network related features in defconfig causes build to
fail so make them optional.

Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS Grouper E1565
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Signed-off-by: Jonas Schwöbel <jonasschwoebel@yahoo.de>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-06-30 15:20:37 +02:00
Svyatoslav Ryhel
12b3887088 configs: tegra-common-post: add GPIO keyboard as STDIN device
GPIO keyboard is used on many newly upstreamed devices.

Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS Grouper E1565
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-06-30 15:20:37 +02:00
Tomasz Maciej Nowak
da880bf7c1 ARM: dts: trimslice: sync SPI node with Linux dts
After "spi: spi_flash_probe_bus_cs() rely on DT for spi speed and mode"
series flash speed and mode wasn't passed to driver anymore, which
resulted in:

Loading Environment from SPIFlash... tegra20_sflash spi@7000c380: Invalid chip select 0:0 (err=-19)
*** Warning - spi_flash_probe_bus_cs() failed, using default environment

Fix it by syncing SPI node of affected device dts with Linux kernel dts.
The changed SPI bus frequency doesn't influence stability of read/write
operations.

Ref: https://patchwork.ozlabs.org/project/uboot/cover/20220518064648.1843664-1-patrice.chotard@foss.st.com
Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
2023-06-23 13:43:48 +02:00
Thierry Reding
e55448c780 ARM: tegra: Enable poweroff command on Jetson TX2
This command is useful to power off the system from within U-Boot.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom <twarren@nvidia.com>
2023-06-23 13:43:48 +02:00
Thierry Reding
9c2f454647 ARM: tegra: Enable poweroff command on Jetson TX1 and Jetson Nano
This command is useful to power off the system from within U-Boot.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom <twarren@nvidia.com>
2023-06-23 13:43:48 +02:00
882 changed files with 16808 additions and 4882 deletions

View File

@@ -179,25 +179,6 @@ stages:
# seems to hang forever with pre-configured "container" environment
docker run -v $PWD:$(work_dir) $(ci_runner_image) /bin/bash $(work_dir)/build.sh
- job: nokia_rx51_test
displayName: 'Run tests for Nokia RX-51 (aka N900)'
pool:
vmImage: $(ubuntu_vm)
container:
image: $(ci_runner_image)
options: $(container_option)
steps:
- script: |
mkdir nokia_rx51_tmp
ln -s /opt/nokia/u-boot-gen-combined nokia_rx51_tmp/
ln -s /opt/nokia/qemu-n900.tar.gz nokia_rx51_tmp/
ln -s /opt/nokia/kernel_2.6.28-20103103+0m5_armel.deb nokia_rx51_tmp/
ln -s /opt/nokia/libc6_2.5.1-1eglibc27+0m5_armel.deb nokia_rx51_tmp/
ln -s /opt/nokia/busybox_1.10.2.legal-1osso30+0m5_armel.deb nokia_rx51_tmp/
ln -s /opt/nokia/qemu-system-arm nokia_rx51_tmp/
export PATH=/opt/gcc-13.1.0-nolibc/arm-linux-gnueabi/bin:$PATH
test/nokia_rx51_test.sh
- job: pylint
displayName: Check for any pylint regressions
pool:
@@ -426,7 +407,7 @@ stages:
cp images/spi-nor.img ${UBOOT_TRAVIS_BUILD_DIR}/;
fi
if [[ "${TEST_PY_BD}" == "coreboot" ]]; then
wget -O - "https://drive.google.com/uc?id=1x6nrtWIyIRPLS2cQBwYTnT2TbOI8UjmM&export=download" |xz -dc >${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom;
wget -O - "https://drive.google.com/uc?id=1uJ2VkUQ8czWFZmhJQ90Tp8V_zrJ6BrBH&export=download" |xz -dc >${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom;
wget -O - "https://drive.google.com/uc?id=149Cz-5SZXHNKpi9xg6R_5XITWohu348y&export=download" >cbfstool;
chmod a+x cbfstool;
./cbfstool ${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom add-flat-binary -f ${UBOOT_TRAVIS_BUILD_DIR}/u-boot.bin -n fallback/payload -c LZMA -l 0x1110000 -e 0x1110000;
@@ -468,6 +449,7 @@ stages:
- stage: world_build
jobs:
- job: build_the_world
timeoutInMinutes: 0 # Use the maximum allowed
displayName: 'Build the World'
pool:
vmImage: $(ubuntu_vm)

View File

@@ -69,7 +69,7 @@ stages:
fi
- if [[ "${TEST_PY_BD}" == "coreboot" ]]; then
wget -O -
"https://drive.google.com/uc?id=1x6nrtWIyIRPLS2cQBwYTnT2TbOI8UjmM&export=download" |
"https://drive.google.com/uc?id=1uJ2VkUQ8czWFZmhJQ90Tp8V_zrJ6BrBH&export=download" |
xz -dc >${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom;
wget -O -
"https://drive.google.com/uc?id=149Cz-5SZXHNKpi9xg6R_5XITWohu348y&export=download" >
@@ -225,19 +225,6 @@ Run binman, buildman, dtoc, Kconfig and patman testsuites:
./tools/patman/patman test;
make testconfig
Run tests for Nokia RX-51 (aka N900):
stage: testsuites
script:
- mkdir nokia_rx51_tmp;
ln -s /opt/nokia/u-boot-gen-combined nokia_rx51_tmp/;
ln -s /opt/nokia/qemu-n900.tar.gz nokia_rx51_tmp/;
ln -s /opt/nokia/kernel_2.6.28-20103103+0m5_armel.deb nokia_rx51_tmp/;
ln -s /opt/nokia/libc6_2.5.1-1eglibc27+0m5_armel.deb nokia_rx51_tmp/;
ln -s /opt/nokia/busybox_1.10.2.legal-1osso30+0m5_armel.deb nokia_rx51_tmp/;
ln -s /opt/nokia/qemu-system-arm nokia_rx51_tmp/;
export PATH=/opt/gcc-13.1.0-nolibc/arm-linux-gnueabi/bin:$PATH;
test/nokia_rx51_test.sh
# Check for any pylint regressions
Run pylint:
stage: testsuites

11
Kconfig
View File

@@ -372,6 +372,17 @@ if EXPERT
When disabling this, please check if malloc calls, maybe
should be replaced by calloc - if one expects zeroed memory.
config SPL_SYS_MALLOC_CLEAR_ON_INIT
bool "Init with zeros the memory reserved for malloc (slow) in SPL"
depends on SPL
default SYS_MALLOC_CLEAR_ON_INIT
help
Same as SYS_MALLOC_CLEAR_ON_INIT, but for SPL. It's possible to
Enable it without SYS_MALLOC_CLEAR_ON_INIT. It's useful for boards
that must have particular memory regions zero'ed before first use.
If SYS_SPL_MALLOC_START is configured to be in such region, this
option should be enabled.
config SYS_MALLOC_DEFAULT_TO_INIT
bool "Default malloc to init while reserving the memory for it"
help

View File

@@ -132,6 +132,7 @@ M: Tom Rini <trini@konsulko.com>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-arm.git
F: arch/arm/
F: arch/arm/dts/Makefile
F: cmd/arm/
ARM ALTERA SOCFPGA
@@ -266,6 +267,19 @@ F: drivers/net/cortina_ni.h
F: drivers/net/phy/ca_phy.c
F: configs/cortina_presidio-asic-pnand_defconfig
ARM FF-A
M: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
S: Maintained
F: arch/sandbox/include/asm/sandbox_arm_ffa.h
F: arch/sandbox/include/asm/sandbox_arm_ffa_priv.h
F: cmd/armffa.c
F: doc/arch/arm64.ffa.rst
F: doc/usage/cmd/armffa.rst
F: drivers/firmware/arm-ffa/
F: include/arm_ffa.h
F: test/cmd/armffa.c
F: test/dm/ffa.c
ARM FREESCALE IMX
M: Stefano Babic <sbabic@denx.de>
M: Fabio Estevam <festevam@gmail.com>
@@ -351,7 +365,6 @@ F: drivers/watchdog/orion_wdt.c
F: include/configs/mv-common.h
ARM MARVELL PCIE CONTROLLER DRIVERS
M: Pali Rohár <pali@kernel.org>
M: Stefan Roese <sr@denx.de>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-marvell.git
@@ -620,6 +633,7 @@ F: include/dt-bindings/clock/stm32mp*
F: include/dt-bindings/pinctrl/stm32-pinfunc.h
F: include/dt-bindings/reset/stm32mp*
F: include/stm32_rcc.h
F: tools/logos/st.bmp
F: tools/stm32image.c
N: stm
N: stm32
@@ -709,7 +723,10 @@ F: drivers/usb/musb-new/ux500.c
F: drivers/video/mcde_simple.c
ARM UNIPHIER
S: Orphan (Since 2020-09)
M: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
R: Dai Okamura <okamura.dai@socionext.com>
S: Maintained
F: arch/arm/dts/uniphier-*
F: arch/arm/mach-uniphier/
F: configs/uniphier_*_defconfig
N: uniphier
@@ -1000,7 +1017,6 @@ F: tools/mkeficapsule.c
ENVIRONMENT
M: Joe Hershberger <joe.hershberger@ni.com>
R: Wolfgang Denk <wd@denx.de>
S: Maintained
F: env/
F: include/env*
@@ -1010,7 +1026,6 @@ F: tools/mkenvimage.c
ENVIRONMENT AS TEXT
M: Simon Glass <sjg@chromium.org>
R: Wolfgang Denk <wd@denx.de>
S: Maintained
F: doc/usage/environment.rst
F: scripts/env2string.awk
@@ -1328,8 +1343,7 @@ F: drivers/power/
F: include/power/
POWERPC
M: Wolfgang Denk <wd@denx.de>
S: Maintained
S: Orphan (Since 2022-10-21)
F: arch/powerpc/
POWERPC MPC8XX
@@ -1584,7 +1598,8 @@ T: git https://source.denx.de/u-boot/custodians/u-boot-ubi.git
F: drivers/mtd/ubi/
UFS
M: Faiz Abbas <faiz_abbas@ti.com>
M: Bhupesh Sharma <bhupesh.linux@gmail.com>
M: Neha Malcom Francis <n-francis@ti.com>
S: Maintained
F: drivers/ufs/
@@ -1605,6 +1620,11 @@ T: git https://source.denx.de/u-boot/custodians/u-boot-usb.git topic-xhci
F: drivers/usb/host/xhci*
F: include/usb/xhci.h
UUID testing
M: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
S: Maintained
F: test/lib/uuid.c
VIDEO
M: Anatolij Gustschin <agust@denx.de>
S: Maintained

View File

@@ -3,7 +3,7 @@
VERSION = 2023
PATCHLEVEL = 10
SUBLEVEL =
EXTRAVERSION = -rc2
EXTRAVERSION =
NAME =
# *DOCUMENTATION*
@@ -1328,11 +1328,6 @@ u-boot.ldr: u-boot
# Use 'make BINMAN_VERBOSE=3' to set vebosity level
default_dt := $(if $(DEVICE_TREE),$(DEVICE_TREE),$(CONFIG_DEFAULT_DEVICE_TREE))
# Temporary workaround for Venice boards
ifneq ($(CONFIG_TARGET_IMX8MM_VENICE),$(CONFIG_TARGET_IMX8MN_VENICE),$(CONFIG_TARGET_IMX8MP_VENICE),)
ignore_dups := --ignore-dup-phandles
endif
quiet_cmd_binman = BINMAN $@
cmd_binman = $(srctree)/tools/binman/binman $(if $(BINMAN_DEBUG),-D) \
$(foreach f,$(BINMAN_TOOLPATHS),--toolpath $(f)) \
@@ -1354,7 +1349,6 @@ cmd_binman = $(srctree)/tools/binman/binman $(if $(BINMAN_DEBUG),-D) \
-a spl-dtb=$(CONFIG_SPL_OF_REAL) \
-a tpl-dtb=$(CONFIG_TPL_OF_REAL) \
-a pre-load-key-path=${PRE_LOAD_KEY_PATH} \
$(ignore_dups) \
$(BINMAN_$(@F))
OBJCOPYFLAGS_u-boot.ldr.hex := -I binary -O ihex

View File

@@ -2101,7 +2101,7 @@ config SERIAL_TAG
config STATIC_MACH_TYPE
bool "Statically define the Machine ID number"
default y if TARGET_DS109 || TARGET_NOKIA_RX51 || TARGET_DS414 || DEFAULT_DEVICE_TREE = "sun7i-a20-icnova-swac"
default y if TARGET_DS109 || TARGET_DS414 || DEFAULT_DEVICE_TREE = "sun7i-a20-icnova-swac"
help
When booting via ATAGs, enable this option if we know the correct
machine ID number to use at compile time. Some systems will be
@@ -2111,7 +2111,6 @@ config MACH_TYPE
int "Machine ID number"
depends on STATIC_MACH_TYPE
default 527 if TARGET_DS109
default 1955 if TARGET_NOKIA_RX51
default 3036 if TARGET_DS414
default 4283 if DEFAULT_DEVICE_TREE = "sun7i-a20-icnova-swac"
help

View File

@@ -575,11 +575,6 @@ int get_core_volt_from_fuse(void)
return vdd;
}
__weak int board_switch_core_volt(u32 vdd)
{
return 0;
}
static int setup_core_volt(u32 vdd)
{
return board_setup_core_volt(vdd);

View File

@@ -1,7 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2015, Linaro Limited
*/
* Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
*
* Authors:
* Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
*/
#include <linux/linkage.h>
#include <linux/arm-smccc.h>
#include <generated/asm-offsets.h>
@@ -45,3 +49,54 @@ ENDPROC(__arm_smccc_smc)
ENTRY(__arm_smccc_hvc)
SMCCC hvc
ENDPROC(__arm_smccc_hvc)
#ifdef CONFIG_ARM64
.macro SMCCC_1_2 instr
/* Save `res` and free a GPR that won't be clobbered */
stp x1, x19, [sp, #-16]!
/* Ensure `args` won't be clobbered while loading regs in next step */
mov x19, x0
/* Load the registers x0 - x17 from the struct arm_smccc_1_2_regs */
ldp x0, x1, [x19, #ARM_SMCCC_1_2_REGS_X0_OFFS]
ldp x2, x3, [x19, #ARM_SMCCC_1_2_REGS_X2_OFFS]
ldp x4, x5, [x19, #ARM_SMCCC_1_2_REGS_X4_OFFS]
ldp x6, x7, [x19, #ARM_SMCCC_1_2_REGS_X6_OFFS]
ldp x8, x9, [x19, #ARM_SMCCC_1_2_REGS_X8_OFFS]
ldp x10, x11, [x19, #ARM_SMCCC_1_2_REGS_X10_OFFS]
ldp x12, x13, [x19, #ARM_SMCCC_1_2_REGS_X12_OFFS]
ldp x14, x15, [x19, #ARM_SMCCC_1_2_REGS_X14_OFFS]
ldp x16, x17, [x19, #ARM_SMCCC_1_2_REGS_X16_OFFS]
\instr #0
/* Load the `res` from the stack */
ldr x19, [sp]
/* Store the registers x0 - x17 into the result structure */
stp x0, x1, [x19, #ARM_SMCCC_1_2_REGS_X0_OFFS]
stp x2, x3, [x19, #ARM_SMCCC_1_2_REGS_X2_OFFS]
stp x4, x5, [x19, #ARM_SMCCC_1_2_REGS_X4_OFFS]
stp x6, x7, [x19, #ARM_SMCCC_1_2_REGS_X6_OFFS]
stp x8, x9, [x19, #ARM_SMCCC_1_2_REGS_X8_OFFS]
stp x10, x11, [x19, #ARM_SMCCC_1_2_REGS_X10_OFFS]
stp x12, x13, [x19, #ARM_SMCCC_1_2_REGS_X12_OFFS]
stp x14, x15, [x19, #ARM_SMCCC_1_2_REGS_X14_OFFS]
stp x16, x17, [x19, #ARM_SMCCC_1_2_REGS_X16_OFFS]
/* Restore original x19 */
ldp xzr, x19, [sp], #16
ret
.endm
/*
* void arm_smccc_1_2_smc(const struct arm_smccc_1_2_regs *args,
* struct arm_smccc_1_2_regs *res);
*/
ENTRY(arm_smccc_1_2_smc)
SMCCC_1_2 smc
ENDPROC(arm_smccc_1_2_smc)
#endif

View File

@@ -178,6 +178,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \
rk3566-soquartz-cm4.dtb \
rk3566-soquartz-model-a.dtb \
rk3568-evb.dtb \
rk3568-lubancat-2.dtb \
rk3568-nanopi-r5c.dtb \
rk3568-nanopi-r5s.dtb \
rk3568-odroid-m1.dtb \
@@ -254,9 +255,22 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
tegra20-ventana.dtb \
tegra20-colibri.dtb \
tegra30-apalis.dtb \
tegra30-asus-nexus7-grouper-PM269.dtb \
tegra30-asus-nexus7-grouper-E1565.dtb \
tegra30-asus-nexus7-tilapia-E1565.dtb \
tegra30-asus-p1801-t.dtb \
tegra30-asus-tf201.dtb \
tegra30-asus-tf300t.dtb \
tegra30-asus-tf300tg.dtb \
tegra30-asus-tf300tl.dtb \
tegra30-asus-tf600t.dtb \
tegra30-asus-tf700t.dtb \
tegra30-beaver.dtb \
tegra30-cardhu.dtb \
tegra30-colibri.dtb \
tegra30-htc-endeavoru.dtb \
tegra30-lg-p880.dtb \
tegra30-lg-p895.dtb \
tegra30-tec-ng.dtb \
tegra114-dalmore.dtb \
tegra124-apalis.dtb \

View File

@@ -3,6 +3,8 @@
* Copyright 2020-2022 Toradex
*/
#include "imx7s-u-boot.dtsi"
&{/aliases} {
/* SDHCI instance order: eMMC, SD/MMC */
mmc0 = &usdhc3;

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@@ -1,3 +1,5 @@
#include "imx7s-u-boot.dtsi"
/{
aliases {
mmc0 = &usdhc3;

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@@ -3,6 +3,8 @@
* Copyright 2018 NXP
*/
#include "imx7s-u-boot.dtsi"
&qspi {
flash0: mx25l51245g@0 {
compatible = "jedec,spi-nor";

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@@ -1,3 +1,5 @@
#include "imx7s-u-boot.dtsi"
&fec2 {
status = "disable";
};

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@@ -0,0 +1,3 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
#include "imx7s-u-boot.dtsi"

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@@ -0,0 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
&crypto {
sec_jr0: jr@1000 {
status = "disabled";
};
};

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@@ -41,9 +41,11 @@
};
};
/* This cannot work since it refers to a template node
&binman_configuration {
loadables = "atf", "fip";
};
*/
&fec1 {
phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;

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@@ -140,7 +140,7 @@
configurations {
default = "@config-DEFAULT-SEQ";
binman_configuration: @config-SEQ {
@config-SEQ {
description = "NAME";
fdt = "fdt-SEQ";
firmware = "uboot";

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@@ -204,7 +204,7 @@
configurations {
default = "@config-DEFAULT-SEQ";
binman_configuration: @config-SEQ {
@config-SEQ {
description = "NAME";
fdt = "fdt-SEQ";
firmware = "uboot";

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@@ -162,6 +162,8 @@
};
};
/* This cannot work since it refers to a template node
&binman_configuration {
loadables = "atf", "fip";
};
*/

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@@ -146,7 +146,7 @@
type = "flat_dt";
compression = "none";
uboot_fdt_blob: blob-ext {
blob-ext {
filename = "u-boot.dtb";
};
};
@@ -155,7 +155,7 @@
configurations {
default = "@config-DEFAULT-SEQ";
binman_configuration: @config-SEQ {
@config-SEQ {
description = "NAME";
fdt = "fdt-SEQ";
firmware = "uboot";

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@@ -112,7 +112,7 @@
configurations {
default = "@config-DEFAULT-SEQ";
binman_configuration: @config-SEQ {
@config-SEQ {
description = "NAME";
fdt = "fdt-SEQ";
firmware = "uboot";

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@@ -41,7 +41,7 @@
os = "arm-trusted-firmware";
load = <CONFIG_K3_ATF_LOAD_ADDR>;
entry = <CONFIG_K3_ATF_LOAD_ADDR>;
atf: atf-bl31 {
atf-bl31 {
};
};
@@ -53,7 +53,7 @@
os = "tee";
load = <0x9e800000>;
entry = <0x9e800000>;
tee: tee-os {
tee-os {
};
};
@@ -78,7 +78,7 @@
compression = "none";
load = <CONFIG_SPL_TEXT_BASE>;
entry = <CONFIG_SPL_TEXT_BASE>;
u_boot_spl_nodtb: blob-ext {
blob-ext {
filename = "spl/u-boot-spl-nodtb.bin";
};
};
@@ -88,7 +88,7 @@
type = "flat_dt";
arch = "arm";
compression = "none";
spl_am65x_evm_dtb: blob-ext {
blob-ext {
filename = "spl/dts/k3-am65-iot2050-spl.dtb";
};
};

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@@ -76,12 +76,12 @@
&eth {
status = "okay";
mediatek,gmac-id = <0>;
phy-mode = "sgmii";
phy-mode = "2500base-x";
mediatek,switch = "mt7531";
reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
fixed-link {
speed = <1000>;
speed = <2500>;
full-duplex;
};
};

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@@ -12,6 +12,31 @@
&uart0 {
bootph-all;
clock-frequency = <24000000>;
status = "okay";
};
&pinctrl {
bootph-some-ram;
uart0 {
bootph-some-ram;
};
rtc {
bootph-some-ram;
};
};
&uart0_xfer {
bootph-some-ram;
};
&uart0_cts {
bootph-some-ram;
};
&uart0_rts {
bootph-some-ram;
};
&rtc_32k {
bootph-some-ram;
};

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@@ -54,7 +54,7 @@
};
&spi0 {
spi_flash: spiflash@0 {
spi_flash: flash@0 {
bootph-all;
};
};

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@@ -345,7 +345,7 @@
&spi0 {
status = "okay";
spiflash@0 {
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;

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@@ -26,6 +26,12 @@
0x0 0xff720000 0x0 0x1000
0x0 0xff798000 0x0 0x1000>;
};
rng: rng@ff060000 {
compatible = "rockchip,cryptov1-rng";
reg = <0x0 0xff060000 0x0 0x4000>;
status = "okay";
};
};
&cru {

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@@ -0,0 +1,27 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2023 Rockchip Electronics Co., Ltd
* (C) Copyright 2023 Andy Yan <andyshrk@163.com>
*/
#include "rk356x-u-boot.dtsi"
/ {
chosen {
stdout-path = &uart2;
};
};
&sdhci {
cap-mmc-highspeed;
mmc-ddr-1_8v;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
};
&uart2 {
bootph-all;
clock-frequency = <24000000>;
status = "okay";
};

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@@ -0,0 +1,733 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
* Copyright (c) 2022 EmbedFire <embedfire@embedfire.com>
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/soc/rockchip,vop2.h>
#include "rk3568.dtsi"
/ {
model = "EmbedFire LubanCat 2";
compatible = "embedfire,lubancat-2", "rockchip,rk3568";
aliases {
ethernet0 = &gmac0;
ethernet1 = &gmac1;
mmc0 = &sdmmc0;
mmc1 = &sdhci;
};
chosen: chosen {
stdout-path = "serial2:1500000n8";
};
leds {
compatible = "gpio-leds";
user_led: user-led {
label = "user_led";
linux,default-trigger = "heartbeat";
default-state = "on";
gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&user_led_pin>;
};
};
hdmi-con {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con_in: endpoint {
remote-endpoint = <&hdmi_out_con>;
};
};
};
dc_5v: dc-5v-regulator {
compatible = "regulator-fixed";
regulator-name = "dc_5v";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
vcc3v3_sys: vcc3v3-sys-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc5v0_sys>;
};
vcc5v0_sys: vcc5v0-sys-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&dc_5v>;
};
vcc3v3_m2_pcie: vcc3v3-m2-pcie-regulator {
compatible = "regulator-fixed";
regulator-name = "m2_pcie_3v3";
enable-active-high;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&vcc3v3_m2_pcie_en>;
pinctrl-names = "default";
startup-delay-us = <200000>;
vin-supply = <&vcc5v0_sys>;
};
vcc3v3_mini_pcie: vcc3v3-mini-pcie-regulator {
compatible = "regulator-fixed";
regulator-name = "minipcie_3v3";
enable-active-high;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&vcc3v3_mini_pcie_en>;
pinctrl-names = "default";
startup-delay-us = <5000>;
vin-supply = <&vcc5v0_sys>;
};
vcc5v0_usb20_host: vcc5v0-usb20-host-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_usb20_host";
enable-active-high;
gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&vcc5v0_usb20_host_en>;
pinctrl-names = "default";
};
vcc5v0_usb30_host: vcc5v0-usb30-host-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_usb30_host";
enable-active-high;
gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&vcc5v0_usb30_host_en>;
pinctrl-names = "default";
};
vcc5v0_otg_vbus: vcc5v0-otg-vbus-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_otg_vbus";
enable-active-high;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&vcc5v0_otg_vbus_en>;
pinctrl-names = "default";
};
};
&combphy0 {
status = "okay";
};
&combphy1 {
status = "okay";
};
&combphy2 {
status = "okay";
};
&cpu0 {
cpu-supply = <&vdd_cpu>;
};
&cpu1 {
cpu-supply = <&vdd_cpu>;
};
&cpu2 {
cpu-supply = <&vdd_cpu>;
};
&cpu3 {
cpu-supply = <&vdd_cpu>;
};
&gpu {
mali-supply = <&vdd_gpu>;
status = "okay";
};
&hdmi {
avdd-0v9-supply = <&vdda0v9_image>;
avdd-1v8-supply = <&vcca1v8_image>;
status = "okay";
};
&hdmi_in {
hdmi_in_vp0: endpoint {
remote-endpoint = <&vp0_out_hdmi>;
};
};
&hdmi_out {
hdmi_out_con: endpoint {
remote-endpoint = <&hdmi_con_in>;
};
};
&hdmi_sound {
status = "okay";
};
&i2c0 {
status = "okay";
vdd_cpu: regulator@1c {
compatible = "tcs,tcs4525";
reg = <0x1c>;
fcs,suspend-voltage-selector = <1>;
regulator-name = "vdd_cpu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1150000>;
regulator-ramp-delay = <2300>;
vin-supply = <&vcc5v0_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
rk809: pmic@20 {
compatible = "rockchip,rk809";
reg = <0x20>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
#clock-cells = <1>;
clock-names = "mclk";
clocks = <&cru I2S1_MCLKOUT_TX>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_int>;
rockchip,system-power-controller;
#sound-dai-cells = <0>;
vcc1-supply = <&vcc3v3_sys>;
vcc2-supply = <&vcc3v3_sys>;
vcc3-supply = <&vcc3v3_sys>;
vcc4-supply = <&vcc3v3_sys>;
vcc5-supply = <&vcc3v3_sys>;
vcc6-supply = <&vcc3v3_sys>;
vcc7-supply = <&vcc3v3_sys>;
vcc8-supply = <&vcc3v3_sys>;
vcc9-supply = <&vcc3v3_sys>;
wakeup-source;
regulators {
vdd_logic: DCDC_REG1 {
regulator-name = "vdd_logic";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-init-microvolt = <900000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_gpu: DCDC_REG2 {
regulator-name = "vdd_gpu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-init-microvolt = <900000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_ddr: DCDC_REG3 {
regulator-name = "vcc_ddr";
regulator-always-on;
regulator-boot-on;
regulator-initial-mode = <0x2>;
regulator-state-mem {
regulator-on-in-suspend;
};
};
vdd_npu: DCDC_REG4 {
regulator-name = "vdd_npu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-init-microvolt = <900000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_1v8: DCDC_REG5 {
regulator-name = "vcc_1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdda0v9_image: LDO_REG1 {
regulator-name = "vdda0v9_image";
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdda_0v9: LDO_REG2 {
regulator-name = "vdda_0v9";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdda0v9_pmu: LDO_REG3 {
regulator-name = "vdda0v9_pmu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <900000>;
};
};
vccio_acodec: LDO_REG4 {
regulator-name = "vccio_acodec";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vccio_sd: LDO_REG5 {
regulator-name = "vccio_sd";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v3_pmu: LDO_REG6 {
regulator-name = "vcc3v3_pmu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcca_1v8: LDO_REG7 {
regulator-name = "vcca_1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcca1v8_pmu: LDO_REG8 {
regulator-name = "vcca1v8_pmu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcca1v8_image: LDO_REG9 {
regulator-name = "vcca1v8_image";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_3v3: SWITCH_REG1 {
regulator-name = "vcc_3v3";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v3_sd: SWITCH_REG2 {
regulator-name = "vcc3v3_sd";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
};
};
&i2s1_8ch {
rockchip,trcm-sync-tx-only;
status = "okay";
};
&gmac0 {
phy-mode = "rgmii";
clock_in_out = "output";
snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
/* Reset time is 20ms, 100ms for rtl8211f */
snps,reset-delays-us = <0 20000 100000>;
assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
pinctrl-names = "default";
pinctrl-0 = <&gmac0_miim
&gmac0_tx_bus2
&gmac0_rx_bus2
&gmac0_rgmii_clk
&gmac0_rgmii_bus>;
tx_delay = <0x22>;
rx_delay = <0x0e>;
phy-handle = <&rgmii_phy0>;
status = "okay";
};
&mdio0 {
rgmii_phy0: phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x0>;
};
};
&gmac1 {
phy-mode = "rgmii";
clock_in_out = "output";
snps,reset-gpio = <&gpio3 RK_PA2 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
/* Reset time is 20ms, 100ms for rtl8211f */
snps,reset-delays-us = <0 20000 100000>;
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
pinctrl-names = "default";
pinctrl-0 = <&gmac1m1_miim
&gmac1m1_tx_bus2
&gmac1m1_rx_bus2
&gmac1m1_rgmii_clk
&gmac1m1_rgmii_bus>;
tx_delay = <0x21>;
rx_delay = <0x0e>;
phy-handle = <&rgmii_phy1>;
status = "okay";
};
&mdio1 {
rgmii_phy1: phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x0>;
};
};
&gic {
mbi-ranges = <94 31>, <229 31>, <289 31>;
};
&pcie30phy {
status = "okay";
};
&pcie3x2 {
reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_m2_pcie>;
status = "okay";
};
&pcie2x1 {
reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
disable-gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_mini_pcie>;
status = "okay";
};
&pmu_io_domains {
pmuio2-supply = <&vcc3v3_pmu>;
vccio1-supply = <&vccio_acodec>;
vccio3-supply = <&vccio_sd>;
vccio4-supply = <&vcc_1v8>;
vccio5-supply = <&vcc_3v3>;
vccio6-supply = <&vcc_1v8>;
vccio7-supply = <&vcc_3v3>;
status = "okay";
};
&pwm8 {
status = "okay";
};
&pwm9 {
status = "disabled";
};
&pwm10 {
status = "disabled";
};
&pwm14 {
status = "disabled";
};
&spi3 {
pinctrl-0 = <&spi3m1_pins>;
status = "disabled";
};
&uart2 {
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&uart3m1_xfer>;
status = "disabled";
};
&saradc {
vref-supply = <&vcca_1v8>;
status = "okay";
};
&tsadc {
rockchip,hw-tshut-mode = <1>;
rockchip,hw-tshut-polarity = <0>;
status = "okay";
};
&sdhci {
assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>, <&cru CCLK_EMMC>;
assigned-clock-rates = <200000000>, <24000000>, <200000000>;
bus-width = <8>;
max-frequency = <200000000>;
mmc-hs200-1_8v;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>;
supports-emmc;
status = "okay";
};
&sdmmc0 {
max-frequency = <150000000>;
no-sdio;
no-mmc;
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
disable-wp;
sd-uhs-sdr104;
vmmc-supply = <&vcc3v3_sd>;
vqmmc-supply = <&vccio_sd>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
status = "okay";
};
/* USB OTG/USB Host_1 USB 2.0 Comb */
&usb2phy0 {
status = "okay";
};
&usb2phy0_host {
phy-supply = <&vcc5v0_usb30_host>;
status = "okay";
};
&usb2phy0_otg {
phy-supply = <&vcc5v0_otg_vbus>;
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
/* USB Host_2/USB Host_3 USB 2.0 Comb */
&usb2phy1 {
status = "okay";
};
&usb2phy1_host {
status = "okay";
};
&usb2phy1_otg {
phy-supply = <&vcc5v0_usb20_host>;
status = "okay";
};
&usb_host1_ehci {
status = "okay";
};
&usb_host1_ohci {
status = "okay";
};
/* MULTI_PHY0 For SATA0, USB3.0 OTG Only USB2.0 */
&usb_host0_xhci {
phys = <&usb2phy0_otg>;
phy-names = "usb2-phy";
extcon = <&usb2phy0>;
maximum-speed = "high-speed";
dr_mode = "host";
status = "okay";
};
&sata0 {
status = "okay";
};
/* USB3.0 Host */
&usb_host1_xhci {
status = "okay";
};
&vop {
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
status = "okay";
};
&vop_mmu {
status = "okay";
};
&vp0 {
vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
reg = <ROCKCHIP_VOP2_EP_HDMI0>;
remote-endpoint = <&hdmi_in_vp0>;
};
};
&pinctrl {
leds {
user_led_pin: user-status-led-pin {
rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
usb {
vcc5v0_usb20_host_en: vcc5v0-usb20-host-en {
rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
};
vcc5v0_usb30_host_en: vcc5v0-usb30-host-en {
rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
};
vcc5v0_otg_vbus_en: vcc5v0-otg-vbus-en {
rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pcie {
vcc3v3_m2_pcie_en: vcc3v3-m2-pcie-en {
rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
};
vcc3v3_mini_pcie_en: vcc3v3-mini-pcie-en {
rockchip,pins = <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pmic {
pmic_int: pmic-int {
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};

View File

@@ -126,12 +126,11 @@
&sdhci {
bootph-pre-ram;
status = "okay";
max-frequency = <200000000>;
};
&sdmmc0 {
bootph-pre-ram;
status = "okay";
};
#ifdef CONFIG_ROCKCHIP_SPI_IMAGE

View File

@@ -328,6 +328,8 @@
status = "okay";
phy0: ethernet-phy@0 {
compatible = "ethernet-phy-id0022.1622",
"ethernet-phy-ieee802.3-c22";
rxc-skew-ps = <1500>;
reg = <0>;
interrupt-parent = <&gpio2>;

View File

@@ -169,7 +169,7 @@
ltdc_pins: ltdc@0 {
pins {
pinmux = <STM32_PINMUX('E', 4, AF14)>, /* B0 */
<STM32_PINMUX('G',12, AF14)>, /* B4 */
<STM32_PINMUX('G',12, AF9)>, /* B4 */
<STM32_PINMUX('I', 9, AF14)>, /* VSYNC */
<STM32_PINMUX('I',10, AF14)>, /* HSYNC */
<STM32_PINMUX('I',14, AF14)>, /* CLK */

View File

@@ -258,4 +258,133 @@
bias-disable;
};
};
uart4_idle_pins_a: uart4-idle-0 {
pins1 {
pinmux = <STM32_PINMUX('D', 6, ANALOG)>; /* UART4_TX */
};
pins2 {
pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */
bias-disable;
};
};
uart4_sleep_pins_a: uart4-sleep-0 {
pins {
pinmux = <STM32_PINMUX('D', 6, ANALOG)>, /* UART4_TX */
<STM32_PINMUX('D', 8, ANALOG)>; /* UART4_RX */
};
};
uart8_pins_a: uart8-0 {
pins1 {
pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('F', 9, AF8)>; /* UART8_RX */
bias-pull-up;
};
};
uart8_idle_pins_a: uart8-idle-0 {
pins1 {
pinmux = <STM32_PINMUX('E', 1, ANALOG)>; /* UART8_TX */
};
pins2 {
pinmux = <STM32_PINMUX('F', 9, AF8)>; /* UART8_RX */
bias-pull-up;
};
};
uart8_sleep_pins_a: uart8-sleep-0 {
pins {
pinmux = <STM32_PINMUX('E', 1, ANALOG)>, /* UART8_TX */
<STM32_PINMUX('F', 9, ANALOG)>; /* UART8_RX */
};
};
usart1_pins_a: usart1-0 {
pins1 {
pinmux = <STM32_PINMUX('C', 0, AF7)>, /* USART1_TX */
<STM32_PINMUX('C', 2, AF7)>; /* USART1_RTS */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('B', 0, AF4)>, /* USART1_RX */
<STM32_PINMUX('A', 7, AF7)>; /* USART1_CTS_NSS */
bias-pull-up;
};
};
usart1_idle_pins_a: usart1-idle-0 {
pins1 {
pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* USART1_TX */
<STM32_PINMUX('A', 7, ANALOG)>; /* USART1_CTS_NSS */
};
pins2 {
pinmux = <STM32_PINMUX('C', 2, AF7)>; /* USART1_RTS */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins3 {
pinmux = <STM32_PINMUX('B', 0, AF4)>; /* USART1_RX */
bias-pull-up;
};
};
usart1_sleep_pins_a: usart1-sleep-0 {
pins {
pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* USART1_TX */
<STM32_PINMUX('C', 2, ANALOG)>, /* USART1_RTS */
<STM32_PINMUX('A', 7, ANALOG)>, /* USART1_CTS_NSS */
<STM32_PINMUX('B', 0, ANALOG)>; /* USART1_RX */
};
};
usart2_pins_a: usart2-0 {
pins1 {
pinmux = <STM32_PINMUX('H', 12, AF1)>, /* USART2_TX */
<STM32_PINMUX('D', 4, AF3)>; /* USART2_RTS */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('D', 15, AF1)>, /* USART2_RX */
<STM32_PINMUX('E', 11, AF2)>; /* USART2_CTS_NSS */
bias-disable;
};
};
usart2_idle_pins_a: usart2-idle-0 {
pins1 {
pinmux = <STM32_PINMUX('H', 12, ANALOG)>, /* USART2_TX */
<STM32_PINMUX('E', 11, ANALOG)>; /* USART2_CTS_NSS */
};
pins2 {
pinmux = <STM32_PINMUX('D', 4, AF3)>; /* USART2_RTS */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins3 {
pinmux = <STM32_PINMUX('D', 15, AF1)>; /* USART2_RX */
bias-disable;
};
};
usart2_sleep_pins_a: usart2-sleep-0 {
pins {
pinmux = <STM32_PINMUX('H', 12, ANALOG)>, /* USART2_TX */
<STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */
<STM32_PINMUX('D', 15, ANALOG)>, /* USART2_RX */
<STM32_PINMUX('E', 11, ANALOG)>; /* USART2_CTS_NSS */
};
};
};

View File

@@ -108,14 +108,6 @@
bootph-all;
};
&scmi_shm {
bootph-all;
};
&scmi_sram {
bootph-all;
};
&syscfg {
bootph-all;
};

View File

@@ -40,7 +40,6 @@
#address-cells = <1>;
#size-cells = <0>;
linaro,optee-channel-id = <0>;
shmem = <&scmi_shm>;
scmi_clk: protocol@14 {
reg = <0x14>;
@@ -106,19 +105,6 @@
interrupt-parent = <&intc>;
ranges;
scmi_sram: sram@2ffff000 {
compatible = "mmio-sram";
reg = <0x2ffff000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x2ffff000 0x1000>;
scmi_shm: scmi-sram@0 {
compatible = "arm,scmi-shmem";
reg = <0 0x80>;
};
};
timers2: timer@40000000 {
#address-cells = <1>;
#size-cells = <0>;
@@ -397,12 +383,42 @@
status = "disabled";
};
usart3: serial@4000f000 {
compatible = "st,stm32h7-uart";
reg = <0x4000f000 0x400>;
interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc USART3_K>;
resets = <&rcc USART3_R>;
wakeup-source;
dmas = <&dmamux1 45 0x400 0x5>,
<&dmamux1 46 0x400 0x1>;
dma-names = "rx", "tx";
status = "disabled";
};
uart4: serial@40010000 {
compatible = "st,stm32h7-uart";
reg = <0x40010000 0x400>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc UART4_K>;
resets = <&rcc UART4_R>;
wakeup-source;
dmas = <&dmamux1 63 0x400 0x5>,
<&dmamux1 64 0x400 0x1>;
dma-names = "rx", "tx";
status = "disabled";
};
uart5: serial@40011000 {
compatible = "st,stm32h7-uart";
reg = <0x40011000 0x400>;
interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc UART5_K>;
resets = <&rcc UART5_R>;
wakeup-source;
dmas = <&dmamux1 65 0x400 0x5>,
<&dmamux1 66 0x400 0x1>;
dma-names = "rx", "tx";
status = "disabled";
};
@@ -442,6 +458,32 @@
status = "disabled";
};
uart7: serial@40018000 {
compatible = "st,stm32h7-uart";
reg = <0x40018000 0x400>;
interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc UART7_K>;
resets = <&rcc UART7_R>;
wakeup-source;
dmas = <&dmamux1 79 0x400 0x5>,
<&dmamux1 80 0x400 0x1>;
dma-names = "rx", "tx";
status = "disabled";
};
uart8: serial@40019000 {
compatible = "st,stm32h7-uart";
reg = <0x40019000 0x400>;
interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc UART8_K>;
resets = <&rcc UART8_R>;
wakeup-source;
dmas = <&dmamux1 81 0x400 0x5>,
<&dmamux1 82 0x400 0x1>;
dma-names = "rx", "tx";
status = "disabled";
};
timers1: timer@44000000 {
#address-cells = <1>;
#size-cells = <0>;
@@ -524,6 +566,19 @@
};
};
usart6: serial@44003000 {
compatible = "st,stm32h7-uart";
reg = <0x44003000 0x400>;
interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc USART6_K>;
resets = <&rcc USART6_R>;
wakeup-source;
dmas = <&dmamux1 71 0x400 0x5>,
<&dmamux1 72 0x400 0x1>;
dma-names = "rx", "tx";
status = "disabled";
};
i2s1: audio-controller@44004000 {
compatible = "st,stm32h7-i2s";
reg = <0x44004000 0x400>;
@@ -748,6 +803,32 @@
status = "disabled";
};
usart1: serial@4c000000 {
compatible = "st,stm32h7-uart";
reg = <0x4c000000 0x400>;
interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc USART1_K>;
resets = <&rcc USART1_R>;
wakeup-source;
dmas = <&dmamux1 41 0x400 0x5>,
<&dmamux1 42 0x400 0x1>;
dma-names = "rx", "tx";
status = "disabled";
};
usart2: serial@4c001000 {
compatible = "st,stm32h7-uart";
reg = <0x4c001000 0x400>;
interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc USART2_K>;
resets = <&rcc USART2_R>;
wakeup-source;
dmas = <&dmamux1 43 0x400 0x5>,
<&dmamux1 44 0x400 0x1>;
dma-names = "rx", "tx";
status = "disabled";
};
i2s4: audio-controller@4c002000 {
compatible = "st,stm32h7-i2s";
reg = <0x4c002000 0x400>;
@@ -1001,8 +1082,6 @@
reg = <0x50000000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "hse", "hsi", "csi", "lse", "lsi";
clocks = <&scmi_clk CK_SCMI_HSE>,
<&scmi_clk CK_SCMI_HSI>,

View File

@@ -19,6 +19,13 @@
aliases {
serial0 = &uart4;
serial1 = &usart1;
serial2 = &uart8;
serial3 = &usart2;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@c0000000 {
@@ -267,8 +274,41 @@
};
&uart4 {
pinctrl-names = "default";
pinctrl-names = "default", "sleep", "idle";
pinctrl-0 = <&uart4_pins_a>;
pinctrl-1 = <&uart4_sleep_pins_a>;
pinctrl-2 = <&uart4_idle_pins_a>;
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
};
&uart8 {
pinctrl-names = "default", "sleep", "idle";
pinctrl-0 = <&uart8_pins_a>;
pinctrl-1 = <&uart8_sleep_pins_a>;
pinctrl-2 = <&uart8_idle_pins_a>;
/delete-property/dmas;
/delete-property/dma-names;
status = "disabled";
};
&usart1 {
pinctrl-names = "default", "sleep", "idle";
pinctrl-0 = <&usart1_pins_a>;
pinctrl-1 = <&usart1_sleep_pins_a>;
pinctrl-2 = <&usart1_idle_pins_a>;
uart-has-rtscts;
status = "disabled";
};
/* Bluetooth */
&usart2 {
pinctrl-names = "default", "sleep", "idle";
pinctrl-0 = <&usart2_pins_a>;
pinctrl-1 = <&usart2_sleep_pins_a>;
pinctrl-2 = <&usart2_idle_pins_a>;
uart-has-rtscts;
status = "okay";
};

View File

@@ -1880,6 +1880,21 @@
};
};
spi1_pins_b: spi1-1 {
pins1 {
pinmux = <STM32_PINMUX('A', 5, AF5)>, /* SPI1_SCK */
<STM32_PINMUX('B', 5, AF5)>; /* SPI1_MOSI */
bias-disable;
drive-push-pull;
slew-rate = <1>;
};
pins2 {
pinmux = <STM32_PINMUX('A', 6, AF5)>; /* SPI1_MISO */
bias-disable;
};
};
spi2_pins_a: spi2-0 {
pins1 {
pinmux = <STM32_PINMUX('B', 10, AF5)>, /* SPI2_SCK */
@@ -2163,7 +2178,7 @@
<STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */
bias-disable;
drive-push-pull;
slew-rate = <3>;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('D', 6, AF7)>, /* USART2_RX */
@@ -2181,7 +2196,7 @@
pinmux = <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */
bias-disable;
drive-push-pull;
slew-rate = <3>;
slew-rate = <0>;
};
pins3 {
pinmux = <STM32_PINMUX('D', 6, AF7)>; /* USART2_RX */
@@ -2448,19 +2463,4 @@
bias-disable;
};
};
spi1_pins_b: spi1-1 {
pins1 {
pinmux = <STM32_PINMUX('A', 5, AF5)>, /* SPI1_SCK */
<STM32_PINMUX('B', 5, AF5)>; /* SPI1_MOSI */
bias-disable;
drive-push-pull;
slew-rate = <1>;
};
pins2 {
pinmux = <STM32_PINMUX('A', 6, AF5)>; /* SPI1_MISO */
bias-disable;
};
};
};

View File

@@ -16,7 +16,6 @@
#address-cells = <1>;
#size-cells = <0>;
linaro,optee-channel-id = <0>;
shmem = <&scmi_shm>;
scmi_clk: protocol@14 {
reg = <0x14>;
@@ -60,21 +59,6 @@
};
};
};
soc {
scmi_sram: sram@2ffff000 {
compatible = "mmio-sram";
reg = <0x2ffff000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x2ffff000 0x1000>;
scmi_shm: scmi-sram@0 {
compatible = "arm,scmi-shmem";
reg = <0 0x80>;
};
};
};
};
&reg11 {

View File

@@ -1148,8 +1148,8 @@
usbotg_hs: usb-otg@49000000 {
compatible = "st,stm32mp15-hsotg", "snps,dwc2";
reg = <0x49000000 0x10000>;
clocks = <&rcc USBO_K>;
clock-names = "otg";
clocks = <&rcc USBO_K>, <&usbphyc>;
clock-names = "otg", "utmi";
resets = <&rcc USBO_R>;
reset-names = "dwc2";
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;

View File

@@ -17,9 +17,6 @@
aliases {
ethernet0 = &ethernet0;
serial0 = &uart4;
serial1 = &usart3;
serial2 = &uart7;
};
chosen {

View File

@@ -18,9 +18,6 @@
aliases {
ethernet0 = &ethernet0;
serial0 = &uart4;
serial1 = &usart3;
serial2 = &uart7;
serial3 = &usart2;
};

View File

@@ -16,6 +16,10 @@
model = "STMicroelectronics STM32MP157C eval daughter";
compatible = "st,stm32mp157c-ed1", "st,stm32mp157";
aliases {
serial0 = &uart4;
};
chosen {
stdout-path = "serial0:115200n8";
};
@@ -65,15 +69,6 @@
reg = <0x38000000 0x10000>;
no-map;
};
gpu_reserved: gpu@e8000000 {
reg = <0xe8000000 0x8000000>;
no-map;
};
};
aliases {
serial0 = &uart4;
};
sd_switch: regulator-sd_switch {
@@ -148,10 +143,6 @@
status = "okay";
};
&gpu {
contiguous-area = <&gpu_reserved>;
};
&hash1 {
status = "okay";
};

View File

@@ -14,16 +14,15 @@
model = "STMicroelectronics STM32MP157C eval daughter on eval mother";
compatible = "st,stm32mp157c-ev1", "st,stm32mp157c-ed1", "st,stm32mp157";
chosen {
stdout-path = "serial0:115200n8";
};
aliases {
serial0 = &uart4;
serial1 = &usart3;
ethernet0 = &ethernet0;
};
chosen {
stdout-path = "serial0:115200n8";
};
clocks {
clk_ext_camera: clk-ext-camera {
#clock-cells = <0>;

View File

@@ -118,13 +118,12 @@
&ethernet0 {
status = "okay";
pinctrl-0 = <&ethernet0_rmii_pins_a>;
pinctrl-1 = <&ethernet0_rmii_sleep_pins_a>;
pinctrl-0 = <&ethernet0_rmii_pins_c &mco2_pins_a>;
pinctrl-1 = <&ethernet0_rmii_sleep_pins_c &mco2_sleep_pins_a>;
pinctrl-names = "default", "sleep";
phy-mode = "rmii";
max-speed = <100>;
phy-handle = <&phy0>;
st,eth-ref-clk-sel;
mdio0 {
#address-cells = <1>;
@@ -136,7 +135,7 @@
/* LAN8710Ai */
compatible = "ethernet-phy-id0007.c0f0",
"ethernet-phy-ieee802.3-c22";
clocks = <&rcc ETHCK_K>;
clocks = <&rcc CK_MCO2>;
reset-gpios = <&gpioh 3 GPIO_ACTIVE_LOW>;
reset-assert-us = <500>;
reset-deassert-us = <500>;
@@ -450,6 +449,21 @@
};
};
&rcc {
/* Connect MCO2 output to ETH_RX_CLK input via pad-pad connection */
clocks = <&rcc CK_MCO2>;
clock-names = "ETH_RX_CLK/ETH_REF_CLK";
/*
* Set PLL4P output to 100 MHz to supply SDMMC with faster clock,
* set MCO2 output to 50 MHz to supply ETHRX clock with PLL4P/2,
* so that MCO2 behaves as a divider for the ETHRX clock here.
*/
assigned-clocks = <&rcc CK_MCO2>, <&rcc PLL4_P>;
assigned-clock-parents = <&rcc PLL4_P>;
assigned-clock-rates = <50000000>, <100000000>;
};
&rng1 {
status = "okay";
};

View File

@@ -153,6 +153,20 @@
};
&rcc {
/*
* Reinstate clock names from stm32mp151.dtsi, the MCO2 trick
* used in stm32mp15xx-dhcom-som.dtsi is not supported by the
* U-Boot clock framework.
*/
clock-names = "hse", "hsi", "csi", "lse", "lsi";
clocks = <&clk_hse>, <&clk_hsi>, <&clk_csi>,
<&clk_lse>, <&clk_lsi>;
/* The MCO2 is already configured correctly, remove those. */
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
/delete-property/ assigned-clock-rates;
st,clksrc = <
CLK_MPU_PLL1P
CLK_AXI_PLL2P

View File

@@ -8,6 +8,12 @@
#include <dt-bindings/mfd/st,stpmic1.h>
/ {
aliases {
serial0 = &uart4;
serial1 = &usart3;
serial2 = &uart7;
};
memory@c0000000 {
device_type = "memory";
reg = <0xc0000000 0x20000000>;
@@ -53,11 +59,6 @@
reg = <0x38000000 0x10000>;
no-map;
};
gpu_reserved: gpu@d4000000 {
reg = <0xd4000000 0x4000000>;
no-map;
};
};
led {
@@ -159,10 +160,6 @@
};
};
&gpu {
contiguous-area = <&gpu_reserved>;
};
&hash1 {
status = "okay";
};

View File

@@ -27,7 +27,13 @@
spi@7000c380 {
status = "okay";
spi-max-frequency = <25000000>;
spi-max-frequency = <48000000>;
flash@0 {
compatible = "winbond,w25q80bl", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <48000000>;
};
};
pcie@80003000 {

View File

@@ -0,0 +1,157 @@
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/input/input.h>
#include "tegra30.dtsi"
/ {
chosen {
stdout-path = &uarta;
};
aliases {
i2c0 = &pwr_i2c;
mmc0 = &sdmmc4; /* eMMC */
rtc0 = &pmic;
rtc1 = "/rtc@7000e000";
usb0 = &usb1;
};
memory {
device_type = "memory";
reg = <0x80000000 0x40000000>;
};
host1x@50000000 {
dc@54200000 {
nvidia,180-rotation;
rgb {
status = "okay";
nvidia,panel = <&panel>;
};
};
};
gpio@6000d000 {
volume-buttons-hog {
gpio-hog;
gpios = <TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>,
<TEGRA_GPIO(Q, 0) GPIO_ACTIVE_HIGH>;
output-low;
};
};
uarta: serial@70006000 {
status = "okay";
};
pwm: pwm@7000a000 {
status = "okay";
};
pwr_i2c: i2c@7000d000 {
status = "okay";
clock-frequency = <400000>;
};
sdmmc4: sdhci@78000600 {
status = "okay";
bus-width = <8>;
non-removable;
};
usb1: usb@7d000000 {
status = "okay";
dr_mode = "otg";
};
backlight: backlight {
compatible = "pwm-backlight";
enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
power-supply = <&vdd_5v0_bl>;
pwms = <&pwm 0 50000>;
brightness-levels = <1 35 70 105 140 175 210 255>;
default-brightness-level = <5>;
};
/* PMIC has a built-in 32KHz oscillator which is used by PMC */
clk32k_in: clock-32k {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "pmic-oscillator";
};
gpio-keys {
compatible = "gpio-keys";
key-power {
label = "Power";
gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>;
linux,code = <KEY_ENTER>;
};
key-volume-up {
label = "Volume Up";
gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>;
linux,code = <KEY_UP>;
};
key-volume-down {
label = "Volume Down";
gpios = <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_LOW>;
linux,code = <KEY_DOWN>;
};
};
panel: panel {
compatible = "simple-panel";
power-supply = <&vdd_pnl_reg>;
enable-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_HIGH>;
backlight = <&backlight>;
display-timings {
timing@0 {
/* 1280x800@60Hz */
clock-frequency = <68000000>;
hactive = <800>;
hfront-porch = <24>;
hback-porch = <32>;
hsync-len = <24>;
vactive = <1280>;
vfront-porch = <5>;
vback-porch = <32>;
vsync-len = <1>;
};
};
};
vdd_pnl_reg: regulator-pnl {
compatible = "regulator-fixed";
regulator-name = "vdd_panel";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio TEGRA_GPIO(W, 1) GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vdd_5v0_bl: regulator-bl {
compatible = "regulator-fixed";
regulator-name = "vdd_5v0_bl";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-boot-on;
gpio = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};

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// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "tegra30-asus-grouper-common.dtsi"
/ {
model = "ASUS Google Nexus 7 (Project Nakasi / ME370T) E1565";
compatible = "asus,grouper", "nvidia,tegra30";
i2c@7000d000 {
pmic: max77663@3c {
compatible = "maxim,max77663";
reg = <0x3c>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
interrupt-controller;
system-power-controller;
#gpio-cells = <2>;
gpio-controller;
regulators {
vdd_1v8: sd2 {
regulator-name = "vdd_1v8_gen";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
/* eMMC VDD */
vcore_emmc: ldo3 {
regulator-name = "vcore_emmc";
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <3100000>;
regulator-always-on;
};
};
};
};
};

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// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "tegra30-asus-grouper-common.dtsi"
/ {
model = "ASUS Google Nexus 7 (Project Nakasi / ME370T) PM269";
compatible = "asus,grouper", "nvidia,tegra30";
i2c@7000d000 {
/* Texas Instruments TPS659110 PMIC */
pmic: tps65911@2d {
compatible = "ti,tps65911";
reg = <0x2d>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
interrupt-controller;
ti,system-power-controller;
#gpio-cells = <2>;
gpio-controller;
regulators {
/* eMMC VDD */
vcore_emmc: ldo1 {
regulator-name = "vdd_emmc_core";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
};
};
};

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// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "tegra30-asus-grouper-common.dtsi"
/ {
model = "ASUS Google Nexus 7 (Project Bach / ME370TG) E1565";
compatible = "asus,tilapia", "nvidia,tegra30";
i2c@7000d000 {
pmic: max77663@3c {
compatible = "maxim,max77663";
reg = <0x3c>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
interrupt-controller;
system-power-controller;
#gpio-cells = <2>;
gpio-controller;
regulators {
vdd_1v8: sd2 {
regulator-name = "vdd_1v8_gen";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
/* eMMC VDD */
vcore_emmc: ldo3 {
regulator-name = "vcore_emmc";
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <3100000>;
regulator-always-on;
};
};
};
};
panel {
display-timings {
timing@0 {
/* 1280x800@60Hz */
clock-frequency = <81750000>;
hactive = <800>;
hfront-porch = <64>;
hback-porch = <128>;
hsync-len = <64>;
vactive = <1280>;
vfront-porch = <5>;
vback-porch = <2>;
vsync-len = <1>;
};
};
};
};

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// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "tegra30-asus-transformer.dtsi"
/ {
model = "ASUS Portable AiO P1801-T";
compatible = "asus,p1801-t", "nvidia,tegra30";
/delete-node/ host1x@50000000;
/delete-node/ pwm@7000a000;
/delete-node/ backlight;
/delete-node/ panel;
/delete-node/ regulator-pnl;
/delete-node/ regulator-bl;
};

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// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "tegra30-asus-transformer.dtsi"
/ {
model = "ASUS Transformer Prime TF201";
compatible = "asus,tf201", "nvidia,tegra30";
};

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// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "tegra30-asus-transformer.dtsi"
/ {
model = "ASUS Transformer Pad TF300T";
compatible = "asus,tf300t", "nvidia,tegra30";
gpio@6000d000 {
volume-buttons-hog {
gpio-hog;
gpios = <TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>,
<TEGRA_GPIO(K, 7) GPIO_ACTIVE_HIGH>;
output-low;
};
};
};

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// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "tegra30-asus-transformer.dtsi"
/ {
model = "ASUS Transformer Pad 3G TF300TG";
compatible = "asus,tf300tg", "nvidia,tegra30";
};

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// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "tegra30-asus-transformer.dtsi"
/ {
model = "ASUS Transformer Pad LTE TF300TL";
compatible = "asus,tf300tl", "nvidia,tegra30";
};

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// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "tegra30-asus-transformer.dtsi"
/ {
model = "ASUS VivoTab RT TF600T";
compatible = "asus,tf600t", "nvidia,tegra30";
aliases {
spi0 = &spi4;
};
/delete-node/ host1x@50000000;
pmic_i2c: i2c@7000d000 {
/* Texas Instruments TPS659110 PMIC */
pmic: tps65911@2d {
regulators {
vdd_1v2_bl: vdd1 {
regulator-name = "vdd_1v2_backlight";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
regulator-boot-on;
ti,regulator-ext-sleep-control = <8>;
};
/delete-node/ ldo2;
/delete-node/ ldo3;
/* uSD slot VDDIO */
vddio_usd: ldo5 {
regulator-name = "vddio_sdmmc";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
avdd_dsi_csi: ldo6 {
regulator-name = "avdd_dsi_csi";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
};
};
};
spi4: spi@7000da00 {
status = "okay";
spi-max-frequency = <25000000>;
spi-flash@1 {
compatible = "winbond,w25q32", "jedec,spi-nor";
reg = <1>;
spi-max-frequency = <20000000>;
};
};
backlight {
power-supply = <&vdd_1v2_bl>;
};
gpio-keys {
key-volume-up {
label = "Volume Up";
gpios = <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_LOW>;
linux,code = <KEY_UP>;
};
key-volume-down {
label = "Volume Down";
gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
linux,code = <KEY_DOWN>;
};
};
/delete-node/ panel;
vdd_usd: regulator-usd {
compatible = "regulator-fixed";
regulator-name = "vdd_usd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
/delete-node/ regulator-pnl;
/delete-node/ regulator-bl;
};

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// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "tegra30-asus-transformer.dtsi"
/ {
model = "ASUS Transformer Infinity TF700T";
compatible = "asus,tf700t", "nvidia,tegra30";
/delete-node/ host1x@50000000;
/delete-node/ panel;
};

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// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/input/input.h>
#include "tegra30.dtsi"
/ {
chosen {
stdout-path = &uarta;
};
aliases {
i2c0 = &pwr_i2c;
i2c1 = &gen1_i2c;
mmc0 = &sdmmc4; /* eMMC */
mmc1 = &sdmmc1; /* uSD slot */
rtc0 = &pmic;
rtc1 = "/rtc@7000e000";
usb0 = &usb1;
usb1 = &usb3; /* Dock USB */
};
memory {
device_type = "memory";
reg = <0x80000000 0x40000000>;
};
host1x@50000000 {
dc@54200000 {
rgb {
status = "okay";
nvidia,panel = <&panel>;
};
};
};
uarta: serial@70006000 {
status = "okay";
};
pwm: pwm@7000a000 {
status = "okay";
};
gen1_i2c: i2c@7000c000 {
status = "okay";
clock-frequency = <100000>;
};
pwr_i2c: i2c@7000d000 {
status = "okay";
clock-frequency = <400000>;
/* Texas Instruments TPS659110 PMIC */
pmic: tps65911@2d {
compatible = "ti,tps65911";
reg = <0x2d>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
interrupt-controller;
ti,system-power-controller;
#gpio-cells = <2>;
gpio-controller;
regulators {
/* eMMC VDD */
vcore_emmc: ldo1 {
regulator-name = "vdd_emmc_core";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
/* uSD slot VDD */
vdd_usd: ldo2 {
regulator-name = "vdd_usd";
regulator-min-microvolt = <3100000>;
regulator-max-microvolt = <3100000>;
};
/* uSD slot VDDIO */
vddio_usd: ldo3 {
regulator-name = "vddio_usd";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3100000>;
};
};
};
};
sdmmc1: sdhci@78000000 {
status = "okay";
bus-width = <4>;
cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
vmmc-supply = <&vdd_usd>;
vqmmc-supply = <&vddio_usd>;
};
sdmmc4: sdhci@78000600 {
status = "okay";
bus-width = <8>;
non-removable;
};
/* USB via ASUS connector */
usb1: usb@7d000000 {
status = "okay";
dr_mode = "otg";
};
/* Dock's USB port */
usb3: usb@7d008000 {
status = "okay";
};
backlight: backlight {
compatible = "pwm-backlight";
enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
power-supply = <&vdd_5v0_bl>;
pwms = <&pwm 0 4000000>;
brightness-levels = <1 35 70 105 140 175 210 255>;
default-brightness-level = <5>;
};
/* PMIC has a built-in 32KHz oscillator which is used by PMC */
clk32k_in: clock-32k {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "pmic-oscillator";
};
gpio-keys {
compatible = "gpio-keys";
key-power {
label = "Power";
gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>;
linux,code = <KEY_ENTER>;
};
key-volume-up {
label = "Volume Up";
gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>;
linux,code = <KEY_UP>;
};
key-volume-down {
label = "Volume Down";
gpios = <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_LOW>;
linux,code = <KEY_DOWN>;
};
};
panel: panel {
compatible = "simple-panel";
power-supply = <&vdd_pnl_reg>;
enable-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_HIGH>;
backlight = <&backlight>;
display-timings {
timing@0 {
/* 1280x800@60Hz */
clock-frequency = <68000000>;
hactive = <1280>;
hfront-porch = <48>;
hback-porch = <18>;
hsync-len = <30>;
vactive = <800>;
vfront-porch = <3>;
vback-porch = <12>;
vsync-len = <5>;
};
};
};
vdd_pnl_reg: regulator-pnl {
compatible = "regulator-fixed";
regulator-name = "vdd_panel";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio TEGRA_GPIO(W, 1) GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vdd_5v0_bl: regulator-bl {
compatible = "regulator-fixed";
regulator-name = "vdd_5v0_bl";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-boot-on;
gpio = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};

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// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
/* This dts file describes the HTC One X smartphone */
/* CPU Speedo ID 4, Soc Speedo ID 1, CPU Process: 1, Core Process: 0 */
#include <dt-bindings/input/input.h>
#include "tegra30.dtsi"
/ {
model = "HTC One X";
compatible = "htc,endeavoru", "nvidia,tegra30";
chosen {
stdout-path = &uarta;
};
aliases {
i2c0 = &pwr_i2c;
mmc0 = &sdmmc4; /* eMMC */
rtc0 = &pmic;
rtc1 = "/rtc@7000e000";
usb0 = &micro_usb;
};
memory {
device_type = "memory";
reg = <0x80000000 0x40000000>;
};
host1x@50000000 {
dc@54200000 {
clocks = <&tegra_car TEGRA30_CLK_DISP1>,
<&tegra_car TEGRA30_CLK_PLL_D_OUT0>;
rgb {
status = "okay";
nvidia,panel = <&dsia>;
};
};
dsia: dsi@54300000 {
status = "okay";
avdd-dsi-csi-supply = <&avdd_dsi_csi>;
panel = <&panel>;
};
};
uarta: serial@70006000 {
status = "okay";
};
pwr_i2c: i2c@7000d000 {
status = "okay";
clock-frequency = <100000>;
/* Texas Instruments TPS80032 PMIC */
pmic: tps80032@48 {
compatible = "ti,tps80032";
reg = <0x48>;
regulators {
/* DSI VDD */
avdd_dsi_csi: ldo1 {
regulator-name = "avdd_dsi_csi";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
};
};
};
};
sdmmc4: sdhci@78000600 {
status = "okay";
bus-width = <8>;
non-removable;
};
micro_usb: usb@7d000000 {
status = "okay";
dr_mode = "otg";
};
backlight: backlight {
compatible = "nvidia,tegra-pwm-backlight";
nvidia,pwm-source = <1>;
nvidia,default-brightness = <0x8E>;
};
/* PMIC has a built-in 32KHz oscillator which is used by PMC */
clk32k_in: clock-32k {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "pmic-oscillator";
};
gpio-keys {
compatible = "gpio-keys";
key-power {
label = "Power";
gpios = <&gpio TEGRA_GPIO(U, 6) GPIO_ACTIVE_LOW>;
linux,code = <KEY_ENTER>;
};
key-volume-up {
label = "Volume Up";
gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>;
linux,code = <KEY_UP>;
};
key-volume-down {
label = "Volume Down";
gpios = <&gpio TEGRA_GPIO(W, 3) GPIO_ACTIVE_LOW>;
linux,code = <KEY_DOWN>;
};
};
panel: panel {
compatible = "htc,edge-panel";
reset-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_LOW>;
vdd-supply = <&vdd_3v3_panel>;
vddio-supply = <&vdd_1v8_panel>;
backlight = <&backlight>;
};
vcore_emmc: regulator-emmc {
compatible = "regulator-fixed";
regulator-name = "vdd_2v85_sdmmc";
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2850000>;
gpio = <&gpio TEGRA_GPIO(M, 3) GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vdd_3v3_panel: regulator-lcm {
compatible = "regulator-fixed";
regulator-name = "v_lcm_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio TEGRA_GPIO(E, 2) GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vdd_1v8_panel: regulator-lcmio {
compatible = "regulator-fixed";
regulator-name = "v_lcmio_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpio = <&gpio TEGRA_GPIO(E, 5) GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};

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// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "tegra30-lg-x3.dtsi"
/ {
model = "LG Optimus 4X HD";
compatible = "lge,p880", "nvidia,tegra30";
aliases {
mmc1 = &sdmmc3; /* uSD slot */
};
sdmmc3: sdhci@78000400 {
status = "okay";
bus-width = <4>;
cd-gpios = <&gpio TEGRA_GPIO(W, 5) GPIO_ACTIVE_LOW>;
vmmc-supply = <&vdd_usd>;
vqmmc-supply = <&vdd_1v8_vio>;
};
gpio-keys {
key-volume-up {
label = "Volume Up";
gpios = <&gpio TEGRA_GPIO(O, 7) GPIO_ACTIVE_LOW>;
linux,code = <KEY_UP>;
};
};
panel: panel {
compatible = "jdi,dx12d100vm0eaa";
enable-gpios = <&gpio TEGRA_GPIO(Y, 0) GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
backlight = <&backlight>;
};
};

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// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "tegra30-lg-x3.dtsi"
/ {
model = "LG Optimus Vu";
compatible = "lge,p895", "nvidia,tegra30";
gpio-keys {
key-volume-up {
label = "Volume Up";
gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_LOW>;
linux,code = <KEY_UP>;
};
};
panel: panel {
compatible = "hitachi,tx13d100vm0eaa";
reset-gpios = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
renesas,gamma = <3>;
renesas,inversion;
renesas,contrast;
vcc-supply = <&vcc_3v0_lcd>;
iovcc-supply = <&iovcc_1v8_lcd>;
backlight = <&backlight>;
};
vcc_3v0_lcd: regulator-lcd {
compatible = "regulator-fixed";
regulator-name = "vcc_3v0_lcd";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
gpio = <&gpio TEGRA_GPIO(BB, 0) GPIO_ACTIVE_HIGH>;
enable-active-high;
};
iovcc_1v8_lcd: regulator-lcdvio {
compatible = "regulator-fixed";
regulator-name = "iovcc_1v8_lcd";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpio = <&gpio TEGRA_GPIO(Y, 0) GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};

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// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/input/input.h>
#include "tegra30.dtsi"
/ {
chosen {
stdout-path = &uartd;
};
aliases {
i2c0 = &pwr_i2c;
i2c1 = &gen2_i2c;
mmc0 = &sdmmc4; /* eMMC */
rtc0 = &pmic;
rtc1 = "/rtc@7000e000";
spi0 = &dsi_spi;
usb0 = &micro_usb;
};
memory {
device_type = "memory";
reg = <0x80000000 0x40000000>;
};
host1x@50000000 {
dc@54200000 {
rgb {
status = "okay";
nvidia,panel = <&bridge>;
};
};
};
uartd: serial@70006300 {
status = "okay";
};
gen2_i2c: i2c@7000c400 {
status = "okay";
clock-frequency = <400000>;
backlight: lm3533@36 {
compatible = "ti,lm3533";
reg = <0x36>;
enable-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_HIGH>;
default-brightness-level = <128>;
};
muic@44 {
compatible = "maxim,max14526-muic";
reg = <0x44>;
maxim,ap-usb;
usif-gpios = <&gpio TEGRA_GPIO(Y, 3) GPIO_ACTIVE_HIGH>;
dp2t-gpios = <&gpio TEGRA_GPIO(CC, 2) GPIO_ACTIVE_HIGH>;
};
};
pwr_i2c: i2c@7000d000 {
status = "okay";
clock-frequency = <400000>;
pmic: max77663@1c {
compatible = "maxim,max77663";
reg = <0x1c>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
interrupt-controller;
#gpio-cells = <2>;
gpio-controller;
system-power-controller;
regulators {
vdd_1v8_vio: sd2 {
regulator-name = "vdd_1v8_gen";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
vdd_usd: ldo3 {
regulator-name = "vdd_sdmmc3";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-always-on;
regulator-boot-on;
};
vcore_emmc: ldo5 {
regulator-name = "vdd_ddr_rx";
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2850000>;
regulator-always-on;
regulator-boot-on;
};
};
};
};
dsi_spi: spi@7000dc00 {
status = "okay";
spi-max-frequency = <25000000>;
bridge: bridge-spi@2 {
compatible = "solomon,ssd2825";
reg = <2>;
spi-cpol;
spi-cpha;
spi-max-frequency = <1000000>;
power-gpios = <&gpio TEGRA_GPIO(B, 1) GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio TEGRA_GPIO(O, 2) GPIO_ACTIVE_HIGH>;
clocks = <&ssd2825_refclk>;
clock-names = "tx_clk";
panel = <&panel>;
};
};
sdmmc4: sdhci@78000600 {
status = "okay";
bus-width = <8>;
non-removable;
vmmc-supply = <&vcore_emmc>;
vqmmc-supply = <&vdd_1v8_vio>;
};
micro_usb: usb@7d000000 {
status = "okay";
dr_mode = "otg";
};
/* PMIC has a built-in 32KHz oscillator which is used by PMC */
clk32k_in: clock-32k {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "pmic-oscillator";
};
ssd2825_refclk: clock-ssd2825 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
clock-output-names = "ssd2825-refclk";
};
gpio-keys {
compatible = "gpio-keys";
key-power {
label = "Power";
gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
linux,code = <KEY_ENTER>;
};
key-volume-down {
label = "Volume Down";
gpios = <&gpio TEGRA_GPIO(O, 4) GPIO_ACTIVE_LOW>;
linux,code = <KEY_DOWN>;
};
};
};

View File

@@ -189,6 +189,21 @@ enum {
DCLK_VOP_DIV_SHIFT = 0,
DCLK_VOP_DIV_MASK = 0xff,
/* CRU_CLKSEL_CON10 */
/* CRU_CLKSEL_CON13 */
/* CRU_CLKSEL_CON16 */
/* CRU_CLKSEL_CON19 */
/* CRU_CLKSEL_CON22 */
CLK_UART_PLL_SEL_SHIFT = 13,
CLK_UART_PLL_SEL_MASK = 0x7 << CLK_UART_PLL_SEL_SHIFT,
CLK_UART_PLL_SEL_DPLL = 0,
CLK_UART_PLL_SEL_VPLL0,
CLK_UART_PLL_SEL_VPLL1,
CLK_UART_PLL_SEL_480M,
CLK_UART_PLL_SEL_24M,
CLK_UART_DIV_CON_SHIFT = 0,
CLK_UART_DIV_CON_MASK = 0x1f << CLK_UART_DIV_CON_SHIFT,
/* CRU_CLK_SEL25_CON */
/* CRU_CLK_SEL26_CON */
/* CRU_CLK_SEL27_CON */

View File

@@ -15,6 +15,8 @@
# include <asm/arch-rockchip/cru_rk3288.h>
#elif defined(CONFIG_ROCKCHIP_RK3399)
# include <asm/arch-rockchip/cru_rk3399.h>
#elif defined(CONFIG_ROCKCHIP_RK3568)
#include <asm/arch-rockchip/cru_rk3568.h>
#endif
/* CRU_GLB_RST_ST */

View File

@@ -106,6 +106,8 @@ struct rk3568_cru {
unsigned int emmc_con[2];/* Address Offset: 0x0598 */
};
#define rockchip_cru rk3568_cru
check_member(rk3568_cru, mode_con00, 0xc0);
check_member(rk3568_cru, softrst_con[0], 0x400);
@@ -493,7 +495,7 @@ enum {
/* CRU_CLK_SEL81_CON */
CPLL_25M_DIV_SHIFT = 8,
CPLL_25M_DIV_MASK = 0x1f << CPLL_25M_DIV_SHIFT,
CPLL_25M_DIV_MASK = 0x3f << CPLL_25M_DIV_SHIFT,
CPLL_50M_DIV_SHIFT = 0,
CPLL_50M_DIV_MASK = 0x1f << CPLL_50M_DIV_SHIFT,

View File

@@ -19,4 +19,11 @@ struct fuse_regs {
u32 security_mode; /* 0x1A0: FUSE_SECURITY_MODE */
};
/**
* Calculate SoC UID
*
* Return: uid if ok, 0 on error
*/
unsigned long long tegra_chip_uid(void);
#endif /* ifndef _FUSE_H_ */

View File

@@ -9,6 +9,11 @@
* generate asm statements containing #defines,
* compile this file to assembler, and then extract the
* #defines from the assembly-language output.
*
* Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
*
* Authors:
* Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
*/
#include <common.h>
@@ -90,6 +95,17 @@ int main(void)
DEFINE(ARM_SMCCC_RES_X2_OFFS, offsetof(struct arm_smccc_res, a2));
DEFINE(ARM_SMCCC_QUIRK_ID_OFFS, offsetof(struct arm_smccc_quirk, id));
DEFINE(ARM_SMCCC_QUIRK_STATE_OFFS, offsetof(struct arm_smccc_quirk, state));
#ifdef CONFIG_ARM64
DEFINE(ARM_SMCCC_1_2_REGS_X0_OFFS, offsetof(struct arm_smccc_1_2_regs, a0));
DEFINE(ARM_SMCCC_1_2_REGS_X2_OFFS, offsetof(struct arm_smccc_1_2_regs, a2));
DEFINE(ARM_SMCCC_1_2_REGS_X4_OFFS, offsetof(struct arm_smccc_1_2_regs, a4));
DEFINE(ARM_SMCCC_1_2_REGS_X6_OFFS, offsetof(struct arm_smccc_1_2_regs, a6));
DEFINE(ARM_SMCCC_1_2_REGS_X8_OFFS, offsetof(struct arm_smccc_1_2_regs, a8));
DEFINE(ARM_SMCCC_1_2_REGS_X10_OFFS, offsetof(struct arm_smccc_1_2_regs, a10));
DEFINE(ARM_SMCCC_1_2_REGS_X12_OFFS, offsetof(struct arm_smccc_1_2_regs, a12));
DEFINE(ARM_SMCCC_1_2_REGS_X14_OFFS, offsetof(struct arm_smccc_1_2_regs, a14));
DEFINE(ARM_SMCCC_1_2_REGS_X16_OFFS, offsetof(struct arm_smccc_1_2_regs, a16));
#endif
#endif
return 0;

View File

@@ -32,6 +32,7 @@ config IMX_RDC
config IMX_BOOTAUX
bool "Support boot auxiliary core"
depends on ARCH_MX7 || ARCH_MX6 || ARCH_VF610 || ARCH_IMX8 || ARCH_IMX8M
select LIB_ELF
help
bootaux [addr] to boot auxiliary core.

View File

@@ -662,7 +662,7 @@ static int do_authenticate_image_or_failover(struct cmd_tbl *cmdtp, int flag,
{
int ret = CMD_RET_FAILURE;
if (argc != 4) {
if (argc < 3) {
ret = CMD_RET_USAGE;
goto error;
}
@@ -703,7 +703,7 @@ U_BOOT_CMD(
"addr length ivt_offset\n"
"addr - image hex address\n"
"length - image hex length\n"
"ivt_offset - hex offset of IVT in the image"
"ivt_offset - hex offset of IVT in the image (optional)"
);
U_BOOT_CMD(
@@ -715,11 +715,11 @@ U_BOOT_CMD(
U_BOOT_CMD(
hab_auth_img_or_fail, 4, 0,
do_authenticate_image_or_failover,
"authenticate image via HAB on failure drop to USB BootROM mode",
"authenticate image via HAB. Switch to USB BootROM mode on failure",
"addr length ivt_offset\n"
"addr - image hex address\n"
"length - image hex length\n"
"ivt_offset - hex offset of IVT in the image"
"ivt_offset - hex offset of IVT in the image (optional)"
);
U_BOOT_CMD(

View File

@@ -244,7 +244,7 @@ int dram_init(void)
return ret;
/* rom_pointer[1] contains the size of TEE occupies */
if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && rom_pointer[1])
if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && !IS_ENABLED(CONFIG_SPL_BUILD) && rom_pointer[1])
gd->ram_size = sdram_size - rom_pointer[1];
else
gd->ram_size = sdram_size;
@@ -273,7 +273,7 @@ int dram_init_banksize(void)
}
gd->bd->bi_dram[bank].start = PHYS_SDRAM;
if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && rom_pointer[1]) {
if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && !IS_ENABLED(CONFIG_SPL_BUILD) && rom_pointer[1]) {
phys_addr_t optee_start = (phys_addr_t)rom_pointer[0];
phys_size_t optee_size = (size_t)rom_pointer[1];
@@ -318,7 +318,8 @@ phys_size_t get_effective_memsize(void)
sdram_b1_size = sdram_size;
}
if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && rom_pointer[1]) {
if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && !IS_ENABLED(CONFIG_SPL_BUILD) &&
rom_pointer[1]) {
/* We will relocate u-boot to Top of dram1. Tee position has two cases:
* 1. At the top of dram1, Then return the size removed optee size.
* 2. In the middle of dram1, return the size of dram1.
@@ -333,7 +334,7 @@ phys_size_t get_effective_memsize(void)
}
}
phys_size_t board_get_usable_ram_top(phys_size_t total_size)
phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
ulong top_addr;

View File

@@ -361,7 +361,7 @@ int dram_init(void)
return ret;
/* rom_pointer[1] contains the size of TEE occupies */
if (rom_pointer[1])
if (!IS_ENABLED(CONFIG_SPL_BUILD) && rom_pointer[1])
gd->ram_size = sdram_size - rom_pointer[1];
else
gd->ram_size = sdram_size;
@@ -390,7 +390,7 @@ int dram_init_banksize(void)
}
gd->bd->bi_dram[bank].start = PHYS_SDRAM;
if (rom_pointer[1]) {
if (!IS_ENABLED(CONFIG_SPL_BUILD) && rom_pointer[1]) {
phys_addr_t optee_start = (phys_addr_t)rom_pointer[0];
phys_size_t optee_size = (size_t)rom_pointer[1];
@@ -435,7 +435,7 @@ phys_size_t get_effective_memsize(void)
else
sdram_b1_size = sdram_size;
if (rom_pointer[1]) {
if (!IS_ENABLED(CONFIG_SPL_BUILD) && rom_pointer[1]) {
/* We will relocate u-boot to top of dram1. TEE position has two cases:
* 1. At the top of dram1, Then return the size removed optee size.
* 2. In the middle of dram1, return the size of dram1.

View File

@@ -24,14 +24,6 @@ config SPL_TEXT_BASE
depends on SPL
default 0x00912000
config OPTEE_TZDRAM_SIZE
hex "Amount of Trust-Zone RAM for the OPTEE image"
default 0x0000000
depends on OPTEE_LIB
help
The size of pre-allocated Trust Zone DRAM to allocate for the OPTEE
runtime.
choice
prompt "MX7 board select"
optional

View File

@@ -30,7 +30,7 @@ DECLARE_GLOBAL_DATA_PTR;
*/
#define USABLE_RAM_SIZE 0x80000000ULL
phys_size_t board_get_usable_ram_top(phys_size_t total_size)
phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
unsigned long top = CFG_SYS_SDRAM_BASE + min(gd->ram_size, USABLE_RAM_SIZE);

View File

@@ -105,15 +105,6 @@ config TARGET_OMAP3_LOGIC
select OMAP3_GPIO_6
imply CMD_DM
config TARGET_NOKIA_RX51
bool "Nokia RX51"
select POSITION_INDEPENDENT
select SKIP_LOWLEVEL_INIT
select SUPPORT_PASSING_ATAGS
select CMDLINE_TAG
select INITRD_TAG
select REVISION_TAG
config TARGET_TAO3530
bool "TAO3530"
select OMAP3_GPIO_2
@@ -166,7 +157,6 @@ source "board/timll/devkit8000/Kconfig"
source "board/ti/omap3evm/Kconfig"
source "board/isee/igep00x0/Kconfig"
source "board/logicpd/omap3som/Kconfig"
source "board/nokia/rx51/Kconfig"
source "board/lg/sniper/Kconfig"
endif

View File

@@ -25,6 +25,13 @@ cmd_objcopy = $(OBJCOPY) --gap-fill=0x00 $(OBJCOPYFLAGS) \
spl/u-boot-spl.srec: spl/u-boot-spl FORCE
$(call if_changed,objcopy)
srec_cat_gte_160 := ${shell expr `srec_cat -VERSION | grep ^srec_cat | sed 's/^.* //g' | cut -f1-2 -d.` \>= "1.60"}
ifeq "$(srec_cat_gte_160)" "1"
srec_cat_le_cmd := "-constant-l-e"
else
srec_cat_le_cmd := "-l-e-constant"
endif
ifneq ($(CONFIG_R8A774C0)$(CONFIG_R8A77990)$(CONFIG_R8A77995),)
#
# The first 6 generate statements generate the R-Car Gen3 SCIF loader header.
@@ -52,34 +59,34 @@ quiet_cmd_srec_cat = SRECCAT $@
cmd_srec_cat = srec_cat -output $@ -M 8 $< -M 8 \
-offset -0x13fd0 \
-Output_Block_Size 16 \
-generate 0xe6300400 0xe6300404 -l-e-constant 0x0 4 \
-generate 0xe630048c 0xe6300490 -l-e-constant 0x0 4 \
-generate 0xe63005d4 0xe63005d8 -l-e-constant 0xe6304000 4 \
-generate 0xe63006e4 0xe63006e8 -l-e-constant $2 4 \
-generate 0xe6301154 0xe6301158 -l-e-constant 0xe6304000 4 \
-generate 0xe6301264 0xe6301268 -l-e-constant $2 4 \
-generate 0xe6304000 0xe6304004 -l-e-constant 0xd2bcc000 4 \
-generate 0xe6304004 0xe6304008 -l-e-constant 0xb26c0400 4 \
-generate 0xe6304008 0xe630400c -l-e-constant 0xb2720001 4 \
-generate 0xe630400c 0xe6304010 -l-e-constant 0xb27c0421 4 \
-generate 0xe6304010 0xe6304014 -l-e-constant 0xb2710402 4 \
-generate 0xe6304014 0xe6304018 -l-e-constant 0xaa0203e0 4 \
-generate 0xe6304018 0xe630401c -l-e-constant 0xd28e0003 4 \
-generate 0xe630401c 0xe6304020 -l-e-constant 0xa8c11424 4 \
-generate 0xe6304020 0xe6304024 -l-e-constant 0xa8811444 4 \
-generate 0xe6304024 0xe6304028 -l-e-constant 0xf1004063 4 \
-generate 0xe6304028 0xe630402c -l-e-constant 0x54ffffaa 4 \
-generate 0xe630402c 0xe6304030 -l-e-constant 0xd61f0000 4
-generate 0xe6300400 0xe6300404 $(srec_cat_le_cmd) 0x0 4 \
-generate 0xe630048c 0xe6300490 $(srec_cat_le_cmd) 0x0 4 \
-generate 0xe63005d4 0xe63005d8 $(srec_cat_le_cmd) 0xe6304000 4 \
-generate 0xe63006e4 0xe63006e8 $(srec_cat_le_cmd) $2 4 \
-generate 0xe6301154 0xe6301158 $(srec_cat_le_cmd) 0xe6304000 4 \
-generate 0xe6301264 0xe6301268 $(srec_cat_le_cmd) $2 4 \
-generate 0xe6304000 0xe6304004 $(srec_cat_le_cmd) 0xd2bcc000 4 \
-generate 0xe6304004 0xe6304008 $(srec_cat_le_cmd) 0xb26c0400 4 \
-generate 0xe6304008 0xe630400c $(srec_cat_le_cmd) 0xb2720001 4 \
-generate 0xe630400c 0xe6304010 $(srec_cat_le_cmd) 0xb27c0421 4 \
-generate 0xe6304010 0xe6304014 $(srec_cat_le_cmd) 0xb2710402 4 \
-generate 0xe6304014 0xe6304018 $(srec_cat_le_cmd) 0xaa0203e0 4 \
-generate 0xe6304018 0xe630401c $(srec_cat_le_cmd) 0xd28e0003 4 \
-generate 0xe630401c 0xe6304020 $(srec_cat_le_cmd) 0xa8c11424 4 \
-generate 0xe6304020 0xe6304024 $(srec_cat_le_cmd) 0xa8811444 4 \
-generate 0xe6304024 0xe6304028 $(srec_cat_le_cmd) 0xf1004063 4 \
-generate 0xe6304028 0xe630402c $(srec_cat_le_cmd) 0x54ffffaa 4 \
-generate 0xe630402c 0xe6304030 $(srec_cat_le_cmd) 0xd61f0000 4
else
quiet_cmd_srec_cat = SRECCAT $@
cmd_srec_cat = srec_cat -output $@ -M 8 $< -M 8 \
-Output_Block_Size 16 \
-generate 0xe6300400 0xe6300404 -l-e-constant 0x0 4 \
-generate 0xe630048c 0xe6300490 -l-e-constant 0x0 4 \
-generate 0xe63005d4 0xe63005d8 -l-e-constant $(CONFIG_SPL_TEXT_BASE) 4 \
-generate 0xe63006e4 0xe63006e8 -l-e-constant $2 4 \
-generate 0xe6301154 0xe6301158 -l-e-constant $(CONFIG_SPL_TEXT_BASE) 4 \
-generate 0xe6301264 0xe6301268 -l-e-constant $2 4
-generate 0xe6300400 0xe6300404 $(srec_cat_le_cmd) 0x0 4 \
-generate 0xe630048c 0xe6300490 $(srec_cat_le_cmd) 0x0 4 \
-generate 0xe63005d4 0xe63005d8 $(srec_cat_le_cmd) $(CONFIG_SPL_TEXT_BASE) 4 \
-generate 0xe63006e4 0xe63006e8 $(srec_cat_le_cmd) $2 4 \
-generate 0xe6301154 0xe6301158 $(srec_cat_le_cmd) $(CONFIG_SPL_TEXT_BASE) 4 \
-generate 0xe6301264 0xe6301268 $(srec_cat_le_cmd) $2 4
endif
spl/u-boot-spl.scif: spl/u-boot-spl.srec spl/u-boot-spl.bin

View File

@@ -86,7 +86,7 @@ static int rmobile_cpuinfo_idx(void)
int i = 0;
u32 cpu_type = rmobile_get_cpu_type();
for (; i < ARRAY_SIZE(rmobile_cpuinfo); i++)
for (; i < ARRAY_SIZE(rmobile_cpuinfo) - 1; i++)
if (rmobile_cpuinfo[i].cpu_type == cpu_type)
break;

View File

@@ -359,6 +359,7 @@ config ROCKCHIP_RV1126
select PMIC_RK8XX
select BOARD_LATE_INIT
imply ROCKCHIP_COMMON_BOARD
imply OF_LIBFDT_OVERLAY
imply TPL_DM
imply TPL_LIBCOMMON_SUPPORT
imply TPL_LIBGENERIC_SUPPORT

View File

@@ -280,15 +280,5 @@ void spl_board_init(void)
if (cru->glb_rst_st != 0)
rk3399_force_power_on_reset();
}
if (IS_ENABLED(CONFIG_SPL_DM_REGULATOR)) {
/*
* Turning the eMMC and SPI back on (if disabled via the Qseven
* BIOS_ENABLE) signal is done through a always-on regulator).
*/
if (regulators_enable_boot_on(false))
debug("%s: Cannot enable boot on regulator\n",
__func__);
}
}
#endif

View File

@@ -216,7 +216,7 @@ int dram_init(void)
return 0;
}
phys_size_t board_get_usable_ram_top(phys_size_t total_size)
phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
unsigned long top = CFG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE;

View File

@@ -112,19 +112,6 @@ void board_init_f(ulong dummy)
{
int ret;
#ifdef CONFIG_DEBUG_UART
/*
* Debug UART can be used from here if required:
*
* debug_uart_init();
* printch('a');
* printhex8(0x1234);
* printascii("string");
*/
debug_uart_init();
debug("\nspl:debug uart enabled in %s\n", __func__);
#endif
board_early_init_f();
ret = spl_early_init();

View File

@@ -40,7 +40,7 @@ int dram_init(void)
return 0;
}
phys_size_t board_get_usable_ram_top(phys_size_t total_size)
phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
phys_size_t size;
phys_addr_t reg;

View File

@@ -729,7 +729,7 @@ void __secure psci_system_suspend(u32 __always_unused function_id,
setbits_le32(STM32_RCC_BASE + RCC_MP_CIER, RCC_MP_CIFR_WKUPF);
setbits_le32(STM32_PWR_BASE + PWR_MPUCR,
PWR_MPUCR_CSSF | PWR_MPUCR_CSTDBYDIS | PWR_MPUCR_PDDS);
PWR_MPUCR_CSSF | PWR_MPUCR_CSTDBYDIS);
saved_mcudivr = readl(STM32_RCC_BASE + RCC_MCUDIVR);
saved_pll3cr = readl(STM32_RCC_BASE + RCC_PLL3CR);

View File

@@ -64,7 +64,7 @@ static struct mm_region sunxi_mem_map[] = {
};
struct mm_region *mem_map = sunxi_mem_map;
phys_size_t board_get_usable_ram_top(phys_size_t total_size)
phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
/* Some devices (like the EMAC) have a 32-bit DMA limit. */
if (gd->ram_top > (1ULL << 32))

View File

@@ -32,6 +32,10 @@ endif
obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o
obj-y += pmc.o
ifndef CONFIG_TEGRA186
obj-y += fuse.o
endif
obj-$(CONFIG_TEGRA20) += tegra20/
obj-$(CONFIG_TEGRA30) += tegra30/
obj-$(CONFIG_TEGRA114) += tegra114/

View File

@@ -403,7 +403,7 @@ int dram_init_banksize(void)
* This function is called before dram_init_banksize(), so we can't simply
* return gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size.
*/
phys_size_t board_get_usable_ram_top(phys_size_t total_size)
phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
ulong ram_top;

151
arch/arm/mach-tegra/fuse.c Normal file
View File

@@ -0,0 +1,151 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2012-2013
* NVIDIA Corporation <www.nvidia.com>
*
* (C) Copyright 2022
* Svyatoslav Ryhel <clamor95@gmail.com>
*/
#include <common.h>
#include <linux/delay.h>
#include <asm/io.h>
#include <asm/arch/tegra.h>
#include <asm/arch/gp_padctrl.h>
#include <asm/arch/clock.h>
#include <asm/arch-tegra/fuse.h>
#include "cpu.h"
#define FUSE_UID_LOW 0x108
#define FUSE_UID_HIGH 0x10c
#define FUSE_VENDOR_CODE 0x200
#define FUSE_FAB_CODE 0x204
#define FUSE_LOT_CODE_0 0x208
#define FUSE_LOT_CODE_1 0x20c
#define FUSE_WAFER_ID 0x210
#define FUSE_X_COORDINATE 0x214
#define FUSE_Y_COORDINATE 0x218
#define FUSE_VENDOR_CODE_MASK 0xf
#define FUSE_FAB_CODE_MASK 0x3f
#define FUSE_WAFER_ID_MASK 0x3f
#define FUSE_X_COORDINATE_MASK 0x1ff
#define FUSE_Y_COORDINATE_MASK 0x1ff
static u32 tegra_fuse_readl(unsigned long offset)
{
return readl(NV_PA_FUSE_BASE + offset);
}
static void tegra_fuse_init(void)
{
u32 reg;
/*
* Performed by downstream and is not
* documented by TRM. Whithout setting
* this bit fuse region will not work.
*/
reg = readl_relaxed(NV_PA_CLK_RST_BASE + 0x48);
reg |= BIT(28);
writel(reg, NV_PA_CLK_RST_BASE + 0x48);
clock_enable(PERIPH_ID_FUSE);
udelay(2);
reset_set_enable(PERIPH_ID_FUSE, 0);
}
unsigned long long tegra_chip_uid(void)
{
u64 uid = 0ull;
u32 reg;
u32 cid;
u32 vendor;
u32 fab;
u32 lot;
u32 wafer;
u32 x;
u32 y;
u32 i;
tegra_fuse_init();
/* This used to be so much easier in prior chips. Unfortunately, there
is no one-stop shopping for the unique id anymore. It must be
constructed from various bits of information burned into the fuses
during the manufacturing process. The 64-bit unique id is formed
by concatenating several bit fields. The notation used for the
various fields is <fieldname:size_in_bits> with the UID composed
thusly:
<CID:4><VENDOR:4><FAB:6><LOT:26><WAFER:6><X:9><Y:9>
Where:
Field Bits Position Data
------- ---- -------- ----------------------------------------
CID 4 60 Chip id
VENDOR 4 56 Vendor code
FAB 6 50 FAB code
LOT 26 24 Lot code (5-digit base-36-coded-decimal,
re-encoded to 26 bits binary)
WAFER 6 18 Wafer id
X 9 9 Wafer X-coordinate
Y 9 0 Wafer Y-coordinate
------- ----
Total 64
*/
switch (tegra_get_chip()) {
case CHIPID_TEGRA20:
/* T20 has simple calculation */
return ((unsigned long long)tegra_fuse_readl(FUSE_UID_HIGH) << 32ull) |
(unsigned long long)tegra_fuse_readl(FUSE_UID_LOW);
case CHIPID_TEGRA30:
/* T30 chip id is 0 */
cid = 0;
break;
case CHIPID_TEGRA114:
/* T11x chip id is 1 */
cid = 1;
break;
case CHIPID_TEGRA124:
/* T12x chip id is 3 */
cid = 3;
break;
case CHIPID_TEGRA210:
/* T210 chip id is 5 */
cid = 5;
default:
return 0;
}
vendor = tegra_fuse_readl(FUSE_VENDOR_CODE) & FUSE_VENDOR_CODE_MASK;
fab = tegra_fuse_readl(FUSE_FAB_CODE) & FUSE_FAB_CODE_MASK;
/* Lot code must be re-encoded from a 5 digit base-36 'BCD' number
to a binary number. */
lot = 0;
reg = tegra_fuse_readl(FUSE_LOT_CODE_0) << 2;
for (i = 0; i < 5; ++i) {
u32 digit = (reg & 0xFC000000) >> 26;
lot *= 36;
lot += digit;
reg <<= 6;
}
wafer = tegra_fuse_readl(FUSE_WAFER_ID) & FUSE_WAFER_ID_MASK;
x = tegra_fuse_readl(FUSE_X_COORDINATE) & FUSE_X_COORDINATE_MASK;
y = tegra_fuse_readl(FUSE_Y_COORDINATE) & FUSE_Y_COORDINATE_MASK;
uid = ((unsigned long long)cid << 60ull)
| ((unsigned long long)vendor << 56ull)
| ((unsigned long long)fab << 50ull)
| ((unsigned long long)lot << 24ull)
| ((unsigned long long)wafer << 18ull)
| ((unsigned long long)x << 9ull)
| ((unsigned long long)y << 0ull);
return uid;
}

View File

@@ -20,10 +20,26 @@ config TARGET_COLIBRI_T30
bool "Toradex Colibri T30 board"
select BOARD_LATE_INIT
config TARGET_ENDEAVORU
bool "HTC Endeavoru T30 board"
select BOARD_LATE_INIT
config TARGET_GROUPER
bool "Asus and Google Grouper board"
select BOARD_LATE_INIT
config TARGET_TEC_NG
bool "Avionic Design TEC-NG board"
select BOARD_LATE_INIT
config TARGET_TRANSFORMER_T30
bool "Asus Tegra30 Transformer board"
select BOARD_LATE_INIT
config TARGET_X3_T30
bool "LG X3 Tegra30 board"
select BOARD_LATE_INIT
endchoice
config SYS_SOC
@@ -33,6 +49,10 @@ source "board/toradex/apalis_t30/Kconfig"
source "board/nvidia/beaver/Kconfig"
source "board/nvidia/cardhu/Kconfig"
source "board/toradex/colibri_t30/Kconfig"
source "board/htc/endeavoru/Kconfig"
source "board/asus/grouper/Kconfig"
source "board/avionic-design/tec-ng/Kconfig"
source "board/asus/transformer-t30/Kconfig"
source "board/lg/x3-t30/Kconfig"
endif

View File

@@ -76,7 +76,7 @@ void board_init_f(ulong dummy)
}
#endif /* CONFIG_SPL_BUILD */
phys_size_t board_get_usable_ram_top(phys_size_t total_size)
phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
return CFG_SYS_SDRAM_BASE + (256 * 1024 * 1024);
}

View File

@@ -77,7 +77,7 @@ phys_size_t get_effective_memsize(void)
return UBOOT_RAM_SIZE_MAX;
}
phys_size_t board_get_usable_ram_top(phys_size_t total_size)
phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
if (IS_ENABLED(CONFIG_RAM_OCTEON)) {
/* Map a maximum of 256MiB - return not size but address */

View File

@@ -26,6 +26,7 @@ config TARGET_SIFIVE_UNMATCHED
config TARGET_STARFIVE_VISIONFIVE2
bool "Support StarFive VisionFive2 Board"
select BOARD_LATE_INIT
config TARGET_TH1520_LPI4A
bool "Support Sipeed's TH1520 Lichee PI 4A Board"
@@ -64,6 +65,14 @@ config SPL_SYS_DCACHE_OFF
help
Do not enable data cache in SPL.
config SPL_ZERO_MEM_BEFORE_USE
bool "Zero memory before use"
depends on SPL
default n
help
Zero stack/GD/malloc area in SPL before using them, this is needed for
Sifive core devices that uses L2 cache to store SPL.
# board-specific options below
source "board/AndesTech/ae350/Kconfig"
source "board/emulation/qemu-riscv/Kconfig"

View File

@@ -66,7 +66,7 @@ static inline bool supports_extension(char ext)
#endif /* CONFIG_CPU */
}
static int riscv_cpu_probe(void)
static int riscv_cpu_probe(void *ctx, struct event *event)
{
#ifdef CONFIG_CPU
int ret;
@@ -79,6 +79,7 @@ static int riscv_cpu_probe(void)
return 0;
}
EVENT_SPY(EVT_DM_POST_INIT_R, riscv_cpu_probe);
/*
* This is called on secondary harts just after the IPI is init'd. Currently
@@ -95,7 +96,7 @@ int riscv_cpu_setup(void *ctx, struct event *event)
{
int ret;
ret = riscv_cpu_probe();
ret = riscv_cpu_probe(ctx, event);
if (ret)
return ret;
@@ -149,12 +150,6 @@ EVENT_SPY(EVT_DM_POST_INIT_F, riscv_cpu_setup);
int arch_early_init_r(void)
{
int ret;
ret = riscv_cpu_probe();
if (ret)
return ret;
if (IS_ENABLED(CONFIG_SYSRESET_SBI))
device_bind_driver(gd->dm_root, "sbi-sysreset",
"sbi-sysreset", NULL);

View File

@@ -21,7 +21,7 @@ int dram_init_banksize(void)
return fdtdec_setup_memory_banksize();
}
phys_size_t board_get_usable_ram_top(phys_size_t total_size)
phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
/*
* Ensure that we run from first 4GB so that all

View File

@@ -20,7 +20,7 @@ int dram_init_banksize(void)
return fdtdec_setup_memory_banksize();
}
phys_size_t board_get_usable_ram_top(phys_size_t total_size)
phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
#ifdef CONFIG_64BIT
/*

View File

@@ -21,7 +21,7 @@ int dram_init_banksize(void)
return fdtdec_setup_memory_banksize();
}
phys_size_t board_get_usable_ram_top(phys_size_t total_size)
phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
/*
* Ensure that we run from first 4GB so that all

View File

@@ -13,6 +13,8 @@ config STARFIVE_JH7110
select SUPPORT_SPL
select SPL_RAM if SPL
select SPL_STARFIVE_DDR
select SYS_CACHE_SHIFT_6
select SPL_ZERO_MEM_BEFORE_USE
select PINCTRL_STARFIVE_JH7110
imply MMC
imply MMC_BROKEN_CD
@@ -26,3 +28,4 @@ config STARFIVE_JH7110
imply SPL_LOAD_FIT
imply SPL_OPENSBI
imply SPL_RISCV_ACLINT
imply SPL_SYS_MALLOC_CLEAR_ON_INIT

View File

@@ -21,7 +21,7 @@ int dram_init_banksize(void)
return fdtdec_setup_memory_banksize();
}
phys_size_t board_get_usable_ram_top(phys_size_t total_size)
phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
/*
* Ensure that we run from first 4GB so that all

View File

@@ -13,7 +13,6 @@
#include <init.h>
#define CSR_U74_FEATURE_DISABLE 0x7c1
#define L2_LIM_MEM_END 0x81FFFFFUL
DECLARE_GLOBAL_DATA_PTR;
@@ -59,9 +58,6 @@ int spl_soc_init(void)
void harts_early_init(void)
{
ulong *ptr;
u8 *tmp;
ulong len, remain;
/*
* Feature Disable CSR
*
@@ -70,25 +66,4 @@ void harts_early_init(void)
*/
if (CONFIG_IS_ENABLED(RISCV_MMODE))
csr_write(CSR_U74_FEATURE_DISABLE, 0);
/* clear L2 LIM memory
* set __bss_end to 0x81FFFFF region to zero
* The L2 Cache Controller supports ECC. ECC is applied to SRAM.
* If it is not cleared, the ECC part is invalid, and an ECC error
* will be reported when reading data.
*/
ptr = (ulong *)&__bss_end;
len = L2_LIM_MEM_END - (ulong)&__bss_end;
remain = len % sizeof(ulong);
len /= sizeof(ulong);
while (len--)
*ptr++ = 0;
/* clear the remain bytes */
if (remain) {
tmp = (u8 *)ptr;
while (remain--)
*tmp++ = 0;
}
}

View File

@@ -111,6 +111,18 @@ call_board_init_f:
* It's essential before any function call, otherwise, we get data-race.
*/
/* clear stack if necessary */
#if CONFIG_IS_ENABLED(ZERO_MEM_BEFORE_USE)
clear_stack:
li t1, 1
slli t1, t1, CONFIG_STACK_SIZE_SHIFT
sub t1, sp, t1
clear_stack_loop:
SREG zero, 0(t1) /* t1 is always 16 byte aligned */
addi t1, t1, REGBYTES
blt t1, sp, clear_stack_loop
#endif
call_board_init_f_0:
/* find top of reserve space */
#if CONFIG_IS_ENABLED(SMP)

View File

@@ -311,7 +311,7 @@
&pcie0 {
reset-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>;
status = "disabled";
status = "okay";
};
&pcie1 {

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