Commit Graph

28120 Commits

Author SHA1 Message Date
Macpaul Lin
041364141b scsi: Adjust SCSI inquiry command data length
Per the SCSI SPC-4 specification, the standard inquiry data length
should not be less than 36 bytes. The current implementation uses 512
bytes, which causes detection failures on some UFS devices (e.g.,
Longsys) that do not expect a transfer length exceeding the standard
inquiry size.

Align the default standard inquiry length with the Linux kernel's
implementation (see drivers/scsi/scsi_scan.c), which uses 36 bytes as
the default. Devices requiring vendor-specific inquiry lengths should
be handled through quirk settings in the future.

Signed-off-by: ht.lin <ht.lin@mediatek.com>
Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
Reviewed-by: Marek Vasut <marek.vasut@mailbox.org>
2026-03-16 10:39:26 -06:00
Tom Rini
841856ed96 Merge patch series "Add PCIe Boot support for TI J784S4 SoC"
Siddharth Vadapalli <s-vadapalli@ti.com> says:

This series adds PCIe endpoint boot support for the TI J784S4 SoC.
Series is based on commit f9ffeec4bd ("board: toradex: Make A53 get RAM
size from DT in K3 boards") of the master branch of U-Boot.

PCIe Boot Logs (J784S4-EVM running Linux as Root-Complex transfers
bootloaders to another J784S4-EVM configured for PCIe Boot):
https://gist.github.com/Siddharth-Vadapalli-at-TI/2d157003818441fe79a139d0dec1058a

Link: https://lore.kernel.org/r/20260216102858.2745657-1-s-vadapalli@ti.com
2026-03-16 08:24:18 -06:00
Hrushikesh Salunke
35e1083fb9 phy: ti: Add config to enable J721E WIZ SERDES wrapper at SPL stage
Add SPL_PHY_J721E_WIZ configuration option to enable the WIZ SERDES
wrapper driver in SPL stage. This is required for PCIe boot support
where SERDES configuration must be done early in the boot sequence
before loading the bootloader image over PCIe.

Signed-off-by: Hrushikesh Salunke <h-salunke@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
2026-03-16 08:24:04 -06:00
Hrushikesh Salunke
2a21f48771 phy: cadence: Add config to enable Cadence Torrent PHY at SPL stage
Add SPL_PHY_CADENCE_TORRENT configuration option to enable the Cadence
Torrent PHY driver in SPL stage. This is required for PCIe boot support
where SERDES configuration must be done early in the boot sequence
before loading the bootloader image over PCIe.

Signed-off-by: Hrushikesh Salunke <h-salunke@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
2026-03-16 08:24:03 -06:00
Tom Rini
071e914b4a Merge tag 'u-boot-dfu-20260316' of https://source.denx.de/u-boot/custodians/u-boot-dfu into next
u-boot-dfu-20260316

DFU:
* Make DFU_WRITE_ALT symbol available outside of DFU
* Fix PCI subclass_code warning in spl_dfu

Usb Gadget:
* Mark udc_disconnect() as static
2026-03-16 08:22:58 -06:00
Tom Rini
4b77b07811 dfu: Make the DFU_WRITE_ALT symbol available outside of DFU
The DFU_WRITE_ALT symbol is used both directly and indirectly (via
UPDATE_COMMON) for EFI capsule updates (FIT or raw), but does not depend
on DFU itself. Move this symbol outside of "if DFU" to remove a Kconfig
dependency problem.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Link: https://lore.kernel.org/r/20260310162621.1163932-1-trini@konsulko.com
Signed-off-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
2026-03-16 10:38:47 +01:00
Tom Rini
e298a3faa3 Merge patch series "Minor fixes for the k3_fuse driver"
Anshul Dalal <anshuld@ti.com> says:

This series adds some minor *non-critical* fixes to the k3_fuse misc
driver in U-Boot.

Link: https://lore.kernel.org/r/20260226-k3_fuse_fixes-v1-0-86c81c298bc5@ti.com
2026-03-13 14:58:33 -06:00
Vignesh Raghavendra
34c7bcacfa misc: k3_fuse: Limit writes to 25bit values
K3 OTP bits can only be programmed 25bits at a time. Limit the value
accordingly using a 25 bit mask.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Anshul Dalal <anshuld@ti.com>
2026-03-13 14:58:27 -06:00
Vignesh Raghavendra
b533d457ae misc: k3_fuse: Enable fuse Sense support
fuse sense is essentially read, map it to fuse read.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Anshul Dalal <anshuld@ti.com>
2026-03-13 14:58:27 -06:00
Vignesh Raghavendra
494782b6e0 misc: k3_fuse: Check readback on fuse prog
Error out if readback value doesn't match the programmed value.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Anshul Dalal <anshuld@ti.com>
2026-03-13 14:58:27 -06:00
Vignesh Raghavendra
e98e9b1ec9 misc: k3_fuse: Fix printing of error codes
Use signed int format to print error codes so that its more readable

Fixes: ed5f2e5bed ("drivers: k3_fuse: Add fuse sub-system func calls")
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Anshul Dalal <anshuld@ti.com>
2026-03-13 14:58:27 -06:00
Nikita Shubin
660d8e4fe9 serial: ns16550: Fix return-type warning
Fix compiler warning:

drivers/serial/ns16550.c: In function ‘serial_in_dynamic’:
drivers/serial/ns16550.c:153:1: warning: control reaches end
    of non-void function [-Wreturn-type]
  153 | }
      | ^

Observed with gcc 15.2.1:

$ riscv64-unknown-linux-gnu-gcc --version
riscv64-unknown-linux-gnu-gcc (Gentoo 15.2.1_p20260214 p5) 15.2.1

Fixes: 62cbde4c4e ("serial: ns16550: Support run-time configuration")
Signed-off-by: Nikita Shubin <nikita.shubin@maquefel.me>
Reviewed-by: Tom Rini <trini@konsulko.com>
2026-03-13 13:21:59 -06:00
Tom Rini
dba21bf0b6 Merge tag 'u-boot-ufs-20260313' of https://source.denx.de/u-boot/custodians/u-boot-ufs into next
- ufs_hba_ops callbacks cleanup
- Rockchip UFS reset support
- UFS support in SPL
2026-03-13 10:52:03 -06:00
Tom Rini
2f52473884 Merge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-riscv into next
CI: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/29497
- sifive: switch to OF_UPSTREAM
- driver: cache: Remove SiFive PL2 driver
- riscv: fixes for non-existent CONFIG
2026-03-13 10:52:03 -06:00
Tom Rini
6dc75d440d Merge tag 'net-20260312' of https://source.denx.de/u-boot/custodians/u-boot-net into next
Pull request net-20260312.

net:
- Move network PHY under NETDEVICES
- s/DM_CLK/CLK/ in HIFEMAC_{ETH,MDIO}
- Add support for Airoha AN8811HB PHY
- airoha: PCS and MDIO support for Airoha AN7581 SoC

net-lwip:
- Fix issue when TFTP blocksize is >8192
- Adjust PBUF_POOL_SIZE/IP_REASS_MAX_PBUFS for better performance and
  resource usage.
- Enable mii command for NET_LWIP
2026-03-13 10:52:03 -06:00
Tom Rini
a5fcbd5a83 net: Move network PHY under NETDEVICES
A number of network PHY drivers have Kconfig dependencies on various
network drivers under NETDEVICES. This is in addition to logical
dependencies of network PHYs needing network drivers. Resolve the
Kconfig problems by moving the network PHY lines to be after the network
devices, within the overall NETDEVICES guard.

Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Jerome Forissier <jerome.forissier@arm.com>
2026-03-13 10:52:02 -06:00
Heinrich Schuchardt
1939a7f7fb net: do not use non-existent CONFIG_DM_CLK
For enabling the clock driver we use symbol CONFIG_CLK.
Select this symbol for the HiSilicon Fast Ethernet Controller driver.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
2026-03-13 10:52:02 -06:00
Tommy Shih
2a8bb06ff5 net: phy: air_en8811: add support for Airoha AN8811HB PHY
Add support for the Airoha AN8811HB 2.5 Gigabit PHY to the existing
en8811h driver. This PHY supports 10/100/1000/2500 Mbps speeds.

Update the driver to recognize the AN8811HB PHY ID and handle its
specific firmware loading requirements. The firmware loading mechanism
remains consistent with the existing implementation.

This driver is based on:
  - Linux upstream PHY subsystem (v7.0-rc1)
  - air_an8811hb v0.0.4 out-of-tree uboot driver written by
    "Lucien.Jheng <lucien.jheng@airoha.com>"

Tested on MT7987 RFB board.

Link: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=6f1769ec5892ac41d82e820d94dcdc68e904aa99
Link: https://patchwork.kernel.org/project/netdevbpf/patch/20260122071601.1057083-3-bjorn@mork.no/
Signed-off-by: Tommy Shih <tommy.shih@airoha.com>
Reviewed-by: Lucien.Jheng <lucienzx159@gmail.com>
2026-03-13 10:51:46 -06:00
Nick Hu
61e2430360 driver: cache: Remove SiFive PL2 driver
Under single core boot platform, the secondary cores won't enter the
u-boot spl. Therefore we move the pl2 driver from u-boot to the Opensbi.

Signed-off-by: Nick Hu <nick.hu@sifive.com>
Signed-off-by: Jimmy Ho <jimmy.ho@sifive.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2026-03-13 02:57:15 +08:00
Andreas Schwab
4dcff3b572 sifive: switch to OF_UPSTREAM
Tested on HiFive Unleashed and HiFive Unmatched, both SPIFlash and MMC boot.

Signed-off-by: Andreas Schwab <schwab@suse.de>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2026-03-13 02:56:52 +08:00
Mikhail Kshevetskiy
96d9e7c464 net: airoha: use mt7531 mdio for GDM1
Current code just bind mt7531 mdio with it's driver, so mdio device may
not be probed and hense not usable.

This patch:
 * Forces probing of mt7531 mdio for GDM1 port
 * Renames the mt7531 mdio bus interface to 'mt7531-mdio'. We may have
   multiple available MDIO, so the name 'mdio' isn't descriptive enough.
 * Sets mdio bus for the GDM port device

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
2026-03-12 15:53:41 +01:00
Mikhail Kshevetskiy
08fa7baad5 net: airoha: makes PCS support optional
It's not possible to disable PCS support just now, an7581 u-boot will not
compile. This patch fixes an issue.

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
2026-03-12 15:53:41 +01:00
Christian Marangi
a527b11051 net: airoha: fill in support for PCS/PHY in Airoha Ethernet driver
Add required changes to call PCS function to configure the Serdes Port.
The Ethernet driver is adapted following Upstream Kernel node structure.

Function calling order is the same of Phylink upstream kernel.

With the PCS support, also add support for attaching PHY. With
"in-band-status" set in DT for the managed property, a rudimental
support for SFP module is present.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2026-03-12 15:53:41 +01:00
Mikhail Kshevetskiy
2a7f69203f net: airoha-pcs: an7581: sync with linux code a bit
based on linux kernel patches from
https://github.com/Ansuel/openwrt/commits/openwrt-24.10-airoha-an7581-stable/
created by Christian Marangi <ansuelsmth@gmail.com>

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
2026-03-12 15:53:41 +01:00
Tom Rini
9f1059bc73 Merge tag 'mediatek-for-next-2026-03-11' of https://source.denx.de/u-boot/custodians/u-boot-mediatek into next
A fix:
* Fixing compiling MT8195 due to some independent changes that were applied
  around the same time as MT8195 support was merged. (CI would not have caught
  this since we didn't have a defconfig until now).

And few small features:
* New defconfig for MT8395/Genio 1200 EVK.
* pinctrl support for MT8189-compatible SoCs.
2026-03-12 07:45:29 -06:00
Mikhail Kshevetskiy
5b6b5d6f0b net: airoha: pcs: improve/fix building rules
pcs-airoha-common.o should not build unconditionally,
also make building rules looks better.

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
2026-03-12 12:49:35 +01:00
Christian Marangi
d4dd6eb29b net: airoha: add support for Airoha PCS driver
Add support for Airoha PCS driver present on AN7581 SoC.
This is needed to configure the Serdes port for the different PHY mode.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2026-03-12 12:49:35 +01:00
Mikhail Kshevetskiy
794c30b9d8 net: airoha: init switch before GDM port initialization
Call airoha_switch_init() before creating GDM instances, so if
allocation of GDM port fails, early created GDM instances will work
normally.

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
2026-03-12 12:49:35 +01:00
Mikhail Kshevetskiy
b4029a4049 net: airoha: do not call airoha_fe_init() from GDM port independent code
We should not call airoha_fe_init() from GDM port independent code,
because it do a GDM specific things.

Makes airoha_fe_maccr_init() and airoha_fe_init() port dependent
and call them from airoha_eth_port_probe()

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
2026-03-12 12:49:35 +01:00
Mikhail Kshevetskiy
be0c12296e net: airoha: declare airoha_eth_port as U_BOOT_DRIVER()
Declare airoha_eth_port as U_BOOT_DRIVER(), fix airoha_alloc_gdm_port()
to lookup a driver instead of direct airoha_eth_port usage.

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
2026-03-12 12:49:35 +01:00
Mikhail Kshevetskiy
7ad4c7f8cf net: airoha: avoid out of boundary writing/access to gdm_port_str[] array
In the case of an7581 possible GDM port id are: 1, 2 and 4.
Initialization of port GDM4 will lead to out of boundary writing
to gdm_port_str[] array.

Let's increase the array size by 1 to avoid it.

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
2026-03-12 12:49:35 +01:00
Christian Marangi
0561b0b25a net: airoha: add initial support for multiple GDM port
Rework the driver to support multiple GDM port. The driver is split to
main driver as a MISC driver with forced probe (by using the
DM_FLAG_PROBE_AFTER_BIND) and each GDM port register a ETH driver.

This permit a 1:1 implementation with the linux kernel driver and permit
to use the same exact DT nodes.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2026-03-12 12:49:35 +01:00
Christian Marangi
abd1efa992 net: mdio-mt7531-mmio: use common header priv struct
Instead of having duplicate priv struct for mdio-mt7531-mmio driver in
both driver and header, use the one exposed by the header directly.

This make sure we have consistent priv struct if the driver will be
updated in the future.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2026-03-12 12:49:35 +01:00
Alexey Charkov
67d8731d4a ufs: rockchip: Add device reset support
Wire up the GPIO line which Rockchip RK3576 UFS controller uses to reset
the connected UFS device.

This seems necessary at least for some UFS modules and fixes the following
error while enumerating UFS storage:

ufshcd-rockchip ufshc@2a2d0000: ufshcd_link_startup: Device not present
ufshcd-rockchip ufshc@2a2d0000: link startup failed -6
ufshcd-rockchip ufshc@2a2d0000: ufshcd_pltfrm_init() failed -6

Note that the GPIO descriptor for device resets is already required by the
DT binding (link enclosed).

Link: https://elixir.bootlin.com/linux/v6.18.5/source/Documentation/devicetree/bindings/ufs/rockchip,rk3576-ufshc.yaml#L70
Fixes: 76465ce21e ("ufs: rockchip: Add initial support")
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Alexey Charkov <alchark@gmail.com>
Link: https://patch.msgid.link/20260120-rk3576-ufs-v5-3-0edb61b301b7@gmail.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2026-03-12 09:30:44 +01:00
Alexey Charkov
c664b4d5f3 spl: Make UFS available for SPL builds
Add minimal infrastructure to build SPL images with support for UFS
storage devices. This also pulls in SCSI support and charset functions,
which are dependencies of the UFS code.

With this, only a fixed offset is supported for loading the next image,
which should be specified in CONFIG_SPL_UFS_RAW_U_BOOT_SECTOR as the
number of 4096-byte sectors into the UFS block device.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Alexey Charkov <alchark@gmail.com>
Link: https://patch.msgid.link/20260120-rk3576-ufs-v5-1-0edb61b301b7@gmail.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2026-03-12 09:30:44 +01:00
Bo-Chen Chen
05677fedd6 pinctrl: mediatek: add support for mt8189
Add pinctrl support for mt8189.

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Co-developed-by: David Lechner <dlechner@baylibre.com>
Reviewed-by: Macpaul Lin <macpaul.lin@mediatek.com>
Link: https://patch.msgid.link/20260209-mtk-pinctl-mt8189-v1-3-a7a3069eda6c@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
2026-03-11 10:44:27 -05:00
David Lechner
920b0bc608 pinctl: mediatek: increase max number of base addresses
Increase the maximum number of base addresses that can be handled by the
mediatek pinctrl driver from 10 to 15. This is needed for the MT8189
which has 15 base addresses.

Reviewed-by: Macpaul Lin <macpaul.lin@mediatek.com>
Link: https://patch.msgid.link/20260209-mtk-pinctl-mt8189-v1-2-a7a3069eda6c@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
2026-03-11 10:42:03 -05:00
David Lechner
64d48d21b5 pinctl: mediatek: add bounds check on number of base addresses
Add a bounds check on the number of base addresses to prevent
out-of-bounds access to the priv->base array.

Reviewed-by: Macpaul Lin <macpaul.lin@mediatek.com>
Link: https://patch.msgid.link/20260209-mtk-pinctl-mt8189-v1-1-a7a3069eda6c@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
2026-03-11 10:42:03 -05:00
Heinrich Schuchardt
65b776e6d2 dma: ti: don't use non-existent CONFIG_TI_K3_NAVSS_PSILCFG
Symbol CONFIG_TI_K3_NAVSS_PSILCFG does not exist.
Don't select it.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2026-03-10 12:35:02 -06:00
Tom Rini
d93a63acfe Merge tag 'u-boot-rockchip-20260309' of https://source.denx.de/u-boot/custodians/u-boot-rockchip into next
CI: https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/pipelines/29452

- New SoC support: RK3506, RK3582;
- New Board support: RK3528 FriendlyElec NanoPi Zero2;
- Other fixes
2026-03-10 10:07:04 -06:00
Jonas Karlman
52877548d3 arch: arm: rockchip: Add initial support for RK3506
Rockchip RK3506 is a ARM-based SoC with tri-core Cortex-A7.

Add initial arch support for the RK3506 SoC.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Acked-by: Mattijs Korpershoek <mkorpershoek@kernel.org> # drivers/usb/gadget
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2026-03-10 10:07:03 -06:00
Jonas Karlman
5b5616f846 net: dwc_eth_qos_rockchip: Add support for RK3506
Rockchip RK3506 has two Ethernet controllers based on Synopsys DWC
Ethernet QoS IP.

Add initial support for the RK3506 GMAC variant.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2026-03-10 10:07:03 -06:00
Jonas Karlman
7404646f03 phy: rockchip-inno-usb2: Add support for RK3506
Add support for the two USB2.0 PHYs use in the RK3506 SoC.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Tested-by: Aaron Griffith <aargri@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2026-03-10 10:07:03 -06:00
Jonas Karlman
5bc966054f rockchip: otp: Add support for RK3506
Add support for the OTP controller in RK3506. The OTPC is similar to the
OTPC in RK3568 and can use the same ops for reading OTP data.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2026-03-10 10:07:03 -06:00
Ye Zhang
6225eeff57 pinctrl: rockchip: Add support for RK3506
Add pinctrl driver for RK3506.

Imported from vendor U-Boot linux-6.1-stan-rkr6 tag with adjustments
to use regmap_update_bits().

Signed-off-by: Ye Zhang <ye.zhang@rock-chips.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Tested-by: Aaron Griffith <aargri@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2026-03-10 10:07:03 -06:00
Jonas Karlman
ea45ebafd8 pinctrl: rockchip: Use syscon_regmap_lookup_by_phandle()
Use syscon_regmap_lookup_by_phandle() to simplify the code.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
2026-03-10 10:07:03 -06:00
Finley Xiao
fbf72dce91 clk: rockchip: Add support for RK3506
Add clock driver for RK3506.

Imported from vendor U-Boot linux-6.1-stan-rkr6 tag with minor
adjustments and fixes for mainline.

Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2026-03-10 10:07:03 -06:00
Jonas Karlman
05b8228648 ram: rockchip: Add basic support for RK3506
Add support for reading DRAM size information from PMUGRF os_reg2 reg.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Tested-by: Aaron Griffith <aargri@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2026-03-10 10:07:03 -06:00
Tom Rini
1e240f7206 Merge tag 'v2026.04-rc4' into next
Prepare v2026.04-rc4
2026-03-09 15:26:34 -06:00
Tom Rini
532a4804e9 Merge patch series "64-bit PCIe for AM64, AM69, J7200, J722S and J784S4"
Siddharth Vadapalli <s-vadapalli@ti.com> says:

Since Linux device-tree has switched to 64-bit Address space for the
PCIe Controllers on TI SoCs, currently, U-Boot needs to support the
same. This series adds support for 64-bit addressing for PCIe along with
enabling Root-Complex mode of operation for AM69 and J784S4 SoCs.

Series has been tested on all platforms being affected by this series.
Test Logs:
1. AM642-EVM
https://gist.github.com/Siddharth-Vadapalli-at-TI/82512389f8396a51e4f167c7ebe4c2a3
2. AM69-SK
https://gist.github.com/Siddharth-Vadapalli-at-TI/b20b2811804ffc6e6c063564330c0a35
3. J7200-EVM
https://gist.github.com/Siddharth-Vadapalli-at-TI/c545da68bd28a5e036803bb60f32d8e9
4. J722S-EVM
https://gist.github.com/Siddharth-Vadapalli-at-TI/3dde05c4c7076076aa20ac47a6e2d176
5. J784S4-EVM
https://gist.github.com/Siddharth-Vadapalli-at-TI/a93c1b2cd5d90f494e885d1831d3d23e

Link: https://lore.kernel.org/r/20260227115841.333073-1-s-vadapalli@ti.com
2026-03-09 09:35:51 -06:00