Merge patch series "configs: imx95: enable PCI_INIT_R for Toradex modules"

Franz Schnyder <fra.schnyder@gmail.com> says:

Currently, on the Toradex SMARC iMX95 and the Verdin iMX95 the ENETC
device is not enumerated before network initialization because
pci_init() is not called. As a result, no Ethernet device is registered.

Enable CONFIG_PCI_INIT_R so the PCI buses are enumerated early enough
for the Ethernet Controller to be detected and used.

Link: https://lore.kernel.org/r/20260612-fix-smarc-verdin-imx95-eth-v1-0-851197b36dcc@toradex.com

.gitignore

@@ -80,7 +80,7 @@ fit-dtb.blob*
 /*imx8mimage*
 /*imx8mcst*
 /*rcar4-sa0*
-/drivers/video/u_boot_logo.S
+/drivers/video/u_boot_logo.bmp.S
 /test/fdt_overlay/test-fdt-overlay-stacked.dtbo.S
 /test/fdt_overlay/test-fdt-overlay.dtbo.S
 capsule_esl_file

.gitlab-ci-sage-lab.yml

@@ -26,7 +26,7 @@
       . /tmp/venv/bin/activate;
       pip install -r test/py/requirements.txt -r tools/binman/requirements.txt
         -r tools/buildman/requirements.txt -r tools/u_boot_pylib/requirements.txt
-        labgrid setuptools
+        labgrid==25.0.1 setuptools
     # Acquire and turn on the exporter.
     - labgrid-client reserve --wait board=${LABGRID_EXPORTER} &&
       labgrid-client -p ${LABGRID_EXPORTER} acquire &&
@@ -153,20 +153,13 @@ Raspberry Pi 4 (rpi_arm64):
     LABGRID_EXPORTER: "sage-exporter-rpi4-1"
     LG_PLACE: "rpi4-1"
     TEST_PY_BD: "rpi_arm64"
-    OVERRIDE: "-a UNIT_TEST -a ~CMD_EFIDEBUG -a CMD_BOOTMENU -a CMD_LOG -a ~CMD_BOOTEFI_SELFTEST -a CMD_TFTPPUT -a FIT -a FIT_SIGNATURE -a FIT_BEST_MATCH -a SYS_BOOTM_LEN=0x4000000 -a BOOTSTAGE -a BOOTSTAGE_STASH -a CMD_BOOTSTAGE -a BOOTSTAGE_STASH_ADDR=0x02400000"
-
-Raspberry Pi 4 (rpi_arm64, lwIP):
-  <<: *sage_lab_dfn
-  needs: [ "Raspberry Pi 4 (rpi_arm64)" ]
-  variables:
-    LABGRID_EXPORTER: "sage-exporter-rpi4-1"
-    LG_PLACE: "rpi4-1"
-    TEST_PY_BD: "rpi_arm64"
-    OVERRIDE: "-a UNIT_TEST -a ~CMD_EFIDEBUG -a CMD_BOOTMENU -a CMD_LOG -a ~CMD_BOOTEFI_SELFTEST -a FIT -a FIT_SIGNATURE -a FIT_BEST_MATCH -a SYS_BOOTM_LEN=0x4000000 -a BOOTSTAGE -a BOOTSTAGE_STASH -a CMD_BOOTSTAGE -a BOOTSTAGE_STASH_ADDR=0x02400000 -a NET_LWIP"
+    # DHCP is not being run first, needs to be investigated.
+    TEST_PY_TEST_SPEC: "not test_efi_helloworld_net_http"
+    OVERRIDE: "-a UNIT_TEST -a ~CMD_EFIDEBUG -a CMD_BOOTMENU -a CMD_LOG -a ~CMD_BOOTEFI_SELFTEST -a FIT -a FIT_SIGNATURE -a FIT_BEST_MATCH -a SYS_BOOTM_LEN=0x4000000 -a BOOTSTAGE -a BOOTSTAGE_STASH -a CMD_BOOTSTAGE -a BOOTSTAGE_STASH_ADDR=0x02400000"
 
 Raspberry Pi 4 (rpi_4_32b):
   <<: *sage_lab_dfn
-  needs: [ "Raspberry Pi 4 (rpi_arm64, lwIP)" ]
+  needs: [ "Raspberry Pi 4 (rpi_arm64)" ]
   variables:
     LABGRID_EXPORTER: "sage-exporter-rpi4-1"
     LG_PLACE: "rpi4-1"
@@ -197,20 +190,13 @@ Raspberry Pi 3 (rpi_arm64):
     LABGRID_EXPORTER: "sage-exporter-rpi3-1"
     LG_PLACE: "rpi3-1"
     TEST_PY_BD: "rpi_arm64"
-    OVERRIDE: "-a UNIT_TEST -a ~CMD_EFIDEBUG -a CMD_BOOTMENU -a CMD_LOG -a ~CMD_BOOTEFI_SELFTEST -a CMD_TFTPPUT -a FIT -a FIT_SIGNATURE -a FIT_BEST_MATCH -a SYS_BOOTM_LEN=0x4000000 -a BOOTSTAGE -a BOOTSTAGE_STASH -a CMD_BOOTSTAGE -a BOOTSTAGE_STASH_ADDR=0x02400000"
-
-Raspberry Pi 3 (rpi_arm64, lwIP):
-  <<: *sage_lab_dfn
-  needs: [ "Raspberry Pi 3 (rpi_arm64)" ]
-  variables:
-    LABGRID_EXPORTER: "sage-exporter-rpi3-1"
-    LG_PLACE: "rpi3-1"
-    TEST_PY_BD: "rpi_arm64"
-    OVERRIDE: "-a UNIT_TEST -a ~CMD_EFIDEBUG -a CMD_BOOTMENU -a CMD_LOG -a ~CMD_BOOTEFI_SELFTEST -a FIT -a FIT_SIGNATURE -a FIT_BEST_MATCH -a SYS_BOOTM_LEN=0x4000000 -a BOOTSTAGE -a BOOTSTAGE_STASH -a CMD_BOOTSTAGE -a BOOTSTAGE_STASH_ADDR=0x02400000 -a NET_LWIP"
+    # DHCP is not being run first, needs to be investigated.
+    TEST_PY_TEST_SPEC: "not test_efi_helloworld_net_http"
+    OVERRIDE: "-a UNIT_TEST -a ~CMD_EFIDEBUG -a CMD_BOOTMENU -a CMD_LOG -a ~CMD_BOOTEFI_SELFTEST -a FIT -a FIT_SIGNATURE -a FIT_BEST_MATCH -a SYS_BOOTM_LEN=0x4000000 -a BOOTSTAGE -a BOOTSTAGE_STASH -a CMD_BOOTSTAGE -a BOOTSTAGE_STASH_ADDR=0x02400000"
 
 Raspberry Pi 3 (rpi_3_32b):
   <<: *sage_lab_dfn
-  needs: [ "Raspberry Pi 3 (rpi_arm64, lwIP)" ]
+  needs: [ "Raspberry Pi 3 (rpi_arm64)" ]
   variables:
     LABGRID_EXPORTER: "sage-exporter-rpi3-1"
     LG_PLACE: "rpi3-1"

Makefile

@@ -3,7 +3,7 @@
 VERSION = 2026
 PATCHLEVEL = 07
 SUBLEVEL =
-EXTRAVERSION = -rc3
+EXTRAVERSION = -rc4
 NAME =
 
 # *DOCUMENTATION*
@@ -920,7 +920,7 @@ endif
 ifdef CONFIG_CC_OPTIMIZE_FOR_SIZE
 KBUILD_CFLAGS	+= -Os
 else ifdef CONFIG_CC_OPTIMIZE_FOR_DEBUG
--KBUILD_CFLAGS  += -Og
+KBUILD_CFLAGS  += -Og
 # Avoid false positives -Wmaybe-uninitialized
 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78394
 KBUILD_CFLAGS  += -Wno-maybe-uninitialized
@@ -2544,7 +2544,7 @@ CLEAN_FILES  += $(MODVERDIR) \
 			$(filter-out include, $(shell ls -1 $d 2>/dev/null))))
 
 CLEAN_FILES += include/autoconf.mk* include/bmp_logo.h include/bmp_logo_data.h \
-	       include/config.h include/generated/env.* drivers/video/u_boot_logo.S \
+	       include/config.h include/generated/env.* drivers/video/u_boot_logo.bmp.S \
 	       tools/version.h u-boot* MLO* SPL System.map fit-dtb.blob* \
 	       u-boot-ivt.img.log u-boot-dtb.imx.log SPL.log u-boot.imx.log \
 	       lpc32xx-* bl31.c bl31.elf bl31_*.bin image.map tispl.bin* \

arch/arm/config.mk

@@ -112,6 +112,14 @@ endif
 # needed for relocation
 LDFLAGS_u-boot += -pie
 
+ifeq ($(CONFIG_ARM64),y)
+# U-Boot uses fixed 4K granules, so we force the linker to match.
+# Otherwise, we're subject to toolchain preferences, (e.g Fedora's
+# aarch64-linux-none toolchain selects 64K granules) and we end up wasting
+# a lot of space in ELFs with MMU_PGPROT enabled.
+LDFLAGS_u-boot += -z common-page-size=0x1000 -z max-page-size=0x1000
+endif
+
 #
 # FIXME: binutils versions < 2.22 have a bug in the assembler where
 # branches to weak symbols can be incorrectly optimized in thumb mode

arch/arm/dts/Makefile

@@ -45,12 +45,6 @@ dtb-$(CONFIG_MACH_S900) += \
 dtb-$(CONFIG_MACH_S700) += \
 	s700-cubieboard7.dtb
 
-dtb-$(CONFIG_ROCKCHIP_RK3128) += \
-	rk3128-evb.dtb
-
-dtb-$(CONFIG_ROCKCHIP_RK322X) += \
-	rk3229-evb.dtb
-
 dtb-$(CONFIG_ROCKCHIP_RK3368) += \
 	rk3368-sheep.dtb \
 	rk3368-geekbox.dtb \
@@ -899,6 +893,9 @@ dtb-$(CONFIG_RZA1) += \
 	r7s72100-genmai.dtb \
 	r7s72100-gr-peach.dtb
 
+dtb-$(CONFIG_RCAR_GEN3) += \
+	r8a779md-geist.dtb
+
 dtb-$(CONFIG_RCAR_GEN5) += \
 	r8a78000-ironhide-cm33.dtb
 

arch/arm/dts/imx8mm-u-boot.dtsi

@@ -50,14 +50,6 @@
 	section {
 		pad-byte = <0x00>;
 
-#ifdef CONFIG_FSPI_CONF_HEADER
-		fspi_conf_block {
-			filename = CONFIG_FSPI_CONF_FILE;
-			type = "blob-ext";
-			size = <0x1000>;
-		};
-#endif
-
 #ifdef CONFIG_IMX_HAB
 		nxp-imx8mcst@0 {
 			filename = "u-boot-spl-mkimage.signed.bin";
@@ -68,7 +60,12 @@
 
 			binman_imx_spl: nxp-imx8mimage {
 				filename = "u-boot-spl-mkimage.bin";
+#ifdef CONFIG_FSPI_CONF_HEADER
+				nxp,boot-from = "fspi";
+				nxp,fspi-header-filename = CONFIG_FSPI_CONF_FILE;
+#else
 				nxp,boot-from = "sd";
+#endif
 				nxp,rom-version = <1>;
 				nxp,loader-address = <CONFIG_SPL_TEXT_BASE>;
 				args;	/* Needed by mkimage etype superclass */

arch/arm/dts/imx8mn-u-boot.dtsi

@@ -104,14 +104,6 @@
 	section {
 		pad-byte = <0x00>;
 
-#ifdef CONFIG_FSPI_CONF_HEADER
-		fspi_conf_block {
-			filename = CONFIG_FSPI_CONF_FILE;
-			type = "blob-ext";
-			offset = <0x400>;
-		};
-#endif
-
 #ifdef CONFIG_IMX_HAB
 		nxp-imx8mcst@0 {
 			filename = "u-boot-spl-mkimage.signed.bin";
@@ -122,7 +114,12 @@
 
 			binman_imx_spl: nxp-imx8mimage {
 				filename = "u-boot-spl-mkimage.bin";
+#ifdef CONFIG_FSPI_CONF_HEADER
+				nxp,boot-from = "fspi";
+				nxp,fspi-header-filename = CONFIG_FSPI_CONF_FILE;
+#else
 				nxp,boot-from = "sd";
+#endif
 				nxp,rom-version = <2>;
 				nxp,loader-address = <CONFIG_SPL_TEXT_BASE>;
 				args;	/* Needed by mkimage etype superclass */

arch/arm/dts/ipq5424-rdp466-u-boot.dtsi

@@ -12,6 +12,9 @@
 		reg = <0x0 0x80000000 0x0 0x20000000>;
 	};
 
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
 };
 
 	&sdhc {

arch/arm/dts/k3-am68-sk-r5-base-board.dts

@@ -6,7 +6,7 @@
 /dts-v1/;
 
 #include "k3-am68-sk-base-board.dts"
-#include "k3-j721s2-ddr-evm-lp4-4266.dtsi"
+#include "k3-am68-ddr-sk-lp4-4266.dtsi"
 #include "k3-j721s2-ddr.dtsi"
 #include "k3-am68-sk-base-board-u-boot.dtsi"
 #include "k3-j721s2-r5.dtsi"

arch/arm/dts/k3-am69-r5-sk.dts

@@ -6,7 +6,7 @@
 /dts-v1/;
 
 #include "k3-am69-sk.dts"
-#include "k3-j784s4-ddr-evm-lp4-4266.dtsi"
+#include "k3-am69-ddr-sk-lp4-4266.dtsi"
 #include "k3-j784s4-ddr.dtsi"
 #include "k3-am69-sk-u-boot.dtsi"
 #include "k3-j784s4-r5.dtsi"

arch/arm/dts/k3-j7200-ddr-evm-lp4-3200.dtsi

@@ -1,14 +1,22 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
- * This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.6.0
- * This file was generated on 06/01/2021
+ * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
+ * This file was generated with the following tool revisions:
+ *     - SysConfig: Revision 1.25.0+4268
+ *     - Jacinto7_DDRSS_RegConfigTool: Revision 0.12.0
+ * This file was generated on Thu Oct 30 2025 13:11:41 GMT+0530 (India Standard Time)
 */
 
-#define DDRSS_PLL_FHS_CNT 10
+#define DDRSS_PLL_FHS_CNT 5
 #define DDRSS_PLL_FREQUENCY_0 27500000
-#define DDRSS_PLL_FREQUENCY_1 666500000
-#define DDRSS_PLL_FREQUENCY_2 666500000
+#define DDRSS_PLL_FREQUENCY_1 800000000
+#define DDRSS_PLL_FREQUENCY_2 800000000
+
+#define DDR_REG0_SIZE_MSB 0x00000000
+#define DDR_REG0_SIZE_LSB 0x80000000
+#define DDR_REG1_SIZE_MSB 0x00000000
+#define DDR_REG1_SIZE_LSB 0x80000000
+
 
 #define DDRSS_CTL_00_DATA 0x00000B00
 #define DDRSS_CTL_01_DATA 0x00000000
@@ -21,16 +29,16 @@
 #define DDRSS_CTL_08_DATA 0x0001ADAF
 #define DDRSS_CTL_09_DATA 0x00000005
 #define DDRSS_CTL_10_DATA 0x0000006E
-#define DDRSS_CTL_11_DATA 0x000411AB
-#define DDRSS_CTL_12_DATA 0x0028B0AB
+#define DDRSS_CTL_11_DATA 0x0004E200
+#define DDRSS_CTL_12_DATA 0x0030D400
 #define DDRSS_CTL_13_DATA 0x00000005
-#define DDRSS_CTL_14_DATA 0x00000A6B
-#define DDRSS_CTL_15_DATA 0x000411AB
-#define DDRSS_CTL_16_DATA 0x0028B0AB
+#define DDRSS_CTL_14_DATA 0x00000C80
+#define DDRSS_CTL_15_DATA 0x0004E200
+#define DDRSS_CTL_16_DATA 0x0030D400
 #define DDRSS_CTL_17_DATA 0x00000005
-#define DDRSS_CTL_18_DATA 0x00000A6B
+#define DDRSS_CTL_18_DATA 0x00000C80
 #define DDRSS_CTL_19_DATA 0x01010000
-#define DDRSS_CTL_20_DATA 0x02011001
+#define DDRSS_CTL_20_DATA 0x01011001
 #define DDRSS_CTL_21_DATA 0x02010000
 #define DDRSS_CTL_22_DATA 0x00020100
 #define DDRSS_CTL_23_DATA 0x0000000B
@@ -38,66 +46,66 @@
 #define DDRSS_CTL_25_DATA 0x00000000
 #define DDRSS_CTL_26_DATA 0x00000000
 #define DDRSS_CTL_27_DATA 0x03020200
-#define DDRSS_CTL_28_DATA 0x00003636
+#define DDRSS_CTL_28_DATA 0x00004040
 #define DDRSS_CTL_29_DATA 0x00100000
 #define DDRSS_CTL_30_DATA 0x00000000
 #define DDRSS_CTL_31_DATA 0x00000000
 #define DDRSS_CTL_32_DATA 0x00000000
 #define DDRSS_CTL_33_DATA 0x00000000
 #define DDRSS_CTL_34_DATA 0x040C0000
-#define DDRSS_CTL_35_DATA 0x0C300C30
+#define DDRSS_CTL_35_DATA 0x0E400E40
 #define DDRSS_CTL_36_DATA 0x00050804
 #define DDRSS_CTL_37_DATA 0x09040008
-#define DDRSS_CTL_38_DATA 0x0D000204
-#define DDRSS_CTL_39_DATA 0x113C0057
-#define DDRSS_CTL_40_DATA 0x0D00291B
-#define DDRSS_CTL_41_DATA 0x113C0057
-#define DDRSS_CTL_42_DATA 0x2000291B
+#define DDRSS_CTL_38_DATA 0x14000304
+#define DDRSS_CTL_39_DATA 0x15480068
+#define DDRSS_CTL_40_DATA 0x14004220
+#define DDRSS_CTL_41_DATA 0x15480068
+#define DDRSS_CTL_42_DATA 0x20004220
 #define DDRSS_CTL_43_DATA 0x000A0A09
-#define DDRSS_CTL_44_DATA 0x0400078A
-#define DDRSS_CTL_45_DATA 0x130E0B04
-#define DDRSS_CTL_46_DATA 0x0A00B6D0
-#define DDRSS_CTL_47_DATA 0x130E0B0A
-#define DDRSS_CTL_48_DATA 0x0A00B6D0
-#define DDRSS_CTL_49_DATA 0x0203040A
-#define DDRSS_CTL_50_DATA 0x1C040500
-#define DDRSS_CTL_51_DATA 0x081D1C1D
+#define DDRSS_CTL_44_DATA 0x040003C5
+#define DDRSS_CTL_45_DATA 0x17100D04
+#define DDRSS_CTL_46_DATA 0x0C006DB0
+#define DDRSS_CTL_47_DATA 0x17100D0C
+#define DDRSS_CTL_48_DATA 0x0C006DB0
+#define DDRSS_CTL_49_DATA 0x0203040C
+#define DDRSS_CTL_50_DATA 0x21060500
+#define DDRSS_CTL_51_DATA 0x08222122
 #define DDRSS_CTL_52_DATA 0x14000E0A
-#define DDRSS_CTL_53_DATA 0x02010A0A
-#define DDRSS_CTL_54_DATA 0x01010002
-#define DDRSS_CTL_55_DATA 0x04383808
-#define DDRSS_CTL_56_DATA 0x041F1F04
-#define DDRSS_CTL_57_DATA 0x00001F1F
+#define DDRSS_CTL_53_DATA 0x03010A0A
+#define DDRSS_CTL_54_DATA 0x01010003
+#define DDRSS_CTL_55_DATA 0x0442420A
+#define DDRSS_CTL_56_DATA 0x04252504
+#define DDRSS_CTL_57_DATA 0x00002525
 #define DDRSS_CTL_58_DATA 0x00010100
 #define DDRSS_CTL_59_DATA 0x03010000
 #define DDRSS_CTL_60_DATA 0x00001008
-#define DDRSS_CTL_61_DATA 0x000000CE
-#define DDRSS_CTL_62_DATA 0x00000176
-#define DDRSS_CTL_63_DATA 0x00001448
-#define DDRSS_CTL_64_DATA 0x00000176
-#define DDRSS_CTL_65_DATA 0x00001448
+#define DDRSS_CTL_61_DATA 0x00000068
+#define DDRSS_CTL_62_DATA 0x000001C0
+#define DDRSS_CTL_63_DATA 0x00000C28
+#define DDRSS_CTL_64_DATA 0x000001C0
+#define DDRSS_CTL_65_DATA 0x00000C28
 #define DDRSS_CTL_66_DATA 0x00000005
 #define DDRSS_CTL_67_DATA 0x00040000
-#define DDRSS_CTL_68_DATA 0x005D0012
-#define DDRSS_CTL_69_DATA 0x005D0282
-#define DDRSS_CTL_70_DATA 0x00400282
+#define DDRSS_CTL_68_DATA 0x00700005
+#define DDRSS_CTL_69_DATA 0x0070017E
+#define DDRSS_CTL_70_DATA 0x0040017E
 #define DDRSS_CTL_71_DATA 0x00120103
-#define DDRSS_CTL_72_DATA 0x000A0005
-#define DDRSS_CTL_73_DATA 0x1F08000A
-#define DDRSS_CTL_74_DATA 0x0505011F
+#define DDRSS_CTL_72_DATA 0x000C0005
+#define DDRSS_CTL_73_DATA 0x2408000C
+#define DDRSS_CTL_74_DATA 0x05050124
 #define DDRSS_CTL_75_DATA 0x0301030A
-#define DDRSS_CTL_76_DATA 0x03130A07
-#define DDRSS_CTL_77_DATA 0x0A070301
-#define DDRSS_CTL_78_DATA 0x00010313
+#define DDRSS_CTL_76_DATA 0x03170C08
+#define DDRSS_CTL_77_DATA 0x0C080301
+#define DDRSS_CTL_78_DATA 0x00010317
 #define DDRSS_CTL_79_DATA 0x00100010
-#define DDRSS_CTL_80_DATA 0x01800180
-#define DDRSS_CTL_81_DATA 0x01800180
+#define DDRSS_CTL_80_DATA 0x01CC01CC
+#define DDRSS_CTL_81_DATA 0x01CC01CC
 #define DDRSS_CTL_82_DATA 0x03050505
 #define DDRSS_CTL_83_DATA 0x03010303
-#define DDRSS_CTL_84_DATA 0x14070A07
-#define DDRSS_CTL_85_DATA 0x03030A03
-#define DDRSS_CTL_86_DATA 0x14070A07
-#define DDRSS_CTL_87_DATA 0x03030A03
+#define DDRSS_CTL_84_DATA 0x18080C08
+#define DDRSS_CTL_85_DATA 0x03030C03
+#define DDRSS_CTL_86_DATA 0x18080C08
+#define DDRSS_CTL_87_DATA 0x03030C03
 #define DDRSS_CTL_88_DATA 0x03010000
 #define DDRSS_CTL_89_DATA 0x00010000
 #define DDRSS_CTL_90_DATA 0x00000000
@@ -112,27 +120,27 @@
 #define DDRSS_CTL_99_DATA 0x00000000
 #define DDRSS_CTL_100_DATA 0x00040005
 #define DDRSS_CTL_101_DATA 0x00000000
-#define DDRSS_CTL_102_DATA 0x00003380
-#define DDRSS_CTL_103_DATA 0x00003380
-#define DDRSS_CTL_104_DATA 0x00003380
-#define DDRSS_CTL_105_DATA 0x00003380
-#define DDRSS_CTL_106_DATA 0x00003380
+#define DDRSS_CTL_102_DATA 0x000018C0
+#define DDRSS_CTL_103_DATA 0x000018C0
+#define DDRSS_CTL_104_DATA 0x000018C0
+#define DDRSS_CTL_105_DATA 0x000018C0
+#define DDRSS_CTL_106_DATA 0x000018C0
 #define DDRSS_CTL_107_DATA 0x00000000
-#define DDRSS_CTL_108_DATA 0x000005A2
-#define DDRSS_CTL_109_DATA 0x00051200
-#define DDRSS_CTL_110_DATA 0x00051200
-#define DDRSS_CTL_111_DATA 0x00051200
-#define DDRSS_CTL_112_DATA 0x00051200
-#define DDRSS_CTL_113_DATA 0x00051200
+#define DDRSS_CTL_108_DATA 0x000002B5
+#define DDRSS_CTL_109_DATA 0x00030A00
+#define DDRSS_CTL_110_DATA 0x00030A00
+#define DDRSS_CTL_111_DATA 0x00030A00
+#define DDRSS_CTL_112_DATA 0x00030A00
+#define DDRSS_CTL_113_DATA 0x00030A00
 #define DDRSS_CTL_114_DATA 0x00000000
-#define DDRSS_CTL_115_DATA 0x00008DF8
-#define DDRSS_CTL_116_DATA 0x00051200
-#define DDRSS_CTL_117_DATA 0x00051200
-#define DDRSS_CTL_118_DATA 0x00051200
-#define DDRSS_CTL_119_DATA 0x00051200
-#define DDRSS_CTL_120_DATA 0x00051200
+#define DDRSS_CTL_115_DATA 0x00005518
+#define DDRSS_CTL_116_DATA 0x00030A00
+#define DDRSS_CTL_117_DATA 0x00030A00
+#define DDRSS_CTL_118_DATA 0x00030A00
+#define DDRSS_CTL_119_DATA 0x00030A00
+#define DDRSS_CTL_120_DATA 0x00030A00
 #define DDRSS_CTL_121_DATA 0x00000000
-#define DDRSS_CTL_122_DATA 0x00008DF8
+#define DDRSS_CTL_122_DATA 0x00005518
 #define DDRSS_CTL_123_DATA 0x00000000
 #define DDRSS_CTL_124_DATA 0x00000000
 #define DDRSS_CTL_125_DATA 0x00000000
@@ -141,8 +149,8 @@
 #define DDRSS_CTL_128_DATA 0x00000000
 #define DDRSS_CTL_129_DATA 0x00000000
 #define DDRSS_CTL_130_DATA 0x00000000
-#define DDRSS_CTL_131_DATA 0x07030500
-#define DDRSS_CTL_132_DATA 0x00030703
+#define DDRSS_CTL_131_DATA 0x08030500
+#define DDRSS_CTL_132_DATA 0x00030803
 #define DDRSS_CTL_133_DATA 0x0A090000
 #define DDRSS_CTL_134_DATA 0x0A090701
 #define DDRSS_CTL_135_DATA 0x0900000E
@@ -177,31 +185,31 @@
 #define DDRSS_CTL_164_DATA 0x000B0000
 #define DDRSS_CTL_165_DATA 0x000E0006
 #define DDRSS_CTL_166_DATA 0x000E0404
-#define DDRSS_CTL_167_DATA 0x0086010B
-#define DDRSS_CTL_168_DATA 0x0A0A014E
-#define DDRSS_CTL_169_DATA 0x010B014E
-#define DDRSS_CTL_170_DATA 0x014E0086
-#define DDRSS_CTL_171_DATA 0x014E0A0A
+#define DDRSS_CTL_167_DATA 0x00A00140
+#define DDRSS_CTL_168_DATA 0x0C0C0190
+#define DDRSS_CTL_169_DATA 0x01400190
+#define DDRSS_CTL_170_DATA 0x019000A0
+#define DDRSS_CTL_171_DATA 0x01900C0C
 #define DDRSS_CTL_172_DATA 0x00000000
 #define DDRSS_CTL_173_DATA 0x00000000
 #define DDRSS_CTL_174_DATA 0x00000000
-#define DDRSS_CTL_175_DATA 0x24C40084
-#define DDRSS_CTL_176_DATA 0x2B0024C4
-#define DDRSS_CTL_177_DATA 0x00002B2B
+#define DDRSS_CTL_175_DATA 0x2DD40084
+#define DDRSS_CTL_176_DATA 0xEB002DD4
+#define DDRSS_CTL_177_DATA 0x0000EBEB
 #define DDRSS_CTL_178_DATA 0x36000000
 #define DDRSS_CTL_179_DATA 0x27270036
 #define DDRSS_CTL_180_DATA 0x0F0F0000
 #define DDRSS_CTL_181_DATA 0x15000000
 #define DDRSS_CTL_182_DATA 0x00841515
-#define DDRSS_CTL_183_DATA 0x24C424C4
-#define DDRSS_CTL_184_DATA 0x2B2B2B00
+#define DDRSS_CTL_183_DATA 0x2DD42DD4
+#define DDRSS_CTL_184_DATA 0xEBEBEB00
 #define DDRSS_CTL_185_DATA 0x00000000
 #define DDRSS_CTL_186_DATA 0x00363600
 #define DDRSS_CTL_187_DATA 0x00002727
 #define DDRSS_CTL_188_DATA 0x00000F0F
 #define DDRSS_CTL_189_DATA 0x15151500
 #define DDRSS_CTL_190_DATA 0x00000020
-#define DDRSS_CTL_191_DATA 0x00000000
+#define DDRSS_CTL_191_DATA 0x01000000
 #define DDRSS_CTL_192_DATA 0x00000001
 #define DDRSS_CTL_193_DATA 0x00000000
 #define DDRSS_CTL_194_DATA 0x01000000
@@ -239,17 +247,17 @@
 #define DDRSS_CTL_226_DATA 0x00000000
 #define DDRSS_CTL_227_DATA 0x15110000
 #define DDRSS_CTL_228_DATA 0x00040C18
-#define DDRSS_CTL_229_DATA 0x00000000
-#define DDRSS_CTL_230_DATA 0x00000000
+#define DDRSS_CTL_229_DATA 0xF000C000
+#define DDRSS_CTL_230_DATA 0x0000F000
 #define DDRSS_CTL_231_DATA 0x00000000
 #define DDRSS_CTL_232_DATA 0x00000000
-#define DDRSS_CTL_233_DATA 0x00000000
-#define DDRSS_CTL_234_DATA 0x00000000
+#define DDRSS_CTL_233_DATA 0xC0000000
+#define DDRSS_CTL_234_DATA 0xF000F000
 #define DDRSS_CTL_235_DATA 0x00000000
 #define DDRSS_CTL_236_DATA 0x00000000
 #define DDRSS_CTL_237_DATA 0x00000000
-#define DDRSS_CTL_238_DATA 0x00000000
-#define DDRSS_CTL_239_DATA 0x00000000
+#define DDRSS_CTL_238_DATA 0xF000C000
+#define DDRSS_CTL_239_DATA 0x0000F000
 #define DDRSS_CTL_240_DATA 0x00000000
 #define DDRSS_CTL_241_DATA 0x00000000
 #define DDRSS_CTL_242_DATA 0x00030000
@@ -271,13 +279,13 @@
 #define DDRSS_CTL_258_DATA 0x00370040
 #define DDRSS_CTL_259_DATA 0x00020008
 #define DDRSS_CTL_260_DATA 0x00400100
-#define DDRSS_CTL_261_DATA 0x00280536
+#define DDRSS_CTL_261_DATA 0x00300640
 #define DDRSS_CTL_262_DATA 0x01000200
-#define DDRSS_CTL_263_DATA 0x05360040
-#define DDRSS_CTL_264_DATA 0x00000028
-#define DDRSS_CTL_265_DATA 0x00430003
-#define DDRSS_CTL_266_DATA 0x01000043
-#define DDRSS_CTL_267_DATA 0x00000000
+#define DDRSS_CTL_263_DATA 0x06400040
+#define DDRSS_CTL_264_DATA 0x00000030
+#define DDRSS_CTL_265_DATA 0x00500003
+#define DDRSS_CTL_266_DATA 0x01000050
+#define DDRSS_CTL_267_DATA 0x03030303
 #define DDRSS_CTL_268_DATA 0x01010000
 #define DDRSS_CTL_269_DATA 0x00000202
 #define DDRSS_CTL_270_DATA 0x00000FFF
@@ -301,14 +309,14 @@
 #define DDRSS_CTL_288_DATA 0x00000000
 #define DDRSS_CTL_289_DATA 0x00000000
 #define DDRSS_CTL_290_DATA 0x03030300
-#define DDRSS_CTL_291_DATA 0x00000001
+#define DDRSS_CTL_291_DATA 0x00010101
 #define DDRSS_CTL_292_DATA 0x00000000
 #define DDRSS_CTL_293_DATA 0x00000000
 #define DDRSS_CTL_294_DATA 0x00000000
 #define DDRSS_CTL_295_DATA 0x00000000
 #define DDRSS_CTL_296_DATA 0x00000000
-#define DDRSS_CTL_297_DATA 0x00000000
-#define DDRSS_CTL_298_DATA 0x00000000
+#define DDRSS_CTL_297_DATA 0xFFFFFFFF
+#define DDRSS_CTL_298_DATA 0x00000FFF
 #define DDRSS_CTL_299_DATA 0x00000000
 #define DDRSS_CTL_300_DATA 0x00000000
 #define DDRSS_CTL_301_DATA 0x00000000
@@ -328,15 +336,15 @@
 #define DDRSS_CTL_315_DATA 0x01000101
 #define DDRSS_CTL_316_DATA 0x01010001
 #define DDRSS_CTL_317_DATA 0x00010101
-#define DDRSS_CTL_318_DATA 0x05070703
-#define DDRSS_CTL_319_DATA 0x0A081414
-#define DDRSS_CTL_320_DATA 0x0009030A
-#define DDRSS_CTL_321_DATA 0x080C030F
-#define DDRSS_CTL_322_DATA 0x080C0306
-#define DDRSS_CTL_323_DATA 0x0C090006
-#define DDRSS_CTL_324_DATA 0x0100000C
-#define DDRSS_CTL_325_DATA 0x05020501
-#define DDRSS_CTL_326_DATA 0x00000002
+#define DDRSS_CTL_318_DATA 0x05080803
+#define DDRSS_CTL_319_DATA 0x0C081C1C
+#define DDRSS_CTL_320_DATA 0x0009030C
+#define DDRSS_CTL_321_DATA 0x090B030F
+#define DDRSS_CTL_322_DATA 0x090B0306
+#define DDRSS_CTL_323_DATA 0x0B090006
+#define DDRSS_CTL_324_DATA 0x0100000B
+#define DDRSS_CTL_325_DATA 0x06030601
+#define DDRSS_CTL_326_DATA 0x00000003
 #define DDRSS_CTL_327_DATA 0x00000000
 #define DDRSS_CTL_328_DATA 0x00010000
 #define DDRSS_CTL_329_DATA 0x00280D00
@@ -397,32 +405,32 @@
 #define DDRSS_CTL_384_DATA 0x00000000
 #define DDRSS_CTL_385_DATA 0x00000000
 #define DDRSS_CTL_386_DATA 0x00000000
-#define DDRSS_CTL_387_DATA 0x2E2E1B00
+#define DDRSS_CTL_387_DATA 0x33331B00
 #define DDRSS_CTL_388_DATA 0x000A0000
-#define DDRSS_CTL_389_DATA 0x0000019C
+#define DDRSS_CTL_389_DATA 0x000000C6
 #define DDRSS_CTL_390_DATA 0x00000200
 #define DDRSS_CTL_391_DATA 0x00000200
 #define DDRSS_CTL_392_DATA 0x00000200
 #define DDRSS_CTL_393_DATA 0x00000200
-#define DDRSS_CTL_394_DATA 0x000004D4
-#define DDRSS_CTL_395_DATA 0x00001018
+#define DDRSS_CTL_394_DATA 0x00000270
+#define DDRSS_CTL_395_DATA 0x000007BC
 #define DDRSS_CTL_396_DATA 0x00000204
-#define DDRSS_CTL_397_DATA 0x00002890
+#define DDRSS_CTL_397_DATA 0x00001850
 #define DDRSS_CTL_398_DATA 0x00000200
 #define DDRSS_CTL_399_DATA 0x00000200
 #define DDRSS_CTL_400_DATA 0x00000200
 #define DDRSS_CTL_401_DATA 0x00000200
-#define DDRSS_CTL_402_DATA 0x000079B0
-#define DDRSS_CTL_403_DATA 0x000195A0
-#define DDRSS_CTL_404_DATA 0x0000080E
-#define DDRSS_CTL_405_DATA 0x00002890
+#define DDRSS_CTL_402_DATA 0x000048F0
+#define DDRSS_CTL_403_DATA 0x0000F320
+#define DDRSS_CTL_404_DATA 0x00000A14
+#define DDRSS_CTL_405_DATA 0x00001850
 #define DDRSS_CTL_406_DATA 0x00000200
 #define DDRSS_CTL_407_DATA 0x00000200
 #define DDRSS_CTL_408_DATA 0x00000200
 #define DDRSS_CTL_409_DATA 0x00000200
-#define DDRSS_CTL_410_DATA 0x000079B0
-#define DDRSS_CTL_411_DATA 0x000195A0
-#define DDRSS_CTL_412_DATA 0x0202080E
+#define DDRSS_CTL_410_DATA 0x000048F0
+#define DDRSS_CTL_411_DATA 0x0000F320
+#define DDRSS_CTL_412_DATA 0x02020A14
 #define DDRSS_CTL_413_DATA 0x03030202
 #define DDRSS_CTL_414_DATA 0x00000022
 #define DDRSS_CTL_415_DATA 0x00000000
@@ -433,13 +441,13 @@
 #define DDRSS_CTL_420_DATA 0x00000000
 #define DDRSS_CTL_421_DATA 0x00030000
 #define DDRSS_CTL_422_DATA 0x0007001F
-#define DDRSS_CTL_423_DATA 0x0013002B
-#define DDRSS_CTL_424_DATA 0x0013002B
+#define DDRSS_CTL_423_DATA 0x0016002E
+#define DDRSS_CTL_424_DATA 0x0016002E
 #define DDRSS_CTL_425_DATA 0x00000000
 #define DDRSS_CTL_426_DATA 0x00000000
 #define DDRSS_CTL_427_DATA 0x02000000
 #define DDRSS_CTL_428_DATA 0x01000404
-#define DDRSS_CTL_429_DATA 0x05120512
+#define DDRSS_CTL_429_DATA 0x071A071A
 #define DDRSS_CTL_430_DATA 0x00000105
 #define DDRSS_CTL_431_DATA 0x00010101
 #define DDRSS_CTL_432_DATA 0x00010101
@@ -448,8 +456,8 @@
 #define DDRSS_CTL_435_DATA 0x02000201
 #define DDRSS_CTL_436_DATA 0x02010000
 #define DDRSS_CTL_437_DATA 0x00000200
-#define DDRSS_CTL_438_DATA 0x18060000
-#define DDRSS_CTL_439_DATA 0x00000118
+#define DDRSS_CTL_438_DATA 0x1E060000
+#define DDRSS_CTL_439_DATA 0x0000011E
 #define DDRSS_CTL_440_DATA 0xFFFFFFFF
 #define DDRSS_CTL_441_DATA 0xFFFFFFFF
 #define DDRSS_CTL_442_DATA 0x00000000
@@ -482,8 +490,8 @@
 #define DDRSS_PI_09_DATA 0x00000000
 #define DDRSS_PI_10_DATA 0x00000000
 #define DDRSS_PI_11_DATA 0x00000000
-#define DDRSS_PI_12_DATA 0x00000007
-#define DDRSS_PI_13_DATA 0x00010002
+#define DDRSS_PI_12_DATA 0x00000003
+#define DDRSS_PI_13_DATA 0x00010001
 #define DDRSS_PI_14_DATA 0x0800000F
 #define DDRSS_PI_15_DATA 0x00000103
 #define DDRSS_PI_16_DATA 0x00000005
@@ -516,7 +524,7 @@
 #define DDRSS_PI_43_DATA 0x00000000
 #define DDRSS_PI_44_DATA 0x00000000
 #define DDRSS_PI_45_DATA 0x000F0F00
-#define DDRSS_PI_46_DATA 0x00000017
+#define DDRSS_PI_46_DATA 0x00000019
 #define DDRSS_PI_47_DATA 0x000007D0
 #define DDRSS_PI_48_DATA 0x00000300
 #define DDRSS_PI_49_DATA 0x00000000
@@ -531,18 +539,18 @@
 #define DDRSS_PI_58_DATA 0x00000000
 #define DDRSS_PI_59_DATA 0x00000000
 #define DDRSS_PI_60_DATA 0x0A0A140A
-#define DDRSS_PI_61_DATA 0x10020101
+#define DDRSS_PI_61_DATA 0x10020201
 #define DDRSS_PI_62_DATA 0x00020805
 #define DDRSS_PI_63_DATA 0x01000404
 #define DDRSS_PI_64_DATA 0x00000000
 #define DDRSS_PI_65_DATA 0x00000000
-#define DDRSS_PI_66_DATA 0x00000100
-#define DDRSS_PI_67_DATA 0x0001010F
+#define DDRSS_PI_66_DATA 0x01000100
+#define DDRSS_PI_67_DATA 0x0102020F
 #define DDRSS_PI_68_DATA 0x00340000
 #define DDRSS_PI_69_DATA 0x00000000
 #define DDRSS_PI_70_DATA 0x00000000
 #define DDRSS_PI_71_DATA 0x0000FFFF
-#define DDRSS_PI_72_DATA 0x00000000
+#define DDRSS_PI_72_DATA 0x01000000
 #define DDRSS_PI_73_DATA 0x00080100
 #define DDRSS_PI_74_DATA 0x02000200
 #define DDRSS_PI_75_DATA 0x01000100
@@ -631,104 +639,104 @@
 #define DDRSS_PI_158_DATA 0x00000000
 #define DDRSS_PI_159_DATA 0x00000401
 #define DDRSS_PI_160_DATA 0x00000000
-#define DDRSS_PI_161_DATA 0x00010000
-#define DDRSS_PI_162_DATA 0x00000000
-#define DDRSS_PI_163_DATA 0x1B1B0200
+#define DDRSS_PI_161_DATA 0x05010000
+#define DDRSS_PI_162_DATA 0x00000001
+#define DDRSS_PI_163_DATA 0x20200201
 #define DDRSS_PI_164_DATA 0x00000034
-#define DDRSS_PI_165_DATA 0x00000051
-#define DDRSS_PI_166_DATA 0x00020051
+#define DDRSS_PI_165_DATA 0x0000005C
+#define DDRSS_PI_166_DATA 0x0002005C
 #define DDRSS_PI_167_DATA 0x02000200
-#define DDRSS_PI_168_DATA 0x300C0C04
-#define DDRSS_PI_169_DATA 0x0010300C
-#define DDRSS_PI_170_DATA 0x000000CE
-#define DDRSS_PI_171_DATA 0x00000176
-#define DDRSS_PI_172_DATA 0x00001448
-#define DDRSS_PI_173_DATA 0x00000176
-#define DDRSS_PI_174_DATA 0x04001448
+#define DDRSS_PI_168_DATA 0x400E0C04
+#define DDRSS_PI_169_DATA 0x0010400E
+#define DDRSS_PI_170_DATA 0x00000068
+#define DDRSS_PI_171_DATA 0x000001C0
+#define DDRSS_PI_172_DATA 0x00000C28
+#define DDRSS_PI_173_DATA 0x000001C0
+#define DDRSS_PI_174_DATA 0x04000C28
 #define DDRSS_PI_175_DATA 0x01010404
-#define DDRSS_PI_176_DATA 0x00001501
+#define DDRSS_PI_176_DATA 0x00001500
 #define DDRSS_PI_177_DATA 0x00150015
 #define DDRSS_PI_178_DATA 0x01000100
 #define DDRSS_PI_179_DATA 0x00000100
 #define DDRSS_PI_180_DATA 0x00000000
 #define DDRSS_PI_181_DATA 0x01010101
-#define DDRSS_PI_182_DATA 0x00000101
-#define DDRSS_PI_183_DATA 0x00000100
-#define DDRSS_PI_184_DATA 0x00000100
-#define DDRSS_PI_185_DATA 0x0E040100
-#define DDRSS_PI_186_DATA 0x0808020E
+#define DDRSS_PI_182_DATA 0x00010000
+#define DDRSS_PI_183_DATA 0x00010100
+#define DDRSS_PI_184_DATA 0x00010100
+#define DDRSS_PI_185_DATA 0x14040100
+#define DDRSS_PI_186_DATA 0x0A0A0214
 #define DDRSS_PI_187_DATA 0x00040402
 #define DDRSS_PI_188_DATA 0x000D0035
-#define DDRSS_PI_189_DATA 0x00198041
-#define DDRSS_PI_190_DATA 0x00198041
-#define DDRSS_PI_191_DATA 0x01010101
-#define DDRSS_PI_192_DATA 0x0002000E
-#define DDRSS_PI_193_DATA 0x0002014E
-#define DDRSS_PI_194_DATA 0x0100014E
+#define DDRSS_PI_189_DATA 0x001C0044
+#define DDRSS_PI_190_DATA 0x001C0044
+#define DDRSS_PI_191_DATA 0x01000101
+#define DDRSS_PI_192_DATA 0x0003000E
+#define DDRSS_PI_193_DATA 0x00030190
+#define DDRSS_PI_194_DATA 0x01000190
 #define DDRSS_PI_195_DATA 0x000F000F
-#define DDRSS_PI_196_DATA 0x014F0100
-#define DDRSS_PI_197_DATA 0x0100014F
-#define DDRSS_PI_198_DATA 0x014F014F
-#define DDRSS_PI_199_DATA 0x32103200
-#define DDRSS_PI_200_DATA 0x01013210
+#define DDRSS_PI_196_DATA 0x01910100
+#define DDRSS_PI_197_DATA 0x01000191
+#define DDRSS_PI_198_DATA 0x01910191
+#define DDRSS_PI_199_DATA 0x2F1B3200
+#define DDRSS_PI_200_DATA 0x01012F1B
 #define DDRSS_PI_201_DATA 0x0A070601
-#define DDRSS_PI_202_DATA 0x140D080D
-#define DDRSS_PI_203_DATA 0x140D0810
-#define DDRSS_PI_204_DATA 0x0000C010
+#define DDRSS_PI_202_DATA 0x180F090D
+#define DDRSS_PI_203_DATA 0x180F0911
+#define DDRSS_PI_204_DATA 0x0000C011
 #define DDRSS_PI_205_DATA 0x00C01000
 #define DDRSS_PI_206_DATA 0x00C01000
 #define DDRSS_PI_207_DATA 0x00021000
-#define DDRSS_PI_208_DATA 0x001C000E
-#define DDRSS_PI_209_DATA 0x001C014E
-#define DDRSS_PI_210_DATA 0x0011014E
+#define DDRSS_PI_208_DATA 0x001E000E
+#define DDRSS_PI_209_DATA 0x001E0190
+#define DDRSS_PI_210_DATA 0x00110190
 #define DDRSS_PI_211_DATA 0x32000056
-#define DDRSS_PI_212_DATA 0x00000301
-#define DDRSS_PI_213_DATA 0x005A002A
+#define DDRSS_PI_212_DATA 0x00000101
+#define DDRSS_PI_213_DATA 0x005E0030
 #define DDRSS_PI_214_DATA 0x03013212
-#define DDRSS_PI_215_DATA 0x00002A00
-#define DDRSS_PI_216_DATA 0x3212005A
-#define DDRSS_PI_217_DATA 0x09000301
-#define DDRSS_PI_218_DATA 0x04010504
-#define DDRSS_PI_219_DATA 0x040006C9
+#define DDRSS_PI_215_DATA 0x00003000
+#define DDRSS_PI_216_DATA 0x3212005E
+#define DDRSS_PI_217_DATA 0x09000001
+#define DDRSS_PI_218_DATA 0x06010504
+#define DDRSS_PI_219_DATA 0x04000364
 #define DDRSS_PI_220_DATA 0x0A032001
-#define DDRSS_PI_221_DATA 0x1C1F0B0A
-#define DDRSS_PI_222_DATA 0x00001D12
-#define DDRSS_PI_223_DATA 0x3C00A488
-#define DDRSS_PI_224_DATA 0x13142005
-#define DDRSS_PI_225_DATA 0x1C1F0B0E
-#define DDRSS_PI_226_DATA 0x00001D12
-#define DDRSS_PI_227_DATA 0x3C00A488
-#define DDRSS_PI_228_DATA 0x13142005
-#define DDRSS_PI_229_DATA 0x00019C0E
-#define DDRSS_PI_230_DATA 0x00001018
-#define DDRSS_PI_231_DATA 0x00002890
-#define DDRSS_PI_232_DATA 0x000195A0
-#define DDRSS_PI_233_DATA 0x00002890
-#define DDRSS_PI_234_DATA 0x000195A0
-#define DDRSS_PI_235_DATA 0x01800010
-#define DDRSS_PI_236_DATA 0x03030180
+#define DDRSS_PI_221_DATA 0x21250D0A
+#define DDRSS_PI_222_DATA 0x00002216
+#define DDRSS_PI_223_DATA 0x480062B8
+#define DDRSS_PI_224_DATA 0x17182006
+#define DDRSS_PI_225_DATA 0x21250D10
+#define DDRSS_PI_226_DATA 0x00002216
+#define DDRSS_PI_227_DATA 0x480062B8
+#define DDRSS_PI_228_DATA 0x17182006
+#define DDRSS_PI_229_DATA 0x0000C610
+#define DDRSS_PI_230_DATA 0x000007BC
+#define DDRSS_PI_231_DATA 0x00001850
+#define DDRSS_PI_232_DATA 0x0000F320
+#define DDRSS_PI_233_DATA 0x00001850
+#define DDRSS_PI_234_DATA 0x0000F320
+#define DDRSS_PI_235_DATA 0x01CC0010
+#define DDRSS_PI_236_DATA 0x030301CC
 #define DDRSS_PI_237_DATA 0x002AF803
 #define DDRSS_PI_238_DATA 0x0001ADAF
 #define DDRSS_PI_239_DATA 0x00000005
 #define DDRSS_PI_240_DATA 0x0000006E
 #define DDRSS_PI_241_DATA 0x00000010
-#define DDRSS_PI_242_DATA 0x000411AB
+#define DDRSS_PI_242_DATA 0x0004E200
 #define DDRSS_PI_243_DATA 0x0001ADAF
 #define DDRSS_PI_244_DATA 0x00000005
-#define DDRSS_PI_245_DATA 0x00000A6B
-#define DDRSS_PI_246_DATA 0x00000180
-#define DDRSS_PI_247_DATA 0x000411AB
+#define DDRSS_PI_245_DATA 0x00000C80
+#define DDRSS_PI_246_DATA 0x000001CC
+#define DDRSS_PI_247_DATA 0x0004E200
 #define DDRSS_PI_248_DATA 0x0001ADAF
 #define DDRSS_PI_249_DATA 0x00000005
-#define DDRSS_PI_250_DATA 0x00000A6B
-#define DDRSS_PI_251_DATA 0x01000180
+#define DDRSS_PI_250_DATA 0x00000C80
+#define DDRSS_PI_251_DATA 0x010001CC
 #define DDRSS_PI_252_DATA 0x00370040
 #define DDRSS_PI_253_DATA 0x00010008
-#define DDRSS_PI_254_DATA 0x05360040
-#define DDRSS_PI_255_DATA 0x00010028
-#define DDRSS_PI_256_DATA 0x05360040
-#define DDRSS_PI_257_DATA 0x00000328
-#define DDRSS_PI_258_DATA 0x00430043
+#define DDRSS_PI_254_DATA 0x06400040
+#define DDRSS_PI_255_DATA 0x00010030
+#define DDRSS_PI_256_DATA 0x06400040
+#define DDRSS_PI_257_DATA 0x00000330
+#define DDRSS_PI_258_DATA 0x00500050
 #define DDRSS_PI_259_DATA 0x08040404
 #define DDRSS_PI_260_DATA 0x00000055
 #define DDRSS_PI_261_DATA 0x55083C5A
@@ -745,29 +753,29 @@
 #define DDRSS_PI_272_DATA 0x00080804
 #define DDRSS_PI_273_DATA 0x00000000
 #define DDRSS_PI_274_DATA 0x00000000
-#define DDRSS_PI_275_DATA 0x002B0084
+#define DDRSS_PI_275_DATA 0x00EB0084
 #define DDRSS_PI_276_DATA 0x00150000
-#define DDRSS_PI_277_DATA 0x362B24C4
+#define DDRSS_PI_277_DATA 0x36EB2DD4
 #define DDRSS_PI_278_DATA 0x00150F27
-#define DDRSS_PI_279_DATA 0x362B24C4
+#define DDRSS_PI_279_DATA 0x36EB2DD4
 #define DDRSS_PI_280_DATA 0x00150F27
-#define DDRSS_PI_281_DATA 0x002B0084
+#define DDRSS_PI_281_DATA 0x00EB0084
 #define DDRSS_PI_282_DATA 0x00150000
-#define DDRSS_PI_283_DATA 0x362B24C4
+#define DDRSS_PI_283_DATA 0x36EB2DD4
 #define DDRSS_PI_284_DATA 0x00150F27
-#define DDRSS_PI_285_DATA 0x362B24C4
+#define DDRSS_PI_285_DATA 0x36EB2DD4
 #define DDRSS_PI_286_DATA 0x00150F27
-#define DDRSS_PI_287_DATA 0x002B0084
+#define DDRSS_PI_287_DATA 0x00EB0084
 #define DDRSS_PI_288_DATA 0x00150000
-#define DDRSS_PI_289_DATA 0x362B24C4
+#define DDRSS_PI_289_DATA 0x36EB2DD4
 #define DDRSS_PI_290_DATA 0x00150F27
-#define DDRSS_PI_291_DATA 0x362B24C4
+#define DDRSS_PI_291_DATA 0x36EB2DD4
 #define DDRSS_PI_292_DATA 0x00150F27
-#define DDRSS_PI_293_DATA 0x002B0084
+#define DDRSS_PI_293_DATA 0x00EB0084
 #define DDRSS_PI_294_DATA 0x00150000
-#define DDRSS_PI_295_DATA 0x362B24C4
+#define DDRSS_PI_295_DATA 0x36EB2DD4
 #define DDRSS_PI_296_DATA 0x00150F27
-#define DDRSS_PI_297_DATA 0x362B24C4
+#define DDRSS_PI_297_DATA 0x36EB2DD4
 #define DDRSS_PI_298_DATA 0x00150F27
 #define DDRSS_PI_299_DATA 0x00000000
 
@@ -783,7 +791,7 @@
 #define DDRSS_PHY_09_DATA 0x00000000
 #define DDRSS_PHY_10_DATA 0x00000000
 #define DDRSS_PHY_11_DATA 0x01000001
-#define DDRSS_PHY_12_DATA 0x00000100
+#define DDRSS_PHY_12_DATA 0x00000200
 #define DDRSS_PHY_13_DATA 0x000800C0
 #define DDRSS_PHY_14_DATA 0x060100CC
 #define DDRSS_PHY_15_DATA 0x00030066
@@ -802,9 +810,9 @@
 #define DDRSS_PHY_28_DATA 0x2A000000
 #define DDRSS_PHY_29_DATA 0x00000808
 #define DDRSS_PHY_30_DATA 0x0F000000
-#define DDRSS_PHY_31_DATA 0x00000F0F
-#define DDRSS_PHY_32_DATA 0x10200000
-#define DDRSS_PHY_33_DATA 0x0C002007
+#define DDRSS_PHY_31_DATA 0x00000F08
+#define DDRSS_PHY_32_DATA 0x10400000
+#define DDRSS_PHY_33_DATA 0x0C002006
 #define DDRSS_PHY_34_DATA 0x00000000
 #define DDRSS_PHY_35_DATA 0x00000000
 #define DDRSS_PHY_36_DATA 0x55555555
@@ -871,20 +879,20 @@
 #define DDRSS_PHY_97_DATA 0x00050010
 #define DDRSS_PHY_98_DATA 0x51517041
 #define DDRSS_PHY_99_DATA 0x31C06000
-#define DDRSS_PHY_100_DATA 0x07AB0340
+#define DDRSS_PHY_100_DATA 0x07AB01AB
 #define DDRSS_PHY_101_DATA 0x00C0C001
-#define DDRSS_PHY_102_DATA 0x09080001
+#define DDRSS_PHY_102_DATA 0x0B0A0101
 #define DDRSS_PHY_103_DATA 0x10001000
-#define DDRSS_PHY_104_DATA 0x0C063E42
-#define DDRSS_PHY_105_DATA 0x0F0C2701
+#define DDRSS_PHY_104_DATA 0x0C073E42
+#define DDRSS_PHY_105_DATA 0x0F0C2D01
 #define DDRSS_PHY_106_DATA 0x01000140
-#define DDRSS_PHY_107_DATA 0x04000420
+#define DDRSS_PHY_107_DATA 0x0C000420
 #define DDRSS_PHY_108_DATA 0x00000198
 #define DDRSS_PHY_109_DATA 0x0A0000D0
 #define DDRSS_PHY_110_DATA 0x00030200
 #define DDRSS_PHY_111_DATA 0x02800000
 #define DDRSS_PHY_112_DATA 0x80800000
-#define DDRSS_PHY_113_DATA 0x00092010
+#define DDRSS_PHY_113_DATA 0x000B2010
 #define DDRSS_PHY_114_DATA 0x76543210
 #define DDRSS_PHY_115_DATA 0x00000008
 #define DDRSS_PHY_116_DATA 0x02800280
@@ -901,8 +909,8 @@
 #define DDRSS_PHY_127_DATA 0x00A000A0
 #define DDRSS_PHY_128_DATA 0x00A000A0
 #define DDRSS_PHY_129_DATA 0x00A000A0
-#define DDRSS_PHY_130_DATA 0x01C400A0
-#define DDRSS_PHY_131_DATA 0x01A00003
+#define DDRSS_PHY_130_DATA 0x011900A0
+#define DDRSS_PHY_131_DATA 0x01A00004
 #define DDRSS_PHY_132_DATA 0x00000000
 #define DDRSS_PHY_133_DATA 0x00000000
 #define DDRSS_PHY_134_DATA 0x00080200
@@ -1039,7 +1047,7 @@
 #define DDRSS_PHY_265_DATA 0x00000000
 #define DDRSS_PHY_266_DATA 0x00000000
 #define DDRSS_PHY_267_DATA 0x01000001
-#define DDRSS_PHY_268_DATA 0x00000100
+#define DDRSS_PHY_268_DATA 0x00000200
 #define DDRSS_PHY_269_DATA 0x000800C0
 #define DDRSS_PHY_270_DATA 0x060100CC
 #define DDRSS_PHY_271_DATA 0x00030066
@@ -1058,9 +1066,9 @@
 #define DDRSS_PHY_284_DATA 0x2A000000
 #define DDRSS_PHY_285_DATA 0x00000808
 #define DDRSS_PHY_286_DATA 0x0F000000
-#define DDRSS_PHY_287_DATA 0x00000F0F
-#define DDRSS_PHY_288_DATA 0x10200000
-#define DDRSS_PHY_289_DATA 0x0C002007
+#define DDRSS_PHY_287_DATA 0x00000F08
+#define DDRSS_PHY_288_DATA 0x10400000
+#define DDRSS_PHY_289_DATA 0x0C002006
 #define DDRSS_PHY_290_DATA 0x00000000
 #define DDRSS_PHY_291_DATA 0x00000000
 #define DDRSS_PHY_292_DATA 0x55555555
@@ -1127,20 +1135,20 @@
 #define DDRSS_PHY_353_DATA 0x00050010
 #define DDRSS_PHY_354_DATA 0x51517041
 #define DDRSS_PHY_355_DATA 0x31C06000
-#define DDRSS_PHY_356_DATA 0x07AB0340
+#define DDRSS_PHY_356_DATA 0x07AB01AB
 #define DDRSS_PHY_357_DATA 0x00C0C001
-#define DDRSS_PHY_358_DATA 0x09080001
+#define DDRSS_PHY_358_DATA 0x0B0A0101
 #define DDRSS_PHY_359_DATA 0x10001000
-#define DDRSS_PHY_360_DATA 0x0C063E42
-#define DDRSS_PHY_361_DATA 0x0F0C2701
+#define DDRSS_PHY_360_DATA 0x0C073E42
+#define DDRSS_PHY_361_DATA 0x0F0C2D01
 #define DDRSS_PHY_362_DATA 0x01000140
-#define DDRSS_PHY_363_DATA 0x04000420
+#define DDRSS_PHY_363_DATA 0x0C000420
 #define DDRSS_PHY_364_DATA 0x00000198
 #define DDRSS_PHY_365_DATA 0x0A0000D0
 #define DDRSS_PHY_366_DATA 0x00030200
 #define DDRSS_PHY_367_DATA 0x02800000
 #define DDRSS_PHY_368_DATA 0x80800000
-#define DDRSS_PHY_369_DATA 0x00092010
+#define DDRSS_PHY_369_DATA 0x000B2010
 #define DDRSS_PHY_370_DATA 0x76543210
 #define DDRSS_PHY_371_DATA 0x00000008
 #define DDRSS_PHY_372_DATA 0x02800280
@@ -1157,8 +1165,8 @@
 #define DDRSS_PHY_383_DATA 0x00A000A0
 #define DDRSS_PHY_384_DATA 0x00A000A0
 #define DDRSS_PHY_385_DATA 0x00A000A0
-#define DDRSS_PHY_386_DATA 0x01C400A0
-#define DDRSS_PHY_387_DATA 0x01A00003
+#define DDRSS_PHY_386_DATA 0x011900A0
+#define DDRSS_PHY_387_DATA 0x01A00004
 #define DDRSS_PHY_388_DATA 0x00000000
 #define DDRSS_PHY_389_DATA 0x00000000
 #define DDRSS_PHY_390_DATA 0x00080200
@@ -1295,7 +1303,7 @@
 #define DDRSS_PHY_521_DATA 0x00000000
 #define DDRSS_PHY_522_DATA 0x00000000
 #define DDRSS_PHY_523_DATA 0x01000001
-#define DDRSS_PHY_524_DATA 0x00000100
+#define DDRSS_PHY_524_DATA 0x00000200
 #define DDRSS_PHY_525_DATA 0x000800C0
 #define DDRSS_PHY_526_DATA 0x060100CC
 #define DDRSS_PHY_527_DATA 0x00030066
@@ -1314,9 +1322,9 @@
 #define DDRSS_PHY_540_DATA 0x2A000000
 #define DDRSS_PHY_541_DATA 0x00000808
 #define DDRSS_PHY_542_DATA 0x0F000000
-#define DDRSS_PHY_543_DATA 0x00000F0F
-#define DDRSS_PHY_544_DATA 0x10200000
-#define DDRSS_PHY_545_DATA 0x0C002007
+#define DDRSS_PHY_543_DATA 0x00000F08
+#define DDRSS_PHY_544_DATA 0x10400000
+#define DDRSS_PHY_545_DATA 0x0C002006
 #define DDRSS_PHY_546_DATA 0x00000000
 #define DDRSS_PHY_547_DATA 0x00000000
 #define DDRSS_PHY_548_DATA 0x55555555
@@ -1383,20 +1391,20 @@
 #define DDRSS_PHY_609_DATA 0x00050010
 #define DDRSS_PHY_610_DATA 0x51517041
 #define DDRSS_PHY_611_DATA 0x31C06000
-#define DDRSS_PHY_612_DATA 0x07AB0340
+#define DDRSS_PHY_612_DATA 0x07AB01AB
 #define DDRSS_PHY_613_DATA 0x00C0C001
-#define DDRSS_PHY_614_DATA 0x09080001
+#define DDRSS_PHY_614_DATA 0x0B0A0101
 #define DDRSS_PHY_615_DATA 0x10001000
-#define DDRSS_PHY_616_DATA 0x0C063E42
-#define DDRSS_PHY_617_DATA 0x0F0C2701
+#define DDRSS_PHY_616_DATA 0x0C073E42
+#define DDRSS_PHY_617_DATA 0x0F0C2D01
 #define DDRSS_PHY_618_DATA 0x01000140
-#define DDRSS_PHY_619_DATA 0x04000420
+#define DDRSS_PHY_619_DATA 0x0C000420
 #define DDRSS_PHY_620_DATA 0x00000198
 #define DDRSS_PHY_621_DATA 0x0A0000D0
 #define DDRSS_PHY_622_DATA 0x00030200
 #define DDRSS_PHY_623_DATA 0x02800000
 #define DDRSS_PHY_624_DATA 0x80800000
-#define DDRSS_PHY_625_DATA 0x00092010
+#define DDRSS_PHY_625_DATA 0x000B2010
 #define DDRSS_PHY_626_DATA 0x76543210
 #define DDRSS_PHY_627_DATA 0x00000008
 #define DDRSS_PHY_628_DATA 0x02800280
@@ -1413,8 +1421,8 @@
 #define DDRSS_PHY_639_DATA 0x00A000A0
 #define DDRSS_PHY_640_DATA 0x00A000A0
 #define DDRSS_PHY_641_DATA 0x00A000A0
-#define DDRSS_PHY_642_DATA 0x01C400A0
-#define DDRSS_PHY_643_DATA 0x01A00003
+#define DDRSS_PHY_642_DATA 0x011900A0
+#define DDRSS_PHY_643_DATA 0x01A00004
 #define DDRSS_PHY_644_DATA 0x00000000
 #define DDRSS_PHY_645_DATA 0x00000000
 #define DDRSS_PHY_646_DATA 0x00080200
@@ -1551,7 +1559,7 @@
 #define DDRSS_PHY_777_DATA 0x00000000
 #define DDRSS_PHY_778_DATA 0x00000000
 #define DDRSS_PHY_779_DATA 0x01000001
-#define DDRSS_PHY_780_DATA 0x00000100
+#define DDRSS_PHY_780_DATA 0x00000200
 #define DDRSS_PHY_781_DATA 0x000800C0
 #define DDRSS_PHY_782_DATA 0x060100CC
 #define DDRSS_PHY_783_DATA 0x00030066
@@ -1570,9 +1578,9 @@
 #define DDRSS_PHY_796_DATA 0x2A000000
 #define DDRSS_PHY_797_DATA 0x00000808
 #define DDRSS_PHY_798_DATA 0x0F000000
-#define DDRSS_PHY_799_DATA 0x00000F0F
-#define DDRSS_PHY_800_DATA 0x10200000
-#define DDRSS_PHY_801_DATA 0x0C002007
+#define DDRSS_PHY_799_DATA 0x00000F08
+#define DDRSS_PHY_800_DATA 0x10400000
+#define DDRSS_PHY_801_DATA 0x0C002006
 #define DDRSS_PHY_802_DATA 0x00000000
 #define DDRSS_PHY_803_DATA 0x00000000
 #define DDRSS_PHY_804_DATA 0x55555555
@@ -1639,20 +1647,20 @@
 #define DDRSS_PHY_865_DATA 0x00050010
 #define DDRSS_PHY_866_DATA 0x51517041
 #define DDRSS_PHY_867_DATA 0x31C06000
-#define DDRSS_PHY_868_DATA 0x07AB0340
+#define DDRSS_PHY_868_DATA 0x07AB01AB
 #define DDRSS_PHY_869_DATA 0x00C0C001
-#define DDRSS_PHY_870_DATA 0x09080001
+#define DDRSS_PHY_870_DATA 0x0B0A0101
 #define DDRSS_PHY_871_DATA 0x10001000
-#define DDRSS_PHY_872_DATA 0x0C063E42
-#define DDRSS_PHY_873_DATA 0x0F0C2701
+#define DDRSS_PHY_872_DATA 0x0C073E42
+#define DDRSS_PHY_873_DATA 0x0F0C2D01
 #define DDRSS_PHY_874_DATA 0x01000140
-#define DDRSS_PHY_875_DATA 0x04000420
+#define DDRSS_PHY_875_DATA 0x0C000420
 #define DDRSS_PHY_876_DATA 0x00000198
 #define DDRSS_PHY_877_DATA 0x0A0000D0
 #define DDRSS_PHY_878_DATA 0x00030200
 #define DDRSS_PHY_879_DATA 0x02800000
 #define DDRSS_PHY_880_DATA 0x80800000
-#define DDRSS_PHY_881_DATA 0x00092010
+#define DDRSS_PHY_881_DATA 0x000B2010
 #define DDRSS_PHY_882_DATA 0x76543210
 #define DDRSS_PHY_883_DATA 0x00000008
 #define DDRSS_PHY_884_DATA 0x02800280
@@ -1669,8 +1677,8 @@
 #define DDRSS_PHY_895_DATA 0x00A000A0
 #define DDRSS_PHY_896_DATA 0x00A000A0
 #define DDRSS_PHY_897_DATA 0x00A000A0
-#define DDRSS_PHY_898_DATA 0x01C400A0
-#define DDRSS_PHY_899_DATA 0x01A00003
+#define DDRSS_PHY_898_DATA 0x011900A0
+#define DDRSS_PHY_899_DATA 0x01A00004
 #define DDRSS_PHY_900_DATA 0x00000000
 #define DDRSS_PHY_901_DATA 0x00000000
 #define DDRSS_PHY_902_DATA 0x00080200
@@ -1810,7 +1818,7 @@
 #define DDRSS_PHY_1036_DATA 0x00000080
 #define DDRSS_PHY_1037_DATA 0x00DCBA98
 #define DDRSS_PHY_1038_DATA 0x03000000
-#define DDRSS_PHY_1039_DATA 0x00200000
+#define DDRSS_PHY_1039_DATA 0x00200001
 #define DDRSS_PHY_1040_DATA 0x00000000
 #define DDRSS_PHY_1041_DATA 0x00000000
 #define DDRSS_PHY_1042_DATA 0x00000000
@@ -1826,7 +1834,7 @@
 #define DDRSS_PHY_1052_DATA 0x00000033
 #define DDRSS_PHY_1053_DATA 0x00543210
 #define DDRSS_PHY_1054_DATA 0x003F0000
-#define DDRSS_PHY_1055_DATA 0x000F013F
+#define DDRSS_PHY_1055_DATA 0x000F3F3F
 #define DDRSS_PHY_1056_DATA 0x20202003
 #define DDRSS_PHY_1057_DATA 0x00202020
 #define DDRSS_PHY_1058_DATA 0x20008008
@@ -1835,7 +1843,7 @@
 #define DDRSS_PHY_1061_DATA 0x00000000
 #define DDRSS_PHY_1062_DATA 0x00000000
 #define DDRSS_PHY_1063_DATA 0x00000000
-#define DDRSS_PHY_1064_DATA 0x000205BB
+#define DDRSS_PHY_1064_DATA 0x000305CC
 #define DDRSS_PHY_1065_DATA 0x00030000
 #define DDRSS_PHY_1066_DATA 0x00000300
 #define DDRSS_PHY_1067_DATA 0x00000300
@@ -1844,8 +1852,8 @@
 #define DDRSS_PHY_1070_DATA 0x00000300
 #define DDRSS_PHY_1071_DATA 0x42080010
 #define DDRSS_PHY_1072_DATA 0x0000803E
-#define DDRSS_PHY_1073_DATA 0x00000001
-#define DDRSS_PHY_1074_DATA 0x01000102
+#define DDRSS_PHY_1073_DATA 0x00000004
+#define DDRSS_PHY_1074_DATA 0x01000002
 #define DDRSS_PHY_1075_DATA 0x00008000
 #define DDRSS_PHY_1076_DATA 0x00000000
 #define DDRSS_PHY_1077_DATA 0x00000000
@@ -2074,14 +2082,14 @@
 #define DDRSS_PHY_1300_DATA 0x00040101
 #define DDRSS_PHY_1301_DATA 0x0000010F
 #define DDRSS_PHY_1302_DATA 0x00000000
-#define DDRSS_PHY_1303_DATA 0x0000FFFF
+#define DDRSS_PHY_1303_DATA 0x00000064
 #define DDRSS_PHY_1304_DATA 0x00000000
 #define DDRSS_PHY_1305_DATA 0x01010000
 #define DDRSS_PHY_1306_DATA 0x01080402
 #define DDRSS_PHY_1307_DATA 0x01200F02
 #define DDRSS_PHY_1308_DATA 0x00194280
 #define DDRSS_PHY_1309_DATA 0x00000004
-#define DDRSS_PHY_1310_DATA 0x00052000
+#define DDRSS_PHY_1310_DATA 0x00042000
 #define DDRSS_PHY_1311_DATA 0x00000000
 #define DDRSS_PHY_1312_DATA 0x00000000
 #define DDRSS_PHY_1313_DATA 0x00000000
@@ -2165,10 +2173,10 @@
 #define DDRSS_PHY_1391_DATA 0x00000000
 #define DDRSS_PHY_1392_DATA 0x00000000
 #define DDRSS_PHY_1393_DATA 0x0001F7C0
-#define DDRSS_PHY_1394_DATA 0x00000002
+#define DDRSS_PHY_1394_DATA 0x00000003
 #define DDRSS_PHY_1395_DATA 0x00000000
 #define DDRSS_PHY_1396_DATA 0x00001142
-#define DDRSS_PHY_1397_DATA 0x010207AB
+#define DDRSS_PHY_1397_DATA 0x040207AB
 #define DDRSS_PHY_1398_DATA 0x01000080
 #define DDRSS_PHY_1399_DATA 0x03900390
 #define DDRSS_PHY_1400_DATA 0x03900390
@@ -2177,20 +2185,23 @@
 #define DDRSS_PHY_1403_DATA 0x00000390
 #define DDRSS_PHY_1404_DATA 0x00000390
 #define DDRSS_PHY_1405_DATA 0x00000005
-#define DDRSS_PHY_1406_DATA 0x01813FBB
-#define DDRSS_PHY_1407_DATA 0x000000BB
+#define DDRSS_PHY_1406_DATA 0x01813FCC
+#define DDRSS_PHY_1407_DATA 0x000000CC
 #define DDRSS_PHY_1408_DATA 0x0C000DFF
 #define DDRSS_PHY_1409_DATA 0x30000DFF
 #define DDRSS_PHY_1410_DATA 0x3F0DFF11
 #define DDRSS_PHY_1411_DATA 0x000100F0
-#define DDRSS_PHY_1412_DATA 0x780DFFBB
+#define DDRSS_PHY_1412_DATA 0x780DFFCC
 #define DDRSS_PHY_1413_DATA 0x00007E31
 #define DDRSS_PHY_1414_DATA 0x000CBF11
-#define DDRSS_PHY_1415_DATA 0x01770010
+#define DDRSS_PHY_1415_DATA 0x01990010
 #define DDRSS_PHY_1416_DATA 0x000CBF11
-#define DDRSS_PHY_1417_DATA 0x01770010
+#define DDRSS_PHY_1417_DATA 0x01990010
 #define DDRSS_PHY_1418_DATA 0x3F0DFF11
-#define DDRSS_PHY_1419_DATA 0x017700F0
+#define DDRSS_PHY_1419_DATA 0x00EF00F0
 #define DDRSS_PHY_1420_DATA 0x3F0DFF11
 #define DDRSS_PHY_1421_DATA 0x01FF00F0
 #define DDRSS_PHY_1422_DATA 0x20040006
+
+
+

arch/arm/dts/k3-j7200-r5-common-proc-board.dts

@@ -6,7 +6,7 @@
 /dts-v1/;
 
 #include "k3-j7200-common-proc-board.dts"
-#include "k3-j7200-ddr-evm-lp4-2666.dtsi"
+#include "k3-j7200-ddr-evm-lp4-3200.dtsi"
 #include "k3-j721e-ddr.dtsi"
 #include "k3-j7200-common-proc-board-u-boot.dtsi"
 #include "k3-j7200-r5.dtsi"

arch/arm/dts/lemans-evk-u-boot.dtsi

@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2026, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/ {
+	/* Will be removed when bootloader updates later */
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x0 0x3ee00000>,
+		      <0x0 0xc0000000 0x0 0x0fd00000>,
+		      <0xD 0x00000000 0x2 0x54100000>,
+		      <0xA 0x80000000 0x1 0x80000000>,
+		      <0x9 0x00000000 0x1 0x80000000>,
+		      <0x1 0x00000000 0x3 0x00000000>,
+		      <0x0 0xd0000000 0x0 0x01900000>,
+		      <0x0 0xd3500000 0x0 0x2cb00000>;
+	};
+};

arch/arm/dts/r8a779md-geist-u-boot.dtsi

@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source extras for U-Boot for the Geist board with r8a779md
+ *
+ * Copyright (C) 2025-2026 Renesas Electronics Corp.
+ */
+
+/ {
+	aliases {
+		spi0 = &rpc;
+	};
+};
+
+&pfc {
+	qspi0_pins: qspi0 {
+		groups = "qspi0_ctrl", "qspi0_data4";
+		function = "qspi0";
+	};
+};
+
+/*
+ * SPI access works only if TFA is built with RCAR_RPC_HYPERFLASH_LOCKED=0
+ * and SPD=none , otherwise the RPC access is blocked either by TFA in case
+ * the former is set to 1, or by OPTEE-OS in case SPD=opteed .
+ */
+&rpc {
+	pinctrl-0 = <&qspi0_pins>;
+	pinctrl-names = "default";
+
+	#address-cells = <1>;
+	#size-cells = <0>;
+	spi-max-frequency = <40000000>;
+	status = "okay";
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <40000000>;
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <1>;
+	};
+};
+
+&sdhi0 {
+	sd-uhs-sdr12;
+	sd-uhs-sdr25;
+	sd-uhs-sdr104;
+	max-frequency = <208000000>;
+};
+
+&sdhi2 {
+	mmc-ddr-1_8v;
+	mmc-hs200-1_8v;
+	max-frequency = <200000000>;
+};
+
+&vcc_sdhi0 {
+	u-boot,off-on-delay-us = <20000>;
+};

arch/arm/dts/r8a779md-geist.dts

@@ -0,0 +1,717 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the Geist board with R-Car M3Le
+ *
+ * Copyright (C) 2025-2026 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include "r8a779md.dtsi"
+
+/ {
+	model = "Renesas Geist board based on r8a779md";
+	compatible = "renesas,geist", "renesas,r8a779md", "renesas,r8a77965";
+
+	aliases {
+		serial0 = &scif2;
+		serial1 = &hscif1;
+		ethernet0 = &avb;
+		mmc0 = &sdhi2;
+		mmc1 = &sdhi0;
+	};
+
+	chosen {
+		bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
+		stdout-path = "serial0:115200n8";
+	};
+
+	audio_clkout: audio-clkout {
+		/*
+		 * This is same as <&rcar_sound 0>
+		 * but needed to avoid cs2500/rcar_sound probe dead-lock
+		 */
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <12288000>;
+	};
+
+	backlight: backlight {
+		compatible = "pwm-backlight";
+		pwms = <&pwm1 0 50000>;
+
+		brightness-levels = <256 128 64 16 8 4 0>;
+		default-brightness-level = <6>;
+
+		power-supply = <&reg_12v>;
+		enable-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
+	};
+
+	cvbs-in {
+		compatible = "composite-video-connector";
+		label = "CVBS IN";
+
+		port {
+			cvbs_con: endpoint {
+				remote-endpoint = <&adv7482_ain7>;
+			};
+		};
+	};
+
+	hdmi-in {
+		compatible = "hdmi-connector";
+		label = "HDMI IN";
+		type = "a";
+
+		port {
+			hdmi_in_con: endpoint {
+				remote-endpoint = <&adv7482_hdmi>;
+			};
+		};
+	};
+
+	keys {
+		compatible = "gpio-keys";
+
+		pinctrl-0 = <&keys_pins>;
+		pinctrl-names = "default";
+
+		key-1 {
+			gpios = <&gpio5 17 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_1>;
+			label = "SW4-1";
+			wakeup-source;
+			debounce-interval = <20>;
+		};
+
+		key-2 {
+			gpios = <&gpio5 20 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_2>;
+			label = "SW4-2";
+			wakeup-source;
+			debounce-interval = <20>;
+		};
+
+		key-3 {
+			gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_3>;
+			label = "SW4-3";
+			wakeup-source;
+			debounce-interval = <20>;
+		};
+
+		key-4 {
+			gpios = <&gpio5 23 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_4>;
+			label = "SW4-4";
+			wakeup-source;
+			debounce-interval = <20>;
+		};
+
+		key-a {
+			gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_A>;
+			label = "TSW0";
+			wakeup-source;
+			debounce-interval = <20>;
+		};
+
+		key-b {
+			gpios = <&gpio6 12 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_B>;
+			label = "TSW1";
+			wakeup-source;
+			debounce-interval = <20>;
+		};
+
+		key-c {
+			gpios = <&gpio6 13 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_C>;
+			label = "TSW2";
+			wakeup-source;
+			debounce-interval = <20>;
+		};
+	};
+
+	memory@48000000 {
+		device_type = "memory";
+		/* first 128MB is reserved for secure area. */
+		reg = <0x0 0x48000000 0x0 0x78000000>;
+	};
+
+	memory@480000000 {
+		device_type = "memory";
+		reg = <0x4 0x80000000 0x0 0x80000000>;
+	};
+
+	reg_1p8v: regulator-1p8v {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-1.8V";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	reg_3p3v: regulator-3p3v {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-3.3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	reg_12v: regulator-12v {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-12V";
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	vbus0_usb2: regulator-vbus0-usb2 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "USB20_VBUS0";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+
+		gpio = <&gpio6 16 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	vcc_sdhi0: regulator-vcc-sdhi0 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "SDHI0 Vcc";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	vccq_sdhi0: regulator-vccq-sdhi0 {
+		compatible = "regulator-gpio";
+
+		regulator-name = "SDHI0 VccQ";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
+		gpios-states = <1>;
+		states = <3300000 1>, <1800000 0>;
+	};
+
+	sound_card: sound {
+		compatible = "audio-graph-card";
+
+		label = "rcar-sound";
+		dais = <&rsnd_port0>; /* AK4619 Audio Codec */
+	};
+
+	x12_clk: x12-clock {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <24576000>;
+	};
+
+	/* External DU dot clocks */
+	x21_clk: x21-clock {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <33000000>;
+	};
+
+	x22_clk: x22-clock {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <33000000>;
+	};
+
+	x23_clk: x23-clock {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <25000000>;
+	};
+
+	x3013_clk: x3013-clock {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <25000000>;
+	};
+};
+
+&audio_clk_a {
+	clock-frequency = <22579200>;
+};
+
+&avb {
+	pinctrl-0 = <&avb_pins>;
+	pinctrl-names = "default";
+	phy-handle = <&phy0>;
+	tx-internal-delay-ps = <2000>;
+	status = "okay";
+
+	phy0: ethernet-phy@0 {
+		compatible = "ethernet-phy-id0022.1622";
+		rxc-skew-ps = <1500>;
+		reg = <0>;
+		interrupts-extended = <&gpio2 11 IRQ_TYPE_LEVEL_LOW>;
+		reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
+		reset-assert-us = <10000>;
+		reset-deassert-us = <300>;
+	};
+};
+
+&csi40 {
+	status = "okay";
+
+	ports {
+		port@0 {
+			csi40_in: endpoint {
+				clock-lanes = <0>;
+				data-lanes = <1 2 3 4>;
+				remote-endpoint = <&adv7482_txa>;
+			};
+		};
+	};
+};
+
+&ehci0 {
+	dr_mode = "otg";
+	status = "okay";
+};
+
+&extalr_clk {
+	clock-frequency = <32768>;
+};
+
+&extal_clk {
+	clock-frequency = <16666666>;
+};
+
+&hscif1 {
+	pinctrl-0 = <&hscif1_pins>;
+	pinctrl-names = "default";
+
+	uart-has-rtscts;
+	/* Please only enable hscif1 or scif1 */
+	status = "okay";
+};
+
+&hsusb {
+	dr_mode = "otg";
+	status = "okay";
+};
+
+&i2c2 {
+	pinctrl-0 = <&i2c2_pins>;
+	pinctrl-names = "default";
+	clock-frequency = <100000>;
+	status = "okay";
+
+	ak4619: codec@10 {
+		compatible = "asahi-kasei,ak4619";
+		reg = <0x10>;
+		clocks = <&rcar_sound 3>;
+		clock-names = "mclk";
+		#sound-dai-cells = <0>;
+
+		port {
+			ak4619_endpoint: endpoint {
+				remote-endpoint = <&rsnd_endpoint0>;
+			};
+		};
+	};
+
+	/* Pin-to-pin, register map, and control compatible with CS2000 and CS2200 */
+	cs2500: clock-controller@4f {
+		#clock-cells = <0>;
+		compatible = "cirrus,cs2500", "cirrus,cs2000-cp";
+		reg = <0x4f>;
+		clocks = <&audio_clkout>, <&x12_clk>;
+		clock-names = "clk_in", "ref_clk";
+
+		assigned-clocks = <&cs2500>;
+		assigned-clock-rates = <24576000>; /* 1/1 divide */
+	};
+};
+
+&i2c4 {
+	clock-frequency = <400000>;
+	status = "okay";
+
+	versaclock3: clock-controller@68 {
+		compatible = "renesas,5p35023";
+		reg = <0x68>;
+		#clock-cells = <1>;
+		clocks = <&x3013_clk>;
+		assigned-clocks = <&versaclock3 4>, <&versaclock3 5>;
+		assigned-clock-rates = <100000000>, <100000000>;
+	};
+
+	versaclock5: clock-controller@6a {
+		compatible = "idt,5p49v5923";
+		reg = <0x6a>;
+		#clock-cells = <1>;
+		clocks = <&x23_clk>;
+		clock-names = "xin";
+	};
+
+	video-receiver@70 {
+		compatible = "adi,adv7482";
+		reg = <0x70 0x71 0x72 0x73 0x74 0x75
+		       0x60 0x61 0x62 0x63 0x64 0x65>;
+		reg-names = "main", "dpll", "cp", "hdmi", "edid", "repeater",
+			    "infoframe", "cbus", "cec", "sdp", "txa", "txb" ;
+
+		interrupts-extended = <&gpio6 30 IRQ_TYPE_LEVEL_LOW>,
+				      <&gpio6 31 IRQ_TYPE_LEVEL_LOW>;
+		interrupt-names = "intrq1", "intrq2";
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@7 {
+				reg = <7>;
+
+				adv7482_ain7: endpoint {
+					remote-endpoint = <&cvbs_con>;
+				};
+			};
+
+			port@8 {
+				reg = <8>;
+
+				adv7482_hdmi: endpoint {
+					remote-endpoint = <&hdmi_in_con>;
+				};
+			};
+
+			port@a {
+				reg = <10>;
+
+				adv7482_txa: endpoint {
+					clock-lanes = <0>;
+					data-lanes = <1 2 3 4>;
+					remote-endpoint = <&csi40_in>;
+				};
+			};
+		};
+	};
+
+	csa_vdd: adc@7c {
+		compatible = "maxim,max9611";
+		reg = <0x7c>;
+
+		shunt-resistor-micro-ohms = <5000>;
+	};
+
+	csa_dvfs: adc@7f {
+		compatible = "maxim,max9611";
+		reg = <0x7f>;
+
+		shunt-resistor-micro-ohms = <5000>;
+	};
+};
+
+&i2c_dvfs {
+	status = "okay";
+
+	clock-frequency = <400000>;
+
+	eeprom@50 {
+		compatible = "rohm,br24t01", "atmel,24c01";
+		reg = <0x50>;
+		pagesize = <8>;
+	};
+};
+
+&ohci0 {
+	dr_mode = "otg";
+	status = "okay";
+};
+
+&pcie_bus_clk {
+	clock-frequency = <100000000>;
+	status = "disabled";
+};
+
+&pciec0 {
+	clocks = <&cpg CPG_MOD 319>, <&versaclock3 4>;
+	status = "okay";
+};
+
+&pfc {
+	pinctrl-0 = <&scif_clk_pins>;
+	pinctrl-names = "default";
+
+	avb_pins: avb {
+		mux {
+			groups = "avb_link", "avb_mdio", "avb_mii";
+			function = "avb";
+		};
+
+		pins_mdio {
+			groups = "avb_mdio";
+			drive-strength = <24>;
+		};
+
+		pins_mii_tx {
+			pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0",
+			       "PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3";
+			drive-strength = <12>;
+		};
+	};
+
+	hscif1_pins: hscif1 {
+		groups = "hscif1_data_a", "hscif1_ctrl_a";
+		function = "hscif1";
+	};
+
+	i2c2_pins: i2c2 {
+		groups = "i2c2_a";
+		function = "i2c2";
+	};
+
+	irq0_pins: irq0 {
+		groups = "intc_ex_irq0";
+		function = "intc_ex";
+	};
+
+	keys_pins: keys {
+		pins = "GP_5_17", "GP_5_20", "GP_5_22";
+		bias-pull-up;
+	};
+
+	pwm1_pins: pwm1 {
+		groups = "pwm1_a";
+		function = "pwm1";
+	};
+
+	scif1_pins: scif1 {
+		groups = "scif1_data_a", "scif1_ctrl";
+		function = "scif1";
+	};
+
+	scif2_pins: scif2 {
+		groups = "scif2_data_a";
+		function = "scif2";
+	};
+
+	scif_clk_pins: scif_clk {
+		groups = "scif_clk_a";
+		function = "scif_clk";
+	};
+
+	sdhi0_pins: sd0 {
+		groups = "sdhi0_data4", "sdhi0_ctrl";
+		function = "sdhi0";
+		power-source = <3300>;
+	};
+
+	sdhi0_pins_uhs: sd0_uhs {
+		groups = "sdhi0_data4", "sdhi0_ctrl";
+		function = "sdhi0";
+		power-source = <1800>;
+	};
+
+	sdhi2_pins: sd2 {
+		groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
+		function = "sdhi2";
+		power-source = <1800>;
+	};
+
+	sound_pins: sound {
+		groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a";
+		function = "ssi";
+	};
+
+	sound_clk_pins: sound_clk {
+		groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clk_c_a",
+			 "audio_clkout_a", "audio_clkout3_a";
+		function = "audio_clk";
+	};
+
+	usb0_pins: usb0 {
+		groups = "usb0";
+		function = "usb0";
+	};
+};
+
+&pwm1 {
+	pinctrl-0 = <&pwm1_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&rcar_sound {
+	pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
+	pinctrl-names = "default";
+
+	/* Single DAI */
+	#sound-dai-cells = <0>;
+
+	/* audio_clkout0/1/2/3 */
+	#clock-cells = <1>;
+	clock-frequency = <12288000 11289600>;
+
+	status = "okay";
+
+	/* update <audio_clk_b> to <cs2500> */
+	clocks = <&cpg CPG_MOD 1005>,
+		 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
+		 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
+		 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
+		 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
+		 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
+		 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
+		 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
+		 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
+		 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
+		 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
+		 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
+		 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
+		 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
+		 <&audio_clk_a>, <&cs2500>,
+		 <&audio_clk_c>,
+		 <&cpg CPG_MOD 922>;
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		rsnd_port0: port@0 {
+			reg = <0>;
+
+			rsnd_endpoint0: endpoint {
+				remote-endpoint = <&ak4619_endpoint>;
+				dai-format = "left_j";
+				bitclock-master = <&rsnd_endpoint0>;
+				frame-master = <&rsnd_endpoint0>;
+				playback = <&ssi0>, <&src0>, <&dvc0>;
+				capture = <&ssi1>, <&src1>, <&dvc1>;
+			};
+		};
+	};
+};
+
+&rwdt {
+	timeout-sec = <60>;
+	status = "okay";
+};
+
+&scif1 {
+	pinctrl-0 = <&scif1_pins>;
+	pinctrl-names = "default";
+
+	uart-has-rtscts;
+	/* Please only enable hscif1 or scif1 */
+	/* status = "okay"; */
+};
+
+&scif2 {
+	pinctrl-0 = <&scif2_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&scif_clk {
+	clock-frequency = <14745600>;
+};
+
+&sdhi0 {
+	pinctrl-0 = <&sdhi0_pins>;
+	pinctrl-1 = <&sdhi0_pins_uhs>;
+	pinctrl-names = "default", "state_uhs";
+
+	vmmc-supply = <&vcc_sdhi0>;
+	vqmmc-supply = <&vccq_sdhi0>;
+	cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
+	wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
+	bus-width = <4>;
+	sd-uhs-sdr50;
+	sd-uhs-sdr104;
+	status = "okay";
+};
+
+&sdhi2 {
+	/* used for on-board 8bit eMMC */
+	pinctrl-0 = <&sdhi2_pins>;
+	pinctrl-1 = <&sdhi2_pins>;
+	pinctrl-names = "default", "state_uhs";
+
+	vmmc-supply = <&reg_3p3v>;
+	vqmmc-supply = <&reg_1p8v>;
+	bus-width = <8>;
+	mmc-hs200-1_8v;
+	no-sd;
+	no-sdio;
+	non-removable;
+	fixed-emmc-driver-type = <1>;
+	full-pwr-cycle-in-suspend;
+	status = "okay";
+};
+
+&ssi1 {
+	shared-pin;
+};
+
+&usb_extal_clk {
+	clock-frequency = <50000000>;
+};
+
+&usb2_phy0 {
+	pinctrl-0 = <&usb0_pins>;
+	pinctrl-names = "default";
+
+	vbus-supply = <&vbus0_usb2>;
+	status = "okay";
+};
+
+&vin0 {
+	status = "okay";
+};
+
+&vin1 {
+	status = "okay";
+};
+
+&vin2 {
+	status = "okay";
+};
+
+&vin3 {
+	status = "okay";
+};
+
+&vin4 {
+	status = "okay";
+};
+
+&vin5 {
+	status = "okay";
+};
+
+&vin6 {
+	status = "okay";
+};
+
+&vin7 {
+	status = "okay";
+};
+
+&vspb {
+	status = "okay";
+};
+
+&vspi0 {
+	status = "okay";
+};

arch/arm/dts/r8a779md.dtsi

@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the R-Car M3Le (R8A779MD) SoC
+ *
+ * Copyright (C) 2025-2026 Renesas Electronics Corp.
+ */
+
+#include "r8a77965.dtsi"
+
+/ {
+	compatible = "renesas,r8a779md", "renesas,r8a77965";
+};
+
+/delete-node/ &csi20;
+/delete-node/ &drif00;
+/delete-node/ &drif01;
+/delete-node/ &drif10;
+/delete-node/ &drif11;
+/delete-node/ &drif20;
+/delete-node/ &drif21;
+/delete-node/ &drif30;
+/delete-node/ &drif31;
+/delete-node/ &du;
+/delete-node/ &ehci1;
+/delete-node/ &hdmi0;
+/delete-node/ &lvds0;
+/delete-node/ &mlp;
+/delete-node/ &ohci1;
+/delete-node/ &pciec1;
+/delete-node/ &sata;
+/delete-node/ &usb2_phy1;
+/delete-node/ &usb3_peri0;
+/delete-node/ &usb3_phy0;
+/delete-node/ &vin0csi20;
+/delete-node/ &vin1csi20;
+/delete-node/ &vin2csi20;
+/delete-node/ &vin3csi20;
+/delete-node/ &vin4csi20;
+/delete-node/ &vin5csi20;
+/delete-node/ &vin6csi20;
+/delete-node/ &vin7csi20;
+/delete-node/ &xhci0;
+
+&sdhi0 {
+	compatible = "renesas,sdhi-r8a779md", "renesas,rcar-gen3-sdhi";
+};
+
+&sdhi1 {
+	compatible = "renesas,sdhi-r8a779md", "renesas,rcar-gen3-sdhi";
+};
+
+&sdhi2 {
+	compatible = "renesas,sdhi-r8a779md", "renesas,rcar-gen3-sdhi";
+};
+
+&sdhi3 {
+	compatible = "renesas,sdhi-r8a779md", "renesas,rcar-gen3-sdhi";
+	no-mmc;
+};

arch/arm/dts/rk3128-evb.dts

@@ -1,99 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2017 Rockchip Electronics Co., Ltd
- */
-
-/dts-v1/;
-
-#include "rk3128.dtsi"
-
-/ {
-	model = "Rockchip RK3128 Evaluation board";
-	compatible = "rockchip,rk3128-evb", "rockchip,rk3128";
-
-	chosen {
-		stdout-path = &uart2;
-	};
-
-	memory@60000000 {
-		device_type = "memory";
-		reg = <0x60000000 0x40000000>;
-	};
-
-	vcc5v0_otg: vcc5v0-otg-drv {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc5v0_otg";
-		gpio = <&gpio0 26 GPIO_ACTIVE_HIGH>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&otg_vbus_drv>;
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-	};
-
-	vcc5v0_host: vcc5v0-host-drv {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc5v0_host";
-		gpio = <&gpio2 23 GPIO_ACTIVE_HIGH>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&host_vbus_drv>;
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		regulator-always-on;
-	};
-};
-
-&emmc {
-	fifo-mode;
-	status = "okay";
-};
-
-&i2c1 {
-	status = "okay";
-
-	hym8563: hym8563@51 {
-		compatible = "haoyu,hym8563";
-		reg = <0x51>;
-		#clock-cells = <0>;
-		clock-frequency = <32768>;
-		clock-output-names = "xin32k";
-	};
-};
-
-&u2phy {
-	status = "okay";
-};
-
-&u2phy_otg {
-	status = "okay";
-};
-
-&u2phy_host {
-	status = "okay";
-};
-
-&usb_host_ehci {
-	status = "okay";
-};
-
-&usb_host_ohci {
-	status = "okay";
-};
-
-&usb_otg {
-	vbus-supply = <&vcc5v0_otg>;
-	status = "okay";
-};
-
-&pinctrl {
-	usb_otg {
-		otg_vbus_drv: host-vbus-drv {
-			rockchip,pins = <0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-	};
-
-	usb_host {
-		host_vbus_drv: host-vbus-drv {
-			rockchip,pins = <2 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-	};
-};

arch/arm/dts/rk3128.dtsi

@@ -1,780 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2017 Rockchip Electronics Co., Ltd
- */
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/pinctrl/rockchip.h>
-#include <dt-bindings/clock/rk3128-cru.h>
-
-/ {
-	compatible = "rockchip,rk3128";
-	rockchip,sram = <&sram>;
-	interrupt-parent = <&gic>;
-	#address-cells = <1>;
-	#size-cells = <1>;
-
-	aliases {
-		gpio0 = &gpio0;
-		gpio1 = &gpio1;
-		gpio2 = &gpio2;
-		gpio3 = &gpio3;
-		i2c0 = &i2c0;
-		i2c1 = &i2c1;
-		i2c2 = &i2c2;
-		i2c3 = &i2c3;
-		spi0 = &spi0;
-		serial0 = &uart0;
-		serial1 = &uart1;
-		serial2 = &uart2;
-		mmc0 = &emmc;
-		mmc1 = &sdmmc;
-	};
-
-	arm-pmu {
-		compatible = "arm,cortex-a7-pmu";
-		interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		enable-method = "rockchip,rk3128-smp";
-
-		cpu0: cpu@0 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a7";
-			reg = <0x0>;
-			operating-points = <
-				/* KHz    uV */
-				 816000 1000000
-			>;
-			#cooling-cells = <2>; /* min followed by max */
-			clock-latency = <40000>;
-			clocks = <&cru ARMCLK>;
-		};
-
-		cpu1: cpu@1 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a7";
-			reg = <0x1>;
-		};
-
-		cpu2: cpu@2 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a7";
-			reg = <0x2>;
-		};
-
-		cpu3: cpu@3 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a7";
-			reg = <0x3>;
-		};
-	};
-
-	cpu_axi_bus: cpu_axi_bus {
-		compatible = "rockchip,cpu_axi_bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges;
-
-		qos {
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges;
-
-			crypto {
-				reg = <0x10128080 0x20>;
-			};
-
-			core {
-				reg = <0x1012a000 0x20>;
-			};
-
-			peri {
-				reg = <0x1012c000 0x20>;
-			};
-
-			gpu {
-				reg = <0x1012d000 0x20>;
-			};
-
-			vpu {
-				reg = <0x1012e000 0x20>;
-			};
-
-			rga {
-				reg = <0x1012f000 0x20>;
-			};
-			ebc {
-				reg = <0x1012f080 0x20>;
-			};
-
-			iep {
-				reg = <0x1012f100 0x20>;
-			};
-
-			lcdc {
-				reg = <0x1012f180 0x20>;
-				rockchip,priority = <3 3>;
-			};
-
-			vip {
-				reg = <0x1012f200 0x20>;
-				rockchip,priority = <3 3>;
-			};
-		};
-
-		msch {
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges;
-
-			msch@10128000 {
-				reg = <0x10128000 0x20>;
-				rockchip,read-latency = <0x3f>;
-			};
-		};
-	};
-
-	psci {
-		compatible      = "arm,psci";
-		method          = "smc";
-		cpu_suspend     = <0x84000001>;
-		cpu_off         = <0x84000002>;
-		cpu_on          = <0x84000003>;
-		migrate         = <0x84000005>;
-	};
-
-	amba {
-		compatible = "arm,amba-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		interrupt-parent = <&gic>;
-		ranges;
-
-		pdma: dma-controller@20078000 {
-			compatible = "arm,pl330", "arm,primecell";
-			reg = <0x20078000 0x4000>;
-			arm,pl330-broken-no-flushp;//2
-			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
-			#dma-cells = <1>;
-			clocks = <&cru ACLK_DMAC>;
-			clock-names = "apb_pclk";
-		};
-	};
-
-	xin24m: xin24m {
-		compatible = "fixed-clock";
-		clock-frequency = <24000000>;
-		clock-output-names = "xin24m";
-		#clock-cells = <0>;
-	};
-
-	xin12m: xin12m {
-		compatible = "fixed-clock";
-		clock-frequency = <12000000>;
-		clock-output-names = "xin12m";
-		#clock-cells = <0>;
-	};
-
-	timer {
-		compatible = "arm,armv7-timer";
-		arm,cpu-registers-not-fw-configured;
-		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
-			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
-		clock-frequency = <24000000>;
-	};
-
-	timer@20044000 {
-		compatible = "arm,armv7-timer";
-		reg = <0x20044000 0xb8>;
-		interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
-		rockchip,broadcast = <1>;
-	};
-
-	watchdog: watchdog@2004c000 {
-		compatible = "rockchip,rk3128-wdt", "snps,dw-wdt";
-		reg = <0x2004c000 0x100>;
-		clocks = <&cru PCLK_WDT>;
-		interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
-		rockchip,irq = <1>;
-		rockchip,timeout = <60>;
-		rockchip,atboot = <1>;
-		rockchip,debug = <0>;
-	};
-
-	reset: reset@20000110 {
-		compatible = "rockchip,reset";
-		reg = <0x20000110 0x24>;
-		#reset-cells = <1>;
-	};
-
-	nandc: nand-controller@10500000 {
-		compatible = "rockchip,rk3128-nfc", "rockchip,rk2928-nfc";
-		reg = <0x10500000 0x4000>;
-		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&nandc_ale &nandc_cle &nandc_wrn &nandc_rdn &nandc_rdy &nandc_cs0 &nandc_data>;
-		clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
-		clock-names = "ahb", "nfc";
-	};
-
-	cru: clock-controller@20000000 {
-		compatible = "rockchip,rk3128-cru";
-		reg = <0x20000000 0x1000>;
-		clocks = <&xin24m>;
-		clock-names = "xin24m";
-		rockchip,grf = <&grf>;
-		#clock-cells = <1>;
-		#reset-cells = <1>;
-		assigned-clocks = <&cru PLL_GPLL>;
-		assigned-clock-rates = <594000000>;
-	};
-
-	uart0: serial@20060000 {
-		compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
-		reg = <0x20060000 0x100>;
-		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
-		reg-shift = <2>;
-		reg-io-width = <4>;
-		clock-frequency = <24000000>;
-		clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
-		clock-names = "baudclk", "apb_pclk";
-		pinctrl-names = "default";
-		pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
-		dmas = <&pdma 2>, <&pdma 3>;
-		#dma-cells = <2>;
-	};
-
-	uart1: serial@20064000 {
-		compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
-		reg = <0x20064000 0x100>;
-		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
-		reg-shift = <2>;
-		reg-io-width = <4>;
-		clock-frequency = <24000000>;
-		clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
-		clock-names = "baudclk", "apb_pclk";
-		pinctrl-names = "default";
-		pinctrl-0 = <&uart1_xfer>;
-		dmas = <&pdma 4>, <&pdma 5>;
-		#dma-cells = <2>;
-	};
-
-	uart2: serial@20068000 {
-		compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
-		reg = <0x20068000 0x100>;
-		interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
-		reg-shift = <2>;
-		reg-io-width = <4>;
-		clock-frequency = <24000000>;
-		clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
-		clock-names = "baudclk", "apb_pclk";
-		pinctrl-names = "default";
-		pinctrl-0 = <&uart2_xfer>;
-		dmas = <&pdma 6>, <&pdma 7>;
-		#dma-cells = <2>;
-	};
-
-	saradc: saradc@2006c000 {
-		compatible = "rockchip,saradc";
-		reg = <0x2006c000 0x100>;
-		interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
-		#io-channel-cells = <1>;
-		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
-		clock-names = "saradc", "apb_pclk";
-		resets = <&cru SRST_SARADC>;
-		reset-names = "saradc-apb";
-		status = "disabled";
-	};
-
-	pwm0: pwm@20050000 {
-		compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
-		reg = <0x20050000 0x10>;
-		#pwm-cells = <3>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pwm0_pin>;
-		clocks = <&cru PCLK_PWM>;
-	};
-
-	pwm1: pwm@20050010 {
-		compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
-		reg = <0x20050010 0x10>;
-		#pwm-cells = <3>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pwm1_pin>;
-		clocks = <&cru PCLK_PWM>;
-	};
-
-	pwm2: pwm@20050020 {
-		compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
-		reg = <0x20050020 0x10>;
-		#pwm-cells = <3>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pwm2_pin>;
-		clocks = <&cru PCLK_PWM>;
-	};
-
-	pwm3: pwm@20050030 {
-		compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
-		reg = <0x20050030 0x10>;
-		#pwm-cells = <3>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pwm3_pin>;
-		clocks = <&cru PCLK_PWM>;
-	};
-
-	sram: sram@10080400 {
-		compatible = "rockchip,rk3128-smp-sram", "mmio-sram";
-		reg = <0x10080400 0x1C00>;
-		map-exec;
-		map-cacheable;
-	};
-
-	pmu: syscon@100a0000 {
-		compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
-		reg = <0x100a0000 0x1000>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-	};
-
-	gic: interrupt-controller@10139000 {
-		compatible = "arm,gic-400";
-		interrupt-controller;
-		#interrupt-cells = <3>;
-		#address-cells = <0>;
-		reg = <0x10139000 0x1000>,
-		      <0x1013a000 0x1000>,
-		      <0x1013c000 0x2000>,
-		      <0x1013e000 0x2000>;
-		interrupts = <GIC_PPI 9 0xf04>;
-	};
-
-	u2phy: usb2phy {
-		compatible = "rockchip,rk3128-usb2phy";
-		reg = <0x017c 0x0c>;
-		rockchip,grf = <&grf>;
-		clocks = <&cru SCLK_OTGPHY0>;
-		clock-names = "phyclk";
-		#clock-cells = <0>;
-		clock-output-names = "usb480m_phy";
-		status = "disabled";
-
-		u2phy_otg: otg-port {
-			#phy-cells = <0>;
-			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "otg-bvalid", "otg-id",
-					  "linestate";
-			status = "disabled";
-		};
-
-		u2phy_host: host-port {
-			#phy-cells = <0>;
-			interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "linestate";
-			status = "disabled";
-		};
-	};
-
-	usb_otg: usb@10180000 {
-		compatible = "rockchip,rk3128-usb", "rockchip,rk3066-usb", "snps,dwc2";
-		reg = <0x10180000 0x40000>;
-		interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&cru HCLK_OTG>;
-		clock-names = "otg";
-		dr_mode = "otg";
-		phys = <&u2phy_otg>;
-		phy-names = "usb2-phy";
-		status = "disabled";
-	};
-
-	usb_host_ehci: usb@101c0000 {
-		compatible = "generic-ehci";
-		reg = <0x101c0000 0x20000>;
-		interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
-		phys = <&u2phy_host>;
-		phy-names = "usb";
-		status = "disabled";
-	};
-
-	usb_host_ohci: usb@101e0000 {
-		compatible = "generic-ohci";
-		reg = <0x101e0000 0x20000>;
-		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
-		phys = <&u2phy_host>;
-		phy-names = "usb";
-		status = "disabled";
-	};
-
-	sdmmc: mmc@10214000 {
-		compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc";
-		reg = <0x10214000 0x4000>;
-		max-frequency = <150000000>;
-		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
-			 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
-		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
-		fifo-depth = <0x100>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
-		bus-width = <4>;
-		status = "disabled";
-	};
-
-	emmc: mmc@1021c000 {
-		compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc";
-		reg = <0x1021c000 0x4000>;
-		max-frequency = <150000000>;
-		interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
-			 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
-		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
-		bus-width = <8>;
-		default-sample-phase = <158>;
-		num-slots = <1>;
-		fifo-depth = <0x100>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
-		resets = <&cru SRST_EMMC>;
-		reset-names = "reset";
-		status = "disabled";
-	};
-
-	i2c0: i2c@20072000 {
-		compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
-		reg = <20072000 0x1000>;
-		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		clock-names = "i2c";
-		clocks = <&cru PCLK_I2C0>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&i2c0_xfer>;
-	};
-
-	i2c1: i2c@20056000 {
-		compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
-		reg = <0x20056000 0x1000>;
-		interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		clock-names = "i2c";
-		clocks = <&cru PCLK_I2C1>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&i2c1_xfer>;
-	};
-
-	i2c2: i2c@2005a000 {
-		compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
-		reg = <0x2005a000 0x1000>;
-		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		clock-names = "i2c";
-		clocks = <&cru PCLK_I2C2>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&i2c2_xfer>;
-	};
-
-	i2c3: i2c@2005e000 {
-		compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
-		reg = <0x2005e000 0x1000>;
-		interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		clock-names = "i2c";
-		clocks = <&cru PCLK_I2C3>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&i2c3_xfer>;
-	};
-
-	spi0: spi@20074000 {
-		compatible = "rockchip,rk3128-spi", "rockchip,rk3066-spi";
-		reg = <0x20074000 0x1000>;
-		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&spi0_txd_mux0 &spi0_rxd_mux0 &spi0_clk_mux0 &spi0_cs0_mux0 &spi0_cs1_mux0>;
-		rockchip,spi-src-clk = <0>;
-		num-cs = <2>;
-		clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
-		clock-names = "spiclk", "apb_pclk";
-		dmas = <&pdma 8>, <&pdma 9>;
-		#dma-cells = <2>;
-		dma-names = "tx", "rx";
-	};
-
-	grf: syscon@20008000 {
-		compatible = "rockchip,rk3128-grf", "syscon";
-		reg = <0x20008000 0x1000>;
-	};
-
-	pinctrl: pinctrl@20008000 {
-		compatible = "rockchip,rk3128-pinctrl";
-		reg = <0x20008000 0xA8>,
-		      <0x200080A8 0x4C>,
-		      <0x20008118 0x20>,
-		      <0x20008100 0x04>;
-		reg-names = "base", "mux", "pull", "drv";
-		rockchip,grf = <&grf>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges;
-
-		gpio0: gpio@2007c000 {
-			compatible = "rockchip,gpio-bank";
-			reg = <0x2007c000 0x100>;
-			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&cru PCLK_GPIO0>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			interrupt-controller;
-			#interrupt-cells = <2>;
-		};
-
-		gpio1: gpio@20080000 {
-			compatible = "rockchip,gpio-bank";
-			reg = <0x20080000 0x100>;
-			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&cru PCLK_GPIO1>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			interrupt-controller;
-			#interrupt-cells = <2>;
-		};
-
-		gpio2: gpio@20084000 {
-			compatible = "rockchip,gpio-bank";
-			reg = <0x20084000 0x100>;
-			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&cru PCLK_GPIO2>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			interrupt-controller;
-			#interrupt-cells = <2>;
-		};
-
-		gpio3: gpio@20088000 {
-			compatible = "rockchip,gpio-bank";
-			reg = <0x20088000 0x100>;
-			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&cru PCLK_GPIO3>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			interrupt-controller;
-			#interrupt-cells = <2>;
-		};
-
-		pcfg_pull_up: pcfg-pull-up {
-			bias-pull-up;
-		};
-
-		pcfg_pull_down: pcfg-pull-down {
-			bias-pull-down;
-		};
-
-		pcfg_pull_none: pcfg-pull-none {
-			bias-disable;
-		};
-
-		emmc {
-			/*
-			 * We run eMMC at max speed; bump up drive strength.
-			 * We also have external pulls, so disable the internal ones.
-			 */
-
-			emmc_clk: emmc-clk {
-				rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>;
-			};
-
-			emmc_cmd: emmc-cmd {
-				rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
-			};
-
-			emmc_pwren: emmc-pwren {
-				rockchip,pins = <2 RK_PA5 2 &pcfg_pull_none>;
-			};
-
-			emmc_bus8: emmc-bus8 {
-				rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>,
-						<1 RK_PD1 2 &pcfg_pull_none>,
-						<1 RK_PD2 2 &pcfg_pull_none>,
-						<1 RK_PD3 2 &pcfg_pull_none>,
-						<1 RK_PD4 2 &pcfg_pull_none>,
-						<1 RK_PD5 2 &pcfg_pull_none>,
-						<1 RK_PD6 2 &pcfg_pull_none>,
-						<1 RK_PD7 2 &pcfg_pull_none>;
-			};
-		};
-
-		nandc{
-			nandc_ale:nandc-ale {
-				rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>;
-			};
-
-			nandc_cle:nandc-cle {
-				rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>;
-			};
-
-			nandc_wrn:nandc-wrn {
-				rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>;
-			};
-
-			nandc_rdn:nandc-rdn {
-				rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>;
-			};
-
-			nandc_rdy:nandc-rdy {
-				rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>;
-			};
-
-			nandc_cs0:nandc-cs0 {
-				rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>;
-			};
-
-			nandc_data: nandc-data {
-				rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>;
-			};
-		};
-
-		uart0 {
-			uart0_xfer: uart0-xfer {
-				rockchip,pins = <0 RK_PC0 1 &pcfg_pull_none>,
-						<0 RK_PC1 1 &pcfg_pull_none>;
-			};
-
-			uart0_cts: uart0-cts {
-				rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>;
-			};
-
-			uart0_rts: uart0-rts {
-				rockchip,pins = <0 RK_PC3 1 &pcfg_pull_none>;
-			};
-		};
-
-		uart1 {
-			uart1_xfer: uart1-xfer {
-				rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>,
-						<2 RK_PC7 1 &pcfg_pull_none>;
-			};
-		};
-
-		uart2 {
-			uart2_xfer: uart2-xfer {
-				rockchip,pins = <1 RK_PC2 2 &pcfg_pull_none>,
-						<1 RK_PC3 2 &pcfg_pull_none>;
-			};
-		};
-
-		sdmmc {
-			sdmmc_clk: sdmmc-clk {
-				rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>;
-			};
-
-			sdmmc_cmd: sdmmc-cmd {
-				rockchip,pins = <1 RK_PC1 1 &pcfg_pull_up>;
-			};
-
-			sdmmc_wp: sdmmc-wp {
-				rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up>;
-			};
-
-			sdmmc_pwren: sdmmc-pwren {
-				rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up>;
-			};
-
-			sdmmc_bus4: sdmmc-bus4 {
-				rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up>,
-						<1 RK_PC3 1 &pcfg_pull_up>,
-						<1 RK_PC4 1 &pcfg_pull_up>,
-						<1 RK_PC5 1 &pcfg_pull_up>;
-			};
-		};
-
-		pwm0 {
-			pwm0_pin: pwm0-pin {
-				rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>;
-			};
-		};
-
-		pwm1 {
-			pwm1_pin: pwm1-pin {
-				rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>;
-			};
-		};
-
-		pwm2 {
-			pwm2_pin: pwm2-pin {
-				rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>;
-			};
-		};
-
-		pwm3 {
-			pwm3_pin: pwm3-pin {
-				rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
-			};
-		};
-
-		i2c0 {
-			i2c0_xfer: i2c0-xfer {
-				rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
-						<0 RK_PA1 1 &pcfg_pull_none>;
-			};
-		};
-
-		i2c1 {
-			i2c1_xfer: i2c1-xfer {
-				rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
-						<0 RK_PA3 1 &pcfg_pull_none>;
-			};
-		};
-
-		i2c2 {
-			i2c2_xfer: i2c2-xfer {
-				rockchip,pins = <2 RK_PC4 3 &pcfg_pull_none>,
-						<2 RK_PC5 3 &pcfg_pull_none>;
-			};
-		};
-
-		i2c3 {
-			i2c3_xfer: i2c3-xfer {
-				rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
-						<0 RK_PA7 1 &pcfg_pull_none>;
-			};
-		};
-
-		spi0 {
-			spi0_txd_mux0:spi0-txd-mux0 {
-				rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
-			};
-
-			spi0_rxd_mux0:spi0-rxd-mux0 {
-				rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
-			};
-
-			spi0_clk_mux0:spi0-clk-mux0 {
-				rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
-			};
-
-			spi0_cs0_mux0:spi0-cs0-mux0 {
-				rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
-			};
-
-			spi0_cs1_mux0:spi0-cs1-mux0 {
-				rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
-			};
-		};
-
-	};
-};

arch/arm/dts/rk3229-evb.dts

@@ -1,256 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-
-/dts-v1/;
-
-#include <dt-bindings/input/input.h>
-#include "rk3229.dtsi"
-
-/ {
-	model = "Rockchip RK3229 Evaluation board";
-	compatible = "rockchip,rk3229-evb", "rockchip,rk3229";
-
-	aliases {
-		mmc0 = &emmc;
-	};
-
-	memory@60000000 {
-		device_type = "memory";
-		reg = <0x60000000 0x40000000>;
-	};
-
-	dc_12v: dc-12v-regulator {
-		compatible = "regulator-fixed";
-		regulator-name = "dc_12v";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <12000000>;
-		regulator-max-microvolt = <12000000>;
-	};
-
-	ext_gmac: ext_gmac {
-		compatible = "fixed-clock";
-		clock-frequency = <125000000>;
-		clock-output-names = "ext_gmac";
-		#clock-cells = <0>;
-	};
-
-	vcc_host: vcc-host-regulator {
-		compatible = "regulator-fixed";
-		enable-active-high;
-		gpio = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&host_vbus_drv>;
-		regulator-name = "vcc_host";
-		regulator-always-on;
-		regulator-boot-on;
-		vin-supply = <&vcc_sys>;
-	};
-
-	vcc_phy: vcc-phy-regulator {
-		compatible = "regulator-fixed";
-		enable-active-high;
-		regulator-name = "vcc_phy";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-		regulator-always-on;
-		regulator-boot-on;
-		vin-supply = <&vccio_1v8>;
-	};
-
-	vcc_sys: vcc-sys-regulator {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc_sys";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		vin-supply = <&dc_12v>;
-	};
-
-	vccio_1v8: vccio-1v8-regulator {
-		compatible = "regulator-fixed";
-		regulator-name = "vccio_1v8";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-		regulator-always-on;
-		vin-supply = <&vcc_sys>;
-	};
-
-	vccio_3v3: vccio-3v3-regulator {
-		compatible = "regulator-fixed";
-		regulator-name = "vccio_3v3";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-always-on;
-		vin-supply = <&vcc_sys>;
-	};
-
-	vdd_arm: vdd-arm-regulator {
-		compatible = "pwm-regulator";
-		pwms = <&pwm1 0 25000 1>;
-		pwm-supply = <&vcc_sys>;
-		regulator-name = "vdd_arm";
-		regulator-min-microvolt = <950000>;
-		regulator-max-microvolt = <1400000>;
-		regulator-always-on;
-		regulator-boot-on;
-	};
-
-	vdd_log: vdd-log-regulator {
-		compatible = "pwm-regulator";
-		pwms = <&pwm2 0 25000 1>;
-		pwm-supply = <&vcc_sys>;
-		regulator-name = "vdd_log";
-		regulator-min-microvolt = <1000000>;
-		regulator-max-microvolt = <1300000>;
-		regulator-always-on;
-		regulator-boot-on;
-	};
-
-	gpio_keys {
-		compatible = "gpio-keys";
-		autorepeat;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pwr_key>;
-
-		power_key: power-key {
-			label = "GPIO Key Power";
-			gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_POWER>;
-			debounce-interval = <100>;
-			wakeup-source;
-		};
-	};
-};
-
-&cpu0 {
-	cpu-supply = <&vdd_arm>;
-};
-
-&cpu1 {
-	cpu-supply = <&vdd_arm>;
-};
-
-&cpu2 {
-	cpu-supply = <&vdd_arm>;
-};
-
-&cpu3 {
-	cpu-supply = <&vdd_arm>;
-};
-
-&emmc {
-	cap-mmc-highspeed;
-	non-removable;
-	status = "okay";
-};
-
-&gmac {
-	assigned-clocks = <&cru SCLK_MAC_EXTCLK>, <&cru SCLK_MAC>;
-	assigned-clock-parents = <&ext_gmac>, <&cru SCLK_MAC_EXTCLK>;
-	clock_in_out = "input";
-	phy-supply = <&vcc_phy>;
-	phy-mode = "rgmii";
-	pinctrl-names = "default";
-	pinctrl-0 = <&rgmii_pins>;
-	snps,reset-gpio = <&gpio2 RK_PD0 GPIO_ACTIVE_LOW>;
-	snps,reset-active-low;
-	snps,reset-delays-us = <0 10000 1000000>;
-	tx_delay = <0x30>;
-	rx_delay = <0x10>;
-	status = "okay";
-};
-
-&io_domains {
-	status = "okay";
-
-	vccio1-supply = <&vccio_3v3>;
-	vccio2-supply = <&vccio_1v8>;
-	vccio4-supply = <&vccio_3v3>;
-};
-
-&pinctrl {
-	keys {
-		pwr_key: pwr-key {
-			rockchip,pins = <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>;
-		};
-	};
-
-	usb {
-		host_vbus_drv: host-vbus-drv {
-			rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-	};
-};
-
-&pwm1 {
-	status = "okay";
-};
-
-&pwm2 {
-	status = "okay";
-};
-
-&tsadc {
-	rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
-	status = "okay";
-};
-
-&uart2 {
-	status = "okay";
-};
-
-&u2phy0 {
-	status = "okay";
-
-	u2phy0_otg: otg-port {
-		status = "okay";
-	};
-
-	u2phy0_host: host-port {
-		phy-supply = <&vcc_host>;
-		status = "okay";
-	};
-};
-
-&u2phy1 {
-	status = "okay";
-
-	u2phy1_otg: otg-port {
-		phy-supply = <&vcc_host>;
-		status = "okay";
-	};
-
-	u2phy1_host: host-port {
-		phy-supply = <&vcc_host>;
-		status = "okay";
-	};
-};
-
-&usb_host0_ehci {
-	status = "okay";
-};
-
-&usb_host0_ohci {
-	status = "okay";
-};
-
-&usb_host1_ehci {
-	status = "okay";
-};
-
-&usb_host1_ohci {
-	status = "okay";
-};
-
-&usb_host2_ehci {
-	status = "okay";
-};
-
-&usb_host2_ohci {
-	status = "okay";
-};
-
-&usb_otg {
-	status = "okay";
-};

arch/arm/dts/rk3229.dtsi

@@ -1,52 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
- */
-
-#include "rk322x.dtsi"
-
-/ {
-	compatible = "rockchip,rk3229";
-
-	/delete-node/ opp-table0;
-
-	cpu0_opp_table: opp-table-0 {
-		compatible = "operating-points-v2";
-		opp-shared;
-
-		opp-408000000 {
-			opp-hz = /bits/ 64 <408000000>;
-			opp-microvolt = <950000>;
-			clock-latency-ns = <40000>;
-			opp-suspend;
-		};
-		opp-600000000 {
-			opp-hz = /bits/ 64 <600000000>;
-			opp-microvolt = <975000>;
-		};
-		opp-816000000 {
-			opp-hz = /bits/ 64 <816000000>;
-			opp-microvolt = <1000000>;
-		};
-		opp-1008000000 {
-			opp-hz = /bits/ 64 <1008000000>;
-			opp-microvolt = <1175000>;
-		};
-		opp-1200000000 {
-			opp-hz = /bits/ 64 <1200000000>;
-			opp-microvolt = <1275000>;
-		};
-		opp-1296000000 {
-			opp-hz = /bits/ 64 <1296000000>;
-			opp-microvolt = <1325000>;
-		};
-		opp-1392000000 {
-			opp-hz = /bits/ 64 <1392000000>;
-			opp-microvolt = <1375000>;
-		};
-		opp-1464000000 {
-			opp-hz = /bits/ 64 <1464000000>;
-			opp-microvolt = <1400000>;
-		};
-	};
-};

arch/arm/dts/rk3576-u-boot.dtsi

@@ -12,7 +12,7 @@
 	};
 
 	chosen {
-		u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci;
+		u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci, &ufshc;
 	};
 
 	dmc {
@@ -81,6 +81,17 @@
 	bootph-some-ram;
 };
 
+#ifdef CONFIG_SPL_UFS_SUPPORT
+&gpio4 {
+	/* This is specifically for GPIO4_D0, which is the only 1.2V capable
+	 * pin on RK3576 available for use as the UFS device reset, thus
+	 * &gpio4 is required for booting from UFS on RK3576.
+	 */
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+#endif
+
 &ioc_grf {
 	bootph-all;
 };
@@ -89,6 +100,11 @@
 	bootph-some-ram;
 };
 
+&pcfg_pull_down {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
 &pcfg_pull_none {
 	bootph-all;
 };
@@ -172,6 +188,21 @@
 	bootph-pre-ram;
 };
 
+&ufshc {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&ufs_refclk {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&ufs_rstgpio {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
 &xin24m {
 	bootph-all;
 };

arch/arm/dts/rk3588-rock-5b-u-boot.dtsi

@@ -19,33 +19,6 @@
 	bootph-some-ram;
 };
 
-&i2c4 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c4m1_xfer>;
-	status = "okay";
-
-	usbc0: usb-typec@22 {
-		compatible = "fcs,fusb302";
-		reg = <0x22>;
-		interrupt-parent = <&gpio3>;
-		interrupts = <RK_PB4 IRQ_TYPE_LEVEL_LOW>;
-		pinctrl-names = "default";
-		status = "okay";
-
-		usb_con: connector {
-			compatible = "usb-c-connector";
-			label = "USB-C";
-			data-role = "dual";
-			power-role = "sink";
-			try-power-role = "sink";
-			op-sink-microwatt = <1000000>;
-			sink-pdos =
-				<PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>,
-				<PDO_VAR(5000, 20000, 5000)>;
-		};
-	};
-};
-
 &saradc {
 	bootph-pre-ram;
 	vdd-microvolts = <1800000>;
@@ -63,20 +36,6 @@
 	};
 };
 
-&u2phy0 {
-	status = "okay";
-};
-
-&u2phy0_otg {
-	status = "okay";
-};
-
-&usbdp_phy0 {
-	status = "okay";
-};
-
-&usb_host0_xhci {
-	dr_mode = "peripheral";
-	maximum-speed = "high-speed";
+&usbc0 {
 	status = "okay";
 };

arch/arm/dts/stm32mp15-scmi-u-boot.dtsi

@@ -21,6 +21,13 @@
 		pinctrl1 = &pinctrl_z;
 	};
 
+	arm_wdt: watchdog {
+		compatible = "arm,smc-wdt";
+		arm,smc-id = <0xbc000000>;
+		timeout-sec = <32>;
+		status = "okay";
+	};
+
 	binman: binman {
 		multiple-images;
 	};
@@ -103,7 +110,7 @@
 };
 
 &iwdg2 {
-	bootph-all;
+	status = "disabled";
 };
 
 /* pre-reloc probe = reserve video frame buffer in video_reserve() */

arch/arm/include/asm/arch-rockchip/bootrom.h

@@ -51,6 +51,7 @@ enum {
 	BROM_BOOTSOURCE_SPINOR = 3,
 	BROM_BOOTSOURCE_SPINAND = 4,
 	BROM_BOOTSOURCE_SD = 5,
+	BROM_BOOTSOURCE_UFS = 7,
 	BROM_BOOTSOURCE_I2C = 8,
 	BROM_BOOTSOURCE_SPI = 9,
 	BROM_BOOTSOURCE_USB = 10,

arch/arm/include/asm/arch-rockchip/cru_rk3576.h

@@ -222,6 +222,20 @@ enum {
 	REF_CLK0_OUT_PLL_DIV_SHIFT	= 0,
 	REF_CLK0_OUT_PLL_DIV_MASK	= 0xff << REF_CLK0_OUT_PLL_DIV_SHIFT,
 
+	/* CRU_CLK_SEL36_CON */
+	CLK_REFCLKO25M_GMAC0_DIV_SHIFT	= 0,
+	CLK_REFCLKO25M_GMAC0_DIV_MASK	= 0x7f << CLK_REFCLKO25M_GMAC0_DIV_SHIFT,
+	CLK_REFCLKO25M_GMAC0_SEL_SHIFT	= 7,
+	CLK_REFCLKO25M_GMAC0_SEL_MASK	= 1 << CLK_REFCLKO25M_GMAC0_SEL_SHIFT,
+	CLK_REFCLKO25M_GMAC0_SEL_GPLL	= 0,
+	CLK_REFCLKO25M_GMAC0_SEL_CPLL	= 1,
+	CLK_REFCLKO25M_GMAC1_DIV_SHIFT	= 8,
+	CLK_REFCLKO25M_GMAC1_DIV_MASK	= 0x7f << CLK_REFCLKO25M_GMAC1_DIV_SHIFT,
+	CLK_REFCLKO25M_GMAC1_SEL_SHIFT	= 15,
+	CLK_REFCLKO25M_GMAC1_SEL_MASK	= 1 << CLK_REFCLKO25M_GMAC1_SEL_SHIFT,
+	CLK_REFCLKO25M_GMAC1_SEL_GPLL	= 0,
+	CLK_REFCLKO25M_GMAC1_SEL_CPLL	= 1,
+
 	/* CRU_CLK_SEL55_CON */
 	ACLK_BUS_ROOT_SEL_SHIFT		= 9,
 	ACLK_BUS_ROOT_SEL_MASK		= 1 << ACLK_BUS_ROOT_SEL_SHIFT,

arch/arm/mach-bcm283x/include/mach/acpi/bcm2711.h

@@ -54,6 +54,7 @@
 #define  MISC_CTRL_CFG_READ_UR_MODE_MASK          0x2000
 #define  MISC_CTRL_MAX_BURST_SIZE_MASK            0x300000
 #define  MISC_CTRL_MAX_BURST_SIZE_128             0x0
+#define  MISC_CTRL_MAX_BURST_SIZE_128_2712		0x100000
 #define  MISC_CTRL_SCB0_SIZE_MASK                 0xf8000000
 
 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO          0x400c
@@ -70,6 +71,7 @@
 #define PCIE_MISC_RC_BAR2_CONFIG_HI               0x4038
 #define PCIE_MISC_RC_BAR3_CONFIG_LO               0x403c
 #define  RC_BAR3_CONFIG_LO_SIZE_MASK                0x1f
+#define PCIE_MISC_PCIE_CTRL			  0x4064
 #define PCIE_MISC_PCIE_STATUS                     0x4068
 #define  STATUS_PCIE_PORT_MASK                      0x80
 #define  STATUS_PCIE_PORT_SHIFT                        7
@@ -108,6 +110,10 @@
 
 #define PCIE_RGR1_SW_INIT_1                   0x9210
 #define PCIE_EXT_CFG_INDEX                    0x9000
+#define  RGR1_SW_INIT_1_PERST_MASK			0x1
+#define  RGR1_SW_INIT_1_PERSTB_MASK			0x4
+#define  RGR1_SW_INIT_1_INIT_MASK			0x2
+
 /* A small window pointing at the ECAM of the device selected by CFG_INDEX */
 #define PCIE_EXT_CFG_DATA                     0x8000
 

arch/arm/mach-bcm283x/init.c

@@ -18,7 +18,7 @@
 #ifdef CONFIG_ARM64
 #include <asm/armv8/mmu.h>
 
-#define MEM_MAP_MAX_ENTRIES (4)
+#define MEM_MAP_MAX_ENTRIES (5)
 
 static struct mm_region bcm283x_mem_map[MEM_MAP_MAX_ENTRIES] = {
 	{
@@ -83,6 +83,14 @@ static struct mm_region bcm2712_mem_map[MEM_MAP_MAX_ENTRIES] = {
 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 			 PTE_BLOCK_NON_SHARE |
 			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		/* Whole PCIe section */
+		.virt = 0x1800000000UL,
+		.phys = 0x1800000000UL,
+		.size = 0x0800000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	}, {
 		/* SoC bus */
 		.virt = 0x107c000000UL,

arch/arm/mach-renesas/Kconfig.rcar3

@@ -164,12 +164,20 @@ config TARGET_ULCB
 	help
 	  Support for Renesas R-Car Gen3 ULCB platform
 
+config TARGET_GEIST
+	bool "Geist board"
+	imply R8A77965
+	imply SYS_MALLOC_F
+	help
+	  Support for Renesas R-Car Gen3 Geist platform
+
 endchoice
 
 source "board/renesas/condor/Kconfig"
 source "board/renesas/draak/Kconfig"
 source "board/renesas/eagle/Kconfig"
 source "board/renesas/ebisu/Kconfig"
+source "board/renesas/geist/Kconfig"
 source "board/renesas/salvator-x/Kconfig"
 source "board/renesas/ulcb/Kconfig"
 source "board/renesas/v3hsk/Kconfig"

arch/arm/mach-renesas/cpu_info.c

@@ -114,6 +114,8 @@ int arch_misc_init(void)
 
 int print_cpuinfo(void)
 {
+	const uintptr_t pfc_base = 0xe6060000;
+	void __iomem *rcar_m3nm3l_ident = (void __iomem *)pfc_base + 0x800;
 	int i = renesas_cpuinfo_idx();
 
 	if (renesas_cpuinfo[i].cpu_type == RENESAS_CPU_TYPE_R8A7796 &&
@@ -123,6 +125,17 @@ int print_cpuinfo(void)
 		return 0;
 	}
 
+	/*
+	 * M3Le PRR ID is the same as M3N , but PFC register 0x800 reads 0
+	 * on M3N and 1 on M3Le. Use this to discern M3Le from M3N .
+	 */
+	if (renesas_cpuinfo[i].cpu_type == RENESAS_CPU_TYPE_R8A77965 &&
+	    readl(rcar_m3nm3l_ident) == 1) {
+		printf("CPU:   Renesas Electronics R8A779MD rev %d.%d\n",
+		       renesas_get_cpu_rev_integer(), renesas_get_cpu_rev_fraction());
+		return 0;
+	}
+
 	printf("CPU:   Renesas Electronics %s rev %d.%d\n",
 		get_cpu_name(i), renesas_get_cpu_rev_integer(),
 		renesas_get_cpu_rev_fraction());

arch/arm/mach-rockchip/Kconfig

@@ -65,6 +65,7 @@ config ROCKCHIP_RK3066
 config ROCKCHIP_RK3128
 	bool "Support Rockchip RK3128"
 	select CPU_V7A
+	imply OF_UPSTREAM
 	imply ROCKCHIP_COMMON_BOARD
 	help
 	  The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7
@@ -108,6 +109,7 @@ config ROCKCHIP_RK322X
 	select TPL_OF_LIBFDT
 	select TPL_HAVE_INIT_STACK if TPL
 	select SPL_DRIVERS_MISC
+	imply OF_UPSTREAM
 	imply ROCKCHIP_COMMON_BOARD
 	imply SPL_SERIAL
 	imply SPL_ROCKCHIP_COMMON_BOARD

arch/arm/mach-rockchip/rk3576/MAINTAINERS

@@ -10,6 +10,12 @@ S:	Maintained
 F:	arch/arm/dts/rk3576-nanopi-m5*
 F:	configs/nanopi-m5-rk3576_defconfig
 
+NANOPI-R76S-RK3576
+M:	Jonas Karlman <jonas@kwiboo.se>
+S:	Maintained
+F:	arch/arm/dts/rk3576-nanopi-r76s*
+F:	configs/nanopi-r76s-rk3576_defconfig
+
 OMNI3576-RK3576
 M:	Jonas Karlman <jonas@kwiboo.se>
 S:	Maintained

arch/arm/mach-rockchip/rk3576/rk3576.c

@@ -49,6 +49,7 @@ const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
 	[BROM_BOOTSOURCE_FSPI0] = "/soc/spi@2a340000/flash@0",
 	[BROM_BOOTSOURCE_FSPI1_M1] = "/soc/spi@2a300000/flash@0",
 	[BROM_BOOTSOURCE_SD] = "/soc/mmc@2a310000",
+	[BROM_BOOTSOURCE_UFS] = "/soc/ufshc@2a2d0000",
 };
 
 static struct mm_region rk3576_mem_map[] = {

arch/arm/mach-rockchip/spl-boot-order.c

@@ -76,6 +76,9 @@ static int spl_node_to_boot_device(int node)
 	if (!uclass_find_device_by_of_offset(UCLASS_SPI_FLASH, node, &parent))
 		return BOOT_DEVICE_SPI;
 
+	if (!uclass_find_device_by_of_offset(UCLASS_UFS, node, &parent))
+		return BOOT_DEVICE_UFS;
+
 	return -1;
 }
 
@@ -231,6 +234,17 @@ int spl_decode_boot_device(u32 boot_device, char *buf, size_t buflen)
 		return -ENODEV;
 	}
 
+	if (boot_device == BOOT_DEVICE_UFS) {
+		ret = uclass_find_device(UCLASS_UFS, 0, &dev);
+		if (ret) {
+			debug("%s: could not find device for UFS: %d\n",
+			      __func__, ret);
+			return ret;
+		}
+
+		return ofnode_get_path(dev_ofnode(dev), buf, buflen);
+	}
+
 #if CONFIG_IS_ENABLED(BLK)
 	dev_num = (boot_device == BOOT_DEVICE_MMC1) ? 0 : 1;
 

arch/arm/mach-stm32mp/include/mach/sys_proto.h

@@ -61,20 +61,20 @@
 /* ID for STM32MP25x = Device Part Number (RPN) (bit31:0) */
 #define CPU_STM32MP257Cxx	0x00002000
 #define CPU_STM32MP255Cxx	0x00082000
-#define CPU_STM32MP253Cxx	0x000B2004
-#define CPU_STM32MP251Cxx	0x000B3065
+#define CPU_STM32MP253Cxx	0x000B300C
+#define CPU_STM32MP251Cxx	0x000B306D
 #define CPU_STM32MP257Axx	0x40002E00
 #define CPU_STM32MP255Axx	0x40082E00
-#define CPU_STM32MP253Axx	0x400B2E04
-#define CPU_STM32MP251Axx	0x400B3E65
+#define CPU_STM32MP253Axx	0x400B3E0C
+#define CPU_STM32MP251Axx	0x400B3E6D
 #define CPU_STM32MP257Fxx	0x80002000
 #define CPU_STM32MP255Fxx	0x80082000
-#define CPU_STM32MP253Fxx	0x800B2004
-#define CPU_STM32MP251Fxx	0x800B3065
+#define CPU_STM32MP253Fxx	0x800B300C
+#define CPU_STM32MP251Fxx	0x800B306D
 #define CPU_STM32MP257Dxx	0xC0002E00
 #define CPU_STM32MP255Dxx	0xC0082E00
-#define CPU_STM32MP253Dxx	0xC00B2E04
-#define CPU_STM32MP251Dxx	0xC00B3E65
+#define CPU_STM32MP253Dxx	0xC00B3E0C
+#define CPU_STM32MP251Dxx	0xC00B3E6D
 
 /* return CPU_STMP32MP...Xxx constants */
 u32 get_cpu_type(void);

board/edgeble/neural-compute-module-6/MAINTAINERS

@@ -5,9 +5,5 @@ F:	board/edgeble/neural-compute-module-6
 F:	include/configs/neural-compute-module-6.h
 F:	configs/neu6a-io-rk3588_defconfig
 F:	configs/neu6b-io-rk3588_defconfig
-F:	arch/arm/dts/rk3588-edgeble-neu6a.dtsi
-F:	arch/arm/dts/rk3588-edgeble-neu6a-io.dts
-F:	arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi
-F:	arch/arm/dts/rk3588-edgeble-neu6b.dtsi
-F:	arch/arm/dts/rk3588-edgeble-neu6b-io.dts
-F:	arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi
+F:	arch/arm/dts/rk3588-edgeble-neu6a-io*
+F:	arch/arm/dts/rk3588-edgeble-neu6b-io*

board/hardkernel/odroid_m1/MAINTAINERS

@@ -4,5 +4,4 @@ S:	Maintained
 F:	board/hardkernel/odroid_m1/
 F:	include/configs/odroid_m1.h
 F:	configs/odroid-m1-rk3568_defconfig
-F:	arch/arm/dts/rk3568-odroid-m1.dts
-F:	arch/arm/dts/rk3568-odroid-m1-u-boot.dtsi
+F:	arch/arm/dts/rk3568-odroid-m1*

board/khadas/khadas-edge2-rk3588s/MAINTAINERS

@@ -3,4 +3,4 @@ M:	Jacobe Zang <jacobe.zang@wesion.com>
 S:	Maintained
 F:	configs/khadas-edge2-rk3588s_defconfig
 F:	include/configs/khadas-edge2-rk3588s.h
-F:	dts/upstream/src/arm64/rockchip/rk3588s-khadas-edge2.dts
+F:	arch/arm/dts/rk3588s-khadas-edge2*

board/pine64/quartz64_rk3566/MAINTAINERS

@@ -9,26 +9,11 @@ F:	configs/quartz64-b-rk3566_defconfig
 F:	configs/soquartz-blade-rk3566_defconfig
 F:	configs/soquartz-cm4-rk3566_defconfig
 F:	configs/soquartz-model-a-rk3566_defconfig
-F:	arch/arm/dts/rk3566-quartz64-a.dts
-F:	arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi
-F:	arch/arm/dts/rk3566-quartz64-b.dts
-F:	arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi
-F:	arch/arm/dts/rk3566-soquartz.dtsi
-F:	arch/arm/dts/rk3566-soquartz-u-boot.dtsi
-F:	arch/arm/dts/rk3566-soquartz-blade.dts
-F:	arch/arm/dts/rk3566-soquartz-blade-u-boot.dtsi
-F:	arch/arm/dts/rk3566-soquartz-cm4.dts
-F:	arch/arm/dts/rk3566-soquartz-cm4-u-boot.dtsi
-F:	arch/arm/dts/rk3566-soquartz-model-a.dts
-F:	arch/arm/dts/rk3566-soquartz-model-a-u-boot.dtsi
+F:	arch/arm/dts/rk3566-quartz64*
+F:	arch/arm/dts/rk3566-soquartz*
 
 PINETAB2-RK3566
 M:	Jonas Karlman <jonas@kwiboo.se>
 S:	Maintained
 F:	configs/pinetab2-rk3566_defconfig
-F:	arch/arm/dts/rk3566-pinetab2.dtsi
-F:	arch/arm/dts/rk3566-pinetab2-u-boot.dtsi
-F:	arch/arm/dts/rk3566-pinetab2-v0.1.dts
-F:	arch/arm/dts/rk3566-pinetab2-v0.1-u-boot.dtsi
-F:	arch/arm/dts/rk3566-pinetab2-v2.0.dts
-F:	arch/arm/dts/rk3566-pinetab2-v2.0-u-boot.dtsi
+F:	arch/arm/dts/rk3566-pinetab2*

board/pine64/quartzpro64-rk3588/MAINTAINERS

@@ -4,5 +4,4 @@ S:	Maintained
 F:	board/pine64/quartzpro64-rk3588
 F:	include/configs/quartzpro64-rk3588.h
 F:	configs/quartzpro64-rk3588_defconfig
-F:	arch/arm/dts/rk3588-quartzpro64.dts
-F:	arch/arm/dts/rk3588-quartzpro64-u-boot.dtsi
+F:	arch/arm/dts/rk3588-quartzpro64*

board/qualcomm/dragonboard410c/configs/chainloaded.config

@@ -4,4 +4,4 @@ CONFIG_TEXT_BASE=0x0
 # CONFIG_REMAKE_ELF is not set
 CONFIG_POSITION_INDEPENDENT=y
 CONFIG_INIT_SP_RELATIVE=y
-CONFIG_SYS_INIT_SP_BSS_OFFSET=524288
+CONFIG_SYS_INIT_SP_BSS_OFFSET=0x80000

board/qualcomm/qcom-phone.env

@@ -39,7 +39,7 @@ bootmenu_5=Reset device=reset
 bootmenu_6=Dump clocks=clk dump; pause
 bootmenu_7=Dump environment=printenv; pause
 bootmenu_8=Board info=bdinfo; pause
-bootmenu_9=Dump bootargs=fdt print /chosen bootargs; pause
+bootmenu_9=Dump bootargs=fdt addr $fdt_addr_r; fdt print /chosen bootargs; pause
 
 # Allow holding the volume down button while U-Boot loads to enter
 # the boot menu

board/radxa/rock5a-rk3588s/MAINTAINERS

@@ -5,5 +5,4 @@ S:	Maintained
 F:	board/radxa/rock5a-rk3588s
 F:	include/configs/rock5a-rk3588s.h
 F:	configs/rock5a-rk3588s_defconfig
-F:	arch/arm/dts/rk3588s-rock-5a.dts
-F:	arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi
+F:	arch/arm/dts/rk3588s-rock-5a*

board/renesas/geist/Kconfig

@@ -0,0 +1,15 @@
+if TARGET_GEIST
+
+config SYS_SOC
+	default "renesas"
+
+config SYS_BOARD
+	default "geist"
+
+config SYS_VENDOR
+	default "renesas"
+
+config SYS_CONFIG_NAME
+	default "geist"
+
+endif

board/renesas/geist/Makefile

@@ -0,0 +1,9 @@
+#
+# Copyright (C) 2025-2026 Renesas Electronics Corporation
+#
+# SPDX-License-Identifier: GPL-2.0-only
+#
+
+ifndef CONFIG_XPL_BUILD
+obj-y	+= geist.o
+endif

board/renesas/geist/geist.c

@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * This file is Geist board support.
+ *
+ * Copyright (C) 2025-2026 Renesas Electronics Corporation
+ */
+
+#include <asm/io.h>
+#include <asm/arch/rcar-mstp.h>
+#include <asm/arch/renesas.h>
+#include <init.h>
+
+#define HSUSB_MSTP704		BIT(4)	/* HSUSB */
+
+/* HSUSB block registers */
+#define HSUSB_REG_LPSTS			0xE6590102
+#define HSUSB_REG_LPSTS_SUSPM_NORMAL	BIT(14)
+#define HSUSB_REG_UGCTRL2		0xE6590184
+#define HSUSB_REG_UGCTRL2_USB0SEL	0x30
+#define HSUSB_REG_UGCTRL2_USB0SEL_EHCI	0x10
+
+int board_init(void)
+{
+	/* USB1 pull-up */
+	setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);
+
+	/* Configure the HSUSB block */
+	mstp_clrbits_le32(SMSTPCR7, SMSTPCR7, HSUSB_MSTP704);
+	/* Choice USB0SEL */
+	clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL,
+			HSUSB_REG_UGCTRL2_USB0SEL_EHCI);
+	/* low power status */
+	setbits_le16(HSUSB_REG_LPSTS, HSUSB_REG_LPSTS_SUSPM_NORMAL);
+
+	return 0;
+}

board/rockchip/evb_rk3229/MAINTAINERS

@@ -1,7 +1,6 @@
 EVB-RK3229
 M:      Kever Yang <kever.yang@rock-chips.com>
 S:      Maintained
-F:	arch/arm/dts/rk3229-evb.dts
 F:	arch/arm/dts/rk3229-evb-u-boot.dtsi
 F:      board/rockchip/evb_rk3229
 F:      include/configs/evb_rk3229.h

board/rockchip/evb_rk3328/MAINTAINERS

@@ -4,8 +4,7 @@ S:      Maintained
 F:      board/rockchip/evb_rk3328
 F:      include/configs/evb_rk3328.h
 F:      configs/evb-rk3328_defconfig
-F:      arch/arm/dts/rk3328-evb.dts
-F:      arch/arm/dts/rk3328-evb-u-boot.dtsi
+F:      arch/arm/dts/rk3328-evb*
 
 GENERIC-RK3328
 M:	Jonas Karlman <jonas@kwiboo.se>
@@ -17,14 +16,12 @@ NANOPI-R2C-RK3328
 M:      Tianling Shen <cnsztl@gmail.com>
 S:      Maintained
 F:      configs/nanopi-r2c-rk3328_defconfig
-F:      arch/arm/dts/rk3328-nanopi-r2c.dts
 F:      arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi
 
 NANOPI-R2C-PLUS-RK3328
 M:      Tianling Shen <cnsztl@gmail.com>
 S:      Maintained
 F:      configs/nanopi-r2c-plus-rk3328_defconfig
-F:      arch/arm/dts/rk3328-nanopi-r2c-plus.dts
 F:      arch/arm/dts/rk3328-nanopi-r2c-plus-u-boot.dtsi
 
 NANOPI-R2S-RK3328
@@ -32,7 +29,6 @@ M:      David Bauer <mail@david-bauer.net>
 S:      Maintained
 F:      configs/nanopi-r2s-rk3328_defconfig
 F:      arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi
-F:      arch/arm/dts/rk3328-nanopi-r2s.dts
 
 NANOPI-R2S-PLUS-RK3328
 M:      Jonas Karlman <jonas@kwiboo.se>
@@ -44,14 +40,12 @@ ORANGEPI-R1-PLUS-RK3328
 M:      Tianling Shen <cnsztl@gmail.com>
 S:      Maintained
 F:      configs/orangepi-r1-plus-rk3328_defconfig
-F:      arch/arm/dts/rk3328-orangepi-r1-plus.dts
 F:      arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
 
 ORANGEPI-R1-PLUS-LTS-RK3328
 M:      Tianling Shen <cnsztl@gmail.com>
 S:      Maintained
 F:      configs/orangepi-r1-plus-lts-rk3328_defconfig
-F:      arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts
 F:      arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
 
 ROC-RK3328-CC
@@ -60,16 +54,14 @@ M:      Chen-Yu Tsai <wens@csie.org>
 R:      Jonas Karlman <jonas@kwiboo.se>
 S:      Maintained
 F:      configs/roc-cc-rk3328_defconfig
-F:      arch/arm/dts/rk3328-roc-cc.dts
-F:      arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
+F:      arch/arm/dts/rk3328-roc-cc*
 
 ROCK64-RK3328
 M:      Matwey V. Kornilov <matwey.kornilov@gmail.com>
 R:      Jonas Karlman <jonas@kwiboo.se>
 S:      Maintained
 F:      configs/rock64-rk3328_defconfig
-F:      arch/arm/dts/rk3328-rock64.dts
-F:      arch/arm/dts/rk3328-rock64-u-boot.dtsi
+F:      arch/arm/dts/rk3328-rock64*
 
 ROCKPIE-RK3328
 M:      Banglang Huang <banglang.huang@foxmail.com>

board/rockchip/evb_rk3399/MAINTAINERS

@@ -24,9 +24,7 @@ KHADAS-EDGE
 M:	Nick Xie <nick@khadas.com>
 S:	Maintained
 F:	configs/khadas-edge-rk3399_defconfig
-F:	arch/arm/dts/rk3399-khadas-edge.dts
-F:	arch/arm/dts/rk3399-khadas-edge.dtsi
-F:	arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi
+F:	arch/arm/dts/rk3399-khadas-edge*
 
 KHADAS-EDGE-CAPTAIN
 M:	Nick Xie <nick@khadas.com>
@@ -56,8 +54,7 @@ NANOPI-M4
 M:	Jagan Teki <jagan@amarulasolutions.com>
 S:	Maintained
 F:	configs/nanopi-m4-rk3399_defconfig
-F:	arch/arm/dts/rk3399-nanopi-m4.dts
-F:	arch/arm/dts/rk3399-nanopi-m4-u-boot.dtsi
+F:	arch/arm/dts/rk3399-nanopi-m4*
 
 NANOPI-M4-2GB
 M:	Jagan Teki <jagan@amarulasolutions.com>

board/rockchip/evb_rk3568/MAINTAINERS

@@ -2,8 +2,7 @@ BANANAPI-BPI-R2-PRO
 M:	Frank Wunderlich <frank-w@public-files.de>
 S:	Maintained
 F:	configs/bpi-r2-pro-rk3568_defconfig
-F:	arch/arm/dts/rk3568-bpi-r2-pro.dts
-F:	arch/arm/dts/rk3568-bpi-r2-pro-u-boot.dtsi
+F:	arch/arm/dts/rk3568-bpi-r2-pro*
 
 EVB-RK3568
 M:	Joseph Chen <chenjh@rock-chips.com>
@@ -11,78 +10,67 @@ S:	Maintained
 F:	board/rockchip/evb_rk3568
 F:	include/configs/evb_rk3568.h
 F:	configs/evb-rk3568_defconfig
-F:	arch/arm/dts/rk3568-evb-u-boot.dtsi
-F:	arch/arm/dts/rk3568-evb.dts
+F:	arch/arm/dts/rk3568-evb*
 
 FASTRHINO-R66S-RK3568
 M:	Tianling Shen <cnsztl@gmail.com>
 R:	Jonas Karlman <jonas@kwiboo.se>
 S:	Maintained
 F:	configs/fastrhino-r66s-rk3568_defconfig
-F:	arch/arm/dts/rk3568-fastrhino-r66s-u-boot.dtsi
+F:	arch/arm/dts/rk3568-fastrhino-r66s*
 
 GENERIC-RK3568
 M:	Jonas Karlman <jonas@kwiboo.se>
 S:	Maintained
 F:	configs/generic-rk3568_defconfig
-F:	arch/arm/dts/rk3568-generic.dts
-F:	arch/arm/dts/rk3568-generic-u-boot.dtsi
+F:	arch/arm/dts/rk3568-generic*
 
 LUBANCAT-2
 M:	Andy Yan <andyshrk@163.com>
 S:	Maintained
 F:	configs/lubancat-2-rk3568_defconfig
-F:	arch/arm/dts/rk3568-lubancat-2.dts
-F:	arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi
+F:	arch/arm/dts/rk3568-lubancat-2*
 
 NANOPI-R3S
 M:	Tianling Shen <cnsztl@gmail.com>
 R:	Jonas Karlman <jonas@kwiboo.se>
 S:	Maintained
 F:	configs/nanopi-r3s-rk3566_defconfig
-F:	arch/arm/dts/rk3566-nanopi-r3s-u-boot.dtsi
+F:	arch/arm/dts/rk3566-nanopi-r3s*
 
 NANOPI-R5C
 M:	Tianling Shen <cnsztl@gmail.com>
 R:	Jonas Karlman <jonas@kwiboo.se>
 S:	Maintained
 F:	configs/nanopi-r5c-rk3568_defconfig
-F:	arch/arm/dts/rk3568-nanopi-r5c.dts
-F:	arch/arm/dts/rk3568-nanopi-r5c-u-boot.dtsi
+F:	arch/arm/dts/rk3568-nanopi-r5c*
 
 NANOPI-R5S
 M:	Tianling Shen <cnsztl@gmail.com>
 R:	Jonas Karlman <jonas@kwiboo.se>
 S:	Maintained
 F:	configs/nanopi-r5s-rk3568_defconfig
-F:	arch/arm/dts/rk3568-nanopi-r5s.dts
-F:	arch/arm/dts/rk3568-nanopi-r5s.dtsi
-F:	arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi
+F:	arch/arm/dts/rk3568-nanopi-r5s*
 
 RADXA-CM3-IO
 M:	Jagan Teki <jagan@amarulasolutions.com>
 R:	Jonas Karlman <jonas@kwiboo.se>
 S:	Maintained
 F:	configs/radxa-cm3-io-rk3566_defconfig
-F:	arch/arm/dts/rk3566-radxa-cm3.dtsi
-F:	arch/arm/dts/rk3566-radxa-cm3-io.dts
-F:	arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi
+F:	arch/arm/dts/rk3566-radxa-cm3-io*
 
 RADXA-E25
 M:	Jonas Karlman <jonas@kwiboo.se>
 S:	Maintained
 F:	configs/radxa-e25-rk3568_defconfig
-F:	arch/arm/dts/rk3568-radxa-cm3i.dtsi
-F:	arch/arm/dts/rk3568-radxa-e25.dts
-F:	arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi
+F:	arch/arm/dts/rk3568-radxa-e25*
 
 ROCK-3A
 M:	Akash Gajjar <gajjar04akash@gmail.com>
 R:	Jonas Karlman <jonas@kwiboo.se>
 S:	Maintained
 F:	configs/rock-3a-rk3568_defconfig
-F:	arch/arm/dts/rk3568-rock-3a.dts
-F:	arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
+F:	arch/arm/dts/rk3568-rock-3a*
 
 ROCK-3B
 M:	Jonas Karlman <jonas@kwiboo.se>
@@ -94,11 +82,11 @@ ROCK-3C
 M:	Jonas Karlman <jonas@kwiboo.se>
 M:	Maxim Moskalets <maximmosk4@gmail.com>
 S:	Maintained
-F:	arch/arm/dts/rk3566-rock-3c-u-boot.dtsi
+F:	arch/arm/dts/rk3566-rock-3c*
 F:	configs/rock-3c-rk3566_defconfig
 
 LCKFB-TaishanPi
 M:	Jiehui He <jiehui.he@foxmail.com>
 S:	Maintained
 F:	configs/lckfb-tspi-rk3566_defconfig
-F:	arch/arm/dts/rk3566-lckfb-tspi-u-boot.dtsi
+F:	arch/arm/dts/rk3566-lckfb-tspi*

board/rockchip/evb_rk3588/MAINTAINERS

@@ -2,16 +2,13 @@ COOLPI-4B-RK3588S
 M:	Andy Yan <andyshrk@163.com>
 S:	Maintained
 F:	configs/coolpi-4b-rk3588s_defconfig
-F:	arch/arm/dts/rk3588s-coolpi-4b.dts
-F:	arch/arm/dts/rk3588s-coolpi-u-boot.dtsi
+F:	arch/arm/dts/rk3588s-coolpi-4b*
 
 COOLPI-CM5-EVB-RK3588
 M:	Andy Yan <andyshrk@163.com>
 S:	Maintained
 F:	configs/coolpi-cm5-evb-rk3588_defconfig
-F:	arch/arm/dts/rk3588-coolpi-cm5.dtsi
-F:	arch/arm/dts/rk3588-coolpi-cm5-evb.dts
-F:	arch/arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi
+F:	arch/arm/dts/rk3588-coolpi-cm5-evb*
 
 EVB-RK3588
 M:	Kever Yang <kever.yang@rock-chips.com>
@@ -19,15 +16,13 @@ S:	Maintained
 F:	board/rockchip/evb_rk3588
 F:	include/configs/evb_rk3588.h
 F:	configs/evb-rk3588_defconfig
-F:	arch/arm/dts/rk3588-evb1-v10.dts
-F:	arch/arm/dts/rk3588-evb1-v10-u-boot.dtsi
+F:	arch/arm/dts/rk3588-evb1-v10*
 
 GENERIC-RK3588
 M:	Jonas Karlman <jonas@kwiboo.se>
 S:	Maintained
 F:	configs/generic-rk3588_defconfig
-F:	arch/arm/dts/rk3588-generic.dts
-F:	arch/arm/dts/rk3588-generic-u-boot.dtsi
+F:	arch/arm/dts/rk3588-generic*
 
 MNT-REFORM2-RK3588
 M:	Peter Robinson <pbrobinson@gmail.com>
@@ -38,24 +33,22 @@ ORANGEPI-5-RK3588
 M:	Jonas Karlman <jonas@kwiboo.se>
 S:	Maintained
 F:	configs/orangepi-5-rk3588s_defconfig
-F:	arch/arm/dts/rk3588s-orangepi-5.dts
 F:	arch/arm/dts/rk3588s-orangepi-5-u-boot.dtsi
 
 ORANGEPI-5-MAX-RK3588
 M:	Ilya Katsnelson <me@0upti.me>
 S:	Maintained
 F:	configs/orangepi-5-max-rk3588_defconfig
-F:	arch/arm/dts/rk3588-orangepi-5-max-u-boot.dtsi
+F:	arch/arm/dts/rk3588-orangepi-5-max*
 
 ORANGEPI-5-PLUS-RK3588
 M:	Jonas Karlman <jonas@kwiboo.se>
 S:	Maintained
 F:	configs/orangepi-5-plus-rk3588_defconfig
-F:	arch/arm/dts/rk3588-orangepi-5-plus.dts
-F:	arch/arm/dts/rk3588-orangepi-5-plus-u-boot.dtsi
+F:	arch/arm/dts/rk3588-orangepi-5-plus*
 
 ORANGEPI-5-RK3588-ULTRA
 M:	Niu Zhihong <zhihong@nzhnb.com>
 S:	Maintained
 F:	configs/orangepi-5-ultra-rk3588_defconfig
-F:	arch/arm/dts/rk3588-orangepi-5-ultra-u-boot.dtsi
+F:	arch/arm/dts/rk3588-orangepi-5-ultra*

board/rockchip/toybrick_rk3588/MAINTAINERS

@@ -4,5 +4,4 @@ S:	Maintained
 F:	board/rockchip/toybrick_rk3588
 F:	include/configs/toybrick_rk3588.h
 F:	configs/toybrick-rk3588_defconfig
-F:	arch/arm/dts/rk3588-toybrick-x0.dts
-F:	arch/arm/dts/rk3588-toybrick-x0-u-boot.dtsi
+F:	arch/arm/dts/rk3588-toybrick-x0*

board/st/common/Makefile

@@ -9,6 +9,7 @@ obj-$(CONFIG_PMIC_STPMIC1) += stpmic1.o
 ifeq ($(CONFIG_ARCH_STM32MP),y)
 obj-$(CONFIG_SET_DFU_ALT_INFO) += stm32mp_dfu.o
 obj-$(CONFIG_$(PHASE_)DFU_VIRT) += stm32mp_dfu_virt.o
+obj-$(CONFIG_FWU_MULTI_BANK_UPDATE) += stm32mp_fwu.o
 endif
 
 obj-$(CONFIG_TYPEC_STUSB160X) += stusb160x.o

board/st/common/stm32mp_fwu.c

@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright (C) 2026 Amarula Solutions, Dario Binacchi <dario.binacchi@amarulasolutions.com>
+ */
+
+#include <fwu.h>
+#include <part_efi.h>
+#include <asm/io.h>
+/**
+ * fwu_plat_get_bootidx() - Get the value of the boot index
+ * @boot_idx: Boot index value
+ *
+ * Get the value of the bank(partition) from which the platform
+ * has booted. This value is passed to U-Boot from the earlier
+ * stage bootloader which loads and boots all the relevant
+ * firmware images
+ *
+ */
+void fwu_plat_get_bootidx(uint *boot_idx)
+{
+	*boot_idx = (readl(TAMP_FWU_BOOT_INFO_REG) >>
+		    TAMP_FWU_BOOT_IDX_OFFSET) & TAMP_FWU_BOOT_IDX_MASK;
+}
+
+int fwu_platform_hook(struct udevice *dev, struct fwu_data *data)
+{
+	uint boot_idx;
+	efi_guid_t boot_uuid, root_uuid;
+	const efi_guid_t boot_type_guid = PARTITION_XBOOTLDR;
+	const efi_guid_t root_type_guid =
+		PARTITION_LINUX_FILE_SYSTEM_DATA_GUID;
+	char uuidbuf[UUID_STR_LEN + 1];
+	int retb, retr;
+
+	fwu_plat_get_bootidx(&boot_idx);
+
+	retb = fwu_mdata_get_image_guid(&boot_uuid, &boot_type_guid, boot_idx);
+	retr = fwu_mdata_get_image_guid(&root_uuid, &root_type_guid, boot_idx);
+
+	if (!retb && !retr) {
+		uuid_bin_to_str(boot_uuid.b, uuidbuf, UUID_STR_FORMAT_GUID);
+		env_set("boot_partuuid", uuidbuf);
+
+		uuid_bin_to_str(root_uuid.b, uuidbuf, UUID_STR_FORMAT_GUID);
+		env_set("root_partuuid", uuidbuf);
+	} else if (!retb && retr) {
+		log_warning("%s: found boot GUID but missing root GUID (%d)\n",
+			    __func__, retr);
+	} else if (!retr && retb) {
+		log_warning("%s: found root GUID but missing boot GUID (%d)\n",
+			    __func__, retb);
+	}
+
+	return 0;
+}

board/st/stm32mp1/stm32mp1.c

@@ -837,24 +837,3 @@ static void board_copro_image_process(ulong fw_image, size_t fw_size)
 }
 
 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_COPRO, board_copro_image_process);
-
-#if defined(CONFIG_FWU_MULTI_BANK_UPDATE)
-
-#include <fwu.h>
-
-/**
- * fwu_plat_get_bootidx() - Get the value of the boot index
- * @boot_idx: Boot index value
- *
- * Get the value of the bank(partition) from which the platform
- * has booted. This value is passed to U-Boot from the earlier
- * stage bootloader which loads and boots all the relevant
- * firmware images
- *
- */
-void fwu_plat_get_bootidx(uint *boot_idx)
-{
-	*boot_idx = (readl(TAMP_FWU_BOOT_INFO_REG) >>
-		    TAMP_FWU_BOOT_IDX_OFFSET) & TAMP_FWU_BOOT_IDX_MASK;
-}
-#endif /* CONFIG_FWU_MULTI_BANK_UPDATE */

board/st/stm32mp2/stm32mp2.c

@@ -188,56 +188,3 @@ void board_quiesce_devices(void)
 {
 	led_boot_off();
 }
-
-#if defined(CONFIG_FWU_MULTI_BANK_UPDATE)
-
-#include <fwu.h>
-
-/**
- * fwu_plat_get_bootidx() - Get the value of the boot index
- * @boot_idx: Boot index value
- *
- * Get the value of the bank(partition) from which the platform
- * has booted. This value is passed to U-Boot from the earlier
- * stage bootloader which loads and boots all the relevant
- * firmware images
- *
- */
-void fwu_plat_get_bootidx(uint *boot_idx)
-{
-	*boot_idx = (readl(TAMP_FWU_BOOT_INFO_REG) >>
-		    TAMP_FWU_BOOT_IDX_OFFSET) & TAMP_FWU_BOOT_IDX_MASK;
-}
-
-int fwu_platform_hook(struct udevice *dev, struct fwu_data *data)
-{
-	uint boot_idx;
-	efi_guid_t boot_uuid, root_uuid;
-	const efi_guid_t boot_type_guid = PARTITION_XBOOTLDR;
-	const efi_guid_t root_type_guid =
-		PARTITION_LINUX_FILE_SYSTEM_DATA_GUID;
-	char uuidbuf[UUID_STR_LEN + 1];
-	int retb, retr;
-
-	fwu_plat_get_bootidx(&boot_idx);
-
-	retb = fwu_mdata_get_image_guid(&boot_uuid, &boot_type_guid, boot_idx);
-	retr = fwu_mdata_get_image_guid(&root_uuid, &root_type_guid, boot_idx);
-
-	if (!retb && !retr) {
-		uuid_bin_to_str(boot_uuid.b, uuidbuf, UUID_STR_FORMAT_GUID);
-		env_set("boot_partuuid", uuidbuf);
-
-		uuid_bin_to_str(root_uuid.b, uuidbuf, UUID_STR_FORMAT_GUID);
-		env_set("root_partuuid", uuidbuf);
-	} else if (!retb && retr) {
-		log_warning("%s: found boot GUID but missing root GUID (%d)\n",
-			    __func__, retr);
-	} else if (!retr && retb) {
-		log_warning("%s: found root GUID but missing boot GUID (%d)\n",
-			    __func__, retb);
-	}
-
-	return 0;
-}
-#endif /* CONFIG_FWU_MULTI_BANK_UPDATE */

board/toradex/verdin-imx95/verdin-imx95.c

@@ -50,10 +50,10 @@ int board_late_init(void)
 }
 
 static const struct ram_alias_check ram_alias_checks[] = {
-	{ (void *)(PHYS_SDRAM + SZ_8G), (void *)(PHYS_SDRAM), SZ_16G },
-	{ (void *)(PHYS_SDRAM + SZ_4G), (void *)(PHYS_SDRAM), SZ_8G },
-	{ (void *)(PHYS_SDRAM + SZ_2G), (void *)(PHYS_SDRAM), SZ_4G },
-	{ (void *)(PHYS_SDRAM + SZ_1G), (void *)(PHYS_SDRAM), SZ_2G },
+	{ (void *)((uintptr_t)PHYS_SDRAM + SZ_8G), (void *)(PHYS_SDRAM), SZ_16G },
+	{ (void *)((uintptr_t)PHYS_SDRAM + SZ_4G), (void *)(PHYS_SDRAM), SZ_8G },
+	{ (void *)((uintptr_t)PHYS_SDRAM + SZ_2G), (void *)(PHYS_SDRAM), SZ_4G },
+	{ (void *)((uintptr_t)PHYS_SDRAM + SZ_1G), (void *)(PHYS_SDRAM), SZ_2G },
 	{ NULL }
 };
 

board/turing/turing-rk1-rk3588/MAINTAINERS

@@ -4,6 +4,4 @@ S:	Maintained
 F:	board/turing/turing-rk1-rk3588
 F:	include/configs/turing-rk1-rk3588.h
 F:	configs/turing-rk1-rk3588_defconfig
-F:	arch/arm/dts/rk3588-turing-rk1.dts
-F:	arch/arm/dts/rk3588-turing-rk1.dtsi
-F:	arch/arm/dts/rk3588-turing-rk1-u-boot.dtsi
+F:	arch/arm/dts/rk3588-turing-rk1*

board/xunlong/orangepi-5-ultra-rk3588/MAINTAINERS

@@ -3,4 +3,4 @@ M:	Niu Zhihong <zhihong@nzhnb.com>
 S:	Maintained
 F:	board/xunlong/orangepi-5-rk3588-ultra
 F:	configs/orangepi-5-ultra-rk3588_defconfig
-F:	arch/arm/dts/rk3588-orangepi-5-ultra.dts
+F:	arch/arm/dts/rk3588-orangepi-5-ultra*

boot/pxe_utils.c

@@ -546,7 +546,7 @@ static int label_boot(struct pxe_context *ctx, struct pxe_label *label)
 	char *zboot_argv[] = { "zboot", NULL, "0", NULL, NULL };
 	char *kernel_addr = NULL;
 	char *initrd_addr_str = NULL;
-	char initrd_filesize[10];
+	char initrd_filesize[17];
 	char initrd_str[28];
 	char mac_str[29] = "";
 	char ip_str[68] = "";

configs/evb-rk3128_defconfig

@@ -8,7 +8,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x60100000
 CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ENV_OFFSET=0x0
-CONFIG_DEFAULT_DEVICE_TREE="rk3128-evb"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3128-evb"
 CONFIG_DM_RESET=y
 CONFIG_ROCKCHIP_RK3128=y
 CONFIG_SYS_BOOTM_LEN=0x4000000
@@ -18,7 +18,7 @@ CONFIG_DEBUG_UART_CLOCK=24000000
 # CONFIG_DEBUG_UART_BOARD_INIT is not set
 CONFIG_DEBUG_UART=y
 CONFIG_FIT=y
-CONFIG_DEFAULT_FDT_FILE="rk3128-evb.dtb"
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3128-evb.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_CMD_GPT=y

configs/evb-rk3229_defconfig

@@ -9,7 +9,7 @@ CONFIG_NR_DRAM_BANKS=2
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x61100000
 CONFIG_ENV_OFFSET=0x3F8000
-CONFIG_DEFAULT_DEVICE_TREE="rk3229-evb"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3229-evb"
 CONFIG_ROCKCHIP_RK322X=y
 CONFIG_TARGET_EVB_RK3229=y
 CONFIG_SPL_STACK_R_ADDR=0x60600000
@@ -24,7 +24,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_USE_PREBOOT=y
-CONFIG_DEFAULT_FDT_FILE="rk3229-evb.dtb"
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3229-evb.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x100000

configs/kontron-sl-mx6ul_defconfig

@@ -92,6 +92,7 @@ CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SPI_FLASH_MTD=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_ETH_PHY=y
 CONFIG_FEC_MXC=y
 CONFIG_MII=y

configs/nanopi-m5-rk3576_defconfig

@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_SKIP_LOWLEVEL_INIT=y
 CONFIG_COUNTER_FREQUENCY=24000000
 CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SPL_GPIO=y
 CONFIG_SF_DEFAULT_SPEED=50000000
 CONFIG_SF_DEFAULT_MODE=0x2000
 CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3576-nanopi-m5"
@@ -19,8 +20,10 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3576-nanopi-m5.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_SPL_MAX_SIZE=0x40000
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_DM_RESET=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
+CONFIG_SPL_UFS_SUPPORT=y
 CONFIG_CMD_MEMINFO=y
 CONFIG_CMD_MEMINFO_MAP=y
 CONFIG_CMD_ADC=y
@@ -30,6 +33,7 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_MISC=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_PCI=y
+CONFIG_CMD_UFS=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_ROCKUSB=y
 CONFIG_CMD_USB_MASS_STORAGE=y
@@ -63,6 +67,7 @@ CONFIG_PHY_ROCKCHIP_USBDP=y
 CONFIG_DM_PMIC=y
 CONFIG_PMIC_RK8XX=y
 CONFIG_REGULATOR_RK8XX=y
+CONFIG_SCSI=y
 CONFIG_BAUDRATE=1500000
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYS_NS16550_MEM32=y
@@ -75,4 +80,6 @@ CONFIG_USB_DWC3_GENERIC=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_USB_FUNCTION_ROCKUSB=y
+CONFIG_UFS=y
+CONFIG_UFS_ROCKCHIP=y
 CONFIG_ERRNO_STR=y

configs/nanopi-r76s-rk3576_defconfig

@@ -0,0 +1,60 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3576-nanopi-r76s"
+CONFIG_ROCKCHIP_RK3576=y
+CONFIG_SYS_LOAD_ADDR=0x40c00800
+CONFIG_DEBUG_UART_BASE=0x2AD40000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_PCI=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3576-nanopi-r76s.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_MAX_SIZE=0x40000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MEMINFO_MAP=y
+CONFIG_CMD_ADC=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MISC=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_RNG=y
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_BUTTON=y
+CONFIG_BUTTON_GPIO=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_RTL8169=y
+CONFIG_PCIE_DW_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_PHY_ROCKCHIP_USBDP=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_ERRNO_STR=y

configs/qcom_qcs615_defconfig

@@ -22,3 +22,5 @@ CONFIG_REMAKE_ELF=y
 CONFIG_TEXT_BASE=0x9fc00000
 
 CONFIG_FASTBOOT_BUF_ADDR=0xa1600000
+
+CONFIG_WATCHDOG_AUTOSTART=y

configs/qcom_qcs9100_defconfig

@@ -14,3 +14,5 @@ CONFIG_ENV_IS_IN_SCSI=y
 CONFIG_ENV_SCSI_PART_UUID="71cb9cd0-acf1-b6cb-ad91-be9572fe11a9"
 # CONFIG_ENV_IS_DEFAULT is not set
 # CONFIG_ENV_IS_NOWHERE is not set
+
+CONFIG_WATCHDOG_AUTOSTART=y

configs/r8a779md_geist_defconfig

@@ -0,0 +1,75 @@
+#include <configs/renesas_rcar3.config>
+
+# CONFIG_OF_UPSTREAM is not set
+
+CONFIG_ARM=y
+CONFIG_ARCH_RENESAS=y
+CONFIG_RCAR_GEN3=y
+CONFIG_COUNTER_FREQUENCY=16666666
+CONFIG_ARCH_CPU_INIT=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xFFFE0000
+CONFIG_DEFAULT_DEVICE_TREE="r8a779md-geist"
+CONFIG_SPL_TEXT_BASE=0xe6338000
+CONFIG_TARGET_GEIST=y
+CONFIG_SPL_HAVE_INIT_STACK=y
+CONFIG_SPL_STACK=0xe6304000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0xe633f000
+CONFIG_SPL_BSS_MAX_SIZE=0x1000
+CONFIG_PCI=y
+CONFIG_SYS_MONITOR_BASE=0x00000000
+# CONFIG_EFI_UNICODE_CAPITALIZATION is not set
+# CONFIG_BOOTSTD is not set
+CONFIG_USE_BOOTARGS=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setexpr dloadaddr ${loadaddr} + 0x200000 && setexpr dloadaddr ${dloadaddr} \\\\& 0xffc00000 && setexpr kloadaddr ${dloadaddr} + 0x200000 && tftp ${dloadaddr} Image-r8a779md-geist.dtb && tftp ${kloadaddr} Image && booti ${kloadaddr} - ${dloadaddr}"
+CONFIG_DEFAULT_FDT_FILE="r8a779md-geist.dtb"
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
+CONFIG_CMD_DFU=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_MULTI_DTB_FIT_LZO=y
+CONFIG_MULTI_DTB_FIT_USER_DEFINED_AREA=y
+CONFIG_OF_DTB_PROPS_REMOVE=y
+CONFIG_OF_REMOVE_PROPS="dmas dma-names interrupt-parent interrupts interrupts-extended interrupt-names interrupt-map interrupt-map-mask iommus"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_MMC_EMMC_HW_PARTITION=2
+CONFIG_DFU_TFTP=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
+CONFIG_SYS_I2C_RCAR_IIC=y
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x70
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_RENESAS_SDHI=y
+CONFIG_DM_MTD=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_RENESAS_RAVB=y
+CONFIG_NVME_PCI=y
+CONFIG_PCI_REGION_MULTI_ENTRY=y
+CONFIG_PCI_RCAR_GEN3=y
+CONFIG_SYSINFO=y
+CONFIG_TEE=y
+CONFIG_OPTEE=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Renesas"
+CONFIG_USB_GADGET_VENDOR_NUM=0x045b
+CONFIG_USB_GADGET_PRODUCT_NUM=0x023c
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_RENESAS_USBHS=y
+CONFIG_USB_STORAGE=y

configs/rock-4d-rk3576_defconfig

@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_SKIP_LOWLEVEL_INIT=y
 CONFIG_COUNTER_FREQUENCY=24000000
 CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SPL_GPIO=y
 CONFIG_SF_DEFAULT_SPEED=50000000
 CONFIG_SF_DEFAULT_MODE=0x2000
 CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3576-rock-4d"
@@ -19,8 +20,10 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3576-rock-4d.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_SPL_MAX_SIZE=0x40000
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_DM_RESET=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
+CONFIG_SPL_UFS_SUPPORT=y
 CONFIG_CMD_MEMINFO=y
 CONFIG_CMD_MEMINFO_MAP=y
 CONFIG_CMD_ADC=y
@@ -30,6 +33,7 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_MISC=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_PCI=y
+CONFIG_CMD_UFS=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_RNG=y
@@ -56,6 +60,7 @@ CONFIG_PHY_ROCKCHIP_USBDP=y
 CONFIG_DM_PMIC=y
 CONFIG_PMIC_RK8XX=y
 CONFIG_REGULATOR_RK8XX=y
+CONFIG_SCSI=y
 CONFIG_BAUDRATE=1500000
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYS_NS16550_MEM32=y
@@ -65,4 +70,6 @@ CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GENERIC=y
+CONFIG_UFS=y
+CONFIG_UFS_ROCKCHIP=y
 CONFIG_ERRNO_STR=y

configs/rpi_arm64_defconfig

@@ -11,6 +11,7 @@ CONFIG_SYS_LOAD_ADDR=0x1000000
 CONFIG_PCI=y
 CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
 CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
+CONFIG_EFI_HTTP_BOOT=y
 CONFIG_BOOTSTD_DEFAULTS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_FDT_SIMPLEFB=y
@@ -26,11 +27,13 @@ CONFIG_CMD_GPIO=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_PCI=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_SNTP=y
+CONFIG_WGET_HTTPS=y
 CONFIG_CMD_EFIDEBUG=y
 CONFIG_CMD_FS_UUID=y
 CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_TFTP_TSIZE=y
+CONFIG_NET_LWIP=y
 CONFIG_DM_DMA=y
 CONFIG_DFU_MMC=y
 CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
@@ -44,6 +47,8 @@ CONFIG_BCMGENET=y
 CONFIG_PCI_BRCMSTB=y
 CONFIG_PINCTRL=y
 # CONFIG_PINCTRL_GENERIC is not set
+CONFIG_RESET_BRCMSTB=y
+CONFIG_RESET_BRCMSTB_RESCAL=y
 CONFIG_DM_RNG=y
 CONFIG_RNG_IPROC200=y
 # CONFIG_REQUIRE_SERIAL_CONSOLE is not set
@@ -64,4 +69,5 @@ CONFIG_SYS_WHITE_ON_BLACK=y
 CONFIG_VIDEO_BCM2835=y
 CONFIG_CONSOLE_SCROLL_LINES=10
 CONFIG_PHYS_TO_BUS=y
+CONFIG_MBEDTLS_LIB=y
 # CONFIG_HEXDUMP is not set

configs/stm32mp13_defconfig

@@ -113,4 +113,6 @@ CONFIG_USB_GADGET_MANUFACTURER="STMicroelectronics"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0483
 CONFIG_USB_GADGET_PRODUCT_NUM=0x5720
 CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_WDT=y
+CONFIG_WDT_ARM_SMC=y
 CONFIG_ERRNO_STR=y

configs/stm32mp15_defconfig

@@ -1,7 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_STM32MP=y
 CONFIG_TFABOOT=y
-CONFIG_SYS_MALLOC_F_LEN=0x80000
+CONFIG_SYS_MALLOC_F_LEN=0x90000
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0100000
 CONFIG_ENV_OFFSET=0x900000
 CONFIG_ENV_SECT_SIZE=0x40000
@@ -169,5 +169,6 @@ CONFIG_BMP_24BPP=y
 CONFIG_BMP_32BPP=y
 CONFIG_WDT=y
 CONFIG_WDT_STM32MP=y
+CONFIG_WDT_ARM_SMC=y
 # CONFIG_BINMAN_FDT is not set
 CONFIG_ERRNO_STR=y

configs/toradex-smarc-imx95_defconfig

@@ -44,6 +44,7 @@ CONFIG_LOG=y
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 # CONFIG_BOARD_INIT is not set
+CONFIG_PCI_INIT_R=y
 CONFIG_SPL_MAX_SIZE=0x30000
 CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_LOAD_IMX_CONTAINER=y

configs/verdin-imx95_defconfig

@@ -45,6 +45,7 @@ CONFIG_LOG=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 # CONFIG_BOARD_INIT is not set
 CONFIG_BOARD_LATE_INIT=y
+CONFIG_PCI_INIT_R=y
 CONFIG_SPL_MAX_SIZE=0x30000
 CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_LOAD_IMX_CONTAINER=y

doc/board/rockchip/rockchip.rst

@@ -143,6 +143,7 @@ List of mainline supported Rockchip boards:
      - ArmSoM Sige5 (sige5-rk3576)
      - Firefly ROC-RK3576-PC (roc-pc-rk3576)
      - FriendlyElec NanoPi M5 (nanopi-m5-rk3576)
+     - FriendlyElec NanoPi R76S (nanopi-r76s-rk3576)
      - Generic RK3576 (generic-rk3576)
      - Luckfox Omni3576 (omni3576-rk3576)
      - Radxa ROCK 4D (rock-4d-rk3576)

doc/board/ti/k3.rst

@@ -651,6 +651,17 @@ Refer (:ref:`U-boot ARMV8 build <k3_rst_include_start_build_steps_uboot>`)
    This will need to be explicitly disabled by changing the boot_targets to
    disallow fallback during testing.
 
+DDR Configuration
+-----------------
+
+The K3 DDRSS driver (drivers/ram/k3-ddrss/k3-ddrss.c) configures the DDR during
+the R5 SPL stage. The driver utilizes an auto-generated configuration file
+containing necessary settings for the DDR. It configures the frequency, timing
+parameters, training algorithms etc. for DDR initialization. The configuration
+DTSI can be generated using the `Sysconfig tool <https://dev.ti.com/sysconfig>`_
+and selecting the software product as "DDR Configuration for \*" as well as the
+required device.
+
 Saving environment
 ------------------
 

doc/develop/release_cycle.rst

@@ -77,7 +77,7 @@ For the next scheduled release, release candidates were made on:
 
 * U-Boot |next_ver|-rc3 was released on Mon 25 May 2026.
 
-.. * U-Boot |next_ver|-rc4 was released on Mon 08 June 2026.
+* U-Boot |next_ver|-rc4 was released on Mon 08 June 2026.
 
 .. * U-Boot |next_ver|-rc5 was released on Mon 22 June 2026.
 

doc/sphinx/requirements.txt

@@ -23,4 +23,4 @@ sphinxcontrib-jquery==4.1
 sphinxcontrib-jsmath==1.0.1
 sphinxcontrib-qthelp==2.0.0
 sphinxcontrib-serializinghtml==2.0.0
-urllib3==2.6.3
+urllib3==2.7.0

drivers/clk/rockchip/clk_rk3528.c

@@ -1335,6 +1335,7 @@ static ulong rk3528_clk_get_rate(struct clk *clk)
 					     DPLL);
 		break;
 
+	case CLK_REF_USB3OTG:
 	case TCLK_EMMC:
 	case TCLK_WDT_NS:
 		rate = OSC_HZ;
@@ -1455,6 +1456,7 @@ static ulong rk3528_clk_set_rate(struct clk *clk, ulong rate)
 		priv->ppll_hz = rockchip_pll_get_rate(&rk3528_pll_clks[PPLL],
 						      priv->cru, PPLL);
 		break;
+	case CLK_REF_USB3OTG:
 	case TCLK_EMMC:
 	case TCLK_WDT_NS:
 		return (rate == OSC_HZ) ? 0 : -EINVAL;

drivers/clk/rockchip/clk_rk3576.c

@@ -1549,6 +1549,24 @@ static ulong rk3576_gmac_get_clk(struct rk3576_clk_priv *priv, ulong clk_id)
 		con = readl(&cru->clksel_con[31]);
 		div = (con & CLK_GMAC1_125M_DIV_MASK) >> CLK_GMAC1_125M_DIV_SHIFT;
 		return DIV_TO_RATE(priv->cpll_hz, div);
+	case REFCLKO25M_GMAC0_OUT:
+		con = readl(&cru->clksel_con[36]);
+		div = (con & CLK_REFCLKO25M_GMAC0_DIV_MASK) >> CLK_REFCLKO25M_GMAC0_DIV_SHIFT;
+		src = (con & CLK_REFCLKO25M_GMAC0_SEL_MASK) >> CLK_REFCLKO25M_GMAC0_SEL_SHIFT;
+		if (src == CLK_REFCLKO25M_GMAC0_SEL_CPLL)
+			p_rate = priv->cpll_hz;
+		else
+			p_rate = priv->gpll_hz;
+		return DIV_TO_RATE(p_rate, div);
+	case REFCLKO25M_GMAC1_OUT:
+		con = readl(&cru->clksel_con[36]);
+		div = (con & CLK_REFCLKO25M_GMAC1_DIV_MASK) >> CLK_REFCLKO25M_GMAC1_DIV_SHIFT;
+		src = (con & CLK_REFCLKO25M_GMAC1_SEL_MASK) >> CLK_REFCLKO25M_GMAC1_SEL_SHIFT;
+		if (src == CLK_REFCLKO25M_GMAC1_SEL_CPLL)
+			p_rate = priv->cpll_hz;
+		else
+			p_rate = priv->gpll_hz;
+		return DIV_TO_RATE(p_rate, div);
 	default:
 		return -ENOENT;
 	}
@@ -1608,6 +1626,34 @@ static ulong rk3576_gmac_set_clk(struct rk3576_clk_priv *priv,
 			     CLK_GMAC1_125M_DIV_MASK,
 			     (div - 1) << CLK_GMAC1_125M_DIV_SHIFT);
 		break;
+	case REFCLKO25M_GMAC0_OUT:
+		if (!(priv->gpll_hz % rate)) {
+			src = CLK_REFCLKO25M_GMAC0_SEL_GPLL;
+			div = priv->gpll_hz / rate;
+		} else {
+			src = CLK_REFCLKO25M_GMAC0_SEL_CPLL;
+			div = priv->cpll_hz / rate;
+		}
+		rk_clrsetreg(&cru->clksel_con[36],
+			     CLK_REFCLKO25M_GMAC0_SEL_MASK |
+			     CLK_REFCLKO25M_GMAC0_DIV_MASK,
+			     src << CLK_REFCLKO25M_GMAC0_SEL_SHIFT |
+			     (div - 1) << CLK_REFCLKO25M_GMAC0_DIV_SHIFT);
+		break;
+	case REFCLKO25M_GMAC1_OUT:
+		if (!(priv->gpll_hz % rate)) {
+			src = CLK_REFCLKO25M_GMAC1_SEL_GPLL;
+			div = priv->gpll_hz / rate;
+		} else {
+			src = CLK_REFCLKO25M_GMAC1_SEL_CPLL;
+			div = priv->cpll_hz / rate;
+		}
+		rk_clrsetreg(&cru->clksel_con[36],
+			     CLK_REFCLKO25M_GMAC1_SEL_MASK |
+			     CLK_REFCLKO25M_GMAC1_DIV_MASK,
+			     src << CLK_REFCLKO25M_GMAC1_SEL_SHIFT |
+			     (div - 1) << CLK_REFCLKO25M_GMAC1_DIV_SHIFT);
+		break;
 	default:
 		return -ENOENT;
 	}
@@ -1987,6 +2033,8 @@ static ulong rk3576_clk_get_rate(struct clk *clk)
 	case HCLK_SDIO:
 		rate = rk3576_mmc_get_clk(priv, clk->id);
 		break;
+	case CLK_REF_USB3OTG0:
+	case CLK_REF_USB3OTG1:
 	case TCLK_EMMC:
 	case TCLK_WDT0:
 		rate = OSC_HZ;
@@ -2014,6 +2062,8 @@ static ulong rk3576_clk_get_rate(struct clk *clk)
 	case CLK_GMAC1_PTP_REF:
 	case CLK_GMAC0_125M_SRC:
 	case CLK_GMAC1_125M_SRC:
+	case REFCLKO25M_GMAC0_OUT:
+	case REFCLKO25M_GMAC1_OUT:
 		rate = rk3576_gmac_get_clk(priv, clk->id);
 		break;
 	case CLK_UART_FRAC_0:
@@ -2151,6 +2201,8 @@ static ulong rk3576_clk_set_rate(struct clk *clk, ulong rate)
 	case HCLK_SDIO:
 		ret = rk3576_mmc_set_clk(priv, clk->id, rate);
 		break;
+	case CLK_REF_USB3OTG0:
+	case CLK_REF_USB3OTG1:
 	case TCLK_EMMC:
 	case TCLK_WDT0:
 		ret = OSC_HZ;
@@ -2193,6 +2245,8 @@ static ulong rk3576_clk_set_rate(struct clk *clk, ulong rate)
 	case CLK_GMAC1_PTP_REF:
 	case CLK_GMAC0_125M_SRC:
 	case CLK_GMAC1_125M_SRC:
+	case REFCLKO25M_GMAC0_OUT:
+	case REFCLKO25M_GMAC1_OUT:
 		ret = rk3576_gmac_set_clk(priv, clk->id, rate);
 		break;
 	case CLK_UART_FRAC_0:

drivers/cpu/imx8_cpu.c

@@ -222,7 +222,7 @@ static int cpu_imx_get_desc(const struct udevice *dev, char *buf, int size)
 	ret = snprintf(buf, size, "NXP i.MX%s Rev%s %s at %u MHz",
 		       plat->type, plat->rev, plat->name, plat->freq_mhz);
 
-	if (IS_ENABLED(CONFIG_IMX_TMU)) {
+	if (!IS_ENABLED(CONFIG_IMX8)) { /* imx8 does not have segment fuse */
 		switch (get_cpu_temp_grade(&minc, &maxc)) {
 		case TEMP_AUTOMOTIVE:
 			grade = "Automotive temperature grade";
@@ -231,7 +231,10 @@ static int cpu_imx_get_desc(const struct udevice *dev, char *buf, int size)
 			grade = "Industrial temperature grade";
 			break;
 		case TEMP_EXTCOMMERCIAL:
-			grade = "Extended Consumer temperature grade";
+			if (IS_ENABLED(CONFIG_ARCH_IMX9))
+				grade = "Extended Industrial temperature grade";
+			else
+				grade = "Extended Consumer temperature grade";
 			break;
 		default:
 			grade = "Consumer temperature grade";

drivers/gpio/qcom_pmic_gpio.c

@@ -344,7 +344,6 @@ static int qcom_gpio_probe(struct udevice *dev)
 static const struct udevice_id qcom_gpio_ids[] = {
 	{ .compatible = "qcom,pm8916-gpio" },
 	{ .compatible = "qcom,pm8994-gpio" },	/* 22 GPIO's */
-	{ .compatible = "qcom,pm8998-gpio" },
 	{ .compatible = "qcom,pms405-gpio" },
 	{ .compatible = "qcom,pm6125-gpio" },
 	{ .compatible = "qcom,pm8150-gpio" },

drivers/gpio/qcom_spmi_gpio.c

@@ -752,6 +752,7 @@ static const struct udevice_id qcom_spmi_pmic_gpio_ids[] = {
 	{ .compatible = "qcom,pm8550b-gpio" },
 	{ .compatible = "qcom,pm8550ve-gpio" },
 	{ .compatible = "qcom,pm8550vs-gpio" },
+	{ .compatible = "qcom,pm8998-gpio" },
 	{ .compatible = "qcom,pmk8550-gpio" },
 	{ .compatible = "qcom,pmr735d-gpio" },
 	{ }

drivers/mailbox/Kconfig

@@ -32,6 +32,8 @@ config MPFS_MBOX
 	bool "Enable MPFS system controller support"
 	depends on DM_MAILBOX && ARCH_RV64I
 	select DEVRES
+	depends on SYSCON
+	depends on REGMAP
 	help
 	  Enable support for the mailboxes that provide a communication
 	  channel with the system controller integrated on PolarFire SoC.

drivers/mailbox/mpfs-mbox.c

@@ -13,19 +13,21 @@
 #include <dm/device-internal.h>
 #include <dm/device.h>
 #include <dm/device_compat.h>
-#include <dm/devres.h>
 #include <dm/ofnode.h>
 #include <linux/bitops.h>
 #include <linux/compat.h>
-#include <linux/io.h>
-#include <linux/ioport.h>
+#include <linux/err.h>
+#include <linux/errno.h>
 #include <log.h>
 #include <mailbox-uclass.h>
-#include <malloc.h>
 #include <mpfs-mailbox.h>
+#include <regmap.h>
+#include <syscon.h>
 
 #define SERVICES_CR_OFFSET 0x50u
 #define SERVICES_SR_OFFSET 0x54u
+#define MESSAGE_INT_OFFSET 0x18cu
+#define MAILBOX_REG_OFFSET 0x800u
 
 #define SERVICE_CR_REQ_MASK 0x1u
 #define SERVICE_SR_BUSY_MASK 0x2u
@@ -35,17 +37,18 @@
 
 struct mpfs_mbox {
 	struct udevice *dev;
-	void __iomem *ctrl_base;
 	void __iomem *mbox_base;
-	struct mbox_chan *chan;
+	void __iomem *int_reg;
+	struct regmap *control_scb;
+	struct regmap *sysreg_scb;
 };
 
 static bool mpfs_mbox_busy(struct mbox_chan *chan)
 {
 	struct mpfs_mbox *mbox = dev_get_priv(chan->dev);
-	uint16_t status;
+	u32 status;
 
-	status = readl(mbox->ctrl_base + SERVICES_SR_OFFSET);
+	regmap_read(mbox->control_scb, SERVICES_SR_OFFSET, &status);
 
 	return status & SERVICE_SR_BUSY_MASK;
 }
@@ -80,14 +83,15 @@ static int mpfs_mbox_send(struct mbox_chan *chan, const void *data)
 
 	cmd_shifted = msg->cmd_opcode << SERVICE_CR_COMMAND_SHIFT;
 	cmd_shifted |= SERVICE_CR_REQ_MASK;
-	writel(cmd_shifted, mbox->ctrl_base + SERVICES_CR_OFFSET);
+
+	regmap_write(mbox->control_scb, SERVICES_CR_OFFSET, cmd_shifted);
 
 	do {
-		value = readl(mbox->ctrl_base + SERVICES_CR_OFFSET);
+		regmap_read(mbox->control_scb, SERVICES_CR_OFFSET, &value);
 	} while (SERVICE_CR_REQ_MASK == (value & SERVICE_CR_REQ_MASK));
 
 	do {
-		value = readl(mbox->ctrl_base + SERVICES_SR_OFFSET);
+		regmap_read(mbox->control_scb, SERVICES_SR_OFFSET, &value);
 	} while (SERVICE_SR_BUSY_MASK == (value & SERVICE_SR_BUSY_MASK));
 
 	msg->response->resp_status = (value >> SERVICE_SR_STATUS_SHIFT);
@@ -118,6 +122,11 @@ static int mpfs_mbox_recv(struct mbox_chan *chan, void *data)
 	for (idx = 0; idx < response->resp_size; idx++)
 		*((u8 *)(response->resp_msg) + idx) = readb(mbox->mbox_base + msg->resp_offset  + idx);
 
+	if (mbox->sysreg_scb)
+		regmap_write(mbox->sysreg_scb, MESSAGE_INT_OFFSET, 0);
+	else
+		writel_relaxed(0, mbox->int_reg);
+
 	return 0;
 }
 
@@ -126,42 +135,71 @@ static const struct mbox_ops mpfs_mbox_ops = {
 	.recv = mpfs_mbox_recv,
 };
 
-static int mpfs_mbox_probe(struct udevice *dev)
+/*
+ * Use global compatible lookup instead of phandles, as U-Boot may run
+ * with a reduced or firmware-provided device tree where mailbox syscon
+ * phandle properties are not guaranteed to be present.
+ */
+static int mpfs_mbox_syscon_probe(struct udevice *dev, struct mpfs_mbox *mbox)
 {
-	struct mpfs_mbox *mbox;
-	struct resource regs;
 	ofnode node;
-	int ret;
 
-	node = dev_ofnode(dev);
+	node = ofnode_by_compatible(ofnode_null(), "microchip,mpfs-control-scb");
+	if (!ofnode_valid(node))
+		return -ENODEV;
 
-	mbox = devm_kzalloc(dev, sizeof(*mbox), GFP_KERNEL);
-	if (!mbox)
-		return -ENOMEM;
+	mbox->control_scb = syscon_node_to_regmap(node);
+	if (IS_ERR(mbox->control_scb))
+		return PTR_ERR(mbox->control_scb);
 
-	ret = ofnode_read_resource(node, 0, &regs);
-	if (ret) {
-		dev_err(dev, "No reg property for controller base\n");
-		return ret;
-	};
+	node = ofnode_by_compatible(ofnode_null(), "microchip,mpfs-sysreg-scb");
+	if (!ofnode_valid(node))
+		return -ENODEV;
 
-	mbox->ctrl_base = devm_ioremap(dev, regs.start, regs.start - regs.end);
+	mbox->sysreg_scb = syscon_node_to_regmap(node);
+	if (IS_ERR(mbox->sysreg_scb))
+		return PTR_ERR(mbox->sysreg_scb);
 
-	ret = ofnode_read_resource(node, 2, &regs);
-	if (ret) {
-		dev_err(dev, "No reg property for mailbox base\n");
-		return ret;
-	};
-
-	mbox->mbox_base = devm_ioremap(dev, regs.start, regs.start - regs.end);
-
-	mbox->dev = dev;
-	dev_set_priv(dev, mbox);
-	mbox->chan->con_priv = mbox;
+	mbox->mbox_base = dev_read_addr_ptr(dev);
+	if (!mbox->mbox_base)
+		return -EINVAL;
 
 	return 0;
 }
 
+static int mpfs_mbox_legacy_probe(struct udevice *dev, struct mpfs_mbox *mbox)
+{
+	int ret;
+
+	ret = regmap_init_mem_index(dev_ofnode(dev), &mbox->control_scb, 0);
+	if (ret)
+		return ret;
+
+	mbox->mbox_base = dev_read_addr_index_ptr(dev, 2);
+	if (!mbox->mbox_base)
+		mbox->mbox_base = dev_read_addr_index_ptr(dev, 0) + MAILBOX_REG_OFFSET;
+
+	mbox->int_reg = dev_read_addr_index_ptr(dev, 1);
+	if (!mbox->int_reg)
+		return -EINVAL;
+
+	return 0;
+}
+
+static int mpfs_mbox_probe(struct udevice *dev)
+{
+	struct mpfs_mbox *mbox = dev_get_priv(dev);
+	int ret;
+
+	mbox->dev = dev;
+
+	ret = mpfs_mbox_syscon_probe(dev, mbox);
+	if (!ret)
+		return 0;
+
+	return mpfs_mbox_legacy_probe(dev, mbox);
+}
+
 static const struct udevice_id mpfs_mbox_ids[] = {
 	{.compatible = "microchip,mpfs-mailbox"},
 	{ }
@@ -174,4 +212,4 @@ U_BOOT_DRIVER(mpfs_mbox) = {
 	.probe = mpfs_mbox_probe,
 	.priv_auto = sizeof(struct mpfs_mbox),
 	.ops = &mpfs_mbox_ops,
-};
+};

drivers/mmc/bcm2835_sdhci.c

@@ -219,6 +219,10 @@ static int bcm2835_sdhci_probe(struct udevice *dev)
 	host->mmc = &plat->mmc;
 	host->mmc->dev = dev;
 
+	ret = mmc_of_parse(dev, &plat->cfg);
+	if (ret)
+		return ret;
+
 	ret = sdhci_setup_cfg(&plat->cfg, host, emmc_freq, MIN_FREQ);
 	if (ret) {
 		debug("%s: Failed to setup SDHCI (err=%d)\n", __func__, ret);

drivers/mmc/bcmstb_sdhci.c

@@ -56,7 +56,7 @@ struct sdhci_brcmstb_dev_priv {
 
 static int sdhci_brcmstb_init_2712(struct udevice *dev)
 {
-	struct sdhci_host *host = dev_get_priv(dev);
+	struct sdhci_bcmstb_plat *plat = dev_get_plat(dev);
 	void *cfg_regs;
 	u32 reg;
 
@@ -65,8 +65,8 @@ static int sdhci_brcmstb_init_2712(struct udevice *dev)
 	if (!cfg_regs)
 		return -ENOENT;
 
-	if ((host->mmc->host_caps & MMC_CAP_NONREMOVABLE) ||
-	    (host->mmc->host_caps & MMC_CAP_NEEDS_POLL)) {
+	if ((plat->cfg.host_caps & MMC_CAP_NONREMOVABLE) ||
+	    (plat->cfg.host_caps & MMC_CAP_NEEDS_POLL)) {
 		/* Force presence */
 		reg = readl(cfg_regs + SDIO_CFG_CTRL);
 		reg &= ~SDIO_CFG_CTRL_SDCD_N_TEST_LEV;

drivers/net/ti/icssg_prueth.c

@@ -496,14 +496,15 @@ static int prueth_port_probe(struct udevice *dev)
 {
 	struct prueth_priv *priv = dev_get_priv(dev);
 	struct prueth *prueth;
-	char portname[15];
+	char portname[64];
 	int ret;
 
 	priv->dev = dev;
 	prueth = dev_get_priv(dev->parent);
 	priv->prueth = prueth;
 
-	sprintf(portname, "%s-%s", dev->parent->name, dev->name);
+	snprintf(portname, sizeof(portname), "%s-%s", dev->parent->name, dev->name);
+	portname[sizeof(portname) - 1] = '\0';
 
 	device_set_name(dev, portname);
 

drivers/nvme/nvme.c

@@ -27,6 +27,23 @@
 #define IO_TIMEOUT		30
 #define MAX_PRP_POOL		512
 
+/**
+ * nvme_invalidate_cache_aligned() - invalidate cache with proper alignment
+ *
+ * Aligns cache invalidation to cacheline boundaries to ensure correct
+ * behavior even when the DMA buffer is not aligned to page boundaries.
+ *
+ * @addr:	The start address of the buffer
+ * @length:	The length of the buffer in bytes
+ */
+static inline void nvme_invalidate_cache_aligned(uintptr_t addr, int length)
+{
+	uintptr_t start_addr = addr & ~(ARCH_DMA_MINALIGN - 1);
+	uintptr_t end_addr = ALIGN(addr + length, ARCH_DMA_MINALIGN);
+
+	invalidate_dcache_range(start_addr, end_addr);
+}
+
 static int nvme_wait_csts(struct nvme_dev *dev, u32 mask, u32 val)
 {
 	int timeout;
@@ -182,8 +199,10 @@ static int nvme_submit_sync_cmd(struct nvme_queue *nvmeq,
 		if ((status & 0x01) == phase)
 			break;
 		if (timeout_us > 0 && (timer_get_us() - start_time)
-		    >= timeout_us)
+		    >= timeout_us) {
+			pr_warn("nvme: cmd %#x timed out\n", cmd->common.command_id);
 			return -ETIMEDOUT;
+		}
 	}
 
 	ops = (struct nvme_ops *)nvmeq->dev->udev->driver->ops;
@@ -281,11 +300,6 @@ static int nvme_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
 	return nvme_submit_admin_cmd(dev, &c, NULL);
 }
 
-static int nvme_delete_sq(struct nvme_dev *dev, u16 sqid)
-{
-	return nvme_delete_queue(dev, nvme_admin_delete_sq, sqid);
-}
-
 static int nvme_delete_cq(struct nvme_dev *dev, u16 cqid)
 {
 	return nvme_delete_queue(dev, nvme_admin_delete_cq, cqid);
@@ -456,6 +470,7 @@ int nvme_identify(struct nvme_dev *dev, unsigned nsid,
 	u32 page_size = dev->page_size;
 	int offset = dma_addr & (page_size - 1);
 	int length = sizeof(struct nvme_id_ctrl);
+	dma_addr_t orig_dma_addr = dma_addr;
 	int ret;
 
 	memset(&c, 0, sizeof(c));
@@ -473,13 +488,13 @@ int nvme_identify(struct nvme_dev *dev, unsigned nsid,
 
 	c.identify.cns = cpu_to_le32(cns);
 
-	invalidate_dcache_range(dma_addr,
-				dma_addr + sizeof(struct nvme_id_ctrl));
+	nvme_invalidate_cache_aligned((uintptr_t)orig_dma_addr,
+				      sizeof(struct nvme_id_ctrl));
 
 	ret = nvme_submit_admin_cmd(dev, &c, NULL);
 	if (!ret)
-		invalidate_dcache_range(dma_addr,
-					dma_addr + sizeof(struct nvme_id_ctrl));
+		nvme_invalidate_cache_aligned((uintptr_t)orig_dma_addr,
+					      sizeof(struct nvme_id_ctrl));
 
 	return ret;
 }
@@ -545,20 +560,19 @@ static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
 	nvmeq->cq_vector = qid - 1;
 	result = nvme_alloc_cq(dev, qid, nvmeq);
 	if (result < 0)
-		goto release_cq;
+		goto release_ret;
 
 	result = nvme_alloc_sq(dev, qid, nvmeq);
 	if (result < 0)
-		goto release_sq;
+		goto release_cq;
 
 	nvme_init_queue(nvmeq, qid);
 
 	return result;
 
- release_sq:
-	nvme_delete_sq(dev, qid);
  release_cq:
 	nvme_delete_cq(dev, qid);
+ release_ret:
 
 	return result;
 }
@@ -868,14 +882,14 @@ int nvme_init(struct udevice *udev)
 	if (!ndev->prp_pool) {
 		ret = -ENOMEM;
 		printf("Error: %s: Out of memory!\n", udev->name);
-		goto free_nvme;
+		goto free_queue;
 	}
 	ndev->prp_entry_num = MAX_PRP_POOL >> 3;
 
 	ret = nvme_setup_io_queues(ndev);
 	if (ret) {
 		log_debug("Unable to setup I/O queues(err=%dE)\n", ret);
-		goto free_queue;
+		goto free_prp_pool;
 	}
 
 	nvme_get_info_from_identify(ndev);
@@ -885,7 +899,7 @@ int nvme_init(struct udevice *udev)
 	id = memalign(ndev->page_size, sizeof(struct nvme_id_ns));
 	if (!id) {
 		ret = -ENOMEM;
-		goto free_queue;
+		goto free_prp_pool;
 	}
 
 	for (int i = 1; i <= ndev->nn; i++) {
@@ -930,6 +944,8 @@ int nvme_init(struct udevice *udev)
 
 free_id:
 	free(id);
+free_prp_pool:
+	free((void *)ndev->prp_pool);
 free_queue:
 	free((void *)ndev->queues);
 free_nvme:

drivers/pci/pcie_brcmstb.c

@@ -21,6 +21,7 @@
 #include <linux/bitfield.h>
 #include <linux/log2.h>
 #include <linux/iopoll.h>
+#include <reset.h>
 
 /* PCIe parameters */
 #define BRCM_NUM_PCIE_OUT_WINS				4
@@ -49,6 +50,47 @@
 #define SSC_STATUS_PLL_LOCK_MASK			0x800
 #define SSC_STATUS_PLL_LOCK_SHIFT			11
 
+#define PCIE_RC_PL_PHY_CTL_15				0x184c
+#define PCIE_RC_PL_PHY_CTL_15_DIS_PLL_PD_MASK		0x400000
+#define PCIE_RC_PL_PHY_CTL_15_PM_CLK_PERIOD_MASK	0xff
+
+#define PCIE_MISC_UBUS_CTRL				0x40a4
+#define  PCIE_MISC_UBUS_CTRL_UBUS_PCIE_REPLY_ERR_DIS_MASK	BIT(13)
+#define  PCIE_MISC_UBUS_CTRL_UBUS_PCIE_REPLY_DECERR_DIS_MASK	BIT(19)
+#define PCIE_MISC_AXI_READ_ERROR_DATA			0x4170
+#define PCIE_MISC_UBUS_TIMEOUT				0x40A8
+#define PCIE_MISC_RC_CONFIG_RETRY_TIMEOUT		0x405c
+#define PCIE_MISC_RC_BAR4_CONFIG_LO			0x40d4
+#define PCIE_MISC_RC_BAR4_CONFIG_HI			0x40d8
+#define PCIE_MISC_UBUS_BAR_CONFIG_REMAP_HI_MASK		0xff
+#define PCIE_MISC_UBUS_BAR4_CONFIG_REMAP_HI		0x4110
+#define PCIE_MISC_UBUS_BAR_CONFIG_REMAP_ENABLE		0x1
+#define PCIE_MISC_UBUS_BAR_CONFIG_REMAP_LO_MASK		0xfffff000
+#define PCIE_MISC_UBUS_BAR4_CONFIG_REMAP_LO		0x410c
+
+#define PCIE_MISC_UBUS_BAR1_CONFIG_REMAP		0x40ac
+#define PCIE_MISC_UBUS_BAR2_CONFIG_REMAP		0x40b4
+#define  PCIE_MISC_UBUS_BAR2_CONFIG_REMAP_ACCESS_ENABLE_MASK	BIT(0)
+#define  MISC_CTRL_PCIE_RCB_MPS_MODE_MASK		0x400
+
+enum {
+	RGR1_SW_INIT_1,
+	PCIE_HARD_DEBUG,
+};
+
+enum brcm_pcie_type {
+	BCM2711,
+	BCM2712
+};
+
+struct brcm_pcie;
+
+struct brcm_pcie_cfg_data {
+	const int *offsets;
+	const enum brcm_pcie_type type;
+	void (*perst_set)(struct brcm_pcie *pcie, u32 val);
+};
+
 /**
  * struct brcm_pcie - the PCIe controller state
  * @base: Base address of memory mapped IO registers of the controller
@@ -61,6 +103,9 @@ struct brcm_pcie {
 
 	int			gen;
 	bool			ssc;
+	struct reset_ctl	rescal;
+	struct reset_ctl	bridge_reset;
+	const struct brcm_pcie_cfg_data *pcie_cfg;
 };
 
 /**
@@ -79,8 +124,8 @@ static int brcm_pcie_encode_ibar_size(u64 size)
 	if (log2_in >= 12 && log2_in <= 15)
 		/* Covers 4KB to 32KB (inclusive) */
 		return (log2_in - 12) + 0x1c;
-	else if (log2_in >= 16 && log2_in <= 37)
-		/* Covers 64KB to 32GB, (inclusive) */
+	else if (log2_in >= 16 && log2_in <= 36)
+		/* Covers 64KB to 64GB, (inclusive) */
 		return log2_in - 15;
 
 	/* Something is awry so disable */
@@ -104,6 +149,80 @@ static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie)
 	return (val & STATUS_PCIE_PORT_MASK) >> STATUS_PCIE_PORT_SHIFT;
 }
 
+static void brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val)
+{
+	if (val)
+		setbits_le32(pcie->base + pcie->pcie_cfg->offsets[RGR1_SW_INIT_1],
+			     RGR1_SW_INIT_1_PERST_MASK);
+	else
+		clrbits_le32(pcie->base + pcie->pcie_cfg->offsets[RGR1_SW_INIT_1],
+			     RGR1_SW_INIT_1_PERST_MASK);
+}
+
+static void brcm_pcie_perst_set_2712(struct brcm_pcie *pcie, u32 val)
+{
+	u32 tmp;
+
+	/* Perst bit has moved and assert value is 0 */
+	tmp = readl(pcie->base + PCIE_MISC_PCIE_CTRL);
+	u32p_replace_bits(&tmp, !val, RGR1_SW_INIT_1_PERSTB_MASK);
+	writel(tmp, pcie->base + PCIE_MISC_PCIE_CTRL);
+}
+
+static int brcm_pcie_get_resets_dt(struct udevice *dev)
+{
+	struct brcm_pcie *pcie = dev_get_priv(dev);
+	int ret;
+
+	ret = reset_get_by_name(dev, "rescal", &pcie->rescal);
+	if (ret) {
+		printf("Unable to get rescal reset\n");
+		return ret;
+	}
+
+	ret = reset_get_by_name(dev, "bridge", &pcie->bridge_reset);
+	if (ret)
+		printf("Unable to get bridge reset\n");
+
+	return ret;
+}
+
+static int brcm_pcie_do_reset(struct udevice *dev)
+{
+	struct brcm_pcie *pcie = dev_get_priv(dev);
+	int ret;
+
+	ret = reset_deassert(&pcie->rescal);
+	if (ret)
+		printf("failed to deassert 'rescal'\n");
+	return ret;
+}
+
+static int brcm_pcie_bridge_sw_init_set(struct brcm_pcie *pcie, u32 val)
+{
+	int ret = 0;
+
+	if (reset_valid(&pcie->bridge_reset))
+	{
+		if (val)
+			ret = reset_assert(&pcie->bridge_reset);
+		else
+			ret = reset_deassert(&pcie->bridge_reset);
+		if (ret)
+			log_err("failed to %sassert bridge reset, err=%d\n",
+				val ? "" : "de", ret);
+		return ret;
+	}
+
+	if (val)
+		setbits_le32(pcie->base + pcie->pcie_cfg->offsets[RGR1_SW_INIT_1],
+			     RGR1_SW_INIT_1_INIT_MASK);
+	else
+		clrbits_le32(pcie->base + pcie->pcie_cfg->offsets[RGR1_SW_INIT_1],
+			     RGR1_SW_INIT_1_INIT_MASK);
+	return 0;
+}
+
 /**
  * brcm_pcie_link_up() - Check whether the PCIe link is up
  * @pcie: Pointer to the PCIe controller state
@@ -125,7 +244,7 @@ static int brcm_pcie_config_address(const struct udevice *dev, pci_dev_t bdf,
 				    uint offset, void **paddress)
 {
 	struct brcm_pcie *pcie = dev_get_priv(dev);
-	unsigned int pci_bus = PCI_BUS(bdf);
+	unsigned int pci_bus = PCI_BUS(bdf) - dev_seq(dev);
 	unsigned int pci_dev = PCI_DEV(bdf);
 	unsigned int pci_func = PCI_FUNC(bdf);
 	int idx;
@@ -345,28 +464,150 @@ static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie,
 	writel(tmp, base + PCIE_MEM_WIN0_LIMIT_HI(win));
 }
 
+static u32 brcm_bar_reg_offset(int bar)
+{
+	if (bar <= 3)
+		return PCIE_MISC_RC_BAR1_CONFIG_LO + 8 * (bar - 1);
+	else
+		return PCIE_MISC_RC_BAR4_CONFIG_LO + 8 * (bar - 4);
+}
+
+static u32 brcm_ubus_reg_offset(int bar)
+{
+	if (bar <= 3)
+		return PCIE_MISC_UBUS_BAR1_CONFIG_REMAP + 8 * (bar - 1);
+	else
+		return PCIE_MISC_UBUS_BAR4_CONFIG_REMAP_LO + 8 * (bar - 4);
+}
+
+/*
+ * Round size up to the next power of two, as required by
+ * brcm_pcie_encode_ibar_size().  If size is already a power of two
+ * fls64(size - 1) still gives the correct result because the hardware
+ * encodes the exponent, not the raw value.
+ */
+static u64 brcm_ibar_round_size(u64 size)
+{
+	return 1ULL << fls64(size - 1);
+}
+
+static void brcm_pcie_set_inbound_windows(struct udevice *dev)
+{
+	struct brcm_pcie *pcie = dev_get_priv(dev);
+	void __iomem *base = pcie->base;
+	bool is_2712 = (pcie->pcie_cfg->type == BCM2712);
+	int i, ibar_no, ret;
+	u32 tmp;
+
+	ibar_no = 0;
+	/* pre-2712 chips leave the first entry empty */
+	if (pcie->pcie_cfg->type != BCM2712)
+		ibar_no++;
+
+	/* program inbound windows from OF property "dma-regions" */
+	for (i = 0; i < 7; i++, ibar_no++) {
+		u64 bar_cpu, bar_size, bar_pci;
+		struct pci_region region;
+		int ubus_bar_offset, rc_bar_offset;
+
+		ret = pci_get_dma_regions(dev, &region, i);
+		if (ret)	/* no region #i? Then we're done. */
+			break;
+		ubus_bar_offset = brcm_ubus_reg_offset(ibar_no + 1);
+		rc_bar_offset = brcm_bar_reg_offset(ibar_no + 1);
+
+		bar_pci = region.bus_start;
+		bar_cpu = region.phys_start;
+		bar_size = region.size;
+
+		if (is_2712) {
+			/* BCM2712: BAR holds raw PCI address; UBUS remap
+			 * registers supply the CPU-side translation. */
+			tmp = lower_32_bits(bar_pci);
+			u32p_replace_bits(&tmp, brcm_pcie_encode_ibar_size(bar_size),
+					  RC_BAR2_CONFIG_LO_SIZE_MASK);
+			writel(tmp, base + rc_bar_offset);
+			writel(upper_32_bits(bar_pci), base + rc_bar_offset + 4);
+
+			tmp = lower_32_bits(bar_cpu) &
+					PCIE_MISC_UBUS_BAR_CONFIG_REMAP_LO_MASK;
+			tmp |= PCIE_MISC_UBUS_BAR_CONFIG_REMAP_ENABLE;
+			writel(tmp, base + ubus_bar_offset);
+
+			tmp = upper_32_bits(bar_cpu) &
+				PCIE_MISC_UBUS_BAR_CONFIG_REMAP_HI_MASK;
+			writel(tmp, base + ubus_bar_offset + 4);
+		} else {
+			/* Pre-BCM2712 (e.g. BCM2711 / RPi4): the BAR config
+			 * register holds the offset (bus_start - phys_start),
+			 * not the raw PCI address.  The size must be rounded
+			 * up to the next power of two before encoding. */
+			u64 bar_offset = bar_pci - bar_cpu;
+			u64 bar_size_po2 = brcm_ibar_round_size(bar_size);
+
+			tmp = lower_32_bits(bar_offset);
+			u32p_replace_bits(&tmp, brcm_pcie_encode_ibar_size(bar_size_po2),
+					  RC_BAR2_CONFIG_LO_SIZE_MASK);
+			writel(tmp, base + rc_bar_offset);
+			writel(upper_32_bits(bar_offset), base + rc_bar_offset + 4);
+			/* UBUS remap registers are not used on pre-2712 hardware. */
+		}
+	}
+}
+
+static void brcm_pcie_munge_pll(struct brcm_pcie *pcie)
+{
+	u32 tmp;
+	int ret, i;
+	u8 regs[] =  { 0x16,   0x17,   0x18,   0x19,   0x1b,   0x1c,   0x1e };
+	u16 data[] = { 0x50b9, 0xbda1, 0x0094, 0x97b4, 0x5030, 0x5030, 0x0007 };
+
+	ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, SET_ADDR_OFFSET,
+				   0x1600);
+	for (i = 0; i < ARRAY_SIZE(regs); i++) {
+		brcm_pcie_mdio_read(pcie->base, MDIO_PORT0, regs[i], &tmp);
+		debug("PCIE MDIO pre_refclk 0x%02x = 0x%04x\n",
+		      regs[i], tmp);
+	}
+	for (i = 0; i < ARRAY_SIZE(regs); i++) {
+		brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, regs[i], data[i]);
+		brcm_pcie_mdio_read(pcie->base, MDIO_PORT0, regs[i], &tmp);
+		debug("PCIE MDIO post_refclk 0x%02x = 0x%04x\n",
+		      regs[i], tmp);
+	}
+
+	udelay(200);
+}
+
 static int brcm_pcie_probe(struct udevice *dev)
 {
 	struct udevice *ctlr = pci_get_controller(dev);
 	struct pci_controller *hose = dev_get_uclass_priv(ctlr);
 	struct brcm_pcie *pcie = dev_get_priv(dev);
 	void __iomem *base = pcie->base;
-	struct pci_region region;
 	bool ssc_good = false;
 	int num_out_wins = 0;
-	u64 rc_bar2_offset, rc_bar2_size;
-	unsigned int scb_size_val;
-	int i, ret;
+	int i, ret = 0;
 	u16 nlw, cls, lnksta;
 	u32 tmp;
 
+	/*
+	 * Ensure rescal reset for BCM2712 is really disabled.
+	 */
+	if (pcie->pcie_cfg->type == BCM2712)
+		ret = brcm_pcie_do_reset(dev);
+	if (ret)
+		return ret;
 	/*
 	 * Reset the bridge, assert the fundamental reset. Note for some SoCs,
 	 * e.g. BCM7278, the fundamental reset should not be asserted here.
 	 * This will need to be changed when support for other SoCs is added.
 	 */
-	setbits_le32(base + PCIE_RGR1_SW_INIT_1,
-		     PCIE_RGR1_SW_INIT_1_INIT_MASK | PCIE_RGR1_SW_INIT_1_PERST_MASK);
+	ret = brcm_pcie_bridge_sw_init_set(pcie, 1);
+	if (ret)
+		return ret;
+	if (pcie->pcie_cfg->type != BCM2712)
+		pcie->pcie_cfg->perst_set(pcie, 1);
 	/*
 	 * The delay is a safety precaution to preclude the reset signal
 	 * from looking like a glitch.
@@ -374,40 +615,78 @@ static int brcm_pcie_probe(struct udevice *dev)
 	udelay(100);
 
 	/* Take the bridge out of reset */
-	clrbits_le32(base + PCIE_RGR1_SW_INIT_1, PCIE_RGR1_SW_INIT_1_INIT_MASK);
-
-	clrbits_le32(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG,
+	ret = brcm_pcie_bridge_sw_init_set(pcie, 0);
+	if (ret)
+		return ret;
+	clrbits_le32(base + pcie->pcie_cfg->offsets[PCIE_HARD_DEBUG],
 		     PCIE_HARD_DEBUG_SERDES_IDDQ_MASK);
 
 	/* Wait for SerDes to be stable */
 	udelay(100);
 
+	if (pcie->pcie_cfg->type == BCM2712) {
+		/* Allow a 54MHz (xosc) refclk source */
+		brcm_pcie_munge_pll(pcie);
+		/* Fix for L1SS errata */
+		tmp = readl(base + PCIE_RC_PL_PHY_CTL_15);
+		tmp &= ~PCIE_RC_PL_PHY_CTL_15_PM_CLK_PERIOD_MASK;
+		/* PM clock period is 18.52ns (round down) */
+		tmp |= 0x12;
+		writel(tmp, base + PCIE_RC_PL_PHY_CTL_15);
+	}
+
+	tmp = (pcie->pcie_cfg->type == BCM2712) ?
+			MISC_CTRL_MAX_BURST_SIZE_128_2712 :
+			MISC_CTRL_MAX_BURST_SIZE_128;
 	/* Set SCB_MAX_BURST_SIZE, CFG_READ_UR_MODE, SCB_ACCESS_EN */
 	clrsetbits_le32(base + PCIE_MISC_MISC_CTRL,
 			MISC_CTRL_MAX_BURST_SIZE_MASK,
 			MISC_CTRL_SCB_ACCESS_EN_MASK |
 			MISC_CTRL_CFG_READ_UR_MODE_MASK |
-			MISC_CTRL_MAX_BURST_SIZE_128);
-
-	pci_get_dma_regions(dev, &region, 0);
-	rc_bar2_offset = region.bus_start - region.phys_start;
-	rc_bar2_size = 1ULL << fls64(region.size - 1);
-
-	tmp = lower_32_bits(rc_bar2_offset);
-	u32p_replace_bits(&tmp, brcm_pcie_encode_ibar_size(rc_bar2_size),
-			  RC_BAR2_CONFIG_LO_SIZE_MASK);
-	writel(tmp, base + PCIE_MISC_RC_BAR2_CONFIG_LO);
-	writel(upper_32_bits(rc_bar2_offset),
-	       base + PCIE_MISC_RC_BAR2_CONFIG_HI);
-
-	scb_size_val = rc_bar2_size ?
-		       ilog2(rc_bar2_size) - 15 : 0xf; /* 0xf is 1GB */
+			MISC_CTRL_PCIE_RCB_MPS_MODE_MASK |
+			tmp);
 
 	tmp = readl(base + PCIE_MISC_MISC_CTRL);
-	u32p_replace_bits(&tmp, scb_size_val,
-			  MISC_CTRL_SCB0_SIZE_MASK);
+	if (pcie->pcie_cfg->type == BCM2712) {
+		/* BCM2712: fixed 32GB SCB0 window */
+		u32p_replace_bits(&tmp, 20, MISC_CTRL_SCB0_SIZE_MASK);
+	} else {
+		/* Pre-BCM2712: size SCB0 to match the actual DMA region.
+		 * rc_bar2_size must be a power of two; ilog2(size) - 15
+		 * gives the hardware encoding (e.g. 1GB -> 15). */
+		struct pci_region region;
+		u64 rc_bar2_size;
+
+		pci_get_dma_regions(dev, &region, 0);
+		rc_bar2_size = brcm_ibar_round_size(region.size);
+		u32p_replace_bits(&tmp, rc_bar2_size ? ilog2(rc_bar2_size) - 15 : 0xf,
+				  MISC_CTRL_SCB0_SIZE_MASK);
+	}
 	writel(tmp, base + PCIE_MISC_MISC_CTRL);
 
+	if (pcie->pcie_cfg->type == BCM2712) {
+		/* Suppress AXI error responses and return 1s for read failures */
+		tmp = readl(base + PCIE_MISC_UBUS_CTRL);
+		u32p_replace_bits(&tmp, 1, PCIE_MISC_UBUS_CTRL_UBUS_PCIE_REPLY_ERR_DIS_MASK);
+		u32p_replace_bits(&tmp, 1, PCIE_MISC_UBUS_CTRL_UBUS_PCIE_REPLY_DECERR_DIS_MASK);
+		writel(tmp, base + PCIE_MISC_UBUS_CTRL);
+		writel(0xffffffff, base + PCIE_MISC_AXI_READ_ERROR_DATA);
+
+		/*
+		 * Adjust timeouts. The UBUS timeout also affects CRS
+		 * completion retries, as the request will get terminated if
+		 * either timeout expires, so both have to be a large value
+		 * (in clocks of 750MHz).
+		 * Set UBUS timeout to 250ms, then set RC config retry timeout
+		 * to be ~240ms.
+		 *
+		 * Setting CRSVis=1 will stop the core from blocking on a CRS
+		 * response, but does require the device to be well-behaved...
+		 */
+		writel(0xB2D0000, base + PCIE_MISC_UBUS_TIMEOUT);
+		writel(0xABA0000, base + PCIE_MISC_RC_CONFIG_RETRY_TIMEOUT);
+	}
+
 	/* Disable the PCIe->GISB memory window (RC_BAR1) */
 	clrbits_le32(base + PCIE_MISC_RC_BAR1_CONFIG_LO,
 		     RC_BAR1_CONFIG_LO_SIZE_MASK);
@@ -422,12 +701,13 @@ static int brcm_pcie_probe(struct udevice *dev)
 	/* Clear any interrupts we find on boot */
 	writel(0xffffffff, base + PCIE_MSI_INTR2_CLR);
 
+	brcm_pcie_set_inbound_windows(dev);
+
 	if (pcie->gen)
 		brcm_pcie_set_gen(pcie, pcie->gen);
 
 	/* Unassert the fundamental reset */
-	clrbits_le32(pcie->base + PCIE_RGR1_SW_INIT_1,
-		     PCIE_RGR1_SW_INIT_1_PERST_MASK);
+	pcie->pcie_cfg->perst_set(pcie, 0);
 
 	/*
 	 * Wait for 100ms after PERST# deassertion; see PCIe CEM specification
@@ -514,14 +794,25 @@ static int brcm_pcie_remove(struct udevice *dev)
 	void __iomem *base = pcie->base;
 
 	/* Assert fundamental reset */
-	setbits_le32(base + PCIE_RGR1_SW_INIT_1, PCIE_RGR1_SW_INIT_1_PERST_MASK);
+	setbits_le32(base + pcie->pcie_cfg->offsets[RGR1_SW_INIT_1],
+		     PCIE_RGR1_SW_INIT_1_PERST_MASK);
 
 	/* Turn off SerDes */
-	setbits_le32(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG,
+	setbits_le32(base + pcie->pcie_cfg->offsets[PCIE_HARD_DEBUG],
 		     PCIE_HARD_DEBUG_SERDES_IDDQ_MASK);
 
 	/* Shutdown bridge */
-	setbits_le32(base + PCIE_RGR1_SW_INIT_1, PCIE_RGR1_SW_INIT_1_INIT_MASK);
+	brcm_pcie_bridge_sw_init_set(pcie, 1);
+
+	/*
+	 * For the controllers that are utilizing reset for bridge Sw init,
+	 * such as BCM2712, reset should be deasserted after assertion.
+	 * Leaving it in asserted state may lead to unexpected hangs in
+	 * the Linux Kernel driver because it do not perform reset initialization
+	 * and start accessing device memory.
+	 */
+	if (pcie->pcie_cfg->type == BCM2712)
+		brcm_pcie_bridge_sw_init_set(pcie, 0);
 
 	return 0;
 }
@@ -546,6 +837,11 @@ static int brcm_pcie_of_to_plat(struct udevice *dev)
 	else
 		pcie->gen = max_link_speed;
 
+	pcie->pcie_cfg = (const struct brcm_pcie_cfg_data *)dev_get_driver_data(dev);
+
+	if (pcie->pcie_cfg->type == BCM2712)
+		return brcm_pcie_get_resets_dt(dev);
+
 	return 0;
 }
 
@@ -554,8 +850,31 @@ static const struct dm_pci_ops brcm_pcie_ops = {
 	.write_config	= brcm_pcie_write_config,
 };
 
+static const int pcie_offsets[] = {
+	[RGR1_SW_INIT_1] = 0x9210,
+	[PCIE_HARD_DEBUG] = 0x4204,
+};
+
+static const struct brcm_pcie_cfg_data bcm2711_cfg = {
+	.offsets	= pcie_offsets,
+	.type		= BCM2711,
+	.perst_set	= brcm_pcie_perst_set_generic,
+};
+
+static const int pcie_offsets_bcm2712[] = {
+	[RGR1_SW_INIT_1] = 0x0,
+	[PCIE_HARD_DEBUG] = 0x4304,
+};
+
+static const struct brcm_pcie_cfg_data bcm2712_cfg = {
+	.offsets	= pcie_offsets_bcm2712,
+	.type		= BCM2712,
+	.perst_set	= brcm_pcie_perst_set_2712,
+};
+
 static const struct udevice_id brcm_pcie_ids[] = {
-	{ .compatible = "brcm,bcm2711-pcie" },
+	{ .compatible = "brcm,bcm2711-pcie", .data = (ulong)&bcm2711_cfg },
+	{ .compatible = "brcm,bcm2712-pcie", .data = (ulong)&bcm2712_cfg },
 	{ }
 };
 

drivers/power/regulator/qcom-rpmh-regulator.c

@@ -295,57 +295,6 @@ static int rpmh_regulator_vrm_get_value(struct udevice *rdev)
 	return vreg->uv;
 }
 
-static int rpmh_regulator_is_enabled(struct udevice *rdev)
-{
-	struct rpmh_vreg *vreg = dev_get_priv(rdev);
-	int ret;
-
-	debug("%s: is_enabled %d\n", rdev->name, vreg->enabled);
-
-	if (vreg->enabled < 0) {
-		struct tcs_cmd cmd = {
-			.addr = vreg->addr + RPMH_REGULATOR_REG_ENABLE,
-		};
-		ret = rpmh_regulator_read_data(vreg, &cmd);
-		/*
-		 * Don't override if disabled since we will also vote the right voltage
-		 * while enabling
-		 */
-		if (!ret && cmd.data)
-			vreg->enabled = cmd.data & RPMH_REGULATOR_ENABLE_MASK;
-	}
-
-	return vreg->enabled > 0;
-}
-
-static int rpmh_regulator_set_enable_state(struct udevice *rdev,
-					   bool enable)
-{
-	struct rpmh_vreg *vreg = dev_get_priv(rdev);
-	struct tcs_cmd cmd = {
-		.addr = vreg->addr + RPMH_REGULATOR_REG_ENABLE,
-		.data = enable,
-	};
-	int ret;
-
-	debug("%s: set_enable %d (current %d)\n", rdev->name, enable,
-	      vreg->enabled);
-
-	if (vreg->enabled == -EINVAL &&
-	    vreg->uv != -ENOTRECOVERABLE) {
-		ret = _rpmh_regulator_vrm_set_value(rdev,
-						    vreg->uv, true);
-		if (ret < 0)
-			return ret;
-	}
-
-	ret = rpmh_regulator_send_request(vreg, &cmd, enable);
-	if (!ret)
-		vreg->enabled = enable;
-
-	return ret;
-}
-
 static int rpmh_regulator_vrm_set_mode_bypass(struct rpmh_vreg *vreg,
 					      unsigned int mode, bool bypassed)
 {
@@ -396,6 +345,63 @@ static int rpmh_regulator_vrm_set_mode(struct udevice *rdev,
 	return ret;
 }
 
+static int rpmh_regulator_is_enabled(struct udevice *rdev)
+{
+	struct rpmh_vreg *vreg = dev_get_priv(rdev);
+	int ret;
+
+	debug("%s: is_enabled %d\n", rdev->name, vreg->enabled);
+
+	if (vreg->enabled < 0) {
+		struct tcs_cmd cmd = {
+			.addr = vreg->addr + RPMH_REGULATOR_REG_ENABLE,
+		};
+		ret = rpmh_regulator_read_data(vreg, &cmd);
+		/*
+		 * Don't override if disabled since we will also vote the right voltage
+		 * while enabling
+		 */
+		if (!ret && cmd.data)
+			vreg->enabled = cmd.data & RPMH_REGULATOR_ENABLE_MASK;
+	}
+
+	return vreg->enabled > 0;
+}
+
+static int rpmh_regulator_set_enable_state(struct udevice *rdev,
+					   bool enable)
+{
+	struct rpmh_vreg *vreg = dev_get_priv(rdev);
+	struct tcs_cmd cmd = {
+		.addr = vreg->addr + RPMH_REGULATOR_REG_ENABLE,
+		.data = enable,
+	};
+	int ret;
+
+	debug("%s: set_enable %d (current %d)\n", rdev->name, enable,
+	      vreg->enabled);
+
+	if (vreg->mode != -EINVAL) {
+		ret = rpmh_regulator_vrm_set_mode_bypass(vreg, vreg->mode, vreg->bypassed);
+		if (ret < 0)
+			return ret;
+	}
+
+	if (vreg->enabled == -EINVAL &&
+	    vreg->uv != -ENOTRECOVERABLE) {
+		ret = _rpmh_regulator_vrm_set_value(rdev,
+						    vreg->uv, true);
+		if (ret < 0)
+			return ret;
+	}
+
+	ret = rpmh_regulator_send_request(vreg, &cmd, enable);
+	if (!ret)
+		vreg->enabled = enable;
+
+	return ret;
+}
+
 static int rpmh_regulator_vrm_get_pmic_mode(struct rpmh_vreg *vreg, int *pmic_mode)
 {
 	struct tcs_cmd cmd = {

drivers/reset/Kconfig

@@ -64,6 +64,22 @@ config RESET_BCM6345
 	help
 	  Support reset controller on BCM6345.
 
+config RESET_BRCMSTB
+	depends on ARCH_BCM283X
+	bool "Generic Reset controller driver for Broadcom"
+	help
+	  This enables reset controller for Broadcom devices.
+	  If you wish to use reset resources managed by the Broadcom
+	  Reset Controller, say Y here. Otherwise, say N.
+
+config RESET_BRCMSTB_RESCAL
+	depends on ARCH_BCM283X
+	bool "Generic Rescal Reset controller driver for Broadcom"
+	help
+	  Support rescal reset controller on Broadcom.
+	  If you wish to use reset resources managed by the Broadcom
+	  Reset Controller, say Y here. Otherwise, say N.
+
 config RESET_UNIPHIER
 	bool "Reset controller driver for UniPhier SoCs"
 	depends on ARCH_UNIPHIER
@@ -100,6 +116,15 @@ config RESET_ROCKCHIP
 	  though is that some reset signals, like I2C or MISC reset multiple
 	  devices.
 
+config SPL_RESET_ROCKCHIP
+	bool "SPL reset controller driver for Rockchip SoCs"
+	depends on SPL_DM_RESET && ARCH_ROCKCHIP && SPL_CLK
+	default y
+	help
+	  Support for the reset controller on Rockchip SoCs in SPL. Select this
+	  if you observe any reset-related warnings or errors when booting SPL,
+	  such as when using UFS storage
+
 config RESET_HSDK
 	bool "Synopsys HSDK Reset Driver"
 	depends on DM_RESET && TARGET_HSDK

drivers/reset/Makefile

@@ -13,10 +13,12 @@ obj-$(CONFIG_RESET_AIROHA) += reset-airoha.o
 obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o
 obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o
 obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
+obj-$(CONFIG_RESET_BRCMSTB) += reset-brcmstb.o
+obj-$(CONFIG_RESET_BRCMSTB_RESCAL) += reset-brcmstb-rescal.o
 obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
 obj-$(CONFIG_RESET_AST2500) += reset-ast2500.o
 obj-$(CONFIG_RESET_AST2600) += reset-ast2600.o
-obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o rst-rk3506.o rst-rk3528.o rst-rk3576.o rst-rk3588.o
+obj-$(CONFIG_$(PHASE_)RESET_ROCKCHIP) += reset-rockchip.o rst-rk3506.o rst-rk3528.o rst-rk3576.o rst-rk3588.o
 obj-$(CONFIG_RESET_MESON) += reset-meson.o
 obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
 obj-$(CONFIG_RESET_MEDIATEK) += reset-mediatek.o

drivers/reset/reset-brcmstb-rescal.c

@@ -0,0 +1,103 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Broadcom STB generic reset controller
+ *
+ * Copyright (C) 2024 EPAM Systems
+ * Moved from linux kernel:
+ * Copyright (C) 2018-2020 Broadcom
+ */
+
+#include <asm/io.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <errno.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/iopoll.h>
+#include <log.h>
+#include <malloc.h>
+#include <reset-uclass.h>
+
+#define BRCM_RESCAL_START 0x0
+#define BRCM_RESCAL_START_BIT BIT(0)
+#define BRCM_RESCAL_CTRL 0x4
+#define BRCM_RESCAL_STATUS 0x8
+#define BRCM_RESCAL_STATUS_BIT BIT(0)
+
+struct brcm_rescal_reset {
+	void __iomem *base;
+};
+
+/* Also doubles a deassert */
+static int brcm_rescal_reset_set(struct reset_ctl *rst)
+{
+	struct brcm_rescal_reset *data = dev_get_priv(rst->dev);
+	void __iomem *base = data->base;
+	u32 reg;
+	int ret;
+
+	reg = readl(base + BRCM_RESCAL_START);
+	writel(reg | BRCM_RESCAL_START_BIT, base + BRCM_RESCAL_START);
+	reg = readl(base + BRCM_RESCAL_START);
+	if (!(reg & BRCM_RESCAL_START_BIT)) {
+		dev_err(rst->dev, "failed to start SATA/PCIe rescal\n");
+		return -EIO;
+	}
+
+	ret = readl_poll_timeout(base + BRCM_RESCAL_STATUS, reg,
+				 (reg & BRCM_RESCAL_STATUS_BIT), 100);
+	if (ret) {
+		dev_err(rst->dev, "time out on SATA/PCIe rescal\n");
+		return ret;
+	}
+
+	reg = readl(base + BRCM_RESCAL_START);
+	writel(reg & ~BRCM_RESCAL_START_BIT, base + BRCM_RESCAL_START);
+
+	dev_dbg(rst->dev, "SATA/PCIe rescal success\n");
+	return 0;
+}
+
+/* A dummy function - deassert/reset does all the work */
+static int brcm_rescal_reset_assert(struct reset_ctl *rst)
+{
+	return 0;
+}
+
+static int brcm_rescal_reset_xlate(struct reset_ctl *reset_ctl,
+				   struct ofnode_phandle_args *args)
+{
+	/* This is needed if #reset-cells == 0. */
+	return 0;
+}
+
+static const struct reset_ops brcm_rescal_reset_ops = {
+	.rst_deassert = brcm_rescal_reset_set,
+	.rst_assert = brcm_rescal_reset_assert,
+	.of_xlate = brcm_rescal_reset_xlate,
+};
+
+static int brcm_rescal_reset_probe(struct udevice *dev)
+{
+	struct brcm_rescal_reset *data = dev_get_priv(dev);
+
+	data->base = dev_remap_addr(dev);
+	if (!data->base)
+		return -EINVAL;
+
+	return 0;
+}
+
+static const struct udevice_id brcm_rescal_reset_of_match[] = {
+	{.compatible = "brcm,bcm7216-pcie-sata-rescal"},
+	{},
+};
+
+U_BOOT_DRIVER(brcmstb_reset_rescal) = {
+	.name = "brcmstb-reset-rescal",
+	.id = UCLASS_RESET,
+	.of_match = brcm_rescal_reset_of_match,
+	.ops = &brcm_rescal_reset_ops,
+	.probe = brcm_rescal_reset_probe,
+	.priv_auto = sizeof(struct brcm_rescal_reset),
+};

drivers/reset/reset-brcmstb.c

@@ -0,0 +1,97 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Broadcom STB generic reset controller
+ *
+ * Copyright (C) 2024 EPAM Systems
+ *
+ * Moved from linux kernel:
+ * Author: Florian Fainelli <f.fainelli@gmail.com>
+ * Copyright (C) 2018 Broadcom
+ */
+
+#include <asm/io.h>
+#include <dm.h>
+#include <errno.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <log.h>
+#include <malloc.h>
+#include <reset-uclass.h>
+
+struct brcmstb_reset {
+	void __iomem *base;
+};
+
+#define SW_INIT_SET 0x00
+#define SW_INIT_CLEAR 0x04
+#define SW_INIT_STATUS 0x08
+
+#define SW_INIT_BIT(id) BIT((id) & 0x1f)
+#define SW_INIT_BANK(id) ((id) >> 5)
+
+#define usleep_range(a, b) udelay((b))
+
+/* A full bank contains extra registers that we are not utilizing but still
+ * qualify as a single bank.
+ */
+#define SW_INIT_BANK_SIZE 0x18
+
+static int brcmstb_reset_assert(struct reset_ctl *rst)
+{
+	unsigned int off = SW_INIT_BANK(rst->id) * SW_INIT_BANK_SIZE;
+	struct brcmstb_reset *priv = dev_get_priv(rst->dev);
+
+	writel_relaxed(SW_INIT_BIT(rst->id), priv->base + off + SW_INIT_SET);
+	return 0;
+}
+
+static int brcmstb_reset_deassert(struct reset_ctl *rst)
+{
+	unsigned int off = SW_INIT_BANK(rst->id) * SW_INIT_BANK_SIZE;
+	struct brcmstb_reset *priv = dev_get_priv(rst->dev);
+
+	writel_relaxed(SW_INIT_BIT(rst->id), priv->base + off + SW_INIT_CLEAR);
+	/* Maximum reset delay after de-asserting a line and seeing block
+	 * operation is typically 14us for the worst case, build some slack
+	 * here.
+	 */
+	usleep_range(100, 200);
+	return 0;
+}
+
+static int brcmstb_reset_status(struct reset_ctl *rst)
+{
+	unsigned int off = SW_INIT_BANK(rst->id) * SW_INIT_BANK_SIZE;
+	struct brcmstb_reset *priv = dev_get_priv(rst->dev);
+
+	return readl_relaxed(priv->base + off + SW_INIT_STATUS) &
+			SW_INIT_BIT(rst->id);
+}
+
+struct reset_ops brcmstb_reset_reset_ops = {
+	.rst_assert = brcmstb_reset_assert,
+	.rst_deassert = brcmstb_reset_deassert,
+	.rst_status = brcmstb_reset_status};
+
+static int brcmstb_reset_probe(struct udevice *dev)
+{
+	struct brcmstb_reset *priv = dev_get_priv(dev);
+
+	priv->base = dev_remap_addr(dev);
+	if (!priv->base)
+		return -EINVAL;
+
+	return 0;
+}
+
+static const struct udevice_id brcmstb_reset_ids[] = {
+	{.compatible = "brcm,brcmstb-reset"}, {/* sentinel */}};
+
+U_BOOT_DRIVER(brcmstb_reset) = {
+	.name = "brcmstb-reset",
+	.id = UCLASS_RESET,
+	.of_match = brcmstb_reset_ids,
+	.ops = &brcmstb_reset_reset_ops,
+	.probe = brcmstb_reset_probe,
+	.priv_auto = sizeof(struct brcmstb_reset),
+};