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1534 Commits

Author SHA1 Message Date
Tom Rini
25049ad560 Prepare v2024.04
Signed-off-by: Tom Rini <trini@konsulko.com>
2024-04-02 06:58:58 -04:00
Tom Rini
425dc46a2c Merge tag 'u-boot-imx-master-20240330' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/20122

- Fix reset regression on mx6cuboxi and warp7.
- Fix Fix board revision detection on mx6cuboxi.
2024-03-30 14:07:37 -04:00
Fabio Estevam
fc07cac02a mx6cuboxi: Convert to watchdog driver model
Commit 68dcbdd594 ("ARM: imx: Add weak default reset_cpu()") caused
the 'reset' command in U-Boot to not cause a board reset.

Fix it by switching to the watchdog driver model via sysreset, which
is the preferred method for implementing the watchdog reset.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Tested-by: Christian Gmeiner <cgmeiner@igalia.com>
2024-03-30 09:49:53 -03:00
Fabio Estevam
ea2b074a1c warp7: Convert to watchdog driver model
Commit 68dcbdd594 ("ARM: imx: Add weak default reset_cpu()") caused
the 'reset' command in U-Boot to not cause a board reset.

Fix it by switching to the watchdog driver model via sysreset, which
is the preferred method for implementing the watchdog reset.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2024-03-30 09:49:34 -03:00
Fabio Estevam
e7b5250612 mx6cuboxi: Fix board revision detection
Currently, an i.MX6 Cuboxi board is incorrectly detected
as the HummingBoard model:

U-Boot 2024.04-rc5 (Mar 26 2024 - 15:59:22 +0100)

CPU:   Freescale i.MX6Q rev1.3 996 MHz (running at 792 MHz)
CPU:   Extended Commercial temperature grade (-20C to 105C) at 26C
Reset cause: POR
Model: SolidRun HummingBoard2 Dual/Quad (1.5som+emmc)
gpio@20a4000: set_dir_flags: error: gpio GPIO3_8 not reserved
gpio@20a4000: get_value: error: gpio GPIO3_8 not reserved
gpio@20a8000: set_dir_flags: error: gpio GPIO4_4 not reserved
gpio@20a8000: get_value: error: gpio GPIO4_4 not reserved
gpio@20b0000: set_dir_flags: error: gpio GPIO6_9 not reserved
gpio@20b0000: get_value: error: gpio GPIO6_9 not reserved
Board: MX6 HummingBoard
DRAM:  2 GiB
...

This error happens because request_detect_gpios() uses the GPIO DM
API, but board_type() still uses the legacy non-DM GPIO API.

Fix it by using the GPIO DM API in board_type() to read the
board revision pins in SPL.

Reported-by: Christian Gmeiner <cgmeiner@igalia.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Tested-by: Christian Gmeiner <cgmeiner@igalia.com>
2024-03-30 09:49:12 -03:00
Tom Rini
9468bf3a69 Merge tag 'doc-2024-04-rc6' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request doc-2024-04-rc6

Documentation:

* man page of 'itest'
* tee: sandbox: fix spelling errors in function documentation
2024-03-28 16:01:03 -04:00
Heinrich Schuchardt
d2fbe1fa29 doc: add reference to itest in if man-page
Add a cross reference to the itest command.

Fix a typo: %s/Example/Examples/.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-03-27 09:30:07 +01:00
Heinrich Schuchardt
1626ef2466 doc: man-page for itest
Provide a man-page for the itest command.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-03-27 09:30:07 +01:00
Igor Opaniuk
5e19fe8ea8 tee: sandbox: fix spelling errors
Fix spelling errors in comments.

Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Igor Opaniuk <igor.opaniuk@gmail.com>
2024-03-27 09:29:00 +01:00
Tom Rini
a5ec56aea1 Merge https://source.denx.de/u-boot/custodians/u-boot-riscv
- Fix RISC-V falcon mode booting issue
2024-03-26 10:00:21 -04:00
Randolph
0cfe1bc6ed spl: riscv: opensbi: fix check of PAYLOAD_ARGS_ADDR
When Falcon Mode is enabled on RISC-V, use CONFIG_VAL
to check PAYLOAD_ARGS_ADDR, not CONFIG_IS_ENABLED.

Fixes: 10c4ab898c ("spl: riscv: falcon: move fdt blob to specified address")
Signed-off-by: Randolph <randolph@andestech.com>
Tested-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-03-26 17:31:24 +08:00
Tom Rini
dde373bde3 Prepare v2024.04-rc5
Signed-off-by: Tom Rini <trini@konsulko.com>
2024-03-25 21:56:50 -04:00
Tom Rini
34f0452e0e Merge tag 'u-boot-amlogic-fixes-20240325' of https://source.denx.de/u-boot/custodians/u-boot-amlogic
- fix Ethernet and random MAC's on WeTek Hub/Play2
- fix buffer overflow in serial, mac & usid read
2024-03-25 08:18:53 -04:00
Neil Armstrong
d54f87f09a board: amlogic: fix buffler overflow in seria, mac & usid read
While meson_sm_read_efuse() doesn't overflow, the string is not
zero terminated and env_set*() will buffer overflow and add random
characters to environment.

Acked-by: Viacheslav Bocharov <adeep@lexina.in>
Link: https://lore.kernel.org/r/20240320-u-boot-fix-p200-serial-v2-1-972be646a301@linaro.org
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2024-03-25 09:16:19 +01:00
Christian Hewitt
65d5c367b0 board: amlogic: add meson_generate_serial_ethaddr fallback to p200
Add a fall-back method to generate ethaddr from CPU serial on p200 boards
if the MAC cannot be read from efuse. This prevents random MAC addresses
on the WeTek Hub/Play2 boards.

Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Link: https://lore.kernel.org/r/20240324151905.3817732-3-christianshewitt@gmail.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2024-03-25 09:14:36 +01:00
Christian Hewitt
cac77418d6 ARM: dts: fix Ethernet on WeTek Hub/Play2
Placing the snps,reset content needed for Ethernet to probe in a common
uboot.dtsi results in the content not being used and broken Ethernet. Fix
this by creating two board specific dtsi files with the right content.

Fixes: 67d5128df9 ("ARM: dts: add support for WeTek Hub and WeTek Play2")
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Link: https://lore.kernel.org/r/20240324151905.3817732-2-christianshewitt@gmail.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2024-03-25 09:14:36 +01:00
Hiago De Franco
bd0aedde3e board: toradex: verdin-am62_r5: Increase SPL_STACK_R_MALLOC_SIMPLE_LEN
Increase the SPL_STACK_R_MALLOC_SIMPLE_LEN to 0x200000 to accommodate the
size of tispl.bin fit image. With the recent upgrade of ti-linux-firmware
from version v9.1.0 to v9.2.5, the size of tispl.bin fit image has
increased to 1.4MB, causing allocation errors in the R5 SPL:

```
alloc space exhausted
Could not get FIT buffer of 1325056 bytes
        check CONFIG_SPL_SYS_MALLOC_SIZE
```

Signed-off-by: Hiago De Franco <hiago.franco@toradex.com>
Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com>
2024-03-22 11:10:51 -04:00
Heinrich Schuchardt
1e3a2c0a4a .mailmap entry for Masahisa Kojima
The Linaro mail address is not valid anymore.

Cc: kojima.masahisa@socionext.com
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Masahisa Kojima <kojima.masahisa@socionext.com>
2024-03-22 11:10:47 -04:00
Joao Paulo Goncalves
2bb18248c6 arm: dts: k3-am625-verdin-r5: Change CPU frequency to 800MHz
The lowest speed grade of Toradex AM62 SoMs is K speed, resulting in a
max value of 800MHz for the CPU operating frequency. A solution with
runtime selection of the CPU frequency is already planned to avoid these
kinds of problems in the future.

Fixes: 8fb8a6d499 ("arm: dts: k3-am625-verdin-r5:Change CPU frequency to 1000MHz")
Signed-off-by: Joao Paulo Goncalves <joao.goncalves@toradex.com>
2024-03-22 11:10:44 -04:00
Fabio Estevam
f0e997dc61 clk: clk-imx8qm: Add LPUART IPG entries
Since commit cc7df0b9e8 ("serial: lpuart: Enable IPG clock")
the apalis-imx8qm board no longer boots.

The reason is that the imx8qm clock driver does not handle the
LPUART IPG clocks inside get_rate(), set_rate() and enable() functions.

Fix the boot regression by adding the LPUART IPG entries.

Fixes: cc7df0b9e8 ("serial: lpuart: Enable IPG clock")
Reported-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2024-03-22 11:10:39 -04:00
Fabio Estevam
bcbd1364cb clk: clk-imx8qxp: Add LPUART IPG entries
Since commit cc7df0b9e8 ("serial: lpuart: Enable IPG clock")
the colibri-imx8qxp board no longer boots.

The reason is that the imx8qxp clock driver does not handle the
LPUART IPG clocks inside get_rate(), set_rate() and enable() functions.

Fix the boot regression by adding the LPUART IPG entries.

Fixes: cc7df0b9e8 ("serial: lpuart: Enable IPG clock")
Reported-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Hiago De Franco <hiago.franco@toradex.com> # Toradex Colibri iMX8X
Acked-by: Sean Anderson <seanga2@gmail.com>
2024-03-22 11:10:39 -04:00
Tom Rini
5397daaed8 Merge tag 'efi-2024-04-rc5-2' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request efi-2024-04-rc5-2

Documentation:

* patman: Properly document the patchwork_url setting
* doc: man-page for if
* colibri-imx8x, apalis-imx8: update board documentation

UEFI:

* correct handling of EFI binary return code
* don't show usage help if EFI binary fails.
* correct error handling for bootefi selftest command
2024-03-21 08:35:23 -04:00
Douglas Anderson
fcd0c8b847 patman: Properly document the patchwork_url setting
The "Series-patchwork-url:" tag description says that it overrides the
settings file but doesn't specify the name of the setting. Elsewhere
in the documentation about the "useful" settings we see a setting that
sounds promising called "patchwork_server" that's actually not a valid
setting. It should be "patchwork_url".

Fix these problems so the doc is right and more useful.

Signed-off-by: Douglas Anderson <dianders@chromium.org>
2024-03-21 07:36:54 +01:00
Heinrich Schuchardt
98b5ea1881 doc: typo Synopis
%s/Synopis/Synopsis/g

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-03-21 07:29:19 +01:00
Heinrich Schuchardt
a9122d2c45 doc: man-page for if
Provide a man-page for the if command.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-03-21 07:29:01 +01:00
Heinrich Schuchardt
68fc0b877b cmd: bootefi: error handling bootefi selftest
If bootefi selftest is executed and a problem with the device-tree
installation occurs, efi_install_fdt() writes sensible error messages.
It never returns EFI_INVALID_PARAMETER. It neither makes sense to check
for EFI_INVALID_PARAMETER nor to show the usage help for the bootefi
command in this case.

Fixes: 296faf4f7e ("cmd: bootefi: re-organize do_bootefi()")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-03-21 07:28:43 +01:00
Heinrich Schuchardt
46e5dd661c cmd: bootefi: Don't show usage help if EFI binary fails.
If an EFI binary returns an error code EFI_INVALID_PARAMETER, we show the
usage help for the bootefi command:

    Shell> exit 0x8000000000000002
    ## Application failed, r = 2
    bootefi - Boots an EFI payload from memory

    Usage:
    bootefi <image address>[:<image size>] [<fdt address>]
      - boot EFI payload
    bootefi bootmgr [fdt address]
      - load and boot EFI payload based on BootOrder/BootXXXX variables.

        If specified, the device tree located at <fdt address> gets
        exposed as EFI configuration table.

This makes no sense.

Fixes: 296faf4f7e ("cmd: bootefi: re-organize do_bootefi()")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-03-21 07:28:43 +01:00
Heinrich Schuchardt
6f90a05a04 efi_loader: correct handling of EFI binary return code
We should not try to remove protocol interfaces from a NULL handle.
efi_run_image() should always return the return code of the executed EFI
binary.

Fixes: 6422820ac3 ("efi_loader: split unrelated code from efi_bootmgr.c")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-03-21 07:28:43 +01:00
Hiago De Franco
b9d4db4e0f doc: board: apalis-imx8: Update and improve documentation
Update and improve the building documentation of Apalis iMX8.
The following changes were made:
- imx-atf repository changed to nxp-imx GitHub.
- imx-atf branch updated to 'lf_v2.6'.
- imx-seco updated to version 5.8.7.
- nxp-imx mfgtools link updated to GitHub releases.
- General writing improvements.

Signed-off-by: Hiago De Franco <hiago.franco@toradex.com>
2024-03-21 07:25:06 +01:00
Hiago De Franco
fa0ed4c401 doc: board: colibri-imx8x: Update and improve documentation
Update and improve the building documentation of Colibri iMX8X.
The following changes were made:
- imx-atf repository changed to nxp-imx GitHub.
- imx-atf branch updated to 'lf_v2.6'.
- imx-seco updated to version 5.8.7.
- nxp-imx mfgtools link updated to GitHub releases.
- General writing improvements.

Signed-off-by: Hiago De Franco <hiago.franco@toradex.com>
Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com>
2024-03-21 07:25:06 +01:00
Tom Rini
6ec096a711 Merge tag 'u-boot-imx-master-20240317' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
CI:
https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/19974

- Fix build error when SoM detection on Phytec board.
- Fix sc_misc_otp_fuse_read() error check on colibri-imx8x/apalis-imx8.
- Fix NPU/VPU fdt disable fixup on i.MX8M.
2024-03-17 19:43:02 -04:00
Vitor Soares
e648c4a345 arm: imx: imx8m: soc: Fix NPU/VPU fdt disable fixup
On imx8m[m|p|q].dtsi, upstream Linux uses different names for NPU/VPU
IP block nodes. It leads variants without such HW block having it
enabled by default.

This patch adds the upstream Linux node's paths to the disable list while
keep the compatibility with downstream Linux.

Signed-off-by: Vitor Soares <vitor.soares@toradex.com>
Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com>
2024-03-17 18:00:04 -03:00
Fabio Estevam
cd7af7ee5a apalis-imx8: Fix sc_misc_otp_fuse_read() error check
Commit bfb3409d67 ("imx: toradex/apalis-imx8: correct SCU API usage")
made an incorrect logic change in the error code check of
sc_misc_otp_fuse_read():

-       if (scierr == SC_ERR_NONE) {
+       if (scierr) {
                /* QP has one A72 core disabled */
                is_quadplus = ((val >> 4) & 0x3) != 0x0;
        }

The other changes in this commit are correct.

sc_misc_otp_fuse_read() returns 0 on a successful fuse read.

This inversion causes board_mem_get_layout() to report incorrect RAM size.

Go back the original error check logic to fix the problem.

Fixes: bfb3409d67 ("imx: toradex/apalis-imx8: correct SCU API usage")
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2024-03-17 17:59:50 -03:00
Fabio Estevam
fdd529fa62 colibri-imx8x: Fix sc_misc_otp_fuse_read() error check
Commit aa6e698a7a ("imx: toradex/colibri-imx8x: correct SCU API usage")
made an incorrect logic change in the error code check of
sc_misc_otp_fuse_read():

-       if (sc_err == SC_ERR_NONE) {
+       if (sc_err) {
                /* DX has two A35 cores disabled */
                return (val & 0xf) != 0x0;
        }

The other changes in this commit are correct.

sc_misc_otp_fuse_read() returns 0 on a successful fuse read.

This inversion causes board_mem_get_layout() to report incorrect RAM size.

Go back the original error check logic to fix the problem.

Fixes: aa6e698a7a ("imx: toradex/colibri-imx8x: correct SCU API usage")
Reported-by: Hiago De Franco <hiago.franco@toradex.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-by: Hiago De Franco <hiago.franco@toradex.com> # Toradex Colibri iMX8X 1GB
2024-03-17 17:59:32 -03:00
Benjamin Hahn
e1897784aa board: phytec: define get_som_type also when SoM detection is disabled
define the phytec_get_som_type function also when the SoM detection is
disabled.

Fixes:
commit 110d321a56 ("board: phytec: common: phytec_som_detection: Add phytec_get_som_type")

Signed-off-by: Benjamin Hahn <B.Hahn@phytec.de>
2024-03-17 17:59:11 -03:00
Tom Rini
86fd291a79 Merge tag 'efi-2024-04-rc5' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request efi-2024-04-rc5

Documentation:

* fix Python string escapes
* develop: commands: Fix function prototype
* fix incorrect path Documentation
* fix mistyped "env flags" command
* board: phytec: phycore-am62x: Update artifact names

UEFI:

* Invoke ft_board_setup() before efi_carve_out_dt_rsv()
2024-03-13 20:39:46 -04:00
Tom Rini
a81242099c Merge tag 'mips-fixes-for-v2024.04' of https://source.denx.de/u-boot/custodians/u-boot-mips
- mips: implement __udivdi3 to fix building of SquashFS
- mips: fix bug in cache init on MIPS32r2 or later
2024-03-13 17:15:46 -04:00
Daniel Schwierzeck
6806a133cd mips: fix change_k0_cca()
The intention of change_k0_cca() is to read the C0.Config register into
register $t0, update $t0 with the new cache coherency mode passed in $a0
and write back $t0 to C0.Config. With MIPS32 R2 or later instruction
sets, this can be achieved with a single instruction with INS. The
source and destination register of the INS instruction is passed as
first parameter. In case of change_k0_cca() it is register $t0. But
for writing back the updated value to C0.Config, the incorrect $a0
register is used. This is only correct in the MIPS32 R1 code path.

Fix the `mtc0` instruction to write back the value of the $t0 register.
Fix the MIPS32 R1 code path to also store the updated value in $t0.

Reported by user ddqxy138 on Github.
b838586086

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2024-03-13 21:15:40 +01:00
Linus Walleij
811dd44b0b mips: implement __udivdi3
Squashfs wasn't compiling because the lldiv() directives
turn into __udivdi3 and we are using private libgcc.

After this squashfs compiles for MIPS.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Tested-by: Bartel Eerdekens <barteleerdekens@gmail.com>
2024-03-13 21:15:40 +01:00
Heinrich Schuchardt
c8a2567475 doc: fix incorrect path Documentation
When copying the build system for Linux we missed to replace some
instances of 'Documentation' by 'doc'.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-03-13 08:16:16 +01:00
Benjamin Gray
b13297cc45 doc/sphinx: fix Python string escapes
Python 3.6 introduced a DeprecationWarning for invalid escape sequences.
This is upgraded to a SyntaxWarning in Python 3.12, and will eventually
be a syntax error.

Fix these now to get ahead of it before it's an error.

Signed-off-by: Benjamin Gray <bgray@linux.ibm.com>
Message-ID: <20230912060801.95533-3-bgray@linux.ibm.com>
Signed-off-by: Jonathan Corbet <corbet@lwn.net>

Adapted for U-Boot
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-03-13 08:16:16 +01:00
Wadim Egorov
f99a1e241f doc: board: phytec: phycore-am62x: Update artifact names
Use proper binary artifact names for HSFS devices.
Do not use the *_unsigned binaries.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
2024-03-13 08:10:00 +01:00
Alexander Dahl
27987b86a0 doc: develop: commands: Fix function prototype
When using the previous prototype you got a compiler warning like this:

    warning: initialization of 'int (*)(struct cmd_tbl *, int,  int,  char * const*)' from incompatible pointer type 'int (*)(struct cmd_tbl *, int,  int,  const char **)' [-Wincompatible-pointer-types]

Fixes: 3d9640f55c ("doc: expand README.commands")
Signed-off-by: Alexander Dahl <ada@thorsis.com>
2024-03-13 08:09:23 +01:00
Mark Kettenis
1431ab8b6c efi_loader: Don't carve out memory reservations too early
Moving the efi_carve_out_dt_rsv() call in commit 1be415b21b
("efi_loader: create memory reservations in ACPI case")
broke boards that create additional memory reservations in
ft_board_setup() since it is now called before those additional
memory reservations are made.  This is the case for the rk3588
boards and breaks booting OpenBSD on those boards.

Move the call back to its original location and add a call in
the code path used for ACPI.

Fixes: 1be415b21b ("efi_loader: create memory reservations in ACPI case")
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-03-13 08:06:57 +01:00
Thomas Weißschuh
0dc8cbda52 doc: fix mistyped "env flags" command
Signed-off-by: Thomas Weißschuh <thomas@t-8ch.de>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2024-03-13 08:05:42 +01:00
Tom Rini
7422f661e2 Merge https://source.denx.de/u-boot/custodians/u-boot-riscv
* riscv: lib: improve extension detection
* riscv: sbi: fix display format and global variable storage
* sifive: fu740: reduce DDR speed
* board: starfive vf2: switch to standard boot and fix DTS
2024-03-12 09:53:06 -04:00
Minda Chen
544af8207c board: starfive: maintainer: Add visionfive2 PCIe driver
Add PCIe driver file to visionfive2 board MAINTAINERS list.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-03-12 14:36:13 +08:00
Minda Chen
999c7ed418 board: starfive: Update maintainer of VisionFive v2 board
Update the maintainer of Starfive VisionFive v2 board.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-03-12 14:36:13 +08:00
Heinrich Schuchardt
3a223ff63c cmd: sbi: formatting PolarFire Hart Software Services version
The 'PolarFire Hart Software Services' SBI implementation returns the
version of the incorporated OpenSBI. Format the number accordingly.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
2024-03-12 14:36:13 +08:00
Heinrich Schuchardt
4de6d37fa2 cmd: sbi: Correctly display unknown implementation IDs
For an unknown implementation ID an output like

    SBI 1.0Unknown implementation ID 16777216
    Extensions:
      sbi_set_timer
      ...

was shown. The number 16777216 is not the implementation ID.

* Show the correct number
* Use a hexadecimal output format
* Add a missing line feed

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Dan Carpenter <dan.carpenter@linaro.org>
2024-03-12 14:36:13 +08:00
Bo Gan
e6b7aeef3d riscv: dts: jh7110: Enable PLL node in SPL
Previously PLL node was missing from SPL dts. This caused BUS_ROOT
to stay on OSC clock (24Mhz). As a result, all peripherals have to
run at a much lower frequency, and loading from sdcard/emmc is slow.
Thus, enabling PLL node in dts to fix this.

Signed-off-by: Bo Gan <ganboing@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-03-12 14:36:13 +08:00
Conor Dooley
0d95add3b1 riscv: cpu: improve multi-letter extension detection in supports_extension()
The first multi-letter extension after the single-letter extensions does
not have to be preceded by an underscore, which could cause the parser
to mistakenly find a single-letter extension after the start of the
multi-letter portion of the string.
Three letters precede multi-letter extensions (s, x & z), none of which
are valid single-letter extensions. The dt-binding also allows
multi-letter extensions starting with h, but no such extension have been
frozen or ratified, and the unprivileged spec no longer uses "h" as a
prefix for multi-letter hypervisor extensions, having moved to "sh"
instead. For that reason, modify the parser to stop at s, x & z to prevent
this overrun, ignoring h.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-03-12 14:36:13 +08:00
Leon M. Busch-George
e1d7ff220c riscv: dts: jh7110: fix indentation
Signed-off-by: Leon M. Busch-George <leon@georgemail.eu>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-03-12 14:36:13 +08:00
Heinrich Schuchardt
25e7d4bf64 serial: move sbi_dbcn_available to .data section
U-Boot SPL loads the device-tree directly behind main U-Boot overlapping
the .bss section. reserve_fdt() is called in board_init_f() to relocate the
device-tree to a safe location.

Debug UARTs are enabled before board_init_f(). With sbi_dbcn_available in
the .bss section the device-tree is corrupted when _debug_uart_init() is
called in the SBI serial driver. Move the variable to the .data section.

Link: https://bugs.launchpad.net/ubuntu/+source/u-boot/+bug/2054091
Fixes: dfe0837494 ("risc-v: implement DBCN based debug console")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Tested-by: Aurelien Jarno <aurelien@aurel32.net>
Tested-by: Conor Dooley <conor.dooley@microchip.com>
2024-03-12 14:36:13 +08:00
Thomas Perrot
7480282eca riscv: sifive: fu740: reduce DDR speed from 1866MT/s to 1600MT/s
It appears that there is some timing marginality either in the
board layout or the SoC that results in occasional data corruption
on some boards.
We observed this issue on some of the new HiFive Unmatched RevB
boards during volume production as well as some of the original
HiFive Unmatched boards from 2021 in our possession. This means
that there are other boards out there that might have the issue
too.

We have done some limited testing with DDR4 at 1600MT/s and
faulty boards (failing at 1866MT/s) passed.
We plan further testing after we procure a temperature chamber.

Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-03-12 14:36:13 +08:00
Nam Cao
e3a904a690 starfive: visionfive2: switch to standard boot
Distro boot scripts are deprecated. Use standard boot instead.

Signed-off-by: Nam Cao <namcao@linutronix.de>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-03-12 14:36:13 +08:00
Tom Rini
f3c979dd00 Prepare v2024.04-rc4
Signed-off-by: Tom Rini <trini@konsulko.com>
2024-03-11 13:11:46 -04:00
Tom Rini
da07a629e1 Merge tag 'u-boot-imx-master-20240311' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
- Use TF-A on imx8mp_beacon to fix boot regression.
- Use latest 6.8 dts for imx8mp_beacon.
- Fix the RAM initialization for phycore_imx8mp PCL-070 rev 1.
- Describe the 0087 i.mx8m mini product variant in tdx-cfg-block.
2024-03-11 09:22:44 -04:00
Tom Rini
b8ed8b1376 configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2024-03-11 09:10:24 -04:00
Adam Ford
4484c7b3c3 arm: dts: imx8mp-beacon-kit: Resync DTS with Linux 6.8
The device tree has evolved over time, so re-sync.  This also
partial reverts one change on the PCIe, because U-Boot doesn't
have a proper driver.  However, since the clock is configured
to generate a 100MHz reference clock by default, a proper driver
isn't really necessary.

Signed-off-by: Adam Ford <aford173@gmail.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
2024-03-11 08:43:42 -03:00
Joao Paulo Goncalves
12d3257fa2 toradex: tdx-cfg-block: add 0087 i.mx8m mini product variant
Add new product id 0087 Verdin iMX8M Mini Quad 2GB IT.

Signed-off-by: Joao Paulo Goncalves <joao.goncalves@toradex.com>
2024-03-11 08:43:27 -03:00
Adam Ford
383d4b130c configs: imx8mp_beacon: Fall back to using TF-A
When the board was originally added, it enabled some features which
allowed it to bypass Trusted Firmware, but as the feature set of
Linux grew and more features became available, the U-Boot config
options which bypassed TF-A caused issues, so it needs to return
to the standard operating mode of using TF-A or the system no
longer boots.

Fixes: ab53bd43db ("arm64: imx: Add support for imx8mp-beacon-kit")
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2024-03-11 08:43:08 -03:00
Benjamin Hahn
76832300a9 board: phycore_imx8mp: Use 2GHz RAM timings for PCL-070 from pcb_rev 1
We need to differ between PCL-070 and PCM-070. PCL-070 supports 2GHz RAM
timings from pcb rev 1 or newer. PCM-070 supports 2GHz RAM timings from
pcb rev 3 or newer.

Signed-off-by: Benjamin Hahn <B.Hahn@phytec.de>
2024-03-11 08:42:44 -03:00
Benjamin Hahn
110d321a56 board: phytec: common: phytec_som_detection: Add phytec_get_som_type
Add a function that gets the som_type from the EEPROM.
Add an enum for the som_type.

Signed-off-by: Benjamin Hahn <B.Hahn@phytec.de>
2024-03-11 08:42:44 -03:00
Tom Rini
0981f8900f Merge https://source.denx.de/u-boot/custodians/u-boot-usb
- Singular quirk DT property rename.
2024-03-09 11:29:48 -05:00
Marek Vasut
91e70367a5 net: phy: Use PHY MDIO address from DT if available
In case the PHY is fully described in DT, use PHY MDIO address
from DT directly instead of always using auto-detection. This
also fixes the behavior of 'mdio list' in such DT setup, which
now prints the PHY connected to the MAC correctly.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
2024-03-09 10:58:48 -05:00
Tom Rini
485bfe1adb Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-marvell
- net: mv88e6xxx: fix missing SMI address initialization (Marek)
- mvebu: turris_omnia: Enable networking via ethernet switch (Marek)
- mvebu: helios-4: add config fragment for spi booting et al (Josua)
- rng: Add Turris Mox rTWM RNG driver (Max)
2024-03-05 07:08:55 -05:00
Tom Rini
46e3871aa6 Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi
One fix makes the reboot more robust on some older board, another one
stabilises the initial clock setup on the A10/A20.
Two patches make sure our DRAM init does not actually change the content
of the DRAM array, which allows to use DRAM for Linux' pstore
functionality.
We get SPI support for U-Boot proper for one more SoC, that patch was
lingering around for a while, and should not affect other SoCs, so I am
merging this now.
As an added bonus, we get the defconfig file for a new board, the DT was
already synced from the kernel tree.

The CI looked happy with changes, and I tested them on five different
boards with different SoCs.
2024-03-05 07:08:10 -05:00
Max Resch
d61b485dbd rng: Add Turris Mox rTWM RNG driver
A RNG driver for Armada 3720 boards running the Turris Mox rWTM firmware
from CZ.NIC in the secure processor.

Signed-off-by: Max Resch <resch.max@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2024-03-05 08:27:59 +01:00
Josua Mayer
e587040706 board: helios-4: add config fragment for spi booting
Add a config fragment with required differences for booting from spi
flash instead of sd-card (default).

Settings for environment location are based on vendor u-boot:
https://github.com/kobol-io/u-boot/blob/helios4/include/configs/helios4.h#L59

The fragment can be applied on top of helios4_defconfig by make:
make helios4_defconfig spiboot.config

Signed-off-by: Josua Mayer <josua@solid-run.com>
2024-03-05 08:27:59 +01:00
Josua Mayer
18c73e30e1 arm: mvebu: helios4_defconfig: enable setexpr command
Update the helios4 defconfig to enable the 'setexpr' command, which is a
default and useful for various complex boot-scripts.

Signed-off-by: Josua Mayer <josua@solid-run.com>
2024-03-05 08:27:59 +01:00
Josua Mayer
52f7530e2d arm: dts: armada-38x-solidrun-microsom: configure i2c0 bus
SolidRun Armada-388 SoM has an i2c bus supporting on-som eeprom, and
peripherals on a carrier.
armada-38x.dtsi disables this bus by default, it should be enabled by
som or carrier dts.

Linux has moved i2c0 from helios-4 board dts to som dtsi, including
status, pinctrl and clock speed.
Copy these settings from mainline.

This fixes accessing i2c bus from u-boot commandline.

Signed-off-by: Josua Mayer <josua@solid-run.com>
2024-03-05 08:27:59 +01:00
Marek Mojík
f56591d326 arm: mvebu: turris_omnia: Enable networking via ethernet switch
The Turris Omnia contains the Marvell 88E6176 ethernet switch. Add
config options and device tree to enable the support.

Signed-off-by: Marek Mojík <marek.mojik@nic.cz>
Signed-off-by: Marek Behún <kabel@kernel.org>
2024-03-05 08:27:59 +01:00
Marek Mojík
faf96b20ee net: mv88e6xxx: fix missing SMI address initialization
The mv88e6xxx driver does not currently initialize the smi_addr field, but
instead keeps the default zero value. This leads to driver being unusable
on devices where the switch is not on address zero of the mdio bus. Fix
this problem by reading the SMI address from device tree.

Signed-off-by: Marek Mojík <marek.mojik@nic.cz>
Reviewed-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2024-03-05 08:27:59 +01:00
Andrey Skvortsov
f1e6a718eb sunxi: restore modified memory
Current sunxi DRAM initialisation code does several test accesses to the
DRAM array to detect aliasing effects and so determine the correct
row/column configuration. This changes the DRAM content, which breaks
use cases like soft reset and Linux's ramoops mechanism.

Fix this problem by saving and restoring the content of the DRAM cells
that is used for the test writes.

Signed-off-by: Andrey Skvortsov <andrej.skvortzov@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2024-03-05 01:16:56 +00:00
Andrey Skvortsov
978808d2b9 sunxi: reorganize mctl_mem_matches_* functions
mctl_mem_matches and mctl_mem_matches_base identical functions. To
avoid code duplication move them to dram_helpers and make
mctl_mem_matches use generic mctl_mem_matches_base.

Signed-off-by: Andrey Skvortsov <andrej.skvortzov@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2024-03-05 01:16:44 +00:00
Jonas Karlman
52378ba496 usb: xhci-dwc3: Fix support for dis_enblslpm_quirk
No device tree in U-Boot or linux use the wrong spelling used in code.

Use correct property name as defined in dwc3 bindings.

Fixes: 062790f461 ("usb: xhci-dwc3: Add USB2 PHY configuration")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Marek Vasut <marex@denx.de>
2024-03-05 01:04:21 +01:00
Tom Rini
773cb2bca7 Merge tag 'u-boot-imx-master-20240304' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/19817

- Fix i.MX93 OP-TEE support.
- Use the container image for i.MX93 revision A1.
- Fix display regression on opos6uldev.
2024-03-04 15:41:38 -05:00
Sébastien Szymanski
9b9f022e73 video: mxsfb: add back imx6ul/imx6ull support
Because of commit bf947d2a4b ("imx6ul: synchronise device tree with
linux"), the compatible property of lcdif in imx6ul.dtsi went from

compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif";

to

compatible = "fsl,imx6ul-lcdif", "fsl,imx6sx-lcdif";

without updating the mxsfb driver to match that change.

Add "fsl,imx6sx-lcdif" as a compatible id to fix that.

Fixes: bf947d2a4b ("imx6ul: synchronise device tree with linux")
Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
2024-03-04 08:18:48 -03:00
Sébastien Szymanski
64ca8db96e opos6uldev: make the LCD work again
Commit 5d7a95f499 ("imx6ul/imx6ull: synchronise device trees with
linux") removed the display timings from the board device tree whereas
they are still needed by the mxsfb driver.
Add the timings back (the correct ones) in the
imx6ul-opos6uldev-u-boot.dtsi file and remove them from the
opos6uldev.env file.

Update the opos6uldev_defconfig file so that the LCD turns on at boot.

Fixes: 5d7a95f499 ("imx6ul/imx6ull: synchronise device trees with linux")
Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
2024-03-04 08:18:48 -03:00
Mathieu Othacehe
71e2082010 imx9: Update to mx93 A1 chip revision.
Use the latest, mx93a1-ahab-container.img that is compatible with the
i.MX93 A1 revision.

Using mx93a1-ahab-container.img on an A0 chip and conversely causes a boot
failure without any traces on the UART.

Signed-off-by: Mathieu Othacehe <othacehe@gnu.org>
2024-03-04 08:18:27 -03:00
Mathieu Othacehe
867f97e1c4 tools: imx9_image: Reword warning message.
If the optional `tee.bin` OP-TEE binary is missing, the image will still be
functional. Adapt the warning message accordingly.

Signed-off-by: Mathieu Othacehe <othacehe@gnu.org>
2024-03-04 08:18:13 -03:00
Mathieu Othacehe
c2666fdab6 imx9: Fix OP-TEE support
This fixes OP-TEE support by:

- Adding tee.bin to container.cfg
- Starting ELE RNG in SPL

Signed-off-by: Mathieu Othacehe <othacehe@gnu.org>
2024-03-04 08:18:13 -03:00
Andre Przywara
bc6e594104 sunxi: H616: Add OrangePi Zero 2W board support
The OrangePi Zero 2W is a tiny development board featuring the Allwinner
H618 SoC, shipping with up to 4GB of LPDDR4 DRAM, a mini-HDMI connector,
two USB Type-C sockets and a 16MB SPI NOR flash.
There is an FPC connector to connect an expansion board, which sports
two more USB Type-A sockets and a 100MBit Ethernet port. Support for
the expansion board is not in the DT yet, probably a DT overlay would
cover this in the future.

Add a defconfig file selecting the right drivers and DRAM options.
Since the .dts file was synced from the Linux kernel repo already, we
just need to add one line to the Makefile to actually build the .dtb.

The DRAM parameters were derived from the values found in the BSP DRAM
drivers on the SPI NOR flash.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2024-03-03 23:43:43 +00:00
Ludwig Kormann
3b08e66f69 sunxi: sun4i: add missing sdelay() to clock_init_safe()
This delay is required after switching the clock source.

See “A20 Reference manual v1.4” Page 50 / section
“1.5.4.16. CPU/AHB/APB0 CLOCK RATIO”: “If the clock
source is changed, at most to wait for 8 present running
clock cycles.”

This is already implemented in clock_set_pll1(), but was
still missing in clock_init_safe().

Signed-off-by: Ludwig Kormann <ludwig.kormann@ict42.de>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2024-03-03 23:43:43 +00:00
Philippe Coval
c93a6fc8f5 arm: sunxi: Reduce inrush current on Olimex A20-OLinuXino_MICRO configs
This change fix reboot, both configurations
were tested on my Olimex A20 Micro Rev E with debian-12.

This issue was also present and fixed on A20 Lime2 (in 8311e84b18),
quoting Olliver Schinagl:

    The lime2 features a too large capacitor on the LDO3 output, which
    causes the PMIC to shutdown when enabling power. To be able to still
    boot up however, we must gradually enable power on LDO3 for this board.
    We do this by enabling both the inrush quirk and the maximum slope the
    AXP209 supports.

Link: https://bugs.debian.org/1060752
Cc: Olliver Schinagl <oliver@schinagl.nl>
Cc: Priit Laes <plaes@plaes.org>
Cc: Maxime Ripard <mripard@kernel.org>
Signed-off-by: Philippe Coval <rzr@users.sf.net>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2024-03-03 23:43:43 +00:00
Maksim Kiselev
2b9d6a1843 spi: sunxi: Add support for R329/D1/R528/T113 SPI controller
These SoCs have two SPI controllers that are quite similar to the SPI
on previous Allwinner SoCs. The main difference is that new SoCs
don't have a clock divider (SPI_CCR register) inside SPI IP.

Instead SPI sample mode should be configured depending on the input clock.

For now SPI input clock source selection is not supported by this driver,
and only HOSC@24MHz can be used as input clock. Therefore, according to
the, manual we could change the SPI sample mode from delay half
cycle(default) to normal.

This patch adds a quirk for this kind of SPI controllers

Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com>
Tested-by: Sam Edwards <CFSworks@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2024-03-03 23:43:43 +00:00
Tom Rini
eac52e4be4 Merge patch series "ARM: renesas: Rename R-Mobile to Renesas"
Marek Vasut <marek.vasut+renesas@mailbox.org> says:

Rename R-Mobile to Renesas all over the place because the chips are
made by Renesas, while only a subset of them is from the R-Mobile line.
2024-03-02 14:30:25 -05:00
Marek Vasut
7b1a24765d git-mailrc: Add renesas entry and update rmobile entry
Add new renesas entry and update rmobile entry to match.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
2024-03-02 14:29:37 -05:00
Marek Vasut
0afbd11325 mmc: renesas-sdhi: Rename rmobile_is_gen3_mmc0() to rcar_is_gen3_mmc0()
Rename rmobile_is_gen3_mmc0() to rcar_is_gen3_mmc0() because
this particular function is specific to Renesas R-Car Gen3.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
2024-03-02 14:29:37 -05:00
Marek Vasut
f252dfbf46 ARM: renesas: Post rename fix ups
Fix up remains of rename from rmobile to renesas,
namely file paths and remaining RMOBILE strings.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
2024-03-02 14:29:36 -05:00
Marek Vasut
40b9d53c74 ARM: renesas: Rename arch-/mach-rmobile to arch-/mach-renesas
Rename arch-rmobile to arch-renesas and mach-rmobile to mach-renesas
because all the chips are made by Renesas, while only a subset of
them is from the R-Mobile line.

Use the following command to perform the rename, with manual move of
the directories using git mv and manual fix up to arch/arm/Makefile:

"
$ git grep -l '\<\(arch\|mach\)-rmobile\>' | \
  xargs -I {} sed -i 's@\<\(arch\|mach\)-rmobile\>@\1-renesas@g' {}
$ sed -i 's@rmobile@renesas@' board/*/*/Kconfig
"

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
2024-03-02 14:29:36 -05:00
Marek Vasut
f9aabd4579 ARM: renesas: Rename ARCH_RMOBILE to ARCH_RENESAS
Rename ARCH_RMOBILE to ARCH_RENESAS because all the chips are made
by Renesas, while only a subset of them is from the R-Mobile
line.

Use the following command to perform the rename:

"
$ git grep -l 'ARCH_RMOBILE' | xargs -I {} sed -i 's@ARCH_RMOBILE@ARCH_RENESAS@g' {}
"

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
2024-03-02 14:29:36 -05:00
Marek Vasut
65abdd1978 ARM: renesas: Rename rmobile.h to renesas.h
Rename rmobile.h to renesas.h because all the chips are made
by Renesas, while only a subset of them is from the R-Mobile
line.

Use the following command to perform the rename:

"
$ git grep -l 'include.*rmobile.h' | \
  xargs -I {} sed -i '/include.*rmobile.h/ s@rmobile.h@renesas.h@g' {}
"

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
2024-03-02 14:29:36 -05:00
Marek Vasut
436eadfe13 ARM: renesas: Rename CONFIG_ARCH_RMOBILE_EXTRAM_BOOT to CONFIG_RENESAS_EXTRAM_BOOT
Rename CONFIG_ARCH_RMOBILE_EXTRAM_BOOT to CONFIG_RMOBILE_EXTRAM_BOOT
because the former symbol does not exist and it is only incorrectly
converted CONFIG_RMOBILE_EXTRAM_BOOT which does exist. Replace the
RMOBILE with RENESAS because all the chips are made by Renesas, while
only a subset of them is from the R-Mobile line.

Use the following command to perform the rename with manual Kconfig.32 fix:

"
$ sed -i 's@CONFIG_ARCH_RMOBILE_EXTRAM_BOOT@CONFIG_RMOBILE_EXTRAM_BOOT@g' board/renesas/*/*
$ sed -i 's@CONFIG_RMOBILE_EXTRAM_BOOT@CONFIG_RENESAS_EXTRAM_BOOT@g' board/renesas/*/*
"

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
2024-03-02 14:29:36 -05:00
Marek Vasut
69aa7ab250 ARM: renesas: Rename ARCH_RMOBILE_BOARD_STRING to ARCH_RENESAS_BOARD_STRING
Rename ARCH_RMOBILE_BOARD_STRING to ARCH_RENESAS_BOARD_STRING
because all the chips are made by Renesas, while only a subset
of them is from the R-Mobile line.

Use the following command to perform the rename:

"
$ git grep -l 'ARCH_RMOBILE_BOARD_STRING' | \
  xargs -I {} sed -i 's@ARCH_RMOBILE_BOARD_STRING@ARCH_RENESAS_BOARD_STRING@g' {}
"

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
2024-03-02 14:29:36 -05:00
Marek Vasut
82026c4779 ARM: renesas: Rename rmobile_get_prr() to renesas_get_prr()
Rename rmobile_get_prr() to renesas_get_prr() because all the
chips are made by Renesas, while only a subset of them is from
the R-Mobile line.

Use the following command to perform the rename:

"
$ git grep -l '\<rmobile_get_prr\>' | \
  xargs -I {} sed -i 's@\<rmobile_get_prr\>@renesas_get_prr@g' {}
"

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
2024-03-02 14:29:36 -05:00
Marek Vasut
217d7191b1 ARM: renesas: Simplify weak symbols
Simplify the weak symbols use in cpu_info.c by using the __weak macro.
The result is identical, but the syntax is much simpler. Furthermore,
drop three more rmobile* symbols which are now unused.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
2024-03-02 14:29:36 -05:00
Marek Vasut
18c3f3a265 ARM: renesas: Rename rmobile_cpuinfo[] to renesas_cpuinfo[]
Rename rmobile_cpuinfo[] to renesas_cpuinfo[] because all
the chips are made by Renesas, while only a subset of them
is from the R-Mobile line.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
2024-03-02 14:29:36 -05:00
Marek Vasut
74215bb0b0 ARM: renesas: Rename rmobile_cpuinfo_idx() to renesas_cpuinfo_idx()
Rename rmobile_cpuinfo_idx() to renesas_cpuinfo_idx() because all
the chips are made by Renesas, while only a subset of them is from
the R-Mobile line.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
2024-03-02 14:29:36 -05:00
Marek Vasut
c2cffb01aa ARM: renesas: Rename RMOBILE_CPU_TYPE_* to RENESAS_CPU_TYPE_*
Rename RMOBILE_CPU_TYPE_* to RENESAS_CPU_TYPE_* because all
the chips are made by Renesas, while only a subset of them is
from the R-Mobile line.

Use the following command to perform the rename:

"
$ git grep -l '\<RMOBILE_CPU_TYPE_[A-Z0-9]\+\>' | \
  xargs -I {} sed -i 's@\<RMOBILE\(_CPU_TYPE_[A-Z0-9]\+\)\>@RENESAS\1@g' {}
"

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
2024-03-02 14:29:36 -05:00
Marek Vasut
ca40ed6d7f ARM: renesas: Rename rmobile_get_cpu_rev_*() to renesas_get_cpu_rev_*()
Rename rmobile_get_cpu_rev_*() to renesas_get_cpu_rev_*() because
all the chips are made by Renesas, while only a subset of them is
from the R-Mobile line.

Use the following command to perform the rename:

"
$ git grep -l '\<rmobile_get_cpu_rev_\(integer\|fraction\)\>' | \
  xargs -I {} sed -i 's@\<rmobile_get_cpu_rev_\(integer\|fraction\)\>@renesas_get_cpu_rev_\1@g' {}
"

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
2024-03-02 14:29:36 -05:00
Marek Vasut
6bd3a95b67 ARM: renesas: Rename rmobile_get_cpu_type() to renesas_get_cpu_type()
Rename rmobile_get_cpu_type() to renesas_get_cpu_type() because
all the chips are made by Renesas, while only a subset of them
is from the R-Mobile line.

Use the following command to perform the rename:

"
$ git grep -l '\<rmobile_get_cpu_type\>' | \
  xargs -I {} sed -i 's@\<rmobile_get_cpu_type\>@renesas_get_cpu_type@g' {}
"

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
2024-03-02 14:29:36 -05:00
Marek Vasut
9a2614b458 ARM: renesas: Drop unused pfc-r8a7790.h
This file is no longer used, the PFC pin controller driver is
superseded by drivers/pinctrl/renesas/pfc-r8a7790.c which
includes all the details of the hardware. Remove this file.
No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
2024-03-02 14:29:36 -05:00
Marek Vasut
9115349e5b ARM: renesas: Drop unused mmc.h
This file is no longer used, the MMCIF controller driver is
superseded by drivers/mmc/sh_mmcif.c which includes all the
details of the hardware. Remove this file include from all
board files and remove the file itself. No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
2024-03-02 14:29:35 -05:00
Marek Vasut
a8ac0f336d ARM: renesas: Drop unused sh_sdhi.h
This file is no longer used, the SDHI controller driver is long
superseded by drivers/mmc/renesas-sdhi.c which includes all the
details of the hardware. Remove this file include from all board
files and remove the file itself. No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
2024-03-02 14:29:35 -05:00
Marek Vasut
c13a8f9370 ARM: renesas: Drop remnants of R8A7740 support
Last board with this SoC has been removed in commit
0fb054b3f7 ("arm: Remove armadillo-800eva board")
in August 2022. Drop the rest of unused code.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
2024-03-02 14:29:35 -05:00
Tom Rini
574aac1c8c Merge branch 'master-riic' of https://source.denx.de/u-boot/custodians/u-boot-sh
- New renesas I2C controller driver and new PMIC driver along with
  enablement of them.
2024-03-02 12:27:21 -05:00
Heinrich Schuchardt
cf6280371f dtoc: avoid invalid escape sequence '\s'
\s is not a valid escape sequence in strings.
Mark regular expressions with r''.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-03-01 09:53:47 -05:00
Florian Schmaus
d4c84d7062 pylibfdt: Fix "invalid escape sequence '\w'" in setup.py
Once u-boot's build system invokes

python3 scripts/dtc/pylibfdt/setup.py --quiet build_ext --inplace

it may fail with

scripts/dtc/pylibfdt/setup.py:40: SyntaxWarning: invalid escape sequence '\w'
  RE_KEY_VALUE = re.compile('(?P<key>\w+) *(?P<plus>[+])?= *(?P<value>.*)$')

depending on the used Python version.

Explicitly mark the regex string as raw string to avoid the warning.

Signed-off-by: Florian Schmaus <flo@geekplace.eu>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-03-01 09:53:47 -05:00
Aradhya Bhatia
72703c7a0d arm: mach-k3: Refactor QoS settings
Refactor common QoS code into a new common header file, and the soc
specific setup_qos functions into a common API.

Rename $(soc)_qos_count and $(soc)_qos_data variables to qos_count and
qos_data. When QoS settings of more SoCs are added, only one pair will
be defined at a time, based on the config SOC_K3_$(soc).

This refactoring has been done for 2 major purposes.

- The auto-generated $(soc)_qos_data.c and $(soc)_qos.h files cannot
  have any code that is specific to any bootloader. Those files have to
  remain agnostic of different bootloader implementations and their
  header files.

- The existing implementation was less than ideal and would have enabled
  multiple $(soc)_qos_count and $(soc)_qos_data variables for all SoC
  variants.

Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com>
2024-03-01 09:15:58 -05:00
Vitor Soares
8fb8a6d499 arm: dts: k3-am625-verdin-r5: Change CPU frequency to 1000MHz
The same U-Boot binary is compatible with multiple Verdin AM62 board
variants. However, some of the SoC models can only operate at a maximum
speed of 1 GHz.

Previously, the boards with lower-speed grades were running at
overclocked speeds, leading to kernel complaints about unsupported
configurations.

To resolve this issue, the operating speed has been decreased to the
maximum allowable value across all Verdin AM62 board variants. As a
result, there is a regression in overall boot time, increasing by around
200 milliseconds for the faster SoC variant.

Signed-off-by: Vitor Soares <vitor.soares@toradex.com>
Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com>
2024-03-01 09:15:58 -05:00
Tom Rini
44a15c3f4e Merge patch series "toradex: fix reset and hardware detection regressions"
Francesco Dolcini <francesco.dolcini@toradex.com> says:

This series fixes two regressions affecting multiple Toradex boards
(i.MX, TI and TEGRA based) and targets the current master, e.g. v2024.04
release.

U-Boot `reset` command is broken on all Tordex i.MX6* based SoMs since
v2023.07, this series fixes it enabling the `wdt-reboot` driver.

Since v2024.04-rc1 reading the Toradex configuration block is not working
properly anymore, the serial number and the hardware version are not read
correctly, preventing the board from functioning correctly (wrong mac address,
wrong DT, ...). This is fixed by reading the config block in `EVT_SETTINGS_R`
and adding a toradex sysinfo driver. In addition to that, we now use a random
mac address in case the config block is invalid.

Reported-by: Sahaj Sarup <sahaj.sarup@linaro.org>
Closes: https://lore.kernel.org/all/CAKZ1LvM45MB8N0CqgU+C7i9=Bjb6kqNTxWo2Tv407HKLWtCMkA@mail.gmail.com/
Reported-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Closes: https://lore.kernel.org/all/e40ed93bd8f371ec56b8fc451dcb458f3ce6dcba.camel@toradex.com/
Reported-by: Francesco Dolcini <francesco@dolcini.it>
Closes: https://lore.kernel.org/all/ZY2ZDWAQuTlRjV9H@francesco-nb/
2024-03-01 09:14:36 -05:00
Parth Pancholi
be23b1331f toradex: imx6*: fix reset using wdt-reboot driver
commit 68dcbdd594 ("ARM: imx: Add weak default reset_cpu()")
introduced a regression that 'reset' command unable to reset
imx6 and imx6ull based Toradex's modules in the u-boot.

This change enables a watchdog-based sysreset driver for
Toradex's colibri-imx6, colibri-imx6ull (with nand and emmc)
and apalis-imx6 which solves the reset command regression on
these modules.

Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Fixes: 68dcbdd594 ("ARM: imx: Add weak default reset_cpu()")
Signed-off-by: Parth Pancholi <parth.pancholi@toradex.com>
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2024-03-01 09:10:44 -05:00
Emanuele Ghidoli
f271276fb0 toradex: common: Use random mac address if toradex config block is missing
Set CONFIG_NET_RANDOM_ETHADDR=y, which sets random eth address in
case there is no toradex config block programmed.
In case of missing toradex config block the generated mac address was
always the same, linked to serial number 0.
Use random generated mac address instead.

Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> # Verdin iMX8M Plus
Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2024-03-01 09:10:44 -05:00
Emanuele Ghidoli
2abc3bbe0c toradex: common: Add sysinfo driver
This commit introduces support for the Toradex sysinfo driver in U-Boot,
which uses information from Toradex config block to print correct
board model.
In case the Toradex config block is not present sysinfo prints the model
of the board provided by device tree removing per board specific prints.

Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> # Verdin iMX8M Plus
Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2024-03-01 09:10:44 -05:00
Emanuele Ghidoli
100121d51b arm: dts: Refactor device trees using "&{/aliases}" syntax
Use the common syntax to define aliases.

Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> # Verdin iMX8M Plus
Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2024-03-01 09:10:44 -05:00
Emanuele Ghidoli
118b17b84f toradex: common: Use SETTINGS_R event to read toradex config block
Use SETTINGS_R event to read toradex config block and checkboard()
to print board info.

Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> # Verdin iMX8M Plus
Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2024-03-01 09:10:44 -05:00
Emanuele Ghidoli
28138dea7b toradex: Remove not necessary model prints from checkboard()
Sysinfo prints the model obtained from device tree, checkboard()
take info from hardware and tdx_checkboard() use the model retrieved by
toradex config block.

Remove the print from checkboard() function because the model obtained
from toradex config block is the most complete.
If toradex config block is missing the model info from device tree is
enough.

Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> # Verdin iMX8M Plus
Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2024-03-01 09:10:44 -05:00
Emanuele Ghidoli
32b64893fb toradex: Fix recursive call to checkboard
Since checkboard() is used instead of show_board_info(), in case toradex
config block is missing or malformed, checkboard is recursively called.
It prints a long list of "MISSING TORADEX CONFIG BLOCK" till the stack
is full.

Fixes: edb0ecd187 ("toradex: Use checkboard() instead of show_board_info()")
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> # Verdin iMX8M Plus
Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2024-03-01 09:10:44 -05:00
Tom Rini
19f6576007 configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2024-03-01 09:10:04 -05:00
Paul Barker
3787ee1d2d board: rzg2l: Support reset via Renesas RAA215300 PMIC
With the SYSRESET subsystem enabled we do not need to implement
reset_cpu() in the board directory.

Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-02-28 18:42:27 +01:00
Paul Barker
a79f96112b pmic: raa215300: Bind sysreset driver
If SYSRESET support is enabled for the RAA215300 PMIC, we need to bind
the raa215300_sysreset driver as a child device of the PMIC.

Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-02-28 18:42:27 +01:00
Paul Barker
167eb89a21 sysreset: Support reset via Renesas RAA215300 PMIC
This patch adds support for resetting a board via the RAA215300 PMIC.

Note that the RAA215300 documentation names the available reset types
differently to u-boot:

  * A "warm" reset via the RAA215300 PMIC will fully reset the SoC
    (CPU & GPIOs), so this corresponds to SYSRESET_COLD.

  * A "cold" reset via the RAA215300 PMIC will cycle all power supply
    rails, so this corresponds to SYSRESET_POWER.

Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-02-28 18:42:27 +01:00
Paul Barker
0c25eaeba4 board: rzg2l: Enable access to Renesas RAA215300 PMIC
Enable the appropriate PMIC driver as well as the `pmic` command.

Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-02-28 18:42:27 +01:00
Paul Barker
af22872152 pmic: Add Renesas RAA215300 PMIC driver
The RZ/G2L SMARC module is powered via a Renesas RAA215300 PMIC which
provides several voltage converters, a real time clock (RTC) and reset
control. A basic driver is implemented for this device so that we can
read, write and dump the PMIC registers.

The raa215300_bind() function is added as a stub, binding of the
sysreset driver will be added in a later patch.

Additional features of this PMIC (such as reset control) may be
supported by future patches.

Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-02-28 18:42:27 +01:00
Paul Barker
266e36f7ec i2c: rzg2l: Add I2C driver for RZ/G2L family
This driver supports the I2C module on the Renesas RZ/G2L (R9A07G044)
SoC, also known as the RIIC module.

This patch is based on both the u-boot driver in the Renesas RZ BSP
3.0.5 release [1] (commit 7fcc1fdc2534), and the Linux v6.7 driver
(commit 0dd3ee311255).

Support for deblocking the I2C bus is included as this may be needed
after triggering a reset via the Power Management IC (PMIC) over I2C
(the PMIC asserts the reset line before the SoC completes the I2C write
transaction with obvious bus locking effects). If the SDA line is
observed to be low during initialisation, we automatically attempt to
deblock.

[1]: https://github.com/renesas-rz/renesas-u-boot-cip

Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-02-28 18:42:27 +01:00
Paul Barker
d4f0ff93c8 arm: dts: rzg2l: Sync with Linux v6.7
Pull in the recent changes to the RZ/G2L device tree and related dtsi
files so that we're aligned with Linux v6.7 (commit 0dd3ee311255).

Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-02-28 18:42:27 +01:00
Paul Barker
aecd69879d clk: renesas: Confirm all clock & reset changes on RZ/G2L
When enabling/disabling a clock or reset signal, confirm that the change
has completed before returning from the function. A somewhat arbitrary
100ms timeout is defined to ensure that the system doesn't lock up in
the case of an error.

Since we need to dynamically determine if we're waiting for a 0 bit or a
1 bit, it's easier to use wait_for_bit_32() than readl_poll_timeout().

This change is needed for reliable initialization of the I2C driver
which is added in a following patch.

Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-02-28 18:42:27 +01:00
Tom Rini
abd4fb5ac1 Merge patch series "Dockerfile: Build coreboot from source"
To make our CI loops more robust, switch to building and providing the
coreboot binary we test with rather than download from a Google Drive
link.
2024-02-27 16:28:57 -05:00
Tom Rini
cb59ca304a CI: Move to latest container image
This moves us to our latest container image, which is now based on the
current "Jammy" tag.

Signed-off-by: Tom Rini <trini@konsulko.com>
2024-02-27 16:28:52 -05:00
Tom Rini
3a79c91f43 CI: Switch to using coreboot from our image
Instead of downloading coreboot binaries from a Google drive location,
use the ones we have built ourselves.

Signed-off-by: Tom Rini <trini@konsulko.com>
2024-02-27 16:28:52 -05:00
Tom Rini
f382050896 Dockerfile: Build coreboot from source
To make CI runs rely less on external servers, build a coreboot release
from source and populate /opt/coreboot with the output.

Signed-off-by: Tom Rini <trini@konsulko.com>
2024-02-27 16:28:52 -05:00
Tom Rini
d49fa3defa Prepare v2024.04-rc3
Signed-off-by: Tom Rini <trini@konsulko.com>
2024-02-26 21:23:36 -05:00
Tom Rini
1a66a7768a Merge tag 'u-boot-imx-master-20240224' of https://source.denx.de/u-boot/custodians/u-boot-imx
- Enable the thermal driver for the imx8m phycore boards.
- Convert imx53-qsb to watchdog driver to fix the 'reset' command.
- Remove multiline string from imx6dl-sielaff.
- Add SPI boot support for imxrt1050-evk.
- Convert opos6uldev to watchdog driver to fix the 'reset' command.
2024-02-24 17:51:50 -05:00
Sébastien Szymanski
7c76b1b91b opos6uldev: Convert to watchdog driver model
Commit 68dcbdd594 ("ARM: imx: Add weak default reset_cpu()") caused
the 'reset' command in U-Boot to not cause a board reset.

Fix it by switching to the watchdog driver model via sysreset, which
is the preferred method for implementing the watchdog reset.

Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2024-02-24 16:29:24 -03:00
Fabio Estevam
73454c85cd imx53-qsb: Convert to watchdog driver model
Commit 68dcbdd594 ("ARM: imx: Add weak default reset_cpu()") caused
the 'reset' command in U-Boot to not cause a board reset.

Fix it by switching to the watchdog driver model via sysreset, which
is the preferred method for implementing the watchdog reset.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
2024-02-24 16:29:00 -03:00
Benjamin Hahn
ed7824c226 imx8mm-phygate-tauri-l_defconfig: Enable CONFIG_IMX_TMU
Enable the imx thermal driver to prevent booting when the system is too
hot.

Signed-off-by: Benjamin Hahn <B.Hahn@phytec.de>
2024-02-24 16:27:15 -03:00
Benjamin Hahn
feb2d51ca8 phycore-imx8mm_defconfig: Enable CONFIG_IMX_TMU
Enable the imx thermal driver to prevent booting when the system is too
hot.

Signed-off-by: Benjamin Hahn <B.Hahn@phytec.de>
2024-02-24 16:27:15 -03:00
Benjamin Hahn
ab88ed62d5 phycore-imx8mp_defconfig: Enable CONFIG_IMX_TMU
Enable the imx thermal driver to prevent booting when the system is too
hot.

Signed-off-by: Benjamin Hahn <B.Hahn@phytec.de>
2024-02-24 16:27:15 -03:00
Mathieu Othacehe
7b6cec8dfb configs: imx93_var_som: Add fastboot support.
Enable the `fastboot` command.

Signed-off-by: Mathieu Othacehe <othacehe@gnu.org>
2024-02-24 16:22:01 -03:00
Mathieu Othacehe
fae9969224 configs: imx93_var_som: Add USB support.
Enable the `usb` command and some USB drivers.

Signed-off-by: Mathieu Othacehe <othacehe@gnu.org>
2024-02-24 16:22:01 -03:00
Mathieu Othacehe
3fd17d8368 arm: dts: imx93-var-som-symphony: Add USB support.
Enable both usbotg1 and usbotg2 ports.

Signed-off-by: Mathieu Othacehe <othacehe@gnu.org>
2024-02-24 16:22:01 -03:00
Mathieu Othacehe
4b6e4eefbf arm: dts: imx93: Add USB support.
Copied from:
https://lore.kernel.org/linux-devicetree/20240131114324.3722428-6-xu.yang_2@nxp.com/

Signed-off-by: Mathieu Othacehe <othacehe@gnu.org>
2024-02-24 16:22:00 -03:00
Frieder Schrempf
91cd41ecda board: imx6dl-sielaff: spl.c: Remove multiline string
Remove the malformed multiline string and fix the checkpatch warning.

Reported-by: Dan Carpenter <dan.carpenter@linaro.org>
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2024-02-24 16:21:34 -03:00
Jesse Taube
59c3f0ee54 imx: imxrt1050-evk: Add documentation for SPI boot
Add documentation for SPI boot.

Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
2024-02-24 16:21:02 -03:00
Jesse Taube
7079eeb72f imx: imxrt1050-evk: Add support for SPI flash booting
Add support for booting the imxrt1050-evk from spi.
Add imximage config and the ability for SPL to boot from NOR.
Enable binman in Kconfig and device tree for imxrt* as it is used to
prepend fspi_header.bin to SPL and u-boot.img.

Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
2024-02-24 16:21:02 -03:00
Tom Rini
bb9d6c7f4f Merge tag 'u-boot-amlogic-fixes-20240223' of https://source.denx.de/u-boot/custodians/u-boot-amlogic
- fix AVB oom error for Khadas VIM3 Android configs
2024-02-23 12:54:03 -05:00
Mattijs Korpershoek
fc0a7431e1 configs: khadas-vim3*_android: fix AVB oom error
When booting Android with AVB enabled, an OOM is observed:

  => avb init ${mmcdev}
  => avb verify _a
  ## Android Verified Boot 2.0 version 1.1.0
  read_is_device_unlocked not supported yet
  read_rollback_index not supported yet
  avb_util.c:182: ERROR: Failed to allocate memory.
  OOM error occurred during verification

A custom malloc length of 128MB is required as documented in
commit 285a83b12b ("configs: meson64_android: increase SYS_MALLOC_LEN to 128M for AVB")

However, this 128M custom malloc length was not ported to Kconfig in
commit 7cfbba36e9 ("Convert CONFIG_SYS_MALLOC_LEN to Kconfig")

Add it back to fix AVB verification on VIM3/VIM3L.

Fixes: 7cfbba36e9 ("Convert CONFIG_SYS_MALLOC_LEN to Kconfig")
Co-developed-by: Guillaume La Roque <glaroque@baylibre.com>
Signed-off-by: Guillaume La Roque <glaroque@baylibre.com>
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Igor Opaniuk <igor.opaniuk@gmail.com>
Link: https://lore.kernel.org/r/20240209-vim3-avb-malloc-v1-1-91427d8c19ab@baylibre.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2024-02-23 18:22:50 +01:00
Tom Rini
5e4a0c7f4a Merge branch 'qcom-fixes-2024.04' of https://gitlab.denx.de/u-boot/custodians/u-boot-snapdragon
- Two fixes for the qcom-pmic button driver
2024-02-22 11:34:59 -05:00
Tom Rini
7bb761c42d Merge patch series "board/ti: k3 boards: Stop using findfdt"
Nishanth Menon <nm@ti.com> says:

This is a wide cleanup to switch to setting fdtfile using env_set
instead of scripted magic. 'fdtfile' is expected to be set by default.
This allows the stdboot triggered efi loaders to find the correct OS
device tree file even if regular boot process is interrupted by user
intervention.
2024-02-20 17:57:52 -05:00
Nishanth Menon
452bab0ac7 include: env: ti: Drop default_findfdt
We shouldn't need finfdt anymore. Drop the env script.

Reviewed-by: Jonathan Humphreys <j-humphreys@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Signed-off-by: Nishanth Menon <nm@ti.com>
2024-02-20 17:57:41 -05:00
Nishanth Menon
d904c6820f board: beagle: beagleplay: Set fdtfile from C code instead of findfdt script
Stop using the findfdt script and switch to setting the fdtfile from C
code.

Reviewed-by: Jonathan Humphreys <j-humphreys@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Signed-off-by: Nishanth Menon <nm@ti.com>
2024-02-20 17:57:41 -05:00
Nishanth Menon
ce56536f2c board: beagle: beagleboneai64: Set fdtfile from C code instead of findfdt script
Stop using the findfdt script and switch to setting the fdtfile from C
code.

Reviewed-by: Jonathan Humphreys <j-humphreys@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Signed-off-by: Nishanth Menon <nm@ti.com>
2024-02-20 17:57:41 -05:00
Nishanth Menon
e41453c999 board: ti: j721s2: Set fdtfile from C code instead of findfdt script
We now can provide a map and have the standard fdtfile variable set from
code itself. This allows for bootstd to "just work".

While at this, replace findfdt in environment with a warning as it is no
longer needed.

Reviewed-by: Jonathan Humphreys <j-humphreys@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Signed-off-by: Nishanth Menon <nm@ti.com>
2024-02-20 17:57:41 -05:00
Nishanth Menon
c6d065817c board: ti: j721e: Set fdtfile from C code instead of findfdt script
We now can provide a map and have the standard fdtfile variable set from
code itself. This allows for bootstd to "just work".

While at this, replace findfdt in environment with a warning as it is no
longer needed.

Reviewed-by: Jonathan Humphreys <j-humphreys@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Signed-off-by: Nishanth Menon <nm@ti.com>
2024-02-20 17:57:40 -05:00
Nishanth Menon
6e20016924 board: ti: am65x: Set fdtfile from C code instead of findfdt script
We now can provide a map and have the standard fdtfile variable set from
code itself. This allows for bootstd to "just work".

While at this, replace findfdt in environment with a warning as it is no
longer needed.

Reviewed-by: Jonathan Humphreys <j-humphreys@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Signed-off-by: Nishanth Menon <nm@ti.com>
2024-02-20 17:57:40 -05:00
Nishanth Menon
f2c1205f88 board: ti: am64x: Set fdtfile from C code instead of findfdt script
We now can provide a map and have the standard fdtfile variable set from
code itself. This allows for bootstd to "just work".

While at this, replace findfdt in environment with a warning as it is no
longer needed.

Reviewed-by: Jonathan Humphreys <j-humphreys@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Signed-off-by: Nishanth Menon <nm@ti.com>
2024-02-20 17:57:40 -05:00
Nishanth Menon
0de0672e7e board: ti: am62x: Set fdtfile from C code instead of findfdt script
Stop using the findfdt script and switch to setting the fdtfile from
C code.

While at this, replace findfdt in environment with a warning as it is
no longer needed

Reviewed-by: Jonathan Humphreys <j-humphreys@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Signed-off-by: Nishanth Menon <nm@ti.com>
2024-02-20 17:57:40 -05:00
Nishanth Menon
39ae370cca board: ti: am62ax: Set fdtfile from C code instead of findfdt script
Stop using the findfdt script and switch to setting the fdtfile from
C code.

While at this, replace findfdt in environment with a warning as it is
no longer needed

Reviewed-by: Jonathan Humphreys <j-humphreys@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Signed-off-by: Nishanth Menon <nm@ti.com>
2024-02-20 17:57:40 -05:00
Nishanth Menon
fa94f8eec3 board: ti: common: Introduce a common fdt ops library
Introduce a common fdt operations library for basic device tree
operations that are common between various boards.

The first library to introduce here is the capability to set up
fdtfile as a standard variable as part of board identification rather
than depend on scripted ifdeffery.

Reviewed-by: Jonathan Humphreys <j-humphreys@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Signed-off-by: Nishanth Menon <nm@ti.com>
2024-02-20 17:57:40 -05:00
Nishanth Menon
66ebb10b0f board: ti: Add missing common/Kconfig references
Add missing board/ti/common/Kconfig references for the platforms that
missed it. The intent is for the common Kconfig to be usable across TI
reference boards as required.

Reported-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2024-02-20 17:57:40 -05:00
Tom Rini
1817afe30f Merge https://gitlab.denx.de/u-boot/custodians/u-boot-usb 2024-02-20 08:03:21 -05:00
Tom Rini
bebf916f9e Merge https://gitlab.denx.de/u-boot/custodians/u-boot-samsung 2024-02-20 08:02:49 -05:00
Mathieu Othacehe
d9a20fea2b usb: ehci-mx6: Add i.MX93 support
i.MX93 uses the same USB IP as i.MX8MM. It can then reuse the ehci-mx6
driver.

Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Mathieu Othacehe <othacehe@gnu.org>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2024-02-19 20:08:51 +01:00
Shantur Rathore
08e2cd6cd3 common: usb-hub: Reset USB 3.0 hubs only
Additional testing of the changes introduced in commit 33e06dcbe5 "common:
usb-hub: Reset hub port before scanning") revealed that some USB 2.0 and 3.0
flash drives didn't work in U-Boot on some Allwinner SoCs that support USB
2.0 interfaces only.  More precisely, some of the tested USB 2.0 and 3.0
flash drives failed to be detected and work on an OrangePi Zero 3, based on
the Allwinner H616 SoC that supports USB 2.0 only, while the same USB flash
drives worked just fine on a Pine64 H64, based on the Allwinner H6 SoC that
supports both USB 2.0 and USB 3.0 interfaces.

The USB ID of the above-mentioned USB 3.0 flash drive that failed to work is
1f75:0917 (Innostor Technology Corporation IS917 Mass storage), it is 32 GB
in size and sold under the PNY brand.  The mentioned USB 2.0 drive is some
inexpensive no-name drive with an invalid USB ID.

Resetting USB 3.0 hubs only, which this patch introduces to the USB hub
resets, has been tested to work as expected, resolving the identified issues
on the Allwinner H616, while not introducing any new issues on other tested
Allwinner SoCs.  Thus, let's fix it that way.

According to the USB 3.0 specification, resetting a USB 3.0 port is required
when an attached USB device transitions between different states, such as
when it resumes from suspend.  Though, the Linux kernel performs additional
USB 3.0 port resets upon initial USB device attachment, as visible in commit
07194ab7be63 ("USB: Reset USB 3.0 devices on (re)discovery") in the kernel
source, to ensure proper state of the USB 3.0 hub port and proper USB mode
negotiation during the initial USB device attachment and enumeration.

These additional types of USB port resets don't exist for USB 2.0 hubs,
according the USB 2.0 specification.  The resets seem to be added to the USB
3.0 specification as part of the port and device mode negotiation.

The Linux kernel resets USB 3.0 (i.e. SuperSpeed) hubs only, as visible in
commit 10d674a82e55 ("USB: When hot reset for USB3 fails, try warm reset.")
in the kernel source.  The check for SuperSpeed hubs is performed in a way
that also applies to newer SuperSpeed Plus (USB 3.1 or 3.2) hubs as well,
which hopefully makes it future proof.

Fixes: 33e06dcbe5 ("common: usb-hub: Reset hub port before scanning")

Link:
https://lore.kernel.org/u-boot/20240207102327.35125-1-i@shantur.com/T/#u
Link:
https://lore.kernel.org/u-boot/20240201164604.13315fa6@donnerap.manchester.arm.com/T/#u

Signed-off-by: Shantur Rathore <i@shantur.com>
Helped-by: Dragan Simic <dsimic@manjaro.org>
Tested-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Dragan Simic <dsimic@manjaro.org>
Reviewed-by: Marek Vasut <marex@denx.de>
2024-02-19 20:08:41 +01:00
Tom Rini
3e6f2a94bf Merge tag 'u-boot-imx-master-20240219' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/19683

- Convert msc_sm2s_imx8mp to DM_SERIAL.
- Make Ethernel functional on msc_sm2s_imx8mp.
- General improvements for msc_sm2s_imx8mp.
- Add suport for the Sielaff i.MX6 Solo board.
- Update GE HealthCare maitainers' e-mail addresses.
2024-02-19 08:55:17 -05:00
Frieder Schrempf
0cfc2e9225 doc: board: Add minimal documentation for Sielaff i.MX6 Solo board
Describe how to build and boot for the Sielaff i.MX6 Solo board.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2024-02-19 08:19:39 -03:00
Frieder Schrempf
588399c2d5 board: Add support for Sielaff i.MX6 Solo board
The Sielaff i.MX6 Solo board is a control and HMI board for vending
machines. Add support for this board.

The devicetree files are taken from pending changes in the Linux
kernel that are available from linux-next and will likely be
part of Linux v6.9.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2024-02-19 08:19:39 -03:00
Frieder Schrempf
d4091971ab mtd: spi-nor-ids: Add support for ESMT/EON EN25Q80B
The datasheet can be found here:
https://www.esmt.com.tw/upload/pdf/ESMT/datasheets/EN25Q80B_Ver.E.pdf

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2024-02-19 08:19:39 -03:00
Ian Ray
cf51339d5b MAINTAINERS: Update after GEHC spin-off
Update our email addresses, from @ge.com to @gehealthcare.com, after GE
HealthCare was spun-off from GE.

Remove Antti, who no longer works on the project.

Signed-off-by: Ian Ray <ian.ray@gehealthcare.com>
2024-02-19 08:19:39 -03:00
Fabio Estevam
7489f192d8 msc_sm2s_imx8mp: Fix CONFIG_DEFAULT_FDT_FILE
There is no imx8mp-msc-sm2s.dtb file in upstream Linux.

Change it to imx8mp-msc-sm2s-ep1.dtb.

Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Ian Ray <ian.ray@gehealthcare.com>
2024-02-19 08:19:39 -03:00
Fabio Estevam
6dfdfad3c3 msc_sm2s_imx8mp: Add redundant environment support
Redundant environment support is required for software updates.

Add support for it.

Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Ian Ray <ian.ray@gehealthcare.com>
2024-02-19 08:19:39 -03:00
Fabio Estevam
399c4a9e1c imx8mp-msc-sm2s: Add mmc aliases
Add mmc alias so that the eMMC is mmc0 and the SD card
is mmc1 to have a well defined device numbering scheme.

Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Ian Ray <ian.ray@gehealthcare.com>
2024-02-19 08:19:39 -03:00
Fabio Estevam
b8d4b1c582 msc_sm2s_imx8mp: Make Ethernet functional
Currently, the Ethernet ports are not working.

The Ethernet PHY reset lines are controlled by the TCA6424 I2C GPIO
expander.

The TCA6424 I2C GPIO expander is supported by the CONFIG_DM_PCA953X
driver.

Select the CONFIG_DM_PCA953X option so that the Ethernet PHYs can
go through a proper reset making Ethernet to be functional.

Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Ian Ray <ian.ray@gehealthcare.com>
2024-02-19 08:19:39 -03:00
Fabio Estevam
a59fb3dcf0 msc_sm2s_imx8mp: Convert to DM_SERIAL
The conversion to DM_SERIAL is mandatory, so do the conversion.

Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Ian Ray <ian.ray@gehealthcare.com>
2024-02-19 08:19:39 -03:00
Tom Rini
e4013bcb10 Merge branch 'master-porter' of https://source.denx.de/u-boot/custodians/u-boot-sh
- Renesas R-Car Gen2 fixes
2024-02-17 18:37:07 -05:00
Marek Vasut
87f9ffbef5 ARM: renesas: Enable LTO on R-Car
Enable LTO globally on Renesas R-Car platforms. This has been enabled
on a subset of boards already, but at this point it is safe to enable
it globally. This saves units or tens of kiB from the resulting build.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
2024-02-17 22:38:20 +01:00
Marek Vasut
1c987e6fb4 ARM: renesas: Set R-Car Gen2 board size limit to 512 kiB
The maximum size of u-boot.img on R-Car Gen2 is 0x80000 or 512 kiB,
set the limit to avoid overflows as new functionality gets pulled in.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
2024-02-17 22:38:20 +01:00
Marek Vasut
e4c2f0f786 ARM: renesas: Disable EFI on R-Car Gen2
These systems are unlikely to use EFI as this functionality has not been
enabled until it got pulled in by Kconfig default. This functionality
does add some 60-70 kiB to the u-boot.img size, which overflows the size
limit. Disable it.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
2024-02-17 22:38:20 +01:00
Niklas Söderlund
49ad0c8eee clk: renesas: Fix broken clocks on all Gen2 boards
To prepare support for multiple register layouts pointers to register
tables where added to struct cpg_mssr_info. These pointers are suppose
to be filled in at probe time and no intended change in behavior was
intended.

However the new pointers where only filled in by some paths of the
driver implemented in clk-rcar-gen3.c. The path implemented in
clk-rcar-gen2.c was not updated leaving the pointers uninitialized
leading to a crash when trying to probe the clocks.

Fix this by filling in the pointers in the Gen2 code path with the
values used before they where moved to struct cpg_mssr_info.

Fixes: d413214fb7 ("clk: renesas: Add register pointers into struct cpg_mssr_info")
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Acked-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Tested-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # R8A7791 Porter
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-02-17 22:38:18 +01:00
Tom Rini
9e00b6993f Merge tag 'u-boot-dfu-20240215' of https://source.denx.de/u-boot/custodians/u-boot-dfu
u-boot-dfu-20240215

- Fix avb_verify command with SD cards
- Add u-boot-dfu maintainer tree for AB/AVB
- Avb: report verified boot state based on lock state
- Misc avb refactors improve code quality
2024-02-15 10:26:24 -05:00
Igor Opaniuk
e2f6270f2d doc: android: avb: sync usage details
Sync usage info with the one cmd/avb.c.

Signed-off-by: Igor Opaniuk <igor.opaniuk@gmail.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Link: https://lore.kernel.org/r/20240209192045.3961832-8-igor.opaniuk@foundries.io
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
2024-02-15 10:38:34 +01:00
Igor Opaniuk
df3cfceeb1 cmd: avb: rework do_avb_verify_part
Use existing str_avb_slot_error() function for obtaining
verification fail reason details.
Take into account device lock state for setting correct
androidboot.verifiedbootstate kernel cmdline parameter.

Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Signed-off-by: Igor Opaniuk <igor.opaniuk@gmail.com>
Link: https://lore.kernel.org/r/20240209192045.3961832-7-igor.opaniuk@foundries.io
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
2024-02-15 10:38:34 +01:00
Igor Opaniuk
fc7ef0f9e7 common: avb_verify: add str_avb_io_error/str_avb_slot_error
Introduce str_avb_io_error() and str_avb_slot_error() functions,
that provide a pointer to AVB runtime error message.

Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Signed-off-by: Igor Opaniuk <igor.opaniuk@gmail.com>
Link: https://lore.kernel.org/r/20240209192045.3961832-6-igor.opaniuk@foundries.io
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
2024-02-15 10:38:34 +01:00
Igor Opaniuk
0ef0825a8c cmd: avb: rework prints
Simplify and add more context for prints where it's needed.

Signed-off-by: Igor Opaniuk <igor.opaniuk@gmail.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Link: https://lore.kernel.org/r/20240209192045.3961832-5-igor.opaniuk@foundries.io
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
2024-02-15 10:38:34 +01:00
Igor Opaniuk
0508a7c667 common: avb_verify: rework error/debug prints
Make error prints more verbose with additional context.
Also s/print/debug/g for prints, which might be relevant only
for debugging purposes.

Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Signed-off-by: Igor Opaniuk <igor.opaniuk@gmail.com>
Link: https://lore.kernel.org/r/20240209192045.3961832-4-igor.opaniuk@foundries.io
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
2024-02-15 10:38:34 +01:00
Igor Opaniuk
a14aa59e7e avb: move SPDX license identifiers to the first line
Move SPDX license identifiers to the first line, so it conforms
to license placement rule [1]:

Placement:
The SPDX license identifier in kernel files shall be added at the first
possible line in a file which can contain a comment.  For the majority
of files this is the first line, except for scripts which require the
'#!PATH_TO_INTERPRETER' in the first line.  For those scripts the SPDX
identifier goes into the second line.

[1] https://www.kernel.org/doc/Documentation/process/license-rules.rst

Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Signed-off-by: Igor Opaniuk <igor.opaniuk@gmail.com>
Link: https://lore.kernel.org/r/20240209192045.3961832-3-igor.opaniuk@foundries.io
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
2024-02-15 10:38:34 +01:00
Igor Opaniuk
c2f72d00ab common: avb_verify: don't call mmc_switch_part for SD
mmc_switch_part() is used for switching between hw partitions
on eMMC (boot0, boot1, user, rpmb).
There is no need to do that for SD card.

This fixes the avb command usage on SD cards.

Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Signed-off-by: Igor Opaniuk <igor.opaniuk@gmail.com>
Reviewed-by: Dragan Simic <dsimic@manjaro.org>
Link: https://lore.kernel.org/r/20240209192045.3961832-2-igor.opaniuk@foundries.io
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
2024-02-15 10:38:34 +01:00
Igor Opaniuk
cfbeb4b0b9 MAINTAINERS: add custodian tree info for AVB/AB
Add information about a custodian tree [1] for AVB/AB, which is
maintained by Mattijs Korpershoek.

[1] https://source.denx.de/u-boot/custodians/u-boot-dfu

Signed-off-by: Igor Opaniuk <igor.opaniuk@gmail.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Link: https://lore.kernel.org/r/20240213073638.1125429-1-igor.opaniuk@foundries.io
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
2024-02-15 10:38:34 +01:00
Tom Rini
77ff61a5bb Merge tag 'xilinx-for-v2024.04-rc3' of https://source.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2024.04-rc3

zynqmp:
- Cover missing _SE chip variants to fix fpga programming

versal:
- Enable LTO for mini configurations

versal-net:
- Enable LTO for mini configurations
- Fix GIC address to aligned with real silicon

xilinx:
- DTs cleanup and fixups
- Enable HTTP boot
- Add missing spl header to zynqmp.c
2024-02-14 15:23:10 -05:00
Caleb Connolly
22f391e8be button: qcom-pmic: demote "unknown button" message to debug
This message isn't an error (there can be a watchdog subnode for example)
but it shouldn't be printed unless this driver is being debugged. Demote
it to a debug print.

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-02-14 17:21:50 +00:00
Dan Carpenter
6b929e9f3c button: qcom-pmic: fix some error checking
The pmic_reg_read() function can return errors.  Add a check for that.

Fixes: 4e8aa0065d ("button: qcom-pmic: introduce Qualcomm PMIC button driver")
Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
2024-02-14 17:16:52 +00:00
Michal Simek
c2ad5fb616 arm64: versal-net: Setup correct addresses of GICR/GICD
Previous addresses where used in past in emulation environment but never
gets to silicon that's why use correct addresses.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/5d3d0e1afb1f673ffeb4a1c5d7f040475c806a30.1707220293.git.michal.simek@amd.com
2024-02-14 11:23:43 +01:00
Tom Rini
37345abb97 Prepare v2024.04-rc2
Signed-off-by: Tom Rini <trini@konsulko.com>
2024-02-13 18:16:57 -05:00
Tom Rini
0b66c54a97 Merge branch '2024-02-13-assorted-updates'
- Add the button command patch, update MAINTAINERS entry for a platform,
  fix a problem with the hash command, fix a problem on K3 platforms and
  revert a change on verdin-am62.
2024-02-13 17:32:17 -05:00
Francesco Dolcini
ea7d3eec1e Revert "board: verdin-am62: set cpu core voltage depending on speed grade"
This reverts commit d2099587d6.

According to TI changing the VDD_CORE while the SoC is running is not
allowed, the voltage must be set before the AM62 device reset is
released, revert this change therefore.

The correct solution would be to program the PMIC during manufactoring
according to the speed grade of the SoC.

Link: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1318338/am623-booting-from-mmc-failed-after-lowering-vdd_core-to-0-75v/5036508#5036508
Fixes: d2099587d6 ("board: verdin-am62: set cpu core voltage depending on speed grade")
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
2024-02-13 15:38:49 -05:00
Caleb Connolly
e761035b64 boot: add support for button commands
With the relatively new button API in U-Boot, it's now much easier to
model the common usecase of mapping arbitrary actions to different
buttons during boot - for example entering fastboot mode, setting some
additional kernel cmdline arguments, or booting with a custom recovery
ramdisk, to name a few.

Historically, this functionality has been implemented in board code,
making it fixed for a given U-Boot binary and requiring the code be
duplicated and modified for every board.

Implement a generic abstraction to run an arbitrary command during boot
when a specific button is pressed. The button -> command mapping is
configured via environment variables with the following format:

  button_cmd_N_name=<button label>
  button_cmd_N=<command to run>

Where N is the mapping number starting from 0. For example:

  button_cmd_0_name=vol_down
  button_cmd_0=fastboot usb 0

This will cause the device to enter fastboot mode if volume down is held
during boot.

After we enter the cli loop the button commands are no longer valid,
this allows the buttons to additionally be used for navigating a boot
menu.

Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # Tegra30
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-02-13 15:38:49 -05:00
Igor Opaniuk
348ea87850 cmd: hash: fix param count check
Add correct check for parameter count.

This fixes this issue when `hash` cmd is invoked without params:

=> hash
data abort
pc : [<bf739204>]	   lr : [<ba6effa8>]
reloc pc : [<60019204>]	   lr : [<5afcffa8>]
sp : ba6dd9c8  ip : bf7391f0	 fp : bf74ec14
r10: 00000001  r9 : ba6dfea0	 r8 : bf7ea030
r7 : 00000000  r6 : ba6effa8	 r5 : 00000000  r4 : ffffffff
r3 : bf7c257c  r2 : 00000001	 r1 : 00000000  r0 : bf7e6e34
Flags: nZCv  IRQs off  FIQs on  Mode SVC_32
Code: e5934004 e1a0e003 e59f3050 e2444001 (e5f4c001)
Resetting CPU ...

resetting ...

Signed-off-by: Igor Opaniuk <igor.opaniuk@gmail.com>
2024-02-13 15:38:11 -05:00
Roger Quadros
ef473d541d memory: ti-gpmc: Fix lock up at A53 SPL during NAND boot on AM64-EVM
AM64 ES2.0 bootrom seems to enable WAIT0EDGEDETECTION interrupt.
This causes a lockup at A53 SPL when accessing NAND controller
or ELM registers.

A good option would be to softrest GPMC block at probe
but this cannot be done for AM64 as SOFTRESET bit is marked
as reserved in SYSCONFIG register.

Fix the issue by disabling all IRQs at probe.

Signed-off-by: Roger Quadros <rogerq@kernel.org>
2024-02-13 15:38:11 -05:00
Igor Opaniuk
b12883fc38 poplar: add myself as co-maintainer
Add myself as co-maintainer for Poplar board, as I'm currently
working on it (re-testing releases, addressing issues etc).

CC: Jorge Ramirez-Ortiz <jorge.ramirez.ortiz@gmail.com>
CC: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Jorge Ramirez-Ortiz <jorge.ramirez.ortiz@gmail.com>
2024-02-13 15:38:11 -05:00
Tom Rini
73b5b47dd5 Merge tag 'doc-2024-04-rc2' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request doc-2024-04-rc2

Documentation:

* Fix and extend utf8_to_utf32_stream() documentation
* Fix rendering of OpenSBI logo in VisionFive 2 description
* Document imxrt1170-evk board
* codingstyle.rst: Clarify include section

UEFI:

* simplify error message in efi_disk_create_raw()
2024-02-12 15:22:05 -05:00
Nils Le Roux
a5f877a0bd net: designware: Support high memory nodes
Some platforms (such as the Lichee Pi 4A) have their dwmac device
addressable only in high memory space. Storing the node's base address
on 32 bits is not possible in such case.

Use platform's physical address type to store the base address.

Signed-off-by: Nils Le Roux <gilbsgilbert@gmail.com>
Cc: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2024-02-12 13:41:03 -05:00
Tom Rini
2eb39c9ada doc/develop/codingstyle.rst: Clarify include section
Rework the section about includes slightly. We should not be using
common.h anywhere, so remove that from examples and ask people to send
patches removing it when found. Doing this also means we need to reword
other parts of this section. Be clearer about using alphabetical
ordering.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@gmail.com>
2024-02-12 17:35:34 +01:00
Janne Grunau
1a72acba38 lib: charset: Fix and extend utf8_to_utf32_stream() documentation
Clarify usage of buffer argument.

Signed-off-by: Janne Grunau <j@jannau.net>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-02-12 17:35:34 +01:00
Heinrich Schuchardt
50457f547d efi_loader: simplify error message in efi_disk_create_raw()
The error message

    Adding disk for usb_mass_storage.lun0 failed (err=-9223372036854775788/0x8000000000000014)

provides a decimal and a hexadecimal notation of the EFI status code
EFI_ALREADY_STARTED which is defined as (EFI_ERROR_MASK | 20).
The decimal output does not convey the value 20 clearly.

With the patch we write

    Adding block device usb_mass_storage.lun0 failed, r = 20

similar to other EFI error messages.

Fixes: 952018117a ("dm: sandbox: Switch over to using the new host uclass")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-02-12 17:35:34 +01:00
Heinrich Schuchardt
5bf0802631 doc: board: starfive: fix rendering of OpenSBI logo
The rendering of the OpenSBI logo should look like the screen output.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-02-12 17:35:34 +01:00
Jesse Taube
71b7bd86ed doc: imx: imxrt1170: Document imxrt1170-evk board
Add documentation for imxrt1170-evk.

Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Reviewed-by: Giulio Benetti <giulio.benetti@benettiengineering.com>

Add index page entry, adjust formatting.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-02-12 17:35:34 +01:00
Tom Rini
91c37c4a20 Merge tag 'u-boot-imx-master-20240212' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
CI:
https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/19583

- Fix the i.MX8MP SPI compatible string.
- Let the SPL clock code do the configuration on Data Modul i.MX8M Plus
  eDM SBC.
- Enable secure boot on the imx93_var_som board.
2024-02-12 09:26:20 -05:00
Venkatesh Yadav Abbarapu
db23e67bbd xilinx: zynqmp: Add the missing function prototype
Add missing prototype to fix the below sparse warning
warning: no previous prototype for 'spl_spi_get_uboot_offs'
	 [-Wmissing-prototypes]

Fixes: 2c8a09219c ("arm64: zynqmp: Add multiboot support for SPL/SPI offset calculation")
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20240207083328.1673752-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2024-02-12 09:28:32 +01:00
Michal Simek
a0a24194bc arm64: zynqmp: Disable DP on kd240
When SOM dt is combined with kd240 overlay DPSUB is enabled but kd240 has
no DP wired that's why change disable it via status property.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/f6de217b3350c9d59032ef54800882e48f240398.1706791116.git.michal.simek@amd.com
2024-02-12 09:28:32 +01:00
Michal Simek
04dca75ae3 arm64: zynqmp: Do not expose usbhub nodes on kr260 usb1
usb0 is already updated but forget to also update usb1.

Fixes: 4ff083f09b ("arm64: zynqmp: Do not expose usbhub nodes")
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/862ca748670f18f25d88aa5b43c37e3dd6aa35eb.1706791116.git.michal.simek@amd.com
2024-02-12 09:28:32 +01:00
Michal Simek
f1c24bdf7b arm64: zynqmp: Align nvmem-fw node with dt-schema
Node name has to be renamed to be aligned with dt-schema and also
xlnx,zynqmp-nvmem-fw switched to fixed-layout.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/32899b20c1e282aab16c32074b1c9a3f45f6dac8.1706791116.git.michal.simek@amd.com
2024-02-12 09:28:32 +01:00
Michal Simek
e0cce11434 arm64: zynqmp: Remove arm,cortex-a53-edac node
There is no dt schema associated with it. Also Linux driver have been
removed in Xilinx Linux tree and never gets to upstream that's why remove
description for it.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/6685ee980d9b475f95eef6b2a74795adc4ac4619.1706791116.git.michal.simek@amd.com
2024-02-12 09:28:32 +01:00
Michal Simek
fb16d9321f xilinx: Fix fpga region DT nodes name
fpga-full is not aligned with the latest dt-schema. Generic name
fpga-region should be used.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/78e6e3f287f79917eb92c6c74accbaf955526aad.1706791116.git.michal.simek@amd.com
2024-02-12 09:28:32 +01:00
Michal Simek
f8e125c995 arm64: zynqmp: Fix kr260 clock wiring
kr260 revA/revA01 is using discrete oscilator for DP (27MHz) and si5332 for
other clocks but clocks are different compare to kv260 that's why fix it to
aligned with the latest schematics.

On the other handle kr260 revB/revA03 also contains 74.25 MHz discrete
clock chip for SLVC-EC output which is not defined.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/e87ae94979c6efc909740bb1a569505042e4f876.1706626255.git.michal.simek@amd.com
2024-02-12 09:28:32 +01:00
Michal Simek
8e9566c981 arm64: zynqmp: Describe 25MHz fixed clock for PL GEMs
Describe 25Mhz fixed oscilator which is providing clock for PL based
ethernet IPs. Physicially it is one chip but it is described as 2 fixed
clock to be aligned with other SOM versions which were using integrated
clock generators where clocks could be adjusted via i2c (si5332 chips).

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/c430aeacaa76d9f61ed3f874f721a33049f45eb9.1706514396.git.michal.simek@amd.com
2024-02-12 09:28:32 +01:00
Michal Simek
0845f5c803 arm64: zynqmp: Sync clock labels with kr260 revB
Board description describes the hard part of chip (PS) but programmable
logic (PL) part is not described in this file. But clocks on the board are
not only connected to PS but also wired to PL. And because two revisions
are available where revA is using one si5332 and revB multiple clock chips
using the same clock labels helping with keeping only one device tree
overlay which targets PL. That's why synchronize clock labels and use
labels from revB which are more generic.
Unfortunately if there is driver for si5332 chip split could happen again
but it is still worth to do it now and solve this issue when occurs.

Reported-by: Sagar Karmarkar <sagar.karmarkar@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/abac6069e6029ed4076ec7b9d6b33604b6072aa3.1706253871.git.michal.simek@amd.com
2024-02-12 09:28:32 +01:00
Saeed Nowshadi
cbd87dae91 arm64: zynqmp: Add 'silabs, skip-recall' to all si570 clk nodes
Without 'silabs,skip-recall' property, the driver on System Controller
re-calibrates the output clock frequency at probe() time based on the NVRAM
setting.  This re-calibration causes a glitch on the output clock.  At
power-on, Versal is also booting and expecting a glitch-free clock for
its correct operation.  System Controller should skip the re-calibration
step to prevent any clock instability for Versal.

Signed-off-by: Saeed Nowshadi <saeed.nowshadi@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/bbb2322c94503f0e6b369c60312b7546500fad95.1706170068.git.michal.simek@amd.com
2024-02-12 09:28:32 +01:00
Michal Simek
98f7bf5da4 arm64: xilinx: Enable EFI_HTTP_BOOT by default
Enable EFI_HTTP_BOOT to be able to booting OS via http.
In case of that dhcp server is not providing dns server IP set it up via
setenv dnsip <ip addr>.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/b78a7d8b0100c724f657c0997b273e073cf31a14.1706093917.git.michal.simek@amd.com
2024-02-12 09:28:31 +01:00
Venkatesh Yadav Abbarapu
8a58aed145 configs: versal_net: Enable CONFIG_LTO for mini qspi/ospi
Adding a tiny bit more code for mini u-boot leads to a OCM
image overflow. Fix this by enabling LTO for this board, so that such
changes still can be made to the common U-Boot code.

Enable building mini u-boot image with LTO, which results in about 8KB
reduction in size.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20240126081139.3210211-1-venkatesh.abbarapu@amd.com
2024-02-12 09:28:31 +01:00
Venkatesh Yadav Abbarapu
958526f250 configs: versal: Enable CONFIG_LTO for mini qspi/ospi
Adding a tiny bit more code for mini u-boot leads to a OCM
image overflow. Fix this by enabling LTO for this board, so that such
changes still can be made to the common U-Boot code.

Enable building mini u-boot image with LTO, which results in about 8KB
reduction in size.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20240126080900.3209323-1-venkatesh.abbarapu@amd.com
2024-02-12 09:28:31 +01:00
Venkatesh Yadav Abbarapu
dfc8e5f659 soc: zynqmp: Add the IDcode for dr_SE and eg_SE variants
ID code is added for zu67dr_SE, zu11eg_SE, zu19eg_SE and zu47dr_SE
variants. SE is the select edition of restricted devices with the
capabilities.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20240123045715.893652-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2024-02-12 09:28:31 +01:00
Tom Rini
e8f2404e09 Merge branch 'master-779h0-r2' of https://source.denx.de/u-boot/custodians/u-boot-sh 2024-02-11 12:42:25 -05:00
Mathieu Othacehe
fcd377ed64 configs: imx93_var_som: Enable AHAB support
Enable AHAB support in the imx93_var_som configuration.

Signed-off-by: Mathieu Othacehe <othacehe@gnu.org>
2024-02-10 15:16:13 -03:00
Mathieu Othacehe
db783ee982 board: imx93_var_som: Probe ELE MU
Probing the MU is needed to prevent this error in the SPL:

ele dev is not initialized
Authenticate container hdr failed, return -19, resp 0x0
IND = INVALID

ele dev is not initialized
Error: release container failed, resp 0x0!
IND = INVALID

SPL: failed to boot from all boot devices

Signed-off-by: Mathieu Othacehe <othacehe@gnu.org>
2024-02-10 15:16:13 -03:00
Mathieu Othacehe
2029a4c6be imx93: Use a header for imx9_probe_mu declaration
Put imx9_probe_mu declaration in a new mu.h header file.

Signed-off-by: Mathieu Othacehe <othacehe@gnu.org>
Reviewed-by: Igor Opaniuk <igor.opaniuk@foundries.io>
2024-02-10 15:16:13 -03:00
Marek Vasut
05d3602737 spi: mxc_spi: Add imx6ul-ecspi compatible string
Recent i.MX8MP DTs use new fsl,imx6ul-ecspi compatible string instead
of the fsl,imx51-ecspi compatible string. Add the new compatible string
to fix ECSPI operation on i.MX8MP.

For details, see Linux:
48d74376fb68 ("arm64: dts: imx8mp: update ecspi compatible and clk")
8eb1252bbedf ("spi: imx: remove ERR009165 workaround on i.mx6ul")

Fixes: 451799a6ce ("arm: dts: imx8mp: Sync the DT with kernel 6.4-rc4")
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Marek Vasut <marex@denx.de>
2024-02-10 15:15:55 -03:00
Marek Vasut
0fa60e3c2a ARM: imx: Let SPL configure ECSPI1 clock on Data Modul i.MX8M Plus eDM SBC
The SPL clock code does configure the ECSPI clock frequency, which has
to match the mxc-spi driver configuration for successful SPI NOR boot.
Drop the assigned-clock from DT ecspi1 node on this board to let the
SPL clock code do the configuration and keep it aligned with the driver
expectation.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2024-02-10 15:15:40 -03:00
Hai Pham
53066deccb ARM: renesas: Add Renesas R8A779H0 V4M Gray Hawk board code
Add board code for the Renesas R8A779H0 V4M Gray Hawk board.

Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
2024-02-10 17:08:06 +01:00
Hai Pham
9e9a92e4a3 ARM: dts: renesas: Add Renesas Gray Hawk boards support
Initial support for the Renesas Gray Hawk CPU and BreakOut boards.

The arch/arm/dts/r8a779h0-gray-hawk-cpu.dtsi is extended version of:
https://lore.kernel.org/linux-renesas-soc/b657402113267acd57aece0b4c681b707e704455.1706194617.git.geert+renesas@glider.be/
The version currenty submitted upstream lacks functionality which is
present in this series. Once the upstream support implements that
missing functionality, these DTs will be updated to match.

Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
2024-02-10 17:08:06 +01:00
Hai Pham
903f98e88c ARM: dts: renesas: Add Renesas R8A779H0 V4M DT extras
Add Renesas R8A779H0 V4M DT extras for U-Boot.

Until the RPC node becomes part of main DT, keep it here as
an extension so that board code can enable and use the RPC
to access SPI NOR.

Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
2024-02-10 17:08:06 +01:00
Hai Pham
1acb69d9b3 ARM: dts: renesas: Add Renesas R8A779H0 V4M SoC support
Add initial support for the Renesas R8A779H0 (R-Car V4M) SoC.

The current version is imported and modified from:
https://lore.kernel.org/linux-renesas-soc/4107bc3d7c31932da29e671ddf4b1564ba38a84c.1706194617.git.geert+renesas@glider.be/
The modifications contain nodes from previous version
which are useful in U-Boot and not part of the Linux
kernel DT yet. The following nodes were added:
- pfc
- gpio0..gpio7
- i2c0..i2c3
- avb0..avb2
- mmc0

Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
2024-02-10 17:08:06 +01:00
Hai Pham
c49f936455 mtd: spi: renesas: Add R8A779H0 V4M support
Support RPC SPI on R8A779H0 V4M SoC.

Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2024-02-10 17:08:06 +01:00
Hai Pham
e02ec8cf49 ARM: renesas: Add R8A779H0 V4M Kconfig entry and PRR ID
Add Kconfig entry and PRR ID to support R8A779H0 V4M SoC.

Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
2024-02-10 17:08:06 +01:00
Hai Pham
995a857a01 pinctrl: renesas: Add R8A779H0 V4M PFC tables
Add pinctrl tables for R8A779H0 V4M SoC.

The current version of these PFC tables is imported and squashed from:
https://lore.kernel.org/linux-renesas-soc/cover.1706264667.git.geert+renesas@glider.be/

Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
2024-02-10 17:08:06 +01:00
Marek Vasut
0fb76cc0bc clk: renesas: Implement R8A779H0 V4M PLL7 support
Add PLL7 support to Gen3/Gen4 common clock driver. Add initial PLL7
multiplier and divider values into table in R8A779H0 V4M clock driver.

The PLL7 is new PLL added in R8A779H0 V4M SoC. Only integer multiplication
mode is supported by PLL7. The PLL reference clock are either 16.66 MHz or
20 MHz on R8A779H0 V4M SoC, and the output frequency must be 2000 MHz. The
multiplier values fitting this requirement are calculated to 120 or 100.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-02-10 17:08:06 +01:00
Hai Pham
13a014c38c clk: renesas: Add R8A779H0 V4M clock tables
Add clock tables for R8A779H0 V4M SoC.

The current version is imported from:
https://lore.kernel.org/linux-renesas-soc/c678ef7164e3777fa91572f72e47ef385cea64b8.1706194617.git.geert+renesas@glider.be/
The current version still contains PLL7 extras from the
previous version to provide ethernet support in U-Boot.

Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
2024-02-10 17:08:06 +01:00
Duy Nguyen
42a064d1d7 dt-bindings: power: Add R8A779H0 V4M SYSC power domain definitions
Add power domain indices for R-Car V4M (R8A779H0).

The current version is imported from:
https://lore.kernel.org/linux-renesas-soc/c5cbef71178cada761e9da7bcbb6f21334f93ef8.1706194617.git.geert+renesas@glider.be/

Signed-off-by: Duy Nguyen <duy.nguyen.rh@renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
2024-02-10 17:08:06 +01:00
Duy Nguyen
ad005d8a77 dt-bindings: clock: Add R8A779H0 V4M CPG Core Clock Definitions
Add all Clock Pulse Generator Core Clock Outputs for the Renesas R-Car
V4M (R8A779H0) SoC.

The current version is imported from:
https://lore.kernel.org/linux-renesas-soc/11acbd2a30b58607474e9c32eb798b3a00e85e73.1706194617.git.geert+renesas@glider.be/

Signed-off-by: Duy Nguyen <duy.nguyen.rh@renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
2024-02-10 17:08:06 +01:00
Tom Rini
d7aaaf4223 Merge tag 'u-boot-dfu-20240209' of https://source.denx.de/u-boot/custodians/u-boot-dfu
u-boot-dfu-20240209

- sparse error checking fix when using raw chunks
- 2 new additions (AVB, AB) of myself to the MAINTAINERS file
2024-02-09 09:00:42 -05:00
Sean Anderson
766f04a297 lib: sparse: Fix error checking for write_sparse_chunk_raw
The return value of write_sparse_chunk_raw is unsigned, so the existing
check has no effect. Use IS_ERR_VALUE to detect error instead, which is
what write_sparse_chunk_raw does itself.

Fixes: 62649165cb ("lib: sparse: Make CHUNK_TYPE_RAW buffer aligned")
Reported-by: Dan Carpenter <dan.carpenter@linaro.org>
Link: https://lore.kernel.org/u-boot/1b323ec3-59b0-490b-a2f0-fd961dafcf49@moroto.mountain/
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Link: https://lore.kernel.org/r/20240201181851.221701-1-sean.anderson@seco.com
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
2024-02-09 09:42:04 +01:00
Mattijs Korpershoek
ec19e11373 MAINTAINERS: add Mattijs for Android AVB
Igor has not been active for quite some time on lore:
https://lore.kernel.org/all/?q=igor.opaniuk@gmail.com

I'm interested in helping with maintaining the android_avb
command. I'm a long time android/aosp developer and my daily job is
still doing android work.

Add myself as maintainer for Android AVB.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Igor Opaniuk <igor.opaniuk@foundries.io>
Acked-by: Igor Opaniuk <igor.opaniuk@foundries.io>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20240112-maintainers-ab-v1-2-f2a538eab18a@baylibre.com
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
2024-02-09 09:42:04 +01:00
Mattijs Korpershoek
b1907e7304 MAINTAINERS: add Mattijs for Android AB
Igor has not been active for quite some time on lore:
https://lore.kernel.org/all/?q=igor.opaniuk@gmail.com

I'm interested in helping with maintaining the android_ab
command. I'm a long time android/aosp developer and my daily job is
still doing android work.

Add myself as maintainer for Android AB.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Acked-by: Igor Opaniuk <igor.opaniuk@foundries.io>
Link: https://lore.kernel.org/r/20240112-maintainers-ab-v1-1-f2a538eab18a@baylibre.com
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
2024-02-09 09:42:04 +01:00
Andrew Davis
a4650bf65e ti: keystone2: Move common Kconfig selections to under ARCH_KEYSTONE
These select/imply settings are common to the whole architecture not just
these boards, move these settings to the architecture config.

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2024-02-08 14:42:56 -05:00
Andrew Davis
f2ae98a682 ti: keystone2: Imply NFS command support
TI KS2 boards have the nfs command in their common environment boot
configuration, enable this command.

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2024-02-08 14:42:56 -05:00
Tom Rini
2b51069b7c Merge tag 'u-boot-imx-master-20240208' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
- Add USB support for phycore-imx8mp
- Fix environment corruption, reset on mx6sabresd
- Print reset cause on imx8
- Extend mkimage to support generating an image for i.MXRT FlexSPI
- Add new apalis and colibri variants
- Add support for phyBOARD-Segin-i.MX93 support
- Fix when FEC is primarily used instead of EQOS on i.MX93.
2024-02-08 09:37:16 -05:00
Tom Rini
a7fb2f57ad Merge tag 'fsl-qoriq-2024-2-8' of https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq
Add TJA1120 driver support
fsl-layerscape/soc.c: do not destroy bootcmd environment
2024-02-08 09:10:41 -05:00
Benjamin Hahn
8dcf1df48d phycore-imx8mp: add support for booting and flashing emmc via UUU
add support for Serial Downloader Boot via UUU as well as flashing emmc
via UUU on USB0 Port of phyBOARD Pollux.

Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Benjamin Hahn <B.Hahn@phytec.de>
2024-02-08 10:11:46 -03:00
Benjamin Hahn
199229e28b phycore-imx8mp: add USB mass storage support
add support for USB mass storage to USB0 port of phyBOARD Pollux.

tested with "ums 0 mmc 2"

Signed-off-by: Benjamin Hahn <B.Hahn@phytec.de>
2024-02-08 10:11:46 -03:00
Benjamin Hahn
04bd6d9af4 phycore-imx8mp: add USB host support
The phyBOARD Pollux has two USB ports. Add support for USB host and USB
storage for the USB1 port.

Signed-off-by: Benjamin Hahn <B.Hahn@phytec.de>
2024-02-08 10:11:46 -03:00
Benjamin Hahn
a519d28cdb imx8mp-phyboard-pollux-rdk: sync with kernel devicetree from v6.8-rc2
sync devicetree with kernel v6.8-rc2.

New commits on kernel v6.8-rc2:
4a58fcdb1818 arm64: dts: imx8mp-phyboard-pollux: Add support for RS232/RS485
3bd7fdcc359e arm64: dts: imx8mp-phyboard-pollux: Add gpio-line-names
f5faa633daf8 arm64: dts: imx8mp-phyboard-pollux: Enable USB support
27c0dc128d04 arm64: dts: imx8mp-phyboard-pollux: Add flexcan support
fa2a1ec50456 arm64: dts: imx8mp-phyboard-pollux: Add missing usdhc clocks assignment
055e38c76388 arm64: dts: imx8mp-phyboard-pollux-rdk: Fix led sub-node names

Signed-off-by: Benjamin Hahn <B.Hahn@phytec.de>
2024-02-08 10:11:46 -03:00
Fabio Estevam
450af2495e mx6sabresd: Remove board_phy_config()
With Ethernet DM in place, there is no longer the need for having
the board_phy_config() anymore.

Remove it.

Confirmed that TFTP transfer still works fine without board_phy_config().

Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Igor Opaniuk <igor.opaniuk@foundries.io>
2024-02-08 09:18:32 -03:00
Fabio Estevam
dbc4814515 mx6sabresd: Convert to watchdog driver model
Commit 68dcbdd594 ("ARM: imx: Add weak default reset_cpu()") caused
the 'reset' command in U-Boot to not cause a board reset.

Fix it by switching to the watchdog driver model via sysreset, which
is the preferred method for implementing the watchdog reset.

Signed-off-by: Fabio Estevam <festevam@denx.de>
2024-02-08 09:18:32 -03:00
Fabio Estevam
41fdfae064 mx6sabresd: Fix U-Boot corruption after saving the environment
U-Boot binary has grown in such a way that it goes beyond the reserved
area for the environment variables.

Running "saveenv" and rebooting the board causes U-Boot to hang because
of this overlap.

Fix this problem by selecting CONFIG_LTO so that the U-Boot proper
size can be reduced.

Also, to prevent this same problem to happen in the future, use
CONFIG_BOARD_SIZE_LIMIT, which can detect the overlap in build-time.

CONFIG_BOARD_SIZE_LIMIT is calculated as follows:

CONFIG_BOARD_SIZE_LIMIT = CONFIG_ENV_OFFSET - u-boot-img.dtb offset
CONFIG_BOARD_SIZE_LIMIT = 0xc000 - 69 * 1024
CONFIG_BOARD_SIZE_LIMIT = 715766

Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@foundries.io>
2024-02-08 09:18:32 -03:00
Joao Paulo Goncalves
006538670d toradex: tdx-cfg-block: add 0086 i.mx8m mini sku
Add new product id 0086 Verdin iMX8M Mini DualLite 2GB IT.

Signed-off-by: Joao Paulo Goncalves <joao.goncalves@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@foundries.io>
2024-02-08 09:18:11 -03:00
Igor Opaniuk
c4bc7db966 imx: imx8: print reset cause
Add support for printing reset cause during boot.

Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>
2024-02-08 09:17:46 -03:00
Igor Opaniuk
0bc69a1d38 imx: scu_api: add implementation of sc_pm_reset_reason
Add implementation of sc_pm_reset_reason() call for obtaining
reset reason.

Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>
2024-02-08 09:17:46 -03:00
Mathieu Othacehe
7c1f8ce395 board: phytec: phycore-imx93: Add phyBOARD-Segin-i.MX93 support
Add initial support for the PHYTEC phyBOARD-Segin-i.MX93 board based on
the PHYTEC phyCORE-i.MX93 SoM.

Supported features:
- 1GB LPDDR4 RAM
- eMMC
- external SD
- FEC Ethernet
- debug UART
- watchdog

Signed-off-by: Mathieu Othacehe <othacehe@gnu.org>
Tested-by: Primoz Fiser <primoz.fiser@norik.com>
Reviewed-by: Yannic Moog <y.moog@phytec.de>
2024-02-08 09:05:11 -03:00
Primoz Fiser
259e101271 imx9: clock: Fix board_interface_eth_init for FEC
Commit d5eae216d8 ("net: dwc_eth_qos: Add board_interface_eth_init()
for i.MX93") implemented board_interface_eth_init for i.MX9 platforms.
However it only accounted for the EQOS interface while any board using
FEC as primary Ethernet interface was left out as return value -EINVAL
is always returned from the function in such case.

Fix this by returning 0 (success) when FEC interface is primarily used
instead of EQOS interface on i.MX93.

Fixes: d5eae216d8 ("net: dwc_eth_qos: Add board_interface_eth_init() for i.MX93")
Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
Tested-by: Mathieu Othacehe <m.othacehe@gmail.com>
2024-02-08 09:01:22 -03:00
Jesse Taube
b0adbd6f8e tools: mkimage: Add support for i.MXRT FlexSPI Header
Modify imx8m Flex SPI Configuration Block to work with imxrt.
Add more Flex SPI configuration options to Kconfig.

Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Tested-by:  Adam Ford <aford173@gmail.com> #imx8mn-beacon
2024-02-08 09:01:22 -03:00
Marek Vasut
9425977c47 ARM: imx: Enable kaslrseed command on Data Modul i.MX8M Mini/Plus eDM SBC
Linux 6.6.y with KASLR enabled would print the following message on boot:
"
KASLR disabled due to lack of seed
"
Enable the 'kaslrseed' command so a random number seed can be pulled
from CAAM and inserted into the /chosen node 'kaslr-seed' property of
Linux kernel DT before boot, thus letting KASLR work properly.

Signed-off-by: Marek Vasut <marex@denx.de>
2024-02-08 09:01:22 -03:00
Joao Paulo Goncalves
216ead4d59 toradex: tdx-cfg-block: Add new apalis and colibri pid
Add new apalis imx6 and colibri imx6/imx7 products IDs.

Signed-off-by: Joao Paulo Goncalves <joao.goncalves@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2024-02-08 09:01:22 -03:00
Mike Looijmans
121696c957 fsl-layerscape/soc.c: do not destroy bootcmd environment
When an XXX_BOOTCOMMAND isn't defined, the result is that bootcmd is set
to some random memory content. Fix it so that the function does nothing
in that case and leaves the bootcmd environment unmodified.

Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
Reviewed-by: Dan Carpenter <dan.carpenter@linaro.org>
2024-02-08 10:45:32 +08:00
Radu Pirea (NXP OSS)
55fc0cbbd6 net: phy: nxp-c45-tja11xx: add tja1120 support
Add TJA1120 driver structure and report 1G speed.

Signed-off-by: "Radu Pirea (NXP OSS)" <radu-nicolae.pirea@oss.nxp.com>
2024-02-08 10:41:24 +08:00
Radu Pirea (NXP OSS)
7e02c3accb net: phy: nxp-c45-tja11xx: rename nxp_c45_tja11xx structure
Rename nxp_c45_tja11xx structure to nxp_c45_tja1103. The driver will
support more PHYs and nxp_c45_tja11xx is too generic.

Signed-off-by: "Radu Pirea (NXP OSS)" <radu-nicolae.pirea@oss.nxp.com>
2024-02-08 10:41:24 +08:00
Radu Pirea (NXP OSS)
84e57e7dfb net: phy: nxp-c45-tja11xx: read PHY the speed from hardware
Read PHY speed from hardware instead of assuming 100Mbps by default.
The TJA1103 works only at 100Mbps, but the driver will support more PHYs.

Signed-off-by: "Radu Pirea (NXP OSS)" <radu-nicolae.pirea@oss.nxp.com>
2024-02-08 10:41:23 +08:00
Radu Pirea (NXP OSS)
6c43208a6d net: phy: nxp-c45-tja11xx: use local definion of features
Use a local definition for the PHY features. PHY_100BT1_FEATURES are
not defined using the 100BaseT1 bit, so keep this workaround in the driver.

Signed-off-by: "Radu Pirea (NXP OSS)" <radu-nicolae.pirea@oss.nxp.com>
2024-02-08 10:41:23 +08:00
Tom Rini
0101a2ffe1 Merge branch '2024-02-06-assorted-fixes'
A number of assorted fixes
2024-02-07 09:47:47 -05:00
Tom Rini
7ebc77fede Merge tag 'u-boot-rockchip-20240207' of https://source.denx.de/u-boot/custodians/u-boot-rockchip
- Add board: rv1126 Sonoff iHost board
- rv1126 ddr4 support;
- Enable BOOTSTD_FULL for RK3399 and RK3588;
- rk3036 spl stack addr fix;
- dts sync from linux v6.8-rc1 for rk356x, rk3588, rv1126;
- Enable eMMC HS200 mode by default for rk3568 and rk3588;
2024-02-07 08:33:47 -05:00
Shantur Rathore
b8f1f60c23 arm: dts: rockpro64: Add RockPro64 smbios
Add smbios information for Pine64 RockPro64 board and enable in
config

Signed-off-by: Shantur Rathore <i@shantur.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2024-02-07 10:49:13 +08:00
Dan Carpenter
e5e7d8bbcf blk: host_dev: Fix error code in host_sb_attach_file()
This error path should return -EINVAL instead of success.

Fixes: e261fbf347 ("blk: host_dev: Sanity check on the size of host backing file")
Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
2024-02-06 16:31:07 -05:00
Dhruva Gole
c59720c5f4 firmware: ti_sci: Add comment explaining the is_secure code
Add a comment to explain the code under is_secure condition of
ti_sci_do_xfer. This will help avoid confusion amongst people who may in
future touch upon this code.

Reviewed-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Dhruva Gole <d-gole@ti.com>
2024-02-06 16:31:06 -05:00
Dhruva Gole
0c4e36d65f firmware: ti_sci: fix the secure_hdr in do_xfer
The ti_sci driver in U-Boot has support for secure_msg as part of it's
do_xfer function. This let's U-boot send secure messages during boot up.

The protocol to send such secure messages is described as part of the
struct ti_sci_secure_msg_hdr. As part of this, there are 2 fields for
checksum and reserved that occupy the first 4 bytes of any secure
message. This is called as the secure_hdr.

As of now, the secure_hdr needs to be 0 init-ed before sending secure
messages. However the existing code was never putting the zero-inited vars
into the secure_buf, leading to possibility of the first 4 bytes of
secure_buf being possibly garbage.

Fix this by initialising the secure_hdr itself to the secure_buf
location, thus when we make secure_hdr members 0, it automatically ensures
the first 4 bytes of secure_buf are 0.

Fixes: 32cd25128b ("firmware: Add basic support for TI System Control Interface (TI SCI)")
Reviewed-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Dhruva Gole <d-gole@ti.com>
2024-02-06 16:31:06 -05:00
Neha Malcom Francis
94cfc6fc96 arm: mach-k3: j721s2_init: Support less than max DDR controllers
The number of DDR controllers to be initialised and used should depend
on the device tree with the constraint of the maximum number of
controllers the device supports. Since J721S2 has multiple (2)
controllers, instead of hardcoding the number of probes, move to
depending on the device tree UCLASS_RAM nodes present.

Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com>
2024-02-06 16:31:06 -05:00
MD Danish Anwar
4312a1dfca dma: ti: k3-udma: Use ring_idx to pair k3 nav rings
Use ring_idx to pair rings. ring_idx will be same as tx flow_id for all
non-negative flow_ids. For negative flow_ids, ring_idx will be tchan->id
added with bchan_cnt.

Link: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/dma/ti/k3-udma.c?h=v6.8-rc2#n1686
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
Reviewed-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
2024-02-06 16:31:06 -05:00
Ole P. Orhagen
798ad3e6b2 vexpress_ca9x4: Enable DM_SERIAL
This commit enables support for DM_SERIAL in the vexpress_ca9x4 boards.

When running the board with the DM_SERIAL driver, the board ran out of
memory in SPL when initialising the DM serial driver.

Thus this required an increase in the pre-allocated SRAM memory. I did
increase it to 0x800, and it now works graciously.

It could probably be set lower, but I do not see any reason not to use the
available SRAM at this point.

Also adds stdout-path to the 'chosen' node in the device tree.

Signed-off-by: Ole P. Orhagen <ole.orhagen@northern.tech>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
2024-02-06 16:31:06 -05:00
Heinrich Schuchardt
0c5110ccf8 common: event: check event_type_name() argument
In event_type_name() we should avoid possible buffer overruns by checking
the type argument.

Addresses-Coverity-ID: 478862 Out-of-bounds access
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-02-06 16:31:06 -05:00
Jim Liu
dd0807804e arm: dts: nuvoton: modify npcm8xx reset property
Change reset method from generic to reset driver

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2024-02-06 16:31:06 -05:00
Brandon Maier
cb6f4d6510 scripts/gen_compile_commands: update to Linux v6.7
Adds support for assembly files and updates the LINE_PATTERN so it
supports both "cmd" and "savedcmd", which allows reverting the U-Boot
modification in commit 97fbb2eb01 ("scripts/gen_compile_commands.py:
adapt _LINE_PATTERN").

Upstream commits:

- 880946158b011 gen_compile_commands.py: fix path resolve with symlinks in it
- 9e56d3be4bfd2 gen_compile_commands: Sort output compile commands by file name
- 52c15e7e79285 gen_compile_commands: Allow the line prefix to still be cmd_
- 1c67921444bf6 gen_compile_commands: add assembly files to compilation database

Signed-off-by: Brandon Maier <brandon.maier@collins.com>
Cc: Joao Marcos Costa <jmcosta944@gmail.com>
2024-02-06 16:31:06 -05:00
Tom Rini
daa3100250 Merge patch series "board: siemens: clean up subfolders"
Enrico Leto <enrico.leto@siemens.com> says:

    The common folder was initialially created for the common parts of
    the products based on draco-am355x board family. We have the
    product lines 'pxm2', 'rut' and the base line unfortunately named
    'draco'! Adding the new capricorn-imx8 board family, the files
    were enhanced without cleanup.

    Simplify first EEPROM probe and access that implements both i2c
    with & without driver model. Use abstraction functions for this.

    Move all am355x specifics to a new file 'board_am335x'.

    Clean-up includes, config checks, maintainer.
2024-02-05 13:33:01 -05:00
Enrico Leto
b062eef075 siemens: factoryset: use correct config for soc specific implementation
Adding the capricorn board family some parts diverge from draco family.
The switches used were not pertinent and need to be enhanced for each new
board of the capricorn family. Replace them through the SOC name 'AM33XX'
and 'IMX8'.

Signed-off-by: Enrico Leto <enrico.leto@siemens.com>
2024-02-05 13:32:48 -05:00
Enrico Leto
60ad0fdb19 siemens: board: clean up includes
Many includes were not removed when code parts were moved or removed.

Signed-off-by: Enrico Leto <enrico.leto@siemens.com>
2024-02-05 13:32:48 -05:00
Enrico Leto
d89a97ef94 siemens: board: clean up products folders vs common
The common folder was initialially created for the common parts of the
products based on draco-am355x board family. These are the product lines
'pxm2', 'rut' and the base line named 'draco'!

Adding the new capricorn-imx8 board family, common was enhanced without
cleanup.
- rename 'common/board.c' to 'common/board_am335x.c'
- add 'common/board_am335x.h' for export to the product lines

Reviewed-by: Alexander Sverdlin <alexander.sverdlin@siemens.com>
Signed-off-by: Enrico Leto <enrico.leto@siemens.com>
2024-02-05 13:32:48 -05:00
Enrico Leto
671be9f539 siemens: board: etamin: remove deprecated nand config
NAND was used in the early development phase of etamin. The board runs now
on MMC. This setting is no more used -> remove to simplify the board file.

Further clean-up of etamin should remove all NAND settings. Complete clean-
up of etamin board will take place in a separate patch serie.

Signed-off-by: Enrico Leto <enrico.leto@siemens.com>
2024-02-05 13:32:48 -05:00
Enrico Leto
12e60282cb siemens draco: i2c: use driver model for u-boot
Add support for driver model where EEPROM data are read in draco board.

Reviewed-by: Alexander Sverdlin <alexander.sverdlin@siemens.com>
Signed-off-by: Enrico Leto <enrico.leto@siemens.com>
2024-02-05 13:32:48 -05:00
Enrico Leto
e9ef9a1377 siemens: eeprom: simplify setup & read
Since we have boards using the driver model or not for i2c, use abstraction
function to probe the i2c, check the EEPROM and read from EEPROM.

Signed-off-by: Enrico Leto <enrico.leto@siemens.com>
2024-02-05 13:32:48 -05:00
Enrico Leto
5ae54613eb siemens: eeprom: clean up definitions
Move the I2C and EEPROM address definitions in common board header.

Reviewed-by: Alexander Sverdlin <alexander.sverdlin@siemens.com>
Signed-off-by: Enrico Leto <enrico.leto@siemens.com>
2024-02-05 13:32:48 -05:00
Tom Rini
090d8463b0 Merge tag 'rpi-next-2024.04' of https://source.denx.de/u-boot/custodians/u-boot-raspberrypi
Add RaspberryPi5 basic support.

Acked-by: Peter Robinson <pbrobinson@gmail.com>
2024-02-05 09:31:48 -05:00
Jonas Karlman
363cbd5781 rockchip: rk3568-generic: Enable eMMC HS200 mode
Writing to eMMC using HS200 mode work more reliably then other modes on
RK356x boards.

Add device tree props and enable Kconfig options for eMMC HS200 mode on
the generic RK3566/RK3568 board. Also enable the pinctrl driver in SPL
and add missing rk3568-generic.dtb to Makefile.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-02-05 15:06:04 +08:00
Andy Yan
1814eb72a3 rockchip: rk3588-evb: Enable USB support
Enable USB releated config to support
boot from usb.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-02-05 15:04:47 +08:00
Jonas Karlman
5c053f3adc mmc: rockchip_sdhci: Fix HS400 mode write on RK3568
Testing has shown that writing to eMMC using HS400 modes on RK3568
result in an ERROR.

Change the tap number for transmit clock to fix this.

Also stop DLL when config_dll() is called to disable DLL.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-02-05 15:00:51 +08:00
Jonas Karlman
6de9d7b2f1 rockchip: rk35xx: Enable eMMC HS200 mode by default
Testing has shown that writing to eMMC using a slower mode then HS200
typically generate an ERROR on first attempt on RK3588.

  # Rescan using MMC legacy mode
  => mmc rescan 0

  # Write a single block to sector 0x4000 fails with ERROR
  => mmc write 20000000 4000 1

  # Write a single block to sector 0x4000 now works
  => mmc write 20000000 4000 1

With the MMC_SPEED_MODE_SET Kconfig option enabled.

Writing to eMMC using HS200 mode work more reliably than slower modes on
RK35xx boards. Enable MMC_HS200_SUPPORT Kconfig option by default to
prefer use of HS200 mode on RK356x and RK3588.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-02-05 15:00:51 +08:00
Jonas Karlman
ebe293bae7 rockchip: rk35xx: Remove use of eMMC DDR52 mode
Testing has shown that writing to eMMC using DDR52 mode does not seem to
work on RK356x and RK3588 boards.

A simple test of writing a single block to e.g. sector 0x4000 fails:

  # Rescan using DDR52 mode
  => mmc rescan 4

  # Write a single block to sector 0x4000 fails with ERROR
  => mmc write 20000000 4000 1

With the MMC_SPEED_MODE_SET Kconfig option enabled.

Fix this by removing the mmc-ddr-1_8v prop from sdhci nodes in affected
board u-boot.dtsi files.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-02-05 15:00:51 +08:00
Jonas Karlman
b323baffd5 rockchip: rk3588-quartzpro64: Enable AHCI, PCI and USB
Enable Kconfig options to support AHCI, PCI and USB features. This help
keep rk3588-quartzpro64 in sync with other RK3588 boards.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-02-05 15:00:32 +08:00
Jonas Karlman
8ef97f8138 rockchip: rk3588: Enable eMMC HS200 mode
Writing to eMMC using HS200 mode work more reliably then other modes on
RK3588 boards.

Enable MMC_HS200_SUPPORT Kconfig option to prefer use of HS200 mode.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Weizhao Ouyang <o451686892@gmail.com>
2024-02-05 15:00:32 +08:00
Jonas Karlman
e927782527 rockchip: rk35xx: Remove unnecessary status props
Remove unnecessary status props from rk35xx u-boot.dtsi files, regular
device tree files or default value already enable the affected nodes.

Also reorder bootph-pre-ram and clock-frequency props alphabetically in
rk3588s-u-boot.dtsi uart2 node.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-02-04 18:47:26 +08:00
Jonas Karlman
e1292c2016 rockchip: rk3588: Add default u-boot,spl-boot-order prop
Add a default u-boot,spl-boot-order prop to rk3588s-u-boot.dtsi and
remove the prop from board u-boot.dtsi files using the default value.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-02-04 18:47:26 +08:00
Jonas Karlman
73707d31f6 rockchip: rk3588: Sync device tree from linux v6.8-rc1
Sync rk3588 device tree from linux v6.8-rc1.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
2024-02-04 18:47:25 +08:00
Jonas Karlman
7c3e42b613 rockchip: rk3588: Sync device tree with linux v6.7
Sync rk3588 device tree from linux v6.7.

Also drop the rockchip,rk3568-dwc3 compatible now that dwc3-generic
driver support the rockchip,rk3588-dwc3 compatible.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
2024-02-04 18:47:25 +08:00
Jonas Karlman
473e54e795 rockchip: rk356x: Move common uart2 props to rk356x-u-boot.dtsi
Move uart2 bootph-pre-ram and clock-frequency props from board to SoC
u-boot.dtsi. Regular board device tree already enables the uart2 node,
so status prop is dropped from u-boot.dtsi file.

Also remove unnecessary stdout-path = &uart2, regular board device tree
already provide a stdout-path = "serial2:" value.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-02-04 18:47:25 +08:00
Jonas Karlman
d7b100ab32 rockchip: rk356x: Sync device tree from linux v6.8-rc1
Sync rk356x device tree from linux v6.8-rc1.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-02-04 18:47:25 +08:00
Jonas Karlman
9e4d11a39a rockchip: rk356x: Sync device tree from linux v6.7
Sync rk356x device tree from linux v6.7.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-02-04 18:47:25 +08:00
Shantur Rathore
ebb0ad4eef arch: arm: mach-rockchip: Kconfig: Enable BOOTSTD_FULL for RK3399 and RK3588
Rockchip RK3399 and RK3588 SoCs can support wide range of bootflows.
Without full bootflow commands, it can be difficult to
figure out issues if any, hence enable by default.

Reviewed-by: Simon Glass <sjg@chromium.org>

Signed-off-by: Shantur Rathore <i@shantur.com>
2024-02-04 18:47:10 +08:00
Tim Lunn
e6593b5d1d rockchip: rv1126: Move RAM disk address
OPTEE gets loaded into a memory region overlapping with the ram disk.

Fix the ramdisk address so it doesn't overlap with the OPTEE memory
region.

Signed-off-by: Tim Lunn <tim@feathertop.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-02-04 18:45:58 +08:00
Tim Lunn
16c8321549 rockchip: rv1126: select SPL_OPTEE_IMAGE
rv1126 requires OPTEE as it provides pcsi support. Mainline Linux
kernel will fail to boot without this.

Select SPL_OPTEE_IMAGE when building FIT image. TEE must be provided
when building.

Signed-off-by: Tim Lunn <tim@feathertop.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-02-04 18:45:58 +08:00
Tim Lunn
e5eba349d6 board: rockchip: Add Sonoff iHost board
Sonoff iHost is gateway device designed to provide a Smart Home Hub,
it is based on Rockchip RV1126. There is also a version with 2GB RAM
based off the RV1109 dual core SoC however this works with the same
config as the RV1126 for uboot purposes.

Features:
- Rockchip RV1126
- 4GB DDR4
- 8GB eMMC
- microSD slot
- RMII Ethernet PHY
- 1x USB 2.0 Host
- 1x USB 2.0 OTG
- Realtek RTL8723DS WiFi/BT
- EFR32MG21 Silabs Zigbee radio
- Speaker/Microphone

Signed-off-by: Tim Lunn <tim@feathertop.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-02-04 18:45:58 +08:00
Tim Lunn
3da3bb9636 rockchip: Convert rv1126 to standard boot
RV1126 soc appears to have been missed with the conversion of
rockchip socs to standard boot.

Remove remnants of distro boot for rv1126 common and the one
existing board.

Signed-off-by: Tim Lunn <tim@feathertop.org>
Link: https://lore.kernel.org/all/20230407223645.v8.8.I4cf7708a1ba953b9abd81375d93af34665c7b251@changeid/
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-02-04 18:45:58 +08:00
Tim Lunn
644e8fc2d5 ram: rockchip: Add rv1126 ddr4 support
Add support for ddr4 on rv1126. Timing detection files are imported
from downstream Rockchip BSP u-boot. Allow selecting ddr4 ram with
define CONFIG_RAM_ROCKCHIP_DDR4.

Signed-off-by: Tim Lunn <tim@feathertop.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-02-04 18:45:58 +08:00
Tim Lunn
03ee0553a0 arm: dts: rockchip: Sync rv1126 dts from linux 6.8-rc1
Sync linux dts files for rv1126 boards from linux v6.8-rc1 tag. Includes
the newly added dts for Sonoff iHost.

Signed-off-by: Tim Lunn <tim@feathertop.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-02-04 18:45:58 +08:00
Jonas Karlman
33380a5a91 rockchip: rk3328-rock-pi-e: Enable DM_ETH_PHY and PHY_REALTEK
Enable the DM_ETH_PHY and PHY_REALTEK now that the designware ethernet
driver call eth_phy_set_mdio_bus() to assist with resetting the eth PHY
during probe.

Fixes ethernet on the v1.21 hw revision of Radxa ROCK Pi E:

  => mdio list
  ethernet@ff540000:
  1 - RealTek RTL8211F <--> ethernet@ff540000
  => net list
  eth0 : ethernet@ff540000 86:e0:c0:ea:fa:a9 active
  eth1 : ethernet@ff550000 86:e0:c0:ea:fa:a8
  => dhcp
  Speed: 1000, full duplex
  BOOTP broadcast 1
  BOOTP broadcast 2
  BOOTP broadcast 3
  DHCP client bound to address 192.168.1.114 (1004 ms)

Reported-by: Trevor Woerner <twoerner@gmail.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-02-04 18:02:45 +08:00
Jonas Karlman
f1e2f412b0 net: designware: Reset eth phy before phy connect
Some ethernet PHY require being reset before a phy-id can be read back
on the MDIO bus. This can result in the following message being show
on e.g. a Radxa ROCK Pi E v1.21 with a RTL8211F ethernet PHY.

  Could not get PHY for ethernet@ff540000: addr -1

Add support to designware ethernet driver to reset eth phy by calling
the eth phy uclass function eth_phy_set_mdio_bus(). The call use NULL
as bus parameter to not set a shared mdio bus reference that would be
freed when probe fails. Also add a eth_phy_get_addr() call to try and
get the phy addr from DT when DM_MDIO is disabled.

This help fix ethernet on Radxa ROCK Pi E v1.21:

  => mdio list
  ethernet@ff540000:
  1 - RealTek RTL8211F <--> ethernet@ff540000

Reported-by: Trevor Woerner <twoerner@gmail.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-02-04 18:02:45 +08:00
Kever Yang
52e3353385 configs: rockchip: rk3036: Fix CONFIG_SPL_STACK define
The CONFIG_SPL_STACK for rk3036 is removed in below patch, need to add
it back.

Fixes: f113d7d303 ("Convert CONFIG_SPL_STACK to Kconfig")
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2024-02-04 18:01:03 +08:00
Kever Yang
ce7ae9d2db spl: Make SPL_STACK available for ROCKCHIP_RK3036 without spl framework
rk3036 soc has limit internal sram, and not able to support spl
framework.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2024-02-04 18:01:03 +08:00
YouMin Chen
875bc40a00 rockchip: sdram: fix LPDDR5 bank info for sys_reg version 3
This patch add support for additional bank info used by LPDDR5.

Series-version: 2

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2024-02-04 18:01:03 +08:00
Tom Rini
819abd0a1e Merge tag 'smbios-2024-04-rc2' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request smbios-2024-04-rc2

* In smbios command
  - write 'Not Specified' for missing strings
  - show correct table size for SMBIOS2.1 entry point
  - adjust formatting of handle numbers
  - add missing colon after UUID
* In generated SMBIOS table
  - avoid introducing 'Unknown' string for missing properties
  - provide RISC-V vendor ID in the type 4 structure
  - provide the correct chassis handle in structure type 2
* Rename Structure Table Maximum Size field in SMBIOS 3 entry point
2024-02-03 09:11:25 -05:00
Heinrich Schuchardt
406c410ef7 smbios: correctly name Structure Table Maximum Size field
In the SMBIOS 3 entry point the Structure Table Maximum Size field was
incorrectly named max_struct_size. A Maximum Structure Size field only
exists in the SMBIOS 2.1 entry point and has a different meaning.

Call the Structure Table Length field table_maximum_size.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-02-02 19:57:45 +01:00
Heinrich Schuchardt
e494258ded smbios: do not determine maximum structure size
Only the SMBIOS 2.1 entry point has a field for the maximum structure size.
As we have switched to an SMBIOS 3 entry point remove the superfluous
calculation.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-02-02 19:57:45 +01:00
Heinrich Schuchardt
551bc96be5 cmd: smbios: show correct table size for SMBIOS2.1 entry point
The SMBIOS table size for SMBIOS2.1 entry points is in field 'Structure
Table Length' (offset 0x16) and not in field 'Maximum Structure Size'
(offset 0x08).

Rename the receiving variable max_struct_size to table_maximum_size
to avoid future confusion.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-02-02 19:57:45 +01:00
Heinrich Schuchardt
5778c88eb0 smbios: correctly fill chassis handle
The chassis handle field in the type 2 structure must point to the handle
of the type 3 structure.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-02-02 19:57:16 +01:00
Heinrich Schuchardt
545e0e42b9 smbios: provide type 4 RISC-V SMBIOS Processor ID
For RISC-V CPUs the SMBIOS Processor ID field contains
the Machine Vendor ID from CSR mvendorid.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-02-02 19:57:16 +01:00
Heinrich Schuchardt
6ebf9136ec smbios: if a string value is unknown, use string number 0
The SMBIOS specification describes: "If a string field references no string,
a null (0) is placed in that string field."

Accordingly we should avoid writing a string "Unknown" to the SMBIOS table.

dmidecode displays 'Not Specified' if the string number is 0.

Commit 00a871d34e ("smbios: empty strings in smbios_add_string()")
correctly identified that strings may not have length 0 as two
consecutive NULs indentify the end of the string list. But the suggested
solution did not match the intent of the SMBIOS specification.

Fixes: 00a871d34e ("smbios: empty strings in smbios_add_string()")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-02-02 19:56:54 +01:00
Matthias Brugger
e31efe50b5 smbios: Fix table when no string is present
When no string is present in a table, next_ptr points to the same
location as eos. When calculating the string table length, we would only
reserve one \0. By spec a SMBIOS table has to end with two \0\0 when no
strings a present.

Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-02-02 19:56:54 +01:00
Heinrich Schuchardt
c11f176ab1 cmd: smbios: replace missing string by 'Not Specified'
A missing string value is indicated by a string index of 0. In this case
print 'Not Specified' like the Linux dmidecode command does.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-02-02 19:56:54 +01:00
Heinrich Schuchardt
e799f8a48d cmd: smbios: add missing colon after UUID
For consistent formatting add a colon ':' after the UUID label.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-02-02 19:56:34 +01:00
Heinrich Schuchardt
7ca4b0ea6a cmd: smbios: always use '0x%04x' for printing handles
Handles are u16 numbers. Consistently use '0x%04x' to print them.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-02-02 19:55:29 +01:00
Heinrich Schuchardt
b327e64d5f smbios: get_str_from_dt() - add sysinfo_id description
Add description for parameter sysinfo_id of function get_str_from_dt().

Fixes: 07c9e683a4 ("smbios: Allow a few values to come from sysinfo")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-02-02 19:55:29 +01:00
Heinrich Schuchardt
85e490b22e lib: smbios_entr() use logical or for booleans
As a matter of programming style use logical or to combine two boolean
results.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-02-02 19:55:29 +01:00
Tom Rini
050a9b981d Merge tag 'u-boot-amlogic-fixes-20240201' of https://source.denx.de/u-boot/custodians/u-boot-amlogic
- stop printing board model twice after sysinfo update
2024-02-01 09:59:53 -05:00
Tom Rini
f0df21b40c Merge https://source.denx.de/u-boot/custodians/u-boot-watchdog
- add andes atcwdt200 support (Randolph)
2024-02-01 09:59:09 -05:00
Randolph
094eda0660 configs: andes: add watchdog support fot andes ae350
It adds the ATCWDT200 support for Andes AE350 platform.
It also enables wdt command support.

Signed-off-by: CL Wang <cl634@andestech.com>
Signed-off-by: Randolph <randolph@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-02-01 09:08:44 +01:00
Randolph
4350e99937 drivers: watchdog: add andes atcwdt200 support
This patch adds an implementation of the Andes watchdog ATCWDT200 driver.

Signed-off-by: CL Wang <cl634@andestech.com>
Signed-off-by: Randolph <randolph@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-02-01 09:08:44 +01:00
Tom Rini
b6d8969bcb Merge tag 'u-boot-at91-2024.04-a' of https://source.denx.de/u-boot/custodians/u-boot-at91
First set of u-boot-at91 features for the 2024.04 cycle:

This set includes some DT alignments and solves a compile issue for
custom nand defconfigs.
2024-01-31 10:44:33 -05:00
Tom Rini
625e68ef65 Merge https://source.denx.de/u-boot/custodians/u-boot-riscv
* Add RISC-V falcon mode documentation
* Add Clang build support
* Add cmd to detect Debug Trigger Extension support

* Add PWM setting for Unmatched board
* Add Milk-V Duo board support
* Add new device node and enable new config option for VisionFive2 board
* Add second virtio device for RISC-V QEMU
2024-01-31 08:49:35 -05:00
Nam Cao
6882255ac3 riscv: dts: starfive: add regulator device
Add the axp15060 regulator device. OpenSBI uses this device to perform
board reset and shutdown.

Signed-off-by: Nam Cao <namcao@linutronix.de>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-01-31 16:52:53 +08:00
Nam Cao
92802e12ef riscv: dts: jh7110: add power management unit controller node
JH7110 has a power management unit controller node. Add this node.

This device is used by OpenSBI during board reset/shutdown.

Signed-off-by: Nam Cao <namcao@linutronix.de>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-01-31 16:52:53 +08:00
Lukasz Tekieli
70f150759b board: visionfive2: configure PHY pad drive strength
Configure the pad drive strength register for both PHYs.
The values correspond to what can be found in the Linux DTS
for VisionFive2 v1.3b.

Pad drive strength configuration is required for the phy0 to work correctly
with 100Mbit links.

Signed-off-by: Lukasz Tekieli <tekieli.lukasz@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-01-31 16:52:49 +08:00
Lukasz Tekieli
c025c8afd4 net: phy: motorcomm: configure pad drive strength register
This ports the pad drive strength register configuration which can be
already found in the Linux driver for this PHY.

Signed-off-by: Lukasz Tekieli <tekieli.lukasz@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-01-31 16:52:49 +08:00
Kongyang Liu
36278b7051 doc: sophgo: milkv_duo: document Milk-V Duo board
Add document for Milk-V Duo board which based on Sophgo's CV1800B SoC.

Signed-off-by: Kongyang Liu <seashell11234455@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-01-31 16:52:45 +08:00
Kongyang Liu
0dc6ee6d2b riscv: sophgo: milkv_duo: initial support added
Add support for Sophgo's Milk-V Duo board, only minimal device tree and
serial console are enabled, and it can boot via vendor first stage
bootloader.

Signed-off-by: Kongyang Liu <seashell11234455@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-01-31 16:52:45 +08:00
Kongyang Liu
f03d2ab206 riscv: dts: sophgo: add basic device tree for Milk-V Duo board
Import device tree from Linux kernel to add basic support for CPU, PLIC,
UART and Timer. The name cv1800b in the filename represent the chip used
on Milk-V Duo board.

Signed-off-by: Kongyang Liu <seashell11234455@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-01-31 16:52:45 +08:00
Aurelien Jarno
386db9a26b configs: visionfive2: Disable ENV_IS_NOWHERE
The VisionFive 2 board supports saving the u-boot environment settings
are saved to on-board SPI flash. However the defconfig enables both
ENV_IS_NOWHERE and ENV_IS_IN_SPI_FLASH, preventing the "saveenv" command
to work. Fix that by disabling ENV_IS_NOWHERE.

Fixes: 7d79bed00c ("configs: starfive: Enable environment in SPI flash support")

Reported-by: E Shattow <lucent@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-01-31 16:52:38 +08:00
kleines Filmröllchen
ee9f9d6a41 riscv: Support building with Clang
The -ffixed-gp option of GCC has an exact equivalent of -ffixed-x3 in
Clang.

Signed-off-by: kleines Filmröllchen <filmroellchen@serenityos.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2024-01-31 16:52:36 +08:00
Heinrich Schuchardt
6b0520c939 cmd: sbi: add support for Debug Trigger Extension
Detect and show if the SBI implements the Debug Trigger Extension.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-01-31 16:52:30 +08:00
Vincent Chen
282159ff24 board: sifive: spl: Initialized the PWM setting in the SPL stage
LEDs and multiple fans can be controlled by SPL. This patch ensures
that all fans have been enabled in the SPL stage. In addition, the
LED's color will be set to yellow.

Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
Co-developed-by: Nylon Chen <nylon.chen@sifive.com>
Signed-off-by: Nylon Chen <nylon.chen@sifive.com>
Co-developed-by: Zong Li <zong.li@sifve.com>
Signed-off-by: Zong Li <zong.li@sifve.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-01-31 16:52:24 +08:00
Aurelien Jarno
cbc45cb596 riscv: qemu: enable booting on a second virtio device
QEMU RISC-V supports multiple virtio devices, but only tries to boot to
the first one. Enable support for a second virtio device, that is useful
for instance to boot on a disk image + an installer. Ideally that should
be made dynamic, but that's a first step.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-01-31 16:52:15 +08:00
Aurelien Jarno
465e7e6d50 board: starfive: handle compatible property in dynamic DT configuration
The difference between the StarFive VisionFive 2 1.2A and 1.3B boards is
handled dynamically by looking at the PCB version in the EEPROM in order
to have a single u-boot version for both versions of the board. While
the "model" property is correctly handled, the "compatible" one is
always the the one of version 1.3b.

This patch add support for dynamically configuring that property.

Fixes: 9b7060bd15 ("riscv: dts: jh7110: Combine the board device tree files of 1.2A and 1.3B")

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-01-31 16:52:07 +08:00
Randolph
a400ffad02 configs: andes: add the fdt blob copy address for SPL
Add the address to which the FDT blob is to be moved.

Signed-off-by: Randolph <randolph@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-01-31 16:51:03 +08:00
Randolph
10c4ab898c spl: riscv: falcon: move fdt blob to specified address
In Falcon Boot mode, the fdt blob should be move to the RAM from
kernel BSS section. To avoid being cleared by BSS initialisation.
SPL_PAYLOAD_ARGS_ADDR is the address where SPL copies.

Signed-off-by: Randolph <randolph@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-01-31 16:51:03 +08:00
Randolph
011d07b4d8 doc: falcon: riscv: Falcon Mode boot on RISC-V
Add documentation to introduce the Falcon Mode on RISC-V.
In this mode, the boot sequence is SPL -> OpenSBI -> Linux kernel.

Signed-off-by: Randolph <randolph@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-01-31 16:51:03 +08:00
Ivan T. Ivanov
12d479d018 configs: rpi_arm64: build position independent code
Latest RPi5 EEPROM firmware versions after "DATE: 2023/10/30", has changed
kernel load address from 0x80000 to 0x200000 which break boot process.
Switch to position independent code to be able to boot the same binary
on top of different EEPROM firmware versions.

Tested on:
Raspberry Pi 5 Model B Rev 1.0
Raspberry Pi 4 Model B Rev 1.1
Raspberry Pi 3 Model B Plus Rev 1.3
Raspberry Pi Zero 2 W Rev 1.0
Raspberry Pi 2 Model B Rev 1.2
Raspberry Pi Compute Module 4 Rev 1.0
Raspberry Pi Compute Module 3 Rev 1.0

Tested-by: Jens Maus <mail@jens-maus.de>
Tested-by: Darko Alavanja <darko.alavanja@konsulko.com>
Signed-off-by: Ivan T. Ivanov <iivanov@suse.de>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2024-01-30 17:40:13 +01:00
Ivan T. Ivanov
239fd8651d configs: rpi_arm64: enable SDHCI BCMSTB driver
RPi5 have "brcm,bcm2712-sdhci" controller which is
handled by "sdhci-bcmstb" driver, so enable it.

Tested-by: Jens Maus <mail@jens-maus.de>
Tested-by: Darko Alavanja <darko.alavanja@konsulko.com>
Signed-off-by: Ivan T. Ivanov <iivanov@suse.de>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2024-01-30 17:40:07 +01:00
Ivan T. Ivanov
10127cdbab mmc: bcmstb: Add support for bcm2712 SD controller
Make sure that core SDHCI accessors are used and add
device specific card detection initialization, which
is borrowed from vendor Linux driver code.

Tested-by: Jens Maus <mail@jens-maus.de>
Tested-by: Darko Alavanja <darko.alavanja@konsulko.com>
Signed-off-by: Ivan T. Ivanov <iivanov@suse.de>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2024-01-30 17:40:01 +01:00
Ivan T. Ivanov
cce167eb8d bcm2835: Dynamically calculate bytes per pixel parameter
brcm,bcm2708-fb device provided by firmware on RPi5 uses
16 bits per pixel, so lets calculate framebuffer bytes
per pixel dynamically based on queried information.

Tested to work for RPi2b v1.2, RPi3b v1.3, RPi4b v1.1,
RPi2 Zero W, RPi5b v1.0.

Reviewed-by: Matthias Brugger <mbrugger@suse.com>
Tested-by: Jens Maus <mail@jens-maus.de>
Tested-by: Darko Alavanja <darko.alavanja@konsulko.com>
Signed-off-by: Ivan T. Ivanov <iivanov@suse.de>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2024-01-30 17:39:51 +01:00
Ivan T. Ivanov
08a5b4bd6c rpi5: Use devicetree to retrieve board revision
Firmware on RPi5 return error on board revision query
through firmware interface, but on the other hand it fills
"linux,revision" in "system" node, so use it to detect board
revision.

	system {
		linux,revision = <0xc04170>;
		linux,serial = <0x6cf44e80 0x3c533ede>;
	};

Reviewed-by: Matthias Brugger <mbrugger@suse.com>
Tested-by: Jens Maus <mail@jens-maus.de>
Tested-by: Darko Alavanja <darko.alavanja@konsulko.com>
Signed-off-by: Ivan T. Ivanov <iivanov@suse.de>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2024-01-30 17:39:46 +01:00
Dmitry Malkin
60878e753c rpi5: Use devicetree as alternative way to read IO base addresses
MBOX and Watchdog on RPi5/bcm2712 have a different base IO offsets.
Find them via devicetree blob passed by bootloader.

Signed-off-by: Dmitry Malkin <dmitry@bedrocksystems.com>
Reviewed-by: Matthias Brugger <mbrugger@suse.com>
Tested-by: Jens Maus <mail@jens-maus.de>
Tested-by: Darko Alavanja <darko.alavanja@konsulko.com>
Signed-off-by: Ivan T. Ivanov <iivanov@suse.de>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2024-01-30 17:39:39 +01:00
Dmitry Malkin
a5a27eafc4 rpi5: add initial memory map for bcm2712
This includes:
* 1GB of RAM (from 4GB or 8GB total)
* AXI ranges (main peripherals)

When HDMI cable is plugged in at boot time firmware will
insert "simple-framebuffer" device into devicetree and will
shrink first memory region to 0x3f800000UL. Board setup then
will properly reserve framebuffer region.

When no HDMI cable is plugged in the size of the region will
be 0x3fc00000UL.

Signed-off-by: Dmitry Malkin <dmitry@bedrocksystems.com>
Tested-by: Jens Maus <mail@jens-maus.de>
Tested-by: Darko Alavanja <darko.alavanja@konsulko.com>
Signed-off-by: Ivan T. Ivanov <iivanov@suse.de>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2024-01-30 17:39:31 +01:00
Tom Rini
28760ce864 Merge tag 'clk-2024.04-rc2' of https://source.denx.de/u-boot/custodians/u-boot-clk
Clock changes for v2024.04

This pull has the usual fixes and new (clock-adjacent) drivers. It also has some
cleanups for the clock API; in particular removing the unused rfree callback.

CI: https://source.denx.de/u-boot/custodians/u-boot-clk/-/pipelines/19486
2024-01-30 07:54:28 -05:00
Neil Armstrong
076529725f ARM: meson: stop printing board model after sysinfo update
After the sysinfo update, Model is printed twice, remove
the now duplicate Model print from mach-meson/board-info.

Link: https://lore.kernel.org/r/20240124-u-boot-model-print-fix-v1-1-484960069623@linaro.org
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2024-01-30 09:35:51 +01:00
Svyatoslav Ryhel
a8dc4965f0 clk: clk-gpio: add actual gated clock
Existing gpio-gate-clock driver acts like a simple GPIO switch without any
effect on gated clock. Add actual clock actions into enable/disable ops and
implement get_rate op by passing gated clock if it is enabled.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Link: https://lore.kernel.org/r/20240110160956.4476-2-clamor95@gmail.com
[ sorted includes ]
Signed-off-by: Sean Anderson <seanga2@gmail.com>
2024-01-29 22:35:34 -05:00
Sean Anderson
0bfbb83055 clk: Document clk_ops return codes and behavior
Currently, clock consumers cannot take any programmatic action based on the
return code of a clock function. This is because there is no
standardization, and generally no way of separating e.g. "there was a major
problem setting the rate for this clock" which usually should not be
recovered from, from "this clock doesn't support setting its rate" or "this
clock doesn't support *this* rate" which could be absolutely fine depending
on the driver.

This commit aims to standardize the acceptable codes which may be returned
from clock operations. In general,

- ENOSYS should be returned when an operation is not supported for a
  particular clock.
- ENOENT may be returned if the clock ID is invalid. However, it is
  encouraged to move any checks to request() to reduce code duplication.
- EINVAL should be returned for logical errors only (such as requesting an
  invalid rate).

Each function has had specific guidance added for when to return each error
code. This is just guidance for now; most of the clock subsystem does not
yet conform to this standard. However, it is expected that new clock
drivers return these error codes.

Additionally, this commit adds expected behavior for each of the clock
operations. I believe these should be mostly straightforward and correspond
to existing behavior. I remember not understanding what the expected
invariants were for several clock functions, so hopefully this should help
out new driver authors. In the future, some of these invariants could be
checked via an optional config option.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Link: https://lore.kernel.org/r/20231216193843.2463779-4-seanga2@gmail.com
2024-01-29 22:35:02 -05:00
Sean Anderson
c9309f40a6 treewide: Remove clk_free
This function is a no-op. Remove it.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Link: https://lore.kernel.org/r/20231216193843.2463779-3-seanga2@gmail.com
2024-01-29 22:35:02 -05:00
Sean Anderson
82719d3f40 clk: Remove rfree
Nothing uses this function. Remove it. Since clk_free no longer does
anything, just stub it out.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Link: https://lore.kernel.org/r/20231216193843.2463779-2-seanga2@gmail.com
2024-01-29 22:35:02 -05:00
Julien Masson
b500447ad6 clk: fix clk_get_rate() always return ulong
When we call clk_get_rate(), we expect to get clock rate value as
ulong.
In that case we should not use log_ret() macro since it use internally
an int.
Otherwise we may return an invalid/truncated clock rate value.

Signed-off-by: Julien Masson <jmasson@baylibre.com>
Fixes: 5c5992cb90 ("clk: Add debugging for return values")
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Link: https://lore.kernel.org/r/87o7erv9p4.fsf@baylibre.com
2024-01-29 22:34:52 -05:00
Neil Armstrong
2da1331d20 clk: meson: add Hardware Clock measure driver
Amlogic SoCs embeds an hardware clock measure block, port it
from Linux and implement it as a UCLK_CLK with only the dump
op and fail-only xlate.

Based on the Linux driver introduced in [1].

[1] commit 2b45ebef39a2 ("soc: amlogic: Add Meson Clock Measure driver").

Reviewed-by: Sean Anderson <seanga2@gmail.com>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20231218-uboot-meson-clk-msr-v3-1-acf4d90ccfee@linaro.org
2024-01-29 22:34:39 -05:00
Tom Rini
6faba41927 Prepare v2024.04-rc1
Signed-off-by: Tom Rini <trini@konsulko.com>
2024-01-29 20:53:19 -05:00
Tom Rini
d5c0c990c3 Merge tag 'efi-2024-04-rc1-4' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request efi-2024-04-rc1-4

Documentation:

* uefi: remove ".py" suffix for pytest.py command
* correct date in migration plan for CONFIG_DM

UEFI:

* fix conflicting SPDX license in RISC-V EFI linker scripts
* page align EFI binary section in RISC-V EFI binaries
* separate .data and .text sections of RISC-V EFI binaries
* use common function to get EFI configuration table
2024-01-29 16:19:10 -05:00
Quentin Schulz
341e8a6c7c tools: buildman: fix non-existing SafeConfigParser in Python 3.12+
SafeConfigParser was renamed back in Python 3.2 (yes, no typo) to
ConfigParser[1], but it was still working as an alias until it got
removed in 3.12[2].

[1] https://docs.python.org/3.8/whatsnew/3.2.html#configparser
[2] https://github.com/python/cpython/pull/92503

Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
2024-01-29 14:54:15 -05:00
Janne Grunau
24adbee344 video: console: Fix buffer overflow in cmd 'font list'
vidconsole_ops.get_font is documented to return -ENOENT after the last
video_fontdata entry.

Signed-off-by: Janne Grunau <j@jannau.net>
2024-01-29 14:53:11 -05:00
Janne Grunau
3883c9add0 video: Support VIDEO_X2R10G10B10 in truetype console
Without explicit support for VIDEO_X2R10G10B10 VIDEO_X8R8G8B8 white
will be rendered as cyan-ish. The conversion leaves to lowest 2 bits
unset for more compact code.

Signed-off-by: Janne Grunau <j@jannau.net>
2024-01-29 14:53:06 -05:00
Ralph Siemsen
04add62e8c env: sf: report malloc error to caller
In the non-redundant code for env_sf_save(), a failure to malloc() the
temporary buffer produces the following output:

    Saving Environment to SPIFlash... OK

This is misleading as the flash has neither been erased nor written.

Fix it to return an error to the caller, so the output will be:

    Saving Environment to SPIFlash... Failed (-12)

Note that there is another copy of env_sf_save() in the same file, for
handling redundant environment, and it already has the same logic.

Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
2024-01-29 14:52:23 -05:00
Devarsh Thakkar
ca6d60df2f video: tidss: Use DT property names for parsing nodes
Use device-tree node property names for parsing nodes instead of
indexing as indexing could be different between different SoCs based on
number of DSS entities available on that particular SoC.

Also correct the video layer naming in driver to match to actual one
being used in upstream DSS device-tree node [1].

This also fixes AM62x splash screen usage using the latest upstream DSS
device-tree nodes where hard-coded indexing which driver was using
before this patch was not matching the correct properties in the DT
node.

[1]: Upstream AM62x DSS node:
https://github.com/torvalds/linux/blob/v6.8-rc1/arch/arm64/boot/dts/ti/k3-am62-main.dtsi#L774

Fixes: 5f9f816bb8 ("drivers: video: tidss: TIDSS video driver support for AM62x")
Signed-off-by: Devarsh Thakkar <devarsht@ti.com>
Reviewed-by: Nikhil M Jain <n-jain1@ti.com>
2024-01-29 14:50:15 -05:00
Devarsh Thakkar
54245af0ae common: splash_source: Don't compile ubifs splash cmd for SPL build
Don't compile ubifs splash mount command for SPL build as this command
is not supported (and also not enabled) during SPL stage.

This fixes below compilation error, when CONFIG_CMD_UBIFS is enabled in
defconfig along with splash screen enabled at SPL stage:

"aarch64-none-linux-gnu-ld.bfd: common/cli.o: in function `run_command':
u-boot-next/u-boot/common/cli.c:51: undefined reference to
`parse_string_outer'
u-boot-next/u-boot/common/cli.c:51:(.text.run_command+0x10): relocation
truncated to fit: R_AARCH64_JUMP26 against undefined symbol
`parse_string_outer' make[2]: ***
[u-boot-next/u-boot/scripts/Makefile.spl:527: spl/u-boot-spl] Error 1
make[1]: *** [u-boot-next/u-boot/Makefile:2053: spl/u-boot-spl] Error 2
make[1]: Leaving directory 'u-boot-next/u-boot/out/a53' make: ***
[Makefile:177: sub-make] Error 2"

Fixes: eb9217dc03 ("common: Enable splash functions at SPL")
Signed-off-by: Devarsh Thakkar <devarsht@ti.com>
Reviewed-by: Nikhil M Jain <n-jain1@ti.com>
2024-01-29 14:50:05 -05:00
Tom Rini
073f4f10b9 Merge patch series "Move framebuffer reservation for SPL to RAM end"
Devarsh Thakkar <devarsht@ti.com> says:

Move video memory reservation for SPL at end of RAM so that it does
not interefere with reservations for next stage so that the next stage
need not have holes in between for passed regions and instead it can
maintain continuity in reservations.

Also catch the bloblist before starting reservations to avoid the same
problem.

While at it, also fill missing fields in video handoff struct before
passing it to next stage.

This is as per discussions at :
For moving SPL framebuffer reservation at end of RAM:

https://lore.kernel.org/all/CAPnjgZ3xSoe_G3yrqwuAvoiVjUfZ+YQgkOR0ZTVXGT9VK8TwJg@mail.gmail.com/

For filling missing video handoff fields :
https://lore.kernel.org/all/CAPnjgZ1Hs0rNf0JDirp6YPsOQ5=QqQSP9g9qRwLoOASUV8a4cw@mail.gmail.com/
2024-01-29 14:49:25 -05:00
Devarsh Thakkar
aaeb330cac doc: spl: Add info regarding memory reservation
Add details regarding scheme which need to be followed in SPL and
further stages for those regions which need to be preserved across
bootstages.

Signed-off-by: Devarsh Thakkar <devarsht@ti.com>
Reviewed-by: Simon Glass <sjg@chromium>
2024-01-29 14:49:17 -05:00
Devarsh Thakkar
b557e9f06e doc: spl: Add info for missing Kconfigs
Add info regarding splash screen, video, bloblist and GPIO related
Kconfigs which were missing in the documentation.

Signed-off-by: Devarsh Thakkar <devarsht@ti.com>
Reviewed-by: Simon Glass <sjg@chromium>
2024-01-29 14:49:17 -05:00
Devarsh Thakkar
b30414f089 video: Fill video handoff in video post probe
Fill video handoff fields in video_post_probe as at this point we have
full framebuffer-related information.

Also fill all the fields available in video hand-off struct as those
were missing earlier and U-boot framework expects them to be filled for
some of the functionalities.

While filling framebuffer size in video hand-off structure use the
actual framebuffer region size as derived from gd->video_top and
gd->video_bottom instead of directly using the size populated in
video_uc_plat as it contains unaligned size.

Reported-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Devarsh Thakkar <devarsht@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2024-01-29 14:49:17 -05:00
Devarsh Thakkar
eefe23c127 video: Skip framebuffer reservation if already reserved
Skip framebufer reservation if it was already reserved from previous
stage and whose information was passed using a bloblist.

Return error in case framebuffer information received from bloblist is
invalid i.e NULL or empty.

While at it, improve the debug message to make it more clear that
address in discussion is of framebuffer and not bloblist and also match
it with printing scheme followed in video_reserve function.

Signed-off-by: Devarsh Thakkar <devarsht@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2024-01-29 14:49:17 -05:00
Devarsh Thakkar
4ef9c77248 common/board_f: Catch bloblist before starting reservations
Start reservations needed for init sequence only after catching
bloblists from previous stage.

This is to avoid catching bloblists in the middle causing gaps while
u-boot is reserving.

Adjust the relocaddr as per video hand-off information received from
previous stage so that further reservations start only after regions
reserved for previous stages

Skip reservation for video memory if it was already filled by a
bloblist.

Signed-off-by: Devarsh Thakkar <devarsht@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2024-01-29 14:49:17 -05:00
Devarsh Thakkar
945053fd64 board: ti: am62x: evm: Remove video_setup from spl_board_init
Remove video_setup from evm_init sequence since video memory is getting
called at an earlier place to make sure video memory is reserved at
the end of RAM.

Suggested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Devarsh Thakkar <devarsht@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2024-01-29 14:49:17 -05:00
Devarsh Thakkar
ba20b2443c arm: mach-k3: common: Reserve video memory from end of the RAM
Setup video memory before page table reservation using
"spl_reserve_video_from_ram_top" which ensures framebuffer memory gets
reserved from the end of RAM.

This is done to enable the next stage to directly skip the
pre-reserved area from previous stage right from the end of RAM without
having to make any gaps/holes to accommodate those regions which was the
case before as previous stage reserved region not from the end of RAM.

Use gd->ram_top instead of local ram_top and update gd->reloc_addr after
each reservation to ensure further regions are reserved properly.

Signed-off-by: Devarsh Thakkar <devarsht@ti.com>
Reviewed-by: Nikhil M Jain <n-jain1@ti.com>
2024-01-29 14:49:17 -05:00
Devarsh Thakkar
1d3c266758 spl: Enforce framebuffer reservation from end of RAM
Add an API which enforces framebuffer reservation from end of RAM.
This is done so that next stage can directly skip this region before
carrying out further reservations.

Signed-off-by: Devarsh Thakkar <devarsht@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2024-01-29 14:49:17 -05:00
Tom Rini
7af90646df board/sunxi/MAINTAINERS: Add new defconfigs
Add entries for the recently added defconfig files. I had thought I had
committed these updates but lost them before pushing the branch.

Signed-off-by: Tom Rini <trini@konsulko.com>
2024-01-29 13:49:29 -05:00
Tom Rini
8986be59e7 Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-spi
- Support Infineon S28HS02GT (Takahiro)
2024-01-29 12:58:42 -05:00
Tom Rini
41a737bb85 Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi
- Some cleanups in header files: those do not affect the generated
  binaries at all.
- The usual update of DT files from the kernel repo, mostly adding new
  board files this time. On the wake of this there is one defconfig to
  enable a new board, some H618 TV box branded as "Transpeed".
- Samuel's series to support SPL FIT image loading for 32-bit SoCs as
  well, so far this was restricted to ARM64 boards. I refrained from
  automatically enabling this everywhere, instead this requires user
  intervention during board configuration. This allows to ship the
  "crust" management processor firmware on H3 boards, which enables
  better power saving.
- One defconfig for an older H3 board. There was a close-by defconfig
  for a related board, but there are some differences which deserve a
  separate file.
- Support for the EMAC driver to work with fixed-link PHYs, which allows
  to directly wire the MAC to a switch IC.
2024-01-29 12:50:34 -05:00
Tom Rini
ce54325c42 Merge branch '2024-01-29-pytest-enhancements'
- Update pygit2 version and add a number of additional hardware pytests
2024-01-29 12:50:34 -05:00
Love Kumar
e24e5405d2 test/py: scsi: Add test for scsi commands
Add a following test cases for scsi commands:
scsi_reset - To reset SCSI controller
scsi_info - To show available SCSI devices
scsi_scan - To (re-)scan SCSI bus
scsi_device - To show or set surrent device
scsi_part - To print partition table of selected SCSI device

Signed-off-by: Love Kumar <love.kumar@amd.com>
2024-01-29 12:50:34 -05:00
Love Kumar
1c5b6edad3 test/py: usb: Add tests for USB device
Add the test cases for usb commands to test its various functionality
such as start, stop, reset, info, tree, storage, dev, part, ls, load,
and save. It also adds different file systems cases such as fat32, ext2
and ext4.

Signed-off-by: Love Kumar <love.kumar@amd.com>
2024-01-29 10:31:24 -05:00
Love Kumar
6c509cab6a test/py: mmc: Add tests for MMC device
Add the test cases for mmc commands to test its various functionality
such as mmc list, dev, info, rescan, part, ls, load, and save. It also
adds different file systems cases such as fat32, ext2 and ext4.

Signed-off-by: Love Kumar <love.kumar@amd.com>
2024-01-29 10:31:24 -05:00
Love Kumar
a0d9432c4d test/py: secure: Add secure tests for Zynq & ZynqMP
Add test cases to verify the different type of secure boot images loaded
at DDR location for AMD's ZynqMP SoC. It also adds tests authentication
and decryption functionality using AES and RSA features for Zynq.

Signed-off-by: Love Kumar <love.kumar@amd.com>
2024-01-29 10:31:24 -05:00
Love Kumar
d07f9e6661 test/py: gpio: Add gpio pins generic test
Add gpio pins generic test for the set of gpio pin list to test various
gpio related functionality, such as the input, set, clear, and toggle,
it also tests the input and output functionality for shorted gpio pins.
This test depends on boardenv* configuration to define gpio pins names.

Signed-off-by: Love Kumar <love.kumar@amd.com>
2024-01-29 10:31:24 -05:00
Love Kumar
e894c10c04 test/py: zynqmp_rpu: Add test for loading RPU apps
Add testcases for loading RPU applications in split and lockstep mode
including the negative one for AMD's ZynqMP SoC.

Signed-off-by: Love Kumar <love.kumar@amd.com>
2024-01-29 10:31:24 -05:00
Caleb Connolly
274e9acff4 pytest: update requirements.txt
Update pygit2 and py to their latest versions. Even in the venv pygit2
still links against the system libgit2 library which is failing on
latest Arch Linux.

The py library also needs updating to fix a KeyNotFound exception during
test initialisation.

Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-01-29 10:31:23 -05:00
Samuel Holland
539612e276 sunxi: Consider SPL size limitations for FIT loading
Now that 32-bit SoCs can load U-Boot proper (and possibly other firmware)
from a FIT, people can use that by enabling CONFIG_SPL_LOAD_FIT.
However SPL_FIT_IMAGE_TINY is required to stay within the 24 or 32 KiB
SPL size limit on early SoCs; for consistency, enable it everywhere.

Signed-off-by: Samuel Holland <samuel@sholland.org>
[Andre: drop unconditional FIT image enablement for all SoCs]
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2024-01-29 14:31:00 +00:00
Samuel Holland
4a8592eeab sunxi: binman: Support FIT generation for 32-bit SoCs
Some 32-bit SoCs can use SCP firmware to implement additional PSCI
functionality, such as system suspend. In order to load this firmware
from SPL, we need to generate and use a FIT instead of a legacy image.

Adjust the binman FIT definition so it does not rely on TF-A BL31, as
this is not used on 32-bit SoCs. Instead, after loading the firmware,
U-Boot proper is executed directly. This requires to provide an
entry point property for the U-Boot image node, which confuses some
loaders like sunxi-fel, so protect that to only be used if we have no
BL31.

Signed-off-by: Samuel Holland <samuel@sholland.org>
[Andre: filter U-Boot entry point property]
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2024-01-29 14:31:00 +00:00
Samuel Holland
53c0ad5d27 sunxi: binman: Move BL31 and SCP firmware addresses to Kconfig
This is easier to read than the #ifdef staircase, provides better
visibility into the memory map (alongside the other Kconfig
definitions), and allows these addresses to be reused from code.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2024-01-29 14:30:59 +00:00
Samuel Holland
d72494a064 sunxi: spl: Disable padding from SPL_PAD_TO
Starting with H6, Allwinner removed the artificial 32 KiB SPL size limit
from the boot ROM. Now SPL size is only limited by the available SRAM.
This limit ranges from 152 KiB on H6 to a whopping 2052 KiB on R329. To
take advantage of this additional space, we must increase SPL_MAX_SIZE.
Since we do not want to unnecessarily pad SPL out to these giant sizes,
we must set SPL_PAD_TO to zero. This causes no problems because binman
already takes care of appending the SPL payload at the right offset.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2024-01-29 14:30:59 +00:00
Chuanhong Guo
57b6eb9005 sunxi: add defconfig for nanopi_duo2
FriendlyElec NanoPi Duo2 is a tiny SBC with Allwinner H3 and
Ampak AP6212 WiFi module. The device-tree for it is already
available in u-boot source tree. Add a default config for it.

Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
[Andre: enable USB gadgets]
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2024-01-29 14:30:59 +00:00
Maksim Kiselev
2bfab76f4c net: sun8i-emac: Add support for fixed-link phy
Make the "phy-handle" property optional, which allows support
for a fixed-link phy configuration.

Thus if the "phy-handle" is present in a DT, then driver will work as
before. Otherwise, phyaddr initialization will not be necessary,
as it is not needed in case of a fixed-link config.

Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2024-01-29 14:30:59 +00:00
Nick Alilovic
1cca1011cb sunxi: add Transpeed 8K618-T board support
This is a Chinese TV box based on Allwinner H618 SoC.

The DRAM parameters were derived from the values found in a firmware update.

Signed-off-by: Nick Alilovic <nickalilovic@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2024-01-29 14:30:59 +00:00
Andre Przywara
60bb9aa51c sunxi: dts: update devicetree files from Linux-v6.8-rc1
Sync the devicetree files from the official Linux kernel tree, v6.8-rc1.
This time only small changes in the existing files, but five new boards
got added, which opens the door for their respective defconfig files.

As before, this omits the non-backwards compatible changes to the R_INTC
controller, to remain compatible with older kernels.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2024-01-29 14:30:59 +00:00
Takahiro Kuwano
16dd109510 mtd: spi-nor-ids: Add Infineon(Cypress) s28hs02gt ID
Infineon(Cypress) S28HS02GT is 1.8V, 2Gb (256MB) NOR Flash memory with
Octal interface. It is a dual-die package parts and has same features
with existing S28 series.

Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2024-01-29 19:34:17 +05:30
Takahiro Kuwano
e70ac28870 mtd: spi-nor-core: Rework spi_nor_cypress_octal_dtr_enable()
Enabling Octal DTR mode in multi-die package parts requires reister setup
for each die. That can be done by simple for-loop. write_enable() takes
effect to all die at once so we can call it before the loop. Besides we
can replace spi_mem_exec_op() calls with spansion_read/write_any_reg().
And finally, we must mask CFR2V[7:4] when changing dummy cycles, as
CFR2V[7] indicates current addressing mode and that should be 1 (4-byte
address mode) for multi-die package parts.

Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2024-01-29 19:34:17 +05:30
Takahiro Kuwano
d386fa8b0d mtd: spi-nor-core: Consolidate post_bfpt_fixup() for Infineon(Cypress) S25 and S28
s28hx_t_post_bfpt_fixup() fixes erase opcode, erase size, and page size.
s25_post_bfpt_fixup() is doing same thing including multi-die support.
We can consolidate s28hx_t_post_bfpt_fixup() and s25_post_bfpt_fixup()
into one named s25_s28_post_bfpt_fixup().

In s25_s28_post_bfpt_fixup(), set_4byte() is called to force the device to
be 4-byte addressing mode. In S28HS02GT datasheet, the B7 opcode is missing
but it works actually (confirmed).

Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2024-01-29 19:34:17 +05:30
Takahiro Kuwano
33934e11d4 mtd: spi-nor-core: Consolidate setup() hook for Infineon(Cypress) S25 and S28
s28hx_t_setup() only checks sector layout setting. To support multi-die
package parts like S28HS02GT, it needs to check device size and assign
ready() hook for multi-die package parts. These are covered in s25_setup()
so we can consolidate s28hx_t_setup() and s25_setup() into one named
s25_s28_setup().

spi_nor_wait_till_ready() at the beginning of s28hx_t_setup() can be
removed since there is no op that makes device busy state before setup.

Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2024-01-29 19:34:17 +05:30
Takahiro Kuwano
c4de92d949 mtd: spi-nor-core: Rework s25_mdp_ready() to support Octal DTR mode
s25_mdp_ready() handles status polling for multi-die package parts that
requires to read and check status register for each die. To support
S28HS02GT(dual-die package with Octal DTR support), rename function and
use nor->rdsr_dummy in octal DTR mode.

Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2024-01-29 19:34:17 +05:30
Takahiro Kuwano
9901312e09 mtd: spi-nor-core: Use CLPEF(0x82) as alternative to CLSR(0x30) for S25 and S28
Infineon(Cypress) S28Hx-T family does not support legacy CLSR(0x30) opcode.
Instead, it supports CLPEF(0x82) which has the same functionality as CLSR.
spansion_sr_ready() is for multi-die package parts including S28HS02GT, so
we need to use CLPEF instead of CLSR.

This change does not affect to S25x02GT which uses spansion_sr_ready() as
S25Hx-T family also supports CLPEF(0x82) as well as CLSR(0x30).

Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2024-01-29 19:34:17 +05:30
Takahiro Kuwano
9768d7c7ec mtd: spi-nor-core: Rework spansion_read_any_reg() to support Octal DTR mode
In Infineon multi-die package parts, we need to use Read Any Register op
to read status register in 2nd or further die. Infineon S28HS02GT is
dual-die package and supports Octal DTR interface. To support this,
spansion_read_any_reg() needs to be reworked. Implementation is similar
to existing read_sr() that already supports Octal DTR mode.

Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2024-01-29 19:34:17 +05:30
Takahiro Kuwano
a3a5cc7613 mtd: spi-nor-core: Consolidate non-uniform erase helpers for S25 and S28
s25_erase_non_uniform() and s28hx_t_erase_uniform() support hybrid sector
layout (32 x 4KB sectors overlaid at bottom address) and doing same thing.
Consolidate them into single helper named s25_s28_erase_non_uniform().

Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2024-01-29 19:34:17 +05:30
Takahiro Kuwano
7a67bc55b9 mtd: spi-nor-core: Clean up macros for Infineon(Cypress) S25 and S28
Some macro definitions used in Infineon(Cypress) S25 and S28 series are
redundant and some have inconsistent prefix. This patch removes
redundant ones and renames some to have same prefix as others.

Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2024-01-29 19:34:17 +05:30
Ssunk
f07ca7907e mtd: spi: spi-nor-ids: Add more XM25Q series chips
- XM25QH128C
- XM25QH256C
- XM25QU256C
- XM25QH512C
- XM25QU512C

Signed-off-by: Kankan Sun <ssunkkan@gmail.com>
[jagan: update the commit message]
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2024-01-29 19:34:17 +05:30
Tejas Bhumkar
b4b0228db8 spi: cadence_qspi: Address the comparison failure for 0-8 bytes of data
The current implementation encounters issues when testing data ranging
from 0 to 8 bytes. This was confirmed through testing with both ISSI
(IS25WX256) and Micron (MT35XU02G) Flash exclusively in SDR mode.

Upon investigation, it was observed that utilizing the
"SPI_NOR_OCTAL_READ" flag and attempting to read less than 8 bytes in
STIG mode results in a read failure, leading to a compare test failure.

To resolve this issue, the CMD_4BYTE_FAST_READ opcode is now utilized
instead of CMD_4BYTE_OCTAL_READ, specifically in SDR mode.

This is based on patch series:
https://lore.kernel.org/all/cover.1701853668.git.tejas.arvind.bhumkar@amd.com/

Signed-off-by: Tejas Bhumkar <tejas.arvind.bhumkar@amd.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2024-01-29 19:34:17 +05:30
Tejas Bhumkar
18e61f2378 mtd: spi-nor-ids: Add is25lx512 chip
Added support for the ISSI OSPI flash part IS25LX512M.
Initial testing was performed on the Tenzing-se1 board using
SDR mode, covering basic erase, write, and readback operations.

Signed-off-by: Tejas Bhumkar <tejas.arvind.bhumkar@amd.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2024-01-29 19:34:17 +05:30
Maksim Kiselev
26bb23b0bd spi: dw: add check for Rx FIFO overflow
If even one byte is lost due to Rx FIFO overflow then we will never
exit the read loop. Because the (priv->rx != priv->rx_end) condition will
be always true.

Let's check if Rx FIFO overflow occurred and exit the read loop
in this case.

Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2024-01-29 17:18:12 +05:30
Masahisa Kojima
21489b4478 efi_loader: check efi_get_variable_int return value
efi_get_variable_int() may fail, the buffer should be
cleared before using it.

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Addresses-Coverity-ID: 478333 ("Error handling issues")
2024-01-29 11:31:44 +01:00
Heinrich Schuchardt
796469c453 efi_loader: replace find_smbios_table by library function
The code in find_smbios_table() is redundant to
efi_get_configuration_table(). Replace it.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-01-29 11:31:28 +01:00
Heinrich Schuchardt
102ab672d3 cmd: in do_efi_capsule_esrt use efi_get_configuration_table
Use library function efi_get_configuration_table() to find the ESRT.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-01-29 11:31:06 +01:00
Heinrich Schuchardt
fa0772180e efi_loader: export efi_get_configuration_table
In multiple places we need a function to find an EFI configuration table.
Rename get_config_table() to efi_get_configuration_table() and export it.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-01-29 11:31:06 +01:00
Wei Ming Chen
3a99d05a39 doc: uefi: remove ".py" suffix for pytest.py command
the file pytest.py does not exist

Signed-off-by: Wei Ming Chen <jj251510319013@gmail.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-01-29 11:30:28 +01:00
Heinrich Schuchardt
3e911b7419 riscv: separate .data and .text sections of EFI binaries
EFI binaries should not contain sections that are both writable and
executable. Separate the RX .text section from the RW .data section

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-01-29 11:30:10 +01:00
Heinrich Schuchardt
a5c3c1ba8a riscv: page align EFI binary section
Change the alignment of the relocation code in EFI binaries to match page
boundaries.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-01-29 11:29:52 +01:00
Heinrich Schuchardt
396daa7497 riscv: conflicting SPDX license linker scripts
Fix conflicting SPDX license information in linker scripts introduced by
commit 7215787c4e ("SPDX: Convert single license tags to Linux Kernel
style").

Fixes: 7215787c4e ("SPDX: Convert single license tags to Linux Kernel style")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2024-01-29 11:29:52 +01:00
Heinrich Schuchardt
59a2866bd7 efi_selftest: add missing line feed in efi_selftest_miniapp_exit
If an error occurs we may see an output like:

    EFI application calling Exit

    Could not open loaded image protocolLoaded image protocol missing

Add the missing line feed.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-01-29 11:29:19 +01:00
Alexander Dahl
ea773cf291 doc: dm: Fix typo
That's most probably a typo, because driver model design documents seem
to be from 2012 and there is no 2010.01 release.

Fixes: 282ed24fb3 ("dm: MIGRATION: Add migration plan for CONFIG_DM")
Signed-off-by: Alexander Dahl <ada@thorsis.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-01-29 11:28:44 +01:00
Andre Przywara
5375fb1d50 sunxi: simplify U-Boot proper only builds
At the moment every Allwinner board builds and requires an SPL, even
though we select this individually in each _defconfig file.
For experiments and for early bringup of new SoCs it would be beneficial
to only build U-Boot proper, for instance to postpone a tedious SPL port
(including DRAM support) in the initial phase.

Protect some SPL related symbols that we unconditionally select at the
moment with "if SPL", to avoid Kconfig conflicts when CONFIG_SPL is
disabled.

This alone does not cleanly build U-Boot proper only yet, but gets it
far enough so that the binary can be harvested.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2024-01-29 01:18:52 +00:00
Andre Przywara
d785a06a5a sunxi: remove common.h inclusion
The usage of the common.h include file is deprecated, and has already
been removed from several files.

Get rid of all inclusions in the arch/arm/mach-sunxi directory. Most
files actually don't need the header at all, for the few others just
include the headers that we actually require.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2024-01-29 01:18:52 +00:00
Andre Przywara
5862eb8b85 sunxi: sun9i: remove unneeded base addresses from header
The cpu_sun9i.h header file defined the base addresses for quite some
peripherals of the Allwinner A80 CPU, even though we now only use a
fraction of that.
Most of the addresses are now either read from the DT, or were never
used in U-Boot in the first place.

Removed the ones that are not used in the whole of the U-Boot source.
to make it clear that this file only contains addresses that are needed
for the SPL operation.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2024-01-29 01:18:52 +00:00
Andre Przywara
2f2cb03b6f sunxi: sun4i: remove unneeded base addresses from header
The cpu_sun4i.h header file defined the base addresses for quite some
peripherals of earlier Allwinner CPUs, even though we now only use a
fraction of that.
Most of the addresses are now either read from the DT, or were never
used in U-Boot in the first place.

Removed the ones that are not used in the whole of the U-Boot source.
to make it clear that this file only contains addresses that are needed
for the SPL operation.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2024-01-29 01:18:52 +00:00
Andre Przywara
4c5f03ef3f sunxi: sun50i-h6: remove unneeded base addresses from header
The cpu_sun50i_h6.h header file defined the base addresses for quite some
peripherals of the Allwinner H6 and related CPUs, even though we now only
use a fraction of that.
Most of the addresses are now either read from the DT, or were never used
in U-Boot in the first place.

Removed the ones that are not used in the whole of the U-Boot source.
to make it clear that this file only contains addresses that are needed
for the SPL operation.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2024-01-29 01:18:52 +00:00
Andre Przywara
1ebb9ef288 sunxi: cleanup sunxi-common.h
The sunxi-common.h configs header used to contain a lot of random
Allwinner platform related constants, but over the years we moved a lot
of those definitions out there.

Clean up the file to remove outdated comments which are leftovers from
the olden days. Also remove the definition of LOW_LEVEL_SRAM_STACK,
which is actually used nowhere in the whole source tree.

This also uses the opportunity to add some section comments that helps
structuring the header file and improving readability.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2024-01-29 01:18:51 +00:00
Tom Rini
526a865fe4 Merge branch 'master-cleanup' of https://source.denx.de/u-boot/custodians/u-boot-sh
- Assorted code clean-ups
2024-01-27 20:43:20 -05:00
Marek Vasut
8a725c6106 ARM: renesas: whitehawk: Drop extra leading space
Drop leading space in front of a comment. No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
2024-01-27 20:17:04 +01:00
Marek Vasut
e12337915c ARM: renesas: Drop include common.h
The header file is not necessary in either of those files,
remove it as common.h is going away.

Include missing asm/arch/rmobile.h in board/renesas/rcar-common/v3-common.c
to prevent build failure of r8a77970_eagle r8a779a0_falcon r8a77980_v3hsk
and r8a77970_v3msk .

Include missing asm/u-boot.h in falcon.c and grpeach.c to fix build failure
due to missing definition of struct bd_info . Include errno.h in grpeach.c
to fix build error due to missing definition of EINVAL.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
2024-01-27 20:16:39 +01:00
Marek Vasut
b90862d2f4 pinctrl: renesas: Drop include common.h
The header file is not necessary in either of those files,
remove it as common.h is going away.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
2024-01-27 20:16:39 +01:00
Marek Vasut
402786c494 clk: renesas: Drop include common.h
The header file is not necessary in either of those files,
remove it as common.h is going away.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
2024-01-27 20:16:39 +01:00
Tom Rini
fb5fe1bf84 Merge tag 'smbios-2024-04-rc1-2' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request smbios-2024-04-rc1-2

* Add missing field to SMBIOS type 2 structure definition
* Provide smbios command to display smbios table
* Enable the command on sandbox and qemu_arm64_defconfig
* Provide a python test for the smbios command
* Fix copying SMBIOS 2.1 table from QEMU
* Correct EFI TCG measurement to assume SMBIOS 3 table
2024-01-27 07:53:29 -05:00
Heinrich Schuchardt
91cc06bcab lib: support SMBIOS3 table in uuid_guid_get_str()
As we support installing SMBIOS3 tables in U-Boot we need to add this GUID
to the translation table used buy uuid_guid_get_str().

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
2024-01-26 14:17:55 +01:00
Masahisa Kojima
b92d0f78dc smbios: use struct_table_length to get SMBIOS 2.1 total table length
The current code convert the SMBIOS 2.1 entry point structure to
SMBIOS 3.0 entry point structure. The max_struct_size member in
SMBIOS 2.1 entry point structure indicates
"Size of the largest SMBIOS structure, in bytes".
We need to use struct_table_length instead.

Fixes: 1c5aab803c ("smbios: copy QEMU tables")
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2024-01-26 14:16:46 +01:00
Masahisa Kojima
2497f6a84c efi_loader: migrate SMBIOS 3.0 entry point structure for measurement
Current U-Boot only supports the SMBIOS 3.0 entry point structure.
TCG2 measurement code should migrate to SMBIOS 3.0 entry
point structure.

efi_selftest tcg2 test also needs to be updated, and expected
PCR[1] result is changed since guid for SMBIOS EFI system table
uses different guid SMBIOS3_TABLE_GUID instead of SMBIOS_TABLE_GUID.

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-01-26 14:16:17 +01:00
Heinrich Schuchardt
d4f721bc14 configs: enable smbios command on qemu_arm64_defconfig
We have a Python test the copying of SMBIOS tables from QEMU.
To make use of the test we need the smbios command.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-01-26 14:15:08 +01:00
Heinrich Schuchardt
c5380d7697 configs: enable smbios command on sandbox
To make use of the Python smbios test we need the smbios command.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-01-26 14:15:08 +01:00
Heinrich Schuchardt
b07d98afdf test: unit test for smbios command
Provide a unit test for the smbios command.

Provide different test functions for QEMU, sandbox, and other systems.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-01-26 14:15:08 +01:00
Heinrich Schuchardt
a7e81ff6ee doc: man-page for smbios command
Provide a man-page for the smbios command.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-01-26 14:15:08 +01:00
Heinrich Schuchardt
9de4ec81c9 cmd: provide command to display SMBIOS information
U-Boot can either generated an SMBIOS table or copy it from a prior boot
stage, e.g. QEMU.

Provide a command to display the SMBIOS information.

Currently only type 1 and 2 are translated to human readable text.
Other types may be added later. Currently only a hexdump and the list of
strings is provided for these.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-01-26 14:15:08 +01:00
Heinrich Schuchardt
a5866c3c99 smbios: type2: contained object handles
The type 2 structure must include information about the contained objects.
It is fine to set the number of contained object handles to 0.

Add the missing field.

Fixes: 721e992a8a ("x86: Add SMBIOS table support")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-01-26 14:15:08 +01:00
Tom Rini
e7f9e5eb58 Merge branch '2024-01-24-assorted-fixes-and-updates'
- Increase SYS_MAXARGS default, verdin-am62 improvements (and required
  cleanup), assorted cleanups throughout the code base.
2024-01-25 11:01:38 -05:00
Yang Xiwen
53c3e38606 reset: reset-hisilicon: also handle #reset-cells = <2>
It's also valid to have #reset-cells = <2> while the third arg defaults
to ASSERT_SET.

Signed-off-by: Yang Xiwen <forbidden405@outlook.com>
2024-01-24 16:17:14 -05:00
Heinrich Schuchardt
aeba385e41 test: enhance unicode_test_utf8_to_utf32_stream()
Additionally test a UTF-8 string where each code point translates to three
UTF-8 bytes.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-01-24 16:17:14 -05:00
Heinrich Schuchardt
3150da34c2 lib: add comment in utf8_to_utf32_stream()
The logic of utf8_to_utf32_stream() is not easy to understand.
Add a comment.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-01-24 16:17:14 -05:00
Tom Rini
3d878b83d0 docker: Add tools/buildman/requirements.txt to the cache
As we have had this file for a while now, we should include installing
and populating our pip cache from here as well.

Signed-off-by: Tom Rini <trini@konsulko.com>
2024-01-24 16:17:14 -05:00
Patrice Chotard
9152a51e3c common: console: Fix print complete stdio device list
In case CONSOLE_MUX and SYS_CONSOLE_IS_IN_ENV are on and
stdin or stdout or stderr are missing in environment, as fallback, get
these either from stdio_devices[std] or stdio_devices[std]->name.

Fixes: 6b343ab38d ("console: Print out complete stdio device list")

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-01-24 11:12:11 -05:00
Svyatoslav Ryhel
983d6e5bf0 cmd: bootmenu: rename U-Boot console to Exit
It seems that the U-Boot console entry of the bootmenu has lost
its original meaning. Now, even if it is chosen, the probability
that you will enter the actual U-Boot console is quite low.
Boot env, bootflow, bootcommand script may appear, but not the
actual console. Hence, let's remove ambiguity and name this
entry by what it actually does: 'Exit' the bootmenu.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2024-01-24 11:12:11 -05:00
Max Krummenacher
d2099587d6 board: verdin-am62: set cpu core voltage depending on speed grade
Speed grade T requires the VDD_CORE voltage to be 0.85V if using
the maximum core frequency.

Speed grades G, K, S allow the VDD_CORE voltage to be 0.75V up to the
maximum core frequency but allow to run at 0.85V.

For efficiency in manufacturing and code maintenance we use 0.85V for
the PMIC defaults and device tree settings and dynamically adjust the
voltage in the PMIC and device tree to 0.75V for lower speed SKU to
gain more than 100mW power consumption reduction.

Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
2024-01-24 11:12:11 -05:00
Max Krummenacher
00812e2257 arm: mach-k3: am62: provide more soc feature info accessors
Add two functions, one which returns the SoC speed grade and one
which returns the SoC operating temperature range.

Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
2024-01-24 11:12:11 -05:00
Max Krummenacher
9c68b0427c arm: mach-k3: am62: move device identification accessor functions to header
mach-k3/am625_fdt.c does fdt fixup depending on fields in the device
identification register. Move the accessors to the device identification
register as inline functions into the am62_hardware.h header, so that
they can be used for other functionality.

Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
2024-01-24 11:12:11 -05:00
Max Krummenacher
a1f466a940 board: verdin-am62: improve comment on usb phy core voltage
TI recommends to clear the bit independent of the used voltage.
So the comment which claims to do it due to the core voltage
at 0.85V is bogus.

See https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1252724/am625-usb-phy-core-voltage-selection-and-vdda_core_usb-mismatch

Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
2024-01-24 11:12:11 -05:00
Max Krummenacher
e2e69291ee headers: don't depend on errno.h being available
These headers follow the pattern:

| #if CONFIG_IS_ENABLED(FANCY_FEATURE)
|   void foo(void);
| #else
|   static inline void foo(void) { return -ENOSYS; }
| #endif

In the #else path ENOSYS is used, however linux/errno.h is not included.
If errno.h has not been included already the compiler errors out even
if the inline function is not referenced.

Make those headers self contained.

Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2024-01-24 11:12:11 -05:00
Heinrich Schuchardt
cc7e3d1929 cmd: increase default for SYS_MAXARGS
The value of CONFIG SYS_MAXARGS limits the usability of the 'for' command.
The current default of 16 is too low for some use case. Cf.
https://bugs.launchpad.net/snap-core18/+bug/1910094

Increase the default to 64.

Reported-by: Dave Jones <dave.jones@canonical.com>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-01-24 11:12:11 -05:00
Prasanth Babu Mantena
dd83c1c865 board: ti: common: board_detect: Fix EEPROM offset read for 1-byte
EEPROM detection logic in ti_i2c_eeprom_get() involves reading
the total size and the 1-byte size with an offset 1. The commit
9f393a2d7a ("board: ti: common: board_detect: Fix EEPROM read
quirk for 2-byte") that attempts to fix this uses a wrong pointer to
compare.

The value with one offset is read into offset_test, but the pointer
used to match was still ep, resulting in an invalid comparison of the
values. The intent is to identify bad 2-byte addressing eeproms that
get stuck on the successive reads.

Fixes: 9f393a2d7a (board: ti: common: board_detect: Fix EEPROM read quirk for 2-byte)
Signed-off-by: Prasanth Babu Mantena <p-mantena@ti.com>
Tested-by: Matwey V. Kornilov <matwey.kornilov@gmail.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
2024-01-24 11:12:04 -05:00
Sam Protsenko
1e81d12e34 MAINTAINERS: Add new Samsung subsystems
Add next Samsung subsystems with Sam Protsenko as a maintainer:

- Samsung CCF Clock Framework
- Exynos850 SoC Support
- Samsung SoC Drivers

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2024-01-24 11:23:20 +09:00
Sam Protsenko
3d80ec5265 board: samsung: Add support for E850-96 board
Add support for WinLink E850-96 board [1]. It's based on Exynos850 SoC
and follows 96boards specification, so it's compatible with 96boards
mezzanine boards [2]. This patch enables next features:

  * Serial console
  * USI
  * PMU (muxing AP UART path)
  * Pinctrl
  * Clocks
  * Timer (ARMv8 architected)
  * Reset control

It's quite a minimal enablement. Features like MMC, USB and Ethernet
will be enabled later.

The rationale for config values is as follows:

  * TEXT_BASE = 0xf8800000

    That's where BL2 loads the U-Boot payload, so TEXT_BASE must be
    exactly this value. Overall the memory map is designed in a way to
    keep the bootloader in the upper 128 MiB area of RAM, which is
    0xf8000000..0xffffffff. That includes bootloader's code, stack,
    data, heap, MMU tables, etc. All the memory below that 128 MiB chunk
    can be used for storing boot images (0x80000000..0xf8000000).

  * CUSTOM_SYS_INIT_SP_ADDR = 0xf8c00000

    Just 4 MiB above the TEXT_BASE address, to leave enough space for
    U-Boot code and stack itself (grows downwards).

  * SYS_LOAD_ADDR = 0x80000000

    The beginning of RAM. That's where Linux kernel image must be
    loaded.

  * SYS_MALLOC_LEN = 0x81f000

    8 MiB for malloc() + ENV_SIZE (128 KiB)

  * SYS_MALLOC_F_LEN = 0x4000

    Increase malloc() pool size available before relocation from 8 KiB
    (default) to 16 KiB. Otherwise "alloc space exhausted" message
    appears in U-Boot log during board_init_f() stage. There are next
    reasons for doing so:

      1. Having "bootph-all" flags in some dts nodes leads to binding
         those during pre-relocation stage, and binding (DM) uses
         dynamic memory allocation
      2. clk-exynos850 driver uses CCF clocks, which in turn use dynamic
         memory allocation

Device tree file was imported from Linux kernel. All nodes and boot
phase flags added in exynos850-e850-96-u-boot.dtsi are only needed to
enable serial console:

  * oscclk -> cmu_top -> cmu_peri: generate UART/USI clocks
  * pinctrl_alive and uart1_pins: needed to mux UART pins
  * pmu_system_controller: configures AP UART path to uart1_pins
  * usi_uart: configures USI block to operate as a UART protocol
  * serial_0: enables serial console (UART)

[1] https://www.96boards.org/product/e850-96b/
[2] https://www.96boards.org/products/mezzanine/

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2024-01-24 11:23:20 +09:00
Sam Protsenko
e6e300d5ef arm: exynos: Add Exynos850 SoC support
Samsung Exynos850 is ARMv8-based mobile-oriented SoC. It features
Cortex-A55 CPU (8 cores) and it's built using 8nm process.

Add Exynos850 support by enabling next features:

  * Import Exynos850 SoC dtsi files from Linux kernel
  * Add Exynos850 MMU memory map
  * Introduce ARCH_EXYNOS9 platform config option

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2024-01-24 11:23:20 +09:00
Sam Protsenko
c2e8b97c60 serial: s5p: Add Exynos850 compatible
Enable serial support for Exynos850 SoC by adding the corresponding
compatible string. No additional changes needed, the driver works as is
on Exynos850. Related USI and PMU configuration is enabled in separate
drivers. The only other dependencies are clock and pinctrl drivers,
which are already enabled too.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2024-01-24 11:23:20 +09:00
Sam Protsenko
f09a355d17 pinctrl: exynos: Add pinctrl support for Exynos850
Add pinctrl support for Exynos850 SoC. It was mostly extracted from
corresponding Linux kernel code [1]. Power down modes and external
interrupt data were removed while converting the code for U-Boot, but
everything else was kept almost unchanged.

[1] drivers/pinctrl/samsung/pinctrl-exynos-arm64.c

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Chanho Park <chanho61.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2024-01-24 11:23:20 +09:00
Sam Protsenko
a36cc5e3ef clk: exynos: Add Exynos850 clock driver
Heavily influenced by its Linux kernel counterpart. It's implemented on
top of recently added Samsung CCF clock framework API. For now only UART
leaf clocks are implemented, along with all preceding clocks in CMU_TOP
and CMU_PERI. The UART baud clock is required in the serial driver, to
get its rate for the consequent baud rate calculation.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Chanho Park <chanho61.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2024-01-24 11:23:20 +09:00
Sam Protsenko
ff3e8b8c6c clk: exynos: Add Samsung clock framework
Heavily based on Linux kernel Samsung clock framework, with some changes
to accommodate the differences in U-Boot CCF implementation. It's also
quite minimal as compared to the Linux version.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Chanho Park <chanho61.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2024-01-24 11:23:20 +09:00
Sam Protsenko
0caae9fdc2 clk: exynos: Move pll code into clk-exynos7420
PLL utilities code is only used by clk-exynos7420 driver at the moment.
Move it into clk-exynos7420 to make clk-pll.c file available for CCF PLL
clocks implementation, which is coming in the next patches.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Chanho Park <chanho61.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2024-01-24 11:23:20 +09:00
Sam Protsenko
8fd06aeb8a soc: samsung: Add Exynos PMU driver
Add basic Power Management Unit (PMU) driver for Exynos SoCs. For now
it's only capable of changing UART path in PMU, which is needed for
E850-96 board. The driver's structure resembles the exynos-pmu driver
from Linux kernel, and although it's very basic and slim at the moment,
it can be easily extended in future if the need arises.

UCLASS_NOP is used, as there are no benefits in using more elaborate
classes like UCLASS_MISC in this case. The DM_FLAG_PROBE_AFTER_BIND flag
is added in bind function, as the probe function must be always called
for this driver.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Chanho Park <chanho61.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2024-01-24 11:23:20 +09:00
Sam Protsenko
c9a3efdfc0 soc: samsung: Add Exynos USI driver
USIv2 IP-core is found on modern ARM64 Exynos SoCs (like Exynos850) and
provides selectable serial protocol (one of: UART, SPI, I2C). USIv2
registers usually reside in the same register map as a particular
underlying protocol it implements, but have some particular offset. E.g.
on Exynos850 the USI_UART has 0x13820000 base address, where UART
registers have 0x00..0x40 offsets, and USI registers have 0xc0..0xdc
offsets. Desired protocol can be chosen via SW_CONF register from System
Register block of the same domain as USI.

Before starting to use a particular protocol, USIv2 must be configured
properly:
  1. Select protocol to be used via System Register
  2. Clear "reset" flag in USI_CON
  3. Configure HWACG behavior (e.g. for UART Rx the HWACG must be
     disabled, so that the IP clock is not gated automatically); this is
     done using USI_OPTION register
  4. Keep both USI clocks (PCLK and IPCLK) running during USI registers
     modification

This driver implements the above behavior. Of course, USIv2 driver
should be probed before UART/I2C/SPI drivers. It can be achieved by
embedding UART/I2C/SPI nodes inside of the USI node (in Device Tree);
driver then walks underlying nodes and instantiates those. Driver also
handles USI configuration on PM resume, as register contents can be lost
during CPU suspend.

This driver is designed with different USI versions in mind. So it
should be relatively easy to add new USI revisions to it later.

Driver's code was copied over from Linux kernel [1] and adapted
correspondingly for U-Boot API. UCLASS_MISC is used, and although no
misc operations are implemented, it makes it easier to probe the driver
this way (as compared to UCLASS_NOP) and keep the code compact.

[1] drivers/soc/samsung/exynos-usi.c

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Chanho Park <chanho61.park@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2024-01-24 11:23:20 +09:00
Sam Protsenko
bd6bff71b8 dt-bindings: clock: Add Exynos850 clock controller
Add bindings documentation and the header file for Exynos850 clock
controller. It was taken from Linux kernel [1,2].

[1] Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
[2] include/dt-bindings/clock/exynos850.h

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2024-01-24 11:23:20 +09:00
Sam Protsenko
18c0556233 dt-bindings: soc: samsung: Add Exynos PMU
Add bindings documentation for Exynos PMU hardware block. It was taken
from Linux kernel [1], but minimized and modified to reflect features
that will be actually supported in U-Boot soon. For example,
the "samsung,uart-debug-1" property is not available in Linux kernel
bindings and only present in U-Boot.

[1] Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2024-01-24 11:23:20 +09:00
Sam Protsenko
5473a06dd6 dt-bindings: soc: samsung: Add Exynos USI
Add USI bindings documentation and header file. Those are taken from
Linux kernel [1,2], but the documentation was reworked a bit to only
describe the compatibles that will be supported in U-Boot soon.

[1] Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml
[2] include/dt-bindings/soc/samsung,exynos-usi.h

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2024-01-24 11:23:20 +09:00
Tom Rini
15e7927b5a Merge patch series "omap3: Make SPL_OMAP3_ID_NAND depend on NAND_OMAP_GPMC"
This series results in making it such that with CONFIG_MTD disabled we
then do not prompt the user for a number of memory technology device
related options and so clean up our configuration menu / display.
2024-01-22 14:18:55 -05:00
Tom Rini
db04ff42c7 mtd: Make CONFIG_MTD be the gate symbol for the menu
The help for CONFIG_MTD explains that it needs to be enabled for various
things like NAND, etc to be available. It however then doesn't enforce
this dependency and so if you have none of these systems present you
still need to disable a number of options. Fix this by making places
that select/imply one type of flash, but did not do the same, also do
this for "MTD". Make boards which hadn't been enabling MTD already but
need it now, do so. In a few places, disable CONFIG_CMD_MTDPARTS as it
wasn't previously enabled but was now being implied.

Signed-off-by: Tom Rini <trini@konsulko.com>
2024-01-22 14:18:54 -05:00
Tom Rini
cda3f81b06 cmd/flash: Make this default y for CFI and NOR only
This command is only useful on CFI and NOR type flashes and not others.
Update the dependency so that it's not enabled by default in other
cases. This will lead to a number of platforms no longer building this
command, where it was not useful.

Signed-off-by: Tom Rini <trini@konsulko.com>
2024-01-22 14:17:35 -05:00
Tom Rini
9913a82128 env: Make ENV_IS_IN_SPI_FLASH depend on SPI flash being present
In order for our environment to be present on SPI flash we need to
depend not on the symbol for a SPI controller but rather that SPI flash
of some sort is present. Update the dependencies.

Signed-off-by: Tom Rini <trini@konsulko.com>
2024-01-22 14:17:35 -05:00
Tom Rini
246c94f192 cmd/mtdparts: Make this select MTD_PARTITIONS
Rather than rely on someone selecting or implying this hidden symbol
that the command requires, select it explicitly.

Signed-off-by: Tom Rini <trini@konsulko.com>
2024-01-22 14:17:35 -05:00
Tom Rini
fee9e48c89 omap3: Make SPL_OMAP3_ID_NAND depend on NAND_OMAP_GPMC
This specific bit logic is used to determine what NAND chip is present
on a board in order to then know what revision of the board we have and
so what DDR chips are present. We can only do this if we have a NAND
chip, and so we will have NAND_OMAP_GPMC enabled.

Signed-off-by: Tom Rini <trini@konsulko.com>
2024-01-22 14:17:35 -05:00
Shantur Rathore
33e06dcbe5 common: usb-hub: Reset hub port before scanning
Currently when a hub is turned on, all the ports are powered on.
This works well for hubs which have individual power control.

For the hubs without individual power control this has no effect.
Mostly in these scenarios the hub port is powered before the USB
controller is enabled, this can lead to some devices in unexpected
state.

With this patch, we explicitly reset the port while powering up hub
This resets the port for hubs without port power control and has
no effect on hubs with port power control as the port is still off.

Before this patch AMicro AM8180 based NVME to USB adapter won't be
detected as a USB3.0 Mass Storage device but with this it works as
expected.

Tested working after this patch:
1. AMicro AM8180 based NVME to USB Adapter
2. Kingston DataTraveler 3.0
3. GenesysLogic USB3.0 Hub

The drives were tested while connected directly and via the hub.

Signed-off-by: Shantur Rathore <i@shantur.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2024-01-22 12:49:03 -05:00
Tom Rini
c09ec8e1cb Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell
- solidrun: clearfog gtr: add serdes configuration (Josua)
2024-01-22 10:59:20 -05:00
Tom Rini
d64e05fc5b Merge tag 'u-boot-imx-master-20240122' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
- Allow i.MX8M Plus DHCOM to operate in overdrive mode.
- Allow i.MX8M Plus eDM SBC to operate in overdrive mode.
- Enable the 'kaslrseed' command on DH i.MX8M Plus DHCOM.
- Select LTO by default on i.MX8M.
- Convert pico-dwarf/hobbit-imx6ul to CONFIG_DM_SERIAL.
- Fix 'reset' command on wandboard.
2024-01-22 09:47:52 -05:00
Tom Rini
79a9697894 Merge commit '3c9bb8fbdc77f6bd56e97597d875d8965db3b96c' of https://github.com/tienfong/uboot_mainline
A few small SoCFPGA updates
2024-01-22 09:35:38 -05:00
Josua Mayer
bb6e89048c board: solidrun: clearfog: fix serdes 1 / eth2 speed for clearfog gtr
Clearfog GTR connects eth2 / serdes 1 to a 2.5Gbps capable ethernet
switch port. Linux already configures a fixed-link at speed 2500 from
device-tree.

Upgrade serdes 1 rate to 3.125Gbps to support a 2.5Gbps link.

Additionally add comments documenting each serdes' function of clearfog
gtr, which are shared with clearfog pro.

Signed-off-by: Josua Mayer <josua@solid-run.com>
2024-01-22 12:47:45 +01:00
Josua Mayer
26c7de353f arm: mvebu: clearfog gtr: add config option to select serdes0 interface
Clearfog GTR has an assembly option for a SATA connector, CON18.
It shares the serdes with mini-pcie connector CON3.

Add new kconfig option to select betweenata and pci, defaulting to pci
as it was previously configured in board-file.

Clearfog GTR connects eth2 / serdes 1 to a 2.5Gbps capable ethernet
switch port. Linux already configures a fixed-link at speed 2500 from
device-tree.
Upgrade serdes 1 rate to 3.125Gbps to support a 2.5Gbps network link on
Clearfog GTR.

Signed-off-by: Josua Mayer <josua@solid-run.com>
2024-01-22 12:47:45 +01:00
Marek Vasut
a80e0e7711 ARM: imx: Enable kaslrseed command on DH i.MX8M Plus DHCOM
Linux 6.6.y with KASLR enabled would print the following message on boot:
"
KASLR disabled due to lack of seed
"
Enable the 'kaslrseed' command so a random number seed can be pulled
from CAAM and inserted into the /chosen node 'kaslr-seed' property of
Linux kernel DT before boot, thus letting KASLR work properly.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2024-01-22 08:40:02 -03:00
Fabio Estevam
0912368af3 pico-dwarf/hobbit-imx6ul: Convert to CONFIG_DM_SERIAL
The conversion to CONFIG_DM_SERIAL is mandatory, so select
this option.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
2024-01-22 08:39:41 -03:00
Fabio Estevam
b06bfd65b6 wandboard: Convert to watchdog driver model
Commit 68dcbdd594 ("ARM: imx: Add weak default reset_cpu()") caused
the 'reset' command in U-Boot to not cause a board reset.

Fix it by switching to the watchdog driver model via sysreset, which
is the preferred method for implementing the watchdog reset.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
2024-01-22 08:39:27 -03:00
Marek Vasut
67de291400 ARM: imx: Configure GIC clock parent on Data Modul i.MX8M Plus eDM SBC
The CONFIG_SPL_BOARD_INIT lets SPL common code call spl_board_init()
during the SPL start up. On this particular system, spl_board_init()
is used to reconfigure GIC clock parent to PLL2 500M, which is the
configuration expected by the Linux kernel. Enable SPL_BOARD_INIT
and fill in the GIC clock configuration code.

Set GIC clock to 500 MHz for OD VDD_SOC. Kernel driver does not
allow to change it. Should set the clock after PMIC setting done.
Default is 400 MHz (system_pll1_800m with div = 2) set by ROM for
ND VDD_SOC.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2024-01-22 08:39:08 -03:00
Marek Vasut
4dd80cb09e ARM: imx: Enable SPL_BOARD_INIT on DH i.MX8M Plus DHCOM
The CONFIG_SPL_BOARD_INIT lets SPL common code call spl_board_init()
during the SPL start up. On this particular system, spl_board_init()
is used to reconfigure GIC clock parent to PLL2 500M, which is the
configuration expected by the Linux kernel. Enable SPL_BOARD_INIT .

Set GIC clock to 500 MHz for OD VDD_SOC. Kernel driver does not
allow to change it. Should set the clock after PMIC setting done.
Default is 400 MHz (system_pll1_800m with div = 2) set by ROM for
ND VDD_SOC.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2024-01-22 08:38:48 -03:00
Fabio Estevam
f8cebb4f78 imx8m: Enable LTO by default
In an attempt to select ARMV8_SPL_EXCEPTION_VECTORS, the SPL size
could not fit into the internal SRAM of some imx8m targets:

   aarch64:  +   imx8mm_phg
+aarch64-linux-ld.bfd: u-boot-spl section `__u_boot_list' will not fit in region `.sram'
+aarch64-linux-ld.bfd: region `.sram' overflowed by 1824 bytes

Select LTO to prevent that.

Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
2024-01-22 08:38:32 -03:00
Dinesh Maniyam
3c9bb8fbdc arm: dts: agilex: Increase reserved memory size to 32MB
The reserved space is extended to 32MB in Linux kernel because
additional space is needed for authorization execution of JIC/RBF file.
U-Boot required to align with Linux.

Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2024-01-22 16:51:29 +08:00
Dinesh Maniyam
9d8f814beb clk: altera: n5x: Fix MEMCLKMGR_EXTCNTRST_C0CNTRST to bit(0)
MEMCLKMGR_EXTCNTRST_C0CNTRST register defined as BIT[0] in documentation
but it is wrongly defined as BIT[7] in u-boot code. This register is used
to hold associated pingpong counter in reset
while PLL and 5:1 mux configuration is changed.

Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2024-01-22 16:51:17 +08:00
Dinesh Maniyam
158d648d9f arm: socfpga: stratix10: SPI clock support
This patch is to add SPI clock support for stratix10. Get clock rate
function always returning 0 because the DW-SPI driver get the rate
from clock node in dts but Stratix10 does not support device tree
clock node.To overcome this spi will get the clock_rate directly
from spi clock controller override the weaker function.

Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2024-01-22 16:50:55 +08:00
Alexander Dahl
a1c6b08274 mtd: nand: raw: atmel: Remove duplicate definitions
These removed definitions were specific to some sam9 SoCs, but not
generic over all at91 SoCs.  The correct SoC specific definitions for
ATMEL_BASE_PMECC are spread over different header files in
arch/arm/mach-at91/include/mach directory.

Fixes a build error on a custon board based on SAMA5D2:

    Building current source for 73 boards (16 threads, 1 job per thread)
           arm:  +   vera2
    +drivers/mtd/nand/raw/atmel/pmecc.c:819: warning: "ATMEL_BASE_PMECC" redefined
    +  819 | #define ATMEL_BASE_PMECC        0xffffe000
    +      |
    +In file included from include/configs/vera2.h:11,
    +                 from include/config.h:3,
    +                 from include/linux/mtd/rawnand.h:16,
    +                 from drivers/mtd/nand/raw/atmel/pmecc.c:44:
    +include/asm/arch/sama5d2.h:171: note: this is the location of the previous definition
    +  171 | #define ATMEL_BASE_PMECC        (ATMEL_BASE_HSMC + 0x70)
    +drivers/mtd/nand/raw/atmel/pmecc.c:820: warning: "ATMEL_BASE_PMERRLOC" redefined
    +  820 | #define ATMEL_BASE_PMERRLOC     0xffffe600
    +include/asm/arch/sama5d2.h:172: note: this is the location of the previous definition
    +  172 | #define ATMEL_BASE_PMERRLOC     (ATMEL_BASE_HSMC + 0x500)

Fixes: a490e1b7c0 ("nand: atmel: Add pmecc driver")
Signed-off-by: Alexander Dahl <ada@thorsis.com>
2024-01-22 06:05:26 +02:00
Alexander Dahl
23308cd150 ARM: dts: at91: sama5d2: Align more node names with Linux
Port from Linux v6.7-rc4.  Should not hurt U-Boot but makes diffing
easier and allows referencing node names in board dts.

Signed-off-by: Alexander Dahl <ada@thorsis.com>
2024-01-22 06:05:26 +02:00
Alexander Dahl
e81a0159a8 ARM: dts: at91: sama5d2: Port ebi/nand nodes from linux
Required for using the new DM based atmel nand driver.
Ported from Linux v6.7-rc4.

Signed-off-by: Alexander Dahl <ada@thorsis.com>
2024-01-22 06:05:26 +02:00
Alexander Dahl
42c4dcbbce ARM: dts: at91: sama5d2: Move sfr node
Nodes are ordered by register offset.

Fixes: 56246d1e87 ("ARM: dts: at91: sama5: Add the sfr node")
Signed-off-by: Alexander Dahl <ada@thorsis.com>
2024-01-22 06:05:25 +02:00
Tom Rini
22aeab2d96 Merge tag 'efi-2024-04-rc1-3' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request efi-2024-04-rc1-3

Documentation:

* correct documentation of part_get_bootable()
* remove duplicate word "has" in UEFI documentation

UEFI:

* rename check_disk_has_default_file function
* auto-generate boot option for each blkio device
* auto-generate removable media boot option first
* avoid pointer access after calling efi_delete_handle
* create common function to free struct efi_disk_obj
* return immediately in UCLASS_EFI_LOADER removal
2024-01-21 09:11:33 -05:00
Masahisa Kojima
2c98f7435c efi_loader: return immediately in UCLASS_EFI_LOADER removal
In case of UCLASS_EFI_LOADER, EFI handles are managed by
EFI application/driver, we must not delete EFI handles.

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-01-21 11:24:24 +01:00
Masahisa Kojima
0351b659dd efi_loader: create common function to free struct efi_disk_obj
Current error handling of creating raw disk/partition has
following issues.
 - duplicate free for EFI handle, EFI handle is already freed
   in efi_delete_handle()
 - missing free for struct efi_device_path and
   struct efi_simple_file_system_protocol in some error paths

To address those issues, this commit creates the common function
to free the struct efi_disk_obj resources and calls it in case
of error.

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-01-21 11:24:24 +01:00
Masahisa Kojima
f674a2f9a9 efi_loader: avoid pointer access after calling efi_delete_handle
efi_delete_handle() calls efi_purge_handle(), then it finally
frees the EFI handle.
Both diskobj and handle variables in efi_disk_remove() have
the same pointer, we can not access diskobj->dp after calling
efi_delete_handle().

This commit saves the struct efi_device_path pointer before
calling efi_delete_handle(). This commit also fixes the
missing free for volume member in struct efi_disk_obj.

This commit also removes the container_of() calls, and
adds the TODO comment of missing efi_close_protocol() call
for the parent EFI_BLOCK_IO_PROTOCOL.

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-01-21 11:24:24 +01:00
Masahisa Kojima
3f7822bf9f efi_loader: auto-generate removable media boot option first
This commit auto-generates the boot option for removable
block io devices followed by fixed block io devices.
This is what EDK II reference implementation does.

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-01-21 11:24:24 +01:00
Masahisa Kojima
f86fba8adb efi_loader: auto-generate boot option for each blkio device
Current efibootmgr auto-generates the boot option for all
disks and partitions installing EFI_SIMPLE_FILE_SYSTEM_PROTOCOL,
while EDK II reference implementation auto-generates the boot option
for all devices installing  EFI_BLOCK_IO_PROTOCOL with
eliminating logical partitions.

This commit modifies the efibootmgr to get aligned to EDK II.

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-01-21 11:24:24 +01:00
Masahisa Kojima
eb2f0867a1 efi_loader: rename check_disk_has_default_file function
check_disk_has_default_file() function checks if the
architecture-specific default file exists on the block
device, and fills the default file device path if it exists.

Rename the function name to fill_default_file_path().

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-01-21 11:24:24 +01:00
Heinrich Schuchardt
e75e4cf5d9 part: correct documentation of part_get_bootable()
We have to use 'Return:' to render the description of the return value in
the HTML documentation.

Fixes: f55aa4454a ("part: Add a fallback for part_get_bootable()")
Fixes: dcffa4428d ("part: Add a function to find the first bootable partition")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-01-21 11:24:24 +01:00
Wei Ming Chen
0d7634ebc1 doc: uefi: remove duplicate word "has"
There should be only one "has" instead of "has has"

Signed-off-by: Wei Ming Chen <jj251510319013@gmail.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-01-21 11:24:18 +01:00
Tom Rini
3c04fcf313 Merge patch series "k3-j721e: beagleboneai: Fix USB"
Roger Quadros <rogerq@kernel.org> says:

Hi,

This series fixes USB operation on k3-j721e based boards.
2024-01-20 11:39:13 -05:00
Roger Quadros
172c846f39 configs/j721e_beagleboneai64_a72_defconfig: Enable Sierra PHY
This is required for USB Super-Speed operation.

Signed-off-by: Roger Quadros <rogerq@kernel.org>
2024-01-20 11:38:18 -05:00
Roger Quadros
17d3cb7610 arm: dts: k3-j721e-beagleboneai64: Fix USB operation
Without correct SERDES MUX and Lane control settings
USB0 will be broken. Set the MUX and Lane control devices
to be auto probed so they are configured correctly.

Signed-off-by: Roger Quadros <rogerq@kernel.org>
2024-01-20 11:38:18 -05:00
Roger Quadros
7d5a12018e arm: dts: k3-j721e: Fix USB0 operation
Without correct SERDES MUX and Lane control settings
USB0 will be broken. Set the MUX and Lane control devices
to be auto probed so they are configured correctly.

Fixes: 69b19ca67b ("arm: dts: k3-j721e: Sync with v6.6-rc1")
Signed-off-by: Roger Quadros <rogerq@kernel.org>
2024-01-20 11:38:18 -05:00
Roger Quadros
cd295286c7 usb: cdns3: avoid error messages if phys don't exist
The phys property is optional so don't complain
if it doesn't exist in device tree.

Signed-off-by: Roger Quadros <rogerq@kernel.org>
2024-01-20 11:38:18 -05:00
Roger Quadros
434f84b749 board: ti: j721e: Drop SERDES PHY init from board file
Since commit 69b19ca67b ("arm: dts: k3-j721e: Sync with v6.6-rc1"),
the following error message is seen at u-boot
	"Sierra init failed:-19"

Probing and initializing the SERDES PHY from
board file is not a clean solution so drop it.

Proper use case should be via PHY_UCLASS APIs.

Signed-off-by: Roger Quadros <rogerq@kernel.org>
2024-01-20 11:38:18 -05:00
Shantur Rathore
fea3efb757 Kconfig: boot: Imply BOOTSTD_DEFAULT when BOOTSTD_FULL=y
We need BOOTSTD_DEFAULT when BOOTSTD_FULL is selected.

Signed-off-by: Shantur Rathore <i@shantur.com>
2024-01-19 18:30:08 -05:00
Tom Rini
83a8424722 Merge tag 'u-boot-stm32-20240119' of https://source.denx.de/u-boot/custodians/u-boot-stm
Add CMDLINE dependecy for CMD_STM32KEY

STM32MP1:
---------
Set stdio to serial on DH STM32MP15xx DHSOM
Fix reset for usart1 in scmi configuration

STM32MP2:
---------
Add BSEC and OTP support for STM32MP25
Fix CONFIG_STM32MP25X flag usage
2024-01-19 11:59:28 -05:00
Patrice Chotard
8a4d098bb0 stm32mp2: Fix CONFIG_STM32MP25X flag usage
"#if" was used instead of "#ifdef"

Fixes: 01a701994b ("stm32mp2: initial support")
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2024-01-19 15:49:20 +01:00
Patrick Delaunay
c2c2977227 stm32mp: Add dependencies on CMDLINE for command stm32key
We cannot use stm32key commands without CONFIG_CMDLINE so add the
required condition.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2024-01-19 15:10:06 +01:00
Marek Vasut
82f5942e51 ARM: stm32: Set stdio to serial on DH STM32MP15xx DHSOM
In case CONSOLE_MUX and SYS_CONSOLE_IS_IN_ENV are enabled, the console
stdin, stdout, stderr must be defined in environment. Define the default
settings to fix the following warning on boot:

"
In:    No input devices available!
Out:   No output devices available!
Err:   No error devices available!
"

Sort the default environment as well.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2024-01-19 15:07:12 +01:00
Tom Rini
f4d5486506 Merge branch '2024-01-18-assorted-fixes'
- A number of OS boot related cleanups, a number of TI platform
  fixes/cleanups, SMBIOS fixes, tweak get_maintainers.pl to report me
  for more places, fix the "clean the build" pytest and add a bootstage
  pytest, fix PKCS11 URI being omitted in some valid cases, make an iommu
  problem easier to debug on new platforms, nvme and pci improvements,
  refactor image-host code a bit, fix a typo in env setting, add a missing
  dependency for CMD_LICENSE, and correct how we call getchar() in some
  places.
2024-01-19 08:46:47 -05:00
Patrick Delaunay
9f1dc110cc arm: Rename STM32MP15x
CONFIG options must not use lower-case letter. Convert this and related
ones to upper case.

Signed-off-by: Simon Glass <sjg@chromium.org
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2024-01-19 14:38:59 +01:00
Patrick Delaunay
49de864a25 arm: Rename STM32MP13x
CONFIG options must not use lower-case letter. Convert this and related
ones to upper case.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@foundries.io>
2024-01-19 14:38:59 +01:00
Patrick Delaunay
eff29f0a60 board: st: stm32mp2: display the board identification
Add the display of the STMicroelectronics board identification saved in OTP
in stm32mp2 checkboard function.

Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2024-01-19 14:38:59 +01:00
Patrick Delaunay
1067d7e3a0 board: st: stm32mp2: add checkboard
Implement the weak function checkboard to identify the used board with
compatible in device tree for the support of stm32mp2 STMicroelectronics
boards.

Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2024-01-19 14:38:59 +01:00
Patrick Delaunay
ebf32b2548 stm32mp: activate the command stboard for stm32mp25 boards
Activate the command stboard for stm32mp25 STMicroelectronics boards,
add the default used OTP identifier and the associated board identifier:
- stm32mp25xx-ev1 = MB1936
- stm32mp25xx-dk = MB1605

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2024-01-19 14:38:59 +01:00
Patrick Delaunay
4d58bb32d1 stm32mp: stm32prog: add support of stm32mp25
Change OTP number to 364 for STM32MP25 as it is done in bsec driver.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2024-01-19 14:38:12 +01:00
Patrick Delaunay
8eb535e3b0 smt32mp: add setup_mac_address for stm32mp25
Add a function setup_mac_address() to update the MAC address from the
default location in OTP for stm32mp2 platform.

The max number of OTP for MAC address is increased to 8 for STM32MP25,
defined with get_eth_nb() and checked in setup_mac_address.

The MAC address FF:FF:FF:FF:FF:FF, the broadcast ethaddr, is a invalid
value used for unused MAC address slot in OTP, for example for board
with STM32MP25x part number allows up to 5 ethernet ports but it is not
supported by the hardware, without switch; the associated variable
"enetaddr%d" is not created.

Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2024-01-19 14:38:01 +01:00
Patrice Chotard
9c2f5b8ad6 stm32mp: add setup_serial_number for stm32mp25
Add support of serial number for stm32mp25, gets from OTP with BSEC driver.

Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@foundries.io>
2024-01-19 14:37:50 +01:00
Patrick Delaunay
1af148da84 stm32mp: add soc.c file
Add a new file soc.c for common functions between stm32mp1 and stm32mp2
family and move print_cpuinfo() in this new file.

Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@foundries.io>
2024-01-19 14:37:10 +01:00
Patrick Delaunay
c20e0fc7d6 configs: stm32mp25: add support of fuse command
Add support of the command fuse with CONFIG_CMD_FUSE to allow access
on OTP with command line.

Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2024-01-19 14:19:43 +01:00
Patrick Delaunay
e508b597f0 stm32mp: bsec: add support of stm32mp25
Add support of BSEC for STM32MP25x family to access OTP.

Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2024-01-19 14:19:42 +01:00
Patrick Delaunay
0d0266c46c stm32mp: bsec: add driver data
Add driver data in  BSEC driver to test presence of OP-TEE TA,
mandatory for STM32MP13 family and prepare the support of new device
with more OTP than 95.

Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2024-01-19 14:19:42 +01:00
Yann Gautier
5c76937659 arm: stm32mp: add Rev.B support for STM32MP25
Add chip revision B support for STM32MP25, for displaying it in trace.

Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2024-01-19 14:19:42 +01:00
Patrick Delaunay
792122baa7 arm64: dts: st: add bsec support to stm32mp25
Add BSEC support to STM32MP25 SoC family with SoC information:
- RPN = Device part number (BSEC_OTP_DATA9)
- PKG = package data register (Bits 2:0 of BSEC_OTP_DATA122)

Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-01-19 14:19:42 +01:00
Patrice Chotard
ea5a4d69d8 ARM: dts: stm32: Fix reset for usart1 in scmi configuration
In SCMI configuration, usart1 is secure, so all its resources are secured
(clock and reset) and can't be set/unset by non-secure world but by OP-TEE.

Fixes: 6cccc8d396 ("ARM: dts: stm32: add SCMI version of STM32 boards (DK1/DK2/ED1/EV1)")

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2024-01-19 14:03:28 +01:00
Tom Rini
cb49375239 Merge tag 'u-boot-rockchip-20240119' of https://source.denx.de/u-boot/custodians/u-boot-rockchip
- Add board: rk3328 FriendlyARM NanoPi R2C Plus, rk3588 Turing RK1 SoM;
- Enable SPI boot for rk3588 and rk3528;
- Set boot device in SPL as common code;
- other misc fixes;
2024-01-19 08:02:58 -05:00
Quentin Schulz
c16c7ac2fe rockchip: rk3128: remove noop file
arch_cpu_init is already returning 0 in its weak definition in
common/board_f.c so let's just remove the file entirely since nothing
else is done in it.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
2024-01-19 10:57:36 +08:00
Quentin Schulz
f66d9dd81f rockchip: remove unused global data ptr
Remove leftover import and global data ptr from files since they aren't
used anymore.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
2024-01-19 10:57:36 +08:00
Quentin Schulz
d57e16c7e7 rockchip: find U-boot proper boot device by inverting the logic that sets it
BOOT_DEVICE_* is set by spl_node_to_boot_device() depending on the block
device number associated with the MMC device the SPL used to load U-Boot
proper from. It is NOT related to the mmc alias in the Device Tree.

For SPI flashes, all SPI flashes will return BOOT_DEVICE_SPI so there's
currently no way to know from which one the SPL loaded U-Boot proper
from. Therefore, let's just find the first valid candidate in
/chosen/u-boot,spl-boot-order that is a SPI flash and return that path.
This is a best effort.

While the original implementation may have worked, using the exact same
mechanism but in inverted fashion makes it less likely to have
surprising corner-cases or side-effects.

A nice side-effect is that all existing and future Rockchip SoCs now
automatically have their /chosen/u-boot,spl-boot-device set.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
2024-01-19 10:57:36 +08:00
Quentin Schulz
948b315e41 rockchip: factor out spl_perform_fixups into common spl-boot-order
All SoCs are susceptible to wanting to know which storage medium was
used to load U-Boot SPL. So instead of reimplementing the same functions
in SoCs over and over again (here just rk3399 and px30 but rk3588 is
coming), let's just put all this in common into spl-boot-order.c
allowing to support a new SoC just by defining the spl_boot_devices
array in the appropriate SoC file.

Note that spl_perform_fixups() now calls spl_image_fdt_addr() to get the
address of the fdt instead of directly reading the
spl_image_info->fdt_addr member, because that member is not guaranteed
to be present (guarded with compile flags). This is essential because we
move the logic away from px30 and rk3399 which had those compile flags
enabled to code run for all Rockchip SoCs.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
2024-01-19 10:57:36 +08:00
Quentin Schulz
a5843cfce8 rockchip: px30: simplify logic for getting SPL boot medium DT node
In preparation of moving spl_perform_fixups to spl-boot-order.c, let's
simplify the logic around mapping the BOOT_DEVICE_x enum index to a DT
node by using an instantiated array of chars instead of creating a new
data structure on the fly.
This will make it easier to factor out the code handling the SPL boot
medium detection by having spl_decode_boot_device common to all SoCs.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
2024-01-19 10:57:36 +08:00
Quentin Schulz
543f24dffc rockchip: rk3399: simplify logic for getting SPL boot medium DT node
In preparation of moving spl_perform_fixups to spl-boot-order.c, let's
simplify the logic around mapping the BOOT_DEVICE_x enum index to a DT
node by using an instantiated array of chars instead of creating a new
data structure on the fly.

This will make it easier to factor out the code handling the SPL boot
medium detection by having spl_decode_boot_device common to all SoCs.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
2024-01-19 10:57:36 +08:00
Chris Morgan
350afb9752 doc: board: anbernic: Update rgxx3 to add new boards
Update the RGxx3 documentation to note that it now supports the
RG-ARC-D, RG-ARC-S, Powkiddy RK2023, and Powkiddy RGB30. Also update
verbiage around panel detection to note that it is no longer hard coded
to the RG503.

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-01-19 10:57:36 +08:00
Chris Morgan
0cc6cbe84d board: rockchip: Add support for new boards to RGxx3
Add support for the Anbernic RG-ARC-D, Anbernic RG-ARC-S, Powkiddy
RK2023, and Powkiddy RGB30 to the Anbernic RGxx3. While the Powkiddy
devices are manufactured by Powkiddy instead of Anbernic,
the hardware is so similar they can all use the same bootloader.

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-01-19 10:57:36 +08:00
Chris Morgan
d2048bafae rockchip: board: Add board_rng_seed() for all Rockchip devices
Allow all rockchip devices to use the hardware RNG to seed Linux
RNG.

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-01-19 10:57:36 +08:00
Chris Morgan
4913ce37c4 board: rockchip: Refactor panel auto-detect code
Make the inability to detect a panel using the auto detection code not
fail the entire boot process. This means that if the panel ID cannot
be read we don't set an environment variable for the panel, and if an
environment variable for the panel is not set we don't attempt to
update the compatible string. Changes to the code also ensure that
when there are multiple compatible strings required for the panel
we use them both, which solves some issues that will pop up soon
for the Linux driver.

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-01-19 10:57:36 +08:00
Jonas Karlman
5708e8eeae rockchip: rk3328: Set efuse auto mode and timing control
Reading from efuse return zero when mainline TF-A is used.

  => dump_efuse
  00000000: 00 00 00 00  ....
  00000004: 00 00 00 00  ....
  00000008: 00 00 00 00  ....
  0000000c: 00 00 00 00  ....
  00000010: 00 00 00 00  ....
  00000014: 00 00 00 00  ....
  00000018: 00 00 00 00  ....
  0000001c: 00 00 00 00  ....

However, when vendor TF-A blobs is used reading from efuse works.

Change to use auto mode, enable finish and auto access err interrupts
and set timing control using same values that vendor TF-A blob use to
fix this.

With this efuse can be read when either of mainline TF-A or vendor blob
is used.

  => dump_efuse
  00000000: 52 4b 33 82  RK3.
  00000004: 00 fe 21 55  ..!U
  00000008: 52 4b 57 34  RKW4
  0000000c: 35 30 32 39  5029
  00000010: 00 00 00 00  ....
  00000014: 08 25 0c 0f  .%..
  00000018: 02 0d 08 00  ....
  0000001c: 00 00 f0 00  ....

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-01-19 10:57:36 +08:00
Quentin Schulz
d2c90bfc4c rockchip: theobroma-systems: fix modified boot_targets detection
U-Boot proper automatically modifies boot_targets to swap the order in
which MMC storage media are used for standard boot based on which MMC
storage medium was used to load U-Boot proper. This is however only done
if the user has not changed it manually, therefore a check between the
default and current value is done.

This used to work fine until the migration to standard boot where
boot_targets value size in the default environment went above the 32
characters that env_get_default function can return, thus resulting in a
truncated variable.

Therefore the check between default and current value would always fail.

By using the newly added env_get_default_into function, a buffer of
the appropriate size can be allocated on the stack to get the whole
value of boot_targets in the default environment and thus fixing the
check.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
2024-01-19 10:57:36 +08:00
Quentin Schulz
87d3c472a2 env: migrate env_get_default to call env_get_default_into
Since both functions share a similar goal and env_get_default_into can
do what env_get_default wants to do with specific arguments, let's make
env_get_default call env_get_default_into so as to avoid code
duplication.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
2024-01-19 10:57:36 +08:00
Quentin Schulz
23c1ab92be env: allow to copy value from default environment into a buffer
env_get_default suffers from a particular issue int that it can only
return a value truncated to gd->env_buf (32) characters. This may be
enough for most variables but it isn't for others, so let's allow users
to provide a preallocated buffer to copy the value into instead,
allowing for more control, though it'll still be truncated if the value
size is bigger than the preallocated buffer.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
2024-01-19 10:57:36 +08:00
Quentin Schulz
56bb09f502 rockchip: ringneck-px30/puma-rk3399: factor out storage medium selection
Ringneck PX30 and Puma RK3399 both have the same expectation with regard
to bootstd device order and U-Boot environment storage device, except
that Puma RK3399 also supports SPI Flash.

Let's move all of this into a common file where common logic can be put.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-01-19 10:57:36 +08:00
Quentin Schulz
6fdcf00605 rockchip: puma-rk3399: do not hardcode MMC controller paths
To prepare to put the similar logic around storage medium selection for
Ringneck PX30 and Puma RK3399 in common, let's not use hardcoded paths
but use uclass functions instead to find udevice based on their DT node
full path.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-01-19 10:57:36 +08:00
Quentin Schulz
796bc7d0f3 rockchip: ringneck-px30: do not hardcode MMC controller paths
To prepare to put the similar logic around storage medium selection for
Ringneck PX30 and Puma RK3399 in common, let's not use hardcoded paths
but use uclass functions instead to find udevice based on their DT node
full path.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-01-19 10:57:36 +08:00
Joshua Riek
153ac950a5 board: rockchip: Add the Turing RK1 SoM
The Turing RK1 is a Rockchip RK3588 based SoM from Turing Machines.

Specifications:

    Rockchip RK3588 SoC
    4x ARM Cortex-A76, 4x ARM Cortex-A55
    8/16/32GB memory LPDDR4x
    Mali G610MC4 GPU
    32GB eMMC HS400
    2x USB 2.0, 2x USB 3.0
    2x MIPI CSI 4x lanes
    1x MIPI-DSI DPHY 2x lanes
    PCIe 2.0 x1, PCIe 3.0 x4
    1x HDMI 2.1 output, 1x DP 1.4 output
    Gigabit Ethernet
    Size: 69.6mm x 45mm (260-pin SO-DIMM connector)

Kernel commit:
2806a69f3fef ("arm64: dts: rockchip: Add Turing RK1 SoM support")

Signed-off-by: Joshua Riek <jjriek@verizon.net>
Tested-by: Sam Edwards <CFSworks@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-01-19 10:57:36 +08:00
Jonas Karlman
595a7184e5 rockchip: rk3588s-orangepi-5: Build SPI image
Enable building of the SPI image, u-boot-rockchip-spi.bin, now that we
know what bootsource id values BootRom use for SPI flash on RK3588.

Fixes: 28c5f941ed ("board: rockchip: Add Xunlong Orange Pi 5")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-01-19 10:57:36 +08:00
Slawomir Stepien
7c084fd51c rockchip: rk3588-orangepi-5-plus: Build SPI image
Enable building of the SPI image, u-boot-rockchip-spi.bin, now that we
know what bootsource id values BootRom use for SPI flash on RK3588.

Fixes: b51cf8bb09 ("board: rockchip: Add Xunlong Orange Pi 5 Plus")
Signed-off-by: Slawomir Stepien <sst@poczta.fm>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-01-19 10:57:36 +08:00
John Clark
cb35cbdb93 rockchip: rk3588-nanopc-t6: Build SPI image
Enable building of the SPI image, u-boot-rockchip-spi.bin, now that we
know what bootsource id values BootRom use for SPI flash on RK3588.

Fixes: b0b8086898 ("board: rockchip: add FriendlyElec NanoPC-T6 rk3588 board")
Signed-off-by: John Clark <inindev@gmail.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-01-19 10:57:36 +08:00
Jonas Karlman
0d5104cdb7 rockchip: rk3588: Fix boot from SPI flash
The commit fd6e425be2 ("rockchip: rk3588-rock-5b: Enable boot from SPI
NOR flash") added a new BROM_BOOTSOURCE_SPINOR_RK3588 with value 6.

At the time the reason for this new bootsource id value 6 was unknown.

We now know that the BootRom on RK3588 use different bootsource id
values depending on the iomux used by the flash spi controller, and not
by the type of spi nor or spi nand flash used.

Add the following enum values and use them for RK3588 boot_devices.

- BROM_BOOTSOURCE_FSPI_M0 = 3
- BROM_BOOTSOURCE_FSPI_M1 = 4
- BROM_BOOTSOURCE_FSPI_M2 = 6

Fixes: fd6e425be2 ("rockchip: rk3588-rock-5b: Enable boot from SPI NOR flash")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Tested-by: Slawomir Stepien <sst@poczta.fm>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-01-19 10:57:36 +08:00
Tianling Shen
0bc16c6a87 board: rockchip: Add support for FriendlyARM NanoPi R2C Plus
The NanoPi R2C Plus is a small variant of NanoPi R2C with a on-board
eMMC flash (8G) included.

The device tree is taken from the kernel v6.5.

Signed-off-by: Tianling Shen <cnsztl@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-01-19 10:57:36 +08:00
Johan Jonker
b5db04c63a arm: dts: rockchip: rk3288: move to 64 bit reg size
To make automatic Rockchip DT syncing possible from Linux to U-boot prepare
rk3288.dtsi by moving to 64 bit reg size.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-01-19 10:57:36 +08:00
Hugh Cole-Baker
69b73877f0 rockchip: rk35xx: expand space for decompressed kernel
An uncompressed 6.7.0-rc1 Linux kernel Image built with the arm64
defconfig is about 40MB. This does not fit in to the space between
kernel_comp_addr_r and fdt_addr_r, so when uncompressing an Image.gz
to this size, the FDT will be overwritten. Rearrange addresses to have
128MiB for the kernel and its decompression buffer, then devicetree,
overlay and ramdisk at the end.

Signed-off-by: Hugh Cole-Baker <sigmaris@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-01-19 10:57:36 +08:00
Jonas Karlman
bcbd9a6f5c rockchip: board: Remove dwc3 usb init and gadget handler functions
Remove board_usb_init() and dm_usb_gadget_handle_interrupts() functions
related to dwc3, they use e.g. a hard-coded reg address for RK3399 and
are obsolete with use of DM_USB_GADGET.

Use of DM_USB_GADGET, USB_DWC3_GENERIC and USB_DWC3_GADGET have replaced
same feature provided by the removed functions on RK3399 boards.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-01-19 10:57:36 +08:00
Jonas Karlman
e1f83dd592 configs: rockchip: Use dwc3-generic driver on RK3328 and RK3399
Complete the transition away from xhci-dwc3 and dwc3-of-simple drivers
and change to use the dwc3-generic driver on remaining RK3328 and RK3399
boards.

MISC, USB_DWC3 and USB_DWC3_GENERIC is enabled on boards that used to
enable USB_XHCI_DWC3. USB_XHCI_DWC3 is dropped from updated boards along
with the default y of USB_XHCI_DWC3_OF_SIMPLE.

There is no intended change in functionality with this changes, USB 3.0
is expected to continue same as before this change.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-01-19 10:57:36 +08:00
Anthony Loiseau
46371f2699 get_maintainer.pl: slightly modify penguin_chief
Penguin chiefs are actually stripped out from get_maintainer results unless
--git-chief-penguins is provided, which appends them to all results instead.

This is a issue for U-Boot since Tom Rini (penguin chief) is also maintainer
of some sub-trees ("ARM", "ARM TI" and "THE REST").

Hopefully, this match is performed case-senditive over name and email,
therefore upper-casing Tom Rini last name workarounds the issue.

Important note: This also fixes "THE REST" catch all section resulting
in Tom Rini listed as (maintainer:THE REST) for all files. Hope there is not
too much developers scripting their patch email header from get_maintainer.pl
output, otherwise Tom Rini may be flooded.

Cc: Tom Rini <trini@konsulko.com>
Signed-off-by: Anthony Loiseau <anthony.loiseau@allcircuits.com>
2024-01-18 20:24:13 -05:00
Ilias Apalodimas
b6488caa1f smbios: fix matching issues for table types
commit 738b34668f ("smbios: Fallback to the default DT if sysinfo nodes are missing")
allowed the code to fallback and fill in SMBIOS tables with properties
from the compatible and product nodes of the DT, in case the
'smbios,sysinfo' node is missing.
That works fine for Type1/2 tables, but for other types we need to
match the smbios,sysinfo subnode name as well. So add it to the
smbios_ctx and check it during the sysinfo <-> DT mathcing

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-01-18 20:24:13 -05:00
Ilias Apalodimas
5e2b472bd0 smbios: shorten sysinfo_str declarations and use
sysinfo_str is a bit too long and makes indentation weird. Shorten it
to si_str.

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-01-18 20:24:13 -05:00
Ivan Orlov
cf536daeed cmd: license: Add CONFIG_GZIP dependency
'License' command processing code could be successfully compiled only
when CONFIG_GZIP option is enabled, otherwise it can't find the 'gunzip'
function definition (it is defined in lib/gunzip.c).

Add CONFIG_GZIP dependency to 'license' command config option in the
corresponding Kconfig.

Signed-off-by: Ivan Orlov <ivan.orlov@codethink.co.uk>
2024-01-18 20:24:13 -05:00
Heinrich Schuchardt
0afee2623d cmd: bootflow: remove dead code in do_bootflow_cmdline()
Checking argc < 3 twice is redundant.

Addresses-Coverity-ID: 477198 Logically dead code
Fixes: 921f63e572 ("bootflow: Allow setting a cmdline arg with no value")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-01-18 20:24:13 -05:00
Heinrich Schuchardt
ccefbf320d smbios: buffer overflow when zeroing entry point
A SMBIOS 3 entry point has a different length than an SMBIOS 2.1 entry
point.

Fixes: 70924294f3 ("smbios: Use SMBIOS 3.0 to support an address above 4GB")
Fixes: 1c5f6fa388 ("smbios: Drop support for SMBIOS2 tables")
Addresses-Coverity-ID: 477212 ("Wrong sizeof argument")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-01-18 20:24:13 -05:00
Moritz Fischer
85946d69d6 nvme: Update nvme_scan_namespace to keep trying on busy
A busy controller shouldn't be game-over for all controllers,
so keep trying on hitting -EBUSY.

This change brings the actual behavior of the routine in line
with what the descriptions says.

Fixes: 982388eaa9 ("nvme: Add NVM Express driver support")
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Moritz Fischer <moritzf@google.com>
2024-01-18 20:24:13 -05:00
Moritz Fischer
5775b0f787 nvme: Fix error code and log to indicate busy
Return -EBUSY if controller is found busy rather than -ENOMEM
and update the error message accordingly.

Fixes: 982388eaa9 ("nvme: Add NVM Express driver support")
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Moritz Fischer <moritzf@google.com>
2024-01-18 20:24:13 -05:00
Moritz Fischer
0408347034 drivers: pci: Fix dm_pci_map_bar() to support 64b BARs
This enables 64b BARs if CONFIG_SYS_PCI_64BIT is enabled.

Reviewed-by: Philip Oberfichtner <pro@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Moritz Fischer <moritzf@google.com>
2024-01-18 20:24:13 -05:00
Tom Rini
21a2c129ad getchar(): Correct usage
The function getchar() returns an 'int' and not a 'char'. Coverity notes
that "Assigning the return value of getchar to char ... truncates its value."
and so for the most part we can resolve this easily by using 'int' as
intended, and often used throughout the codebase. A few places are not
so simple and would require further re-architecting of the code in order
to change this, so we leave them be.

Signed-off-by: Tom Rini <trini@konsulko.com>
2024-01-18 20:24:13 -05:00
Love Kumar
bded9f13b2 test/py: bootstage: Add test for bootstage command
Add test cases for bootstage command to print the bootstage report, to
stash the data into memory and to unstash the data from memory.

Signed-off-by: Love Kumar <love.kumar@amd.com>
2024-01-18 20:24:12 -05:00
Sekhar Nori
22d238f25d arch: mach-k3: Fix incorrect mapping of higher DDR addresses as device memory
Entry for physical address 0x500000000 in memory map table for MMU
configuration is spilling over and inadvertently making DDR available at
higher address (above 4GB address space) get mapped as device memory
(nGnRnE).

Fix this by adjusting entry size. Tested on AM62A SK. Before this patch:

=> time crc32 0x881000000 0x20000000
crc32 for 881000000 ... 8a0ffffff ==> 7f34d7ca

time: 1 minutes, 14.716 seconds

After patch:

=> time crc32 0x881000000 0x20000000
crc32 for 881000000 ... 8a0ffffff ==> 7f34d7ca

time: 2.710 seconds

Acked-by: Andrew Davis <afd@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
2024-01-18 20:24:12 -05:00
Tobias Deiminger
2d30b293c8 test: Skip cleanup test if not built out of tree
With commit 42c0e5bb05 ("test: Find leftovers after clean/mrproper")
we assume that we are performing out of tree builds. test_clean and
test_mrproper fail if the assumption isn't met.

However there are valid scenarios where tests run with in source builds
(i.e., test.py --build-dir=.).

Automatically skip cleanup tests in such scenarios to prevent false
positives.

Signed-off-by: Tobias Deiminger <tdmg@linutronix.de>
Reviewed-by: Harald Seiler <u-boot@rahix.de>
2024-01-18 20:23:37 -05:00
Ivan Orlov
3c3270b569 cmd: nvedit: Fix typo in 'illegal character' error
Fix a typo: add a space after the single quote in 'illegal character'
error message in 'env set' command

Signed-off-by: Ivan Orlov <ivan.orlov@codethink.co.uk>
2024-01-18 17:50:27 -05:00
Hugo Cornelis
bc01d9ff93 image-host: refactor and protect for very long filenames
This patch adds a function fit_image_read_key_iv_data that checks the
return value of snprintf and allows to generate a sensible error
message when generating binary images using filenames that are too
long for the OS to handle.

This is especially relevant for automated builds such as Buildroot and
Yocto builds.

Signed-off-by: Hugo Cornelis <hugo.cornelis@essensium.com>
2024-01-18 17:50:27 -05:00
Roger Quadros
9ba8187a84 board: ti: am64: Support TMDS64EVM
The TMDS64EVM [1] ships with AM64X SR2.0 HS-FS chip
and a slightly different board name in the board information
EEPROM header. Support this board.

[1] https://www.ti.com/tool/TMDS64EVM

Gets rid of below message at boot
"Unidentified board claims AM64-EVM in eeprom header"

Signed-off-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Nishanth Menon <nm@ti.com>
2024-01-18 17:50:27 -05:00
Manorit Chawdhry
27cc5951c8 include: env: ti: add default for do_main_cpsw0_qsgmii_phyinit
By default this variable is unset and this causes the test condition to
fail on devices that don't have this defined. Set a default value for
this.

   => boot
   ## Error: "main_cpsw0_qsgmii_phyinit" not defined
   [...]

Fixes: 0d72b0f2f8 ("include: env: ti: ti_common: Run main_cpsw0_qsgmii_phyinit conditionally")

Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
2024-01-18 17:50:27 -05:00
Manorit Chawdhry
a99d652ff1 include: env: ti: ti_common: Fix a missing semicolon
Fix a missing semicolon that leads to syntax error while booting j721s2.

    Importing environment from mmc1 ...
    syntax error at 'run'HUSH died!

Fixes: 0d72b0f2f8 ("include: env: ti: ti_common: Run main_cpsw0_qsgmii_phyinit conditionally")

Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
2024-01-18 17:50:27 -05:00
Heinrich Schuchardt
3a7744ed1e boot: superfluous assignment in bootflow_menu_new()
ret is assigned a value 0 which is never used but
is immediately overwritten in the next statement.

Addresses-Coverity-ID: 453304 ("Unused value")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-01-18 17:50:27 -05:00
Heinrich Schuchardt
3f9312236a boot: remove dead code in bootflow_check()
The 'return 0;' statement is not reachable. Remove it.
'else' is superfluous after an if statement with return.

Addresses-Coverity-ID: 352451 ("Logically dead code")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-01-18 17:50:27 -05:00
Csókás Bence
f055d6e8f0 lib: rsa: Allow legacy URI specification without "pkcs11:"
But emit a warning for it. Then we can remove support when
everyone had time to update their scripts, docs, CI etc.

Fixes: ece85cc020 rsa: use pkcs11 uri as defined in rfc7512

Signed-off-by: Csókás Bence <csokas.bence@prolan.hu>
2024-01-18 17:50:27 -05:00
Csókás Bence
11ad2bbfa2 lib: rsa: Fix PKCS11 URI if one is not given in keydir
If `keydir` is not present, we need to build a PKCS11 URI
from just the key name. In this case, we *do* need 'pkcs11:'

Fixes: ece85cc020 rsa: use pkcs11 uri as defined in rfc7512

Signed-off-by: Csókás Bence <csokas.bence@prolan.hu>
2024-01-18 17:50:27 -05:00
Neha Malcom Francis
10fee88d42 tools: binman: ti_board_cfg: Check for linting problems
Use yamllint for checking whether YAML configuration files are adhering
to default yamllint rules.

Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Suggested-by: Nishanth Menon <nm@ti.com>
2024-01-18 17:50:27 -05:00
Neha Malcom Francis
0cc7a701e9 board: ti: *-cfg.yaml: Adhere to yamllint rules
Clean up all configuration files to adhere to yamllint rules.

Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
[trini: Update more yaml files added since this was posted]
Signed-off-by: Tom Rini <trini@konsulko.com>
Suggested-by: Nishanth Menon <nm@ti.com>
2024-01-18 17:50:26 -05:00
Caleb Connolly
b185618011 iommu: dont fail silently
When attempting to probe a device which has an associated IOMMU, if the
IOMMU device can't be found (no driver, disabled driver, driver failed
to probe, etc) then we currently fail to probe the device with no
discernable error.

If we fail to hook the device up to its IOMMU, we should make sure that
the user knows about it. Write some better error messages for
dev_iommu_enable() to facilitate this.

Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-01-18 12:18:48 -05:00
Caleb Connolly
9d92c418ac bootdev: avoid infinite probe loop
Sometimes, when only one bootdev is available, and it fails to probe, we
end up in an infinite loop calling probe() on the same device over and
over. With only debug level log output.

Break the loop if we fail to probe the same device twice in a row, and
promote the probe failure message to log_warning().

Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Dragan Simic <dsimic@manjaro.org>
2024-01-18 12:18:48 -05:00
Tom Rini
f7cca7ccc5 Revert "test: hush: dollar: fix bugous behavior"
What we were doing here amounts to simplifying the code for the new hush
parser, and the workarounds are required when using the old one. As we
have returned to having the old parser be default for now, we must undo
this so that the test passes again.

This reverts commit 6c2f753f4a.

Signed-off-by: Tom Rini <trini@konsulko.com>
2024-01-18 11:38:25 -05:00
Tom Rini
3c3a73424e Revert "cmd: Set modern hush as default shell"
Currently at least two SoC families are able to cause a crash using
their regular boot scripts, with the new parser.  For now, revert to the
old parser as default.

This reverts commit 78912cfde2.

Signed-off-by: Tom Rini <trini@konsulko.com>
2024-01-18 09:07:25 -05:00
Tom Rini
5b3cd0f31d Revert "test/py: net: Add dhcp abort test"
In practice, as this test defaults to enabled rather than disabled, too
many platforms now fail.

This reverts commit d836473862.

Signed-off-by: Tom Rini <trini@konsulko.com>
2024-01-18 09:05:38 -05:00
Tom Rini
b8f7b374bc CI: Move to latest Ubuntu "Jammy" tag
Move to the latest "Jammy" tag from Ubuntu.

Signed-off-by: Tom Rini <trini@konsulko.com>
2024-01-18 09:04:34 -05:00
Tom Rini
1858bebeaf test: test_trace.py: Have trace-cmd report always use -l
With newer versions of trace-cmd the report subcommand will have
different output from before if we do or do not pass -l. However, with
the -l flag passed our put is consistent here. This updates our regular
expressions and comments for this as well now.

Signed-off-by: Tom Rini <trini@konsulko.com>
2024-01-18 09:04:34 -05:00
Tom Rini
662eade79e test/py/requirements.txt: Update packaging requirement
Update packaging to be version 23.2 to match our Sphinx requirements.
This will let us build a pip cache out of both of our requirements.txt
files.

Signed-off-by: Tom Rini <trini@konsulko.com>
2024-01-17 15:24:22 -05:00
Heinrich Schuchardt
50a907edbb docker: build QEMU v8.2.0
ACPI support for RISC-V requires a recent QEMU.

Upgrade the used QEMU to v8.2.0.

QEMU commit 0c7ffc977195 ("hw/net: cadence_gem: Fix MDIO_OP_xxx values")
is needed to fix the Ethernet PHY driver used by the emulated SiFive
Unleashed Board emulation.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-01-17 14:37:00 -05:00
Tom Rini
002764d739 Merge tag 'xilinx-for-v2024.04-rc1-v2' of https://source.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2024.04-rc1-v2

xilinx:
- Enable NFS, WGET, DNS and BLKMAP by default

zynqmp:
- Support new power-management node
- Remove multiple blank lines from DTSes
- Wire multiboot with DFU infrastructure
- Fix i2c-gpio pinctrl group name
- SOM DT changes (phy on kd240, kv260 cleanups
- Cleanup i2c bus on zcu1285
- DT cleanup (fix node names not to use _)
- Fix USB interrupts
- Cleanup zcu100 DT
- Add support for kaslr-seed

zynqmp_r5:
- Fix W=1 issue with missing dir

tools:
- Improve zynqmpimage mkimage support
2024-01-17 09:27:43 -05:00
Tom Rini
bdaa0b27b3 Merge tag 'efi-2024-04-rc1-2' of https://source.denx.de/u-boot/custodians/u-boot-efi
Documentation:

* add generated index to table of contents
* create index entries for commands
* update Python packages used to build the documentation
* fix typos in dfu documentation

UEFI:

* split unrelated code from efi_bootmgr.c
* rename CONFIG_BOOTEFI_BOOTMGR to CONFIG_EFI_BOOTMGR
* net: tftp: remove explicit EFI configuration dependency
* fs: remove explicit EFI configuration dependency

Other:

* Add Goldfish RTC driver and make it available on RISC-V QEMU
2024-01-17 09:27:23 -05:00
Tom Rini
106332d6cc Merge branch '2024-01-16-assorted-updates-and-improvements'
- Add more pytests to exercise functionality on real hardware, cleanup
  and add tests around "cp"/memmove, add phyCORE-AM62x and Phytium
  Pe2201 platforms, Nuvoton NPCM BMC reset driver and improve QEMU
  SMBIOS support
2024-01-17 09:12:27 -05:00
Tom Rini
a300ac3851 test.py: Update pycryptodomex to address CVE-2023-52323
The version of pycryptodomex that we use is vulnerable to this CVE.
While not likely an issue for us, let us upgrade to be on the safe side.

Reported-by: GitHub dependabot
Signed-off-by: Tom Rini <trini@konsulko.com>
2024-01-17 08:00:07 -05:00
Rasmus Villemoes
994f1cecc1 doc: drop references to non-existing CONFIG_MEM_SUPPORT_64BIT_DATA
Such a config option does not exist. Rephrase, and avoid mentioning
MEM_SUPPORT_64BIT_DATA, which is an implementation detail.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2024-01-17 08:00:07 -05:00
Rasmus Villemoes
d060c49afe README: drop mention of MEM_SUPPORT_64BIT_DATA
The first sentence is half-way true; the macro is always defined, but
has the value 0 or 1.

The second is outright false. A lot of code guarded by
MEM_SUPPORT_64BIT_DATA uses a "ulong" to store values, so if
sizeof(long) is not 8, that code would probably compile, but not work
at all as expected.

It would probably be possible to make all such code explicitly use u64
and thus make it work on 32 bit targets, but until that is done, do
not pretend that it's ok to override the automatic value of
MEM_SUPPORT_64BIT_DATA.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2024-01-17 08:00:07 -05:00
Rasmus Villemoes
4762c51562 cmd/mem.c: fix wrong use of ifdef, drop pointless SUPPORT_64BIT_DATA macro
The macro MEM_SUPPORT_64BIT_DATA is always defined, as either 1 or 0,
so using "#ifdef MEM_SUPPORT_64BIT_DATA" doesn't do what one
expects.

This means that currently all 32 bit targets get compiled with the .q
suffix mentioned in the help text, while it doesn't actually work.

Use the proper "#if" instead.

There's really no point defining another similarly-named macro with
exactly the same value, so just use MEM_SUPPORT_64BIT_DATA throughout.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2024-01-17 08:00:07 -05:00
Rasmus Villemoes
13f4c85828 test: add test of "cp" shell command
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2024-01-17 08:00:05 -05:00
Heinrich Schuchardt
21c856797e riscv: qemu: imply GOLDFISH_RTC
QEMU's virt board provides an emulated Goldfish RTC. Enable the driver by
default.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-01-17 09:03:43 +01:00
Heinrich Schuchardt
2d6dc19fd2 rtc: driver for Goldfish RTC
The Goldfish RTC is a virtual device which may be supplied by QEMU.
It is enabled by default on QEMU's RISC-V virt machine.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-01-17 09:03:43 +01:00
AKASHI Takahiro
467979b672 fs: remove explicit efi configuration dependency
Now it is clear that the feature actually depends on efi interfaces,
not "bootefi" command. efi_set_bootdev() will automatically be nullified
if necessary efi component is disabled.

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2024-01-17 08:40:25 +01:00
AKASHI Takahiro
593607c581 net: tftp: remove explicit efi configuration dependency
Now it is clear that the feature actually depends on efi interfaces,
not "bootefi" command. efi_set_bootdev() will automatically be nullified
if necessary efi component is disabled.

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2024-01-17 08:40:25 +01:00
AKASHI Takahiro
279b03d979 efi_loader: rename BOOTEFI_BOOTMGR to EFI_BOOTMGR
At this point, EFI boot manager interfaces is fully independent from
bootefi command. So just rename the configuration parameter.

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2024-01-17 08:40:25 +01:00
AKASHI Takahiro
6422820ac3 efi_loader: split unrelated code from efi_bootmgr.c
Some code moved from cmd/bootefi.c is actually necessary only for "bootefi
<addr>" command (starting an image manually loaded by a user using U-Boot
load commands or other methods (like JTAG debugger).

The code will never been opted out as unused code by a compiler which
doesn't know how EFI boot manager is implemented. So introduce a new
configuration, CONFIG_EFI_BINARY_EXEC, to enforce them opted out
explicitly.

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
2024-01-17 08:40:25 +01:00
Heinrich Schuchardt
0ab829d4de doc: update requirements.txt
Update requirements.txt to most current packages as produced by

   python3 -m pip install six sphinx-rtd-theme sphinx-prompt
   python3 -m pip freeze

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2024-01-17 08:40:19 +01:00
Heinrich Schuchardt
479edbaf89 doc: import Sphinx theme.css and pygments.css
We want to override the Sphinx theme only partially. So we need to
import the Sphinx theme.css. Cf.
https://docs.readthedocs.io/en/stable/guides/adding-custom-css.html

We also need to import the pygments.css for syntax highlighing.

Use sans-serif for body.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-01-17 08:40:19 +01:00
Heinrich Schuchardt
0c098a5136 doc: update theme_overrides.css
Update theme_overrides.css from Linux v6.7.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-01-17 08:40:19 +01:00
Heinrich Schuchardt
31a221d3f2 doc: add sphinx_rtd_theme extension
Newer versions of sphinx_rtd_theme require to add sphinx_rtd_theme to the
list of extensions. Cf.
https://github.com/readthedocs/readthedocs.org/pull/9654

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-01-17 08:40:19 +01:00
Oliver Faso
f5209829af docs/sphinx: Explicitly convert Sphinx paths to str
Sphinx 7.2+ is switching to using pathlib.Path
instead of str to represent paths. This fixes the
current deprecation warnings and eventual breakage.
This conversion will be a no-op when using older
Sphinx versions.

Signed-off-by: Oliver Faso <erer1243@gmail.com>
Tested-by: Akira Yokosawa <akiyks@gmail.com>
Signed-off-by: Jonathan Corbet <corbet@lwn.net>
Link: https://lore.kernel.org/r/20230910040811.53046-1-erer1243@gmail.com
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-01-17 08:40:19 +01:00
Heinrich Schuchardt
60971e63e6 doc: create index entries for commands
Add the description of CLI commands to the generated index.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-01-17 08:40:19 +01:00
Heinrich Schuchardt
93d1721bd1 doc: add generated index to table of contents
Show the index in the navigation sidebar.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-01-17 08:40:19 +01:00
Mattijs Korpershoek
a1c57be712 doc: dfu: fix a handful of typos
Reword some sentences, add missing periods and fix various typos in the
dfu documentation.

This was originally contributed on [1]

[1] 9a21ed8ba7

Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
2024-01-17 08:40:19 +01:00
Venkatesh Yadav Abbarapu
0a4595b538 configs: zynqmp_kria: Enable CONFIG_OF_BOARD_SETUP
Enable CONFIG_OF_BOARD_SETUP, so we could use ft_board_setup()
to enable the kaslr-seed and pass to kernel.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20240117032014.1014084-3-venkatesh.abbarapu@amd.com
2024-01-17 08:12:21 +01:00
Venkatesh Yadav Abbarapu
a270099e83 xilinx: board: Update the kaslr-seed property
Create a ft_board_setup() api that gets called as part
of bootm/booti before jumping to kernel. In this
ft_board_setup() callback that will inspect the DTB
and insert the device tree blob with the "kaslr-seed" property.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20240117032014.1014084-2-venkatesh.abbarapu@amd.com
2024-01-17 08:12:20 +01:00
Rasmus Villemoes
92fa22a1bb cmd/command.c: relax length check in cmd_get_data_size()
Just check that the length is at least 2. This allows passing strings
like ".b", which can be convenient when constructing
tests (i.e. parametrizing the suffix used).

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2024-01-16 17:05:29 -05:00
Rasmus Villemoes
48f31ee742 cmd/command.c: constify "arg" argument of cmd_get_data_size()
This function obviously does not and must not modify "arg". Change the
prototype to allow passing an argument of type "const char*" without
requiring a cast.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2024-01-16 17:05:29 -05:00
Rasmus Villemoes
88a5b32057 doc/usage/cmd/cp.rst: document that overlapping regions are supported
Now that the cp command is changed to use memmove() internally, update
the documentation to explicitly state that overlapping regions are
allowed.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2024-01-16 17:05:29 -05:00
Rasmus Villemoes
d631681e8c cmd/mem.c: use memmove in do_mem_cp()
There's no 'mv' shell command for handling overlapping src and dst
regions, and there's no point introducing one, when we can just make
the existing 'cp' command DTRT in all cases. memmove() should at most
be a few instructions more then memcpy() (to detect the appropriate
direction to do the copy), which is of course completely in the noise
with all the string processing that a shell command does.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2024-01-16 17:05:29 -05:00
Love Kumar
22efc1cf27 test/py: memtest: Add tests for mtest command
Add the following memory tests:
memtest_negative - To test mtest command by providing incorrect inputs
memtest_ddr - To test memory write-read-comparision for DDR memory

Signed-off-by: Love Kumar <love.kumar@amd.com>
2024-01-16 17:05:29 -05:00
Jim Liu
883a7a982a reset: npcm: Add support for Nuvoton NPCM BMC family
Add reset controller driver for Nuvoton BMCs.
The npcm reset driver not only supports reset each module reset
but setting initial value of reset Control Registers.

And The driver support each module reset.

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2024-01-16 17:05:29 -05:00
Love Kumar
9b8b0431ea test/py: i2c: Add tests for i2c command
Add below test cases for i2c commands:
i2c_bus - To show i2c bus info,
i2c_dev - To set or show the current bus,
i2c_probe - To probe the i2c device,
i2c_eeprom - To test i2c eeprom device,
i2c_probe_all_buses - To list down all the buses and probes it

Signed-off-by: Love Kumar <love.kumar@amd.com>
2024-01-16 17:05:29 -05:00
Love Kumar
f0d6e29f97 test/py: mii: Add tests for mii command
Add below test cases for mii commands:
mii_info -To display MII PHY info
mii_list - To list MII devices
mii_set_device - To set MII device
mii_read - To reads register from MII PHY address
mii_dump - To display data from MII PHY address

Signed-off-by: Love Kumar <love.kumar@amd.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2024-01-16 17:05:29 -05:00
TracyMg_Li
e6a8c6f5c0 ARM add initial support for the Phytium Pe2201 Board.
Add pe2201 platform code and the device tree of pe2201 platform board.
The initial support comprises the UART and PCIe.

Signed-off-by: TracyMg_Li <TracyMg_Li@outlook.com>
Changes since v1:
        fix space corrupt.
Changes since v2:
        switch to bootstd and text environment.
Changes since v3:
        add environment variables.
2024-01-16 17:05:29 -05:00
Heinrich Schuchardt
ddcfb9ede8 lib: smbios: remove redundant next_header()
next_header() and get_next_header() only differ in how the const attribute
is used. One function taking a const parameter and returning a non-const is
good enough.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-01-16 17:05:29 -05:00
Heinrich Schuchardt
1c5aab803c smbios: copy QEMU tables
QEMU provides SMBIOS tables with detailed information. We should not try to
replicate them in U-Boot.

If we want to inform about U-Boot, we can add a Firmware Inventory
Information (type 45) table in future.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2024-01-16 17:05:29 -05:00
Neha Malcom Francis
481ffca485 arm: dts: k3-j721e-binman: Add support for HS-SE 2.0
Add support for J721E HS-SE 2.0 device. Make use of the existing
templates and override the phandles for sysfw.itb so that builds do not
fail.

Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
2024-01-16 12:01:16 -05:00
Wadim Egorov
aa048fa686 doc: board: phytec: Add phyCORE-AM62x
Add documentation for PHYTEC phyCORE-AM62x SoM.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
2024-01-16 12:01:16 -05:00
Wadim Egorov
085cd6459d board: phytec: am62x: Add PHYTEC phyCORE-AM62x SoM
Add basic support for PHYTEC phyCORE-AM62x SoM.

Supported features:
  - 2GB DDR4 RAM
  - eMMC Flash
  - OSPI NOR Flash
  - external uSD
  - Ethernet
  - debug UART

Product page SoM: https://www.phytec.com/product/phycore-am62x

Device trees were taken from Linux v6.7-rc3.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
2024-01-16 12:00:05 -05:00
Love Kumar
53157bfa99 test/py: mdio: Add tests for mdio command
Add below test cases for mdio commands:
mdio_list - To list MDIO buses
mdio_read - To read PHY's register at <devad>.<reg>
mdio_write - To write PHY's register at <devad>.<reg>

Signed-off-by: Love Kumar <love.kumar@amd.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2024-01-16 12:00:05 -05:00
Love Kumar
d836473862 test/py: net: Add dhcp abort test
Abort the dhcp request in the middle by pressing ctrl + c on u-boot
prompt and validate the abort status.

Signed-off-by: Love Kumar <love.kumar@amd.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2024-01-16 12:00:05 -05:00
Tom Rini
043ca8c8a9 Merge tag 'qcom-2024.04-rc1' of https://gitlab.denx.de/u-boot/custodians/u-boot-snapdragon
Qualcomm architecture changes:

* Move clock and pinctrl drivers out of mach-snapdragon
* Various clock driver improvements
* Convert PMIC power/reset key driver to use the button API
* Preparetory work for migrating to upstream DT
2024-01-16 09:51:16 -05:00
Tom Rini
6ca9349b67 Merge tag 'u-boot-imx-20240115' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx 2024-01-16 09:49:48 -05:00
Caleb Connolly
4c3dfa1b8b sandbox_flattree: enable button support
sandbox_flattree enables QCOM_PMIC_GPIO which now depends on BUTTON. As
a result the button tests now get run, but fail because the ADC and GPIO
button drivers aren't enabled.

Enable them to run the tests for sandbox_flattree.

Reported-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-01-16 12:26:54 +00:00
Caleb Connolly
4d6d25be5f test: spmi: fix tests
With the recent changes to the Qualcomm PMIC GPIO driver the sandbox
tests for it no longer pass, update the DTS and tests to work with the
changes.

Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-01-16 12:26:54 +00:00
Caleb Connolly
64550c7f4d pmic: qcom: dont use dev_read_addr to get USID
Linux DTs stuff a value indicating if the USID is a USID or a GSID in the
reg property, the Linux SPMI driver then reads the two address cells
separately. U-boot's dev_read_addr() doesn't know how to handle this, so
use ofnode_read_u32_index() to get just the USID.

The Qcom pmic driver doesn't have support for GSID handling, so just
ignore the second value for now.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Tested-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-01-16 12:26:54 +00:00
Caleb Connolly
92fe08921c spmi: msm: fix register range names
The core and chnl register ranges were swapped on SDM845. Fix it, and
fetch the register ranges by name instead of by index.

Drop the cosmetic "version" variable and clean up the debug logging.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Tested-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-01-16 12:26:54 +00:00
Caleb Connolly
f1d66ed728 gpio: qcom_pmic: drop gpio-count property
This property is not part of the dt bindings and all boards use the new
gpio-ranges property instead. Drop support for this.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Tested-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-01-16 12:26:53 +00:00
Caleb Connolly
a712ececbd dts: qcom: adjust pmic gpio to use upstream bindings
Use the upstream gpio-ranges property instead of gpio-count, and drop
the bank-name property for Qualcomm boards.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Tested-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-01-16 12:26:53 +00:00
Caleb Connolly
ab4214333d gpio: qcom_pmic: support upstream DT
Upstream uses the gpio-ranges property to define the number of GPIOs,
support for parsing this when gpio-count is unspecified

Additionally, drop the bank-name property as it isn't used in upstream,
and we can just hardcode the bank name instead.

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Tested-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-01-16 12:26:53 +00:00
Caleb Connolly
5415d5f0e7 gpio: qcom_pmic: drop pon GPIO driver
Remove the (now unused) GPIO driver for the power and resin buttons on
the PMIC.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Tested-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-01-16 12:26:53 +00:00
Caleb Connolly
b7f189541e mach-snapdragon: switch to PMIC button driver
The PMIC button driver is a much better representation of the hardware
here, adjust the boards to use upstream DT and the PMIC button driver
instead of exposing the buttons as GPIOs and relying on the GPIO-button
driver.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Tested-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-01-16 12:26:53 +00:00
Caleb Connolly
4e8aa0065d button: qcom-pmic: introduce Qualcomm PMIC button driver
Qualcomm PMICs include a "pon" function which handles two buttons, the
power button and "resin" button (usually volume down). Introduce a new
driver following upstream Linux DT to enable these and map them to Enter
and Down respectively to enable use in boot menus.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Tested-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-01-16 12:26:53 +00:00
Caleb Connolly
033f09b4b4 gpio: qcom_pmic: fix silent dev_read_addr downcast
priv->pid is uint32_t, but dev_read_addr() returns a uint64_t on arm64,
with the upper bits being used for error codes. Do error checking before
downcasting to u32 to prevent errors being silently ignored.

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Tested-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-01-16 12:26:53 +00:00
Caleb Connolly
a4ba2a6663 serial: msm-geni: handle devm_clk_get() errors
devm_clk_get() returns an ERR_PTR on failure, not null. Fix the check to
avoid the board crashing when the clock isn't available.

Additionally, add the missing error handling for this function.

Fixes: 324df15a29 ("serial: qcom: add support for GENI serial driver")
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-01-16 12:26:53 +00:00
Caleb Connolly
836b7f4474 serial: msm-geni: don't rely on parent misc device
commit 1b15483deb ("misc: add Qualcomm GENI SE QUP device driver")
introduced support for platform-specific oversampling values, necessary
to configure the UART clocks on all platforms at runtime. However it
relies in probing a parent device. Despite the DM_FLAG_PRE_RELOC flag,
this is not done consistently during boot.

Instead, take another approach by relying on ofnode_ helpers to read the
serial engine base address and do the read directly. This fixes early
UART on boards with a non-default oversampling rate.

Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-01-16 12:26:52 +00:00
Caleb Connolly
6156e39e42 msm_gpio: use unsigned int
Replaces the uses of "unsigned" with "unsigned int".

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-01-16 12:26:52 +00:00
Caleb Connolly
2c2cc3e9c0 pinctrl: qcom: make compatible with linux DTs
The pinctrl and GPIO drivers are currently heavily incompatible with
upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at
it's own address. Introduce support for these by allowing the soc driver
to specify per-pin register offsets similarly to the Linux driver.

Adjust the GPIO driver to handle these too, and finally enable support
for all pins with the same numbering as used in Linux.

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-01-16 12:26:52 +00:00
Caleb Connolly
24d2908e98 pinctrl: qcom: move ipq4019 driver from mach-ipq40xx
Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add
it to drivers/pinctrl/qcom.

Acked-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-01-16 12:26:49 +00:00
Caleb Connolly
53b2c7af69 pinctrl: qcom: move out of mach-snapdragon
Move the Qualcomm pinctrl drivers out of mach-snapdragon and over to the
rest of the pinctrl drivers, adjust the drivers so that support for each
platform can be enabled/disabled individually and introduce platform
specific configuration options.

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-01-16 12:26:24 +00:00
Caleb Connolly
d5db46cf93 clk/qcom: fix rcg divider value
The RCG divider field takes a value of (2*h - 1) where h is the divisor.
This allows fractional dividers to be supported by calculating them at
compile time using a macro.

However, the clk_rcg_set_rate_mnd() function was also performing the
calculation. Clean this all up and consistently use the F() macro to
calculate these at compile time and properly support fractional divisors.

Additionally, improve clk_bcr_update() to timeout with a warning rather
than hanging the board, and make the freq_tbl struct and helpers common
so that they can be reused by future platforms.

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-01-16 12:26:24 +00:00
Caleb Connolly
6acc44319b clk/qcom: add mnd_width to clk_rcg_set_rate_mnd()
This property is needed on some platforms to ensure that only the
relevant bits are set in the M/N/D registers.

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-01-16 12:26:24 +00:00
Caleb Connolly
37ea1343ac clk/qcom: use function pointers for enable and set_rate
Currently, it isn't possible to build clock drivers for more than one
platform due to how the msm_enable() and msm_set_rate() callbacks are
implemented.

Extend qcom_clk_data to include function pointers for these and convert
all platforms to use them.

Previously, clock drivers relied on include/configs/<board.h> to include the
board specific sysmap header, however as most of the header contents are clock
driver related, import the contents directly into each clock driver and
remove the header. The only exception here is the dragonboard820c board file
which includes some pinctrl macros, those are also inlined.

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
[caleb: remove additional sysmap-sdm845.h mention]
2024-01-16 12:26:24 +00:00
Caleb Connolly
0e7fec02ce clk/qcom: sdm845: add register map for simple gate clocks
Many gate clocks can be enabled with a single register write, add support
for defining these simple gate clocks and add the ones found on SDM845.

While we're here, inline clk_init_uart() into msm_set_rate().

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-01-16 12:26:24 +00:00
Konrad Dybcio
3ead661633 clk/qcom: handle resets and clocks in one device
Qualcomm's clock controller blocks actually do much more than it
says on the tin.. They provide clocks, resets and power domains.
Currently, U-Boot requires one to spawn 2 separate devices for
controlling clocks and resets, both spanning the same register space.
Refactor the code to make it work with just a single DT node, making
it compatible with upstream Linux bindings and dropping the dedicated
reset driver in favour of including it in the clock driver.

Heavily inspired by Renesas code for a similar hw block.

[caleb: moved drivers to clk/qcom, added reset driver and adjusted bind
logic. Imported qcom,gcc-ipq4019.h from Linux]

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-01-16 12:26:23 +00:00
Caleb Connolly
fac2121a47 clk/qcom: move ipq4019 driver from mach-ipq40xx
This driver is just a stub, but it's necessary to support the upcoming
reset driver changes.

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-01-16 12:26:23 +00:00
Caleb Connolly
a623c14f43 clk/qcom: move from mach-snapdragon
Clock drivers don't belong here, move them to the right place and
declutter mach-snapdragon a bit.

To de-couple these drivers from specific "target" platforms, add
additional config options to enable each clock driver gated behind a
common CLK_QCOM option and enable them by default for the respective
targets. This will make future work easier as we move towards a generic
Qualcomm target.

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-01-16 12:26:23 +00:00
Tom Rini
b9631fe781 Merge tag 'u-boot-nand-20240115' of https://source.denx.de/u-boot/custodians/u-boot-nand-flash
Pull request for u-boot-nand-20240115

The first patch is by Heinrich Schuchardt and fixes an integer overflow

The following two patches are by Dario Binacchi and add arguments check
to the nand_mtd_to_devnum() and nand_register() functions.

The remaining patches are by Roger Quadros and include various fixes for
the OMAP platform.
2024-01-15 09:29:57 -05:00
Anatolij Gustschin
662e7ef7f0 arm: xea: Add support for boot image source descriptor in SPL
We load two boot image source descriptor structures from last
two sectors in the SPI NOR flash and determine the boot source
for loading the kernel/DTB images, then adjust the boot order for
loading image from eMMC boot0 or boot1 partition.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Lukasz Majewski <lukma@denx.de>
2024-01-15 10:55:42 -03:00
Lukasz Majewski
decc451a85 arm: config: Enable CRC8 support in SPL on imx287 XEA board
The boot0/1 feature uses simple CRC8 to check (in SPL) if
SPI-NOR content is not corrupted, hence the need to enable
it.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2024-01-15 10:55:42 -03:00
Lukasz Majewski
dbde4c6155 arm: xea: Move XEA's environment variables from xea.h to xea.env
The default set of environment variables from CFG_EXTRA_ENV_SETTINGS
has been moved to a separate file - board/liebherr/xea/xea.env

Adjustments done:
- fitImage support
- SPI-NOR layout re-organization

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2024-01-15 10:55:42 -03:00
Yannic Moog
1aebea9bde board: phytec: fix link error when disabling PHYTEC_SOM_DETECTION
Commit aa7858fe5e ("board: phytec: som_detection: move definitions to
source file") moved function definitions from header to source file.
Makefile however was not updated to unconditionally (from
[..]_SOM_DETECTION) build the imx8 and phytec som detection units.
Also remove unused includes that cause build failures on arm 32bit
boards. SoM detection shall support 32bit boards as well, but arch
specific code should not be included in the generic module.

Fixes: aa7858fe5e ("board: phytec: som_detection: move definitions to source file")
Signed-off-by: Yannic Moog <y.moog@phytec.de>
2024-01-15 06:35:50 -03:00
Roger Quadros
4dfa08af79 arm: mach-k3: am642: Define NAND boot device
AM642 SoC supports booting from GPMC NAND device.
Define boot device for it.

Signed-off-by: Roger Quadros <rogerq@kernel.org>
Link: https://www.mail-archive.com/u-boot@lists.denx.de/msg499180.html
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2024-01-15 08:58:24 +01:00
Roger Quadros
e76959aba5 mtd: rawnand: omap_gpmc: fix OF based partition parsing for NAND
Set NAND chip ofnode and device so OF based partition parsing
can work.

Signed-off-by: Roger Quadros <rogerq@kernel.org>
Link: https://www.mail-archive.com/u-boot@lists.denx.de/msg499178.html
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2024-01-15 08:58:24 +01:00
Roger Quadros
dd01a229c8 mtd: rawnand: omap_gpmc: Use DT provided IO address
For DM case we can get the NAND chip's IO address from DT
so we don't need to rely on CFG_SYS_NAND_BASE.

Signed-off-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Link: https://www.mail-archive.com/u-boot@lists.denx.de/msg499177.html
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2024-01-15 08:58:24 +01:00
Roger Quadros
58d6f349e4 memory: ti-gpmc: Fix build
sys_proto.h no longer exists for K3 platform so drop it.
Include sizes.h to so SZ_16M is visible.

Signed-off-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Link: https://www.mail-archive.com/u-boot@lists.denx.de/msg499176.html
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2024-01-15 08:58:24 +01:00
Roger Quadros
f6e7d8d2f3 mtd: rawnand: omap_elm: Fix elm_init definition
The macro ELM_BASE is defined in mach/hardware.h and is
not visible at the omap_elm.h header file. Avoid using it
in omap_elm.h.

Reported-by: Hong Guan <hguan@ti.com>
Fixes: 7363cf0581 ("mtd: rawnand: omap_elm: u-boot driver model support")
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/all/20231211114600.4414-3-rogerq@kernel.org
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2024-01-15 08:58:24 +01:00
Roger Quadros
84e6fe3c04 mtd: nand: omap_gpmc: Fix NAND in SPL for AM335x
AM335x uses a special driver "am335x_spl_bch.c" as SPL
NAND loader. This driver expects 1 sector at a time ECC
and doesn't work well with multi-sector ECC that was implemented in
commit 04fcd25873 ("mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based correction")

Additionally, the omap_elm driver does not support multi sector ECC and will
need more work and tests to get multi sector working correctly on all
platforms.

Switch back to 1 sector at a time read/ECC.

Fixes: 04fcd25873 ("mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based correction")
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Tested-by: Enrico Leto <enrico.leto@siemens.com>
Tested-by: Heiko Schocher <hs@denx.de>
Link: https://lore.kernel.org/all/20231211114600.4414-2-rogerq@kernel.org/
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2024-01-15 08:58:24 +01:00
Dario Binacchi
cbfff3b123 mtd: nand: check nand_mtd_to_devnum() argument
If the "mtd" parameter is NULL, the search will definitely yield a
negative result. In that case, it's better to exit immediately.

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Link: https://lore.kernel.org/all/20231102113829.58852-1-dario.binacchi@amarulasolutions.com
2024-01-15 08:58:24 +01:00
Dario Binacchi
6b3d175928 mtd: nand: complete nand_register() arguments check
The patch checks that the "mtd" parameter is accessible before
proceeding.

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Link: https://lore.kernel.org/all/20231102112743.57420-1-dario.binacchi@amarulasolutions.com
2024-01-15 08:58:24 +01:00
Heinrich Schuchardt
6b37320c76 cmd: mtd: avoid unintentional integer overflow
mtd dump beyond 4 GiB will show incorrect results.

Multiplying two u32 will yield a u32. Add a missing cast.

Fixes: 5db66b3aee ("cmd: mtd: add 'mtd' command")
Addresses-Coverity-ID: 477205 ("Unintentional integer overflow")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/all/20240111073155.19545-1-heinrich.schuchardt@canonical.com
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2024-01-15 08:58:24 +01:00
Tom Rini
697758e7c8 Merge branch 'master-sync-dts-663' of https://source.denx.de/u-boot/custodians/u-boot-sh 2024-01-14 18:07:49 -05:00
Marek Vasut
73595fd4c0 ARM: dts: renesas: Synchronize R-Car R8A779F0 S4 DTs with Linux 6.6.3
Synchronize R-Car R8A779F0 S4 DTs with Linux 6.6.3,
commit bd3a9e5771a8b332f466d06f7c130a69cab0d526 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-01-14 20:35:21 +01:00
Marek Vasut
5a9eea75dd ARM: dts: renesas: Synchronize R-Car R8A77990 E3 DTs with Linux 6.6.3
Synchronize R-Car R8A77990 E3 DTs with Linux 6.6.3,
commit bd3a9e5771a8b332f466d06f7c130a69cab0d526 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-01-14 20:35:21 +01:00
Marek Vasut
33713261bf ARM: dts: renesas: Synchronize R-Car R8A77970 V3M DTs with Linux 6.6.3
Synchronize R-Car R8A77970 V3M DTs with Linux 6.6.3,
commit bd3a9e5771a8b332f466d06f7c130a69cab0d526 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-01-14 20:35:21 +01:00
Marek Vasut
61d32fb92c ARM: dts: renesas: Synchronize R-Car R8A7792 V2H DTs with Linux 6.6.3
Synchronize R-Car R8A7792 V2H DTs with Linux 6.6.3,
commit bd3a9e5771a8b332f466d06f7c130a69cab0d526 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-01-14 20:35:21 +01:00
Marek Vasut
a1997a3892 clk: renesas: Synchronize RZ R8A774E1 RZ/G2H clock tables with Linux 6.6.3
Synchronize RZ R8A774E1 RZ/G2H clock tables with Linux 6.6.3,
commit bd3a9e5771a8b332f466d06f7c130a69cab0d526 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-01-14 20:35:21 +01:00
Marek Vasut
94c2f5b622 clk: renesas: Synchronize RZ R8A774C0 RZ/G2E clock tables with Linux 6.6.3
Synchronize RZ R8A774C0 RZ/G2E clock tables with Linux 6.6.3,
commit bd3a9e5771a8b332f466d06f7c130a69cab0d526 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-01-14 20:35:21 +01:00
Marek Vasut
0e2433efe0 clk: renesas: Synchronize RZ R8A774B1 RZ/G2N clock tables with Linux 6.6.3
Synchronize RZ R8A774B1 RZ/G2N clock tables with Linux 6.6.3,
commit bd3a9e5771a8b332f466d06f7c130a69cab0d526 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-01-14 20:35:21 +01:00
Marek Vasut
e811b03e4a clk: renesas: Synchronize RZ R8A774A1 RZ/G2M clock tables with Linux 6.6.3
Synchronize RZ R8A774A1 RZ/G2M clock tables with Linux 6.6.3,
commit bd3a9e5771a8b332f466d06f7c130a69cab0d526 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-01-14 20:35:21 +01:00
Marek Vasut
f26739e23b clk: renesas: Synchronize R-Car R8A77995 D3 clock tables with Linux 6.6.3
Synchronize R-Car R8A77995 D3 clock tables with Linux 6.6.3,
commit bd3a9e5771a8b332f466d06f7c130a69cab0d526 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-01-14 20:35:21 +01:00
Marek Vasut
aa580d8c80 clk: renesas: Synchronize R-Car R8A77990 E3 clock tables with Linux 6.6.3
Synchronize R-Car R8A77990 E3 clock tables with Linux 6.6.3,
commit bd3a9e5771a8b332f466d06f7c130a69cab0d526 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-01-14 20:35:21 +01:00
Marek Vasut
25558301d2 clk: renesas: Synchronize R-Car R8A77965 M3-N clock tables with Linux 6.6.3
Synchronize R-Car R8A77965 M3-N clock tables with Linux 6.6.3,
commit bd3a9e5771a8b332f466d06f7c130a69cab0d526 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-01-14 20:35:21 +01:00
Marek Vasut
dca7e0c40e clk: renesas: Synchronize R-Car R8A77960 M3-W and R8A77961 M3-W+ clock tables with Linux 6.6.3
Synchronize R-Car R8A77960 M3-W and R8A77961 M3-W+ clock tables with Linux 6.6.3,
commit bd3a9e5771a8b332f466d06f7c130a69cab0d526 .

Add ZG clock macro into rcar-gen3-cpg.h to cover the new clock type .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-01-14 20:35:21 +01:00
Tom Rini
817fdce324 Merge tag 'efi-2024-04-rc1' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request efi-2024-04-rc1

Documentation:

* update coreboot graphics documentation
* fix '---' rendering

UEFI:

* add missing pointer check after memory allocation in efidebug
* replace duplicate functions efi_dp_append and efi_dp_concat
* support fmp versioning for multi bank update
* avoid using dm_scan_other() in EFI app
2024-01-14 09:34:14 -05:00
Marek Vasut
645add770e ARM: imx: Set stdio to serial on Data Modul i.MX8M Mini/Plus eDM SBC
In case CONSOLE_MUX and SYS_CONSOLE_IS_IN_ENV are enabled, the console
stdin, stdout, stderr must be defined in environment. Define the default
settings to fix the following warning on boot:

"
In:    No input devices available!
Out:   No output devices available!
Err:   No error devices available!
"

Sort the default environment as well.

Signed-off-by: Marek Vasut <marex@denx.de>
2024-01-13 15:02:47 -03:00
Marek Vasut
eba41982cf ARM: imx: Set stdio to serial on DH i.MX8M Plus DHCOM
In case CONSOLE_MUX and SYS_CONSOLE_IS_IN_ENV are enabled, the console
stdin, stdout, stderr must be defined in environment. Define the default
settings to fix the following warning on boot:

"
In:    No input devices available!
Out:   No output devices available!
Err:   No error devices available!
"

Sort the default environment as well.

Signed-off-by: Marek Vasut <marex@denx.de>
2024-01-13 15:02:24 -03:00
Heinrich Schuchardt
55125bbfb4 cmd: efidebug: check pointer after memory allocation
After calling efi_alloc() we must check that the return value is not NULL.

Fixes: f01c961ee3 ("cmd: efidebug: add uri device path")
Addresses-Coverity-ID: 477185 Dereference null return value
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-01-13 18:17:47 +01:00
Masahisa Kojima
b20c9c3d86 efi_loader: support fmp versioning for multi bank update
This commit stores the firmware version into the array
of fmp_state structure to support the fmp versioning
for multi bank update. The index of the array is identified
by the bank index.

This modification keeps the backward compatibility with
the existing versioning feature.

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-01-13 18:17:47 +01:00
Masahisa Kojima
af7a34acfd fwu: fix fwu_get_image_index interface
The capsule update uses the DFU framework for updating
storage. fwu_get_image_index() currently returns the
image_index calculated by (dfu_alt_num + 1), but this is
different from the image_index in UEFI terminology.

Since capsule update implementation calls dfu_write_by_alt
function, it is better that FWU returns the dfu_alt_num.

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-01-13 18:17:47 +01:00
Ilias Apalodimas
f19171c919 efi_loader: Clean up efi_dp_append and efi_dp_concat
Looking back at the initrd storing functionality, we introduced three
functions, efi_dp_append_or_concatenate(), efi_dp_append/concat(). In
hindsight we could have simplified that by a lot. First of all none of
the functions append anything. They all allocate a new device path and
concatenate the contents of two device paths in one. A boolean parameter
controls the final device path -- if that's true an end node is injected
between the two device paths.

So let's rewrite this and make it a bit easier to read. Get rid of
efi_dp_append(), efi_dp_concat() and rename
efi_dp_append_or_concatenate() to efi_dp_concat(). This is far more
intuitive and the only adjustment that is needed is an extra boolean
argument on all callsites.

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-01-13 18:17:47 +01:00
Grzegorz Szymaszek
753f76e417 doc: fix three-dash references in reStructuredText
The "Sending patches" and "Patman patch manager" documents refer to the
three-dash, "---", that separates patch parts. The symbol is written in
the documentation in the same form as it is in actual patches: as three
U+002D HYPHEN-MINUS characters. When building the documentation, Sphinx
converts this symbol to a U+2014 EM DASH, that is invalid in this case.

Make the three-dash symbol a reStructuredText inline literal to prevent
its conversion; that is, enclose it in a pair of double backquotes (`).

Signed-off-by: Grzegorz Szymaszek <gszymaszek@short.pl>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
2024-01-13 18:17:46 +01:00
Bin Meng
86efd04934 doc: coreboot: Update stale graphics enabling instructions
With latest coreboot (e.g.: v4.22.01), the instructions to enable
graphics support has changed. Refresh the doc.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2024-01-13 18:17:46 +01:00
Masahisa Kojima
6caf3a3e89 efi_loader: remove unused members from struct efi_disk_obj
part and dev_index in struct efi_disk_obj are not used,
let's remove it.

This commit also removes the invalid structure comment
for @dev, it does not exist.

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2024-01-13 18:17:46 +01:00
Simon Glass
50662260c4 efi: Avoid using dm_scan_other()
This function is defined by bootstd so using it precludes using that
feature. Use the board_early_init_r() feature instead.

Nove the affected code into a new file, so that it is clear that
this relates to board init.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2024-01-13 18:17:46 +01:00
Masahisa Kojima
5a0970ee8c efi_loader: fix iteration of FMP protocols
If one of the FMP protocols fails when calling GetImageInfo(),
populating the ESRT ends up with failure and other FMP protocols
are not added to the ESRT. We should still add all other FMP
protocols to the ESRT.

With this commit, iteration of all FMP protocols continues
even though one of the FMP protocols fails.

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Tested-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-01-13 18:17:46 +01:00
Lukasz Majewski
b19ef134f5 defconfig: xea: Change default spi-nor memory bus to 2 (single binary)
After the re-sync with Linux kernel (v6.0) of the XEA DTS
(SHA1: 7d08ddd09b) the alias
for SPI bus, to which SPI-NOR  memory is connected, has changed from
'spi3' to 'spi2'.

To be in sync with current u-boot's xea dts, the default bus number
(which allows running 'sf probe' without any extra parameters given)
has been adjusted.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2024-01-12 15:02:09 -03:00
Primoz Fiser
3233349fa6 imx: imx9: fixup thermal trips from fuses
Read i.MX9 CPU temp grade from fuses and fixup thermal trips in Linux
device-tree accordingly.

Based on commit 0543a1ed27 ("imx8m: fixup thermal trips")

Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
2024-01-12 15:01:55 -03:00
Yannic Moog
0e00632a83 board: phytec: MAINTAINERS: add missing phytec doc files
Add rst documentation files to the respective MAINTAINERS file for
PHYTEC boards.

Signed-off-by: Yannic Moog <y.moog@phytec.de>
Reviewed-by: Teresa Remmet <t.remmet@phytec.de>
2024-01-12 13:09:56 -03:00
Yannic Moog
ba9762da1c doc: board: phytec: Add phyGATE-Tauri board documentation
Add brief documentation on how to build a bootable U-Boot image for the
phyGATE-Tauri-L.

Signed-off-by: Yannic Moog <y.moog@phytec.de>
Reviewed-by: Teresa Remmet <t.remmet@phytec.de>
2024-01-12 13:09:56 -03:00
Yannic Moog
b64af30a9d Add support for phyGATE-Tauri-L-iMX8MM
phyGATE-Tauri-L-iMX8MM is a Gateway based on the phycore-imx8mm SoM.
As a result, all the board code of the phycore-imx8mm is used.
Device tree synced with kernel v6.7.

Signed-off-by: Yannic Moog <y.moog@phytec.de>
Reviewed-by: Teresa Remmet <t.remmet@phytec.de>
2024-01-12 13:09:56 -03:00
Fabio Estevam
53b03a5c9e imx8m: Select BINMAN at SoC level
All i.MX8M targets rely on using binman to generate the U-Boot
binary.

Select it at the SoC level instead of per board.

Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2024-01-12 13:09:56 -03:00
Fabio Estevam
dffbf45110 imx9: Select BINMAN at SoC level
All i.MX93 targets rely on using binman to generate the U-Boot
binary.

Select it at the SoC level instead of per board.

Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2024-01-12 13:09:56 -03:00
Fabio Estevam
c5dc44f816 doc: imx93_var_som: Adjust the underline length
Adjust the underline length so that it matches the title length.

Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2024-01-12 13:09:56 -03:00
Tom Rini
547d3dd28a Merge branch '2024-01-12-assorted-fixes'
- Allow defconfigs to #include files (so we can construct a defconfig
  from fragments), update phy-mtk-tphy binding, assorted test fixes,
  allow building host tools without cryptographic libraries again,
  android_ab bugfix, and make some SPL debugging cases easier.
2024-01-12 08:34:50 -05:00
Andrew Davis
2027e99e61 Makefile: Run defconfig files through the C preprocessor
This allows us to use some of the normal preprocessor directives inside
defconfig files. Such as #define and #include.

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Nishanth Menon <nm@ti.com>
2024-01-12 08:34:19 -05:00
Michal Simek
ef67a04e7e arm64: zynqmp: Start TPM automatically via preboot on Kria
SOMs have HW tpm but previous stages won't start it that's why start it at
U-Boot which will also provide access to random generator and it's usage
with KASLR.

Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/dffd2ee4cf2844832ebbdabefca0099cd2629ccc.1704980933.git.michal.simek@amd.com
2024-01-12 09:29:32 +01:00
Venkatesh Yadav Abbarapu
4536da00e5 xilinx: r5: Include the sys_r5_proto.h header for future use
Currently when using "W=1" with xilinx_zynqmp_r5_defconfig, getting
below warnings.
cc1.real: warning: ./arch/arm/mach-zynqmp-r5/include:
		No such file or directory [-Wmissing-include-dirs]
Fix W=1 missing-include-dirs warnings by including the headers and
sys_r5_proto.h file which can be used.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20240111030029.2565827-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2024-01-12 09:29:17 +01:00
Alexey Romanov
bf2df68028 android_ab: don't ignore ab_control_store return code
ab_control_store() can return an error if writing to disk fails.
In this case, we have to pass the error code to the caller.

Signed-off-by: Alexey Romanov <avromanov@salutedevices.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
2024-01-11 22:14:57 -05:00
Paul-Erwan Rio
03e598263e tools: fix build without LIBCRYPTO support
Commit cb9faa6f98 ("tools: Use a single target-independent config to
enable OpenSSL") introduced a target-independent configuration to build
crypto features in host tools.

But since commit 2c21256b27 ("hash: Use Kconfig to enable hashing in
host tools and SPL") the build without OpenSSL is broken, due to FIT
signature/encryption features. Add missing conditional compilation
tokens to fix this.

Signed-off-by: Paul-Erwan Rio <paulerwan.rio@gmail.com>
Tested-by: Alexander Dahl <ada@thorsis.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2024-01-11 22:09:11 -05:00
Alexander Dahl
b646a1053f tools: kwbimage: Allow disabling build on non-mvebu platforms
Some users want to build with CONFIG_TOOLS_LIBCRYPTO disabled, which in
general is possible for at least some boards.  32-bit mvebu however
requires kwbimage for building SPL, and kwbimage has a hard dependency
to host OpenSSL.

The new symbol CONFIG_TOOLS_KWBIMAGE allows disabling kwbimage build on
non-mvebu platforms, and thus building without host libcrypto from
OpenSSL.

Based on previous work and discussions, see links below.

Link: https://lore.kernel.org/u-boot/20211021093304.25399-1-pali@kernel.org/
Link: https://lore.kernel.org/u-boot/20220111153120.1276641-1-marex@denx.de/
Link: https://lore.kernel.org/u-boot/20230121154743.667253-2-paulerwan.rio@gmail.com/
Cc: Marek Vasut <marex@denx.de>
Cc: Paul-Erwan Rio <paulerwan.rio@gmail.com>
Signed-off-by: Alexander Dahl <ada@thorsis.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2024-01-11 22:09:11 -05:00
Peter Robinson
bbd6618fb5 test: fs: fs-test: Move the tests to use sha256sum
Move the use of md5s for recording filesystem file integrity
checks to sha256 hashes as they're preferred due to being
less likely to produce clashing hashes. In the process
generalise some of the wording to use the more generic
hash term.

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
2024-01-11 21:19:25 -05:00
Tom Rini
3d74a0977f ti: am335x: Remove unused linker script
The board specific linker script has not been used in a long time here,
remove it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2024-01-11 21:19:25 -05:00
Csókás Bence
29f390bbd5 arm: spl: Use separate fault handlers instead of a single common one
It may be necessary to set breakpoints etc. on a specific fault handler in SPL.
Add a Kconfig option to separate the different handlers into their own individual infinite loops.

Signed-off-by: Csókás Bence <csokas.bence@prolan.hu>
2024-01-11 21:19:25 -05:00
Heinrich Schuchardt
6e75ae1a39 test: CONFIG_UT_BOOTSTD must depend on CONFIG_BOOTSTD
Building sandbox_defconfig with

    CONFIG_BOOTSTD=n
    CONFIG_UT_BOOTSTD=y

leads to an error

    /usr/bin/ld: test/cmd_ut.o:(.data.rel.cmd_ut_sub+0xc0):
    undefined reference to `do_ut_bootstd'

Add the missing dependency.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2024-01-11 21:19:25 -05:00
Heinrich Schuchardt
64c67b68d1 boot: CONFIG_CEDIT must depend on CONFIG_EXPO
Building sandbox_defconfig with

    CONFIG_CMD_CEDIT=y
    CONFIG_EXPO=n

fails with

    cmd/cedit.c:258:(.text.do_cedit_run+0x4c):
    undefined reference to `expo_apply_theme

Fix the dependencies.

Fixes: a0874dc4ac ("expo: Add a configuration editor")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2024-01-11 21:19:25 -05:00
Heinrich Schuchardt
6a8a23ccfb test: build test/boot for CONFIG_UT_BOOTSTD=n
Building sandbox_defconfig with

    CONFIG_UT_BOOTSTD=n
    CONFIG_MEASURMENT=y

results in an error:

    /usr/bin/ld: test/cmd_ut.o:(.data.rel.cmd_ut_sub+0x408):
    undefined reference to `do_ut_measurement'

Fixes: 5999ea20fa ("test: Add sandbox TPM boot measurement")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-01-11 21:19:25 -05:00
Simon Glass
99abd60d59 boot: Support decompressing non-kernel OS images
Sometimes the kernel is built as an EFI application rather than a
binary. We still want to support compression for this case.

For arm64 the entry point is set later in the bootm_load_os() function,
since these images are typically relocated due to the 2MB-alignment
requirement of arm64 images. But since the EFI image is not in the same
format, we need to update the entry point earlier.

Set the entry point always, for kernel_noload to resolve this problem.
It should be harmless to do this always.

Signed-off-by: Simon Glass <sjg@chromium.org>
2024-01-11 21:19:25 -05:00
Chunfeng Yun
4f6dd25800 phy: phy-mtk-tphy: add properties for phy tuning
Add properties to improve eye diagram which sometimes need adjust
some parameters of u2phy;
Add a property to tune disconnect threshold;

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
2024-01-11 21:19:25 -05:00
Chunfeng Yun
69600f4156 dt-bindings: phy-mtk-tphy: add properties for phy tuning
Add properties to improve eye diagram which sometimes need adjust
some parameters of u2phy;
Add a property to tune disconnect threshold;

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
2024-01-11 21:19:25 -05:00
Tom Rini
2ee7a8ec6f Merge patch series "net fixes prior lwip"
Maxim Uvarov <maxim.uvarov@linaro.org> says:

Add small net fixes prior lwip patches.
2024-01-11 11:25:07 -05:00
Maxim Uvarov
d914487f8f Makefile: add dtbs to clean
CI test checks that generated dtb has to be cleaned up.
Use the same clean procedure as Linux top level Makefile has.

Signed-off-by: Maxim Uvarov <maxim.uvarov@linaro.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2024-01-11 11:24:58 -05:00
Maxim Uvarov
6c84e71258 omap3: use device specific naming for mem_init
Use device specific naming for functions so as to not overlap
with common function names.

Signed-off-by: Maxim Uvarov <maxim.uvarov@linaro.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2024-01-11 11:24:58 -05:00
Maxim Uvarov
0c6d645d3f bcm_ns3: use device specific naming for variables
Use device specific naming for variables so as to not overlap
with common function names.

Signed-off-by: Maxim Uvarov <maxim.uvarov@linaro.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Peter Robinson <pbrobinson@gmail.com>
2024-01-11 11:24:58 -05:00
Maxim Uvarov
9c77cffabd mach-socfpga: do not overlap defines with lwip
Fix compilation issue with overlapping lwip and march defines.

Signed-off-by: Maxim Uvarov <maxim.uvarov@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2024-01-11 11:24:58 -05:00
Maxim Uvarov
c64a1e43ac driver/net/rtl8139: remove debug print
debug print delays reset of the driver. Finally I see
bunch of "rx error FFFF" errors in the screen. CI can
not handle many prints. While network works fine there

Reproduced with:
make CROSS_COMPILE=sh2-linux- r2dplus_defconfig all
qemu-system-sh4 -M r2d -nographic -serial null \
-serial mon:stdio -net user,tftp=`pwd` \
-net nic,model=rtl8139 -kernel ./u-boot.bin

Signed-off-by: Maxim Uvarov <maxim.uvarov@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2024-01-11 11:24:58 -05:00
Maxim Uvarov
f3384d7fbb sandbox: eth-raw-os: successful return code is 0
all network drivers return 0 on the successful
transmission.

Signed-off-by: Maxim Uvarov <maxim.uvarov@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2024-01-11 11:24:58 -05:00
Maxim Uvarov
f5ead4c5fb net/smc911x: fix return from smc911x_send
return value of smc911x_send is ignored, but on sucesseful
send we need return 0 and or error -ETIMEOUT, not opposite.

Signed-off-by: Maxim Uvarov <maxim.uvarov@linaro.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2024-01-11 11:24:58 -05:00
Maxim Uvarov
e6163467a3 test_net: print out net list
Printing net list is useful in CI log files.

Signed-off-by: Maxim Uvarov <maxim.uvarov@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2024-01-11 11:24:58 -05:00
Tom Rini
d3dba8a28b Merge tag 'u-boot-dfu-20240111' of https://source.denx.de/u-boot/custodians/u-boot-dfu
u-boot-dfu-20240111

- Implement fastboot multi-response. This allows multi-line response and
  most importantly, finally adds support for fastboot getvar all command.

- New 'fastboot oem console' command. Useful for debugging to send data
  the u-boot shell via fastboot

- Console recording fixes
2024-01-11 10:03:51 -05:00
Michal Simek
64a31fe710 arm64: zynqmp: Remove ltc2954 node
Remove already disabled node. GPIO connections are handled by pmufw that's
why there is no reason to have it described for non secure firmware.
If someone wants to handle it from OS revert this patch and also update
PMUFW configuration and pinctrl setting for these GPIO pins.

Link: https://lore.kernel.org/r/f26b1a780ec44444d62e2dd696a05e2a37fa0993.1704890056.git.michal.simek@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2024-01-11 14:16:34 +01:00
Tom Rini
7a59d520ef configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2024-01-10 10:45:49 -05:00
Tom Rini
254a81c6b6 Merge https://source.denx.de/u-boot/custodians/u-boot-marvell
- AC5: Use finer grained memory map (Chris)
- Espressobin: Misc improvements (Robert)
- eDPU: Support new board revision (Robert)
2024-01-10 09:53:29 -05:00
Robert Marko
46471e6c1d arm: mvebu: eDPU: support new board revision
There is a new eDPU revision that uses Marvell 88E6361 switch onboard.
We can rely on detecting the switch to enable and fixup the Linux DTS
so a single DTS can be used.

There is currently no support for the 88E6361 switch and thus no working
networking in U-Boot, so we disable both ports.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Reviewed-by: Stefan Roese <sr@denx.de>
2024-01-10 09:38:55 +01:00
Robert Marko
fde58124c3 arm: mvebu: Espressobin: move network setup into a separate function
Currently, Esspresobin switch is being setup directly in last_stage_init()
which makes it hard to add support for any other board to be setup.

So, lets just move the switch setup code to a separate function and call it
if compatible matches, there should be no functional change.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Reviewed-by: Stefan Roese <sr@denx.de>
2024-01-10 09:38:55 +01:00
Robert Marko
9a43eb12db arm: mvebu: Espressobin: move FDT fixup into a separate function
Currently, Esspresobin FDT is being fixed up directly in ft_board_setup()
which makes it hard to add support for any other board to be fixed up.

So, lets just move the FDT fixup code to a separate function and call it
if compatible matches, there should be no functional change.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Reviewed-by: Stefan Roese <sr@denx.de>
2024-01-10 09:38:55 +01:00
Chris Packham
cb71a30857 arm: mvebu: AC5: Use finer grained memory map
The ATF implementation for AC5/AC5X ends up with bl31 living in some
internal SRAM. This is in the middle of the large MMIO region that we
were using. Adjust this to be finer grained blocks based on the address
map from the AC5X Family Control and Management Subsystem Functional
Datasheet.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
2024-01-10 09:38:55 +01:00
Brandon Maier
c9190693b0 tools: zynqmpimage: print partition names
Each partition may belong to an image, which has a name. That name can
be useful for debugging as it helps identify where the partition came
from.

Signed-off-by: Brandon Maier <brandon.maier@collins.com>
Link: https://lore.kernel.org/r/20240104185258.39465-4-brandon.maier@collins.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2024-01-10 09:27:12 +01:00
Brandon Maier
d47935b35f tools: zynqmpimage: add partition extracting
Extract partitions from a Xilinx Boot Image using dumpimage.

Add helper for_each_zynqmp_part() to reuse the partition walking code
between the printing and extracting functions.

Signed-off-by: Brandon Maier <brandon.maier@collins.com>
Link: https://lore.kernel.org/r/20240104185258.39465-3-brandon.maier@collins.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2024-01-10 09:27:12 +01:00
Brandon Maier
2ddd0248e9 tools: zynqmpimage: print all partition sizes
Two of the partition size fields are not printed. Currently only the
"total" size is displayed, which is the size of the image data
(encrypted), padding, expansion, and authentication data. Add the
"unencrypted data" size, which is the original size of the data before
being encrypted. And "encrypted data" size, which is just the encrypted
data.

To avoid printing useless information, only print the encrypted and
unencrypted sizes if they are different from the total.

Signed-off-by: Brandon Maier <brandon.maier@collins.com>
Link: https://lore.kernel.org/r/20240104185258.39465-2-brandon.maier@collins.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2024-01-10 09:27:12 +01:00
Brandon Maier
85acf83a09 tools: zynqmpimage: show info on partition 0
The zynqmpimage_print_header() skips printing the first partition. This
is because the image header can contain duplicate fields as the first
partition. However some fields, like the partition attributes, are only
present in the partition table. It is also possible for the first
partition to not be declared in the image header, if the image is not a
bootloader image.

Signed-off-by: Brandon Maier <brandon.maier@collins.com>
Link: https://lore.kernel.org/r/20240104185258.39465-1-brandon.maier@collins.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2024-01-10 09:27:12 +01:00
Michal Simek
b121dc80c3 arm64: zynqmp: Rename zynqmp-power node to power-management
Rename zynqmp-power node name to power-management which is more aligned
with generic node name recommendation.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/a2f7fe30e3630c262c2773a595b7a0c8918573a0.1704359569.git.michal.simek@amd.com
2024-01-10 09:18:09 +01:00
Michal Simek
cedc03dd62 arm64: zynqmp: Match dwc3 interrupts description with values
Correct IRQ values don't match IRQ line description.
There is one more IRQ (hiber) but it is not described in DT binding spec
that's why value is not described. Just for completeness dwc3_0 has hiber
IRQ at 75 and dwc3_1 at 76.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/578d758ce2af7e307e38ac8b7fa28ba9efba16d4.1704364111.git.michal.simek@amd.com
2024-01-10 09:17:45 +01:00
Michal Simek
a93e09f058 arm64: zynqmp: Add support for new power-management node name
zynqmp-power node is going to be renamed to power-management which should
be generic enough. New name came from dt-binding review that's why there is
no way around. Add support new name but also at the same time check old
name just in case older dt binding is used.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/967aa76f9f72604c874b580476aa85f5260ccd65.1704448544.git.michal.simek@amd.com
2024-01-10 09:17:41 +01:00
Michal Simek
e5d9df9571 arm64: zynqmp: Replace '-' by '_' in fixed clock nodes
Using '_' in node name is not recommended that's why convert them to use
'-' instead.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/3979167636f0a5970a9ab642a4e0ea6a46b3f8d7.1704705872.git.michal.simek@amd.com
2024-01-10 09:17:41 +01:00
Michal Simek
4626039c94 arm64: xilinx: Remove multiple blank lines from DTSes
There is no reason to have multiple blank lines in DTS files that's why
remove them.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/6aaa9fa91c88ca3d3e5645d66a795ec09b8cec61.1704708642.git.michal.simek@amd.com
2024-01-10 09:17:41 +01:00
Michal Simek
a46c43cc0e arm64: zynqmp: Add missing description for efuse aeskey/pufuser
Add missing description for efuse aeskey/pufuser offsets.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/9975c501c92d8e9d6e307dfd3f4146e08a2fc68e.1704799551.git.michal.simek@amd.com
2024-01-10 09:17:41 +01:00
Michal Simek
5bf527b1b3 arm64: zynqmp: Describe interrupt by using macro (OCM)
OCM controller interrupt description hasn't been converted by using macros
that's why fix it now.

Fixes: 6b049190c9 ("arm64: zynqmp: Describe interrupts by using macros")
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/6a51f47d239002679db03a787057fdc58610515d.1704709554.git.michal.simek@amd.com
2024-01-10 09:17:41 +01:00
Shubhrajyoti Datta
3c65670cb6 arm64: zynqmp: Update the i2c0 node for zcu1285
The pca mux is not added to the i2c0 bus so remove it from the bus.

Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/3dfe8b41142de2e8c25c56702450ae1a6b1becc0.1704725223.git.michal.simek@amd.com
2024-01-10 09:17:41 +01:00
Tom Rini
344667db64 Merge tag 'smbios-2024-04-rc1' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request smbios-2024-04-rc1

* make table_compute_checksum() arguments const
* remove duplicate function verify_checksum()
* enable setting processor family > 0xff
* set correct SMBIOS processor family value for RISC-V
* avoid importing ofnode.h in smbios.h
* provide a UEFI tool to dump SMBIOS table
2024-01-09 12:50:04 -05:00
Tom Rini
0727b10f6b Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-samsung 2024-01-09 10:59:29 -05:00
Sam Protsenko
5bf111b77c pinctrl: exynos: Convert to use livetree API for fdt access
Use counterpart dev_read_* functions instead of fdt* ones. It fixes
checkpatch warnings like this:

    WARNING: Use the livetree API (dev_read_...)
    #54: FILE: drivers/pinctrl/exynos/pinctrl-exynos.c:137:
        pinvals[idx] = fdtdec_get_int(fdt, node,

and also makes it possible to avoid using the global data pointer in the
driver.

No functional change.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2024-01-09 10:59:28 -05:00
Sam Protsenko
da06fefcef pinctrl: exynos: Reduce variables scope
Pull some variables declared in exynos_pinctrl_set_state() into its
loop, to reduce their scope. Style commit, no functional change.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2024-01-09 10:59:28 -05:00
Sam Protsenko
aad0f6abf1 pinctrl: exynos: Refactor handling the pin related dt properties
All pin related dt properties (pin-function, pin-pud and pin-drv) are
handled in a very similar way. Get rid of that code duplication by
extracting the corresponding data knowledge into an actual data
structure (array), and then just iterating over it.

No functional change, it's a refactoring commit.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2024-01-09 10:59:28 -05:00
Sam Protsenko
2ed4ba83fb pinctrl: exynos: Support different register types in pin banks
Get rid of hard-coded register offsets and widths. Instead provide a way
for pinctrl drivers to specify different pin bank register offsets and
widths. This in turn makes it possible to add support for new SoCs that
have registers with offset/width values different than generic ones
already available in pinctrl-exynos driver.

Offset constants (now unused in pinctrl-exynos.c) are moved to
pinctrl-exynos7420 driver, which is the single user of those constants.

The design of this patch follows Linux kernel pinctrl-exynos driver
design, in terms of added data structures and types. This patch doesn't
add support for any new SoCs and shouldn't introduce any functional
changes.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2024-01-09 10:59:28 -05:00
Sam Protsenko
2dfcb250d0 pinctrl: exynos: Rework pin_to_bank_base() to obtain data by name
Rework pin_to_bank_base() function to obtain bank data structure by bank
name instead of getting bank base address by pin name, and rename it to
get_bank() to reflect this change. This in turn leads to the extraction
of parse_pin(), so the caller has to use it before calling get_bank().

No functional change. This is a refactoring commit which prepares
pinctrl driver code for handling different sizes of register fields,
which will be added next.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2024-01-09 10:59:28 -05:00
Sam Protsenko
58e84bf3d7 pinctrl: exynos: Extract pin parsing code into a separate function
Next commits are going to re-design the pin_to_bank_base() function and
its usage in a way that the pin parsing code will be called separately.
Extract it into a separate function first, as a refactoring commit.

No functional change.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2024-01-09 10:59:28 -05:00
Sam Protsenko
7b34206e3f pinctrl: exynos: Improve coding style
Style commit, no functional change.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2024-01-09 10:59:28 -05:00
Ion Agorria
6c2f753f4a test: hush: dollar: fix bugous behavior
The dollar test was merged with bugous console behavior, and
instead of fixing it, this behavior was just workarounded.

It seems like without the fix the ut_assert_skipline(); didn't clear
console and running ut_assert_skipline(); many times would give always
OK. With

lib: membuff: fix readline not returning line in case of overflow

the line is cleared correctly and next assert fails because now there
is nothing to clean which is correct if we look the this a bit above
the failing assert:

    if (gd->flags & GD_FLG_HUSH_MODERN_PARSER) {
         /*
          * For some strange reasons, the console is not empty after
          * running above command.
          * So, we reset it to not have side effects for other tests.
          */
         console_record_reset_enable();
    } else if (gd->flags & GD_FLG_HUSH_OLD_PARSER) {
         ut_assert_console_end();
    }

Which further confirms that tests workaround the old problem and now
that problem is fixed we can remove the whole if blocks and simply
place ut_assert_console_end() right after ut_assert_skipline() without
any conditional and will pass green.

So this part of code goes from:
    ut_assert_skipline();
    ut_assert_skipline();

    if (gd->flags & GD_FLG_HUSH_MODERN_PARSER) {
        /* See above comments. */
        console_record_reset_enable();
    } else if (gd->flags & GD_FLG_HUSH_OLD_PARSER) {
        ut_assert_console_end();
    }

to become:
    ut_assert_skipline();
    ut_assert_console_end();

Same thing should be done with the if block mentioned above that calls
console_record_reset_enable().

Signed-off-by: Ion Agorria <ion@agorria.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Tested-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Link: https://lore.kernel.org/r/20240105072212.6615-8-clamor95@gmail.com
[mkorpershoek: reworded commit title]
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
2024-01-09 15:31:59 +01:00
Tom Rini
c7937a4199 Merge tag 'rng-2024-04-rc1' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi
Pull request rng-2024-04-rc1

QEMU does not provide information in the device-tree if the ARMv8.5 RNDR
or the RISC-V Zkr RNG have been enabled on the command line.

In different parts of our code we assume that the first RNG device is the
one to be used. Therefore it is preferable to detect the availability of
said devices already in the bind method.

There has been a related discussion if the U_BOOT_DRVINFO() macro should be
used for architectural devices
(https://lore.kernel.org/u-boot/20231031125552.26698-1-heinrich.schuchardt@canonical.com/).
This aspect is not touched by this series.
2024-01-09 09:00:39 -05:00
Ion Agorria
16f79dd4cd fastboot: add oem console command support
"oem console" serves to read console record buffer.

Signed-off-by: Ion Agorria <ion@agorria.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Link: https://lore.kernel.org/r/20240105072212.6615-7-clamor95@gmail.com
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
2024-01-09 14:58:33 +01:00
Ion Agorria
e58bafc35f lib: membuff: fix readline not returning line in case of overflow
If line overflows readline it will not be returned, fix this behavior,
make it optional and documented properly.

Signed-off-by: Ion Agorria <ion@agorria.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Link: https://lore.kernel.org/r/20240105072212.6615-6-clamor95@gmail.com
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
2024-01-09 14:58:33 +01:00
Ion Agorria
90087dd076 common: console: record console from the beginning
Set flag to enable console record on console_record_init
and not only on console_record_reset_enable. This fixes
missing start of U-Boot log for fastboot oem console
command.

Signed-off-by: Ion Agorria <ion@agorria.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Link: https://lore.kernel.org/r/20240105072212.6615-5-clamor95@gmail.com
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
2024-01-09 14:58:33 +01:00
Ion Agorria
9ce75f4912 common: console: introduce console_record_isempty helper
Add console_record_isempty to check if console record buffer
contains any data.

Signed-off-by: Ion Agorria <ion@agorria.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Link: https://lore.kernel.org/r/20240105072212.6615-4-clamor95@gmail.com
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
2024-01-09 14:58:33 +01:00
Ion Agorria
475aa9aabe fastboot: implement "getvar all"
This commit implements "fastboot getvar all" listing
by iterating the existing dispatchers that don't require
parameters (as we pass NULL), uses fastboot multiresponse.

Signed-off-by: Ion Agorria <ion@agorria.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Link: https://lore.kernel.org/r/20240105072212.6615-3-clamor95@gmail.com
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
2024-01-09 14:58:33 +01:00
Ion Agorria
85fcd69dc2 fastboot: multiresponse support
Currently u-boot fastboot can only send one message back to host,
so if there is a need to print more than one line messages must be
kept sending until all the required data is obtained. This behavior
can be adjusted using multiresponce ability (getting multiple lines
of response) proposed in this patch.

Signed-off-by: Ion Agorria <ion@agorria.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Link: https://lore.kernel.org/r/20240105072212.6615-2-clamor95@gmail.com
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
2024-01-09 14:58:33 +01:00
Tejas Bhumkar
3ae0ce7153 xilinx: Enable the NFS command by default
Enabled the default utilization of the NFS command across all Xilinx
platforms to facilitate the booting of images through the network
using the NFS protocol.

Fixes: 10de125707 ("disable NFS support by default")

Signed-off-by: Tejas Bhumkar <tejas.arvind.bhumkar@amd.com>
Link: https://lore.kernel.org/r/20240104045217.2966454-1-tejas.arvind.bhumkar@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2024-01-09 14:51:04 +01:00
Michal Simek
8026aa6149 arm64: zynqmp: Rename i2c?-gpio to i2c?-gpio-grp
Anything ending with gpio/gpios is taken as gpio phande/description which
is reported as the issue coming from gpio-consumer.yaml schema.
That's why rename the gpio suffix to gpio-grp to avoid name collision.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/407b0b67ba019be5a2073d09d578b381c639cbc6.1703002605.git.michal.simek@amd.com
2024-01-09 14:51:04 +01:00
Michal Simek
b0462416d8 arm64: zynqmp: Remove mt25qu512a compatible string from SOM
mt25qu512a is not documented in DT binding that's why remove it.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/517672560a472de33c8e5c4ffc729d8e288da43c.1703002605.git.michal.simek@amd.com
2024-01-09 14:51:04 +01:00
Michal Simek
34ee661d69 arm64: zynqmp: Fix clock node name in kv260 cards
node name shouldn't use '_' that's why convert it to '-'.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/8f392c7ff13bdf2322798818ddeda06446b6d7b8.1703002605.git.michal.simek@amd.com
2024-01-09 14:51:04 +01:00
Michal Simek
2223731360 arm64: zynqmp: Move fixed clock to / for kv260
fixed clock nodes can't be on the bus because they are missing reg
property. That's why move them to root.
And because it is root it is good to have it as the first node in a file.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/9a6c17fa754add356b3b03356e41d15e4a18648b.1703002605.git.michal.simek@amd.com
2024-01-09 14:51:04 +01:00
Michal Simek
6132047d49 arm64: zynqmp: Generate dfu_alt_info based on multiboot register
Commit 2c8a09219c ("arm64: zynqmp: Add multiboot support for SPL/SPI
offset calculation") enabled u-boot.itb offset calculation based on
multiboot register. It is also good to reflect location of u-boot.itb image
for dfu_alt generation.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/5abc5f3047ce586b4d2740b5eea775d063295e28.1702906896.git.michal.simek@amd.com
2024-01-09 14:51:04 +01:00
Michal Simek
af37f71efa arm64: zynqmp: Fix i2c bus for kd240
i2c1 is having all chips on it that's why use it instead of 0.

You can see this error when you boot system.
eth0: ethernet@ff0c0000
Setting bus to 0
Failure changing bus number (-19)
Enable permission for node ID 33
Enable permission for node ID 47
Hit any key to stop autoboot:  0

It also get USB to work.

Fixes: dd4a822016 ("arm64: zynqmp: Introduce kria SOM defconfig")
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/cf07682a611de9895271d629ee00fb2809d99d0e.1702904913.git.michal.simek@amd.com
2024-01-09 14:51:04 +01:00
Michal Simek
df68c2c9aa arm64: zynqmp: Describe ethernet phy on kd240
Describe ADIN phy present on KD240 via ethernet-phy-id compatible string.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/61f89dc055f191fd4138b80bb7e3217d814502f5.1702904236.git.michal.simek@amd.com
2024-01-09 14:51:04 +01:00
Michal Simek
5c687b2160 xilinx: Enable DNS/WGET and BLKMAP for http boot
Enable DNS/WGET and BLKMAP to be able to download images over HTTP and map
them.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/4fa9b425459947e6424c8ce27376fdc7a14bf839.1696592702.git.michal.simek@amd.com
2024-01-09 14:51:04 +01:00
Heinrich Schuchardt
8aec703111 efi_loader: provide tool to dump SMBIOS table
An EFI binary smbiosdump.efi is provided that can be used to check the
SMBIOS table for consistency and to dump it as a file.

The tool provides the following commands:

check
    Check the SMBIOS table for consistency.

exit
    Leave the tool.

help
    Show available commands.

save
    Save the SMBIOS table to a file on the EFI system partition. The file
    can be further analyzed with the dmidecode command line tool::

        dmidecode --from-dump <filename>

Specifying 'nocolor' as load option data suppresses colored output and
clearing of the screen.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-01-09 10:09:15 +01:00
Heinrich Schuchardt
efe441a0a3 smbios: smbios.h should not import ofnode.h
The smbios.h include does not use any definitions from ofnode.h.
So don't include it.

As DECLARE_GLOBAL_DATA_PTR is no longer defined via dm/of.h we need to
add it to efi_smbios.c.

Add now missing includes to smbios-parser.c.

Remove a superfluous check comparing the sizes of the SMBIOS 2.1 and SMBIOS
3.0 anchors.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2024-01-09 10:09:15 +01:00
Heinrich Schuchardt
1b6228f28d cpu: riscv: set correct SMBIOS processor family value
The SMBIOS specification requires to set the processor family in the type 4
(Processor Information) table to specific values depending only on the
bitness of the system (0x200 for RV32 and 0x201 for RV64).

With this patch dmidecode shows

    Handle 0x0004, DMI type 4, 48 bytes
    Processor Information
	Socket Designation: Not Specified
	Type: Central Processor
	Family: RV64

for qemu-riscv64_smode_defconfig.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-01-09 10:09:15 +01:00
Heinrich Schuchardt
0920bd50dc smbios: enable setting processor family > 0xff
Many value of processor type exceed 0xff and have to be stored as u16
value. In the type 4 table set processor_family = 0xfe signaling that
field processor_family2 is used and write the actual value into the
processor_family2 field.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2024-01-09 10:09:15 +01:00
Heinrich Schuchardt
dc2fe5d84e lib: smbios: verify_checksum() is duplicate
The function verify_checksum() duplicates what table_compute_checksum()
does. Replace it. table_compute_checksum() is always compiled.

Fixes: 415eab0655 ("smbios: add parsing API")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-01-09 10:09:09 +01:00
Heinrich Schuchardt
e3db8d60be lib: make table_compute_checksum() arguments const
table_compute_checksum() does neither changes the content of the
checksummed buffer nor the buffer length. Adding const to the
definition makes the function wider usable.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-01-09 10:08:52 +01:00
Heinrich Schuchardt
1351cd3b4b rng: detect RISC-V Zkr RNG device in bind method
The existence of devices should be checked in the bind method and not in
the probe method. Adjust the RISC-V Zkr RNG driver accordingly.

Use ENOENT (and not ENODEV) to signal that the device is not available.

Fixes: ceec977ba1 ("rng: Provide a RNG based on the RISC-V Zkr ISA extension")
Reported-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-01-09 07:37:05 +01:00
Heinrich Schuchardt
badef4cd4a rng: fix ARMv8.5 RNDR driver
In different parts of our code we assume that the first RNG device is the
one to be used. Therefore it is preferable to detect the availability of
the RNDR register already in the bind method.

For signaling the non-existence of a device the driver model requires using
ENOENT (and not ENODEV).

Fixes: 31565bb0aa ("driver: rng: Add DM_RNG interface for ARMv8.5 RNDR registers")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Andre Przywara <andre.przywara@arm.com>
2024-01-09 07:36:18 +01:00
Tom Rini
c5e461fbf7 Merge tag 'u-boot-imx-master-20240108' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
- Removed fdt_addr from verdin-imx8mm to fix booting via bootefi.
- Support Ethernet PHY autodection on Data Modul i.MX8M Mini/Plus eDM
  SBC
- Add i.MX93 binman support
- Add support for imx93-var-som
2024-01-08 13:39:43 -05:00
Mathieu Othacehe
54e1aa236f Add imx93-var-som support
Add support for the Variscite VAR-SOM-IMX93 evaluation kit. The SoM
consists of an NXP iMX93 dual A55 CPU. The SoM is mounted on a Variscite
Symphony SBC.

Signed-off-by: Mathieu Othacehe <m.othacehe@gmail.com>
2024-01-08 14:37:57 -03:00
Mathieu Othacehe
bfbef0e8e7 imx9: imx93_evk: Add binman support.
Signed-off-by: Mathieu Othacehe <m.othacehe@gmail.com>
2024-01-08 14:37:55 -03:00
Mathieu Othacehe
f637dfe8c4 mach-imx: Add i.MX93 binman support.
Add dedicated Makefile targets for the i.MX93 and a new imx93-u-boot.dtsi
device-tree to create binman images.

Signed-off-by: Mathieu Othacehe <m.othacehe@gmail.com>
2024-01-08 14:37:53 -03:00
Mathieu Othacehe
da96f93cda spl: binman: Disable u_boot_any symbols for i.MX93 boards
This is extending commit 6516c9b349 ("spl: binman: Disable u_boot_any
symbols for i.MX8M boards") to i.MX93 boards.

Signed-off-by: Mathieu Othacehe <m.othacehe@gmail.com>
2024-01-08 14:37:50 -03:00
Francesco Dolcini
59a72caba9 verdin-imx8mm: Remove stale fdt_addr env variable
fdt_addr variable is the location in flash of the device tree blob [1], it
does not exist for verdin-imx8mm.

Because of this the bootefi command fails unless the optional
`[fdt address]` parameter is passed on the command line,
bootefi.c:efi_install_fdt() assumes that `fdt_addr` is valid when
present.

Fix this removing fdt_addr from the U-Boot environment.

[1] doc/usage/environment.rst

Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2024-01-08 14:34:34 -03:00
Marek Vasut
32a41b7c37 ARM: imx: Auto-detect PHY on Data Modul i.MX8M Mini/Plus eDM SBC
Implement fdtdec_board_setup() auto-detection of ethernet PHY.
This uses properties of the hardware and pull resistor placement.

If GPIO1_16 RGMII_MDC is HIGH, then R530 (MX8MM eDM SBC) or
R390 (MX8MP eDM SBC) is populated. R530 or R390 is populated
only on boards with AR8031 PHY.

If GPIO1_16 RGMII_MDC is LOW, then the in-SoM pull down is the
dominant pull resistor. This is the case on boards with BCM54213PE
PHY.

In case AR8031 PHY is populated, the PHY MDIO address is 0, in
case BCM54213PE PHY is populated, the PHY MDIO address is 1, the
fdtdec_board_setup() is used to patch the correct address into
the U-Boot control DT.

Enable broadcom PHY support to support both PHYs.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2024-01-08 14:34:16 -03:00
Tom Rini
93d91e9485 Merge branch 'next' 2024-01-08 12:00:18 -05:00
Tom Rini
f28a77589e Merge tag 'dm-next-7jan23' of https://source.denx.de/u-boot/custodians/u-boot-dm into next
switch to SMBIOS3 tables
allow devicetree from bloblist
ACPI support for ARM and RISC-V
2024-01-08 09:11:53 -05:00
Heinrich Schuchardt
8c4b37ce97 arm: enable support for QEMU firmware tables
Enable the QEMU firmware interface if ACPI tables are to be supported on
the QEMU platform.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-01-07 13:49:15 -07:00
Heinrich Schuchardt
b8bb5704ae configs: qemu: add config fragment for ACPI
Provide a configuration fragment to enable ACPI on QEMU.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2024-01-07 13:49:15 -07:00
Heinrich Schuchardt
b17e280bb2 riscv: allow usage of ACPI
Select CONFIG_SUPPORT_ACPI to allow usage of ACPI tables with RISC-V.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2024-01-07 13:49:15 -07:00
Heinrich Schuchardt
91970e83ed riscv: add support for QEMU firmware tables
Enable the QEMU firmware interface if ACPI tables are to be supported on
the QEMU platform.

Enable the QFW MMIO interface if the QEMU firmware interface is enabled.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-01-07 13:49:15 -07:00
Heinrich Schuchardt
638cc36348 acpi: enable writing ACPI tables on QEMU
Invoke write_acpi_tables() via EVT_LAST_STAGE_INIT on QEMU except on X86.
X86 calls write_acpi_tables() in write_tables().

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2024-01-07 13:49:15 -07:00
Heinrich Schuchardt
b7d029bb8a riscv: add ACPI fields to global data
Add fields for the location of ACPI tables to the global data.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2024-01-07 13:49:15 -07:00
Heinrich Schuchardt
22fcd1da55 arm: add ACPI fields to global data
Add fields for the location of ACPI tables to the global data.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2024-01-07 13:49:15 -07:00
Heinrich Schuchardt
27a66fc3f3 acpi: carve out qfw_acpi.c
Move the code related to copying tables from QEMU to a separate code
module.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-01-07 13:49:15 -07:00
Heinrich Schuchardt
b2f088c121 acpi: Kconfig symbol CONFIG_QFW_ACPI
We have two implementations of write_acpi_tables(). One for writing ACPI
tables based on ACPI_WRITER() entries another based on copying tables from
QEMU.

Create a symbol CONFIG_QFW_ACPI that signifies copying ACPI tables from
QEMU and use it consistently.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2024-01-07 13:49:15 -07:00
Heinrich Schuchardt
f47c86f6d3 acpi: support 64bit in acpi_find_table for DSDT and FACS
Use X_DSDT and X_FIRMWARE_CTRL if available.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Rebased on -next to use nomap:
Signed-off-by: Simon Glass <sjg@chromium.org>
2024-01-07 13:49:08 -07:00
Heinrich Schuchardt
c95ade8dcd cmd: acpi: check HW reduced flag in acpi list
On non x86 platforms the hardware reduce flag must be set in the FADT
table. Write an error message if the flag is missing.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Rebased on -next to use nomap, add hyphens:
Signed-off-by: Simon Glass <sjg@chromium.org>
2024-01-07 13:49:02 -07:00
Heinrich Schuchardt
c5924b1cd3 cmd: acpi: fix listing DSDT and FACS
If field X_FIRMWARE_CTRL is filled, field FIRMWARE must be ignored. If
field X_DSDT is filled, field DSDT must be ignored.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Rebased on -next to use nomap:
Signed-off-by: Simon Glass <sjg@chromium.org>
2024-01-07 13:48:30 -07:00
Heinrich Schuchardt
a083ae71e0 acpi: use 64-bit addresses in FADT table
Fields X_FIRMWAE_CTRL and X_DSDT must be 64bit wide. Convert pointers to
to uintptr_t to fill these.

If field X_FIRMWARE_CTRL is filled, field FIRMWARE must be ignored. If
field X_DSDT is filled, field DSDT must be ignored. We should not fill
unused fields.

See the field definitions in chapter "5.2.9 Fixed ACPI Description Table
(FADT)" of the ACPI Specification 6.5.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2024-01-07 13:45:07 -07:00
Simon Glass
70fe238594 fdt: Allow the devicetree to come from a bloblist
Standard passage provides for a bloblist to be passed from one firmware
phase to the next. That can be used to pass the devicetree along as well.
Add an option to support this.

Tests for this will be added as part of the Universal Payload work.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-01-07 13:45:07 -07:00
Simon Glass
06ef8089f8 efi: Correct smbios-table installation
At present this code allocates memory when writing the tables and
then unnecessarily adds another memory map when installing it.

Adjust the code to allocate the tables using the normal U-Boot
mechanism. This avoids doing an EFI memory allocation early in
U-Boot, which may use memory that would be overwritten by a
'load' command, for example.

Signed-off-by: Simon Glass <sjg@chromium.org>
2024-01-07 13:45:07 -07:00
Simon Glass
a8efebe719 acpi: Write pointers to tables instead of addresses
Sandbox uses an API to map between addresses and pointers. This allows
it to have (emulated) memory at zero and avoid arch-specific addressing
details. It also allows memory-mapped peripherals to work.

As an example, on many machines sandbox maps address 100 to pointer
value 10000000.

However this is not correct for ACPI, if sandbox starts another program
(e.g EFI app) and passes it the tables. That app has no knowledge of
sandbox's address mapping. So to make this work we want to store
10000000 as the value in the table.

Add two new 'nomap' functions which clearly make this exeption to how
sandbox works.

This should allow EFI apps to access ACPI tables with sandbox, e.g. for
testing purposes.

Signed-off-by: Simon Glass <sjg@chromium.org>
Suggested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2024-01-07 13:45:07 -07:00
Simon Glass
5e3adc44a4 acpi: Rename test dm_test_setup_ctx_and_base_tables()
Use the word 'acpi' in this test so that it runs along with all the
other ACPI tests.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2024-01-07 13:45:07 -07:00
Simon Glass
aa8499680c efi: smbios: Drop support for SMBIOS2 tables
Only the v3 table is supported now, so always use this when installing
the EFI table.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2024-01-07 13:45:07 -07:00
Simon Glass
1c5f6fa388 smbios: Drop support for SMBIOS2 tables
These tables are a pain since there is no way to handle memory above
4GB. Use SMBIOS3 always.

This should hopefully not create problems on x86 devices, since SMBIOS3
was released seven years ago (2015).

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Peter Robinson <pbrobinson@gmail.com>
2024-01-07 13:45:07 -07:00
Simon Glass
31f950a963 smbios: Require the caller to align the SMBIOS table
All callers handle this alignment, so drop the unnecessary code. This
simplifies things a little.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-01-07 13:45:07 -07:00
Simon Glass
138e69149b efi: Use the correct GUID for the SMBIOS table
EFI does not use the 'anchor string' to determine the SMBIOS table
version, instead preferring to have two separate GUIDs. Use the correct
one, depending on the table version.

Call unmap_system() to balance to the use of map_sysmem()

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-01-07 13:45:07 -07:00
Simon Glass
b2b58e1ef5 smbios: Correct gd_smbios_start()
This should access arch-specific properties. Fix it and update the
existing usage.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-01-07 13:45:06 -07:00
Simon Glass
70924294f3 smbios: Use SMBIOS 3.0 to support an address above 4GB
When the SMBIOS table is written to an address above 4GB a 32-bit table
address is not large enough.

Use an SMBIOS3 table in that case.

Note that we cannot use efi_allocate_pages() since this function has
nothing to do with EFI. There is no equivalent function to allocate
memory below 4GB in U-Boot. One solution would be to create a separate
malloc() pool, or just always put the malloc() pool below 4GB.

- Use log_debug() for warning
- Rebase on Heinrich's smbios.h patch
- Set the checksum for SMBIOS3

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2024-01-07 13:45:06 -07:00
Heinrich Schuchardt
de4b91ca68 smbios: SMBIOS 3.0 (64-bit) Entry Point structure
Add definition of the SMBIOS 3.0 (64-bit) Entry Point structure.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>

Signed-off-by: Simon Glass <sjg@chromium.org>
2024-01-07 13:45:06 -07:00
Simon Glass
f19cf8d43a smbios: Move the rest of the SMBIOS2 code
Move all of this logic into the else clause, since it will not be used
for SMBIOS3

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-01-07 13:45:06 -07:00
Simon Glass
58c638330a smbios: Refactor 32-bit code into an else statement
In preparation for adding support for SMBIOS3 move this code into an
else statement. There is no functional change.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-01-07 13:45:06 -07:00
Tom Rini
c2c598e87c Merge branch 'staging' of https://source.denx.de/u-boot/custodians/u-boot-tegra into next
Documentation updates for endeavoru, lg_x3, grouper and transformers,
addition of MIPI calibration clock name for T114 (inline with T124+),
conversion of TEGRA_SUPPORT_NON_SECURE into Kconfig and endeavoru
stability improvements.
2024-01-06 09:57:56 -05:00
Tom Rini
18fa946ab9 Merge branch '2024-01-05-fw_env-fixes' into next
- A few fw_env fixes
2024-01-06 09:57:30 -05:00
Anthony Loiseau
d73a664186 fw_env: autodetect NAND erase size and env sectors
As already done for NOR chips, if device ESIZE and ENVSECTORS static
configurations are both zero, then autodetect them at runtime.

Cc: Joe Hershberger <joe.hershberger@ni.com>
cc: Stefan Agner <stefan@agner.ch>
cc: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Signed-off-by: Anthony Loiseau <anthony.loiseau@allcircuits.com>
2024-01-05 15:41:47 -05:00
Rafał Miłecki
9e3003f79d fw_env: keep calling read() until whole flash block is read
It's totally valid for read() to provide less bytes than requested
maximum. It may happen if there is no more data available yet or source
pushes data in small chunks.

This actually happens when trying to read env data from NVMEM device.
Kernel may provide NVMEM content in page size parts (like 4096 B).

This fixes warnings like:
Warning on /sys/bus/nvmem/devices/u-boot-env0/nvmem: Attempted to read 16384 bytes but got 4096
Warning on /sys/bus/nvmem/devices/u-boot-env0/nvmem: Attempted to read 12288 bytes but got 4096
Warning on /sys/bus/nvmem/devices/u-boot-env0/nvmem: Attempted to read 8192 bytes but got 4096

Since the main loop in flash_read_buf() is used to read blocks this
patch adds a new nested one.

Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
2024-01-05 15:41:47 -05:00
Rafał Miłecki
73b30800f5 fw_env: rename variables holding env data content
Rename "addr0" and "addr1" to "buf0" and "buf1" accordingly. Name "addr"
suggests that variable contains a numeric value being some kind of
address. Name "buf" is de facto a standard name for pointer to allocated
memory for reading data to.

While at it drop redundant checks for NULL before calling free().

Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
2024-01-05 15:41:47 -05:00
Rafał Miłecki
f29c5ca33d fw_env: fix reading NVMEM device's "compatible" value
Call to fread() was changed to check for return value. The problem is it
can't be checked for returning 1 (as it is) to determine success.

We call fread() with buffer size as "size" argument. Reading any
"compatible" value shorter than buffer size will result in returning 0
even on success.

Modify code to use fstat() to determine expected read length.

This fixes regression that broke using fw_env with NVMEM devices.

Fixes: c059a22b77 ("tools: env: fw_env: Fix unused-result warning")
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
2024-01-05 15:41:47 -05:00
Svyatoslav Ryhel
86e581a560 board: htc: endeavoru: add an early SPL RCM hook
Unlike all other supported Tegra devices and most known Tegra devices, the
HTC One X has no hardware way to enter APX/RCM mode, which may lead to a
dangerous situation when, if BCT is set correctly and the bootloader is
faulty, the device will hang in a permanent brick state. Exiting from this
state can be done only by disassembling the device and shortening the
testpad to the ground.

To prevent this or to minimize the probability of such an accident, it was
proposed to add the RCM rebooting hook as early into SPL as possible since
SPL is much more robust and has minimal changes that can break bootflow.

gpio_early_init_uart() function was chosen as it is the earliest function
exposed for setup by the device. Hook performs a check for volume up button
state and triggers RCM if it is pressed.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2024-01-05 18:05:42 +02:00
Tom Rini
0d53be75c7 Merge patch series "ATF and OP-TEE Firewalling for K3 devices."
Manorit Chawdhry <m-chawdhry@ti.com> says:

K3 devices have firewalls that are used to prevent illegal accesses to
memory regions that are deemed secure. The series prevents the illegal
accesses to ATF and OP-TEE regions that are present in different K3
devices.

AM62X, AM62AX and AM64X are currently in hold due to some firewall
configurations that our System Controller (TIFS) needs to handle.
The devices that are not configured with the firewalling nodes will not
be affected and can continue to work fine until the firewall nodes are
added so will be a non-blocking merge.

Test Logs: https://gist.github.com/manorit2001/4cead2fb3a19eb5d19005b3f54682627
CICD Run: https://github.com/u-boot/u-boot/pull/442
2024-01-04 16:53:49 -05:00
Manorit Chawdhry
7ff09d484e docs: board: ti: k3: Add secure booting documentation
This commit adds a general flow to explain the usage of firewalls and
the chain of trust in K3 devices.

Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2024-01-04 16:48:00 -05:00
Manorit Chawdhry
4ebb8ae040 docs: board: ti: k3: Cleanup FIT signature documentation
The previous documentation had been very crude so refactor it to make it
cleaner and concise.

Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2024-01-04 16:48:00 -05:00
Manorit Chawdhry
8ae586e08c arm: dts: k3-j7200-binman: Add firewall configurations
The following commits adds the configuration of firewalls required to
protect ATF and OP-TEE memory region from non-secure reads and
writes using master and slave firewalls present in our K3 SOCs.

Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Tested-by: Thomas Richard <thomas.richard@bootlin.com>
2024-01-04 16:48:00 -05:00
Manorit Chawdhry
b8dea0c85e arm: dts: k3-j721s2-binman: Add firewall configurations
The following commits adds the configuration of firewalls required to
protect ATF and OP-TEE memory region from non-secure reads and
writes using master and slave firewalls present in our K3 SOCs.

Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2024-01-04 16:48:00 -05:00
Manorit Chawdhry
c485567ee6 arm: dts: k3-j721e-binman: Add firewall configurations
The following commits adds the configuration of firewalls required to
protect ATF and OP-TEE memory region from non-secure reads and
writes using master and slave firewalls present in our K3 SOCs.

Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2024-01-04 16:48:00 -05:00
Manorit Chawdhry
89caf6d6c5 arm: dts: k3-binman: Add k3-security.h and include it in k3-binman.dtsi
For readability during configuring firewalls, adding k3-security.h file
and including it in k3-binman.dtsi to be accessible across K3 SoCs

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Reviewed-by: Andrew Davis <afd@ti.com>
2024-01-04 16:48:00 -05:00
Manorit Chawdhry
ba51299f60 binman: ftest: Add test for ti-secure firewall node
Add test for TI firewalling node in ti-secure.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2024-01-04 16:48:00 -05:00
Manorit Chawdhry
a3e407bef7 binman: ti-secure: Add support for firewalling entities
We can now firewall entities while loading them through our secure
entity TIFS, the required information should be present in the
certificate that is being parsed by TIFS.

The following commit adds the support to enable the certificates to be
generated if the firewall configurations are present in the binman dtsi
nodes.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2024-01-04 16:48:00 -05:00
Manorit Chawdhry
b1839fcf75 dtoc: Change dst to self in debug message
Fix the error message to not use dst and use self as it is copying the
properties to self.

While using templating if there are no subnodes defined, we end up in
this situation where "dst" isn't defined and it tries to print the error
message and fails.

'UnboundLocalError: local variable 'dst' referenced before assignment'

Fixes: 55e1278d5e ("dtoc: Allow inserting a list of nodes into another")

Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2024-01-04 16:48:00 -05:00
Svyatoslav Ryhel
5c39fbfa13 ARM: tegra114: support nonsecure state detection
Principle is exactly the same as on T124, testing of register
which behaves differently in secure and non-secure states.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2024-01-03 20:20:12 +02:00
Svyatoslav Ryhel
e692aded5e ARM: tegra114: expand MC register map
This expansion is required for nonsecure detection to work correctly.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2024-01-03 20:18:38 +02:00
Svyatoslav Ryhel
27e69fe99a ARM: tegra124: convert TEGRA_SUPPORT_NON_SECURE into Kconfig
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2024-01-03 20:18:24 +02:00
Tom Rini
42fb448a20 configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2024-01-03 09:26:16 -05:00
Tom Rini
93a0138acb Merge tag 'v2024.01-rc6' into next
Prepare v2024.01-rc6
2024-01-03 09:22:47 -05:00
Svyatoslav Ryhel
bb8a602ca9 tegra114: clock: define MIPI calibration peripheral clock
TEGRA114_CLK_MIPI_CAL is a fixed child of PLLP and is used
as clock source of the MIPI PHY calibration mechanism.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2024-01-02 19:21:24 +02:00
Svyatoslav Ryhel
ec8528c22f doc: board: tegra30: update information in board documents
Recently, the U-Boot installation process has changed significantly.
This should be depicted in documentation.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2024-01-02 19:18:42 +02:00
Tom Rini
dffa6d0210 Merge tag 'dm-next-1124' of https://source.denx.de/u-boot/custodians/u-boot-dm into next
support propagating supernode properties with bootph schema
align bloblist with v0.9 of Firmware Handoff spec
2024-01-01 12:38:15 -05:00
Simon Glass
e266d27311 bloblist: Update documentation and header comment
Align the documentation with the v0.9 spec.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Raymond Mao <raymond.mao@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2023-12-31 07:21:02 -07:00
Simon Glass
7d790a80b6 bloblist: Add alignment to bloblist_new()
Allow the alignment to be specified when creating a bloblist.

Signed-off-by: Simon Glass <sjg@chromium.org>
Co-developed-by: Raymond Mao <raymond.mao@linaro.org>
Signed-off-by: Raymond Mao <raymond.mao@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2023-12-31 07:21:02 -07:00
Simon Glass
b86b2d940c bloblist: Adjust the bloblist header
The v0.9 spec provides for a 24-byte header. Update the implementation
to match this.
Rename the fields of the bloblist header to align to the spec.
Adds an alignment field into the bloblist header.
Update the related bloblist APIs and UT testcases.

Signed-off-by: Simon Glass <sjg@chromium.org>
Co-developed-by: Raymond Mao <raymond.mao@linaro.org>
Signed-off-by: Raymond Mao <raymond.mao@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2023-12-31 07:21:02 -07:00
Simon Glass
b6e83826ef bloblist: Reduce blob-header size
The v0.9 spec provides for an 8-byte header for each blob, with fewer
fields.
The blob data start address should be aligned to the alignment specified
by the bloblist header.
Update the implementation to match this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Co-developed-by: Raymond Mao <raymond.mao@linaro.org>
Signed-off-by: Raymond Mao <raymond.mao@linaro.org>
2023-12-31 07:21:02 -07:00
Simon Glass
f9ef9fb033 bloblist: Handle alignment with a void entry
Rather than setting the alignment using the header size, add an entirely
new entry to cover the gap left by the alignment.

Signed-off-by: Simon Glass <sjg@chromium.org>
Co-developed-by: Raymond Mao <raymond.mao@linaro.org>
Signed-off-by: Raymond Mao <raymond.mao@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2023-12-31 07:21:02 -07:00
Simon Glass
997dac6ede bloblist: Checksum the entire bloblist
Use a sinple 8-bit checksum for bloblist, as specified by the spec
version 0.9.
Spec v0.9 specifies that the entire bloblist area is checksummed,
including unused portions. Update the code to follow this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Co-developed-by: Raymond Mao <raymond.mao@linaro.org>
Signed-off-by: Raymond Mao <raymond.mao@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2023-12-31 07:21:02 -07:00
Simon Glass
47e1047b0c bloblist: Drop spare value from bloblist record
Drop spare value from bloblist record header.

For now it is still present in the header, with an underscore, so that
tests continue to pass.

Signed-off-by: Simon Glass <sjg@chromium.org>
Co-developed-by: Raymond Mao <raymond.mao@linaro.org>
Signed-off-by: Raymond Mao <raymond.mao@linaro.org>
2023-12-31 07:21:02 -07:00
Simon Glass
1f06ed41cc bloblist: Access record hdr_size and tag via a function
Convert accesses to tag and hdr_size via function for grouping tag and
hdr_size together later.

Signed-off-by: Simon Glass <sjg@chromium.org>
Co-developed-by: Raymond Mao <raymond.mao@linaro.org>
Signed-off-by: Raymond Mao <raymond.mao@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2023-12-31 07:21:02 -07:00
Simon Glass
0b9f77f140 bloblist: Set version to 1
The new bloblist for v0.9 has version 1 so update this value.

Signed-off-by: Simon Glass <sjg@chromium.org>
Co-developed-by: Raymond Mao <raymond.mao@linaro.org>
Signed-off-by: Raymond Mao <raymond.mao@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-12-31 07:21:02 -07:00
Simon Glass
5a53e56011 bloblist: Change the magic value
This uses a new value with spec v0.9 so change it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Co-developed-by: Raymond Mao <raymond.mao@linaro.org>
Signed-off-by: Raymond Mao <raymond.mao@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-12-31 07:21:02 -07:00
Simon Glass
1a2e02f955 bloblist: Adjust API to align in powers of 2
The updated bloblist structure stores the alignment as a power-of-two
value in its structures. Adjust the API to use this, to avoid needing to
calling ilog2().
Update the bloblist alignment from 16 bytes to 8 bytes.
Drop a stale comment while we are here.

Signed-off-by: Simon Glass <sjg@chromium.org>
Co-developed-by: Raymond Mao <raymond.mao@linaro.org>
Signed-off-by: Raymond Mao <raymond.mao@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2023-12-31 07:21:02 -07:00
Simon Glass
e748e4b780 bloblist: Update the tag numbering
Align bloblist tags with the FW handoff spec v0.9.
The most common ones are from 0.
TF related ones are from 0x100.
All non-standard ones from 0xfff000.

Added new defined tags:
BLOBLISTT_OPTEE_PAGABLE_PART for TF.
BLOBLISTT_TPM_EVLOG and BLOBLISTT_TPM_CRB_BASE for TPM.

Signed-off-by: Simon Glass <sjg@chromium.org>
Co-developed-by: Raymond Mao <raymond.mao@linaro.org>
Signed-off-by: Raymond Mao <raymond.mao@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2023-12-31 07:21:02 -07:00
Simon Glass
aca95282c1 Makefile: Use the fdtgrep -u flag
Use this flag so that the bootph binding is obeyed correctly.

Add a comment about what is going on.

Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes: https://source.denx.de/u-boot/custodians/u-boot-dm/-/issues/12
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-12-31 07:21:02 -07:00
Simon Glass
7a06cc2027 fdtgrep: Allow propagating properties up to supernodes
The existing bootph binding is defined such that properties in a
subnode are also implied in the supernode also, as in this example:

   buttons {
      /* bootph,pre-ram is implied by btn1 */
      compatible = "gpio-keys";

      btn1 {
         bootph,pre-ram;
         gpios = <&gpio_a 3 0>;
         label = "button1";
         linux,code = <BTN_1>;
      };

Provide an option to implement this in fdtgrep.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-12-31 07:21:02 -07:00
Simon Glass
0b2e47be2c sandbox: Correct SPL condition for building devicetree
With sandbox, CONFIG_SANDBOX is y so the current rule ends up building
the devicetree for only those SPL builds where it is unwanted.

Correct the condition. This allows sandbox_vpl to produce a
u-boot-vpl.dtb file.

Fixes: e7fb789612 ("sandbox: Remove OF_HOSTFILE")

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-12-31 07:21:02 -07:00
Simon Glass
61a695e451 fdtgrep: Move property checking into a function
The h_include() function includes a piece which checks if a node
contains a property being searched for. Move this into its own
function to reduce the size of the h_include() function.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-12-31 07:21:02 -07:00
Simon Glass
490afe7428 fdtgrep: Simplify code to inverting the match
The code to invert the match in h_include() is a bit convoluted.
Simplify it by using disp->invert only once.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-12-31 07:21:02 -07:00
Simon Glass
b1823ed171 fdtgrep: Tidy up comment for h_include()
Copy the comment from fdt_first_region() so that it is clear what value
this function returns.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-12-31 07:21:02 -07:00
Simon Glass
f3acd20685 fdtgrep: Correct references to fdt_find_regions()
The function name is actually fdtgrep_find_regions() so update the name
in comments accordinging.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-12-31 07:21:02 -07:00
Simon Glass
9dab5bd3f8 fdtgrep: Correct ordering of flags
Two of the flags are out of order, so fix this.

Also adjust the ordering of one flag in the main switch()

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-12-31 07:21:02 -07:00
Simon Glass
233a61373b fdtgrep: Tidy up a few type warnings and comments
Align the code with the upstream version at fdt-tools which had a few
tweaks before being applied.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-12-31 07:21:02 -07:00
Simon Glass
2c714d682d x86: coral: Align bootph SPI-flash subnodes with parent
The subnode has different tags from the parents, which is not correct.
Fix the subnode.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-12-31 07:21:02 -07:00
Heinrich Schuchardt
69c3705be9 binman: used-before-assignment in ftest.py
Pytest 7.4.3 complains if a variable is used in a finally clause without
having been initialized before the try clause.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-12-31 07:21:02 -07:00
Heinrich Schuchardt
86aeacca67 buildman: type cotaining
%s/cotaining/containing/

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-12-31 07:21:02 -07:00
Tom Rini
2b28c3b871 Merge patch series "Modernize U-Boot shell"
Francis Laniel <francis.laniel@amarulasolutions.com> says:

During 2021 summer, Sean Anderson wrote a contribution to add a new shell, based
on LIL, to U-Boot [1, 2].
While one of the goals of this contribution was to address the fact actual
U-Boot shell, which is based on Busybox hush, is old there was a discussion
about adding a new shell versus updating the actual one [3, 4].

So, in this series, with Harald Seiler, we updated the actual U-Boot shell to
reflect what is currently in Busybox source code.
Basically, this contribution is about taking a snapshot of Busybox shell/hush.c
file (as it exists in commit 37460f5da) and adapt it to suit U-Boot needs.

This contribution was written to be as backward-compatible as possible to avoid
breaking the existing.
So, the modern hush flavor offers the same as the actual, that is to say:
1. Variable expansion.
2. Instruction lists (;, && and ||).
3. If, then and else.
4. Loops (for, while and until).
No new features offered by Busybox hush were implemented (e.g. functions).

It is possible to change the parser at runtime using the "cli" command:
=> cli print
old
=> cli set modern
=> cli print
modern
=> cli set old
The default parser is the old one.
Note that to use both parser, you would need to set both
CONFIG_HUSH_MODERN_PARSER and CONFIG_HUSH_OLD_PARSER.

In terms of testing, new unit tests were added to ut to ensure the new behavior
is the same as the old one and it does not add regression.
Nonetheless, if old behavior was buggy and fixed upstream, the fix is then added
to U-Boot [5].
In sandbox, all of these tests pass smoothly:
=> printenv board
board=sandbox
=> ut hush
Running 20 hush tests
...
Failures: 0
=> cli set modern
=> ut hush
Running 20 hush tests
...
Failures: 0

Thanks to the effort of Harald Seiler, I was successful booting a board:
=> printenv fdtfile
fdtfile=amlogic/meson-gxl-s905x-libretech-cc.dtb
=> cli get
old
=> boot
...
root@lepotato:~#
root@lepotato:~# reboot
...
=> cli set modern
=> cli get
modern
=> printenv fdtfile
fdtfile=amlogic/meson-gxl-s905x-libretech-cc.dtb
=> boot
...
root@lepotato:~#

This contribution indeed adds a lot of code and there were concern about its
size [6, 7].
With regard to the amount of code added, the cli_hush_upstream.c is 13030 lines
long but it seems a smaller subset is really used:
gcc -D__U_BOOT__ -E common/cli_hush_upstream.c | wc -l
2870
Despite this, it is better to still have the whole upstream code for the sake of
easing maintenance.
With regard to memory size, I conducted some experiments for version 8 of this
series and for a subset of arm64 boards and found the worst case to be 4K [8].
Tom Rini conducted more research on this and also found the increase to be
acceptable [9].

If you want to review it - your review will really be appreciated - here are
some information regarding the commits:
* commits marked as "test:" deal with unit tests.
* commit "cli: Add Busybox upstream hush.c file." copies Busybox shell/hush.c
into U-Boot tree, this explain why this commit contains around 12000 additions.
* commit "cli: Port Busybox 2021 hush to U-Boot." modifies previously added file
to permit us to use this as new shell.
The really good idea of #include'ing Busybox code into a wrapper file to define
some particular functions while minimizing modifications to upstream code comes
from Harald Seiler.
* commit "cmd: Add new parser command" adds a new command which permits
selecting parser at runtime.
I am not really satisfied with the fact it calls cli_init() and cli_loop() each
time the parser is set, so your reviews would be welcomed.
* Other commits focus on enabling features we need (e.g. if).
2023-12-28 14:38:25 -05:00
Francis Laniel
2a58783f94 configs: Use old hush for several boards
The keymile board family is not compatible with modern hush parser.
Indeed, This boards used set_local_var() to store some variables as local shell.
They then used get_local_var() to retrieve the variables values.
Sadly, this two functions do not exist with CONFIG_HUSH_MODERN_PARSER.
A patch was proposed to use environment variables rather than local variables
but it does not tackle the problem, so complementary work is needed to make
this boards use CONFIG_HUSH_MODERN_PARSER.

Also, with CONFIG_HUSH_MODERN_PARSER, kirkwoord sheevaplug and phytec bk4r1 hit
their board limits, so better to stick with old hush.

Cc: Holger Brunck <holger.brunck@hitachienergy.com>
Link: https://marc.info/?l=u-boot&m=165541917618725&w=2
Signed-off-by: Francis Laniel <francis.laniel@amarulasolutions.com>
2023-12-28 12:02:56 -05:00
Francis Laniel
78912cfde2 cmd: Set modern hush as default shell
Signed-off-by: Francis Laniel <francis.laniel@amarulasolutions.com>
2023-12-28 12:02:56 -05:00
Francis Laniel
c24cb3ebff cli: modern_hush: Add upstream commits up to 2nd October 2023.
This commit adds the following hush busybox upstream commits:
791b222dd55d ("sleep: fix "sleep -- ARGS"")
5353df91cba7 ("Update applet size estimates")
e41e481fd571 ("hush: fix a compile failure")
07a95cfcabb0 ("ash: disable check for "good" function name, bash does not check this")
e5692e2342c6 ("hush: quote values in "readonly" output")
96769486e20f ("shell: move varcmp() to shell_common.h and use it in hush")
bab8828b0dad ("hush: fix expansion of space in "a=${a:+$a }c" construct")
b5be8da350b5 ("hush: make "false" built-in")
6824298ab4d3 ("hush: fix ELIF cmd1;cmd2 THEN ... not executing cmd2, closes 15571")
3a7f00eadcf4 ("hush: add comment about abort on syntax error %{^}")
acae889dd972 ("ash,hush: tab completion of functions and aliases")
90b607d79a13 ("hush: quote variable values printed by "set" (match ash behavior)")
6748e6494c22 ("hush (NOMMU): fix LINENO in execed children")
fd5fb2d2b596 ("hush: speed up "big heredoc" code")
1409432d072e ("hush: add TODO comment")
93ae7464e6e4 ("hush: restore SIGHUP handling, this time explain why we do what we do")
1fdb33bd07e5 ("hush: restore tty pgrp on SIGHUP")
6101b6d3eaa0 ("hush: remove special handling of SIGHUP")
93e0898c663a ("shell: fix SIGWINCH and SIGCHLD (in hush) interrupting line input, closes 15256")
969e00816835 ("hush: code shrink")
27be0e8cfeb6 ("shell: fix compile failures in some configs")
7d1c7d833785 ("ash,hush: use HOME for tab completion and prompts")
21afddefd258 ("hush: fix "error: invalid preprocessing directive ##"")
e53c7dbafc78 ("hush: fix set -n to act immediately, not just after run_list()")
574b9c446da1 ("hush: fix var_LINENO3.tests failure")
49bcf9f40cff ("hush: speed up ${x//\*/|} too")
53b2fdcdba4c ("*: add NOINLINEs where code noticeably shrinks")
7c3e96d4b3d4 ("shell: use more compact SHELL_ASH / HUSH config defines. no code changes")
62f1eed1e191 ("hush: in a comment, document what -i might be doing")
aaf3d5ba74c5 ("shell: tweak --help")
db5546ca1018 ("libbb: code shrink: introduce and use [_]exit_SUCCESS()")
931c55f9e2b4 ("libbb: invert the meaning of SETUP_ENV_NO_CHDIR -> SETUP_ENV_CHDIR")
12566e7f9b5e ("ash,hush: fix handling of SIGINT while waiting for interactive input")
987be932ed3c ("*: slap on a few ALIGN_PTR where appropriate")

Signed-off-by: Francis Laniel <francis.laniel@amarulasolutions.com>
2023-12-28 12:02:56 -05:00
Francis Laniel
2223c49c75 test: hush: Fix loop tests for modern hush
Modifies return code got from while loop as modern hush always returns 0 from
while loop.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Francis Laniel <francis.laniel@amarulasolutions.com>
2023-12-28 12:02:56 -05:00
Francis Laniel
e252f50f27 cli: hush_modern: Enable loops
Enables the use of for, while and until loops for command line as
well as with run_command().

Signed-off-by: Francis Laniel <francis.laniel@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-12-28 12:02:56 -05:00
Francis Laniel
374b77ed9e cli: hush_modern: Enable if keyword
Adds support for "if then else" construct both for command line interface and
through run_command().

Signed-off-by: Francis Laniel <francis.laniel@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-12-28 12:02:56 -05:00
Francis Laniel
d8b256308d cli: hush_modern: Enable using < and > as string compare operators
In Busybox hush, '<' and '>' are used as redirection operators.
For example, cat foo > bar will write content of file foo inside file bar.
In U-Boot, we do not have file system, so we can hardly redirect command output
inside a file.

But, in actual U-Boot hush, these operators ('<' and '>') are used as string
compare operators.
For example, test aaa < bbb returns 0 as aaa is before bbb in the dictionary.
Busybox hush also permits this, but operators need to be escaped ('\<' and
'\>').
Indeed, if escaping is needed it permits the developer to think about its code,
as in a lot of case, we want to compare integers (using '-lt' or '-gt') rather
than strings.

As testing in U-Boot is handled by the test command, we will stick with the
original behaviour and not adapt to Busybox one.

Nonetheless, if one day we decide to implement test with '[[ ]]', we will then
stick to upstream Busybox behavior.

Signed-off-by: Francis Laniel <francis.laniel@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-12-28 12:02:56 -05:00
Francis Laniel
410e78df06 test: hush: Fix variable expansion tests for modern hush
Modifies the expected result for modern hush.
Indeed, there were bugs in actual U-Boot hush which were fixed in upstream
Busybox.
As modern hush is based on upstream Busybox, these bugs no longer exist.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Francis Laniel <francis.laniel@amarulasolutions.com>
2023-12-28 12:02:56 -05:00
Francis Laniel
6d3914f9c1 test: hush: Fix instructions list tests for modern hush
Modifies the expected result for modern hush.
Indeed, there were bugs in actual U-Boot hush which were fixed in upstream
Busybox.
As modern hush is based on upstream Busybox, these bugs no longer exist.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Francis Laniel <francis.laniel@amarulasolutions.com>
2023-12-28 12:02:56 -05:00
Francis Laniel
3ea3c57ef5 cli: add modern hush as parser for run_command*()
Enables using, in code, modern hush as parser for run_command function family.
It also enables the command run to be used by CLI user of modern hush.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Francis Laniel <francis.laniel@amarulasolutions.com>
2023-12-28 12:02:56 -05:00
Francis Laniel
3b13faf9f3 cli: hush_modern: Add functions to be called from run_command()
run_command() is called internally by the command run and it can also be called
directly from U-Boot code, e.g. to do unit tests.
This commit adds this path to go to modern hush.

Signed-off-by: Francis Laniel <francis.laniel@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-12-28 12:02:56 -05:00
Francis Laniel
74e425407f cli: hush_modern: Enable variables expansion for modern hush
Enables variables expansion for modern hush, both for local and environment
variables.
So the following commands:
foo=bar
echo $foo
setenv bar foo
echo $bar
leads to "bar" and "foo" being printed on console output.

Signed-off-by: Francis Laniel <francis.laniel@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-12-28 12:02:56 -05:00
Francis Laniel
9a06837731 cli: Enables using modern hush parser as command line parser
If one defines HUSH_MODERN_PARSER, it is then possible to use modern parser with:
=> cli get
old
=> cli set modern
=> cli get
modern

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Francis Laniel <francis.laniel@amarulasolutions.com>
2023-12-28 12:02:56 -05:00
Francis Laniel
6bb39f5d16 cmd: Add new cli command
This command can be used to print the current parser with 'cli get'.
It can also be used to set the current parser with 'cli set'.
For the moment, only one value is valid for set: old.

Signed-off-by: Francis Laniel <francis.laniel@amarulasolutions.com>
2023-12-28 12:02:56 -05:00
Francis Laniel
603a814a33 global_data.h: add GD_FLG_HUSH_OLD_PARSER flag
This flag is used to indicate we are using the hush parser.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Francis Laniel <francis.laniel@amarulasolutions.com>
2023-12-28 12:02:56 -05:00
Francis Laniel
30dcef8951 cli: Add menu for hush parser
For the moment, the menu contains only entry: HUSH_OLD_PARSER which is the
default.
The goal is to prepare the field to add a new hush parser which guarantees
actual behavior is still correct.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Francis Laniel <francis.laniel@amarulasolutions.com>
2023-12-28 12:02:56 -05:00
Francis Laniel
8197f01b9d cli: Port upstream Busybox hush to U-Boot
Adds new file cli_hush_upstream.c, it is a copy of Busybox hush file as it was of
time to commit 37460f5da.
This commit modifies Busybox hush to not compile some part specific to Busybox
and adds some code needed by U-Boot.
The modifications consists mainly on adding code #if(n)def guards.

For the moment, this refurbished flavor of hush only permits running command
without any keywords (i.e., if and for are not recognized) or variable expansion
(i.e., echo $foo prints foo and not value stored in variable foo).

A new file was also added to define some functions specific to U-Boot.

Signed-off-by: Francis Laniel <francis.laniel@amarulasolutions.com>
Signed-off-by: Harald Seiler <hws@denx.de>
2023-12-28 12:02:56 -05:00
Francis Laniel
b234f7e3c3 cli: Add Busybox upstream hush.c file
This commit adds new file cli_hush_upstream.c, it is a copy of Busybox hush
file it was of time to Busybox commit 37460f5da.

Signed-off-by: Francis Laniel <francis.laniel@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-12-28 12:02:56 -05:00
Francis Laniel
432c997eb3 test: hush: Test hush loops
The added tests verifies correct behavior of for, while and until loops.

Signed-off-by: Francis Laniel <francis.laniel@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-12-28 12:02:56 -05:00
Francis Laniel
2a70feaeee test: hush: Test hush commands list
Verifies behavior of commands separated by ';', '&&' and '||'.

Signed-off-by: Francis Laniel <francis.laniel@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-12-28 12:02:56 -05:00
Francis Laniel
261d29e2f3 test: hush: Test hush variable expansion
Verifies shell variables are replaced by their values.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Francis Laniel <francis.laniel@amarulasolutions.com>
2023-12-28 12:02:56 -05:00
Francis Laniel
4dc305f95b test/py: hush_if_test: Remove the test file
5804ebfeb1ce ("test: hush: Test hush if/else") translated this test to a C test,
so this python file is no more needed.

Signed-off-by: Francis Laniel <francis.laniel@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-12-28 12:02:56 -05:00
Francis Laniel
d3bc2c54ac test: hush: Test hush if/else
As asked in commit 9c6bf1715f ("test/py: hush_if_test: Add tests to cover
octal/hex values"), this commit translates test_hush_if_test.py to a C test.

Signed-off-by: Francis Laniel <francis.laniel@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-12-28 12:02:56 -05:00
Francis Laniel
cb1277cc4d test: Add framework to test hush behavior
Introduce a new subcommand to ut: ut hush.
For the moment, this command does nothing, future commits will add tests which
will be run on command call.

Note that CONFIG_HUSH_PARSER must be defined to compile this new subcommand.

Signed-off-by: Francis Laniel <francis.laniel@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-12-28 12:02:56 -05:00
Tom Rini
64e47952f5 Merge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-riscv into next
- Andes: Enable Andes CPU memboost and ECC feature by default
- Sifive: Add private L2 cache driver
2023-12-28 07:54:54 -05:00
Leo Yu-Chi Liang
9924d44dbc andes: ae350: Enable MISC_INIT_R for ae350 platform
Enable MISC_INIT_R for ae350 to support CPU name detection
and re-sync the configs via make savedefconfig.

Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
2023-12-27 17:29:11 +08:00
Leo Yu-Chi Liang
936b503030 andes: ae350: Save cpu name to env
Detect CPU name through marchid and then save it to env.

Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
2023-12-27 17:29:11 +08:00
Leo Yu-Chi Liang
61d5c543f3 andes: cpu: Enable cache and TLB ECC support
Andes CPU supports cache and TLB ECC.
Enable them by default.

Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
2023-12-27 17:29:07 +08:00
Leo Yu-Chi Liang
bf12bb99d8 andes: cpu: Enable memboost feature
Andes CPU has memboost feature including prefetch,
write-around and non-blocking load. Enable them by default.

Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
2023-12-27 17:29:07 +08:00
Leo Yu-Chi Liang
b0469041c0 andes: ae350: Implement cache switch via Kconfig
Kconfig provides SYS_[I|D]CACHE_OFF config options to switch off caches.
Provide the corresponding implementation to the options.

Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
2023-12-27 17:29:07 +08:00
Leo Yu-Chi Liang
c36eb2f917 andes: csr.h: Clean up CSR definition
Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
2023-12-27 17:29:07 +08:00
Michal Simek
670db88c79 riscv: Extend board compatible string with "qemu,mbv"
Extend compatible string to match the latest change in dt binding.

Fixes: 7576ab2fac ("riscv: Add support for AMD/Xilinx MicroBlaze V")
Signed-off-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-12-27 17:29:02 +08:00
Zong Li
40c76dfed2 riscv: cache: support cache enable in SPL stage
The power gating feature of pl2 should be enabled as early as possible,
it would be better to put it in SPL stage.

Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-12-27 17:28:57 +08:00
Zong Li
64e8482f1c cache: add sifive private L2 cache driver
This driver is currently responsible for enabling the clock gating
feature of SiFive pre core's private L2 cache.

Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-12-27 17:28:57 +08:00
Heinrich Schuchardt
4b151562bb bootmeth: pass size to efi_binary_run()
If we call efi_binary_run() with size parameter set to zero, we get an error

     Not a PE-COFF file

Fill the missing value.

Fixes: 1373ffde52 ("Merge tag 'v2024.01-rc5' into next")
Fixes: 7017fc54a5 ("bootmeth: use efi_loader interfaces instead of bootefi command")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2023-12-22 10:36:50 -05:00
Tom Rini
7c4647b8fb Merge patch series "Complete decoupling of bootm logic from commands"
Simon Glass <sjg@chromium.org> says:

This series continues refactoring the bootm code to allow it to be used
with CONFIG_COMMAND disabled. The OS-handling code is refactored and
a new bootm_run() function is created to run through the bootm stages.
This completes the work.

A booti_go() function is created also, in case it proves useful, but at
last for now standard boot does not use this.

This is cmdd (part d of CMDLINE refactoring)
It depends on dm/bootstda-working
which depends on dm/cmdc-working
2023-12-21 16:10:00 -05:00
Simon Glass
d37086a95f bootm: Create a new boot_run() function to handle booting
Create a common function used by the three existing bootz/i/m_run()
functions, to reduce duplicated code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Suggested-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-12-21 16:07:52 -05:00
Simon Glass
e7683c3675 bootm: Create a function to run through the booti states
In a few places, the booti command is used to handle a boot. We want
these to be done without needing CONFIG_CMDLINE, so add a new
booti_run() function to handle this.

So far this is not used.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-12-21 16:07:52 -05:00
Simon Glass
e4cee649b9 stm32: Use bootm_run() and bootz_run()
Use the new bootm/z_run() functions to avoid having to create an
argument list for the stm32prog code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2023-12-21 16:07:52 -05:00
Simon Glass
3405c9b6a5 bootm: Create a function to run through the bootz states
In a few places, the bootz command is used to handle a boot. We want
these to be done without needing CONFIG_CMDLINE, so add a new
bootz_run() function to handle this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-12-21 16:07:52 -05:00
Simon Glass
6b50aff13f stm32: Use local vars in stm32prog for initrd and fdt
Rather than assigning to the bootm_argv[] array multiple times, use
local variables for the two things that can change and assign them at
the end.

This makes it easier to drop the array eventually.

Tidu up an overly short line while we are here.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2023-12-21 16:07:52 -05:00
Simon Glass
e1a24c025c bootm: Create a function to run through the bootm states
In quite a few places, the bootm command is used to handle a boot. We
want these to be done without needing CONFIG_CMDLINE, so add a new
bootm_run() function to handle this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-12-21 16:07:52 -05:00
Simon Glass
725ddf1f24 bootm: Tidy up boot_selected_os()
Use struct bootm_info with this function, to avoiding needing to
create a new one.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-12-21 16:07:52 -05:00
Simon Glass
b5d397f489 bootm: Rename do_bootm_states() to bootm_run_states()
Rename the function to bootm_run_states() to better indicate ts
purpose. The 'do_' prefix is used to indicate a command processor,
which this is now not.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-12-21 16:07:52 -05:00
Simon Glass
a6c49161cb bootm: Drop arguments from do_bootm_states()
Use the bootm_info struct to hold the information required by bootm.

Now that none of the functions called from do_bootm_states() needs an
argv[] list, change the arguments of do_bootm_states() as well. Take
care to use the same value for boot_progress even though it is a little
inconsistent.

For booti make sure it only uses argv[] and argc at the top of the
function, so we can eventually refactor to remove these parameters.

With bootm, some OSes need access to the arguments provided to the
command, so set these up in the bootm_info struct, for bootm only.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-12-21 16:07:52 -05:00
Simon Glass
31fda96bb6 bootz: Avoid use of #ifdef
Use the compiler to get the set of states, instead of the preprocessor.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-12-21 16:07:52 -05:00
Simon Glass
0c96b6817f booti: Avoid use of #ifdef
Use the compiler to get the set of states, instead of the preprocessor.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-12-21 16:07:52 -05:00
Simon Glass
e370e3df10 bootm: Move do_bootm_states() comment to header file
This is an exported function, so move the function comment to the
bootm.h header file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-12-21 16:07:52 -05:00
Simon Glass
c2211ff651 bootm: Add more fields to bootm_info
Add fields for the three bootm parameters and other things needed for
booting. Also add a helper to set up the struct correctly.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-12-21 16:07:52 -05:00
Simon Glass
a48336e5ea bootm: Adjust arguments of boot_os_fn
Adjust boot_os_fn to use struct bootm_info instead of the separate
argc, argv and image parameters. Update the handlers accordingly. Few
of the functions make use of the arguments, so this improves code size
slightly.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-12-21 16:07:52 -05:00
Simon Glass
c49216253d bootm: Create a struct for argument information
Some OS functions require the arguments to the 'bootm' command. This is
inconvenient for two reasons.

Firstly, there may not be any actual command, if CMDLINE is not enabled
and programmatic boot is being used.

Secondly, most functions don't require the arguments, so it is
inefficient to pass them when not needed. For example it increases code
size.

Create a new struct which holds the arguments, which can be used if
needed.

Add the images pointer as well, since this is commonly needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-12-21 16:07:52 -05:00
Simon Glass
59ca40a954 sandbox: bootm: Enable more bootm OS methods
It is useful for sandbox to build as much code as possible. Enable
support for booting various other operating systems. Add the missing
cache functions.

These operating systems do not actually boot on sandbox, of course.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-12-21 16:07:52 -05:00
Simon Glass
6443a3dad5 bootm: Adjust how the board is reset
Use reset_cpu() to reset the board, copying the logic from the 'reset'
command. This makes more sense than directly calling the do_reset()
function with the arguments passsed to the bootm command.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
2023-12-21 16:07:52 -05:00
Simon Glass
c35bfd07ec riscv: Add a reset_cpu() function
The current do_reset() is called from a command context. Add a function
which can be used from anywhere, as is done on ARM. Adjust do_reset()
to call it.

Note that reset_cpu() is normally provided by SYSRESET so make this
declaration conditional on that being disabled.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Chanho Park <chanho61.park@samsung.com>
Tested-by: Chanho Park <chanho61.park@samsung.com>
2023-12-21 16:07:52 -05:00
Simon Glass
6557eb73d6 nios2: Add a reset_cpu() function
The current do_reset() is called from a command context. Add a function
which can be used from anywhere, as is done on ARM.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-12-21 16:07:52 -05:00
Simon Glass
5ee545a9db ppc: Add a reset_cpu() function
The current do_reset() is called from a command context. Add a function
which can be used from anywhere, as is done on ARM.

This is only needed if CONFIG_SYSRESET is disabled.

Since there are lots of reset functions, this one actually just calls
do_reset(). Future refactoring could correct this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-12-21 16:07:52 -05:00
Simon Glass
79353aab15 m68k: Add a reset_cpu() function
The current do_reset() is called from a command context. Add a function
which can be used from anywhere, as is done on ARM.

Since there are lots of reset functions, this one actually just calls
do_reset(). Future refactoring could correct this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Angelo Dureghello <angelo@kernel-spcece.org>
2023-12-21 16:07:52 -05:00
Simon Glass
4f4490a79e mips: Add a reset_cpu() function
The current do_reset() is called from a command context. Add a function
which can be used from anywhere, as is done on ARM.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-12-21 16:07:52 -05:00
Tom Rini
ced928b199 Merge branch '2023-12-21-assorted-updates-and-fixes' into next
- A few board fixes along with IOMMU enhancements and general fixes
2023-12-21 15:35:03 -05:00
Csókás Bence
fa78301a98 lib: rsa: Print detailed error info in rsa_engine_init() on engine resolution failure
Signed-off-by: Csókás Bence <csokas.bence@prolan.hu>
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-12-21 11:59:49 -05:00
Tomas Alvarez Vanoli
63a2a5082e board/keymile/kmcent2: fix update-nor indentation
variable was indented as part of the value of the previous variable.

Signed-off-by: Tomas Alvarez Vanoli <tomas.alvarez-vanoli@hitachienergy.com>
Signed-off-by: Holger Brunck <holger.brunck@hitachienergy.com>
2023-12-21 11:59:49 -05:00
Caleb Connolly
d3db45cb9c iommu: add qcom-hyp-smmu
Add a basic implementation of the ARM SMMU. This driver is intended for
use on Qualcomm platforms where the SMMU has been configured by a previous
bootloader, cannot be turned off, and doesn't support BYPASS streams.
It keeps all existing stream mappings and only creates new ones for stream
ids that aren't already configured.

This driver is necessary to support peripherals that perform DMA which
weren't configured by the previous stage bootloader (for example USB).
It works by allocating a context bank using identity mapping (as U-Boot
doesn't use virtual addresses).

Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2023-12-21 11:59:49 -05:00
Caleb Connolly
76c53dad6b iommu: add a connect op
Add an optional iommu callback to be invoked before a device probes.
This can be used to configure the IOMMU in preparation for the device
(e.g. by allocating a context bank)

Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2023-12-21 11:59:49 -05:00
Caleb Connolly
e96ecbe719 iommu: fix compilation when CONFIG_PCI disabled
The dev_pci_iommu_enable() function is only available when CONFIG_PCI is
enabled, replace the runtime check with a preprocessor one to fix
compilation with pci disabled.

Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2023-12-21 11:59:49 -05:00
Francesco Dolcini
f1b809c55c configs: verdin-am62: Disable SPL FIT Overlay
Disable CONFIG_SPL_LOAD_FIT_APPLY_OVERLAY, this is not required nor used
on verdin am62, disable it to save precious binary size.

Update defconfig using savedefconfig, this adds CONFIG_OF_LIBFDT_OVERLAY
explicitly.

Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2023-12-21 11:59:49 -05:00
Matthias Schiffer
e91d6607af boot: add support for fdt_fixup command in environment
The "fdt" command is convenient for making small changes to the OS FDT,
especially during development. This is easy when the kernel and FDT are
loaded separately, but can be cumbersome for FIT images, requiring to
unpack the image, manually apply overlays, etc.

Add an option to execute a command "fdt_fixup" from the environment at
the beginning of image_setup_libfdt() (after overlays are applied, and
before the other fixups).

Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-12-21 11:59:49 -05:00
Manorit Chawdhry
0d72b0f2f8 include: env: ti: ti_common: Run main_cpsw0_qsgmii_phyinit conditionally
The main_cpsw0_qsgmii_phyinit command is defined only for certain TI
SoCs which have the do_main_cpsw0_qsgmii_phyinit variable set.

Add a check to ensure that the main_cpsw0_qsgmii_phyinit command is run
only for such SoCs.

Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
2023-12-21 11:58:18 -05:00
Mayuresh Chitale
cd57cf9ac4 fs: Fix SPL build if FS_LOADER is enabled
If FS_LOADER is enabled for the SPL then the build fails with the error:

fs/fs.o:(.data.rel.fstypes+0x128):
undefined reference to `smh_fs_set_blk_dev'
fs/fs.o:(.data.rel.fstypes+0x140):
undefined reference to `smh_fs_size'
fs/fs.o:(.data.rel.fstypes+0x148):
undefined reference to `smh_fs_read'
fs/fs.o:(.data.rel.fstypes+0x150):
undefined reference to `smh_fs_write'

Fix the error by populating the semihosting entry in the fs_types array
only for non-SPL builds.

Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
2023-12-21 11:58:18 -05:00
Tom Rini
ae797e022e Merge branch '2023-12-21-header-inclusion-cleanup' into next
- Merge in changes to clean up various places that used <common.h> or
  <linux/kconfig.h>
2023-12-21 11:51:58 -05:00
Tom Rini
467382ca03 lib: Remove <common.h> inclusion from these files
After some header file cleanups to add missing include files, remove
common.h from all files in the lib directory. This primarily means just
dropping the line but in a few cases we need to add in other header
files now.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-12-21 08:54:37 -05:00
Tom Rini
1e8ce11a0b include: Further cleanup includes
Add some missing headers such as <linux/errno.h> or <linux/types.h> or
<linux/kernel.h> to header files that make direct usage of things
provided by these headers.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-12-21 08:54:37 -05:00
Tom Rini
4abbed7e42 display_options: Clean up headers
In include/display_options.h we cannot include ourself, but do need
<linux/types.h> directly. Then in lib/display_options.c we further clean
the list to remove common.h.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-12-21 08:54:37 -05:00
Tom Rini
c38cb227d3 efi_loader: Remove <common.h>
We largely do not need <common.h> in these files, so drop it. The only
exception here is that efi_freestanding.c needs <linux/types.h> and had
been getting that via <common.h>.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-12-21 08:54:37 -05:00
Tom Rini
d1f072aa25 rmobile: Add <mach/rmobile.h> to cpu_info-rzg2l.c
In order for RMOBILE_CPU_TYPE_R9A07G044L to be defined we need to
include <mach/rmobile.h> here.

Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-12-21 08:54:37 -05:00
Tom Rini
bc9c7ccc87 lib/sha*.c: Update header list
Cleanup the list of headers we include here. For the tools build we only
need to exclude <cyclic.h> as that's used by the target build for the
prototype for schedule(), and we don't need to get that via
<watchdog.h>. We can also make use of our <string.h> intentionally
existing as a redirection to <linux/string.h> to reduce ifdef'd lines.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-12-21 08:54:37 -05:00
Tom Rini
071cf2767f global: Rework architecture global_data.h to include <linux/types.h>
In most cases, the architecture global data currently makes use of
assorted linux types, but does not include <linux/types.h> to provide
them. Add <linux/types.h> instead of relying on indirect inclusion.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-12-21 08:54:37 -05:00
Tom Rini
f90dee1a39 m68k: Rework asm/global_data.h slightly
In the architecture global data, replace the one case of u32 with
unsigned long. Now, we can drop config.h here but then do need to add it
in two m68k-centric spaces.

Acked-by: Angelo Dureghello <angelo@kernel-space.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-12-21 08:54:37 -05:00
Tom Rini
9d7f634811 sandbox: Add <linux/types.h> to asm/global_data.h and asm/io.h
We need <linux/types.h> in these files as we reference Linux types.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-12-21 08:54:37 -05:00
Tom Rini
78e326d631 arm: Remove <asm/types.h> from asm/global_data.h
We need and include <linux/types.h> and this in turn already includes
<asm/types.h>, so drop it here.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-12-21 08:54:37 -05:00
Tom Rini
ac2370a856 global: Remove duplicate common.h inclusions
These files include <common.h> twice. Start by removing the second
inclusion of the file.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-12-21 08:54:37 -05:00
Tom Rini
cb3ce95401 global: Drop common.h inclusion
In order to make it easier to move on to dropping common.h from code
directly, remove common.h inclusion from the rest of the header file
which had been including it.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-12-21 08:54:37 -05:00
Tom Rini
460b2c068c sandbox: Audit config.h and common.h usage
Remove and replace common.h and config.h in sandbox when it's not needed
and add some explicit includes where needed.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-12-21 08:54:37 -05:00
Tom Rini
7776960f4d arm: Partial cleanup and audit usage of <config.h>
We need to include <config.h> directly when a file needs to have
something such as CFG_SYS_SDRAM_SIZE referenced as this file is not
automatically globally included and is most commonly indirectly included
via common.h.  Remove most cases of arm including config.h directly, but
add it where needed. This includes a few board-specific fixes.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-12-21 08:54:37 -05:00
Tom Rini
28388f4ddb arc: Cleanup and audit usage of <config.h>
We need to include <config.h> directly when a file needs to have
something such as CFG_SYS_SDRAM_SIZE referenced as this file is not
automatically globally included and is most commonly indirectly included
via common.h.  Remove most cases of arc including config.h directly, but
add it where needed. Further clean up the tb100 board config.h file so
that we don't rely on config.h being included there for a value used in
a single place.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-12-21 08:54:37 -05:00
Tom Rini
10be393cf0 qe: Add <config.h> to linux/immap_qe.h
Given how we define QE_MURAM_SIZE today, this header needs to have
<config.h> added to it.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-12-21 08:54:37 -05:00
Tom Rini
b106961c2e global: Restrict use of '#include <linux/kconfig.h>'
In general terms, we -include include/linux/kconfig.h and so normal
U-Boot code does not need to also #include it. However, for code which
is shared with userspace we may need to add it so that either our full
config is available or so that macros such as CONFIG_IS_ENABLED() can be
evaluated. In this case make sure that we guard these includes with a
test for USE_HOSTCC so that it clear as to why we're doing this.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-12-21 08:54:05 -05:00
Tom Rini
36d3db6c2c Merge branch '2023-12-20-assorted-general-updates' into next
- Assorted fixes around the tree
2023-12-20 16:00:22 -05:00
Tom Rini
a0d0e132b3 Merge tag 'u-boot-imx-next-20231220' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx into next
- Put the USB hub out of reset on colibri-imx8x
- Fix VDDx brownout interrupt register of i.MX23/i.MX28
- Fix Phytec imx8m SoM detection
- Add TPM support for gw72xx boards
2023-12-20 14:14:46 -05:00
Marek Vasut
97135d9f42 cmd: part: Cover both part type entries with GUID ifdef
The 'part type' subcommand depends on GUID partition table support.
The help text exposes one of two 'part type' subcommand entries,
hide both in case GUID partition table support is not enabled to
avoid confusing users.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-12-20 14:13:20 -05:00
Ilias Apalodimas
738b34668f smbios: Fallback to the default DT if sysinfo nodes are missing
In order to fill in the SMBIOS tables U-Boot currently relies on a
"u-boot,sysinfo-smbios" compatible node.  This is fine for the boards
that already include such nodes.  However with some recent EFI changes,
the majority of boards can boot up distros, which usually rely on
things like dmidecode etc for their reporting.  For boards that
lack this special node the SMBIOS output looks like:

System Information
        Manufacturer: Unknown
        Product Name: Unknown
        Version: Unknown
        Serial Number: Unknown
        UUID: Not Settable
        Wake-up Type: Reserved
        SKU Number: Unknown
        Family: Unknown

This looks problematic since most of the info are "Unknown".  The DT spec
specifies standard properties containing relevant information like
'model' and 'compatible' for which the suggested format is
<manufacturer,model>. Unfortunately the 'model' string found in DTs is
usually lacking the manufacturer so we can't use it for both
'Manufacturer' and 'Product Name' SMBIOS entries reliably.

So let's add a last resort to our current smbios parsing.  If none of
the sysinfo properties are found, scan for those information in the
root node of the device tree. Use the 'model' to fill the 'Product
Name' and the first value of 'compatible' for the 'Manufacturer', since
that always contains one.

pre-patch:
Handle 0x0001, DMI type 1, 27 bytes
System Information
        Manufacturer: Unknown
        Product Name: Unknown
        Version: Unknown
        Serial Number: 100000000bb24ceb
        UUID: 30303031-3030-3030-3061-613234636435
        Wake-up Type: Reserved
        SKU Number: Unknown
        Family: Unknown
[...]

and post patch:
Handle 0x0001, DMI type 1, 27 bytes
System Information
        Manufacturer: raspberrypi
        Product Name: Raspberry Pi 4 Model B Rev 1.1
        Version: Unknown
        Serial Number: 100000000bb24ceb
        UUID: 30303031-3030-3030-3061-613234636435
        Wake-up Type: Reserved
        SKU Number: Unknown
        Family: Unknown
[...]

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Peter Robinson <pbrobinson@gmail.com>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
2023-12-20 14:13:20 -05:00
Ilias Apalodimas
a986ccea54 smbios: Simplify reporting of unknown values
If a value is not valid during the DT or SYSINFO parsing,  we explicitly
set that to "Unknown Product" and "Unknown" for the product and
manufacturer respectively.  It's cleaner if we move the checks insisde
smbios_add_prop_si() and provide an alternative string in case the
primary is NULL or empty

pre-patch dmidecode
<snip>
Handle 0x0001, DMI type 1, 27 bytes
System Information
        Manufacturer: Unknown
        Product Name: Unknown Product
        Version: Not Specified
        Serial Number: Not Specified
        UUID: Not Settable
        Wake-up Type: Reserved
        SKU Number: Not Specified
        Family: Not Specified

[...]

post-patch dmidecode:

Handle 0x0001, DMI type 1, 27 bytes
System Information
        Manufacturer: Unknown
        Product Name: Unknown
        Version: Unknown
        Serial Number: Unknown
        UUID: Not Settable
        Wake-up Type: Reserved
        SKU Number: Unknown
        Family: Unknown
[...]

While at it make smbios_add_prop_si() add a string directly if the prop
node is NULL and replace smbios_add_string() calls with
smbios_add_prop_si(ctx, NULL, ....)

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Peter Robinson <pbrobinson@gmail.com>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
2023-12-20 14:13:20 -05:00
Michael Trimarchi
4268ef9282 pxe_utils: Increase feedback to user when fdt file is not found
extlinux.conf can set fdtdir. fdtdir look for fdt file using
information found in the environment variable. The function does
not report any error in the case the file is not found

Scanning for bootflows in all bootdevs
Seq  Method       State   Uclass    Part  Name                      Filename
---  -----------  ------  --------  ----  ------------------------  ----------------
Scanning global bootmeth 'efi_mgr':
No EFI system partition
No EFI system partition
Failed to persist EFI variables
Scanning bootdev 'mmc@fa10000.bootdev':
  0  extlinux     ready   mmc          1  mmc@fa10000.bootdev.part_ /boot/extlinux/extlinux.conf
** Booting bootflow 'mmc@fa10000.bootdev.part_1' with extlinux
1:      am62x-sk-buildroot
Retrieving file: /boot/Image
append: console=ttyS2,115200n8 root=PARTUUID=c586a30c-0bf1-4323-aba8-779c814ee135 rw
		rootfstype=ext4 rootwait earlycon=ns16550a,mmio32,0x02800000
Retrieving file: /boot/k3-am623_ccm_m3.dtb
Skipping fdtdir /boot/ for failure retrieving dts

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-12-20 14:12:59 -05:00
Andrejs Cainikovs
8a72d193cf colibri-imx8x: configure usb hub to bypass mode
This change configures Toradex Colibri iMX8X SoM USB
hub to bypass mode, and brings out of the reset state.

Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
2023-12-20 15:04:46 -03:00
Andrejs Cainikovs
9c59447444 colibri-imx8x: remove -u-boot.dtsi include
This file is included automatically since quite some time now.

From documentation:

U-Boot automatically looks for and includes a file with updates
to the standard devicetree for your board, searching for them in
the same directory as the main file, in this order:

<orig_filename>-u-boot.dtsi
<CONFIG_SYS_SOC>-u-boot.dtsi
<CONFIG_SYS_CPU>-u-boot.dtsi
<CONFIG_SYS_VENDOR>-u-boot.dtsi
u-boot.dtsi

Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
2023-12-20 15:04:46 -03:00
Andrejs Cainikovs
6a77fb3b4c apalis-imx8: remove -u-boot.dtsi include
This file is included automatically since quite some time now.

From documentation:

U-Boot automatically looks for and includes a file with updates
to the standard devicetree for your board, searching for them in
the same directory as the main file, in this order:

<orig_filename>-u-boot.dtsi
<CONFIG_SYS_SOC>-u-boot.dtsi
<CONFIG_SYS_CPU>-u-boot.dtsi
<CONFIG_SYS_VENDOR>-u-boot.dtsi
u-boot.dtsi

Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
2023-12-20 15:04:46 -03:00
Yannic Moog
e2449ee968 board: phytec: phytec_som_detection: fix uninitialized bug
When som_type does not match any case, it is uninitialized and the
function still tries to print the SoM info. Rather, this is an error
condition and the function should abort prematurely. Highlight this by
printing an error message and returning early.

Signed-off-by: Yannic Moog <y.moog@phytec.de>
2023-12-20 15:04:46 -03:00
Yannic Moog
aa7858fe5e board: phytec: som_detection: move definitions to source file
Move all function definitions in {phytec|imx8m}_som_detection from the
header to the source file to prevent potential linker error regarding
multiple definitions. Also move the #if blocks with the definitions.

Signed-off-by: Yannic Moog <y.moog@phytec.de>
2023-12-20 15:04:46 -03:00
Yannic Moog
71714cda3d board: phytec: phytec_som_detection: fix eeprom_data zero check
In phytec_eeprom_data_init, after reading eeprom data into buffer, it is
checked whether all bytes are 0x0 by iterating over chunks of the
buffer. The offset, or index of the chunk, was never changed, leading to
repeated comparison of only the first chunk. Use array notation and
access chunk via array index to compare all chunks of the buffer.

Signed-off-by: Yannic Moog <y.moog@phytec.de>
2023-12-20 15:04:46 -03:00
Yannic Moog
da37f78525 board: phytec: imx8m_som_detection: fix uninitialized pointer bug
Pointer in phytec_imx8m_detect was accessed without checking it first.
Fix this by moving the pointer check in front of any accesses.

Signed-off-by: Yannic Moog <y.moog@phytec.de>
2023-12-20 15:04:46 -03:00
Yannic Moog
e2be177c85 board: phytec: imx8m_som_detection: change phytec_imx8m_detect return type
phytec_imx8m_detect returns -1 on error, but the return type is u8
leading to 255 return values. Fix this by changing the return type to
int; there is no reason to keep it as u8 .

Signed-off-by: Yannic Moog <y.moog@phytec.de>
2023-12-20 15:04:46 -03:00
Tim Harvey
cd3387f132 configs: imx8m{m, n, p}_venice_defconfig: add arch_misc_init
Enable call to arch_misc_init in order to probe the CAAM driver.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2023-12-20 15:00:47 -03:00
Tim Harvey
c0689191f1 arm: dts: imx8mp-venice-gw72xx: add TPM device
Add the TPM device found on the GW72xx revision F PCB.

This hangs off of SPI2, uses gpio1_10 as a CS and gpio1_11 as RST#.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2023-12-20 15:00:47 -03:00
Tim Harvey
b1c40d0692 arm: dts: imx8mm-venice-gw72xx: add TPM device
Add the TPM device found on the GW72xx revision F PCB.

This hangs off of SPI2, uses gpio1_10 as a CS and gpio1_11 as RST#.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2023-12-20 15:00:47 -03:00
Cody Green
2264bfba19 mxs: Fix VDDx brownout interrupt disable/enable
Incorrect registers HW_POWER_VDDIOCTRL, HW_POWER_VDDACTRL
and HW_POWER_VDDDCTRL are used in the current code to disable/enable
brownout interrupts in 'mxs_power_set_vddx()'.
Change register to HW_POWER_CTRL which contains brownout interrupt
enable bits ENIRQ_VDDIO_BO, ENIRQ_VDDA_BO and ENIRQ_VDDD_BO.

Signed-off-by: Cody Green <cody@londelec.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Lukasz Majewski <lukma@denx.de>
2023-12-20 15:00:47 -03:00
Marek Vasut
0de448d032 command: Move command completion temporary buffer to stack
The command completion temporary buffer seems to be only
used by the argv tokenizer, move it to stack. This saves
2 kiB from the binary size (depends on configuration) per:
$ aarch64-linux-gnu-readelf -s u-boot | sort -n -k 3

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-12-20 10:46:54 -05:00
Marek Vasut
400cb2a850 command: Allocate history buffer using calloc()
The history buffer is currently a static array which can be some
10-40 kiB depending on configuration, and so adds considerably to
the U-Boot binary size. Allocate it dynamically instead to reduce
the U-Boot binary size.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-12-20 10:46:54 -05:00
Simon Glass
921f63e572 bootflow: Allow setting a cmdline arg with no value
This is supposed to be supported by the 'bootflow cmd' command, at
least according to the help. There is a 'bootflow cmd clear' but it is
often more intuitive to use 'bootcmd cmd set' with an empty value.

Update the command to pass BOOTFLOWCL_EMPTY in this case.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-12-20 10:46:54 -05:00
Piotr Kubik
7481632b19 bootm: Fix flags used for bootargs string substitution
Commit 51bb33846a ("bootm: Support string substitution in
bootargs") introduced a feature of bootargs string substitution
and changed a flag used in bootm_process_cmdline_env() call
to be either true or false. With this flag value,
condition in bootm_process_cmdline()
`if (flags & BOOTM_CL_SUBST)` is never true
and process_subst() is never called.

Add a simple test to verify if substitution works OK.

Signed-off-by: Piotr Kubik <piotr.kubik@iopsys.eu>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-12-20 10:46:54 -05:00
Robert Catherall
785834d62e arm: afs: Set the filesize env. var. on load
The `afs load` command copies data to RAM. Set the filesize
environment variable to record how much data was 'loaded'

Signed-off-by: Robert Catherall <robert.catherall@arm.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Andre Przywara <andre.przywara@arm.com>
2023-12-20 10:46:54 -05:00
Ayoub Zaki
ece85cc020 rsa: use pkcs11 uri as defined in rfc7512
pkcs11 : change engine uri to use full pk11-URI as defined in:

https://www.rfc-editor.org/rfc/rfc7512.html
Signed-off-by: Ayoub Zaki <ayoub.zaki@embetrix.com>
2023-12-20 09:48:17 -05:00
Nikita Shubin
05e8e2403c imxtract: specify max gunzip size
Specify max gunzip size from config to override SYS_XIMG_LEN
default value wich is 0x800000. In case we have a large portion of FIT
image, for example gzipped kernel with decompressed size large than
0x800000 we should enlarge imxract area, otherwise extracting it will
fail.

It used to be a hardcoded define in cmd/ximg.c and we are moving it to
config.

Signed-off-by: Nikita Shubin <n.shubin@yadro.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-12-20 09:48:16 -05:00
Tom Rini
f7655af980 Merge tag 'u-boot-amlogic-next-20231220' of https://source.denx.de/u-boot/custodians/u-boot-amlogic into next
- Add support for new GXL MDIO mux, with driver and Linux DT sync from v6.4
2023-12-20 08:34:12 -05:00
Tom Rini
1f115bdeb8 Merge branch 'staging' of https://source.denx.de/u-boot/custodians/u-boot-tegra into next
This PR contains 4 patchsets:

1. PMIC GPIO cells bringup. Created drivers for MAX7663 and Palmas
PMICs and gpio-uclass patch isolated behind configs for these 2
drivers. No unintentional size increase on any board. (proposed
2023-11-06 without any reaction)

2. Simple PLL clocks support in common tegra clock code which allows
use of simple PLL the same way main PLLs are used (before only
clock_start_pll was available). PLLD2 is an example of simple PLL, it
is used as a video subsystem parent clock and was used to test this
code. So far everything worked as expected. (proposed 2023-11-16
without any reaction)

3. A small patch for tegra emmc to allow pass max frequency from
device tree since some devices may not support full speed.

4. Pinmux DM conversion. Patchset consists of commit with DM wrapper
for existing pinmux code for t20/t30/t114, pinmux and funcmux files
relocation into a dedicated folder inside pinctrl, conversion of some
tegra boards to device tree pinmux setup.
2023-12-20 08:12:56 -05:00
Svyatoslav Ryhel
4989628c1d board: compal: paz00: clean up the board
Since implementation of pinctrl driver for T20 Paz00 can switch
to device tree pinmux setup along with remove of board pinmux
and some minor device tree and defconfig tweaks.

Tested-by: Agneli <poczt@protonmail.ch> # Toshiba AC100 T20
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2023-12-19 21:24:30 +02:00
Svyatoslav Ryhel
14281b082a board: htc: endeavoru: switch to DM pinmux
Drop the pinmux setup in the board in favor of setting it up in
the device tree. Device tree nodes match nodes used for the Linux
device tree and are set according to the downstream kernel. 

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2023-12-19 21:24:30 +02:00
Svyatoslav Ryhel
8a861dd769 board: asus: transformer: switch to DM pinmux
Drop the pinmux setup in the board in favor of setting it up in
the device tree. Device tree nodes match nodes used in the Linux
device tree. 

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2023-12-19 21:24:30 +02:00
Svyatoslav Ryhel
fd211f85cc board: lg: x3-t30: switch to DM pinmux
Drop the pinmux setup in the board in favor of setting it up in
the device tree. Device tree nodes match nodes used for the Linux
device tree and are set according to the service manual.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2023-12-19 21:24:30 +02:00
Svyatoslav Ryhel
98a1c3b51c board: asus: grouper: switch to DM pinmux
Drop the pinmux setup in the board in favor of setting it up in
the device tree. Device tree nodes match nodes used in the Linux
device tree.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2023-12-19 21:24:30 +02:00
Svyatoslav Ryhel
b98bed0e9c drivers: pinctrl: tegra: incorporate existing code
Move all existing pinmux and funcmux code into a dedicated folder in
pinctrl to simplify further maintenance.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2023-12-19 21:24:30 +02:00
Svyatoslav Ryhel
91069320a5 drivers: pinctrl: create Tegra DM pinctrl driver
The existing pinctrl driver available for Tegra SOC is well
designed, but it lacks DM support. Let's add a DM compatible
overlay, which allows use of the device tree, along with preserving
backward compatibility with all existing setups and the ability
to use it in SPL board configuration stage.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2023-12-19 21:24:30 +02:00
Svyatoslav Ryhel
886b1da83b ARM: mach-tegra: rearrange SPL configs
SPL configs are used only by the ARMv7-based Tegra SOC's, so move
SPL_SYSRESET under TEGRA_ARMV7_COMMON selection and enable SPL_DM
since SPL_SYSRESET depends on it.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2023-12-19 21:24:30 +02:00
Peter Geis
34aeb386af mmc: tegra: use max-frequency from device tree if provided
The driver currently hard-codes the max freqency for the sdhci
controllers. If the controller is unable to operate at the max
frequency, the mmc card will not be available on the first scan.
Subsequent scans will eventually find a working combination.

Fix this by allowing the driver to check for the max-frequency
property and default to the original value if it doesn't exist.

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2023-12-19 21:24:12 +02:00
Svyatoslav Ryhel
944ac34075 ARM: tegra114: clock: implement PLLD2 support
PLLD2 is a simple clock (controlled by 2 registers) and appears starting
from T30. Primary use of PLLD2 is as main HDMI clock parent.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2023-12-19 21:24:11 +02:00
Svyatoslav Ryhel
e63ab85dba ARM: tegra30: clock: implement PLLD2 support
PLLD2 is a simple clock (controlled by 2 registers) and appears starting
from T30. Primary use of PLLD2 is as main HDMI clock parent.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2023-12-19 21:24:11 +02:00
Svyatoslav Ryhel
1ba80d1b2c ARM: tegra: clock: support get and set rate for simple PLL
Simple PLL clocks like PLLD2 were omitted since they do not share common
4 register structure with main clocks. Such clocks are containd in simple
PLL group. Only clock_start_pll function supported them. This patch expands
this support on clock_set_rate and clock_get_rate which should make
simple PLL clocks equal to main PLL clocks.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2023-12-19 21:24:11 +02:00
Svyatoslav Ryhel
c03cd98d1a drivers: gpio-uclass: support PMIC GPIO children
UCLASS_PMIC may have GPIO children without exposed fdt node,
in this case if requesting fails, check if uclass is PMIC.

Restrict build for supported devices only to save those precious
bytes on devices with no spare memory.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2023-12-19 21:23:47 +02:00
Svyatoslav Ryhel
52b6bbf162 drivers: gpio: implement PALMAS GPIO cell
Add gpio driver for TI Palmas series PMIC. This has 8 gpio which can
work as input/output.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2023-12-19 20:53:53 +02:00
Svyatoslav Ryhel
6b24c372c1 drivers: gpio: implement MAX77663 GPIO cell
MAXIM Semiconductor's PMIC, MAX77663 has 8 GPIO pins and 3 GPIO-like
pins. It also supports interrupts from these pins.

Add GPIO driver for these pins to control via GPIO APIs.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2023-12-19 20:53:53 +02:00
Tom Rini
936d0f9dd7 Merge patch series "Fix J7200 kernel boot when using upstream u-boot"
Reid Tonking <reidt@ti.com> says:

Since the 09.01.00.002 release of ti-linux-firmware [0] upstream uboot
has led to the kernel hanging during boot [1] for the TI J7200 S0C. The
issue was found to be a few patches that had be added to ti-u-boot, but not
yet upstreamed. This series adds the missing two patches to allow upstream
u-boot to boot the kernel properly [2].

[0] https://git.ti.com/cgit/processor-firmware/ti-linux-firmware/commit/?h=ti-linux-firmware-next&id=952fd03e36a50ec070e73560dc1060102d637ce0

Boot logs:
[1] https://gist.github.com/reidt1/5f4e85a0db258bcf20d7168bd0caebd0
[2] https://gist.github.com/reidt1/e950dc97f15ad0a09623d64f81edac39

Links to patches on ti-u-boot:
https://git.ti.com/cgit/ti-u-boot/ti-u-boot/commit/?h=ti-u-boot-2023.04-next&id=d878fbef4d4460e87608d8d2dfe5311499de49c5
https://git.ti.com/cgit/ti-u-boot/ti-u-boot/commit/?h=ti-u-boot-2023.04-next&id=543e735fe495be233a8a75b19b3d7f8ed44251e0
2023-12-19 11:42:03 -05:00
Tom Rini
9cfef5fcfb Merge patch series "Add support for MediaTek MT8365 EVK Board"
Julien Masson <jmasson@baylibre.com> says:

This patch series add the support for the MediaTek MT8365 EVK Board [1].
Most of the code have been copied/adapted from Linux tag v6.7-rc2.

For now we only enable/test these features:
Boot, UART, Watchdog and MMC.

[trini: This includes two clocks not listed in the Linux binding, which
 needs resyncing later]
2023-12-19 11:42:03 -05:00
Tom Rini
298419ba4d Merge branch '2023-12-19-assorted-platform-updates' into next
- Assorted platform updates for TI K3, vexpress64, mediatek and related
  cleanups to the DW GPIO driver and OPTEE
2023-12-19 11:42:03 -05:00
Reid Tonking
3d6cb03905 arm: dts: k3-j7200-r5-common-proc-board: Set parent clock for clock ID 323
Previously, dynamic frequency scaling supported rates only through fixed
divison.

This virtual clock mux configuration enables more varied rates on A72
clock ID 202 by setting up the required register.

Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
Signed-off-by: Reid Tonking <reidt@ti.com>
2023-12-19 10:15:54 -05:00
Bryan Brattlof
9fc5e19c2e arm: mach-k3: j72xx: add new 'virtual' mux
In order for the Cortex-A72s to operate at different frequencies other
than the default 2GHz, add in a new 'virtual' mux (a mux that does not
physically exist in the clock tree) that can be selected.

CC: Vishal Mahaveer <vishalm@ti.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
Signed-off-by: Reid Tonking <reidt@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
2023-12-19 10:15:53 -05:00
Julien Masson
1c2c0c6359 board: mediatek: add MT8365 EVK board support
This adds support for the MT8365 EVK board with the following
features enabled/tested: Boot, UART, Watchdog and MMC.

Signed-off-by: Julien Masson <jmasson@baylibre.com>
2023-12-19 10:09:06 -05:00
Julien Masson
5679eccb83 dt-bindings: clock: add Mediatek MT8365 pinctrl bindings
This adds the pinctrl bindings for Mediatek MT8365 SoC based on the
dt-bindings in Linux tag v6.7-rc2.
(commit 8b4c397d88d97d4fd9c3f3527aa66688b1a3387a)

Signed-off-by: Julien Masson <jmasson@baylibre.com>
2023-12-19 10:09:06 -05:00
Julien Masson
ee33f6539d arm: mediatek: add support for MediaTek MT8365 SoC
This patch adds basic support for MediaTek MT8365 SoC.
The dtsi has been copied from Linux source code tag v6.7-rc2.
(commit 9b5d64654ea8f51fe1e8e29ca1777b620be8fb7c)

Signed-off-by: Julien Masson <jmasson@baylibre.com>
2023-12-19 10:09:06 -05:00
Julien Masson
80cdb6df22 dt-bindings: power: add power-domain header for MediaTek MT8365 SoC
Add power-domain header for MediaTek MT8365 SoC copied from Linux
source code tag v6.7-rc2.
(commit a1571f1f333c2fced076f0d54ed771d1838d827f)

Signed-off-by: Julien Masson <jmasson@baylibre.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
2023-12-19 10:09:06 -05:00
Julien Masson
ac80c6a647 clk: mediatek: add clock driver support for MediaTek MT8365 SoC
This patch adds clock driver support for MediaTek MT8365 SoC.
The changes are based on the Linux source code tag v6.7-rc2.

clk-mt8365.c has been written based on these kernel files:
- clk-mt8365.c (a96cbb146a9736f501fe66ebda6a9018735e5e8a)
- clk-mt8365-apmixedsys.c (65c9ad77cbc0eed78db94d80041aba675cfbdfa9)
And adapted following the clk attributes supported by U-Boot.

Signed-off-by: Julien Masson <jmasson@baylibre.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
2023-12-19 10:09:06 -05:00
Julien Masson
af3fa853fa dt-bindings: clock: add Mediatek MT8365 SoC clock bindings
This adds the clock bindings for Mediatek MT8365 SoC based on the
dt-bindings in Linux tag v6.7-rc2.
(commit c61978175ac1337f028ac1f956666f16db84f4e5)

Signed-off-by: Julien Masson <jmasson@baylibre.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
2023-12-19 10:09:06 -05:00
Michael Trimarchi
6645934646 arm: mach-k3: am625: Relax emmc boot condition
spl_mmc_emmc_boot_partition return a number different from 0
if the partition is a boot one. We can have the uboot img
for instance in a raw offset in emmc partition 0 so we would
like to continue to load the next stage. If the user want
to use EMMC as boot device allow him to use any part of the
emmc and not only boot partition

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2023-12-19 10:07:48 -05:00
Julien Masson
fd8de9730c mmc: mediatek: set b_max according CONFIG_SYS_MMC_MAX_BLK_COUNT
The block count limit on MMC based devices should be set according to
CONFIG_SYS_MMC_MAX_BLK_COUNT instead of hardcoding value.

Signed-off-by: Julien Masson <jmasson@baylibre.com>
2023-12-19 10:07:48 -05:00
Maksim Kiselev
00b0493398 gpio: dw: Drop unused headers
Drop headers which are not used or needed in this file.

Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com>
2023-12-19 10:07:48 -05:00
Etienne Carriere
51774b3b03 tee: optee: don't enumerate services if there ain't any
Change optee driver service enumeration to not enumerate (and
allocate a zero sized shared memory buffer) when OP-TEE
reports that there is no service to enumerate.

This change fixes an existing issue that occurs when the such zero
sized shared memory buffer allocated from malloc() has a physical
address of offset 0 of a physical 4kB page. In such case, OP-TEE
secure world refuses to register the zero-sized shared memory
area and makes U-Boot optee service enumeration to fail.

Fixes: 94ccfb78a4 ("drivers: tee: optee: discover OP-TEE services")
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
2023-12-19 10:07:48 -05:00
Etienne Carriere
ab9500e9c3 tee: optee: don't fail on services enumeration failure
Change optee probe function to only warn when service enumeration
sequence fails instead of reporting an optee driver probe failure.
Indeed U-Boot can still use OP-TEE even if some OP-TEE services are
not discovered.

Fixes: 94ccfb78a4 ("drivers: tee: optee: discover OP-TEE services")
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
2023-12-19 10:07:48 -05:00
Udit Kumar
34fc186123 remoteproc: k3-dsp: Avoid reloading of firmware
DSP core is going into abnormal state when load callback is called
after starting of DSP core.
Reload of firmware needs core to be stopped first, followed by
load.
So avoid loading of firmware, when core is started.

Signed-off-by: Udit Kumar <u-kumar1@ti.com>
2023-12-19 10:07:48 -05:00
Robert Catherall
c86c1d0383 arm: vexpress64: juno: Allow boot from VirtIO
The AEM and Juno FVPs (Fixed Virtual Platforms) support a VirtIO
disc interface. Adding VIRTIO to the list of boot devices allows
these FastModel platforms to boot from 'disc' in the same way
the hardware counterpart can boot from SATA or USB.

This is a NOP if CONFIG_CMD_VIRTIO is not enabled, so no impact
on Juno hardware (which is built with vexpress_aemv8a_juno_defconfig)

Signed-off-by: Robert Catherall <robert.catherall@arm.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2023-12-19 10:07:48 -05:00
Neil Armstrong
4d4fbf0415 ARM: dts: sync Amlogic GX DT to Linux v6.4
Sync Amlogic GXBB, GXL & GXM DTs from Linux v6.4, and also
switch to GXL MDIO MUX driver to adapt to DT change,

Most of the changes are only cosmetic or doesn't concern U-Boot,
the most important change for U-Boot is the GXL mdio mux compatible
switch to amlogic,gxl-mdio-mux.

Link: https://lore.kernel.org/r/20231213-u-boot-gxl-mdio-mux-v2-2-c56bb02a75ea@linaro.org
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2023-12-19 11:24:38 +01:00
Neil Armstrong
b4534ddeff net: Add Amlogic GXL MDIO Mux driver
Port the mdio-mux-meson-gxl.c Linux driver introduced in [1],
and adapt it to U-Boot.

This driver is needed to boot U-Boot with Linux DT since v6.4,
since it switched the MDIO mux from the mmio to a proper GXL driver.

[1] 9a24e1ff4326 ("net: mdio: add amlogic gxl mdio mux support")

Link: https://lore.kernel.org/r/20231213-u-boot-gxl-mdio-mux-v2-1-c56bb02a75ea@linaro.org
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2023-12-19 11:24:38 +01:00
Tom Rini
a6f86132e3 Merge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-riscv into next
- VisionFive2: Enable CONFIG_SYSRESET
- StarFive: Modify starfive timer driver
- AMD/Xilinx: Add MicroBlaze V support
- Unmatched: Migrate to text environment
2023-12-18 09:56:58 -05:00
Tom Rini
cd908ba186 Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-spi into next
- spi_nor_read_sfdp_dma_unsafe (Vaishnav)
- w25q01/02 (Jim)
2023-12-18 09:56:42 -05:00
Tom Rini
1373ffde52 Merge tag 'v2024.01-rc5' into next
Prepare v2024.01-rc5
2023-12-18 09:55:32 -05:00
Yong-Xuan Wang
44a792c994 riscv: sifive: unmatched: migrate to text environment
Migrate to the new environment format and drop most of the config.h.

Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-12-18 11:09:01 +08:00
Kuan Lim Lee
429fa3b32d timer: starfive: Add Starfive timer support
Add timer driver in Starfive SoC. It is an timer that outside
of CPU core and inside Starfive SoC.

Signed-off-by: Kuan Lim Lee <kuanlim.lee@starfivetech.com>
Signed-off-by: Wei Liang Lim <weiliang.lim@starfivetech.com>

Changes for v2:
- correct driver name, comment, variable
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-12-18 11:08:54 +08:00
Michal Simek
7576ab2fac riscv: Add support for AMD/Xilinx MicroBlaze V
MicroBlaze V is new AMD/Xilinx soft-core 32bit RISC-V processor IP.
It is hardware compatible with classic MicroBlaze processor.

The patch contains initial wiring and configuration for initial HW design
with memory, cpu, interrupt controller, timers and uartlite console
(interrupt controller is listed but U-Boot is not using it).

Provided DT is just describing one configuration and should be taken only
as example.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
2023-12-18 11:08:49 +08:00
Jaehoon Chung
0d14f04d5d configs: visionfive2: Enable CONFIG_SYSRESET config
Enable CONFIG_SYSRESET config to do reset.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-12-18 11:08:42 +08:00
Jaehoon Chung
202a5c6fa4 riscv: dts: jh7110: Add a gpio-restart node
Add gpio-restart node to do reset.

Before applied this patch, System Reset Extension doesn't appear with
sbi command.

OpenSBI 1.3
Machine:
  Vendor ID 489
  Architecture ID 8000000000000007
  Implementation ID 4210427
Extensions:
  sbi_set_timer
  sbi_console_putchar
...[snip]...
  IPI Extension
  RFENCE Extension
  Hart State Management Extension
  Performance Monitoring Unit Extension

After applied this patch, System Reset Extension is supported from SBI.

OpenSBI 1.3
Machine:
  Vendor ID 489
  Architecture ID 8000000000000007
  Implementation ID 4210427
Extensions:
  sbi_set_timer
  sbi_console_putchar
...[snip]...
  IPI Extension
  RFENCE Extension
  Hart State Management Extension
  System Reset Extension
  Performance Monitoring Unit Extension

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-12-18 11:08:28 +08:00
Tom Rini
fdefb4e194 Merge tag 'efi-next-20231217' of https://source.denx.de/u-boot/custodians/u-boot-efi into next
Pull request for efi-next-20231217

Documentation:

* replace MD5 and SHA1 by SHA256 in examples

UEFI:

* Refactor boot manager and bootefi command to let the EFI boot method work
  without shell.
2023-12-17 09:11:06 -05:00
Sean Anderson
291ab91935 doc: Replace examples of MD5 and SHA1 with SHA256
Both SHA1 and (especially) MD5 are no longer as safe as they once were for
cryptographic use. Replaces examples which use them with examples using
SHA256 instead. This will provide more-secure defaults for users who use
documentation examples as a base for their own use. This is not too
necessary for non-verified-boot scenarios (since someone could just replace
the checksum), but I wanted to be complete.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-12-17 13:06:48 +01:00
AKASHI Takahiro
7017fc54a5 bootmeth: use efi_loader interfaces instead of bootefi command
Now that efi_loader subsystem provides interfaces that are equivalent
with bootefi command, we can replace command invocations with APIs.

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
2023-12-17 13:04:54 +01:00
AKASHI Takahiro
01adf0a408 cmd: efidebug: ease efi configuration dependency
Now it is clear that the command actually depends on interfaces,
not "bootefi bootmgr" command.

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
2023-12-17 13:04:54 +01:00
AKASHI Takahiro
0bef4b0123 cmd: bootefi: move library interfaces under lib/efi_loader
In the prior commits, interfaces for executing EFI binary and boot manager
were carved out. Move them under efi_loader directory so that they can
be called from other places without depending on bootefi command.

Only efi_selftest-related code will be left in bootefi.c.

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
2023-12-17 13:04:54 +01:00
AKASHI Takahiro
d07e7be7ea cmd: bootefi: localize global device paths for efi_selftest
Device paths allocated in bootefi_test_prepare() will be immediately
consumed by do_efi_selftest() and there is no need to keep them for later
use. Introduce test-specific varialbles to make it easier to move other
bootmgr functions into library directory in the next commit.

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
2023-12-17 13:04:54 +01:00
AKASHI Takahiro
5c129fe5f5 cmd: bootefi: carve out binary execution interface
Carve binary execution code out of do_bootefi_image() in order to move
binary-execution specific code into library directory in the later
commit.

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
2023-12-17 13:04:54 +01:00
AKASHI Takahiro
c3530aec14 cmd: bootefi: carve out EFI boot manager interface
Carve EFI boot manager related code out of do_bootefi_image() in order
to move boot manager specific code into library directory in the later
commit.

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
2023-12-17 13:04:54 +01:00
AKASHI Takahiro
296faf4f7e cmd: bootefi: re-organize do_bootefi()
Replicate some code and re-organize do_bootefi() into three cases, which
will be carved out as independent functions in the next two commits.

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
2023-12-17 13:04:54 +01:00
AKASHI Takahiro
05e2cade01 cmd: bootefi: unfold do_bootefi_image()
Unfold do_bootefi_image() into do_bootefi() in order to make it easier
to re-organize do_bootefi() in the next commit.

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
2023-12-17 13:04:53 +01:00
Tom Rini
cd94821033 Revert "board: ti: am62x/am62ax: Update virtual interrupt allocations in board config"
After talking with the author off-list I was reminded that this part of
the series was not supposed to be merged, only parts 1-3 upon further
review.

This reverts commit 58a277c207.

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-12-15 20:23:59 -05:00
Tom Rini
8bb3cd7fe7 Merge tag 'clk-2024.01-next' of https://source.denx.de/u-boot/custodians/u-boot-clk into next
clock patches for u-boot/next

The main thing in here is Igor's conversion of soc_clk_dump to a clk_ops
member. There's also a write-protect feature for nuvoton clocks.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2023-12-15 17:49:13 -05:00
Tom Rini
57e584d941 Merge branch '2023-12-15-assorted-TI-platform-updates' into next
- Assorted updates and fixes for some TI K3 platforms and SoCs
2023-12-15 16:20:49 -05:00
Andrew Davis
a213289953 board: ti: k3: Remove need for CFG_SYS_SDRAM_BASE
The base address of extended DDR does not change across the K3 family.
Setting this per SoC is not needed. Remove this definition to help
remove the last bits from K3 include/configs/*.h files.

Signed-off-by: Andrew Davis <afd@ti.com>
2023-12-15 15:39:42 -05:00
Vishal Mahaveer
58a277c207 board: ti: am62x/am62ax: Update virtual interrupt allocations in board config
Updates as a result of TIFS core now reserving a virtual interrupt
for enabling interrupts between DM to TIFS core. Because of this
change other virtual interrupt counts decrease by one.

Signed-off-by: Vishal Mahaveer <vishalm@ti.com>
2023-12-15 15:27:48 -05:00
Vishal Mahaveer
ef756f1bcd board: ti: am62x/am62ax: Update MCU GPIO interrupt allocation in board config
Share the MCU GPIO interrupts between A53 core and DM R5 core. Allocating
2 instances each to A53 and DM R5.

Signed-off-by: Vishal Mahaveer <vishalm@ti.com>
2023-12-15 15:27:48 -05:00
Vishal Mahaveer
3d1322c41c board: ti: am62ax: Add C7x resource allocation entries to board config
Update am62ax rm-cfg with allocation entries for C7x core. Following
updates are added for C7x:
- Share split BCDMA tx and rx channels between DM R5 and C7x
- Share rings for split BCDMA tx and rx channels between DM R5 and C7x
- Add Global events and Virtual interrupts for C7x

Signed-off-by: Vishal Mahaveer <vishalm@ti.com>
2023-12-15 15:27:48 -05:00
Vishal Mahaveer
d55829957d board: ti: am62x/am62ax: Formatting updates to board config files
Minor formatting updates to the rm board configuration file for
am62x and am62ax boards.

Signed-off-by: Vishal Mahaveer <vishalm@ti.com>
2023-12-15 15:27:48 -05:00
Andrew Davis
7c9c6e1925 arm: mach-k3: Merge initial memory maps
The Device vs Normal memory map is the same for all K3 SoCs. Merge
the SoC specific maps into one.

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Tested-by: Nishanth Menon <nm@ti.com>
2023-12-15 15:27:48 -05:00
Andrew Davis
c90462e691 arm: mach-k3: Remove non-cached memory map areas
All normal memory areas should be mapped as such.

We added these un-cached holes in our memory map to hack around the
remoteproc driver missing the proper cache maintenance operations.

The problem is having these non-cached memory map areas causes stability
issues later in system operation due to the nature of the K3 coherency
architecture. Plus these are board specific carveouts and instead
should have been added at the board level, not here in the SoC common
code area.

Remove these non-cached memory map areas.

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Tested-by: Nishanth Menon <nm@ti.com>
2023-12-15 15:27:48 -05:00
Andrew Davis
4b4ebdb4a4 arm: mach-k3: Do not map ATF and OPTEE regions in MMU
ATF and OPTEE regions may be firewalled from non-secure entities. To
prevent access to this area we leave a hole there in the MMU map. This
is the same idea as [0] but we complete that patch by adding the same
for AM65, J721e, J7200, and J721s2 here.

[0] commit 0688ff3ae2 ("arm: mach-k3: arm64-mmu: do not map ATF and OPTEE regions in A53 MMU")

Signed-off-by: Andrew Davis <afd@ti.com>
2023-12-15 15:27:48 -05:00
Andrew Davis
d7b889403c arm: mach-k3: Let the compiler size the mem_map lists
NR_MMU_REGIONS is a copy/paste from another platform that extends
this list later. We do not do that, so let the list be the size
of the initializer list.

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Tested-by: Nishanth Menon <nm@ti.com>
2023-12-15 15:27:47 -05:00
Andrew Davis
4621960754 arm: mach-k3: Move K3 common schema.yaml out of board directory
This file is common for all K3, move it out of board/ directory and
into mach-k3. As we need to change the path in k3-binman.dtsi let's
take this opportunity to switch to absolute paths which makes adding
non-TI boards (like Toradex Verdin) not need to override these paths.

Signed-off-by: Andrew Davis <afd@ti.com>
2023-12-15 15:27:47 -05:00
Tom Rini
c936ef7870 Merge tag 'u-boot-stm32-20231215' of https://source.denx.de/u-boot/custodians/u-boot-stm into next
_ run savedefconfig on all STM32 defconfig

STM32 MCU:
_ Sync stm32f469-disco DT with Linux 6.5
_ rework ltdc node for stm32f769-disco
_ clk: stm32f: Fix settings for LCD_CLK
_ Support display on stm32f469-disco board

STM32 MPU:
_ stm32mp_dfu : Fix board_get_alt_info_mtd()
_ stm32mp_dfu : Simplify MTD device parsing
2023-12-15 13:33:11 -05:00
Jim Liu
652d8d4561 clk: nuvoton: add read only feature for clk driver
Add a flag to set ahb/apb/fiu/spi clock divider as read-only
The spi clock setting is related to booting flash, it is setup by early
bootloader.
It just protects the clock source and can't modify it in uboot.

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Link: https://lore.kernel.org/r/20231114090004.3746024-1-JJLIU0@nuvoton.com
2023-12-15 13:05:55 -05:00
Igor Prusov
5666558a6c cmd: clk: Make soc_clk_dump static
After introducing dump to clk_ops there is no need to override or expose
this symbol anymore.

Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Tested-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Signed-off-by: Igor Prusov <ivprusov@sberdevices.ru>
Link: https://lore.kernel.org/r/20231109105516.24892-9-ivprusov@sberdevices.ru
2023-12-15 13:05:55 -05:00
Igor Prusov
bc3e313ff6 clk: treewide: switch to clock dump from clk_ops
Switch to using new dump operation in clock provider drivers instead of
overriding soc_clk_dump.

Tested-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Signed-off-by: Igor Prusov <ivprusov@sberdevices.ru>
Link: https://lore.kernel.org/r/20231109105516.24892-8-ivprusov@sberdevices.ru
2023-12-15 13:05:54 -05:00
Igor Prusov
258c100238 cmd: clk: Use dump function from clk_ops
Add another loop to dump additional info from clock providers that
implement dump operation.

Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Tested-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Signed-off-by: Igor Prusov <ivprusov@sberdevices.ru>
Link: https://lore.kernel.org/r/20231109105516.24892-7-ivprusov@sberdevices.ru
2023-12-15 13:05:54 -05:00
Igor Prusov
505ef5f627 clk: Add dump operation to clk_ops
This adds dump function to struct clk_ops which should replace
soc_clk_dump. It allows clock drivers to provide custom dump
implementation without overriding generic CCF dump function.

Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Tested-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Signed-off-by: Igor Prusov <ivprusov@sberdevices.ru>
[ Fixed parameter name in documentation ]
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Link: https://lore.kernel.org/r/20231109105516.24892-6-ivprusov@sberdevices.ru
2023-12-15 13:05:54 -05:00
Igor Prusov
4f48202ba8 clk: amlogic: Move driver and ops structs
Move driver and ops structs to avoid forward declaration after switching
to dump in clk_ops.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Igor Prusov <ivprusov@sberdevices.ru>
Link: https://lore.kernel.org/r/20231109105516.24892-5-ivprusov@sberdevices.ru
2023-12-15 12:33:09 -05:00
Igor Prusov
77beaad3d1 clk: k210: Move soc_clk_dump function
Move clock dump function to avoid forward declaration after switching to
dump in clk_ops.

Reviewed-by: Sean Anderson <seanga2@gmail.com>
Signed-off-by: Igor Prusov <ivprusov@sberdevices.ru>
Link: https://lore.kernel.org/r/20231109105516.24892-4-ivprusov@sberdevices.ru
2023-12-15 12:33:09 -05:00
Igor Prusov
3f192541df clk: ast2600: Move soc_clk_dump function
Move clock dump function to avoid forward declaration after switching to
dump in clk_ops.

Signed-off-by: Igor Prusov <ivprusov@sberdevices.ru>
Link: https://lore.kernel.org/r/20231109105516.24892-3-ivprusov@sberdevices.ru
2023-12-15 12:33:09 -05:00
Igor Prusov
bdac755114 clk: zynq: Move soc_clk_dump to Zynq clock driver
Move clock dump function in preparation for switching to dump function
in clk_ops.

Acked-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Igor Prusov <ivprusov@sberdevices.ru>
Link: https://lore.kernel.org/r/20231109105516.24892-2-ivprusov@sberdevices.ru
2023-12-15 12:33:09 -05:00
Tom Rini
d7a2c7ff75 Merge patch series "bootm: Handle compressed arm64 images with bootm"
To quote the author:

This little series corrects a problem I noticed with arm64 images,
where the kernel is not recognised if compression is used:

   U-Boot> tftp image.fit
   Using ethernet@7d580000 device
   TFTP from server 192.168.4.7; our IP address is 192.168.4.147
   Filename 'image.fit'.
   Load address: 0x1000000
   Loading: ##################################################  23 MiB
   	 20.5 MiB/s
   done
   Bytes transferred = 24118272 (1700400 hex)
   U-Boot> bootm
   ## Loading kernel from FIT Image at 01000000 ...
      Using 'conf-768' configuration
      Trying 'kernel' kernel subimage
        Description:  Linux
        Type:         Kernel Image (no loading done)
        Compression:  gzip compressed
        Data Start:   0x01000120
        Data Size:    13662338 Bytes = 13 MiB
      Verifying Hash Integrity ... OK
   Bad Linux ARM64 Image magic!

With this series:

   U-Boot> tftp 20000000 image.fit
   Using ethernet@7d580000 device
   TFTP from server 192.168.4.7; our IP address is 192.168.4.147
   Filename 'image.fit'.
   Load address: 0x20000000
   Loading: ##################################################  23.5 MiB
   	 20.8 MiB/s
   done
   Bytes transferred = 24642560 (1780400 hex)
   U-Boot> bootm 0x20000000
   ## Loading kernel from FIT Image at 20000000 ...
      Using 'conf-768' configuration
      Trying 'kernel' kernel subimage
        Description:  Linux
        Type:         Kernel Image (no loading done)
        Compression:  zstd compressed
        Data Start:   0x20000120
        Data Size:    14333475 Bytes = 13.7 MiB
      Verifying Hash Integrity ... OK
   Using kernel load address 80000
   ## Loading fdt from FIT Image at 20000000 ...
      Using 'conf-768' configuration
      Trying 'fdt-768' fdt subimage
        Description:  Raspberry Pi 4 Model B
        Type:         Flat Device Tree
        Compression:  zstd compressed
        Data Start:   0x215f820c
        Data Size:    9137 Bytes = 8.9 KiB
        Architecture: AArch64
      Verifying Hash Integrity ... OK
      Uncompressing Flat Device Tree to 3aff3010
      Booting using the fdt blob at 0x3aff3010
   Working FDT set to 3aff3010
      Uncompressing Kernel Image (no loading done) to 80000
   Moving Image from 0x80000 to 0x200000, end=2b00000
      Using Device Tree in place at 000000003aff3010, end 000000003afff4c4
   Working FDT set to 3aff3010

   Starting kernel ...

   [    0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd083]

The problem is that the arm64 magic is checked before the image is
decompressed. However this is only part of it. The kernel_noload image
type doesn't work with compression, since the kernel is not loaded. So
this series deals with that by using an lmb-allocated buffer for the
uncompressed kernel.

Another issue is that the arm64 handling is done too early, before the
image is loaded. This series moves it to after loading, so that
compression can be handled.

A patch is included to show the kernel load-address, so it is easy to
see what is going on.

One annoying feature of arm64 is that the image is often copied to
another address. It might be possible for U-Boot to figure that out
earlier and decompress it to the right place, but perhaps not.

With all of this it should be possible to boot a compressed kernel on
any of the 990 arm64 boards supported by Linux, although I have only
tested two.
2023-12-15 09:41:44 -05:00
Simon Glass
69544c4fd8 bootm: Support kernel_noload with compression
It is not currently possible to execute the kernel in-place without
loading it. Use lmb to allocate memory for it.

Co-developed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Suggested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-12-15 09:41:38 -05:00
Simon Glass
bb07cdb191 bootm: Move arm64-image processing later
If the image is compressed, then the existing check fails, since the
header is wrong.

Move the check later in the boot process, after the kernel is
decompressed. This allows use of bootm with compressed kernels, while
still permitting an uncompressed kernel to be used.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-12-15 09:41:38 -05:00
Simon Glass
30ad6366c0 image: Show the load address when decompressing
The destination address for decompression (or copying) is useful
information. Show this to the user while booting, e.g.:

   Uncompressing Kernel Image (no loading done) to 2080000

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-12-15 09:41:38 -05:00
Simon Glass
cedcf38fff image: Correct load_bug typo
Correct a typo in the function comment for image_decomp().

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-12-15 09:41:38 -05:00
Patrice Chotard
395507e50d configs: stm32: Apply savedefconfig
Apply savedefconfig on all stm32 defconfig.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-12-15 15:41:23 +01:00
Patrice Chotard
ec29c07a40 board: st: common: simplify MTD device parsing
Simplify the way all MTD devices are parsed.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2023-12-15 15:41:23 +01:00
Patrice Chotard
b40f67a635 board: st: common: Fix board_get_alt_info_mtd()
Since MTD devices are partioned, we got the following
error when command "dfu 0" is executed:

DFU alt info setting: done
ERROR: Too many arguments for nor0
ERROR: DFU entities configuration failed!
ERROR: (partition table does not match dfu_alt_info?)

Fixes: 31325e1b8b ("stm32mp1: dynamically build DFU_ALT_INFO")

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2023-12-15 15:41:23 +01:00
Dario Binacchi
29e3b2430b board: stm32f469-disco: add splash screen with stmicroelectronics logo
Display the STMicroelectronics logo with features VIDEO_LOGO and
SPLASH_SCREEN on stm32f469-disco board.

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-12-15 15:41:23 +01:00
Dario Binacchi
47256b040c board: stm32f469-disco: add support to display
Add support to Orise Tech OTM8009A display on stm32f469-disco board.

It was necessary to retrieve the framebuffer address from the device tree
because the address returned by the video-uclass driver pointed to a memory
area that was not usable.

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-12-15 15:41:23 +01:00
Dario Binacchi
88c938f874 ARM: dts: stm32: support MIPI DSI on stm32f469-disco board
Unlike Linux, the DSI driver requires the LTDC clock to be properly
probed. Hence, the changes made to the DSI node.

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-12-15 15:41:23 +01:00
Dario Binacchi
451ae8daa2 ARM: dts: stm32: make the DSI clock usable by the clock driver
As described in [1], the "clocks" property contains "a phandle to the
clock device node, an index selecting between gated clocks (0) and other
clocks (1), and an index specifying the clock to use." The current version
of the clock driver, unlike the kernel, is currently able to properly
handle nodes with "clocks" properties with an index set to 0.

This patch is preparatory for future developments that require the use
of the DSI clock.

[1] Documentation/devicetree/bindings/clock/st,stm32-rcc.txt
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-12-15 15:41:23 +01:00
Dario Binacchi
6212e5bc69 ARM: dts: stm32: make the LTDC clock usable by the clock driver
As described in [1], the "clocks" property contains "a phandle to the
clock device node, an index selecting between gated clocks (0) and other
clocks (1), and an index specifying the clock to use." The current version
of the clock driver, unlike the kernel, is currently able to properly
handle nodes with "clocks" properties with an index set to 0.

This patch is preparatory for future developments that require the use
of the LTDC clock.

[1] Documentation/devicetree/bindings/clock/st,stm32-rcc.txt
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-12-15 15:41:23 +01:00
Dario Binacchi
95d1900d22 ARM: dts: stm32f469-disco: sync with Linux 6.5
Sync the devicetree with linux 6.5 for stm32f746-disco board.

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-12-15 15:41:23 +01:00
Dario Binacchi
767ca6d682 clk: stm32f: fix setting of LCD clock
Set pllsaidivr only if the PLLSAIR output frequency is an exact multiple
of the pixel clock rate. Otherwise, we search through all combinations
of pllsaidivr * pllsair and use the one which gives the rate closest to
requested one.

Fixes: 5e993508cb ("clk: clk_stm32f: Add set_rate for LTDC clock")
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-12-15 15:03:18 +01:00
Dario Binacchi
bd6eb5ddd7 clk: stm32f: fix setting of division factor for LCD_CLK
The value to be written to the register must be appropriately shifted,
as is correctly done in other parts of the code.

Fixes: 5e993508cb ("clk: clk_stm32f: Add set_rate for LTDC clock")
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-12-15 15:03:18 +01:00
Dario Binacchi
555cf4c495 ARM: dts: stm32f769-disco: rework ltdc node
With commit f479f5dbb7 ("ARM: dts: stm32: add ltdc support on
stm32f746 MCU"), which adds the 'ltdc' node in stm32f746.dtsi, we can
simplify stm32f769-disco-uboot.dtsi and align stm32f769-disco.dtsi with
the kernel version.

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-12-15 14:57:02 +01:00
Tom Rini
fa3f19aa56 Merge tag 'xilinx-for-v2024.04-rc1' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next
Xilinx changes for v2024.04-rc1

zynqmp:
- Introduce Kria specific defconfig
- Calculate SPI image location based on boot offset
- DT updates

zynqmp-clk:
- Fix topsw_lsbus_clock for DP

axi-enet:
- Support older DT binding

mailbox:
- Add support for multiple mailboxes

pcie-xilinx:
- Covert driver to newer interface
- Enable MMIO region

zynq:
- dfu updates
- Enable capsule update for Antminer S9
- DT updates

xilinx_spi:
- Add new xfer callback and support runtime fifo depth discovery
2023-12-14 13:27:11 -05:00
Jan Kiszka
959a4a0838 spi: cadence-quadspi: Fix error message on stuck busy state
We are not iterating CQSPI_REG_RETRY, we are waiting 'timeout' ms, since
day 1.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2023-12-14 23:56:19 +05:30
Bruce Suen
fd9851e0f4 mtd: spi-nor-ids: add support for xtx XT55Q02G
Add support for XTX XT55Q02G(1.8V,2Gbit).

Signed-off-by: Bruce Suen <bruce_suen@163.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2023-12-14 23:53:16 +05:30
Igor Prusov
0f2c632b8c mtd: spinand: add support for ESMT F50x1G41LB
Adaptation of Linux commit d74c36480a67

This patch adds support for ESMT F50L1G41LB and F50D1G41LB.
It seems that ESMT likes to use random JEDEC ID from other vendors.
Their 1G chips uses 0xc8 from GigaDevice and 2G/4G chips uses 0x2c from
Micron. For this reason, the ESMT entry is named esmt_c8 with explicit
JEDEC ID in variable name.

Datasheets:
https://www.esmt.com.tw/upload/pdf/ESMT/datasheets/F50L1G41LB(2M).pdf
https://www.esmt.com.tw/upload/pdf/ESMT/datasheets/F50D1G41LB(2M).pdf

Signed-off-by: Igor Prusov <ivprusov@salutedevices.com>
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
Signed-off-by: Martin Kurbanov <mmkurbanov@sberdevices.ru>
Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
Tested-by: Martin Kurbanov <mmkurbanov@sberdevices.ru>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2023-12-14 23:50:00 +05:30
Vaishnav Achath
961c3e9f12 mtd: spi-nor-core: Implement spi_nor_read_sfdp_dma_unsafe() for sfdp parse
During SFDP header parse and BFPT parse, structures in stack are used
to perform spi_nor_read_sfdp() which expects a dma-safe buffer.

This commit introduces spi_nor_read_sfdp_dma_unsafe() to wrap
spi_nor_read_sfdp() using a kmalloc'ed bounce buffer which is
the same implementation in Linux (drivers/mtd/spi-nor/sfdp.c).

Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2023-12-14 23:47:13 +05:30
Tom Rini
11e1cc7aae Merge tag 'u-boot-imx-next-20231214' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx into next
- Add TPM support for venice boards
- Add networking support for imx93-evk
- Enable TCP, IPv6, wget for DHCOM and Data Modul boards
- Enable fastboot support for Toradex boards
- Allow pico-imx7d to boot from SD
- Enable fastboot for beacon imx8m beacon boards, disabled
  SYS_CONSOLE_IS_IN_ENV
- Fix mxsboot to prevent NAND blocks being reported as bad
- Add imx8mm PWM clock support
- Several devicetree syncs with the kernel
- Add support for i.MX8MP Polyhex Debix Model A SBC
- Reworked ddr_load_train_firmware() to get a 50ms boot time improvement
2023-12-14 07:37:02 -05:00
Marek Vasut
6b73200aed arm64: imx8mp: Enable TCP, IPv6, wget on Data Modul i.MX8M eDM SBC
Enable support for TCP protocol, wget, and IPv6 on this platform.
The former two allow users download payload into the U-Boot from
a web server, which may be more convenient or easier to set up
than TFTP server. The later is enabled to future proof the IP
stack on this platform.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2023-12-14 06:24:27 -03:00
Marek Vasut
91613b1539 arm64: imx8mp: Enable TCP, IPv6, wget on DH i.MX8MP DHCOM
Enable support for TCP protocol, wget, and IPv6 on this platform.
The former two allow users download payload into the U-Boot from
a web server, which may be more convenient or easier to set up
than TFTP server. The later is enabled to future proof the IP
stack on this platform.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2023-12-14 06:20:32 -03:00
Marek Vasut
0d1186991e arm: imx6: Enable TCP, IPv6, wget on DH i.MX6 DHCOM
Enable support for TCP protocol, wget, and IPv6 on this platform.
The former two allow users download payload into the U-Boot from
a web server, which may be more convenient or easier to set up
than TFTP server. The later is enabled to future proof the IP
stack on this platform.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2023-12-14 06:20:13 -03:00
Tom Rini
86f623dcf8 Merge tag 'dm-next-13dec23' of https://gitlab.denx.de/u-boot/custodians/u-boot-dm into next
minor improvements to test, acpi
updates for new PyPl release
2023-12-13 18:39:06 -05:00
Heinrich Schuchardt
229c4da6ca test: vboot: Using variable 'old_dtb' before assignment
old_dtb can only be assumed initialized in the finally block
if it is assigned a value before the try statement.

Avoid a pylint error reported by current pylint.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-12-13 18:39:06 -05:00
Heinrich Schuchardt
643f5c37fb test: fit: Using variable 'old_dtb' before assignment
old_dtb can only be assumed initialized in the finally block
if it is assigned a value before the try statement.

Avoid a pylint error reported by current pylint.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-12-13 18:39:06 -05:00
Heinrich Schuchardt
ace49c7df7 binman: elf: Using variable 'old_val' before assignment
old_val can only be assumed initialized in the finally block
if it is assigned a value before the try statement.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-12-13 18:39:06 -05:00
Heinrich Schuchardt
aafbe1daa5 cmd: check argc for acpi dump
'acpi dump' without parameter results in a NULL dereference. Check the
number of arguments.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-12-13 18:39:06 -05:00
Ilias Apalodimas
eb09c33084 bootstd: Fix a memory leak in the efi manager bootflow
efi_get_var() allocates memory which has to be freed after the value of
the variable is consumed. Free the memory properly

Fixes: f2bfa0cb17 ("bootstd: Make efi_mgr bootmeth work for non-sandbox setups")
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
2023-12-13 18:39:06 -05:00
Neha Malcom Francis
09a17b0d01 doc: board: ti: k3: Mention TI_DM argument
Mention TI_DM argument can be used to fetch a custom DM binary in the
A72 build instructions for K3 devices.

Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Andrew Davis <afd@ti.com>
Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-12-13 18:39:06 -05:00
Neha Malcom Francis
3ef977e085 arm: dts: k3-*-binman: Move to using ti-dm entry type
Move the DM entry in tispl.bin FIT image from default fetching an
external blob entry to fetching using ti-dm entry type. This way, the
DM entry will be populated by the TI_DM pathname if provided. Else it
will resort to the ti-dm.bin file.

Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Andrew Davis <afd@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-12-13 18:39:06 -05:00
Neha Malcom Francis
23d2ef91ef binman: etype: dm: Add entry type for TI DM
K3 devices introduces the concept of centralized power, resource and
security management to System Firmware. This is to overcome challenges
by the traditional approach that implements system control functions on
each of the processing units.

The software interface for System Firmware is split into TIFS and DM. DM
(Device Manager) is responsible for resource and power management from
secure and non-secure hosts. This additional binary is necessary for
specific platforms' ROM boot images and is to be packaged into tispl.bin

Add an entry for DM. The entry can be used for the packaging of
tispl.bin by binman along with ATF and TEE.

Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Andrew Davis <afd@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-12-13 18:39:06 -05:00
Dario Binacchi
838447aa7b binman: doc: fix typo
s/use set/set/

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-By: Michael Trimarchi <michael@amarulasolutions.com>
2023-12-13 18:39:06 -05:00
Heinrich Schuchardt
36e3a1e91a cmd: acpi: fix acpi list command
ACPI tables may comprise either RSDT, XSDT, or both. The current code fails
to check the presence of the RSDT table before accessing it. This leads to
an exception if the RSDT table is not provided.

The XSDT table takes precedence over the RSDT table.

The return values of list_rsdt() and list_rsdp() are always zero and not
checked. Remove the return values.

Addresses in the XSDT table are 64-bit. Adjust the output accordingly.

As the RSDT table has to be ignored if the XSDT command is present there is
no need to compare the tables in a display command. Anyway the
specification does not require that the sequence of addresses in the RSDT
and XSDT table are the same.

The FACS table header does not provide revision information. Correct the
description of dump_hdr().

Adjust the ACPI test to match the changed output format of the 'acpi list'
command.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-12-13 18:39:06 -05:00
Heinrich Schuchardt
bda020e762 acpi: fix struct acpi_xsdt
The size of the ACPI table header is not a multiple of 8. We have to mark
struct acpi_xsdt as packed to correctly access field Entry.

Add a unit test for the offsets of field Entry in the RSDT and XSDT tables.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-12-13 18:39:06 -05:00
Simon Glass
049ee90903 tools: Move python tools to version 0.0.6
A new release has been done with this version, so update it. Use the
version numbers in dependencies also.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-12-13 18:39:06 -05:00
Simon Glass
dff917d973 patman: Update the run script
Patman now has its main program in a function, so update the toml file
to match.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-12-13 18:39:06 -05:00
Simon Glass
01feeec559 tools/make_pip: Add mention of u_boot_pylib in tool list
This is not a tool but it is handled by the script, so update the help
to include it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-12-13 18:39:06 -05:00
Simon Glass
6b9fbb47e4 u_boot_pylib: Correct files used for pip release
The files list is incorrect and dates from a time when the script was
run from a different directory. Update it to match all the other tools.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-12-13 18:39:06 -05:00
Simon Glass
f12465ce91 tools: Keep test_util and patman test files in the pip release
The test_util module is actually imported by some tools, e.g. binman so
include it in the pip release.

The patman tool uses its test code when starting up, so keep that too.

Show a list of deleted files so it is clear what is happening.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-12-13 18:39:06 -05:00
Simon Glass
ec31f8bac7 u_boot_pylib: Correct readme formatting
Correct a heading which is too short in the readme.

Fixes: 75554dfac2 ("patman: Add support for building a u_boot_tools...")

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-12-13 18:39:05 -05:00
Simon Glass
4c4977cbc9 doc: Update documentation URL
Update to use the new docs.u-boot.org URL for documentation.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-12-13 18:39:05 -05:00
Heinrich Schuchardt
0c2f6c317f test: unit test for acpi_find_table()
Provide a unit test for acpi_find_table()

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-12-13 18:39:05 -05:00
Heinrich Schuchardt
5574d82fbc acpi: consider XSDT in acpi_find_table()
The RSDT table is deprecated and does not exist on all systems.

By preference scan XSDT for the table to find. If no XSDT table exists, try
to use the RSDT table.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2023-12-13 18:39:05 -05:00
Heinrich Schuchardt
fef4896dc8 acpi: simplify acpi_write_ssdt()
* Converting to void * is superfluous when calling memset().
* acpi_fill_header() already fills oem_table_id.

Fixes: d953137526 ("x86: Move SSDT table to a writer function")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-12-13 18:39:05 -05:00
Heinrich Schuchardt
c7b31a9ad5 acpi: cannot have RSDT above 4 GiB
The field RsdtAddress has only 32 bit. The RSDT table cannot be located
beyond 4 GiB.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-12-13 18:39:05 -05:00
Simon Glass
dbdc9c6aef fdt: Move ft_verify_fdt() before the final fixups
Move this check before the FDT fixups so that we can use a livetree
after this point.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-12-13 18:39:05 -05:00
Simon Glass
79e9727f15 fdt: Drop the confusing casts in lmb_free()
Just use map_to_sysmem() instead of all the casting.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-12-13 18:39:05 -05:00
Simon Glass
f2cbe6e43e boot: Move adding initrd earlier in image_setup_libfdt()
This may as well happen before the general event is emitted, so move it.
This will allow us to use the livetree for the event part, but the
flattree for the earlier part.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-12-13 18:39:05 -05:00
Simon Glass
83cd8fb13c fdt: ppc: Drop extra size for ramdisk
This code dates from around 2008:

   56844a22b7 powerpc: Fix bootm to boot up again with a Ramdisk

Since then we have added FDT relocation which provides enough space
for expansion. We have also added all sorts of fixups earlier in
image_setup_libfdt() which require more space, with ramdisk being the
least of them.

Therefore this extra hack for ramdisk seems unnecessary. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-12-13 18:39:05 -05:00
Simon Glass
451c1ab6b0 fdt: Improve the comment for fdt_shrink_to_minimum()
Add a bit more detail about what this function does.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-12-13 18:39:05 -05:00
Simon Glass
9578dd856a fdt: Check for a valid fdt in oftree_ensure()
Check the header before starting to use it, since this could provide
very confusing later, when ofnode calls start to fail.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-12-13 18:39:05 -05:00
Simon Glass
1de1a03487 boot: Drop size parameter from image_setup_libfdt()
The of_size parameter is not used, so remove it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-12-13 18:39:05 -05:00
Heinrich Schuchardt
c659ac7cca acpi: move acpi_get_rsdp_addr() to acpi/acpi_table.h
Function acpi_get_rsdp_addr() is needed on all architectures which
write ACPI tables. Move the definition from the x86 include to an
architecture independent one.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-12-13 18:39:05 -05:00
Simon Glass
a4bee0b455 bootstd: Add a menu option to bootflow scan
Allow showing a menu and automatically booting, with 'bootflow scan'.
This is more convenient than using a script.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-12-13 18:39:05 -05:00
Simon Glass
6b8f26bca4 sandbox: Add a dummy booti command
Add basic sandbox support for 'booti' so we can start to boot the test
ARMbian image. This is helpful in checking that it is parsed correctly.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-12-13 18:39:05 -05:00
Simon Glass
cde03fa23e video: Add a function to clear the display
Move the code from the 'cls' command into the console file, so it can
be called from elsewhere.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-12-13 18:39:05 -05:00
Simon Glass
c0e708eb9f test: print: Skip test on x86
These tests cannot work on x86 machines as memory at address zero is
not writable. Add a condition to skip these.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-12-13 18:39:05 -05:00
Simon Glass
631d8a34f3 test: lmb: Move tests into the lib suite
These tests are marked as driver model tests, but have nothing to do
with driver model. As a result, they are run as part of 'ut dm' which
only exists for sandbox.

Move them to the 'lib' suite and drop the requirement for initing
devices, since they don't use devices.

Also put the lib_test_lmb_max_regions() macro inside the same #ifdef
as its function, to avoid a build error if the condition is false.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-12-13 18:39:05 -05:00
Simon Glass
14f0cc49df test: event: Only run test_event_probe() on sandbox
This needs test devices which are only present on sandbox. Add a check
for this and skip just this test if running on a real board.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-12-13 18:39:05 -05:00
Simon Glass
078c6e2f8a test: font: Add dependencies on fonts
The font test needs two fonts. If one is not available, skip out early,
to avoid an error.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-12-13 18:39:05 -05:00
Simon Glass
40565bba7c test: fdt: Add a special case for real boards
The error that this test checks for is only shown on sandbox. For real
boards, there is normally no error. Add a special case to handle this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-12-13 18:39:05 -05:00
Simon Glass
3535f60726 test: bdinfo: Add missing asserts
Calling into sub-test functions should be done using ut_assertok() so
that the test exits immediately on failure. Add those which are
missing.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-12-13 18:39:05 -05:00
Simon Glass
80a8a2ebb3 test: Handle use of stack pointer in bdinfo
This test assumes that the stack pointer is the same across two calls
to lmb_init_and_reserve() but this is not the case on x86, for example.

Add a special case to handle this, along with a detailed comment.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-12-13 18:39:05 -05:00
Simon Glass
07073d2beb test: Run bootstd tests only on sandbox
These make use of disk images which are not available on reak boards.
Add a new Kconfig to ensure these tests only run where they are valid.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-12-13 18:39:05 -05:00
Simon Glass
f2311519ca test: Make UT_LIB_ASN1 depend on sandbox
This doesn't seem to work on a real board, so use the test on sandbox
only.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-12-13 18:39:05 -05:00
Simon Glass
30a75e7794 test: Add helper to skip to partial console line
Sometimes we need to skip to a line but it includes addresses or other
information which can vary depending on the runtime conditions.

Add a new ut_assert_skip_to_linen() which is similar to the existing
ut_assert_skip_to_line() function but only checks that the console line
matches up to the length of the provided string.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-12-13 18:39:05 -05:00
Simon Glass
4001e5ab9b test: Add a new suite for commands
Add a new suite for 'cmd' tests, used for testing commands. These are
kept in the test/cmd directory.

For now it is empty, but it will be used for coreboot-command tests.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-12-13 18:39:04 -05:00
Benjamin Szőke
03622f3012 pico-imx7d: add baseboard SD card boot detect
Technexion PICO-IMX7 SoM is supporting USDHC3 (eMMC or micro SD on SoM)
and USDHC1 (SD on carrier board) to use on any carrier board like
PICO-NYMPH. Based on the U-Boot version from Technexion it adds
baseboard SD card boot detect to able to boot from selected USDHC1
or USDHC3 boot devices.

Signed-off-by: Benjamin Szőke <egyszeregy@freemail.hu>
Tested-by: Fabio Estevam <festevam@gmail.com>
2023-12-13 15:55:13 -03:00
Fabio Estevam
04bb59b408 imx: imx-hab: Select SPL_DRIVERS_MISC in the SPL case
Selecting CONFIG_IMX_HAB=y on a SPL target, such as apalis_imx6_defconfig,
for example, leads to the following build error:

/usr/bin/arm-linux-gnueabihf-ld.bfd: arch/arm/mach-imx/hab.o: in function `imx_hab_is_enabled':
arch/arm/mach-imx/hab.c:879: undefined reference to `fuse_read'

fuse_read() comes from SPL_MXC_OCOTP, which depends on SPL_DRIVERS_MISC,
since commit 251a3053b1 ("misc: imx: remove DM dependency for ocotp
driver in SPL").

Select SPL_DRIVERS_MISC in the SPL case to fix this build issue.

Reported-by: Lisandro Pérez Meyer <lpmeyer@ics.com>
Signed-off-by: Fabio Estevam <festevam@denx.de>
Tested-by: Lisandro Pérez Meyer <lpmeyer@ics.com>
2023-12-13 15:37:52 -03:00
Alessandro Rubini
4ac5620270 tools: mxsboot: pre-fill buffer with 0xff, not 0
The tool works for me, with imx28 and NAND memory, but the resulting
blocks are reported as bad, both by u-boot and the kernel.

This makes it impossible to erase from Linux (for an upgrade without
console access, for example -- u-boot can "nand scrub" but linux can't).

pre-filling with 0xff creates a proper boot loader image, but no
bad-block marker is there when written to flash.

Signed-off-by: Alessandro Rubini <rubini@gnudd.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2023-12-13 15:33:57 -03:00
Marek Vasut
712aa6e24c arm: mxs: Clear CPSR V bit to activate low vectors
The MXS starts with CPSR V bit set, which makes the CPU jump to high vectors
in case of an exception. Those high vectors are located at 0xffff0000, which
is where the BootROM exception table is located as well. U-Boot should handle
exceptions on its own using its own exception handling code, which is located
at 0x0, i.e. at low vectors. Clear the CPSR V bit, so that the CPU would jump
to low vectors on exception instead, and therefore run the U-Boot exception
handling code.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2023-12-13 15:33:21 -03:00
Tom Rini
9565771076 Merge patch series "bootm: Refactoring to reduce reliance on CMDLINE (part A)"
To quote the author:

It would be useful to be able to boot an OS when CONFIG_CMDLINE is
disabled. This could allow reduced code size.

Standard boot provides a way to handle programmatic boot, without
scripts, so such a feature is possible. The main impediment is the
inability to use the booting features of U-Boot without a command line.
So the solution is to avoid passing command arguments and the like to
code in boot/

A similar process has taken place with filesystems, for example, where
we have (somewhat) separate Kconfig options for the filesystem commands
and the filesystems themselves.

This series starts the process of refactoring the bootm logic so that
it can be called from standard boot without using the command line.
Mostly it removes the use of argc, argv and cmdtbl from the internal
logic.

Some limited tidy-up is included, but this is kept to smaller patches,
rather than trying to remove all #ifdefs etc. Some function comments
are added, however.

A simple programmatic boot is provided as a starting point.

This work will likely take many series, so this is just the start.

Size growth with this series for firefly-rk3288 (Thumb2) is:

       arm: (for 1/1 boards) all +23.0 rodata -49.0 text +72.0

This should be removed by:

   https://source.denx.de/u-boot/custodians/u-boot-dm/-/issues/11

but it is not included in this series as it is already large enough.

No functional change is intended in this series.

Changes in v3:
- Add a panic if programmatic boot fails
- Drop RFC tag

Changes in v2:
- Add new patch to adjust position of unmap_sysmem() in boot_get_kernel()
- Add new patch to obtain command arguments
- Fix 'boot_find_os' typo
- Pass in the command name
- Use the command table to provide the command name, instead of "bootm"
2023-12-13 11:51:53 -05:00
Simon Glass
8632b36b96 command: Introduce functions to obtain command arguments
Add some functions which provide an argument to a command, or NULL if
the argument does not exist.

Use the same numbering as argv[] since it seems less confusing than the
previous idea.

Signed-off-by: Simon Glass <sjg@chromium.org>
Suggested-by: Tom Rini <trini@konsulko.com>
2023-12-13 11:51:24 -05:00
Simon Glass
1047b5340c bootstd: Introduce programmatic boot
At present bootstd requires CONFIG_CMDLINE to operate. Add a new
'programmatic' boot which can be used when no command line is available.
For now it does almost nothing, since most bootmeths require the
command line.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-12-13 11:51:24 -05:00
Simon Glass
984e6fedb5 bootm: Reduce arguments to bootm_find_other()
Rather than passing the full list of command arguments, pass only those
which are needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-12-13 11:51:24 -05:00
Simon Glass
65f0bfe28a bootm: Add a function to check overlap
Move this code into a function to reduce code size and make it easier
to understand. Drop the unnecessary 0x to help a little with code size.

Use this in bootm_find_images()

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-12-13 11:51:24 -05:00
Simon Glass
3ac85bdc6a bootm: Adjust the parameters of bootm_find_images()
Rather than passing it all the command-line args, pass in the pieces
that it needs. These are the image address, the ramdisk address/name
and the FDT address/name.

Ultimately this will allow usage of this function without being called
from the command line.

Move the function comment to the header file and tidy it a little.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-12-13 11:51:24 -05:00
Simon Glass
b020254d71 bootm: optee: Drop special call to bootm_find_other()
The normal bootm flow calls bootm_find_other() can call the
BOOTM_STATE_FINDOTHER state as part of its processing. Fix the
condition there so that this hack can be removed.

Also drop the confusing check for the OS type, since do_bootm_tee() is
only called if the condition is met - see bootm_os_get_boot_func()

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-12-13 11:51:24 -05:00
Simon Glass
e2fc90e5ad bootm: efi: Drop special call to bootm_find_other()
The normal bootm flow calls bootm_find_other() can call the
BOOTM_STATE_FINDOTHER state as part of its processing. Fix the
condition there so that this hack can be removed.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-12-13 11:51:24 -05:00
Simon Glass
46aee252af bootm: Simplify Android ramdisk addr in bootm_find_images()
The Android mechanism uses the loadaddr envrionment-variable to get the
load address, if none is provided. This is equivalent to
image_load_addr so use that instead, converting it to a string as
needed.

This change will permit passing img_addr to this function, in a future
change.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-12-13 11:51:24 -05:00
Simon Glass
96456285c2 bootm: Reduce arguments to boot_get_loadables()
This function only uses two arguments. The 'arch' always has a constant
value, so drop it. This simplifies the function call.

Tidy up the function comment while we are here.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-12-13 11:51:24 -05:00
Simon Glass
745367b218 bootm: Reduce arguments to boot_get_fpga()
This function only uses two arguments. The 'arch' always has a constant
value, so drop it. This simplifies the function call.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-12-13 11:51:24 -05:00
Simon Glass
0aa923aba5 bootm: Reduce arguments to boot_get_fdt()
This function only uses one argument from bootm (argv[2]) so pass it in
directly.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-12-13 11:51:24 -05:00
Simon Glass
ba5e3f7f78 bootm: Pass image buffer to boot_get_fdt()
Rather than having boot_get_fdt() calculate this, move the calculation
into the caller. This removes the access to argv[0] in this function,
so we can later refactor it to just accept argv[2] instead of the whole
argv[].

Move the function comment to the header file and fix the u8 argument,
while we are here.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-12-13 11:51:24 -05:00
Simon Glass
972d524893 bootm: Drop #ifdef in bootm_find_images()
The OF_LIBFDT #ifdef makes it harder to use a local variable for that
code block. Convert it to if() instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-12-13 11:51:24 -05:00
Simon Glass
813f75d858 fdt: Allow use of fdt_support inside if() statements
Most of the fdt_support.h header file is included only if OF_LIBFDT or
OF_CONTROL are enabled. This means that calling functions defined in
that file must happen inside an #ifdef

This is unnecessary, so reduce the condition to just !USE_HOSTCC

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-12-13 11:51:24 -05:00
Simon Glass
8eda15bc6a bootm: Reduce arguments to boot_get_ramdisk()
This function normally only uses one argument so pass it in directly.
Move comments to the header file so could one day include these
functions in API docs. Fix up the u8 argument while here, since it
avoids the compiler having to mask the value on some machines.

The Android case here is bit strange, since it can use argv[0], so deal
with that in the caller.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-12-13 11:51:24 -05:00
Simon Glass
3e3bd5bda7 bootm: Reduce arguments to bootm_find_os()
This function only uses one argument so pass it in directly.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-12-13 11:51:24 -05:00
Simon Glass
b13e94886c bootm: Move error printing out of boot_get_kernel()
The same error message is printed in two places. Move it out to the
caller so we can avoid passing in the command name. Leave the bootstage
handling where it is.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-12-13 11:51:24 -05:00
Simon Glass
bdfa1b6785 bootstage: Drop BOOTSTAGE_ID_FIT_KERNEL_INFO
This is a misnomer since we don't necessarily know that the image is a
FIT. Use the existing BOOTSTAGE_ID_CHECK_IMAGETYPE instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-12-13 11:51:24 -05:00
Simon Glass
4c76f5e49a bootm: Use the error return from boot_get_kernel()
Rather than looking for a zero-sized image, use the error code returned
to determine if things are OK.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-12-13 11:51:24 -05:00
Simon Glass
4f77169c94 bootm: Adjust position of unmap_sysmem() in boot_get_kernel()
These unmaps should happen regardless of the return value. Move them
before the 'return' statement.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-12-13 11:51:24 -05:00
Simon Glass
7721e71f03 bootm: Adjust boot_get_kernel() to return an error
This function obtains lots of error codes and then throws them away.
Update it to return the error, moving the image pointer to an
argument.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-12-13 11:51:24 -05:00
Simon Glass
429acb38db image: Document error codes from fit_image_load()
Put a list of these in the function documentation so it is easier to
decode what went wrong.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-12-13 11:51:24 -05:00
Simon Glass
820110c453 bootm: Reduce arguments to boot_get_kernel()
This function only uses one argument and just needs to know the name of
the command which called it. Adjust the function to use only what it
needs. This will make it easier to call from a non-command context.

Tidy up the function comment while we are here.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-12-13 11:51:24 -05:00
Simon Glass
530cc4797f image: Tidy up genimg_get_kernel_addr_fit()
This function does not modify its first argument, so mark it const. Also
move the comments to the header file and expand them to provide more
useful information.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-12-13 11:51:24 -05:00
Simon Glass
7f3b1ee3b2 bootm: Move boot_get_kernel() higher in the file
Move this code and image_get_kernel() higher in the file to avoid the
need for a forward declaration.

No attempt is made to remove #ifdefs or adjust the code in any other
way.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-12-13 11:51:24 -05:00
Simon Glass
921070bcdc bootm: Simplify arguments for bootm_pre_load()
Move the argument decoding to the caller, to avoid needing to pass the
command-line arguments.

Add a function comment while we are here.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-12-13 11:51:24 -05:00
Simon Glass
a50e886a7f bootm: Drop arguments from bootm_start()
This function does not use its arguments. Drop them.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2023-12-13 11:51:24 -05:00
Simon Glass
e62714ca5f bootstd: Add missing header file from bootdev.h
Add a dm/uclass-id.h to the bootdev header file, since it uses
enum uclass_id

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2023-12-13 11:51:24 -05:00
Simon Glass
10c398d6e4 treewide: Tidy up semicolon after command macros
The U_BOOT_CMD_COMPLETE() macro has a semicolon at the end, perhaps
inadvertently. Some code has taken advantage of this.

Tidy this up by dropping the semicolon from the macro and adding it to
macro invocations as required.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2023-12-13 11:51:24 -05:00
Simon Glass
f7fac5e7f5 mmc: env: Unify the U_BOOT_ENV_LOCATION conditions
The declaration of U_BOOT_ENV_LOCATION() uses a different #ifdef
condition from the code it calls. Use the same condition to avoid a
build warning if CONFIG_CMD_SAVEENV is disabled.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2023-12-13 11:51:24 -05:00
Simon Glass
1d38722e01 README: Correct docs for CONFIG_SPL_BUILD
This option is defined in both SPL and TPL builds, so correct the docs
related to this. Also point to spl_phase() which is normally a better
option. Mention VPL as well.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2023-12-13 11:51:24 -05:00
Simon Glass
b1f8b56f45 arm: x86: Drop discarding of command linker-lists
Since we can now cleanly disable CMDLINE when needed, drop the rules
which discard the command code.  It will not be built in the first
place.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2023-12-13 11:51:24 -05:00
Tom Rini
bfe3c7b93b Merge patch series "some LED patches"
To quote the author:

I wanted to add support for ti,lp5562, and found an old submission
from Doug. While trying to modify that to work in current U-Boot, I
found a problem with the "move label handling to core" patches.

Patch 1 is a prerequisite for the ti,lp5562 driver, which turned out
to be needed by Christian as well.

Patch 2 is an attempt at (quick-)fixing the mentioned "move label
handling to core" problem. The real fix consists of changing remaining
drivers to not bind the same driver to the top node as to the child
nodes, but I can't test those other drivers.

Patch 3 introduces a helper which should allow removing some
boilerplate in most individual drivers, and 4,5 apply that in the gpio
and pwm drivers. Converting remaining drivers is trivial, but left out
for now.

Finally patch 6 is the reworked lp5562 driver. While I've changed it
to match existing DT bindings (with the goal of making it work with
our .dts that is known to work with the linux driver), most of the
logic is unchanged from Doug's original patch, so he is still listed
as author.

Changes in v2: Interchange order of patches 1 and 2, add a few R-bs,
and try to trim down the commit message in patch 2.
2023-12-13 11:35:17 -05:00
Doug Zobel
f9dc67d18e led: add TI LP5562 LED driver
Driver for the TI LP5562 4 channel LED controller. Supports
independent on/off control of all 4 channels. Supports LED_BLINK on 3
independent channels: blue/green/red. The white channel can blink, but
shares the blue channel blink rate.

Heavily based on patch originally from Doug Zobel [1].

I have modified it so it matches the DT bindings in the linux tree,
and also follows the linux driver implementation more closely. This
should address Tom's concerns, and also matches my goal of making the
U-Boot driver work with our existing .dts which is known to work in
linux.

As our boards only have the R,G,B outputs connected, I have not
actually tested how the white channel behaves, but the R,G,B work
exactly as expected.

[1] https://lore.kernel.org/u-boot/1547150757-1561-1-git-send-email-douglas.zobel@climate.com/

Cc: Doug Zobel <douglas.zobel@climate.com>
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2023-12-13 11:35:16 -05:00
Rasmus Villemoes
d45e712f88 led: led_pwm: use led_bind_generic() helper
Use the helper led_bind_generic() to reduce code duplication.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2023-12-13 11:35:15 -05:00
Rasmus Villemoes
82eb8e5171 led: led_gpio: use led_bind_generic() helper
Use the helper led_bind_generic() to reduce code duplication.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2023-12-13 11:35:15 -05:00
Rasmus Villemoes
3bf0515a07 led: introduce led_bind_generic()
All existing drivers in drivers/led/ contain a .bind method that does
exactly the same thing, with just the actual driver name
differing. Create a helper so all those individual methods can be
changed to one-liners.

Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2023-12-13 11:35:13 -05:00
Rasmus Villemoes
067e4ce35b led-uclass: do not create fallback label for top-level node
Many existing drivers, and led-uclass itself, rely on uc_plat->label
being NULL for the device representing the top node, as opposed to the
child nodes representing individual LEDs. This means that the drivers
whose .probe methods rely on this were broken by commit 83c63f0d11
("led: Move OF "label" property parsing to core"), and also that the top
node wrongly shows up with 'led list'.

Binding the same driver to the top node as to the individual child
nodes is arguably wrong, and the approach of using a UCLASS_NOP driver
for the top node is probably better - this has for example been done in
commit 0107469780 ("led: gpio: Use NOP uclass driver for top-level
node") and commit 910b01c27c ("drivers: led: bcm6753: do not use null
label to find the top")

Until remaining affected drivers are fixed, we can use a heuristic
that only sets the label to the fallback value derived from the node
name if the node does not have a "compatible" property - i.e., if it
has been bound to the LED driver explicitly via
device_bind_driver_to_node(). This is similar to what commit
e3aa76644c ("led: gpio: Check device compatible string to determine
the top level node") did for gpio_led, but that fix was then supplanted
by commit 0107469780 ("led: gpio: Use NOP uclass driver for top-level
node")

Fixes: 83c63f0d11 ("led: Move OF "label" property parsing to core")
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2023-12-13 11:34:53 -05:00
Rasmus Villemoes
5bf61f918d led-uclass: honour ->label field populated by driver's own .bind
If the driver's own .bind method has populated uc_plat->label, don't
override that. This is necessary for an upcoming driver for ti,lp5562,
where the DT binding unfortunately says to use "chan-name" and not
"label".

Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2023-12-13 11:34:49 -05:00
Venkatesh Yadav Abbarapu
4f340244b9 clk: zynqmp: enable topsw_lsbus clock
Display port is using topsw_lsbus clock, it is failing
while enabling the clock, so enable the topsw_lsbus clock.

Signed-off-by: Sreekanth Sunnam <sreekanth.sunnam@amd.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20231204084515.9488-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-12-13 16:48:15 +01:00
Nicolas Heemeryck
cb1d68b143 clk: imx8mn: add pwm clocks
Based on Linux kernel 6.7-rc4, add necessary clocks for the PWM
controllers.

Signed-off-by: Nicolas Heemeryck <nicolas.heemeryck@devialet.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2023-12-13 10:03:46 -03:00
Hiago De Franco
220bb4e150 board: apalis/colibri imx6/imx6ull/imx7: Add fastboot bootcmd support
This commit adds support for Fastboot boot commands by checking both
CONFIG_CMD_USB_SDP and CONFIG_USB_FUNCTION_FASTBOOT. If either of these
configurations is set, it indicates that the board is in recovery mode
and can use either SDP or Fastboot.

The default option remains the SDP command, but if
CONFIG_CMD_FASTBOOT is set, it changes to 'fastboot usb 0' as
the boot command.

Signed-off-by: Hiago De Franco <hiago.franco@toradex.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2023-12-13 10:03:14 -03:00
Hiago De Franco
50c67ddbe4 apalis/colibri imx6/imx6ull/imx7: defconfig: Enable fastboot support
Add fastboot support for Apalis iMX6, Colibri iMX6, Colibri iMX6ULL and
Colibri iMX7 boards. Remove CONFIG_FASTBOOT_BUF_SIZE from
colibri_imx7_emmc_defconfig to get the default value of 0x7000000 instead
of 0x10000000, to make it consistent with the other boards.

Signed-off-by: Hiago De Franco <hiago.franco@toradex.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2023-12-13 10:03:13 -03:00
Fabio Estevam
4b5c1175a2 imx7d-pico-pi-u-boot.dtsi: Fix aliases indentation
The aliases are currently indented using spaces.

Fix it to use the standard tab indentation.

Signed-off-by: Fabio Estevam <festevam@denx.de>
2023-12-13 10:02:45 -03:00
Fabio Estevam
99da64e1ef pico-imx7d: Remove board_phy_config()
With Ethernet DM in place, there is no longer the need for having
the board_phy_config() anymore.

Remove it.

Tested on imx7d-pico-pi board:

=> setenv autoload no
=> dhcp
BOOTP broadcast 1
*** Unhandled DHCP Option in OFFER/ACK: 42
DHCP client bound to address 192.168.0.138 (138 ms)
=> tftp zImage
Using ethernet@30be0000 device
TFTP from server 192.168.0.16; our IP address is 192.168.0.138
Filename 'zImage'.
Load address: 0x80800000
Loading: #################################################################
....
	 #################################################################
	 ##########
	 4.3 MiB/s
done
Bytes transferred = 9034120 (89d988 hex)

Signed-off-by: Fabio Estevam <festevam@denx.de>
2023-12-13 10:02:04 -03:00
Arnaud Ferraris
62b1bbdfdf librem5: Add addresses for compressed kernel load
The "booti" command to load arm64 Linux kernels supports automatic
decompression of zipped kernel images, but relies on some environment
variables to point to usable buffer RAM.

Add those variables and let them point to some default values, that
should cover most use-cases.

Signed-off-by: Arnaud Ferraris <arnaud.ferraris@collabora.com>
2023-12-13 10:01:09 -03:00
Arnaud Ferraris
4ae3fcdf7b librem5: properly set the fdtfile env variable
In order to use the generic "distro boot" using an extlinux.conf file,
the `fdtfile` environment variable is mandatory. This commit ensure this
variable is properly constructed based on the detected board revision.

Signed-off-by: Arnaud Ferraris <arnaud.ferraris@collabora.com>
2023-12-13 10:00:43 -03:00
Adam Ford
4c303a3895 configs: imx8mn_beacon: Disable the WDT autostart
Auto-starting the WDT can cause false reboots when the user
is not intentionally trying to use the WDT, so leave it off until
it is requested.

Signed-off-by: Adam Ford <aford173@gmail.com>
2023-12-13 10:00:13 -03:00
Adam Ford
353c9aa18c configs: imx8mn_beacon: Do not set SYS_CONSOLE_IS_IN_ENV
The hardware only supports a specific console port, so  remove the
option to change the console location in the environment.

Signed-off-by: Adam Ford <aford173@gmail.com>
2023-12-13 10:00:13 -03:00
Adam Ford
856227292a configs: imx8mm_beacon: Disable the WDT autostart
Auto-starting the WDT can cause false reboots when the user
is not intentionally trying to use the WDT, so leave it off until
it is requested.

Signed-off-by: Adam Ford <aford173@gmail.com>
2023-12-13 10:00:13 -03:00
Adam Ford
495bec2ec8 configs: imx8mm_beacon: Enable fastboot downloading
Fastboot is necessary to use UUU enhanced functions, so enable it.

Signed-off-by: Adam Ford <aford173@gmail.com>
2023-12-13 10:00:13 -03:00
Adam Ford
dc48e263a6 configs: imx8mp_beacon: Do not set SYS_CONSOLE_IS_IN_ENV
The hardware only supports a specific console port, so  remove the
option to change the console location in the environment.

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2023-12-13 10:00:13 -03:00
Hugo Villeneuve
bdd32b8cbc MAINTAINERS: Remove non-working address from MAINTAINERS
The address ariel.dalessandro@collabora.com is no longer working:

  A message that you sent could not be delivered to one or more of its
  recipients. This is a permanent error. The following address(es) failed:

  ariel.dalessandro@collabora.com
    host mx.collabora.co.uk [46.235.227.165]
    SMTP error from remote mail server after RCPT TO:<ariel.dalessandro@collabora.com>:
    550 5.1.1 <ariel.dalessandro@collabora.com>: Recipient address rejected:
    undeliverable address: host mail.collabora.co.uk[46.235.227.172] said:
    550 5.1.1 <ariel.dalessandro@collabora.com>: Recipient address rejected:
    User unknown in local recipient table (in reply to RCPT TO command)

Remove this address from MAINTAINERS.

Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2023-12-13 09:59:32 -03:00
Hugo Villeneuve
739d9b8f7c imx8mn-var-som: Simplify FEC initialization
With DM enabled, there is no need for board code to initialize
the FEC interface.

The ethernet PHYs on the symphony carrier board have a dedicated
crystal/oscillator. If the SOM has the EC configuration option
(onboard ethernet PHY), it also has a dedicated crystal/oscillator.
So in all cases, there is no need to enable the RGMII TX clk output.

This follows a similar change introduced by Fabio Estevam:
  Link: https://lore.kernel.org/u-boot/20231019170441.1610453-1-festevam@gmail.com/

Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2023-12-13 09:58:46 -03:00
Hugo Villeneuve
38bcce4bb6 imx8mn_var_som: Add myself to MAINTAINERS
I would like to help maintaining the imx8mn_var_som symphony board.

Add myself to MAINTAINERS.

Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2023-12-13 09:58:27 -03:00
Fabio Estevam
458ab6b9f2 clock_imx8mm: Add a stub for imx8mp_fec_interface_init()
When CONFIG_DWC_ETH_QOS_IMX=y and CONFIG_FEC_MXC is not selected, the
following warning is seen:

arch/arm/mach-imx/imx8m/clock_imx8mm.c: In function 'board_interface_eth_init':
arch/arm/mach-imx/imx8m/clock_imx8mm.c:914:24: warning: implicit declaration of function 'imx8mp_fec_interface_init; did you mean 'imx8mp_eqos_interface_init'? [-Wimplicit-function-declaration]

Fix it by adding a stub for imx8mp_fec_interface_init() to handle this
case.

This follows the same approach done on imx8mp_eqos_interface_init().

Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
2023-12-13 09:54:32 -03:00
Fabio Estevam
7d6b706d10 imx8mp_evk: Remove unneeded header files
Cleanup the file by removing unneeded header files.

Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
2023-12-13 09:54:00 -03:00
Fabio Estevam
21b30c237a imx8mp_evk: Simplify Ethernet initialization
With DM enabled, there is no need for board code to initialize
the Ethernet interfaces.

The RTL8211FDI Ethernet PHYs have 25MHz oscillator, so there is no
need to enable the RGMII TX clk output.

Also, there is no need for describing the deprecated phy-reset FEC
properties, nor passing reset properties to the EQOS interface in
u-boot.dtsi.

Remove all these unneeded pieces.

Tested both Ethernet interfaces after these changes.

Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
2023-12-13 09:54:00 -03:00
Fabio Estevam
7e3d6ec9bf phy: phy-imx8mq-usb: Remove .exit operation
Currently, when running "ums 0 mmc 2" and breaking it via
CTRL + C, the following message is seen:

u-boot=> ums 0 mmc 1
UMS: LUN 0, dev mmc 1, hwpart 0, sector 0x0, count 0x1dacc00
CTRL+C - Operation aborted
clk usb_phy_root_clk already disabled

The USB PHY clock is disabled twice: first it gets disabled
inside imx8mq_usb_phy_power_off(), then it is disabled again
inside imx8mq_usb_phy_exit().

Let the USB PHY clock be disabled only once inside
imx8mq_usb_phy_power_off() by removing the .exit operation.

Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
2023-12-13 09:52:53 -03:00
Fabio Estevam
f319766891 arm: dts: imx8mp: Sync with linux-next 20231019
Sync imx8mp.dtsi and imx8mp-clock.h with linux-next 20231019.

Signed-off-by: Fabio Estevam <festevam@denx.de>
2023-12-13 09:52:18 -03:00
Fabio Estevam
05dffb9fb1 arm: dts: imx8mn: Sync with linux-next 20231019
Sync imx8mn.dtsi with linux-next 20231019.

Signed-off-by: Fabio Estevam <festevam@denx.de>
2023-12-13 09:52:18 -03:00
Fabio Estevam
5037bd532d arm: dts: imx8mm: Sync with linux-next 20231019
Sync imx8mm.dtsi with linux-next 20231019.

The motivation for doing this sync was a bug when doing "ums 0 mmc 1"
on imx8mm-evk. It worked well for the first time, but after doing
a CTRL+C and launching the ums again, the command did not work.

Adam Ford suggested to sync imx8mm.dtsi with the Linux dts, as there was
a recent USB power domain reorganization there.

After syncing the imx8mm.dtsi with Linux, the ums command works without
problem after a CTRL+C.

Suggested-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Fabio Estevam <festevam@denx.de>
Acked-by: Tim Harvey <tharvey@gateworks.com>
2023-12-13 09:52:18 -03:00
Fabio Estevam
ae09edaeec imx8mp_evk: Add myself to MAINTAINERS
I would like to help maintaining the imx8mp_evk board.

Add myself to MAINTAINERS.

Signed-off-by: Fabio Estevam <festevam@denx.de>
Acked-by: Peng Fan <peng.fan@nxp.com>
2023-12-13 09:51:27 -03:00
Fabio Estevam
6e6492c85d imx8mp_evk: Convert to DM_PMIC
Currently, the imx8mp_evk uses the non-DM code to initialize the PMIC.

Convert to DM_PMIC, which is the recommended way to access the PMIC.

While at it, fix multi-line comments style.

Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-12-13 09:51:27 -03:00
Tim Harvey
a7d54d3de8 arm: dts: imx8mp-venice-gw73xx: add TPM device
Add the TPM device found on the GW73xx revision F PCB.

This hangs off of SPI2, uses gpio1_10 as a CS and gpio1_11 as RST#.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2023-12-13 09:50:37 -03:00
Tim Harvey
bb1e22ca53 arm: dts: imx8mm-venice-gw73xx: add TPM device
Add the TPM device found on the GW73xx revision F PCB.

This hangs off of SPI2, uses gpio1_10 as a CS and gpio1_11 as RST#.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2023-12-13 09:50:19 -03:00
Hugo Villeneuve
2b9bcc2f47 imx8mn-var-som: add manufacturer to target description
Add Variscite manufacturer to the IMX8MN_VAR_SOM target menu label as
the majority of targets include the manufacturer as part of their menu
description/label and it helps when looking for a particular
manufacturer/board.

Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2023-12-13 09:49:51 -03:00
Sébastien Szymanski
97af4d69d2 arm: dts: imx93-evk: remove wrong eqos compatible string
The correct compatible string for i.MX93 variant of DWC EQoS MAC is now
"nxp,imx93-dwmac-eqos".

Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
2023-12-13 09:48:56 -03:00
Sébastien Szymanski
f935716935 net: phy: realtek: Add support for RTL8211F(D)(I)-VD-CG
Add support for the RTL8211F(D)(I)-VD-CG PHY present on the i.MX93 EVK
board.

Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
2023-12-13 09:48:38 -03:00
Sébastien Szymanski
d5eae216d8 net: dwc_eth_qos: Add board_interface_eth_init() for i.MX93
Add a common board_interface_eth_init() called by the DWC MAC driver to
setup the MAC <-> PHY interface according to the PHY mode obtained from
DT.
Remove the board-side configuration in the i.MX93 EVK files.

Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
2023-12-13 09:48:26 -03:00
Sébastien Szymanski
9e1f79bd69 net: dwc_eth_qos: add i.MX93 support
Add support for DWC EQoS MAC on i.MX93.

Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2023-12-13 09:48:03 -03:00
Ricardo Salveti
85053a1c14 ARM: imx8ulp: support env in fat and ext4
Change boot device logic to also allow environment stored in fat and
in ext4 when booting from SD or eMMC.

As the boot device check for SD and for eMMC was depending on
ENV_IS_IN_MMC being defined, change the ifdef blocks at
env_get_location to use IS_ENABLED instead for all modes, returning
NOWHERE when no valid mode is found.

Signed-off-by: Ricardo Salveti <ricardo@foundries.io>
Co-developed-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
2023-12-13 09:43:23 -03:00
Igor Opaniuk
9e9d92f823 imx: imx8: ahab: refactor do_ahab_close command
Move an OEM closing logic to ahab_close() function to be able to use
it directly without calling a u-boot command.

Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>
Co-developed-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
2023-12-13 09:42:14 -03:00
Marek Vasut
452e385b08 arm: mxs: Fix ICOLL macro name typo
The interrupt collector macro name for i.MX23 is MXS_ICOLL_BASE,
this is correct and matches the documentation of both i.MX23 and
i.MX28. Align the i.MX28 macro accordingly. No functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2023-12-13 09:40:52 -03:00
Cem Tenruh
3e0b196696 arm: dts: imx8mm-phyboard-polis-rdk: Sync dts files with kernel
Sync the devicetree files used in the kernel for the imx8mm-phyboard-polis
with the corresponding devicetree files in U-Boot.
Replaced phycore-imx8mm.dts with kernel dts imx8mm-phyboard-polis-rdk.dts

Synced with kernel 6.5.0-rc1 commit
e752a4f9589c (arm64: dts: freescale: imx8mm-phyboard: Add I2C4 pinmuxing)

Signed-off-by: Cem Tenruh <c.tenruh@phytec.de>
2023-12-13 09:39:19 -03:00
Fabio Estevam
c435538888 imx7d-sdb: Sync devicetree with kernel 6.5-rc1
Commit 0aea5dda29 ("ARM: dts: imx7d-sdb-u-boot: Fix usdhc1 UHS
operation") did a temporary workaround by addng the usdhc1 fix
inside the -u-boot.dtsi file.

The imx7d-sdb.dts from kernel 6.5-rc1 contains the proper UHS
fix, so sync the devicetree tree and remove the previous fix
from -u-boot.dtsi.

Also, adjust the PMIC node name inside pmic_get() to match
the devicetree update.

Signed-off-by: Fabio Estevam <festevam@denx.de>
2023-12-13 09:38:28 -03:00
Gilles Talis
994a51d9ac imx: imx8mp: Add support for Polyhex Debix Model A SBC
Add support for the Polyhex Debix Model A SBC board.
It is an industrial grade single board computer based on
NXP's i.MX 8M Plus.
Currently supported interfaces are:
- Serial console
- Micro SD
- eQOS and FEC Ethernet

imx8mp-debix-model-a.dts is taken from Linux 6.3.

Signed-off-by: Gilles Talis <gilles.talis@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-12-13 09:32:06 -03:00
Fabio Estevam
595b8be3af imx8qm_dmsse20a1: Improve SPL memory configuration
Currently, building imx8qm_dmsse20a1_defconfig leads to the following
warning:

aarch64-linux-ld.bfd: invalid origin for memory region .sdram

Fix it by using the same SPL memory layout as done in the imx8mq_evk.

Reported-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Fabio Estevam <festevam@denx.de>
Tested-by: Oliver Graute <oliver.graute@kococonnector.com>
2023-12-13 09:18:01 -03:00
Shawn Guo
b614ddb5d3 ddr: imx: Save the FW loading if it hasn't changed
Function ddr_load_train_firmware() is called 4 times in a loop by
ddr_cfg_phy(). The first 3 calls are all '1D' type and just loading the
same FWs.  Let's add a type check and save 2 of them.  This helps to
reduce DDRPHY training time from 269 ms down to 212 ms, and thus speed
up boot time ~ 50 ms.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2023-12-13 08:44:59 -03:00
Tanmay Shah
622db30860 dts: zynqmp: add missing destination mailbox compatible
The commit in linux kernel 81186dc16101 ("dt-bindings: zynqmp: add
destination mailbox compatible") make compatible string for child nodes
mandatory that's why add it.

Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
Link: https://lore.kernel.org/r/20231204215620.63334-5-tanmay.shah@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-12-13 08:58:07 +01:00
Tanmay Shah
babee72ff6 mailbox: zynqmp: support mulitple mboxes via device-tree
As of now only one mailbox agent is supported by mailbox driver.
On zynqmp platform there are about 7 mailbox agents which can communicate
over same IPI channel to U-Boot. This patch series introduces new
"zynqmp_ipi_dest" driver which adds one to multi-channel mailbox
support.

Following format in device-tree is expected as per latest bindings:
zynqmp-ipi {
	compatible = "xlnx,zynqmp-ipi-mailbox";

	mbox_1: mailbox@1 {
		/* New compatible for child node */
		compatible = "xlnx,zynqmp-ipi-dest-mailbox";
		...
	};

	...

	mbox_n: mailbox@n {
		compatible = "xlnx,zynqmp-ipi-dest-mailbox";
		...
	}
};

Then mailbox client uses child mailbox node as following:

ipi-dest-1 {
	...
	mboxes = <mbox_1 0>, <mbox_1 1>;
	mbox-names = "tx", "rx";
	...
};

New "zynqmp_ipi_dest" driver is for devices with
"xlnx,zynqmp-ipi-dest-mailbox" compatible string. This driver will take care
of mailbox send recv ops and it replaces previous "zynqmp_ipi" driver.
Now "zynqmp_ipi" driver simply binds each child device with "zynqmp_ipi_dest"
driver.

However, its important to maintain backward comaptibility with previous
bindings where child node does not have compatible string. In such case, new
driver isn't probed by U-Boot during boot and system fails to boot. To
resolve this issue firmware-zynqmp.c driver probes all the IPI parent node
driver which binds each child node device with "zynqmp_ipi_dest" driver.

This makes sure corresponding child driver will be
probed when requested using mbox_get_by_name or mbox_get_by_idx
framework calls.

This way multiple mailbox agents are supported in device-tree without breaking
previous binding support.

Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
Link: https://lore.kernel.org/r/20231204215620.63334-4-tanmay.shah@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-12-13 08:58:07 +01:00
Tanmay Shah
e2c3e9c2b1 mailbox: add el3 support only for zynqmp platform
If U-Boot is running in Exception Level 3 then use hardcode
register values for mailbox message passing with PMU.
This is only supported for zynqmp platform.

Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
Link: https://lore.kernel.org/r/20231204215620.63334-3-tanmay.shah@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-12-13 08:58:07 +01:00
Tanmay Shah
cfb41b011d mailbox: zynqmp: support smc calls to TF-A
Use SMC calls to TF-A to operate IPI for execution level below 3. For
EL3 use hardcode IPI registers as TF-A isn't available in EL3.
Hence, in EL3 remote and local IPI ids retrieved using xlnx,ipi-id
property are unused.

Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
Link: https://lore.kernel.org/r/20231204215620.63334-2-tanmay.shah@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-12-13 08:58:07 +01:00
Michal Simek
0e54b473f2 ARM: zynq: Remove deprecated device_type property
Based on DT specification device_type property is deprecated and should be
used only for cpu and memory nodes. That's why remove other usage. In this
case ethernet-phy.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/70201ca4ad49ace6f7c27015af9df58a335d2a1f.1700831800.git.michal.simek@amd.com
2023-12-13 08:58:07 +01:00
Michal Simek
2c8a09219c arm64: zynqmp: Add multiboot support for SPL/SPI offset calculation
In case of A/B update systems there should be an option to load the same
binary/binaries to different location and they should work.
Before this patch boot.bin with U-Boot SPL can be added to whatever 32k
offset in SPI and SPL finds u-boot.itb at CONFIG_SYS_SPI_U_BOOT_OFFS
offset. In case of A/B update systems that means that SPL is at different
locations but it still points to the same u-boot.itb which is not correct.
That's why include multiboot value to offset calculation to be able to
point to image from the same base.
It doesn't affect any current system which starts from 0 offset.

This patch also change Kria defconfig which uses A/B setup. Partition
A starts at multiboot 64, partition B at multiboot 496.

And also print message about used SPI offset which is useful for all cases.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/93903a53ad9358ae69991558b787f574797effbe.1699619666.git.michal.simek@amd.com
2023-12-13 08:58:06 +01:00
Mayuresh Chitale
218539e2e7 drivers: xilinx_spi: Probe fifo_depth at runtime
If the fifo-size DT parameter is not provided then probe the
controller's fifo depth at runtime. This is ported from a patch
in the Linux Xilinx SPI driver.

Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/1422029330-10971-5-git-send-email-ricardo.ribalda@gmail.com
Tested-by: Love Kumar <love.kumar@amd.com>
Link: https://lore.kernel.org/r/20231116164336.140171-4-mchitale@ventanamicro.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-12-13 08:58:06 +01:00
Mayuresh Chitale
954d437d26 drivers: xilinx_spi: Add xfer callback
Add the xfer callback which is used by the MMC_SPI driver and generally by
the dm_spi_xfer callback.

Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Tested-by: Love Kumar <love.kumar@amd.com>
Link: https://lore.kernel.org/r/20231116164336.140171-3-mchitale@ventanamicro.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-12-13 08:58:06 +01:00
Mayuresh Chitale
4c18d9f6d0 drivers: xilinx_spi: Use udevice in start_tranfer
Modify start_transfer and related functions to take a udevice parameter
as input instead of spi_slave. This is needed so that start_transfer can
be used directly via the xfer callback. Also fix a compiler warning.

Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Tested-by: Love Kumar <love.kumar@amd.com>
Link: https://lore.kernel.org/r/20231116164336.140171-2-mchitale@ventanamicro.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-12-13 08:58:06 +01:00
Michal Simek
a6955800bf xilinx: zynq: Enable capsule update for Antminer S9
Capsule update helps with easier firmware development that's why enable it
by default to be able to update system without replugging SD card again and
again.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/8f8deb5f46c0f2d4b687b626f4de221873133856.1699866313.git.michal.simek@amd.com
2023-12-13 08:58:06 +01:00
Michal Simek
1cd876bdac xilinx: zynq: Generate dfu for SPI only when enabled
Bitmain S9 board is not enabling SPI that's why CONFIG_SYS_SPI_U_BOOT_OFFS
symbol is not present which ends in build failure when EFI/DFU
infrastructure is enabled.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/3ea0572dbda8f21270c00a77528eb6ec954c7c40.1699866313.git.michal.simek@amd.com
2023-12-13 08:58:06 +01:00
Mayuresh Chitale
a62b01ded1 pci: xilinx: Enable MMIO region
The host bridge MMIO region is disabled by default due to which MMIO
accesses cause an exception. Fix it by setting the bridge enable bit.
This change is ported from the linux pcie-xilinx driver.

Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20231116165103.140968-3-mchitale@ventanamicro.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-12-13 08:58:06 +01:00
Mayuresh Chitale
891b481480 pci: xilinx: Fix "reg" not found error
Fix the driver to use the dev_read_addr_size API to fetch the reg
property from the DT.

Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Link: https://lore.kernel.org/r/20231116165103.140968-2-mchitale@ventanamicro.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-12-13 08:58:06 +01:00
Mayuresh Chitale
3c6b1fdade net: axi_emac: Use reg property for DMA registers
As per the xlnx,axi-ethernet-1.00.a DT documentation in linux, the AXI
DMA registers can be obtained via the reg property or via a separate
node for the axistream DMA controller. Currently only the latter is
supported, so add support to fetch the DMA controller registers from the
"reg" property.

Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20231116164024.139934-1-mchitale@ventanamicro.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-12-13 08:58:06 +01:00
Michal Simek
c7c82cbe2d arm64: zynqmp: Remove description for 8T49N240
8T49N240 driver was never upstreamed by IDT and there is no user of this
driver that's why remove description for this chip with also remove this
driver.

Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/52aec21f121713160d5953b0a41a10cb196482b3.1699428990.git.michal.simek@amd.com
2023-12-13 08:58:06 +01:00
Michal Simek
4ff083f09b arm64: zynqmp: Do not expose usbhub nodes
Upstream dwc3 U-Boot driver is not able to handle child nodes properly
that's why comment them in DT for now. This patch should be reverted when
dwc3 driver handles it properly.
DT node itself is aligned with dt schema.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/537c91a7ac0843358c4e33aa10d9e035d8e92faf.1699286139.git.michal.simek@amd.com
2023-12-13 08:58:06 +01:00
Venkatesh Yadav Abbarapu
dd4a822016 arm64: zynqmp: Introduce kria SOM defconfig
Enable the initial kria SOM specific configurations like pinctrl,
pinconf etc. Also add the environment file.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20231109042407.6123-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-12-13 08:58:06 +01:00
Marek Vasut
be4a5f7c35 test: bdinfo: Handle systems without getopt
Systems without getopt support fall back to plain full bdinfo print,
handle such a case, which occurs e.g. with sandbox_flattree_defconfig .

Fixes: 8827a38714 ("test: bdinfo: Test bdinfo -h")
Fixes: 2696f3ab81 ("test: bdinfo: Test bdinfo -m")
Fixes: 3ff2d796a6 ("test: bdinfo: Test bdinfo -e")
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-12-10 10:08:30 -05:00
Tom Rini
3a2b6ba5cf test/py: Disable error E0611 in two cases for pylint
Recently pylint has started to complain about:
No name 'fs_helper' in module 'tests' (no-name-in-module)

Due to:
from tests import fs_helper

However, we have:
test/py/tests/fs_helper.py

And since we do not want to add a dummy test/py/tests/__init__.py to
silence this warning we instead just disable it as needed.

Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-12-09 15:59:13 -05:00
Tom Rini
e54987d6af Merge patch series "cmd: bdinfo: Optionally use getopt and implement bdinfo -a"
Clean up our bdinfo command a bit and introduce "bdinfo -a"
2023-12-09 08:42:49 -05:00
Marek Vasut
3ff2d796a6 test: bdinfo: Test bdinfo -e
The bdinfo -e should print only the board ethernet settings.
Test the expected output.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-12-09 08:42:29 -05:00
Marek Vasut
2696f3ab81 test: bdinfo: Test bdinfo -m
The bdinfo -m should print only the board memory layout.
Test the expected output.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-12-09 08:42:29 -05:00
Marek Vasut
8827a38714 test: bdinfo: Test bdinfo -h
The bdinfo -h should print error message that -h is an unknown
parameter and then command help text. Test the expected output.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-12-09 08:42:29 -05:00
Marek Vasut
4823b05f01 test: bdinfo: Test both bdinfo and bdinfo -a
Factor out the core of test for all bdinfo output into bdinfo_test_all()
and then reuse it to verify that both 'bdinfo' and 'bdinfo -a' print all
the bdinfo output.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-12-09 08:42:29 -05:00
Marek Vasut
5bd32a96ad test: bdinfo: Rename bdinfo_test_move() to bdinfo_test_full()
Rename bdinfo_test_move() to bdinfo_test_full(). The former is a
remnant of deriving this test from another test. No functional
change.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-12-09 08:42:29 -05:00
Marek Vasut
3e4225aa91 configs: sandbox: Enable GETOPT for sandbox and sandbox64 target
Enable GETOPT so that 'bdinfo' command with getopt() support can be
tested in CI.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-12-09 08:42:29 -05:00
Marek Vasut
ea9637c92f cmd: bdinfo: Implement support for printing ethernet settings via bdinfo -e
Add support for printing ethernet settings only via 'bdinfo -e' .

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-12-09 08:42:29 -05:00
Marek Vasut
f1774a8030 cmd: bdinfo: Implement support for printing memory layout via bdinfo -m
Add support for printing memory layout only via 'bdinfo -m' .

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-12-09 08:42:29 -05:00
Marek Vasut
b6a90ac090 cmd: bdinfo: Optionally use getopt and implement bdinfo -a
Add optional support for getopt() and in case this is enabled via
GETOPT configuration option, implement support for 'bdinfo -a'.
The 'bdinfo -a' behaves exactly like bdinfo and prints 'all' the
bdinfo information. This is implemented in preparation for other
more fine-grained options.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-12-09 08:42:29 -05:00
Jim Liu
b2906f5b61 mtd: spi-nor: add flash model w25q01/02 support
add flash w25q01jv, w25q01jvfim and w25q02jv support

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2023-12-09 16:44:24 +05:30
Udit Kumar
c77efca283 spi: cadence_qspi: Select flash subnode at runtime
Currently spi driver gets flash parameter from first subnode.

Few boards have more than one flash with different parameters
and selection of flash is done by on board switch settings.
In such case, uboot needs to be recompiled with updated
device tree to align with board switch settings.

This patch allows to select flash node at runtime.

Boards those are supporting multiple flashes
needs to implement cadence_qspi_get_subnode function and return correct
flash node.

Cc: Apurva Nandan <a-nandan@ti.com>
Signed-off-by: Udit Kumar <u-kumar1@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2023-12-09 16:43:00 +05:30
Godfrey Mwangi
a08f7de39d mtd: spi-nor: Add MT25QU128AB params
Add Micron MT25QU128AB flash.

Signed-off-by: Godfrey Mwangi <godmwan@microsoft.com>
[jagan: fix the commit head]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2023-12-09 16:40:48 +05:30
Jit Loon Lim
bf41cb3d30 mtd: spi-nor: Add MT25U01G part number for SPI NOR Flash
MT25QU01 OPN with 4B OPCODE support is currently not supported in
source code and the driver reuses the definition for "n25q00a"
which has the same silicon ID but is a slower part.

Adding mt25u01g definition to the source code to support a faster
read response for MT25QU01 QSPI NOR Flash device.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
[jagan: fix the id position and commit head]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2023-12-09 16:39:03 +05:30
Teik Heng Chong
77f3b5e4ad drivers: mtd: spi: Add support for GD55LB02GEBIR SPI NOR flash
Add Support for GigaDevice GD55LB02GEBIR SPI NOR flash as QSPI
configuration flash

Signed-off-by: Teik Heng Chong <teik.heng.chong@intel.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2023-12-09 16:36:16 +05:30
Jonas Karlman
791e2bf9a8 mtd: spi-nor: Add support for Silicon Kaiser sk25lp128
Add support for Silicon Kaiser sk25lp128 SPI NOR flash found in Pine64
PinePhone Pro and PineTab2.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
2023-12-06 18:04:46 +05:30
William Zhang
672c97b646 spi: bcm63xx-hsspi: Fix compiler warning
When build for arm64 target, comipler reports the following warning:
drivers/spi/bcm63xx_hsspi.c: In function ‘bcm63xx_hsspi_xfer_dummy_cs’:
include/linux/kernel.h:184:17: warning: comparison of distinct pointer
types lacks a cast
  184 |  (void) (&_min1 == &_min2);  \
      |                 ^~
drivers/spi/bcm63xx_hsspi.c:298:22: note: in expansion of macro ‘min’
  298 |   size_t curr_step = min(step_size, data_bytes);

This change fix this warning by casting the data_bytes to size_t.

Fixes: 0e144ec38c ("spi: bcm63xx-hsspi: Add prepend mode support")
Signed-off-by: William Zhang <william.zhang@broadcom.com>
2023-12-06 18:00:50 +05:30
Tom Rini
d379150621 Merge tag 'v2024.01-rc4' into next
Prepare v2024.01-rc4

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# gpg: Signature made Mon 04 Dec 2023 01:47:24 PM EST
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2023-12-04 21:39:57 -05:00
Tom Rini
4a363dd516 Merge branch 'staging' of https://source.denx.de/u-boot/custodians/u-boot-tegra into next
Device tree improvents for Paz00 and DM PMIC convertion of recently
merged Tegra boards.
2023-11-30 09:33:31 -05:00
Tom Rini
6357cf0cc4 Merge branch '2023-11-29-assorted-platform-updates' into next
- Add a TFTP put test, a few TI Keystone 2 updates, fix stack-protector
  for PowerPC, fixes in lib/slre, timer-uclass and pvblock.
2023-11-29 11:16:13 -05:00
Andrew Davis
53a2300012 ARM: keystone2: Remove unneeded inclusions of common.h
Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-11-29 09:32:15 -05:00
Andrew Davis
cef52c9cb2 configs: keystone2: Do not include hardware.h
This is a hacky way to have this file included in all source files that
include common.h, instead just include from the files that need it.

Signed-off-by: Andrew Davis <afd@ti.com>
2023-11-29 09:32:15 -05:00
Andrew Davis
83ad745cb9 configs: keystone2: Remove unused SPL_MALLOC_F_SIZE and KEYSTONE_SPL_STACK_SIZE
These are leftover definitions. While here cleanup some leftover comments.

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-11-29 09:32:15 -05:00
Christophe Leroy
4072572b0f Fix stack-protector for powerpc
On powerpc, stack protector expects a function called
__stack_chk_fail_local() instead of __stack_chk_fail()

And some versions of GCC for powerpc default to TLS canary
instead of global canary, so always force GCC to use global
canary with -mstack-protector-guard=global

Cc: Joel Peshkin <joel.peshkin@broadcom.com>
Fixes: 4e9bce1243 ("Add support for stack-protector")
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
2023-11-29 09:32:15 -05:00
AKASHI Takahiro
654580eee1 xen: pvblock: fix the maximum io size in one operation
The current implementation may cause BUG_ON() in blkfront_aio()
	BUG_ON(n > BLKIF_MAX_SEGMENTS_PER_REQUEST);

In pvblock_iop(), a read/write operation will be split into smaller
chunks of data so that the size in one access (aio_nbytes) is limited
to, at the maximum,
	BLKIF_MAX_SEGMENTS_PER_REQUEST * PAGE_SIZE

But this works only if when the *buffer* passed in to pvblock_io()
is page-aligned. If not, the given data region may stand across
(BLKIF_MAX_SEGMENTS_PER_REQUEST + 1) pages. See the logic in
blkfront_aio():
	start = (uintptr_t)aiocbp->aio_buf & PAGE_MASK;
	end = ((uintptr_t)aiocbp->aio_buf + aiocbp->aio_nbytes +
	       PAGE_SIZE - 1) & PAGE_MASK;
Then this will lead to BUG_ON() above.

This can be fixed by decreasing the maximum size of aio_nbytes.

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Fixes: commit 3a739cc6c9 ("xen: pvblock: Implement front-back protocol and do IO")
2023-11-29 09:32:15 -05:00
Alex Bee
d6d8078cb3 timer-uclass: Always use "clock-frequency" property as fallback
Currently the "clock-frequency" DT property is only being considered as an
fallback if either there is no clock driver, the clock driver implements
the request-op correctly or there is no clock defined for the timer at all.

This patch makes "clock-frequency" also being picked as a fallback if
getting the clock-rate fails, since clk_get(_by_index) will return no
error, if a clock driver does not implement the request-op and does also
not support getting the rate of the clock in question.
timer_post_probe will take care if the property does not exist in the DT or
is defined as 0.

Signed-off-by: Alex Bee <knaerzche@gmail.com>
2023-11-29 09:32:15 -05:00
Francois Berder
891b178c57 lib/slre: Fix memory leak if regex compilation fails
Signed-off-by: Francois Berder <fberder@outlook.fr>
2023-11-29 09:32:15 -05:00
Love Kumar
9f0588a1a9 test/py: net: Add a TFTP put test
Execute tftpput command for uploading files to a server and validate its
size & CRC32.

Signed-off-by: Love Kumar <love.kumar@amd.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-11-29 09:32:15 -05:00
Tom Rini
339d96822e Merge patch series "cmd: add scmi command"
To quote the author:

"Scmi" command will be re-introduced per Michal's request.
The functionality is the same as I put it in my patch set of adding
SCMI base protocol support, but made some tweak to make UT, "ut dm
scmi_cmd," more flexible and tolerable when enabling/disabling a specific
SCMI protocol for test purpose.

Each commit may have some change history inherited from the preceding
patch series.

Test
====
The patch series was tested on the following platforms:
* sandbox
2023-11-28 22:31:09 -05:00
AKASHI Takahiro
3d6fe58437 test: dm: add scmi command test
In this test, "scmi" command is tested against different sub-commands.
Please note that scmi command is for debug purpose and is not intended
in production system.

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
2023-11-28 22:31:03 -05:00
AKASHI Takahiro
23b159ed4a doc: cmd: add documentation for scmi
This is a help text for scmi command.

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
2023-11-28 22:31:03 -05:00
AKASHI Takahiro
8055f90bd0 cmd: add scmi command for SCMI firmware
This command, "scmi", may provide a command line interface to various SCMI
protocols. It supports at least initially SCMI base protocol and is
intended mainly for debug purpose.

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
2023-11-28 22:31:03 -05:00
AKASHI Takahiro
9c07c0a4fc firmware: scmi: support protocols on sandbox only if enabled
This change will be useful when we manually test SCMI on sandbox
by enabling/disabling a specific SCMI protocol.

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-11-28 22:31:03 -05:00
AKASHI Takahiro
63cd0dceea test: dm: skip scmi tests against disabled protocols
This is a precautionary change to make scmi tests workable whether or not
a specific protocol be enabled. If a given protocol is not configured,
we skip the test by returning -EAGAIN.

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-11-28 22:31:03 -05:00
Tom Rini
e2a9edc0ce Merge patch series "fs: fat: calculate FAT type based on cluster count"
To quote the author:

This series fixes an issue where the FAT type (FAT12, FAT16) is not
correctly detected, e.g. when the BPB field BS_FilSysType contains the
valid value "FAT     ".

This issue occures, for example, if a partition is formatted by
swupdate using its diskformat handler. swupdate uses the FAT library
from http://elm-chan.org/fsw/ff/ internally.

See https://groups.google.com/g/swupdate/c/7Yc3NupjXx8 for a
discussion in the swupdate mailing list.

Please refer to the commit messages for more details.

1. Added bootsector checks

Most tests from https://www.win.tue.nl/~aeb/linux/fs/fat/fat-2.html
are added in the commit 'fs: fat: add bootsector validity check'.
Only the tests VIII, IX and X are not implemented.

I also checked the Linux kernel code (v6.6) and did not find any
checks on 'vistart->fs_type'. This is the reason why is skipped them
here.

See section '2. Size comparisons' for the impact on the binary size.

2. Size comparisons

I executed bloat-o-meter from the Linux kernel for an arm64
target (config xilinx_zynqmp_mini_emmc0_defconfig):

Comparison of the binary spl/u-boot-spl between master (rev
e17d174773) and this patch
series (including the added validity checks of the boot sector):

add/remove: 0/0 grow/shrink: 1/1 up/down: 100/-12 (88)
Function                                     old     new   delta
read_bootsectandvi                           308     408    +100
fat_itr_root                                 444     432     -12
Total: Before=67977, After=68065, chg +0.13%

When compare the size of the binary spl/u-boot-spl between master this
series without the the validity checks of the boot sector:

add/remove: 0/0 grow/shrink: 0/2 up/down: 0/-24 (-24)
Function                                     old     new   delta
read_bootsectandvi                           308     296     -12
fat_itr_root                                 444     432     -12
Total: Before=67977, After=67953, chg -0.04%

So the size of the spl on this arm64 target increases by 88 bytes for
this series. When i remove the validity check the size decreases by 24 bytes.
2023-11-28 20:10:36 -05:00
Christian Taedcke
8154ac1613 test: fs: Add test to detect fat type
Ensure that a large FAT12 filesystem and a small FAT16 filesystem are
detected correctly.

Signed-off-by: Christian Taedcke <christian.taedcke@weidmueller.com>
2023-11-28 20:10:25 -05:00
Christian Taedcke
c667b26b26 test: Add size granularity parameter to mk_fs
Without this commit it is only possible to create filesystem images
with a size granularity of 1MB.
This commit adds the option to create file systems with different
sizes, e.g 8.5MB.

Signed-off-by: Christian Taedcke <christian.taedcke@weidmueller.com>
2023-11-28 20:10:25 -05:00
Christian Taedcke
1e85b66212 test: fs: Add fat12 to supported fs of some tests
The tests fs_ext, fs_mkdir and fs_unlink support fat12 without
modifications.
The fs_basic test uses a partition that is too large for fat12, so it
is omitted here.

Signed-off-by: Christian Taedcke <christian.taedcke@weidmueller.com>
2023-11-28 20:10:25 -05:00
Christian Taedcke
764b411824 test: Add support to create a fat12 fs
This enables to implement tests for fat12 filesystem.

Signed-off-by: Christian Taedcke <christian.taedcke@weidmueller.com>
2023-11-28 20:10:25 -05:00
Christian Taedcke
c489937a6f fs: fat: add bootsector validity check
The performed checks are similar to the checks performed by the Linux
kernel in the function fat_read_bpb() in the file fs/fat/inode.c.

Signed-off-by: Christian Taedcke <christian.taedcke@weidmueller.com>
2023-11-28 20:10:25 -05:00
Christian Taedcke
33daef49b0 fs: fat: simplify gotos from read_bootsectandvi
This simplifies the code a little bit.

Signed-off-by: Christian Taedcke <christian.taedcke@weidmueller.com>
2023-11-28 20:10:24 -05:00
Christian Taedcke
08f622a127 fs: fat: calculate FAT type based on cluster count
This fixes an issue where the FAT type (FAT12, FAT16) is not
correctly detected, e.g. when the BPB field BS_FilSysType contains the
valid value "FAT     ".

According to the FAT spec the field BS_FilSysType has only
informational character and does not determine the FAT type.

The logic of this code is based on the linux kernel implementation
from the file fs/fat/inode.c function fat_fill_super().

For details about FAT see http://elm-chan.org/docs/fat_e.html

Signed-off-by: Christian Taedcke <christian.taedcke@weidmueller.com>
2023-11-28 20:10:24 -05:00
Christian Taedcke
601d33f31a test: spl: Remove usage of FAT32_SIGN
FAT32_SIGN is removed in the following commits.

Signed-off-by: Christian Taedcke <christian.taedcke@weidmueller.com>
2023-11-28 20:10:24 -05:00
Christian Taedcke
24caa6964a fs: fat: use get_unaligned_le16 to convert u8[2] to u16
This reduces code duplications.

Signed-off-by: Christian Taedcke <christian.taedcke@weidmueller.com>
2023-11-28 20:10:24 -05:00
Tom Rini
38cc6cdeb1 Merge patch series "Import "string" I/O functions from Linux"
To quote the author:

This series imports generic versions of ioread_rep/iowrite_rep and
reads/writes from Linux. Some cleanup is done to make sure that all
platforms have proper defines for implemented functions and there are no
redefinitions.
2023-11-28 16:19:19 -05:00
Igor Prusov
89994d64ac musb-new: Remove implementation of io.h functions
Since {read,write}s{l, w, b}() functions are now supported in linux/io.h
there is no need to add custom implementation to driver.

Signed-off-by: Igor Prusov <ivprusov@salutedevices.com>
2023-11-28 16:19:06 -05:00
Igor Prusov
e515a2bb1a treewide: Include linux/io.h instead of asm-generic/io.h
Directly including asm-generic/io.h may break build because it will
cause redefenition of generic io macros if linux/io.h gets included
later, hence replace it with direct include of linux/io.h

Signed-off-by: Igor Prusov <ivprusov@salutedevices.com>
2023-11-28 16:19:06 -05:00
Igor Prusov
d26db04db1 spi: meson_spifc_a1: Switch to io{read,write}32_rep()
Use io{read,write}32_rep() functions to sync code with Linux version.

Signed-off-by: Igor Prusov <ivprusov@salutedevices.com>
2023-11-28 16:19:06 -05:00
Igor Prusov
fa34fbf9a1 asm-generic: Import functions from Linux
Currently {read,write}s{b,w,lq}() functions are available only on some
architectures, and there are no io{read,write}{8,16,32,64}_rep()
functions in u-boot. This patch adds generic versions that may be used
without arch-specific implementation.

Since some of added functions were already added locally in some files,
remove them to avoid redeclaration errors.

Signed-off-by: Igor Prusov <ivprusov@salutedevices.com>
2023-11-28 16:19:06 -05:00
Igor Prusov
02585ad9e5 xtensa: io.h: Add defines for ins/outs functions
Add defines for {in,out}s{b,w,l}() functions to make asm-generic/io.h
aware of them.

Signed-off-by: Igor Prusov <ivprusov@salutedevices.com>
2023-11-28 16:19:06 -05:00
Igor Prusov
0c39bbd8c9 powerpc: io.h: Add defines for __raw_{read, write} functions
Add defines for __raw_{read,write}{b,w,l}() functions to make
make asm-generic/io.h aware of them.

Signed-off-by: Igor Prusov <ivprusov@salutedevices.com>
2023-11-28 16:19:06 -05:00
Igor Prusov
4c6d92df07 nios2: io.h: Add defines for ins/outs functions
Add defines for {in,out}s{b,w,l}  functions to make asm-generic/io.h
aware of them.

Signed-off-by: Igor Prusov <ivprusov@salutedevices.com>
2023-11-28 16:19:06 -05:00
Igor Prusov
55baed4dbb riscv: io.h: Fix signatures of reads/writes functions
Change type of address parameter from int* to volatile void* for
{read,write}s{b,w,l}() functions and add const qualifier for reads. This
is done to keep function signatures in sync with asm-generic/io.h and
other platforms.

Signed-off-by: Igor Prusov <ivprusov@salutedevices.com>
2023-11-28 16:19:06 -05:00
Igor Prusov
7c107ef205 riscv: io.h: Add defines for reads/writes functions
Add defines for {read,write}s{b,w,l} functions to make asm-generic/io.h
aware of them.

Signed-off-by: Igor Prusov <ivprusov@salutedevices.com>
2023-11-28 16:19:06 -05:00
Igor Prusov
65778d1f3d mips: io.h: Add defines for read/write/in/out functions
Add defines for {read,write}{b,w,l,q}(), {read,write}s{b,w,l,q}() and
{in,out}s{b,w,l,q}() functions to make asm-generic/io.h aware of them.

Signed-off-by: Igor Prusov <ivprusov@salutedevices.com>
2023-11-28 16:19:06 -05:00
Igor Prusov
9539702219 mips: io.h: Add const to reads functions params
Currently reads{b,w,l}() functions don't have const qualifier for their
address parameter. Since asm-generic/io.h in Linux has const for all
read functions, add it here as well to keep signatures in sync.

Signed-off-by: Igor Prusov <ivprusov@salutedevices.com>
2023-11-28 16:19:06 -05:00
Igor Prusov
93e1552cb1 x86: Add defines for ins/outs functions
Add defines for {in,out}s{b,w,l}() functions to make sure that
they will be used by asm-generic/io.h

Signed-off-by: Igor Prusov <ivprusov@salutedevices.com>
2023-11-28 16:19:06 -05:00
Igor Prusov
4f7a3463c4 sandbox: move asm-generic include to the end of file
Generic version of io.h should be included at the end of
architecture-specific ones to make sure that arch implementations are
used and to avoid redefinitions.

Signed-off-by: Igor Prusov <ivprusov@salutedevices.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-11-28 16:19:06 -05:00
Tom Rini
66c21738fd Merge patch series "sysinfo: Expand sysinfo with some more banner information"
To quote the author:

The show_board_info() function was adjusted to weak so that it could be
entirely replaced with a board-specific implementation.

The intended way for boards to provide their own information is via a
sysinfo driver. But currently there is no way to show anything other
than the model name.

This series adds support for showing a few more items, in a way that is
easy for boards to extend.

Since there is already a weak checkboard() function, we don't need to
have two levels of weak function here. So this series drops the weak
attribute from show_board_info()

Existing boards will see a slight change in output, in that the model
name will appear first, before any custom output. If that is a problem,
then the solution is to implement a sysinfo driver for the board.
2023-11-28 12:53:14 -05:00
Simon Glass
e1302b3e30 x86: coreboot: Add a sysinfo driver
Create a sysinfo driver to avoid needing a custom checkboard()
function. With this the following information is printed when booting
from coreboot under QEMU:

   Model: Standard PC (i440FX + PIIX, 1996)
   Manufacturer: QEMU
   Prior-stage version: 4.21-885-g2a87ef1eca56
   Prior-stage date: 11/11/2023

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-11-28 12:53:04 -05:00
Simon Glass
6f646d13f4 sysinfo: Allow displaying more info on startup
At present only the model name is shown on start. Some boards want to
display more information. Add some more options to allow display of the
manufacturer as well as the version and date of any prior-stage
firmware.

This is useful for coreboot, at least. If other boards have more
information to display, it is easy to add it, now.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-11-28 12:53:04 -05:00
Simon Glass
d2a1b432a8 Revert "generic-board: make show_board_info a weak function"
We already have:

- a sysinfo driver-interface which can obtain the model
- a weak function called checkboard() for showing board info

The current implementation has a weak function on top of a weak
function. Now that all boards have been updated to use checkboard()
instead, drop the __weak on show_board_info()

This reverts commit f7637cc014.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-11-28 12:53:04 -05:00
Simon Glass
16e4b7818b udoo: Use checkboard() instead of show_board_info()
Boards can use a sysinfo driver if a particular model name is needed.
Update this board to use checkboard() directly, rather than having a
weak function laid on top of a weak function.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-11-28 12:53:04 -05:00
Simon Glass
edb0ecd187 toradex: Use checkboard() instead of show_board_info()
Boards can use a sysinfo driver if a particular model name is needed.
Update this board to use checkboard() directly, rather than having a
weak function laid on top of a weak function.

Make all the checkboard() functions call the new tdx_checkboard() so
that the same information is displayed.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-11-28 12:53:04 -05:00
Simon Glass
56720b2ce2 solidrun: Use checkboard() instead of show_board_info()
Boards can use a sysinfo driver if a particular model name is needed.
Update this board to use checkboard() directly, rather than having a
weak function laid on top of a weak function.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-11-28 12:53:03 -05:00
Simon Glass
8cd4bf7dc9 turris: Use checkboard() instead of show_board_info()
Boards can use a sysinfo driver if a particular model name is needed.
Update this board to use checkboard() directly, rather than having a
weak function laid on top of a weak function.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-11-28 12:53:03 -05:00
Simon Glass
53c4ef0e65 meson: Use checkboard() instead of show_board_info()
Boards can use a sysinfo driver if a particular model name is needed.
Update this board to use checkboard() directly, rather than having a
weak function laid on top of a weak function.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
2023-11-28 12:53:03 -05:00
Simon Glass
ef211ab252 board: Move show_board_info() comment to header file
Move this comment to its prototype and tidy it up a bit.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-11-28 12:53:03 -05:00
Svyatoslav Ryhel
e22d5799dc ARM: dts: tegra30: enable USB PHY node on some devices
Enable USB PHY nodes on ASUS Transformers, Grouper, Enadevoru
and LG X3. This is not mandatory since driver will use default
values but preferable for new devices.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2023-11-28 09:17:18 +02:00
Svyatoslav Ryhel
555b28dacd board: grouper: convert ASUS Google Nexus 7 (2012) to use DM PMIC
Since required drivers were merged, we can safely clean up the
board and switch to DM based driver with device tree support.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2023-11-28 09:16:55 +02:00
Svyatoslav Ryhel
8849951057 board: transformer-t30: convert ASUS Transformers to use DM PMIC
Since required drivers were merged, we can safely clean up the
board and switch to DM based driver with device tree support.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2023-11-28 09:16:26 +02:00
Svyatoslav Ryhel
441dea268b board: endeavoru: convert HTC One X to use DM PMIC
Since required drivers were merged, we can safely clean up the
board and switch to DM based driver with device tree support.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2023-11-28 09:15:50 +02:00
Svyatoslav Ryhel
459d6d9f1e board: lg-x3: convert LG Optimus 4X and Vu to use DM PMIC
Since required drivers were merged, we can safely clean up the
board and switch to DM based driver with device tree support.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2023-11-28 09:14:54 +02:00
Svyatoslav Ryhel
14f2e54975 ARM: tegra: call regulators_enable_boot_on on board init
Call regulators_enable_boot_on on board init to set all regulators
with boot-on property in device tree. If regulator is not used by
any device in the device tree but is essential for the device to
work a regression will occur.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2023-11-28 09:09:53 +02:00
Thierry Reding
9d3f7f881e ARM: dts: Reuse I2C3 for NVEC
Instead of duplicating the I2C3 node and adding NVEC specific
properties, reuse the I2C3 node, extend it with NVEC specific properties
and drop properties that are not needed by NVEC. This results in a DTB
that is a bit cleaner and avoids accidentally using I2C3 and NVEC which
would have them fight over the same hardware resources.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-11-28 09:00:20 +02:00
Tom Rini
d6e052c615 Merge patch series "ufs: Add a PCI UFS controller support"
To quote the author:

This adds a PCI UFS controller support and enables the support on
QEMU RISC-V for testing.

Requiring QEMU v8.2+.
2023-11-27 16:19:09 -05:00
Bin Meng
3555c92583 qemu: riscv: Enable UFS support
This enables UFS support for QEMU RISC-V 'virt' machine.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-11-27 16:18:59 -05:00
Bin Meng
5b2d25a2e3 ufs: Handle UFS 3.1 controllers
Extend the version check to handle UFS 3.1 controllers as well.
Tested on QEMU emulated UFS 3.1 controller.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-11-27 16:18:59 -05:00
Bin Meng
2ec7d657c0 ufs: Add a PCI based UFS controller driver
This adds a simple PCI based UFS controller driver with a QEMU
emulated UFS controller on the PCI bus.

Requiring QEMU v8.2+.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-11-27 16:18:59 -05:00
Bin Meng
e5c19ce47c ufs: Allow mmio registers on the PCI bus
Check if the UFS controller is on the PCI bus, and get its register
base address accordingly.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
2023-11-27 16:18:59 -05:00
Bin Meng
07a64f0a34 pci_ids: Add Red Hat vendor and device IDs
Red Hat, Inc. donates a part of its device ID range [1] to QEMU,
to be used for virtual devices. This commit adds several typical
devices that are useful in U-Boot.

[1] https://www.qemu.org/docs/master/specs/pci-ids.html

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-11-27 16:18:59 -05:00
Bin Meng
ba537e9b27 cmd: ufs: Correct the help text
Remove the additional space and use "sub-system" for consistency
with other commands like "scsi" and "usb".

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
2023-11-27 16:18:59 -05:00
Bin Meng
ff039a8704 cmd: kconfig: Make ufs prompt look similar to other commands
At present the 'ufs' command prompt does not look similar like other
commands. Update it.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
2023-11-27 16:18:59 -05:00
Bin Meng
1b3dab2d29 ufs: Add a line feed to the end of some dev_xxx() messages
Add a line feed to improve readability of some dev_xxx() messages.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-11-27 16:18:59 -05:00
Bin Meng
b2d01681ab ufs: Correct the UFS terminlogy
UFS stands for Universal Flash Storage, not Subsytem.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
2023-11-27 16:18:58 -05:00
Tom Rini
129d6a0d87 Merge tag 'u-boot-dfu-next-20231124' of https://source.denx.de/u-boot/custodians/u-boot-dfu into next
u-boot-dfu-next-20231124

- Make dfu entity name size configurable in KConfig
- Implement start-stop for UMS (graceful shutdown via eject)
- Improve help messages for cmd/bind
- Improve help message for udc bind failures
2023-11-25 12:34:23 -05:00
Tom Rini
1682d97db9 Merge branch '2023-11-25-assorted-platform-updates' into next
- Updates for the Siemens AM335x platforms, Nuvoton platforms, and
  disable CONFIG_NET on platforms that lack NETDEVICES, so that
  NETDEVICES can be implied by NET.
2023-11-25 12:32:48 -05:00
Tom Rini
f4449038f6 net: Make NET imply NETDEVICES
Normally, when NET is enabled, CMD_NET will then be enabled and in turn
NETDEVICES will (likely) be enabled via imply. However, if we disable
CMDLINE in a defconfig we now no longer get CMD_NET enabling NETDEVICES
for us. This suggestion (as an imply is) really isn't about the network
commands but network itself and is a legacy of how intertwined
NET/CMD_NET were historically. Move this over to the NET entry instead
where it is a more logical fit.

Reported-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2023-11-22 19:53:39 -05:00
Tom Rini
6df4e7b50a boards: Disable NET on platforms without NETDEVICES
None of these platforms enabled a networking devices, and disabled
CMD_NET. Given that we used to gate network support on CMD_NET rather
than NET, we disable CONFIG_NET on these platforms now.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-11-22 19:53:39 -05:00
Jim Liu
5a2070783d board: nuvoton: update console environment variable
If CONFIG_SYS_SKIP_UART_INIT is enabled, calculate the
current baud rate and update the "console" environment
variable.

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2023-11-22 19:11:27 -05:00
Jim Liu
65660bfe85 serial: npcm: support skip uart clock setting
Skip the uart clock setting if CONFIG_SYS_SKIP_UART_INIT is enabled.
Fix divisor error.

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2023-11-22 19:10:04 -05:00
Jim Liu
1504813eb8 configs: arbel: Enable full functions
Enable more functions/commands for arbel evb.

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2023-11-22 19:10:04 -05:00
Jim Liu
438d253943 arm: dts: npcm845-evb: fix/add node and aliases
Modify spi and usb aliases name.
Add dt-binding for usb phy define and fix usb phy reset error.
Add tpm/otpee and host_intf node.

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2023-11-22 19:10:04 -05:00
Enrico Leto
437fa09673 configs: draco: restore clock driver
Fix 'failed to get fck clock' error on boot. Add missing configs.

Signed-off-by: Enrico Leto <enrico.leto@siemens.com>
2023-11-22 19:10:04 -05:00
Enrico Leto
ba0d6a284a configs: draco: disable misc init
The initcall sequence fails at arch_misc_init. Disable misc init until
driver model and DT are clean.

Signed-off-by: Enrico Leto <enrico.leto@siemens.com>
2023-11-22 19:10:04 -05:00
Enrico Leto
3328e6ec77 configs: draco: remove unused resources from spl
We don't need device tree, GPIO & SPI in SPL.

Signed-off-by: Enrico Leto <enrico.leto@siemens.com>
2023-11-22 19:10:04 -05:00
Enrico Leto
f01e947c4a configs: thuban, rastaban: remove emmc
These targets use NAND FLASH only. Maybe some MMC definitions were added by
trying MMC for the etamin target evaluation and were not removed.

Signed-off-by: Enrico Leto <enrico.leto@siemens.com>
2023-11-22 19:10:04 -05:00
Enrico Leto
6fd75b7d19 configs: draco: remove spi flash support
The SPI FLASH was set in the early development phase for evaluations.
Any target use it anymore.

Signed-off-by: Enrico Leto <enrico.leto@siemens.com>
2023-11-22 19:10:04 -05:00
Enrico Leto
1c73e05b03 siemens,am335x: clean-up draco targets
Draco is a family of 3 boards: thuban, rastaban & etamin. Rename all
targets of the family adding the draco- prefix to increase readibility
and simplify future commits about concerning all boards of the family.

The name draco was initially used for the first target. It's deprecated
since a 2nd target was introduced. Unfortunately the draco target was
copied to the thuban target instead to be renamed. Remove it to save
unnecessary maintenance effort.

Signed-off-by: Enrico Leto <enrico.leto@siemens.com>
2023-11-22 19:10:03 -05:00
Tom Rini
054222eb68 Merge branch '2023-11-22-TI-K3-cleanups' into next
This brings in a large number of cleanups and reorganizations to the TI
K3 family of SoCs. We get DTS resyncs for most of the SoCs under that
umbrella as well, and a few enhancements too.
2023-11-22 14:05:53 -05:00
Manorit Chawdhry
2fadd62fe6 arm: dts: k3-am68*: Sync with kernel v6.7-rc1
Sync devicetree with kernel v6.7-rc1

Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-11-22 13:48:20 -05:00
Manorit Chawdhry
7e7d2bfb2c arm: dts: k3-j721s2*: Sync with kernel v6.7-rc1
Sync devicetree with kernel v6.7-rc1

Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-11-22 13:48:20 -05:00
Neha Malcom Francis
4509b9ff0b arm: dts: k3-*-binman: Move to using templated FITs
Reduce redundancy in code by using templates to generate the A72 boot
binaries (tispl.bin and u-boot.img) as well as R5 boot binary sysfw.itb
(for legacy boot following devices J721E and AM65x).

Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Acked-by: Andrew Davis <afd@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-11-22 13:48:20 -05:00
Neha Malcom Francis
b153bad0f1 arm: dts: k3-binman: Add support for FIT templates
Add templates for FIT images used extensively across K3 boards with most
of the code common. This includes the FIT portions of:
	- tispl.bin
	- u-boot.img
	- sysfw.itb (in case of legacy boot flow)

Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-11-22 13:48:20 -05:00
Nishanth Menon
b1c7fa0bf0 arm: dts: k3-am625-sk-r5/u-boot: Drop duplicate bootph-nodes
Kernel dts import now provides bootph-all and bootph-pre-ram properties
for the properties we have been overriding so far. Drop the same.

While at this enable the DM and TIFS UARTs for programming pinmux
since they are marked reserved by board.dts

Reviewed-by: Dhruva Gole <d-gole@ti.com>
Tested-by: Dhruva Gole <d-gole@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2023-11-22 13:48:20 -05:00
Nishanth Menon
ab9d07b181 arm: dts: k3-am625-beagleplay-u-boot: drop duplicate bootph-nodes
Kernel dts import now provides bootph-all and bootph-pre-ram properties
for the properties we have been overriding so far. Drop the same.

Reviewed-by: Dhruva Gole <d-gole@ti.com>
Tested-by: Dhruva Gole <d-gole@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2023-11-22 13:48:20 -05:00
Joao Paulo Goncalves
52a86e69e2 arm: k3: Enable instruction cache for main domain SPL
Change spl_enable_dcache so it also enable icache on SPL
initialization for the main domain part of the boot flow. This
improves bootloader booting time.

Link: https://lore.kernel.org/all/20231109140958.1093235-1-joao.goncalves@toradex.com/
Signed-off-by: Joao Paulo Goncalves <joao.goncalves@toradex.com>
Tested-by: Nishanth Menon <nm@ti.com>
2023-11-22 13:47:39 -05:00
Nishanth Menon
1146dc0854 arm: dts: k3-am625: Drop SoC provided bootph params from board u-boot/r5 dtsi
k3-am62* SoC dtsi files now provide the following:

bootph-all: dmss secure_proxy_main dmsc k3_pds k3_clks k3_reset
   main_pmx0 main_timer0 mcu_pmx0 wkup_conf chipid

bootph-pre-ram: secure_proxy_sa3 main_esm mcu_esm

Drop these from board r5 and u-boot.dtsi files as these are duplicate in
them now.

Acked-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Tested-by: Dhruva Gole <d-gole@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2023-11-22 13:47:39 -05:00
Jai Luthra
7fea353686 doc: board: ti: Add AM62A documentation
Add generic boot-flow diagrams, and SoC-specific info around build
steps.

Signed-off-by: Jai Luthra <j-luthra@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2023-11-22 13:47:39 -05:00
Nishanth Menon
a0ca5f24c8 arm: dts: k3-am625*: Sync with kernel v6.7-rc1
Sync with kernel v6.7-rc1 and sync up the u-boot dts files accordingly.

Tested-by: Dhruva Gole <d-gole@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2023-11-22 13:47:39 -05:00
Roger Quadros
0fc6f663ea arm: dts: k3-am625-verdin-wifi-dev-u-boot.dtsi: Fix DMA with BCDMA
BCDMA can be used at SPL for OSPI boot and mem-to-mem DMA
so add "bootph-all" to BCDMA node.

Suggested-by: Nishanth Menon <nm@ti.com>
Fixes: 9a3f2b6798 ("arm: dts: k3-am625-verdin-wifi-dev-u-boot.dtsi: Fix DMA/Ethernet")
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Nishanth Menon <nm@ti.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2023-11-22 13:47:39 -05:00
Reid Tonking
910bcb76f6 arm: dts: k3-j7200: Sync with Linux 6.7-rc1
Sync u-boot device tree with Linux kernel 6.7-rc1

Signed-off-by: Reid Tonking <reidt@ti.com>
2023-11-22 13:47:39 -05:00
Nishanth Menon
cff2a172ef configs: am62ax_evm_a53_defconfig: switch to stdboot
Switch over to stdboot

Signed-off-by: Nishanth Menon <nm@ti.com>
2023-11-22 13:46:33 -05:00
Nishanth Menon
24a0806ee7 board: ti: am62ax: env: Set the boot_targets
Set the default boot_targets to map up SD card as priority followed by
emmc and so on.

Signed-off-by: Nishanth Menon <nm@ti.com>
2023-11-22 13:46:33 -05:00
Nishanth Menon
1fd40fa019 board: ti: am62ax: env: Use default findfdt
Use the default findfdt instead of local logic.

Signed-off-by: Nishanth Menon <nm@ti.com>
2023-11-22 13:46:33 -05:00
Nishanth Menon
46a6c116fa configs: am62ax_evm_a53_defconfig: Enable networking
Enable networking

Signed-off-by: Nishanth Menon <nm@ti.com>
2023-11-22 13:46:33 -05:00
Vignesh Raghavendra
70b450b56c dma: ti: k3-udma: Introduce DMA support for the am62ax
In preparation for enabling ethernet for the am62ax family of SoCs,
introduce the initial DMA channel settings for the am62ax

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
[bb@ti.com: expanded on commit message]
Signed-off-by: Bryan Brattlof <bb@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2023-11-22 13:46:33 -05:00
Nishanth Menon
5b70caa6a4 arm: dts: k3-am62a*: Sync with kernel v6.7-rc1
Sync with kernel v6.7-rc1 and sync up the u-boot dts files accordingly.

Signed-off-by: Nishanth Menon <nm@ti.com>
2023-11-22 13:46:33 -05:00
Nishanth Menon
6a331b8014 arm: mach-k3: am62a: Add main_timer0 id to the dev list
main_timer0 is used by u-boot as the tick-timer. Add it to the soc
devices list so it an be enabled via the k3 power controller.

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
2023-11-22 13:46:33 -05:00
Neha Malcom Francis
170ae49d81 arm: dts: k3-j721e-*: Sync with kernel v6.7-rc1
Sync the U-Boot DTS files with those of Kernel v6.7-rc1.

Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
2023-11-22 13:46:33 -05:00
Neha Malcom Francis
d11f9f36da dt-bindings: misc: Move esm-k3.txt to ti,j721e-esm.yaml
Move esm-k3.txt to ti,j721e-esm.yaml in line with the devicetree
documentation in kernel.

Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-11-22 13:46:33 -05:00
Nishanth Menon
ef8489a21d doc: board: beagle: Add BeagleBone AI-64 documentation
Add base documentation for BeagleBone AI-64.

Signed-off-by: Nishanth Menon <nm@ti.com>
2023-11-22 13:22:24 -05:00
Nishanth Menon
a5f6153b78 configs: Add j721e_beagleboneai64_* configs
Add basic support for mmc/emmc and networking support for BeagleBone
AI-64.

Signed-off-by: Nishanth Menon <nm@ti.com>
2023-11-22 13:22:24 -05:00
Nishanth Menon
429ac50fdd board: beagle: Add BeagleBone AI-64 support
Add base support for BeagleBone AI-64 board support.

Further information at  https://beagleboard.org/ai-64

Signed-off-by: Nishanth Menon <nm@ti.com>
2023-11-22 13:22:24 -05:00
Robert Nelson
7f78636667 arm: dts: Add k3-j721e-beagleboneai64
BeagleBoard.org BeagleBone AI-64 is an open source hardware single
board computer based on the Texas Instruments TDA4VM SoC featuring
dual-core 2.0GHz Arm Cortex-A72 processor, C7x+MMA and 2 C66x
floating-point VLIW DSPs, 3x dual ARM Cortex-R5 co-processors,
2x 6-core Programmable Real-Time Unit and Industrial Communication
SubSystem, PowerVR Rogue 8XE GE8430 3D GPU. The board features 4GB
DDR4, USB3.0 Type-C, 2x USB SS Type-A, miniDisplayPort, 2x 4-lane
CSI, DSI, 16GB eMMC flash, 1G Ethernet, M.2 E-key for WiFi/BT, and
BeagleBone expansion headers.

This board family can be indentified by the BBONEAI-64-B0 in the
at24 eeprom:

[aa 55 33 ee 01 37 00 10  2e 00 42 42 4f 4e 45 41 |.U3..7....BBONEA|]
[49 2d 36 34 2d 42 30 2d  00 00 42 30 30 30 37 38 |I-64-B0-..B00078|]

Baseline of the devicetree is from v6.6-rc1

https://beagleboard.org/ai-64
https://git.beagleboard.org/beagleboard/beaglebone-ai-64

Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2023-11-22 13:22:24 -05:00
Nishanth Menon
0218b20888 board: Move omap3 beagle under beagle vendor folder
Move the omap3 beagle to the beagle vendor folder representing
BeagleBoard.org platforms.

Suggested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2023-11-22 13:22:24 -05:00
Nishanth Menon
76997af6f4 doc: board: Move am62x_beagleplay to it's own vendor
Move BeaglePlay documentation to beagle as a board vendor and update
references accordingly.

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
2023-11-22 13:22:22 -05:00
Nishanth Menon
73e88a9010 board: Move beagleplay under beagle vendor folder
Move beagleplay support away from ti/am62x to it's own beagle vendor
folder.

This forms the starting point for new beagle platforms added under it's
own board vendor folder.

As part of this create all the associated files with a bare minimum
beagleplay.c file.

Suggested-by: Andrew Davis <afd@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
[trini: Update k3-binman.dtsi to use full path to scheme.yaml now]
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-11-22 13:22:01 -05:00
Nishanth Menon
2969ed31b8 configs: Add am62x_beagleplay_*_defconfig
Add am62x_beagleplay_* defconfig customized for the configuration of
BeaglePlay and drop the config fragments.

This is in preparation for dropping the dependency on ti vendor folder
entirely.

Signed-off-by: Nishanth Menon <nm@ti.com>
2023-11-22 12:04:14 -05:00
Nishanth Menon
b25c2d7127 arm: dts: k3-am625-beagleplay-u-boot/r5: Just depend on k3-binman.dtsi
With the upcoming folder separation, there is no further need to depend
on am625-binman.dtsi. Duplicate the existing definitions to u-boot.dtsi
and r5.dts as appropriate.

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
2023-11-22 12:04:14 -05:00
Nishanth Menon
d35dcc686a doc: board: ti: j721e_evm: Use board relative path for include directives
When using include directives within a section that is included by non
TI board rst file, k3.rst and other include paths need to be relative to
doc/board/ base.

Signed-off-by: Nishanth Menon <nm@ti.com>
2023-11-22 12:04:14 -05:00
Nishanth Menon
868b6c7e42 configs: j7200_evm_a72_defconfig: Switch to bootstd
Switch to using bootstd. Note with this change, we will stop using
distro_bootcmd and instead depend entirely on bootflow method of
starting the system up.

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
2023-11-22 12:04:14 -05:00
Nishanth Menon
53ffd00780 configs: j7200: Remove HBMC_AM654 config
Kernel commit 1b77265626a4 ("arm64: dts: ti: k3-j7200-mcu-wakeup: Add
HyperBus node") was merged to kernel without its dependent patch [1].
Similar fix is needed in U-Boot, and hbmc currently breaks boot. Till
this gets fixed in U-Boot, disable the config by default so that the
hbmc probe that happens in board/ti/j721e/evm.c will not take place
and lead to boot failure.

This is similar to the approach in commit 5b2671594b ("configs:
j721e: Remove HBMC_AM654 config"), introduced to j7200 evm platform.

[1] https://lore.kernel.org/all/20230424184810.29453-1-afd@ti.com/

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
2023-11-22 12:04:14 -05:00
Nishanth Menon
c36377d09e arm: mach-k3: j721e: Improve support for UDA FS
Commit 5019170970 ("arch: arm: mach-k3: j721e: add support for UDA
FS") introduced basic UDA FS support, however, we can Take approach
similar to commit 0f1c1e8b36 ("arm: mach-k3: am625: Add support for
UDA FS"). While boot partition support with EMMC boot is useful, it is
constrained by the size of boot hardware partition itself.

In the case of K3 devices, tispl images can contain OP-TEE images that
can substantially vary in size and the u-boot image itself can vary over
time as we enable various features.

So use the CSD information in the case of EMMC_BOOT configuration being
enabled to pick boot partition or UDA FS mode operation to pick.

If EMMC_BOOT is disabled, then depend on filesystem configuration to
pick data from UDA.

Signed-off-by: Nishanth Menon <nm@ti.com>
2023-11-22 12:04:14 -05:00
Nishanth Menon
fdb7d45c76 arm: mach-k3: arm64-mmu: Refactor to be independent of board
Refactor J721E J7200 definition to make this independent of board
macros.

Signed-off-by: Nishanth Menon <nm@ti.com>
2023-11-22 12:04:14 -05:00
Nishanth Menon
3c11584c21 board: ti: j721e: Select SOC_K3_J721E_J7200 for J7200evm
Enable SOC_K3_J721E_J7200 when board is J7200 EVM - this allows us to
differentiate J7200 platform cleanly in board independent codebase.

Signed-off-by: Nishanth Menon <nm@ti.com>
2023-11-22 12:04:14 -05:00
Nishanth Menon
97bf082c9f arm: mach-k3: Kconfig: Introduce a symbol to indicate J7200
J7200 shares quite a few characteristics with J721E. However a few sets
are different. Introduce a Kconfig to differentiate the two to allow for
new boards to be introduced in a seamless manner.

Signed-off-by: Nishanth Menon <nm@ti.com>
2023-11-22 12:04:14 -05:00
Nishanth Menon
7b15bf75fe configs: j721e_evm_a72_defconfig: Switch to bootstd
Switch to using bootstd. Note with this change, we will stop using
distro_bootcmd and instead depend entirely on bootflow method of
starting the system up.

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
2023-11-22 12:04:14 -05:00
Nishanth Menon
437765b364 board: ti: j721e: j721e.env: Add explicit boot_targets
Add explicit boot_targets to indicate the specific boot sequence to
follow.

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
2023-11-22 12:04:14 -05:00
Nishanth Menon
21a704a8bf board: ti: j721e: evm: Switch to using IS_ENABLED
Switch to using IS_ENABLED() for inline function usage.

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
2023-11-22 12:04:14 -05:00
Nishanth Menon
d672e15aa8 board: ti: j721e: evm: Drop board check for ESM
When config is enabled, the esm dt probe makes sense. Simplify by
dropping board specific checks.

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
2023-11-22 12:04:14 -05:00
Nishanth Menon
4abe8c9f08 board: ti: j721e: evm: Drop unused headers
Drop headers that are no longer necessary for build

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
2023-11-22 12:04:14 -05:00
Nishanth Menon
110b07c8bc arm: mach-k3: Move TI dummy keys out of board folder
This file is used to emulate customer keys on TI development board
ecosystems, move it out of board/ directory and into mach-k3. And
change the relative paths to absolute paths in the binman paths.

While at it, drop the reference in verdin-binman file which is
redundant.

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Acked-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-11-22 12:04:14 -05:00
Nishanth Menon
f1c8e9c442 arm: mach-k3: Move K3 degenerate keys out of board folder
This file is common for all of K3, move it out of board/ directory and
into mach-k3. And change the relative paths to absolute paths in the
binman paths.

While at it, drop the reference in verdin-binman file which is
redundant.

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Reviewed-by: Andrew Davis <afd@ti.com>
2023-11-22 12:04:14 -05:00
Andrew Davis
140d427cc9 arm: mach-k3: Move sysfw-loader into R5 directory
SYSFW is only ever loaded by the R5 core, move the code into that
directory. While here also move the related Kconfig symbols.

Signed-off-by: Andrew Davis <afd@ti.com>
2023-11-22 12:04:14 -05:00
Andrew Davis
cf2a075b8c arm: mach-k3: Remove incorrect checks for SPL build
The kconfig option SPL means this build supports SPL but not that
this build is SPL, nor that this build is the SPL running on R5.
For options that are for R5 SPL use CPU_V7R.

Signed-off-by: Andrew Davis <afd@ti.com>
2023-11-22 12:04:14 -05:00
Andrew Davis
ffda1089dd arm: mach-k3: Move R5 specific code into new r5/ directory
This makes it clear these are only to be used by the R5 builds of SPL.
And this will be used to later more cleanly split the two builds.

Signed-off-by: Andrew Davis <afd@ti.com>
2023-11-22 12:04:13 -05:00
Andrew Davis
5710d0a853 arm: mach-k3: j721s2: Move board selection to mach-k3
Currently each set of board targets from a vendor is selected inside
the board directory for that vendor. This has the problem of multiple
targets, one from each vendor, being selectable at the same time.
For instance you can select both TARGET_AM654_A53_EVM and
TARGET_IOT2050_A53 in the same build.

To fix this we need to move the target board choice to a common location
for each parent SoC selection. Do this in arch/arm/mach-k3.

Signed-off-by: Andrew Davis <afd@ti.com>
2023-11-22 09:37:23 -05:00
Andrew Davis
e4439cadb6 arm: mach-k3: am62ax: Move board selection to mach-k3
Currently each set of board targets from a vendor is selected inside
the board directory for that vendor. This has the problem of multiple
targets, one from each vendor, being selectable at the same time.
For instance you can select both TARGET_AM654_A53_EVM and
TARGET_IOT2050_A53 in the same build.

To fix this we need to move the target board choice to a common location
for each parent SoC selection. Do this in arch/arm/mach-k3.

Signed-off-by: Andrew Davis <afd@ti.com>
2023-11-22 09:37:23 -05:00
Andrew Davis
f3bfec72d1 arm: mach-k3: am62x: Move board selection to mach-k3
Currently each set of board targets from a vendor is selected inside
the board directory for that vendor. This has the problem of multiple
targets, one from each vendor, being selectable at the same time.
For instance you can select both TARGET_AM654_A53_EVM and
TARGET_IOT2050_A53 in the same build.

To fix this we need to move the target board choice to a common location
for each parent SoC selection. Do this in arch/arm/mach-k3.

Signed-off-by: Andrew Davis <afd@ti.com>
2023-11-22 09:37:23 -05:00
Andrew Davis
ed51c911a6 arm: mach-k3: am64x: Move board selection to mach-k3
Currently each set of board targets from a vendor is selected inside
the board directory for that vendor. This has the problem of multiple
targets, one from each vendor, being selectable at the same time.
For instance you can select both TARGET_AM654_A53_EVM and
TARGET_IOT2050_A53 in the same build.

To fix this we need to move the target board choice to a common location
for each parent SoC selection. Do this in arch/arm/mach-k3.

Signed-off-by: Andrew Davis <afd@ti.com>
2023-11-22 09:37:23 -05:00
Andrew Davis
c3a9f9b2b9 arm: mach-k3: am65x: Move board selection to mach-k3
Currently each set of board targets from a vendor is selected inside
the board directory for that vendor. This has the problem of multiple
targets, one from each vendor, being selectable at the same time.
For instance you can select both TARGET_AM654_A53_EVM and
TARGET_IOT2050_A53 in the same build.

To fix this we need to move the target board choice to a common location
for each parent SoC selection. Do this in arch/arm/mach-k3.

Signed-off-by: Andrew Davis <afd@ti.com>
2023-11-22 09:37:23 -05:00
Andrew Davis
1736b2f0fd arm: mach-k3: j721e: Move board selection to mach-k3
Currently each set of board targets from a vendor is selected inside
the board directory for that vendor. This has the problem of multiple
targets, one from each vendor, being selectable at the same time.
For instance you can select both TARGET_AM654_A53_EVM and
TARGET_IOT2050_A53 in the same build.

To fix this we need to move the target board choice to a common location
for each parent SoC selection. Do this in arch/arm/mach-k3.

Signed-off-by: Andrew Davis <afd@ti.com>
2023-11-22 09:37:23 -05:00
Andrew Davis
5936351be1 board: ti: Add dependency from TARGET selection to SOC
Currently the K3 selection for TARGET boards does not depend on the SoC
for which it is based. This leds to the odd ability to select for instance
both SOC_K3_AM625 and TARGET_J721E_A72_EVM.

To fix this the target choice should depend on the matching SOC config.

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
2023-11-22 09:37:22 -05:00
Tom Rini
0744fef6a3 Merge tag 'tpm-next-22112023' of https://source.denx.de/u-boot/custodians/u-boot-tpm into next
tpm_tis_send-cleanup
2023-11-22 08:26:46 -05:00
Heinrich Schuchardt
9086e8f04d tpm: remove superfluous check in tpm_tis_send()
Checking if variable chip is NULL after dereferencing it makes no sense.
As discribed in [1] it is not expected that the variable can ever be NULL.

[1] Re: [PATCH] tpm: avoid NULL pointer dereference in tpm_tis_send()
    https://lore.kernel.org/u-boot/YaFwDtKKYRr7qzWc@apalos.home/

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2023-11-22 10:03:55 +02:00
Miquel Raynal
8a0d07807a usb: udc: Try to clarify an error message
At some point when trying to use USB gadgets, two situations may arise
and lead to a failure. Either the UDC (USB Device Controller) is not
available at all (not described or not probed) or the UDC is already in
use. For instance, as the USB Ethernet gadget remains bound to the UDC,
the use of any other USB gadget (fastboot, dfu, etc) *after* will always
fail with the "couldn't find an available UDC" error.

Let's give a more helpful message by making a difference between the two
cases. Let's also hint people who would get this error and grep it into
the sources a better explanation of what's wrong with their workflow.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Link: https://lore.kernel.org/r/20231010090304.49335-4-miquel.raynal@bootlin.com
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
2023-11-21 15:48:38 +01:00
Miquel Raynal
249a75d8e8 cmd: bind: Try to improve the (un)bind help
While it may sound totally obvious for the regular U-Boot developer to
get the parameters of the bind/unbind commands from the output of 'dm
tree', it did not felt straightforward to me until I was explicitly
told to look there. And even when I knew the command, I did not make a
direct link between the arguments of this command and the columns
returned by 'dm tree'.

Several of us lost a lot of time because of that, I would like to kindly
help other users by slightly improving this textual line. Unfortunately,
because of how this string is used (like within the 'help' command) I
cannot detail much more, but at least the pointer is there.

While we add this message, we can also imply CMD_DM when we enable
CMD_BIND so the debug message does not lead to an unknown command. This
way the 'dm' command will likely be there unless explicitly disabled.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Link: https://lore.kernel.org/r/20231010090304.49335-3-miquel.raynal@bootlin.com
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
2023-11-21 15:48:38 +01:00
Miquel Raynal
9b63fcaec6 cmd: Change the dependencies between CMD_BIND and USB_GADGET
Today CMD_BIND defaults to 'y' when USB_ETHER is enabled. In practice,
CMD_BIND should default to 'y' when any USB gadget is enabled not only
USB_ETHER. Let's invert the logic of the dependency and use the weak
'imply' keyword to enforce this.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Tested-by: Mattijs Korpershoek <mkorpershoek@baylibre.com> # on vim3
Link: https://lore.kernel.org/r/20231010090304.49335-2-miquel.raynal@bootlin.com
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
2023-11-21 15:48:38 +01:00
Marek Vasut
1041ee64eb usb: gadget: f_mass_storage: Stop ums on START-STOP UNIT SCSI command
Exit the UMS handler loop in case START-STOP UNIT SCSI command is
received. This is sent e.g. by the util-linux eject(1) command and
indicates to the device that it is supposed to spin down the media
and enter low power state.

This effectively adds support for exitting the 'ums' command from
host using 'eject /dev/sdN' that is on par with 'dfu-util -e' .

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Link: https://lore.kernel.org/r/20231107001018.55640-1-marex@denx.de
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
2023-11-21 15:28:15 +01:00
Jaehoon Chung
f490623309 dfu: add CONFIG_DFU_NAME_MAX_SIZE configuration
Add CONFIG_DFU_NAME_MAX_SIZE to change the proper size.
If name is longer than default size, it can do wrong behavior during updating
image. So it need to change the proper maximum size.

This patch is proviced the solution to change value with configuration.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Link: https://lore.kernel.org/r/20220620111354.448512-1-jh80.chung@samsung.com
[mkorpershoek: fixed build errors for dfu.h includes]
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
2023-11-21 15:28:15 +01:00
Tom Rini
dca7a8958f Merge tag 'v2024.01-rc3' into next
Prepare v2024.01-rc3
2023-11-20 09:19:50 -05:00
Tom Rini
9e4b42267e Merge tag 'efi-next-18112023' of https://source.denx.de/u-boot/custodians/u-boot-tpm into next
EFI HTTP Boot is currently supported by using a combination of
wget, blkmap and bootefi commands. The user has to download the
image, mount it using blkmap and then execute the efi installer
using bootefi.
This series simplifies the user experience. Instead of doing all the
steps manually, users can now enable a new Kconfig (EFI_HTTP_BOOT)
which will select wget, blkmap and dns options. They can then use
efidebug command to add a boot option for the EFI Bootmanager using
=> efidebug boot add -u 3 netinst http://<path>
=> efidebug boot order 3
=> bootefi bootmgr

The boot manager will automatically download and mount the image.
Once it's mounted it will locate and launch the installer.

It's worth noting that this rarely fails, but the reason is irrelevant
to the current patchset. More information can be found here
https://lore.kernel.org/u-boot/CAOMZO5CoduEgwgdQiybmoKh6qQZOezUtRRQO4ecaGdZBBz5dDw@mail.gmail.c
om/
The tl;dr is that wget sometimes fails to download the file correctly
or set the size env variables. We expect all these to be solved once
LWIP is stable and pulled
2023-11-18 15:52:53 -05:00
Masahisa Kojima
c022eed4be doc: uefi: add HTTP Boot support
This adds the description about HTTP Boot.

[Ilias add the new EFI_HTTP_BOOT option in docs]
Lore: https://lore.kernel.org/u-boot/20231110042542.3797301-1-masahisa.kojima@linaro.org/T/#m36acf922a888cc14f74e823ec57bacd9f977194e
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2023-11-18 10:08:09 +02:00
Masahisa Kojima
f01c961ee3 cmd: efidebug: add uri device path
This adds the URI device path option for 'boot add' subcommand.
User can add the URI load option for downloading ISO image file
or EFI application through network. Currently HTTP is only supported.

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2023-11-18 10:08:09 +02:00
Masahisa Kojima
d7d07a8b50 efi_loader: support boot from URI device path
This supports to boot from the URI device path.
When user selects the URI device path, bootmgr downloads
the file using wget into the address specified by loadaddr
env variable.
If the file is .iso or .img file, mount the image with blkmap
then try to boot with the default file(e.g. EFI/BOOT/BOOTAA64.EFI).
Since boot option indicating the default file is automatically
created when new disk is detected, system can boot by selecting
the automatically created blkmap boot option.
If the file is PE-COFF file, load and start the downloaded file.

The buffer used to download the ISO image file must be
reserved to avoid the unintended access to the image and
expose the ramdisk to the OS.
For PE-COFF file case, this memory reservation is done
in LoadImage Boot Service.

[Ilias fix a few memory leaks by replacing returns with gotos]
Lore: https://lore.kernel.org/u-boot/20231110042542.3797301-1-masahisa.kojima@linaro.org/T/#mbac31da301ff465b60894b38f3a587b2868cf817
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2023-11-18 10:08:09 +02:00
Masahisa Kojima
e0d1a1ea68 efi_loader: add return to efibootmgr event group
When the image loaded by efibootmgr returns, efibootmgr
needs to clean the resources. Adding the event of returning
to efibootmgr is useful to simplify the implementation.

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2023-11-18 10:08:09 +02:00
Masahisa Kojima
e23c8e81eb efi_loader: add missing const classifier for event service
const classifier is missing in EventGroup parameter of
CreateEventEx(). Fix it to remove the compiler warning.

NotifyContext parameter of CreateEventEx() is also defined
with const in UEFI specification, but NotifyContext parameter
of CreateEvent() is defined without const.
Since current implementation calls the common efi_create_event()
function from both CreateEventEx() and CreateEvent() services,
NotifyContext parameter leaves as is.

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2023-11-18 10:08:09 +02:00
Raymond Mao
550862bc12 efi_loader: Boot var automatic management
Changes for complying to EFI spec §3.5.1.1
'Removable Media Boot Behavior'.
Boot variables can be automatically generated during a removable
media is probed. At the same time, unused boot variables will be
detected and removed.

Please note that currently the function 'efi_disk_remove' has no
ability to distinguish below two scenarios
a) Unplugging of a removable media under U-Boot
b) U-Boot exiting and booting an OS
Thus currently the boot variables management is not added into
'efi_disk_remove' to avoid boot options being added/erased
repeatedly under scenario b) during power cycles
See TODO comments under function 'efi_disk_remove' for more details

The original efi_secboot tests expect that BootOrder EFI variable
is not defined. With this commit, the BootOrder EFI variable is
automatically added when the disk is detected. The original
efi_secboot tests end up with unexpected failure.
The efi_secboot tests need to be modified to explicitly set
the BootOrder EFI variable.

squashfs and erofs ls tests are also affected by this modification,
need to clear the previous state before squashfs ls test starts.

Co-developed-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Signed-off-by: Raymond Mao <raymond.mao@linaro.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Joao Marcos Costa <jmcosta944@gmail.com>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2023-11-18 10:08:08 +02:00
Masahisa Kojima
d822255d65 blk: blkmap: add ramdisk creation utility function
User needs to call several functions to create the ramdisk
with blkmap.
This adds the utility function to create blkmap device and
mount the ramdisk.

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2023-11-18 10:08:08 +02:00
Masahisa Kojima
8cf18da1a9 net: wget: add wget with dns utility function
Current wget takes the target uri in this format:
 "<http server ip>:<file path>"  e.g.) 192.168.1.1:/bar
The http server ip address must be resolved before
calling wget.

This commit adds the utility function runs wget with dhs.
User can call wget with the uri like "http://foo/bar".

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2023-11-18 10:08:08 +02:00
Masahisa Kojima
04592adbdb net: wget: prevent overwriting reserved memory
This introduces the valid range check to store the received
blocks using lmb. The same logic is implemented in tftp.

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2023-11-18 10:08:08 +02:00
Tom Rini
ae7ec8b0be Merge branch '2023-11-16-assorted-updates' into next
- squashfs improvements, remove common.h in some places, assorted code
  fixes, fix a few CONFIG symbol names in Kconfig files, bring in
  linux's <linux/time.h> conversion functions, poplar updates, bcb
  improvements.
2023-11-17 08:38:05 -05:00
Simon Glass
b83fae673a blk: Drop reference to DM_SPL
The intent here is to only allow SPL_LEGACY_BLK if !SPL_DM - i.e. that
when driver model is enabled in SPL, legacy block cannot be used.

However this combination is used by about 240 boards, so we cannot
disallow it, at least not yet.

So just drop the condition.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-11-16 18:59:58 -05:00
Simon Glass
a07408384b dm: core: Correct reference to DM_SPL in SPL_DM_STATS
This does not existing anymore. Update SPL_DM_STATS to use the correct
Kconfig option, which is SPL_DM

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-11-16 18:59:58 -05:00
Sam Edwards
6d6ea52b62 fs: btrfs: fix reading when length specified
The btrfs read function limits the read length to ensure that it
and the read offset do not together exceed the size of the file.
However, this size was only being queried if the read length was
passed a value of zero (meaning "whole file"), and the size is
defaulted to 0 otherwise. This means the clamp will just zero out
the length if one is specified, preventing reading of the file.

Fix this by checking the file size unconditionally, and unifying
the default length and clamping logic as a single range check instead.

This bug was discovered when trying to boot Linux with initrd= via
'bootefi' from a btrfs partition. The EFI stub entered an infinite
loop of zero-length reads while trying to read the initrd, and the
boot process stalled indefinitely.

Signed-off-by: Sam Edwards <CFSworks@gmail.com>
Reviewed-by: Qu Wenruo <wqu@suse.com>
2023-11-16 18:59:58 -05:00
Dmitrii Merkurev
dfeb4f0d79 cmd: bcb: extend BCB C API to allow read/write the fields
Currently BCB C API only allows to modify 'command' BCB field.
Extend it so that we can also read and modify all the available
BCB fields (command, status, recovery, stage).

Co-developed-by: Cody Schuffelen <schuffelen@google.com>
Signed-off-by: Cody Schuffelen <schuffelen@google.com>
Signed-off-by: Dmitrii Merkurev <dimorinny@google.com>
Cc: Eugeniu Rosca <erosca@de.adit-jv.com>
Cc: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Cc: Simon Glass <sjg@chromium.org>
Cc: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Cc: Sean Anderson <sean.anderson@seco.com>
Cc: Cody Schuffelen <schuffelen@google.com>
Tested-by: Mattijs Korpershoek <mkorpershoek@baylibre.com> # on vim3
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
2023-11-16 18:59:58 -05:00
Dmitrii Merkurev
a654369b49 cmd: bcb: support various block device interfaces for BCB command
Currently BCB command-line, C APIs and implementation only
support MMC interface. Extend it to allow various block
device interfaces.

Signed-off-by: Dmitrii Merkurev <dimorinny@google.com>
Cc: Eugeniu Rosca <erosca@de.adit-jv.com>
Cc: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Cc: Simon Glass <sjg@chromium.org>
Cc: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Cc: Sean Anderson <sean.anderson@seco.com>
Cc: Cody Schuffelen <schuffelen@google.com>
Tested-by: Mattijs Korpershoek <mkorpershoek@baylibre.com> # on vim3
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
2023-11-16 18:59:58 -05:00
Igor Opaniuk
66a3618b9a poplar: provide more space for kernel image
Adjust mem layout, providing more space for linux kernel image.

This fixes the problem:
ERROR: FDT image overlaps OS image (OS=0x30000000..0x32580000)

Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
2023-11-16 18:59:58 -05:00
Igor Opaniuk
01201dbd3b poplar: use random mac address
Set CONFIG_NET_RANDOM_ETHADDR=y, which sets random eth address in
case there is no configuration provided neither in CONFIG_ETHADDR
nor in "ethaddr" env variable.

This fixes the problem:
poplar# dhcp
Error: ethernet@9841000 address not set.

Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
2023-11-16 18:59:58 -05:00
Igor Prusov
13248d66ae treewide: use linux/time.h for time conversion defines
Now that we have time conversion defines from in time.h there is no need
for each driver to define their own version.

Signed-off-by: Igor Prusov <ivprusov@salutedevices.com>
Reviewed-by: Svyatoslav Ryhel <clamor95@gmail.com> # tegra
Reviewed-by: Eugen Hristev <eugen.hristev@collabora.com> #at91
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> #qcom geni
Reviewed-by: Stefan Bosch <stefan_b@posteo.net> #nanopi2
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-11-16 18:59:58 -05:00
Igor Prusov
35425507b3 spi: meson_spifc_a1: Use define for time interval
Use USEC_PER_MSEC define for timeout to sync code with Linux version.

Signed-off-by: Igor Prusov <ivprusov@salutedevices.com>
2023-11-16 18:59:58 -05:00
Igor Prusov
d7ce04c7f4 linux/time.h: Add Linux time conversion defines
Currently there are no defines for time conversion in time.h, which
leads to drivers declaring those locally or not using defines at all, so
add them from Linux.

Signed-off-by: Igor Prusov <ivprusov@salutedevices.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-11-16 18:59:58 -05:00
Sean Anderson
7667bdeb0e fs: ext4: Remove unused parameter from ext4_mount
The part_length parameter is not used. Remove it.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2023-11-16 18:53:09 -05:00
Paul Barker
da35ab68de sysreset: Fix unsupported request return values
The description of the sysreset request method in <sysreset.h> says that
the return value should be -EPROTONOSUPPORT if the requested reset type
is not supported by this device.

Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-11-16 18:53:09 -05:00
Christophe Leroy
15e871fc5d board: cssi: Remove usage of common.h
Remove inclusion of common.h and add relevant
includes when necessary.

Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
2023-11-16 18:53:09 -05:00
Christophe Leroy
80ac19fd56 powerpc: mpc8xx: Remove usage of common.h
Remove inclusion of common.h and add relevant
includes when necessary.

Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
2023-11-16 18:53:09 -05:00
David Oberhollenzer
fa894a36a9 fs/squashfs: enable LZ4 compression support
The structure is identical to the existing compressor implementations,
trivially adding lz4 decompression to sqfs_decompress.

The changes were tested using a sandbox build. An LZ4 compressed
squashfs image was bound as a host block device.

Signed-off-by: David Oberhollenzer <goliath@infraroot.at>
Reviewed-by: Joao Marcos Costa <jmcosta944@gmail.com>
2023-11-16 18:53:09 -05:00
David Oberhollenzer
99374ff189 fs/squashfs: remove unused declarations
This patch removes a number of struct and macro declaration that
were found through `git-grep` to be unused. Most of those are
related to compressor options and super block flags.

For reading a SquashFS image, we do not need the compressor options
or the flags. Those only encode settings used for packing the image,
mksquashfs uses them when appending data to an existing image. The
kernel implementation does not touch those, and we don't need them
either.

Signed-off-by: David Oberhollenzer <goliath@infraroot.at>
2023-11-16 18:53:09 -05:00
Sean Anderson
1125e291fb bootm: Enable legacy VxWorks booting from FITs
This works without issue, so don't fail.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2023-11-16 16:21:38 -05:00
Sean Anderson
2a1812de20 test: eth: Don't crash if env_get returns NULL
env_get can return NULL if it fails to find the variable. Check its result
before using it.

Fixes: 6d9764c2a8 ("dm: test: Add a new test case against dm eth codes for NULL pointer access")
Fixes: df33fd2889 ("test: eth: Add test for ethernet addresses")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
2023-11-16 16:21:38 -05:00
Tom Rini
6c1608b1ff Merge patch series "spl: Use common function for loading/parsing images"
To quote the author:

This series adds support for loading all image types (Legacy (with and without
LZMA), FIT (with and without LOAD_FIT_FULL), and i.MX) to the MMC, SPI, NOR,
NET, FAT, EXT, NVMe, and semihosting load methods. It does this by introducing a
helper function which handles the minutiae of invoking the proper parsing
function, and reading the rest of the image.

Hopefully, this will make it easier for load methods to support all image types
that U-Boot supports, without having undocumented unsupported image types. I
applied this to several loaders which were invoking spl_load_simple_fit and/or
spl_parse_image_header, but I did not use it with others (e.g. DFU/RAM) which
had complications in the mix.

This series is organized roughly into two parts. Patches up to "spl: Add generic
spl_load function" are all setup or size-reduction oriented. Later patches
generally convert various load functions to spl_load.

bloat-o-meter results (for CONFIG_SPL only) at [1]. Size growth has been the
bigegst challenge to preparing this series. I have used every trick I can think
of to reduce bloat. Some SAMA boards no longer fit, but I have a plan to fix
them [2].

This is bar far the largest and most-difficult revision of this series to-date.
There are probably still things which can reduce the size, but I have been
working on this series for the better part of two months and I think it is a
good idea to get some feedback. Because of the SAMA bloat, this series will not
pass CI, so I expect to do a v7 before this is ready to apply. Feel free,
however, to apply patches in the first half (especially the fixes).

This version of the series is better-tested than ever before, thanks to some new
unit tests. However, things like the i.MX ROMAPI are untested. NAND should also
be tested more-widely, for reasons listed in the commit message. I encourage you
try this series out on your favorite board.

[1] https://gist.github.com/Forty-Bot/5bfe88676dd3c2aec6ebc23abb08e06f
    This includes some changes to am335x_evm_spiboot and am65x_evm_r5_usbdfu
    which have since been undone. This was ran for v6.
[2] https://lore.kernel.org/u-boot/20231105022742.632175-1-seanga2@gmail.com/
2023-11-16 13:49:14 -05:00
Sean Anderson
54a8d845be spl: fat: Add option to disable DMA alignment
If we don't DMA-align buffers we pass to FAT, it will align them itself.
This behaviour likely should be deprecated in favor of
CONFIG_BOUNCE_BUFFER, but that's a task for another series. For the
meantime, don't bother aligning the buffer unless we had been doing so in
the past.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-11-16 13:49:14 -05:00
Sean Anderson
14509a28aa spl: spi: Consolidate spi_load_image_os into spl_spi_load_image
spi_load_image_os performs almost the same steps as the non-falcon-boot
path of spl_spi_load_image. The load address is different, and it also
loads a device tree, but that's it. Refactor the boot process so that
they can both use the same load function.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-11-16 13:49:14 -05:00
Sean Anderson
a04d5f60a5 spl: Convert spi to spl_load
This converts the spi load method to use spl_load. The address used for
LOAD_FIT_FULL may be different, but there are no in-tree users of that
config. Since payload_offs is only used without OS_BOOT, we defer its
initialization.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-11-16 13:49:14 -05:00
Sean Anderson
9b9c6aaaf2 spl: Convert semihosting to spl_load
This converts the semihosting load method to use spl_load. As a result, it
also adds support for LOAD_FIT_FULL and IMX images.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2023-11-16 13:49:14 -05:00
Sean Anderson
6029a0e1af spl: Convert NVMe to spl_load
This converts the blk load method (used exclusively by NVMe) to use
spl_load. As a consequence, it also adds support for LOAD_FIT_FULL and
IMX images.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-11-16 13:49:14 -05:00
Sean Anderson
cbe86576cb spl: Convert nor to spl_load
This converts the nor load method to use spl_load. As a result it also
adds support for LOAD_FIT_FULL. Since this is the last caller of
spl_load_legacy_img, it has been removed.

We can't load FITs with external data with SPL_LOAD_FIT_FULL, so disable the
test in that case. No boards enable SPL_NOR_SUPPORT and SPL_LOAD_FIT_FULL, so
this is not a regression.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-11-16 13:49:14 -05:00
Sean Anderson
2e5476b5a7 spl: Convert net to spl_load
This converts the net load method to use spl_load. As a result, it also
adds support for LOAD_FIT_FULL and IMX images.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-11-16 13:49:14 -05:00
Sean Anderson
11f834614e spl: Convert nand to spl_load
This converts the nand load method to use spl_load. nand_page_size may not
be valid until after nand_spl_load_image is called (see e.g. fsl_ifc_spl),
so we set bl_len in spl_nand_read. Since spl_load reads the header for us,
we can remove that argument from spl_nand_load_element.

There are two possible regressions which could result from this commit.
First, we ask for a negative address from spl_get_load_buffer. That is,
instead of

	header = spl_get_load_buffer(0, sizeof(*header));

we do

	header = spl_get_load_buffer(-sizeof(*header), sizeof(*header));

this could cause a problem if spl_get_load_buffer does not return valid
memory for negative offsets. Second, we now set bl_len for legacy images.
This can cause memory up to a bl_len - 1 before the image load address to
be written, which might not have been the case before. If this turns out to
be a problem, we can add an option for a bounce buffer.

We can't load FITs with external data with SPL_LOAD_FIT_FULL, so disable the
test in that case. No boards enable SPL_NAND_SUPPORT and SPL_LOAD_FIT_FULL, so
this is not a regression.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-11-16 13:49:14 -05:00
Sean Anderson
5d3401a448 spl: Convert mmc to spl_load
This converts the mmc loader to spl_load. Legacy images are handled by
spl_load (via spl_parse_image_header), so mmc_load_legacy can be
omitted. To accurately determine whether mmc_load_image_raw_sector is used
(which might not be the case if SYS_MMCSD_FS_BOOT is enabled), we introduce
a helper config SYS_MMCSD_RAW_MODE. This ensures we can inline spl_load
correctly when a board only boots from filesystems. We still need to check
for SPL_MMC, since some boards enable configure raw mode even without MMC
support.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-11-16 13:49:14 -05:00
Sean Anderson
682184e9b9 spl: Convert fat to spl_load
This converts the fat loader to use spl_load. Some platforms are very
tight on space, so we take care to only include the code we really need.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-11-16 13:49:14 -05:00
Sean Anderson
b8ed722567 spl: Convert ext to use spl_load
This converts the ext load method to use spl_load. As a consequence, it
also adds support for FIT and IMX images.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-11-16 13:49:14 -05:00
Sean Anderson
775074165d spl: Add generic spl_load function
Implementers of SPL_LOAD_IMAGE_METHOD have to correctly determine what
type of image is being loaded and then call the appropriate image load
function correctly. This is tricky, because some image load functions
expect the whole image to already be loaded (CONFIG_SPL_LOAD_FIT_FULL),
some will load the image automatically using spl_load_info.read()
(CONFIG_SPL_LOAD_FIT/CONFIG_SPL_LOAD_IMX_CONTAINER), and some just parse
the header and expect the caller to do the actual loading afterwards
(legacy/raw images). Load methods often only support a subset of the
above methods, meaning that not all image types can be used with all
load methods. Further, the code to invoke these functions is
duplicated between different load functions.

To address this problem, this commit introduces a "spl_load" function.
It aims to handle image detection and correct invocation of each of the
parse/load functions.

Although this function generally results in a size reduction with
several users, it tends to bloat boards with only a single user.
This is generally because programmers open-coding the contents of this
function can make optimizations based on the specific loader. For
example, NOR flash is memory-mapped, so it never bothers calling
load->read. The compiler can't really make these optimizations across
translation units. LTO solves this, but it is only available on some
arches. To address this, perform "pseudo-LTO" by inlining spl_load when
there are one or fewer users. At the moment, there are no users, so
define SPL_LOAD_USERS to be 0.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-11-16 13:49:14 -05:00
Sean Anderson
5b3debc61e test: spl: Support testing LEGACY_LZMA filesystem images
These will soon be supported, so we need to be able to test it. Export the
lzma data and generally use the same process in spl_test_mmc_fs as
do_spl_test_load.  If we end up needing this in third place in the future,
it would probably be good to refactor things out.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-11-16 13:49:14 -05:00
Sean Anderson
efe92cd2f9 spl: legacy: Split off LZMA decompression into its own function
To allow for easier reuse of this functionality, split it off into its
own function.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-11-16 13:49:14 -05:00
Sean Anderson
0ddfa868ba spl: nand: Remove spl_nand_legacy_read
Now that spl_nand_fit_read works in units of bytes, it can be combined with
spl_nand_legacy_read. Rename the resulting function spl_nand_read, since it
is no longer FIT-specific.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-11-16 13:49:14 -05:00
Sean Anderson
5271e359a4 spl: Only support bl_len when we have to
Aligning addresses and sizes causes overhead which is unnecessary when we
are not loading from block devices. Remove bl_len when it is not needed.

For example, on iot2050 we save 144 bytes with this patch (once the rest of
this series is applied):

add/remove: 0/0 grow/shrink: 0/3 up/down: 0/-144 (-144)
Function                                     old     new   delta
spl_load_simple_fit                          920     904     -16
load_simple_fit                              496     444     -52
spl_spi_load_image                           384     308     -76
Total: Before=87431, After=87287, chg -0.16%

We use panic() instead of BUILD_BUG_ON in spl_set_bl_len because we still
need to be able to compile it for things like mmc_load_image_raw_sector,
even if that function will not be used.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-11-16 13:49:14 -05:00
Sean Anderson
afdd2d98c2 spl: Remove filename from spl_load_info
For filesystems, filename serves the same purpose as priv. However,
spl_load_fit_image also uses it to determine whether to use a DMA-aligned
buffer. This is beneficial for FAT, which uses a bounce-buffer if the
destination is not DMA-aligned. However, this is unnecessary now that
filesystems set bl_len to ARCH_DMA_MINALIGN instead. With this done, we can
remove filename entirely.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-11-16 13:49:14 -05:00
Sean Anderson
b63664be6a spl: Set FAT bl_len to ARCH_DMA_MINALIGN
Instead of relying on the presence of filename to determine whether we are
dealing with a FAT filesystem (and should DMA-align the buffer), have FAT set
bl_len to ARCH_DMA_MINALIGN instead. With this done, we can remove the
special-case logic checking for the presence of filename.

Because filesystems are not block-based, we may read less than the size passed
to spl_load_info.read. This can happen if the file size is not DMA-aligned. This
is fine as long as we read the amount we originally wanted to. Modify the
conditions for callers of spl_load_info.read to check against the original,
unaligned size to avoid failing spuriously.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-11-16 13:49:14 -05:00
Sean Anderson
73c40fcb73 spl: Refactor spl_load_info->read to use units of bytes
Simplify things a bit for callers of spl_load_info->read by refactoring it
to use units of bytes instead of bl_len. This generally simplifies the
logic, as MMC is the only loader which actually works in sectors. It will
also allow further refactoring to remove the special-case handling of
filename.  spl_load_legacy_img already works in units of bytes (oops) so it
doesn't need to be changed.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-11-16 13:49:14 -05:00
Sean Anderson
33c8d01a4d spl: Take advantage of bl_len's power-of-twoness
bl_len must be a power of two, so we can use ALIGN instead of roundup and
similar tricks to avoid divisions.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-11-16 13:49:14 -05:00
Tom Rini
5e6a112e11 Merge patch series "nand: Add sandbox tests"
To quote the author:

This series tests raw nand flash in sandbox and fixes various bugs discovered in
the process. I've tried to do things in a contemporary manner, avoiding the
(numerous) variations present on only a few boards. The test is pretty minimal.
Future work could test the rest of the nand API as well as the MTD API.

Bloat (for v1) at [1] (for boards with SPL_NAND_SUPPORT enabled). Almost
everything grows by a few bytes due to nand_page_size. A few boards grow more,
mostly those using nand_spl_loaders.c. CI at [2].

[1] https://gist.github.com/Forty-Bot/9694f3401893c9e706ccc374922de6c2
[2] https://source.denx.de/u-boot/custodians/u-boot-clk/-/pipelines/18443
2023-11-16 13:49:13 -05:00
Sean Anderson
0c6c83e6a2 spl: Remove dev from spl_load_info
dev and priv serve the same purpose, and are never set at the same time.
Remove dev and convert all users to priv. While we're at it, reorder bl_len
to be last for better alignment.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-11-16 13:49:13 -05:00
Sean Anderson
feaeb8fa6f spl: Remove NULL assignments in spl_load_info
Remove NULL assignments to fields in spl_load_info when .load doesn't
reference these fields. This can result in more efficient code. filename
must stay even if it is unused, since load_simple_fit uses it.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-11-16 13:49:13 -05:00
Sean Anderson
517e70856f spl: semihosting: Don't close fd before spl_load_simple_fit
On real hardware, semihosting calls tend to have a large constant
overhead (on the order of tens of milliseconds). Reduce the number of
calls by one by reusing the existing fd in smh_fit_read, and closing it
at the end of spl_smh_load_image.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-11-16 13:49:13 -05:00
Sean Anderson
06b1bca69d spl: Make SHOW_ERRORS depend on LIBCOMMON
The purpose of SHOW_ERRORS is to print extra information. Make it depend
on LIBCOMMON to avoid having to check for two configs.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-11-16 13:49:13 -05:00
Sean Anderson
3b46cdd7a0 arm: Disable SPL_FS_FAT when it isn't used
Several boards enable SPL_FS_FAT and SPL_LIBDISK_SUPPORT when they can't be
used (as there is no block device support enabled). Disable these configs.
The list of boards was generated with the following command:

    $ tools/qconfig.py -f SPL SPL_FS_FAT ~SPL_MMC ~SPL_BLK_FS ~SPL_SATA \
                          ~SPL_USB_STORAGE ~ENV_IS_IN_FAT ~EFI

LIBDISK was left enabled for the am* boards, since it seems to result in
actual size reduction, indicating that partitions are being used for
something.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Michal Simek <michal.simek@amd.com>
2023-11-16 13:49:13 -05:00
Sean Anderson
1e86296f7f spl: blk_fs: Fix uninitialized return value when we can't get a blk_desc
Initialize ret to avoid returning garbage if blk_get_devnum_by_uclass_id
fails.

Fixes: 8ce6a2e175 ("spl: blk: Support loading images from fs")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-11-16 13:49:13 -05:00
Sean Anderson
a9a7379973 arm: Enable SYS_THUMB_BUILD on AT91
Several AT91 boards are quite close to their SPL size limit. For example,
sama5d27_wlsom1_ek_mmc is just 173 bytes short of its limit and doesn't
even fit with older GCCs.

All AT91 processors should have thumb support. Enable SYS_THUMB_BUILD. This
shrinks SPL by around 30%.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2023-11-16 13:48:58 -05:00
Sean Anderson
8502b5bf20 test: spl: Add a test for NAND
Add a SPL test for the NAND load method. We use some different functions to
do the writing from the main test since things like nand_write_skip_bad
aren't available in SPL.

We disable BBT scanning, since scan_bbt is only populated when not in SPL.
We use nand_spl_loaders.c as it seems to be common to at least a few boards
already. However, we do not use nand_spl_simple.c because it would require
us to implement cmd_ctrl.  The various nand load functions are adapted from
omap_gpmc. However, they have been modified for simplicity/correctness.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2023-11-16 12:43:49 -05:00
Sean Anderson
bc8e8a4bfa nand: Add sandbox driver
Add a sandbox NAND flash driver to facilitate testing. This driver supports
any number of devices, each using a single chip-select. The OOB data is
stored in-band, with the separation enforced through the API.

For now, create two devices to test with. The first is a very small device
with basic ECC. The second is an 8G device (chosen to be larger than 32
bits). It uses ONFI, with the values copied from the datasheet. It also
doesn't need too strong ECC, which speeds things up.

Although the nand subsystem determines the parameters of a chip based on
the ID, the driver itself requires devicetree properties for each
parameter. We do not derive parameters from the ID because parsing the ID
is non-trivial. We do not just use the parameters that the nand subsystem
has calculated since that is something we should be testing. An exception
is made for the ECC layout, since that is difficult to encode in the device
tree and is not a property of the device itself.

Despite using file I/O to access the backing data, we do not support using
external files. In my experience, these are unnecessary for testing since
tests can generally be written to write their expected data beforehand.
Additionally, we would need to store the "programmed" information somewhere
(complicating the format and the programming process) or try to detect
whether block are erased at runtime (degrading probe speeds).

Information about whether each page has been programmed is stored in an
in-memory buffer. To simplify the implementation, we only support a single
program per erase. While this is accurate for many larger flashes, some
smaller flashes (512 byte) support multiple programs and/or subpage
programs. Support for this could be added later as I believe some
filesystems expect this.

To test ECC, we support error-injection. Surprisingly, only ECC bytes in
the OOB area are protected, even though all bytes are equally susceptible
to error. Because of this, we take care to only corrupt ECC bytes.
Similarly, because ECC covers "steps" and not the whole page, we must take
care to corrupt data in the same way.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2023-11-16 12:43:49 -05:00
Sean Anderson
9181cb0507 arch: sandbox: Add function to create temporary files
When working with sparse data buffers that may be larger than the address
space, it is convenient to work with files instead. Add a function to create
temporary files of a certain size.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2023-11-16 12:43:49 -05:00
Sean Anderson
333d43f6a3 nand: Allow reinitialization
NAND devices are destroyed in between unit tests. Provide a function to
reinitialize the subsystem at the beginning of each test.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-11-16 12:43:49 -05:00
Sean Anderson
c203482177 nand: Add function to unregister NAND devices
This performs the opposite of nand_register, allowing drivers to unregister
nand devices. This is probably unnecessary for most regular drivers, but we
expect sandbox drivers to get repeatedly bound/unbound, so this will help
avoid dangling pointers.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-11-16 12:43:49 -05:00
Sean Anderson
b37a9208a2 mtd: Add some fallbacks for add/del_mtd_device
This allows using these functions without ifdefs. OneNAND depends on MTD,
so this ifdef was redundant in the first place.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-11-16 12:43:49 -05:00
Sean Anderson
b35df87ae5 mtd: Rename SPL_MTD_SUPPORT to SPL_MTD
Rename SPL_MTD_SUPPORT to SPL_MTD in order to match MTD. This allows using
CONFIG_IS_ENABLED to test for MTD support.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2023-11-16 12:43:48 -05:00
Sean Anderson
bd9573c11c spl: nand: Map memory before accessing it
In sandbox we must map memory before accessing it. Do so for the NAND load
method.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2023-11-16 12:43:48 -05:00
Sean Anderson
d2e0a9a691 cmd: nand: Map memory before accessing it
In sandbox, all memory must be mapped before accessing it. Do so for the
nand command.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2023-11-16 12:43:48 -05:00
Sean Anderson
38ef64e6ce spl: nand: Set bl_len to page size
Since commit 34793598c8 ("mtd: nand: mxs_nand_spl: Remove the page aligned
access") there are no longer any users of nand_get_mtd. However, it is
still important to know what the page size is so we can allocate a
large-enough buffer. If the image size is not page-aligned, we will go off
the end of the buffer and clobber some memory.

Introduce a new function nand_page_size which returns the page size. For
most drivers it is easy to determine the page size. However, a few need to
be modified since they only keep the page size around temporarily.

It's possible that this patch could cause a regression on some platforms if
the offset is non-aligned and there is invalid address space immediately
before the load address. spl_load_legacy_img does not (except when
compressing) respect bl_len, so only boards with SPL_LOAD_FIT (8 boards) or
SPL_LOAD_IMX_CONTAINER (none in tree) would be affected.

defconfig               CONFIG_TEXT_BASE
======================= ================
am335x_evm              0x80800000
am43xx_evm              0x80800000
am43xx_evm_rtconly      0x80800000
am43xx_evm_usbhost_boot 0x80800000
am43xx_hs_evm           0x80800000
dra7xx_evm              0x80800000
gwventana_nand          0x17800000
imx8mn_bsh_smm_s2       0x40200000

All the sitara boards have DDR mapped at 0x80000000. gwventana is an i.MX6Q
which has DDR at 0x10000000. I don't have the IMX8MNRM handy, but on the
i.MX8M DDR starts at 0x40000000. Therefore all of these boards can handle a
little underflow.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2023-11-16 12:43:48 -05:00
Sean Anderson
57d3da6fee spl: legacy: Honor bl_len when decompressing
When allocating a buffer to load compressed data into, we need to ensure we
have enough space for over- and under-flow due to alignment. Otherwise we
will clobber the malloc bookkeeping data. Calculate the correct amount of
overhead and use it when determining the size.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2023-11-16 12:43:48 -05:00
Sean Anderson
cdc0434ac0 nand: spl_loaders: Only read enough pages to load the image
All other implementations of nand_spl_load_image only read as many pages as
are necessary to load the image. However, nand_spl_loaders.c loads the full
block. Align it with other load functions so that it is easier to
determine how large of a load buffer we need.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
2023-11-16 12:43:48 -05:00
Sean Anderson
601b8901e0 nand: Calculate SYS_NAND_BLOCK_PAGES (neé SYS_NAND_PAGE_COUNT) automatically
Contrary to what the help message says, this is the number of pages per
block. Calculate it automatically based on SYS_NAND_BLOCK_SIZE and
SYS_NAND_PAGE_SIZE. To better reflect its semantics, rename it to
SYS_NAND_BLOCK_PAGES.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2023-11-16 12:43:48 -05:00
Sean Anderson
23c2ebe4d4 nand: Don't dereference NULL manufacturer_desc
When no manufacturer is matched, manufacturer_desc is NULL. Avoid
dereferencing it in that case.

Fixes: 4e67c57125 ("mtd,ubi,ubifs: sync with linux v3.15")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
2023-11-16 12:43:48 -05:00
Sean Anderson
23fe0c0747 spl: nand: Fix NULL-pointer dereference
spl_nand_fit_read unconditionally accesses load->priv. Ensure it is set.

Fixes: 00e180cc51 ("spl: nand: support loading i.MX container format file")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
2023-11-16 12:43:48 -05:00
Tom Rini
be0724601a Merge tag 'u-boot-stm32-20231113' of https://source.denx.de/u-boot/custodians/u-boot-stm into next
Introduce STM32MP2 SoCs family support
Add STM32MP257F-EV1 board

[trini: Adjust some includes]
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-11-13 13:35:57 -05:00
Patrice Chotard
01a701994b stm32mp2: initial support
Add initial support for STM32MP2 SoCs family.

SoCs information are available here :
https://www.st.com/content/st_com/en/campaigns/microprocessor-stm32mp2.html

Migrate all MP1 related code into stm32mp1/ directory
Create stm32mp2 directory dedicated for STM32MP2 SoCs.

Common code to MP1, MP13 and MP25 is kept into
arch/arm/mach-stm32/mach-stm32mp directory :
  - boot_params.c
  - bsec
  - cmd_stm32key
  - cmd_stm32prog
  - dram_init.c
  - syscon.c
  - ecdsa_romapi.c

For STM32MP2, it also :
  - adds memory region description needed for ARMv8 MMU.
  - enables early data cache before relocation.
    During the transition before/after relocation, the MMU, initially setup
    at the beginning of DDR, must be setup again at a correct address after
    relocation. This is done in enables_caches() by disabling cache, force
    arch.tlb_fillptr to NULL which will force the MMU to be setup again but
    with a new value for gd->arch.tlb_addr. gd->arch.tlb_addr has been
    updated after relocation in arm_reserve_mmu().

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2023-11-13 10:55:38 +01:00
Patrice Chotard
970d1673b0 ARM: dts: stm32: Add STM32MP257F Evaluation board support
Add STM32MP257F Evaluation board support. It embeds a STM32MP257FAI SoC,
with 4GB of DDR4, TSN switch (2+1 ports), 2*USB typeA, 1*USB2 typeC,
SNOR OctoSPI, mini PCIe, STPMIC2 for power distribution ...

Sync device tree with kernel v6.6-rc1.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2023-11-13 10:55:38 +01:00
Patrice Chotard
778f4eaa80 pinctrl: pinctrl_stm32: Add stm32mp2 support
Add stm32mp2 compatible.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2023-11-13 10:55:38 +01:00
Patrice Chotard
6261cf6abd serial: stm32: Fix AARCH64 compilation warnings
When building with AARCH64 defconfig, we got warnings, fix them
by using registers base address defined as void __iomem * instead of
fdt_addr_t.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2023-11-13 10:55:38 +01:00
Patrice Chotard
3e0b12af8a stm32mp: bsec: Fix AARCH64 compilation warnings
When building with AARCH64 defconfig, we got warnings, fix them.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2023-11-13 10:55:38 +01:00
Patrice Chotard
75ba0fd570 stm32mp: dram_init: Limit DDR usage under 4GB boundary for STM32MP
Limit DDR usage under 4GB boundary on STM32MP regardless of
memory size declared in device tree.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2023-11-13 10:55:38 +01:00
Patrick Delaunay
ee15c72da2 stm32mp: dram_init: Fix AARCH64 compilation warnings
When building with AARCH64 defconfig, we got warnings for debug
message
- format '%x' expects argument of type 'unsigned int',
   but argument 3 has type 'size_t' {aka 'long unsigned int'}).
- format '%lx' expects argument of type 'long unsigned int',
  but argument 2 has type 'phys_addr_t' {aka 'long long unsigned
  int'}

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2023-11-13 10:55:38 +01:00
Patrice Chotard
dba8d92a3d stm32mp: dram_init: Get RAM size from DT if no RAM driver found
In case there is no RAM driver retrieve RAM size from DT as fallback.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2023-11-13 10:55:38 +01:00
Patrice Chotard
2f9886c668 arm: caches: Make DCACHE_DEFAULT_OPTION accessible for ARM64 arch
This fixes the following compilation error in ARM64:
arch/arm/mach-stm32mp/dram_init.c: In function ‘board_get_usable_ram_top’:
arch/arm/mach-stm32mp/dram_init.c:59:45: error: ‘DCACHE_DEFAULT_OPTION’ undeclared (first use in this function)
   59 |  mmu_set_region_dcache_behaviour(reg, size, DCACHE_DEFAULT_OPTION);
      |                                             ^~~~~~~~~~~~~~~~~~~~~

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2023-11-13 10:55:38 +01:00
Tom Rini
3b6db6901f Merge branch '2023-11-10-improve-semihosting-armv6' into next
To quote the author:
This series has a few fixes for semihosting on ARMv6 and older CPUs. The
first two patches address problems regarding the stack pointer and link
register. U-Boot runs in supervisor mode, so taking a software interrupt
will clobber sp/lr. I think we really should run in system mode, since
it has separate sp/lr registers. To quote ARM DDI 0100I:

> The remaining mode is System mode, which is not entered by any
> exception and has exactly the same registers available as User mode.
> However, it is a privileged mode and is therefore not subject to the
> User mode restrictions. It is intended for use by operating system
> tasks that need access to system resources, but wish to avoid using
> the additional registers associated with the exception modes. Avoiding
> such use ensures that the task state is not corrupted by the
> occurrence of any exception.

However, the processor mode has been supervisor for such a long time
(since relocation got introduced) that I would rather not touch it.
2023-11-10 12:52:33 -05:00
Sean Anderson
47cfdb2192 arm: semihosting: Support semihosting fallback on 32-bit ARM
Add support for a semihosting fallback on 32-bit ARM. The assembly is
lightly adapted from the irq return code, except there is no offset
since lr already points to the correct instruction. The C side is mostly
like ARM64, except we have fewer cases to deal with.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2023-11-10 12:52:33 -05:00
Sean Anderson
6ef83ab6be arm: semihosting: Fix returning from traps on ARMv6 and lower
U-Boot runs in supervisor mode. On ARMv6 and lower, software interrupts
are taken in supervisor mode. When entering an interrupt, the link
register is set to the address of the next instruction. However, if we
are already in supervisor mode, this clobbers the link register. The
debugger can't help us, since by the time it notices we've taken a
software interrupt, the link register is already gone. Work around this
by moving the return address to another register.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2023-11-10 12:52:28 -05:00
Sean Anderson
298c26c5c7 arm: Fix software interrupt handler
When we take a software interrupt, we are already in supervisor mode.
get_bad_stack assumes we are not in supervisor mode so it can clobber
the stack pointer. This causes us to have an invalid stack once that
macro finishes. Revert back to the get_bad_stack_swi macro which was
previously removed.

Fixes: 41623c91b0 ("arm: move exception handling out of start.S files")
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2023-11-10 11:55:17 -05:00
Tom Rini
b630f8b3ae scsi: Forceably finish migration to DM_SCSI
The migration deadline for moving to DM_SCSI was v2023.04. A further
reminder was sent out in August 2023 to the remaining platforms that had
not migrated already, and that a few more over the line (or configs
deleted).

With this commit we:
- Rename CONFIG_DM_SCSI to CONFIG_SCSI.
- Remove all of the non-DM SCSI code. This includes removing other
  legacy symbols and code and removes some legacy non-DM AHCI code.
- Some platforms that had previously been DM_SCSI=y && SCSI=n are now
  fully migrated to DM_SCSI as a few corner cases in the code assumed
  DM_SCSI=y meant SCSI=y.

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-11-07 18:36:06 -05:00
Tom Rini
1e4d9dd871 Merge branch '2023-11-07-assorted-big-cleanups' into next
- Merge in changes such that CONFIG_CMDLINE can be disabled and merge
  in a series that starts to remove <common.h> usage.
2023-11-07 18:33:09 -05:00
Tom Rini
d7f592da6e x86: Drop <common.h> from remaining header files
None of these header files need to include <common.h> so we can just
drop that entirely.

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-11-07 14:50:52 -05:00
Tom Rini
e8acfd2bb2 arm: Drop <common.h> from remaining header files
None of these header files need to include <common.h> so we can just
drop that entirely.

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-11-07 14:50:52 -05:00
Tom Rini
4935b15980 sandbox: Drop <common.h>
None of these headers need <common.h> to be included, drop it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-11-07 14:50:52 -05:00
Tom Rini
ac23bb63cf ti: k3: Drop <common.h> usage
None of these files need <common.h> to be included, drop it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-11-07 14:50:52 -05:00
Tom Rini
7f38e9c9a4 include: Drop <common.h> from include lists
At this point, we don't need to have <common.h> be included because of
properties in the header itself, it only includes other common header
files. We've also audited the code enough at this point that we can drop
<common.h> from being included in headers and rely on code to have the
correct inclusions themselves, or at least <common.h>.

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-11-07 14:50:52 -05:00
Tom Rini
c675222d04 include/linux/mii.h: Add <linux/types.h>
As this file uses u8/u16 we need to bring in <linux/types.h> here.

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-11-07 14:50:52 -05:00
Tom Rini
678be88bbe fsl-mc: Add prototype for bd_info
As the functions fsl_mc_ldpaa_init/fsl_mc_ldpaa_exit take a bd_info as
an argument, add a struct bd_info to this header file rather than add
<asm/u-boot.h> to the overall chain.

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-11-07 14:50:52 -05:00
Tom Rini
43f8542193 ls2080aqds: Add missing headers to eth_ls1088aqds.c
As we call sprintf in this file we need to include vsprintf.h in order
to get the function prototype and we need linux/string.h for strcmp.

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-11-07 14:50:52 -05:00
Tom Rini
71b68b2d41 ls1088a: Add missing headers to eth_ls1088aqds.c
As we call sprintf in this file we need to include vsprintf.h in order
to get the function prototype and we need linux/string.h for strcmp.

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-11-07 14:50:52 -05:00
Tom Rini
322ca743d2 pg-wcom-ls102xa: Include <config.h> in the board file
Given that this file references CFG_* defines, we need to be explicit in
our inclusion of config.h, so that these will be defined.

Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-11-07 14:50:52 -05:00
Tom Rini
8db127d983 powerpc: Rework <asm/fsl_lbc.h> includes
This file should not include <config.h> nor should it include <common.h>
so remove both.

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-11-07 14:50:52 -05:00
Tom Rini
2dbb4967b6 qe: Add <asm/ppc.h> on PowerPC
This driver needs <asm/ppc.h> when building on PowerPC, add it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-11-07 14:50:51 -05:00
Tom Rini
639eab42e5 mpc85xx: Add missing include in mpc85xx_sleep.c
This file needs the include file that provides the prototypes for
flush_dcache() and others.

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-11-07 14:50:51 -05:00
Tom Rini
dd1365c2e9 powerpc: mpc83xx: Rework includes slightly
In order to not rely on common.h providing a number of common includes,
cleanup what we include directly in order to be able to drop common.h
later.

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-11-07 14:50:51 -05:00
Tom Rini
362d84c6a2 spi: Add <errno.h> to spi-mem-nodm.c
This file uses errno return values in functions, so include <errno.h>
here rather than rely on indirect inclusion.

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-11-07 14:50:51 -05:00
Tom Rini
3cb2e7cb5a omap3: Add <asm/arch/omap3.h> to <asm/arch/cpu.h>
The include <asm/arch/cpu.h> references values in <asm/arch/omap3.h> and
so include it directly here rather than rely on indirect inclusion.

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-11-07 14:50:51 -05:00
Tom Rini
5faf66a2d1 fsl_qe: Drop common.h
In both include/fsl_qe.h and then also remove common.h from the files
which had included fsl_qe.h

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-11-07 14:50:51 -05:00
Tom Rini
dcda1f27f5 display_options.h: Correct includes
First, a header should never include itself so remove that. Second, this
header needs <linux/types.h> to be included as the function prototypes
use types that we get via that header.

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-11-07 14:50:51 -05:00
Tom Rini
704b6d82ba powerpc: Switch <asm/global_data.h> to <linux/types.h>
In matching other architectures that have their global_data.h need to
bring in a types.h header, switch to <linux/types.h> on PowerPC.

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-11-07 14:50:51 -05:00
Tom Rini
2a7ea65037 m68k: Remove CONFIG_FSLDMAFEC
There are no platforms which enable this feature, so remove it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-11-07 14:50:51 -05:00
Tom Rini
56ea7c8b75 CI, pytest: Add a test for sandbox without LTO
The primary motivation for having a sandbox without LTO build in CI is
to ensure that we don't have that option break. We now have the ability
to run tests of specific options being enabled/disabled, so drop the
parts of CI that build and test that configuration specifically and add
a build test instead. We still test that "NO_LTO=1" rather than editing
the config file works via the ftrace tests.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-11-07 14:49:40 -05:00
Simon Glass
703b5b33cd sandbox: Add a test for disabling CONFIG_CMDLINE
Now that everything is working, add a test to make sure that this
builds correctly.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-11-07 14:49:40 -05:00
Tom Rini
d563bb5d16 clk_k210.c: Clean up how we handle nop
Now that sandbox has <asm/barrier.h> and defines nop() there we should
include that in our driver for clarity and then remove our local nop()
from <k210/pll.h>.

Reviewed-by: Sean Anderson <seanga2@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-11-07 14:49:40 -05:00
Tom Rini
eff0aa47b5 sandbox: Add <asm/barrier.h>
Add a mostly empty asm/barrier.h file for sandbox where we define nop() to
be an empty function.

Reviewed-by: Sean Anderson <seanga2@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-11-07 14:49:40 -05:00
Simon Glass
512369a782 sandbox: Avoid requiring CMDLINE
Add some dependencies on features that we had been selecting so that we
can still disable CMDLINE.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-11-07 14:49:40 -05:00
Simon Glass
909b15ca64 sandbox: Disable CONFIG_DISTRO_DEFAULTS
This is not used for sandbox, so drop it. Enable the things that it
controls to avoid dstrastic changes in the config settings for
sandbox builds.

The end result is that these are enabled:

   BOOTMETH_DISTRO
   BOOTSTD_DEFAULTS

and these are disabled:

   USE_BOOTCOMMAND
   BOOTCOMMAND (was "run distro_bootcmd")
   DISTRO_DEFAULTS

Note that the tools-only build has already disabled DISTRO_DEFAULTS
and BOOTSTD_FULL

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-11-07 14:49:40 -05:00
AKASHI Takahiro
f1b671511e block: rkmtd: select CONFIG_RANDOM_UUID explicitly
This option is necessary to compile any way.

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
2023-11-07 14:49:10 -05:00
AKASHI Takahiro
a4dc3d5699 lib: uuid: move CONFIG_RANDOM_UUID
This option is independent from any commands and should be managed
under lib. For instance, drivers/block/rkmtd.c is a user.

It would be better to remove this configuration.

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-11-07 14:49:10 -05:00
Tom Rini
3165565e5b fastboot: Depend on CMDLINE
Much of the functionality of fastboot relies on being able to run
commands as defined in the environment. This means it does depend on
CMDLINE being enabled.

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-11-07 14:49:10 -05:00
Simon Glass
88d9b2617e cmd: Make most commands depend on CMDLINE
If we disable CMDLINE then we should not ask about enabling the hush
parser nor any of the commands that would be run on the command line as
it is no longer available. Convert the CMDLINE option into a menuconfig
and make every command referenced under cmd/Kconfig depend on it.

This leaves as future work moving the commands that are not under the
cmd/ hierarchy as future work.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-11-07 14:49:09 -05:00
Tom Rini
dbdb4b3374 boot: Make preboot and bootcmd require CMDLINE
In order for a predefined "preboot" or "bootcmd" to be executed by the
running system we must have a command line.  Add CMDLINE as a
dependency.

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-11-07 14:49:09 -05:00
Tom Rini
558787fd58 bootmeth_script: Depend on CMDLINE
As this particular bootmeth requires the command line and assorted
commands to function, make sure we have CMDLINE enabled.

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-11-07 14:49:09 -05:00
Tom Rini
0b59c13a6f bootmeth_cros: Require bootm.o and bootm_os.o
In order to use bootmeth_cros, at least on non-X86, we need to be able
to start any type of kernel that the "bootm" code paths can handle.  Add
these objects to the required list for this option.

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-11-07 14:49:09 -05:00
Tom Rini
9d298c96af boot: Move SYS_BOOTM_LEN to be by LEGACY_IMAGE_FORMAT
This particular option is required for booting all image types,
regardless of if we are starting an OS via command line or something
else.  Move the question for SYS_BOOTM_LEN to be by the question for
LEGACY_IMAGE_FORMAT, as that's where our generic OS questions start.

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-11-07 14:49:09 -05:00
Tom Rini
2180a454fc boot: Rework BOOT_DEFAULTS to allow for CMDLINE to be disabled
We split BOOT_DEFAULTS to have BOOT_DEFAULTS_FEATURES and
BOOT_DEFAULTS_CMDS that in turn list general features or commands that
we want enabled when BOOT_DEFAULTS is selected.  We only select
BOOT_DEFAULTS_CMDS if CMDLINE is set.

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-11-07 14:48:51 -05:00
Tom Rini
fc97d93058 boot: Make DISTRO_DEFAULTS select CMDLINE
The implementation of DISTRO_DEFAULTS is done in environment scripts and
requires the command line in order to work. Because of this, select
CMDLINE here.

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-11-07 14:48:51 -05:00
Simon Glass
5bcfc7ab65 autoboot: Correct dependencies on CMDLINE
Make AUTOBOOT depend on CMDLINE since it is mostly meaningless without it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-11-07 14:48:51 -05:00
Tom Rini
0bb4abd5d0 bootmeth: Make BOOTMETH_EFILOADER depend on CMD_BOOTEFI
Today, the bootmeth for using the EFI loader via bootefi depends on
calling the bootefi command directly, so make this in turn depend on
CMD_BOOTEFI.

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-11-07 14:48:51 -05:00
Simon Glass
422822cfc0 efi: Rearrange the Kconfig for CMD_BOOTEFI_BOOTMGR
The command should not be used to enable library functionality. Add a
new BOOTEFI_BOOTMGR Kconfig for that. Adjust the conditions so that the
same code is built.

Signed-off-by: Simon Glass <sjg@chromium.org>
Suggested-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
2023-11-07 14:48:51 -05:00
Tom Rini
2cb52fbf1d cli_simple: Rework this support slightly
The interactive portion of our non-HUSH 'simple' parser is guarded by
CONFIG_CMDLINE already.  Much of the code behind this simple parser is
also used as "input" parser, such as from menu interfaces and so forth
and not strictly command line input.  To support this, always build the
assorted cli object files, but guard the interactive portions of
cli_simple.c with a CMDLINE check.

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-11-07 14:48:51 -05:00
Simon Glass
d83f4e6265 video: Don't require the font command
While it is nice to have the font command, using 'select' makes it
impossible to build the console code without it. Stop using 'select' and
make it default if CONSOLE_TRUETYPE is enabled when asking the command.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-11-07 14:48:51 -05:00
Simon Glass
8b888917ca test: Make UNIT_TEST depend on CMDLINE
Many tests make some use of the command line, so require it for all test
code.

This could be teased apart, perhaps with a test flag indicating that it
uses the command line. Leave that for later.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-11-07 14:48:19 -05:00
Tom Rini
d972192520 env: Move env_set() out of cmd/nvedit.c and in to env/common.c
Inside of env/common.c we already have our helper env_set_xxx functions,
and even have a comment that explains why env_set() itself wasn't moved.
We now handle that move. This requires that we rename the previous
_do_env_set() to env_do_env_set() and note it as an internal env
function. Add comments about this function to explain why we do this
when we add the prototype. Add a new function, env_inc_id() to allow for
the counter to be updated by both commands and callers, and document
this as well by the prototype.

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-11-07 14:48:19 -05:00
Tom Rini
d900449a7a Kconfig: Move CONFIG_SYS_[CP]BSIZE to common/Kconfig
Move CONFIG_SYS_CBSIZE (console buffer size) and CONFIG_SYS_PBSIZE
(console print buffer size) out of cmd/Kconfig and in to common/Kconfig.
Create help entries for both which explain their usage and why they are
both not entirely command centric.

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-11-07 14:48:19 -05:00
Tom Rini
bfaa048d94 qemu: Correct CMD_QFW dependencies in Kconfig
Rather than selecting CMD_QFW, we should make the option itself by
enabled by default on these platforms.  Then in the board-specific
Kconfig we should select the appropriate back-end as needed if the
command is enabled.

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-11-07 14:48:19 -05:00
Tom Rini
54ecce2cbf version: Separate our version string from the version command
In order to be able to disable all commands we need to construct our
version string in a common file, and have the version command reference
that string, like the other users of it do.  Create common/version.c
with just the strings.

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-11-07 14:48:19 -05:00
Tom Rini
9f8b1508ca dfu: Make DFU_TFTP depend on NETDEVICES
In order to do a DFU update over TFTP we need to have some network
device available, so make this depend on NETDEVICES

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-11-07 14:48:19 -05:00
Tom Rini
a8a53cfa8d virtio: Make VIRTIO_NET depend on NETDEVICES
As VIRTIO_NET is the symbol for enabling network devices, make this
depend on NETDEVICES

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-11-07 14:48:19 -05:00
Simon Glass
dc314185be buildman: Use oldconfig when adjusting the config
We cannot be sure that the new config is consistent, particularly when
changing a major item like CONFIG_CMDLINE. Use 'make oldconfig' to
check that and avoid any such problems.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-11-07 14:48:19 -05:00
3553 changed files with 119606 additions and 43371 deletions

View File

@@ -2,7 +2,7 @@ variables:
windows_vm: windows-2019
ubuntu_vm: ubuntu-22.04
macos_vm: macOS-12
ci_runner_image: trini/u-boot-gitlab-ci-runner:jammy-20230804-25Aug2023
ci_runner_image: trini/u-boot-gitlab-ci-runner:jammy-20240125-12Feb2024
# Add '-u 0' options for Azure pipelines, otherwise we get "permission
# denied" error when it tries to "useradd -m -u 1001 vsts_azpcontainer",
# since our $(ci_runner_image) user is not root.
@@ -236,10 +236,9 @@ stages:
cp images/spi-nor.img \${UBOOT_TRAVIS_BUILD_DIR}/;
fi
if [[ "\${TEST_PY_BD}" == "coreboot" ]]; then
wget -O - "https://drive.google.com/uc?id=1uJ2VkUQ8czWFZmhJQ90Tp8V_zrJ6BrBH&export=download" |xz -dc >\${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom;
wget -O - "https://drive.google.com/uc?id=149Cz-5SZXHNKpi9xg6R_5XITWohu348y&export=download" >cbfstool;
chmod a+x cbfstool;
./cbfstool \${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom add-flat-binary -f \${UBOOT_TRAVIS_BUILD_DIR}/u-boot.bin -n fallback/payload -c LZMA -l 0x1110000 -e 0x1110000;
cp /opt/coreboot/coreboot.rom \${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom;
/opt/coreboot/cbfstool \${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom remove -n fallback/payload;
/opt/coreboot/cbfstool \${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom add-flat-binary -f \${UBOOT_TRAVIS_BUILD_DIR}/u-boot.bin -n fallback/payload -c LZMA -l 0x1110000 -e 0x1110000;
fi
virtualenv -p /usr/bin/python3 /tmp/venv
. /tmp/venv/bin/activate
@@ -287,9 +286,6 @@ stages:
sandbox64_clang:
TEST_PY_BD: "sandbox64"
OVERRIDE: "-O clang-16"
sandbox_nolto:
TEST_PY_BD: "sandbox"
BUILD_ENV: "NO_LTO=1"
sandbox_spl:
TEST_PY_BD: "sandbox_spl"
TEST_PY_TEST_SPEC: "test_ofplatdata or test_handoff or test_spl"

View File

@@ -10,7 +10,7 @@ default:
# Grab our configured image. The source for this is found
# in the u-boot tree at tools/docker/Dockerfile
image: ${MIRROR_DOCKER}/trini/u-boot-gitlab-ci-runner:jammy-20230804-25Aug2023
image: ${MIRROR_DOCKER}/trini/u-boot-gitlab-ci-runner:jammy-20240125-12Feb2024
# We run some tests in different order, to catch some failures quicker.
stages:
@@ -70,14 +70,9 @@ stages:
cp images/spi-nor.img ${UBOOT_TRAVIS_BUILD_DIR}/;
fi
- if [[ "${TEST_PY_BD}" == "coreboot" ]]; then
wget -O -
"https://drive.google.com/uc?id=1uJ2VkUQ8czWFZmhJQ90Tp8V_zrJ6BrBH&export=download" |
xz -dc >${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom;
wget -O -
"https://drive.google.com/uc?id=149Cz-5SZXHNKpi9xg6R_5XITWohu348y&export=download" >
cbfstool;
chmod a+x cbfstool;
./cbfstool ${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom add-flat-binary -f ${UBOOT_TRAVIS_BUILD_DIR}/u-boot.bin -n fallback/payload -c LZMA -l 0x1110000 -e 0x1110000;
cp /opt/coreboot/coreboot.rom ${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom;
/opt/coreboot/cbfstool ${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom remove -n fallback/payload;
/opt/coreboot/cbfstool ${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom add-flat-binary -f ${UBOOT_TRAVIS_BUILD_DIR}/u-boot.bin -n fallback/payload -c LZMA -l 0x1110000 -e 0x1110000;
fi
- virtualenv -p /usr/bin/python3 /tmp/venv
- . /tmp/venv/bin/activate
@@ -258,12 +253,6 @@ sandbox with clang test.py:
OVERRIDE: "-O clang-16"
<<: *buildman_and_testpy_dfn
sandbox without LTO test.py:
variables:
TEST_PY_BD: "sandbox"
BUILD_ENV: "NO_LTO=1"
<<: *buildman_and_testpy_dfn
sandbox64 test.py:
variables:
TEST_PY_BD: "sandbox64"
@@ -275,12 +264,6 @@ sandbox64 with clang test.py:
OVERRIDE: "-O clang-16"
<<: *buildman_and_testpy_dfn
sandbox64 without LTO test.py:
variables:
TEST_PY_BD: "sandbox64"
BUILD_ENV: "NO_LTO=1"
<<: *buildman_and_testpy_dfn
sandbox_spl test.py:
variables:
TEST_PY_BD: "sandbox_spl"

View File

@@ -57,6 +57,7 @@ John Linn <john.linn@amd.com> <john.linn@xilinx.com>
Jyotheeswar Reddy Mutthareddyvari <jyotheeswar.reddy.mutthareddyvari@amd.com> <jyothee@xilinx.com>
Jyotheeswar Reddy Mutthareddyvari <jyotheeswar.reddy.mutthareddyvari@amd.com> <jyotheeswar.reddy.mutthareddyvari@xilinx.com>
Kalyani Akula <kalyani.akula@amd.com> <kalyani.akula@xilinx.com>
Masahisa Kojima <kojima.masahisa@socionext.com> <masahisa.kojima@linaro.org>
Love Kumar <love.kumar@amd.com> <love.kumar@xilinx.com>
Lukasz Majewski <lukma@denx.de>
Marek Behún <kabel@kernel.org> <marek.behun@nic.cz>

View File

@@ -500,13 +500,14 @@ config BUILD_TARGET
config HAS_BOARD_SIZE_LIMIT
bool "Define a maximum size for the U-Boot image"
default y if RCAR_64
default y if RCAR_32 || RCAR_64
help
In some cases, we need to enforce a hard limit on how big the U-Boot
image itself can be.
config BOARD_SIZE_LIMIT
int "Maximum size of the U-Boot image in bytes"
default 524288 if RCAR_32
default 1048576 if RCAR_64
depends on HAS_BOARD_SIZE_LIMIT
help

View File

@@ -53,13 +53,16 @@ Maintainers List (try to look for most precise areas first)
ACPI:
M: Simon Glass <sjg@chromium.org>
S: Maintained
F: board/emulation/configs/acpi.config
F: cmd/acpi.c
F: lib/acpi/
ANDROID AB
M: Igor Opaniuk <igor.opaniuk@gmail.com>
M: Mattijs Korpershoek <mkorpershoek@baylibre.com>
R: Sam Protsenko <semen.protsenko@linaro.org>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-dfu.git
F: boot/android_ab.c
F: cmd/ab_select.c
F: doc/android/ab.rst
@@ -68,7 +71,9 @@ F: test/py/tests/test_android/test_ab.py
ANDROID AVB
M: Igor Opaniuk <igor.opaniuk@gmail.com>
M: Mattijs Korpershoek <mkorpershoek@baylibre.com>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-dfu.git
F: cmd/avb.c
F: common/avb_verify.c
F: doc/android/avb2.rst
@@ -411,6 +416,8 @@ F: drivers/watchdog/mtk_wdt.c
F: drivers/net/mtk_eth.c
F: drivers/net/mtk_eth.h
F: drivers/reset/reset-mediatek.c
F: include/dt-bindings/clock/mediatek,*
F: include/dt-bindings/power/mediatek,*
F: tools/mtk_image.c
F: tools/mtk_image.h
F: tools/mtk_nand_headers.c
@@ -448,7 +455,7 @@ F: drivers/timer/mchp-pit64b-timer.c
ARM MSC SM2S IMX8MP SOM
M: Martyn Welch <martyn.welch@collabora.com>
M: Ian Ray <ian.ray@ge.com>
M: Ian Ray <ian.ray@gehealthcare.com>
S: Maintained
F: arch/arm/dts/imx8mp-msc-sm2s*
F: board/msc/sm2s_imx8mp/
@@ -490,7 +497,7 @@ M: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
M: Marek Vasut <marek.vasut+renesas@mailbox.org>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-sh.git
F: arch/arm/mach-rmobile/
F: arch/arm/mach-renesas/
F: drivers/clk/renesas/
F: drivers/gpio/gpio-rcar.c
F: drivers/i2c/rcar_*
@@ -560,6 +567,31 @@ F: arch/arm/mach-exynos/
F: arch/arm/mach-s5pc1xx/
F: arch/arm/cpu/armv7/s5p-common/
ARM SAMSUNG CLOCK
M: Sam Protsenko <semen.protsenko@linaro.org>
S: Maintained
F: drivers/clk/exynos/clk-pll.c
F: drivers/clk/exynos/clk-pll.h
F: drivers/clk/exynos/clk.c
F: drivers/clk/exynos/clk.h
ARM SAMSUNG EXYNOS850 SOC
M: Sam Protsenko <semen.protsenko@linaro.org>
S: Maintained
F: arch/arm/dts/exynos850-pinctrl.dtsi
F: arch/arm/dts/exynos850.dtsi
F: doc/device-tree-bindings/clock/samsung,exynos850-clock.yaml
F: drivers/clk/exynos/clk-exynos850.c
F: drivers/pinctrl/exynos/pinctrl-exynos850.c
F: include/dt-bindings/clock/exynos850.h
ARM SAMSUNG SOC DRIVERS
M: Sam Protsenko <semen.protsenko@linaro.org>
S: Maintained
F: doc/device-tree-bindings/soc/samsung/*
F: drivers/soc/samsung/*
F: include/dt-bindings/soc/samsung,*.h
ARM SANCLOUD
M: Paul Barker <paul.barker@sancloud.com>
R: Marc Murphy <marc.murphy@sancloud.com>
@@ -572,9 +604,12 @@ M: Neil Armstrong <neil.armstrong@linaro.org>
R: Sumit Garg <sumit.garg@linaro.org>
S: Maintained
F: arch/arm/mach-snapdragon/
F: drivers/button/button-qcom-pmic.c
F: drivers/clk/qcom/
F: drivers/gpio/msm_gpio.c
F: drivers/mmc/msm_sdhci.c
F: drivers/phy/msm8916-usbh-phy.c
F: drivers/pinctrl/qcom/
F: drivers/serial/serial_msm.c
F: drivers/serial/serial_msm_geni.c
F: drivers/smem/msm_smem.c
@@ -982,7 +1017,7 @@ EFI APP
M: Simon Glass <sjg@chromium.org>
M: Heinrich Schuchardt <xypron.glpk@gmx.de>
S: Maintained
W: https://u-boot.readthedocs.io/en/latest/develop/uefi/u-boot_on_efi.html
W: https://docs.u-boot.org/en/latest/develop/uefi/u-boot_on_efi.html
F: board/efi/efi-x86_app
F: configs/efi-x86_app*
F: doc/develop/uefi/u-boot_on_efi.rst
@@ -1555,6 +1590,11 @@ M: Liviu Dudau <liviu.dudau@foss.arm.com>
S: Maintained
F: drivers/video/tda19988.c
TI LP5562 LED DRIVER
M: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
S: Supported
F: drivers/led/led_lp5562.c
TI SYSTEM SECURITY
M: Andrew F. Davis <afd@ti.com>
S: Supported

View File

@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0+
VERSION = 2024
PATCHLEVEL = 01
PATCHLEVEL = 04
SUBLEVEL =
EXTRAVERSION =
NAME =
@@ -750,6 +750,7 @@ endif
ifeq ($(CONFIG_STACKPROTECTOR),y)
KBUILD_CFLAGS += $(call cc-option,-fstack-protector-strong)
KBUILD_CFLAGS += $(call cc-option,-mstack-protector-guard=global)
CFLAGS_EFI += $(call cc-option,-fno-stack-protector)
else
KBUILD_CFLAGS += $(call cc-option,-fno-stack-protector)
@@ -851,7 +852,7 @@ HAVE_VENDOR_COMMON_LIB = $(if $(wildcard $(srctree)/board/$(VENDOR)/common/Makef
libs-$(CONFIG_API) += api/
libs-$(HAVE_VENDOR_COMMON_LIB) += board/$(VENDOR)/common/
libs-y += boot/
libs-y += cmd/
libs-$(CONFIG_CMDLINE) += cmd/
libs-y += common/
libs-$(CONFIG_OF_EMBED) += dts/
libs-y += env/
@@ -1153,7 +1154,6 @@ endif
@# is enable to tell 'deprecated' that one of these symbols exists
$(call deprecated,CONFIG_TIMER,Timer drivers,v2023.01,$(if $(strip $(CFG_SYS_TIMER_RATE)$(CFG_SYS_TIMER_COUNTER)),x))
$(call deprecated,CONFIG_DM_SERIAL,Serial drivers,v2023.04,$(CONFIG_SERIAL))
$(call deprecated,CONFIG_DM_SCSI,SCSI drivers,v2023.04,$(CONFIG_SCSI))
@# Check that this build does not override OF_HAS_PRIOR_STAGE by
@# disabling OF_BOARD.
$(call cmd,ofcheck,$(KCONFIG_CONFIG))
@@ -1266,7 +1266,7 @@ spl/u-boot-spl.srec: spl/u-boot-spl FORCE
$(call if_changed,objcopy)
%.scif: %.srec
$(Q)$(MAKE) $(build)=arch/arm/mach-rmobile $@
$(Q)$(MAKE) $(build)=arch/arm/mach-renesas $@
OBJCOPYFLAGS_u-boot-nodtb.bin := -O binary \
$(if $(CONFIG_X86_16BIT_INIT),-R .start16 -R .resetvec) \
@@ -1349,6 +1349,7 @@ cmd_binman = $(srctree)/tools/binman/binman $(if $(BINMAN_DEBUG),-D) \
$(foreach f,$(BINMAN_INDIRS),-I $(f)) \
-a atf-bl31-path=${BL31} \
-a tee-os-path=${TEE} \
-a ti-dm-path=${TI_DM} \
-a opensbi-path=${OPENSBI} \
-a default-dt=$(default_dt) \
-a scp-path=$(SCP) \
@@ -2195,6 +2196,8 @@ clean: $(clean-dirs)
@find $(if $(KBUILD_EXTMOD), $(KBUILD_EXTMOD), .) $(RCS_FIND_IGNORE) \
\( -name '*.[oas]' -o -name '*.ko' -o -name '.*.cmd' \
-o -name '*.ko.*' -o -name '*.su' -o -name '*.pyc' \
-o -name '*.dtb' -o -name '*.dtbo' \
-o -name '*.dtb.S' -o -name '*.dtbo.S' \
-o -name '.*.d' -o -name '.*.tmp' -o -name '*.mod.c' \
-o -name '*.lex.c' -o -name '*.tab.[ch]' \
-o -name '*.asn1.[ch]' \

47
README
View File

@@ -300,13 +300,6 @@ The following options need to be configured:
different from COUNTER_FREQUENCY, and can only be determined
at run time.
- Tegra SoC options:
CONFIG_TEGRA_SUPPORT_NON_SECURE
Support executing U-Boot in non-secure (NS) mode. Certain
impossible actions will be skipped if the CPU is in NS mode,
such as ARM architectural timer initialization.
- Linux Kernel Interface:
CONFIG_OF_LIBFDT
@@ -1191,11 +1184,10 @@ The following options need to be configured:
Support for a lightweight UBI (fastmap) scanner and
loader
CONFIG_SYS_NAND_5_ADDR_CYCLE, CONFIG_SYS_NAND_PAGE_COUNT,
CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE,
CONFIG_SYS_NAND_BLOCK_SIZE, CONFIG_SYS_NAND_BAD_BLOCK_POS,
CFG_SYS_NAND_ECCPOS, CFG_SYS_NAND_ECCSIZE,
CFG_SYS_NAND_ECCBYTES
CONFIG_SYS_NAND_5_ADDR_CYCLE, CONFIG_SYS_NAND_PAGE_SIZE,
CONFIG_SYS_NAND_OOBSIZE, CONFIG_SYS_NAND_BLOCK_SIZE,
CONFIG_SYS_NAND_BAD_BLOCK_POS, CFG_SYS_NAND_ECCPOS,
CFG_SYS_NAND_ECCSIZE, CFG_SYS_NAND_ECCBYTES
Defines the size and behavior of the NAND that SPL uses
to read U-Boot
@@ -1248,9 +1240,6 @@ typically in board_init_f() and board_init_r().
Configuration Settings:
-----------------------
- MEM_SUPPORT_64BIT_DATA: Defined automatically if compiled as 64-bit.
Optionally it can be defined to support 64-bit memory commands.
- CONFIG_SYS_LONGHELP: Defined when you want long help messages included;
undefine this when you're short of memory.
@@ -1545,16 +1534,26 @@ Low Level (hardware related) configuration options:
globally (CONFIG_CMD_MEMORY).
- CONFIG_SPL_BUILD
Set when the currently-running compilation is for an artifact
that will end up in the SPL (as opposed to the TPL or U-Boot
proper). Code that needs stage-specific behavior should check
this.
Set when the currently running compilation is for an artifact
that will end up in one of the 'xPL' builds, i.e. SPL, TPL or
VPL. Code that needs phase-specific behaviour can check this,
or (where possible) use spl_phase() instead.
Note that CONFIG_SPL_BUILD *is* always defined when either
of CONFIG_TPL_BUILD / CONFIG_VPL_BUILD is defined. This can be
counter-intuitive and should perhaps be changed.
- CONFIG_TPL_BUILD
Set when the currently-running compilation is for an artifact
that will end up in the TPL (as opposed to the SPL or U-Boot
proper). Code that needs stage-specific behavior should check
this.
Set when the currently running compilation is for an artifact
that will end up in the TPL build (as opposed to SPL, VPL or
U-Boot proper). Code that needs phase-specific behaviour can
check this, or (where possible) use spl_phase() instead.
- CONFIG_VPL_BUILD
Set when the currently running compilation is for an artifact
that will end up in the VPL build (as opposed to the SPL, TPL
or U-Boot proper). Code that needs phase-specific behaviour can
check this, or (where possible) use spl_phase() instead.
- CONFIG_ARCH_MAP_SYSMEM
Generally U-Boot (and in particular the md command) uses
@@ -2650,5 +2649,5 @@ Contributing
The U-Boot projects depends on contributions from the user community.
If you want to participate, please, have a look at the 'General'
section of https://u-boot.readthedocs.io/en/latest/develop/index.html
section of https://docs.u-boot.org/en/latest/develop/index.html
where we describe coding standards and the patch submission process.

View File

@@ -67,13 +67,6 @@ void dev_stor_init(void)
specs[ENUM_SATA].type = DEV_TYP_STOR | DT_STOR_SATA;
specs[ENUM_SATA].name = "sata";
#endif
#if defined(CONFIG_SCSI)
specs[ENUM_SCSI].max_dev = SCSI_MAX_DEVICE;
specs[ENUM_SCSI].enum_started = 0;
specs[ENUM_SCSI].enum_ended = 0;
specs[ENUM_SCSI].type = DEV_TYP_STOR | DT_STOR_SCSI;
specs[ENUM_SCSI].name = "scsi";
#endif
#if defined(CONFIG_CMD_USB) && defined(CONFIG_USB_STORAGE)
specs[ENUM_USB].max_dev = USB_MAX_STOR_DEV;
specs[ENUM_USB].enum_started = 0;

View File

@@ -108,6 +108,7 @@ config PPC
config RISCV
bool "RISC-V architecture"
select CREATE_ARCH_SYMLINK
select SUPPORT_ACPI
select SUPPORT_OF_CONTROL
select OF_CONTROL
select DM
@@ -134,7 +135,7 @@ config SANDBOX
select ARCH_SUPPORTS_LTO
select BOARD_LATE_INIT
select BZIP2
select CMD_POWEROFF
select CMD_POWEROFF if CMDLINE
select DM
select DM_EVENT
select DM_FUZZING_ENGINE
@@ -148,14 +149,15 @@ config SANDBOX
select GZIP_COMPRESSED
select IO_TRACE
select LZO
select MTD
select OF_BOARD_SETUP
select PCI_ENDPOINT
select SPI
select SUPPORT_OF_CONTROL
select SYSRESET_CMD_POWEROFF
select SYSRESET_CMD_POWEROFF if CMD_POWEROFF
select SYS_CACHE_SHIFT_4
select IRQ
select SUPPORT_EXTENSION_SCAN
select SUPPORT_EXTENSION_SCAN if CMDLINE
select SUPPORT_ACPI
imply BITREVERSE
select BLOBLIST
@@ -210,6 +212,9 @@ config SANDBOX
imply BINMAN
imply CMD_MBR
imply CMD_MMC
imply BOOTSTD_DEFAULTS if BOOTSTD_FULL && CMDLINE
imply BOOTMETH_DISTRO if BOOTSTD_FULL && CMDLINE
imply CMD_SYSBOOT if BOOTSTD_FULL
config SH
bool "SuperH architecture"
@@ -248,8 +253,9 @@ config X86
imply DM_KEYBOARD
imply DM_MMC
imply DM_RTC
imply DM_SCSI
imply SCSI
imply DM_SERIAL
imply MTD
imply DM_SPI
imply DM_SPI_FLASH
imply DM_USB

View File

@@ -13,8 +13,6 @@
#define __ARC_BCR_H
#ifndef __ASSEMBLY__
#include <config.h>
union bcr_di_cache {
struct {
#ifdef CONFIG_CPU_BIG_ENDIAN

View File

@@ -7,7 +7,6 @@
#define _ASM_ARC_ARCREGS_H
#include <asm/cache.h>
#include <config.h>
/*
* ARC architecture has additional address space - auxiliary registers.

View File

@@ -6,8 +6,6 @@
#ifndef __ASM_ARC_CACHE_H
#define __ASM_ARC_CACHE_H
#include <config.h>
/*
* As of today we may handle any L1 cache line length right in software.
* For that essentially cache line length is a variable not constant.

View File

@@ -3,6 +3,7 @@
* Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
*/
#include <bootm.h>
#include <bootstage.h>
#include <env.h>
#include <image.h>
@@ -78,8 +79,10 @@ static void boot_jump_linux(struct bootm_headers *images, int flag)
board_jump_and_run(kernel_entry, r0, 0, r2);
}
int do_bootm_linux(int flag, int argc, char *argv[], struct bootm_headers *images)
int do_bootm_linux(int flag, struct bootm_info *bmi)
{
struct bootm_headers *images = bmi->images;
/* No need for those on ARC */
if ((flag & BOOTM_STATE_OS_BD_T) || (flag & BOOTM_STATE_OS_CMDLINE))
return -1;

View File

@@ -3,6 +3,7 @@
* Copyright (C) 2013-2014, 2018 Synopsys, Inc. All rights reserved.
*/
#include <config.h>
#include <clock_legacy.h>
#include <init.h>
#include <malloc.h>

View File

@@ -79,6 +79,15 @@ config SPL_SYS_NO_VECTOR_TABLE
depends on SPL
bool
config SPL_USE_SEPARATE_FAULT_HANDLERS
bool "Use separate fault handlers instead of a single common one"
depends on !SPL_SYS_NO_VECTOR_TABLE && !ARM64 && !CPU_V7M
help
Instead of a common fault handler, generate a separate one for
undefined_instruction, software_interrupt, prefetch_abort etc.
This is for debugging purposes, when you want to set breakpoints
on them separately.
config LINUX_KERNEL_IMAGE_HEADER
depends on ARM64
bool
@@ -568,6 +577,7 @@ config ARCH_AT91
select GPIO_EXTRA_HEADER
select SPL_BOARD_INIT if SPL && !TARGET_SMARTWEB
select SPL_SEPARATE_BSS if SPL
imply SYS_THUMB_BUILD
config ARCH_DAVINCI
bool "TI DaVinci"
@@ -604,6 +614,7 @@ config ARCH_MVEBU
select DM_SPI
select DM_SPI_FLASH
select GPIO_EXTRA_HEADER
select MTD
select SPL_DM_SPI if SPL
select SPL_DM_SPI_FLASH if SPL
select SPL_TIMER if SPL
@@ -629,6 +640,7 @@ config TARGET_STV0991
select DM_SPI_FLASH
select GPIO_EXTRA_HEADER
select PL01X_SERIAL
select MTD
select SPI
select SPI_FLASH
imply CMD_DM
@@ -666,7 +678,7 @@ config ARCH_BCMBCA
config TARGET_VEXPRESS_CA9X4
bool "Support vexpress_ca9x4"
select CPU_V7A
select PL011_SERIAL
select PL01X_SERIAL
config TARGET_BCMNS
bool "Support Broadcom Northstar"
@@ -714,6 +726,7 @@ config ARCH_EXYNOS
select DM_SERIAL
select DM_SPI
select DM_SPI_FLASH
select MTD
select SPI
select GPIO_EXTRA_HEADER
imply SYS_THUMB_BUILD
@@ -766,19 +779,27 @@ config ARCH_IPQ40XX
select CLK
select SMEM
select OF_CONTROL
select CLK_QCOM_IPQ4019
select PINCTRL_QCOM_IPQ4019
imply CMD_DM
config ARCH_KEYSTONE
bool "TI Keystone"
select CMD_DDR3
select CMD_POWEROFF
select CPU_V7A
select DDR_SPD
select SPL_BOARD_INIT if SPL
select SUPPORT_SPL
select SYS_ARCH_TIMER
select SYS_THUMB_BUILD
imply CMD_MTDPARTS
imply CMD_NFS
imply CMD_SAVES
imply DM_I2C
imply FIT
imply SOC_TI
imply TI_KEYSTONE_SERDES
config ARCH_K3
bool "Texas Instruments' K3 Architecture"
@@ -996,6 +1017,7 @@ config ARCH_APPLE
select VIDEO
select IOMMU
select LINUX_KERNEL_IMAGE_HEADER
select MTD
select OF_BOARD_SETUP
select OF_CONTROL
select PCI
@@ -1049,11 +1071,12 @@ config ARCH_QEMU
imply USB_KEYBOARD
imply CMD_USB
config ARCH_RMOBILE
config ARCH_RENESAS
bool "Renesas ARM SoCs"
select DM
select DM_SERIAL
select GPIO_EXTRA_HEADER
select LTO
imply BOARD_EARLY_INIT_F
imply CMD_DM
imply FAT_WRITE
@@ -1066,6 +1089,7 @@ config ARCH_SNAPDRAGON
select DM
select DM_GPIO
select DM_SERIAL
select DM_RESET
select GPIO_EXTRA_HEADER
select MSM_SMEM
select OF_CONTROL
@@ -1107,6 +1131,7 @@ config ARCH_SOCFPGA
imply DM_SPI
imply DM_SPI_FLASH
imply FAT_WRITE
imply MTD
imply SPL
imply SPL_DM
imply SPL_DM_SPI
@@ -1130,10 +1155,9 @@ config ARCH_SUNXI
select DM_GPIO
select DM_I2C if I2C
select DM_SPI if SPI
select DM_SPI_FLASH if SPI
select DM_SPI_FLASH if SPI && MTD
select DM_KEYBOARD
select DM_MMC if MMC
select DM_SCSI if SCSI
select DM_SERIAL
select OF_BOARD_SETUP
select OF_CONTROL
@@ -1143,14 +1167,14 @@ config ARCH_SUNXI
select SPL_SEPARATE_BSS if SPL
select SPL_STACK_R if SPL
select SPL_SYS_MALLOC_SIMPLE if SPL
select SPL_SYS_THUMB_BUILD if !ARM64
select SPL_SYS_THUMB_BUILD if SPL && !ARM64
select SUNXI_GPIO
select SYS_NS16550
select SYS_THUMB_BUILD if !ARM64
select USB if DISTRO_DEFAULTS
select USB_KEYBOARD if DISTRO_DEFAULTS && USB_HOST
select USB_STORAGE if DISTRO_DEFAULTS && USB_HOST
select SPL_USE_TINY_PRINTF
select SPL_USE_TINY_PRINTF if SPL
select USE_PREBOOT
select SYS_RELOC_GD_ENV_ADDR
imply BOARD_LATE_INIT
@@ -1249,6 +1273,7 @@ config ARCH_ZYNQ
select DM_SPI
select DM_SPI_FLASH
select OF_CONTROL
select MTD
select SPI
select SPL_BOARD_INIT if SPL
select SPL_CLK if SPL
@@ -1287,6 +1312,7 @@ config ARCH_ZYNQMP
imply DM_MAILBOX
select DM_MMC if MMC
select DM_SERIAL
select MTD
select DM_SPI if SPI
select DM_SPI_FLASH if DM_SPI
imply FIRMWARE
@@ -1833,12 +1859,13 @@ config TARGET_SL28
select DM_GPIO
select DM_I2C
select DM_MMC
select MTD
select DM_SPI_FLASH
select DM_MDIO
select PCI
select DM_RNG
select DM_RTC
select DM_SCSI
select SCSI
select DM_SERIAL
select DM_SPI
select GPIO_EXTRA_HEADER
@@ -1945,7 +1972,7 @@ config ARCH_STM32MP
select REGMAP
select SYSCON
select SYSRESET
select SYS_THUMB_BUILD
select SYS_THUMB_BUILD if !ARM64
imply SPL_SYSRESET
imply CMD_DM
imply CMD_POWEROFF
@@ -1974,8 +2001,10 @@ config ARCH_ROCKCHIP
select DM_SERIAL
select DM_SPI
select DM_SPI_FLASH
select DM_USB_GADGET if USB_DWC3_GADGET
select ENABLE_ARM_SOC_BOOT0_HOOK
select OF_CONTROL
select MTD
select SPI
select SPL_DM if SPL
select SPL_DM_SPI if SPL
@@ -2053,13 +2082,18 @@ config TARGET_POMELO
select PCI
select DM_PCI
select SCSI
select DM_SCSI
select DM_SERIAL
imply CMD_PCI
help
Support for pomelo platform.
It has 8GB Sdram, uart and pcie.
config TARGET_PE2201
bool "Support Phytium PE2201 Platform"
select ARM64
help
Support for pe2201 platform.It has 2GB Sdram, uart and pcie.
config TARGET_PRESIDIO_ASIC
bool "Support Cortina Presidio ASIC Platform"
select ARM64
@@ -2235,7 +2269,7 @@ source "arch/arm/mach-orion5x/Kconfig"
source "arch/arm/mach-owl/Kconfig"
source "arch/arm/mach-rmobile/Kconfig"
source "arch/arm/mach-renesas/Kconfig"
source "arch/arm/mach-meson/Kconfig"
@@ -2336,6 +2370,7 @@ source "board/variscite/dart_6ul/Kconfig"
source "board/vscom/baltos/Kconfig"
source "board/phytium/durian/Kconfig"
source "board/phytium/pomelo/Kconfig"
source "board/phytium/pe2201/Kconfig"
source "board/xen/xenguest_arm64/Kconfig"
source "arch/arm/Kconfig.debug"

View File

@@ -75,7 +75,7 @@ machine-$(CONFIG_ARCH_NPCM) += npcm
machine-$(CONFIG_ARCH_OMAP2PLUS) += omap2
machine-$(CONFIG_ARCH_ORION5X) += orion5x
machine-$(CONFIG_ARCH_OWL) += owl
machine-$(CONFIG_ARCH_RMOBILE) += rmobile
machine-$(CONFIG_ARCH_RENESAS) += renesas
machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip
machine-$(CONFIG_ARCH_S5PC1XX) += s5pc1xx
machine-$(CONFIG_ARCH_SNAPDRAGON) += snapdragon

View File

@@ -71,6 +71,7 @@ void reset_cpu(void)
* actually 0x20, this the associated <destination address>. Loading the PC
* register with an address performs a jump to that address.
*/
noinline __attribute__((target("arm")))
void mx28_fixup_vt(uint32_t start_addr)
{
/* ldr pc, [pc, #0x18] */
@@ -85,6 +86,9 @@ void mx28_fixup_vt(uint32_t start_addr)
/* cppcheck-suppress nullPointer */
vt[i + 8] = start_addr + (4 * i);
}
/* Make sure ARM core points to low vectors */
set_cr(get_cr() & ~CR_V);
}
#ifdef CONFIG_ARCH_MISC_INIT

View File

@@ -17,6 +17,7 @@
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/sections.h>
#include <asm/system.h>
#include <linux/compiler.h>
#include "mxs_init.h"
@@ -93,7 +94,9 @@ static uint8_t mxs_get_bootmode_index(void)
return i;
}
static void mxs_spl_fixup_vectors(void)
static noinline
__attribute__((target("arm")))
void mxs_spl_fixup_vectors(void)
{
/*
* Copy our vector table to 0x0, since due to HAB, we cannot
@@ -104,6 +107,9 @@ static void mxs_spl_fixup_vectors(void)
/* cppcheck-suppress nullPointer */
memcpy(0x0, _start, 0x60);
/* Make sure ARM core points to low vectors */
set_cr(get_cr() & ~CR_V);
}
static void mxs_spl_console_init(void)

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@@ -1177,8 +1177,9 @@ static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg,
if (adjust_up && cfg->bo_irq) {
if (powered_by_linreg) {
bo_int = readl(cfg->reg);
clrbits_le32(cfg->reg, cfg->bo_enirq);
bo_int = readl(&power_regs->hw_power_ctrl);
clrbits_le32(&power_regs->hw_power_ctrl,
cfg->bo_enirq);
}
setbits_le32(cfg->reg, cfg->bo_offset_mask);
}
@@ -1220,7 +1221,8 @@ static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg,
if (adjust_up && powered_by_linreg) {
writel(cfg->bo_irq, &power_regs->hw_power_ctrl_clr);
if (bo_int & cfg->bo_enirq)
setbits_le32(cfg->reg, cfg->bo_enirq);
setbits_le32(&power_regs->hw_power_ctrl,
cfg->bo_enirq);
}
clrsetbits_le32(cfg->reg, cfg->bo_offset_mask,

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@@ -811,6 +811,8 @@ __weak int fsl_setenv_bootcmd(void)
enum boot_src src = get_boot_src();
char bootcmd_str[MAX_BOOTCMD_SIZE];
bootcmd_str[0] = 0;
switch (src) {
#ifdef IFC_NOR_BOOTCOMMAND
case BOOT_SOURCE_IFC_NOR:
@@ -859,6 +861,9 @@ __weak int fsl_setenv_bootcmd(void)
break;
}
if (!bootcmd_str[0])
return 0;
ret = env_set("bootcmd", bootcmd_str);
if (ret) {
printf("Failed to set bootcmd: ret = %d\n", ret);

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@@ -14,9 +14,6 @@ OUTPUT_ARCH(arm)
ENTRY(_start)
SECTIONS
{
#ifndef CONFIG_CMDLINE
/DISCARD/ : { *(__u_boot_list_2_cmd_*) }
#endif
#if defined(CONFIG_ARMV7_SECURE_BASE) && defined(CONFIG_ARMV7_NONSEC)
/*
* If CONFIG_ARMV7_SECURE_BASE is true, secure code will not

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@@ -31,6 +31,7 @@ dtb-$(CONFIG_EXYNOS7420) += exynos7420-espresso7420.dtb
dtb-$(CONFIG_TARGET_A5Y17LTE) += exynos78x0-axy17lte.dtb
dtb-$(CONFIG_TARGET_A3Y17LTE) += exynos78x0-axy17lte.dtb
dtb-$(CONFIG_TARGET_A7Y17LTE) += exynos78x0-axy17lte.dtb
dtb-$(CONFIG_TARGET_E850_96) += exynos850-e850-96.dtb
dtb-$(CONFIG_ARCH_APPLE) += \
t8103-j274.dtb \
@@ -126,6 +127,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \
dtb-$(CONFIG_ROCKCHIP_RK3328) += \
rk3328-evb.dtb \
rk3328-nanopi-r2c.dtb \
rk3328-nanopi-r2c-plus.dtb \
rk3328-nanopi-r2s.dtb \
rk3328-orangepi-r1-plus.dtb \
rk3328-orangepi-r1-plus-lts.dtb \
@@ -180,6 +182,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \
rk3566-soquartz-model-a.dtb \
rk3568-bpi-r2-pro.dtb \
rk3568-evb.dtb \
rk3568-generic.dtb \
rk3568-lubancat-2.dtb \
rk3568-nanopi-r5c.dtb \
rk3568-nanopi-r5s.dtb \
@@ -195,6 +198,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3588) += \
rk3588s-orangepi-5.dtb \
rk3588-orangepi-5-plus.dtb \
rk3588-quartzpro64.dtb \
rk3588-turing-rk1.dtb \
rk3588s-rock-5a.dtb \
rk3588-rock-5b.dtb
@@ -835,7 +839,9 @@ dtb-$(CONFIG_MACH_SUN50I_H6) += \
sun50i-h6-tanix-tx6-mini.dtb
dtb-$(CONFIG_MACH_SUN50I_H616) += \
sun50i-h616-orangepi-zero2.dtb \
sun50i-h618-orangepi-zero2w.dtb \
sun50i-h618-orangepi-zero3.dtb \
sun50i-h618-transpeed-8k618-t.dtb \
sun50i-h616-x96-mate.dtb
dtb-$(CONFIG_MACH_SUN50I) += \
sun50i-a64-amarula-relic.dtb \
@@ -926,6 +932,7 @@ dtb-y += \
imx6dl-riotboard.dtb \
imx6dl-sabreauto.dtb \
imx6dl-sabresd.dtb \
imx6dl-sielaff.dtb \
imx6dl-wandboard-revd1.dtb \
imx6s-dhcom-drc02.dtb
@@ -1075,6 +1082,8 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mm-kontron-bl-osm-s.dtb \
imx8mm-mx8menlo.dtb \
imx8mm-phg.dtb \
imx8mm-phyboard-polis-rdk.dtb \
imx8mm-phygate-tauri-l.dtb \
imx8mm-venice.dtb \
imx8mm-venice-gw71xx-0x.dtb \
imx8mm-venice-gw72xx-0x.dtb \
@@ -1085,7 +1094,6 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mm-venice-gw7904.dtb \
imx8mm-venice-gw7905-0x.dtb \
imx8mm-verdin-wifi-dev.dtb \
phycore-imx8mm.dtb \
imx8mn-bsh-smm-s2.dtb \
imx8mn-bsh-smm-s2pro.dtb \
imx8mn-ddr4-evk.dtb \
@@ -1105,6 +1113,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mp-dhcom-som-overlay-eth1xfast.dtbo \
imx8mp-dhcom-som-overlay-eth2xfast.dtbo \
imx8mp-dhcom-pdk-overlay-eth2xfast.dtbo \
imx8mp-debix-model-a.dtb \
imx8mp-dhcom-pdk2.dtb \
imx8mp-dhcom-pdk3.dtb \
imx8mp-dhcom-pdk3-overlay-rev100.dtbo \
@@ -1124,7 +1133,9 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mq-librem5-r4.dtb
dtb-$(CONFIG_ARCH_IMX9) += \
imx93-11x11-evk.dtb
imx93-11x11-evk.dtb \
imx93-var-som-symphony.dtb \
imx93-phyboard-segin.dtb
dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \
imxrt1020-evk.dtb \
@@ -1164,7 +1175,8 @@ dtb-$(CONFIG_RCAR_GEN3) += \
dtb-$(CONFIG_RCAR_GEN4) += \
r8a779a0-falcon-u-boot.dtb \
r8a779f0-spider-u-boot.dtb \
r8a779g0-white-hawk-u-boot.dtb
r8a779g0-white-hawk-u-boot.dtb \
r8a779h0-gray-hawk-u-boot.dtb
dtb-$(CONFIG_TARGET_RZG2L) += \
r9a07g044l2-smarc.dts
@@ -1358,10 +1370,10 @@ dtb-$(CONFIG_ASPEED_AST2600) += ast2600-evb.dtb
dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb
dtb-$(CONFIG_STM32MP13x) += \
dtb-$(CONFIG_STM32MP13X) += \
stm32mp135f-dk.dtb
dtb-$(CONFIG_STM32MP15x) += \
dtb-$(CONFIG_STM32MP15X) += \
stm32mp157a-dk1.dtb \
stm32mp157a-dk1-scmi.dtb \
stm32mp157a-icore-stm32mp1-ctouch2.dtb \
@@ -1382,6 +1394,9 @@ dtb-$(CONFIG_STM32MP15x) += \
stm32mp15xx-dhcor-drc-compact.dtb \
stm32mp15xx-dhcor-testbench.dtb
dtb-$(CONFIG_STM32MP25X) += \
stm32mp257f-ev1.dtb
dtb-$(CONFIG_SOC_K3_AM654) += \
k3-am654-base-board.dtb \
k3-am654-r5-base-board.dtb \
@@ -1398,7 +1413,10 @@ dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \
k3-j7200-common-proc-board.dtb \
k3-j7200-r5-common-proc-board.dtb \
k3-j721e-sk.dtb \
k3-j721e-r5-sk.dtb
k3-j721e-r5-sk.dtb \
k3-j721e-beagleboneai64.dtb \
k3-j721e-r5-beagleboneai64.dtb
dtb-$(CONFIG_SOC_K3_J721S2) += k3-am68-sk-base-board.dtb\
k3-am68-sk-r5-base-board.dtb\
k3-j721s2-common-proc-board.dtb\
@@ -1413,7 +1431,9 @@ dtb-$(CONFIG_SOC_K3_AM625) += k3-am625-sk.dtb \
k3-am625-beagleplay.dtb \
k3-am625-r5-beagleplay.dtb \
k3-am625-verdin-wifi-dev.dtb \
k3-am625-verdin-r5.dtb
k3-am625-verdin-r5.dtb \
k3-am625-phyboard-lyra-rdk.dtb \
k3-am625-r5-phycore-som-2gb.dtb
dtb-$(CONFIG_SOC_K3_AM62A7) += k3-am62a7-sk.dtb \
k3-am62a7-r5-sk.dtb
@@ -1469,6 +1489,7 @@ dtb-$(CONFIG_TARGET_TOTAL_COMPUTE) += total_compute.dtb
dtb-$(CONFIG_TARGET_DURIAN) += phytium-durian.dtb
dtb-$(CONFIG_TARGET_POMELO) += phytium-pomelo.dtb
dtb-$(CONFIG_TARGET_PE2201) += phytium-pe2201.dtb
dtb-$(CONFIG_TARGET_PRESIDIO_ASIC) += ca-presidio-engboard.dtb

View File

@@ -32,14 +32,17 @@
bootph-all;
};
&eth0 {
/* G.hn does not work without additional configuration */
status = "disabled";
};
&eth1 {
fixed-link {
speed = <1000>;
full-duplex;
};
};
/*
* eDPU v2 has a MV88E6361 switch on the MDIO bus and U-boot is used
* to patch the Linux DTS if its found so enable MDIO by default.
*/
&mdio {
status = "okay";
};

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@@ -12,3 +12,50 @@
&eth0 {
phy-mode = "2500base-x";
};
/*
* External MV88E6361 switch is only available on v2 of the board.
* U-Boot will enable the MDIO bus and switch nodes.
*/
&mdio {
status = "disabled";
pinctrl-names = "default";
pinctrl-0 = <&smi_pins>;
/* Actual device is MV88E6361 */
switch: switch@0 {
compatible = "marvell,mv88e6190";
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "cpu";
phy-mode = "2500base-x";
managed = "in-band-status";
ethernet = <&eth0>;
};
port@9 {
reg = <9>;
label = "downlink";
phy-mode = "2500base-x";
managed = "in-band-status";
};
port@a {
reg = <10>;
label = "uplink";
phy-mode = "2500base-x";
managed = "in-band-status";
sfp = <&sfp_eth1>;
};
};
};
};

View File

@@ -35,6 +35,57 @@
};
};
&mdio {
switch@10 {
mdio {
#address-cells = <1>;
#size-cells = <0>;
sw_phy0: ethernet-phy@0 {
reg = <0x0>;
};
sw_phy1: ethernet-phy@1 {
reg = <0x1>;
};
sw_phy2: ethernet-phy@2 {
reg = <0x2>;
};
sw_phy3: ethernet-phy@3 {
reg = <0x3>;
};
sw_phy4: ethernet-phy@4 {
reg = <0x4>;
};
};
ports {
ports@0 {
phy-handle = <&sw_phy0>;
phy-mode = "internal";
};
ports@1 {
phy-handle = <&sw_phy1>;
phy-mode = "internal";
};
ports@2 {
phy-handle = <&sw_phy2>;
phy-mode = "internal";
};
ports@3 {
phy-handle = <&sw_phy3>;
phy-mode = "internal";
};
ports@4 {
phy-handle = <&sw_phy4>;
phy-mode = "internal";
};
};
};
};
#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
&spi0 {
flash@0 {

View File

@@ -99,6 +99,11 @@
};
&i2c0 {
clock-frequency = <400000>;
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
status = "okay";
eeprom@53 {
compatible = "atmel,24c02";
reg = <0x53>;

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@@ -42,14 +42,3 @@
gpios = <&pm8916_gpios 3 0>;
};
};
&pm8916_pon {
key_vol_down {
gpios = <&pm8916_pon 1 0>;
};
key_power {
gpios = <&pm8916_pon 0 0>;
};
};

View File

@@ -147,20 +147,31 @@
#address-cells = <0x1>;
#size-cells = <0x1>;
pm8916_pon: pm8916_pon@800 {
compatible = "qcom,pm8916-pwrkey";
reg = <0x800 0x96>;
#gpio-cells = <2>;
gpio-controller;
pon@800 {
compatible = "qcom,pm8916-pon";
reg = <0x800 0x100>;
mode-bootloader = <0x2>;
mode-recovery = <0x1>;
pwrkey {
compatible = "qcom,pm8941-pwrkey";
debounce = <15625>;
bias-pull-up;
};
pm8916_resin: resin {
compatible = "qcom,pm8941-resin";
debounce = <15625>;
bias-pull-up;
};
};
pm8916_gpios: pm8916_gpios@c000 {
compatible = "qcom,pm8916-gpio";
reg = <0xc000 0x400>;
gpio-controller;
gpio-count = <4>;
gpio-ranges = <&pm8916_gpios 0 0 4>;
#gpio-cells = <2>;
gpio-bank-name="pmic";
};
};

View File

@@ -30,15 +30,3 @@
};
};
};
&pm8994_pon {
key_vol_down {
gpios = <&pm8994_pon 1 0>;
label = "key_vol_down";
};
key_power {
gpios = <&pm8994_pon 0 0>;
label = "key_power";
};
};

View File

@@ -109,21 +109,31 @@
#address-cells = <0x1>;
#size-cells = <0x1>;
pm8994_pon: pm8994_pon@800 {
compatible = "qcom,pm8994-pwrkey";
reg = <0x800 0x96>;
#gpio-cells = <2>;
gpio-controller;
gpio-bank-name="pm8994_key.";
pm8994_pon: pon@800 {
compatible = "qcom,pm8916-pon";
reg = <0x800 0x100>;
mode-bootloader = <0x2>;
mode-recovery = <0x1>;
pwrkey {
compatible = "qcom,pm8941-pwrkey";
debounce = <15625>;
bias-pull-up;
};
pm8994_resin: resin {
compatible = "qcom,pm8941-resin";
debounce = <15625>;
bias-pull-up;
};
};
pm8994_gpios: pm8994_gpios@c000 {
compatible = "qcom,pm8994-gpio";
reg = <0xc000 0x400>;
gpio-controller;
gpio-count = <24>;
gpio-ranges = <&pm8994_gpios 0 0 22>;
#gpio-cells = <2>;
gpio-bank-name="pm8994.";
};
};

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@@ -19,19 +19,8 @@
bootph-all;
};
pinctrl_north@3900000 {
pinctrl@3400000 {
bootph-all;
};
};
};
&pm8998_pon {
key_vol_down {
gpios = <&pm8998_pon 1 0>;
label = "key_vol_down";
};
key_power {
gpios = <&pm8998_pon 0 0>;
label = "key_power";
};
};

View File

@@ -41,4 +41,8 @@
};
};
&pm8998_resin {
status = "okay";
};
#include "dragonboard845c-uboot.dtsi"

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@@ -0,0 +1,79 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Samsung Exynos DTS pinctrl constants
*
* Copyright (c) 2016 Samsung Electronics Co., Ltd.
* http://www.samsung.com
* Copyright (c) 2022 Linaro Ltd
* Author: Krzysztof Kozlowski <krzk@kernel.org>
*/
#ifndef __DTS_ARM64_SAMSUNG_EXYNOS_PINCTRL_H__
#define __DTS_ARM64_SAMSUNG_EXYNOS_PINCTRL_H__
#define EXYNOS_PIN_PULL_NONE 0
#define EXYNOS_PIN_PULL_DOWN 1
#define EXYNOS_PIN_PULL_UP 3
/* Pin function in power down mode */
#define EXYNOS_PIN_PDN_OUT0 0
#define EXYNOS_PIN_PDN_OUT1 1
#define EXYNOS_PIN_PDN_INPUT 2
#define EXYNOS_PIN_PDN_PREV 3
/*
* Drive strengths for Exynos5410, Exynos542x, Exynos5800, Exynos7885, Exynos850
* (except GPIO_HSI block), ExynosAutov9 (FSI0, PERIC1)
*/
#define EXYNOS5420_PIN_DRV_LV1 0
#define EXYNOS5420_PIN_DRV_LV2 1
#define EXYNOS5420_PIN_DRV_LV3 2
#define EXYNOS5420_PIN_DRV_LV4 3
/* Drive strengths for Exynos5433 */
#define EXYNOS5433_PIN_DRV_FAST_SR1 0
#define EXYNOS5433_PIN_DRV_FAST_SR2 1
#define EXYNOS5433_PIN_DRV_FAST_SR3 2
#define EXYNOS5433_PIN_DRV_FAST_SR4 3
#define EXYNOS5433_PIN_DRV_FAST_SR5 4
#define EXYNOS5433_PIN_DRV_FAST_SR6 5
#define EXYNOS5433_PIN_DRV_SLOW_SR1 8
#define EXYNOS5433_PIN_DRV_SLOW_SR2 9
#define EXYNOS5433_PIN_DRV_SLOW_SR3 0xa
#define EXYNOS5433_PIN_DRV_SLOW_SR4 0xb
#define EXYNOS5433_PIN_DRV_SLOW_SR5 0xc
#define EXYNOS5433_PIN_DRV_SLOW_SR6 0xf
/* Drive strengths for Exynos7 (except FSYS1) */
#define EXYNOS7_PIN_DRV_LV1 0
#define EXYNOS7_PIN_DRV_LV2 2
#define EXYNOS7_PIN_DRV_LV3 1
#define EXYNOS7_PIN_DRV_LV4 3
/* Drive strengths for Exynos7 FSYS1 block */
#define EXYNOS7_FSYS1_PIN_DRV_LV1 0
#define EXYNOS7_FSYS1_PIN_DRV_LV2 4
#define EXYNOS7_FSYS1_PIN_DRV_LV3 2
#define EXYNOS7_FSYS1_PIN_DRV_LV4 6
#define EXYNOS7_FSYS1_PIN_DRV_LV5 1
#define EXYNOS7_FSYS1_PIN_DRV_LV6 5
/* Drive strengths for Exynos850 GPIO_HSI block */
#define EXYNOS850_HSI_PIN_DRV_LV1 0 /* 1x */
#define EXYNOS850_HSI_PIN_DRV_LV1_5 1 /* 1.5x */
#define EXYNOS850_HSI_PIN_DRV_LV2 2 /* 2x */
#define EXYNOS850_HSI_PIN_DRV_LV2_5 3 /* 2.5x */
#define EXYNOS850_HSI_PIN_DRV_LV3 4 /* 3x */
#define EXYNOS850_HSI_PIN_DRV_LV4 5 /* 4x */
#define EXYNOS_PIN_FUNC_INPUT 0
#define EXYNOS_PIN_FUNC_OUTPUT 1
#define EXYNOS_PIN_FUNC_2 2
#define EXYNOS_PIN_FUNC_3 3
#define EXYNOS_PIN_FUNC_4 4
#define EXYNOS_PIN_FUNC_5 5
#define EXYNOS_PIN_FUNC_6 6
#define EXYNOS_PIN_FUNC_EINT 0xf
#define EXYNOS_PIN_FUNC_F EXYNOS_PIN_FUNC_EINT
#endif /* __DTS_ARM64_SAMSUNG_EXYNOS_PINCTRL_H__ */

View File

@@ -0,0 +1,37 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2023 Linaro Ltd.
*/
&cmu_top {
bootph-all;
};
&cmu_peri {
bootph-all;
};
&oscclk {
bootph-all;
};
&pinctrl_alive {
bootph-all;
};
&pmu_system_controller {
bootph-all;
samsung,uart-debug-1;
};
&serial_0 {
bootph-all;
};
&uart1_pins {
bootph-all;
};
&usi_uart {
bootph-all;
};

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@@ -0,0 +1,273 @@
// SPDX-License-Identifier: GPL-2.0
/*
* WinLink E850-96 board device tree source
*
* Copyright (C) 2018 Samsung Electronics Co., Ltd.
* Copyright (C) 2021 Linaro Ltd.
*
* Device tree source file for WinLink's E850-96 board which is based on
* Samsung Exynos850 SoC.
*/
/dts-v1/;
#include "exynos850.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
/ {
model = "WinLink E850-96 board";
compatible = "winlink,e850-96", "samsung,exynos850";
aliases {
mmc0 = &mmc_0;
serial0 = &serial_0;
};
chosen {
stdout-path = &serial_0;
};
connector {
compatible = "gpio-usb-b-connector", "usb-b-connector";
label = "micro-USB";
type = "micro";
vbus-supply = <&reg_usb_host_vbus>;
id-gpios = <&gpa0 0 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&micro_usb_det_pins>;
port {
usb_dr_connector: endpoint {
remote-endpoint = <&usb1_drd_sw>;
};
};
};
/*
* RAM: 4 GiB (eMCP):
* - 2 GiB at 0x80000000
* - 2 GiB at 0x880000000
*
* 0xbab00000..0xbfffffff: secure memory (85 MiB).
*/
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x3ab00000>,
<0x0 0xc0000000 0x40000000>,
<0x8 0x80000000 0x80000000>;
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&key_voldown_pins &key_volup_pins>;
volume-down-key {
label = "Volume Down";
linux,code = <KEY_VOLUMEDOWN>;
gpios = <&gpa1 0 GPIO_ACTIVE_LOW>;
};
volume-up-key {
label = "Volume Up";
linux,code = <KEY_VOLUMEUP>;
gpios = <&gpa0 7 GPIO_ACTIVE_LOW>;
};
};
leds {
compatible = "gpio-leds";
/* HEART_BEAT_LED */
user_led1: led-1 {
label = "yellow:user1";
gpios = <&gpg2 2 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_YELLOW>;
function = LED_FUNCTION_HEARTBEAT;
linux,default-trigger = "heartbeat";
};
/* eMMC_LED */
user_led2: led-2 {
label = "yellow:user2";
gpios = <&gpg2 3 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_YELLOW>;
linux,default-trigger = "mmc0";
};
/* SD_LED */
user_led3: led-3 {
label = "white:user3";
gpios = <&gpg2 4 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_WHITE>;
function = LED_FUNCTION_SD;
linux,default-trigger = "mmc2";
};
/* WIFI_LED */
wlan_active_led: led-4 {
label = "yellow:wlan";
gpios = <&gpg2 6 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_YELLOW>;
function = LED_FUNCTION_WLAN;
linux,default-trigger = "phy0tx";
default-state = "off";
};
/* BLUETOOTH_LED */
bt_active_led: led-5 {
label = "blue:bt";
gpios = <&gpg2 7 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_BLUE>;
function = LED_FUNCTION_BLUETOOTH;
linux,default-trigger = "hci0-power";
default-state = "off";
};
};
/* TODO: Remove this once PMIC is implemented */
reg_dummy: regulator-0 {
compatible = "regulator-fixed";
regulator-name = "dummy_reg";
};
reg_usb_host_vbus: regulator-1 {
compatible = "regulator-fixed";
regulator-name = "usb_host_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpa3 5 GPIO_ACTIVE_LOW>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <1>;
ranges;
ramoops@f0000000 {
compatible = "ramoops";
reg = <0x0 0xf0000000 0x200000>;
record-size = <0x20000>;
console-size = <0x20000>;
ftrace-size = <0x100000>;
pmsg-size = <0x20000>;
};
};
/*
* RTC clock (XrtcXTI); external, must be 32.768 kHz.
*
* TODO: Remove this once RTC clock is implemented properly as part of
* PMIC driver.
*/
rtcclk: clock-rtcclk {
compatible = "fixed-clock";
clock-output-names = "rtcclk";
#clock-cells = <0>;
clock-frequency = <32768>;
};
};
&cmu_hsi {
clocks = <&oscclk>, <&rtcclk>,
<&cmu_top CLK_DOUT_HSI_BUS>,
<&cmu_top CLK_DOUT_HSI_MMC_CARD>,
<&cmu_top CLK_DOUT_HSI_USB20DRD>;
clock-names = "oscclk", "rtcclk", "dout_hsi_bus",
"dout_hsi_mmc_card", "dout_hsi_usb20drd";
};
&mmc_0 {
status = "okay";
mmc-hs200-1_8v;
mmc-hs400-1_8v;
cap-mmc-highspeed;
non-removable;
mmc-hs400-enhanced-strobe;
card-detect-delay = <200>;
clock-frequency = <800000000>;
bus-width = <8>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <0 4>;
samsung,dw-mshc-ddr-timing = <2 4>;
samsung,dw-mshc-hs400-timing = <0 2>;
pinctrl-names = "default";
pinctrl-0 = <&sd0_clk_pins &sd0_cmd_pins &sd0_rdqs_pins &sd0_nreset_pins
&sd0_bus1_pins &sd0_bus4_pins &sd0_bus8_pins>;
};
&oscclk {
clock-frequency = <26000000>;
};
&pinctrl_alive {
key_voldown_pins: key-voldown-pins {
samsung,pins = "gpa1-0";
samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
};
key_volup_pins: key-volup-pins {
samsung,pins = "gpa0-7";
samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
};
micro_usb_det_pins: micro-usb-det-pins {
samsung,pins = "gpa0-0";
samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
};
};
&rtc {
status = "okay";
clocks = <&cmu_apm CLK_GOUT_RTC_PCLK>, <&rtcclk>;
clock-names = "rtc", "rtc_src";
};
&serial_0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
};
&usbdrd {
status = "okay";
vdd10-supply = <&reg_dummy>;
vdd33-supply = <&reg_dummy>;
};
&usbdrd_dwc3 {
dr_mode = "otg";
usb-role-switch;
role-switch-default-mode = "host";
port {
usb1_drd_sw: endpoint {
remote-endpoint = <&usb_dr_connector>;
};
};
};
&usbdrd_phy {
status = "okay";
};
&usi_uart {
samsung,clkreq-on; /* needed for UART mode */
status = "okay";
};
&watchdog_cl0 {
status = "okay";
};
&watchdog_cl1 {
status = "okay";
};

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@@ -0,0 +1,663 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Samsung's Exynos850 SoC pin-mux and pin-config device tree source
*
* Copyright (C) 2017 Samsung Electronics Co., Ltd.
* Copyright (C) 2021 Linaro Ltd.
*
* Samsung's Exynos850 SoC pin-mux and pin-config options are listed as device
* tree nodes in this file.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "exynos-pinctrl.h"
&pinctrl_alive {
gpa0: gpa0-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
};
gpa1: gpa1-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
};
gpa2: gpa2-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
};
gpa3: gpa3-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
};
gpa4: gpa4-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
};
gpq0: gpq0-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
/* I2C5 (also called CAM_PMIC_I2C in TRM) */
i2c5_pins: i2c5-pins {
samsung,pins = "gpa3-5", "gpa3-6";
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
};
/* I2C6 (also called MOTOR_I2C in TRM) */
i2c6_pins: i2c6-pins {
samsung,pins = "gpa3-7", "gpa4-0";
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
};
/* USI: UART_DEBUG_0 pins */
uart0_pins: uart0-pins {
samsung,pins = "gpq0-0", "gpq0-1";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
};
/* USI: UART_DEBUG_1 pins */
uart1_pins: uart1-pins {
samsung,pins = "gpa3-7", "gpa4-0";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
};
};
&pinctrl_cmgp {
gpm0: gpm0-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
};
gpm1: gpm1-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
};
gpm2: gpm2-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
};
gpm3: gpm3-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
};
gpm4: gpm4-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
};
gpm5: gpm5-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
};
gpm6: gpm6-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
};
gpm7: gpm7-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
};
/* USI_CMGP0: HSI2C function */
hsi2c3_pins: hsi2c3-pins {
samsung,pins = "gpm0-0", "gpm1-0";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
};
/* USI_CMGP0: UART function (4 pins, Auto Flow Control) */
uart1_single_pins: uart1-single-pins {
samsung,pins = "gpm0-0", "gpm1-0", "gpm2-0", "gpm3-0";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
};
/* USI_CMGP0: UART function (2 pins, Non-Auto Flow Control) */
uart1_dual_pins: uart1-dual-pins {
samsung,pins = "gpm0-0", "gpm1-0";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
};
/* USI_CMGP0: SPI function */
spi1_pins: spi1-pins {
samsung,pins = "gpm0-0", "gpm1-0", "gpm2-0", "gpm3-0";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
};
/* USI_CMGP1: HSI2C function */
hsi2c4_pins: hsi2c4-pins {
samsung,pins = "gpm4-0", "gpm5-0";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
};
/* USI_CMGP1: UART function (4 pins, Auto Flow Control) */
uart2_single_pins: uart2-single-pins {
samsung,pins = "gpm4-0", "gpm5-0", "gpm6-0", "gpm7-0";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
};
/* USI_CMGP1: UART function (2 pins, Non-Auto Flow Control) */
uart2_dual_pins: uart2-dual-pins {
samsung,pins = "gpm4-0", "gpm5-0";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
};
/* USI_CMGP1: SPI function */
spi2_pins: spi2-pins {
samsung,pins = "gpm4-0", "gpm5-0", "gpm6-0", "gpm7-0";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
};
};
&pinctrl_aud {
gpb0: gpb0-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpb1: gpb1-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
aud_codec_mclk_pins: aud-codec-mclk-pins {
samsung,pins = "gpb0-0";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
};
aud_codec_mclk_idle_pins: aud-codec-mclk-idle-pins {
samsung,pins = "gpb0-0";
samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
};
aud_i2s0_pins: aud-i2s0-pins {
samsung,pins = "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
};
aud_i2s0_idle_pins: aud-i2s0-idle-pins {
samsung,pins = "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4";
samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
};
aud_i2s1_pins: aud-i2s1-pins {
samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
};
aud_i2s1_idle_pins: aud-i2s1-idle-pins {
samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3";
samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
};
aud_fm_pins: aud-fm-pins {
samsung,pins = "gpb1-4";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
};
aud_fm_idle_pins: aud-fm-idle-pins {
samsung,pins = "gpb1-4";
samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
};
};
&pinctrl_hsi {
gpf2: gpf2-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
sd2_clk_pins: sd2-clk-pins {
samsung,pins = "gpf2-0";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-drv = <EXYNOS850_HSI_PIN_DRV_LV2>;
};
sd2_cmd_pins: sd2-cmd-pins {
samsung,pins = "gpf2-1";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
samsung,pin-drv = <EXYNOS850_HSI_PIN_DRV_LV2>;
};
sd2_bus1_pins: sd2-bus1-pins {
samsung,pins = "gpf2-2";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
samsung,pin-drv = <EXYNOS850_HSI_PIN_DRV_LV2>;
};
sd2_bus4_pins: sd2-bus4-pins {
samsung,pins = "gpf2-3", "gpf2-4", "gpf2-5";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
samsung,pin-drv = <EXYNOS850_HSI_PIN_DRV_LV2>;
};
sd2_pdn_pins: sd2-pdn-pins {
samsung,pins = "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3",
"gpf2-4", "gpf2-5";
samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
};
};
&pinctrl_core {
gpf0: gpf0-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpf1: gpf1-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
sd0_clk_pins: sd0-clk-pins {
samsung,pins = "gpf0-0";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
};
sd0_cmd_pins: sd0-cmd-pins {
samsung,pins = "gpf0-1";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
};
sd0_rdqs_pins: sd0-rdqs-pins {
samsung,pins = "gpf0-2";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
};
sd0_nreset_pins: sd0-nreset-pins {
samsung,pins = "gpf0-3";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
};
sd0_bus1_pins: sd0-bus1-pins {
samsung,pins = "gpf1-0";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
};
sd0_bus4_pins: sd0-bus4-pins {
samsung,pins = "gpf1-1", "gpf1-2", "gpf1-3";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
};
sd0_bus8_pins: sd0-bus8-pins {
samsung,pins = "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
};
};
&pinctrl_peri {
gpc0: gpc0-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpc1: gpc1-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpg0: gpg0-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpg1: gpg1-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpg2: gpg2-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpg3: gpg3-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpp0: gpp0-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpp1: gpp1-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpp2: gpp2-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
sensor_mclk0_in_pins: sensor-mclk0-in-pins {
samsung,pins = "gpc0-0";
samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
};
sensor_mclk0_out_pins: sensor-mclk0-out-pins {
samsung,pins = "gpc0-0";
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
};
sensor_mclk0_fn_pins: sensor-mclk0-fn-pins {
samsung,pins = "gpc0-0";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
};
sensor_mclk1_in_pins: sensor-mclk1-in-pins {
samsung,pins = "gpc0-1";
samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
};
sensor_mclk1_out_pins: sensor-mclk1-out-pins {
samsung,pins = "gpc0-1";
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
};
sensor_mclk1_fn_pins: sensor-mclk1-fn-pins {
samsung,pins = "gpc0-1";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
};
sensor_mclk2_in_pins: sensor-mclk2-in-pins {
samsung,pins = "gpc0-2";
samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
};
sensor_mclk2_out_pins: sensor-mclk2-out-pins {
samsung,pins = "gpc0-2";
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
};
sensor_mclk2_fn_pins: sensor-mclk2-fn-pins {
samsung,pins = "gpc0-2";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
};
/* USI: HSI2C0 */
hsi2c0_pins: hsi2c0-pins {
samsung,pins = "gpc1-0", "gpc1-1";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
};
/* USI: HSI2C1 */
hsi2c1_pins: hsi2c1-pins {
samsung,pins = "gpc1-2", "gpc1-3";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
};
/* USI: HSI2C2 */
hsi2c2_pins: hsi2c2-pins {
samsung,pins = "gpc1-4", "gpc1-5";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
};
/* USI: SPI */
spi0_pins: spi0-pins {
samsung,pins = "gpp2-0", "gpp2-1", "gpp2-2", "gpp2-3";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
};
i2c0_pins: i2c0-pins {
samsung,pins = "gpp0-0", "gpp0-1";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
};
i2c1_pins: i2c1-pins {
samsung,pins = "gpp0-2", "gpp0-3";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
};
i2c2_pins: i2c2-pins {
samsung,pins = "gpp0-4", "gpp0-5";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
};
i2c3_pins: i2c3-pins {
samsung,pins = "gpp1-0", "gpp1-1";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
};
i2c4_pins: i2c4-pins {
samsung,pins = "gpp1-2", "gpp1-3";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
};
xclkout_pins: xclkout-pins {
samsung,pins = "gpq0-2";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
};
};

809
arch/arm/dts/exynos850.dtsi Normal file
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@@ -0,0 +1,809 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Samsung Exynos850 SoC device tree source
*
* Copyright (C) 2018 Samsung Electronics Co., Ltd.
* Copyright (C) 2021 Linaro Ltd.
*
* Samsung Exynos850 SoC device nodes are listed in this file.
* Exynos850 based board files can include this file and provide
* values for board specific bindings.
*/
#include <dt-bindings/clock/exynos850.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/samsung,exynos-usi.h>
/ {
/* Also known under engineering name Exynos3830 */
compatible = "samsung,exynos850";
#address-cells = <2>;
#size-cells = <1>;
interrupt-parent = <&gic>;
aliases {
pinctrl0 = &pinctrl_alive;
pinctrl1 = &pinctrl_cmgp;
pinctrl2 = &pinctrl_aud;
pinctrl3 = &pinctrl_hsi;
pinctrl4 = &pinctrl_core;
pinctrl5 = &pinctrl_peri;
};
arm-pmu {
compatible = "arm,cortex-a55-pmu";
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
<&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
};
/* Main system clock (XTCXO); external, must be 26 MHz */
oscclk: clock-oscclk {
compatible = "fixed-clock";
clock-output-names = "oscclk";
#clock-cells = <0>;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
core2 {
cpu = <&cpu2>;
};
core3 {
cpu = <&cpu3>;
};
};
cluster1 {
core0 {
cpu = <&cpu4>;
};
core1 {
cpu = <&cpu5>;
};
core2 {
cpu = <&cpu6>;
};
core3 {
cpu = <&cpu7>;
};
};
};
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0>;
enable-method = "psci";
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x1>;
enable-method = "psci";
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x2>;
enable-method = "psci";
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x3>;
enable-method = "psci";
};
cpu4: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x100>;
enable-method = "psci";
};
cpu5: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x101>;
enable-method = "psci";
};
cpu6: cpu@102 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x102>;
enable-method = "psci";
};
cpu7: cpu@103 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x103>;
enable-method = "psci";
};
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
timer {
compatible = "arm,armv8-timer";
/* Hypervisor Virtual Timer interrupt is not wired to GIC */
interrupts =
<GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
};
soc: soc@0 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x0 0x20000000>;
chipid@10000000 {
compatible = "samsung,exynos850-chipid";
reg = <0x10000000 0x100>;
};
timer@10040000 {
compatible = "samsung,exynos850-mct",
"samsung,exynos4210-mct";
reg = <0x10040000 0x800>;
interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&oscclk>, <&cmu_peri CLK_GOUT_MCT_PCLK>;
clock-names = "fin_pll", "mct";
};
gic: interrupt-controller@12a01000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
#address-cells = <0>;
reg = <0x12a01000 0x1000>,
<0x12a02000 0x2000>,
<0x12a04000 0x2000>,
<0x12a06000 0x2000>;
interrupt-controller;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
IRQ_TYPE_LEVEL_HIGH)>;
};
pmu_system_controller: system-controller@11860000 {
compatible = "samsung,exynos850-pmu", "syscon";
reg = <0x11860000 0x10000>;
reboot: syscon-reboot {
compatible = "syscon-reboot";
regmap = <&pmu_system_controller>;
offset = <0x3a00>; /* SYSTEM_CONFIGURATION */
mask = <0x2>; /* SWRESET_SYSTEM */
value = <0x2>; /* reset value */
};
};
watchdog_cl0: watchdog@10050000 {
compatible = "samsung,exynos850-wdt";
reg = <0x10050000 0x100>;
interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu_peri CLK_GOUT_WDT0_PCLK>, <&oscclk>;
clock-names = "watchdog", "watchdog_src";
samsung,syscon-phandle = <&pmu_system_controller>;
samsung,cluster-index = <0>;
status = "disabled";
};
watchdog_cl1: watchdog@10060000 {
compatible = "samsung,exynos850-wdt";
reg = <0x10060000 0x100>;
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu_peri CLK_GOUT_WDT1_PCLK>, <&oscclk>;
clock-names = "watchdog", "watchdog_src";
samsung,syscon-phandle = <&pmu_system_controller>;
samsung,cluster-index = <1>;
status = "disabled";
};
cmu_peri: clock-controller@10030000 {
compatible = "samsung,exynos850-cmu-peri";
reg = <0x10030000 0x8000>;
#clock-cells = <1>;
clocks = <&oscclk>, <&cmu_top CLK_DOUT_PERI_BUS>,
<&cmu_top CLK_DOUT_PERI_UART>,
<&cmu_top CLK_DOUT_PERI_IP>;
clock-names = "oscclk", "dout_peri_bus",
"dout_peri_uart", "dout_peri_ip";
};
cmu_g3d: clock-controller@11400000 {
compatible = "samsung,exynos850-cmu-g3d";
reg = <0x11400000 0x8000>;
#clock-cells = <1>;
clocks = <&oscclk>, <&cmu_top CLK_DOUT_G3D_SWITCH>;
clock-names = "oscclk", "dout_g3d_switch";
};
cmu_apm: clock-controller@11800000 {
compatible = "samsung,exynos850-cmu-apm";
reg = <0x11800000 0x8000>;
#clock-cells = <1>;
clocks = <&oscclk>, <&cmu_top CLK_DOUT_CLKCMU_APM_BUS>;
clock-names = "oscclk", "dout_clkcmu_apm_bus";
};
cmu_cmgp: clock-controller@11c00000 {
compatible = "samsung,exynos850-cmu-cmgp";
reg = <0x11c00000 0x8000>;
#clock-cells = <1>;
clocks = <&oscclk>, <&cmu_apm CLK_GOUT_CLKCMU_CMGP_BUS>;
clock-names = "oscclk", "gout_clkcmu_cmgp_bus";
};
cmu_core: clock-controller@12000000 {
compatible = "samsung,exynos850-cmu-core";
reg = <0x12000000 0x8000>;
#clock-cells = <1>;
clocks = <&oscclk>, <&cmu_top CLK_DOUT_CORE_BUS>,
<&cmu_top CLK_DOUT_CORE_CCI>,
<&cmu_top CLK_DOUT_CORE_MMC_EMBD>,
<&cmu_top CLK_DOUT_CORE_SSS>;
clock-names = "oscclk", "dout_core_bus",
"dout_core_cci", "dout_core_mmc_embd",
"dout_core_sss";
};
cmu_top: clock-controller@120e0000 {
compatible = "samsung,exynos850-cmu-top";
reg = <0x120e0000 0x8000>;
#clock-cells = <1>;
clocks = <&oscclk>;
clock-names = "oscclk";
};
cmu_mfcmscl: clock-controller@12c00000 {
compatible = "samsung,exynos850-cmu-mfcmscl";
reg = <0x12c00000 0x8000>;
#clock-cells = <1>;
clocks = <&oscclk>,
<&cmu_top CLK_DOUT_MFCMSCL_MFC>,
<&cmu_top CLK_DOUT_MFCMSCL_M2M>,
<&cmu_top CLK_DOUT_MFCMSCL_MCSC>,
<&cmu_top CLK_DOUT_MFCMSCL_JPEG>;
clock-names = "oscclk", "dout_mfcmscl_mfc",
"dout_mfcmscl_m2m", "dout_mfcmscl_mcsc",
"dout_mfcmscl_jpeg";
};
cmu_dpu: clock-controller@13000000 {
compatible = "samsung,exynos850-cmu-dpu";
reg = <0x13000000 0x8000>;
#clock-cells = <1>;
clocks = <&oscclk>, <&cmu_top CLK_DOUT_DPU>;
clock-names = "oscclk", "dout_dpu";
};
cmu_hsi: clock-controller@13400000 {
compatible = "samsung,exynos850-cmu-hsi";
reg = <0x13400000 0x8000>;
#clock-cells = <1>;
clocks = <&oscclk>,
<&cmu_top CLK_DOUT_HSI_BUS>,
<&cmu_top CLK_DOUT_HSI_MMC_CARD>,
<&cmu_top CLK_DOUT_HSI_USB20DRD>;
clock-names = "oscclk", "dout_hsi_bus",
"dout_hsi_mmc_card", "dout_hsi_usb20drd";
};
cmu_is: clock-controller@14500000 {
compatible = "samsung,exynos850-cmu-is";
reg = <0x14500000 0x8000>;
#clock-cells = <1>;
clocks = <&oscclk>,
<&cmu_top CLK_DOUT_IS_BUS>,
<&cmu_top CLK_DOUT_IS_ITP>,
<&cmu_top CLK_DOUT_IS_VRA>,
<&cmu_top CLK_DOUT_IS_GDC>;
clock-names = "oscclk", "dout_is_bus", "dout_is_itp",
"dout_is_vra", "dout_is_gdc";
};
cmu_aud: clock-controller@14a00000 {
compatible = "samsung,exynos850-cmu-aud";
reg = <0x14a00000 0x8000>;
#clock-cells = <1>;
clocks = <&oscclk>, <&cmu_top CLK_DOUT_AUD>;
clock-names = "oscclk", "dout_aud";
};
pinctrl_alive: pinctrl@11850000 {
compatible = "samsung,exynos850-pinctrl";
reg = <0x11850000 0x1000>;
wakeup-interrupt-controller {
compatible = "samsung,exynos850-wakeup-eint";
};
};
pinctrl_cmgp: pinctrl@11c30000 {
compatible = "samsung,exynos850-pinctrl";
reg = <0x11c30000 0x1000>;
wakeup-interrupt-controller {
compatible = "samsung,exynos850-wakeup-eint";
};
};
pinctrl_core: pinctrl@12070000 {
compatible = "samsung,exynos850-pinctrl";
reg = <0x12070000 0x1000>;
interrupts = <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_hsi: pinctrl@13430000 {
compatible = "samsung,exynos850-pinctrl";
reg = <0x13430000 0x1000>;
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_peri: pinctrl@139b0000 {
compatible = "samsung,exynos850-pinctrl";
reg = <0x139b0000 0x1000>;
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_aud: pinctrl@14a60000 {
compatible = "samsung,exynos850-pinctrl";
reg = <0x14a60000 0x1000>;
};
rtc: rtc@11a30000 {
compatible = "samsung,s3c6410-rtc";
reg = <0x11a30000 0x100>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu_apm CLK_GOUT_RTC_PCLK>;
clock-names = "rtc";
status = "disabled";
};
mmc_0: mmc@12100000 {
compatible = "samsung,exynos7-dw-mshc-smu";
reg = <0x12100000 0x2000>;
interrupts = <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&cmu_core CLK_GOUT_MMC_EMBD_ACLK>,
<&cmu_core CLK_GOUT_MMC_EMBD_SDCLKIN>;
clock-names = "biu", "ciu";
fifo-depth = <0x40>;
status = "disabled";
};
i2c_0: i2c@13830000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x13830000 0x100>;
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
clocks = <&cmu_peri CLK_GOUT_I2C0_PCLK>;
clock-names = "i2c";
status = "disabled";
};
i2c_1: i2c@13840000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x13840000 0x100>;
interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
clocks = <&cmu_peri CLK_GOUT_I2C1_PCLK>;
clock-names = "i2c";
status = "disabled";
};
i2c_2: i2c@13850000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x13850000 0x100>;
interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins>;
clocks = <&cmu_peri CLK_GOUT_I2C2_PCLK>;
clock-names = "i2c";
status = "disabled";
};
i2c_3: i2c@13860000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x13860000 0x100>;
interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c3_pins>;
clocks = <&cmu_peri CLK_GOUT_I2C3_PCLK>;
clock-names = "i2c";
status = "disabled";
};
i2c_4: i2c@13870000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x13870000 0x100>;
interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c4_pins>;
clocks = <&cmu_peri CLK_GOUT_I2C4_PCLK>;
clock-names = "i2c";
status = "disabled";
};
/* I2C_5 (also called CAM_PMIC_I2C in TRM) */
i2c_5: i2c@13880000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x13880000 0x100>;
interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c5_pins>;
clocks = <&cmu_peri CLK_GOUT_I2C5_PCLK>;
clock-names = "i2c";
status = "disabled";
};
/* I2C_6 (also called MOTOR_I2C in TRM) */
i2c_6: i2c@13890000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x13890000 0x100>;
interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c6_pins>;
clocks = <&cmu_peri CLK_GOUT_I2C6_PCLK>;
clock-names = "i2c";
status = "disabled";
};
sysmmu_mfcmscl: sysmmu@12c50000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x12c50000 0x9000>;
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "sysmmu";
clocks = <&cmu_mfcmscl CLK_GOUT_MFCMSCL_SYSMMU_CLK>;
#iommu-cells = <0>;
};
sysmmu_dpu: sysmmu@130c0000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x130c0000 0x9000>;
interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "sysmmu";
clocks = <&cmu_dpu CLK_GOUT_DPU_SMMU_CLK>;
#iommu-cells = <0>;
};
sysmmu_is0: sysmmu@14550000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x14550000 0x9000>;
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "sysmmu";
clocks = <&cmu_is CLK_GOUT_IS_SYSMMU_IS0_CLK>;
#iommu-cells = <0>;
};
sysmmu_is1: sysmmu@14570000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x14570000 0x9000>;
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "sysmmu";
clocks = <&cmu_is CLK_GOUT_IS_SYSMMU_IS1_CLK>;
#iommu-cells = <0>;
};
sysmmu_aud: sysmmu@14850000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x14850000 0x9000>;
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "sysmmu";
clocks = <&cmu_aud CLK_GOUT_AUD_SYSMMU_CLK>;
#iommu-cells = <0>;
};
sysreg_peri: syscon@10020000 {
compatible = "samsung,exynos850-peri-sysreg",
"samsung,exynos850-sysreg", "syscon";
reg = <0x10020000 0x10000>;
clocks = <&cmu_peri CLK_GOUT_SYSREG_PERI_PCLK>;
};
sysreg_cmgp: syscon@11c20000 {
compatible = "samsung,exynos850-cmgp-sysreg",
"samsung,exynos850-sysreg", "syscon";
reg = <0x11c20000 0x10000>;
clocks = <&cmu_cmgp CLK_GOUT_SYSREG_CMGP_PCLK>;
};
usbdrd: usb@13600000 {
compatible = "samsung,exynos850-dwusb3";
ranges = <0x0 0x13600000 0x10000>;
clocks = <&cmu_hsi CLK_GOUT_USB_BUS_EARLY_CLK>,
<&cmu_hsi CLK_GOUT_USB_REF_CLK>;
clock-names = "bus_early", "ref";
#address-cells = <1>;
#size-cells = <1>;
status = "disabled";
usbdrd_dwc3: usb@0 {
compatible = "snps,dwc3";
reg = <0x0 0x10000>;
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usbdrd_phy 0>;
phy-names = "usb2-phy";
};
};
usbdrd_phy: phy@135d0000 {
compatible = "samsung,exynos850-usbdrd-phy";
reg = <0x135d0000 0x100>;
clocks = <&cmu_hsi CLK_GOUT_USB_PHY_ACLK>,
<&cmu_hsi CLK_GOUT_USB_PHY_REF_CLK>;
clock-names = "phy", "ref";
samsung,pmu-syscon = <&pmu_system_controller>;
#phy-cells = <1>;
status = "disabled";
};
usi_uart: usi@138200c0 {
compatible = "samsung,exynos850-usi";
reg = <0x138200c0 0x20>;
samsung,sysreg = <&sysreg_peri 0x1010>;
samsung,mode = <USI_V2_UART>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
clocks = <&cmu_peri CLK_GOUT_UART_PCLK>,
<&cmu_peri CLK_GOUT_UART_IPCLK>;
clock-names = "pclk", "ipclk";
status = "disabled";
serial_0: serial@13820000 {
compatible = "samsung,exynos850-uart";
reg = <0x13820000 0xc0>;
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
clocks = <&cmu_peri CLK_GOUT_UART_PCLK>,
<&cmu_peri CLK_GOUT_UART_IPCLK>;
clock-names = "uart", "clk_uart_baud0";
status = "disabled";
};
};
usi_hsi2c_0: usi@138a00c0 {
compatible = "samsung,exynos850-usi";
reg = <0x138a00c0 0x20>;
samsung,sysreg = <&sysreg_peri 0x1020>;
samsung,mode = <USI_V2_I2C>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
clocks = <&cmu_peri CLK_GOUT_HSI2C0_PCLK>,
<&cmu_peri CLK_GOUT_HSI2C0_IPCLK>;
clock-names = "pclk", "ipclk";
status = "disabled";
hsi2c_0: i2c@138a0000 {
compatible = "samsung,exynosautov9-hsi2c";
reg = <0x138a0000 0xc0>;
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hsi2c0_pins>;
clocks = <&cmu_peri CLK_GOUT_HSI2C0_IPCLK>,
<&cmu_peri CLK_GOUT_HSI2C0_PCLK>;
clock-names = "hsi2c", "hsi2c_pclk";
status = "disabled";
};
};
usi_hsi2c_1: usi@138b00c0 {
compatible = "samsung,exynos850-usi";
reg = <0x138b00c0 0x20>;
samsung,sysreg = <&sysreg_peri 0x1030>;
samsung,mode = <USI_V2_I2C>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
clocks = <&cmu_peri CLK_GOUT_HSI2C1_PCLK>,
<&cmu_peri CLK_GOUT_HSI2C1_IPCLK>;
clock-names = "pclk", "ipclk";
status = "disabled";
hsi2c_1: i2c@138b0000 {
compatible = "samsung,exynosautov9-hsi2c";
reg = <0x138b0000 0xc0>;
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hsi2c1_pins>;
clocks = <&cmu_peri CLK_GOUT_HSI2C1_IPCLK>,
<&cmu_peri CLK_GOUT_HSI2C1_PCLK>;
clock-names = "hsi2c", "hsi2c_pclk";
status = "disabled";
};
};
usi_hsi2c_2: usi@138c00c0 {
compatible = "samsung,exynos850-usi";
reg = <0x138c00c0 0x20>;
samsung,sysreg = <&sysreg_peri 0x1040>;
samsung,mode = <USI_V2_I2C>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
clocks = <&cmu_peri CLK_GOUT_HSI2C2_PCLK>,
<&cmu_peri CLK_GOUT_HSI2C2_IPCLK>;
clock-names = "pclk", "ipclk";
status = "disabled";
hsi2c_2: i2c@138c0000 {
compatible = "samsung,exynosautov9-hsi2c";
reg = <0x138c0000 0xc0>;
interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hsi2c2_pins>;
clocks = <&cmu_peri CLK_GOUT_HSI2C2_IPCLK>,
<&cmu_peri CLK_GOUT_HSI2C2_PCLK>;
clock-names = "hsi2c", "hsi2c_pclk";
status = "disabled";
};
};
usi_spi_0: usi@139400c0 {
compatible = "samsung,exynos850-usi";
reg = <0x139400c0 0x20>;
samsung,sysreg = <&sysreg_peri 0x1050>;
samsung,mode = <USI_V2_SPI>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
clocks = <&cmu_peri CLK_GOUT_SPI0_PCLK>,
<&cmu_peri CLK_GOUT_SPI0_IPCLK>;
clock-names = "pclk", "ipclk";
status = "disabled";
};
usi_cmgp0: usi@11d000c0 {
compatible = "samsung,exynos850-usi";
reg = <0x11d000c0 0x20>;
samsung,sysreg = <&sysreg_cmgp 0x2000>;
samsung,mode = <USI_V2_I2C>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>,
<&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>;
clock-names = "pclk", "ipclk";
status = "disabled";
hsi2c_3: i2c@11d00000 {
compatible = "samsung,exynosautov9-hsi2c";
reg = <0x11d00000 0xc0>;
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hsi2c3_pins>;
clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>,
<&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>;
clock-names = "hsi2c", "hsi2c_pclk";
status = "disabled";
};
serial_1: serial@11d00000 {
compatible = "samsung,exynos850-uart";
reg = <0x11d00000 0xc0>;
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&uart1_single_pins>;
clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>,
<&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>;
clock-names = "uart", "clk_uart_baud0";
status = "disabled";
};
};
usi_cmgp1: usi@11d200c0 {
compatible = "samsung,exynos850-usi";
reg = <0x11d200c0 0x20>;
samsung,sysreg = <&sysreg_cmgp 0x2010>;
samsung,mode = <USI_V2_I2C>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>,
<&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>;
clock-names = "pclk", "ipclk";
status = "disabled";
hsi2c_4: i2c@11d20000 {
compatible = "samsung,exynosautov9-hsi2c";
reg = <0x11d20000 0xc0>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hsi2c4_pins>;
clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>,
<&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>;
clock-names = "hsi2c", "hsi2c_pclk";
status = "disabled";
};
serial_2: serial@11d20000 {
compatible = "samsung,exynos850-uart";
reg = <0x11d20000 0xc0>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&uart2_single_pins>;
clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>,
<&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>;
clock-names = "uart", "clk_uart_baud0";
status = "disabled";
};
};
};
};
#include "exynos850-pinctrl.dtsi"

View File

@@ -3,6 +3,12 @@
* Copyright 2019 Toradex AG
*/
/ {
sysinfo {
compatible = "toradex,sysinfo";
};
};
&mu {
bootph-some-ram;
};

View File

@@ -9,7 +9,6 @@
/memreserve/ 0x80000000 0x00020000;
#include "fsl-imx8qm.dtsi"
#include "fsl-imx8qm-apalis-u-boot.dtsi"
/ {
model = "Toradex Apalis iMX8";

View File

@@ -3,6 +3,12 @@
* Copyright 2019 Toradex AG
*/
/ {
sysinfo {
compatible = "toradex,sysinfo";
};
};
&{/imx8qx-pm} {
bootph-some-ram;
@@ -84,6 +90,21 @@
bootph-some-ram;
};
&gpio_expander_43 {
usb-bypass-n-hog {
gpio-hog;
gpios = <5 GPIO_ACTIVE_LOW>;
line-name = "usb-bypass-n";
output-high;
};
usb-reset-n-hog {
gpio-hog;
gpios = <4 GPIO_ACTIVE_LOW>;
line-name = "usb-reset-n";
output-low;
};
};
&gpio0 {
bootph-some-ram;
};

View File

@@ -6,7 +6,6 @@
/dts-v1/;
#include "fsl-imx8qxp.dtsi"
#include "fsl-imx8qxp-colibri-u-boot.dtsi"
/ {
model = "Toradex Colibri iMX8X";
@@ -320,8 +319,6 @@
gpio-controller;
#gpio-cells = <2>;
reg = <0x43>;
initial_io_dir = <0xff>;
initial_output = <0x05>;
};
};

View File

@@ -0,0 +1,13 @@
// SPDX-License-Identifier: GPL-2.0+
/ {
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
bootph-pre-ram;
};
};
&wdog1 {
bootph-pre-ram;
};

View File

@@ -5,13 +5,27 @@
#include "imx6qdl-u-boot.dtsi"
&{/aliases} {
/* U-Boot won't find PMIC otherwise */
i2c0 = &i2c3;
i2c1 = &i2c2;
/* SDHCI instance order: eMMC, 4-bit SD/MMC (U-Boot won't find ConfigBlock otherwise) */
mmc0 = &usdhc3;
mmc1 = &usdhc1;
/ {
aliases {
/* U-Boot won't find PMIC otherwise */
i2c0 = &i2c3;
i2c1 = &i2c2;
/* SDHCI instance order: eMMC, 4-bit SD/MMC
* (U-Boot won't find ConfigBlock otherwise)
*/
mmc0 = &usdhc3;
mmc1 = &usdhc1;
};
sysinfo {
compatible = "toradex,sysinfo";
};
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
bootph-pre-ram;
};
};
&wdog1 {

View File

@@ -0,0 +1,38 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright (C) 2022 Kontron Electronics GmbH
*/
#include "imx6qdl-u-boot.dtsi"
/ {
binman: binman {
filename = "flash.bin";
pad-byte = <0x00>;
spl: blob-ext@1 {
offset = <0x0>;
filename = "SPL";
};
uboot: blob-ext@2 {
offset = <0x11000>;
filename = "u-boot.img";
};
};
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
};
};
&fec {
phy-mode = "rmii";
phy-reset-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
phy-reset-duration = <100>;
};
&gpmi {
fsl,legacy-bch-geometry;
};

View File

@@ -0,0 +1,533 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright (C) 2022 Kontron Electronics GmbH
*/
/dts-v1/;
#include "imx6dl.dtsi"
#include <dt-bindings/clock/imx6qdl-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
model = "Sielaff i.MX6 Solo";
compatible = "sielaff,imx6dl-board", "fsl,imx6dl";
chosen {
stdout-path = &uart2;
};
backlight: pwm-backlight {
compatible = "pwm-backlight";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_backlight>;
pwms = <&pwm3 0 50000 0>;
brightness-levels = <0 0 64 88 112 136 184 232 255>;
default-brightness-level = <4>;
enable-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>;
power-supply = <&reg_backlight>;
};
cec {
compatible = "cec-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hdmi_cec>;
cec-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
hdmi-phandle = <&hdmi>;
};
enet_ref: clock-enet-ref {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
clock-output-names = "enet-ref";
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_keys>;
key-0 {
gpios = <&gpio2 16 0>;
debounce-interval = <10>;
linux,code = <1>;
};
key-1 {
gpios = <&gpio3 27 0>;
debounce-interval = <10>;
linux,code = <2>;
};
key-2 {
gpios = <&gpio5 4 0>;
debounce-interval = <10>;
linux,code = <3>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
led-debug {
label = "debug-led";
gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>;
default-state = "off";
linux,default-trigger = "heartbeat";
};
};
memory@80000000 {
reg = <0x80000000 0x20000000>;
device_type = "memory";
};
osc_eth_phy: clock-osc-eth-phy {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
clock-output-names = "osc-eth-phy";
};
panel {
compatible = "lg,lb070wv8";
backlight = <&backlight>;
power-supply = <&reg_3v3>;
port {
panel_in_lvds: endpoint {
remote-endpoint = <&lvds_out>;
};
};
};
reg_3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
reg_backlight: regulator-backlight {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_backlight>;
enable-active-high;
gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>;
regulator-name = "backlight";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
};
reg_usb_otg_vbus: regulator-usb-otg-vbus {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usbotg_vbus>;
enable-active-high;
gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>;
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
};
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
cs-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>;
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <20000000>;
};
};
&fec {
/*
* Set PTP clock to external instead of internal reference, as the
* REF_CLK from the PHY is fed back into the i.MX6 and the GPR
* register needs to be set accordingly (see mach-imx6q.c).
*/
clocks = <&clks IMX6QDL_CLK_ENET>,
<&clks IMX6QDL_CLK_ENET>,
<&enet_ref>,
<&clks IMX6QDL_CLK_ENET_REF>;
clock-names = "ipg", "ahb", "ptp", "enet_out";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-connection-type = "rmii";
phy-handle = <&ethphy>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy: ethernet-phy@1 {
reg = <1>;
clocks = <&osc_eth_phy>;
clock-names = "rmii-ref";
micrel,led-mode = <1>;
reset-assert-us = <500>;
reset-deassert-us = <100>;
reset-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
};
};
};
&gpio1 {
gpio-line-names =
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "key-out", "key-in",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
};
&gpio2 {
gpio-line-names =
"", "", "", "", "", "", "", "",
"lan9500a-rst", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
};
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
status = "okay";
};
&hdmi {
ddc-i2c-bus = <&i2c4>;
status = "okay";
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
clock-frequency = <100000>;
status = "okay";
rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
};
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
clock-frequency = <100000>;
status = "okay";
touchscreen@55 {
compatible = "sitronix,st1633";
reg = <0x55>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_touch>;
interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
interrupt-parent = <&gpio5>;
gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
status = "disabled";
};
touchscreen@5d {
compatible = "goodix,gt928";
reg = <0x5d>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_touch>;
interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&gpio5>;
irq-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
status = "disabled";
};
};
&i2c4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
clock-frequency = <100000>;
status = "okay";
};
&ldb {
status = "okay";
lvds: lvds-channel@0 {
fsl,data-mapping = "spwg";
fsl,data-width = <24>;
status = "okay";
port@4 {
reg = <4>;
lvds_out: endpoint {
remote-endpoint = <&panel_in_lvds>;
};
};
};
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
&usbh1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbh1>;
disable-over-current;
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
usb1@1 {
compatible = "usb4b4,6570";
reg = <1>;
clocks = <&clks IMX6QDL_CLK_CKO>;
assigned-clocks = <&clks IMX6QDL_CLK_CKO>,
<&clks IMX6QDL_CLK_CKO2_SEL>;
assigned-clock-parents = <&clks IMX6QDL_CLK_CKO2>,
<&clks IMX6QDL_CLK_OSC>;
assigned-clock-rates = <12000000 0>;
};
};
&usbotg {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
dr_mode = "host";
over-current-active-low;
vbus-supply = <&reg_usb_otg_vbus>;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3>;
cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_3v3>;
voltage-ranges = <3300 3300>;
no-1-8-v;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl_hog: hoggrp {
fsl,pins = <
MX6QDL_PAD_RGMII_RD0__GPIO6_IO25 0x1b0b0 /* PMIC_IRQ */
MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x1b0b0
MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x1b0b0
MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0
MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0
MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0
>;
};
pinctrl_backlight: backlightgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x100b1
>;
};
pinctrl_ecspi2: ecspi2grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1
MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1
MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1
MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x100b1
>;
};
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1
>;
};
pinctrl_gpio_keys: gpiokeysgrp {
fsl,pins = <
MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x1b080
MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x1b080
MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b080
>;
};
pinctrl_gpio_leds: gpioledsgrp {
fsl,pins = <
MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1b0b0
>;
};
pinctrl_gpmi_nand: gpminandgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
>;
};
pinctrl_hdmi_cec: hdmicecgrp {
fsl,pins = <
MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x1b8b1
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001f8b1
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001f8b1
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX6QDL_PAD_GPIO_7__I2C4_SCL 0x4001b8b1
MX6QDL_PAD_GPIO_8__I2C4_SDA 0x4001b8b1
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
>;
};
pinctrl_reg_backlight: regbacklightgrp {
fsl,pins = <
MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b1
>;
};
pinctrl_reg_usbotg_vbus: regusbotgvbusgrp {
fsl,pins = <
MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b1
>;
};
pinctrl_touch: touchgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b0
MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b0
>;
};
pinctrl_usbh1: usbh1grp {
fsl,pins = <
MX6QDL_PAD_GPIO_3__USB_H1_OC 0x1b0b1
MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x1b0b0
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b1
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x100b1
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_9__WDOG1_B 0x1b0b0
>;
};
};

View File

@@ -5,18 +5,30 @@
#include "imx6qdl-u-boot.dtsi"
&{/aliases} {
/* U-Boot won't find PMIC otherwise */
i2c0 = &i2c1;
i2c1 = &i2c2;
i2c2 = &i2c3;
/*
* SDHCI instance order: eMMC, 8-bit SD/MMC, 4-bit SD
* (U-Boot won't find ConfigBlock otherwise)
*/
mmc0 = &usdhc3;
mmc1 = &usdhc1;
mmc2 = &usdhc2;
/ {
aliases {
/* U-Boot won't find PMIC otherwise */
i2c0 = &i2c1;
i2c1 = &i2c2;
i2c2 = &i2c3;
/*
* SDHCI instance order: eMMC, 8-bit SD/MMC, 4-bit SD
* (U-Boot won't find ConfigBlock otherwise)
*/
mmc0 = &usdhc3;
mmc1 = &usdhc1;
mmc2 = &usdhc2;
};
sysinfo {
compatible = "toradex,sysinfo";
};
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
bootph-pre-ram;
};
};
&wdog1 {

View File

@@ -13,6 +13,12 @@
&gpio6 4 0
>;
};
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
bootph-pre-ram;
};
};
&soc {
@@ -58,3 +64,7 @@
&usdhc3 {
bootph-all;
};
&wdog1 {
bootph-pre-ram;
};

View File

@@ -9,6 +9,11 @@
aliases {
mmc1 = &usdhc3;
};
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog2>;
bootph-pre-ram;
};
};
&usdhc3 {
@@ -18,3 +23,7 @@
&pinctrl_usdhc3 {
bootph-pre-ram;
};
&wdog2 {
bootph-pre-ram;
};

View File

@@ -6,4 +6,14 @@
aliases {
mmc0 = &usdhc3;
};
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
bootph-pre-ram;
};
};
&wdog1 {
bootph-pre-ram;
};

View File

@@ -9,6 +9,12 @@
soc {
bootph-pre-ram;
};
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
bootph-pre-ram;
};
};
&aips2 {
@@ -26,3 +32,7 @@
&usdhc1 {
bootph-pre-ram;
};
&wdog1 {
bootph-pre-ram;
};

View File

@@ -7,12 +7,6 @@
#include "imx6ul-opos6ul-u-boot.dtsi"
/ {
aliases {
display0 = &lcdif;
};
};
&aips1 {
bootph-pre-ram;
@@ -22,7 +16,29 @@
};
&lcdif {
display = <&display0>;
bootph-some-ram;
display0: display0 {
bits-per-pixel = <18>;
bus-width = <18>;
display-timings {
timing0 {
clock-frequency = <33300000>;
hactive = <800>;
vactive = <480>;
hback-porch = <36>;
hfront-porch = <210>;
vback-porch = <13>;
vfront-porch = <22>;
hsync-len = <10>;
vsync-len = <10>;
de-active = <1>;
pixelclk-active = <0>;
};
};
};
};
&pinctrl_uart1 {

View File

@@ -9,6 +9,16 @@
usb0 = &usbotg1; /* required for ums */
display0 = &lcdif;
};
sysinfo {
compatible = "toradex,sysinfo";
};
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
bootph-pre-ram;
};
};
&pinctrl_uart1 {
@@ -54,3 +64,7 @@
};
};
};
&wdog1 {
bootph-pre-ram;
};

View File

@@ -5,10 +5,16 @@
#include "imx7s-u-boot.dtsi"
&{/aliases} {
/* SDHCI instance order: eMMC, SD/MMC */
mmc0 = &usdhc3;
mmc1 = &usdhc1;
/ {
aliases {
/* SDHCI instance order: eMMC, SD/MMC */
mmc0 = &usdhc3;
mmc1 = &usdhc1;
};
sysinfo {
compatible = "toradex,sysinfo";
};
};
&lcdif {

View File

@@ -1,11 +1,12 @@
#include "imx7s-u-boot.dtsi"
/{
aliases {
mmc0 = &usdhc3;
usb0 = &usbotg1;
display0 = &lcdif;
};
aliases {
mmc0 = &usdhc3;
mmc1 = &usdhc1;
usb0 = &usbotg1;
display0 = &lcdif;
};
wdt-reboot {
compatible = "wdt-reboot";

View File

@@ -18,57 +18,6 @@
dr_mode = "peripheral";
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
};
&pinctrl_usdhc1 {
fsl,pins = <
MX7D_PAD_SD1_CMD__SD1_CMD 0x59
MX7D_PAD_SD1_CLK__SD1_CLK 0x19
MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
>;
};
&iomuxc {
pinctrl_usdhc1_gpio: usdhc1gpiogrp {
fsl,pins = <
MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */
MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */
MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */
MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59 /* VSELECT */
>;
};
pinctrl_usdhc1_100mhz: usdhc1100mhzgrp {
fsl,pins = <
MX7D_PAD_SD1_CMD__SD1_CMD 0x5a
MX7D_PAD_SD1_CLK__SD1_CLK 0x1a
MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a
MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a
MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a
MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a
>;
};
pinctrl_usdhc1_200mhz: usdhc1200mhzgrp {
fsl,pins = <
MX7D_PAD_SD1_CMD__SD1_CMD 0x5b
MX7D_PAD_SD1_CLK__SD1_CLK 0x1b
MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b
MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b
MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b
MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b
>;
};
};
&wdog1 {
bootph-pre-ram;
};

View File

@@ -24,14 +24,14 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_keys>;
volume-up {
key-volume-up {
label = "Volume Up";
gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEUP>;
wakeup-source;
};
volume-down {
key-volume-down {
label = "Volume Down";
gpios = <&gpio5 10 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEDOWN>;
@@ -39,12 +39,12 @@
};
};
spi4 {
spi-4 {
compatible = "spi-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi4>;
gpio-sck = <&gpio1 13 GPIO_ACTIVE_HIGH>;
gpio-mosi = <&gpio1 9 GPIO_ACTIVE_HIGH>;
sck-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
mosi-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
num-chipselects = <1>;
#address-cells = <1>;
@@ -60,6 +60,17 @@
};
};
reg_sd1_vmmc: regulator-sd1-vmmc {
compatible = "regulator-fixed";
regulator-name = "VDD_SD1";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
enable-active-high;
startup-delay-us = <200000>;
off-on-delay-us = <20000>;
};
reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_otg1_vbus";
@@ -205,13 +216,8 @@
pinctrl-0 = <&pinctrl_tsc2046_pendown>;
interrupt-parent = <&gpio2>;
interrupts = <29 0>;
pendown-gpio = <&gpio2 29 GPIO_ACTIVE_HIGH>;
ti,x-min = /bits/ 16 <0>;
ti,x-max = /bits/ 16 <0>;
ti,y-min = /bits/ 16 <0>;
ti,y-max = /bits/ 16 <0>;
ti,pressure-max = /bits/ 16 <0>;
ti,x-plate-ohms = /bits/ 16 <400>;
pendown-gpio = <&gpio2 29 GPIO_ACTIVE_LOW>;
touchscreen-max-pressure = <255>;
wakeup-source;
};
};
@@ -269,7 +275,7 @@
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
pmic: pfuze3000@8 {
pmic: pmic@8 {
compatible = "fsl,pfuze3000";
reg = <0x08>;
@@ -478,10 +484,13 @@
};
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
vmmc-supply = <&reg_sd1_vmmc>;
wakeup-source;
keep-power-in-suspend;
status = "okay";
@@ -736,6 +745,15 @@
>;
};
pinctrl_usdhc1_gpio: usdhc1_gpiogrp {
fsl,pins = <
MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */
MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */
MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */
MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59 /* VSELECT */
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX7D_PAD_SD1_CMD__SD1_CMD 0x59
@@ -744,9 +762,28 @@
MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */
MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */
MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */
>;
};
pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
fsl,pins = <
MX7D_PAD_SD1_CMD__SD1_CMD 0x5a
MX7D_PAD_SD1_CLK__SD1_CLK 0x1a
MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a
MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a
MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a
MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a
>;
};
pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
fsl,pins = <
MX7D_PAD_SD1_CMD__SD1_CMD 0x5b
MX7D_PAD_SD1_CLK__SD1_CLK 0x1b
MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b
MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b
MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b
MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b
>;
};

View File

@@ -7,6 +7,12 @@
chosen {
stdout-path = &uart1;
};
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
bootph-pre-ram;
};
};
&aips3 {
@@ -24,3 +30,7 @@
&uart1 {
bootph-all;
};
&wdog1 {
bootph-pre-ram;
};

View File

@@ -0,0 +1,460 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2022 PHYTEC Messtechnik GmbH
* Author: Teresa Remmet <t.remmet@phytec.de>
*/
/dts-v1/;
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/phy/phy-imx8-pcie.h>
#include "imx8mm-phycore-som.dtsi"
/ {
model = "PHYTEC phyBOARD-Polis-i.MX8MM RDK";
compatible = "phytec,imx8mm-phyboard-polis-rdk",
"phytec,imx8mm-phycore-som", "fsl,imx8mm";
chosen {
stdout-path = &uart3;
};
bt_osc_32k: bt-lp-clock {
compatible = "fixed-clock";
clock-frequency = <32768>;
clock-output-names = "bt_osc_32k";
#clock-cells = <0>;
};
can_osc_40m: can-clock {
compatible = "fixed-clock";
clock-frequency = <40000000>;
clock-output-names = "can_osc_40m";
#clock-cells = <0>;
};
fan {
compatible = "gpio-fan";
gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>;
gpio-fan,speed-map = <0 0
13000 1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fan>;
#cooling-cells = <2>;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_leds>;
led-0 {
color = <LED_COLOR_ID_RED>;
function = LED_FUNCTION_DISK;
gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "mmc2";
};
led-1 {
color = <LED_COLOR_ID_BLUE>;
function = LED_FUNCTION_DISK;
gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "mmc1";
};
led-2 {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_CPU;
gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
usdhc1_pwrseq: pwr-seq {
compatible = "mmc-pwrseq-simple";
post-power-on-delay-ms = <100>;
power-off-delay-us = <60>;
reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
};
reg_can_en: regulator-can-en {
compatible = "regulator-fixed";
gpio = <&gpio1 9 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can_en>;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "CAN_EN";
startup-delay-us = <20>;
};
reg_usb_otg1_vbus: regulator-usb-otg1 {
compatible = "regulator-fixed";
gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg1pwrgrp>;
regulator-name = "usb_otg1_vbus";
regulator-max-microvolt = <5000000>;
regulator-min-microvolt = <5000000>;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
off-on-delay-us = <20000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "VSD_3V3";
};
reg_vcc_3v3: regulator-vcc-3v3 {
compatible = "regulator-fixed";
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "VCC_3V3";
};
};
/* SPI - CAN MCP251XFD */
&ecspi1 {
cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
can0: can@0 {
compatible = "microchip,mcp251xfd";
clocks = <&can_osc_40m>;
interrupt-parent = <&gpio1>;
interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can_int>;
reg = <0>;
spi-max-frequency = <20000000>;
xceiver-supply = <&reg_can_en>;
};
};
&gpio1 {
gpio-line-names = "nINT_ETHPHY", "LED_RED", "WDOG_INT", "X_RTC_INT",
"", "", "", "RESET_ETHPHY",
"CAN_nINT", "CAN_EN", "nENABLE_FLATLINK", "",
"USB_OTG_VBUS_EN", "", "LED_GREEN", "LED_BLUE";
};
&gpio2 {
gpio-line-names = "", "", "", "",
"", "", "BT_REG_ON", "WL_REG_ON",
"BT_DEV_WAKE", "BT_HOST_WAKE", "", "",
"X_SD2_CD_B", "", "", "",
"", "", "", "SD2_RESET_B";
};
&gpio4 {
gpio-line-names = "", "", "", "",
"", "", "", "",
"FAN", "miniPCIe_nPERST", "", "",
"COEX1", "COEX2";
};
&gpio5 {
gpio-line-names = "", "", "", "",
"", "", "", "",
"", "ECSPI1_SS0";
};
&i2c4 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
};
/* PCIe */
&pcie0 {
assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
<&clk IMX8MM_CLK_PCIE1_CTRL>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
<&clk IMX8MM_SYS_PLL2_250M>;
assigned-clock-rates = <10000000>, <250000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
reset-gpio = <&gpio4 9 GPIO_ACTIVE_LOW>;
status = "okay";
};
&pcie_phy {
clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
fsl,clkreq-unsupported;
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
fsl,tx-deemph-gen1 = <0x2d>;
fsl,tx-deemph-gen2 = <0xf>;
status = "okay";
};
&rv3028 {
trickle-resistor-ohms = <3000>;
};
&snvs_pwrkey {
status = "okay";
};
/* UART - RS232/RS485 */
&uart1 {
assigned-clocks = <&clk IMX8MM_CLK_UART1>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
uart-has-rtscts;
status = "okay";
};
/* UART - Sterling-LWB Bluetooth */
&uart2 {
assigned-clocks = <&clk IMX8MM_CLK_UART2>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
fsl,dte-mode;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2_bt>;
uart-has-rtscts;
status = "okay";
bluetooth {
compatible = "brcm,bcm43438-bt";
clocks = <&bt_osc_32k>;
clock-names = "lpo";
device-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
interrupt-names = "host-wakeup";
interrupt-parent = <&gpio2>;
interrupts = <9 IRQ_TYPE_EDGE_BOTH>;
max-speed = <2000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_bt>;
shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
vddio-supply = <&reg_vcc_3v3>;
};
};
/* UART - console */
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
/* USB */
&usbotg1 {
adp-disable;
dr_mode = "otg";
over-current-active-low;
samsung,picophy-pre-emp-curr-control = <3>;
samsung,picophy-dc-vol-level-adjust = <7>;
srp-disable;
vbus-supply = <&reg_usb_otg1_vbus>;
status = "okay";
};
&usbotg2 {
disable-over-current;
dr_mode = "host";
samsung,picophy-pre-emp-curr-control = <3>;
samsung,picophy-dc-vol-level-adjust = <7>;
status = "okay";
};
/* SDIO - Sterling-LWB Wifi */
&usdhc1 {
assigned-clocks = <&clk IMX8MM_CLK_USDHC1>;
assigned-clock-rates = <200000000>;
bus-width = <4>;
mmc-pwrseq = <&usdhc1_pwrseq>;
non-removable;
no-1-8-v;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wlan>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
brcmf: wifi@1 {
compatible = "brcm,bcm4329-fmac";
reg = <1>;
};
};
/* SD-Card */
&usdhc2 {
assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
assigned-clock-rates = <200000000>;
bus-width = <4>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
disable-wp;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
vmmc-supply = <&reg_usdhc2_vmmc>;
vqmmc-supply = <&reg_nvcc_sd2>;
status = "okay";
};
&iomuxc {
pinctrl_bt: btgrp {
fsl,pins = <
MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x00
MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x00
MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x00
>;
};
pinctrl_can_en: can-engrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x00
>;
};
pinctrl_can_int: can-intgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x00
>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x80
MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x80
MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x80
MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x00
>;
};
pinctrl_fan: fan0grp {
fsl,pins = <
MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x16
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c2
MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c2
>;
};
pinctrl_leds: leds1grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x16
MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x16
MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x16
>;
};
pinctrl_pcie: pciegrp {
fsl,pins = <
MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x00
MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x12
MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x12
>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x40
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x00
MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x00
MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x00
MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x00
>;
};
pinctrl_uart2_bt: uart2btgrp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_RXC_UART2_DTE_RTS_B 0x00
MX8MM_IOMUXC_SAI3_RXD_UART2_DTE_CTS_B 0x00
MX8MM_IOMUXC_SAI3_TXC_UART2_DTE_RX 0x00
MX8MM_IOMUXC_SAI3_TXFS_UART2_DTE_TX 0x00
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x40
MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x40
>;
};
pinctrl_usbotg1pwrgrp: usbotg1pwrgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x00
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x182
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0xc6
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc6
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc6
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc6
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc6
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x40
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x192
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d2
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d2
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d2
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d2
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d2
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
>;
};
pinctrl_wlan: wlangrp {
fsl,pins = <
MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x00
>;
};
};

View File

@@ -0,0 +1,440 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2022 PHYTEC Messtechnik GmbH
* Author: Teresa Remmet <t.remmet@phytec.de>
*/
#include "imx8mm.dtsi"
#include <dt-bindings/net/ti-dp83867.h>
/ {
model = "PHYTEC phyCORE-i.MX8MM";
compatible = "phytec,imx8mm-phycore-som", "fsl,imx8mm";
aliases {
rtc0 = &rv3028;
rtc1 = &snvs_rtc;
};
memory@40000000 {
device_type = "memory";
reg = <0x0 0x40000000 0 0x80000000>;
};
reg_vdd_3v3_s: regulator-vdd-3v3-s {
compatible = "regulator-fixed";
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "VDD_3V3_S";
};
};
&A53_0 {
cpu-supply = <&reg_vdd_arm>;
};
&A53_1 {
cpu-supply = <&reg_vdd_arm>;
};
&A53_2 {
cpu-supply = <&reg_vdd_arm>;
};
&A53_3 {
cpu-supply = <&reg_vdd_arm>;
};
&ddrc {
operating-points-v2 = <&ddrc_opp_table>;
ddrc_opp_table: opp-table {
compatible = "operating-points-v2";
opp-25000000 {
opp-hz = /bits/ 64 <25000000>;
};
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
};
opp-750000000 {
opp-hz = /bits/ 64 <750000000>;
};
};
};
/* Ethernet */
&fec1 {
fsl,magic-packet;
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
enet-phy-lane-no-swap;
ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
reg = <0>;
reset-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
reset-assert-us = <1000>;
reset-deassert-us = <1000>;
};
};
};
/* SPI Flash */
&flexspi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexspi0>;
status = "okay";
som_flash: flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <80000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <1>;
};
};
&gpio1 {
gpio-line-names = "nINT_ETHPHY", "", "WDOG_INT", "X_RTC_INT",
"", "", "", "RESET_ETHPHY",
"", "", "nENABLE_FLATLINK";
};
/* I2C1 */
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default","gpio";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
pmic@8 {
compatible = "nxp,pf8121a";
reg = <0x08>;
regulators {
reg_nvcc_sd1: ldo1 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "NVCC_SD1 (LDO1)";
regulator-state-mem {
regulator-off-in-suspend;
};
};
reg_nvcc_sd2: ldo2 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <1800000>;
regulator-name = "NVCC_SD2 (LDO2)";
vselect-en;
regulator-state-mem {
regulator-off-in-suspend;
};
};
reg_vcc_enet: ldo3 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <2500000>;
regulator-min-microvolt = <1500000>;
regulator-name = "VCC_ENET_2V5 (LDO3)";
regulator-state-mem {
regulator-off-in-suspend;
};
};
reg_vdda_1v8: ldo4 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <1500000>;
regulator-name = "VDDA_1V8 (LDO4)";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-min-microvolt = <1500000>;
regulator-suspend-max-microvolt = <1500000>;
};
};
reg_soc_vdda_phy: buck1 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <900000>;
regulator-min-microvolt = <400000>;
regulator-name = "VDD_SOC_VDDA_PHY_0P8 (BUCK1)";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-min-microvolt = <400000>;
regulator-suspend-max-microvolt = <400000>;
};
};
reg_vdd_gpu_dram: buck2 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1000000>;
regulator-min-microvolt = <1000000>;
regulator-name = "VDD_GPU_DRAM (BUCK2)";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-max-microvolt = <1000000>;
regulator-suspend-min-microvolt = <1000000>;
};
};
reg_vdd_gpu: buck3 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1000000>;
regulator-min-microvolt = <400000>;
regulator-name = "VDD_VPU (BUCK3)";
regulator-state-mem {
regulator-off-in-suspend;
};
};
reg_vdd_mipi: buck4 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1050000>;
regulator-min-microvolt = <900000>;
regulator-name = "VDD_MIPI_0P9 (BUCK4)";
regulator-state-mem {
regulator-off-in-suspend;
};
};
reg_vdd_arm: buck5 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1050000>;
regulator-min-microvolt = <400000>;
regulator-name = "VDD_ARM (BUCK5)";
regulator-state-mem {
regulator-off-in-suspend;
};
};
reg_vdd_1v8: buck6 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <1800000>;
regulator-name = "VDD_1V8 (BUCK6)";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-max-microvolt = <1800000>;
regulator-suspend-min-microvolt = <1800000>;
};
};
reg_nvcc_dram: buck7 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1100000>;
regulator-min-microvolt = <1100000>;
regulator-name = "NVCC_DRAM_1P1V (BUCK7)";
};
reg_vsnvs: vsnvs {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <1800000>;
regulator-name = "NVCC_SNVS_1P8 (VSNVS)";
};
};
};
sn65dsi83: bridge@2d {
compatible = "ti,sn65dsi83";
enable-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sn65dsi83>;
reg = <0x2d>;
status = "disabled";
};
eeprom@51 {
compatible = "atmel,24c32";
pagesize = <32>;
reg = <0x51>;
vcc-supply = <&reg_vdd_3v3_s>;
};
rv3028: rtc@52 {
compatible = "microcrystal,rv3028";
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&gpio1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rtc>;
reg = <0x52>;
};
};
/* EMMC */
&usdhc3 {
assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
assigned-clock-rates = <400000000>;
bus-width = <8>;
keep-power-in-suspend;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
non-removable;
status = "okay";
};
/* Watchdog */
&wdog1 {
fsl,ext-reset-output;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
status = "okay";
};
&iomuxc {
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x2
MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x2
MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x90
MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x90
MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x90
MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x90
MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x90
MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x90
MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x16
MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x16
MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x16
MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x16
MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x16
MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x16
MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x10
>;
};
pinctrl_flexspi0: flexspi0grp {
fsl,pins = <
MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2
MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c0
MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c0
>;
};
pinctrl_i2c1_gpio: i2c1gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x1e0
MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x1e0
>;
};
pinctrl_rtc: rtcgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0
>;
};
pinctrl_sn65dsi83: sn65dsi83grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x0
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
>;
};
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
>;
};
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x26
>;
};
};

View File

@@ -0,0 +1,70 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2024 PHYTEC Messtechnik GmbH
*/
#include "imx8mm-u-boot.dtsi"
/ {
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
bootph-pre-ram;
};
};
&pinctrl_uart3 {
bootph-pre-ram;
};
&pinctrl_usdhc2_gpio {
bootph-pre-ram;
};
&pinctrl_usdhc2 {
bootph-pre-ram;
};
&pinctrl_usdhc3 {
bootph-pre-ram;
};
&pinctrl_wdog {
bootph-pre-ram;
};
&gpio1 {
bootph-pre-ram;
};
&gpio2 {
bootph-pre-ram;
};
&gpio3 {
bootph-pre-ram;
};
&gpio4 {
bootph-pre-ram;
};
&gpio5 {
bootph-pre-ram;
};
&uart3 {
bootph-pre-ram;
};
&usdhc2 {
bootph-pre-ram;
};
&usdhc3 {
bootph-pre-ram;
};
&wdog1 {
bootph-pre-ram;
};

View File

@@ -0,0 +1,489 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2023 PHYTEC Messtechnik GmbH
*/
/dts-v1/;
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/leds/common.h>
#include "imx8mm-phycore-som.dtsi"
/ {
model = "PHYTEC phyGATE-Tauri-L-iMX8MM";
compatible = "phytec,imx8mm-phygate-tauri-l",
"phytec,imx8mm-phycore-som", "fsl,imx8mm";
chosen {
stdout-path = &uart3;
};
can_osc_40m: clock-can {
compatible = "fixed-clock";
clock-frequency = <40000000>;
clock-output-names = "can_osc_40m";
#clock-cells = <0>;
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpiokeys>;
key {
gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
label = "KEY-A";
linux,code = <KEY_A>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_leds>;
led-1 {
color = <LED_COLOR_ID_RED>;
gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "none";
};
led-2 {
color = <LED_COLOR_ID_YELLOW>;
gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "none";
};
};
usdhc1_pwrseq: pwr-seq {
compatible = "mmc-pwrseq-simple";
post-power-on-delay-ms = <100>;
power-off-delay-us = <60>;
reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
};
reg_usb_hub_vbus: regulator-hub-otg1 {
compatible = "regulator-fixed";
gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbhubpwr>;
regulator-name = "usb_hub_vbus";
regulator-max-microvolt = <5000000>;
regulator-min-microvolt = <5000000>;
};
reg_usb_otg1_vbus: regulator-usb-otg1 {
compatible = "regulator-fixed";
gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg1pwr>;
regulator-name = "usb_otg1_vbus";
regulator-max-microvolt = <5000000>;
regulator-min-microvolt = <5000000>;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
off-on-delay-us = <20000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "VSD_3V3";
};
};
&ecspi1 {
cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>,
<&gpio5 13 GPIO_ACTIVE_LOW>,
<&gpio5 2 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
/* CAN MCP251XFD */
can0: can@0 {
compatible = "microchip,mcp251xfd";
reg = <0>;
clocks = <&can_osc_40m>;
interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&gpio1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can_int>;
spi-max-frequency = <10000000>;
};
tpm: tpm@1 {
compatible = "tcg,tpm_tis-spi";
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&gpio2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tpm>;
reg = <1>;
spi-max-frequency = <38000000>;
};
};
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_gpio>;
scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
temp_sense0: temperature-sensor@49 {
compatible = "ti,tmp102";
reg = <0x49>;
interrupt-parent = <&gpio4>;
interrupts = <31 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tempsense>;
#thermal-sensor-cells = <1>;
};
};
&i2c3 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
pinctrl-1 = <&pinctrl_i2c3_gpio>;
scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
&i2c4 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
pinctrl-1 = <&pinctrl_i2c4_gpio>;
scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
/* PCIe */
&pcie0 {
assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
<&clk IMX8MM_CLK_PCIE1_PHY>,
<&clk IMX8MM_CLK_PCIE1_CTRL>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
<&clk IMX8MM_SYS_PLL2_100M>,
<&clk IMX8MM_SYS_PLL2_250M>;
assigned-clock-rates = <10000000>, <100000000>, <250000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
reset-gpio = <&gpio3 22 GPIO_ACTIVE_LOW>;
status = "okay";
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "okay";
};
&pwm4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
};
/* RTC */
&rv3028 {
trickle-resistor-ohms = <3000>;
};
&uart1 {
assigned-clocks = <&clk IMX8MM_CLK_UART1>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
/* UART2 - RS232 */
&uart2 {
assigned-clocks = <&clk IMX8MM_CLK_UART2>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
/* UART - console */
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
/* USB */
&usbotg1 {
adp-disable;
dr_mode = "otg";
over-current-active-low;
samsung,picophy-pre-emp-curr-control = <3>;
samsung,picophy-dc-vol-level-adjust = <7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg1>;
srp-disable;
vbus-supply = <&reg_usb_otg1_vbus>;
status = "okay";
};
&usbotg2 {
disable-over-current;
dr_mode = "host";
samsung,picophy-pre-emp-curr-control = <3>;
samsung,picophy-dc-vol-level-adjust = <7>;
vbus-supply = <&reg_usb_hub_vbus>;
status = "okay";
};
/* SD-Card */
&usdhc2 {
assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
assigned-clock-rates = <200000000>;
bus-width = <4>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
disable-wp;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
vmmc-supply = <&reg_usdhc2_vmmc>;
vqmmc-supply = <&reg_nvcc_sd2>;
status = "okay";
};
&iomuxc {
pinctrl_can_int: can-intgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x00
>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
>;
};
pinctrl_ecspi1_cs: ecspi1csgrp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x00
MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x00
MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x00
>;
};
pinctrl_gpiokeys: keygrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x00
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c2
MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c2
>;
};
pinctrl_i2c2_gpio: i2c2gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1e0
MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1e0
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c2
MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c2
>;
};
pinctrl_i2c3_gpio: i2c3gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1e0
MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1e0
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c2
MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c2
>;
};
pinctrl_i2c4_gpio: i2c4gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x1e0
MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x1e0
>;
};
pinctrl_leds: leds1grp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x00
MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x00
>;
};
pinctrl_pcie: pciegrp {
fsl,pins = <
/* COEX2 */
MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x00
/* COEX1 */
MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x12
>;
};
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x40
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x40
>;
};
pinctrl_pwm4: pwm4grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO15_PWM4_OUT 0x40
>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x40
>;
};
pinctrl_tempsense: tempsensegrp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x00
>;
};
pinctrl_tpm: tpmgrp {
fsl,pins = <
MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x140
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x00
MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x00
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x00
MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x00
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
>;
};
pinctrl_usbhubpwr: usbhubpwrgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x00
>;
};
pinctrl_usbotg1pwr: usbotg1pwrgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x00
>;
};
pinctrl_usbotg1: usbotg1grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x80
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x182
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0xc6
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc6
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc6
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc6
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc6
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x40
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x192
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d2
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d2
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d2
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d2
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d2
>;
};
pinctrl_usdhc2_100mhz: usdhc2100mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
>;
};
pinctrl_usdhc2_200mhz: usdhc2200mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
>;
};
};

View File

@@ -39,6 +39,13 @@
gpios = <9 GPIO_ACTIVE_HIGH>;
line-name = "dio1";
};
tpm_rst {
gpio-hog;
output-high;
gpios = <11 GPIO_ACTIVE_HIGH>;
line-name = "tpm_rst#";
};
};
&gpio4 {

View File

@@ -84,8 +84,15 @@
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi2>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>,
<&gpio1 10 GPIO_ACTIVE_LOW>;
status = "okay";
tpm@1 {
compatible = "tcg,tpm_tis-spi";
reg = <0x1>;
spi-max-frequency = <36000000>;
};
};
&gpio1 {
@@ -314,6 +321,7 @@
MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6
MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6
MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6
MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xd6
>;
};

View File

@@ -39,6 +39,13 @@
gpios = <9 GPIO_ACTIVE_HIGH>;
line-name = "dio1";
};
tpm_rst {
gpio-hog;
output-high;
gpios = <11 GPIO_ACTIVE_HIGH>;
line-name = "tpm_rst#";
};
};
&gpio4 {

View File

@@ -104,8 +104,15 @@
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi2>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>,
<&gpio1 10 GPIO_ACTIVE_LOW>;
status = "okay";
tpm@1 {
compatible = "tcg,tpm_tis-spi";
reg = <0x1>;
spi-max-frequency = <36000000>;
};
};
&gpio1 {
@@ -364,6 +371,7 @@
MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6
MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6
MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6
MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xd6
>;
};

View File

@@ -6,6 +6,16 @@
#include "imx8mm-u-boot.dtsi"
/ {
aliases {
eeprom0 = &eeprom_module;
eeprom1 = &eeprom_carrier_board;
eeprom2 = &eeprom_display_adapter;
};
sysinfo {
compatible = "toradex,sysinfo";
};
wdt-reboot {
compatible = "wdt-reboot";
bootph-pre-ram;
@@ -13,12 +23,6 @@
};
};
&{/aliases} {
eeprom0 = &eeprom_module;
eeprom1 = &eeprom_carrier_board;
eeprom2 = &eeprom_display_adapter;
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@25} {
bootph-pre-ram;
};

View File

@@ -139,6 +139,7 @@
A53_L2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
cache-unified;
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
@@ -276,6 +277,7 @@
assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
clock-names = "main_clk";
power-domains = <&pgc_otg1>;
};
usbphynop2: usbphynop2 {
@@ -285,6 +287,7 @@
assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
clock-names = "main_clk";
power-domains = <&pgc_otg2>;
};
soc: soc@0 {
@@ -396,6 +399,7 @@
"pll8k", "pll11k", "clkext3";
dmas = <&sdma2 24 25 0x80000000>;
dma-names = "rx";
#sound-dai-cells = <0>;
status = "disabled";
};
@@ -493,6 +497,8 @@
compatible = "fsl,imx8mm-tmu";
reg = <0x30260000 0x10000>;
clocks = <&clk IMX8MM_CLK_TMU_ROOT>;
nvmem-cells = <&tmu_calib>;
nvmem-cell-names = "calib";
#thermal-sensor-cells = <0>;
};
@@ -547,8 +553,8 @@
reg = <0x30330000 0x10000>;
};
gpr: iomuxc-gpr@30340000 {
compatible = "fsl,imx8mm-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", "syscon";
gpr: syscon@30340000 {
compatible = "fsl,imx8mm-iomuxc-gpr", "syscon";
reg = <0x30340000 0x10000>;
};
@@ -560,22 +566,40 @@
#address-cells = <1>;
#size-cells = <1>;
imx8mm_uid: unique-id@410 {
/*
* The register address below maps to the MX8M
* Fusemap Description Table entries this way.
* Assuming
* reg = <ADDR SIZE>;
* then
* Fuse Address = (ADDR * 4) + 0x400
* Note that if SIZE is greater than 4, then
* each subsequent fuse is located at offset
* +0x10 in Fusemap Description Table (e.g.
* reg = <0x4 0x8> describes fuses 0x410 and
* 0x420).
*/
imx8mm_uid: unique-id@4 { /* 0x410-0x420 */
reg = <0x4 0x8>;
};
cpu_speed_grade: speed-grade@10 {
cpu_speed_grade: speed-grade@10 { /* 0x440 */
reg = <0x10 4>;
};
fec_mac_address: mac-address@90 {
tmu_calib: calib@3c { /* 0x4f0 */
reg = <0x3c 4>;
};
fec_mac_address: mac-address@90 { /* 0x640 */
reg = <0x90 6>;
};
};
anatop: anatop@30360000 {
compatible = "fsl,imx8mm-anatop", "syscon";
anatop: clock-controller@30360000 {
compatible = "fsl,imx8mm-anatop";
reg = <0x30360000 0x10000>;
#clock-cells = <1>;
};
snvs: snvs@30370000 {
@@ -674,13 +698,11 @@
pgc_otg1: power-domain@2 {
#power-domain-cells = <0>;
reg = <IMX8MM_POWER_DOMAIN_OTG1>;
power-domains = <&pgc_hsiomix>;
};
pgc_otg2: power-domain@3 {
#power-domain-cells = <0>;
reg = <IMX8MM_POWER_DOMAIN_OTG2>;
power-domains = <&pgc_hsiomix>;
};
pgc_gpumix: power-domain@4 {
@@ -1098,6 +1120,61 @@
#size-cells = <1>;
ranges = <0x32c00000 0x32c00000 0x400000>;
lcdif: lcdif@32e00000 {
compatible = "fsl,imx8mm-lcdif", "fsl,imx6sx-lcdif";
reg = <0x32e00000 0x10000>;
clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>,
<&clk IMX8MM_CLK_DISP_APB_ROOT>,
<&clk IMX8MM_CLK_DISP_AXI_ROOT>;
clock-names = "pix", "axi", "disp_axi";
assigned-clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>,
<&clk IMX8MM_CLK_DISP_AXI>,
<&clk IMX8MM_CLK_DISP_APB>;
assigned-clock-parents = <&clk IMX8MM_VIDEO_PLL1_OUT>,
<&clk IMX8MM_SYS_PLL2_1000M>,
<&clk IMX8MM_SYS_PLL1_800M>;
assigned-clock-rates = <594000000>, <500000000>, <200000000>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_LCDIF>;
status = "disabled";
port {
lcdif_to_dsim: endpoint {
remote-endpoint = <&dsim_from_lcdif>;
};
};
};
mipi_dsi: dsi@32e10000 {
compatible = "fsl,imx8mm-mipi-dsim";
reg = <0x32e10000 0x400>;
clocks = <&clk IMX8MM_CLK_DSI_CORE>,
<&clk IMX8MM_CLK_DSI_PHY_REF>;
clock-names = "bus_clk", "sclk_mipi";
assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>,
<&clk IMX8MM_CLK_DSI_PHY_REF>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
<&clk IMX8MM_CLK_24M>;
assigned-clock-rates = <266000000>, <24000000>;
samsung,pll-clock-frequency = <24000000>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_DSI>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsim_from_lcdif: endpoint {
remote-endpoint = <&lcdif_to_dsim>;
};
};
};
};
csi: csi@32e20000 {
compatible = "fsl,imx8mm-csi", "fsl,imx7-csi";
reg = <0x32e20000 0x1000>;
@@ -1145,10 +1222,9 @@
compatible = "fsl,imx8mm-mipi-csi2";
reg = <0x32e30000 0x1000>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
assigned-clocks = <&clk IMX8MM_CLK_CSI1_CORE>,
<&clk IMX8MM_CLK_CSI1_PHY_REF>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>,
<&clk IMX8MM_SYS_PLL2_1000M>;
assigned-clocks = <&clk IMX8MM_CLK_CSI1_CORE>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>;
clock-frequency = <333000000>;
clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>,
<&clk IMX8MM_CLK_CSI1_ROOT>,
@@ -1177,7 +1253,7 @@
};
usbotg1: usb@32e40000 {
compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb", "fsl,imx27-usb";
reg = <0x32e40000 0x200>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
@@ -1186,18 +1262,19 @@
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
phys = <&usbphynop1>;
fsl,usbmisc = <&usbmisc1 0>;
power-domains = <&pgc_otg1>;
power-domains = <&pgc_hsiomix>;
status = "disabled";
};
usbmisc1: usbmisc@32e40200 {
compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc",
"fsl,imx6q-usbmisc";
#index-cells = <1>;
reg = <0x32e40200 0x200>;
};
usbotg2: usb@32e50000 {
compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb", "fsl,imx27-usb";
reg = <0x32e50000 0x200>;
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
@@ -1206,12 +1283,13 @@
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
phys = <&usbphynop2>;
fsl,usbmisc = <&usbmisc2 0>;
power-domains = <&pgc_otg2>;
power-domains = <&pgc_hsiomix>;
status = "disabled";
};
usbmisc2: usbmisc@32e50200 {
compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc",
"fsl,imx6q-usbmisc";
#index-cells = <1>;
reg = <0x32e50200 0x200>;
};
@@ -1238,16 +1316,15 @@
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
#dma-cells = <1>;
dma-channels = <4>;
clocks = <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
};
gpmi: nand-controller@33002000{
gpmi: nand-controller@33002000 {
compatible = "fsl,imx8mm-gpmi-nand", "fsl,imx7d-gpmi-nand";
#address-cells = <1>;
#size-cells = <1>;
#size-cells = <0>;
reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
reg-names = "gpmi-nand", "bch";
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
@@ -1268,8 +1345,8 @@
#size-cells = <2>;
device_type = "pci";
bus-range = <0x00 0xff>;
ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */
0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */
<0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
num-lanes = <1>;
num-viewport = <4>;
interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
@@ -1282,6 +1359,10 @@
<0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
fsl,max-link-speed = <2>;
linux,pci-domain = <0>;
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>,
<&clk IMX8MM_CLK_PCIE1_PHY>,
<&clk IMX8MM_CLK_PCIE1_AUX>;
clock-names = "pcie", "pcie_bus", "pcie_aux";
power-domains = <&pgc_pcie>;
resets = <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
<&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
@@ -1291,6 +1372,30 @@
status = "disabled";
};
pcie0_ep: pcie-ep@33800000 {
compatible = "fsl,imx8mm-pcie-ep";
reg = <0x33800000 0x400000>,
<0x18000000 0x8000000>;
reg-names = "dbi", "addr_space";
num-lanes = <1>;
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "dma";
fsl,max-link-speed = <2>;
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>,
<&clk IMX8MM_CLK_PCIE1_PHY>,
<&clk IMX8MM_CLK_PCIE1_AUX>;
clock-names = "pcie", "pcie_bus", "pcie_aux";
power-domains = <&pgc_pcie>;
resets = <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
<&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
reset-names = "apps", "turnoff";
phys = <&pcie_phy>;
phy-names = "pcie-phy";
num-ib-windows = <4>;
num-ob-windows = <4>;
status = "disabled";
};
gpu_3d: gpu@38000000 {
compatible = "vivante,gc";
reg = <0x38000000 0x8000>;

View File

@@ -139,6 +139,7 @@
A53_L2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
cache-unified;
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
@@ -295,6 +296,7 @@
sai2: sai@30020000 {
compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
reg = <0x30020000 0x10000>;
#sound-dai-cells = <0>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_SAI2_IPG>,
<&clk IMX8MN_CLK_DUMMY>,
@@ -309,6 +311,7 @@
sai3: sai@30030000 {
compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
reg = <0x30030000 0x10000>;
#sound-dai-cells = <0>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_SAI3_IPG>,
<&clk IMX8MN_CLK_DUMMY>,
@@ -323,6 +326,7 @@
sai5: sai@30050000 {
compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
reg = <0x30050000 0x10000>;
#sound-dai-cells = <0>;
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_SAI5_IPG>,
<&clk IMX8MN_CLK_DUMMY>,
@@ -339,6 +343,7 @@
sai6: sai@30060000 {
compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
reg = <0x30060000 0x10000>;
#sound-dai-cells = <0>;
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_SAI6_IPG>,
<&clk IMX8MN_CLK_DUMMY>,
@@ -366,6 +371,7 @@
"pll8k", "pll11k", "clkext3";
dmas = <&sdma2 24 25 0x80000000>;
dma-names = "rx";
#sound-dai-cells = <0>;
status = "disabled";
};
@@ -396,6 +402,7 @@
sai7: sai@300b0000 {
compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
reg = <0x300b0000 0x10000>;
#sound-dai-cells = <0>;
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_SAI7_IPG>,
<&clk IMX8MN_CLK_DUMMY>,
@@ -497,6 +504,8 @@
compatible = "fsl,imx8mn-tmu", "fsl,imx8mm-tmu";
reg = <0x30260000 0x10000>;
clocks = <&clk IMX8MN_CLK_TMU_ROOT>;
nvmem-cells = <&tmu_calib>;
nvmem-cell-names = "calib";
#thermal-sensor-cells = <0>;
};
@@ -551,7 +560,7 @@
reg = <0x30330000 0x10000>;
};
gpr: iomuxc-gpr@30340000 {
gpr: syscon@30340000 {
compatible = "fsl,imx8mn-iomuxc-gpr", "syscon";
reg = <0x30340000 0x10000>;
};
@@ -563,23 +572,40 @@
#address-cells = <1>;
#size-cells = <1>;
imx8mn_uid: unique-id@410 {
/*
* The register address below maps to the MX8M
* Fusemap Description Table entries this way.
* Assuming
* reg = <ADDR SIZE>;
* then
* Fuse Address = (ADDR * 4) + 0x400
* Note that if SIZE is greater than 4, then
* each subsequent fuse is located at offset
* +0x10 in Fusemap Description Table (e.g.
* reg = <0x4 0x8> describes fuses 0x410 and
* 0x420).
*/
imx8mn_uid: unique-id@4 { /* 0x410-0x420 */
reg = <0x4 0x8>;
};
cpu_speed_grade: speed-grade@10 {
cpu_speed_grade: speed-grade@10 { /* 0x440 */
reg = <0x10 4>;
};
fec_mac_address: mac-address@90 {
tmu_calib: calib@3c { /* 0x4f0 */
reg = <0x3c 4>;
};
fec_mac_address: mac-address@90 { /* 0x640 */
reg = <0x90 6>;
};
};
anatop: anatop@30360000 {
compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop",
"syscon";
anatop: clock-controller@30360000 {
compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop";
reg = <0x30360000 0x10000>;
#clock-cells = <1>;
};
snvs: snvs@30370000 {
@@ -662,7 +688,6 @@
pgc_otg1: power-domain@1 {
#power-domain-cells = <0>;
reg = <IMX8MN_POWER_DOMAIN_OTG1>;
power-domains = <&pgc_hsiomix>;
};
pgc_gpumix: power-domain@2 {
@@ -1038,6 +1063,72 @@
#size-cells = <1>;
ranges;
lcdif: lcdif@32e00000 {
compatible = "fsl,imx8mn-lcdif", "fsl,imx6sx-lcdif";
reg = <0x32e00000 0x10000>;
clocks = <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>,
<&clk IMX8MN_CLK_DISP_APB_ROOT>,
<&clk IMX8MN_CLK_DISP_AXI_ROOT>;
clock-names = "pix", "axi", "disp_axi";
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_LCDIF>;
status = "disabled";
port {
lcdif_to_dsim: endpoint {
remote-endpoint = <&dsim_from_lcdif>;
};
};
};
mipi_dsi: dsi@32e10000 {
compatible = "fsl,imx8mn-mipi-dsim", "fsl,imx8mm-mipi-dsim";
reg = <0x32e10000 0x400>;
clocks = <&clk IMX8MN_CLK_DSI_CORE>,
<&clk IMX8MN_CLK_DSI_PHY_REF>;
clock-names = "bus_clk", "sclk_mipi";
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_MIPI_DSI>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsim_from_lcdif: endpoint {
remote-endpoint = <&lcdif_to_dsim>;
};
};
};
};
isi: isi@32e20000 {
compatible = "fsl,imx8mn-isi";
reg = <0x32e20000 0x8000>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
<&clk IMX8MN_CLK_DISP_APB_ROOT>;
clock-names = "axi", "apb";
fsl,blk-ctrl = <&disp_blk_ctrl>;
power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_ISI>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
isi_in: endpoint {
remote-endpoint = <&mipi_csi_out>;
};
};
};
};
disp_blk_ctrl: blk-ctrl@32e28000 {
compatible = "fsl,imx8mn-disp-blk-ctrl", "syscon";
reg = <0x32e28000 0x100>;
@@ -1063,11 +1154,60 @@
"lcdif-axi", "lcdif-apb", "lcdif-pix",
"dsi-pclk", "dsi-ref",
"csi-aclk", "csi-pclk";
assigned-clocks = <&clk IMX8MN_CLK_DSI_CORE>,
<&clk IMX8MN_CLK_DSI_PHY_REF>,
<&clk IMX8MN_CLK_DISP_PIXEL>,
<&clk IMX8MN_CLK_DISP_AXI>,
<&clk IMX8MN_CLK_DISP_APB>;
assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>,
<&clk IMX8MN_CLK_24M>,
<&clk IMX8MN_VIDEO_PLL1_OUT>,
<&clk IMX8MN_SYS_PLL2_1000M>,
<&clk IMX8MN_SYS_PLL1_800M>;
assigned-clock-rates = <266000000>,
<24000000>,
<594000000>,
<500000000>,
<200000000>;
#power-domain-cells = <1>;
};
mipi_csi: mipi-csi@32e30000 {
compatible = "fsl,imx8mm-mipi-csi2";
reg = <0x32e30000 0x1000>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
assigned-clocks = <&clk IMX8MN_CLK_CAMERA_PIXEL>;
assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_1000M>;
assigned-clock-rates = <333000000>;
clock-frequency = <333000000>;
clocks = <&clk IMX8MN_CLK_DISP_APB_ROOT>,
<&clk IMX8MN_CLK_CAMERA_PIXEL>,
<&clk IMX8MN_CLK_CSI1_PHY_REF>,
<&clk IMX8MN_CLK_DISP_AXI_ROOT>;
clock-names = "pclk", "wrap", "phy", "axi";
power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_MIPI_CSI>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
};
port@1 {
reg = <1>;
mipi_csi_out: endpoint {
remote-endpoint = <&isi_in>;
};
};
};
};
usbotg1: usb@32e40000 {
compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb";
compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb", "fsl,imx27-usb";
reg = <0x32e40000 0x200>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>;
@@ -1076,12 +1216,13 @@
assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>;
phys = <&usbphynop1>;
fsl,usbmisc = <&usbmisc1 0>;
power-domains = <&pgc_otg1>;
power-domains = <&pgc_hsiomix>;
status = "disabled";
};
usbmisc1: usbmisc@32e40200 {
compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc";
compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc",
"fsl,imx6q-usbmisc";
#index-cells = <1>;
reg = <0x32e40200 0x200>;
};
@@ -1094,7 +1235,6 @@
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
#dma-cells = <1>;
dma-channels = <4>;
clocks = <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
@@ -1103,7 +1243,7 @@
gpmi: nand-controller@33002000 {
compatible = "fsl,imx8mn-gpmi-nand", "fsl,imx7d-gpmi-nand";
#address-cells = <1>;
#size-cells = <1>;
#size-cells = <0>;
reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
reg-names = "gpmi-nand", "bch";
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
@@ -1175,5 +1315,6 @@
assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>;
clock-names = "main_clk";
power-domains = <&pgc_otg1>;
};
};

View File

@@ -6,6 +6,13 @@
#include "imx8mp-u-boot.dtsi"
/ {
/* U-Boot does not yet have a proper PCIe clk driver */
pcie0_refclk: clock-pcie {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
@@ -13,6 +20,10 @@
};
};
&pcie_phy {
clocks = <&pcie0_refclk>;
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@25} {
bootph-pre-ram;
};

View File

@@ -23,6 +23,12 @@
stdout-path = &uart2;
};
clk_xtal25: clock-xtal25 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
connector {
compatible = "usb-c-connector";
label = "USB-C";
@@ -49,6 +55,12 @@
};
};
dmic_codec: dmic-codec {
compatible = "dmic-codec";
num-channels = <1>;
#sound-dai-cells = <0>;
};
gpio-keys {
compatible = "gpio-keys";
autorepeat;
@@ -82,6 +94,17 @@
};
};
bridge-connector {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con: endpoint {
remote-endpoint = <&adv7535_out>;
};
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
@@ -112,10 +135,13 @@
};
};
pcie0_refclk: clock-pcie {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
reg_audio: regulator-wm8962 {
compatible = "regulator-fixed";
regulator-name = "3v3_aud";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&pca6416_1 11 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
@@ -137,6 +163,68 @@
gpio = <&pca6416_1 0 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
sound-adv7535 {
compatible = "simple-audio-card";
simple-audio-card,name = "sound-adv7535";
simple-audio-card,format = "i2s";
simple-audio-card,cpu {
sound-dai = <&sai5>;
system-clock-direction-out;
};
simple-audio-card,codec {
sound-dai = <&adv_bridge>;
};
};
sound-dmic {
compatible = "simple-audio-card";
simple-audio-card,name = "sound-pdm";
simple-audio-card,format = "i2s";
simple-audio-card,bitclock-master = <&dailink_master>;
simple-audio-card,frame-master = <&dailink_master>;
dailink_master: simple-audio-card,cpu {
sound-dai = <&micfil>;
};
simple-audio-card,codec {
sound-dai = <&dmic_codec>;
};
};
sound-wm8962 {
compatible = "simple-audio-card";
simple-audio-card,name = "wm8962";
simple-audio-card,format = "i2s";
simple-audio-card,widgets = "Headphone", "Headphones",
"Microphone", "Headset Mic",
"Speaker", "Speaker";
simple-audio-card,routing = "Headphones", "HPOUTL",
"Headphones", "HPOUTR",
"Speaker", "SPKOUTL",
"Speaker", "SPKOUTR",
"Headset Mic", "MICBIAS",
"IN3R", "Headset Mic";
simple-audio-card,cpu {
sound-dai = <&sai3>;
};
simple-audio-card,codec {
sound-dai = <&wm8962>;
clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO1>;
frame-master;
bitclock-master;
};
};
};
&audio_blk_ctrl {
assigned-clocks = <&clk IMX8MP_AUDIO_PLL1>, <&clk IMX8MP_AUDIO_PLL2>;
assigned-clock-rates = <393216000>, <135475200>;
};
&ecspi2 {
@@ -146,7 +234,7 @@
status = "okay";
tpm: tpm@0 {
compatible = "infineon,slb9670";
compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
reg = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tpm>;
@@ -211,6 +299,42 @@
interrupt-controller;
#interrupt-cells = <2>;
};
adv_bridge: hdmi@3d {
compatible = "adi,adv7535";
reg = <0x3d>, <0x3c>, <0x3e>, <0x3f>;
reg-names = "main", "cec", "edid", "packet";
adi,dsi-lanes = <4>;
#sound-dai-cells = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7535_in: endpoint {
remote-endpoint = <&dsi_out>;
};
};
port@1 {
reg = <1>;
adv7535_out: endpoint {
remote-endpoint = <&hdmi_con>;
};
};
};
};
pcieclk: clock-generator@68 {
compatible = "renesas,9fgv0241";
reg = <0x68>;
clocks = <&clk_xtal25>;
#clock-cells = <1>;
};
};
&i2c3 {
@@ -239,6 +363,34 @@
clock-frequency = <384000>;
status = "okay";
wm8962: audio-codec@1a {
compatible = "wlf,wm8962";
reg = <0x1a>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wm8962>;
clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO1>;
assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO1>;
assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL2_OUT>;
assigned-clock-rates = <22576000>;
DCVDD-supply = <&reg_audio>;
DBVDD-supply = <&reg_audio>;
AVDD-supply = <&reg_audio>;
CPVDD-supply = <&reg_audio>;
MICVDD-supply = <&reg_audio>;
PLLVDD-supply = <&reg_audio>;
SPKVDD1-supply = <&reg_audio>;
SPKVDD2-supply = <&reg_audio>;
gpio-cfg = <
0x0000 /* 0:Default */
0x0000 /* 1:Default */
0x0000 /* 2:FN_DMICCLK */
0x0000 /* 3:Default */
0x0000 /* 4:FN_DMICCDAT */
0x0000 /* 5:Default */
>;
#sound-dai-cells = <0>;
};
pca6416: gpio@20 {
compatible = "nxp,pcal6416";
reg = <0x20>;
@@ -301,6 +453,34 @@
};
};
&lcdif1 {
status = "okay";
};
&micfil {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pdm>;
assigned-clocks = <&clk IMX8MP_CLK_PDM>;
assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
assigned-clock-rates = <49152000>;
status = "okay";
};
&mipi_dsi {
samsung,esc-clock-frequency = <10000000>;
status = "okay";
ports {
port@1 {
reg = <1>;
dsi_out: endpoint {
remote-endpoint = <&adv7535_in>;
};
};
};
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
@@ -309,12 +489,34 @@
};
&pcie_phy {
fsl,clkreq-unsupported;
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
clocks = <&pcie0_refclk>;
clocks = <&pcieclk 1>;
clock-names = "ref";
status = "okay";
};
&sai3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
assigned-clocks = <&clk IMX8MP_CLK_SAI3>,
<&clk IMX8MP_AUDIO_PLL2> ;
assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL2_OUT>;
assigned-clock-rates = <12288000>, <361267200>;
fsl,sai-mclk-direction-output;
status = "okay";
};
&sai5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai5>;
assigned-clocks = <&clk IMX8MP_CLK_SAI5>;
assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
assigned-clock-rates = <12288000>;
fsl,sai-mclk-direction-output;
status = "okay";
};
&snvs_pwrkey {
status = "okay";
};
@@ -471,12 +673,37 @@
>;
};
pinctrl_pdm: pdmgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_PDM_CLK 0xd6
MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_PDM_BIT_STREAM00 0xd6
>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
>;
};
pinctrl_sai3: sai3grp {
fsl,pins = <
MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6
MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6
MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6
MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6
MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6
>;
};
pinctrl_sai5: sai5grp {
fsl,pins = <
MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI5_TX_DATA00 0xd6
MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI5_TX_BCLK 0xd6
MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI5_TX_SYNC 0xd6
>;
};
pinctrl_tpm: tpmgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x19 /* Reset */
@@ -547,4 +774,10 @@
MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
>;
};
pinctrl_wm8962: wm8962grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO14__CCM_CLKO1 0x59
>;
};
};

View File

@@ -50,6 +50,8 @@
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
snps,force_thresh_dma_mode;
snps,mtl-rx-config = <&mtl_rx_setup>;
snps,mtl-tx-config = <&mtl_tx_setup>;
status = "okay";
mdio {
@@ -66,6 +68,71 @@
interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
};
};
mtl_rx_setup: rx-queues-config {
snps,rx-queues-to-use = <5>;
snps,rx-sched-sp;
queue0 {
snps,dcb-algorithm;
snps,priority = <0x1>;
snps,map-to-dma-channel = <0>;
};
queue1 {
snps,dcb-algorithm;
snps,priority = <0x2>;
snps,map-to-dma-channel = <1>;
};
queue2 {
snps,dcb-algorithm;
snps,priority = <0x4>;
snps,map-to-dma-channel = <2>;
};
queue3 {
snps,dcb-algorithm;
snps,priority = <0x8>;
snps,map-to-dma-channel = <3>;
};
queue4 {
snps,dcb-algorithm;
snps,priority = <0xf0>;
snps,map-to-dma-channel = <4>;
};
};
mtl_tx_setup: tx-queues-config {
snps,tx-queues-to-use = <5>;
snps,tx-sched-sp;
queue0 {
snps,dcb-algorithm;
snps,priority = <0x1>;
};
queue1 {
snps,dcb-algorithm;
snps,priority = <0x2>;
};
queue2 {
snps,dcb-algorithm;
snps,priority = <0x4>;
};
queue3 {
snps,dcb-algorithm;
snps,priority = <0x8>;
};
queue4 {
snps,dcb-algorithm;
snps,priority = <0xf0>;
};
};
};
&flexspi {
@@ -206,6 +273,10 @@
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
uart-has-rtscts;
status = "okay";
bluetooth {
compatible = "nxp,88w8997-bt";
};
};
&usdhc1 {

View File

@@ -45,18 +45,15 @@
};
&ecspi1 {
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-rates;
/delete-property/ assigned-clock-parents;
bootph-pre-ram;
flash@0 {
bootph-pre-ram;
};
};
&eqos {
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
/delete-property/ assigned-clock-rates;
};
&gpio1 {
bootph-pre-ram;
};

View File

@@ -0,0 +1,141 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2019, 2021 NXP
* Copyright 2023 Gilles Talis <gilles.talis@gmail.com>
*/
#include "imx8mp-u-boot.dtsi"
/ {
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
bootph-pre-ram;
};
firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
};
};
};
&crypto {
bootph-pre-ram;
};
&ethphy0 {
reset-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>;
reset-delay-us = <15000>;
reset-post-delay-us = <100000>;
};
&fec {
phy-reset-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
phy-reset-duration = <15>;
phy-reset-post-delay = <100>;
};
&gpio1 {
bootph-pre-ram;
};
&gpio2 {
bootph-pre-ram;
};
&gpio3 {
bootph-pre-ram;
};
&gpio4 {
bootph-pre-ram;
};
&gpio5 {
bootph-pre-ram;
};
&i2c1 {
bootph-pre-ram;
};
&pinctrl_i2c1 {
bootph-pre-ram;
};
&pinctrl_pmic {
bootph-pre-ram;
};
&pinctrl_uart2 {
bootph-pre-ram;
};
&pinctrl_usdhc2_gpio {
bootph-pre-ram;
};
&pinctrl_usdhc2 {
bootph-pre-ram;
};
&pinctrl_usdhc3 {
bootph-pre-ram;
};
&pinctrl_wdog {
bootph-pre-ram;
};
&pmic {
bootph-pre-ram;
regulators {
bootph-pre-ram;
};
};
&reg_usdhc2_vmmc {
u-boot,off-on-delay-us = <20000>;
};
&reg_usdhc2_vmmc {
bootph-pre-ram;
};
&uart2 {
bootph-pre-ram;
};
&sec_jr0 {
bootph-pre-ram;
};
&sec_jr1 {
bootph-pre-ram;
};
&sec_jr2 {
bootph-pre-ram;
};
&usdhc1 {
bootph-pre-ram;
};
&usdhc2 {
bootph-pre-ram;
sd-uhs-sdr104;
sd-uhs-ddr50;
};
&usdhc3 {
bootph-pre-ram;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
};
&wdog1 {
bootph-pre-ram;
};

View File

@@ -0,0 +1,507 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2019 NXP
* Copyright 2022 Ideas on Board Oy
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/usb/pd.h>
#include "imx8mp.dtsi"
/ {
model = "Polyhex Debix Model A i.MX8MPlus board";
compatible = "polyhex,imx8mp-debix-model-a", "polyhex,imx8mp-debix", "fsl,imx8mp";
chosen {
stdout-path = &uart2;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_led>;
led-0 {
function = LED_FUNCTION_POWER;
color = <LED_COLOR_ID_RED>;
gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
&A53_0 {
cpu-supply = <&buck2>;
};
&A53_1 {
cpu-supply = <&buck2>;
};
&A53_2 {
cpu-supply = <&buck2>;
};
&A53_3 {
cpu-supply = <&buck2>;
};
&eqos {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eqos>;
phy-connection-type = "rgmii-id";
phy-handle = <&ethphy0>;
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 { /* RTL8211E */
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
reset-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>;
reset-assert-us = <20>;
reset-deassert-us = <200000>;
};
};
};
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
pmic: pmic@25 {
compatible = "nxp,pca9450c";
reg = <0x25>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
interrupt-parent = <&gpio1>;
interrupts = <3 IRQ_TYPE_EDGE_RISING>;
regulators {
buck1: BUCK1 {
regulator-name = "BUCK1";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <2187500>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
};
buck2: BUCK2 {
regulator-name = "BUCK2";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <2187500>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
nxp,dvs-run-voltage = <950000>;
nxp,dvs-standby-voltage = <850000>;
};
buck4: BUCK4{
regulator-name = "BUCK4";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
buck5: BUCK5{
regulator-name = "BUCK5";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
buck6: BUCK6 {
regulator-name = "BUCK6";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
ldo1: LDO1 {
regulator-name = "LDO1";
regulator-min-microvolt = <1600000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo2: LDO2 {
regulator-name = "LDO2";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1150000>;
regulator-boot-on;
regulator-always-on;
};
ldo3: LDO3 {
regulator-name = "LDO3";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo4: LDO4 {
regulator-name = "LDO4";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo5: LDO5 {
regulator-name = "LDO5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
};
&i2c3 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
};
&i2c4 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
status = "okay";
eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
pagesize = <16>;
};
rtc@51 {
compatible = "haoyu,hym8563";
reg = <0x51>;
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "xin32k";
interrupt-parent = <&gpio2>;
interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rtc_int>;
};
};
&i2c6 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c6>;
status = "okay";
};
&snvs_pwrkey {
status = "okay";
};
&uart2 {
/* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
status = "okay";
};
/* SD Card */
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_usdhc2_vmmc>;
bus-width = <4>;
status = "okay";
};
/* eMMC */
&usdhc3 {
assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
assigned-clock-rates = <400000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl_eqos: eqosgrp {
fsl,pins = <
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x1f
MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x1f
MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x19
>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3
MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3
MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91
MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91
MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91
MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91
MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91
MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f
MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f
MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f
MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f
MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f
MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f
MX8MP_IOMUXC_SAI1_RXD1__ENET1_1588_EVENT1_OUT 0x1f
MX8MP_IOMUXC_SAI1_RXD0__ENET1_1588_EVENT1_IN 0x1f
MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x19
>;
};
pinctrl_gpio_led: gpioledgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3
MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3
>;
};
pinctrl_i2c6: i2c6grp {
fsl,pins = <
MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL 0x400001c3
MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA 0x400001c3
>;
};
pinctrl_pmic: pmicirqgrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41
>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41
>;
};
pinctrl_rtc_int: rtcintgrp {
fsl,pins = <
MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x140
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x14f
MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x14f
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x49
MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x49
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49
MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
>;
};
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
>;
};
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6
>;
};
};

View File

@@ -13,6 +13,22 @@
};
};
&pinctrl_i2c1 {
bootph-all;
};
&pinctrl_pmic {
bootph-all;
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@25} {
bootph-all;
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} {
bootph-all;
};
&reg_usdhc2_vmmc {
u-boot,off-on-delay-us = <20000>;
};
@@ -66,7 +82,7 @@
};
&i2c1 {
bootph-pre-ram;
bootph-all;
};
&i2c2 {
@@ -121,17 +137,3 @@
&wdog1 {
bootph-pre-ram;
};
&ethphy0 {
reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
reset-delay-us = <15000>;
reset-post-delay-us = <100000>;
};
&fec {
phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
phy-reset-duration = <15>;
phy-reset-post-delay = <100>;
};

View File

@@ -9,6 +9,11 @@
model = "MSC SM2S-IMX8MPLUS";
compatible = "avnet,sm2s-imx8mp", "fsl,imx8mp";
aliases {
mmc0 = &usdhc3;
mmc1 = &usdhc2;
};
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
@@ -63,3 +68,11 @@
&pmic {
bootph-pre-ram;
};
&uart2 {
bootph-pre-ram;
};
&pinctrl_uart2 {
bootph-pre-ram;
};

View File

@@ -70,6 +70,10 @@
bootph-pre-ram;
};
&usb_dwc3_0 {
dr_mode = "peripheral";
};
&usdhc2 {
bootph-pre-ram;
};

View File

@@ -19,6 +19,36 @@
stdout-path = &uart1;
};
reg_can1_stby: regulator-can1-stby {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1_reg>;
gpio = <&gpio3 20 GPIO_ACTIVE_LOW>;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "can1-stby";
};
reg_can2_stby: regulator-can2-stby {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2_reg>;
gpio = <&gpio3 21 GPIO_ACTIVE_LOW>;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "can2-stby";
};
reg_usb1_vbus: regulator-usb1-vbus {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1_vbus>;
gpio = <&gpio1 12 GPIO_ACTIVE_LOW>;
regulator-max-microvolt = <5000000>;
regulator-min-microvolt = <5000000>;
regulator-name = "usb1_host_vbus";
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
pinctrl-names = "default";
@@ -57,6 +87,21 @@
};
};
/* CAN FD */
&flexcan1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
xceiver-supply = <&reg_can1_stby>;
status = "okay";
};
&flexcan2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
xceiver-supply = <&reg_can2_stby>;
status = "okay";
};
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default", "gpio";
@@ -76,15 +121,15 @@
compatible = "nxp,pca9533";
reg = <0x62>;
led1 {
led-1 {
type = <PCA9532_TYPE_LED>;
};
led2 {
led-2 {
type = <PCA9532_TYPE_LED>;
};
led3 {
led-3 {
type = <PCA9532_TYPE_LED>;
};
};
@@ -101,8 +146,51 @@
status = "okay";
};
/* USB1 Host mode Type-A */
&usb3_phy0 {
vbus-supply = <&reg_usb1_vbus>;
status = "okay";
};
&usb3_0 {
status = "okay";
};
&usb_dwc3_0 {
dr_mode = "host";
status = "okay";
};
/* USB2 4-port USB3.0 HUB */
&usb3_phy1 {
status = "okay";
};
&usb3_1 {
fsl,permanently-attached;
fsl,disable-port-power-control;
status = "okay";
};
&usb_dwc3_1 {
dr_mode = "host";
status = "okay";
};
/* RS232/RS485 */
&uart2 {
assigned-clocks = <&clk IMX8MP_CLK_UART2>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
uart-has-rtscts;
status = "okay";
};
/* SD-Card */
&usdhc2 {
assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
assigned-clock-rates = <200000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_pins>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_pins>;
@@ -113,6 +201,33 @@
status = "okay";
};
&gpio1 {
gpio-line-names = "", "", "X_PMIC_WDOG_B", "",
"PMIC_SD_VSEL", "", "", "", "", "",
"", "", "USB1_OTG_PWR", "", "", "X_nETHPHY_INT";
};
&gpio2 {
gpio-line-names = "", "", "", "",
"", "", "", "", "", "",
"", "", "X_SD2_CD_B", "", "", "",
"", "", "", "SD2_RESET_B";
};
&gpio3 {
gpio-line-names = "", "", "", "",
"", "", "", "", "", "",
"", "", "", "", "", "",
"", "", "", "", "nCAN1_EN", "nCAN2_EN";
};
&gpio4 {
gpio-line-names = "", "", "", "",
"", "", "", "", "", "",
"", "", "", "", "", "",
"", "", "X_PMIC_IRQ_B", "", "nENET0_INT_PWDN";
};
&iomuxc {
pinctrl_eqos: eqosgrp {
fsl,pins = <
@@ -134,6 +249,32 @@
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x154
MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x154
>;
};
pinctrl_flexcan2: flexcan2grp {
fsl,pins = <
MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154
MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154
>;
};
pinctrl_flexcan1_reg: flexcan1reggrp {
fsl,pins = <
MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x154
>;
};
pinctrl_flexcan2_reg: flexcan2reggrp {
fsl,pins = <
MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x154
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
@@ -161,6 +302,21 @@
>;
};
pinctrl_usb1_vbus: usb1vbusgrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x10
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140
MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140
MX8MP_IOMUXC_SAI3_RXC__UART2_DCE_CTS 0x140
MX8MP_IOMUXC_SAI3_RXD__UART2_DCE_RTS 0x140
>;
};
pinctrl_usdhc2_pins: usdhc2-gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4

View File

@@ -4,6 +4,15 @@
*/
#include "imx8mp-venice-gw702x-u-boot.dtsi"
&gpio1 {
tpm_rst {
gpio-hog;
output-high;
gpios = <11 GPIO_ACTIVE_HIGH>;
line-name = "tpm_rst#";
};
};
&gpio4 {
dio_1 {
gpio-hog;

View File

@@ -83,8 +83,14 @@
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi2>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>,
<&gpio1 10 GPIO_ACTIVE_LOW>;
status = "okay";
tpm@1 {
compatible = "tcg,tpm_tis-spi";
reg = <0x1>;
spi-max-frequency = <36000000>;
};
};
&gpio4 {
@@ -286,6 +292,7 @@
MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140
MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140
MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140
MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x140
>;
};

View File

@@ -10,6 +10,15 @@
reset-post-delay-us = <300000>;
};
&gpio1 {
tpm_rst {
gpio-hog;
output-high;
gpios = <11 GPIO_ACTIVE_HIGH>;
line-name = "tpm_rst#";
};
};
&gpio4 {
dio_1 {
gpio-hog;

View File

@@ -95,8 +95,14 @@
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi2>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>,
<&gpio1 10 GPIO_ACTIVE_LOW>;
status = "okay";
tpm@1 {
compatible = "tcg,tpm_tis-spi";
reg = <0x1>;
spi-max-frequency = <36000000>;
};
};
&gpio4 {
@@ -327,6 +333,7 @@
MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140
MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140
MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140
MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x140
>;
};

View File

@@ -6,6 +6,16 @@
#include "imx8mp-u-boot.dtsi"
/ {
aliases {
eeprom0 = &eeprom_module;
eeprom1 = &eeprom_carrier_board;
eeprom2 = &eeprom_display_adapter;
};
sysinfo {
compatible = "toradex,sysinfo";
};
wdt-reboot {
compatible = "wdt-reboot";
bootph-pre-ram;
@@ -13,12 +23,6 @@
};
};
&{/aliases} {
eeprom0 = &eeprom_module;
eeprom1 = &eeprom_carrier_board;
eeprom2 = &eeprom_display_adapter;
};
&clk {
bootph-all;
bootph-pre-ram;

View File

@@ -202,6 +202,60 @@
clock-output-names = "clk_ext4";
};
funnel {
/*
* non-configurable funnel don't show up on the AMBA
* bus. As such no need to add "arm,primecell".
*/
compatible = "arm,coresight-static-funnel";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
ca_funnel_in_port0: endpoint {
remote-endpoint = <&etm0_out_port>;
};
};
port@1 {
reg = <1>;
ca_funnel_in_port1: endpoint {
remote-endpoint = <&etm1_out_port>;
};
};
port@2 {
reg = <2>;
ca_funnel_in_port2: endpoint {
remote-endpoint = <&etm2_out_port>;
};
};
port@3 {
reg = <3>;
ca_funnel_in_port3: endpoint {
remote-endpoint = <&etm3_out_port>;
};
};
};
out-ports {
port {
ca_funnel_out_port0: endpoint {
remote-endpoint = <&hugo_funnel_in_port0>;
};
};
};
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
@@ -304,6 +358,153 @@
nvmem-cells = <&imx8mp_uid>;
nvmem-cell-names = "soc_unique_id";
etm0: etm@28440000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0x28440000 0x1000>;
cpu = <&A53_0>;
clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
clock-names = "apb_pclk";
out-ports {
port {
etm0_out_port: endpoint {
remote-endpoint = <&ca_funnel_in_port0>;
};
};
};
};
etm1: etm@28540000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0x28540000 0x1000>;
cpu = <&A53_1>;
clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
clock-names = "apb_pclk";
out-ports {
port {
etm1_out_port: endpoint {
remote-endpoint = <&ca_funnel_in_port1>;
};
};
};
};
etm2: etm@28640000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0x28640000 0x1000>;
cpu = <&A53_2>;
clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
clock-names = "apb_pclk";
out-ports {
port {
etm2_out_port: endpoint {
remote-endpoint = <&ca_funnel_in_port2>;
};
};
};
};
etm3: etm@28740000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0x28740000 0x1000>;
cpu = <&A53_3>;
clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
clock-names = "apb_pclk";
out-ports {
port {
etm3_out_port: endpoint {
remote-endpoint = <&ca_funnel_in_port3>;
};
};
};
};
funnel@28c03000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x28c03000 0x1000>;
clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
clock-names = "apb_pclk";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
hugo_funnel_in_port0: endpoint {
remote-endpoint = <&ca_funnel_out_port0>;
};
};
port@1 {
reg = <1>;
hugo_funnel_in_port1: endpoint {
/* M7 input */
};
};
port@2 {
reg = <2>;
hugo_funnel_in_port2: endpoint {
/* DSP input */
};
};
/* the other input ports are not connect to anything */
};
out-ports {
port {
hugo_funnel_out_port0: endpoint {
remote-endpoint = <&etf_in_port>;
};
};
};
};
etf@28c04000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0x28c04000 0x1000>;
clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
clock-names = "apb_pclk";
in-ports {
port {
etf_in_port: endpoint {
remote-endpoint = <&hugo_funnel_out_port0>;
};
};
};
out-ports {
port {
etf_out_port: endpoint {
remote-endpoint = <&etr_in_port>;
};
};
};
};
etr@28c06000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0x28c06000 0x1000>;
clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
clock-names = "apb_pclk";
in-ports {
port {
etr_in_port: endpoint {
remote-endpoint = <&etf_out_port>;
};
};
};
};
aips1: bus@30000000 {
compatible = "fsl,aips-bus", "simple-bus";
reg = <0x30000000 0x400000>;
@@ -497,7 +698,7 @@
snvs_rtc: snvs-rtc-lp {
compatible = "fsl,sec-v4.0-mon-rtc-lp";
regmap =<&snvs>;
regmap = <&snvs>;
offset = <0x34>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
@@ -534,26 +735,16 @@
<&clk IMX8MP_CLK_A53_CORE>,
<&clk IMX8MP_CLK_NOC>,
<&clk IMX8MP_CLK_NOC_IO>,
<&clk IMX8MP_CLK_GIC>,
<&clk IMX8MP_CLK_AUDIO_AHB>,
<&clk IMX8MP_CLK_AUDIO_AXI_SRC>,
<&clk IMX8MP_AUDIO_PLL1>,
<&clk IMX8MP_AUDIO_PLL2>;
<&clk IMX8MP_CLK_GIC>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
<&clk IMX8MP_ARM_PLL_OUT>,
<&clk IMX8MP_SYS_PLL2_1000M>,
<&clk IMX8MP_SYS_PLL1_800M>,
<&clk IMX8MP_SYS_PLL2_500M>,
<&clk IMX8MP_SYS_PLL1_800M>,
<&clk IMX8MP_SYS_PLL1_800M>;
<&clk IMX8MP_SYS_PLL2_500M>;
assigned-clock-rates = <0>, <0>,
<1000000000>,
<800000000>,
<500000000>,
<400000000>,
<800000000>,
<393216000>,
<361267200>;
<500000000>;
};
src: reset-controller@30390000 {
@@ -595,6 +786,19 @@
reg = <IMX8MP_POWER_DOMAIN_USB2_PHY>;
};
pgc_audio: power-domain@5 {
#power-domain-cells = <0>;
reg = <IMX8MP_POWER_DOMAIN_AUDIOMIX>;
clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>,
<&clk IMX8MP_CLK_AUDIO_AXI>;
assigned-clocks = <&clk IMX8MP_CLK_AUDIO_AHB>,
<&clk IMX8MP_CLK_AUDIO_AXI_SRC>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
<&clk IMX8MP_SYS_PLL1_800M>;
assigned-clock-rates = <400000000>,
<600000000>;
};
pgc_gpu2d: power-domain@6 {
#power-domain-cells = <0>;
reg = <IMX8MP_POWER_DOMAIN_GPU2D>;
@@ -653,7 +857,7 @@
pgc_vpumix: power-domain@19 {
#power-domain-cells = <0>;
reg = <IMX8MP_POWER_DOMAIN_VPUMIX>;
clocks =<&clk IMX8MP_CLK_VPU_ROOT>;
clocks = <&clk IMX8MP_CLK_VPU_ROOT>;
};
pgc_vpu_g1: power-domain@20 {
@@ -1147,6 +1351,198 @@
};
};
aips5: bus@30c00000 {
compatible = "fsl,aips-bus", "simple-bus";
reg = <0x30c00000 0x400000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
spba-bus@30c00000 {
compatible = "fsl,spba-bus", "simple-bus";
reg = <0x30c00000 0x100000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
sai1: sai@30c10000 {
compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
reg = <0x30c10000 0x10000>;
#sound-dai-cells = <0>;
clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_IPG>,
<&clk IMX8MP_CLK_DUMMY>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK3>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
dma-names = "rx", "tx";
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
sai2: sai@30c20000 {
compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
reg = <0x30c20000 0x10000>;
#sound-dai-cells = <0>;
clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_IPG>,
<&clk IMX8MP_CLK_DUMMY>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK3>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
dma-names = "rx", "tx";
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
sai3: sai@30c30000 {
compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
reg = <0x30c30000 0x10000>;
#sound-dai-cells = <0>;
clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_IPG>,
<&clk IMX8MP_CLK_DUMMY>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK3>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
dma-names = "rx", "tx";
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
sai5: sai@30c50000 {
compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
reg = <0x30c50000 0x10000>;
#sound-dai-cells = <0>;
clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_IPG>,
<&clk IMX8MP_CLK_DUMMY>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK3>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
dma-names = "rx", "tx";
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
sai6: sai@30c60000 {
compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
reg = <0x30c60000 0x10000>;
#sound-dai-cells = <0>;
clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_IPG>,
<&clk IMX8MP_CLK_DUMMY>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK3>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
dma-names = "rx", "tx";
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
sai7: sai@30c80000 {
compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
reg = <0x30c80000 0x10000>;
#sound-dai-cells = <0>;
clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_IPG>,
<&clk IMX8MP_CLK_DUMMY>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK3>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>;
dma-names = "rx", "tx";
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
easrc: easrc@30c90000 {
compatible = "fsl,imx8mp-easrc", "fsl,imx8mn-easrc";
reg = <0x30c90000 0x10000>;
interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_ASRC_IPG>;
clock-names = "mem";
dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>,
<&sdma2 18 23 0> , <&sdma2 19 23 0>,
<&sdma2 20 23 0> , <&sdma2 21 23 0>,
<&sdma2 22 23 0> , <&sdma2 23 23 0>;
dma-names = "ctx0_rx", "ctx0_tx",
"ctx1_rx", "ctx1_tx",
"ctx2_rx", "ctx2_tx",
"ctx3_rx", "ctx3_tx";
firmware-name = "imx/easrc/easrc-imx8mn.bin";
fsl,asrc-rate = <8000>;
fsl,asrc-format = <2>;
status = "disabled";
};
micfil: audio-controller@30ca0000 {
compatible = "fsl,imx8mp-micfil";
reg = <0x30ca0000 0x10000>;
#sound-dai-cells = <0>;
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_PDM_IPG>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_PDM_SEL>,
<&clk IMX8MP_AUDIO_PLL1_OUT>,
<&clk IMX8MP_AUDIO_PLL2_OUT>,
<&clk IMX8MP_CLK_EXT3>;
clock-names = "ipg_clk", "ipg_clk_app",
"pll8k", "pll11k", "clkext3";
dmas = <&sdma2 24 25 0x80000000>;
dma-names = "rx";
status = "disabled";
};
};
sdma3: dma-controller@30e00000 {
compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
reg = <0x30e00000 0x10000>;
#dma-cells = <3>;
clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT>,
<&clk IMX8MP_CLK_AUDIO_ROOT>;
clock-names = "ipg", "ahb";
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
};
sdma2: dma-controller@30e10000 {
compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
reg = <0x30e10000 0x10000>;
#dma-cells = <3>;
clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SDMA2_ROOT>,
<&clk IMX8MP_CLK_AUDIO_ROOT>;
clock-names = "ipg", "ahb";
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
};
audio_blk_ctrl: clock-controller@30e20000 {
compatible = "fsl,imx8mp-audio-blk-ctrl";
reg = <0x30e20000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>,
<&clk IMX8MP_CLK_SAI1>,
<&clk IMX8MP_CLK_SAI2>,
<&clk IMX8MP_CLK_SAI3>,
<&clk IMX8MP_CLK_SAI5>,
<&clk IMX8MP_CLK_SAI6>,
<&clk IMX8MP_CLK_SAI7>;
clock-names = "ahb",
"sai1", "sai2", "sai3",
"sai5", "sai6", "sai7";
power-domains = <&pgc_audio>;
};
};
noc: interconnect@32700000 {
compatible = "fsl,imx8mp-noc", "fsl,imx8m-noc";
reg = <0x32700000 0x100000>;
@@ -1174,6 +1570,118 @@
#size-cells = <1>;
ranges;
isi_0: isi@32e00000 {
compatible = "fsl,imx8mp-isi";
reg = <0x32e00000 0x4000>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
<&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
clock-names = "axi", "apb";
fsl,blk-ctrl = <&media_blk_ctrl>;
power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISI>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
isi_in_0: endpoint {
remote-endpoint = <&mipi_csi_0_out>;
};
};
port@1 {
reg = <1>;
isi_in_1: endpoint {
remote-endpoint = <&mipi_csi_1_out>;
};
};
};
};
dewarp: dwe@32e30000 {
compatible = "nxp,imx8mp-dw100";
reg = <0x32e30000 0x10000>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
<&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
clock-names = "axi", "ahb";
power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_DWE>;
};
mipi_csi_0: csi@32e40000 {
compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2";
reg = <0x32e40000 0x10000>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <500000000>;
clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
<&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>,
<&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>,
<&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;
clock-names = "pclk", "wrap", "phy", "axi";
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;
assigned-clock-rates = <500000000>;
power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_1>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
};
port@1 {
reg = <1>;
mipi_csi_0_out: endpoint {
remote-endpoint = <&isi_in_0>;
};
};
};
};
mipi_csi_1: csi@32e50000 {
compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2";
reg = <0x32e50000 0x10000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <266000000>;
clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
<&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>,
<&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>,
<&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;
clock-names = "pclk", "wrap", "phy", "axi";
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;
assigned-clock-rates = <266000000>;
power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_2>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
};
port@1 {
reg = <1>;
mipi_csi_1_out: endpoint {
remote-endpoint = <&isi_in_1>;
};
};
};
};
mipi_dsi: dsi@32e60000 {
compatible = "fsl,imx8mp-mipi-dsim";
reg = <0x32e60000 0x400>;
@@ -1382,8 +1890,8 @@
#size-cells = <2>;
device_type = "pci";
bus-range = <0x00 0xff>;
ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */
<0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */
<0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
num-lanes = <1>;
num-viewport = <4>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;

View File

@@ -3,6 +3,8 @@
* Copyright 2022 NXP
*/
#include "imx93-u-boot.dtsi"
/ {
wdt-reboot {
compatible = "wdt-reboot";
@@ -131,10 +133,6 @@
phy-reset-post-delay = <100>;
};
&eqos {
compatible = "fsl,imx-eqos";
};
&ethphy1 {
reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>;
reset-assert-us = <15000>;

View File

@@ -0,0 +1,293 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2023 PHYTEC Messtechnik GmbH
* Christoph Stoidner <c.stoidner@phytec.de>
*
* Product homepage:
* phyBOARD-Segin carrier board is reused for the i.MX93 design.
* https://www.phytec.eu/en/produkte/single-board-computer/phyboard-segin-imx6ul/
*/
#include "imx93-u-boot.dtsi"
/ {
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog3>;
bootph-pre-ram;
bootph-some-ram;
};
aliases {
ethernet0 = &fec;
ethernet1 = &eqos;
};
firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
};
};
};
&{/soc@0} {
bootph-all;
bootph-pre-ram;
};
&aips1 {
bootph-pre-ram;
bootph-all;
};
&aips2 {
bootph-pre-ram;
bootph-some-ram;
};
&aips3 {
bootph-pre-ram;
bootph-some-ram;
};
&iomuxc {
bootph-pre-ram;
bootph-some-ram;
};
&reg_usdhc2_vmmc {
u-boot,off-on-delay-us = <20000>;
bootph-pre-ram;
bootph-some-ram;
};
&pinctrl_reg_usdhc2_vmmc {
bootph-pre-ram;
};
&pinctrl_uart1 {
bootph-pre-ram;
bootph-some-ram;
};
&pinctrl_usdhc1 {
bootph-pre-ram;
bootph-some-ram;
};
&pinctrl_usdhc2_cd {
bootph-pre-ram;
bootph-some-ram;
};
&pinctrl_usdhc2_default {
bootph-pre-ram;
bootph-some-ram;
};
&pinctrl_usdhc2_100mhz {
bootph-pre-ram;
bootph-some-ram;
};
&pinctrl_usdhc2_200mhz {
bootph-pre-ram;
bootph-some-ram;
};
&gpio1 {
bootph-pre-ram;
bootph-some-ram;
};
&gpio2 {
bootph-pre-ram;
bootph-some-ram;
};
&gpio3 {
bootph-pre-ram;
bootph-some-ram;
};
&gpio4 {
bootph-pre-ram;
bootph-some-ram;
};
&lpuart1 {
bootph-pre-ram;
bootph-some-ram;
};
&usdhc1 {
bootph-pre-ram;
bootph-some-ram;
};
&usdhc2 {
bootph-pre-ram;
bootph-some-ram;
fsl,signal-voltage-switch-extra-delay-ms = <8>;
};
&lpi2c1 {
bootph-pre-ram;
bootph-some-ram;
};
&lpi2c2 {
bootph-pre-ram;
bootph-some-ram;
};
&lpi2c3 {
bootph-pre-ram;
bootph-some-ram;
};
&s4muap {
bootph-pre-ram;
bootph-some-ram;
status = "okay";
};
&clk {
bootph-all;
bootph-pre-ram;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-rates;
/delete-property/ assigned-clock-parents;
};
&osc_32k {
bootph-all;
bootph-pre-ram;
};
&osc_24m {
bootph-all;
bootph-pre-ram;
};
&clk_ext1 {
bootph-all;
bootph-pre-ram;
};
&wdog3 {
bootph-all;
bootph-pre-ram;
};
/*
* The two nodes below won't be needed once nxp,pca9451a
* support is added to the Linux kernel.
*/
&iomuxc {
pinctrl_lpi2c3: lpi2c3grp {
bootph-pre-ram;
fsl,pins = <
MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e
MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e
>;
};
pinctrl_pmic: pmicgrp {
bootph-pre-ram;
fsl,pins = <
MX93_PAD_ENET2_RD3__GPIO4_IO27 0x31e
>;
};
};
&lpi2c3 {
bootph-pre-ram;
bootph-some-ram;
clock-frequency = <400000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_lpi2c3>;
pinctrl-1 = <&pinctrl_lpi2c3>;
status = "okay";
pmic@25 {
bootph-pre-ram;
bootph-some-ram;
compatible = "nxp,pca9451a";
reg = <0x25>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
interrupt-parent = <&gpio4>;
interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
regulators {
bootph-pre-ram;
bootph-some-ram;
buck1: BUCK1 {
regulator-name = "VDD_SOC";
regulator-min-microvolt = <610000>;
regulator-max-microvolt = <950000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
};
buck2: BUCK2 {
regulator-name = "VDDQ_0V6";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <600000>;
regulator-boot-on;
regulator-always-on;
};
buck4: BUCK4 {
regulator-name = "VDD_3V3_BUCK";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
buck5: BUCK5 {
regulator-name = "VDD_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
buck6: BUCK6 {
regulator-name = "VDD_1V1";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-boot-on;
regulator-always-on;
};
ldo1: LDO1 {
regulator-name = "PMIC_SNVS_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
ldo4: LDO4 {
regulator-name = "VDD_0V8";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <800000>;
regulator-boot-on;
regulator-always-on;
};
ldo5: LDO5 {
regulator-name = "NVCC_SD2";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
};
};

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@@ -0,0 +1,117 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2023 PHYTEC Messtechnik GmbH
* Author: Wadim Egorov <w.egorov@phytec.de>, Christoph Stoidner <c.stoidner@phytec.de>
* Copyright (C) 2024 Mathieu Othacehe <m.othacehe@gmail.com>
*
* Product homepage:
* phyBOARD-Segin carrier board is reused for the i.MX93 design.
* https://www.phytec.eu/en/produkte/single-board-computer/phyboard-segin-imx6ul/
*/
/dts-v1/;
#include "imx93-phycore-som.dtsi"
/{
model = "PHYTEC phyBOARD-Segin-i.MX93";
compatible = "phytec,imx93-phyboard-segin", "phytec,imx93-phycore-som",
"fsl,imx93";
chosen {
stdout-path = &lpuart1;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "VCC_SD";
};
};
/* Console */
&lpuart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
/* eMMC */
&usdhc1 {
no-1-8-v;
};
/* SD-Card */
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2_default>, <&pinctrl_usdhc2_cd>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>;
bus-width = <4>;
cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
no-mmc;
no-sdio;
vmmc-supply = <&reg_usdhc2_vmmc>;
status = "okay";
};
&iomuxc {
pinctrl_uart1: uart1grp {
fsl,pins = <
MX93_PAD_UART1_RXD__LPUART1_RX 0x31e
MX93_PAD_UART1_TXD__LPUART1_TX 0x30e
>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e
>;
};
pinctrl_usdhc2_cd: usdhc2cdgrp {
fsl,pins = <
MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e
>;
};
pinctrl_usdhc2_default: usdhc2grp {
fsl,pins = <
MX93_PAD_SD2_CLK__USDHC2_CLK 0x179e
MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e
MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x138e
MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e
MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
pinctrl_usdhc2_100mhz: usdhc2grp {
fsl,pins = <
MX93_PAD_SD2_CLK__USDHC2_CLK 0x179e
MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e
MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x139e
MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e
MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
pinctrl_usdhc2_200mhz: usdhc2grp {
fsl,pins = <
MX93_PAD_SD2_CLK__USDHC2_CLK 0x178e
MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e
MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x139e
MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x139e
MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x139e
MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e
MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
};

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@@ -0,0 +1,126 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2023 PHYTEC Messtechnik GmbH
* Author: Wadim Egorov <w.egorov@phytec.de>, Christoph Stoidner <c.stoidner@phytec.de>
* Copyright (C) 2024 Mathieu Othacehe <m.othacehe@gmail.com>
*
* Product homepage:
* https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-91-93/
*/
#include <dt-bindings/leds/common.h>
#include "imx93.dtsi"
/{
model = "PHYTEC phyCORE-i.MX93";
compatible = "phytec,imx93-phycore-som", "fsl,imx93";
reserved-memory {
ranges;
#address-cells = <2>;
#size-cells = <2>;
linux,cma {
compatible = "shared-dma-pool";
reusable;
alloc-ranges = <0 0x80000000 0 0x40000000>;
size = <0 0x10000000>;
linux,cma-default;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_leds>;
led-0 {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_HEARTBEAT;
gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
};
/* Ethernet */
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
phy-mode = "rmii";
phy-handle = <&ethphy1>;
fsl,magic-packet;
assigned-clocks = <&clk IMX93_CLK_ENET_TIMER1>,
<&clk IMX93_CLK_ENET_REF>,
<&clk IMX93_CLK_ENET_REF_PHY>;
assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
<&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
<&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
assigned-clock-rates = <100000000>, <50000000>, <50000000>;
status = "okay";
mdio: mdio {
clock-frequency = <5000000>;
#address-cells = <1>;
#size-cells = <0>;
ethphy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
};
/* eMMC */
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
bus-width = <8>;
non-removable;
status = "okay";
};
/* Watchdog */
&wdog3 {
status = "okay";
};
&iomuxc {
pinctrl_fec: fecgrp {
fsl,pins = <
MX93_PAD_ENET2_MDC__ENET1_MDC 0x50e
MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x502
MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e
MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e
MX93_PAD_ENET2_RXC__ENET1_RX_ER 0x5fe
MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e
MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x50e
MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x50e
MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x50e
MX93_PAD_ENET2_TD2__ENET1_TX_CLK 0x4000050e
>;
};
pinctrl_leds: ledsgrp {
fsl,pins = <
MX93_PAD_I2C1_SDA__GPIO1_IO01 0x31e
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX93_PAD_SD1_CLK__USDHC1_CLK 0x179e
MX93_PAD_SD1_CMD__USDHC1_CMD 0x1386
MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x138e
MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x1386
MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x138e
MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x1386
MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x1386
MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x1386
MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x1386
MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x1386
MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e
>;
};
};

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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2023 Mathieu Othacehe <m.othacehe@gmail.com>
*/
/ {
binman: binman {
multiple-images;
};
};
&binman {
u-boot-spl-ddr {
align = <4>;
align-size = <4>;
filename = "u-boot-spl-ddr.bin";
pad-byte = <0xff>;
u-boot-spl {
align-end = <4>;
filename = "u-boot-spl.bin";
};
ddr-1d-imem-fw {
filename = "lpddr4_imem_1d_v202201.bin";
align-end = <4>;
type = "blob-ext";
};
ddr-1d-dmem-fw {
filename = "lpddr4_dmem_1d_v202201.bin";
align-end = <4>;
type = "blob-ext";
};
ddr-2d-imem-fw {
filename = "lpddr4_imem_2d_v202201.bin";
align-end = <4>;
type = "blob-ext";
};
ddr-2d-dmem-fw {
filename = "lpddr4_dmem_2d_v202201.bin";
align-end = <4>;
type = "blob-ext";
};
};
spl {
filename = "spl.bin";
mkimage {
args = "-n spl/u-boot-spl.cfgout -T imx8image -e 0x2049A000";
blob {
filename = "u-boot-spl-ddr.bin";
};
};
};
u-boot-container {
filename = "u-boot-container.bin";
mkimage {
args = "-n u-boot-container.cfgout -T imx8image -e 0x0";
blob {
filename = "u-boot.bin";
};
};
};
imx-boot {
filename = "flash.bin";
pad-byte = <0x00>;
spl: blob-ext@1 {
filename = "spl.bin";
offset = <0x0>;
align-size = <0x400>;
align = <0x400>;
};
uboot: blob-ext@2 {
filename = "u-boot-container.bin";
};
};
};

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@@ -0,0 +1,266 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2022 NXP
* Copyright 2023 Variscite Ltd.
*/
#include "imx93-u-boot.dtsi"
/ {
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog3>;
bootph-pre-ram;
bootph-some-ram;
};
aliases {
ethernet0 = &eqos;
ethernet1 = &fec;
};
firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
};
};
};
&{/soc@0} {
bootph-all;
bootph-pre-ram;
};
&aips1 {
bootph-pre-ram;
bootph-all;
};
&aips2 {
bootph-pre-ram;
bootph-some-ram;
};
&aips3 {
bootph-pre-ram;
bootph-some-ram;
};
&iomuxc {
bootph-pre-ram;
bootph-some-ram;
};
&reg_usdhc2_vmmc {
u-boot,off-on-delay-us = <20000>;
bootph-pre-ram;
bootph-some-ram;
};
&pinctrl_reg_usdhc2_vmmc {
bootph-pre-ram;
};
&pinctrl_uart1 {
bootph-pre-ram;
bootph-some-ram;
};
&pinctrl_usdhc2 {
bootph-pre-ram;
bootph-some-ram;
};
&gpio1 {
bootph-pre-ram;
bootph-some-ram;
};
&gpio2 {
bootph-pre-ram;
bootph-some-ram;
};
&gpio3 {
bootph-pre-ram;
bootph-some-ram;
};
&gpio4 {
bootph-pre-ram;
bootph-some-ram;
};
&lpuart1 {
bootph-pre-ram;
bootph-some-ram;
};
&usdhc1 {
bootph-pre-ram;
bootph-some-ram;
};
&usdhc2 {
bootph-pre-ram;
bootph-some-ram;
fsl,signal-voltage-switch-extra-delay-ms = <8>;
};
&ethphy0 {
reset-gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
reset-assert-us = <15000>;
reset-deassert-us = <100000>;
};
&ethphy1 {
reset-gpios = <&pca9534 5 GPIO_ACTIVE_LOW>;
reset-assert-us = <15000>;
reset-deassert-us = <100000>;
};
&s4muap {
bootph-pre-ram;
bootph-some-ram;
status = "okay";
};
&clk {
bootph-all;
bootph-pre-ram;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-rates;
};
&osc_32k {
bootph-all;
bootph-pre-ram;
};
&osc_24m {
bootph-all;
bootph-pre-ram;
};
&clk_ext1 {
bootph-all;
bootph-pre-ram;
};
/*
* The two nodes below won't be needed once nxp,pca9451a
* support is added to the Linux kernel.
*/
&iomuxc {
pinctrl_lpi2c3: lpi2c3grp {
bootph-pre-ram;
fsl,pins = <
MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e
MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e
>;
};
};
&lpi2c3 {
bootph-pre-ram;
bootph-some-ram;
clock-frequency = <400000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_lpi2c3>;
pinctrl-1 = <&pinctrl_lpi2c3>;
status = "okay";
pmic@25 {
bootph-pre-ram;
bootph-some-ram;
compatible = "nxp,pca9451a";
reg = <0x25>;
pinctrl-names = "default";
regulators {
bootph-pre-ram;
buck1: BUCK1 {
regulator-name = "BUCK1";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <2187500>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
};
buck2: BUCK2 {
regulator-name = "BUCK2";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <2187500>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
};
buck4: BUCK4{
regulator-name = "BUCK4";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
buck5: BUCK5{
regulator-name = "BUCK5";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
buck6: BUCK6 {
regulator-name = "BUCK6";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
ldo1: LDO1 {
regulator-name = "LDO1";
regulator-min-microvolt = <1600000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo2: LDO2 {
regulator-name = "LDO2";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1150000>;
regulator-boot-on;
regulator-always-on;
};
ldo3: LDO3 {
regulator-name = "LDO3";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo4: LDO4 {
regulator-name = "LDO4";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo5: LDO5 {
regulator-name = "LDO5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
};
};

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2021 NXP
* Copyright 2023 Variscite Ltd.
*/
/dts-v1/;
#include "imx93-var-som.dtsi"
/{
model = "Variscite VAR-SOM-MX93 on Symphony evaluation board";
compatible = "variscite,var-som-mx93-symphony",
"variscite,var-som-mx93", "fsl,imx93";
aliases {
ethernet0 = &eqos;
ethernet1 = &fec;
};
chosen {
stdout-path = &lpuart1;
};
/*
* Needed only for Symphony <= v1.5
*/
reg_fec_phy: regulator-fec-phy {
compatible = "regulator-fixed";
regulator-name = "fec-phy";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-enable-ramp-delay = <20000>;
gpio = <&pca9534 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 18 GPIO_ACTIVE_HIGH>;
off-on-delay-us = <20000>;
enable-active-high;
};
reg_vref_1v8: regulator-adc-vref {
compatible = "regulator-fixed";
regulator-name = "vref_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
ethosu_mem: ethosu-region@88000000 {
compatible = "shared-dma-pool";
reusable;
reg = <0x0 0x88000000 0x0 0x8000000>;
};
vdev0vring0: vdev0vring0@87ee0000 {
reg = <0 0x87ee0000 0 0x8000>;
no-map;
};
vdev0vring1: vdev0vring1@87ee8000 {
reg = <0 0x87ee8000 0 0x8000>;
no-map;
};
vdev1vring0: vdev1vring0@87ef0000 {
reg = <0 0x87ef0000 0 0x8000>;
no-map;
};
vdev1vring1: vdev1vring1@87ef8000 {
reg = <0 0x87ef8000 0 0x8000>;
no-map;
};
rsc_table: rsc-table@2021f000 {
reg = <0 0x2021f000 0 0x1000>;
no-map;
};
vdevbuffer: vdevbuffer@87f00000 {
compatible = "shared-dma-pool";
reg = <0 0x87f00000 0 0x100000>;
no-map;
};
ele_reserved: ele-reserved@87de0000 {
compatible = "shared-dma-pool";
reg = <0 0x87de0000 0 0x100000>;
no-map;
};
};
};
/* Use external instead of internal RTC*/
&bbnsm_rtc {
status = "disabled";
};
&eqos {
mdio {
ethphy1: ethernet-phy@5 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <5>;
qca,disable-smarteee;
eee-broken-1000t;
reset-gpios = <&pca9534 5 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <20000>;
vddio-supply = <&vddio1>;
vddio1: vddio-regulator {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
};
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
phy-mode = "rgmii";
phy-handle = <&ethphy1>;
phy-supply = <&reg_fec_phy>;
status = "okay";
};
&flexcan1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
status = "okay";
};
&iomuxc {
pinctrl_fec: fecgrp {
fsl,pins = <
MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e
MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e
MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e
MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e
MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x5fe
MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e
MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e
MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e
MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e
MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e
MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x5fe
MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX93_PAD_PDM_CLK__CAN1_TX 0x139e
MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e
>;
};
pinctrl_lpi2c1: lpi2c1grp {
fsl,pins = <
MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e
MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e
>;
};
pinctrl_lpi2c1_gpio: lpi2c1gpiogrp {
fsl,pins = <
MX93_PAD_I2C1_SCL__GPIO1_IO00 0x31e
MX93_PAD_I2C1_SDA__GPIO1_IO01 0x31e
>;
};
pinctrl_lpi2c5: lpi2c5grp {
fsl,pins = <
MX93_PAD_GPIO_IO23__LPI2C5_SCL 0x40000b9e
MX93_PAD_GPIO_IO22__LPI2C5_SDA 0x40000b9e
>;
};
pinctrl_lpi2c5_gpio: lpi2c5gpiogrp {
fsl,pins = <
MX93_PAD_GPIO_IO23__GPIO2_IO23 0x31e
MX93_PAD_GPIO_IO22__GPIO2_IO22 0x31e
>;
};
pinctrl_pca9534: pca9534grp {
fsl,pins = <
MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x31e
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX93_PAD_UART1_RXD__LPUART1_RX 0x31e
MX93_PAD_UART1_TXD__LPUART1_TX 0x31e
>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
MX93_PAD_GPIO_IO18__GPIO2_IO18 0x31e
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe
MX93_PAD_SD2_CMD__USDHC2_CMD 0x13fe
MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe
MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe
MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe
MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe
MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e
>;
};
};
&lpi2c1 {
clock-frequency = <400000>;
pinctrl-names = "default", "sleep", "gpio";
pinctrl-0 = <&pinctrl_lpi2c1>;
pinctrl-1 = <&pinctrl_lpi2c1_gpio>;
pinctrl-2 = <&pinctrl_lpi2c1_gpio>;
scl-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
status = "okay";
/* DS1337 RTC module */
rtc@68 {
compatible = "dallas,ds1337";
reg = <0x68>;
};
};
&lpi2c5 {
clock-frequency = <400000>;
pinctrl-names = "default", "sleep", "gpio";
pinctrl-0 = <&pinctrl_lpi2c5>;
pinctrl-1 = <&pinctrl_lpi2c5_gpio>;
pinctrl-2 = <&pinctrl_lpi2c5_gpio>;
scl-gpios = <&gpio2 23 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>;
status = "okay";
pca9534: gpio@20 {
compatible = "nxp,pca9534";
reg = <0x20>;
gpio-controller;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pca9534>;
interrupt-parent = <&gpio3>;
interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
#gpio-cells = <2>;
wakeup-source;
};
};
/* Console */
&lpuart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
clocks = <&clk IMX93_CLK_LPUART1_GATE>, <&clk IMX93_CLK_LPUART1_GATE>;
clock-names = "ipg", "per";
status = "okay";
};
&usbotg1 {
dr_mode = "otg";
hnp-disable;
srp-disable;
adp-disable;
disable-over-current;
status = "okay";
};
&usbotg2 {
dr_mode = "host";
hnp-disable;
srp-disable;
adp-disable;
disable-over-current;
status = "okay";
};
/* SD */
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_usdhc2_vmmc>;
bus-width = <4>;
status = "okay";
no-sdio;
no-mmc;
};
/* Watchdog */
&wdog3 {
status = "okay";
};

View File

@@ -0,0 +1,111 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2022 NXP
* Copyright 2023 Variscite Ltd.
*/
/dts-v1/;
#include "imx93.dtsi"
/{
model = "Variscite VAR-SOM-MX93 module";
compatible = "variscite,var-som-mx93", "fsl,imx93";
mmc_pwrseq: mmc-pwrseq {
compatible = "mmc-pwrseq-simple";
post-power-on-delay-ms = <100>;
power-off-delay-us = <10000>;
reset-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>, /* WIFI_RESET */
<&gpio3 7 GPIO_ACTIVE_LOW>; /* WIFI_PWR_EN */
};
reg_eqos_phy: regulator-eqos-phy {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_eqos_phy>;
regulator-name = "eth_phy_pwr";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
startup-delay-us = <100000>;
regulator-always-on;
};
};
&eqos {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eqos>;
phy-mode = "rgmii";
phy-handle = <&ethphy0>;
phy-supply = <&reg_eqos_phy>;
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <1000000>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
eee-broken-1000t;
};
};
};
&iomuxc {
pinctrl_eqos: eqosgrp {
fsl,pins = <
MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e
MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e
MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e
MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e
MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e
MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e
MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x5fe
MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e
MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e
MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e
MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e
MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e
MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe
MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e
>;
};
pinctrl_reg_eqos_phy: regeqosgrp {
fsl,pins = <
MX93_PAD_UART2_TXD__GPIO1_IO07 0x51e
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe
MX93_PAD_SD1_CMD__USDHC1_CMD 0x13fe
MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe
MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe
MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe
MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe
MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe
MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe
MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe
MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe
MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
>;
};
};
/* eMMC */
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1>;
pinctrl-2 = <&pinctrl_usdhc1>;
bus-width = <8>;
non-removable;
status = "okay";
};

View File

@@ -149,6 +149,20 @@
};
};
usbphynop1: usbphynop1 {
compatible = "usb-nop-xceiv";
#phy-cells = <0>;
clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>;
clock-names = "main_clk";
};
usbphynop2: usbphynop2 {
compatible = "usb-nop-xceiv";
#phy-cells = <0>;
clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>;
clock-names = "main_clk";
};
soc@0 {
compatible = "simple-bus";
#address-cells = <1>;
@@ -844,5 +858,49 @@
#power-domain-cells = <1>;
status = "disabled";
};
usbotg1: usb@4c100000 {
compatible = "fsl,imx93-usb", "fsl,imx7d-usb", "fsl,imx27-usb";
reg = <0x4c100000 0x200>;
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>,
<&clk IMX93_CLK_HSIO_32K_GATE>;
clock-names = "usb_ctrl_root_clk", "usb_wakeup";
assigned-clocks = <&clk IMX93_CLK_HSIO>;
assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
assigned-clock-rates = <133000000>;
phys = <&usbphynop1>;
fsl,usbmisc = <&usbmisc1 0>;
status = "disabled";
};
usbmisc1: usbmisc@4c100200 {
compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc",
"fsl,imx6q-usbmisc";
reg = <0x4c100200 0x200>;
#index-cells = <1>;
};
usbotg2: usb@4c200000 {
compatible = "fsl,imx93-usb", "fsl,imx7d-usb", "fsl,imx27-usb";
reg = <0x4c200000 0x200>;
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>,
<&clk IMX93_CLK_HSIO_32K_GATE>;
clock-names = "usb_ctrl_root_clk", "usb_wakeup";
assigned-clocks = <&clk IMX93_CLK_HSIO>;
assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
assigned-clock-rates = <133000000>;
phys = <&usbphynop2>;
fsl,usbmisc = <&usbmisc2 0>;
status = "disabled";
};
usbmisc2: usbmisc@4c200200 {
compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc",
"fsl,imx6q-usbmisc";
reg = <0x4c200200 0x200>;
#index-cells = <1>;
};
};
};

View File

@@ -5,6 +5,10 @@
*/
/ {
binman: binman {
multiple-images;
};
chosen {
bootph-pre-ram;
};

View File

@@ -8,6 +8,10 @@
#include "imxrt1050-pinfunc.h"
/ {
binman: binman {
multiple-images;
};
aliases {
display0 = &lcdif;
usbphy0 = &usbphy1;
@@ -113,6 +117,33 @@
};
};
&binman {
#ifdef CONFIG_FSPI_CONF_HEADER
imx-boot {
filename = "flash.bin";
pad-byte = <0x00>;
fspi_conf_block {
filename = CONFIG_FSPI_CONF_FILE;
type = "blob-ext";
offset = <0x0>;
};
spl {
filename = "SPL";
offset = <0x1000>;
type = "blob-ext";
};
binman_uboot: uboot {
filename = "u-boot.img";
offset = <0x10000>;
type = "blob-ext";
};
};
#endif
};
&osc {
bootph-pre-ram;
};

View File

@@ -6,6 +6,10 @@
*/
/ {
binman: binman {
multiple-images;
};
chosen {
bootph-pre-ram;
};

View File

@@ -81,7 +81,8 @@
};
dmss: bus@48000000 {
compatible = "simple-mfd";
bootph-all;
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
dma-ranges;
@@ -90,6 +91,7 @@
ti,sci-dev-id = <25>;
secure_proxy_main: mailbox@4d000000 {
bootph-all;
compatible = "ti,am654-secure-proxy";
#mbox-cells = <1>;
reg-names = "target_data", "rt", "scfg";
@@ -165,6 +167,7 @@
};
dmsc: system-controller@44043000 {
bootph-all;
compatible = "ti,k2g-sci";
ti,host-id = <12>;
mbox-names = "rx", "tx";
@@ -174,16 +177,19 @@
reg = <0x00 0x44043000 0x00 0xfe0>;
k3_pds: power-controller {
bootph-all;
compatible = "ti,sci-pm-domain";
#power-domain-cells = <2>;
};
k3_clks: clock-controller {
bootph-all;
compatible = "ti,k2g-sci-clk";
#clock-cells = <2>;
};
k3_reset: reset-controller {
bootph-all;
compatible = "ti,sci-reset";
#reset-cells = <2>;
};
@@ -202,6 +208,7 @@
};
secure_proxy_sa3: mailbox@43600000 {
bootph-pre-ram;
compatible = "ti,am654-secure-proxy";
#mbox-cells = <1>;
reg-names = "target_data", "rt", "scfg";
@@ -217,6 +224,7 @@
};
main_pmx0: pinctrl@f4000 {
bootph-all;
compatible = "pinctrl-single";
reg = <0x00 0xf4000 0x00 0x2ac>;
#pinctrl-cells = <1>;
@@ -225,12 +233,14 @@
};
main_esm: esm@420000 {
bootph-pre-ram;
compatible = "ti,j721e-esm";
reg = <0x00 0x420000 0x00 0x1000>;
ti,esm-pins = <160>, <161>, <162>, <163>, <177>, <178>;
};
main_timer0: timer@2400000 {
bootph-all;
compatible = "ti,am654-timer";
reg = <0x00 0x2400000 0x00 0x400>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;

View File

@@ -7,6 +7,7 @@
&cbass_mcu {
mcu_pmx0: pinctrl@4084000 {
bootph-all;
compatible = "pinctrl-single";
reg = <0x00 0x04084000 0x00 0x88>;
#pinctrl-cells = <1>;
@@ -15,6 +16,7 @@
};
mcu_esm: esm@4100000 {
bootph-pre-ram;
compatible = "ti,j721e-esm";
reg = <0x00 0x4100000 0x00 0x1000>;
ti,esm-pins = <0>, <1>, <2>, <85>;

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