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348 Commits

Author SHA1 Message Date
Tom Rini
88dc278877 Prepare v2026.04
Signed-off-by: Tom Rini <trini@konsulko.com>
2026-04-06 11:59:18 -06:00
Peter Robinson
0290cec364 Add an initial CONTRIBUTE.rst
Add a contributors file to provide a high level overview
for people who wish to contribute to the project outlining
basic details and setting some project expectations.

This isn't intended to replace any of the existing documentation
but rather provide a succinct top level document that's easy
to find to enable users to understand the project and get
started as quickly as possible.

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
[trini: Correct merge window length, release day and typo in the main
        index]
Signed-off-by: Tom Rini <trini@konsulko.com>
2026-04-06 11:56:52 -06:00
Tom Rini
47e064f131 Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sh
Two trivial fixes for 2026.04 , one fix for possible NULL pointer
dereference which was not triggered thus far but got detected on Gen5
RSIP, and one basic disablement of SCIF1 in DT to which a driver was
never bound. But it would be nice to have them corrected.
2026-04-05 09:10:21 -06:00
Marek Vasut
d8bd70741f arm64: dts: renesas: Disable SCIF1 in Renesas R-Car X5H R8A78000 SoC DT
Disable incorrectly enabled SCIF1 in Renesas R-Car X5H R8A78000 SoC DT.
The SCIF1 should be enabled on board DT level in case it is needed, but
should be disabled in SoC DT by default. This had no adverse effect on
the currently upstream platforms, because those managed to probe only
the HSCIF0 device and SCIF1 was ignored.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2026-04-04 23:46:31 +02:00
Marek Vasut
e7b5aee706 net: rswitch: Avoid NULL pointer dereference during PHY access
At the very early stage when PHY ID is being auto-detected, the
PHY device is not yet instantiated and rswitch_etha .phydev is
still NULL. Add missing check for this condition and perform C22
fallback access in this PHY ID auto-detection case.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2026-04-04 23:46:31 +02:00
Prasanth Babu Mantena
214aababe0 Revert "usb: cdns3: use VBUS Valid to determine role for dr_mode OTG"
While USB DFU boot works with this patch, but the non USB boot modes like
SD Boot and flash boot fails for J784S4 EVM device.

So, Reverting this patch.

This reverts commit bfb530e06c.

Signed-off-by: Prasanth Babu Mantena <p-mantena@ti.com>
2026-04-03 17:50:16 -06:00
Michal Simek
4dc4080805 .mailmap: Fix Jerome's entry
When patman is used email address is composed together with both email
address from .mailmal file. Having two commit emails is not proper format.

Error:
error: unable to extract a valid address from: Jerome Forissier
<jerome.forissier@arm.comjerome@forissier.org>

Fixes: f2566c3a71 ("MAINTAINERS: update my email address")
Signed-off-by: Michal Simek <michal.simek@amd.com>
Acked-by: Jerome Forissier <jerome.forissier@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2026-04-02 17:41:11 -06:00
J. Neuschäfer
74f5e3ef30 powerpc/mpc83xx: Move alignment padding into __u_boot_list section
u-boot-dtb.bin is built by concatenating u-boot-nodtb.bin and u-boot.dtb.
u-boot-nodtb.bin, in turn, is generated by objcopy'ing the contents of
u-boot (U-Boot in ELF format) into a raw file.

In order to find the bundled FDT (u-boot.dtb), the code in lib/fdtdec.c
uses the _end symbol. Platform-specific linker scripts ensure that _end is
8-byte aligned, which is required by libfdt.

For the PowerPC MPC83xx platform, the ALIGN(8) directive was outside a
section, with the unfortunate effect that the potentially generated padding
bytes would not be copied by objcopy. This resulted in a discrepancy
between the _end symbol on the one hand, and the size of u-boot-nodtb.bin
and thus the starting location of the actual FDT on the other side. Under
these conditions, the FDT could not be found and boot would fail early.

This commit fixes it by moving the ALIGN(8) into the __u_boot_list section,
which is non-empty and thus copied into u-boot-nodtb.bin.

Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
Reviewed-by: Tom Rini <trini@konsulko.com>
2026-04-02 17:41:02 -06:00
Tom Rini
c704af3c8b Merge tag 'doc-2026-04-rc6' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request doc-2026-04-rc6

CI: https://source.denx.de/u-boot/custodians/u-boot-efi/-/pipelines/29687

Documentation:

* TI boards
  - fix OP-TEE args
  - fix incorrect labels for boot switches
* Fix typo in pstore documentation.
* Fix document references pointing to replaced uImage.FIT.
* buildman: Add missing :: for examples.
* overlay-fdt-boot: .dtbos do not need load addresses.
* When building the documentation use sys.path.append for pytests.
2026-03-27 09:20:45 -06:00
Rasmus Villemoes
c009771427 doc: overlay-fdt-boot: .dtbos do not need load addresses
The requirement that .dtbos have load addresses in the FIT image
vanished five years ago with

  4c531d9f58 ("fit: Load DTO into temporary buffer and ignore load address")

Fix the documentation accordingly.

Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
Reviewed-by: Marek Vasut <marek.vasut@mailbox.org>
2026-03-27 10:57:08 +01:00
Anshul Dalal
22037a6ebb doc: board: ti: fix incorrect labels for boot switches
The labels for the boot mode switches were incorreclty documented for
some TI boards, this patch fixes them as per the official user guides
linked below:

  AM62x     https://www.ti.com/lit/ug/spruj40e/spruj40e.pdf
  AM62dx    https://www.ti.com/lit/ug/sprujg2/sprujg2.pdf
  AM62ax    https://www.ti.com/lit/ug/spruj66b/spruj66b.pdf
  AM62px    https://www.ti.com/lit/ug/spruj40e/spruj40e.pdf
  AM6254atl https://www.ti.com/lit/ug/spruja1a/spruja1a.pdf

Signed-off-by: Anshul Dalal <anshuld@ti.com>
2026-03-27 10:56:01 +01:00
Anshul Dalal
155cd08561 doc: board: fix OPTEE args for TI SoCs
CFG_WITH_SOFTWARE_PRNG=y was added as an OPTEE argument to workaround
some bugs related to TRNG which have been fixed now[1]. Therefore this
patch drops the redundant argument from the documentation.

[1]: e313f4765f

Signed-off-by: Anshul Dalal <anshuld@ti.com>
Acked-by: Francesco Dolcini <francesco.dolcini@toradex.com> # Toradex Verdin AM62
2026-03-27 10:55:46 +01:00
Tom Rini
d0dfaacf57 doc: Use sys.path.append for pytests being found
Rather than having our "docs" build tagets modify PTYHONPATH, have
doc/conf.py append the required paths at runtime instead. This will
ensure that our builds from readthedocs will also find all of the
required files.

Signed-off-by: Tom Rini <trini@konsulko.com>
2026-03-27 10:53:28 +01:00
David Lechner
2632deee5f doc/buildman: fix missing :: on examples
Fix 4 instances in buildman.rst where examples were missing :: for
proper formatting. Three cases just had a single : and in one case,
: didn't make grammatical sense, so it gets a stand-alone :: along
with fixing the indent.

Signed-off-by: David Lechner <dlechner@baylibre.com>
2026-03-27 10:52:43 +01:00
Aristo Chen
4bcac9511c doc: pstore: fix typo
Use "parameters have been set" and "they need" for correct grammar
in the pstore documentation.

Signed-off-by: Aristo Chen <aristo.chen@canonical.com>
2026-03-27 10:51:47 +01:00
Daniel Golle
72cc446490 treewide: fix uImage.FIT document paths
Commit 488445cefa ("doc: Move FIT into its own directory") moved the
documentation in doc/uImage.FIT to doc/usage/fit, subsequently all
documents and example sources have been converted to reStructuredText.

Fix (almost) all of the remaining occurrences of the old path and
filenames across the tree.

The exception is doc/uImage.FIT/command_syntax_extensions.txt which
apparently has been removed entirely, or at least I was unable to
locate where that document is now.

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
2026-03-27 10:50:29 +01:00
Tom Rini
c24a72c35a Merge tag 'rpi-2026.04-rc5' of https://source.denx.de/u-boot/custodians/u-boot-raspberrypi
Updates for RPi for 2026.04-rc5:

- rpi: Update the naming for bcm2712 SoC RevD naming
- arm: bcm: Include missing errno.h
2026-03-26 09:02:05 -06:00
Peter Robinson
4e64ea8858 rpi: Update the naming for bcm2712 SoC RevD naming
The downstream Raspberry Pi uses two namings for the revD
SoC device trees, both bcm2712d0-rpi-5-b and bcm2712-d-rpi-5-b
but it seems upstream has settled on just the later, so lets
use that as it's the name that maps both upstream and downstream.

Fixes: c15a791972 ("board/raspberrypi: add bcm2712d0-rpi-5-b for Raspberry Pi 5")
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Matthias Brugger <mbrugger@suse.com>
2026-03-26 08:29:48 +00:00
Marek Vasut
b04e4b19d4 arm: bcm: Include missing errno.h
The msg.c file uses EIO macro defined in errno.h , include errno.h
to avoid build failure:

"
arch/arm/mach-bcm283x/msg.c: In function 'bcm2835_power_on_module':
arch/arm/mach-bcm283x/msg.c:73:25: error: 'EIO' undeclared (first use in this function)
   73 |                 return -EIO;
      |                         ^~~
"

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2026-03-26 08:29:18 +00:00
Tom Rini
075bd023c7 Merge tag 'qcom-fixes-24Mar2026' of https://source.denx.de/u-boot/custodians/u-boot-snapdragon
- Assorted Qualcomm platform fixes
2026-03-24 09:15:03 -06:00
Casey Connolly
1cf505e51b watchdog: qcom: stop watchdog by default
Prevent the Qualcomm watchdog from autostarting and ensure it's stopped
when the driver probed. In some cases the watchdog is left running by
a previous bootloader stage. Disable autostart so it isn't left running
when we boot into the OS, this behaviour can be changed by enabling
autostart in the board defconfig.

Reviewed-by: Stefan Roese <stefan.roese@mailbox.org>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Link: https://patch.msgid.link/20260121003659.69305-1-casey.connolly@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2026-03-24 11:51:52 +01:00
Casey Connolly
4577a672ec qcom: rpmh: don't error for SLEEP requests
Just stub out non-active votes, if we return an error the caller may
propagate it and not send its active vote. Since we don't suspend
there's no risk of us entering a broken state due to missing votes.

Link: https://patch.msgid.link/20260320-casey-qcom-rpmh-serial-fixes-v1-2-b81d05832eec@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2026-03-24 11:49:17 +01:00
Casey Connolly
7f09aff399 serial: msm-geni: allow invalid clock
Pre-relocation we may not have a clock but it's usually been enabled for
us already, or worst case we will enable it after relocation. Erroring
out in this case will almost always cause U-Boot to hang pre-relocation
which is undesirable and may be hard to debug.

Link: https://patch.msgid.link/20260320-casey-qcom-rpmh-serial-fixes-v1-1-b81d05832eec@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2026-03-24 11:49:17 +01:00
Tom Rini
bb5012fb66 power: regulator: qcom: Correct dependenecies for DM_REGULATOR_QCOM_USB_VBUS
The DM_REGULATOR_QCOM_USB_VBUS functionality can only work with DM_PMIC
enabled as well, so express this dependency in Kconfig.

Signed-off-by: Tom Rini <trini@konsulko.com>
Link: https://patch.msgid.link/20260323195302.2363577-1-trini@konsulko.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2026-03-24 11:42:19 +01:00
Balaji Selvanathan
0f265c20a5 phy: qcom: qusb2: Add QCS615 QUSB2 PHY support
Add support for QCS615 QUSB2 PHY by introducing platform-specific
initialization table and register layout. The implementation reuses
the IPQ6018 register layout and defines QCS615-specific tuning
parameters for proper USB PHY operation.

Taken from Linux commit 8adbf20e0502 ("phy: qcom-qusb2: Add support for QCS615")

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://patch.msgid.link/20260213-talos_usb-v1-3-4c4355d61437@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2026-03-24 11:35:06 +01:00
Balaji Selvanathan
c4169dfa1d clk: qcom: qcs615: Add GCC_AHB2PHY_WEST_CLK clock support
Add GCC_AHB2PHY_WEST_CLK gate clock definition to the QCS615
clock driver. This clock is required for proper PHY operation
and eliminates clock-related warnings during USB initialization.

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://patch.msgid.link/20260213-talos_usb-v1-2-4c4355d61437@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2026-03-24 11:34:58 +01:00
Balaji Selvanathan
c4f40d0925 clk: qcom: qcs615: Add GCC_USB3_PRIM_CLKREF_CLK support
Add support for GCC_USB3_PRIM_CLKREF_CLK to the QCS615 clock driver.
This clock is referenced in the device tree USB node but was not
implemented in U-Boot, causing "Clock 152 not found" warnings during
fastboot run.

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Link: https://patch.msgid.link/20260213-talos_usb-v1-1-4c4355d61437@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2026-03-24 11:34:58 +01:00
Tom Rini
eb95914b9f Prepare v2026.04-rc5
Signed-off-by: Tom Rini <trini@konsulko.com>
2026-03-23 14:19:17 -06:00
Tom Rini
e21ac93091 Merge tag 'fsl-qoriq-for-2026.04-rc5' of https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq
CI: https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq/-/pipelines/29615

- Fix SPI flash clock for ls102xa
2026-03-23 08:03:17 -06:00
Tom Rini
f09e500f6d serial: Enable SYS_NS16550 on incorrectly migrated platforms
With the migration to DM_SERIAL in commit 191b10ac70 ("PowerPC /
Layerscape: Finish migration to DM_SERIAL") a number of platforms were
incorrectly migrated and did not enable SYS_NS16550 despite previously
having enabled the non-DM NS16650 serial driver. Enable these now.

Fixes: 191b10ac70 ("PowerPC / Layerscape: Finish migration to DM_SERIAL")
Reported-by: Michael Walle <mwalle@kernel.org>
Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2026-03-23 08:02:08 -06:00
Michael Walle
1f305f99d2 armv7: ls102xa: fix SPI flash clock
Commit bb6f3c0f76 ("armv7: ls102xa: Update SCFG_QSPI_CLKSEL value")
broke the SPI boot on the LS1021ATSN board (ls1021atsn_qspi_defconfig)
at least.

The commit message reads
   Update SCFG_QSPI_CLKSEL value : 0xC -> 0x5
   which means ClusterPLL/16

The original submitted patch had the following description:
   Value 0xC is reserved. Replace it with correct value 0x5 which
   is ClusterPLL/16

Unfortunatly, the little information which was there, was stripped even
further. Why is 0x5 the "correct" value? In fact, it seems that the
upper bit is just ignored and thus the value 0xC translates to 0x4 which
is ClusterPLL/20. This, will result in a SPI clock of 60MHz (if the PLL
is clocked at 1.2GHz). But even that is too much for the (default) 03h
read opcode (max 50MHz). Set the value to ClusterPLL/24 which is 50MHz.

Link: https://lore.kernel.org/r/1568804284-25162-1-git-send-email-kuldeep.singh@nxp.com/
Fixes: bb6f3c0f76 ("armv7: ls102xa: Update SCFG_QSPI_CLKSEL value")
Signed-off-by: Michael Walle <mwalle@kernel.org>
Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-03-23 14:27:24 +08:00
Michael Walle
a5e46ecc35 configs: ls1021atsn: enable serial driver
Switching to DM_SERIAL disabled any serial driver. Re-enable it again.

Fixes: 191b10ac70 ("PowerPC / Layerscape: Finish migration to DM_SERIAL")
Signed-off-by: Michael Walle <mwalle@kernel.org>
Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-03-23 14:27:23 +08:00
Michael Walle
6dad9838d3 arm: dts: ls1021a-tsn: add default serial output
Since switching to DM_SERIAL 'stdout-path' seems to be necessary.

Signed-off-by: Michael Walle <mwalle@kernel.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-03-23 14:27:23 +08:00
Tom Rini
a22e9e1b8e tests: FIT: Add "clone" image attack image test
Related to the problem resolved with commit 2092322b31 ("boot: Add
fit_config_get_hash_list() to build signed node list"), add a testcase
for the problem as well.

Reported-by: Apple Security Engineering and Architecture (SEAR)
Signed-off-by: Tom Rini <trini@konsulko.com>
2026-03-22 19:47:05 -06:00
Tom Rini
33756fd4a8 Merge tag 'mediatek-for-master-2026-03-17' of https://source.denx.de/u-boot/custodians/u-boot-mediatek
* A fix for mt7622 infracfg and pericfg clocks that were unusable.
2026-03-18 11:07:18 -06:00
Tom Rini
e6e3383f5b Merge patch series "update MAINTAINERS for PWM LED"
Quentin Schulz <foss+uboot@0leil.net> says:

The entry is named LED while it only matches PWM LED binding and driver,
so rename it to PWM LED.

Ivan's email is bouncing, so mark the PWM LED entry as orphaned.

Link: https://lore.kernel.org/r/20260303-pwm-led-orphan-v1-0-54d14a430cb7@cherry.de
2026-03-18 11:06:15 -06:00
Quentin Schulz
b28b77caac MAINTAINERS: make PWM LED orphan
Ivan's mail is bouncing, so update the entry status.

Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
2026-03-18 11:06:10 -06:00
Quentin Schulz
a5533e7417 MAINTAINERS: rename LED into PWM LED
It clearly only lists PWM LED driver and bindings so we should have the
entry reflect that.

Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
2026-03-18 11:06:10 -06:00
Kunihiko Hayashi
eeca6ed86f image-fit: Fix mismatched parameter type in comment
The functions use 'ulong', however, the comments said 'uint32_t'.
Update the comments to match the prototype.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
2026-03-18 11:05:57 -06:00
Daniel Golle
52d84fccfd clk: mediatek: mt7622: fix infracfg and pericfg clock operations
The MT7622 infracfg and pericfg drivers both use
mtk_common_clk_infrasys_init() for probe, which populates struct
mtk_clk_priv and stores gate definitions in the clk_tree. However,
both drivers were incorrectly wired to mtk_clk_gate_ops which expects
struct mtk_cg_priv with separately populated gates/num_gates/gates_offs
fields from mtk_common_clk_gate_init().

Since those fields were never set, any attempt to enable an infracfg or
pericfg gate clock (e.g. CLK_INFRA_TRNG) would fail with -EINVAL.

Switch both to mtk_clk_infrasys_ops and struct mtk_clk_priv to match
the init function.

Fixes: 72ab603b20 ("clk: mediatek: add driver for MT7622")
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Reviewed-by: David Lechner <dlechner@baylibre.com>
Signed-off-by: David Lechner <dlechner@baylibre.com>
2026-03-17 13:51:45 -05:00
Tom Rini
eefb822fb5 Merge tag 'rpi-2026.04-rc4' of https://source.denx.de/u-boot/custodians/u-boot-raspberrypi
Updates for RPi for 2026.04-rc4:

- board/raspberrypi: add bcm2712d0-rpi-5-b for Raspberry Pi 5
- board/raspberrypi: add multi-FDT support
- rpi: pass the Video Core logs DT parameter through
- pinctrl: bcm283x: Fix GPIO pull state register values for BCM2711
2026-03-12 16:10:46 -06:00
Filip Kokosiński
c15a791972 board/raspberrypi: add bcm2712d0-rpi-5-b for Raspberry Pi 5
This commit adds an FDT entry for the d0 stepping of the BCM2712 SoC.
This entry is used by the v1.1 revision of the board
(revision & 0x0f == 1).

Signed-off-by: Filip Kokosiński <filip.kokosinski@gmail.com>
Reviewed-by: Peter Robinson <pbrobinson@gmail.com>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
2026-03-12 12:11:24 +00:00
Filip Kokosiński
e263f901c1 board/raspberrypi: add multi-FDT support
This patch adds support for multiple FDT files per board model. This is
done by adding the FDTFILES macro, which initializes two rpi_model
struct members: fdtfiles and fdtcount.

The new-style revision codes designate LSB bits as board revision; this
value is used to choose between provided FDTs. The first element of the
fdtfiles list is used should no revision match.

Signed-off-by: Filip Kokosiński <filip.kokosinski@gmail.com>
Reviewed-by: Peter Robinson <pbrobinson@gmail.com>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
2026-03-12 12:11:24 +00:00
Peter Robinson
7d5d8400fa rpi: pass the Video Core logs DT parameter through
Pass the VC logs DT parameter through to the kernel
device tree. This is used by the vclog tool and is
a useful debugging tool.

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Acked-by: Matthias Brugger <mbrugger@suse.com>
2026-03-12 12:02:59 +00:00
Cibil Pankiras
5fa0237c83 pinctrl: bcm283x: Fix GPIO pull state register values for BCM2711
BCM2711 has different pull-up/down register values compared to BCM2835

- BCM2835: NONE=0, DOWN=1, UP=2
- BCM2711: NONE=0, UP=1, DOWN=2

This patch fixes the pull state register values for BCM2711.

Fixes: 2c39d975f8 ("pinctrl: bcm283x: Add GPIO pull-up/down control for BCM2835 and BCM2711")
Signed-off-by: Cibil Pankiras <cibil.pankiras@egym.com>
Reviewed-by: Matthias Brugger <mbrugger@suse.com>
Reviewed-by: Peter Robinson <pbrobinson@gmail.com>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
2026-03-12 12:02:21 +00:00
Ilias Apalodimas
4cbb1c4d99 kbuild: fix cross_tools compilation
Frieder reports that after the kbuild sync running
make tools-only_defconfig
make cross_tools
fails with

UPD     include/generated/timestamp_autogenerated.h
PYMOD   rebuild
tools/Makefile:359: *** insufficient number of arguments (1) to function
'filter'.  Stop.
make: *** [Makefile:2191: tools] Error 2

After the sync 'hostprogs-always-y' contains the complete list of
the tools we need to strip, so the $(filter) command is not needed.

Fixes: bd3f9ee679 ("kbuild: Bump the build system to 6.1")
Reported-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2026-03-10 15:06:55 -06:00
Tom Rini
ba7bf918da Prepare v2026.04-rc4
Signed-off-by: Tom Rini <trini@konsulko.com>
2026-03-09 13:52:04 -06:00
Simon Glass
2092322b31 boot: Add fit_config_get_hash_list() to build signed node list
The hashed-nodes property in a FIT signature node lists which FDT paths
are included in the signature hash. It is intended as a hint so should
not be used for verification.

Add a function to build the node list from scratch by iterating the
configuration's image references. Skip properties known not to be image
references. For each image, collect the path plus all hash and cipher
subnodes.

Use the new function in fit_config_check_sig() instead of reading
'hashed-nodes'.

Update the test_vboot kernel@ test case: fit_check_sign now catches the
attack at signature-verification time (the @-suffixed node is hashed
instead of the real one, causing a mismatch) rather than at
fit_check_format() time.

Update the docs to cover this. The FIT spec can be updated separately.

Signed-off-by: Simon Glass <simon.glass@canonical.com>
Closes: https://lore.kernel.org/u-boot/20260302220937.3682128-1-trini@konsulko.com/
Reported-by: Apple Security Engineering and Architecture (SEAR)
Tested-by: Tom Rini <trini@konsulko.com>
2026-03-09 09:49:50 -06:00
Tom Rini
532a4804e9 Merge patch series "64-bit PCIe for AM64, AM69, J7200, J722S and J784S4"
Siddharth Vadapalli <s-vadapalli@ti.com> says:

Since Linux device-tree has switched to 64-bit Address space for the
PCIe Controllers on TI SoCs, currently, U-Boot needs to support the
same. This series adds support for 64-bit addressing for PCIe along with
enabling Root-Complex mode of operation for AM69 and J784S4 SoCs.

Series has been tested on all platforms being affected by this series.
Test Logs:
1. AM642-EVM
https://gist.github.com/Siddharth-Vadapalli-at-TI/82512389f8396a51e4f167c7ebe4c2a3
2. AM69-SK
https://gist.github.com/Siddharth-Vadapalli-at-TI/b20b2811804ffc6e6c063564330c0a35
3. J7200-EVM
https://gist.github.com/Siddharth-Vadapalli-at-TI/c545da68bd28a5e036803bb60f32d8e9
4. J722S-EVM
https://gist.github.com/Siddharth-Vadapalli-at-TI/3dde05c4c7076076aa20ac47a6e2d176
5. J784S4-EVM
https://gist.github.com/Siddharth-Vadapalli-at-TI/a93c1b2cd5d90f494e885d1831d3d23e

Link: https://lore.kernel.org/r/20260227115841.333073-1-s-vadapalli@ti.com
2026-03-09 09:35:51 -06:00
Siddharth Vadapalli
f0bb3940b1 configs: j722s_evm_a53_defconfig: enable 64-bit addressing for PCIe
The PCIe0 instance of PCIe on the J722S SoC uses the 4 GB Address Window
starting from 0x6_0000_0000 to map System Addresses to PCIe Bus Addresses.
Hence, enable CONFIG_SYS_PCI_64BIT.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Fixes: 79f3e77133 ("Subtree merge tag 'v6.16-dts' of dts repo [1] into dts/upstream")
2026-03-09 09:35:50 -06:00
Siddharth Vadapalli
b04d709459 configs: j7200_evm_a72_defconfig: enable 64-bit addressing for PCIe
The PCIe1 instance of PCIe on the J7200 SoC uses the 4 GB Address Window
starting from 0x41_0000_0000 to map System Addresses to PCIe Bus Addresses.
Hence, enable CONFIG_SYS_PCI_64BIT.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Fixes: 79f3e77133 ("Subtree merge tag 'v6.16-dts' of dts repo [1] into dts/upstream")
2026-03-09 09:35:49 -06:00
Siddharth Vadapalli
430874ce20 configs: am64x_evm_a53_defconfig: enable 64-bit addressing for PCIe
The PCIe0 instance of PCIe on the AM64x SoC uses the 4 GB Address Window
starting from 0x6_0000_0000 to map System Addresses to PCIe Bus Addresses.
Hence, enable CONFIG_SYS_PCI_64BIT.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Fixes: 79f3e77133 ("Subtree merge tag 'v6.16-dts' of dts repo [1] into dts/upstream")
2026-03-09 09:35:47 -06:00
Siddharth Vadapalli
724952ac41 configs: {am69_sk, j784s4_evm}_a72_defconfig: enable PCIe Root-Complex mode
The PCIe Controllers on the J784S4 and AM69 SoCs support Root-Complex
mode of operation. PCIe0 instance of PCIe on both of the SoCs is brought
out on the Starter-Kit (AM69) and EVM (J784S4) boards. Hence, enable
the configs required for Root-Complex mode of operation.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Fixes: 79f3e77133 ("Subtree merge tag 'v6.16-dts' of dts repo [1] into dts/upstream")
2026-03-09 09:35:46 -06:00
Siddharth Vadapalli
068d05ad5f pci: pcie_cdns_ti: enable PCIe root-complex mode for J784S4 SoC
The PCIe Controllers on the J784S4 SoC support Root-Complex mode of
operation. Hence, enable it.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Fixes: 79f3e77133 ("Subtree merge tag 'v6.16-dts' of dts repo [1] into dts/upstream")
2026-03-09 09:35:43 -06:00
Siddharth Vadapalli
d62f1c98c5 arm: mach-k3: arm64-mmu: add mapping for PCIe 4 GB Address Windows
The PCIe Controllers in the K3 SoCs have 4 GB Address Windows in the
64-bit address space to map System (CPU) Addresses to PCIe Bus Addresses.
The physical addresses for these Address Windows across PCIe instances
across SoCs is as follows:

+--------+----------------+----------------+----------------+----------------+
| SoC    | PCIe0          | PCIe1          | PCIe2          | PCIe3          |
+--------+----------------+----------------+----------------+----------------+
| AM64   | 0x6_0000_0000  | NA             | NA             | NA             |
| J722S  | 0x6_0000_0000  | NA             | NA             | NA             |
| AM68   | NA             | 0x41_0000_0000 | NA             | NA             |
| J7200  | NA             | 0x41_0000_0000 | NA             | NA             |
| J721S2 | NA             | 0x41_0000_0000 | NA             | NA             |
| J742S2 | 0x40_0000_0000 | 0x41_0000_0000 | NA             | NA             |
| AM69   | 0x40_0000_0000 | 0x41_0000_0000 | 0x42_0000_0000 | 0x43_0000_0000 |
| J721E  | 0x40_0000_0000 | 0x41_0000_0000 | 0x42_0000_0000 | 0x43_0000_0000 |
| J784S4 | 0x40_0000_0000 | 0x41_0000_0000 | 0x42_0000_0000 | 0x43_0000_0000 |
+--------+----------------+----------------+----------------+----------------+

Two regions for a 1:1 mapping from virtual addresses to physical addresses
catering to all of the above will be required, which are:
1. For AM64 and J722S SoCs
=> Start: 0x6_0000_0000 Size: 0x1_0000_0000
2. For AM68, AM69, J7200, J721E, J721S2, J742S2 and J784S4 SoCs
=> Start: 0x40_0000_0000 Size: 0x4_0000_0000

Since the 'Flash Peripherals' region from 0x5_0000_0000 to 0x8_7FFF_FFFF
includes the mapping for AM64 and J722S SoCs, only the second region
mentioned above needs to be added.

Hence, add the region to support 64-bit address space for PCIe.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Fixes: 79f3e77133 ("Subtree merge tag 'v6.16-dts' of dts repo [1] into dts/upstream")
2026-03-09 09:35:18 -06:00
Takahiro Kuwano
8ee2e262d1 MAINTAINERS: update SPI NOR reviewer
Tudor Ambarus will step down as SPI NOR reviewer.
I would like to take this role.

Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Acked-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2026-03-09 08:51:36 -06:00
Raphael Gallais-Pou
0b429f7c6b video: stm32: dsi: add .of_to_plat callback
Drivers should extract device-tree data before probing via the
.of_to_plat hook.

Implement it for stm32_dsi driver.  By doing so, it also solve a
variable shadowing in stm32_dsi_probe() where &clk was used as
peripheral clock and ref clock.

For readability some struct have been renamed such as:

  * struct stm32_dsi_priv *dsi -> struct stm32_dsi_priv *priv
  * struct clk clk -> struct clk pclk

Signed-off-by: Raphael Gallais-Pou <rgallaispou@gmail.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2026-03-09 08:51:05 -06:00
Tom Rini
b26cc03b7c Merge patch series "MAINTAINERS: Update ADI ADSP platform maintainers"
Philip Molloy <philip@philipmolloy.com> says:

This series updates the maintainers for the ADI ADSP platform. It
follows Greg's series adding support for ADI ADSP SoCs.

Timesys spent years developing and maintaining Linux support for ADI
ADSP SoCs. The maintenance contract has ended and ADI has brought that
effort in-house. Additionally, Timesys was acquired by another company.

Thanks to everyone at Timesys for all of their hard work over the years!

Link: https://lore.kernel.org/r/20260226111136.354009-1-philip@philipmolloy.com
2026-03-04 14:25:30 -06:00
Philip Molloy
15e2bacc30 treewide: Remove Timesys from ADI ADSP maintenance
After years of developing the ADI ADSP platform, Timesys was purchased
by another company and is no longer contracted to maintain the platform.

Signed-off-by: Philip Molloy <philip.molloy@analog.com>
Reviewed-by: Greg Malysa <malysagreg@gmail.com>
2026-03-04 14:25:27 -06:00
Philip Molloy
bdc5f6531a MAINTAINERS: Update ARM SC5xx
After years of developing the ADI ADSP platform, Timesys was purchased
by another company and is no longer contracted to maintain the platform.

Utsav is leaving ADI after contributing to ADSP SoCs for the last 3
years. He is a founding member of the in-house team supporting the
chips.

Linux support at ADI has been consolidated. Use the company-wide mailing
list and git repository.

Signed-off-by: Philip Molloy <philip.molloy@analog.com>
Reviewed-by: Greg Malysa <malysagreg@gmail.com>
2026-03-04 14:25:27 -06:00
Daniel Golle
35d9b9c70e tools/atmelimage: add const qualifier to fix compiler warning
More strict checks in GCC 15 expose a new warning:
tools/atmelimage.c: In function ‘atmel_find_pmecc_parameter_in_token’:
tools/atmelimage.c:64:31: error: assignment discards ‘const’ qualifier from pointer target type [-Werror=discarded-qualifiers]
64 |                         param = strstr(token, "=");
   |                               ^
cc1: all warnings being treated as errors

Add 'const' qualifier to variable 'param' to prevent build failing
due to -Werror.

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
2026-03-04 14:25:18 -06:00
Tom Rini
024a0e9125 Merge tag 'u-boot-ufs-20260304' of https://source.denx.de/u-boot/custodians/u-boot-ufs
A few fixes/missing changes for UFS:
- remove unused ufs_post_bind() declaration
- Disable UTP command timeout in slow mode
- Missing MediaTek UFS PHY Driver to be used with the UFS driver
2026-03-04 14:24:59 -06:00
Tom Rini
3e91c6a36a Revert "kbuild: unexport sub_make_done to fix child make invocations"
This unfortunately introduces failure to build in other cases:
$ make ARCH=riscv CROSS_COMPILE=riscv64-unknown-linux-gnu- O=build \
	microchip_mpfs_generic_defconfig
  GEN     Makefile
#
# configuration written to .config
#
$ make ARCH=riscv CROSS_COMPILE=riscv64-unknown-linux-gnu- O=build
  HOSTCC  scripts/basic/fixdep
  GEN     Makefile
  HOSTCC  scripts/kconfig/conf.o
  YACC    scripts/kconfig/zconf.tab.[ch]
  LEX     scripts/kconfig/zconf.lex.c
  HOSTCC  scripts/kconfig/zconf.tab.o
  HOSTLD  scripts/kconfig/conf
scripts/kconfig/conf  --syncconfig Kconfig
***
*** Configuration file ".config" not found!
***
*** Please run some configurator (e.g. "make oldconfig" or
*** "make menuconfig" or "make xconfig").
***
make[4]: *** [/stuff/u-boot/scripts/kconfig/Makefile:75: syncconfig] Error 1
make[3]: *** [/stuff/u-boot/Makefile:702: syncconfig] Error 2
make[2]: *** [../Makefile:189: __sub-make] Error 2
make[1]: *** No rule to make target 'include/config/auto.conf', needed by 'include/config/uboot.release'.  Stop.
make: *** [Makefile:189: __sub-make] Error 2

This reverts commit 4284306d22.

Reported-by: Conor Dooley <conor@kernel.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2026-03-04 11:34:36 -06:00
Marek Vasut
f473a453b0 kbuild: Drop phandle from diff between base DT and U-Boot augmented DT if DEVICE_TREE_DEBUG=1
Remove the "phandle = <0x..>;" properties from the DT diff between
unpatched base DT and U-Boot augmented DT if DEVICE_TREE_DEBUG=1.
The phandle numbers are only generated by DTC, but not referenced
anywhere in the DT, because the original references are specifically
not replaced by phandle numbers when recent DTC is invoked with the
-I dts -O dts flags . The phandle number are therefore only a noise
in the diff, filter them out.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Tested-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
2026-03-03 10:34:57 -06:00
Simon Glass
4284306d22 kbuild: unexport sub_make_done to fix child make invocations
The exported sub_make_done variable leaks into the environment of all
child processes. When make targets like tcheck spawn independent make
invocations with O=, those child makes inherit sub_make_done=1, skip
the KBUILD_OUTPUT setup and try to build in the source tree.

There is a workaround that resets sub_make_done to 0 for specific test
targets, but this isn't great since it has tolist every target that
spawns independent make invocations.

Instead, unexport sub_make_done once we are in the final make
invocation. The direct sub-make already has the value in its
environment from the export, and no further propagation is needed.
This also allows the per-target workaround to be removed.

Fixes: 27529f1cb0 ("kbuild: skip parsing pre sub-make code for recursion")
Signed-off-by: Simon Glass <simon.glass@canonical.com>
2026-03-03 10:34:54 -06:00
Simon Glass
8353239dab menu: Move shortcut-key handling to bootmenu_loop()
The bootmenu_conv_key() function is shared with expo subsystem for key
input. Adding alphanumeric-to-BKEY_SHORTCUT conversion there causes expo
to swallow typed characters instead of inserting them as text, since
BKEY_SHORTCUT falls in the range that expo treats as a command key
rather than passing through.

Move the shortcut-key detection into bootmenu_loop() where it is
only used in the bootmenu context.

Fixes: 8c986521c3 ("cmd: bootmenu: permit to select bootmenu entry with a shortcut")
Signed-off-by: Simon Glass <simon.glass@canonical.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2026-03-03 10:34:52 -06:00
Hugo Villeneuve
e15b78bcf7 drivers: cpu: fix syntax error in Kconfig documentation
Replace then -> they so that the sentence makes sense.

Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
2026-03-03 10:34:49 -06:00
Romain Gantois
39e1ccc777 dm: core: Don't allow ofnode_to_fdt() to return NULL
The ofnode_to_fdt() function may return a NULL pointer in multiple cases.
Or, this function's return value is often passed directly to functions such
as fdt_getprop() which end up dereferencing it, thus causing a NULL pointer
exception.

Don't allow ofnode_to_fdt() to return NULL, to avoid a NULL pointer
dereference.

Reviewed-by: Raphaël Gallais-Pou <raphael.gallais-pou@foss.st.com>
Signed-off-by: Romain Gantois <romain.gantois@bootlin.com>
Reviewed-by: Simon Glass <simon.glass@canonical.com>
2026-03-03 10:34:45 -06:00
Stefan Eichenberger
8d24789abe common/memsize.c: Fix get_ram_size() original data restore
The get_ram_size() function fails to restore the original RAM data when
the data cache is enabled. This issue was observed on an AM625 R5 SPL
with 512MB of RAM and is a regression that became visible with
commit bc07851897 ("board: ti: Pull redundant DDR functions to a common
location and Fixup DDR size when ECC is enabled").

Observed boot failure messages:
  Warning: Did not detect image signing certificate. Skipping authentication to prevent boot failure. This will fail on Security Enforcing(HS-SE) devices
  Authentication passed
  Starting ATF on ARM64 core...

The system then hangs. This indicates that without a data cache flush,
data in the cache is not coherent with RAM, preventing the system from
booting. This was verified by printing the content of this address when
the issue occurs.

Add a data cache flush after each restore operation to resolve this
issue.

Fixes: bc07851897 ("board: ti: Pull redundant DDR functions to a common location and Fixup DDR size when ECC is enabled")
Fixes: 1c64b98c1e ("common/memsize.c: Fix get_ram_size() when cache is enabled")
Signed-off-by: Stefan Eichenberger <stefan.eichenberger@toradex.com>
Reviewed-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
Tested-by: Francesco Dolcini <francesco.dolcini@toradex.com> # Toradex Verdin AM62
2026-03-02 08:21:47 -06:00
Julien Stephan
47905f2846 drivers: ufs: remove unused ufs_post_bind() declaration
Commit 067c1b0332 ("ufs: Call ufs_scsi_bind() from uclass .post_bind")
inlined ufs_scsi_bind() into ufs_post_bind() as trivial
device_bind_driver() call.

ufs_scsi_bind() is no longer referenced anywhere in the codebase, so
drop its declaration from include/ufs.h.

Drivers used to include <ufs.h> to include prototype of ufs_scsi_bind()
function, so we can now safely remove such includes.

Fixes: 067c1b0332 ("ufs: Call ufs_scsi_bind() from uclass .post_bind")
Signed-off-by: Julien Stephan <jstephan@baylibre.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://patch.msgid.link/20260203-cleanup-ufs-header-v1-1-4c10424485f0@baylibre.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2026-03-02 15:20:02 +01:00
Igor Belwon
25f1425431 phy: Add MediaTek UFS PHY Driver
This UFS M-PHY driver can be used on recent MediaTek SoCs as the
primary PHY for the UFS controller.

Signed-off-by: Igor Belwon <igor.belwon@mentallysanemainliners.org>
Link: https://patch.msgid.link/20251011-mtk-ufs-uboot-v1-1-a05f991ee150@mentallysanemainliners.org
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2026-03-02 15:19:17 +01:00
Padmarao Begari
080b4f0995 ufs: Disable UTP command timeout in slow mode
When the UFS controller is operating in slow (PWM) mode,
the driver is disabled the timeout for UTP send commands.
In high-speed mode, the timeout remains enabled to
detect stalled or failed transfers. This change ensures reliable
operation in slow mode, where command completion may take longer
and timeouts are not required.

Signed-off-by: Padmarao Begari <padmarao.begari@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://patch.msgid.link/e6deb9086afab9d2bdd53db8ecbc7db93af5204d.1764169598.git.michal.simek@amd.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2026-03-02 15:19:17 +01:00
Tom Rini
e6e7b2427a Merge tag 'efi-2026-04-rc4' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request efi-2026-04-rc4

CI: https://source.denx.de/u-boot/custodians/u-boot-efi/-/pipelines/29389

UEFI:

* Correct LoadImage() return code for invalid parameters
  and provide a test for it.
* Correct misspells in the test code.
2026-02-27 08:12:22 -06:00
Vincent Stehlé
89f6b9020d efi_selftest: cosmetic: fix spelling in comments
Fix a few UEFI function names, as well as a typo.

Signed-off-by: Vincent Stehlé <vincent.stehle@arm.com>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Cc: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2026-02-27 12:14:56 +01:00
Vincent Stehlé
02b74a7863 efi_selftest: test specific LoadImage() case
Add a test calling the LoadImage() UEFI function with both its SourceBuffer
and DevicePath input arguments equal to NULL.

This test can be run on the sandbox with the following command:

  ./u-boot -T -c "setenv efi_selftest load image from file; \
                  bootefi selftest"

Signed-off-by: Vincent Stehlé <vincent.stehle@arm.com>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Cc: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Cc: Tom Rini <trini@konsulko.com>
2026-02-27 12:14:56 +01:00
Vincent Stehlé
3768968b1e efi_loader: fix specific LoadImage() return code
When the LoadImage() UEFI function is called with both its SourceBuffer and
DevicePath input arguments equal to NULL, it must return EFI_NOT_FOUND [1].
However, it does return EFI_INVALID_PARAMETER instead; fix it.

Link: https://uefi.org/specs/UEFI/2.11/07_Services_Boot_Services.html#efi-boot-services-loadimage [1]
Reported-by: Sathisha Shivaramappa <sathisha.shivaramappa@arm.com>
Signed-off-by: Vincent Stehlé <vincent.stehle@arm.com>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Cc: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Cc: Tom Rini <trini@konsulko.com>
2026-02-27 12:14:56 +01:00
Tom Rini
437ea9f8be Gitlab: Fix TEST_PY_TEST_SPEC for qemu-x86_64 in sjg-lab
With the change to regularize the usage of TEST_PY_TEST_SPEC in the
sjg-lab stanza with commit c7f360f20d ("Gitlab: Rework sjg-lab calling
test.py to be closer to test.py stage") the leading "and " part of the
usage under qemu-x86_64 wasn't removed when it should have been. Do so
now.

Fixes: c7f360f20d ("Gitlab: Rework sjg-lab calling test.py to be closer to test.py stage")
Reviewed-by: Simon Glass <simon.glass@canonical.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2026-02-26 09:06:33 -06:00
Tom Rini
e2dfabcab0 Merge tag 'fsl-qoriq-next-2026-02-25' of https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq
For SCMI, Power Domain and IOMMU, validate device tree node before
continuing, to avoid boot failure.
2026-02-26 09:04:47 -06:00
Peng Fan
efc9be77d8 iommu: Validate device tree node in dev_iommu_enable
Similar to pinctrl_select_state(), add dev_has_ofnode() check before doing the
real work. Device(scmi_base.0) does not have a real device node, ofnode_null()
is assigned as the device tree node for scmi base protocol device:
'commit 7eb4eb541c ("firmware: scmi: install base protocol to SCMI agent")'

However with recent update in
'commit 0535e46d55 ("scripts/dtc: Update to upstream version v1.7.2-35-g52f07dcca47c")',
SPL panic in fdt_check_node_offset_()->fdt_next_tag(), because offset is -1
and SPL_OF_LIBFDT_ASSUME_MASK is 0xFF.

So need to validate device tree node.

Reported-by: Ye Li <ye.li@nxp.com>
Closes: https://lore.kernel.org/u-boot/939a9696-27fa-45a1-b428-feffe21ac6d5@oss.nxp.com/
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-02-26 09:04:46 -06:00
Peng Fan
6ee82240de power: domain: Validate device tree node in dev_power_domain_ctrl
Similar to pinctrl_select_state(), add dev_has_ofnode() check before doing the
real work. Device(scmi_base.0) does not have a real device node, ofnode_null()
is assigned as the device tree node for scmi base protocol device:
'commit 7eb4eb541c ("firmware: scmi: install base protocol to SCMI agent")'

However with recent update in
'commit 0535e46d55 ("scripts/dtc: Update to upstream version v1.7.2-35-g52f07dcca47c")',
SPL panic in fdt_check_node_offset_()->fdt_next_tag(), because offset is -1
and SPL_OF_LIBFDT_ASSUME_MASK is 0xFF.

So need to validate device tree node.

Reported-by: Ye Li <ye.li@nxp.com>
Closes: https://lore.kernel.org/u-boot/939a9696-27fa-45a1-b428-feffe21ac6d5@oss.nxp.com/
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-02-26 09:04:46 -06:00
Peng Fan
3ee1408eeb firmware: scmi: Validate device tree node before setup channel
SCMI base protocol device does not have a device tree, it should use and
need to use the agent base channel.

For scmi_base.[x], there is no real device tree node for it. ofnode_null() is
assigned as the device tree node for scmi base protocol device:
commit 7eb4eb541c ("firmware: scmi: install base protocol to SCMI agent")

However with recent update in commit 0535e46d55
("scripts/dtc: Update to upstream version v1.7.2-35-g52f07dcca47c"),
SPL panic in fdt_check_node_offset_()->fdt_next_tag(), because offset is -1
and SPL_OF_LIBFDT_ASSUME_MASK is 0xFF.

So add a check in x_get_channel() to validate the protocol devices'
ofnode.

Reported-by: Ye Li <ye.li@nxp.com>
Closes: https://lore.kernel.org/u-boot/939a9696-27fa-45a1-b428-feffe21ac6d5@oss.nxp.com/
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-02-26 09:04:46 -06:00
Tom Rini
7995bf8dea Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-samsung
- Assorted platform and video driver updates
2026-02-25 08:49:28 -06:00
Tom Rini
78ea226ddb Merge tag 'u-boot-stm32-20260224' of https://source.denx.de/u-boot/custodians/u-boot-stm
STM32 update:
_ Add STM32MP21 support (board, machine, cmd_stm32key, cmd_stboard, rifsc)
_ pinctrl: stm32 : various update
_ stm32prog: clean stm32prog_data struct
_ stm32mp2: Fix array bound check in setup_boot_mode()
_ stm32mp2: Update dynamically DDR size in MMU table
_ rifsc: various fixes
2026-02-25 08:48:54 -06:00
Kaustabh Chakraborty
336dd39b95 configs: exynos-mobile: add DEFAULT_DEVICE_TREE option
Add a default fallback device tree in order to allow a successful build
without mentioning the DEVICE_TREE= make flag.

Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2026-02-25 10:47:03 +09:00
Kaustabh Chakraborty
0e61fc5364 board: samsung: exynos-mobile: add EFI capsule update support
Add support for EFI capsule updates via U-Boot's DFU. This flashes the
boot partition with the new image provided in the capsule.

Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2026-02-25 10:47:03 +09:00
Kaustabh Chakraborty
db0fe21bd3 board: samsung: exynos-mobile: use blkmap for booting from userdata subpartitions
Some distributions tend to provide a single combined image with EFS and
the system root filesystem. Flashing it as-is in a single partition
(usually done in userdata partition as it is the largest) is not
bootable as U-Boot does not understand subpartitions.

Use blkmap to map the userdata partition into its own block device.

Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2026-02-25 10:47:03 +09:00
Kaustabh Chakraborty
e4001865ff phy: samsung: add support for exynos7870 USB PHY
The USB PHY used by the Exynos7870 SoC has a single USB 2.0 interface.
Add its dedicated variant enum, compatible, and init/exit functions.

The PHY enable bit of Exynos7870's PHY is different in contrast to that
of Exynos850 and most Exynos PHYs. To allow this change, a simple if
condition is added in exynos_usbdrd_phy_isol() which changes the
bitmask. Since the variant enum is required, the function argument is
changed to accept the driver data itself.

Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2026-02-25 10:46:05 +09:00
Kaustabh Chakraborty
ae1e081f83 phy: samsung: add enum for variants based on SoCs
The variant enum is used to uniquely identify which SoC the PHY block
belongs to. It is initially set in the match table, along with the
compatible string, it gets copied to driver data struct during probe.

SoC specific functions must only be called if the respective variant
enum is set. Add switch-case blocks wherever required.

Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2026-02-25 10:46:05 +09:00
Gatien Chevallier
c61d6f67f4 ARM: stm32mp: Check secure state first
Secure state must be checked before handling semaphores,
otherwise it can cause an IAC.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2026-02-24 17:49:43 +01:00
Gatien Chevallier
9d3a9080c9 ARM: stm32mp: Fix CID and semaphore check
Peripheral holding CID0 cannot be accessed, remove this completely
incorrect check. While there, fix and simplify the semaphore checking
that should be performed when the CID filtering is enabled.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2026-02-24 17:49:43 +01:00
Gatien Chevallier
5f92eef2f9 ARM: stm32mp: Do not acquire RIFSC semaphore if CID filtering is disabled
If the CID filtering is enabled, the semaphore mode is disabled as well.
To avoid an incorrect behavior and error trace, add a check of CID
filtering state before acquiring the semaphore.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2026-02-24 17:49:43 +01:00
Patrice Chotard
20727a083f configs: stm32mp25: Enable CMD_STM32KEY
Enable CONFIG_CMD_STM32KEY flag to enable usage of command
stm32key.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2026-02-24 17:47:46 +01:00
Thomas Bourgoin
bd6fd26f15 stm32mp: cmd_stm32key: add support of ADAC public key hash
Add support of ADAC-PKH for STM32MP21.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2026-02-24 17:47:46 +01:00
Gwenael Treuveur
c258621b5e stm32mp: cmd_stm32key: add support of remoteproc firmware public key
Add support of RPROC-FW-PKH for STM32MP25, STM32MP23 and STM32MP21.

Signed-off-by: Gwenael Treuveur <gwenael.treuveur@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2026-02-24 17:47:46 +01:00
Thomas Bourgoin
d8a0db4536 stm32mp: cmd_stm32key: add support of remoteproc firmware encryption key
Add support of RPROC-FW-KEY for STM32MP25, STM32MP23 and STM32MP21.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2026-02-24 17:47:46 +01:00
Thomas Bourgoin
cbd3977207 stm32mp: cmd_stm32key: add support of OTP key format 2
Add support of OTP key format 2 used by OP-TEE.
Key formats are describes in the STM32MPUs references manuals
section OTP mapping.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2026-02-24 17:47:46 +01:00
Thomas Bourgoin
dcb304943e stm32mp: cmd_stm32key: add support of STM32MP21x SoC
Update stm32key to support stm32mp21 OTP mapping.
Create a new list of key to support the following differences :
  - STM32MP21x SoC support 128b and 25b FSBL encryption keys.
  - OEM-KEY1 and OEM-KEY2 used for authentication are in different OTP
    from STM32MP25 and STM32MP23.

stm32key is compatible with platform STM32MP2 (aarch64)
Hence, use unsigned long to handle argument addr of function
read_key_value() instead of u32.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2026-02-24 17:47:31 +01:00
Patrice Chotard
ac7f28523c stm32mp1: Add check on syscon_get_first_range() return value
syscon_get_first_range()'s return value is used as base address to perform
a read, without any checks.
In case stmp32mp_syscon is not binded, syscon_get_first_range() returns
-ENODEV which leads to a "Synchronous abort".

Add syscon_get_first_range() check on return value.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2026-02-24 17:44:09 +01:00
Patrice Chotard
ab965d31a2 stm32mp2: Add check on syscon_get_first_range() return value
syscon_get_first_range()'s return value is used as base address to perform
a read, without any checks.
In case stmp32mp_syscon is not binded, syscon_get_first_range() returns
-ENODEV which leads to a "Synchronous abort".

Add syscon_get_first_range() check on return value.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2026-02-24 17:44:09 +01:00
Patrice Chotard
4aac418854 stm32mp2: Migrate duplicated code into stm32mp2x.c
Same code is duplicated into stm32mp25x.c, stm32mp23x.c and stm32mp21x.c.

Migrate read_deviceid(), get_cpu_dev(), get_cpu_rev(), get_cpu_type() and
get_cpu_package() into new stm32mp2x.c.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2026-02-24 17:44:09 +01:00
Patrice Chotard
5af044da9b ARM: dts: stm32: Add bootph-all in stm32mp215f-dk-u-boot.dtsi
Add temporarily bootph-all property in usart2 and syscfg nodes
to allows stm32mp215f-dk board to boot.
When DT kernel series [1] will be merged and synchronized in U-Boot
this patch will be reverted.

[1] https://lore.kernel.org/linux-arm-kernel/20260203-upstream_uboot_properties-v6-0-0a2280e84d31@foss.st.com/

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2026-02-24 17:41:48 +01:00
Patrice Chotard
ec3fc57da4 ARM: dts: stm32: Add stm32mp215f-dk-u-boot
Add U-Boot specific file for stm32mp215f-dk board

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2026-02-24 17:41:48 +01:00
Patrice Chotard
d557099fb0 ARM: stm32mp: Add STM32MP21 support
STM32MP21 application processors (STM32 MPUs) based on a single
Arm Cortex®-A35 core running up to 1.5 GHz and Cortex®-M33 core
running at 300 MHz.

It is pin-compatible with the STM32MP2 series in the VFBGA361
10×10 mm package: the STM32MP21 uses a subset of the STM32MP23
pinout, which itself is a subset of the STM32MP25.

More details available here :
https://www.st.com/en/microcontrollers-microprocessors/stm32mp2-series.html

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2026-02-24 17:41:48 +01:00
Patrice Chotard
42fa38b925 stm32mp: cmd_stm32key: add support of STM32MP21x
Add cmd_stm32key support for STM32MP21x SoCs family.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2026-02-24 17:39:34 +01:00
Patrice Chotard
0ec3b31310 stm32mp: syscon: Add STM32MP21 support
Add "st,stm32mp21-syscfg" compatible.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2026-02-24 17:39:34 +01:00
Patrice Chotard
5635627833 reset: stm32mp21: add stm32mp21 reset driver
Implement STM32MP21 reset drivers using stm32-core-reset API.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2026-02-24 17:39:34 +01:00
Patrice Chotard
a44b36a044 clk: stm32mp21: Add clock driver support
Add clock driver support for STM32MP21 SoCs.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2026-02-24 17:39:34 +01:00
James Hilliard
0b2939464f boot: fit: validate FDT/DTO payload before fdt_open_into()
boot_get_fdt_fit_into_buffer() calls fdt_open_into() for both the
base FDT and overlay DTO blobs loaded from a FIT image.

Those blobs come from FIT payload data. In the overlay path,
fit_image_load() is called with FIT_LOAD_IGNORED, so the IH_TYPE_FLATDT
header check in fit_image_load() is skipped. This leaves fdt_open_into()
to consume header-derived offsets/sizes from unvalidated input.

Validate the full blob against the payload length first with
fdt_check_full(fdtsrcbuf, srclen), then proceed with fdt_totalsize() and
fdt_open_into(). This fixes Coverity CID 644638 (TAINTED_SCALAR).

Fixes: 5ebf0c55a2 ("image: fit: Apply overlays using aligned writable FDT copies")
Link: https://lore.kernel.org/all/20260223195109.GG3233182@bill-the-cat/
Signed-off-by: James Hilliard <james.hilliard1@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2026-02-24 10:28:37 -06:00
Devarsh Thakkar
26048cdb4c arm: mach-k3: common: Clamp RAM end address to board-usable region in spl_enable_cache()
commit ba20b2443c ("arm: mach-k3: common: Reserve video memory from
end of the RAM") switched spl_enable_cache() to use gd->ram_top directly
but omitted the board_get_usable_ram_top() call that limits RAM
configuration and provides updated RAM end address per memory map
used by board and impacts subsequent allocations and reservations.
For e.g. here it impacts how high the TLB may be placed.

On Verdin AM62 (512 MiB), the raw end of RAM (0xA0000000) is inside
OP-TEE's region. board_get_usable_ram_top() in verdin-am62.c returns
0x9C000000 to keep relocations below it, but spl_enable_cache() never
called it. commit 42b3ee7fa5 ("arm: mach-k3: am62x: Enable memory
firewall support") then enforced the OP-TEE firewall, turning the silent
corruption into a hard hang.

Fix by calling board_get_usable_ram_top() after computing raw ram_top,
consistent with setup_dest_addr() in board_f.c. A weak default is
provided for boards that do not need to restrict the RAM top.

Fixes: ba20b2443c ("arm: mach-k3: common: Reserve video memory from end of the RAM")
Reported-by: Francesco Dolcini <francesco@dolcini.it>
Link: https://lore.kernel.org/all/20260224102121.GB340942@francesco-nb/
Signed-off-by: Devarsh Thakkar <devarsht@ti.com>
Tested-by: Francesco Dolcini <francesco.dolcini@toradex.com> # Verdin AM62 512MB
2026-02-24 10:28:21 -06:00
Mark Kettenis
afa8f076db arm: armv8: Flush TLB before enabling MMU
Commit 9ebdbbc43e ("arm: armv8: invalidate dcache entries on
dcache_enable") broke Apple Silicon machines in certain scenarios.
If the MMU is currently not enabled we need to flush the TLB
before we enable it to prevent stale TLB entries from becoming
active again.  So move the __asm_invalidate_tlb_all() back
immediately before the mmu_setup() call.

Fixes: 9ebdbbc43e ("arm: armv8: invalidate dcache entries on dcache_enable")
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2026-02-24 08:16:06 -06:00
Patrice Chotard
6a6f2eb3e6 board: st: common: add uclass_get_device_by_driver()'s return value check
class_get_device_by_driver()'s return value is not checked, in case of BSEC
driver is not probed, dev is not set and used just after as parameter of
misc_read() which leads to a Synchronous Abort.

Add uclass_get_device_by_driver()'s return value check to fix it.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2026-02-24 14:14:15 +01:00
Patrice Chotard
32912d0908 board: st: common: Add support of stm32mp21xx-dk board
Add board identifier for STM32MP21 discovery board = MB2059.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2026-02-24 14:14:15 +01:00
Patrice Chotard
d5cedabe8b stm32mp2: Update size of DDR entry in MMU table
On 1GB board, in particular cases, a prefetch operation is done just above
the 1GB boundary. The DDR size is 1GB (0x80000000 to 0xc0000000), there is
an access on 0xc00017c0 (ie 0x800017c0).

As beginning of DDR is protected by MMU until CONFIG_TEXT_BASE
(0x80000000 to 0x84000000), it triggers the following IAC:

E/TC:0   stm32_iac_itr:192 IAC exceptions [159:128]: 0x200
E/TC:0   stm32_iac_itr:197 IAC exception ID: 137
I/TC:

DUMPING DATA FOR risaf@420d0000
I/TC: =====================================================
I/TC: Status register (IAESR0): 0x11
I/TC: -----------------------------------------------------
I/TC: Faulty address (IADDR0): 0xc00017c0
I/TC: =====================================================
E/TC:0   Panic at /usr/src/debug/optee-os-stm32mp/4.0.0-gitvalid.8>
E/TC:0   TEE load address @ 0x82000000
E/TC:0   Call stack:
E/TC:0    0x82007f30
E/TC:0    0x820444b4
E/TC:0    0x8202dc54
E/TC:0    0x82041fe0
E/TC:0    0x820143b8

By default, in MMU table, the DDR size is set to 4GB, but not all
STM32MP2 based board embeds 4GB, some has only 1 or 2GB of DDR.

The MMU table entry dedicated to DDR need to be updated with the real
DDR size previously read from DT.
After relocation, in enable_caches(), update the MMU table between the
dcache_disable() / dcache_enable() with the real DDR size.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2026-02-24 14:13:08 +01:00
Patrice Chotard
5d5195073c stm32mp: fix array bounds checks
Fix index check against array size. If that index is equal
to the array size, we'll access one-past-the-end of the array.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2026-02-24 14:12:34 +01:00
Patrice Chotard
71433d2771 stm32mp: stm32prog: Remove fsbl_nor_detected from stm32prog_data struct
No more need to test if a fsbl partition is present on NOR when booting
from serial or USB. Now MTD devices are automatically populated with
partition information found in DT. Remove fsbl_nor_detected boolean from
stm32prog_data struct and all code using it.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2026-02-24 14:11:59 +01:00
Fabien Dessenne
04dcaadd43 pinctrl: pinctrl_stm32: prevent the use of the secure protected pins
The hardware denies any access from the U-Boot non-secure world to the
secure-protected pins. Hence, prevent any driver to configure such a pin.
Identify the secure pins with "NO ACCESS" through the 'pinmux status -a'
command.
Use a driver data structure to identify which hardware versions support
this feature.

Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2026-02-24 14:09:45 +01:00
Fabien Dessenne
7accb716c1 gpio: stm32-gpio: prevent the use of the secure protected pins
The hardware denies any access from the U-Boot non-secure world to the
secure-protected pins. Hence, prevent any driver to request such a pin.

Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2026-02-24 14:09:45 +01:00
Tom Rini
4f70106bea Prepare v2026.04-rc3
Signed-off-by: Tom Rini <trini@konsulko.com>
2026-02-23 13:17:02 -06:00
Eric Kilmer
e365a269df fs/squashfs: fix heap buffer overflow in sqfs_frag_lookup()
sqfs_frag_lookup() reads a 16-bit metadata block header whose lower
15 bits encode the data size. Unlike sqfs_read_metablock() in
sqfs_inode.c, this function does not validate that the decoded size is
within SQFS_METADATA_BLOCK_SIZE (8192). A malformed SquashFS image can
set the size field to any value up to 32767, causing memcpy to write
past the 8192-byte 'entries' heap buffer.

Add the same bounds check used by sqfs_read_metablock(): reject any
metadata block header with SQFS_METADATA_SIZE(header) exceeding
SQFS_METADATA_BLOCK_SIZE.

Found by fuzzing with libFuzzer + AddressSanitizer.

Signed-off-by: Eric Kilmer <eric.kilmer@trailofbits.com>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
2026-02-23 12:45:50 -06:00
Kaustabh Chakraborty
11198fa347 doc: board: samsung: exynos-mobile: remove requirement of stub device tree
Flashing U-Boot for Exynos 7870 requires creating a stub device tree,
where certain properties and nodes are defined which are populated by
the previous bootloader in the phones.

Since these properties are now available in the U-Boot device tree, it's
now possible to use the same blob generated by U-Boot in place of the
stub, when creating boot images. Update the build documentation to
reflect the same.

Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2026-02-23 15:35:33 +09:00
Kaustabh Chakraborty
d73efc6841 ARM: dts: exynos7870-on7xelte: add properties to make S-BOOT happy
Add properties in the DTSI file which is required for S-BOOT when used
an external device tree when booting into U-Boot. S-BOOT is Samsung's
proprietary bootloader, which chainloads U-Boot.

Since this device has multiple bank nodes, add memory nodes for each RAM
bank. This is the format S-BOOT recognizes, and (re)populates it with
the correct bank sizes.

Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2026-02-23 15:35:33 +09:00
Kaustabh Chakraborty
cc77806b5d ARM: dts: exynos7870-j6lte: add properties to make S-BOOT happy
Add properties in the DTSI file which is required for S-BOOT when used
an external device tree when booting into U-Boot. S-BOOT is Samsung's
proprietary bootloader, which chainloads U-Boot.

Since this device has multiple bank nodes, add memory nodes for each RAM
bank. This is the format S-BOOT recognizes, and (re)populates it with
the correct bank sizes.

Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2026-02-23 15:35:33 +09:00
Kaustabh Chakraborty
579349593a ARM: dts: exynos7870-a2corelte: add properties to make S-BOOT happy
Add properties in the DTSI file which is required for S-BOOT when used
an external device tree when booting into U-Boot. S-BOOT is Samsung's
proprietary bootloader, which chainloads U-Boot.

Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2026-02-23 15:35:33 +09:00
Kaustabh Chakraborty
be1b1cd641 doc: board: samsung: exynos-mobile: use u-boot-nodtb.bin for packaging process
U-Boot for this board is programmed to use the external DTB if an
internal device tree is not available. This makes it safe to build boot
images using the non-DTB U-Boot binary, while taking up less space.
Reflect this change in documentation.

Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2026-02-23 15:35:33 +09:00
Kaustabh Chakraborty
ac93c4534f doc: board: samsung: exynos-mobile: add DEVICE_TREE make flag in build
Since there is only one internal device tree allowed in U-Boot, the
DEVICE_TREE flag is required for building images for various devices.
Document it in the build guide.

Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2026-02-23 15:35:33 +09:00
Kaustabh Chakraborty
743b91bab7 configs: exynos-mobile: remove DEFAULT_DEVICE_TREE and add OF_UPSTREAM_BUILD_VENDOR
Since the build documentation recommends using the DEVICE_TREE= make
flag, and the "board" supports multiple devices, remove the default
device tree option so as to enforce the make flag during build.

OF_UPSTREAM_BUILD_VENDOR is added so as to build all device trees
associated with the vendor with their U-Boot includes.

Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2026-02-23 15:35:33 +09:00
Kaustabh Chakraborty
e215c1a558 board: samsung: exynos-mobile: enable OF_BOARD support
OF_BOARD allows to choose the internal device tree in runtime. Use it to
pass the external FDT as an internal one if it is not present. This
approach is also used by qcom-phone, and it reduces boot image size. It
is expected that an external FDT is present as U-Boot is packaged as an
Android boot image.

Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2026-02-23 15:35:33 +09:00
Kaustabh Chakraborty
6220037e7c board: samsung: exynos-mobile: disable MULTI_DTB_FIT support
MULTI_DTB_FIT allowed a single U-Boot image to be booted in multiple
devices, but it was not a scalable solution; as more devices are added,
the U-Boot binary is bound to increase, space taken up by devicetrees
which are not even used.

The other approach is to be able to build separate images for multiple
devices using the same "board" defined in U-Boot. This is used by
qcom_phone to support muitiple devices.

Follow the said approach for Exynos devices as well, disable
MULTI_DTB_FIT for this board.

Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2026-02-23 15:35:33 +09:00
Kaustabh Chakraborty
23ad0660c1 board: samsung: exynos-mobile: resolve env vars without board_info data
Move environment variable setup procedure to exynos_env_setup(). This
function is independent of data from exynos_board_info as it is due for
removal in the succeding commits.

Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2026-02-23 15:35:33 +09:00
Kaustabh Chakraborty
3b9f3620b8 board: samsung: exynos-mobile: simplify parsing RAM banks from device tree
Remove the baked-in bank addresses used for figuring out RAM banks from
device tree. Instead, sequentially fill in the bank addresses and sizes,
and doing away with an extra array for specifying bases.

Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2026-02-23 15:35:33 +09:00
Anshul Dalal
30b8c03d8c board: ti: am64,j721*: use correct fdt if eeprom detection fails
We currently provide default board names for each board in their
respective evm.c file. However for custom boards, this behaviour
overwrites the default DT as set in the defconfig
(CONFIG_DEFAULT_FDT_FILE or CONFIG_DEFAULT_DEVICE_TREE).

This patch changes the default name to be NULL which prevents this
overwrite and allows ti_set_fdt_env to instead fallback to the correct
DT as set in Kconfig.

Signed-off-by: Anshul Dalal <anshuld@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
2026-02-20 08:46:56 -06:00
Chintan Vankar
ebe62142fc arm: mach-k3: j722s: Update SoC data to add wake-up I2C device
Update dev-data and clk-data to include wake-up I2C device for J722s.

Signed-off-by: Chintan Vankar <c-vankar@ti.com>
Tested-by: Richard Genoud <richard.genoud@bootlin.com>
2026-02-20 08:46:51 -06:00
Tom Rini
7dca54ef4c Merge patch series "test: cmd: Add test for zip/unzip/gzwrite commands"
Marek Vasut <marek.vasut+renesas@mailbox.org> says:

Enable zip command in sandbox so it is always build tested.
Add simple test for zip/unzip/gzwrite commands so they are
unit tested.

Link: https://lore.kernel.org/r/20260205014153.218621-1-marek.vasut+renesas@mailbox.org
2026-02-18 15:02:58 -06:00
Marek Vasut
6be3db6c1a test: cmd: Add test for zip/unzip/gzwrite commands
Add simple test for zip/unzip/gzwrite commands. The test works as
follows. First, create three buffers with a bit of space between
each of them, fill them with random data, then compress data in
buffer 1 into buffer 2, decompress data in buffer 2 either directly
into buffer 3 or into MMC 1 and then read them back into buffer 3,
and finally compare buffer 1 and buffer 3, they have to be identical.

The buffers are filled with random data to detect out of bounds writes.
Test for various sizes, both small and large and unaligned.

The test uses ut_assert_skip_to_line() to skip over gzwrite progress
bar. Since the progress bar updates fill up the console record buffer,
increase the size of it to compensate.

Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Tested-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2026-02-18 15:02:58 -06:00
Marek Vasut
8a056a1058 configs: sandbox: Enable zip command
What is not being built and tested in CI, breaks. Enable the 'zip'
command in sandbox to get it build tested in preparation for an
actual unit test.

Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2026-02-18 15:02:58 -06:00
Wadim Egorov
73823d1c58 arm: dts: k3-am64-phycore-som-ddr4: Update DDR timings
Update DDR timings to increase stability in higher temperature ranges.

Update DDR settings:
  - SysConfig DDR tool v0.09.05
  - Package: ALV
  - Extended temperature range -40C to 105C
  - Lower tREFI (ns) to 3900

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Tested-by: Daniel Schultz <d.schultz@phytec.de>
2026-02-18 14:57:31 -06:00
Jeremy Compostella
8666b16015 x86/coreboot: Exclude memory regions starting above 4GB
This commit updates the RAM region filtering logic in
board_get_usable_ram_top() to skip any memory regions whose start address
is above 4GB. Previously, only the end address was capped at 4GB, but
regions entirely above this threshold were still considered.

Typically, the following memory map entries would cause
board_get_usable_ram_top() to return 0x100000000, which is incorrect.

    start=00000000, end=00001000, type=16
    start=00001000, end=000a0000, type=1
    start=000a0000, end=000f6000, type=2
    start=000f6000, end=000f7000, type=16
    start=000f7000, end=00100000, type=2
    start=00100000, end=6f170000, type=1
    start=6f170000, end=70000000, type=16
    start=70000000, end=80800000, type=2
    start=e0000000, end=f8000000, type=2
    start=fa000000, end=fc000000, type=2
    start=fc800000, end=fc880000, type=2
    start=fd800000, end=fe800000, type=2
    start=feb00000, end=feb80000, type=2
    start=fec00000, end=fed00000, type=2
    start=fed20000, end=fed80000, type=2
    start=feda1000, end=feda2000, type=2
    start=fedc0000, end=fede0000, type=2
    start=100000000, end=102400000, type=2
    start=102400000, end=47f800000, type=1
    start=4000000000, end=4020000000, type=2

By adding a check to continue the loop if the region's start address
exceeds 0xffffffffULL, the function now properly ignores regions that are
not usable in 32-bit address space.

Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
2026-02-16 12:00:42 -06:00
Siddharth Vadapalli
e7ef80f670 board: ti: j721e,j7200: fix do_main_cpsw0_qsgmii_phyinit
Since commit 27cc5951c8 ("include: env: ti: add default for
do_main_cpsw0_qsgmii_phyinit"), the value of the environment variable
do_main_cpsw0_qsgmii_phyinit happened to remain '0' and couldn't be
changed without user intervention. This behavior is due to the following
cyclic dependency:
A) ti_common.env sets do_main_cpsw0_qsgmii_phyinit to '0' and its value
   can only be updated automatically by main_cpsw0_qsgmii_phyinit.
B) main_cpsw0_qsgmii_phyinit is defined in j721e.env and it can run only
   if 'do_main_cpsw0_qsgmii_phyinit' is already '1' which isn't possible
   unless the user manually assigns the value.

Fix the aforementioned cyclic dependency by using board_late_init() to
detect the QSGMII Daughtercard and set do_main_cpsw0_qsgmii_phyinit.

Additionally, to address the issue of do_main_cpsw0_qsgmii_phyinit being
'undefined' for other platforms, replace:
	if test ${do_main_cpsw0_qsgmii_phyinit} -eq 1;
with:
	if env exists do_main_cpsw0_qsgmii_phyinit;
in ti_common.env.

Fixes: 27cc5951c8 ("include: env: ti: add default for do_main_cpsw0_qsgmii_phyinit")
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Anshul Dalal <anshuld@ti.com>
2026-02-16 11:52:02 -06:00
Martin Schwan
c3538f788d bootstd: rauc: Fix null pointer access while checking root part
Fix a segmentation fault caused by a null pointer access during root
partition checking. The function part_get_info() was falsely given null
for the disk_partition struct, which later resulted in accessing a null
pointer and thus undefined behavior.

Fixes: 5d7c080ae5 ("bootstd: rauc: Don't check root part filesystem")
Signed-off-by: Martin Schwan <m.schwan@phytec.de>
2026-02-16 11:52:01 -06:00
Hugo Villeneuve
2ac30d21e4 cmd: pxe_utils: fix syntax error in comments
Add missing "to" so that the sentence makes sense.

Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
2026-02-16 11:52:01 -06:00
James Hilliard
5ebf0c55a2 image: fit: Apply overlays using aligned writable FDT copies
libfdt expects FDT/DTO blobs to be 8-byte aligned. When loading the
base FDT or overlays from a FIT, the mapped buffer may be unaligned,
which can break fdt_open_into() on strict-alignment architectures.

boot_get_fdt_fit() relocates the base FDT with boot_relocate_fdt()
before applying overlays. That uses the bootm memory map and can
overlap with the FIT buffer when the FIT is loaded into RAM,
corrupting data needed to load the kernel and ramdisk.

Allocate writable, 8-byte aligned copies of the base FDT and overlays
with memalign() and fdt_open_into(). Grow the base buffer as needed,
apply overlays to it and pack the final tree. Free each temporary
overlay copy after application and check fdt_pack() errors.

Fixes: 8fbcc0e0e8 ("boot: Assure FDT is always 8-byte aligned")
Fixes: 881f0b77dc ("image: apply FDTOs on FDT image node")
Signed-off-by: James Hilliard <james.hilliard1@gmail.com>
Cc: Jamie Gibbons <Jamie.Gibbons@microchip.com>
Reviewed-by: Marek Vasut <marek.vasut@mailbox.org>
2026-02-16 11:52:01 -06:00
Tom Rini
a79edd52a8 MAINTAINERS: Remove a few inactive people
It has been a long while since Jagan Teki, Joe Hershberger or Ramon
Fried have been active in the community. We thank them for their time
over the years. Remove them from the active maintainer list and mark a
few things as Orphaned for now.

Signed-off-by: Tom Rini <trini@konsulko.com>
2026-02-16 11:52:01 -06:00
David Lechner
6f96026b1e test/py: Fix spelling of source_dir in docstring
Fix a typo in the docstring for run_build() where source_dir was
misspelled.

Signed-off-by: David Lechner <dlechner@baylibre.com>
2026-02-16 11:52:01 -06:00
Tom Rini
fec27316cf Merge branch 'master' of git://source.denx.de/u-boot-usb
- A fix for CDNS3 in correctly determining dr_mode for OTG.
2026-02-16 11:52:01 -06:00
Siddharth Vadapalli
bfb530e06c usb: cdns3: use VBUS Valid to determine role for dr_mode OTG
The cdns3_bind() function is responsible for identifying the appropriate
driver to bind to the USB Controller's device-tree node. If the device-tree
node has the 'dr_mode' property set to 'otg', the existing approach fails
to bind a driver, leading to loss of functionality.

To address this, use the VBUS Valid field of the OTG Status register to
determine the role as follows:
- If VBUS Valid field is set, it indicates that a USB Host is supplying
  power and the Controller should assume the Peripheral role.
- If VBUS Valid field is clear, it indicates the absence of a USB Host and
  the Controller should assume the Host role.

Additionally, when 'dr_mode' happens to be 'otg' and the STRAP settings
are not specified, use VBUS Valid to determine the role in cdns3_drd_init()
and assign it to cdns->dr_mode.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Marek Vasut <marek.vasut@mailbox.org>
2026-02-16 15:08:43 +01:00
Tom Rini
6274e400fc Merge tag 'efi-2026-04-rc3' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request efi-2026-04-rc3

CI: https://source.denx.de/u-boot/custodians/u-boot-efi/-/pipelines/29293

UEFI:

* add missing EFI_CALL around tcg2 read_blocks calls
* fix ECPT table size computation
2026-02-15 15:08:14 -06:00
Vincent Stehlé
ca4eda24c6 efi_loader: fix ecpt size computation
The size of the memory allocated for the EFI Conformance Profiles Table is
computed with `num_entries' always equal to zero, which is incorrect when
CONFIG_EFI_EBBR_2_1_CONFORMANCE is enabled.

This can be verified by allocating the ECPT memory with malloc() instead of
efi_allocate_pool(), building u-boot with sandbox_defconfig and
CONFIG_VALGRIND=y, and by finally running the following command:

  valgrind --suppressions=scripts/u-boot.supp \
    ./u-boot -T -c 'efidebug tables'

Fix this by using an array of the supported profiles GUIDs instead, which
should also be easier to extend in the future as U-Boot should publish the
GUIDs for all supported EBBR revisions.

Fixes: 6b92c17352 ("efi: Create ECPT table")
Suggested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Vincent Stehlé <vincent.stehle@arm.com>
Cc: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Cc: Tom Rini <trini@konsulko.com>
Cc: Jose Marinho <jose.marinho@arm.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2026-02-15 08:30:57 +01:00
Vincent Stehlé
05b13c0589 efi_loader: add missing EFI_CALL around tcg2 read_blocks calls
The read_blocks() function from the Block IO protocol is a UEFI function;
make sure to call it from within U-Boot using the EFI_CALL() macro.

To demonstrate the issue on an AArch64 machine, define the DEBUG macro in
include/efi_loader.h and build u-boot with sandbox_defconfig, then download
and uncompress the ACS-DT image [1], and finally execute the following
command:

  $ ./u-boot -T -c " \
      host bind 0 systemready-dt_acs_live_image.wic; \
      setenv loadaddr 0x10000; \
      load host 0 \${loadaddr} EFI/BOOT/Shell.efi; \
      bootefi \${loadaddr} \${fdtcontroladdr}"

The following assertion should fail:

  lib/efi_loader/efi_net.c:858: efi_network_timer_notify: Assertion `__efi_entry_check()' failed.

This happens due to the following EFIAPI functions call chain:

  efi_start_image()
    efi_disk_read_blocks()
      (due to the missing EFI_CALL, entry_count == 2)
      efi_network_timer_notify()

Link: https://github.com/ARM-software/arm-systemready/releases/download/v25.12_DT_3.1.1/systemready-dt_acs_live_image.wic.xz [1]
Fixes: ce3dbc5d08 ("efi_loader: add UEFI GPT measurement")
Signed-off-by: Vincent Stehlé <vincent.stehle@arm.com>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Cc: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Cc: Tom Rini <trini@konsulko.com>
Cc: Masahisa Kojima <kojima.masahisa@socionext.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Acked-by: Masahisa Kojima <kojima.masahisa@socionext.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2026-02-15 08:26:33 +01:00
Suhaas Joshi
f9ffeec4bd board: toradex: Make A53 get RAM size from DT in K3 boards
`dram_init()` is called by R5 SPL and U-Boot, both. It starts by
computing the size of the RAM. In verdin-am62(p), it does so by calling
`get_ram_size()`. This function computes the size of the RAM by writing
over the RAM.

When R5 computes the size of the RAM, it does not update the DT with
this size. As a result, when A53 invokes `dram_init()` again, it has to
compute the size through `get_ram_size()` again.

Commit 13c54cf588 and 0c3a6f748c add firewall over ATF's and OPTEE's
regions. This firewall is added during the R5 SPL stage of boot. So when
A53 attempts to write over RAM in `get_ram_size()`, it writes over the
protected region. Since A53 is a non-secure core, this is blocked by the
firewall.

To fix this, do the following:
    * Implement `spl_perform_board_fixups()` function for verdin-am62
      and verdin-am62p. Make this function call `fixup_memory_node()`,
      which updates the DT.
    * Add an if-block in `dram_init()`, to ensure that only R5 is able
      to call `get_ram_size()`, and that A53 reads this size from the
      DT.

Signed-off-by: Suhaas Joshi <s-joshi@ti.com>
Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com>
2026-02-12 08:12:09 -06:00
Tom Rini
f71ae39529 Merge tag 'xilinx-for-v2026.04-rc3' of https://source.denx.de/u-boot/custodians/u-boot-microblaze
AMD/Xilinx/FPGA changes for v2026.04-rc3

clk:
- zynqmp clk fixes

phy:
- sync vsc8541 config

versal2:
- fix GIC configuration
2026-02-12 08:05:44 -06:00
Tom Rini
dffccda75c Merge tag 'u-boot-dfu-20260211' of https://source.denx.de/u-boot/custodians/u-boot-dfu
u-boot-dfu-20260211

USB Gadget:
* dwc3: Support ip and version type
* dwc3: Increase controller halt timeout
* dwc3: Don't send unintended link state change
* dwc3: Improve reset sequence
* dwc2: Move dr_mode check to bind to support RK3288/RK3506 with
  2 DWC2 controllers
2026-02-11 08:38:19 -06:00
Tom Rini
0e4baa3291 Merge tag 'tpm-master-11022026' of https://source.denx.de/u-boot/custodians/u-boot-tpm
A coverity fix and documentation update from Heiko on SM3 support
2026-02-11 08:37:44 -06:00
Heiko Schocher
1e79d9c763 doc: cmd: add documentation for sm3sum
add documentation for sm3sum command.

Signed-off-by: Heiko Schocher <hs@nabladev.com>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2026-02-11 11:13:47 +02:00
Heiko Schocher
546687c8dc lib: sm3: fix coverity error
Coverity scan reported:

CID 449815:         Memory - illegal accesses  (OVERRUN)
Overrunning array of 64 bytes at byte offset 64 by dereferencing pointer
"sctx->buffer + partial". [Note: The source code implementation of the
function has been overridden by a builtin model.]

In line: 252
   memset(sctx->buffer + partial, 0, SM3_BLOCK_SIZE - partial);

The respective line should be:

memset(sctx->buffer + partial, 0, SM3_BLOCK_SIZE - partial - 1);

as partial gets incremented by one before.

Signed-off-by: Heiko Schocher <hs@nabladev.com>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2026-02-11 11:13:47 +02:00
Pranav Tilak
ce6fc049b7 net: phy: mscc: Enable RMII clock output for VSC8541 PHY
Set RMII reference clock output to enabled (1) by default for VSC8541
PHY in RMII mode. The RMII specification requires a 50MHz reference
clock, and many board designs expect the PHY to provide this clock to
the MAC controller.

Previously, the driver defaulted rmii_clk_out to 0 (disabled) for all
interface modes, which caused the PHY to not output the required 50MHz
clock. This resulted in MAC-PHY communication failures and prevented
network operations like DHCP from working on RMII-configured boards.

This change alligns with the hardware power-up default behavior and
aligns with both the generic PHY driver and Linux MSCC PHY driver
implementations.

Signed-off-by: Pranav Tilak <pranav.vinaytilak@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20260129081054.1703479-1-pranav.vinaytilak@amd.com
2026-02-11 09:41:26 +01:00
Maheedhar Bollapalli
85bbd16750 arm64: versal2: fix GICD/GICR base addresses for Versal Gen 2
Versal2 was using wrong GIC base mappings, causing GICR_TYPER reads to
not match EL1 MPIDR. This led U-Boot to walk beyond the per-CPU GICR
frames, access out-of-range addresses, and hit a synchronous exception
during early gic init percpu while booting up on alternate core
i.e., non cpu0.

Update Versal Gen 2 headers to the correct Versal Gen 2 bases.

Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/d0bc3fe1af8409fcfe505e55fb7042a33b845a4e.1770721325.git.michal.simek@amd.com
2026-02-11 09:26:17 +01:00
Tom Rini
712765339a Merge patch series "Update DDR Configurations"
Santhosh Kumar K <s-k6@ti.com> says:

This series updates the DDR Configurations according to the SysConfig DDR
Configuration tool v0.10.32 for the following devices [1]
 - AM64x EVM
 - AM62x SK
 - AM62x LP SK
 - AM62Ax SK
 - AM62Px SK

Testing:
memtester - 50% of memory for 10 loops - PASSED

[1] https://dev.ti.com/tirex/content/Processor_DDR_Config_0.10.32.0000/docs/REVISION_HISTORY.html

Link: https://lore.kernel.org/r/20260203063529.1551907-1-s-k6@ti.com
2026-02-10 12:57:02 -06:00
Santhosh Kumar K
3391e5ff15 arm: dts: k3-am62p: Update DDR Configurations
Update the DDR Configurations for AM62Px SK according to the SysConfig
DDR Configuration tool v0.10.32. [1]

[1] https://dev.ti.com/tirex/content/Processor_DDR_Config_0.10.32.0000/docs/REVISION_HISTORY.html

Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
2026-02-10 12:56:54 -06:00
Santhosh Kumar K
4f5fcfcea7 arm: dts: k3-am62a: Update DDR Configurations
Update the DDR Configurations for AM62Ax SK according to the SysConfig
DDR Configuration tool v0.10.32. [1]

[1] https://dev.ti.com/tirex/content/Processor_DDR_Config_0.10.32.0000/docs/REVISION_HISTORY.html

Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
2026-02-10 12:56:54 -06:00
Santhosh Kumar K
92f1f586c2 arm: dts: k3-am62-lp: Update DDR Configurations
Update the DDR Configurations for AM62x LP SK according to the SysConfig
DDR Configuration tool v0.10.32. [1]

[1] https://dev.ti.com/tirex/content/Processor_DDR_Config_0.10.32.0000/docs/REVISION_HISTORY.html

Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
2026-02-10 12:56:54 -06:00
Santhosh Kumar K
9ce3b50b8d arm: dts: k3-am62x: Update DDR Configurations
Update the DDR Configurations for AM62x SK according to the SysConfig
DDR Configuration tool v0.10.32. [1]

[1] https://dev.ti.com/tirex/content/Processor_DDR_Config_0.10.32.0000/docs/REVISION_HISTORY.html

Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
2026-02-10 12:56:54 -06:00
Santhosh Kumar K
f5ef79fe65 arm: dts: k3-am64: Update DDR Configurations
Update the DDR Configurations for AM64x EVM according to the SysConfig
DDR Configuration tool v0.10.32. [1]

[1] https://dev.ti.com/tirex/content/Processor_DDR_Config_0.10.32.0000/docs/REVISION_HISTORY.html

Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
2026-02-10 12:56:54 -06:00
Peter Korsgaard
6d865c1ee6 drivers/clk/clk_zynqmp.c: get rid of compiler warning for !CONFIG_CMD_CLK builds
When built without CONFIG_CMD_CLK, we get a warning about the unused
clk_names variable:

../drivers/clk/clk_zynqmp.c:153:27: warning: ‘clk_names’ defined but not used [-Wunused-const-variable=]
  153 | static const char * const clk_names[clk_max] = {

So also guard it with CONFIG_CMD_CLK to get rid of that.

Signed-off-by: Peter Korsgaard <peter@korsgaard.com>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20260119095437.2775081-2-peter@korsgaard.com
2026-02-10 09:27:48 +01:00
Peter Korsgaard
00ea1fc21a drivers/clk/Kconfig: fix "related" typo in help text
It looks like the original zynqmp typo was copied to versal as well.  Fix
both.

Signed-off-by: Peter Korsgaard <peter@korsgaard.com>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20260119095437.2775081-1-peter@korsgaard.com
2026-02-10 09:27:48 +01:00
Tom Rini
b99da05e15 Prepare v2026.04-rc2
Signed-off-by: Tom Rini <trini@konsulko.com>
2026-02-09 15:07:50 -06:00
Tom Rini
89965b5eb5 arm: spl: Ensure 8 byte alignment of appended DTB without separate BSS
Historically, when we have an appended device tree and also our
resulting binary will contain the BSS section, we have ensured that
everything will be where it's expected to be by declaring that the BSS
is overlayed with a symbol matches the end of the port of the ELF binary
that is objcopy'd to the binary we concatenate with. This in turn means
that the logic to generate a "pad" file, which is the size found in the
__bss_size symbol, will be correct and then we can concatenate the
device tree and it will begin at __bss_size at run time.

With commit 5ffc1dcc26 ("arm: Remove rel.dyn from SPL linker scripts")
we removed this overlay as part of trying to ensure that we met both the
requirements of the device tree to be 8 byte aligned as well as that our
logic to generate the -pad file would match what ended up in the
resulting binary. While it was correct to remove an unused section it
did not solve ultimately solve the problem for all cases.

To really fix the problem, we need to do two things. First, our final
section prior to _image_binary_end must be 8 byte aligned (for the case
of having a separate BSS and so our appended DTB exists at this
location). This cannot be '.binman_sym_table' as it may be empty, and in
turn the ELF type would be NOBITS and so not copied with objcopy. The
__u_boot_list section will never be empty, so it is our final section,
and ends with a '. = ALIGN(8)' statement. Second, as this is the end of
our copied data it is safe to declare that the BSS starts here, so use
the OVERLAY keyword to place the BSS here.

Fixes: 5ffc1dcc26 ("arm: Remove rel.dyn from SPL linker scripts")
Reported-by: Brian Sune <briansune@gmail.com>
Reported-by: Phil Phil Sutter <phil@nwl.cc>
Tested-by: Brian Sune <briansune@gmail.com>
Tested-by: Phil Sutter <phil@nwl.cc>
Tested-by: Greg Malysa <malysagreg@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2026-02-09 09:33:20 -06:00
Tom Rini
b270d01a9a configs: Resync with savedefconfig
Resync all defconfig files using qconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2026-02-09 09:32:19 -06:00
Tom Rini
d395ea73dc Merge tag 'net-20260209' of https://source.denx.de/u-boot/custodians/u-boot-net
Pull request net-20260209.

net:
- airoha: mdio support for the switch
- phy: mscc: allow RGMII with internal delay for the VSC8541
- dwc_eth_qos: Update tail pointer handling

net-legacy:
- Stop conflating return value with file size in net_loop()

net-lwip:
- wget: rework the '#' printing
- tftp: add support of tsize option to client
2026-02-09 08:28:01 -06:00
Tom Rini
42b3ee7fa5 Merge tag 'u-boot-at91-2026.04-a' of https://source.denx.de/u-boot/custodians/u-boot-at91
First set of u-boot-at91 features for the 2026.04 cycle:

This small fixes set includes fixing 64 bit builds and some warnings for
the at91 serial driver, and some cleanup on the nand driver.
2026-02-08 10:14:45 -06:00
Paresh Bhagat
c7fbe028ee arm: dts: k3-am62d-evm-binman: Fix device tree reference
Fix ti-secure content reference from spl_am62a7_sk_dtb to
spl_am62d2_evm_dtb or AM62d dtb. Also remove redundant k3-binman.dtsi
include.

Fixes: 14dfa6b861 ("Add initial support for AM62D2-EVM")
Signed-off-by: Paresh Bhagat <p-bhagat@ti.com>
Reviewed-by: Andrew Davis <afd@ti.com>
2026-02-07 15:53:13 -06:00
Bryan Brattlof
da6d5a93dd arm: mach-k3: r5: j721e: clk-data: manually set the main_pll3 frequency
Moving forward, DM firmware will no longer mess with the MAIN_PLL3.
This means MAIN_PLL3 will need to be manually set to 2GHz in order for
the CPSW9G HSDIV to have the correct 250MHz output for RGMII.

Signed-off-by: Bryan Brattlof <bb@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
2026-02-07 15:53:13 -06:00
Raymond Mao
c9d1fe757d MAINTAINERS: Add entry for SMBIOS
Add entry for SMBIOS in MAINTAINERS and assign myself as maintainer.

Signed-off-by: Raymond Mao <raymond.mao@riscstar.com>
2026-02-07 11:52:09 -06:00
Tom Rini
b887a1c1a1 Merge patch series "Add command for getting ramsize in scripts"
Frank Wunderlich <frank-w@public-files.de> says:

Add command for getting ramsize in scripts

Link: https://lore.kernel.org/r/20260204184045.111808-1-linux@fw-web.de
2026-02-07 11:51:43 -06:00
Frank Wunderlich
b4842032d5 doc: cmd: add usage doc for memsize
Add documentation for memsize command.

Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
2026-02-07 11:51:34 -06:00
Frank Wunderlich
8acc8a6546 test: cmd: add test for memsize
Add a test for memsize command in same way as meminfo.

Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
2026-02-07 11:51:33 -06:00
Frank Wunderlich
e202eca183 cmd: mem: add command for getting ram size for use in scripts
Add a command for getting detected ram size with possibility to
assign it to an environment variable.

example usage:

BPI-R4> memsize
4096 MiB
BPI-R4> memsize memsz
BPI-R4> printenv memsz
memsz=4096
BPI-R4>

board with 8GB ram:

BPI-R4> memsize
8192 MiB
BPI-R4> memsize memsz
BPI-R4> printenv memsz
memsz=8192
BPI-R4>

Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
2026-02-07 11:51:33 -06:00
Tom Rini
2ffab9da91 Merge patch series "Firewall ATF and OP-TEE memory regions in Sitara"
Suhaas Joshi <s-joshi@ti.com> says:

This series starts by replacing hard-coded addresses in firewall
templates that are defined in k3-binman.dtsi, by Kconfigs. Using
Kconfigs makes it easier for someone to move ATF and OP-TEE to another
location, since they wouldn't have to fiddle with the firewall
configurations in dtsi files.

The rest of the commits in this series add firewall configs to each
device's dtsi files.

I have only tested this patch series with TI boards. For non-TI Sitara
boards, respective board maintainers are requested to test the relevant
patch and confirm whether it works.

To test this, I used `k3conf <read|write> <address> [<value>]`. Both of
these operations were disallowed, as expected.

Link: https://lore.kernel.org/r/20260127081652.506357-1-s-joshi@ti.com
2026-02-07 11:51:14 -06:00
Suhaas Joshi
64daef1ada arm: dts: k3-am642-phycore-binman: Configure firewall for ATF/OPTEE
Add firewall configurations to protect ATF and OP-TEE memory regions
from non-secure read's and write's in Phycore AM64 SOM.

Signed-off-by: Suhaas Joshi <s-joshi@ti.com>
2026-02-07 11:50:06 -06:00
Suhaas Joshi
31d5d1b378 arm: dts: k3-am64x-binman: Configure firewall for ATF/OPTEE
Add firewall configurations to protect ATF and OP-TEE memory regions
from non-secure reads and writes in AM64x.

Signed-off-by: Suhaas Joshi <s-joshi@ti.com>
2026-02-07 11:50:06 -06:00
Suhaas Joshi
3c6c2f3f5c arm: dts: k3-am62a-phycore-binman: Configure firewall for ATF/OPTEE
Add firewall configurations to protect ATF and OP-TEE memory regions
from non-secure read's and write's in Phycore AM62A SOM.

Signed-off-by: Suhaas Joshi <s-joshi@ti.com>
2026-02-07 11:50:06 -06:00
Suhaas Joshi
cb238a6b66 arm: dts: k3-am62a-binman: Configure firewall for ATF/OPTEE
Add firewall configurations to protect ATF and OP-TEE memory regions
from non-secure reads and writes in AM62A.

Signed-off-by: Suhaas Joshi <s-joshi@ti.com>
2026-02-07 11:50:06 -06:00
Suhaas Joshi
0c3a6f748c arm: dts: k3-am62p5-verdin-binman: Configure firewall for ATF/OPTEE
Add firewall configurations to protect ATF and OP-TEE memory regions
from non-secure read's and write's in Verdin AM62P board.

Signed-off-by: Suhaas Joshi <s-joshi@ti.com>
2026-02-07 11:50:06 -06:00
Suhaas Joshi
eaaec18f7a arm: dts: k3-am62p-binman: Configure firewall for ATF/OPTEE
Add firewall configurations to protect ATF and OP-TEE memory regions
from non-secure reads and writes in AM62P.

Signed-off-by: Suhaas Joshi <s-joshi@ti.com>
2026-02-07 11:50:06 -06:00
Suhaas Joshi
13c54cf588 arm: dts: k3-am625-verdin-binman: Configure Firewall for ATF/OPTEE
Add firewall configurations to protect ATF and OP-TEE memory regions
from non-secure read's and write's in Verdin AM62 board.

Signed-off-by: Suhaas Joshi <s-joshi@ti.com>
2026-02-07 11:50:06 -06:00
Suhaas Joshi
0cee13fe86 arm: dts: k3-am625-phycore-binman: Configure firewall for ATF/OPTEE
Add firewall configurations to protect ATF and OP-TEE from non-secure
reads and writes in Phycore AM625 SOM.

Signed-off-by: Suhaas Joshi <s-joshi@ti.com>
2026-02-07 11:50:06 -06:00
Suhaas Joshi
27f105fbbd arm: dts: k3-am625-binman: Configure firewall for ATF/OPTEE
Add firewall configurations to protect ATF and OP-TEE memory regions
from non-secure reads and writes in AM62x.

Signed-off-by: Suhaas Joshi <s-joshi@ti.com>
2026-02-07 11:50:06 -06:00
Suhaas Joshi
24338c81ec arm: dts: k3-binman: Use configs for ATF/OPTEE addresses
Instead of hard-coding ATF and OPTEE addresses in firewall configuration
templates, use K3_*_LOAD_ADDR. Doing so ensures that if someone moves
ATF/OPTEE regions, the change gets picked up by binman without
explicitly having to modify dts files.

Signed-off-by: Suhaas Joshi <s-joshi@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
2026-02-07 11:50:06 -06:00
Tom Rini
3243a73102 Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sh
- Enable wget and TCP on R-Car systems
2026-02-07 07:50:55 -06:00
Tom Rini
717cd8d54c Merge tag 'u-boot-imx-master-20260206' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/29216

- Convert imx8mn_var_som to OF_UPSTREAM and several cleanups.
- Fix ele_ahab buid error on imx93_qsb.
- Add i.MX95 EVK remoteproc support.
- Several i.MX8/9 EVK cleanups.
2026-02-07 07:50:05 -06:00
Niko Mauno
470ea759aa mach-imx: ele_ahab: Mitigate imx93_qsb build error
Add include to avoid following build error with imx93_qsb, when
AHAB_BOOT is enabled:

  .../arch/arm/mach-imx/ele_ahab.c:262:24: error: 'IMG_CONTAINER_BASE' undeclared (first use in this function); did you mean 'IMG_CONTAINER_END_BASE'?
  .../arch/arm/mach-imx/ele_ahab.c:477:20: error: 'FSB_BASE_ADDR' undeclared (first use in this function); did you mean 'WDOG_BASE_ADDR'?
  .../arch/arm/mach-imx/ele_ahab.c:543:20: error: 'FSB_BASE_ADDR' undeclared (first use in this function); did you mean 'WDOG_BASE_ADDR'?

Signed-off-by: Niko Mauno <niko.mauno@vaisala.com>
2026-02-06 20:35:56 -03:00
Hugo Villeneuve
48133bcd16 board: imx8mn-var-som: compile SPL-only stuff only in SPL build
SPL-specific stuff is already in spl.c, so avoid compiling other source
files in SPL build.

Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
2026-02-06 20:32:36 -03:00
Hugo Villeneuve
40b8b34315 board: imx8mn-var-som: remove unneeded header files
Cleanup the file by removing unneeded header files.

Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
2026-02-06 20:32:36 -03:00
Hugo Villeneuve
ced337fccb board: imx8mn_var_som: let clock system enable UART clock
Now that the UART driver can enable the required clocks, remove
the hard-coded clock enable.

Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
2026-02-06 20:32:36 -03:00
Hugo Villeneuve
56246896a3 arm: dts: imx8mn-var-som-symphony: migrate to OF_UPSTREAM
Switch to OF_UPSTREAM to make use of the upstream device trees.

Remove the now obsolete device tree files:
- imx8mn-var-som-symphony.dts
- imx8mn-var-som.dtsi

Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
2026-02-06 20:32:36 -03:00
Hugo Villeneuve
57d9399b46 arm: dts: imx8mn-var-som: add som-eeprom alias to SOM u-boot dtsi
The som-eeprom alias is specific to U-Boot, and not present in upstream
linux imx8mn-var-som device tree.

Add it to the SOM U-Boot specific device tree file in preparation
for migration to OF_UPSTREAM.

Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
2026-02-06 20:32:36 -03:00
Hugo Villeneuve
57fce421a4 arm: dts: imx8mn-var-som: Move SOM-specific nodes to SOM u-boot.dtsi
Move SOM-specific stuff into a new SOM u-boot.dtsi file.
This way, it can be used by multiple boards.

Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
2026-02-06 20:32:36 -03:00
Peng Fan
650b381d27 toradex: smarc-imx95: Drop init_uart_clk
Rely on serial driver calling clk_enable to enable the lpuart clk, no
need to do init_uart_clk in board_early_init_f().

Also remove board_early_init_f(), because it is empty now.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Francesco Dolcini <francesco.dolcini@toradex.com>
2026-02-06 20:32:10 -03:00
Peng Fan
7412a1dbaf nxp: imx94_evk: Drop init_uart_clk
Rely on serial driver calling clk_enable to enable the lpuart clk, no
need to do init_uart_clk in board_early_init_f().

Also remove board_early_init_f(), because it is empty now.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-02-06 20:32:10 -03:00
Peng Fan
620c1aaa2b nxp: imx95_evk: Drop init_uart_clk
Rely on serial driver calling clk_enable to enable the lpuart clk, no
need to do init_uart_clk in board_early_init_f().

Also remove board_early_init_f(), because it is empty now.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-02-06 20:32:10 -03:00
Peng Fan
36d93a7cd7 imx95_evk: Enable remoteproc for i.MX95 EVK
Select remoteproc related configs for i.MX95 EVK to support manage CM7
using 'rproc' cmd.
Update doc to show details on starting CM7 using rproc cmd.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-02-06 20:31:33 -03:00
Peng Fan
7bb12b8dfe arm: dts: imx95: Add cm7 node
Add i.MX95 CM7 node for remoteproc usage. The dt-bindings for CM7 was
accepted, by the node has not been upstreamed to Linux device tree.

Put the node here to let the driver probe. After Linux upstream repo
has this node landed, the node in imx95-u-boot.dtsi could be removed.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-02-06 20:31:32 -03:00
Peng Fan
3fa7b1055b remoteproc: imx: Add i.MX95 support
i.MX95 uses System Manager(sm) API to start/stop logical machine or cpu.
There are two modes:
 M7 in a dedicated logical machine, use LMM API
 M7 and A55 in same logical machine, use CPU API

Extend the driver to using LMM and CPU protocol to manage the M7 core:
 - Detect using LMM or CPU API in probe using API scmi_imx_lmm_info().
 - Compare linux LM ID(got using scmi_imx_lmm_info) and M7 LM ID(the ID
   is fixed as 1 in SM firmware if M7 is in a separate LM),
   if Linux LM ID is not same as M7 LM ID(linux and M7 in same LM), use
   LMM protocol to start/stop. Whether using CPU or LMM protocol to
   start/stop, the M7 status detection could use CPU protocol to detect
   started or not. So in imx_rproc_is_running, use scmi_imx_cpu_started to
   check the status of M7.
 - For above case (2), Use scmi_imx_lmm_power_boot to detect whether
   the M7 LM is under control of A55 LM.
 - For above case , after using SCMI_IMX_LMM_POWER_ON to check
   permission, scmi_imx_lmm_shutdown API should be called to shutdown
   the M7 LM.
 - Add a new ops imx_rproc_ops_sm.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-02-06 20:31:32 -03:00
Peng Fan
15cb4033c9 remoteproc: imx: Support ECC initialization
Add a new flag ATT_ECC which indicates the memory region needs ECC
initialization. If the flag is set, clearing the whole memory region to
initialize ECC. If ECC is not initialized, remote core will crash if
directly access the area.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-02-06 20:31:32 -03:00
Francois Berder
944e577827 board: ge: common: vpd: Fix read_i2c_vpd return value
If i2c_eeprom_size fails, the error value is stored in
variable size and not ret.
Also, this commit fixes printing the error value.

Signed-off-by: Francois Berder <fberder@outlook.fr>
2026-02-06 20:30:18 -03:00
Peng Fan
98d6f42fc5 imx93_frdm: Update IMX_BOOT_IMAGE_GUID
Reusing IMX_BOOT_IMAGE_GUID from i.MX93 EVK is wrong. The ID is per
board, so regenerate one using uuidgen.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-02-06 20:30:00 -03:00
Peng Fan
1384a9ddeb imx93_frdm: Drop DECLARE_GLOBAL_DATA_PTR
There is no user of "gd", so drop DECLARE_GLOBAL_DATA_PTR.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-02-06 20:30:00 -03:00
Peng Fan
3cde536025 imx8mq_evk: spl: Drop DECLARE_GLOBAL_DATA_PTR
There is no user of "gd", so drop DECLARE_GLOBAL_DATA_PTR.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-02-06 20:29:59 -03:00
Peng Fan
7e4e4ccc47 imx8ulp_evk: Cleanup headers
Drop unused headers and sort them.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-02-06 20:29:59 -03:00
Peng Fan
ba69cabb64 imx8ulp_evk: Drop board_phy_config
There is already a weak function in drivers/net/phy/phy.c, which
does the same thing. So drop it.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-02-06 20:29:59 -03:00
Peng Fan
8178c23737 imx8ulp_evk: Drop DECLARE_GLOBAL_DATA_PTR
There is no user of "gd", so drop DECLARE_GLOBAL_DATA_PTR.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-02-06 20:29:59 -03:00
Peng Fan
4559cd3ea4 imx8mn_evk: Cleanup headers
Drop unused headers and sort them.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-02-06 20:29:59 -03:00
Peng Fan
e590536a09 imx8mn_evk: spl: Drop DECLARE_GLOBAL_DATA_PTR
There is no user of "gd", so drop DECLARE_GLOBAL_DATA_PTR.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-02-06 20:29:59 -03:00
Peng Fan
652830fa0b imx8mp_evk: Cleanup headers
Drop unused headers and sort them.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-02-06 20:29:59 -03:00
Peng Fan
649a52aeb9 imx8mp_evk: spl: Drop DECLARE_GLOBAL_DATA_PTR
There is no user of "gd", so drop DECLARE_GLOBAL_DATA_PTR.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-02-06 20:29:59 -03:00
Peng Fan
4ea79496b0 imx8mp_evk: spl: Drop i2c_pad_info1
With commit 6e6492c85d ("imx8mp_evk: Convert to DM_PMIC"),
i2c_pad_info1 is no longer needed, remove it.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-02-06 20:29:59 -03:00
Peng Fan
79e1a5b69f imx8mm_evk: Drop DECLARE_GLOBAL_DATA_PTR
There is no user of "gd", so drop DECLARE_GLOBAL_DATA_PTR.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-02-06 20:29:59 -03:00
Primoz Fiser
1a79ea5b36 net: fec_mxc: Add support for i.MX91
The i.MX91 SoC reuses the ENET FEC from i.MX93. Add all required driver
checks to make it work also on the i.MX91 based platforms.

Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
2026-02-06 20:29:30 -03:00
Marek Vasut
0cd81619bb arm: renesas: Enable wget command and TCP on all R-Car systems
Enable the 'wget' command and TCP protocol support on all Renesas R-Car
systems. This allows users to download content from local HTTP server,
which may sometimes be more accessible than TFTP server. Enable TCP SACK
support to improve download performance.

The usage is similar to the TFTP command. To download file from server
http://192.ser.ver.ip/file/path/on/local/server , invoke wget as follows:
"
=> wget $loadaddr 192.ser.ver.ip:/file/path/on/local/server
"

In case the HTTP server listens on port other than default port 80,
set the 'httpdstp' environment variable to download file from server
http://192.ser.ver.ip:8088/file/path/on/local/server
"
=> env set httpdstp 8088
=> wget $loadaddr 192.ser.ver.ip:/file/path/on/local/server
"

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2026-02-06 20:23:12 +01:00
Tom Rini
e5e75ea8c7 Merge tag 'efi-2026-04-rc2' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request efi-2026-04-rc2

CI: https://source.denx.de/u-boot/custodians/u-boot-efi/-/pipelines/29203

Documentation:

* Remove pip from requirements.txt
* develop/process: Clarify name usage in the Signed-off-by line

UEFI:

* Improve EFI variable load message
* Fix use after free in efi_exit() with tcg2
* Fix efi_debug_image_info_normal allocation
* Add missing EFI_CALL in efi_net
2026-02-06 12:35:44 -06:00
Charles Perry
e7b83e64d6 net: phy: mscc: allow RGMII with internal delay for the VSC8541
Add the missing RGMII modes with internal delay for the VSC8541.

Fixes: a5fd13ad19 ("net: phy: MSCC Add Support for VSC8530-VSC8531-VSC8540-VSC8541")
Signed-off-by: Charles Perry <charles.perry@microchip.com>
2026-02-06 16:42:45 +01:00
Mikhail Kshevetskiy
b7984ef41a arm: dts: en7523: add mdio child node to switch node
add mdio node to be able see switch port states

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
2026-02-06 16:42:45 +01:00
Mikhail Kshevetskiy
d58e12688e configs: en7523: add mii/mdio support
This enables mdio/mii command support.

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
2026-02-06 16:42:45 +01:00
Mikhail Kshevetskiy
d8bb4a44a2 arm: dts: an7581: add mdio child node to switch node
add mdio node to be able see switch port states

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
2026-02-06 16:42:45 +01:00
Mikhail Kshevetskiy
0b46bdcf39 configs: an7581: add mii/mdio support
This enables mdio/mii command support.

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
2026-02-06 16:42:45 +01:00
Mikhail Kshevetskiy
3aabc0dae0 net: mdio-mt7531-mmio: fix switch regs initialization
mdio is a child node of the switch, so to get switch base address
we need to lookup for a parent node

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
2026-02-06 16:42:45 +01:00
Mikhail Kshevetskiy
caa62920e3 net: airoha_eth: use proper switch node for en7523 case
Commit d2145a89bc ("net: airoha: bind MDIO controller on Ethernet load")
uses "airoha,en7581-switch" dts node for finding MDIO childs. This is wrong
for EN7523 SoC. The correct node name should be used instead.

Fixes: d2145a89bc ("net: airoha: bind MDIO controller on Ethernet load")
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
2026-02-06 16:42:45 +01:00
Mikhail Kshevetskiy
1db453a5fe net: airoha_eth: fix mdio binding to switch device
Commit d2145a89bc ("net: airoha: bind MDIO controller on Ethernet load")
refers to non-present CONFIG_MDIO_MT7531 and non-present "mt7531-mdio"
driver. It should use CONFIG_MDIO_MT7531_MMIO and "mt7531-mdio-mmio"
instead.

Fixes: d2145a89bc ("net: airoha: bind MDIO controller on Ethernet load")
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
2026-02-06 16:42:45 +01:00
Jonas Karlman
5fdc297b89 net: dwc_eth_qos: Define more of the unused MAC regs
Multicast and Broadcast Queue Enable and Promiscuous Mode Enable bits
are currently written to "unused" registers using magic values.

Define more of the "unused" MAC regs based on information in the
DesignWare Cores Ethernet Quality-of-Service databook.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
2026-02-06 16:42:45 +01:00
Jonas Karlman
8beb70f230 net: dwc_eth_qos: Start DMA and MAC after tail pointers are initialized
The DesignWare Cores Ethernet Quality-of-Service databook state that
receive and transmit descriptor list address and also transmit and
receive tail pointer registers should be initialized before the receive
and transmit DMAs are started.

It also state to enable the MAC receiver only after the DMA is active.
Otherwise, received frames can fill the Rx FIFO and overflow.

Move the activation of receive and transmit DMA and MAC receiver until
after tail pointer registers have been initialized.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
2026-02-06 16:42:45 +01:00
Jonas Karlman
34c1ab534c net: dwc_eth_qos: Initialize the transmit tail pointer in eqos_start()
The DesignWare Cores Ethernet Quality-of-Service databook state that
descriptors up to one location less than the one indicated by the
descriptor tail pointer are owned by the DMA. The DMA continues to
process the descriptors until the following condition occurs:

  Current Descriptor Pointer == Descriptor Tail Pointer

The DMA goes into suspend mode when this condition occurs, and updating
the tail pointer resume the DMA processing.

Configure the transmit tail pointer to the first (current) descriptor
pointer so that the tail pointer is a valid address instead of being
initialized to NULL when transmit DMA is started.

Also update the receive tail pointer comment to state that by pointing
to the last descriptor we are actually implying that all receive
descriptors are owned by and can be processed by the DMA.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
2026-02-06 16:42:45 +01:00
Jonas Karlman
09245e094f net: dwc_eth_qos: Use lower_32_bits() for tail pointers
The DesignWare Cores Ethernet Quality-of-Service databook state that the
descriptor address from the start to the end of the ring must not cross
the 4GB boundary.

Use lower_32_bits() to write the lower 32 bits of descriptor addresses,
including the 32-bit tail pointers, consistently. No functional change
is intended.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
2026-02-06 16:42:45 +01:00
Marek Vasut
68a8f0f1f3 net: lwip: wget: rework the '#' printing
Currently, the LWIP wget command prints excessive amount of progress
indicator '#' for very long file downloads, limit this to one line
that scales according to transfer size.

The HTTP server does report the size of the entire file in protocol
headers, which are received before the actual data transfer. Cache
this information and use it to adaptively print progress indicator
'#' until it fills one entire line worth of '#', which indicates the
transfer has completed. This way, long transfers don't print pages of
'#', but every transfer will print exactly one line worth of '#'. The
algorithm for '#' printing is the same as TFTP tsize one.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Jerome Forissier <jerome.forissier@rm.com>
2026-02-06 16:42:45 +01:00
Marek Vasut
337f50bad2 net: lwip: tftp: add support of tsize option to client
The TFTP server can report the size of the entire file that is about to
be received in the Transfer Size Option, this is described in RFC 2349.
This functionality is optional and the server may not report tsize in
case it is not supported.

Always send tsize request to the server to query the transfer size,
and in case the server does respond, cache that information locally
in tftp_state.tsize, otherwise cache size 0. Introduce new function
tftp_client_get_tsize() which returns the cached tftp_state.tsize so
clients can determine the transfer size and use it.

Update net/lwip/tftp.c to make use of tftp_client_get_tsize() and
avoid excessive printing of '#' during TFTP transfers in case the
transfer size is reported by the server.

Submitted upstream: https://savannah.nongnu.org/patch/index.php?item_id=10557

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Jerome Forissier <jerome.forissier@arm.com>
2026-02-06 16:42:37 +01:00
Yuya Hamamachi
a28db0f1cc net: tftp: Fix TFTP Transfer Size data type
The TFTP transfer size is unsigned integer, update the data type
and print formating string accordingly to prevent an overflow in
case the file size is longer than 2 GiB.

TFTP transfer of a 3 GiB file, before (wrong) and after (right):
Loading: #################################################  16 EiB
Loading: ##################################################  3 GiB

Signed-off-by: Yuya Hamamachi <yuya.hamamachi.sx@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2026-02-06 16:37:31 +01:00
Yuya Hamamachi
86f90e2a5f net: Stop conflating return value with file size in net_loop()
The net_loop() currently conflates return value with file size
at the end of successful transfer, in NETLOOP_SUCCESS state.

The return type of net_loop() is int, which makes this practice
workable for file sizes below 2 GiB, but anything above that will
lead to overflow and bogus negative return value from net_loop().

The return file size is only used by a few sites in the code base,
which can be easily fixed. Change the net_loop() return value to
always be only a return code, in case of error the returned value
is the error code, in case of successful transfer the value is 0
or 1 instead of 0 or net_boot_file_size . This surely always fits
into a signed integer.

By keeping the return code 0 or 1 in case of successful transfer,
no conditionals which depended on the old behavior are broken, but
all the sites had to be inspected and updated accordingly.

Fix the few sites which depend on the file size by making them
directly use the net_boot_file_size variable value. This variable
is accessible to all of those sites already, because they all
include net-common.h .

Signed-off-by: Yuya Hamamachi <yuya.hamamachi.sx@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2026-02-06 16:37:31 +01:00
Tom Rini
a54d613baf CI: Update to using grub-2.14 for our tests
When building grub-2.12 with a newer GCC, we run in to warings (treated
as errors). The simple fix here is to move to the latest release tag. In
order to build a newer grub from source we need the autoconf-archive
package to be installed.

Signed-off-by: Tom Rini <trini@konsulko.com>
2026-02-06 09:29:58 -06:00
Marek Vasut
109e378e9b cmd: zip: Add missing unmap_sysmem() for buffers in the unzip command
Unmap the sysmem that got mapped by this command.

Use symbolic return value for the command while updating
the return value handling.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2026-02-06 09:29:55 -06:00
Marek Vasut
3a76ba66ec cmd: zip: Use map_sysmem() with buffers in the zip command
The current implementation casts an address to a pointer. Make it more
sandbox-friendly by using map_sysmem().

Use symbolic return value for the command while updating
the return value handling.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2026-02-06 09:29:53 -06:00
Marek Vasut
f2c704c0e8 cmd: unzip: Use map_sysmem() with buffers in the gzwrite command
The current implementation casts an address to a pointer. Make it more
sandbox-friendly by using map_sysmem().

Convert 'addr' variable to unsigned long, as that is the return type of
hextoul() and address parameter type of map_sysmem().

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2026-02-06 09:29:50 -06:00
Marek Vasut
02ffe4a0c9 gunzip: Fix len parameter in function signature
The only call site of gzwrite() is cmd/unzip.c do_gzwrite(), where
the 'len' parameter passed to gzwrite(..., len, ...) function is of
type unsigned long. This usage is correct, the 'len' parameter is
an unsigned integer, and the gzwrite() function currently supports
input data 'len' of up to 4 GiB - 1 .

The function signature of gzwrite() function in both include/gzip.h
and lib/gunzip.c does however list 'len' as signed integer, which
is not correct, and ultimatelly limits the implementation to only
2 GiB input data 'len' .

Fix this, update gzwrite() function parameter 'len' data type to
size_t consistently in include/gzip.h and lib/gunzip.c .

Furthermore, update gzwrite() function 'szwritebuf' parameter in
lib/gunzip.c from 'unsigned long' to 'size_t' to be synchronized
with include/gzip.h . Rewrite the other parameters to size_t and
off_t and propagate the change too.

Since the gzwrite() function currently surely only supports input
data size of 4 GiB - 1, add input data size check. The limitation
comes from the current use of zlib z_stream .avail_in parameter,
to which the gzwrite() function sets the entire input data size,
and which is of unsigned int type, which cannot accept any number
beyond 4 GiB - 1. This limitation will be removed in future commit.

Reported-by: Yuya Hamamachi <yuya.hamamachi.sx@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2026-02-06 09:29:48 -06:00
Jamie Gibbons
2e6b5185bd configs: microchip_mpfs_generic: fix boot failure
Recent changes to device resource management (DEVRES) increased early
memory requirements during boot. The previous value was insufficient,
resulting in boot failures. Increase CONFIG_SYS_MALLOC_F_LEN to provide
enough early malloc pool for successful boot and device initialisation.

Signed-off-by: Jamie Gibbons <jamie.gibbons@microchip.com>
2026-02-06 09:27:42 -06:00
Anshul Dalal
3382d75f7a arch: arm: dts: k3: refactor common nodes to k3-*-r5.dtsi
This patch refactors the nodes in each board's R5 device-tree to common
SoC level dtsi. No functional change is intended from this patch.

Signed-off-by: Anshul Dalal <anshuld@ti.com>
Tested-by: Wadim Egorov <w.egorov@phytec.de>
Reviewed-by: Wadim Egorov <w.egorov@phytec.de>
Reviewed-by: Bryan Brattlof <bb@ti.com>
2026-02-06 09:26:13 -06:00
Vincent Stehlé
36e321b487 efi_net: add missing EFI_CALL in efi_net
The efi_reinstall_protocol_interface() function is a UEFI function;
make sure to call it from within U-Boot using the EFI_CALL() macro.

This fixes the following assertion:

  lib/efi_loader/efi_boottime.c:3752: efi_reinstall_protocol_interface: Assertion `__efi_entry_check()' failed.

To reproduce the issue, define LOG_DEBUG in lib/efi_loader/efi_boottime.c
and build u-boot for your platform. Then, boot the U-Boot helloworld.efi
application over the network. Example commands (adjust the URL and boot
entry number):

  => efidebug boot add -u 0 net http://10.0.2.2:8000/helloworld.efi
  => efidebug boot order 0
  => bootefi bootmgr

Fixes: dd5d82a599 ("efi_loader: efi_net: Add device path cache")
Signed-off-by: Vincent Stehlé <vincent.stehle@arm.com>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Cc: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Cc: Tom Rini <trini@konsulko.com>
Cc: Adriano Cordova <adrianox@gmail.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2026-02-06 10:04:30 +01:00
Tom Rini
4c289099b3 doc: develop/process: Clarify name usage in the Signed-off-by line
Long ago we took the Linux Kernel documentation about adding a
Signed-off-by line and adjusted it slightly for how we organized things.
In 2003 Linus clarified the intent and then re-worded what the name
portion of the Signed-off-by line can be. Mirror that change here.

Link: https://git.kernel.org/torvalds/c/d4563201f33a
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
2026-02-06 10:00:49 +01:00
Tom Rini
4a7f6e5bc1 doc: Remove pip from requirements.txt
Our documentation does not require the pip package to build, so it
should not be listed in our requirements.txt file here.

Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2026-02-06 09:59:33 +01:00
Vincent Stehlé
e94d0bd827 efi_loader: fix efi_debug_image_info_normal allocation
When adding a new EFI Debug Image Info entry, we allocate memory for a new
EFI Debug Image Info Normal structure and we add a new entry into the EFI
Debug Image Info Table, which is in fact just a pointer to the allocated
structure.

However, when allocating memory for the new structure we allocate memory
for the wrong type, leading to allocating memory for just a pointer instead
of the desired structure.

Fix the type used during allocation.

Fixes: 146546138a ("efi: add EFI_DEBUG_IMAGE_INFO for debug")
Signed-off-by: Vincent Stehlé <vincent.stehle@arm.com>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Cc: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Cc: Tom Rini <trini@konsulko.com>
Cc: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2026-02-06 09:57:00 +01:00
Pranav Tilak
32b835ccf3 efi_loader: Improve EFI variable load message
Change the EFI variable load message from log_err() to log_info() with
neutral wording. The previous "Failed to load" message caused customer
confusion as it appeared to indicate an error condition.

The efi_var_from_file() function deliberately returns EFI_SUCCESS in
this case to allow the boot process to continue normally. This is
documented in the function's comment block but was not reflected in
the log message level or content.

The message now uses informational wording to reflect that this is
normal behavior when the ubootefi.var file does not yet exist.

Signed-off-by: Pranav Tilak <pranav.vinaytilak@amd.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2026-02-06 09:56:45 +01:00
Vincent Stehlé
beec683454 efi_loader: fix use after free in efi_exit() with tcg2
The efi_exit() function frees the loaded image memory by calling
efi_delete_image(). However, when CONFIG_EFI_TCG2_PROTOCOL is enabled, the
image_obj->image_type structure member is accessed after the memory has
been freed.

Fix this by performing the tcg2 measurement before the image deletion.

Fixes: 8fc4e0b427 ("efi_loader: add boot variable measurement")
Suggested-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Vincent Stehlé <vincent.stehle@arm.com>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Masahisa Kojima <kojima.masahisa@socionext.com>
Acked-by: Masahisa Kojima <kojima.masahisa@socionext.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2026-02-06 09:32:32 +01:00
Heinrich Schuchardt
b5213bbfdc video: menu "TrueType Fonts" depends on TrueType enabled
The Kconfig menu "TrueType Fonts" should only be shown if TrueType is
enabled.

Put all TrueType dependent customization within one if statement.
Remove `depends TRUETYPE` clauses.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <simon.glass@canonical.com>
2026-02-04 10:41:48 -06:00
Tom Rini
5f0b0ad722 Merge patch series "arm: k3: j722s: add PCIe support"
George McCollister <george.mccollister@konsulko.com> says:

This patch series brings over several changes from Linux that are required
to get PCIe working on the j722s and also enables PCIe in
j722s_evm_a53_defconfig. This allows Linux to be booted from an NVMe drive.

The J722S SoC provides pcie0 (using pcie_cdns_ti) thru serdes1
(using phy-cadence-torrent) thru serdes_wiz1 (using phy-j721e-wiz). Changes
to the three drivers needed to be ported from Linux to enable the REFCLK
output which is used with this SoC. These changes should be tested on other
platforms using these drivers by those with the hardware available to make
sure no problems were introduced.

The PCIe controller in this SoC relies on the code performing the PCI scan
not scanning devices which cannot exist. In Linux this is implemented as
only_one_child() in probe.c. If this mechanism is not used, PCI config reads
for subsequent functions will return information for device 0 resulting in
U-Boot detecting 32 devices when only 1 is present. This change should be
tested on other platforms with PCI to ensure the same PCI devices are
enumerated before and after the patch is applied.

I would like to thank Opto 22 for sponsoring the initial development and
anyone that is able to contribute to testing of patches.

Link: https://lore.kernel.org/r/20260130153856.2049575-1-george.mccollister@konsulko.com
2026-02-04 10:40:37 -06:00
George McCollister
0cf1b43dbb configs: j722s_evm_a53_defconfig: enable PCIe
Enable PCIe now that it is fixed.

Signed-off-by: George McCollister <george.mccollister@konsulko.com>
Tested-by: Bryan Brattlof <bb@ti.com>
2026-02-04 10:40:28 -06:00
George McCollister
795b1fd2df pci: pcie_cdns_ti: Add PCIe support for J722S SoC
TI's J722S SoC has one instance of PCIe namely PCIe0 which is a Gen3
single lane PCIe controller. Add support for the "ti,j722s-pcie-host"
compatible specific to J722S SoC.

Based on:
https://lore.kernel.org/all/20240524092349.158443-1-s-vadapalli@ti.com/

Signed-off-by: George McCollister <george.mccollister@konsulko.com>
Tested-by: Bryan Brattlof <bb@ti.com>
2026-02-04 10:40:28 -06:00
George McCollister
3d07fe1390 pci: pcie_cdns_ti: Add support to provide refclk to PCIe connector
Add support to provide refclk to PCIe connector.

Based on: https://lore.kernel.org/r/20210308063550.6227-5-kishon@ti.com

Signed-off-by: George McCollister <george.mccollister@konsulko.com>
Tested-by: Bryan Brattlof <bb@ti.com>
2026-02-04 10:40:28 -06:00
George McCollister
88e3fcef7f phy: cadence-torrent: Add support to drive refclk out
cmn_refclk_<p/m> lines in Torrent SERDES are used for connecting an
external reference clock. cmn_refclk_<p/m> can also be configured to
output the reference clock. Model this derived reference clock as a
"clock" so that platforms like AM642 EVM can enable it.

This is used by PCIe to use the same refclk both in local SERDES
and remote device. Add support here to drive refclk out.

Based on: https://lore.kernel.org/all/20210310120840.16447-7-kishon@ti.com/

Signed-off-by: George McCollister <george.mccollister@konsulko.com>
Tested-by: Bryan Brattlof <bb@ti.com>
2026-02-04 10:40:28 -06:00
George McCollister
d7817a20c9 phy: ti: j721e-wiz: Enable reference clock output in cmn_refclk_<p/m>
cmn_refclk_<p/m> lines in Torrent SERDES are used for an connecting
external reference clock. cmn_refclk_<p/m> can also be configured to
output the reference clock. In order to drive the refclk out from the
SERDES (Cadence Torrent), PHY_EN_REFCLK should be set in SERDES_RST of
WIZ. Model PHY_EN_REFCLK as a clock, so that platforms like AM642 EVM
can enable it.

Based on: https://lore.kernel.org/r/20210310120840.16447-6-kishon@ti.com

Signed-off-by: George McCollister <george.mccollister@konsulko.com>
Tested-by: Bryan Brattlof <bb@ti.com>
2026-02-04 10:40:28 -06:00
George McCollister
fbde868ba4 pci: skip unnecessary PCIe scanning
Use the same mechanism as the Linux kernel to skip unnecessary (and in
the case of the J722S, errant) scanning of direct children of root
ports, downstream ports or bridges.

Based on Linux PCI code in the following files as of b927546677c8:
  drivers/pci/probe.c
  drivers/pci/pci.h
  include/linux/pci.h

Signed-off-by: George McCollister <george.mccollister@konsulko.com>
Tested-by: Bryan Brattlof <bb@ti.com>
2026-02-04 10:40:28 -06:00
Tom Rini
e7a21a985d Merge patch series "part: fix partition searching"
Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> says:

It was noted that a GPT partition with the maximum available partition
number (ex: /dev/mmcblk128) can't be read/write from U-Boot using
read/write commands. Futher investigation shows that the problem is
deeper.

This set of patches fixes uncovered issues.

Link: https://lore.kernel.org/r/20260119223305.3022690-1-mikhail.kshevetskiy@iopsys.eu
2026-02-04 10:31:02 -06:00
Mikhail Kshevetskiy
b06a1785b2 mtd: mtdpart: fix partitions searching
mtdpart internally enumerate partitions starting from zero, but partition
driver API enumerate partitions starting from 1, so wrong partition will
be queried. This is wrong.

Unnecessary debug message also was removed.

Fixes: c29a6daec1 ("disk: support MTD partitions")
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
2026-02-04 10:30:55 -06:00
Mikhail Kshevetskiy
6a1f8c8973 cmd: gpt: fix partition search boundaries
GPT disk partition with max available number (ex: /dev/mmcblk128) can't
be used from U-Boot. Here is an example:

  => mmc part

  Partition Map for mmc device 0  --   Partition Type: EFI

  Part	Start LBA	End LBA		Name
	Attributes
	Type GUID
	Partition GUID
  1	0x00001000	0x000013ff	"env1"
	attrs:	0x0000000000000000
	type:	0fc63daf-8483-4772-8e79-3d69d8477de4
	guid:	5452574f-2211-4433-5566-778899aabb02
  2	0x00001400	0x000017ff	"env2"
	attrs:	0x0000000000000000
	type:	0fc63daf-8483-4772-8e79-3d69d8477de4
	guid:	5452574f-2211-4433-5566-778899aabb03
  .................
  8	0x00158000	0x0034bfff	"apps"
	attrs:	0x0000000000000000
	type:	0fc63daf-8483-4772-8e79-3d69d8477de4
	guid:	5452574f-2211-4433-5566-778899aabb09
  128	0x00000420	0x00000fff	"fip"
	attrs:	0x0000000000000000
	type:	c12a7328-f81f-11d2-ba4b-00a0c93ec93b
	guid:	5452574f-2211-4433-5566-778899aabb01

  => gpt setenv mmc 0 fip
  error!
  => gpt setenv mmc 0 apps
  success!

The error is caused by invalid boundary checks. This patch fixes an
issue.

Fixes: 12fc1f3bb2 ("cmd: gpt: add eMMC and GPT support")
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Acked-by: Quentin Schulz <quentin.schulz@cherry.de>
2026-02-04 10:30:55 -06:00
Mikhail Kshevetskiy
0ced9ef073 disk: part: fix partition search boundaries
GPT disk partition with max available number (ex: /dev/mmcblk128) can't
be read/write from U-Boot using read/write command. Here is an example:

  => mmc part

  Partition Map for mmc device 0  --   Partition Type: EFI

  Part	Start LBA	End LBA		Name
	Attributes
	Type GUID
	Partition GUID
  1	0x00001000	0x000013ff	"env1"
	attrs:	0x0000000000000000
	type:	0fc63daf-8483-4772-8e79-3d69d8477de4
	guid:	5452574f-2211-4433-5566-778899aabb02
  2	0x00001400	0x000017ff	"env2"
	attrs:	0x0000000000000000
	type:	0fc63daf-8483-4772-8e79-3d69d8477de4
	guid:	5452574f-2211-4433-5566-778899aabb03
  .................
  8	0x00158000	0x0034bfff	"apps"
	attrs:	0x0000000000000000
	type:	0fc63daf-8483-4772-8e79-3d69d8477de4
	guid:	5452574f-2211-4433-5566-778899aabb09
  128	0x00000420	0x00000fff	"fip"
	attrs:	0x0000000000000000
	type:	c12a7328-f81f-11d2-ba4b-00a0c93ec93b
	guid:	5452574f-2211-4433-5566-778899aabb01

  => read mmc 0#fip ${loadaddr} 0 4
  Could not find "fip" partition
  ** Bad device specification mmc 0#fip **
  ** Bad device specification mmc 0#fip **
  Couldn't find partition mmc 0#fip

The error is caused by invalid boundary checks. This patch fixes an
issue.

Fixes: 43fd4bcefd ("disk: part: implement generic function part_get_info_by_uuid()")
Fixes: 56670d6fb8 ("disk: part: use common api to lookup part driver")
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Acked-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-By: Michael Trimarchi <michael@amarulasolutions.com>
2026-02-04 10:30:55 -06:00
Tom Rini
eb1562cc3e Merge tag 'net-20260204' of https://source.denx.de/u-boot/custodians/u-boot-net
Pull request net-20260204.

net:
- phy: aquantia: add support for Marvell CUX3410 10Gb PHY
- drivers: phy: fix code documentation typo udevice_ops

net-lwip:
- Command fixes and improvements (dhcp, dns, nfs)
- dhcp, tftp: do not write past end of buffer
- Add TFTPSERVERIP Kconfig option

misc:
- Update Jerome's email address
2026-02-04 08:05:24 -06:00
Andy Yan
1690228bac mtd: nand: raw: atmel: Access device ofnode through functions
According to commit 84a42ae366 ("dm: core: Rename device node to indicate it is private")

node_ should not be aaccess outside driver model.

Signed-off-by: Andy Yan <andyshrk@163.com>
2026-02-04 14:13:02 +02:00
Robert Marko
52be03bdf7 serial: atmel-usart: add support for skiping debug UART init
Currently, atmel-usart does not respect CONFIG_DEBUG_UART_SKIP_INIT so
it will always configure the debug UART.

However, this is unwanted on platforms on which TF-A or some other firmware
has already configured the debug UART.

This will be used for Microchip LAN969x support, so simply return early if
CONFIG_DEBUG_UART_SKIP_INIT is set.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
2026-02-04 14:12:56 +02:00
Robert Marko
a155dbc9f2 serial: atmel-usart: include arch specific headers only for AT91
Microchip LAN969x will not include any arch specific clk.h nor hardware.h,
so in order to support it only include <asm/arch/clk.h> and
<asm/arch/hardware.h> when AT91 is selected.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
2026-02-04 14:12:56 +02:00
Robert Marko
757a7cbb3e dm: platform_data: atmel_serial: fix build warning on 64-bit platforms
Pointer size cannot be assumed to be 32-bit, so use uintptr_t instead of
uint32_t.

Fixes the below build warning on 64-bit builds:
drivers/serial/atmel_usart.c: In function ‘atmel_serial_probe’:
drivers/serial/atmel_usart.c:275:23: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
  275 |         priv->usart = (atmel_usart3_t *)plat->base_addr;

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
2026-02-04 14:12:56 +02:00
Robert Marko
1bc75c2652 arm: at91: move atmel_serial.h to include/dm/platform_data
Move the arch specific atmel_serial.h header from AT91 to the generic
include/dm/platform_data.

This will be used for support on Microchip LAN969x.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
2026-02-04 14:12:56 +02:00
Weijie Gao
f0a1eb8a3d net: phy: aquantia: add support for Marvell CUX3410 10Gb PHY
The CUX3410 is similar to AQR113C. The main difference is CUX3410 does not
support MACSEC.

Signed-off-by: Bo-Cun Chen <bc-bocun.chen@mediatek.com>
2026-02-04 09:04:36 +01:00
Jonas Karlman
3349e3aa1b net: lwip: nfs: Prefer nfsserverip over serverip when set
Prefer use of a 'nfsserverip' env var before falling back to 'serverip'
when using the nfs command. Similar to how the 'tftpserverip' env var
is preferred over 'serverip' by the tftp command.

This also updates the error message to closer match the error message
used by the lwIP tftp command when a server ip is not set.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Jerome Forissier <jerome.forissier@arm.com>
2026-02-04 09:04:36 +01:00
Jonas Karlman
bd1f40a402 net: lwip: dhcp: Save DHCP siaddr field to tftpserverip env var
The DHCP siaddr field contains the IP address of next server to use in
bootstrap. Typically this will be the IP address of a TFTP server or the
IP address of the DHCP server itself.

RFC 2131, 2. Protocol Summary, Page 10:

   DHCP clarifies the interpretation of the 'siaddr' field as the
   address of the server to use in the next step of the client's
   bootstrap process.  A DHCP server may return its own address in the
   'siaddr' field, if the server is prepared to supply the next
   bootstrap service (e.g., delivery of an operating system executable
   image).  A DHCP server always returns its own address in the 'server
   identifier' option.

Set the 'tftpserverip' env variable when the siaddr field contains an
IP address that is different compared to the DHCP server IP address.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Jerome Forissier <jerome.forissier@arm.com>
2026-02-04 09:04:36 +01:00
Jonas Karlman
8d89b16ea4 net: lwip: Use ipaddr helpers
The ip_addr_t of lwIP has support for both IPv6 and IPv4 addresses.
Some lwIP commans is directly accessing the internal addr field of the
ip_addr_t instead of using ipaddr helper functions.

Change to use ipaddr helper functions where appropriate to remove direct
access of the internal addr field. Also change a few instances from ip4
to the version less ipaddr helpers.

There is no intended functional change, besides the change from using
ip4 addr helper to using version less ipaddr helper.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Jerome Forissier <jerome.forissier@arm.com>
2026-02-04 09:04:36 +01:00
Jonas Karlman
3299bffc7c net: lwip: dns: Call env_set() from dns loop instead of found callback
The lwIP dns command handle env_set() calls from the found callback and
printf() to console in the dns loop. Making it more complex than it
needs to be.

Simplify and ensure any environment variable that is being set is the
same value that would have been printed on console.

There should not be any intended change in behavior, besides the change
from using ip4addr helper to using version less ipaddr helper.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Jerome Forissier <jerome.forissier@arm.com>
2026-02-04 09:04:36 +01:00
Jonas Karlman
f3b600efb3 net: lwip: nfs: Print device name based on current udevice
Use udevice name, similar to other lwip commands, instead of using the
legacy eth_get_name() when printing out the device being used.

Fixes: 230cf3bc27 ("net: lwip: nfs: Port the NFS code to work with lwIP")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Jerome Forissier <jerome.forissier@arm.com>
2026-02-04 09:04:36 +01:00
Jonas Karlman
35ee795d63 net: lwip: dns: Fix print of resolved IP address
The lwIP dns command only prints out cached resolved IP addresses.

When a hostname is first resolved and ERR_INPROGRESS is returned the
dns command prints out 0.0.0.0 instead of the resolved IP address.

Fix this by printing out host_ipaddr instead of the temporary ipaddr
that only is valid when ERR_OK is returned.

Fixes: 1361d9f4f0 ("lwip: dns: do not print IP address when a variable is specified")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Jerome Forissier <jerome.forissier@arm.com>
2026-02-04 09:04:36 +01:00
Jonas Karlman
d93b3a38d5 net: lwip: add TFTPSERVERIP Kconfig option
With the legacy networking stack, it is possible to use USE_SERVERIP,
SERVERIP and BOOTP_PREFER_SERVERIP Kconfg options to force use of a
specific TFTP server ip.

Using the lwIP networking stack use of the 'tftpserverip' environment
variable provide the closest equivalent functionality.

Add USE_TFTPSERVERIP and TFTPSERVERIP Kconfig options that can be used
to add the 'tftpserverip' environment variable to force use of a
specific TFTP server ip.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Acked-by: Jerome Forissier <jerome.forissier@arm.com>
2026-02-04 09:04:36 +01:00
Andrew Goodbody
72d4e94b2e net: lwip: dhcp: Do not write past end of buffer
sprintf will write a trailing \0 at the end of the string so when
writing into a buffer, that buffer must be sized to allow for that
trailing zero. In the DHCP code when the index is a number needing two
digits to express the index would use up the two \0 bytes in the buffer
and the trailing \0 from sprintf would be beyond the end of the
allocation. Fix this by adding a third \0 in the buffer.

This was found by code inspection when looking for an issue reported by
Michal Simek, but I do not have the hardware to reproduce, so cannot
confirm if this addresses that issue or not.

Fixes: 98ad145db6 ("net: lwip: add DHCP support and dhcp commmand")
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@arm.com>
2026-02-04 09:04:36 +01:00
Andrew Goodbody
8df6b78746 net: lwip: tftp: Do not write past buffer end
sprintf will add a trailing \0 so manually adding a trailing \0 will
result in an extra unaccounted for character being written. This
overwrote the first byte of the following allocation block resulting in
unexpected behavior.

This was found by Running 'pxe get' with no available file resulting in
multiple attempts, using the default algorithm, to attempt to find a file.
Eventually there would be a failed assert when free() was called.
Failing the assert would result in a system reset.

Fixes: 27d7ccda94 ("net: lwip: tftp: add support of blksize option to client")
Reported-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com>

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Tested-by: Tom Rini <trini@konsulko.com> # Pine64+
Reviewed-by: Jerome Forissier <jerome.forissier@arm.com>
Reviewed-by: Jerome Forissier <jerome.forissier@arm.com>
2026-02-04 09:04:36 +01:00
Jerome Forissier
f2566c3a71 MAINTAINERS: update my email address
I will be using my Arm email address for all contributions. Update
MAINTAINERS and .mailmap accordingly.

Signed-off-by: Jerome Forissier <jerome.forissier@arm.com>
2026-02-04 09:04:36 +01:00
E Shattow
d3697faeb5 drivers: phy: fix code documentation typo udevice_ops
Amend code documentation referring to udevice_ops for struct phy_ops

Fixes: 72e5016f87 ("drivers: phy: add generic PHY framework")
Signed-off-by: E Shattow <e@freeshell.de>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
2026-02-04 09:01:30 +01:00
Tom Rini
3c72973b7a Merge branch 'u-boot-nand-03022026' of https://source.denx.de/u-boot/custodians/u-boot-nand-flash
CI: https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/pipelines/29183

This series provides a comprehensive cleanup of the Allwinner (sunxi)
NAND controller drivers and introduces full support for the H6 and H616
SoCs in both the main U-Boot driver and the SPL.

The series successfully deduplicates register maps between sunxi_nand.c
and sunxi_nand_spl.c while migrating to a capability-based architecture.
This approach allows the driver to handle the H616's specific
requirements—such as shifted register offsets for ECC/OOB, the removal
of 512B ECC block support, and mandatory MBUS clock gating—without
breaking compatibility for legacy A10/A23 devices.
2026-02-03 18:13:54 -06:00
Julien Masson
ede7198a37 board: mediatek: add MT8390 EVK board support
This adds support for the MT8390 EVK board with the following
features enabled/tested: Boot, UART, Watchdog and MMC.

MT8390 is based on MT8188.

Signed-off-by: Julien Masson <jmasson@baylibre.com>
Signed-off-by: Julien Stephan <jstephan@baylibre.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
2026-02-03 18:13:54 -06:00
Tom Rini
28a1ac87b8 Merge patch series "arm: dts: sc5xx: device tree updates and fixes"
Ozan Durgut <ozan.durgut@analog.com> says:

This series introduces updates for Analog Devices SC5xx boards.

It cleans up device trees by renaming GPIO expanders and removing
incorrect SPI flash definitions from the common include file.

For the SC598, this series updates the EZLITE board to the latest
Revision E hardware. It also adds missing GPIO hogs and enables
additional commands for the EZKIT configuration.

Link: https://lore.kernel.org/r/cover.1769439596.git.ozan.durgut@analog.com
2026-02-03 15:46:21 -06:00
Ozan Durgut
d047a99d08 arm: dts: sc598: update EZLITE to latest revision
Update the SC598 SOM EZLITE device tree to use the latest revision of
the System on Module (Rev E).

Signed-off-by: Ozan Durgut <ozan.durgut@analog.com>
Reviewed-by: Greg Malysa <malysagreg@gmail.com>
2026-02-03 15:45:58 -06:00
Ozan Durgut
9a49dcf6ab arm: dts: adi: rename GPIO expanders
The current naming convention for GPIO expanders across ADI SC5xx
device trees is inconsistent. This patch updates the node names to
correct indexing and clarify hardware location.

For SC573, SC584, and SC589 evaluation SBCs, switch to zero-based
indexing to align with standard conventions.

For SC594 and SC598 SoM + carrier evaluation kits, rename the nodes to
crr_gpio_expander. This prefix indicates which board the expander is on.

Signed-off-by: Ozan Durgut <ozan.durgut@analog.com>
Reviewed-by: Greg Malysa <malysagreg@gmail.com>
2026-02-03 15:45:58 -06:00
Philip Molloy
89a197e7e3 arm: dts: sc5xx: drop SPI flash from common dtsi
SPI flash devices are not common across all SC5xx boards. They
already defined in the SoM-specific dtsi files. Keeping the
definition in the common dtsi is therefore incorrect.

Fixes: c9e893d ("board: adi: Add support for SC598")
Signed-off-by: Philip Molloy <philip.molloy@analog.com>
Signed-off-by: Ozan Durgut <ozan.durgut@analog.com>
Reviewed-by: Greg Malysa <malysagreg@gmail.com>
2026-02-03 15:45:58 -06:00
Ozan Durgut
fb4a638931 arm: dts: sc598: add missing GPIO hogs for Rev D
Add missing GPIO hogs for UART0 enable, UART0 flow control,
SD Card and eMMC control signals.

Fixes: c9e893d ("board: adi: Add support for SC598")
Signed-off-by: Ozan Durgut <ozan.durgut@analog.com>
Reviewed-by: Greg Malysa <malysagreg@gmail.com>
2026-02-03 15:45:58 -06:00
Ozan Durgut
d9f1fcb304 configs: sc598-ezkit: enable additional commands
Enable FAT and GPT support, as well as mtd and wget commands

Signed-off-by: Ozan Durgut <ozan.durgut@analog.com>
Reviewed-by: Greg Malysa <malysagreg@gmail.com>
2026-02-03 15:45:58 -06:00
Tom Rini
1b0ac17ccf Merge patch series "toradex: aquila-am69: fix SPL USB DFU, drop obsolete clock"
Ernest Van Hoecke <ernest.vanhoecke@toradex.com> says:

This is a small, board-specific series for Aquila AM69.

Patch 1 fixes intermittent SPL USB DFU gadget enumeration.
Patch 2 drops a stale MCU_CLKOUT0 enable for ETH_1. V1.1 hardware uses
an external 25 MHz crystal, and support for earlier revisions was
already removed from the DT before upstreaming.

Link: https://lore.kernel.org/r/20260127101413.2812815-1-ernestvanhoecke@gmail.com
2026-02-03 15:45:09 -06:00
Ernest Van Hoecke
81cd740838 board: toradex: aquila-am69: Remove ETH_1 MCU_CLKOUT0
On the Toradex Aquila AM69 V1.1, the on-module ETH_1 relies on an
external 25 MHz crystal oscillator. On the V1.0, we needed to enable
MCU_CLKOUT0, but support for this was already dropped from the device
tree before being sent to U-Boot.

Remove this obsolete enabling of MCU_CLKOUT0.

Fixes: 3f0528882c ("board: toradex: add aquila am69 support")
Signed-off-by: Ernest Van Hoecke <ernest.vanhoecke@toradex.com>
Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com>
2026-02-03 15:45:05 -06:00
Ernest Van Hoecke
cdd51332cc arm: dts: k3-am69-aquila: Fix SPL USB DFU gadget failures
Around 1 in 20 times, the current R5 SPL fails to pull up the D+ line to
signal that a new USB device (the USB gadget used for downloading the
next stage) joined the bus.

With these strapping options, this is greatly reduced to 1 in thousands.

Link: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1587424/am69-u-boot-spl-usb-dfu-cdns3-occasionally-fails-to-pull-up-d-in-cdns3_gadget_config
Fixes: 3f0528882c ("board: toradex: add aquila am69 support")
Signed-off-by: Ernest Van Hoecke <ernest.vanhoecke@toradex.com>
Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com>
2026-02-03 15:45:05 -06:00
Richard Genoud
800ebf7e94 tools: sunxi-spl-image-builder: support H6/H616 NAND boot
The H6/H616 boot ROM doesn't expect a SPL scrambled the same way as
older SoCs.
It doesn't use a specific seeds table, it expects a maximized ECC
(BCH-80), a specific BBM (FF000301) and doesn't work if empty pages are
skipped (it needs its specific BBM, even in the padding).

So, add a --soc=h6 option to support H6/616 with:
- more ECC strengths
- specific BBM
- default_scrambler_seeds[] with all values
- no empty pages skip

In Kconfig, select BCH-80 by default for SUNXI_SPL_ECC_STRENGTH to make
BROM happy.

And in scripts/Makefile.xpl, use --soc=h6 option when building for a
SUN50I_GEN_H6 SoC.

Tested on Whatsminer H616 board, booting from NAND.

Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Co-developed-by: James Hilliard <james.hilliard1@gmail.com>
Signed-off-by: James Hilliard <james.hilliard1@gmail.com>
Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2026-02-03 21:45:27 +01:00
Richard Genoud
bd22b7e5d1 mtd: rawnand: sunxi: fix page size in control register
The MACRO NFC_PAGE_SHIFT(x) already deals with removing 10 from
nand->page_shift, so it shouldn't be done twice.

Fixes: 4ccae81cda ("mtd: nand: Add the sunxi NAND controller driver")

Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2026-02-03 21:45:25 +01:00
Richard Genoud
e41e5ae4b5 mtd: rawnand: sunxi_spl: Fix cast to pointer from integer warnings
Fix a cast to pointer from integer warning on ARM64

On 64bits platform, the casts done in {read,write}l() give that kind of
warnings:
drivers/mtd/nand/raw/sunxi_nand_spl.c: In function ‘check_value_inner’:
./arch/arm/include/asm/io.h:110:43: warning: cast to pointer from \
integer of different size [-Wint-to-pointer-cast]
  110 | #define __raw_readl(a) (*(volatile unsigned int *)(a))
      |                          ^
[...]
drivers/mtd/nand/raw/sunxi_nand_spl.c:81:27: note: in expansion of \
macro ‘readl’
   81 |                 int val = readl(offset) & expected_bits;

Introduce {read,write}l_nfc inline function to do the right cast and
push the base address (SUNXI_NFC_BASE) into those functions, making the
code more readable.

Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2026-02-03 21:45:21 +01:00
Richard Genoud
7d1de98011 mtd: rawnand: sunxi_spl: add support for H6/H616 nand controller
Introduce H6/H616 NAND controller support for SPL

The H616 NAND controller has the same base as A10/A23, with some
differences:
- MDMA is based on chained buffers
- its ECC supports up to 80bit per 1024bytes
- some registers layouts are a bit different, mainly due do the stronger
ECC.
- it uses USER_DATA_LEN registers along USER_DATA registers.
- it needs a specific clock for ECC and MBUS.

For SPL, most of the work was setting the clocks, adding the new
capability structure for H616 and supporting the new USER_DATA_LEN
registers.

Tested on Whatsminer H616 board (with and without scrambling, ECC)

Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2026-02-03 21:45:18 +01:00
Richard Genoud
f163da5e6d mtd: rawnand: sunxi: add support for H6/H616 nand controller
Introduce H6/H616 NAND controller support for U-Boot

The H616 NAND controller has the same base as A10/A23, with some
differences:
- MDMA is based on chained buffers
- its ECC supports up to 80bit per 1024bytes
- some registers layouts are a bit different, mainly due do the stronger
  ECC.
- it uses USER_DATA_LEN registers along USER_DATA registers.
- it needs a specific clock for ECC and MBUS.

Introduce the basic support, with ECC and scrambling, but without
DMA/MDMA.

Tested on Whatsminer H616 board (with and without scrambling, ECC)

Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2026-02-03 21:45:16 +01:00
Richard Genoud
4a611a82e5 clk: sunxi: Add MBUS Master Clock Gating Register
Add MBUS Master Clock Gating Register for H6 and H616

For H6/H616, the NAND controller needs the MBUS NAND clock along with
CLK_NAND0/1 and CLK_BUS_NAND.

The bit locations are from H6/H616 User Manuals.

Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2026-02-03 21:45:14 +01:00
Richard Genoud
25cbc335b4 sunxi: clock: H6: add NAND controller clock registers
Add missing NAND controller-related clock registers

The NAND controller on H6/H616 uses one clock for its internal logic
(NAND0_CLK) and one clock for ECC engine (NAND1_CLK) in addition to AHB
and MBUS clocks.

As NAND{0,1}_CLKs and MBUS_GATE are missing, add them.

The bit locations are from H616/H6 User Manual.

Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2026-02-03 21:45:11 +01:00
Richard Genoud
01c5b0ec50 mtd: rawnand: sunxi_spl: use NFC_ECC_MODE and NFC_RANDOM_SEED macros
Use generic macros for ECC_MODE and RANDOM_SEED

As H6/H616 registers are different, use more generic macros than hard
coded values specific to A10-like SoC.

No functional changes.

Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2026-02-03 21:45:09 +01:00
Richard Genoud
442eb06c92 mtd: rawnand: sunxi_spl: increase max_oobsize for 2KiB pages
Increase max_oobsize to take into account bigger OOB on 2KiB pages

Some NAND chip (e.g. Kioxia TC58NVG1S3HTA00) have a 2KiB page size +
128 bytes OOB.
In order to detect them, the max_oobsize has to be increased from 64 to
128 bytes.

Tested on Kioxia TC58NVG1S3HTA00 NAND chip on Whatsminer H616 board.

Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2026-02-03 21:45:06 +01:00
Richard Genoud
50b459973c mtd: rawnand: sunxi_spl: use NFC_ECC_ERR_MSK and NFC_ECC_PAT_FOUND
Use defines instead of hardcoded values for NFC_ECC_{ERR_MSK,PAT_FOUND}

SPL is using hard coded values for ECC error detection and empty chunk
detection.
The H6/H616 registers for that have changed, the pattern found is no
more in the NFC_REG_ECC_ST register.

So, don't presume anymore that pattern_found is in NFC_REG_ECC_ST, and
read the pattern_found register to get this information.

Apart from an additional register reading, no functional change.

Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2026-02-03 21:45:03 +01:00
Richard Genoud
0a80eb8146 mtd: rawnand: sunxi: introduce reg_spare_area in sunxi_nfc_caps
Introduce NDFC Spare Area Register offset in SoC capabilities

The H6/H616 spare area register is not at the same offset as the
A10/A23 one, so move its offset into sunxi_nfc_caps.

No functional change.

Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2026-02-03 21:45:00 +01:00
Richard Genoud
d46bdfe086 mtd: rawnand: sunxi: move NFC_RANDOM_EN register offset in SoC caps
NFC_RANDOM_{EN,DIRECTION} registers offset moved in H616

Let's make it a SoC capability.

NFC_RANDOM_DIRECTION also moved, but it's unused, just remove it.

No functional change.

Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2026-02-03 21:44:58 +01:00
Richard Genoud
0b0f13d503 mtd: rawnand: sunxi_spl: add per SoC capabilities
Introduce per SoC capabilities in sunxi_nand_spl.c

Prepare for the H616 support that has quite a lot of differences in
registers offset and capabilities.

Start with the 512 bytes ECC capability.

No functional change.

Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2026-02-03 21:44:56 +01:00
Richard Genoud
9edd503aad mtd: rawnand: sunxi: introduce reg_pat_id in sunxi_nfc_caps
Introduce NDFC Pattern ID Register in capability structure

The H6/H616 pattern ID register is not at the same offset as the
A10/A23 one, so move its offset into sunxi_nfc_caps.

No functional change.

Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2026-02-03 21:44:53 +01:00
Richard Genoud
b4c005d622 mtd: rawnand: sunxi: move NFC_ECC_MODE offset in SoC caps
NFC_ECC_MODE register offset moved in H616, so let's make it a SoC cap

No functional change.

Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2026-02-03 21:44:51 +01:00
Richard Genoud
f5178513a4 mtd: rawnand: sunxi: add has_ecc_block_512 capability
Introduce has_ecc_block_512 capability

The H616 controller can't handle 512 bytes ECC block size. The
NFC_ECC_BLOCK_512 bit disappeared in H6, and NDFC_RANDOM_EN took its
place.

So, add has_ecc_block_512 capability to only set this bit on SoC having
it.
On the way, let's drop NFC_ECC_BLOCK_SIZE_MSK which was just a mask for
the very same bit.

No functional change.

Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2026-02-03 21:44:48 +01:00
Richard Genoud
2e6852a841 mtd: rawnand: sunxi: move ECC_PAT_FOUND register in SoC caps
Move ECC_PAT_FOUND register in SoC capabilities structure

This register offset moved in H616, it's now its own register (@0x3c,
bits 0-31), not shared with NFC_ECC_ST any more (was @0x38 bits 16-31).
Push that specificity in caps structure.

Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2026-02-03 21:44:46 +01:00
Richard Genoud
eb66861acc mtd: rawnand: sunxi: move USER_DATA register offset in SoC caps
USER_DATA register offset moved in H616, so let's make it a SoC cap

Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2026-02-03 21:44:44 +01:00
Richard Genoud
6124050e53 mtd: rawnand: sunxi: move ECC_ERR_CNT register offset in SoC caps
ECC_ERR_CNT register offset moved in H616, so let's make it a SoC cap

Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2026-02-03 21:44:41 +01:00
Richard Genoud
bd9944c74f mtd: rawnand: sunxi: add per SoC capabilities
Introduce per SoC capabilities in sunxi_nand.c

This prepares for the H616 support that has quite a lot differences in
registers offset and capabilities.

Start with the ECC strength table.

No functional change.

Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2026-02-03 21:44:39 +01:00
Richard Genoud
dadf8a8dec mtd: rawnand: sunxi: merge register definitions for sunxi_nand{, _spl}.c
Merge common register definitions from sunxi_nand{,_spl}.c

The Allwinner NAND controller registers where in both files, so let's
just merge all that in a header, it will be easier for maintenance.

NB: the defines are also harmonized with Linux driver

No functional change

Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2026-02-03 21:44:37 +01:00
Richard Genoud
8034c41d63 mtd: rawnand: sunxi: remove usage of struct sunxi_ccm_reg
The sunxi_ccm_reg is legacy, drop its usage from nand related code

For that, CCU_NAND0_CLK_CFG and CCU_AHB_GATE1 are added to the clock
files when missing.
And clock code in sunxi_nand{,_spl}.c and board.c are changed to use the
new scheme.

Moreover, drop AHB_DIV_1 in favor of the more readable CCM_NAND_CTRL_M/N

Suggested-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2026-02-03 21:44:33 +01:00
Richard Genoud
46d5ef0416 mtd: rawnand: sunxi_spl: cosmetic: use definitions from linux/mtd/rawnand.h
Remove unneeded definitions NFC_CMD_R* in sunxi_nand_spl.c

No need to define NFC_CMD_RNDOUTSTART, NFC_CMD_RNDOUT and
NFC_CMD_READSTART here since they are already in linux/mtd/rawnand.h

Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2026-02-03 21:44:30 +01:00
Richard Genoud
322470fe73 mtd: rawnand: sunxi_spl: harmonize register defines with non spl file
Harmonize registers definition in sunxi_nand{,_spl}.c files

This is a first step to then include the same file from both
sunxi_nand{,_spl}.c files

Unused defines are also removed

Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2026-02-03 21:44:28 +01:00
Richard Genoud
79afb70a93 mtd: rawnand: sunxi_spl: fix pointer from integer without a cast
Fix pointer from interget warning when compiling for ARM64

When compiling for arm64, we get this error:
error: passing argument 2 of ‘__memcpy_fromio’ makes pointer from
			integer without a cast [-Wint-conversion]

Moreover the copy should be made with dedicated readl(), like for any
register access on this peripheral, since they are 32bit wide.

So, instead of memcpy_fromio(), just use a readl() loop.
Introduce nand_readlcpy() to implement this loop.

Fixes: 6ddbb1e936 ("spl: nand: sunxi: use PIO instead of DMA")
Suggested-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2026-02-03 21:44:25 +01:00
Richard Genoud
0eb8de350e mtd: rawnand: sunxi: cosmetic: remove needless comment
Remove 'complete' member from struct sunxi_nfc

The 'complete' member isn't part of the structure, let's remove it.

Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2026-02-03 21:44:18 +01:00
Patrick Rudolph
a8d982e1f1 x86: cpu: Fix crash on FTRACE enabled builds
When compiled with FTRACE=1 U-boot will crash as %rdi is clobbered
in board_init_f_alloc_reserve() and board_init_f_init_reserve() will
memset the .text segment instead of the global_data struct.

According to the System V AMD64 ABI %rdi is not preserved and the
existing code only worked as board_init_f_alloc_reserve() was small
enough to not use %rdi.

Fix that by always passing the correct argument to
board_init_f_init_reserve().

TEST=Can boot on qemu-q35 with FTRACE=1 enabled during build.

Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2026-02-03 12:51:43 -06:00
Guillaume Ranquet
0cb8a88e7a x86: boot: fix unreachable else branch in boot_prep_linux
The else if branch uses the is_zimage boolean which is initialized to 0
and never set before being tested here.

remove the test on is_zimage to make this code reachable.

Signed-off-by: Guillaume Ranquet <ranquet.guillaume@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2026-02-03 12:51:40 -06:00
Shiji Yang
80a3572f9b mips: mtmips: add CPU reset support for MT7628
Allow the system to reset the CPU without calling the reset
controller. This patch also removed the default SYSRESET controller
for MT7628, as it is now optional.

Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
2026-02-03 12:51:37 -06:00
Shiji Yang
00618f7212 mips: mtmips: do not select PINCONF Kconfig symbol for MT7620
Mediatek MT7620 u-boot does not have PINCONF implementation.

Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
2026-02-03 12:51:34 -06:00
Eric Schikschneit
a22a4fbe43 x86: Fix TCPA bloblist size
Excessive default value causes crash on hardware: x86 baytrail E3845

It is unclear where the data is being populated being 'BLOBLISTT_TCPA_LOG'
is not found elsewhere in the u-boot tree. This leads to confusion about
how much space for TPM log is actually needed.

This was tested on hardware using TPMv1.

Signed-off-by: Eric Schikschneit <eric.schikschneit@novatechautomation.com>
2026-02-03 12:51:31 -06:00
Tom Rini
71f2564b17 Merge tag 'mmc-for-2026.04-rc2' of https://source.denx.de/u-boot/custodians/u-boot-mmc
- Add DMA support for mediatek mmc
- Cleanup mmc cmd
- Fix typos in mmc

[trini: Fix "quoted string split across lines" checkpatch warning]
Signed-off-by: Tom Rini <trini@konsulko.com>
2026-02-03 12:46:30 -06:00
Sughosh Ganu
b3d5e06b4b mailmap: Update email address for Sughosh
My Linaro email address is no longer valid. Update entries in the
MAINTAINERS file, and add a mapping in the mailmap file.

Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com>
2026-02-03 12:45:02 -06:00
Yao Zi
b4f0479e07 cmd: mmc: Return symbolic value when part switching fails in mmc dev
Return symbolic value CMD_RET_FAILURE instead of literal "1" when
failing to switch the partition to improve readability.

Signed-off-by: Yao Zi <me@ziyao.cc>
Tested-by: Anshul Dalal <anshuld@ti.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-02-03 22:11:46 +08:00
Yao Zi
f955e00e42 cmd: mmc: Check whether arguments are valid numbers in dev subcommand
Currently when any of speed_mode, part, or dev fails to be parse as a
number, no error is reported. In this case __init_mmc_device() is called
with weird arguments, probably zeroes if there's no digit prefixing the
argument, which is especially confusing when the invocation occasionally
succeeds.

Let's check whether arguments are valid numbers without trailing
characters. This is quite helpful for speed_mode: it requires an index
instead of a mode name, one may easily pass in a string, which will be
parsed as zero (MMC_LEGACY), without carefully reading the
documentation, then finds the MMC device is under an unexpected mode.

Signed-off-by: Yao Zi <me@ziyao.cc>
Tested-by: Anshul Dalal <anshuld@ti.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-02-03 22:11:45 +08:00
Yao Zi
97cc26f6b6 cmd: mmc: Simplify dev subcommand handling
Replace the big if-else block in do_mmc_dev() with switch-case and use
fallthrough to remove the duplicated code for parsing dev and part.

Signed-off-by: Yao Zi <me@ziyao.cc>
Tested-by: Anshul Dalal <anshuld@ti.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-02-03 22:11:45 +08:00
Tanmay Kathpalia
7f9e9b5033 mmc: Fix typos in comments and debug messages
Fix the following typos in drivers/mmc/mmc.c:
- "neiter" -> "neither" in __mmc_switch() comment
- "witdh" -> "width" in bus_width() warning message
- "enver" -> "never" in mmc_select_mode_and_width() comment

Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@altera.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-02-03 22:11:05 +08:00
ht.lin
9652f2591d mmc: mediatek: add DMA mode support
Implement DMA support in the MediaTek MMC driver to enhance data
transfer speed.

- Define DMA control and configuration registers
- Implement functions for starting, stopping, and completing DMA
  transfers
- Modify data transfer logic to utilize DMA when enabled
- Ensure proper cache management during DMA operations

Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
Signed-off-by: ht.lin <ht.lin@mediatek.com>
Signed-off-by: Julien Masson <jmasson@baylibre.com>
Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
Signed-off-by: David Lechner <dlechner@baylibre.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-02-03 22:10:14 +08:00
David Lechner
aa38b17810 mmc: mtk-sd: fix misaligned brace
Indent a brace for proper code style.

Signed-off-by: David Lechner <dlechner@baylibre.com>
Reviewed-by: Macpaul Lin <macpaul.lin@mediatek.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-02-03 22:10:14 +08:00
David Lechner
fe62fd3b8b mmc: mtk-sd: use GENMASK and FIELD macros
Replace separate mask and shift definitions with GENMASK and FIELD_*
macros for better readability and maintainability.

All macros ending in _M have the suffix dropped. The value remains the
same but is now generated with GENMASK. All macros ending in _S are
removed and their uses replaced with FIELD_PREP and FIELD_GET macros.

Signed-off-by: David Lechner <dlechner@baylibre.com>
Reviewed-by: Macpaul Lin <macpaul.lin@mediatek.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-02-03 22:10:13 +08:00
Andrew Goodbody
548e9a254c video: nexell: unsigned parameter cannot be negative
The parameter 'alpha' is declared as an unsigned type so cannot be
negative. The code to test it as being less than zero will always fail
and so is redundant and should be removed.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Stefan Bosch <stefan_b@posteo.net>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2026-02-03 10:42:03 +09:00
Tom Rini
1de103fc29 Merge patch series "m68k: Add support for QEMU virt machine"
Kuan-Wei Chiu <visitorckw@gmail.com> says:

Add support for the QEMU 'virt' machine on the m68k architecture. The
QEMU virt machine models a generic system utilizing Goldfish virtual
peripherals and is capable of emulating various classic 68k CPUs.

Currently, U-Boot's m68k architecture support focuses on ColdFire
variants. This series expands support to include the classic M680x0
architecture, implementing the necessary exception vectors, startup
code, and a bootinfo parser compatible with the QEMU interface.

Drivers for Goldfish peripherals (TTY, Timer, RTC) and the QEMU
Virtual System Controller (sysreset) are also added to enable serial
console, timekeeping, and system reset functionality.

The implementation has been verified on QEMU targeting the M68040 CPU,
confirming successful hardware initialization and boot to the U-Boot
command shell. Additionally, the CI configuration was verified locally
using gitlab-ci-local "qemu_m68k_virt test.py", resulting in
PASS qemu_m68k_virt test.py.

Link: https://lore.kernel.org/r/20260107201838.3448806-1-visitorckw@gmail.com
[trini: Re-sort MAINTAINERS entries]
Signed-off-by: Tom Rini <trini@konsulko.com>
2026-02-02 14:25:48 -06:00
Kuan-Wei Chiu
838e3be9e1 MAINTAINERS: Update m68k entry
Rename the "COLDFIRE" entry to "M68K" to reflect that the architecture
support now encompasses traditional m680x0 CPUs (e.g., M68040) in
addition to ColdFire platforms.

Remove Huan Wang from the maintainers list as she is no longer active,
as suggested by Angelo Dureghello.

Add myself as a co-maintainer to assist with reviewing and testing
m68k-related patches.

Signed-off-by: Kuan-Wei Chiu <visitorckw@gmail.com>
Acked-by: Angelo Dureghello <angelo@kernel-space.org>
2026-02-02 14:24:41 -06:00
Kuan-Wei Chiu
b21d9acdff CI: Add test jobs for QEMU m68k virt machine
Enable CI testing for the newly introduced QEMU m68k 'virt' board on
both GitLab CI and Azure Pipelines. This ensures the new M68040
architecture support is built and booted correctly in the emulated
environment.

Signed-off-by: Kuan-Wei Chiu <visitorckw@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <simon.glass@canonical.com>
2026-02-02 14:24:41 -06:00
Kuan-Wei Chiu
516afc8f76 board: Add QEMU m68k virt board support
Add support for the QEMU 'virt' machine on the m68k architecture. This
board emulates a generic machine based on the Motorola 68040 CPU
equipped with Goldfish virtual peripherals.

Introduce the necessary board configuration and initialization
infrastructure. The implementation includes logic to parse the QEMU
bootinfo interface, enabling dynamic detection of system RAM size to
adapt to the virtual machine's configuration.

Enable the Goldfish TTY driver for serial console output. Additionally,
enable Goldfish RTC and timer drivers to support real-time clock
functionality and nanosecond-resolution delays. Include comprehensive
documentation covering build instructions and usage examples.

Signed-off-by: Kuan-Wei Chiu <visitorckw@gmail.com>
Tested-by: Daniel Palmer <daniel@0x0f.com>
Reviewed-by: Simon Glass <simon.glass@canonical.com>
2026-02-02 14:24:41 -06:00
Kuan-Wei Chiu
c69b6aeaa3 m68k: Add support for M68040 CPU
Add support for the Motorola 68040 architecture. Currently, m68k
support in U-Boot is primarily focused on ColdFire variants. Introduce
the necessary infrastructure to support the classic M680x0 series,
specifically targeting the M68040 as emulated by QEMU.

The implementation includes exception vectors, early startup code, and
minimal CPU initialization and relocation stubs. It also defines the
standard m68k boot information structure used for passing hardware
information to the operating system. To ensure compatibility, ColdFire-
specific library objects such as cache and interrupt handling are
excluded from the build when M68040 is selected.

Additionally, apply a specific workaround during the early memory
reservation stage. Use a manual loop to clear global data instead of
the standard memset() function, as utilizing memset() at this point was
observed to cause a hang on the QEMU platform.

Signed-off-by: Kuan-Wei Chiu <visitorckw@gmail.com>
Acked-by: Angelo Dureghello <angelo@kernel-space.org>
Reviewed-by: Simon Glass <simon.glass@canonical.com>
2026-02-02 14:24:41 -06:00
Kuan-Wei Chiu
0429298a1a sysreset: Add QEMU virtual system controller driver
Introduce a new sysreset driver for the QEMU Virtual System Controller.
This device is found on QEMU "virt" machines (such as the m68k virt
target) and provides a mechanism to trigger system reset and power-off
events.

The driver maps U-Boot sysreset types to the corresponding controller
commands:
- SYSRESET_WARM / SYSRESET_COLD -> VIRT_CTRL_CMD_RESET
- SYSRESET_POWER_OFF -> VIRT_CTRL_CMD_HALT

Signed-off-by: Kuan-Wei Chiu <visitorckw@gmail.com>
Reviewed-by: Simon Glass <simon.glass@canonical.com>
2026-02-02 14:24:40 -06:00
Kuan-Wei Chiu
b41c54488f rtc: goldfish: Support platform data for non-DT probing
Currently, the Goldfish RTC driver exclusively relies on device tree
to retrieve the base address, failing immediately if dev_read_addr()
returns FDT_ADDR_T_NONE. This restriction prevents the driver from
being used on platforms that instantiate devices via U_BOOT_DRVINFO()
instead of device tree, such as the QEMU m68k virt machine.

Add support for platform data to address this limitation. Introduce a
new .of_to_plat hook to handle device tree parsing and populate the
platform data. Update the probe function to rely exclusively on this
platform data, enabling support for both Device Tree and manual
instantiation.

Introduce a new header file include/goldfish_rtc.h to define the
platform data structure.

Signed-off-by: Kuan-Wei Chiu <visitorckw@gmail.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2026-02-02 14:24:40 -06:00
Kuan-Wei Chiu
909f717eaf timer: Add Goldfish timer driver
Add support for the Goldfish timer driver. This driver utilizes the
Goldfish RTC hardware to provide a nanosecond-resolution timer. This
virtual device is commonly found in QEMU virtual machines (such as the
m68k virt machine) and Android emulators.

The driver implements the standard U-Boot timer UCLASS interface,
exposing a 64-bit monotonically increasing counter with a 1GHz clock
rate derived from the RTC registers.

Signed-off-by: Kuan-Wei Chiu <visitorckw@gmail.com>
Tested-by: Daniel Palmer <daniel@0x0f.com>
Reviewed-by: Yao Zi <me@ziyao.cc>
Reviewed-by: Simon Glass <simon.glass@canonical.com>
Reviewed-by: Angelo Dureghello <angelo@kernel-space.org>
2026-02-02 14:24:40 -06:00
Kuan-Wei Chiu
bf55b84736 serial: Add Goldfish TTY driver
Add support for the Google Goldfish TTY serial device. This virtual
device is commonly used in QEMU virtual machines (such as the m68k
virt machine) and Android emulators.

The driver implements basic console output and input polling using the
Goldfish MMIO interface.

Signed-off-by: Kuan-Wei Chiu <visitorckw@gmail.com>
Reviewed-by: Yao Zi <me@ziyao.cc>
Tested-by: Daniel Palmer <daniel@0x0f.com>
Acked-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <simon.glass@canonical.com>
Acked-by: Angelo Dureghello <angelo@kernel-space.org>
2026-02-02 14:24:40 -06:00
Andrew Goodbody
de6b405e61 video: exynos: node variable should not be unsigned
THe variable 'node' is assigned a value of an int, tested for being less
than or equal to zero then passed as an argument to a function that
takes an int so 'node' should not be unsigned. Fix it.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2026-02-02 18:58:44 +09:00
Kaustabh Chakraborty
3f2ab427c1 ARM: dts: add dtsi for exynos7870-on7xelte (Samsung Galaxy J7 Prime)
Add a framebuffer node to the DTSI in order to ensure that display
continues to work, as since v6.19 of devicetree-rebasing sources, it
uses Samsung's DECON (Display Enhancement CONtroller) for display, which
is, as of yet, not supported in U-Boot.

Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2026-02-02 17:06:42 +09:00
Kaustabh Chakraborty
5689cc9c6f ARM: dts: add dtsi for exynos7870-j6lte (Samsung Galaxy J6)
Add a framebuffer node to the DTSI in order to ensure that display
continues to work, as since v6.19 of devicetree-rebasing sources, it
uses Samsung's DECON (Display Enhancement CONtroller) for display, which
is, as of yet, not supported in U-Boot.

Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2026-02-02 17:06:42 +09:00
Kaustabh Chakraborty
1ad1330664 ARM: dts: add dtsi for exynos7870-a2corelte (Samsung Galaxy A2 Core)
Add a framebuffer node to the DTSI in order to ensure that display
continues to work, as since v6.19 of devicetree-rebasing sources, it
uses Samsung's DECON (Display Enhancement CONtroller) for display, which
is, as of yet, not supported in U-Boot.

Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2026-02-02 17:06:42 +09:00
Jonas Karlman
e69841fa71 usb: gadget: dwc2: Move dr_mode check from of_to_plat() to bind()
Rockchip RK3288 and RK3506 contain two DWC2 USB controllers, typically
one controller use dr_mode=otg and the other one use dr_mode=host.

With USB_GADGET_DWC2_OTG, DM_USB_GADGET and USB_DWC2 enabled this result
in the dwc2-udc-otg driver binding to both controllers, however only one
will probe due to use of dr_mode=host on the other one.

After the commit 6668b8e7cc ("dm: core: Support multiple drivers with
same compatibles") it is possible to bind one controller to the
dwc2-udc-otg driver and the other one to the dwc2_usb driver.

Move the dr_mode check from of_to_plat() to bind() to allow dm core to
bind the dwc2 host driver to dr_mode=host controllers.

Before this:

  => dm tree
   ...
   usb_gadget    0  [   ]   dwc2-udc-otg          |   |-- usb@ff740000
   usb_gadget    1  [   ]   dwc2-udc-otg          |   |-- usb@ff780000

  => usb start
  starting USB...
  No USB controllers found

After this:

  dwc2-udc-otg usb@ff780000: Invalid dr_mode 1

  => dm tree
   ...
   usb_gadget    0  [   ]   dwc2-udc-otg          |   |-- usb@ff740000
   usb           0  [   ]   dwc2_usb              |   |-- usb@ff780000

  => usb start
  starting USB...
  USB DWC2
  Bus usb@ff780000: 1 USB Device(s) found

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Reviewed-by: Marek Vasut <marek.vasut@mailbox.org>
Link: https://lore.kernel.org/r/20260129195207.2260264-1-jonas@kwiboo.se
Signed-off-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
2026-01-30 09:01:42 +01:00
Chris Morgan
aef270254f usb: dwc3: core: improve reset sequence
According to Synopsys Databook, we shouldn't be
relying on GCTL.CORESOFTRESET bit as that's only for
debugging purposes. Instead, let's use DCTL.CSFTRST
if we're OTG or PERIPHERAL mode.

Host side block will be reset by XHCI driver if
necessary. Note that this reduces amount of time
spent on dwc3_probe() by a long margin.

We're still gonna wait for reset to finish for a
long time (default to 1ms max), but tests show that
the reset polling loop executed at most 19 times
(modprobe dwc3 && modprobe -r dwc3 executed 1000
times in a row).

Note that this patch was submitted to Linux in 2016 [1], however I can
confirm it is needed to support gadget mode in U-Boot on my device.
While I am referencing this patch from Linux I am in fact taking the
full existing dwc3_core_soft_reset() function from Linux as it exists
in v6.19-rc5, so it may differ slightly from the information in the
2016 patch.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/patch/drivers/usb/dwc3?id=f59dcab176293b646e1358144c93c58c3cda2813

Suggested-by: Mian Yousaf Kaukab <yousaf.kaukab@intel.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Link: https://lore.kernel.org/r/20260115230135.183158-5-macroalpha82@gmail.com
Signed-off-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
2026-01-30 08:59:21 +01:00
Chris Morgan
de69f14a09 usb: dwc3: gadget: Don't send unintended link state change
DCTL.ULSTCHNGREQ is a write-only field. When doing a read-modify-write
to DCTL, the driver must make sure that there's no unintended link state
change request from whatever is read from DCTL.ULSTCHNGREQ. Set link
state change to no-action when the driver writes to DCTL.

Note that this patch was submitted upstream in Linux in 2020 [1],
and I've confirmed I need it in U-Boot to enable gadget mode.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/patch/drivers/usb/dwc3?id=5b738211fb59e114727381d07c647a77c0010996

Signed-off-by: Thinh Nguyen <thinhn@synopsys.com>
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Link: https://lore.kernel.org/r/20260115230135.183158-4-macroalpha82@gmail.com
Signed-off-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
2026-01-30 08:59:21 +01:00
Chris Morgan
7590f29e2c usb: dwc3: Increase DWC3 controller halt timeout
Since EP0 transactions need to be completed before the controller halt
sequence is finished, this may take some time depending on the host and the
enabled functions.  Increase the controller halt timeout, so that we give
the controller sufficient time to handle EP0 transfers.

This patch was originally submitted to Linux in 2022, but is required to
use USB gadget mode on my device in U-Boot.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=461ee467507cb98a348fa91ff8460908bb0ea423

Signed-off-by: Wesley Cheng <quic_wcheng@quicinc.com>
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Link: https://lore.kernel.org/r/20260115230135.183158-3-macroalpha82@gmail.com
Signed-off-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
2026-01-30 08:59:21 +01:00
Chris Morgan
add7152eb0 usb: dwc3: core: Add ip and version_type support from Linux
Add support for the ip and version_type fields from the Linux
version of the dwc3 driver. Included in this is support for a
few additional macros in the header from Linux as well.

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Link: https://lore.kernel.org/r/20260115230135.183158-2-macroalpha82@gmail.com
Signed-off-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
2026-01-30 08:59:21 +01:00
567 changed files with 9982 additions and 4521 deletions

View File

@@ -524,6 +524,9 @@ stages:
TEST_PY_ID: "--id qemu"
TEST_PY_TEST_SPEC: "not sleep and not efi"
OVERRIDE: "-a CONFIG_M68K_QEMU=y -a ~CONFIG_MCFTMR"
qemu_m68k_virt:
TEST_PY_BD: "qemu-m68k"
TEST_PY_TEST_SPEC: "not sleep"
qemu_malta:
TEST_PY_BD: "malta"
TEST_PY_ID: "--id qemu"

View File

@@ -421,6 +421,12 @@ qemu_m68k test.py:
OVERRIDE: "-a CONFIG_M68K_QEMU=y -a ~CONFIG_MCFTMR"
<<: *buildman_and_testpy_dfn
qemu_m68k_virt test.py:
variables:
TEST_PY_BD: "qemu-m68k"
TEST_PY_TEST_SPEC: "not sleep"
<<: *buildman_and_testpy_dfn
qemu_malta test.py:
variables:
TEST_PY_BD: "malta"
@@ -789,5 +795,5 @@ vf2:
qemu-x86_64:
variables:
ROLE: qemu-x86_64
TEST_PY_TEST_SPEC: "and not sleep"
TEST_PY_TEST_SPEC: "not sleep"
<<: *sjg_lab_dfn

View File

@@ -69,7 +69,8 @@ Jagan Teki <jagannadha.sutradharudu-teki@xilinx.com>
Jakob Unterwurzacher <jakob.unterwurzacher@cherry.de> <jakob.unterwurzacher@theobroma-systems.com>
Jay Buddhabhatti <jay.buddhabhatti@amd.com> <jay.buddhabhatti@xilinx.com>
Jernej Skrabec <jernej.skrabec@gmail.com> <jernej.skrabec@siol.net>
Jerome Forissier <jerome@forissier.org> <jerome.forissier@linaro.org>
Jerome Forissier <jerome.forissier@arm.com> <jerome@forissier.org>
Jerome Forissier <jerome.forissier@arm.com> <jerome.forissier@linaro.org>
John Linn <john.linn@amd.com> <john.linn@xilinx.com>
Jyotheeswar Reddy Mutthareddyvari <jyotheeswar.reddy.mutthareddyvari@amd.com> <jyothee@xilinx.com>
Jyotheeswar Reddy Mutthareddyvari <jyotheeswar.reddy.mutthareddyvari@amd.com> <jyotheeswar.reddy.mutthareddyvari@xilinx.com>
@@ -140,6 +141,7 @@ Srinivas Neeli <srinivas.neeli@amd.com> <srinivas.neeli@xilinx.com>
Stefan Roese <stefan.roese@mailbox.org> <stroese>
Stefano Babic <sbabic@nabladev.com>
Stefano Stabellini <stefano.stabellini@amd.com> <stefano.stabellini@xilinx.com>
Sughosh Ganu <sughosh.ganu@arm.com> <sughosh.ganu@linaro.org>
No generic patch CC mail please <noreply@example.com> <swarren@wwwdotorg.org>
No generic patch CC mail please <noreply@example.com> <swarren@nvidia.com>
Sumit Garg <sumit.garg@kernel.org> <sumit.garg@linaro.org>

View File

@@ -626,15 +626,12 @@ S: Supported
F: arch/arm/dts/am335x-sancloud*
ARM SC5XX
M: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
M: Greg Malysa <malysagreg@gmail.com>
M: Ian Roberts <ian.roberts@timesys.com>
M: Vasileios Bimpikas <vasileios.bimpikas@analog.com>
M: Utsav Agarwal <utsav.agarwal@analog.com>
M: Arturs Artamonovs <arturs.artamonovs@analog.com>
L: adsp-linux@analog.com
L: linux@analog.com
S: Supported
T: git https://github.com/analogdevicesinc/lnxdsp-u-boot
T: git https://github.com/analogdevicesinc/u-boot
F: arch/arm/dts/sc5*
F: arch/arm/include/asm/arch-adi/
F: arch/arm/mach-sc5xx/
@@ -751,7 +748,6 @@ N: stm
N: stm32
ARM SUNXI
M: Jagan Teki <jagan@amarulasolutions.com>
M: Andre Przywara <andre.przywara@arm.com>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-sunxi.git
@@ -1048,15 +1044,6 @@ T: git https://source.denx.de/u-boot/custodians/u-boot-clk.git
F: drivers/clk/
F: drivers/clk/imx/
COLDFIRE
M: Huan Wang <alison.wang@nxp.com>
M: Angelo Dureghello <angelo@kernel-space.org>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-coldfire.git
F: arch/m68k/
F: doc/arch/m68k.rst
F: drivers/watchdog/mcf_wdt.c
CPU
M: Simon Glass <sjg@chromium.org>
M: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
@@ -1156,8 +1143,7 @@ F: tools/file2include.c
F: tools/mkeficapsule.c
ENVIRONMENT
M: Joe Hershberger <joe.hershberger@ni.com>
S: Maintained
S: Orphaned
F: env/
F: include/env/
F: include/env*
@@ -1250,7 +1236,7 @@ F: drivers/watchdog/sp805_wdt.c
F: drivers/watchdog/sbsa_gwdt.c
FWU Multi Bank Update
M: Sughosh Ganu <sughosh.ganu@linaro.org>
M: Sughosh Ganu <sughosh.ganu@arm.com>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-efi.git
F: lib/fwu_updates/*
@@ -1263,6 +1249,18 @@ S: Maintained
F: drivers/misc/gsc.c
F: include/gsc.h
GOLDFISH SERIAL DRIVER
M: Kuan-Wei Chiu <visitorckw@gmail.com>
S: Maintained
F: drivers/serial/serial_goldfish.c
F: include/goldfish_tty.h
GOLDFISH TIMER DRIVER
M: Kuan-Wei Chiu <visitorckw@gmail.com>
S: Maintained
F: drivers/timer/goldfish_timer.c
F: include/goldfish_timer.h
INTERCONNECT:
M: Neil Armstrong <neil.armstrong@linaro.org>
S: Maintained
@@ -1297,12 +1295,6 @@ F: doc/README.kwbimage
F: doc/kwboot.1
F: tools/kwb*
LED
M: Ivan Vozvakhov <i.vozvakhov@vk.team>
S: Supported
F: doc/device-tree-bindings/leds/leds-pwm.txt
F: drivers/led/led_pwm.c
LOGGING
M: Simon Glass <sjg@chromium.org>
S: Maintained
@@ -1315,6 +1307,21 @@ F: lib/getopt.c
F: test/log/
F: test/py/tests/test_log.py
M680X0 ARCHITECTURE
M: Kuan-Wei Chiu <visitorckw@gmail.com>
S: Maintained
F: arch/m68k/cpu/m680x0/
F: arch/m68k/include/asm/bootinfo.h
M68K
M: Angelo Dureghello <angelo@kernel-space.org>
M: Kuan-Wei Chiu <visitorckw@gmail.com>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-coldfire.git
F: arch/m68k/
F: doc/arch/m68k.rst
F: drivers/watchdog/mcf_wdt.c
MALI DISPLAY PROCESSORS
M: Liviu Dudau <liviu.dudau@foss.arm.com>
S: Supported
@@ -1444,9 +1451,7 @@ F: drivers/mmc/
N: mmc
NETWORK
M: Joe Hershberger <joe.hershberger@ni.com>
M: Ramon Fried <rfried.dev@gmail.com>
M: Jerome Forissier <jerome@forissier.org>
M: Jerome Forissier <jerome.forissier@arm.com>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-net.git
F: drivers/net/
@@ -1454,7 +1459,7 @@ F: include/net.h
F: net/
NETWORK (LWIP)
M: Jerome Forissier <jerome@forissier.org>
M: Jerome Forissier <jerome.forissier@arm.com>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-net.git
F: cmd/lwip/
@@ -1531,8 +1536,7 @@ F: drivers/pci/pcie_dw_imx.c
F: drivers/phy/phy-imx8m-pcie.c
PCI Endpoint
M: Ramon Fried <rfried.dev@gmail.com>
S: Maintained
S: Orphaned
F: drivers/pci_endpoint/
F: include/pci_ep.h
@@ -1589,6 +1593,17 @@ S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-mpc85xx.git
F: arch/powerpc/cpu/mpc85xx/
PWM LED
S: Orphan
F: doc/device-tree-bindings/leds/leds-pwm.txt
F: drivers/led/led_pwm.c
QEMU VIRTUAL SYSTEM CONTROLLER
M: Kuan-Wei Chiu <visitorckw@gmail.com>
S: Maintained
F: drivers/sysreset/sysreset_qemu_virt_ctrl.c
F: include/qemu_virt_ctrl.h
RAW NAND
M: Dario Binacchi <dario.binacchi@amarulasolutions.com>
M: Michael Trimarchi <michael@amarulasolutions.com>
@@ -1629,7 +1644,7 @@ F: drivers/pinctrl/pinctrl-th1520.c
F: drivers/ram/thead/th1520_ddr.c
RNG
M: Sughosh Ganu <sughosh.ganu@linaro.org>
M: Sughosh Ganu <sughosh.ganu@arm.com>
R: Heinrich Schuchardt <xypron.glpk@gmx.de>
S: Maintained
F: cmd/rng.c
@@ -1708,14 +1723,22 @@ F: cmd/sm3sum.c
F: include/u-boot/sm3.h
F: lib/sm3.c
SMBIOS
M: Raymond Mao <raymondmaoca@gmail.com>
S: Maintained
F: arch/arm/dts/smbios_generic.dtsi
F: cmd/smbios.c
F: drivers/sysinfo/smbios.c
F: include/smbios*
F: lib/smbios.c
SMCCC TRNG
M: Etienne Carriere <etienne.carriere@linaro.org>
S: Maintained
F: drivers/rng/smccc_trng.c
SPI
M: Jagan Teki <jagan@amarulasolutions.com>
S: Maintained
S: Orphaned
T: git https://source.denx.de/u-boot/custodians/u-boot-spi.git
F: drivers/spi/
F: include/spi*
@@ -1729,9 +1752,8 @@ T: git https://source.denx.de/u-boot/custodians/u-boot-nand-flash.git
F: drivers/mtd/nand/spi/
SPI-NOR
M: Jagan Teki <jagan@amarulasolutions.com>
M: Vignesh R <vigneshr@ti.com>
R: Tudor Ambarus <tudor.ambarus@linaro.org>
R: Takahiro Kuwano <takahiro.kuwano@infineon.com>
S: Maintained
F: drivers/mtd/spi/
F: include/spi_flash.h
@@ -1906,7 +1928,7 @@ F: drivers/usb/host/xhci*
F: include/usb/xhci.h
UTHREAD
M: Jerome Forissier <jerome@forissier.org>
M: Jerome Forissier <jerome.forissier@arm.com>
S: Maintained
F: cmd/spawn.c
F: include/uthread.h

View File

@@ -3,7 +3,7 @@
VERSION = 2026
PATCHLEVEL = 04
SUBLEVEL =
EXTRAVERSION = -rc1
EXTRAVERSION =
NAME =
# *DOCUMENTATION*
@@ -2759,8 +2759,7 @@ DOC_TARGETS := xmldocs latexdocs pdfdocs htmldocs epubdocs cleandocs \
linkcheckdocs dochelp refcheckdocs texinfodocs infodocs
PHONY += $(DOC_TARGETS)
$(DOC_TARGETS): scripts_basic FORCE
$(Q)PYTHONPATH=$(srctree)/test/py/tests:$(srctree)/test/py \
$(MAKE) $(build)=doc $@
$(Q)$(MAKE) $(build)=doc $@
PHONY += checkstack ubootrelease ubootversion

2
README
View File

@@ -1662,7 +1662,7 @@ New uImage format (FIT)
Flexible and powerful format based on Flattened Image Tree -- FIT (similar
to Flattened Device Tree). It allows the use of images with multiple
components (several kernels, ramdisks, etc.), with contents protected by
SHA1, MD5 or CRC32. More details are found in the doc/uImage.FIT directory.
SHA1, MD5 or CRC32. More details are found in the doc/usage/fit directory.
Old uImage format

View File

@@ -878,15 +878,16 @@ void flush_dcache_range(unsigned long start, unsigned long stop)
void dcache_enable(void)
{
/* The data cache is not active unless the mmu is enabled */
if (!mmu_status())
if (!mmu_status()) {
__asm_invalidate_tlb_all();
mmu_setup();
}
/* Set up page tables only once (it is done also by mmu_setup()) */
if (!gd->arch.tlb_fillptr)
setup_all_pgtables();
invalidate_dcache_all();
__asm_invalidate_tlb_all();
set_sctlr(get_sctlr() | CR_C);
}

View File

@@ -49,12 +49,6 @@ SECTIONS
} >.sram
#endif
__u_boot_list : {
. = ALIGN(8);
KEEP(*(SORT(__u_boot_list*)));
. = ALIGN(8);
} >.sram
.binman_sym_table : {
. = ALIGN(8);
__binman_sym_start = .;
@@ -63,6 +57,12 @@ SECTIONS
. = ALIGN(8);
} > .sram
__u_boot_list : {
. = ALIGN(8);
KEEP(*(SORT(__u_boot_list*)));
. = ALIGN(8);
} >.sram
__image_copy_end = .;
_end = .;
_image_binary_end = .;
@@ -75,7 +75,7 @@ SECTIONS
__bss_end = .;
} >.sdram
#else
.bss (NOLOAD) : {
.bss _image_binary_end (OVERLAY) : {
__bss_start = .;
*(.bss*)
. = ALIGN(8);
@@ -99,5 +99,6 @@ SECTIONS
ASSERT(_image_binary_end % 8 == 0, \
"_image_binary_end must be 8-byte aligned for device tree");
ASSERT(ADDR(.bss) % 8 == 0, \
".bss must be 8-byte aligned");

View File

@@ -31,16 +31,16 @@ SECTIONS
*(.data*)
}
. = ALIGN(4);
__u_boot_list : {
KEEP(*(SORT(__u_boot_list*)));
}
. = ALIGN(4);
.binman_sym_table : {
__binman_sym_start = .;
KEEP(*(SORT(.binman_sym*)));
__binman_sym_end = .;
}
. = ALIGN(4);
__u_boot_list : {
KEEP(*(SORT(__u_boot_list*)));
. = ALIGN(8);
}
@@ -48,7 +48,7 @@ SECTIONS
_image_binary_end = .;
_end = .;
.bss : {
.bss _image_binary_end (OVERLAY) : {
__bss_start = .;
*(.bss*)
. = ALIGN(8);

View File

@@ -888,7 +888,6 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mm-mx8menlo.dtb \
imx8mm-phg.dtb \
imx8mq-cm.dtb \
imx8mn-var-som-symphony.dtb \
imx8mq-mnt-reform2.dtb \
imx8mq-phanbell.dtb \
imx8mp-data-modul-edm-sbc.dtb \

View File

@@ -57,6 +57,11 @@
switch: switch@1fb58000 {
compatible = "airoha,en7581-switch";
reg = <0 0x1fb58000 0 0x8000>;
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
};
};
snfi: spi@1fa10000 {

View File

@@ -42,6 +42,11 @@
switch: switch@1fb58000 {
compatible = "airoha,en7523-switch";
reg = <0x1fb58000 0x8000>;
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
};
};
snfi: spi@1fa10000 {

View File

@@ -0,0 +1,26 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2026 Kaustabh Chakraborty <kauschluss@disroot.org>
*/
/ {
/* These properties are required by S-BOOT. */
model_info-chip = <7870>;
model_info-hw_rev = <0>;
model_info-hw_rev_end = <255>;
chosen {
#address-cells = <2>;
#size-cells = <1>;
ranges;
framebuffer@67000000 {
compatible = "simple-framebuffer";
reg = <0x0 0x67000000 (540 * 960 * 4)>;
width = <540>;
height = <960>;
stride = <(540 * 4)>;
format = "a8r8g8b8";
};
};
};

View File

@@ -0,0 +1,46 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) Kaustabh Chakraborty <kauschluss@disroot.org>
*/
/ {
/* These properties are required by S-BOOT. */
model_info-chip = <7870>;
model_info-hw_rev = <0>;
model_info-hw_rev_end = <255>;
chosen {
#address-cells = <2>;
#size-cells = <1>;
ranges;
framebuffer@67000000 {
compatible = "simple-framebuffer";
reg = <0x0 0x67000000 (720 * 1480 * 4)>;
width = <720>;
height = <1480>;
stride = <(720 * 4)>;
format = "a8r8g8b8";
};
};
/*
* S-BOOT will populate the memory nodes stated below. Existing
* values redefine the safe memory requirements as stated in upstream
* device tree, in separate nodes for each bank.
*/
memory@40000000 {
device_type = "memory";
reg = <0x0 0x40000000 0x3d800000>;
};
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x40000000>;
};
memory@100000000 {
device_type = "memory";
reg = <0x1 0x00000000 0x00000000>;
};
};

View File

@@ -0,0 +1,41 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2026 Kaustabh Chakraborty <kauschluss@disroot.org>
*/
/ {
/* These properties are required by S-BOOT. */
model_info-chip = <7870>;
model_info-hw_rev = <0>;
model_info-hw_rev_end = <255>;
chosen {
#address-cells = <2>;
#size-cells = <1>;
ranges;
framebuffer@67000000 {
compatible = "simple-framebuffer";
reg = <0x0 0x67000000 (1080 * 1920 * 4)>;
width = <1080>;
height = <1920>;
stride = <(1080 * 4)>;
format = "a8r8g8b8";
};
};
/*
* S-BOOT will populate the memory nodes stated below. Existing
* values redefine the safe memory requirements as stated in upstream
* device tree, in separate nodes for each bank.
*/
memory@40000000 {
device_type = "memory";
reg = <0x0 0x40000000 0x3e400000>;
};
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x80000000>;
};
};

View File

@@ -3,52 +3,7 @@
* Copyright 2021 Collabora Ltd.
*/
#include "imx8mn-u-boot.dtsi"
&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} {
bootph-pre-ram;
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} {
bootph-pre-ram;
};
&eeprom_som {
#address-cells = <1>;
#size-cells = <1>;
eth_mac_address: eth-mac-address@19 {
reg = <0x19 0x06>;
};
};
&fec1 {
nvmem-cells = <&eth_mac_address>;
nvmem-cell-names = "mac-address";
};
&gpio1 {
bootph-pre-ram;
};
&gpio2 {
bootph-pre-ram;
};
&gpio4 {
bootph-pre-ram;
};
&i2c1 {
bootph-all;
};
&pinctrl_i2c1 {
bootph-all;
};
&pinctrl_pmic {
bootph-pre-ram;
};
#include "imx8mn-var-som-u-boot.dtsi"
&pinctrl_reg_usdhc2_vmmc {
bootph-pre-ram;
@@ -62,14 +17,6 @@
bootph-pre-ram;
};
&pinctrl_usdhc3 {
bootph-pre-ram;
};
&pinctrl_wdog {
bootph-pre-ram;
};
&uart4 {
bootph-pre-ram;
};
@@ -77,11 +24,3 @@
&usdhc2 {
bootph-pre-ram;
};
&usdhc3 {
bootph-pre-ram;
};
&eeprom_som {
bootph-all;
};

View File

@@ -1,236 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2019-2020 Variscite Ltd.
* Copyright (C) 2020 Krzysztof Kozlowski <krzk@kernel.org>
*/
/dts-v1/;
#include "imx8mn-var-som.dtsi"
/ {
model = "Variscite VAR-SOM-MX8MN Symphony evaluation board";
compatible = "variscite,var-som-mx8mn-symphony", "variscite,var-som-mx8mn", "fsl,imx8mn";
reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio4 22 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
gpio-keys {
compatible = "gpio-keys";
key-back {
label = "Back";
gpios = <&pca9534 1 GPIO_ACTIVE_LOW>;
linux,code = <KEY_BACK>;
};
key-home {
label = "Home";
gpios = <&pca9534 2 GPIO_ACTIVE_LOW>;
linux,code = <KEY_HOME>;
};
key-menu {
label = "Menu";
gpios = <&pca9534 3 GPIO_ACTIVE_LOW>;
linux,code = <KEY_MENU>;
};
};
leds {
compatible = "gpio-leds";
led {
label = "Heartbeat";
gpios = <&pca9534 0 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
};
};
};
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
pca9534: gpio@20 {
compatible = "nxp,pca9534";
reg = <0x20>;
gpio-controller;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pca9534>;
interrupt-parent = <&gpio1>;
interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
#gpio-cells = <2>;
wakeup-source;
/* USB 3.0 OTG (usbotg1) / SATA port switch, set to USB 3.0 */
usb3-sata-sel-hog {
gpio-hog;
gpios = <4 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "usb3_sata_sel";
};
som-vselect-hog {
gpio-hog;
gpios = <6 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "som_vselect";
};
enet-sel-hog {
gpio-hog;
gpios = <7 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "enet_sel";
};
};
extcon_usbotg1: typec@3d {
compatible = "nxp,ptn5150";
reg = <0x3d>;
interrupt-parent = <&gpio1>;
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ptn5150>;
status = "okay";
};
};
&i2c3 {
/* Capacitive touch controller */
ft5x06_ts: touchscreen@38 {
compatible = "edt,edt-ft5406";
reg = <0x38>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_captouch>;
interrupt-parent = <&gpio5>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
touchscreen-size-x = <800>;
touchscreen-size-y = <480>;
touchscreen-inverted-x;
touchscreen-inverted-y;
};
rtc@68 {
compatible = "dallas,ds1337";
reg = <0x68>;
};
};
/* Header */
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
/* Header */
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
&usbotg1 {
disable-over-current;
extcon = <&extcon_usbotg1>, <&extcon_usbotg1>;
};
&pinctrl_fec1 {
fsl,pins = <
MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
/* Remove the MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 as not used */
>;
};
&pinctrl_fec1_sleep {
fsl,pins = <
MX8MN_IOMUXC_ENET_MDC_GPIO1_IO16 0x120
MX8MN_IOMUXC_ENET_MDIO_GPIO1_IO17 0x120
MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18 0x120
MX8MN_IOMUXC_ENET_TD2_GPIO1_IO19 0x120
MX8MN_IOMUXC_ENET_TD1_GPIO1_IO20 0x120
MX8MN_IOMUXC_ENET_TD0_GPIO1_IO21 0x120
MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29 0x120
MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28 0x120
MX8MN_IOMUXC_ENET_RD1_GPIO1_IO27 0x120
MX8MN_IOMUXC_ENET_RD0_GPIO1_IO26 0x120
MX8MN_IOMUXC_ENET_TXC_GPIO1_IO23 0x120
MX8MN_IOMUXC_ENET_RXC_GPIO1_IO25 0x120
MX8MN_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x120
MX8MN_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x120
/* Remove the MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 as not used */
>;
};
&iomuxc {
pinctrl_captouch: captouchgrp {
fsl,pins = <
MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4 0x16
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
>;
};
pinctrl_pca9534: pca9534grp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x16
>;
};
pinctrl_ptn5150: ptn5150grp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x16
>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x41
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
>;
};
};

View File

@@ -0,0 +1,70 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2025 Dimonoff
*/
#include "imx8mn-u-boot.dtsi"
/ {
aliases {
eeprom-som = &eeprom_som;
};
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} {
bootph-pre-ram;
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} {
bootph-pre-ram;
};
&eeprom_som {
bootph-all;
#address-cells = <1>;
#size-cells = <1>;
eth_mac_address: eth-mac-address@19 {
reg = <0x19 0x06>;
};
};
&fec1 {
nvmem-cells = <&eth_mac_address>;
nvmem-cell-names = "mac-address";
};
&gpio1 {
bootph-pre-ram;
};
&gpio2 {
bootph-pre-ram;
};
&gpio4 {
bootph-pre-ram;
};
&i2c1 {
bootph-all;
};
&usdhc3 {
bootph-pre-ram;
};
&pinctrl_i2c1 {
bootph-all;
};
&pinctrl_wdog {
bootph-pre-ram;
};
&pinctrl_pmic {
bootph-pre-ram;
};
&pinctrl_usdhc3 {
bootph-pre-ram;
};

View File

@@ -1,564 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2019 NXP
* Copyright 2019-2020 Variscite Ltd.
* Copyright (C) 2020 Krzysztof Kozlowski <krzk@kernel.org>
*/
#include "imx8mn.dtsi"
/ {
model = "Variscite VAR-SOM-MX8MN module";
compatible = "variscite,var-som-mx8mn", "fsl,imx8mn";
aliases {
eeprom-som = &eeprom_som;
};
chosen {
stdout-path = &uart4;
};
memory@40000000 {
device_type = "memory";
reg = <0x0 0x40000000 0 0x40000000>;
};
reg_eth_phy: regulator-eth-phy {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_eth_phy>;
regulator-name = "eth_phy_pwr";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 9 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
&A53_0 {
cpu-supply = <&buck2_reg>;
};
&A53_1 {
cpu-supply = <&buck2_reg>;
};
&A53_2 {
cpu-supply = <&buck2_reg>;
};
&A53_3 {
cpu-supply = <&buck2_reg>;
};
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
cs-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>,
<&gpio1 0 GPIO_ACTIVE_LOW>;
/delete-property/ dmas;
/delete-property/ dma-names;
status = "okay";
/* Resistive touch controller */
touchscreen@0 {
reg = <0>;
compatible = "ti,ads7846";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_restouch>;
interrupt-parent = <&gpio1>;
interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
spi-max-frequency = <1500000>;
pendown-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
ti,x-min = /bits/ 16 <125>;
touchscreen-size-x = <4008>;
ti,y-min = /bits/ 16 <282>;
touchscreen-size-y = <3864>;
ti,x-plate-ohms = /bits/ 16 <180>;
touchscreen-max-pressure = <255>;
touchscreen-average-samples = <10>;
ti,debounce-tol = /bits/ 16 <3>;
ti,debounce-rep = /bits/ 16 <1>;
ti,settle-delay-usec = /bits/ 16 <150>;
ti,keep-vref-on;
wakeup-source;
};
};
&fec1 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_fec1>;
pinctrl-1 = <&pinctrl_fec1_sleep>;
phy-mode = "rgmii";
phy-handle = <&ethphy>;
phy-supply = <&reg_eth_phy>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy: ethernet-phy@4 { /* AR8033 or ADIN1300 */
compatible = "ethernet-phy-ieee802.3-c22";
reg = <4>;
reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
/*
* Deassert delay:
* ADIN1300 requires 5ms.
* AR8033 requires 1ms.
*/
reset-deassert-us = <20000>;
};
};
};
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
pmic@4b {
compatible = "rohm,bd71847";
reg = <0x4b>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
interrupt-parent = <&gpio2>;
interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
rohm,reset-snvs-powered;
regulators {
buck1_reg: BUCK1 {
regulator-name = "buck1";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <1250>;
};
buck2_reg: BUCK2 {
regulator-name = "buck2";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <1250>;
rohm,dvs-run-voltage = <1000000>;
rohm,dvs-idle-voltage = <900000>;
};
buck3_reg: BUCK3 {
regulator-name = "buck3";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1350000>;
regulator-boot-on;
regulator-always-on;
};
buck4_reg: BUCK4 {
regulator-name = "buck4";
regulator-min-microvolt = <2600000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
buck5_reg: BUCK5 {
regulator-name = "buck5";
regulator-min-microvolt = <1605000>;
regulator-max-microvolt = <1995000>;
regulator-boot-on;
regulator-always-on;
};
buck6_reg: BUCK6 {
regulator-name = "buck6";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1400000>;
regulator-boot-on;
regulator-always-on;
};
ldo1_reg: LDO1 {
regulator-name = "ldo1";
regulator-min-microvolt = <1600000>;
regulator-max-microvolt = <1900000>;
regulator-boot-on;
regulator-always-on;
};
ldo2_reg: LDO2 {
regulator-name = "ldo2";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <900000>;
regulator-boot-on;
regulator-always-on;
};
ldo3_reg: LDO3 {
regulator-name = "ldo3";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo4_reg: LDO4 {
regulator-name = "ldo4";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
ldo5_reg: LDO5 {
regulator-compatible = "ldo5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
ldo6_reg: LDO6 {
regulator-name = "ldo6";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
};
};
eeprom_som: eeprom@52 {
compatible = "atmel,24c04";
reg = <0x52>;
pagesize = <16>;
};
};
&i2c3 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
/* TODO: configure audio, as of now just put a placeholder */
wm8904: codec@1a {
compatible = "wlf,wm8904";
reg = <0x1a>;
status = "disabled";
};
};
&snvs_pwrkey {
status = "okay";
};
/* Bluetooth */
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
assigned-clocks = <&clk IMX8MN_CLK_UART2>;
assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
uart-has-rtscts;
status = "okay";
};
/* Console */
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
status = "okay";
};
&usbotg1 {
dr_mode = "otg";
usb-role-switch;
status = "okay";
};
/* WIFI */
&usdhc1 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
bus-width = <4>;
non-removable;
keep-power-in-suspend;
status = "okay";
brcmf: bcrmf@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
};
};
/* SD */
&usdhc2 {
assigned-clocks = <&clk IMX8MN_CLK_USDHC2>;
assigned-clock-rates = <200000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
bus-width = <4>;
vmmc-supply = <&reg_usdhc2_vmmc>;
status = "okay";
};
/* eMMC */
&usdhc3 {
assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
assigned-clock-rates = <400000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x13
MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x13
MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x13
MX8MN_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x13
MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x13
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
>;
};
pinctrl_fec1_sleep: fec1sleepgrp {
fsl,pins = <
MX8MN_IOMUXC_ENET_MDC_GPIO1_IO16 0x120
MX8MN_IOMUXC_ENET_MDIO_GPIO1_IO17 0x120
MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18 0x120
MX8MN_IOMUXC_ENET_TD2_GPIO1_IO19 0x120
MX8MN_IOMUXC_ENET_TD1_GPIO1_IO20 0x120
MX8MN_IOMUXC_ENET_TD0_GPIO1_IO21 0x120
MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29 0x120
MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28 0x120
MX8MN_IOMUXC_ENET_RD1_GPIO1_IO27 0x120
MX8MN_IOMUXC_ENET_RD0_GPIO1_IO26 0x120
MX8MN_IOMUXC_ENET_TXC_GPIO1_IO23 0x120
MX8MN_IOMUXC_ENET_RXC_GPIO1_IO25 0x120
MX8MN_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x120
MX8MN_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x120
MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x120
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
>;
};
pinctrl_pmic: pmicirqgrp {
fsl,pins = <
MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x141
>;
};
pinctrl_reg_eth_phy: regethphygrp {
fsl,pins = <
MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x41
>;
};
pinctrl_restouch: restouchgrp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MN_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140
MX8MN_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140
MX8MN_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140
MX8MN_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
>;
};
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x41
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
>;
};
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <
MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
>;
};
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166
>;
};
};

View File

@@ -96,6 +96,10 @@
};
};
};
imx95-cm7 {
compatible = "fsl,imx95-cm7";
};
};
&A55_0 {

View File

@@ -1,20 +1,21 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* This file was generated with the
* AM623/AM625 SysConfig DDR Configuration Tool for AM64x, AM625, AM623, AM62Ax, AM62Px v0.10.02
* Tue Sep 17 2024 13:07:19 GMT+0530 (India Standard Time)
* AM623/AM625 SysConfig DDR Configuration Tool for AM64x, AM625, AM623, AM62Ax, AM62Px, AM62Dx, AM62Lx v0.10.32
* Fri Jan 30 2026 13:45:31 GMT+0530 (India Standard Time)
* DDR Type: LPDDR4
* F0 = 50MHz F1 = NA F2 = 800MHz
* Density (per channel): 16Gb
* Write DBI: Enable
* Number of Ranks: 1
*/
*/
#define DDRSS_PLL_FHS_CNT 3
#define DDRSS_PLL_FREQUENCY_1 400000000
#define DDRSS_PLL_FREQUENCY_2 400000000
#define DDRSS_SDRAM_IDX 15
#define DDRSS_REGION_IDX 16
#define DDRSS_REGION_IDX 15
#define DDRSS_TOOL_VERSION "0.10.32"
#define DDRSS_CTL_0_DATA 0x00000B00
#define DDRSS_CTL_1_DATA 0x00000000
@@ -646,8 +647,8 @@
#define DDRSS_PI_204_DATA 0x00C90100
#define DDRSS_PI_205_DATA 0x010000C9
#define DDRSS_PI_206_DATA 0x00C900C9
#define DDRSS_PI_207_DATA 0x32103200
#define DDRSS_PI_208_DATA 0x01013210
#define DDRSS_PI_207_DATA 0x321E3200
#define DDRSS_PI_208_DATA 0x0101321E
#define DDRSS_PI_209_DATA 0x0A070601
#define DDRSS_PI_210_DATA 0x0D09070D
#define DDRSS_PI_211_DATA 0x0D09070D

View File

@@ -9,84 +9,4 @@
#include "k3-am62-ddr.dtsi"
#include "k3-am62-lp-sk-u-boot.dtsi"
/ {
aliases {
tick-timer = &main_timer0;
remoteproc0 = &sysctrler;
remoteproc1 = &a53_0;
serial0 = &wkup_uart0;
serial3 = &main_uart1;
};
a53_0: a53@0 {
compatible = "ti,am654-rproc";
reg = <0x00 0x00a90000 0x00 0x10>;
power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 135 0>;
clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
clock-names = "gtc", "core";
assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
assigned-clock-parents = <&k3_clks 61 2>;
assigned-clock-rates = <200000000>, <1200000000>;
ti,sci = <&dmsc>;
ti,sci-proc-id = <32>;
ti,sci-host-id = <10>;
bootph-pre-ram;
};
dm_tifs: dm-tifs {
compatible = "ti,j721e-dm-sci";
ti,host-id = <36>;
ti,secure-host;
mbox-names = "rx", "tx";
mboxes= <&secure_proxy_main 22>,
<&secure_proxy_main 23>;
bootph-pre-ram;
};
};
&dmsc {
mboxes= <&secure_proxy_main 0>,
<&secure_proxy_main 1>,
<&secure_proxy_main 0>;
mbox-names = "rx", "tx", "notify";
ti,host-id = <35>;
ti,secure-host;
};
&secure_proxy_sa3 {
/* We require this for boot handshake */
status = "okay";
};
&cbass_main {
sysctrler: sysctrler {
compatible = "ti,am654-tisci-rproc-r5";
mboxes= <&secure_proxy_main 1>,
<&secure_proxy_main 0>,
<&secure_proxy_sa3 0>;
mbox-names = "tx", "rx", "boot_notify";
bootph-pre-ram;
};
};
&main_timer0 {
/delete-property/ clocks;
/delete-property/ clocks-names;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
clock-frequency = <25000000>;
};
/* WKUP UART0 is used for DM firmware logs */
&wkup_uart0 {
status = "okay";
};
/* Main UART1 is used for TIFS firmware logs */
&main_uart1 {
status = "okay";
};
#include "k3-am625-r5.dtsi"

View File

@@ -215,6 +215,36 @@
fit {
images {
atf {
ti-secure {
auth-in-place = <0xa02>;
firewall-1-0 {
insert-template = <&firewall_bg_3>;
id = <1>;
region = <0>;
};
firewall-1-1 {
insert-template = <&firewall_armv8_atf_fg>;
id = <1>;
region = <1>;
};
};
};
tee {
ti-secure {
auth-in-place = <0xa02>;
firewall-1-2 {
insert-template = <&firewall_armv8_optee_fg>;
id = <1>;
region = <2>;
};
};
};
tifsstub-hs {
description = "TIFSSTUB";
type = "firmware";

View File

@@ -11,70 +11,14 @@
#include "k3-am62-ddr.dtsi"
#include "k3-am625-beagleplay-u-boot.dtsi"
#include "k3-am625-r5.dtsi"
/ {
aliases {
remoteproc0 = &sysctrler;
remoteproc1 = &a53_0;
};
a53_0: a53@0 {
compatible = "ti,am654-rproc";
reg = <0x00 0x00a90000 0x00 0x10>;
power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 135 0>;
clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
clock-names = "gtc", "core";
assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
assigned-clock-parents = <&k3_clks 61 2>;
assigned-clock-rates = <200000000>, <1250000000>;
ti,sci = <&dmsc>;
ti,sci-proc-id = <32>;
ti,sci-host-id = <10>;
bootph-pre-ram;
};
dm_tifs: dm-tifs {
compatible = "ti,j721e-dm-sci";
ti,host-id = <36>;
ti,secure-host;
mbox-names = "rx", "tx";
mboxes= <&secure_proxy_main 22>,
<&secure_proxy_main 23>;
bootph-pre-ram;
};
};
&main_timer0 {
/delete-property/ clocks;
/delete-property/ clocks-names;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
clock-frequency = <25000000>;
};
&dmsc {
mboxes= <&secure_proxy_main 0>,
<&secure_proxy_main 1>,
<&secure_proxy_main 0>;
mbox-names = "rx", "tx", "notify";
ti,host-id = <35>;
ti,secure-host;
};
&secure_proxy_sa3 {
/* We require this for boot handshake */
status = "okay";
};
&cbass_main {
sysctrler: sysctrler {
compatible = "ti,am654-tisci-rproc-r5";
mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&secure_proxy_sa3 0>;
mbox-names = "tx", "rx", "boot_notify";
bootph-pre-ram;
};
&a53_0 {
power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
assigned-clock-parents = <&k3_clks 61 2>;
assigned-clock-rates = <200000000>, <1250000000>;
};
&main_pktdma {

View File

@@ -10,42 +10,9 @@
#include "k3-am62-ddr.dtsi"
#include "k3-am625-phyboard-lyra-rdk-u-boot.dtsi"
#include "k3-am625-r5.dtsi"
/ {
aliases {
remoteproc0 = &sysctrler;
remoteproc1 = &a53_0;
serial0 = &wkup_uart0;
serial3 = &main_uart1;
};
a53_0: a53@0 {
compatible = "ti,am654-rproc";
reg = <0x00 0x00a90000 0x00 0x10>;
power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 135 0>;
clocks = <&k3_clks 61 0>;
assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
assigned-clock-parents = <&k3_clks 61 2>;
assigned-clock-rates = <200000000>, <1200000000>;
ti,sci = <&dmsc>;
ti,sci-proc-id = <32>;
ti,sci-host-id = <10>;
bootph-pre-ram;
};
dm_tifs: dm-tifs {
compatible = "ti,j721e-dm-sci";
ti,host-id = <36>;
ti,secure-host;
mbox-names = "rx", "tx";
mboxes= <&secure_proxy_main 22>,
<&secure_proxy_main 23>;
bootph-pre-ram;
};
memory@80000000 {
device_type = "memory";
/* 2G RAM */
@@ -54,45 +21,19 @@
};
};
&main_timer0 {
/delete-property/ clocks;
/delete-property/ clocks-names;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
clock-frequency = <25000000>;
};
&secure_proxy_sa3 {
/* We require this for boot handshake */
status = "okay";
};
&cbass_main {
sysctrler: sysctrler {
compatible = "ti,am654-tisci-rproc-r5";
mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&secure_proxy_sa3 0>;
mbox-names = "tx", "rx", "boot_notify";
bootph-pre-ram;
};
};
&dmsc {
mboxes= <&secure_proxy_main 0>,
<&secure_proxy_main 1>,
<&secure_proxy_main 0>;
mbox-names = "rx", "tx", "notify";
ti,host-id = <35>;
ti,secure-host;
};
&main_bcdma {
ti,sci = <&dm_tifs>;
&a53_0 {
clock-names = "gtc";
clocks = <&k3_clks 61 0>;
};
&main_pktdma {
ti,sci = <&dm_tifs>;
};
&main_bcdma {
ti,sci = <&dm_tifs>;
};
&mcu_pmx0 {
wkup_uart0_pins_default: wkup-uart0-pins-default {
pinctrl-single,pins = <
@@ -105,11 +46,6 @@
};
};
&ospi0 {
reg = <0x00 0x0fc40000 0x00 0x100>,
<0x00 0x60000000 0x00 0x08000000>;
};
/* WKUP UART0 is used for DM firmware logs */
&wkup_uart0 {
pinctrl-names = "default";

View File

@@ -9,92 +9,8 @@
#include "k3-am62-ddr.dtsi"
#include "k3-am625-sk-u-boot.dtsi"
/ {
aliases {
tick-timer = &main_timer0;
remoteproc0 = &sysctrler;
remoteproc1 = &a53_0;
serial0 = &wkup_uart0;
serial3 = &main_uart1;
};
a53_0: a53@0 {
compatible = "ti,am654-rproc";
reg = <0x00 0x00a90000 0x00 0x10>;
power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 135 0>;
clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
clock-names = "gtc", "core";
assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
assigned-clock-parents = <&k3_clks 61 2>;
assigned-clock-rates = <200000000>, <1200000000>;
ti,sci = <&dmsc>;
ti,sci-proc-id = <32>;
ti,sci-host-id = <10>;
bootph-pre-ram;
};
dm_tifs: dm-tifs {
compatible = "ti,j721e-dm-sci";
ti,host-id = <36>;
ti,secure-host;
mbox-names = "rx", "tx";
mboxes= <&secure_proxy_main 22>,
<&secure_proxy_main 23>;
bootph-pre-ram;
};
};
&dmsc {
mboxes= <&secure_proxy_main 0>,
<&secure_proxy_main 1>,
<&secure_proxy_main 0>;
mbox-names = "rx", "tx", "notify";
ti,host-id = <35>;
ti,secure-host;
};
&secure_proxy_sa3 {
/* We require this for boot handshake */
status = "okay";
};
&cbass_main {
sysctrler: sysctrler {
compatible = "ti,am654-tisci-rproc-r5";
mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&secure_proxy_sa3 0>;
mbox-names = "tx", "rx", "boot_notify";
bootph-pre-ram;
};
};
&main_timer0 {
/delete-property/ clocks;
/delete-property/ clocks-names;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
clock-frequency = <25000000>;
};
/* WKUP UART0 is used for DM firmware logs */
&wkup_uart0 {
status = "okay";
};
/* Main UART1 is used for TIFS firmware logs */
&main_uart1 {
status = "okay";
};
&ospi0 {
reg = <0x00 0x0fc40000 0x00 0x100>,
<0x00 0x60000000 0x00 0x08000000>;
};
#include "k3-am625-r5.dtsi"
&main_pktdma {
ti,sci = <&dm_tifs>;
bootph-all;
};

View File

@@ -0,0 +1,88 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2026 Texas Instruments Incorporated - https://www.ti.com/
*/
/ {
aliases {
tick-timer = &main_timer0;
remoteproc0 = &sysctrler;
remoteproc1 = &a53_0;
serial0 = &wkup_uart0;
serial3 = &main_uart1;
};
a53_0: a53@0 {
compatible = "ti,am654-rproc";
reg = <0x00 0x00a90000 0x00 0x10>;
power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 135 0>;
clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
clock-names = "gtc", "core";
assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
assigned-clock-parents = <&k3_clks 61 2>;
assigned-clock-rates = <200000000>, <1200000000>;
ti,sci = <&dmsc>;
ti,sci-proc-id = <32>;
ti,sci-host-id = <10>;
bootph-pre-ram;
};
dm_tifs: dm-tifs {
compatible = "ti,j721e-dm-sci";
ti,host-id = <36>;
ti,secure-host;
mbox-names = "rx", "tx";
mboxes= <&secure_proxy_main 22>,
<&secure_proxy_main 23>;
bootph-pre-ram;
};
};
&dmsc {
mboxes= <&secure_proxy_main 0>,
<&secure_proxy_main 1>,
<&secure_proxy_main 0>;
mbox-names = "rx", "tx", "notify";
ti,host-id = <35>;
ti,secure-host;
};
&secure_proxy_sa3 {
/* We require this for boot handshake */
status = "okay";
};
&cbass_main {
sysctrler: sysctrler {
compatible = "ti,am654-tisci-rproc-r5";
mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&secure_proxy_sa3 0>;
mbox-names = "tx", "rx", "boot_notify";
bootph-pre-ram;
};
};
&main_timer0 {
/delete-property/ clocks;
/delete-property/ clocks-names;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
clock-frequency = <25000000>;
};
/* WKUP UART0 is used for DM firmware logs */
&wkup_uart0 {
status = "okay";
};
/* Main UART1 is used for TIFS firmware logs */
&main_uart1 {
status = "okay";
};
&ospi0 {
reg = <0x00 0x0fc40000 0x00 0x100>,
<0x00 0x60000000 0x00 0x08000000>;
};

View File

@@ -275,6 +275,35 @@
fit {
images {
atf {
ti-secure {
auth-in-place = <0xa02>;
firewall-1-0 {
insert-template = <&firewall_bg_3>;
id = <1>;
region = <0>;
};
firewall-1-1 {
insert-template = <&firewall_armv8_atf_fg>;
id = <1>;
region = <1>;
};
};
};
tee {
ti-secure {
auth-in-place = <0xa02>;
firewall-1-2 {
insert-template = <&firewall_armv8_optee_fg>;
id = <1>;
region = <2>;
};
};
};
tifsstub-hs {
description = "TIFSSTUB";

View File

@@ -9,75 +9,30 @@
#include "k3-am62-ddr.dtsi"
#include "k3-am625-verdin-wifi-dev-u-boot.dtsi"
#include "k3-am625-r5.dtsi"
/ {
a53_0: a53@0 {
compatible = "ti,am654-rproc";
reg = <0x00 0x00a90000 0x00 0x10>;
/*
* FIXME: Currently only the SPL running on the R5 has a clock
* driver. As a workaround therefore move the assigned-clock
* stuff required for our ETH_25MHz_CLK from the cpsw3g_mdio
* node of the regular device tree to here (last one each in
* below three lines, adding a <0> as spacing for parents).
*/
assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>, <&k3_clks 157 20>;
assigned-clock-parents = <&k3_clks 61 2>, <0>, <&k3_clks 157 22>;
assigned-clock-rates = <200000000>, <800000000>, <25000000>;
clocks = <&k3_clks 61 0>;
power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 135 0>;
ti,sci = <&dmsc>;
ti,sci-host-id = <10>;
ti,sci-proc-id = <32>;
bootph-pre-ram;
};
aliases {
serial0 = &main_uart1;
serial1 = &wkup_uart0;
serial2 = &main_uart0;
serial3 = &mcu_uart0;
serial4 = &main_uart5;
remoteproc0 = &sysctrler;
remoteproc1 = &a53_0;
};
dm_tifs: dm-tifs {
compatible = "ti,j721e-dm-sci";
mbox-names = "rx", "tx";
mboxes= <&secure_proxy_main 22>,
<&secure_proxy_main 23>;
ti,host-id = <36>;
ti,secure-host;
bootph-pre-ram;
};
};
&cbass_main {
sysctrler: sysctrler {
compatible = "ti,am654-tisci-rproc-r5";
mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&secure_proxy_sa3 0>;
mbox-names = "tx", "rx", "boot_notify";
bootph-pre-ram;
};
};
&dmsc {
mboxes= <&secure_proxy_main 0>,
<&secure_proxy_main 1>,
<&secure_proxy_main 0>;
mbox-names = "rx", "tx", "notify";
ti,host-id = <35>;
ti,secure-host;
};
&main_timer0 {
/delete-property/ clocks;
/delete-property/ clocks-names;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
clock-frequency = <25000000>;
};
&secure_proxy_sa3 {
/* We require this for boot handshake */
status = "okay";
&a53_0 {
clocks = <&k3_clks 61 0>;
/*
* FIXME: Currently only the SPL running on the R5 has a clock
* driver. As a workaround therefore move the assigned-clock
* stuff required for our ETH_25MHz_CLK from the cpsw3g_mdio
* node of the regular device tree to here (last one each in
* below three lines, adding a <0> as spacing for parents).
*/
assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>, <&k3_clks 157 20>;
assigned-clock-parents = <&k3_clks 61 2>, <0>, <&k3_clks 157 22>;
assigned-clock-rates = <200000000>, <800000000>, <25000000>;
};

View File

@@ -200,6 +200,36 @@
fit {
images {
atf {
ti-secure {
auth-in-place = <0xa02>;
firewall-1-0 {
insert-template = <&firewall_bg_3>;
id = <1>;
region = <0>;
};
firewall-1-1 {
insert-template = <&firewall_armv8_atf_fg>;
id = <1>;
region = <1>;
};
};
};
tee {
ti-secure {
auth-in-place = <0xa02>;
firewall-1-2 {
insert-template = <&firewall_armv8_optee_fg>;
id = <1>;
region = <2>;
};
};
};
tifsstub-hs {
description = "TIFSSTUB";
type = "firmware";

View File

@@ -11,92 +11,8 @@
#include "k3-am62-ddr.dtsi"
#include "k3-am6254atl-sk-u-boot.dtsi"
/ {
aliases {
tick-timer = &main_timer0;
remoteproc0 = &sysctrler;
remoteproc1 = &a53_0;
serial0 = &wkup_uart0;
serial3 = &main_uart1;
};
a53_0: a53@0 {
compatible = "ti,am654-rproc";
reg = <0x00 0x00a90000 0x00 0x10>;
power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 135 0>;
clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
clock-names = "gtc", "core";
assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
assigned-clock-parents = <&k3_clks 61 2>;
assigned-clock-rates = <200000000>, <1200000000>;
ti,sci = <&dmsc>;
ti,sci-proc-id = <32>;
ti,sci-host-id = <10>;
bootph-pre-ram;
};
dm_tifs: dm-tifs {
compatible = "ti,j721e-dm-sci";
ti,host-id = <36>;
ti,secure-host;
mbox-names = "rx", "tx";
mboxes= <&secure_proxy_main 22>,
<&secure_proxy_main 23>;
bootph-pre-ram;
};
};
&dmsc {
mboxes= <&secure_proxy_main 0>,
<&secure_proxy_main 1>,
<&secure_proxy_main 0>;
mbox-names = "rx", "tx", "notify";
ti,host-id = <35>;
ti,secure-host;
};
&secure_proxy_sa3 {
/* We require this for boot handshake */
status = "okay";
};
&cbass_main {
sysctrler: sysctrler {
compatible = "ti,am654-tisci-rproc-r5";
mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&secure_proxy_sa3 0>;
mbox-names = "tx", "rx", "boot_notify";
bootph-pre-ram;
};
};
&main_timer0 {
/delete-property/ clocks;
/delete-property/ clocks-names;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
clock-frequency = <25000000>;
};
/* WKUP UART0 is used for DM firmware logs */
&wkup_uart0 {
status = "okay";
};
/* Main UART1 is used for TIFS firmware logs */
&main_uart1 {
status = "okay";
};
&ospi0 {
reg = <0x00 0x0fc40000 0x00 0x100>,
<0x00 0x60000000 0x00 0x08000000>;
};
#include "k3-am625-r5.dtsi"
&main_pktdma {
ti,sci = <&dm_tifs>;
bootph-all;
};

View File

@@ -1,19 +1,20 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* This file was generated with the
* AM62Ax SysConfig DDR Configuration Tool for AM64x, AM625, AM623, AM62Ax, AM62Px v0.10.02
* Tue Sep 17 2024 10:55:17 GMT+0530 (India Standard Time)
* AM62Ax SysConfig DDR Configuration Tool for AM64x, AM625, AM623, AM62Ax, AM62Px, AM62Dx, AM62Lx v0.10.32
* Fri Jan 30 2026 13:49:36 GMT+0530 (India Standard Time)
* DDR Type: LPDDR4
* F0 = 50MHz F1 = NA F2 = 1866MHz
* Density (per channel): 8Gb
* Number of Ranks: 2
*/
*/
#define DDRSS_PLL_FHS_CNT 5
#define DDRSS_PLL_FREQUENCY_1 933000000
#define DDRSS_PLL_FREQUENCY_2 933000000
#define DDRSS_SDRAM_IDX 16
#define DDRSS_REGION_IDX 17
#define DDRSS_TOOL_VERSION "0.10.32"
#define DDRSS_CTL_0_DATA 0x00000B00
#define DDRSS_CTL_1_DATA 0x00000000
@@ -358,7 +359,7 @@
#define DDRSS_CTL_340_DATA 0x00000000
#define DDRSS_CTL_341_DATA 0x00000000
#define DDRSS_CTL_342_DATA 0x00000000
#define DDRSS_CTL_343_DATA 0x00000000
#define DDRSS_CTL_343_DATA 0x7FFFFFFF
#define DDRSS_CTL_344_DATA 0x00000000
#define DDRSS_CTL_345_DATA 0x00000000
#define DDRSS_CTL_346_DATA 0x00000000
@@ -375,14 +376,14 @@
#define DDRSS_CTL_357_DATA 0x00000000
#define DDRSS_CTL_358_DATA 0x00000000
#define DDRSS_CTL_359_DATA 0x00000000
#define DDRSS_CTL_360_DATA 0x00000000
#define DDRSS_CTL_361_DATA 0x00000000
#define DDRSS_CTL_360_DATA 0xFFFFFFFF
#define DDRSS_CTL_361_DATA 0xFFFF0000
#define DDRSS_CTL_362_DATA 0x00000000
#define DDRSS_CTL_363_DATA 0x00000000
#define DDRSS_CTL_363_DATA 0xFFFFFFFF
#define DDRSS_CTL_364_DATA 0x00000000
#define DDRSS_CTL_365_DATA 0x00000000
#define DDRSS_CTL_366_DATA 0x00000000
#define DDRSS_CTL_367_DATA 0x00000000
#define DDRSS_CTL_365_DATA 0x00FFFFFF
#define DDRSS_CTL_366_DATA 0xFFFF00FF
#define DDRSS_CTL_367_DATA 0x0000FFFF
#define DDRSS_CTL_368_DATA 0x00000000
#define DDRSS_CTL_369_DATA 0x00000000
#define DDRSS_CTL_370_DATA 0x00000000
@@ -669,8 +670,8 @@
#define DDRSS_PI_216_DATA 0x01D40100
#define DDRSS_PI_217_DATA 0x010001D4
#define DDRSS_PI_218_DATA 0x01D401D4
#define DDRSS_PI_219_DATA 0x32103200
#define DDRSS_PI_220_DATA 0x01013210
#define DDRSS_PI_219_DATA 0x200B3200
#define DDRSS_PI_220_DATA 0x0101200B
#define DDRSS_PI_221_DATA 0x0A070601
#define DDRSS_PI_222_DATA 0x1C11090D
#define DDRSS_PI_223_DATA 0x1C110913

View File

@@ -165,6 +165,36 @@
fit {
images {
atf {
ti-secure {
auth-in-place = <0xa02>;
firewall-1-0 {
insert-template = <&firewall_bg_3>;
id = <1>;
region = <0>;
};
firewall-1-1 {
insert-template = <&firewall_armv8_atf_fg>;
id = <1>;
region = <1>;
};
};
};
tee {
ti-secure {
auth-in-place = <0xa02>;
firewall-1-2 {
insert-template = <&firewall_armv8_optee_fg>;
id = <1>;
region = <2>;
};
};
};
tifsstub-hs {
description = "TIFSSTUB";
type = "firmware";

View File

@@ -200,6 +200,36 @@
fit {
images {
atf {
ti-secure {
auth-in-place = <0xa02>;
firewall-1-0 {
insert-template = <&firewall_bg_3>;
id = <1>;
region = <0>;
};
firewall-1-1 {
insert-template = <&firewall_armv8_atf_fg>;
id = <1>;
region = <1>;
};
};
};
tee {
ti-secure {
auth-in-place = <0xa02>;
firewall-1-2 {
insert-template = <&firewall_armv8_optee_fg>;
id = <1>;
region = <2>;
};
};
};
tifsstub-hs {
description = "TIFSSTUB";
type = "firmware";

View File

@@ -13,48 +13,18 @@
#include "k3-am62a-ddr.dtsi"
#include "k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi"
#include "k3-am62a7-r5.dtsi"
/ {
aliases {
remoteproc0 = &sysctrler;
remoteproc1 = &a53_0;
serial0 = &wkup_uart0;
serial3 = &main_uart1;
};
};
a53_0: a53@0 {
compatible = "ti,am654-rproc";
reg = <0x00 0x00a90000 0x00 0x10>;
power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 135 0>;
clocks = <&k3_clks 61 0>;
assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
assigned-clock-parents = <&k3_clks 61 2>;
assigned-clock-rates = <200000000>, <1200000000>;
ti,sci = <&dmsc>;
ti,sci-proc-id = <32>;
ti,sci-host-id = <10>;
bootph-pre-ram;
};
dm_tifs: dm-tifs {
compatible = "ti,j721e-dm-sci";
ti,host-id = <36>;
ti,secure-host;
mbox-names = "rx", "tx";
mboxes= <&secure_proxy_main 22>,
<&secure_proxy_main 23>;
bootph-pre-ram;
};
memory@80000000 {
device_type = "memory";
/* 2G RAM */
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
bootph-pre-ram;
};
&a53_0 {
clocks = <&k3_clks 61 0>;
clock-names = "gtc";
};
&cbass_main {
@@ -79,24 +49,6 @@
};
};
&dmsc {
mboxes= <&secure_proxy_main 0>,
<&secure_proxy_main 1>,
<&secure_proxy_main 0>;
mbox-names = "rx", "tx", "notify";
ti,host-id = <35>;
ti,secure-host;
};
&main_timer0 {
/delete-property/ clocks;
/delete-property/ clocks-names;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
clock-frequency = <25000000>;
bootph-pre-ram;
};
&main_bcdma {
ti,sci = <&dm_tifs>;
};

View File

@@ -9,50 +9,12 @@
#include "k3-am62a-ddr.dtsi"
#include "k3-am62a7-sk-u-boot.dtsi"
#include "k3-am62a7-r5.dtsi"
/ {
aliases {
tick-timer = &main_timer0;
remoteproc0 = &sysctrler;
remoteproc1 = &a53_0;
};
a53_0: a53@0 {
compatible = "ti,am654-rproc";
reg = <0x00 0x00a90000 0x00 0x10>;
power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 135 0>;
clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
clock-names = "gtc", "core";
assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
assigned-clock-parents = <&k3_clks 61 2>;
assigned-clock-rates = <200000000>, <1200000000>;
ti,sci = <&dmsc>;
ti,sci-proc-id = <32>;
ti,sci-host-id = <10>;
bootph-pre-ram;
};
dm_tifs: dm-tifs {
compatible = "ti,j721e-dm-sci";
ti,host-id = <36>;
ti,secure-host;
mbox-names = "rx", "tx";
mboxes= <&secure_proxy_main 22>,
<&secure_proxy_main 23>;
bootph-pre-ram;
};
};
&dmsc {
mboxes= <&secure_proxy_main 0>,
<&secure_proxy_main 1>,
<&secure_proxy_main 0>;
mbox-names = "rx", "tx", "notify";
ti,host-id = <35>;
ti,secure-host;
};
&secure_proxy_sa3 {
@@ -61,26 +23,6 @@
bootph-pre-ram;
};
&cbass_main {
sysctrler: sysctrler {
compatible = "ti,am654-tisci-rproc-r5";
mboxes= <&secure_proxy_main 1>,
<&secure_proxy_main 0>,
<&secure_proxy_sa3 0>;
mbox-names = "tx", "rx", "boot_notify";
bootph-pre-ram;
};
};
&main_timer0 {
/delete-property/ clocks;
/delete-property/ clocks-names;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
clock-frequency = <25000000>;
bootph-pre-ram;
};
&wkup_uart0_pins_default {
bootph-pre-ram;
};

View File

@@ -0,0 +1,69 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2026 Texas Instruments Incorporated - https://www.ti.com/
*/
/ {
aliases {
remoteproc0 = &sysctrler;
remoteproc1 = &a53_0;
};
a53_0: a53@0 {
compatible = "ti,am654-rproc";
reg = <0x00 0x00a90000 0x00 0x10>;
power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 135 0>;
clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
clock-names = "gtc", "core";
assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
assigned-clock-parents = <&k3_clks 61 2>;
assigned-clock-rates = <200000000>, <1200000000>;
ti,sci = <&dmsc>;
ti,sci-proc-id = <32>;
ti,sci-host-id = <10>;
bootph-pre-ram;
};
dm_tifs: dm-tifs {
compatible = "ti,j721e-dm-sci";
ti,host-id = <36>;
ti,secure-host;
mbox-names = "rx", "tx";
mboxes= <&secure_proxy_main 22>,
<&secure_proxy_main 23>;
bootph-pre-ram;
};
};
&dmsc {
mboxes= <&secure_proxy_main 0>,
<&secure_proxy_main 1>,
<&secure_proxy_main 0>;
mbox-names = "rx", "tx", "notify";
ti,host-id = <35>;
ti,secure-host;
};
&cbass_main {
sysctrler: sysctrler {
compatible = "ti,am654-tisci-rproc-r5";
mboxes= <&secure_proxy_main 1>,
<&secure_proxy_main 0>,
<&secure_proxy_sa3 0>;
mbox-names = "tx", "rx", "boot_notify";
bootph-pre-ram;
};
};
&main_timer0 {
/delete-property/ clocks;
/delete-property/ clocks-names;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
clock-frequency = <25000000>;
bootph-pre-ram;
};

View File

@@ -3,7 +3,6 @@
* Copyright (C) 2024-2025 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "k3-binman.dtsi"
#include "k3-am62a-sk-binman.dtsi"
#ifdef CONFIG_TARGET_AM62D2_R5_EVM
@@ -72,7 +71,7 @@
description = "k3-am62d2-evm";
ti-secure {
content = <&spl_am62a7_sk_dtb>;
content = <&spl_am62d2_evm_dtb>;
keyfile = "custMpk.pem";
};

View File

@@ -9,74 +9,4 @@
#include "k3-am62a-ddr.dtsi"
#include "k3-am62d2-evm-u-boot.dtsi"
/ {
aliases {
tick-timer = &main_timer0;
remoteproc0 = &sysctrler;
remoteproc1 = &a53_0;
};
a53_0: a53@0 {
compatible = "ti,am654-rproc";
reg = <0x00 0x00a90000 0x00 0x10>;
power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 135 0>;
clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
clock-names = "gtc", "core";
assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
assigned-clock-parents = <&k3_clks 61 2>;
assigned-clock-rates = <200000000>, <1200000000>;
ti,sci = <&dmsc>;
ti,sci-proc-id = <32>;
ti,sci-host-id = <10>;
bootph-pre-ram;
};
dm_tifs: dm-tifs {
compatible = "ti,j721e-dm-sci";
ti,host-id = <36>;
ti,secure-host;
mbox-names = "rx", "tx";
mboxes= <&secure_proxy_main 22>,
<&secure_proxy_main 23>;
bootph-pre-ram;
};
};
&dmsc {
mboxes= <&secure_proxy_main 0>,
<&secure_proxy_main 1>,
<&secure_proxy_main 0>;
mbox-names = "rx", "tx", "notify";
ti,host-id = <35>;
ti,secure-host;
};
&secure_proxy_sa3 {
/* Needed for initial handshake with ROM */
status = "okay";
bootph-pre-ram;
};
&cbass_main {
sysctrler: sysctrler {
compatible = "ti,am654-tisci-rproc-r5";
mboxes= <&secure_proxy_main 1>,
<&secure_proxy_main 0>,
<&secure_proxy_sa3 0>;
mbox-names = "tx", "rx", "boot_notify";
bootph-pre-ram;
};
};
&main_timer0 {
/delete-property/ clocks;
/delete-property/ clocks-names;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
clock-frequency = <25000000>;
bootph-pre-ram;
};
#include "k3-am62d2-r5.dtsi"

View File

@@ -0,0 +1,75 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2026 Texas Instruments Incorporated - https://www.ti.com/
*/
/ {
aliases {
tick-timer = &main_timer0;
remoteproc0 = &sysctrler;
remoteproc1 = &a53_0;
};
a53_0: a53@0 {
compatible = "ti,am654-rproc";
reg = <0x00 0x00a90000 0x00 0x10>;
power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 135 0>;
clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
clock-names = "gtc", "core";
assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
assigned-clock-parents = <&k3_clks 61 2>;
assigned-clock-rates = <200000000>, <1200000000>;
ti,sci = <&dmsc>;
ti,sci-proc-id = <32>;
ti,sci-host-id = <10>;
bootph-pre-ram;
};
dm_tifs: dm-tifs {
compatible = "ti,j721e-dm-sci";
ti,host-id = <36>;
ti,secure-host;
mbox-names = "rx", "tx";
mboxes= <&secure_proxy_main 22>,
<&secure_proxy_main 23>;
bootph-pre-ram;
};
};
&dmsc {
mboxes= <&secure_proxy_main 0>,
<&secure_proxy_main 1>,
<&secure_proxy_main 0>;
mbox-names = "rx", "tx", "notify";
ti,host-id = <35>;
ti,secure-host;
};
&secure_proxy_sa3 {
/* Needed for initial handshake with ROM */
status = "okay";
bootph-pre-ram;
};
&cbass_main {
sysctrler: sysctrler {
compatible = "ti,am654-tisci-rproc-r5";
mboxes= <&secure_proxy_main 1>,
<&secure_proxy_main 0>,
<&secure_proxy_sa3 0>;
mbox-names = "tx", "rx", "boot_notify";
bootph-pre-ram;
};
};
&main_timer0 {
/delete-property/ clocks;
/delete-property/ clocks-names;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
clock-frequency = <25000000>;
bootph-pre-ram;
};

View File

@@ -1,19 +1,20 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* This file was generated with the
* AM62Px SysConfig DDR Configuration Tool for AM64x, AM625, AM623, AM62Ax, AM62Px v0.10.02
* Tue Sep 17 2024 11:03:07 GMT+0530 (India Standard Time)
* AM62Px SysConfig DDR Configuration Tool for AM64x, AM625, AM623, AM62Ax, AM62Px, AM62Dx, AM62Lx v0.10.32
* Fri Jan 30 2026 13:50:37 GMT+0530 (India Standard Time)
* DDR Type: LPDDR4
* F0 = 50MHz F1 = NA F2 = 1600MHz
* Density (per channel): 16Gb
* Number of Ranks: 2
*/
*/
#define DDRSS_PLL_FHS_CNT 5
#define DDRSS_PLL_FREQUENCY_1 800000000
#define DDRSS_PLL_FREQUENCY_2 800000000
#define DDRSS_SDRAM_IDX 17
#define DDRSS_REGION_IDX 17
#define DDRSS_TOOL_VERSION "0.10.32"
#define DDRSS_CTL_0_DATA 0x00000B00
#define DDRSS_CTL_1_DATA 0x00000000
@@ -358,7 +359,7 @@
#define DDRSS_CTL_340_DATA 0x00000000
#define DDRSS_CTL_341_DATA 0x00000000
#define DDRSS_CTL_342_DATA 0x00000000
#define DDRSS_CTL_343_DATA 0x00000000
#define DDRSS_CTL_343_DATA 0x7FFFFFFF
#define DDRSS_CTL_344_DATA 0x00000000
#define DDRSS_CTL_345_DATA 0x00000000
#define DDRSS_CTL_346_DATA 0x00000000
@@ -375,14 +376,14 @@
#define DDRSS_CTL_357_DATA 0x00000000
#define DDRSS_CTL_358_DATA 0x00000000
#define DDRSS_CTL_359_DATA 0x00000000
#define DDRSS_CTL_360_DATA 0x00000000
#define DDRSS_CTL_361_DATA 0x00000000
#define DDRSS_CTL_360_DATA 0xFFFFFFFF
#define DDRSS_CTL_361_DATA 0xFFFF0000
#define DDRSS_CTL_362_DATA 0x00000000
#define DDRSS_CTL_363_DATA 0x00000000
#define DDRSS_CTL_363_DATA 0xFFFFFFFF
#define DDRSS_CTL_364_DATA 0x00000000
#define DDRSS_CTL_365_DATA 0x00000000
#define DDRSS_CTL_366_DATA 0x00000000
#define DDRSS_CTL_367_DATA 0x00000000
#define DDRSS_CTL_365_DATA 0x00FFFFFF
#define DDRSS_CTL_366_DATA 0xFFFF00FF
#define DDRSS_CTL_367_DATA 0x0000FFFF
#define DDRSS_CTL_368_DATA 0x00000000
#define DDRSS_CTL_369_DATA 0x00000000
#define DDRSS_CTL_370_DATA 0x00000000
@@ -669,8 +670,8 @@
#define DDRSS_PI_216_DATA 0x01910100
#define DDRSS_PI_217_DATA 0x01000191
#define DDRSS_PI_218_DATA 0x01910191
#define DDRSS_PI_219_DATA 0x32103200
#define DDRSS_PI_220_DATA 0x01013210
#define DDRSS_PI_219_DATA 0x301B3200
#define DDRSS_PI_220_DATA 0x0101301B
#define DDRSS_PI_221_DATA 0x0A070601
#define DDRSS_PI_222_DATA 0x180F090D
#define DDRSS_PI_223_DATA 0x180F0911

View File

@@ -217,6 +217,38 @@
fit {
images {
atf {
ti-secure {
auth-in-place = <0xa02>;
firewall-1-0 {
insert-template = <&firewall_bg_3>;
id = <1>;
region = <0>;
};
firewall-1-1 {
insert-template = <&firewall_armv8_atf_fg>;
id = <1>;
region = <1>;
};
};
};
tee {
ti-secure {
auth-in-place = <0xa02>;
firewall-1-2 {
insert-template = <&firewall_armv8_optee_fg>;
id = <1>;
region = <2>;
};
};
};
tifsstub-hs {
description = "TIFSSTUB";
type = "firmware";

View File

@@ -9,81 +9,14 @@
#include "k3-am62p-ddr-lp4-50-1600.dtsi"
#include "k3-am62a-ddr.dtsi"
#include "k3-am62p5-r5.dtsi"
/ {
aliases {
remoteproc0 = &sysctrler;
remoteproc1 = &a53_0;
serial0 = &wkup_uart0;
serial2 = &main_uart0;
serial3 = &main_uart1;
};
a53_0: a53@0 {
compatible = "ti,am654-rproc";
reg = <0x00 0x00a90000 0x00 0x10>;
power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 135 0>;
clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
clock-names = "gtc", "core";
assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
assigned-clock-parents = <&k3_clks 61 2>;
assigned-clock-rates = <200000000>, <1200000000>;
ti,sci = <&dmsc>;
ti,sci-proc-id = <32>;
ti,sci-host-id = <10>;
bootph-all;
};
dm_tifs: dm-tifs {
compatible = "ti,j721e-dm-sci";
ti,host-id = <36>;
ti,secure-host;
mbox-names = "rx", "tx";
mboxes= <&secure_proxy_main 20>,
<&secure_proxy_main 21>;
bootph-all;
};
};
&dmsc {
mboxes= <&secure_proxy_main 0>,
<&secure_proxy_main 1>,
<&secure_proxy_main 0>;
mbox-names = "rx", "tx", "notify";
ti,host-id = <35>;
ti,secure-host;
};
&cbass_main {
sa3_secproxy: secproxy@44880000 {
compatible = "ti,am654-secure-proxy";
#mbox-cells = <1>;
reg = <0x00 0x44880000 0x00 0x20000>,
<0x00 0x44860000 0x00 0x20000>,
<0x00 0x43600000 0x00 0x10000>;
reg-names = "rt", "scfg", "target_data";
bootph-all;
};
sysctrler: sysctrler {
compatible = "ti,am654-tisci-rproc-r5";
mboxes= <&secure_proxy_main 1>,
<&secure_proxy_main 0>,
<&sa3_secproxy 0>;
mbox-names = "tx", "rx", "boot_notify";
bootph-all;
};
};
&main_timer0 {
/delete-property/ clocks;
/delete-property/ clocks-names;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
clock-frequency = <25000000>;
};
/* WKUP UART0 is used for DM firmware logs */

View File

@@ -0,0 +1,77 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2026 Texas Instruments Incorporated - https://www.ti.com/
*/
/ {
aliases {
remoteproc0 = &sysctrler;
remoteproc1 = &a53_0;
};
a53_0: a53@0 {
compatible = "ti,am654-rproc";
reg = <0x00 0x00a90000 0x00 0x10>;
power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 135 0>;
clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
clock-names = "gtc", "core";
assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
assigned-clock-parents = <&k3_clks 61 2>;
assigned-clock-rates = <200000000>, <1200000000>;
ti,sci = <&dmsc>;
ti,sci-proc-id = <32>;
ti,sci-host-id = <10>;
bootph-all;
};
dm_tifs: dm-tifs {
compatible = "ti,j721e-dm-sci";
ti,host-id = <36>;
ti,secure-host;
mbox-names = "rx", "tx";
mboxes= <&secure_proxy_main 20>,
<&secure_proxy_main 21>;
bootph-all;
};
};
&cbass_main {
sa3_secproxy: secproxy@44880000 {
compatible = "ti,am654-secure-proxy";
#mbox-cells = <1>;
reg = <0x00 0x44880000 0x00 0x20000>,
<0x00 0x44860000 0x00 0x20000>,
<0x00 0x43600000 0x00 0x10000>;
reg-names = "rt", "scfg", "target_data";
bootph-all;
};
sysctrler: sysctrler {
compatible = "ti,am654-tisci-rproc-r5";
mboxes= <&secure_proxy_main 1>,
<&secure_proxy_main 0>,
<&sa3_secproxy 0>;
mbox-names = "tx", "rx", "boot_notify";
bootph-all;
};
};
&dmsc {
mboxes= <&secure_proxy_main 0>,
<&secure_proxy_main 1>,
<&secure_proxy_main 0>;
mbox-names = "rx", "tx", "notify";
ti,host-id = <35>;
ti,secure-host;
};
&main_timer0 {
/delete-property/ clocks;
/delete-property/ clocks-names;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
clock-frequency = <25000000>;
};

View File

@@ -9,76 +9,10 @@
#include "k3-am62a-ddr.dtsi"
#include "k3-am62p5-verdin-wifi-dev-u-boot.dtsi"
#include "k3-am62p5-r5.dtsi"
/ {
aliases {
remoteproc0 = &sysctrler;
remoteproc1 = &a53_0;
};
a53_0: a53@0 {
compatible = "ti,am654-rproc";
reg = <0x00 0x00a90000 0x00 0x10>;
power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 135 0>;
clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
clock-names = "gtc", "core";
assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>, <&k3_clks 157 36>;
assigned-clock-parents = <&k3_clks 61 2>, <0>, <&k3_clks 157 38>;
assigned-clock-rates = <200000000>, <1200000000>, <25000000>;
ti,sci = <&dmsc>;
ti,sci-proc-id = <32>;
ti,sci-host-id = <10>;
bootph-all;
};
dm_tifs: dm-tifs {
compatible = "ti,j721e-dm-sci";
ti,host-id = <36>;
ti,secure-host;
mbox-names = "rx", "tx";
mboxes= <&secure_proxy_main 20>,
<&secure_proxy_main 21>;
bootph-all;
};
};
&cbass_main {
sa3_secproxy: secproxy@44880000 {
compatible = "ti,am654-secure-proxy";
#mbox-cells = <1>;
reg = <0x00 0x44880000 0x00 0x20000>,
<0x00 0x44860000 0x00 0x20000>,
<0x00 0x43600000 0x00 0x10000>;
reg-names = "rt", "scfg", "target_data";
bootph-all;
};
sysctrler: sysctrler {
compatible = "ti,am654-tisci-rproc-r5";
mboxes= <&secure_proxy_main 1>,
<&secure_proxy_main 0>,
<&sa3_secproxy 0>;
mbox-names = "tx", "rx", "boot_notify";
bootph-all;
};
};
&dmsc {
mboxes= <&secure_proxy_main 0>,
<&secure_proxy_main 1>,
<&secure_proxy_main 0>;
mbox-names = "rx", "tx", "notify";
ti,host-id = <35>;
ti,secure-host;
};
&main_timer0 {
/delete-property/ clocks;
/delete-property/ clocks-names;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
clock-frequency = <25000000>;
&a53_0 {
assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>, <&k3_clks 157 36>;
assigned-clock-parents = <&k3_clks 61 2>, <0>, <&k3_clks 157 38>;
assigned-clock-rates = <200000000>, <1200000000>, <25000000>;
};

View File

@@ -159,6 +159,38 @@
fit {
images {
atf {
ti-secure {
auth-in-place = <0xa02>;
firewall-1-0 {
insert-template = <&firewall_bg_3>;
id = <1>;
region = <0>;
};
firewall-1-1 {
insert-template = <&firewall_armv8_atf_fg>;
id = <1>;
region = <1>;
};
};
};
tee {
ti-secure {
auth-in-place = <0xa02>;
firewall-1-2 {
insert-template = <&firewall_armv8_optee_fg>;
id = <1>;
region = <2>;
};
};
};
tifsstub-hs {
description = "TIFSSTUB";
type = "firmware";

View File

@@ -1,19 +1,20 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* This file was generated with the
* AM623/AM625 SysConfig DDR Configuration Tool for AM64x, AM625, AM623, AM62Ax, AM62Px v0.10.02
* Tue Sep 17 2024 11:00:17 GMT+0530 (India Standard Time)
* AM623/AM625 SysConfig DDR Configuration Tool for AM64x, AM625, AM623, AM62Ax, AM62Px, AM62Dx, AM62Lx v0.10.32
* Fri Jan 30 2026 13:45:31 GMT+0530 (India Standard Time)
* DDR Type: DDR4
* Frequency = 800MHz (1600MTs)
* Density: 16Gb
* Number of Ranks: 1
*/
*/
#define DDRSS_PLL_FHS_CNT 6
#define DDRSS_PLL_FREQUENCY_1 400000000
#define DDRSS_PLL_FREQUENCY_2 400000000
#define DDRSS_SDRAM_IDX 15
#define DDRSS_REGION_IDX 17
#define DDRSS_REGION_IDX 16
#define DDRSS_TOOL_VERSION "0.10.32"
#define DDRSS_CTL_0_DATA 0x00000A00
#define DDRSS_CTL_1_DATA 0x00000000
@@ -53,12 +54,12 @@
#define DDRSS_CTL_35_DATA 0x00000000
#define DDRSS_CTL_36_DATA 0x00000000
#define DDRSS_CTL_37_DATA 0x00000000
#define DDRSS_CTL_38_DATA 0x0400091C
#define DDRSS_CTL_39_DATA 0x1C1C1C1C
#define DDRSS_CTL_40_DATA 0x0400091C
#define DDRSS_CTL_41_DATA 0x1C1C1C1C
#define DDRSS_CTL_42_DATA 0x0400091C
#define DDRSS_CTL_43_DATA 0x1C1C1C1C
#define DDRSS_CTL_38_DATA 0x0000091C
#define DDRSS_CTL_39_DATA 0x18181818
#define DDRSS_CTL_40_DATA 0x0000091C
#define DDRSS_CTL_41_DATA 0x18181818
#define DDRSS_CTL_42_DATA 0x0000091C
#define DDRSS_CTL_43_DATA 0x18181818
#define DDRSS_CTL_44_DATA 0x05050404
#define DDRSS_CTL_45_DATA 0x00002706
#define DDRSS_CTL_46_DATA 0x0602001D
@@ -71,13 +72,13 @@
#define DDRSS_CTL_53_DATA 0x07001D0B
#define DDRSS_CTL_54_DATA 0x00180807
#define DDRSS_CTL_55_DATA 0x0400DB60
#define DDRSS_CTL_56_DATA 0x07070009
#define DDRSS_CTL_56_DATA 0x07070005
#define DDRSS_CTL_57_DATA 0x00001808
#define DDRSS_CTL_58_DATA 0x0400DB60
#define DDRSS_CTL_59_DATA 0x07070009
#define DDRSS_CTL_59_DATA 0x07070005
#define DDRSS_CTL_60_DATA 0x00001808
#define DDRSS_CTL_61_DATA 0x0400DB60
#define DDRSS_CTL_62_DATA 0x03000009
#define DDRSS_CTL_62_DATA 0x03000005
#define DDRSS_CTL_63_DATA 0x0D0C0002
#define DDRSS_CTL_64_DATA 0x0D0C0D0C
#define DDRSS_CTL_65_DATA 0x01010000
@@ -102,8 +103,8 @@
#define DDRSS_CTL_84_DATA 0x00000000
#define DDRSS_CTL_85_DATA 0x00000000
#define DDRSS_CTL_86_DATA 0x00000000
#define DDRSS_CTL_87_DATA 0x00090009
#define DDRSS_CTL_88_DATA 0x00000009
#define DDRSS_CTL_87_DATA 0x00050005
#define DDRSS_CTL_88_DATA 0x00000005
#define DDRSS_CTL_89_DATA 0x00000000
#define DDRSS_CTL_90_DATA 0x00000000
#define DDRSS_CTL_91_DATA 0x00000000
@@ -171,8 +172,8 @@
#define DDRSS_CTL_153_DATA 0x00000000
#define DDRSS_CTL_154_DATA 0x00000000
#define DDRSS_CTL_155_DATA 0x00000000
#define DDRSS_CTL_156_DATA 0x080C0000
#define DDRSS_CTL_157_DATA 0x080C080C
#define DDRSS_CTL_156_DATA 0x08080000
#define DDRSS_CTL_157_DATA 0x08080808
#define DDRSS_CTL_158_DATA 0x08000000
#define DDRSS_CTL_159_DATA 0x00000808
#define DDRSS_CTL_160_DATA 0x000E0000
@@ -251,12 +252,12 @@
#define DDRSS_CTL_233_DATA 0x00000000
#define DDRSS_CTL_234_DATA 0x00000000
#define DDRSS_CTL_235_DATA 0x00000000
#define DDRSS_CTL_236_DATA 0x00001401
#define DDRSS_CTL_237_DATA 0x00001401
#define DDRSS_CTL_238_DATA 0x00001401
#define DDRSS_CTL_239_DATA 0x00001401
#define DDRSS_CTL_240_DATA 0x00001401
#define DDRSS_CTL_241_DATA 0x00001401
#define DDRSS_CTL_236_DATA 0x00001400
#define DDRSS_CTL_237_DATA 0x00001400
#define DDRSS_CTL_238_DATA 0x00001400
#define DDRSS_CTL_239_DATA 0x00001400
#define DDRSS_CTL_240_DATA 0x00001400
#define DDRSS_CTL_241_DATA 0x00001400
#define DDRSS_CTL_242_DATA 0x00000493
#define DDRSS_CTL_243_DATA 0x00000493
#define DDRSS_CTL_244_DATA 0x00000493
@@ -385,9 +386,9 @@
#define DDRSS_CTL_367_DATA 0x00000000
#define DDRSS_CTL_368_DATA 0x00000000
#define DDRSS_CTL_369_DATA 0x00000000
#define DDRSS_CTL_370_DATA 0x0C000000
#define DDRSS_CTL_371_DATA 0x060C0606
#define DDRSS_CTL_372_DATA 0x06060C06
#define DDRSS_CTL_370_DATA 0x08000000
#define DDRSS_CTL_371_DATA 0x06080606
#define DDRSS_CTL_372_DATA 0x06060806
#define DDRSS_CTL_373_DATA 0x00010101
#define DDRSS_CTL_374_DATA 0x02000000
#define DDRSS_CTL_375_DATA 0x05020101
@@ -407,8 +408,8 @@
#define DDRSS_CTL_389_DATA 0x00000200
#define DDRSS_CTL_390_DATA 0x0000DB60
#define DDRSS_CTL_391_DATA 0x0001E780
#define DDRSS_CTL_392_DATA 0x0C0D0302
#define DDRSS_CTL_393_DATA 0x001E090A
#define DDRSS_CTL_392_DATA 0x080D0302
#define DDRSS_CTL_393_DATA 0x001E0506
#define DDRSS_CTL_394_DATA 0x000030C0
#define DDRSS_CTL_395_DATA 0x00000200
#define DDRSS_CTL_396_DATA 0x00000200
@@ -416,8 +417,8 @@
#define DDRSS_CTL_398_DATA 0x00000200
#define DDRSS_CTL_399_DATA 0x0000DB60
#define DDRSS_CTL_400_DATA 0x0001E780
#define DDRSS_CTL_401_DATA 0x0C0D0302
#define DDRSS_CTL_402_DATA 0x001E090A
#define DDRSS_CTL_401_DATA 0x080D0302
#define DDRSS_CTL_402_DATA 0x001E0506
#define DDRSS_CTL_403_DATA 0x000030C0
#define DDRSS_CTL_404_DATA 0x00000200
#define DDRSS_CTL_405_DATA 0x00000200
@@ -425,8 +426,8 @@
#define DDRSS_CTL_407_DATA 0x00000200
#define DDRSS_CTL_408_DATA 0x0000DB60
#define DDRSS_CTL_409_DATA 0x0001E780
#define DDRSS_CTL_410_DATA 0x0C0D0302
#define DDRSS_CTL_411_DATA 0x0000090A
#define DDRSS_CTL_410_DATA 0x080D0302
#define DDRSS_CTL_411_DATA 0x00000506
#define DDRSS_CTL_412_DATA 0x00000000
#define DDRSS_CTL_413_DATA 0x0302000A
#define DDRSS_CTL_414_DATA 0x01000500
@@ -605,14 +606,14 @@
#define DDRSS_PI_164_DATA 0x00007800
#define DDRSS_PI_165_DATA 0x00780078
#define DDRSS_PI_166_DATA 0x00141414
#define DDRSS_PI_167_DATA 0x0000003A
#define DDRSS_PI_168_DATA 0x0000003A
#define DDRSS_PI_169_DATA 0x0004003A
#define DDRSS_PI_167_DATA 0x00000036
#define DDRSS_PI_168_DATA 0x00000036
#define DDRSS_PI_169_DATA 0x00040036
#define DDRSS_PI_170_DATA 0x04000400
#define DDRSS_PI_171_DATA 0xC8040009
#define DDRSS_PI_172_DATA 0x0400091C
#define DDRSS_PI_171_DATA 0xC8000009
#define DDRSS_PI_172_DATA 0x0000091C
#define DDRSS_PI_173_DATA 0x00091CC8
#define DDRSS_PI_174_DATA 0x001CC804
#define DDRSS_PI_174_DATA 0x001CC800
#define DDRSS_PI_175_DATA 0x00000118
#define DDRSS_PI_176_DATA 0x00001860
#define DDRSS_PI_177_DATA 0x00000118
@@ -622,8 +623,8 @@
#define DDRSS_PI_181_DATA 0x01010404
#define DDRSS_PI_182_DATA 0x00001901
#define DDRSS_PI_183_DATA 0x00190019
#define DDRSS_PI_184_DATA 0x010C010C
#define DDRSS_PI_185_DATA 0x0000010C
#define DDRSS_PI_184_DATA 0x01080108
#define DDRSS_PI_185_DATA 0x00000108
#define DDRSS_PI_186_DATA 0x00000000
#define DDRSS_PI_187_DATA 0x05000000
#define DDRSS_PI_188_DATA 0x01010505
@@ -631,9 +632,9 @@
#define DDRSS_PI_190_DATA 0x00181818
#define DDRSS_PI_191_DATA 0x00000000
#define DDRSS_PI_192_DATA 0x00000000
#define DDRSS_PI_193_DATA 0x0D000000
#define DDRSS_PI_194_DATA 0x0A0A0D0D
#define DDRSS_PI_195_DATA 0x0303030A
#define DDRSS_PI_193_DATA 0x09000000
#define DDRSS_PI_194_DATA 0x06060909
#define DDRSS_PI_195_DATA 0x03030306
#define DDRSS_PI_196_DATA 0x00000000
#define DDRSS_PI_197_DATA 0x00000000
#define DDRSS_PI_198_DATA 0x00000000
@@ -659,32 +660,32 @@
#define DDRSS_PI_218_DATA 0x001600C8
#define DDRSS_PI_219_DATA 0x001600C8
#define DDRSS_PI_220_DATA 0x010100C8
#define DDRSS_PI_221_DATA 0x00001B01
#define DDRSS_PI_221_DATA 0x00001701
#define DDRSS_PI_222_DATA 0x1F0F0053
#define DDRSS_PI_223_DATA 0x05000001
#define DDRSS_PI_224_DATA 0x001B0A0D
#define DDRSS_PI_224_DATA 0x00170A09
#define DDRSS_PI_225_DATA 0x1F0F0053
#define DDRSS_PI_226_DATA 0x05000001
#define DDRSS_PI_227_DATA 0x001B0A0D
#define DDRSS_PI_227_DATA 0x00170A09
#define DDRSS_PI_228_DATA 0x1F0F0053
#define DDRSS_PI_229_DATA 0x05000001
#define DDRSS_PI_230_DATA 0x00010A0D
#define DDRSS_PI_230_DATA 0x00010A09
#define DDRSS_PI_231_DATA 0x0C0B0700
#define DDRSS_PI_232_DATA 0x000D0605
#define DDRSS_PI_233_DATA 0x0000C570
#define DDRSS_PI_234_DATA 0x0000001D
#define DDRSS_PI_235_DATA 0x180A0800
#define DDRSS_PI_236_DATA 0x0B071C1C
#define DDRSS_PI_236_DATA 0x0B071818
#define DDRSS_PI_237_DATA 0x0D06050C
#define DDRSS_PI_238_DATA 0x0000C570
#define DDRSS_PI_239_DATA 0x0000001D
#define DDRSS_PI_240_DATA 0x180A0800
#define DDRSS_PI_241_DATA 0x0B071C1C
#define DDRSS_PI_241_DATA 0x0B071818
#define DDRSS_PI_242_DATA 0x0D06050C
#define DDRSS_PI_243_DATA 0x0000C570
#define DDRSS_PI_244_DATA 0x0000001D
#define DDRSS_PI_245_DATA 0x180A0800
#define DDRSS_PI_246_DATA 0x00001C1C
#define DDRSS_PI_246_DATA 0x00001818
#define DDRSS_PI_247_DATA 0x000030C0
#define DDRSS_PI_248_DATA 0x0001E780
#define DDRSS_PI_249_DATA 0x000030C0
@@ -695,8 +696,8 @@
#define DDRSS_PI_254_DATA 0x03030255
#define DDRSS_PI_255_DATA 0x00025503
#define DDRSS_PI_256_DATA 0x02550255
#define DDRSS_PI_257_DATA 0x0C080C08
#define DDRSS_PI_258_DATA 0x00000C08
#define DDRSS_PI_257_DATA 0x08080808
#define DDRSS_PI_258_DATA 0x00000808
#define DDRSS_PI_259_DATA 0x000890B8
#define DDRSS_PI_260_DATA 0x00000000
#define DDRSS_PI_261_DATA 0x00000000
@@ -740,7 +741,7 @@
#define DDRSS_PI_299_DATA 0x00000000
#define DDRSS_PI_300_DATA 0x00000000
#define DDRSS_PI_301_DATA 0x00000000
#define DDRSS_PI_302_DATA 0x00001401
#define DDRSS_PI_302_DATA 0x00001400
#define DDRSS_PI_303_DATA 0x00000493
#define DDRSS_PI_304_DATA 0x00000000
#define DDRSS_PI_305_DATA 0x00000424
@@ -748,7 +749,7 @@
#define DDRSS_PI_307_DATA 0x00000000
#define DDRSS_PI_308_DATA 0x00000000
#define DDRSS_PI_309_DATA 0x00000000
#define DDRSS_PI_310_DATA 0x00001401
#define DDRSS_PI_310_DATA 0x00001400
#define DDRSS_PI_311_DATA 0x00000493
#define DDRSS_PI_312_DATA 0x00000000
#define DDRSS_PI_313_DATA 0x00000424
@@ -756,7 +757,7 @@
#define DDRSS_PI_315_DATA 0x00000000
#define DDRSS_PI_316_DATA 0x00000000
#define DDRSS_PI_317_DATA 0x00000000
#define DDRSS_PI_318_DATA 0x00001401
#define DDRSS_PI_318_DATA 0x00001400
#define DDRSS_PI_319_DATA 0x00000493
#define DDRSS_PI_320_DATA 0x00000000
#define DDRSS_PI_321_DATA 0x00000424
@@ -764,7 +765,7 @@
#define DDRSS_PI_323_DATA 0x00000000
#define DDRSS_PI_324_DATA 0x00000000
#define DDRSS_PI_325_DATA 0x00000000
#define DDRSS_PI_326_DATA 0x00001401
#define DDRSS_PI_326_DATA 0x00001400
#define DDRSS_PI_327_DATA 0x00000493
#define DDRSS_PI_328_DATA 0x00000000
#define DDRSS_PI_329_DATA 0x00000424
@@ -772,7 +773,7 @@
#define DDRSS_PI_331_DATA 0x00000000
#define DDRSS_PI_332_DATA 0x00000000
#define DDRSS_PI_333_DATA 0x00000000
#define DDRSS_PI_334_DATA 0x00001401
#define DDRSS_PI_334_DATA 0x00001400
#define DDRSS_PI_335_DATA 0x00000493
#define DDRSS_PI_336_DATA 0x00000000
#define DDRSS_PI_337_DATA 0x00000424
@@ -780,7 +781,7 @@
#define DDRSS_PI_339_DATA 0x00000000
#define DDRSS_PI_340_DATA 0x00000000
#define DDRSS_PI_341_DATA 0x00000000
#define DDRSS_PI_342_DATA 0x00001401
#define DDRSS_PI_342_DATA 0x00001400
#define DDRSS_PI_343_DATA 0x00000493
#define DDRSS_PI_344_DATA 0x00000000
#define DDRSS_PHY_0_DATA 0x04C00000
@@ -2102,7 +2103,7 @@
#define DDRSS_PHY_1316_DATA 0x00000000
#define DDRSS_PHY_1317_DATA 0x00000000
#define DDRSS_PHY_1318_DATA 0x00000000
#define DDRSS_PHY_1319_DATA 0x07070001
#define DDRSS_PHY_1319_DATA 0x07030001
#define DDRSS_PHY_1320_DATA 0x00005400
#define DDRSS_PHY_1321_DATA 0x000040A2
#define DDRSS_PHY_1322_DATA 0x00024410

View File

@@ -1,19 +1,20 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* This file was generated with the
* AM64x SysConfig DDR Configuration Tool for AM64x, AM625, AM623, AM62Ax, AM62Px v0.10.02
* Tue Sep 17 2024 11:01:31 GMT+0530 (India Standard Time)
* AM64x SysConfig DDR Configuration Tool for AM64x, AM625, AM623, AM62Ax, AM62Px, AM62Dx, AM62Lx v0.10.32
* Fri Jan 30 2026 13:47:49 GMT+0530 (India Standard Time)
* DDR Type: DDR4
* Frequency = 800MHz (1600MTs)
* Density: 16Gb
* Number of Ranks: 1
*/
*/
#define DDRSS_PLL_FHS_CNT 6
#define DDRSS_PLL_FREQUENCY_1 400000000
#define DDRSS_PLL_FREQUENCY_2 400000000
#define DDRSS_SDRAM_IDX 15
#define DDRSS_REGION_IDX 15
#define DDRSS_TOOL_VERSION "0.10.32"
#define DDRSS_CTL_0_DATA 0x00000A00
#define DDRSS_CTL_1_DATA 0x00000000
@@ -53,12 +54,12 @@
#define DDRSS_CTL_35_DATA 0x00000000
#define DDRSS_CTL_36_DATA 0x00000000
#define DDRSS_CTL_37_DATA 0x00000000
#define DDRSS_CTL_38_DATA 0x0400091C
#define DDRSS_CTL_39_DATA 0x1C1C1C1C
#define DDRSS_CTL_40_DATA 0x0400091C
#define DDRSS_CTL_41_DATA 0x1C1C1C1C
#define DDRSS_CTL_42_DATA 0x0400091C
#define DDRSS_CTL_43_DATA 0x1C1C1C1C
#define DDRSS_CTL_38_DATA 0x0000091C
#define DDRSS_CTL_39_DATA 0x18181818
#define DDRSS_CTL_40_DATA 0x0000091C
#define DDRSS_CTL_41_DATA 0x18181818
#define DDRSS_CTL_42_DATA 0x0000091C
#define DDRSS_CTL_43_DATA 0x18181818
#define DDRSS_CTL_44_DATA 0x05050404
#define DDRSS_CTL_45_DATA 0x00002706
#define DDRSS_CTL_46_DATA 0x0602001D
@@ -71,13 +72,13 @@
#define DDRSS_CTL_53_DATA 0x07001D0B
#define DDRSS_CTL_54_DATA 0x00180807
#define DDRSS_CTL_55_DATA 0x0400DB60
#define DDRSS_CTL_56_DATA 0x07070009
#define DDRSS_CTL_56_DATA 0x07070005
#define DDRSS_CTL_57_DATA 0x00001808
#define DDRSS_CTL_58_DATA 0x0400DB60
#define DDRSS_CTL_59_DATA 0x07070009
#define DDRSS_CTL_59_DATA 0x07070005
#define DDRSS_CTL_60_DATA 0x00001808
#define DDRSS_CTL_61_DATA 0x0400DB60
#define DDRSS_CTL_62_DATA 0x03000009
#define DDRSS_CTL_62_DATA 0x03000005
#define DDRSS_CTL_63_DATA 0x0D0C0002
#define DDRSS_CTL_64_DATA 0x0D0C0D0C
#define DDRSS_CTL_65_DATA 0x01010000
@@ -102,8 +103,8 @@
#define DDRSS_CTL_84_DATA 0x00000000
#define DDRSS_CTL_85_DATA 0x00000000
#define DDRSS_CTL_86_DATA 0x00000000
#define DDRSS_CTL_87_DATA 0x00090009
#define DDRSS_CTL_88_DATA 0x00000009
#define DDRSS_CTL_87_DATA 0x00050005
#define DDRSS_CTL_88_DATA 0x00000005
#define DDRSS_CTL_89_DATA 0x00000000
#define DDRSS_CTL_90_DATA 0x00000000
#define DDRSS_CTL_91_DATA 0x00000000
@@ -171,8 +172,8 @@
#define DDRSS_CTL_153_DATA 0x00000000
#define DDRSS_CTL_154_DATA 0x00000000
#define DDRSS_CTL_155_DATA 0x00000000
#define DDRSS_CTL_156_DATA 0x080C0000
#define DDRSS_CTL_157_DATA 0x080C080C
#define DDRSS_CTL_156_DATA 0x08080000
#define DDRSS_CTL_157_DATA 0x08080808
#define DDRSS_CTL_158_DATA 0x00000000
#define DDRSS_CTL_159_DATA 0x07010A09
#define DDRSS_CTL_160_DATA 0x000E0A09
@@ -251,12 +252,12 @@
#define DDRSS_CTL_233_DATA 0x00000000
#define DDRSS_CTL_234_DATA 0x00000000
#define DDRSS_CTL_235_DATA 0x00000000
#define DDRSS_CTL_236_DATA 0x00001401
#define DDRSS_CTL_237_DATA 0x00001401
#define DDRSS_CTL_238_DATA 0x00001401
#define DDRSS_CTL_239_DATA 0x00001401
#define DDRSS_CTL_240_DATA 0x00001401
#define DDRSS_CTL_241_DATA 0x00001401
#define DDRSS_CTL_236_DATA 0x00001400
#define DDRSS_CTL_237_DATA 0x00001400
#define DDRSS_CTL_238_DATA 0x00001400
#define DDRSS_CTL_239_DATA 0x00001400
#define DDRSS_CTL_240_DATA 0x00001400
#define DDRSS_CTL_241_DATA 0x00001400
#define DDRSS_CTL_242_DATA 0x00000493
#define DDRSS_CTL_243_DATA 0x00000493
#define DDRSS_CTL_244_DATA 0x00000493
@@ -385,9 +386,9 @@
#define DDRSS_CTL_367_DATA 0x00000000
#define DDRSS_CTL_368_DATA 0x00000000
#define DDRSS_CTL_369_DATA 0x00000000
#define DDRSS_CTL_370_DATA 0x0C000000
#define DDRSS_CTL_371_DATA 0x060C0606
#define DDRSS_CTL_372_DATA 0x06060C06
#define DDRSS_CTL_370_DATA 0x08000000
#define DDRSS_CTL_371_DATA 0x06080606
#define DDRSS_CTL_372_DATA 0x06060806
#define DDRSS_CTL_373_DATA 0x00010101
#define DDRSS_CTL_374_DATA 0x02000000
#define DDRSS_CTL_375_DATA 0x05020101
@@ -407,8 +408,8 @@
#define DDRSS_CTL_389_DATA 0x00000200
#define DDRSS_CTL_390_DATA 0x0000DB60
#define DDRSS_CTL_391_DATA 0x0001E780
#define DDRSS_CTL_392_DATA 0x0C0D0302
#define DDRSS_CTL_393_DATA 0x001E090A
#define DDRSS_CTL_392_DATA 0x080D0302
#define DDRSS_CTL_393_DATA 0x001E0506
#define DDRSS_CTL_394_DATA 0x000030C0
#define DDRSS_CTL_395_DATA 0x00000200
#define DDRSS_CTL_396_DATA 0x00000200
@@ -416,8 +417,8 @@
#define DDRSS_CTL_398_DATA 0x00000200
#define DDRSS_CTL_399_DATA 0x0000DB60
#define DDRSS_CTL_400_DATA 0x0001E780
#define DDRSS_CTL_401_DATA 0x0C0D0302
#define DDRSS_CTL_402_DATA 0x001E090A
#define DDRSS_CTL_401_DATA 0x080D0302
#define DDRSS_CTL_402_DATA 0x001E0506
#define DDRSS_CTL_403_DATA 0x000030C0
#define DDRSS_CTL_404_DATA 0x00000200
#define DDRSS_CTL_405_DATA 0x00000200
@@ -425,8 +426,8 @@
#define DDRSS_CTL_407_DATA 0x00000200
#define DDRSS_CTL_408_DATA 0x0000DB60
#define DDRSS_CTL_409_DATA 0x0001E780
#define DDRSS_CTL_410_DATA 0x0C0D0302
#define DDRSS_CTL_411_DATA 0x0000090A
#define DDRSS_CTL_410_DATA 0x080D0302
#define DDRSS_CTL_411_DATA 0x00000506
#define DDRSS_CTL_412_DATA 0x00000000
#define DDRSS_CTL_413_DATA 0x0302000A
#define DDRSS_CTL_414_DATA 0x01000500
@@ -605,14 +606,14 @@
#define DDRSS_PI_164_DATA 0x00007800
#define DDRSS_PI_165_DATA 0x00780078
#define DDRSS_PI_166_DATA 0x00141414
#define DDRSS_PI_167_DATA 0x0000003A
#define DDRSS_PI_168_DATA 0x0000003A
#define DDRSS_PI_169_DATA 0x0004003A
#define DDRSS_PI_167_DATA 0x00000036
#define DDRSS_PI_168_DATA 0x00000036
#define DDRSS_PI_169_DATA 0x00040036
#define DDRSS_PI_170_DATA 0x04000400
#define DDRSS_PI_171_DATA 0xC8040009
#define DDRSS_PI_172_DATA 0x0400091C
#define DDRSS_PI_171_DATA 0xC8000009
#define DDRSS_PI_172_DATA 0x0000091C
#define DDRSS_PI_173_DATA 0x00091CC8
#define DDRSS_PI_174_DATA 0x001CC804
#define DDRSS_PI_174_DATA 0x001CC800
#define DDRSS_PI_175_DATA 0x00000118
#define DDRSS_PI_176_DATA 0x00001860
#define DDRSS_PI_177_DATA 0x00000118
@@ -622,8 +623,8 @@
#define DDRSS_PI_181_DATA 0x01010404
#define DDRSS_PI_182_DATA 0x00001901
#define DDRSS_PI_183_DATA 0x00190019
#define DDRSS_PI_184_DATA 0x010C010C
#define DDRSS_PI_185_DATA 0x0000010C
#define DDRSS_PI_184_DATA 0x01080108
#define DDRSS_PI_185_DATA 0x00000108
#define DDRSS_PI_186_DATA 0x00000000
#define DDRSS_PI_187_DATA 0x05000000
#define DDRSS_PI_188_DATA 0x01010505
@@ -631,9 +632,9 @@
#define DDRSS_PI_190_DATA 0x00181818
#define DDRSS_PI_191_DATA 0x00000000
#define DDRSS_PI_192_DATA 0x00000000
#define DDRSS_PI_193_DATA 0x0D000000
#define DDRSS_PI_194_DATA 0x0A0A0D0D
#define DDRSS_PI_195_DATA 0x0303030A
#define DDRSS_PI_193_DATA 0x09000000
#define DDRSS_PI_194_DATA 0x06060909
#define DDRSS_PI_195_DATA 0x03030306
#define DDRSS_PI_196_DATA 0x00000000
#define DDRSS_PI_197_DATA 0x00000000
#define DDRSS_PI_198_DATA 0x00000000
@@ -659,32 +660,32 @@
#define DDRSS_PI_218_DATA 0x001600C8
#define DDRSS_PI_219_DATA 0x001600C8
#define DDRSS_PI_220_DATA 0x010100C8
#define DDRSS_PI_221_DATA 0x00001B01
#define DDRSS_PI_221_DATA 0x00001701
#define DDRSS_PI_222_DATA 0x1F0F0053
#define DDRSS_PI_223_DATA 0x05000001
#define DDRSS_PI_224_DATA 0x001B0A0D
#define DDRSS_PI_224_DATA 0x00170A09
#define DDRSS_PI_225_DATA 0x1F0F0053
#define DDRSS_PI_226_DATA 0x05000001
#define DDRSS_PI_227_DATA 0x001B0A0D
#define DDRSS_PI_227_DATA 0x00170A09
#define DDRSS_PI_228_DATA 0x1F0F0053
#define DDRSS_PI_229_DATA 0x05000001
#define DDRSS_PI_230_DATA 0x00010A0D
#define DDRSS_PI_230_DATA 0x00010A09
#define DDRSS_PI_231_DATA 0x0C0B0700
#define DDRSS_PI_232_DATA 0x000D0605
#define DDRSS_PI_233_DATA 0x0000C570
#define DDRSS_PI_234_DATA 0x0000001D
#define DDRSS_PI_235_DATA 0x180A0800
#define DDRSS_PI_236_DATA 0x0B071C1C
#define DDRSS_PI_236_DATA 0x0B071818
#define DDRSS_PI_237_DATA 0x0D06050C
#define DDRSS_PI_238_DATA 0x0000C570
#define DDRSS_PI_239_DATA 0x0000001D
#define DDRSS_PI_240_DATA 0x180A0800
#define DDRSS_PI_241_DATA 0x0B071C1C
#define DDRSS_PI_241_DATA 0x0B071818
#define DDRSS_PI_242_DATA 0x0D06050C
#define DDRSS_PI_243_DATA 0x0000C570
#define DDRSS_PI_244_DATA 0x0000001D
#define DDRSS_PI_245_DATA 0x180A0800
#define DDRSS_PI_246_DATA 0x00001C1C
#define DDRSS_PI_246_DATA 0x00001818
#define DDRSS_PI_247_DATA 0x000030C0
#define DDRSS_PI_248_DATA 0x0001E780
#define DDRSS_PI_249_DATA 0x000030C0
@@ -695,8 +696,8 @@
#define DDRSS_PI_254_DATA 0x03030255
#define DDRSS_PI_255_DATA 0x00025503
#define DDRSS_PI_256_DATA 0x02550255
#define DDRSS_PI_257_DATA 0x0C080C08
#define DDRSS_PI_258_DATA 0x00000C08
#define DDRSS_PI_257_DATA 0x08080808
#define DDRSS_PI_258_DATA 0x00000808
#define DDRSS_PI_259_DATA 0x000890B8
#define DDRSS_PI_260_DATA 0x00000000
#define DDRSS_PI_261_DATA 0x00000000
@@ -740,7 +741,7 @@
#define DDRSS_PI_299_DATA 0x00000000
#define DDRSS_PI_300_DATA 0x00000000
#define DDRSS_PI_301_DATA 0x00000000
#define DDRSS_PI_302_DATA 0x00001401
#define DDRSS_PI_302_DATA 0x00001400
#define DDRSS_PI_303_DATA 0x00000493
#define DDRSS_PI_304_DATA 0x00000000
#define DDRSS_PI_305_DATA 0x00000424
@@ -748,7 +749,7 @@
#define DDRSS_PI_307_DATA 0x00000000
#define DDRSS_PI_308_DATA 0x00000000
#define DDRSS_PI_309_DATA 0x00000000
#define DDRSS_PI_310_DATA 0x00001401
#define DDRSS_PI_310_DATA 0x00001400
#define DDRSS_PI_311_DATA 0x00000493
#define DDRSS_PI_312_DATA 0x00000000
#define DDRSS_PI_313_DATA 0x00000424
@@ -756,7 +757,7 @@
#define DDRSS_PI_315_DATA 0x00000000
#define DDRSS_PI_316_DATA 0x00000000
#define DDRSS_PI_317_DATA 0x00000000
#define DDRSS_PI_318_DATA 0x00001401
#define DDRSS_PI_318_DATA 0x00001400
#define DDRSS_PI_319_DATA 0x00000493
#define DDRSS_PI_320_DATA 0x00000000
#define DDRSS_PI_321_DATA 0x00000424
@@ -764,7 +765,7 @@
#define DDRSS_PI_323_DATA 0x00000000
#define DDRSS_PI_324_DATA 0x00000000
#define DDRSS_PI_325_DATA 0x00000000
#define DDRSS_PI_326_DATA 0x00001401
#define DDRSS_PI_326_DATA 0x00001400
#define DDRSS_PI_327_DATA 0x00000493
#define DDRSS_PI_328_DATA 0x00000000
#define DDRSS_PI_329_DATA 0x00000424
@@ -772,7 +773,7 @@
#define DDRSS_PI_331_DATA 0x00000000
#define DDRSS_PI_332_DATA 0x00000000
#define DDRSS_PI_333_DATA 0x00000000
#define DDRSS_PI_334_DATA 0x00001401
#define DDRSS_PI_334_DATA 0x00001400
#define DDRSS_PI_335_DATA 0x00000493
#define DDRSS_PI_336_DATA 0x00000000
#define DDRSS_PI_337_DATA 0x00000424
@@ -780,7 +781,7 @@
#define DDRSS_PI_339_DATA 0x00000000
#define DDRSS_PI_340_DATA 0x00000000
#define DDRSS_PI_341_DATA 0x00000000
#define DDRSS_PI_342_DATA 0x00001401
#define DDRSS_PI_342_DATA 0x00001400
#define DDRSS_PI_343_DATA 0x00000493
#define DDRSS_PI_344_DATA 0x00000000
#define DDRSS_PHY_0_DATA 0x04C00000
@@ -2102,7 +2103,7 @@
#define DDRSS_PHY_1316_DATA 0x00000000
#define DDRSS_PHY_1317_DATA 0x00000000
#define DDRSS_PHY_1318_DATA 0x00000000
#define DDRSS_PHY_1319_DATA 0x07070001
#define DDRSS_PHY_1319_DATA 0x07030001
#define DDRSS_PHY_1320_DATA 0x00005400
#define DDRSS_PHY_1321_DATA 0x000040A2
#define DDRSS_PHY_1322_DATA 0x00024410

View File

@@ -1,8 +1,8 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* This file was generated with the
* AM64x SysConfig DDR Subsystem Register Configuration Tool v0.08.10
* Wed Dec 15 2021 14:35:01 GMT-0800 (Pacific Standard Time)
* AM64x SysConfig DDR Subsystem Register Configuration Tool v0.09.05
* Fri Feb 03 2023 11:04:00 GMT+0100 (Mitteleuropäische Normalzeit)
* DDR Type: DDR4
* Frequency = 800MHz (1600MTs)
* Density: 16Gb
@@ -13,6 +13,7 @@
#define DDRSS_PLL_FREQUENCY_1 400000000
#define DDRSS_PLL_FREQUENCY_2 400000000
#define DDRSS_CTL_0_DATA 0x00000A00
#define DDRSS_CTL_1_DATA 0x00000000
#define DDRSS_CTL_2_DATA 0x00000000
@@ -58,39 +59,39 @@
#define DDRSS_CTL_42_DATA 0x0400091C
#define DDRSS_CTL_43_DATA 0x1C1C1C1C
#define DDRSS_CTL_44_DATA 0x05050404
#define DDRSS_CTL_45_DATA 0x00002806
#define DDRSS_CTL_45_DATA 0x00002706
#define DDRSS_CTL_46_DATA 0x0602001D
#define DDRSS_CTL_47_DATA 0x05001D0C
#define DDRSS_CTL_48_DATA 0x00280605
#define DDRSS_CTL_47_DATA 0x05001D0B
#define DDRSS_CTL_48_DATA 0x00270605
#define DDRSS_CTL_49_DATA 0x0602001D
#define DDRSS_CTL_50_DATA 0x05001D0C
#define DDRSS_CTL_51_DATA 0x00280605
#define DDRSS_CTL_50_DATA 0x05001D0B
#define DDRSS_CTL_51_DATA 0x00270605
#define DDRSS_CTL_52_DATA 0x0602001D
#define DDRSS_CTL_53_DATA 0x07001D0C
#define DDRSS_CTL_53_DATA 0x07001D0B
#define DDRSS_CTL_54_DATA 0x00180807
#define DDRSS_CTL_55_DATA 0x0400DB60
#define DDRSS_CTL_55_DATA 0x04006DB0
#define DDRSS_CTL_56_DATA 0x07070009
#define DDRSS_CTL_57_DATA 0x00001808
#define DDRSS_CTL_58_DATA 0x0400DB60
#define DDRSS_CTL_58_DATA 0x04006DB0
#define DDRSS_CTL_59_DATA 0x07070009
#define DDRSS_CTL_60_DATA 0x00001808
#define DDRSS_CTL_61_DATA 0x0400DB60
#define DDRSS_CTL_61_DATA 0x04006DB0
#define DDRSS_CTL_62_DATA 0x03000009
#define DDRSS_CTL_63_DATA 0x0D0D0002
#define DDRSS_CTL_64_DATA 0x0D0D0D0D
#define DDRSS_CTL_63_DATA 0x0D0C0002
#define DDRSS_CTL_64_DATA 0x0D0C0D0C
#define DDRSS_CTL_65_DATA 0x01010000
#define DDRSS_CTL_66_DATA 0x031A1A1A
#define DDRSS_CTL_67_DATA 0x0C0C0C0C
#define DDRSS_CTL_68_DATA 0x00000C0C
#define DDRSS_CTL_66_DATA 0x03191919
#define DDRSS_CTL_67_DATA 0x0B0B0B0B
#define DDRSS_CTL_68_DATA 0x00000B0B
#define DDRSS_CTL_69_DATA 0x00000101
#define DDRSS_CTL_70_DATA 0x00000000
#define DDRSS_CTL_71_DATA 0x01000000
#define DDRSS_CTL_72_DATA 0x01180803
#define DDRSS_CTL_73_DATA 0x00001860
#define DDRSS_CTL_73_DATA 0x00000C30
#define DDRSS_CTL_74_DATA 0x00000118
#define DDRSS_CTL_75_DATA 0x00001860
#define DDRSS_CTL_75_DATA 0x00000C30
#define DDRSS_CTL_76_DATA 0x00000118
#define DDRSS_CTL_77_DATA 0x00001860
#define DDRSS_CTL_77_DATA 0x00000C30
#define DDRSS_CTL_78_DATA 0x00000005
#define DDRSS_CTL_79_DATA 0x00000000
#define DDRSS_CTL_80_DATA 0x00000000
@@ -132,27 +133,27 @@
#define DDRSS_CTL_116_DATA 0x00040003
#define DDRSS_CTL_117_DATA 0x00040005
#define DDRSS_CTL_118_DATA 0x00000000
#define DDRSS_CTL_119_DATA 0x00061800
#define DDRSS_CTL_120_DATA 0x00061800
#define DDRSS_CTL_121_DATA 0x00061800
#define DDRSS_CTL_122_DATA 0x00061800
#define DDRSS_CTL_123_DATA 0x00061800
#define DDRSS_CTL_119_DATA 0x00030C00
#define DDRSS_CTL_120_DATA 0x00030C00
#define DDRSS_CTL_121_DATA 0x00030C00
#define DDRSS_CTL_122_DATA 0x00030C00
#define DDRSS_CTL_123_DATA 0x00030C00
#define DDRSS_CTL_124_DATA 0x00000000
#define DDRSS_CTL_125_DATA 0x0000AAA0
#define DDRSS_CTL_126_DATA 0x00061800
#define DDRSS_CTL_127_DATA 0x00061800
#define DDRSS_CTL_128_DATA 0x00061800
#define DDRSS_CTL_129_DATA 0x00061800
#define DDRSS_CTL_130_DATA 0x00061800
#define DDRSS_CTL_125_DATA 0x00005550
#define DDRSS_CTL_126_DATA 0x00030C00
#define DDRSS_CTL_127_DATA 0x00030C00
#define DDRSS_CTL_128_DATA 0x00030C00
#define DDRSS_CTL_129_DATA 0x00030C00
#define DDRSS_CTL_130_DATA 0x00030C00
#define DDRSS_CTL_131_DATA 0x00000000
#define DDRSS_CTL_132_DATA 0x0000AAA0
#define DDRSS_CTL_133_DATA 0x00061800
#define DDRSS_CTL_134_DATA 0x00061800
#define DDRSS_CTL_135_DATA 0x00061800
#define DDRSS_CTL_136_DATA 0x00061800
#define DDRSS_CTL_137_DATA 0x00061800
#define DDRSS_CTL_132_DATA 0x00005550
#define DDRSS_CTL_133_DATA 0x00030C00
#define DDRSS_CTL_134_DATA 0x00030C00
#define DDRSS_CTL_135_DATA 0x00030C00
#define DDRSS_CTL_136_DATA 0x00030C00
#define DDRSS_CTL_137_DATA 0x00030C00
#define DDRSS_CTL_138_DATA 0x00000000
#define DDRSS_CTL_139_DATA 0x0000AAA0
#define DDRSS_CTL_139_DATA 0x00005550
#define DDRSS_CTL_140_DATA 0x00000000
#define DDRSS_CTL_141_DATA 0x00000000
#define DDRSS_CTL_142_DATA 0x00000000
@@ -178,7 +179,7 @@
#define DDRSS_CTL_162_DATA 0x0E0A0907
#define DDRSS_CTL_163_DATA 0x0A090000
#define DDRSS_CTL_164_DATA 0x0A090701
#define DDRSS_CTL_165_DATA 0x0000000E
#define DDRSS_CTL_165_DATA 0x0000080E
#define DDRSS_CTL_166_DATA 0x00040003
#define DDRSS_CTL_167_DATA 0x00000007
#define DDRSS_CTL_168_DATA 0x00000000
@@ -219,22 +220,22 @@
#define DDRSS_CTL_203_DATA 0x00000000
#define DDRSS_CTL_204_DATA 0x00042400
#define DDRSS_CTL_205_DATA 0x00000301
#define DDRSS_CTL_206_DATA 0x00000000
#define DDRSS_CTL_206_DATA 0x000000C0
#define DDRSS_CTL_207_DATA 0x00000424
#define DDRSS_CTL_208_DATA 0x00000301
#define DDRSS_CTL_209_DATA 0x00000000
#define DDRSS_CTL_209_DATA 0x000000C0
#define DDRSS_CTL_210_DATA 0x00000424
#define DDRSS_CTL_211_DATA 0x00000301
#define DDRSS_CTL_212_DATA 0x00000000
#define DDRSS_CTL_212_DATA 0x000000C0
#define DDRSS_CTL_213_DATA 0x00000424
#define DDRSS_CTL_214_DATA 0x00000301
#define DDRSS_CTL_215_DATA 0x00000000
#define DDRSS_CTL_215_DATA 0x000000C0
#define DDRSS_CTL_216_DATA 0x00000424
#define DDRSS_CTL_217_DATA 0x00000301
#define DDRSS_CTL_218_DATA 0x00000000
#define DDRSS_CTL_218_DATA 0x000000C0
#define DDRSS_CTL_219_DATA 0x00000424
#define DDRSS_CTL_220_DATA 0x00000301
#define DDRSS_CTL_221_DATA 0x00000000
#define DDRSS_CTL_221_DATA 0x000000C0
#define DDRSS_CTL_222_DATA 0x00000000
#define DDRSS_CTL_223_DATA 0x00000000
#define DDRSS_CTL_224_DATA 0x00000000
@@ -243,12 +244,12 @@
#define DDRSS_CTL_227_DATA 0x00000000
#define DDRSS_CTL_228_DATA 0x00000000
#define DDRSS_CTL_229_DATA 0x00000000
#define DDRSS_CTL_230_DATA 0x00000000
#define DDRSS_CTL_231_DATA 0x00000000
#define DDRSS_CTL_232_DATA 0x00000000
#define DDRSS_CTL_233_DATA 0x00000000
#define DDRSS_CTL_234_DATA 0x00000000
#define DDRSS_CTL_235_DATA 0x00000000
#define DDRSS_CTL_230_DATA 0x0000000C
#define DDRSS_CTL_231_DATA 0x0000000C
#define DDRSS_CTL_232_DATA 0x0000000C
#define DDRSS_CTL_233_DATA 0x0000000C
#define DDRSS_CTL_234_DATA 0x0000000C
#define DDRSS_CTL_235_DATA 0x0000000C
#define DDRSS_CTL_236_DATA 0x00001401
#define DDRSS_CTL_237_DATA 0x00001401
#define DDRSS_CTL_238_DATA 0x00001401
@@ -334,7 +335,7 @@
#define DDRSS_CTL_318_DATA 0x3FFF0000
#define DDRSS_CTL_319_DATA 0x000FFF00
#define DDRSS_CTL_320_DATA 0xFFFFFFFF
#define DDRSS_CTL_321_DATA 0x000FFF00
#define DDRSS_CTL_321_DATA 0x00FFFF00
#define DDRSS_CTL_322_DATA 0x0A000000
#define DDRSS_CTL_323_DATA 0x0001FFFF
#define DDRSS_CTL_324_DATA 0x01010101
@@ -343,7 +344,7 @@
#define DDRSS_CTL_327_DATA 0x00000C01
#define DDRSS_CTL_328_DATA 0x00000000
#define DDRSS_CTL_329_DATA 0x00000000
#define DDRSS_CTL_330_DATA 0x01000000
#define DDRSS_CTL_330_DATA 0x00000000
#define DDRSS_CTL_331_DATA 0x01000000
#define DDRSS_CTL_332_DATA 0x00000100
#define DDRSS_CTL_333_DATA 0x00010000
@@ -398,31 +399,31 @@
#define DDRSS_CTL_382_DATA 0x00000000
#define DDRSS_CTL_383_DATA 0x04000100
#define DDRSS_CTL_384_DATA 0x1E000004
#define DDRSS_CTL_385_DATA 0x000030C0
#define DDRSS_CTL_385_DATA 0x00001860
#define DDRSS_CTL_386_DATA 0x00000200
#define DDRSS_CTL_387_DATA 0x00000200
#define DDRSS_CTL_388_DATA 0x00000200
#define DDRSS_CTL_389_DATA 0x00000200
#define DDRSS_CTL_390_DATA 0x0000DB60
#define DDRSS_CTL_391_DATA 0x0001E780
#define DDRSS_CTL_390_DATA 0x00006DB0
#define DDRSS_CTL_391_DATA 0x0000F3C0
#define DDRSS_CTL_392_DATA 0x0C0D0302
#define DDRSS_CTL_393_DATA 0x001E090A
#define DDRSS_CTL_394_DATA 0x000030C0
#define DDRSS_CTL_394_DATA 0x00001860
#define DDRSS_CTL_395_DATA 0x00000200
#define DDRSS_CTL_396_DATA 0x00000200
#define DDRSS_CTL_397_DATA 0x00000200
#define DDRSS_CTL_398_DATA 0x00000200
#define DDRSS_CTL_399_DATA 0x0000DB60
#define DDRSS_CTL_400_DATA 0x0001E780
#define DDRSS_CTL_399_DATA 0x00006DB0
#define DDRSS_CTL_400_DATA 0x0000F3C0
#define DDRSS_CTL_401_DATA 0x0C0D0302
#define DDRSS_CTL_402_DATA 0x001E090A
#define DDRSS_CTL_403_DATA 0x000030C0
#define DDRSS_CTL_403_DATA 0x00001860
#define DDRSS_CTL_404_DATA 0x00000200
#define DDRSS_CTL_405_DATA 0x00000200
#define DDRSS_CTL_406_DATA 0x00000200
#define DDRSS_CTL_407_DATA 0x00000200
#define DDRSS_CTL_408_DATA 0x0000DB60
#define DDRSS_CTL_409_DATA 0x0001E780
#define DDRSS_CTL_408_DATA 0x00006DB0
#define DDRSS_CTL_409_DATA 0x0000F3C0
#define DDRSS_CTL_410_DATA 0x0C0D0302
#define DDRSS_CTL_411_DATA 0x0000090A
#define DDRSS_CTL_412_DATA 0x00000000
@@ -607,16 +608,16 @@
#define DDRSS_PI_168_DATA 0x0000003A
#define DDRSS_PI_169_DATA 0x0004003A
#define DDRSS_PI_170_DATA 0x04000400
#define DDRSS_PI_171_DATA 0x68040009
#define DDRSS_PI_171_DATA 0xC8040009
#define DDRSS_PI_172_DATA 0x0400091C
#define DDRSS_PI_173_DATA 0x00091C68
#define DDRSS_PI_174_DATA 0x001C6804
#define DDRSS_PI_173_DATA 0x00091CC8
#define DDRSS_PI_174_DATA 0x001CC804
#define DDRSS_PI_175_DATA 0x00000118
#define DDRSS_PI_176_DATA 0x00001860
#define DDRSS_PI_176_DATA 0x00000C30
#define DDRSS_PI_177_DATA 0x00000118
#define DDRSS_PI_178_DATA 0x00001860
#define DDRSS_PI_178_DATA 0x00000C30
#define DDRSS_PI_179_DATA 0x00000118
#define DDRSS_PI_180_DATA 0x04001860
#define DDRSS_PI_180_DATA 0x04000C30
#define DDRSS_PI_181_DATA 0x01010404
#define DDRSS_PI_182_DATA 0x00001901
#define DDRSS_PI_183_DATA 0x00190019
@@ -667,28 +668,28 @@
#define DDRSS_PI_228_DATA 0x1F0F0053
#define DDRSS_PI_229_DATA 0x05000001
#define DDRSS_PI_230_DATA 0x00010A0D
#define DDRSS_PI_231_DATA 0x0D0C0700
#define DDRSS_PI_231_DATA 0x0C0B0700
#define DDRSS_PI_232_DATA 0x000D0605
#define DDRSS_PI_233_DATA 0x0000C570
#define DDRSS_PI_233_DATA 0x000062B8
#define DDRSS_PI_234_DATA 0x0000001D
#define DDRSS_PI_235_DATA 0x180A0800
#define DDRSS_PI_236_DATA 0x0C071C1C
#define DDRSS_PI_237_DATA 0x0D06050D
#define DDRSS_PI_238_DATA 0x0000C570
#define DDRSS_PI_236_DATA 0x0B071C1C
#define DDRSS_PI_237_DATA 0x0D06050C
#define DDRSS_PI_238_DATA 0x000062B8
#define DDRSS_PI_239_DATA 0x0000001D
#define DDRSS_PI_240_DATA 0x180A0800
#define DDRSS_PI_241_DATA 0x0C071C1C
#define DDRSS_PI_242_DATA 0x0D06050D
#define DDRSS_PI_243_DATA 0x0000C570
#define DDRSS_PI_241_DATA 0x0B071C1C
#define DDRSS_PI_242_DATA 0x0D06050C
#define DDRSS_PI_243_DATA 0x000062B8
#define DDRSS_PI_244_DATA 0x0000001D
#define DDRSS_PI_245_DATA 0x180A0800
#define DDRSS_PI_246_DATA 0x00001C1C
#define DDRSS_PI_247_DATA 0x000030C0
#define DDRSS_PI_248_DATA 0x0001E780
#define DDRSS_PI_249_DATA 0x000030C0
#define DDRSS_PI_250_DATA 0x0001E780
#define DDRSS_PI_251_DATA 0x000030C0
#define DDRSS_PI_252_DATA 0x0001E780
#define DDRSS_PI_247_DATA 0x00001860
#define DDRSS_PI_248_DATA 0x0000F3C0
#define DDRSS_PI_249_DATA 0x00001860
#define DDRSS_PI_250_DATA 0x0000F3C0
#define DDRSS_PI_251_DATA 0x00001860
#define DDRSS_PI_252_DATA 0x0000F3C0
#define DDRSS_PI_253_DATA 0x02550255
#define DDRSS_PI_254_DATA 0x03030255
#define DDRSS_PI_255_DATA 0x00025503
@@ -735,49 +736,49 @@
#define DDRSS_PI_296_DATA 0x00000000
#define DDRSS_PI_297_DATA 0x00000424
#define DDRSS_PI_298_DATA 0x00000301
#define DDRSS_PI_299_DATA 0x00000000
#define DDRSS_PI_299_DATA 0x000000C0
#define DDRSS_PI_300_DATA 0x00000000
#define DDRSS_PI_301_DATA 0x00000000
#define DDRSS_PI_301_DATA 0x0000000C
#define DDRSS_PI_302_DATA 0x00001401
#define DDRSS_PI_303_DATA 0x00000493
#define DDRSS_PI_304_DATA 0x00000000
#define DDRSS_PI_305_DATA 0x00000424
#define DDRSS_PI_306_DATA 0x00000301
#define DDRSS_PI_307_DATA 0x00000000
#define DDRSS_PI_307_DATA 0x000000C0
#define DDRSS_PI_308_DATA 0x00000000
#define DDRSS_PI_309_DATA 0x00000000
#define DDRSS_PI_309_DATA 0x0000000C
#define DDRSS_PI_310_DATA 0x00001401
#define DDRSS_PI_311_DATA 0x00000493
#define DDRSS_PI_312_DATA 0x00000000
#define DDRSS_PI_313_DATA 0x00000424
#define DDRSS_PI_314_DATA 0x00000301
#define DDRSS_PI_315_DATA 0x00000000
#define DDRSS_PI_315_DATA 0x000000C0
#define DDRSS_PI_316_DATA 0x00000000
#define DDRSS_PI_317_DATA 0x00000000
#define DDRSS_PI_317_DATA 0x0000000C
#define DDRSS_PI_318_DATA 0x00001401
#define DDRSS_PI_319_DATA 0x00000493
#define DDRSS_PI_320_DATA 0x00000000
#define DDRSS_PI_321_DATA 0x00000424
#define DDRSS_PI_322_DATA 0x00000301
#define DDRSS_PI_323_DATA 0x00000000
#define DDRSS_PI_323_DATA 0x000000C0
#define DDRSS_PI_324_DATA 0x00000000
#define DDRSS_PI_325_DATA 0x00000000
#define DDRSS_PI_325_DATA 0x0000000C
#define DDRSS_PI_326_DATA 0x00001401
#define DDRSS_PI_327_DATA 0x00000493
#define DDRSS_PI_328_DATA 0x00000000
#define DDRSS_PI_329_DATA 0x00000424
#define DDRSS_PI_330_DATA 0x00000301
#define DDRSS_PI_331_DATA 0x00000000
#define DDRSS_PI_331_DATA 0x000000C0
#define DDRSS_PI_332_DATA 0x00000000
#define DDRSS_PI_333_DATA 0x00000000
#define DDRSS_PI_333_DATA 0x0000000C
#define DDRSS_PI_334_DATA 0x00001401
#define DDRSS_PI_335_DATA 0x00000493
#define DDRSS_PI_336_DATA 0x00000000
#define DDRSS_PI_337_DATA 0x00000424
#define DDRSS_PI_338_DATA 0x00000301
#define DDRSS_PI_339_DATA 0x00000000
#define DDRSS_PI_339_DATA 0x000000C0
#define DDRSS_PI_340_DATA 0x00000000
#define DDRSS_PI_341_DATA 0x00000000
#define DDRSS_PI_341_DATA 0x0000000C
#define DDRSS_PI_342_DATA 0x00001401
#define DDRSS_PI_343_DATA 0x00000493
#define DDRSS_PI_344_DATA 0x00000000
@@ -901,7 +902,7 @@
#define DDRSS_PHY_117_DATA 0x00800080
#define DDRSS_PHY_118_DATA 0x00800080
#define DDRSS_PHY_119_DATA 0x01000080
#define DDRSS_PHY_120_DATA 0x01A00000
#define DDRSS_PHY_120_DATA 0x01000000
#define DDRSS_PHY_121_DATA 0x00000000
#define DDRSS_PHY_122_DATA 0x00000000
#define DDRSS_PHY_123_DATA 0x00080200
@@ -1157,7 +1158,7 @@
#define DDRSS_PHY_373_DATA 0x00800080
#define DDRSS_PHY_374_DATA 0x00800080
#define DDRSS_PHY_375_DATA 0x01000080
#define DDRSS_PHY_376_DATA 0x01A00000
#define DDRSS_PHY_376_DATA 0x01000000
#define DDRSS_PHY_377_DATA 0x00000000
#define DDRSS_PHY_378_DATA 0x00000000
#define DDRSS_PHY_379_DATA 0x00080200
@@ -2115,7 +2116,7 @@
#define DDRSS_PHY_1331_DATA 0x00004410
#define DDRSS_PHY_1332_DATA 0x00000000
#define DDRSS_PHY_1333_DATA 0x00000046
#define DDRSS_PHY_1334_DATA 0x00010000
#define DDRSS_PHY_1334_DATA 0x00000400
#define DDRSS_PHY_1335_DATA 0x00000008
#define DDRSS_PHY_1336_DATA 0x00000000
#define DDRSS_PHY_1337_DATA 0x00000000
@@ -2152,7 +2153,7 @@
#define DDRSS_PHY_1368_DATA 0x00000002
#define DDRSS_PHY_1369_DATA 0x00000100
#define DDRSS_PHY_1370_DATA 0x00000000
#define DDRSS_PHY_1371_DATA 0x0001F7C0
#define DDRSS_PHY_1371_DATA 0x00000FC3
#define DDRSS_PHY_1372_DATA 0x00020002
#define DDRSS_PHY_1373_DATA 0x00000000
#define DDRSS_PHY_1374_DATA 0x00001142
@@ -2186,4 +2187,4 @@
#define DDRSS_PHY_1402_DATA 0x01990000
#define DDRSS_PHY_1403_DATA 0x300D3F11
#define DDRSS_PHY_1404_DATA 0x01990000
#define DDRSS_PHY_1405_DATA 0x20040001
#define DDRSS_PHY_1405_DATA 0x20040004

View File

@@ -141,6 +141,37 @@
#address-cells = <1>;
images {
atf {
ti-secure {
auth-in-place = <0xa02>;
firewall-24-5 {
insert-template = <&firewall_armv8_atf_fg>;
id = <24>;
region = <5>;
};
};
};
tee {
ti-secure {
auth-in-place = <0xa02>;
firewall-1-0 {
insert-template = <&firewall_bg_3>;
id = <1>;
region = <0>;
};
firewall-1-1 {
insert-template = <&firewall_armv8_optee_fg>;
id = <1>;
region = <1>;
};
};
};
dm {
blob-ext {
filename = "/dev/null";

View File

@@ -8,56 +8,7 @@
#include "k3-am64-ddr.dtsi"
#include "k3-am642-evm-u-boot.dtsi"
/ {
aliases {
remoteproc0 = &sysctrler;
remoteproc1 = &a53_0;
};
a53_0: a53@0 {
compatible = "ti,am654-rproc";
reg = <0x00 0x00a90000 0x00 0x10>;
power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 137 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 135 0>;
clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
clock-names = "gtc", "core";
assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
assigned-clock-parents = <&k3_clks 61 2>;
assigned-clock-rates = <200000000>, <1000000000>;
ti,sci = <&dmsc>;
ti,sci-proc-id = <32>;
ti,sci-host-id = <10>;
bootph-pre-ram;
};
clk_200mhz: dummy-clock-200mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
bootph-pre-ram;
};
};
&cbass_main {
sysctrler: sysctrler {
compatible = "ti,am654-tisci-rproc-r5";
mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>;
mbox-names = "tx", "rx";
bootph-pre-ram;
};
};
&dmsc {
mboxes= <&secure_proxy_main 0>,
<&secure_proxy_main 1>,
<&secure_proxy_main 0>;
mbox-names = "rx", "tx", "notify";
ti,host-id = <35>;
ti,secure-host;
};
#include "k3-am642-r5.dtsi"
&memorycontroller {
vtt-supply = <&vtt_supply>;
@@ -72,33 +23,3 @@
clocks = <&clk_200mhz>;
clock-names = "clk_xin";
};
/* UART is initialized before SYSFW is started
* so we can't do any power-domain/clock operations.
* Delete clock/power-domain properties to avoid
* UART init failure
*/
&main_uart0 {
/delete-property/ power-domains;
/delete-property/ clocks;
/delete-property/ clock-names;
};
/* timer init is called as part of rproc_start() while
* starting System Firmware, so any clock/power-domain
* operations will fail as SYSFW is not yet up and running.
* Delete all clock/power-domain properties to avoid
* timer init failure.
* This is an always on timer at 20MHz.
*/
&main_timer0 {
/delete-property/ clocks;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
/delete-property/ power-domains;
};
&ospi0 {
reg = <0x00 0x0fc40000 0x00 0x100>,
<0x00 0x60000000 0x00 0x8000000>;
};

View File

@@ -14,83 +14,15 @@
#include "k3-am64-ddr.dtsi"
#include "k3-am642-phyboard-electra-rdk-u-boot.dtsi"
#include "k3-am642-r5.dtsi"
/ {
aliases {
ethernet0 = &cpsw3g;
remoteproc0 = &sysctrler;
remoteproc1 = &a53_0;
};
a53_0: a53@0 {
compatible = "ti,am654-rproc";
reg = <0x00 0x00a90000 0x00 0x10>;
power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 137 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 135 0>;
clocks = <&k3_clks 61 0>;
assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
assigned-clock-parents = <&k3_clks 61 2>;
assigned-clock-rates = <200000000>, <1000000000>;
ti,sci = <&dmsc>;
ti,sci-proc-id = <32>;
ti,sci-host-id = <10>;
bootph-pre-ram;
};
clk_200mhz: dummy-clock-200mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
bootph-pre-ram;
};
};
&cbass_main {
sysctrler: sysctrler {
compatible = "ti,am654-tisci-rproc-r5";
mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>;
mbox-names = "tx", "rx";
bootph-pre-ram;
};
};
&dmsc {
mboxes= <&secure_proxy_main 0>,
<&secure_proxy_main 1>,
<&secure_proxy_main 0>;
mbox-names = "rx", "tx", "notify";
ti,host-id = <35>;
ti,secure-host;
};
/* timer init is called as part of rproc_start() while
* starting System Firmware, so any clock/power-domain
* operations will fail as SYSFW is not yet up and running.
* Delete all clock/power-domain properties to avoid
* timer init failure.
* This is an always on timer at 20MHz.
*/
&main_timer0 {
/delete-property/ clocks;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
/delete-property/ power-domains;
};
/* UART is initialized before SYSFW is started
* so we can't do any power-domain/clock operations.
* Delete clock/power-domain properties to avoid
* UART init failure
*/
&main_uart0 {
/delete-property/ power-domains;
/delete-property/ clocks;
/delete-property/ clock-names;
};
&ospi0 {
reg = <0x00 0x0fc40000 0x00 0x100>,
<0x00 0x60000000 0x00 0x08000000>;
&a53_0 {
clock-names = "gtc";
clocks = <&k3_clks 61 0>;
};

View File

@@ -8,56 +8,7 @@
#include "k3-am64-ddr.dtsi"
#include "k3-am642-sk-u-boot.dtsi"
/ {
aliases {
remoteproc0 = &sysctrler;
remoteproc1 = &a53_0;
};
a53_0: a53@0 {
compatible = "ti,am654-rproc";
reg = <0x00 0x00a90000 0x00 0x10>;
power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 137 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 135 0>;
clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
clock-names = "gtc", "core";
assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
assigned-clock-parents = <&k3_clks 61 2>;
assigned-clock-rates = <200000000>, <1000000000>;
ti,sci = <&dmsc>;
ti,sci-proc-id = <32>;
ti,sci-host-id = <10>;
bootph-pre-ram;
};
clk_200mhz: dummy-clock-200mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
bootph-pre-ram;
};
};
&cbass_main {
sysctrler: sysctrler {
compatible = "ti,am654-tisci-rproc-r5";
mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>;
mbox-names = "tx", "rx";
bootph-pre-ram;
};
};
&dmsc {
mboxes= <&secure_proxy_main 0>,
<&secure_proxy_main 1>,
<&secure_proxy_main 0>;
mbox-names = "rx", "tx", "notify";
ti,host-id = <35>;
ti,secure-host;
};
#include "k3-am642-r5.dtsi"
&sdhci1 {
clocks = <&clk_200mhz>;
@@ -67,33 +18,3 @@
&serdes_wiz0 {
status = "okay";
};
/* UART is initialized before SYSFW is started
* so we can't do any power-domain/clock operations.
* Delete clock/power-domain properties to avoid
* UART init failure
*/
&main_uart0 {
/delete-property/ power-domains;
/delete-property/ clocks;
/delete-property/ clock-names;
};
/* timer init is called as part of rproc_start() while
* starting System Firmware, so any clock/power-domain
* operations will fail as SYSFW is not yet up and running.
* Delete all clock/power-domain properties to avoid
* timer init failure.
* This is an always on timer at 20MHz.
*/
&main_timer0 {
/delete-property/ clocks;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
/delete-property/ power-domains;
};
&ospi0 {
reg = <0x00 0x0fc40000 0x00 0x100>,
<0x00 0x60000000 0x00 0x8000000>;
};

View File

@@ -0,0 +1,84 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2026 Texas Instruments Incorporated - https://www.ti.com/
*/
/ {
aliases {
remoteproc0 = &sysctrler;
remoteproc1 = &a53_0;
};
a53_0: a53@0 {
compatible = "ti,am654-rproc";
reg = <0x00 0x00a90000 0x00 0x10>;
power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 137 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 135 0>;
clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
clock-names = "gtc", "core";
assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
assigned-clock-parents = <&k3_clks 61 2>;
assigned-clock-rates = <200000000>, <1000000000>;
ti,sci = <&dmsc>;
ti,sci-proc-id = <32>;
ti,sci-host-id = <10>;
bootph-pre-ram;
};
clk_200mhz: dummy-clock-200mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
bootph-pre-ram;
};
};
&cbass_main {
sysctrler: sysctrler {
compatible = "ti,am654-tisci-rproc-r5";
mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>;
mbox-names = "tx", "rx";
bootph-pre-ram;
};
};
&dmsc {
mboxes= <&secure_proxy_main 0>,
<&secure_proxy_main 1>,
<&secure_proxy_main 0>;
mbox-names = "rx", "tx", "notify";
ti,host-id = <35>;
ti,secure-host;
};
/* UART is initialized before SYSFW is started
* so we can't do any power-domain/clock operations.
* Delete clock/power-domain properties to avoid
* UART init failure
*/
&main_uart0 {
/delete-property/ power-domains;
/delete-property/ clocks;
/delete-property/ clock-names;
};
/* timer init is called as part of rproc_start() while
* starting System Firmware, so any clock/power-domain
* operations will fail as SYSFW is not yet up and running.
* Delete all clock/power-domain properties to avoid
* timer init failure.
* This is an always on timer at 20MHz.
*/
&main_timer0 {
/delete-property/ clocks;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
/delete-property/ power-domains;
};
&ospi0 {
reg = <0x00 0x0fc40000 0x00 0x100>,
<0x00 0x60000000 0x00 0x8000000>;
};

View File

@@ -139,6 +139,37 @@
#address-cells = <1>;
images {
atf {
ti-secure {
auth-in-place = <0xa02>;
firewall-24-5 {
insert-template = <&firewall_armv8_atf_fg>;
id = <24>;
region = <5>;
};
};
};
tee {
ti-secure {
auth-in-place = <0xa02>;
firewall-1-0 {
insert-template = <&firewall_bg_3>;
id = <1>;
region = <0>;
};
firewall-1-1 {
insert-template = <&firewall_armv8_optee_fg>;
id = <1>;
region = <1>;
};
};
};
dm {
blob-ext {
filename = "/dev/null";

View File

@@ -9,74 +9,7 @@
#include "k3-am654-base-board-u-boot.dtsi"
#include "k3-am654-base-board-ddr4-1600MTs.dtsi"
#include "k3-am654-ddr.dtsi"
/ {
aliases {
remoteproc0 = &sysctrler;
remoteproc1 = &a53_0;
};
a53_0: a53@0 {
compatible = "ti,am654-rproc";
reg = <0x0 0x00a90000 0x0 0x10>;
power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 202 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 202 0>;
clocks = <&k3_clks 61 0>, <&k3_clks 202 0>;
clock-names = "gtc", "core";
assigned-clocks = <&k3_clks 202 0>;
assigned-clock-rates = <800000000>;
ti,sci = <&dmsc>;
ti,sci-proc-id = <32>;
ti,sci-host-id = <10>;
bootph-pre-ram;
};
clk_200mhz: dummy_clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
bootph-pre-ram;
};
};
&secure_proxy_mcu {
status = "okay";
bootph-pre-ram;
};
&cbass_wakeup {
sysctrler: sysctrler {
compatible = "ti,am654-tisci-rproc-r5";
mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>;
mbox-names = "tx", "rx";
bootph-pre-ram;
};
};
/*
* timer init is called as part of rproc_start() while
* starting System Firmware, so any clock/power-domain
* operations will fail as SYSFW is not yet up and running.
* Delete all clock/power-domain properties to avoid
* timer init failure.
* This is an always on timer at 20MHz.
*/
&mcu_timer0 {
/delete-property/ clocks;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
/delete-property/ power-domains;
};
&dmsc {
mboxes = <&secure_proxy_mcu 8>,
<&secure_proxy_mcu 6>,
<&secure_proxy_mcu 5>;
mbox-names = "tx", "rx", "notify";
ti,host-id = <4>;
ti,secure-host;
};
#include "k3-am654-r5.dtsi"
&wkup_uart0 {
status = "okay";
@@ -128,11 +61,6 @@
/delete-property/ power-domains;
};
&ospi0 {
reg = <0x0 0x47040000 0x0 0x100>,
<0x0 0x50000000 0x0 0x8000000>;
};
&dwc3_0 {
status = "okay";
/delete-property/ clocks;

View File

@@ -0,0 +1,77 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2026 Texas Instruments Incorporated - https://www.ti.com/
*/
/ {
aliases {
remoteproc0 = &sysctrler;
remoteproc1 = &a53_0;
};
a53_0: a53@0 {
compatible = "ti,am654-rproc";
reg = <0x0 0x00a90000 0x0 0x10>;
power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 202 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 202 0>;
clocks = <&k3_clks 61 0>, <&k3_clks 202 0>;
clock-names = "gtc", "core";
assigned-clocks = <&k3_clks 202 0>;
assigned-clock-rates = <800000000>;
ti,sci = <&dmsc>;
ti,sci-proc-id = <32>;
ti,sci-host-id = <10>;
bootph-pre-ram;
};
clk_200mhz: dummy_clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
bootph-pre-ram;
};
};
&secure_proxy_mcu {
status = "okay";
bootph-pre-ram;
};
&cbass_wakeup {
sysctrler: sysctrler {
compatible = "ti,am654-tisci-rproc-r5";
mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>;
mbox-names = "tx", "rx";
bootph-pre-ram;
};
};
&dmsc {
mboxes = <&secure_proxy_mcu 8>,
<&secure_proxy_mcu 6>,
<&secure_proxy_mcu 5>;
mbox-names = "tx", "rx", "notify";
ti,host-id = <4>;
ti,secure-host;
};
&ospi0 {
reg = <0x0 0x47040000 0x0 0x100>,
<0x0 0x50000000 0x0 0x8000000>;
};
/*
* timer init is called as part of rproc_start() while
* starting System Firmware, so any clock/power-domain
* operations will fail as SYSFW is not yet up and running.
* Delete all clock/power-domain properties to avoid
* timer init failure.
* This is an always on timer at 20MHz.
*/
&mcu_timer0 {
/delete-property/ clocks;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
/delete-property/ power-domains;
};

View File

@@ -11,72 +11,7 @@
#include "k3-am67a-beagley-ddr-lp4.dtsi"
#include "k3-am62a-ddr.dtsi"
/ {
aliases {
remoteproc0 = &sysctrler;
remoteproc1 = &a53_0;
serial0 = &wkup_uart0;
serial2 = &main_uart0;
};
a53_0: a53@0 {
compatible = "ti,am654-rproc";
reg = <0x00 0x00a90000 0x00 0x10>;
power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 135 0>;
clocks = <&k3_clks 61 0>;
assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
assigned-clock-parents = <&k3_clks 61 2>;
assigned-clock-rates = <200000000>, <1200000000>;
ti,sci = <&dmsc>;
ti,sci-proc-id = <32>;
ti,sci-host-id = <10>;
bootph-all;
};
dm_tifs: dm-tifs {
compatible = "ti,j721e-dm-sci";
ti,host-id = <36>;
ti,secure-host;
mbox-names = "rx", "tx";
mboxes= <&secure_proxy_main 22>,
<&secure_proxy_main 23>;
bootph-all;
};
};
&dmsc {
mboxes= <&secure_proxy_main 0>,
<&secure_proxy_main 1>,
<&secure_proxy_main 0>;
mbox-names = "rx", "tx", "notify";
ti,host-id = <35>;
ti,secure-host;
};
&cbass_main {
sa3_secproxy: secproxy@44880000 {
compatible = "ti,am654-secure-proxy";
#mbox-cells = <1>;
reg = <0x00 0x44880000 0x00 0x20000>,
<0x00 0x44860000 0x00 0x20000>,
<0x00 0x43600000 0x00 0x10000>;
reg-names = "rt", "scfg", "target_data";
bootph-all;
};
sysctrler: sysctrler {
compatible = "ti,am654-tisci-rproc-r5";
mboxes= <&secure_proxy_main 1>,
<&secure_proxy_main 0>,
<&sa3_secproxy 0>;
mbox-names = "tx", "rx", "boot_notify";
bootph-all;
};
};
#include "k3-am67a-r5.dtsi"
/* WKUP UART0 is used for DM firmware logs */
&wkup_uart0 {

View File

@@ -0,0 +1,70 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2026 Texas Instruments Incorporated - https://www.ti.com/
*/
/ {
aliases {
remoteproc0 = &sysctrler;
remoteproc1 = &a53_0;
serial0 = &wkup_uart0;
serial2 = &main_uart0;
};
a53_0: a53@0 {
compatible = "ti,am654-rproc";
reg = <0x00 0x00a90000 0x00 0x10>;
power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 135 0>;
clocks = <&k3_clks 61 0>;
assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
assigned-clock-parents = <&k3_clks 61 2>;
assigned-clock-rates = <200000000>, <1200000000>;
ti,sci = <&dmsc>;
ti,sci-proc-id = <32>;
ti,sci-host-id = <10>;
bootph-all;
};
dm_tifs: dm-tifs {
compatible = "ti,j721e-dm-sci";
ti,host-id = <36>;
ti,secure-host;
mbox-names = "rx", "tx";
mboxes= <&secure_proxy_main 22>,
<&secure_proxy_main 23>;
bootph-all;
};
};
&dmsc {
mboxes= <&secure_proxy_main 0>,
<&secure_proxy_main 1>,
<&secure_proxy_main 0>;
mbox-names = "rx", "tx", "notify";
ti,host-id = <35>;
ti,secure-host;
};
&cbass_main {
sa3_secproxy: secproxy@44880000 {
compatible = "ti,am654-secure-proxy";
#mbox-cells = <1>;
reg = <0x00 0x44880000 0x00 0x20000>,
<0x00 0x44860000 0x00 0x20000>,
<0x00 0x43600000 0x00 0x10000>;
reg-names = "rt", "scfg", "target_data";
bootph-all;
};
sysctrler: sysctrler {
compatible = "ti,am654-tisci-rproc-r5";
mboxes= <&secure_proxy_main 1>,
<&secure_proxy_main 0>,
<&sa3_secproxy 0>;
mbox-names = "tx", "rx", "boot_notify";
bootph-all;
};
};

View File

@@ -144,6 +144,7 @@
};
&usbss0 {
ti,modestrap-peripheral;
ti,usb2-only;
bootph-pre-ram;
};

View File

@@ -476,8 +476,8 @@
permissions = <((FWPRIVID_ARMV8 << FWPRIVID_SHIFT) |
FWPERM_SECURE_PRIV_RWCD |
FWPERM_SECURE_USER_RWCD)>;
start_address = <0x0 0x70000000>;
end_address = <0x0 0x7001ffff>;
start_address = <0x0 CONFIG_K3_ATF_LOAD_ADDR>;
end_address = <0x0 (CONFIG_K3_ATF_LOAD_ADDR + 0x1ffff)>;
};
firewall_armv8_optee_fg: template-8 {
control = <(FWCTRL_EN | FWCTRL_LOCK |
@@ -485,8 +485,8 @@
permissions = <((FWPRIVID_ARMV8 << FWPRIVID_SHIFT) |
FWPERM_SECURE_PRIV_RWCD |
FWPERM_SECURE_USER_RWCD)>;
start_address = <0x0 0x9e800000>;
end_address = <0x0 0x9fffffff>;
start_address = <0x0 CONFIG_K3_OPTEE_LOAD_ADDR>;
end_address = <0x0 (CONFIG_K3_OPTEE_LOAD_ADDR + 0x17fffff)>;
};
ti_falcon_template: template-9 {

View File

@@ -9,92 +9,12 @@
#include "k3-j7200-ddr-evm-lp4-2666.dtsi"
#include "k3-j721e-ddr.dtsi"
#include "k3-j7200-common-proc-board-u-boot.dtsi"
/ {
aliases {
remoteproc0 = &sysctrler;
remoteproc1 = &a72_0;
};
a72_0: a72@0 {
compatible = "ti,am654-rproc";
reg = <0x0 0x00a90000 0x0 0x10>;
power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 202 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 4 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 202 0>;
clocks = <&k3_clks 61 1>, <&k3_clks 202 2>, <&k3_clks 4 1> ;
clock-names = "gtc", "core", "msmc";
assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>, <&k3_clks 4 1>,
<&k3_clks 323 0>;
assigned-clock-parents= <0>, <0>, <0>, <&k3_clks 323 2>;
assigned-clock-rates = <2000000000>, <200000000>, <1000000000>;
ti,sci = <&dmsc>;
ti,sci-proc-id = <32>;
ti,sci-host-id = <10>;
bootph-pre-ram;
};
dm_tifs: dm-tifs {
compatible = "ti,j721e-dm-sci";
ti,host-id = <3>;
ti,secure-host;
mbox-names = "rx", "tx";
mboxes = <&secure_proxy_mcu 21>,
<&secure_proxy_mcu 23>;
bootph-pre-ram;
};
};
&memorycontroller {
power-domains = <&k3_pds 8 TI_SCI_PD_SHARED>,
<&k3_pds 90 TI_SCI_PD_SHARED>;
clocks = <&k3_clks 8 5>, <&k3_clks 30 9>;
bootph-pre-ram;
};
&mcu_timer0 {
/delete-property/ clocks;
/delete-property/ clocks-names;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
clock-frequency = <250000000>;
bootph-pre-ram;
};
&secure_proxy_mcu {
bootph-pre-ram;
status = "okay";
};
&cbass_mcu_wakeup {
sysctrler: sysctrler {
compatible = "ti,am654-tisci-rproc-r5";
mboxes= <&secure_proxy_mcu 4>,
<&secure_proxy_mcu 5>;
mbox-names = "tx", "rx";
bootph-pre-ram;
};
};
&dmsc {
mboxes = <&secure_proxy_mcu 8>,
<&secure_proxy_mcu 6>, <&secure_proxy_mcu 5>;
mbox-names = "tx", "rx", "notify";
ti,host-id = <4>;
ti,secure-host;
bootph-pre-ram;
};
#include "k3-j7200-r5.dtsi"
&wkup_vtm0 {
bootph-pre-ram;
};
&ospi0 {
reg = <0x0 0x47040000 0x0 0x100>,
<0x0 0x50000000 0x0 0x8000000>;
};
&fss {
/* enable ranges missing from the FSS node */
ranges = <0x0 0x47000000 0x0 0x47000000 0x0 0x00068400>,

View File

@@ -0,0 +1,86 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2026 Texas Instruments Incorporated - https://www.ti.com/
*/
/ {
aliases {
remoteproc0 = &sysctrler;
remoteproc1 = &a72_0;
};
a72_0: a72@0 {
compatible = "ti,am654-rproc";
reg = <0x0 0x00a90000 0x0 0x10>;
power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 202 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 4 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 202 0>;
clocks = <&k3_clks 61 1>, <&k3_clks 202 2>, <&k3_clks 4 1> ;
clock-names = "gtc", "core", "msmc";
assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>, <&k3_clks 4 1>,
<&k3_clks 323 0>;
assigned-clock-parents= <0>, <0>, <0>, <&k3_clks 323 2>;
assigned-clock-rates = <2000000000>, <200000000>, <1000000000>;
ti,sci = <&dmsc>;
ti,sci-proc-id = <32>;
ti,sci-host-id = <10>;
bootph-pre-ram;
};
dm_tifs: dm-tifs {
compatible = "ti,j721e-dm-sci";
ti,host-id = <3>;
ti,secure-host;
mbox-names = "rx", "tx";
mboxes = <&secure_proxy_mcu 21>,
<&secure_proxy_mcu 23>;
bootph-pre-ram;
};
};
&memorycontroller {
power-domains = <&k3_pds 8 TI_SCI_PD_SHARED>,
<&k3_pds 90 TI_SCI_PD_SHARED>;
clocks = <&k3_clks 8 5>, <&k3_clks 30 9>;
bootph-pre-ram;
};
&mcu_timer0 {
/delete-property/ clocks;
/delete-property/ clocks-names;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
clock-frequency = <250000000>;
bootph-pre-ram;
};
&secure_proxy_mcu {
bootph-pre-ram;
status = "okay";
};
&cbass_mcu_wakeup {
sysctrler: sysctrler {
compatible = "ti,am654-tisci-rproc-r5";
mboxes= <&secure_proxy_mcu 4>,
<&secure_proxy_mcu 5>;
mbox-names = "tx", "rx";
bootph-pre-ram;
};
};
&dmsc {
mboxes = <&secure_proxy_mcu 8>,
<&secure_proxy_mcu 6>, <&secure_proxy_mcu 5>;
mbox-names = "tx", "rx", "notify";
ti,host-id = <4>;
ti,secure-host;
bootph-pre-ram;
};
&ospi0 {
reg = <0x0 0x47040000 0x0 0x100>,
<0x0 0x50000000 0x0 0x8000000>;
};

View File

@@ -9,92 +9,13 @@
#include "k3-j722s-ddr-lp4-50-4000.dtsi"
#include "k3-am62a-ddr.dtsi"
/ {
aliases {
remoteproc0 = &sysctrler;
remoteproc1 = &a53_0;
serial0 = &wkup_uart0;
serial2 = &main_uart0;
};
a53_0: a53@0 {
compatible = "ti,am654-rproc";
reg = <0x00 0x00a90000 0x00 0x10>;
power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 135 0>;
clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
clock-names = "gtc", "core";
assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
assigned-clock-parents = <&k3_clks 61 2>;
assigned-clock-rates = <200000000>, <1400000000>;
ti,sci = <&dmsc>;
ti,sci-proc-id = <32>;
ti,sci-host-id = <10>;
bootph-all;
};
dm_tifs: dm-tifs {
compatible = "ti,j721e-dm-sci";
ti,host-id = <36>;
ti,secure-host;
mbox-names = "rx", "tx";
mboxes= <&secure_proxy_main 28>,
<&secure_proxy_main 29>;
bootph-all;
};
};
&dmsc {
mboxes= <&secure_proxy_main 0>,
<&secure_proxy_main 1>,
<&secure_proxy_main 0>;
mbox-names = "rx", "tx", "notify";
ti,host-id = <35>;
ti,secure-host;
};
&cbass_main {
sa3_secproxy: secproxy@44880000 {
compatible = "ti,am654-secure-proxy";
#mbox-cells = <1>;
reg = <0x00 0x44880000 0x00 0x20000>,
<0x00 0x44860000 0x00 0x20000>,
<0x00 0x43600000 0x00 0x10000>;
reg-names = "rt", "scfg", "target_data";
bootph-all;
};
sysctrler: sysctrler {
compatible = "ti,am654-tisci-rproc-r5";
mboxes= <&secure_proxy_main 1>,
<&secure_proxy_main 0>,
<&sa3_secproxy 0>;
mbox-names = "tx", "rx", "boot_notify";
bootph-all;
};
};
&main_timer0 {
/delete-property/ clocks;
/delete-property/ clocks-names;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
clock-frequency = <25000000>;
};
#include "k3-j722s-r5.dtsi"
/* WKUP UART0 is used for DM firmware logs */
&wkup_uart0 {
status = "okay";
};
&ospi0 {
reg = <0x00 0x0fc40000 0x00 0x100>,
<0x00 0x60000000 0x00 0x08000000>;
};
&main_bcdma {
ti,sci = <&dm_tifs>;
};

View File

@@ -0,0 +1,84 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2026 Texas Instruments Incorporated - https://www.ti.com/
*/
/ {
aliases {
remoteproc0 = &sysctrler;
remoteproc1 = &a53_0;
serial0 = &wkup_uart0;
serial2 = &main_uart0;
};
a53_0: a53@0 {
compatible = "ti,am654-rproc";
reg = <0x00 0x00a90000 0x00 0x10>;
power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 135 0>;
clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
clock-names = "gtc", "core";
assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
assigned-clock-parents = <&k3_clks 61 2>;
assigned-clock-rates = <200000000>, <1400000000>;
ti,sci = <&dmsc>;
ti,sci-proc-id = <32>;
ti,sci-host-id = <10>;
bootph-all;
};
dm_tifs: dm-tifs {
compatible = "ti,j721e-dm-sci";
ti,host-id = <36>;
ti,secure-host;
mbox-names = "rx", "tx";
mboxes= <&secure_proxy_main 28>,
<&secure_proxy_main 29>;
bootph-all;
};
};
&dmsc {
mboxes= <&secure_proxy_main 0>,
<&secure_proxy_main 1>,
<&secure_proxy_main 0>;
mbox-names = "rx", "tx", "notify";
ti,host-id = <35>;
ti,secure-host;
};
&cbass_main {
sa3_secproxy: secproxy@44880000 {
compatible = "ti,am654-secure-proxy";
#mbox-cells = <1>;
reg = <0x00 0x44880000 0x00 0x20000>,
<0x00 0x44860000 0x00 0x20000>,
<0x00 0x43600000 0x00 0x10000>;
reg-names = "rt", "scfg", "target_data";
bootph-all;
};
sysctrler: sysctrler {
compatible = "ti,am654-tisci-rproc-r5";
mboxes= <&secure_proxy_main 1>,
<&secure_proxy_main 0>,
<&sa3_secproxy 0>;
mbox-names = "tx", "rx", "boot_notify";
bootph-all;
};
};
&main_timer0 {
/delete-property/ clocks;
/delete-property/ clocks-names;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
clock-frequency = <25000000>;
};
&ospi0 {
reg = <0x00 0x0fc40000 0x00 0x100>,
<0x00 0x60000000 0x00 0x08000000>;
};

View File

@@ -22,6 +22,10 @@
ethernet5 = &swp4;
ethernet6 = &swp5;
};
chosen {
stdout-path = &uart0;
};
};
&dspi0 {

View File

@@ -763,7 +763,7 @@
interrupts = <GIC_SPI 4075 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
status = "okay";
status = "disabled";
};
scif3: serial@c0708000 {

View File

@@ -14,7 +14,7 @@
};
&i2c0 {
gpio_expander1: mcp23017@21 {
gpio_expander0: mcp23017@21 {
compatible = "microchip,mcp23017";
reg = <0x21>;
gpio-controller;
@@ -118,7 +118,7 @@
};
};
gpio_expander2: mcp23017@22 {
gpio_expander1: mcp23017@22 {
compatible = "microchip,mcp23017";
reg = <0x22>;
gpio-controller;

View File

@@ -13,7 +13,7 @@
};
&i2c2 {
gpio_expander1: mcp23017@21 {
gpio_expander0: mcp23017@21 {
compatible = "microchip,mcp23017";
reg = <0x21>;
gpio-controller;
@@ -125,7 +125,7 @@
};
};
gpio_expander2: mcp23017@22 {
gpio_expander1: mcp23017@22 {
compatible = "microchip,mcp23017";
reg = <0x22>;
gpio-controller;

View File

@@ -17,7 +17,7 @@
&i2c0 {
#address-cells = <1>;
#size-cells = <0>;
gpio_expander1: mcp23017@21 {
gpio_expander0: mcp23017@21 {
compatible = "microchip,mcp23017";
reg = <0x21>;
gpio-controller;
@@ -145,7 +145,7 @@
};
};
gpio_expander2: mcp23017@22 {
gpio_expander1: mcp23017@22 {
compatible = "microchip,mcp23017";
reg = <0x22>;
gpio-controller;

View File

@@ -13,7 +13,7 @@
};
&i2c2 {
gpio_expander2: mcp23017@22 {
crr_gpio_expander: mcp23017@22 {
compatible = "microchip,mcp23017";
reg = <0x22>;
gpio-controller;

View File

@@ -13,7 +13,7 @@
};
&i2c2 {
gpio_expander: adp5588@30 {
crr_gpio_expander: adp5588@30 {
compatible = "adi,adp5588";
reg = <0x30>;
gpio-controller;

View File

@@ -13,7 +13,7 @@
};
&i2c2 {
gpio_expander2: mcp23017@22 {
crr_gpio_expander: mcp23017@22 {
compatible = "microchip,mcp23017";
reg = <0x22>;
gpio-controller;

View File

@@ -5,7 +5,7 @@
/dts-v1/;
#include "sc598-som-revD.dtsi"
#include "sc598-som-revE.dtsi"
/ {
model = "ADI SC598-SOM-EZLITE";
@@ -13,7 +13,7 @@
};
&i2c2 {
gpio_expander: adp5588@30 {
crr_gpio_expander: adp5588@30 {
compatible = "adi,adp5588";
reg = <0x30>;
gpio-controller;

View File

@@ -55,6 +55,38 @@
line-name = "spi2flash-cs";
bootph-pre-ram;
};
uart0 {
gpio-hog;
gpios = <5 GPIO_ACTIVE_LOW>;
output-high;
line-name = "uart0-en";
bootph-pre-ram;
};
uart0-flow-en {
gpio-hog;
gpios = <6 GPIO_ACTIVE_LOW>;
output-low;
line-name = "uart0-flow-en";
bootph-pre-ram;
};
som-emmc {
gpio-hog;
gpios = <8 GPIO_ACTIVE_LOW>;
output-high;
line-name = "som-emmc-en";
bootph-pre-ram;
};
crr-sdcard {
gpio-hog;
gpios = <9 GPIO_ACTIVE_LOW>;
output-low;
line-name = "crr-sdcard-en";
bootph-pre-ram;
};
};
};

View File

@@ -154,17 +154,6 @@
clock-names = "spi";
status = "okay";
bootph-pre-ram;
flash1: is25lp512@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor", "is25lp512";
reg = <1>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
spi-max-frequency = <10000000>;
bootph-pre-ram;
};
};
wdog: watchdog@31008000 {

View File

@@ -0,0 +1,19 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
/*
* Copyright (C) STMicroelectronics 2026 - All Rights Reserved
*/
/ {
config {
u-boot,boot-led = "led-blue";
u-boot,mmc-env-partition = "u-boot-env";
};
};
&syscfg {
bootph-all;
};
&usart2 {
bootph-all;
};

View File

@@ -2,10 +2,8 @@
/*
* (C) Copyright 2022 - Analog Devices, Inc.
*
* Written and/or maintained by Timesys Corporation
* Written by Timesys Corporation
*
* Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
* Contact: Greg Malysa <greg.malysa@timesys.com>
*/
#ifndef ARCH_ADI_SC5XX_SC5XX_H
#define ARCH_ADI_SC5XX_SC5XX_H

View File

@@ -2,10 +2,8 @@
/*
* (C) Copyright 2022 - Analog Devices, Inc.
*
* Written and/or maintained by Timesys Corporation
* Written by Timesys Corporation
*
* Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
* Contact: Greg Malysa <greg.malysa@timesys.com>
*/
#ifndef BOARD_ADI_COMMON_SOC_H

View File

@@ -2,10 +2,8 @@
/*
* (C) Copyright 2022 - Analog Devices, Inc.
*
* Written and/or maintained by Timesys Corporation
* Written by Timesys Corporation
*
* Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
* Contact: Greg Malysa <greg.malysa@timesys.com>
*/
#ifndef ARCH_ADI_SC5XX_SPL_H
#define ARCH_ADI_SC5XX_SPL_H

View File

@@ -137,7 +137,7 @@ struct ccsr_gur {
#define SCFG_ETSECCMCR_GE0_CLK125 0x00000000
#define SCFG_ETSECCMCR_GE1_CLK125 0x08000000
#define SCFG_PIXCLKCR_PXCKEN 0x80000000
#define SCFG_QSPI_CLKSEL 0x50100000
#define SCFG_QSPI_CLKSEL 0x30100000
#define SCFG_SNPCNFGCR_SEC_RD_WR 0xc0000000
#define SCFG_SNPCNFGCR_DCU_RD_WR 0x03000000
#define SCFG_SNPCNFGCR_SATA_RD_WR 0x00c00000

View File

@@ -11,6 +11,7 @@
#define _SUNXI_CLOCK_SUN4I_H
#define CCU_AHB_GATE0 0x60
#define CCU_NAND0_CLK_CFG 0x80
#define CCU_MMC0_CLK_CFG 0x88
#define CCU_MMC1_CLK_CFG 0x8c
#define CCU_MMC2_CLK_CFG 0x90

View File

@@ -24,7 +24,11 @@
#define CCU_H6_APB2_CFG 0x524
#define CCU_H6_MBUS_CFG 0x540
#define CCU_H6_DRAM_CLK_CFG 0x800
#define CCU_H6_MBUS_GATE 0x804
#define CCU_H6_DRAM_GATE_RESET 0x80c
#define CCU_NAND0_CLK_CFG 0x810
#define CCU_NAND1_CLK_CFG 0x814
#define CCU_H6_NAND_GATE_RESET 0x82c
#define CCU_MMC0_CLK_CFG 0x830
#define CCU_MMC1_CLK_CFG 0x834
#define CCU_MMC2_CLK_CFG 0x838
@@ -146,6 +150,16 @@
#define RESET_SHIFT (16)
#define GATE_SHIFT (0)
/* MBUS gate offsets */
#define MBUS_GATE_OFFSET_DI 11
#define MBUS_GATE_OFFSET_G2D 10
#define MBUS_GATE_OFFSET_CSI 8
#define MBUS_GATE_OFFSET_NAND 5
#define MBUS_GATE_OFFSET_TS0 3
#define MBUS_GATE_OFFSET_VE 2
#define MBUS_GATE_OFFSET_CE 1
#define MBUS_GATE_OFFSET_DMA 0
/* DRAM clock bit field */
#define DRAM_CLK_ENABLE BIT(31)
#define DRAM_MOD_RESET BIT(30)
@@ -155,6 +169,16 @@
#define DRAM_CLK_M_MASK (0x1f)
#define DRAM_CLK_M(m) (((m)-1) << 0)
/* NAND clock bit field */
#define CCM_NAND_CTRL_M(x) ((x) - 1)
#define CCM_NAND_CTRL_N(x) ((x) << 8)
#define CCM_NAND_CTRL_OSCM24 (0x0 << 24)
#define CCM_NAND_CTRL_PLL6 (0x1 << 24)
#define CCM_NAND_CTRL_PLL_PERIPH2 (0x2 << 24)
#define CCM_NAND_CTRL_PLL6X2 (0x3 << 24)
#define CCM_NAND_CTRL_PLL_PERIPH2X2 (0x4 << 24)
#define CCM_NAND_CTRL_ENABLE (0x1 << 31)
/* MMC clock bit field */
#define CCM_MMC_CTRL_M(x) ((x) - 1)
#define CCM_MMC_CTRL_N(x) ((x) << 8)

View File

@@ -11,6 +11,7 @@
#define _SUNXI_CLOCK_SUN6I_H
#define CCU_AHB_GATE0 0x060
#define CCU_NAND0_CLK_CFG 0x080
#define CCU_MMC0_CLK_CFG 0x088
#define CCU_MMC1_CLK_CFG 0x08c
#define CCU_MMC2_CLK_CFG 0x090

View File

@@ -14,6 +14,7 @@
#define _SUNXI_CLOCK_SUN8I_A83T_H
#define CCU_AHB_GATE0 0x060
#define CCU_NAND0_CLK_CFG 0x080
#define CCU_MMC0_CLK_CFG 0x088
#define CCU_MMC1_CLK_CFG 0x08c
#define CCU_MMC2_CLK_CFG 0x090

View File

@@ -12,11 +12,13 @@
#include <linux/bitops.h>
#endif
#define CCU_NAND0_CLK_CFG 0x400
#define CCU_MMC0_CLK_CFG 0x410
#define CCU_MMC1_CLK_CFG 0x414
#define CCU_MMC2_CLK_CFG 0x418
#define CCU_MMC3_CLK_CFG 0x41c
#define CCU_AHB_GATE0 0x580
#define CCU_AHB_GATE1 0x584
#define CCU_AHB_RESET0_CFG 0x5a0
struct sunxi_ccm_reg {

View File

@@ -7,6 +7,7 @@
#include <phys2bus.h>
#include <asm/arch/mbox.h>
#include <linux/delay.h>
#include <linux/errno.h>
struct msg_set_power_state {
struct bcm2835_mbox_hdr hdr;

View File

@@ -10,6 +10,7 @@
#include <asm/mach-imx/ele_api.h>
#include <asm/mach-imx/sys_proto.h>
#include <asm/arch-imx/cpu.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
#include <console.h>
#include <cpu_func.h>

View File

@@ -318,6 +318,7 @@ config TARGET_IMX8MN_VAR_SOM
select I2C_EEPROM
select DM_ETH_PHY
select NVMEM
imply OF_UPSTREAM
config TARGET_KONTRON_PITX_IMX8M
bool "Support Kontron pITX-imx8m"

View File

@@ -29,6 +29,22 @@ struct mm_region k3_mem_map[K3_MEM_MAP_LEN] = {
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, { /*
* PCIe 4 GB Address Window for AM64 and J722S SoCs starts
* from 0x6_0000_0000 and has a size of 0x1_0000_0000.
* Since this is already enabled by the 'Flash Peripherals'
* region above, we don't need to add it again.
*
* The PCIe 4 GB Address Windows for AM68, AM69, J7200, J721E,
* J721S2, J742S2 and J784S4 SoCs are enabled by the following
* region.
*/
.virt = 0x4000000000UL,
.phys = 0x4000000000UL,
.size = 0x400000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, [K3_MEM_MAP_FIRST_BANK_IDX] = { /* First DRAM Bank of size 2G */
.virt = CFG_SYS_SDRAM_BASE,
.phys = CFG_SYS_SDRAM_BASE,

View File

@@ -407,6 +407,11 @@ void k3_fix_rproc_clock(const char *path)
path, a_core_frequency / 1000000, speed_grade);
}
__weak phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
return gd->ram_top;
}
void spl_enable_cache(void)
{
#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
@@ -420,6 +425,7 @@ void spl_enable_cache(void)
gd->arch.tlb_size = PGTABLE_SIZE;
gd->ram_top += get_effective_memsize();
gd->ram_top = board_get_usable_ram_top(0);
gd->relocaddr = gd->ram_top;
ret = spl_reserve_video_from_ram_top();

View File

@@ -8,11 +8,14 @@
#include <spl.h>
/* We need 3 extra entries for:
* SoC peripherals, flash and the sentinel value.
/* We need 4 extra entries for:
* 1. SoC peripherals
* 2. Flash
* 3. PCIe 4GB Windows for AM68, AM69, J7200, J721E, J721S2, J742S2 and J784S4 SoCs
* 4. Sentinel value
*/
#define K3_MEM_MAP_LEN ((CONFIG_NR_DRAM_BANKS) + 3)
#define K3_MEM_MAP_FIRST_BANK_IDX 2
#define K3_MEM_MAP_LEN ((CONFIG_NR_DRAM_BANKS) + 4)
#define K3_MEM_MAP_FIRST_BANK_IDX 3
int dram_init(void);
int dram_init_banksize(void);

View File

@@ -539,7 +539,7 @@ static const struct clk_data clk_list[] = {
CLK_PLL("pllfrac2_ssmod_16fft_main_2_foutvcop_clk", "main_pll_hfosc_sel_out2", 0x682000, 0),
CLK_PLL("pllfrac2_ssmod_16fft_main_23_foutvcop_clk", "main_pll_hfosc_sel_out23", 0x697000, 0),
CLK_PLL("pllfrac2_ssmod_16fft_main_25_foutvcop_clk", "main_pll25_hfosc_sel_out0", 0x699000, 0),
CLK_PLL("pllfrac2_ssmod_16fft_main_3_foutvcop_clk", "main_pll_hfosc_sel_out3", 0x683000, 0),
CLK_PLL_DEFFREQ("pllfrac2_ssmod_16fft_main_3_foutvcop_clk", "main_pll_hfosc_sel_out3", 0x683000, 0, 2000000000),
CLK_PLL("pllfrac2_ssmod_16fft_main_5_foutvcop_clk", "main_pll_hfosc_sel_out5", 0x685000, 0),
CLK_PLL("pllfrac2_ssmod_16fft_main_6_foutvcop_clk", "main_pll_hfosc_sel_out6", 0x686000, 0),
CLK_PLL("pllfrac2_ssmod_16fft_main_7_foutvcop_clk", "main_pll_hfosc_sel_out7", 0x687000, 0),

View File

@@ -5,7 +5,7 @@
* This file is auto generated. Please do not hand edit and report any issues
* to Bryan Brattlof <bb@ti.com>.
*
* Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/
* Copyright (C) 2020-2026 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <linux/clk-provider.h>
@@ -159,6 +159,7 @@ static const struct clk_data clk_list[] = {
CLK_FIXED_RATE("board_0_rmii1_ref_clk_out", 0, 0),
CLK_FIXED_RATE("board_0_rmii2_ref_clk_out", 0, 0),
CLK_FIXED_RATE("board_0_tck_out", 0, 0),
CLK_FIXED_RATE("board_0_wkup_i2c0_scl_out", 0, 0),
CLK_FIXED_RATE("cpsw_3guss_am67_main_0_cpts_genf0", 0, 0),
CLK_FIXED_RATE("cpsw_3guss_am67_main_0_cpts_genf1", 0, 0),
CLK_FIXED_RATE("cpsw_3guss_am67_main_0_mdio_mdclk_o", 0, 0),
@@ -223,6 +224,8 @@ static const struct clk_data clk_list[] = {
CLK_MUX("wkup_clkout_sel_io_out0", wkup_clkout_sel_io_out0_parents, 2, 0x43008020, 24, 1, 0),
CLK_MUX("wkup_clksel_out0", wkup_clksel_out0_parents, 2, 0x43008010, 0, 1, 0),
CLK_MUX("main_usart0_fclk_sel_out0", main_usart0_fclk_sel_out0_parents, 2, 0x108280, 0, 1, 0),
CLK_DIV("hsdiv4_16fft_mcu_0_hsdivout1_clk", "pllfracf2_ssmod_16fft_mcu_0_foutvcop_clk", 0x4040084, 0, 7, 0, 0),
CLK_FIXED_RATE("mshsi2c_wkup_0_porscl", 0, 0),
CLK_DIV("sam62_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "sam62_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0, 0),
CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div24_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x402011c, 0, 5, 0, 0),
};
@@ -307,6 +310,11 @@ static const struct dev_clk soc_dev_clk_data[] = {
DEV_CLK(102, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(102, 1, "board_0_i2c0_scl_out"),
DEV_CLK(102, 2, "hsdiv4_16fft_main_1_hsdivout0_clk"),
DEV_CLK(107, 0, "wkup_clksel_out0"),
DEV_CLK(107, 1, "hsdiv3_16fft_main_15_hsdivout0_clk"),
DEV_CLK(107, 2, "hsdiv4_16fft_mcu_0_hsdivout0_clk"),
DEV_CLK(107, 3, "board_0_wkup_i2c0_scl_out"),
DEV_CLK(107, 4, "hsdiv4_16fft_mcu_0_hsdivout1_clk"),
DEV_CLK(135, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
DEV_CLK(146, 0, "main_usart0_fclk_sel_out0"),
DEV_CLK(146, 1, "usart_programmable_clock_divider_out0"),

View File

@@ -5,7 +5,7 @@
* This file is auto generated. Please do not hand edit and report any issues
* to Bryan Brattlof <bb@ti.com>.
*
* Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/
* Copyright (C) 2020-2026 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "k3-dev.h"
@@ -42,6 +42,7 @@ static struct ti_dev soc_dev_list[] = {
PSC_DEV(16, &soc_lpsc_list[0]),
PSC_DEV(77, &soc_lpsc_list[0]),
PSC_DEV(61, &soc_lpsc_list[0]),
PSC_DEV(107, &soc_lpsc_list[0]),
PSC_DEV(178, &soc_lpsc_list[1]),
PSC_DEV(179, &soc_lpsc_list[2]),
PSC_DEV(57, &soc_lpsc_list[3]),

View File

@@ -2,10 +2,7 @@
#
# (C) Copyright 2022 - Analog Devices, Inc.
#
# Written and/or maintained by Timesys Corporation
#
# Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
# Contact: Greg Malysa <greg.malysa@timesys.com>
# Written by Timesys Corporation
#
# All 32-bit platforms require SYS_ARM_CACHE_WRITETHROUGH

View File

@@ -2,10 +2,7 @@
#
# (C) Copyright 2022 - Analog Devices, Inc.
#
# Written and/or maintained by Timesys Corporation
#
# Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
# Contact: Greg Malysa <greg.malysa@timesys.com>
# Written by Timesys Corporation
#
obj-y += soc.o init/

View File

@@ -2,10 +2,7 @@
#
# (C) Copyright 2022 - Analog Devices, Inc.
#
# Written and/or maintained by Timesys Corporation
#
# Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
# Contact: Greg Malysa <greg.malysa@timesys.com>
# Written by Timesys Corporation
#
ifdef CONFIG_XPL_BUILD

View File

@@ -2,10 +2,7 @@
#
# (C) Copyright 2022 - Analog Devices, Inc.
#
# Written and/or maintained by Timesys Corporation
#
# Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
# Contact: Greg Malysa <greg.malysa@timesys.com>
# Written by Timesys Corporation
#
obj-y += dmcinit.o clkinit.o

View File

@@ -2,10 +2,8 @@
/*
* (C) Copyright 2022 - Analog Devices, Inc.
*
* Written and/or maintained by Timesys Corporation
* Written by Timesys Corporation
*
* Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
* Contact: Greg Malysa <greg.malysa@timesys.com>
*/
#include <asm/arch-adi/sc5xx/sc5xx.h>

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