Prepare v2026.04

Signed-off-by: Tom Rini <trini@konsulko.com>

.azure-pipelines.yml

@@ -2,7 +2,7 @@ variables:
   windows_vm: windows-2022
   ubuntu_vm: ubuntu-24.04
   macos_vm: macOS-14
-  ci_runner_image: trini/u-boot-gitlab-ci-runner:jammy-20251013-26Nov2025
+  ci_runner_image: trini/u-boot-gitlab-ci-runner:noble-20251013-23Jan2026
   # Ensure we do a shallow clone
   Agent.Source.Git.ShallowFetchDepth: 1
   # Add '-u 0' options for Azure pipelines, otherwise we get "permission
@@ -128,8 +128,8 @@ stages:
       - script: |
           ./tools/buildman/buildman --maintainer-check
 
-  - job: tools_only
-    displayName: 'Ensure host tools and env tools build'
+  - job: allyesconfig_and_tools
+    displayName: 'Ensure allyesconfig, tools-only and envtools build'
     pool:
       vmImage: $(ubuntu_vm)
     container:
@@ -137,6 +137,10 @@ stages:
       options: $(container_option)
     steps:
       - script: |
+          # Allow pipefail because of how we use 'yes' here.
+          set +o pipefail;
+          yes 0 | make allyesconfig oldconfig all -j$(nproc)
+          make mrproper
           make tools-only_config tools-only -j$(nproc)
           make mrproper
           make tools-only_config envtools -j$(nproc)
@@ -145,13 +149,14 @@ stages:
     displayName: 'Run binman, buildman, dtoc, Kconfig and patman testsuites'
     pool:
       vmImage: $(ubuntu_vm)
+    container:
+      image: $(ci_runner_image)
+      options: $(container_option)
     steps:
       - script: |
-          cat << "EOF" > build.sh
-          cd $(work_dir)
+          # Configure git
           git config --global user.name "Azure Pipelines"
           git config --global user.email bmeng.cn@gmail.com
-          git config --global --add safe.directory $(work_dir)
           export USER=azure
           python3 -m venv /tmp/venv
           . /tmp/venv/bin/activate
@@ -174,11 +179,6 @@ stages:
           ./tools/dtoc/dtoc -t
           ./tools/patman/patman test
           make O=${UBOOT_TRAVIS_BUILD_DIR} testconfig
-          EOF
-          cat build.sh
-          # We cannot use "container" like other jobs above, as buildman
-          # seems to hang forever with pre-configured "container" environment
-          docker run -v $PWD:$(work_dir) $(ci_runner_image) /bin/bash $(work_dir)/build.sh
 
   - job: pylint
     displayName: Check for any pylint regressions
@@ -312,6 +312,7 @@ stages:
             -r tools/buildman/requirements.txt \
             -r test/py/requirements.txt \
             -r tools/u_boot_pylib/requirements.txt \
+            setuptools \
             pytest-azurepipelines
           tools/buildman/buildman -o \${UBOOT_TRAVIS_BUILD_DIR} -w -E -W -e --board \${TEST_PY_BD} \${OVERRIDE}
           cp /opt/grub/grub_x86.efi \${UBOOT_TRAVIS_BUILD_DIR}/
@@ -391,22 +392,26 @@ stages:
         sandbox:
           TEST_PY_BD: "sandbox"
           TEST_PY_EXTRA: "--timing"
+          # addr2line in Ubuntu 'Noble' and later are broken.
+          TEST_PY_TEST_SPEC: "not event_dump"
         sandbox_asan:
           TEST_PY_BD: "sandbox"
           OVERRIDE: "-a ASAN"
           TEST_PY_TEST_SPEC: "version"
         sandbox_clang:
           TEST_PY_BD: "sandbox"
-          OVERRIDE: "-O clang-18"
+          OVERRIDE: "-O clang-20"
+          # addr2line in Ubuntu 'Noble' and later are broken.
+          TEST_PY_TEST_SPEC: "not event_dump"
         sandbox_clang_asan:
           TEST_PY_BD: "sandbox"
-          OVERRIDE: "-O clang-18 -a ASAN"
+          OVERRIDE: "-O clang-20 -a ASAN"
           TEST_PY_TEST_SPEC: "version"
         sandbox64:
           TEST_PY_BD: "sandbox64"
         sandbox64_clang:
           TEST_PY_BD: "sandbox64"
-          OVERRIDE: "-O clang-18"
+          OVERRIDE: "-O clang-20"
         sandbox64_lwip:
           TEST_PY_BD: "sandbox64_lwip"
         sandbox_spl:
@@ -503,6 +508,7 @@ stages:
         qemu_arm64:
           TEST_PY_BD: "qemu_arm64"
           TEST_PY_TEST_SPEC: "not sleep"
+          OVERRIDE: "-a CONFIG_SEMIHOSTING=y"
         qemu_arm64_lwip:
           TEST_PY_BD: "qemu_arm64_lwip"
           TEST_PY_TEST_SPEC: "test_net_dhcp or test_net_ping or test_net_tftpboot"
@@ -518,6 +524,9 @@ stages:
           TEST_PY_ID: "--id qemu"
           TEST_PY_TEST_SPEC: "not sleep and not efi"
           OVERRIDE: "-a CONFIG_M68K_QEMU=y -a ~CONFIG_MCFTMR"
+        qemu_m68k_virt:
+          TEST_PY_BD: "qemu-m68k"
+          TEST_PY_TEST_SPEC: "not sleep"
         qemu_malta:
           TEST_PY_BD: "malta"
           TEST_PY_ID: "--id qemu"
@@ -652,6 +661,9 @@ stages:
     displayName: 'Build the World'
     pool:
       vmImage: $(ubuntu_vm)
+    container:
+      image: $(ci_runner_image)
+      options: $(container_option)
     strategy:
       # We split the world up in to 10 jobs as we can have at most 10
       # parallel jobs going on the free tier of Azure.
@@ -716,18 +728,13 @@ stages:
           BUILDMAN: $(aarch64_catch_all)
     steps:
       - script: |
-          cat << EOF > build.sh
           set -ex
-          cd ${WORK_DIR}
-          # make environment variables available as tests are running inside a container
-          export BUILDMAN="${BUILDMAN}"
-          git config --global --add safe.directory ${WORK_DIR}
+          # Setup venv, perform build
           python3 -m venv /tmp/venv
           . /tmp/venv/bin/activate
           pip install -r tools/binman/requirements.txt \
-            -r tools/buildman/requirements.txt
-          EOF
-          cat << "EOF" >> build.sh
+            -r tools/buildman/requirements.txt \
+            setuptools
           if [[ "${BUILDMAN}" != "" ]]; then
               ret=0;
               tools/buildman/buildman -o /tmp -PEWM ${BUILDMAN} ${OVERRIDE} || ret=$?;
@@ -736,6 +743,3 @@ stages:
                   exit $ret;
               fi;
           fi
-          EOF
-          cat build.sh
-          docker run -v $PWD:$(work_dir) $(ci_runner_image) /bin/bash $(work_dir)/build.sh

.b4-config

@@ -4,3 +4,8 @@
 [b4]
     send-auto-to-cmd = scripts/get_maintainer.pl --nogit --nogit-fallback --nogit-chief-penguins --norolestats --nom
     send-auto-cc-cmd = scripts/get_maintainer.pl --nogit-fallback --nogit-chief-penguins --norolestats --nol
+    # Patchwork integration. You still need to set pw-key to your API key
+    pw-url = https://patchwork.ozlabs.org/
+    pw-project = uboot
+    pw-review-state = under-review
+    pw-accept-state = accepted

.gitignore

@@ -70,6 +70,7 @@ fit-dtb.blob*
 #
 /spl/
 /tpl/
+/vpl/
 /defconfig
 /generated_defconfig
 /Test*

.gitlab-ci-sage-lab.yml

@@ -0,0 +1,227 @@
+# Definition for the lab connected to the "sage" host and managed with labgrid
+
+.sage_lab_template: &sage_lab_dfn
+  stage: sage-lab
+  rules:
+    - if: $SAGE_LAB == "1"
+      when: always
+    - if: $SAGE_LAB != "1"
+      when: manual
+      allow_failure: true
+  # USB can be unreliable.
+  retry: 2
+  dependencies: []
+  needs: [ "sandbox test.py" ]
+  tags: [ 'konsulko-sage-labgrid' ]
+  before_script:
+    # Clone uboot-test-hooks
+    - git config --global --add safe.directory "${CI_PROJECT_DIR}"
+    - git clone --depth=1 https://source.denx.de/u-boot/u-boot-test-hooks /tmp/uboot-test-hooks
+    - ln -s sage /tmp/uboot-test-hooks/bin/`hostname`
+    - ln -s sage /tmp/uboot-test-hooks/py/`hostname`
+    - export LG_ENV="/tmp/uboot-test-hooks/bin/sage/labgrid-sage-env.yaml";
+      export LG_COORDINATOR=172.17.0.1:20408
+    # Prepare python environment
+    - python3 -m venv /tmp/venv;
+      . /tmp/venv/bin/activate;
+      pip install -r test/py/requirements.txt -r tools/binman/requirements.txt
+        -r tools/buildman/requirements.txt -r tools/u_boot_pylib/requirements.txt
+        labgrid setuptools
+    # Acquire and turn on the exporter.
+    - labgrid-client reserve --wait board=${LABGRID_EXPORTER} &&
+      labgrid-client -p ${LABGRID_EXPORTER} acquire &&
+      labgrid-client -p ${LABGRID_EXPORTER} power on
+    # Prepare ssh
+    - mkdir --mode=0700 ~/.ssh;
+      printf 'Host sage-exporter-*\n\tUser labgrid\n' > ~/.ssh/config
+    # If we have TF-A binaries, we need to use them.
+    - if [[ -d /opt/tf-a/${TEST_PY_BD}${TEST_PY_ID//--id /_} ]]; then
+        cp /opt/tf-a/${TEST_PY_BD}${TEST_PY_ID//--id /_}/* /tmp/;
+      elif [[ -d /opt/tf-a/${TEST_PY_BD} ]]; then
+        cp /opt/tf-a/${TEST_PY_BD}/* /tmp/;
+      fi;
+      export BINMAN_INDIRS=/tmp;
+  script:
+    - export UBOOT_TRAVIS_BUILD_DIR=/tmp/${TEST_PY_BD}
+    # Don't stop on non-zero exit codes now, to provide as much chance as
+    # possible to ensure we don't leave lab resources acquired.
+    - set +e;
+    # Sage is 16 threads and has 4 devices attached, so 4 builder threads.
+    - tools/buildman/buildman -o ${UBOOT_TRAVIS_BUILD_DIR} -w -E -W -e
+        --board ${TEST_PY_BD} ${OVERRIDE} -T 4;
+      RC=`echo $?`;
+    # Wait for the exporter to have the device ready
+    - while test `labgrid-client resources |
+        grep -q ${LABGRID_EXPORTER}/${LG_PLACE}/; echo $?` -ne 0; do sleep 1;
+      done
+    # Fingerprint the exporter
+    - ssh-keyscan ${LABGRID_EXPORTER} > ~/.ssh/known_hosts 2>/dev/null
+    # If we built, run the tests and save the results.
+    - export PATH=/tmp/uboot-test-hooks/bin:${PATH};
+      export PYTHONPATH=/tmp/uboot-test-hooks/py/sage;
+      test $RC -eq 0 && labgrid-client reserve --wait board=${LG_PLACE} &&
+      labgrid-client -p ${LG_PLACE} acquire &&
+      ./test/py/test.py -ra --bd ${TEST_PY_BD} ${TEST_PY_ID}
+        ${TEST_PY_EXTRA:-"--capture=tee-sys"}
+        ${TEST_PY_TEST_SPEC:+"-k ${TEST_PY_TEST_SPEC}"}
+        --build-dir "$UBOOT_TRAVIS_BUILD_DIR"
+        --junitxml=/tmp/${TEST_PY_BD}/results.xml;
+      RC=`echo $?`;
+      cp -v /tmp/${TEST_PY_BD}/*.{html,css,xml} .;
+    # Release and power off everything.
+    - labgrid-client -p ${LG_PLACE} power off
+    - labgrid-client -p ${LG_PLACE} release
+    - labgrid-client -p ${LABGRID_EXPORTER} ssh sudo poweroff && sleep 15 &&
+      labgrid-client -p ${LABGRID_EXPORTER} power off
+    - labgrid-client -p ${LABGRID_EXPORTER} release
+    - exit $RC
+  artifacts:
+    when: always
+    paths:
+      - "*.html"
+      - "*.css"
+      - results.xml
+    reports:
+      junit: results.xml
+    expire_in: 1 week
+
+BeagleBone Black:
+  <<: *sage_lab_dfn
+  variables:
+    LABGRID_EXPORTER: "sage-exporter-bbb-1"
+    LG_PLACE: "bbb-1"
+    TEST_PY_BD: "am335x_evm"
+    OVERRIDE: "-a CMD_BOOTMENU -a CMD_LOG -a CMD_BOOTEFI_HELLO -a CMD_BOOTEFI_SELFTEST"
+
+BeagleBone Black (lwIP):
+  <<: *sage_lab_dfn
+  needs: [ "BeagleBone Black" ]
+  variables:
+    LABGRID_EXPORTER: "sage-exporter-bbb-1"
+    LG_PLACE: "bbb-1"
+    TEST_PY_BD: "am335x_evm"
+    OVERRIDE: "-a CMD_BOOTMENU -a CMD_LOG -a CMD_BOOTEFI_HELLO -a CMD_BOOTEFI_SELFTEST -a NET_LWIP"
+
+Pine64+:
+  <<: *sage_lab_dfn
+  variables:
+    LABGRID_EXPORTER: "sage-exporter-pine64-1"
+    LG_PLACE: "pine64-1"
+    TEST_PY_BD: "pine64_plus"
+    OVERRIDE: "-a CMD_BOOTMENU -a CMD_LOG"
+
+Pine64+ (lwIP):
+  <<: *sage_lab_dfn
+  needs: [ "Pine64+" ]
+  variables:
+    LABGRID_EXPORTER: "sage-exporter-pine64-1"
+    LG_PLACE: "pine64-1"
+    TEST_PY_BD: "pine64_plus"
+    # Leads to crash on lwIP, needs investigation.
+    TEST_PY_TEST_SPEC: "not test_net_pxe_boot_config"
+    OVERRIDE: "-a CMD_BOOTMENU -a CMD_LOG -a NET_LWIP"
+
+SolidRun Hummingboard 2:
+  <<: *sage_lab_dfn
+  variables:
+    LABGRID_EXPORTER: "sage-exporter-hb-1"
+    LG_PLACE: "hb-1"
+    TEST_PY_BD: "mx6cuboxi"
+    OVERRIDE: "-a UNIT_TEST -a ~CMD_EFIDEBUG -a CMD_BOOTMENU -a CMD_LOG"
+
+SolidRun Hummingboard 2 (lwIP):
+  <<: *sage_lab_dfn
+  needs: [ "SolidRun Hummingboard 2" ]
+  variables:
+    LABGRID_EXPORTER: "sage-exporter-hb-1"
+    LG_PLACE: "hb-1"
+    TEST_PY_BD: "mx6cuboxi"
+    OVERRIDE: "-a UNIT_TEST -a ~CMD_EFIDEBUG -a CMD_BOOTMENU -a CMD_LOG -a NET_LWIP"
+
+Raspberry Pi 4:
+  <<: *sage_lab_dfn
+  variables:
+    LABGRID_EXPORTER: "sage-exporter-rpi4-1"
+    LG_PLACE: "rpi4-1"
+    TEST_PY_BD: "rpi_4"
+    OVERRIDE: "-a UNIT_TEST -a ~CMD_EFIDEBUG -a CMD_BOOTMENU -a CMD_LOG -a ~CMD_BOOTEFI_SELFTEST -a CMD_TFTPPUT -a FIT -a FIT_SIGNATURE -a FIT_BEST_MATCH -a SYS_BOOTM_LEN=0x4000000 -a BOOTSTAGE -a BOOTSTAGE_STASH -a CMD_BOOTSTAGE -a BOOTSTAGE_STASH_ADDR=0x02400000"
+
+Raspberry Pi 4 (rpi_arm64):
+  <<: *sage_lab_dfn
+  needs: [ "Raspberry Pi 4" ]
+  variables:
+    LABGRID_EXPORTER: "sage-exporter-rpi4-1"
+    LG_PLACE: "rpi4-1"
+    TEST_PY_BD: "rpi_arm64"
+    OVERRIDE: "-a UNIT_TEST -a ~CMD_EFIDEBUG -a CMD_BOOTMENU -a CMD_LOG -a ~CMD_BOOTEFI_SELFTEST -a CMD_TFTPPUT -a FIT -a FIT_SIGNATURE -a FIT_BEST_MATCH -a SYS_BOOTM_LEN=0x4000000 -a BOOTSTAGE -a BOOTSTAGE_STASH -a CMD_BOOTSTAGE -a BOOTSTAGE_STASH_ADDR=0x02400000"
+
+Raspberry Pi 4 (rpi_arm64, lwIP):
+  <<: *sage_lab_dfn
+  needs: [ "Raspberry Pi 4 (rpi_arm64)" ]
+  variables:
+    LABGRID_EXPORTER: "sage-exporter-rpi4-1"
+    LG_PLACE: "rpi4-1"
+    TEST_PY_BD: "rpi_arm64"
+    OVERRIDE: "-a UNIT_TEST -a ~CMD_EFIDEBUG -a CMD_BOOTMENU -a CMD_LOG -a ~CMD_BOOTEFI_SELFTEST -a FIT -a FIT_SIGNATURE -a FIT_BEST_MATCH -a SYS_BOOTM_LEN=0x4000000 -a BOOTSTAGE -a BOOTSTAGE_STASH -a CMD_BOOTSTAGE -a BOOTSTAGE_STASH_ADDR=0x02400000 -a NET_LWIP"
+
+Raspberry Pi 4 (rpi_4_32b):
+  <<: *sage_lab_dfn
+  needs: [ "Raspberry Pi 4 (rpi_arm64, lwIP)" ]
+  variables:
+    LABGRID_EXPORTER: "sage-exporter-rpi4-1"
+    LG_PLACE: "rpi4-1"
+    TEST_PY_BD: "rpi_4_32b"
+    OVERRIDE: "-a UNIT_TEST -a ~CMD_EFIDEBUG -a CMD_BOOTMENU -a CMD_LOG -a CMD_BOOTEFI_SELFTEST -a CMD_TFTPPUT -a FIT -a FIT_SIGNATURE -a FIT_BEST_MATCH -a SYS_BOOTM_LEN=0x4000000 -a BOOTSTAGE -a BOOTSTAGE_STASH -a CMD_BOOTSTAGE -a BOOTSTAGE_STASH_ADDR=0x02400000"
+
+Raspberry Pi 4 (rpi_4_32b, lwIP):
+  <<: *sage_lab_dfn
+  needs: [ "Raspberry Pi 4 (rpi_4_32b)" ]
+  variables:
+    LABGRID_EXPORTER: "sage-exporter-rpi4-1"
+    LG_PLACE: "rpi4-1"
+    TEST_PY_BD: "rpi_4_32b"
+    OVERRIDE: "-a UNIT_TEST -a ~CMD_EFIDEBUG -a CMD_BOOTMENU -a CMD_LOG -a CMD_BOOTEFI_SELFTEST -a FIT -a FIT_SIGNATURE -a FIT_BEST_MATCH -a SYS_BOOTM_LEN=0x4000000 -a BOOTSTAGE -a BOOTSTAGE_STASH -a CMD_BOOTSTAGE -a BOOTSTAGE_STASH_ADDR=0x02400000 -a NET_LWIP"
+
+Raspberry Pi 3:
+  <<: *sage_lab_dfn
+  variables:
+    LABGRID_EXPORTER: "sage-exporter-rpi3-1"
+    LG_PLACE: "rpi3-1"
+    TEST_PY_BD: "rpi_3"
+    OVERRIDE: "-a UNIT_TEST -a ~CMD_EFIDEBUG -a CMD_BOOTMENU -a CMD_LOG -a CMD_BOOTEFI_SELFTEST -a CMD_TFTPPUT -a FIT -a FIT_SIGNATURE -a FIT_BEST_MATCH -a SYS_BOOTM_LEN=0x4000000 -a BOOTSTAGE -a BOOTSTAGE_STASH -a CMD_BOOTSTAGE -a BOOTSTAGE_STASH_ADDR=0x02400000"
+
+Raspberry Pi 3 (rpi_arm64):
+  <<: *sage_lab_dfn
+  needs: [ "Raspberry Pi 3" ]
+  variables:
+    LABGRID_EXPORTER: "sage-exporter-rpi3-1"
+    LG_PLACE: "rpi3-1"
+    TEST_PY_BD: "rpi_arm64"
+    OVERRIDE: "-a UNIT_TEST -a ~CMD_EFIDEBUG -a CMD_BOOTMENU -a CMD_LOG -a ~CMD_BOOTEFI_SELFTEST -a CMD_TFTPPUT -a FIT -a FIT_SIGNATURE -a FIT_BEST_MATCH -a SYS_BOOTM_LEN=0x4000000 -a BOOTSTAGE -a BOOTSTAGE_STASH -a CMD_BOOTSTAGE -a BOOTSTAGE_STASH_ADDR=0x02400000"
+
+Raspberry Pi 3 (rpi_arm64, lwIP):
+  <<: *sage_lab_dfn
+  needs: [ "Raspberry Pi 3 (rpi_arm64)" ]
+  variables:
+    LABGRID_EXPORTER: "sage-exporter-rpi3-1"
+    LG_PLACE: "rpi3-1"
+    TEST_PY_BD: "rpi_arm64"
+    OVERRIDE: "-a UNIT_TEST -a ~CMD_EFIDEBUG -a CMD_BOOTMENU -a CMD_LOG -a ~CMD_BOOTEFI_SELFTEST -a FIT -a FIT_SIGNATURE -a FIT_BEST_MATCH -a SYS_BOOTM_LEN=0x4000000 -a BOOTSTAGE -a BOOTSTAGE_STASH -a CMD_BOOTSTAGE -a BOOTSTAGE_STASH_ADDR=0x02400000 -a NET_LWIP"
+
+Raspberry Pi 3 (rpi_3_32b):
+  <<: *sage_lab_dfn
+  needs: [ "Raspberry Pi 3 (rpi_arm64, lwIP)" ]
+  variables:
+    LABGRID_EXPORTER: "sage-exporter-rpi3-1"
+    LG_PLACE: "rpi3-1"
+    TEST_PY_BD: "rpi_3_32b"
+    OVERRIDE: "-a UNIT_TEST -a ~CMD_EFIDEBUG -a CMD_BOOTMENU -a CMD_LOG -a CMD_BOOTEFI_SELFTEST -a CMD_TFTPPUT -a FIT -a FIT_SIGNATURE -a FIT_BEST_MATCH -a SYS_BOOTM_LEN=0x4000000 -a BOOTSTAGE -a BOOTSTAGE_STASH -a CMD_BOOTSTAGE -a BOOTSTAGE_STASH_ADDR=0x02400000"
+
+Raspberry Pi 3 (rpi_3_32b, lwIP):
+  <<: *sage_lab_dfn
+  needs: [ "Raspberry Pi 3 (rpi_3_32b)" ]
+  variables:
+    LABGRID_EXPORTER: "sage-exporter-rpi3-1"
+    LG_PLACE: "rpi3-1"
+    TEST_PY_BD: "rpi_3_32b"
+    OVERRIDE: "-a UNIT_TEST -a ~CMD_EFIDEBUG -a CMD_BOOTMENU -a CMD_LOG -a CMD_BOOTEFI_SELFTEST -a FIT -a FIT_SIGNATURE -a FIT_BEST_MATCH -a SYS_BOOTM_LEN=0x4000000 -a BOOTSTAGE -a BOOTSTAGE_STASH -a CMD_BOOTSTAGE -a BOOTSTAGE_STASH_ADDR=0x02400000 -a NET_LWIP"

.gitlab-ci.yml

@@ -5,6 +5,7 @@ variables:
   DEFAULT_AMD64_TAG: "amd64"
   DEFAULT_FAST_TAG: "fast"
   MIRROR_DOCKER: docker.io
+  SAGE_LAB: ""
   SJG_LAB: ""
   PLATFORM: linux/amd64,linux/arm64
 
@@ -18,19 +19,20 @@ workflow:
 
 # Grab our configured image.  The source for this is found
 # in the u-boot tree at tools/docker/Dockerfile
-image: ${MIRROR_DOCKER}/trini/u-boot-gitlab-ci-runner:jammy-20251013-26Nov2025
+image: ${MIRROR_DOCKER}/trini/u-boot-gitlab-ci-runner:noble-20251013-23Jan2026
 
 # We run some tests in different order, to catch some failures quicker.
 stages:
   - testsuites
   - test.py
+  - sage-lab
   - sjg-lab
   - world build
 
 .buildman_and_testpy_template: &buildman_and_testpy_dfn
   stage: test.py
   retry: 2 # QEMU may be too slow, etc.
-  needs: [ "Run binman, buildman, dtoc, Kconfig and patman testsuites" ]
+  needs: [ "Build allyesconfig, tools-only and envtools" ]
   before_script:
     # Clone uboot-test-hooks
     - git config --global --add safe.directory "${CI_PROJECT_DIR}"
@@ -59,6 +61,7 @@ stages:
       . /tmp/venv/bin/activate;
       pip install -r test/py/requirements.txt -r tools/binman/requirements.txt
         -r tools/buildman/requirements.txt -r tools/u_boot_pylib/requirements.txt
+        setuptools
 
   after_script:
     - cp -v /tmp/${TEST_PY_BD}/*.{html,css,xml} .
@@ -151,6 +154,7 @@ build all platforms in a single job:
       . /tmp/venv/bin/activate;
       pip install -r tools/binman/requirements.txt
         -r tools/buildman/requirements.txt
+        setuptools
     - ret=0;
       git config --global --add safe.directory "${CI_PROJECT_DIR}";
       ./tools/buildman/buildman -o /tmp -PEWM -x xtensa || ret=$?;
@@ -191,10 +195,14 @@ Check for configs without MAINTAINERS entry:
     - ./tools/buildman/buildman --maintainer-check
 
 # Ensure host tools build
-Build tools-only and envtools:
+Build allyesconfig, tools-only and envtools:
   extends: .testsuites
   script:
-    - make tools-only_config tools-only -j$(nproc);
+    # Allow pipefail because of how we use 'yes' here.
+    - set +o pipefail;
+      yes 0 | make allyesconfig oldconfig all -j$(nproc);
+      make mrproper;
+      make tools-only_config tools-only -j$(nproc);
       make mrproper;
       make tools-only_config envtools -j$(nproc)
 
@@ -267,6 +275,8 @@ sandbox test.py:
   variables:
     TEST_PY_BD: "sandbox"
     TEST_PY_EXTRA: "--timing"
+    # addr2line in Ubuntu 'Noble' and later are broken.
+    TEST_PY_TEST_SPEC: "not event_dump"
   <<: *buildman_and_testpy_dfn
 
 sandbox with clang test.py:
@@ -278,7 +288,9 @@ sandbox with clang test.py:
     - ${HOST}
   variables:
     TEST_PY_BD: "sandbox"
-    OVERRIDE: "-O clang-18"
+    OVERRIDE: "-O clang-20"
+    # addr2line in Ubuntu 'Noble' and later are broken.
+    TEST_PY_TEST_SPEC: "not event_dump"
   <<: *buildman_and_testpy_dfn
 
 sandbox64 test.py:
@@ -301,7 +313,7 @@ sandbox64 with clang test.py:
     - ${HOST}
   variables:
     TEST_PY_BD: "sandbox64"
-    OVERRIDE: "-O clang-18"
+    OVERRIDE: "-O clang-20"
   <<: *buildman_and_testpy_dfn
 
 sandbox64_lwip test.py:
@@ -379,6 +391,7 @@ qemu_arm64 test.py:
   variables:
     TEST_PY_BD: "qemu_arm64"
     TEST_PY_TEST_SPEC: "not sleep"
+    OVERRIDE: "-a CONFIG_SEMIHOSTING=y"
   <<: *buildman_and_testpy_dfn
 
 qemu_arm64_lwip test.py:
@@ -408,6 +421,12 @@ qemu_m68k test.py:
     OVERRIDE: "-a CONFIG_M68K_QEMU=y -a ~CONFIG_MCFTMR"
   <<: *buildman_and_testpy_dfn
 
+qemu_m68k_virt test.py:
+  variables:
+    TEST_PY_BD: "qemu-m68k"
+    TEST_PY_TEST_SPEC: "not sleep"
+  <<: *buildman_and_testpy_dfn
+
 qemu_malta test.py:
   variables:
     TEST_PY_BD: "malta"
@@ -600,6 +619,9 @@ coreboot test.py:
     TEST_PY_ID: "--id qemu"
   <<: *buildman_and_testpy_dfn
 
+# Add sage-lab stage
+include: .gitlab-ci-sage-lab.yml
+
 .sjg_lab_template: &sjg_lab_dfn
   stage: sjg-lab
   rules:
@@ -773,5 +795,5 @@ vf2:
 qemu-x86_64:
   variables:
     ROLE: qemu-x86_64
-    TEST_PY_TEST_SPEC: "and not sleep"
+    TEST_PY_TEST_SPEC: "not sleep"
   <<: *sjg_lab_dfn

.mailmap

@@ -69,7 +69,8 @@ Jagan Teki <jagannadha.sutradharudu-teki@xilinx.com>
 Jakob Unterwurzacher <jakob.unterwurzacher@cherry.de> <jakob.unterwurzacher@theobroma-systems.com>
 Jay Buddhabhatti <jay.buddhabhatti@amd.com> <jay.buddhabhatti@xilinx.com>
 Jernej Skrabec <jernej.skrabec@gmail.com> <jernej.skrabec@siol.net>
-Jerome Forissier <jerome@forissier.org> <jerome.forissier@linaro.org>
+Jerome Forissier <jerome.forissier@arm.com> <jerome@forissier.org>
+Jerome Forissier <jerome.forissier@arm.com> <jerome.forissier@linaro.org>
 John Linn <john.linn@amd.com> <john.linn@xilinx.com>
 Jyotheeswar Reddy Mutthareddyvari <jyotheeswar.reddy.mutthareddyvari@amd.com> <jyothee@xilinx.com>
 Jyotheeswar Reddy Mutthareddyvari <jyotheeswar.reddy.mutthareddyvari@amd.com> <jyotheeswar.reddy.mutthareddyvari@xilinx.com>
@@ -140,6 +141,7 @@ Srinivas Neeli <srinivas.neeli@amd.com> <srinivas.neeli@xilinx.com>
 Stefan Roese <stefan.roese@mailbox.org> <stroese>
 Stefano Babic <sbabic@nabladev.com>
 Stefano Stabellini <stefano.stabellini@amd.com> <stefano.stabellini@xilinx.com>
+Sughosh Ganu <sughosh.ganu@arm.com> <sughosh.ganu@linaro.org>
 No generic patch CC mail please <noreply@example.com> <swarren@wwwdotorg.org>
 No generic patch CC mail please <noreply@example.com> <swarren@nvidia.com>
 Sumit Garg <sumit.garg@kernel.org> <sumit.garg@linaro.org>

Kbuild

@@ -7,10 +7,11 @@
 
 generic-offsets-file := include/generated/generic-asm-offsets.h
 
-always  := $(generic-offsets-file)
+always-y  := $(generic-offsets-file)
 targets := lib/asm-offsets.s
 
-CFLAGS_REMOVE_asm-offsets.o := $(LTO_CFLAGS)
+CFLAGS_REMOVE_lib/asm-offsets.o := $(LTO_CFLAGS)
+CFLAGS_REMOVE_arch/$(ARCH)/lib/asm-offsets.o := $(LTO_CFLAGS)
 
 $(obj)/$(generic-offsets-file): $(obj)/lib/asm-offsets.s FORCE
 	$(call filechk,offsets,__GENERIC_ASM_OFFSETS_H__)
@@ -22,10 +23,11 @@ ifneq ($(wildcard $(srctree)/arch/$(ARCH)/lib/asm-offsets.c),)
 offsets-file := include/generated/asm-offsets.h
 endif
 
-always  += $(offsets-file)
+always-y  += $(offsets-file)
 targets += arch/$(ARCH)/lib/asm-offsets.s
 
-CFLAGS_asm-offsets.o := -DDO_DEPS_ONLY
+CFLAGS_lib/asm-offsets.o := -DDO_DEPS_ONLY
+CFLAGS_arch/$(ARCH)/lib/asm-offsets.o := -DDO_DEPS_ONLY
 
 $(obj)/$(offsets-file): $(obj)/arch/$(ARCH)/lib/asm-offsets.s FORCE
 	$(call filechk,offsets,__ASM_OFFSETS_H__)

Kconfig

@@ -140,6 +140,15 @@ config SPL_OPTIMIZE_INLINING
 	  do what it thinks is best, which is desirable in some cases for size
 	  reasons.
 
+config TPL_OPTIMIZE_INLINING
+	bool "Allow compiler to uninline functions marked 'inline' in TPL"
+	depends on TPL
+	help
+	  This option determines if U-Boot forces gcc to inline the functions
+	  developers have marked 'inline'. Doing so takes away freedom from gcc to
+	  do what it thinks is best, which is desirable in some cases for size
+	  reasons.
+
 config ARCH_SUPPORTS_LTO
 	bool
 
@@ -163,15 +172,6 @@ config LTO
 
 	  If unsure, say n.
 
-config TPL_OPTIMIZE_INLINING
-	bool "Allow compiler to uninline functions marked 'inline' in TPL"
-	depends on TPL
-	help
-	  This option determines if U-Boot forces gcc to inline the functions
-	  developers have marked 'inline'. Doing so takes away freedom from gcc to
-	  do what it thinks is best, which is desirable in some cases for size
-	  reasons.
-
 config CC_COVERAGE
 	bool "Enable code coverage analysis"
 	depends on SANDBOX
@@ -299,8 +299,8 @@ config SYS_MALLOC_F_LEN
 			 ROCKCHIP_RV1108
 	default 0x600 if ARCH_ZYNQMP_R5 || ARCH_ZYNQMP
 	default 0x800 if ARCH_ZYNQ || ROCKCHIP_RK3128 || ROCKCHIP_RK3188 || \
-			 ROCKCHIP_RK322X || X86
-	default 0x1000 if ARCH_MESON || ARCH_BMIPS || ARCH_MTMIPS
+			 ROCKCHIP_RK322X
+	default 0x1000 if ARCH_MESON || ARCH_BMIPS || ARCH_MTMIPS || X86
 	default 0x1800 if ARCH_TEGRA
 	default 0x4000 if SANDBOX || RISCV || ARCH_APPLE || ROCKCHIP_RK3368 || \
 			  ROCKCHIP_RK3399

MAINTAINERS

@@ -186,6 +186,7 @@ F:	drivers/video/meson/
 F:	drivers/watchdog/meson_gxbb_wdt.c
 F:	include/configs/meson64.h
 F:	include/configs/meson64_android.h
+F:	tools/amlimage*
 F:	doc/board/amlogic/
 N:	meson
 
@@ -314,8 +315,8 @@ F:	arch/arm/include/asm/arch-imx*/
 F:	arch/arm/include/asm/arch-mx*/
 F:	arch/arm/include/asm/arch-vf610/
 F:	arch/arm/include/asm/mach-imx/
-F:	board/freescale/*mx*/
-F:	board/freescale/common/
+F:	board/nxp/*mx*/
+F:	board/nxp/common/
 F:	common/spl/spl_imx_container.c
 F:	doc/board/nxp/
 F:	doc/imx/
@@ -415,6 +416,7 @@ M:	Chunfeng Yun <chunfeng.yun@mediatek.com>
 M:	Igor Belwon <igor.belwon@mentallysanemainliners.org>
 R:	GSS_MTK_Uboot_upstream <GSS_MTK_Uboot_upstream@mediatek.com>
 S:	Maintained
+F:	arch/arm/dts/mt*
 F:	arch/arm/mach-mediatek/
 F:	arch/arm/include/asm/arch-mediatek/
 F:	board/mediatek/
@@ -624,19 +626,17 @@ S:	Supported
 F:	arch/arm/dts/am335x-sancloud*
 
 ARM SC5XX
-M:	Nathan Barrett-Morrison <nathan.morrison@timesys.com>
 M:	Greg Malysa <malysagreg@gmail.com>
-M:	Ian Roberts <ian.roberts@timesys.com>
 M:	Vasileios Bimpikas <vasileios.bimpikas@analog.com>
-M:	Utsav Agarwal <utsav.agarwal@analog.com>
 M:	Arturs Artamonovs <arturs.artamonovs@analog.com>
-L:	adsp-linux@analog.com
+L:	linux@analog.com
 S:	Supported
-T:	git https://github.com/analogdevicesinc/lnxdsp-u-boot
+T:	git https://github.com/analogdevicesinc/u-boot
 F:	arch/arm/dts/sc5*
 F:	arch/arm/include/asm/arch-adi/
 F:	arch/arm/mach-sc5xx/
 F:	board/adi/
+F:	configs/sc5*
 F:	doc/device-tree-bindings/arm/adi/adi,sc5xx.yaml
 F:	doc/device-tree-bindings/clock/adi,sc5xx-clocks.yaml
 F:	doc/device-tree-bindings/pinctrl/adi,adsp-pinctrl.yaml
@@ -656,6 +656,7 @@ F:	drivers/timer/adi_sc5xx_timer.c
 F:	drivers/usb/musb-new/sc5xx.c
 F:	drivers/watchdog/adi_wdt.c
 F:	include/configs/sc5*
+F:	include/dt-bindings/clock/adi-sc5xx-clock.h
 F:	include/dt-bindings/pinctrl/adi-adsp.h
 F:	include/env/adi/
 
@@ -747,7 +748,6 @@ N:	stm
 N:	stm32
 
 ARM SUNXI
-M:	Jagan Teki <jagan@amarulasolutions.com>
 M:	Andre Przywara <andre.przywara@arm.com>
 S:	Maintained
 T:	git https://source.denx.de/u-boot/custodians/u-boot-sunxi.git
@@ -1044,15 +1044,6 @@ T:	git https://source.denx.de/u-boot/custodians/u-boot-clk.git
 F:	drivers/clk/
 F:	drivers/clk/imx/
 
-COLDFIRE
-M:	Huan Wang <alison.wang@nxp.com>
-M:	Angelo Dureghello <angelo@kernel-space.org>
-S:	Maintained
-T:	git https://source.denx.de/u-boot/custodians/u-boot-coldfire.git
-F:	arch/m68k/
-F:	doc/arch/m68k.rst
-F:	drivers/watchdog/mcf_wdt.c
-
 CPU
 M:	Simon Glass <sjg@chromium.org>
 M:	Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
@@ -1152,8 +1143,7 @@ F:	tools/file2include.c
 F:	tools/mkeficapsule.c
 
 ENVIRONMENT
-M:	Joe Hershberger <joe.hershberger@ni.com>
-S:	Maintained
+S:	Orphaned
 F:	env/
 F:	include/env/
 F:	include/env*
@@ -1246,7 +1236,7 @@ F:	drivers/watchdog/sp805_wdt.c
 F:	drivers/watchdog/sbsa_gwdt.c
 
 FWU Multi Bank Update
-M:	Sughosh Ganu <sughosh.ganu@linaro.org>
+M:	Sughosh Ganu <sughosh.ganu@arm.com>
 S:	Maintained
 T:	git https://source.denx.de/u-boot/custodians/u-boot-efi.git
 F:	lib/fwu_updates/*
@@ -1259,6 +1249,29 @@ S:	Maintained
 F:	drivers/misc/gsc.c
 F:	include/gsc.h
 
+GOLDFISH SERIAL DRIVER
+M:	Kuan-Wei Chiu <visitorckw@gmail.com>
+S:	Maintained
+F:	drivers/serial/serial_goldfish.c
+F:	include/goldfish_tty.h
+
+GOLDFISH TIMER DRIVER
+M:	Kuan-Wei Chiu <visitorckw@gmail.com>
+S:	Maintained
+F:	drivers/timer/goldfish_timer.c
+F:	include/goldfish_timer.h
+
+INTERCONNECT:
+M:	Neil Armstrong <neil.armstrong@linaro.org>
+S:	Maintained
+T:	git https://source.denx.de/u-boot/u-boot.git
+F:	arch/sandbox/include/asm/interconnect.h
+F:	doc/api/interconnect.rst
+F:	drivers/interconnect/
+F:	include/interconnect-uclass.h
+F:	include/interconnect.h
+F:	test/dm/interconnect.c
+
 I2C
 M:	Heiko Schocher <hs@nabladev.com>
 S:	Maintained
@@ -1282,12 +1295,6 @@ F:	doc/README.kwbimage
 F:	doc/kwboot.1
 F:	tools/kwb*
 
-LED
-M:	Ivan Vozvakhov <i.vozvakhov@vk.team>
-S:	Supported
-F:	doc/device-tree-bindings/leds/leds-pwm.txt
-F:	drivers/led/led_pwm.c
-
 LOGGING
 M:	Simon Glass <sjg@chromium.org>
 S:	Maintained
@@ -1300,6 +1307,21 @@ F:	lib/getopt.c
 F:	test/log/
 F:	test/py/tests/test_log.py
 
+M680X0 ARCHITECTURE
+M:	Kuan-Wei Chiu <visitorckw@gmail.com>
+S:	Maintained
+F:	arch/m68k/cpu/m680x0/
+F:	arch/m68k/include/asm/bootinfo.h
+
+M68K
+M:	Angelo Dureghello <angelo@kernel-space.org>
+M:	Kuan-Wei Chiu <visitorckw@gmail.com>
+S:	Maintained
+T:	git https://source.denx.de/u-boot/custodians/u-boot-coldfire.git
+F:	arch/m68k/
+F:	doc/arch/m68k.rst
+F:	drivers/watchdog/mcf_wdt.c
+
 MALI DISPLAY PROCESSORS
 M:	Liviu Dudau <liviu.dudau@foss.arm.com>
 S:	Supported
@@ -1429,9 +1451,7 @@ F:	drivers/mmc/
 N:	mmc
 
 NETWORK
-M:	Joe Hershberger <joe.hershberger@ni.com>
-M:	Ramon Fried <rfried.dev@gmail.com>
-M:	Jerome Forissier <jerome@forissier.org>
+M:	Jerome Forissier <jerome.forissier@arm.com>
 S:	Maintained
 T:	git https://source.denx.de/u-boot/custodians/u-boot-net.git
 F:	drivers/net/
@@ -1439,7 +1459,7 @@ F:	include/net.h
 F:	net/
 
 NETWORK (LWIP)
-M:	Jerome Forissier <jerome@forissier.org>
+M:	Jerome Forissier <jerome.forissier@arm.com>
 S:	Maintained
 T:	git https://source.denx.de/u-boot/custodians/u-boot-net.git
 F:	cmd/lwip/
@@ -1516,8 +1536,7 @@ F:	drivers/pci/pcie_dw_imx.c
 F:	drivers/phy/phy-imx8m-pcie.c
 
 PCI Endpoint
-M:	Ramon Fried <rfried.dev@gmail.com>
-S:	Maintained
+S:	Orphaned
 F:	drivers/pci_endpoint/
 F:  include/pci_ep.h
 
@@ -1574,6 +1593,17 @@ S:	Maintained
 T:	git https://source.denx.de/u-boot/custodians/u-boot-mpc85xx.git
 F:	arch/powerpc/cpu/mpc85xx/
 
+PWM LED
+S:	Orphan
+F:	doc/device-tree-bindings/leds/leds-pwm.txt
+F:	drivers/led/led_pwm.c
+
+QEMU VIRTUAL SYSTEM CONTROLLER
+M:	Kuan-Wei Chiu <visitorckw@gmail.com>
+S:	Maintained
+F:	drivers/sysreset/sysreset_qemu_virt_ctrl.c
+F:	include/qemu_virt_ctrl.h
+
 RAW NAND
 M:	Dario Binacchi <dario.binacchi@amarulasolutions.com>
 M:	Michael Trimarchi <michael@amarulasolutions.com>
@@ -1614,7 +1644,7 @@ F:	drivers/pinctrl/pinctrl-th1520.c
 F:	drivers/ram/thead/th1520_ddr.c
 
 RNG
-M:	Sughosh Ganu <sughosh.ganu@linaro.org>
+M:	Sughosh Ganu <sughosh.ganu@arm.com>
 R:	Heinrich Schuchardt <xypron.glpk@gmx.de>
 S:	Maintained
 F:	cmd/rng.c
@@ -1686,14 +1716,29 @@ F:	include/slre.h
 F:	lib/slre.c
 F:	test/lib/slre.c
 
+SM3
+M:	Heiko Schocher <hs@nabladev.com>
+S:	Maintained
+F:	cmd/sm3sum.c
+F:	include/u-boot/sm3.h
+F:	lib/sm3.c
+
+SMBIOS
+M:	Raymond Mao <raymondmaoca@gmail.com>
+S:	Maintained
+F:	arch/arm/dts/smbios_generic.dtsi
+F:	cmd/smbios.c
+F:	drivers/sysinfo/smbios.c
+F:	include/smbios*
+F:	lib/smbios.c
+
 SMCCC TRNG
 M:	Etienne Carriere <etienne.carriere@linaro.org>
 S:	Maintained
 F:	drivers/rng/smccc_trng.c
 
 SPI
-M:	Jagan Teki <jagan@amarulasolutions.com>
-S:	Maintained
+S:	Orphaned
 T:	git https://source.denx.de/u-boot/custodians/u-boot-spi.git
 F:	drivers/spi/
 F:	include/spi*
@@ -1707,9 +1752,8 @@ T:	git https://source.denx.de/u-boot/custodians/u-boot-nand-flash.git
 F:	drivers/mtd/nand/spi/
 
 SPI-NOR
-M:	Jagan Teki <jagan@amarulasolutions.com>
 M:	Vignesh R <vigneshr@ti.com>
-R:	Tudor Ambarus <tudor.ambarus@linaro.org>
+R:	Takahiro Kuwano <takahiro.kuwano@infineon.com>
 S:	Maintained
 F:	drivers/mtd/spi/
 F:	include/spi_flash.h
@@ -1884,7 +1928,7 @@ F:	drivers/usb/host/xhci*
 F:	include/usb/xhci.h
 
 UTHREAD
-M:	Jerome Forissier <jerome@forissier.org>
+M:	Jerome Forissier <jerome.forissier@arm.com>
 S:	Maintained
 F:	cmd/spawn.c
 F:	include/uthread.h

Makefile

@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0+
 
 VERSION = 2026
-PATCHLEVEL = 01
+PATCHLEVEL = 04
 SUBLEVEL =
 EXTRAVERSION =
 NAME =
@@ -12,32 +12,12 @@ NAME =
 # Comments in this file are targeted only to the developer, do not
 # expect to learn how to build the kernel reading this file.
 
-# That's our default target when none is given on the command line
-PHONY := _all
-_all:
+$(if $(filter __%, $(MAKECMDGOALS)), \
+	$(error targets prefixed with '__' are only for internal use))
 
-# Determine target architecture for the sandbox
-include include/host_arch.h
-ifeq ("", "$(CROSS_COMPILE)")
-  MK_ARCH="${shell uname -m}"
-else
-  MK_ARCH="${shell echo $(CROSS_COMPILE) | sed -n 's/^\(.*ccache\)\{0,1\}[[:space:]]*\([^\/]*\/\)*\([^-]*\)-[^[:space:]]*/\3/p'}"
-endif
-unexport HOST_ARCH
-ifeq ("x86_64", $(MK_ARCH))
-  export HOST_ARCH=$(HOST_ARCH_X86_64)
-else ifneq (,$(findstring $(MK_ARCH), "i386" "i486" "i586" "i686"))
-  export HOST_ARCH=$(HOST_ARCH_X86)
-else ifneq (,$(findstring $(MK_ARCH), "aarch64" "armv8l"))
-  export HOST_ARCH=$(HOST_ARCH_AARCH64)
-else ifneq (,$(findstring $(MK_ARCH), "arm" "armv5tel" "armv6l" "armv7" "armv7a" "armv7l"))
-  export HOST_ARCH=$(HOST_ARCH_ARM)
-else ifeq ("riscv32", $(MK_ARCH))
-  export HOST_ARCH=$(HOST_ARCH_RISCV32)
-else ifeq ("riscv64", $(MK_ARCH))
-  export HOST_ARCH=$(HOST_ARCH_RISCV64)
-endif
-undefine MK_ARCH
+# That's our default target when none is given on the command line
+PHONY := __all
+__all:
 
 # We are using a recursive build, so we need to do a little thinking
 # to get the ordering right.
@@ -125,79 +105,88 @@ endif
 
 export quiet Q KBUILD_VERBOSE
 
-# kbuild supports saving output files in a separate directory.
-# To locate output files in a separate directory two syntaxes are supported.
-# In both cases the working directory must be the root of the kernel src.
+# Kbuild will save output files in the current working directory.
+# This does not need to match to the root of the kernel source tree.
+#
+# For example, you can do this:
+#
+#  cd /dir/to/store/output/files; make -f /dir/to/kernel/source/Makefile
+#
+# If you want to save output files in a different location, there are
+# two syntaxes to specify it.
+#
 # 1) O=
 # Use "make O=dir/to/store/output/files/"
 #
 # 2) Set KBUILD_OUTPUT
-# Set the environment variable KBUILD_OUTPUT to point to the directory
-# where the output files shall be placed.
-# export KBUILD_OUTPUT=dir/to/store/output/files/
-# make
+# Set the environment variable KBUILD_OUTPUT to point to the output directory.
+# export KBUILD_OUTPUT=dir/to/store/output/files/; make
 #
 # The O= assignment takes precedence over the KBUILD_OUTPUT environment
 # variable.
 
-# KBUILD_SRC is not intended to be used by the regular user (for now),
-# it is set on invocation of make with KBUILD_OUTPUT or O= specified.
-
-# OK, Make called in directory where kernel src resides
-# Do we want to locate output files in a separate directory?
+# Do we want to change the working directory?
 ifeq ("$(origin O)", "command line")
   KBUILD_OUTPUT := $(O)
 endif
 
-ifneq ($(words $(subst :, ,$(CURDIR))), 1)
-  $(error main directory cannot contain spaces nor colons)
-endif
 
 ifneq ($(KBUILD_OUTPUT),)
-# check that the output directory actually exists
-saved-output := $(KBUILD_OUTPUT)
-KBUILD_OUTPUT := $(shell mkdir -p $(KBUILD_OUTPUT) && cd $(KBUILD_OUTPUT) \
-								&& pwd)
-$(if $(KBUILD_OUTPUT),, \
-     $(error failed to create output directory "$(saved-output)"))
+# Make's built-in functions such as $(abspath ...), $(realpath ...) cannot
+# expand a shell special character '~'. We use a somewhat tedious way here.
+abs_objtree := $(shell mkdir -p $(KBUILD_OUTPUT) && cd $(KBUILD_OUTPUT) && pwd)
+$(if $(abs_objtree),, \
+     $(error failed to create output directory "$(KBUILD_OUTPUT)"))
 
+# $(realpath ...) resolves symlinks
+abs_objtree := $(realpath $(abs_objtree))
+else
+abs_objtree := $(CURDIR)
+endif # ifneq ($(KBUILD_OUTPUT),)
+
+ifeq ($(abs_objtree),$(CURDIR))
+# Suppress "Entering directory ..." unless we are changing the work directory.
+MAKEFLAGS += --no-print-directory
+else
+need-sub-make := 1
+endif
+
+this-makefile := $(lastword $(MAKEFILE_LIST))
+abs_srctree := $(realpath $(dir $(this-makefile)))
+
+ifneq ($(words $(subst :, ,$(abs_srctree))), 1)
+$(error source directory cannot contain spaces or colons)
+endif
+
+ifneq ($(abs_srctree),$(abs_objtree))
 # Look for make include files relative to root of kernel src
 #
-# This does not become effective immediately because MAKEFLAGS is re-parsed
-# once after the Makefile is read.  It is OK since we are going to invoke
-# 'sub-make' below.
-MAKEFLAGS += --include-dir=$(CURDIR)
-
-need-sub-make := 1
-else
-
-# Do not print "Entering directory ..." at all for in-tree build.
-MAKEFLAGS += --no-print-directory
-
-endif # ifneq ($(KBUILD_OUTPUT),)
+# --included-dir is added for backward compatibility, but you should not rely on
+# it. Please add $(srctree)/ prefix to include Makefiles in the source tree.
+MAKEFLAGS += --include-dir=$(abs_srctree)
+endif
 
 ifneq ($(filter 3.%,$(MAKE_VERSION)),)
 # 'MAKEFLAGS += -rR' does not immediately become effective for GNU Make 3.x
 # We need to invoke sub-make to avoid implicit rules in the top Makefile.
 need-sub-make := 1
 # Cancel implicit rules for this Makefile.
-$(lastword $(MAKEFILE_LIST)): ;
+$(this-makefile): ;
 endif
 
+export abs_srctree abs_objtree
 export sub_make_done := 1
 
 ifeq ($(need-sub-make),1)
 
-PHONY += $(MAKECMDGOALS) sub-make
+PHONY += $(MAKECMDGOALS) __sub-make
 
-$(filter-out _all sub-make $(CURDIR)/Makefile, $(MAKECMDGOALS)) _all: sub-make
+$(filter-out $(this-makefile), $(MAKECMDGOALS)) __all: __sub-make
 	@:
 
 # Invoke a second make in the output directory, passing relevant variables
-sub-make:
-	$(Q)$(MAKE) \
-	$(if $(KBUILD_OUTPUT),-C $(KBUILD_OUTPUT) KBUILD_SRC=$(CURDIR)) \
-	-f $(CURDIR)/Makefile $(filter-out _all sub-make,$(MAKECMDGOALS))
+__sub-make:
+	$(Q)$(MAKE) -C $(abs_objtree) -f $(abs_srctree)/Makefile $(MAKECMDGOALS)
 
 endif # need-sub-make
 endif # sub_make_done
@@ -210,6 +199,53 @@ ifeq ($(need-sub-make),)
 # so that IDEs/editors are able to understand relative filenames.
 MAKEFLAGS += --no-print-directory
 
+ifeq ($(abs_srctree),$(abs_objtree))
+        # building in the source tree
+        srctree := .
+	building_out_of_srctree :=
+else
+        ifeq ($(abs_srctree)/,$(dir $(abs_objtree)))
+                # building in a subdirectory of the source tree
+                srctree := ..
+        else
+                srctree := $(abs_srctree)
+        endif
+	building_out_of_srctree := 1
+endif
+
+ifneq ($(KBUILD_ABS_SRCTREE),)
+srctree := $(abs_srctree)
+endif
+
+objtree		:= .
+obj		:= $(objtree)
+VPATH		:= $(srctree)
+
+export building_out_of_srctree srctree objtree VPATH
+
+# Determine target architecture for the sandbox
+include $(srctree)/include/host_arch.h
+ifeq ("", "$(CROSS_COMPILE)")
+  MK_ARCH="${shell uname -m}"
+else
+  MK_ARCH="${shell echo $(CROSS_COMPILE) | sed -n 's/^\(.*ccache\)\{0,1\}[[:space:]]*\([^\/]*\/\)*\([^-]*\)-[^[:space:]]*/\3/p'}"
+endif
+unexport HOST_ARCH
+ifeq ("x86_64", $(MK_ARCH))
+  export HOST_ARCH=$(HOST_ARCH_X86_64)
+else ifneq (,$(findstring $(MK_ARCH), "i386" "i486" "i586" "i686"))
+  export HOST_ARCH=$(HOST_ARCH_X86)
+else ifneq (,$(findstring $(MK_ARCH), "aarch64" "armv8l"))
+  export HOST_ARCH=$(HOST_ARCH_AARCH64)
+else ifneq (,$(findstring $(MK_ARCH), "arm" "armv5tel" "armv6l" "armv7" "armv7a" "armv7l"))
+  export HOST_ARCH=$(HOST_ARCH_ARM)
+else ifeq ("riscv32", $(MK_ARCH))
+  export HOST_ARCH=$(HOST_ARCH_RISCV32)
+else ifeq ("riscv64", $(MK_ARCH))
+  export HOST_ARCH=$(HOST_ARCH_RISCV64)
+endif
+undefine MK_ARCH
+
 # Call a source code checker (by default, "sparse") as part of the
 # C compilation.
 #
@@ -242,27 +278,7 @@ ifeq ("$(origin M)", "command line")
   KBUILD_EXTMOD := $(M)
 endif
 
-ifeq ($(KBUILD_SRC),)
-        # building in the source tree
-        srctree := .
-else
-        ifeq ($(KBUILD_SRC)/,$(dir $(CURDIR)))
-                # building in a subdirectory of the source tree
-                srctree := ..
-        else
-                srctree := $(KBUILD_SRC)
-        endif
-endif
-
-export KBUILD_CHECKSRC KBUILD_EXTMOD KBUILD_SRC
-
-objtree		:= .
-src		:= $(srctree)
-obj		:= $(objtree)
-
-VPATH		:= $(srctree)
-
-export srctree objtree VPATH
+export KBUILD_CHECKSRC KBUILD_EXTMOD
 
 # To make sure we do not include .config for any of the *config targets
 # catch them early, and hand them over to scripts/kconfig/Makefile
@@ -291,6 +307,7 @@ config-targets  := 0
 mixed-targets   := 0
 dot-config      := 1
 may-sync-config := 1
+single-build	:= 0
 
 ifneq ($(filter $(no-dot-config-targets), $(MAKECMDGOALS)),)
 	ifeq ($(filter-out $(no-dot-config-targets), $(MAKECMDGOALS)),)
@@ -349,7 +366,9 @@ __build_one_by_one:
 
 else
 
-include scripts/Kbuild.include
+include $(srctree)/scripts/Kbuild.uboot
+
+include $(srctree)/scripts/Makefile.compiler
 
 # Read UBOOTRELEASE from include/config/uboot.release (if it exists)
 UBOOTRELEASE = $(shell cat include/config/uboot.release 2> /dev/null)
@@ -357,7 +376,7 @@ UBOOTVERSION = $(VERSION)$(if $(PATCHLEVEL),.$(PATCHLEVEL)$(if $(SUBLEVEL),.$(SU
 export VERSION PATCHLEVEL SUBLEVEL UBOOTRELEASE UBOOTVERSION
 
 # Modified for U-Boot
--include scripts/subarch.include
+-include $(srctree)/scripts/subarch.include
 
 # Cross compiling and selecting different set of gcc/bin-utils
 # ---------------------------------------------------------------------------
@@ -408,9 +427,7 @@ KCONFIG_CONFIG	?= .config
 export KCONFIG_CONFIG
 
 # SHELL used by kbuild
-CONFIG_SHELL := $(shell if [ -x "$$BASH" ]; then echo $$BASH; \
-	  else if [ -x /bin/bash ]; then echo /bin/bash; \
-	  else echo sh; fi ; fi)
+CONFIG_SHELL := sh
 
 HOST_LFS_CFLAGS := $(shell getconf LFS_CFLAGS 2>/dev/null)
 HOST_LFS_LDFLAGS := $(shell getconf LFS_LDFLAGS 2>/dev/null)
@@ -443,7 +460,7 @@ endef
 export size_check
 
 export KBUILD_MODULES KBUILD_BUILTIN
-export KBUILD_CHECKSRC KBUILD_SRC KBUILD_EXTMOD
+export KBUILD_CHECKSRC KBUILD_EXTMOD
 
 # Make variables (CC, etc...)
 AS		= $(CROSS_COMPILE)as
@@ -460,12 +477,20 @@ READELF		= $(CROSS_COMPILE)readelf
 LEX		= flex
 YACC		= bison
 AWK		= awk
+BASH		= bash
 INSTALLKERNEL  := installkernel
 DEPMOD		= /sbin/depmod
+KBZIP2		= bzip2
+KGZIP		= gzip
+KLZOP		= lzop
+LZMA		= lzma
+LZ4		= lz4c
 PERL		= perl
 PYTHON		= python
 PYTHON2		= python2
 PYTHON3		= python3
+XZ		= xz
+ZSTD		= zstd
 
 # The devicetree compiler and pylibfdt are automatically built unless DTC is
 # provided. If DTC is provided, it is assumed the pylibfdt is available too.
@@ -497,7 +522,7 @@ USERINCLUDE    := \
 # Needed to be compatible with the O= option
 UBOOTINCLUDE    := \
 	-Iinclude \
-	$(if $(KBUILD_SRC), -I$(srctree)/include) \
+	$(if $(building_out_of_srctree), -I$(srctree)/include) \
 	$(if $(CONFIG_$(XPL_)MBEDTLS_LIB), \
 		"-DMBEDTLS_CONFIG_FILE=\"mbedtls_def_config.h\"" \
 		-I$(srctree)/lib/mbedtls \
@@ -533,9 +558,10 @@ KBUILD_LDFLAGS_MODULE := -T $(srctree)/scripts/module-common.lds
 KBUILD_LDFLAGS :=
 GCC_PLUGINS_CFLAGS :=
 
-export ARCH SRCARCH CONFIG_SHELL HOSTCC KBUILD_HOSTCFLAGS CROSS_COMPILE AS LD CC
+export ARCH SRCARCH CONFIG_SHELL BASH HOSTCC KBUILD_HOSTCFLAGS CROSS_COMPILE AS LD CC
 export CPP AR NM STRIP OBJCOPY OBJDUMP KBUILD_HOSTLDFLAGS KBUILD_HOSTLDLIBS
 export MAKE LEX YACC AWK INSTALLKERNEL PERL PYTHON PYTHON2 PYTHON3 UTS_MACHINE
+export KGZIP KBZIP2 KLZOP LZMA LZ4 XZ ZSTD
 export HOSTCXX KBUILD_HOSTCXXFLAGS LDFLAGS_MODULE CHECK CHECKFLAGS
 
 export KBUILD_CPPFLAGS NOSTDINC_FLAGS LINUXINCLUDE OBJCOPYFLAGS KBUILD_LDFLAGS
@@ -573,6 +599,14 @@ ifeq ($(NO_PYTHON),)
 PYTHON_ENABLE=y
 endif
 
+# Files to ignore in find ... statements
+
+export RCS_FIND_IGNORE := \( -name SCCS -o -name BitKeeper -o -name .svn -o    \
+			  -name CVS -o -name .pc -o -name .hg -o -name .git \) \
+			  -prune -o
+export RCS_TAR_IGNORE := --exclude SCCS --exclude BitKeeper --exclude .svn \
+			 --exclude CVS --exclude .pc --exclude .hg --exclude .git
+
 # ===========================================================================
 # Rules shared between *config targets and build targets
 
@@ -580,18 +614,34 @@ endif
 PHONY += scripts_basic
 scripts_basic:
 	$(Q)$(MAKE) $(build)=scripts/basic
-	$(Q)rm -f .tmp_quiet_recordmcount
 
 PHONY += outputmakefile
+ifdef building_out_of_srctree
+# Before starting out-of-tree build, make sure the source tree is clean.
 # outputmakefile generates a Makefile in the output directory, if using a
 # separate output directory. This allows convenient use of make in the
 # output directory.
 # At the same time when output Makefile generated, generate .gitignore to
 # ignore whole output directory
+
+quiet_cmd_makefile = GEN     Makefile
+      cmd_makefile = { \
+	echo "\# Automatically generated by $(srctree)/Makefile: don't edit"; \
+	echo "include $(srctree)/Makefile"; \
+	} > Makefile
+
 outputmakefile:
-ifneq ($(KBUILD_SRC),)
+	$(Q)if [ -f $(srctree)/.config -o \
+		 -d $(srctree)/include/config -o \
+		 -d $(srctree)/arch/$(SRCARCH)/include/generated ]; then \
+		echo >&2 "***"; \
+		echo >&2 "*** The source tree is not clean, please run 'make$(if $(findstring command line, $(origin ARCH)), ARCH=$(ARCH)) mrproper'"; \
+		echo >&2 "*** in $(abs_srctree)";\
+		echo >&2 "***"; \
+		false; \
+	fi
 	$(Q)ln -fsn $(srctree) source
-	$(Q)$(CONFIG_SHELL) $(srctree)/scripts/mkmakefile $(srctree)
+	$(call cmd,makefile)
 	$(Q)test -e .gitignore || \
 	{ echo "# this is build directory, ignore it"; echo "*"; } > .gitignore
 endif
@@ -656,9 +706,9 @@ else
 # but instead _all depend on modules
 PHONY += all
 ifeq ($(KBUILD_EXTMOD),)
-_all: all
+__all: all
 else
-_all: modules
+__all: modules
 endif
 
 # Decide whether to build built-in, modular, or both.
@@ -778,8 +828,8 @@ ifneq ($(wildcard include/config/auto.conf),)
 autoconf_is_old := $(shell find . -path ./$(KCONFIG_CONFIG) -newer \
 						include/config/auto.conf)
 ifeq ($(autoconf_is_old),)
-include config.mk
-include arch/$(ARCH)/Makefile
+include $(srctree)/config.mk
+include $(srctree)/arch/$(ARCH)/Makefile
 endif
 endif
 endif
@@ -869,6 +919,11 @@ endif
 
 ifdef CONFIG_CC_OPTIMIZE_FOR_SIZE
 KBUILD_CFLAGS	+= -Os
+else ifdef CONFIG_CC_OPTIMIZE_FOR_DEBUG
+-KBUILD_CFLAGS  += -Og
+# Avoid false positives -Wmaybe-uninitialized
+# https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78394
+KBUILD_CFLAGS  += -Wno-maybe-uninitialized
 else
 KBUILD_CFLAGS   += -O2
 endif
@@ -880,8 +935,8 @@ endif
 # Tell gcc to never replace conditional load with a non-conditional one
 KBUILD_CFLAGS	+= $(call cc-option,--param=allow-store-data-races=0)
 
-include scripts/Makefile.kcov
-include scripts/Makefile.gcc-plugins
+include $(srctree)/scripts/Makefile.kcov
+include $(srctree)/scripts/Makefile.gcc-plugins
 LTO_CFLAGS :=
 LTO_FINAL_LDFLAGS :=
 export LTO_CFLAGS LTO_FINAL_LDFLAGS
@@ -969,7 +1024,7 @@ KBUILD_CFLAGS += $(call cc-disable-warning, unused-but-set-variable)
 # Prohibit date/time macros, which would make the build non-deterministic
 KBUILD_CFLAGS   += $(call cc-option,-Werror=date-time)
 
-include scripts/Makefile.extrawarn
+include $(srctree)/scripts/Makefile.extrawarn
 
 # Add user supplied CPPFLAGS, AFLAGS and CFLAGS as the last assignments
 KBUILD_CPPFLAGS += $(KCPPFLAGS)
@@ -986,7 +1041,7 @@ KBUILD_HOSTCFLAGS += $(if $(CONFIG_TOOLS_DEBUG),-g)
 # Needed to be compatible with the O= option
 UBOOTINCLUDE    := \
 	-Iinclude \
-	$(if $(KBUILD_SRC), -I$(srctree)/include) \
+	$(if $(building_out_of_srctree), -I$(srctree)/include) \
 	$(if $(CONFIG_$(XPL_)MBEDTLS_LIB), \
 		"-DMBEDTLS_CONFIG_FILE=\"mbedtls_def_config.h\"" \
 		-I$(srctree)/lib/mbedtls \
@@ -1187,12 +1242,8 @@ endif
 endif
 
 ifdef CONFIG_FUNCTION_TRACER
-ifdef CONFIG_FTRACE_MCOUNT_RECORD
-  # gcc 5 supports generating the mcount tables directly
-  ifeq ($(call cc-option-yn,-mrecord-mcount),y)
-    CC_FLAGS_FTRACE	+= -mrecord-mcount
-    export CC_USING_RECORD_MCOUNT := 1
-  endif
+ifdef CONFIG_FTRACE_MCOUNT_USE_CC
+  CC_FLAGS_FTRACE	+= -mrecord-mcount
   ifdef CONFIG_HAVE_NOP_MCOUNT
     ifeq ($(call cc-option-yn, -mnop-mcount),y)
       CC_FLAGS_FTRACE	+= -mnop-mcount
@@ -1200,7 +1251,17 @@ ifdef CONFIG_FTRACE_MCOUNT_RECORD
     endif
   endif
 endif
+ifdef CONFIG_FTRACE_MCOUNT_USE_OBJTOOL
+  CC_FLAGS_USING	+= -DCC_USING_NOP_MCOUNT
+endif
+ifdef CONFIG_FTRACE_MCOUNT_USE_RECORDMCOUNT
+  ifdef CONFIG_HAVE_C_RECORDMCOUNT
+    BUILD_C_RECORDMCOUNT := y
+    export BUILD_C_RECORDMCOUNT
+  endif
+endif
 ifdef CONFIG_HAVE_FENTRY
+  # s390-linux-gnu-gcc did not support -mfentry until gcc-9.
   ifeq ($(call cc-option-yn, -mfentry),y)
     CC_FLAGS_FTRACE	+= -mfentry
     CC_FLAGS_USING	+= -DCC_USING_FENTRY
@@ -1209,12 +1270,6 @@ endif
 export CC_FLAGS_FTRACE
 KBUILD_CFLAGS	+= $(CC_FLAGS_FTRACE) $(CC_FLAGS_USING)
 KBUILD_AFLAGS	+= $(CC_FLAGS_USING)
-ifdef CONFIG_DYNAMIC_FTRACE
-	ifdef CONFIG_HAVE_C_RECORDMCOUNT
-		BUILD_C_RECORDMCOUNT := y
-		export BUILD_C_RECORDMCOUNT
-	endif
-endif
 endif
 
 # Add optional build target if defined in board/cpu/soc headers
@@ -1430,10 +1485,10 @@ MKIMAGEFLAGS_fit-dtb.blob = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
 MKIMAGEFLAGS_fit-dtb.blob += -B 0x8
 
 ifneq ($(EXT_DTB),)
-u-boot-fit-dtb.bin: u-boot-nodtb.bin $(EXT_DTB)
+u-boot-fit-dtb.bin: u-boot-nodtb.bin $(EXT_DTB) FORCE
 		$(call if_changed,cat)
 else
-u-boot-fit-dtb.bin: u-boot-nodtb.bin $(FINAL_DTB_CONTAINER)
+u-boot-fit-dtb.bin: u-boot-nodtb.bin $(FINAL_DTB_CONTAINER) FORCE
 	$(call if_changed,cat)
 endif
 
@@ -1528,7 +1583,7 @@ binary_size_check: u-boot-nodtb.bin FORCE
 	map_size=$(shell cat u-boot.map | \
 		awk ' \
 			/_image_copy_start/ { start = $$1 } \
-			/_image_binary_end/ { end = $$1 } \
+			/_image_binary_end/ { end = $$1;exit } \
 			END { \
 				if (start != "" && end != "") \
 					print end " " start; \
@@ -1778,14 +1833,18 @@ tpl/u-boot-with-tpl.bin: tpl/u-boot-tpl.bin u-boot.bin FORCE
 SPL: spl/u-boot-spl.bin FORCE
 	$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
 
-#ifeq ($(CONFIG_ARCH_IMX8M)$(CONFIG_ARCH_IMX8), y)
-ifeq ($(CONFIG_SPL_LOAD_IMX_CONTAINER), y)
+ifeq ($(CONFIG_SPL_LOAD_IMX_CONTAINER),y)
+ifeq ($(CONFIG_ARCH_IMX8M)$(CONFIG_ARCH_IMX8),y)
 u-boot.cnt: u-boot.bin FORCE
 	$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
 
 flash.bin: spl/u-boot-spl.bin u-boot.cnt FORCE
 	$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
 else
+flash.bin: spl/u-boot-spl.bin FORCE
+	$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
+endif
+else
 ifeq ($(CONFIG_BINMAN),y)
 flash.bin: spl/u-boot-spl.bin $(INPUTS-y) FORCE
 	$(call if_changed,binman)
@@ -1794,7 +1853,6 @@ flash.bin: spl/u-boot-spl.bin u-boot.itb FORCE
 	$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
 endif
 endif
-#endif
 
 u-boot.uim: u-boot.bin FORCE
 	$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
@@ -1939,7 +1997,7 @@ quiet_cmd_u-boot-elf ?= LD      $@
 	$(if $(CONFIG_SYS_BIG_ENDIAN),-EB,-EL) \
 	-T u-boot-elf.lds --defsym=$(CONFIG_PLATFORM_ELFENTRY)=$(CONFIG_TEXT_BASE) \
 	-Ttext=$(CONFIG_TEXT_BASE)
-u-boot.elf: u-boot.bin u-boot-elf.lds
+u-boot.elf: u-boot.bin u-boot-elf.lds FORCE
 	$(Q)$(OBJCOPY) -I binary $(PLATFORM_ELFFLAGS) $< u-boot-elf.o
 	$(call if_changed,u-boot-elf)
 
@@ -1956,7 +2014,7 @@ PHONY += prepare0
 ifeq ($(CONFIG_SPL),y)
 spl/u-boot-spl-mtk.bin: spl/u-boot-spl
 
-u-boot-mtk.bin: u-boot-with-spl.bin
+u-boot-mtk.bin: u-boot-with-spl.bin FORCE
 	$(call if_changed,copy)
 else
 MKIMAGEFLAGS_u-boot-mtk.bin = -T mtk_image \
@@ -1989,9 +2047,9 @@ quiet_cmd_keep_syms_lto_cc = KSLCC   $@
       cmd_keep_syms_lto_cc = \
 	$(CC) $(filter-out $(LTO_CFLAGS),$(c_flags)) -c -o $@ $<
 
-$(u-boot-keep-syms-lto_c): $(u-boot-main)
+$(u-boot-keep-syms-lto_c): $(u-boot-main) FORCE
 	$(call if_changed,keep_syms_lto)
-$(u-boot-keep-syms-lto): $(u-boot-keep-syms-lto_c)
+$(u-boot-keep-syms-lto): $(u-boot-keep-syms-lto_c) FORCE
 	$(call if_changed,keep_syms_lto_cc)
 else
 u-boot-keep-syms-lto :=
@@ -2173,7 +2231,7 @@ PHONY += prepare archprepare prepare1 prepare3
 # and if so do:
 # 1) Check that make has not been executed in the kernel src $(srctree)
 prepare3: include/config/uboot.release
-ifneq ($(KBUILD_SRC),)
+ifdef building_out_of_srctree
 	@$(kecho) '  Using $(srctree) as source for U-Boot'
 	$(Q)if [ -f $(srctree)/.config -o -d $(srctree)/include/config ]; then \
 		echo >&2 "  $(srctree) is not clean, please run 'make mrproper'"; \
@@ -2267,10 +2325,10 @@ define filechk_timestamp.h
 endef
 
 define filechk_defaultenv.h
-	( { grep -v '^#' | grep -v '^$$' || true ; echo '' ; } | \
+	( ( { grep -v '^#' | grep -v '^$$' || true ; echo '' ; } | \
 	 tr '\n' '\0' | \
 	 sed -e 's/\\\x0\s*//g' | \
-	 xxd -i ; )
+	 xxd -i ; ) < $<; )
 endef
 
 define filechk_dt.h
@@ -2313,7 +2371,7 @@ dtbs_check: export CHECK_DTBS=1
 dtbs_check: dt_binding_check
 
 dtbs_install:
-	$(Q)$(MAKE) $(dtbinst)=$(dtstree)
+	$(Q)$(MAKE) -f $(srctree)/scripts/Makefile.dtbinst obj=$(dtstree)
 
 ifdef CONFIG_OF_EARLY_FLATTREE
 all: dtbs
@@ -2431,7 +2489,7 @@ checkarmreloc: u-boot
 		false; \
 	fi
 
-tools/version.h: include/version.h
+tools/version.h: include/version.h FORCE
 	$(Q)mkdir -p $(dir $@)
 	$(call if_changed,copy)
 
@@ -2463,7 +2521,7 @@ CHANGELOG:
 # make distclean Remove editor backup files, patch leftover files and the like
 
 # Directories & files removed with 'make clean'
-CLEAN_DIRS  += $(MODVERDIR) \
+CLEAN_FILES  += $(MODVERDIR) \
 	       $(foreach d, spl tpl vpl, $(patsubst %,$d/%, \
 			$(filter-out include, $(shell ls -1 $d 2>/dev/null))))
 
@@ -2482,7 +2540,7 @@ CLEAN_FILES += include/autoconf.mk* include/bmp_logo.h include/bmp_logo_data.h \
 	       imx9image* m33-oei-ddrfw* tifalcon.bin
 
 # Directories & files removed with 'make mrproper'
-MRPROPER_DIRS  += include/config include/generated spl tpl vpl \
+MRPROPER_FILES  += include/config include/generated spl tpl vpl \
 		  .tmp_objdiff doc/output include/asm
 
 # Remove include/asm symlink created by U-Boot before v2014.01
@@ -2492,37 +2550,14 @@ MRPROPER_FILES += .config .config.old include/autoconf.mk* include/config.h \
 
 # clean - Delete most, but leave enough to build external modules
 #
-clean: rm-dirs  := $(CLEAN_DIRS)
 clean: rm-files := $(CLEAN_FILES)
-clean-dirs	:= $(foreach f,$(u-boot-alldirs),$(if $(wildcard $(srctree)/$f/Makefile),$f))
-clean-dirs      := $(addprefix _clean_, $(clean-dirs))
 
-PHONY += $(clean-dirs) clean archclean
-$(clean-dirs):
-	$(Q)$(MAKE) $(clean)=$(patsubst _clean_%,%,$@)
+PHONY += archclean
 
-clean: $(clean-dirs)
-	$(call cmd,rmdirs)
-	$(call cmd,rmfiles)
-	@find $(if $(KBUILD_EXTMOD), $(KBUILD_EXTMOD), .) $(RCS_FIND_IGNORE) \
-		\( -name '*.[oas]' -o -name '*.ko' -o -name '.*.cmd' \
-		-o -name '*.ko.*' -o -name '*.su' -o -name '*.pyc' \
-		-o -name '*.dtb' -o -name '*.dtbo' \
-		-o -name '*.dtb.S' -o -name '*.dtbo.S' \
-		-o -name '.*.d' -o -name '.*.tmp' -o -name '*.mod.c' \
-		-o -name '*.lex.c' -o -name '*.tab.[ch]' \
-		-o -name '*.asn1.[ch]' \
-		-o -name '*.symtypes' -o -name 'modules.order' \
-		-o -name modules.builtin -o -name '.tmp_*.o.*' \
-		-o -name 'dsdt_generated.aml' -o -name 'dsdt_generated.asl.tmp' \
-		-o -name 'dsdt_generated.c' \
-		-o -name 'generated_defconfig' \
-		-o -name '*.efi' -o -name '*.gcno' -o -name '*.so' \) \
-		-type f -print | xargs rm -f
+clean: archclean
 
 # mrproper - Delete all generated files, including .config
 #
-mrproper: rm-dirs  := $(wildcard $(MRPROPER_DIRS))
 mrproper: rm-files := $(wildcard $(MRPROPER_FILES))
 mrproper-dirs      := $(addprefix _mrproper_,scripts)
 
@@ -2531,22 +2566,49 @@ $(mrproper-dirs):
 	$(Q)$(MAKE) $(clean)=$(patsubst _mrproper_%,%,$@)
 
 mrproper: clean $(mrproper-dirs)
-	$(call cmd,rmdirs)
 	$(call cmd,rmfiles)
-	@rm -f arch/*/include/asm/arch
 
 # distclean
 #
 PHONY += distclean
 
 distclean: mrproper
-	@find $(srctree) $(RCS_FIND_IGNORE) \
+	@find . $(RCS_FIND_IGNORE) \
 		\( -name '*.orig' -o -name '*.rej' -o -name '*~' \
-		-o -name '*.bak' -o -name '#*#' -o -name '.*.orig' \
-		-o -name '.*.rej' -o -name '*%' -o -name 'core' \
-		-o -name '*.pyc' \) \
+		-o -name '*.bak' -o -name '#*#' -o -name '*%' \
+		-o -name 'core' -o -name tags -o -name TAGS -o -name 'cscope*' \
+		-o -name GPATH -o -name GRTAGS -o -name GSYMS -o -name GTAGS \) \
 		-type f -print | xargs rm -f
-	@rm -f boards.cfg CHANGELOG .binman_stamp
+
+# Modified for U-Boot, the kernel figures this out through it's own variable
+clean-dirs	:= $(foreach f,$(u-boot-alldirs),$(if $(wildcard $(srctree)/$f/Makefile),$f))
+clean-dirs := $(addprefix _clean_, $(clean-dirs))
+PHONY += $(clean-dirs) clean
+$(clean-dirs):
+	$(Q)$(MAKE) $(clean)=$(patsubst _clean_%,%,$@)
+
+clean: $(clean-dirs)
+	$(call cmd,rmfiles)
+	@find $(or $(KBUILD_EXTMOD), .) $(RCS_FIND_IGNORE) \
+		\( -name '*.[aios]' -o -name '*.ko' -o -name '.*.cmd' \
+		-o -name '*.ko.*' -o -name '*.su' -o -name '*.pyc' \
+		-o -name '*.dtb' -o -name '*.dtbo' -o -name '*.dtb.S' -o -name '*.dt.yaml' \
+		-o -name '*.dwo' -o -name '*.lst' \
+		-o -name '*.su' -o -name '*.mod' -o -name '*.usyms' \
+		-o -name '.*.d' -o -name '.*.tmp' -o -name '*.mod.c' \
+		-o -name '*.lex.c' -o -name '*.tab.[ch]' \
+		-o -name '*.asn1.[ch]' \
+		-o -name '*.symtypes' -o -name 'modules.order' \
+		-o -name '.tmp_*' \
+		-o -name '*.c.[012]*.*' \
+		-o -name '*.ll' \
+		-o -name 'dsdt_generated.aml' -o -name 'dsdt_generated.asl.tmp' \
+		-o -name 'dsdt_generated.c' \
+		-o -name 'generated_defconfig' \
+		-o -name '*.gcno' \
+		-o -name '*.efi' -o -name '*.gcno' -o -name '*.so' \
+		-o -name '*.*.symversions' \) -type f -print | xargs rm -f
+
 
 # See doc/develop/python_cq.rst
 PHONY += pylint pylint_err
@@ -2697,8 +2759,7 @@ DOC_TARGETS := xmldocs latexdocs pdfdocs htmldocs epubdocs cleandocs \
 	       linkcheckdocs dochelp refcheckdocs texinfodocs infodocs
 PHONY += $(DOC_TARGETS)
 $(DOC_TARGETS): scripts_basic FORCE
-	$(Q)PYTHONPATH=$(srctree)/test/py/tests:$(srctree)/test/py \
-	$(MAKE) $(build)=doc $@
+	$(Q)$(MAKE) $(build)=doc $@
 
 PHONY += checkstack ubootrelease ubootversion
 
@@ -2779,16 +2840,13 @@ u-boot-initial-env: scripts_basic $(version_h) $(env_h) include/config.h FORCE
 PHONY += coccicheck
 
 coccicheck:
-	$(Q)$(CONFIG_SHELL) $(srctree)/scripts/$@
+	$(Q)$(BASH) $(srctree)/scripts/$@
 
 # FIXME Should go into a make.lib or something
 # ===========================================================================
 
-quiet_cmd_rmdirs = $(if $(wildcard $(rm-dirs)),CLEAN   $(wildcard $(rm-dirs)))
-      cmd_rmdirs = rm -rf $(rm-dirs)
-
 quiet_cmd_rmfiles = $(if $(wildcard $(rm-files)),CLEAN   $(wildcard $(rm-files)))
-      cmd_rmfiles = rm -f $(rm-files)
+      cmd_rmfiles = rm -rf $(rm-files)
 
 # Run depmod only if we have System.map and depmod is executable
 quiet_cmd_depmod = DEPMOD  $(KERNELRELEASE)

README

@@ -1662,7 +1662,7 @@ New uImage format (FIT)
 Flexible and powerful format based on Flattened Image Tree -- FIT (similar
 to Flattened Device Tree). It allows the use of images with multiple
 components (several kernels, ramdisks, etc.), with contents protected by
-SHA1, MD5 or CRC32. More details are found in the doc/uImage.FIT directory.
+SHA1, MD5 or CRC32. More details are found in the doc/usage/fit directory.
 
 
 Old uImage format

arch/Kconfig

@@ -159,6 +159,7 @@ config PPC
 config RISCV
 	bool "RISC-V architecture"
 	select CREATE_ARCH_SYMLINK
+	select HAVE_PRIVATE_LIBGCC if 64BIT
 	select HAVE_SETJMP
 	select HAVE_INITJMP
 	select SUPPORT_ACPI

arch/arm/Kconfig

@@ -670,13 +670,6 @@ config ARCH_MVEBU
 	select SPI
 	imply CMD_DM
 
-config ARCH_ORION5X
-	bool "Marvell Orion"
-	select CPU_ARM926EJS
-	select GPIO_EXTRA_HEADER
-	select SPL_SEPARATE_BSS if SPL
-	select TIMER
-
 config ARCH_BCM283X
 	bool "Broadcom BCM283X family"
 	select CPU
@@ -835,6 +828,8 @@ config ARCH_K3
 	select FIT_SIGNATURE if ARM64
 	select DMA_ADDR_T_64BIT
 	select LTO
+	select SPL_LOAD_FIT if SPL
+	select SPL_USE_TINY_PRINTF_POINTER_SUPPORT if SPL_USE_TINY_PRINTF && DFU && CPU_V7R
 	imply TI_SECURE_DEVICE
 	imply DM_RNG if ARM64
 	imply TEE if ARM64
@@ -864,7 +859,6 @@ config ARCH_MESON
 config ARCH_MEDIATEK
 	bool "MediaTek SoCs"
 	select DM
-	select GPIO_EXTRA_HEADER
 	select OF_CONTROL
 	select SPL_DM if SPL
 	select SPL_LIBCOMMON_SUPPORT if SPL
@@ -1143,6 +1137,7 @@ config ARCH_SNAPDRAGON
 	select SYSRESET
 	select SYSRESET_PSCI
 	select ANDROID_BOOT_IMAGE_IGNORE_BLOB_ADDR
+	select MMU_PGPROT
 	imply OF_UPSTREAM
 	imply CMD_DM
 	imply DM_USB_GADGET
@@ -2345,8 +2340,6 @@ source "arch/arm/mach-omap2/Kconfig"
 
 source "arch/arm/cpu/armv8/fsl-layerscape/Kconfig"
 
-source "arch/arm/mach-orion5x/Kconfig"
-
 source "arch/arm/mach-owl/Kconfig"
 
 source "arch/arm/mach-renesas/Kconfig"
@@ -2422,23 +2415,23 @@ source "board/cavium/thunderx/Kconfig"
 source "board/eets/pdu001/Kconfig"
 source "board/emulation/qemu-arm/Kconfig"
 source "board/emulation/qemu-sbsa/Kconfig"
-source "board/freescale/ls2080aqds/Kconfig"
-source "board/freescale/ls2080ardb/Kconfig"
-source "board/freescale/ls1088a/Kconfig"
-source "board/freescale/ls1028a/Kconfig"
-source "board/freescale/ls1021aqds/Kconfig"
-source "board/freescale/ls1043aqds/Kconfig"
-source "board/freescale/ls1021atwr/Kconfig"
-source "board/freescale/ls1021atsn/Kconfig"
-source "board/freescale/ls1021aiot/Kconfig"
-source "board/freescale/ls1046aqds/Kconfig"
-source "board/freescale/ls1043ardb/Kconfig"
-source "board/freescale/ls1046ardb/Kconfig"
-source "board/freescale/ls1046afrwy/Kconfig"
-source "board/freescale/ls1012aqds/Kconfig"
-source "board/freescale/ls1012ardb/Kconfig"
-source "board/freescale/ls1012afrdm/Kconfig"
-source "board/freescale/lx2160a/Kconfig"
+source "board/nxp/ls2080aqds/Kconfig"
+source "board/nxp/ls2080ardb/Kconfig"
+source "board/nxp/ls1088a/Kconfig"
+source "board/nxp/ls1028a/Kconfig"
+source "board/nxp/ls1021aqds/Kconfig"
+source "board/nxp/ls1043aqds/Kconfig"
+source "board/nxp/ls1021atwr/Kconfig"
+source "board/nxp/ls1021atsn/Kconfig"
+source "board/nxp/ls1021aiot/Kconfig"
+source "board/nxp/ls1046aqds/Kconfig"
+source "board/nxp/ls1043ardb/Kconfig"
+source "board/nxp/ls1046ardb/Kconfig"
+source "board/nxp/ls1046afrwy/Kconfig"
+source "board/nxp/ls1012aqds/Kconfig"
+source "board/nxp/ls1012ardb/Kconfig"
+source "board/nxp/ls1012afrdm/Kconfig"
+source "board/nxp/lx2160a/Kconfig"
 source "board/grinn/chiliboard/Kconfig"
 source "board/hisilicon/hikey/Kconfig"
 source "board/hisilicon/hikey960/Kconfig"

arch/arm/Makefile

@@ -75,7 +75,6 @@ machine-$(CONFIG_ARCH_MVEBU)		+= mvebu
 machine-$(CONFIG_ARCH_NEXELL)		+= nexell
 machine-$(CONFIG_ARCH_NPCM)             += npcm
 machine-$(CONFIG_ARCH_OMAP2PLUS)	+= omap2
-machine-$(CONFIG_ARCH_ORION5X)		+= orion5x
 machine-$(CONFIG_ARCH_OWL)		+= owl
 machine-$(CONFIG_ARCH_RENESAS)		+= renesas
 machine-$(CONFIG_ARCH_ROCKCHIP)		+= rockchip

arch/arm/cpu/arm1136/u-boot-spl.lds

@@ -30,8 +30,10 @@ SECTIONS
 	.rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
 
 	. = ALIGN(4);
-	.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
-	. = ALIGN(4);
+	.data : {
+		*(SORT_BY_ALIGNMENT(.data*))
+		. = ALIGN(8);
+	} >.sram
 	__image_copy_end = .;
 	_end = .;
 
@@ -44,3 +46,5 @@ SECTIONS
 		__bss_end = .;
 	} >.sdram
 }
+
+ASSERT(_end % 8 == 0, "_end must be 8-byte aligned for device tree");

arch/arm/cpu/arm926ejs/mxs/Makefile

@@ -53,23 +53,23 @@ quiet_cmd_mkcst_mxs = MXSCST  $@
 cmd_mkcst_mxs = cst -o $@ < $^						\
 	$(if $(KBUILD_VERBOSE:1=), >/dev/null)
 
-spl/u-boot-spl.ivt: spl/u-boot-spl.bin
+spl/u-boot-spl.ivt: spl/u-boot-spl.bin FORCE
 	$(call if_changed,mkalign_mxs)
 	$(call if_changed,mkivt_mxs,$(CONFIG_SPL_TEXT_BASE),\
 		0x00008000,0x00008040)
 
-u-boot.ivt: u-boot.bin
+u-boot.ivt: u-boot.bin FORCE
 	$(call if_changed,mkalign_mxs)
 	$(call if_changed,mkivt_mxs,$(CONFIG_TEXT_BASE),\
 		0x40001000,0x40001040)
 
-spl/u-boot-spl.csf: spl/u-boot-spl.ivt spl/u-boot-spl.bin board/$(VENDOR)/$(BOARD)/sign/u-boot-spl.csf
+spl/u-boot-spl.csf: spl/u-boot-spl.ivt spl/u-boot-spl.bin board/$(VENDOR)/$(BOARD)/sign/u-boot-spl.csf FORCE
 	$(call if_changed,mkcsfreq_mxs,$(CONFIG_SPL_TEXT_BASE),0x8000)
 
-u-boot.csf: u-boot.ivt u-boot.bin board/$(VENDOR)/$(BOARD)/sign/u-boot.csf
+u-boot.csf: u-boot.ivt u-boot.bin board/$(VENDOR)/$(BOARD)/sign/u-boot.csf FORCE
 	$(call if_changed,mkcsfreq_mxs,$(CONFIG_TEXT_BASE),0x40001000)
 
-%.sig: %.csf
+%.sig: %.csf FORCE
 	$(call if_changed,mkcst_mxs)
 
 MKIMAGEFLAGS_u-boot.sb = -n $< -T mxsimage

arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds

@@ -33,19 +33,11 @@ SECTIONS
 		*(.data*)
 	}
 
-	. = ALIGN(4);
-
-	.rel.dyn : {
-		__rel_dyn_start = .;
-		*(.rel*)
-		__rel_dyn_end = .;
-	}
-
 	.bss : {
 		. = ALIGN(4);
 		__bss_start = .;
 		*(.bss*)
-		. = ALIGN(4);
+		. = ALIGN(8);
 		__bss_end = .;
 	}
 
@@ -62,3 +54,6 @@ SECTIONS
 	.gnu : { *(.gnu*) }
 	.ARM.exidx : { *(.ARM.exidx*) }
 }
+
+ASSERT(_image_binary_end % 8 == 0, \
+       "_image_binary_end must be 8-byte aligned for device tree");

arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds

@@ -31,9 +31,9 @@ SECTIONS
 	. = ALIGN(4);
 	__u_boot_list : {
 		KEEP(*(SORT(__u_boot_list*)));
+		. = ALIGN(8);
 	} > .sram
 
-	. = ALIGN(4);
 	__image_copy_end = .;
 	_end = .;
 	_image_binary_end = .;
@@ -47,3 +47,6 @@ SECTIONS
 		__bss_end = .;
 	} > .sdram
 }
+
+ASSERT(_image_binary_end % 8 == 0, \
+       "_image_binary_end must be 8-byte aligned for device tree");

arch/arm/cpu/armv7/sunxi/u-boot-spl.lds

@@ -40,9 +40,9 @@ SECTIONS
 	. = ALIGN(4);
 	__u_boot_list : {
 		KEEP(*(SORT(__u_boot_list*)));
+		. = ALIGN(8);
 	} > .sram
 
-	. = ALIGN(4);
 	__image_copy_end = .;
 	_end = .;
 	_image_binary_end = .;
@@ -56,3 +56,6 @@ SECTIONS
 		__bss_end = .;
 	} > .sdram
 }
+
+ASSERT(_image_binary_end % 8 == 0, \
+       "_image_binary_end must be 8-byte aligned for device tree");

arch/arm/cpu/armv7/vf610/Kconfig

@@ -30,7 +30,7 @@ endchoice
 config SYS_SOC
 	default "vf610"
 
-source "board/freescale/vf610twr/Kconfig"
+source "board/nxp/vf610twr/Kconfig"
 source "board/phytec/pcm052/Kconfig"
 source "board/toradex/colibri_vf/Kconfig"
 

arch/arm/cpu/armv7/vf610/Makefile

@@ -7,5 +7,5 @@ obj-y	+= timer.o
 
 MKIMAGEFLAGS_u-boot.vyb = -T vybridimage
 
-u-boot.vyb: u-boot.imx
+u-boot.vyb: u-boot.imx FORCE
 	$(call if_changed,mkimage)

arch/arm/cpu/armv8/cache_v8.c

@@ -878,15 +878,16 @@ void flush_dcache_range(unsigned long start, unsigned long stop)
 void dcache_enable(void)
 {
 	/* The data cache is not active unless the mmu is enabled */
-	if (!mmu_status())
+	if (!mmu_status()) {
+		__asm_invalidate_tlb_all();
 		mmu_setup();
+	}
 
 	/* Set up page tables only once (it is done also by mmu_setup()) */
 	if (!gd->arch.tlb_fillptr)
 		setup_all_pgtables();
 
 	invalidate_dcache_all();
-	__asm_invalidate_tlb_all();
 	set_sctlr(get_sctlr() | CR_C);
 }
 

arch/arm/cpu/armv8/fsl-layerscape/fdt.c

@@ -12,6 +12,7 @@
 #include <asm/cache.h>
 #include <linux/libfdt.h>
 #include <fdt_support.h>
+#include <malloc.h>
 #include <phy.h>
 #ifdef CONFIG_FSL_LSCH3
 #include <asm/arch/fdt.h>
@@ -48,6 +49,61 @@ int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc)
 }
 
 #ifdef CONFIG_MP
+static void fdt_fixup_thermal_cooling_device(void *blob, int cpu_off)
+{
+	int cnt, idx, len;
+	int map, maps;
+	int offline, phandle;
+	int ret;
+	int zone, zones;
+	u32 *tbl;
+	struct fdtdec_phandle_args dev;
+
+	zones = fdt_subnode_offset(blob, 0, "thermal-zones");
+	if (zones < 0)
+		return;
+
+	offline = fdt_get_phandle(blob, cpu_off);
+	fdt_for_each_subnode(zone, blob, zones) {
+		maps = fdt_subnode_offset(blob, zone, "cooling-maps");
+		if (maps < 0)
+			continue;
+		fdt_for_each_subnode(map, blob, maps) {
+			if (!fdt_getprop(blob, map, "cooling-device", &len))
+				continue;
+			cnt = fdtdec_parse_phandle_with_args(blob, map,
+							     "cooling-device",
+							     "#cooling-cells",
+							     0, -1, NULL);
+			if (cnt <= 0)
+				continue;
+			tbl = (u32 *)malloc(len);
+			if (!tbl)
+				return;
+			idx = 0;
+			for (int i = 0; i < cnt; i++) {
+				ret = fdtdec_parse_phandle_with_args(blob, map,
+								     "cooling-device",
+								     "#cooling-cells",
+								     0, i,
+								     &dev);
+				if (ret < 0)
+					goto skip_update;
+				phandle = fdt_get_phandle(blob, dev.node);
+				if (phandle == offline)
+					continue;
+				tbl[idx++] = cpu_to_fdt32(phandle);
+				for (int j = 0; j < dev.args_count; j++)
+					tbl[idx++] = cpu_to_fdt32(dev.args[j]);
+			}
+			fdt_setprop(blob, map, "cooling-device", tbl,
+				    (idx*sizeof(*tbl)));
+skip_update:
+			free(tbl);
+		}
+	}
+}
+
 void ft_fixup_cpu(void *blob)
 {
 	int off;
@@ -73,6 +129,7 @@ void ft_fixup_cpu(void *blob)
 		if (reg) {
 			core_id = fdt_read_number(reg, addr_cells);
 			if (!test_bit(id_to_core(core_id), &mask)) {
+				fdt_fixup_thermal_cooling_device(blob, off);
 				fdt_del_node(blob, off);
 				off = off_prev;
 			}

arch/arm/cpu/armv8/u-boot-spl.lds

@@ -49,12 +49,20 @@ SECTIONS
 	} >.sram
 #endif
 
+	.binman_sym_table : {
+		. = ALIGN(8);
+		__binman_sym_start = .;
+		KEEP(*(SORT(.binman_sym*)));
+		__binman_sym_end = .;
+		. = ALIGN(8);
+	} > .sram
+
 	__u_boot_list : {
 		. = ALIGN(8);
 		KEEP(*(SORT(__u_boot_list*)));
+		. = ALIGN(8);
 	} >.sram
 
-	. = ALIGN(8);
 	__image_copy_end = .;
 	_end = .;
 	_image_binary_end = .;
@@ -67,7 +75,7 @@ SECTIONS
 		__bss_end = .;
 	} >.sdram
 #else
-	.bss (NOLOAD) : {
+	.bss _image_binary_end (OVERLAY) : {
 		__bss_start = .;
 		*(.bss*)
 		 . = ALIGN(8);
@@ -89,5 +97,8 @@ SECTIONS
 #endif
 }
 
+ASSERT(_image_binary_end % 8 == 0, \
+       "_image_binary_end must be 8-byte aligned for device tree");
+
 ASSERT(ADDR(.bss) % 8 == 0, \
        ".bss must be 8-byte aligned");

arch/arm/cpu/armv8/u-boot.lds

@@ -146,6 +146,7 @@ SECTIONS
 		__rel_dyn_start = .;
 		*(.rela*)
 		__rel_dyn_end = .;
+		. = ALIGN(8);
 	}
 
 	_end = .;
@@ -175,3 +176,5 @@ SECTIONS
 #include "linux-kernel-image-header-vars.h"
 #endif
 }
+
+ASSERT(_end % 8 == 0, "_end must be 8-byte aligned for device tree");

arch/arm/cpu/u-boot-spl.lds

@@ -31,11 +31,6 @@ SECTIONS
 		*(.data*)
 	}
 
-	. = ALIGN(4);
-	__u_boot_list : {
-		KEEP(*(SORT(__u_boot_list*)));
-	}
-
 	. = ALIGN(4);
 	.binman_sym_table : {
 		__binman_sym_start = .;
@@ -44,20 +39,16 @@ SECTIONS
 	}
 
 	. = ALIGN(4);
-
-	__image_copy_end = .;
-
-	.rel.dyn : {
-		__rel_dyn_start = .;
-		*(.rel*)
-		__rel_dyn_end = .;
+	__u_boot_list : {
+		KEEP(*(SORT(__u_boot_list*)));
+		. = ALIGN(8);
 	}
 
-	. = ALIGN(8);
+	__image_copy_end = .;
 	_image_binary_end = .;
 	_end = .;
 
-	.bss __rel_dyn_start (OVERLAY) : {
+	.bss _image_binary_end (OVERLAY) : {
 		__bss_start = .;
 		*(.bss*)
 		 . = ALIGN(8);
@@ -80,6 +71,9 @@ ASSERT(__image_copy_end - __image_copy_start <= (IMAGE_MAX_SIZE), \
 	"SPL image too big");
 #endif
 
+ASSERT(_image_binary_end % 8 == 0, \
+       "_image_binary_end must be 8-byte aligned for device tree");
+
 #if defined(CONFIG_SPL_BSS_MAX_SIZE)
 ASSERT(__bss_end - __bss_start <= (CONFIG_SPL_BSS_MAX_SIZE), \
 	"SPL image BSS too big");

arch/arm/cpu/u-boot.lds

@@ -164,6 +164,7 @@ SECTIONS
 		__rel_dyn_start = .;
 		*(.rel*)
 		__rel_dyn_end = .;
+		. = ALIGN(8);
 	}
 
 	_end = .;
@@ -192,3 +193,6 @@ SECTIONS
 	/DISCARD/ : { *(.ARM.exidx*) }
 	/DISCARD/ : { *(.gnu.linkonce.armexidx.*) }
 }
+
+ASSERT(_image_binary_end % 8 == 0, \
+       "_image_binary_end must be 8-byte aligned for device tree");

arch/arm/dts/Makefile

@@ -451,6 +451,7 @@ dtb-$(CONFIG_TARGET_THUNDERX_88XX) += thunderx-88xx.dtb
 
 dtb-$(CONFIG_ARCH_SOCFPGA) +=				\
 	socfpga_agilex5_socdk.dtb			\
+	socfpga_agilex5_socdk_emmc.dtb		\
 	socfpga_arria5_secu1.dtb			\
 	socfpga_arria5_socdk.dtb			\
 	socfpga_arria10_chameleonv3_270_2.dtb		\
@@ -880,9 +881,6 @@ dtb-$(CONFIG_ARCH_IMX8) += \
 	fsl-imx8qxp-mek.dtb \
 	imx8-capricorn-cxg3.dtb \
 
-dtb-$(CONFIG_ARCH_IMX8ULP) += \
-	imx8ulp-evk.dtb
-
 dtb-$(CONFIG_ARCH_IMX8M) += \
 	imx8mm-data-modul-edm-sbc.dtb \
 	imx8mm-icore-mx8mm-ctouch2.dtb \
@@ -890,7 +888,6 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
 	imx8mm-mx8menlo.dtb \
 	imx8mm-phg.dtb \
 	imx8mq-cm.dtb \
-	imx8mn-var-som-symphony.dtb \
 	imx8mq-mnt-reform2.dtb \
 	imx8mq-phanbell.dtb \
 	imx8mp-data-modul-edm-sbc.dtb \
@@ -1091,7 +1088,9 @@ dtb-$(CONFIG_SOC_K3_J7200) += k3-j7200-r5-common-proc-board.dtb
 dtb-$(CONFIG_SOC_K3_J721S2) += k3-am68-sk-r5-base-board.dtb\
 			       k3-j721s2-r5-common-proc-board.dtb
 
-dtb-$(CONFIG_SOC_K3_J784S4) += k3-am69-r5-sk.dtb \
+dtb-$(CONFIG_SOC_K3_J784S4) += k3-am69-aquila-dev.dtb \
+			       k3-am69-r5-aquila-dev.dtb \
+			       k3-am69-r5-sk.dtb \
 			       k3-j784s4-r5-evm.dtb
 
 dtb-$(CONFIG_SOC_K3_J722S) += k3-j722s-r5-evm.dtb \

arch/arm/dts/an7581-u-boot.dtsi

@@ -57,6 +57,11 @@
 		switch: switch@1fb58000 {
 			compatible = "airoha,en7581-switch";
 			reg = <0 0x1fb58000 0 0x8000>;
+
+			mdio: mdio {
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
 		};
 
 		snfi: spi@1fa10000 {

arch/arm/dts/at91-sam9x60_curiosity-u-boot.dtsi

@@ -21,8 +21,11 @@
 		bootph-all;
 	};
 
-	config {
-		u-boot,boot-led = "blue";
+	options {
+		u-boot {
+			compatible = "u-boot,config";
+			boot-led = <&led_blue>;
+		};
 	};
 
 	leds {
@@ -34,7 +37,7 @@
 			default-state = "off";
 		};
 
-		led-blue {
+		led_blue: led-blue {
 			default-state = "off";
 		};
 	};

arch/arm/dts/at91sam9g45-corvus.dts

@@ -10,6 +10,7 @@
  *                2011 Nicolas Ferre <nicolas.ferre@atmel.com>
  */
 /dts-v1/;
+#include <dt-bindings/leds/common.h>
 #include "at91sam9g45.dtsi"
 
 / {
@@ -106,4 +107,14 @@
 			status = "okay";
 		};
 	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		red_led: led-0 {
+			gpios = <&pioD 31 GPIO_ACTIVE_HIGH>;
+			color = <LED_COLOR_ID_RED>;
+			default-state = "on";
+		};
+	};
 };

arch/arm/dts/en7523-u-boot.dtsi

@@ -42,6 +42,11 @@
 	switch: switch@1fb58000 {
 		compatible = "airoha,en7523-switch";
 		reg = <0x1fb58000 0x8000>;
+
+		mdio: mdio {
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
 	};
 
 	snfi: spi@1fa10000 {

arch/arm/dts/exynos7870-a2corelte-u-boot.dtsi

@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2026 Kaustabh Chakraborty <kauschluss@disroot.org>
+ */
+
+/ {
+	/* These properties are required by S-BOOT. */
+	model_info-chip = <7870>;
+	model_info-hw_rev = <0>;
+	model_info-hw_rev_end = <255>;
+
+	chosen {
+		#address-cells = <2>;
+		#size-cells = <1>;
+		ranges;
+
+		framebuffer@67000000 {
+			compatible = "simple-framebuffer";
+			reg = <0x0 0x67000000 (540 * 960 * 4)>;
+			width = <540>;
+			height = <960>;
+			stride = <(540 * 4)>;
+			format = "a8r8g8b8";
+		};
+	};
+};

arch/arm/dts/exynos7870-j6lte-u-boot.dtsi

@@ -0,0 +1,46 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) Kaustabh Chakraborty <kauschluss@disroot.org>
+ */
+
+/ {
+	/* These properties are required by S-BOOT. */
+	model_info-chip = <7870>;
+	model_info-hw_rev = <0>;
+	model_info-hw_rev_end = <255>;
+
+	chosen {
+		#address-cells = <2>;
+		#size-cells = <1>;
+		ranges;
+
+		framebuffer@67000000 {
+			compatible = "simple-framebuffer";
+			reg = <0x0 0x67000000 (720 * 1480 * 4)>;
+			width = <720>;
+			height = <1480>;
+			stride = <(720 * 4)>;
+			format = "a8r8g8b8";
+		};
+	};
+
+	/*
+	 * S-BOOT will populate the memory nodes stated below. Existing
+	 * values redefine the safe memory requirements as stated in upstream
+	 * device tree, in separate nodes for each bank.
+	 */
+	memory@40000000 {
+		device_type = "memory";
+		reg = <0x0 0x40000000 0x3d800000>;
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x40000000>;
+	};
+
+	memory@100000000 {
+		device_type = "memory";
+		reg = <0x1 0x00000000 0x00000000>;
+	};
+};

arch/arm/dts/exynos7870-on7xelte-u-boot.dtsi

@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2026 Kaustabh Chakraborty <kauschluss@disroot.org>
+ */
+
+/ {
+	/* These properties are required by S-BOOT. */
+	model_info-chip = <7870>;
+	model_info-hw_rev = <0>;
+	model_info-hw_rev_end = <255>;
+
+	chosen {
+		#address-cells = <2>;
+		#size-cells = <1>;
+		ranges;
+
+		framebuffer@67000000 {
+			compatible = "simple-framebuffer";
+			reg = <0x0 0x67000000 (1080 * 1920 * 4)>;
+			width = <1080>;
+			height = <1920>;
+			stride = <(1080 * 4)>;
+			format = "a8r8g8b8";
+		};
+	};
+
+	/*
+	 * S-BOOT will populate the memory nodes stated below. Existing
+	 * values redefine the safe memory requirements as stated in upstream
+	 * device tree, in separate nodes for each bank.
+	 */
+	memory@40000000 {
+		device_type = "memory";
+		reg = <0x0 0x40000000 0x3e400000>;
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x80000000>;
+	};
+};

arch/arm/dts/imx8mm-phyboard-polis-rdk-u-boot.dtsi

@@ -12,6 +12,22 @@
 		wdt = <&wdog1>;
 		bootph-pre-ram;
 	};
+
+	bootstd {
+		bootph-verify;
+		compatible = "u-boot,boot-std";
+
+		filename-prefixes = "/", "/boot/";
+		bootdev-order = "mmc2", "mmc1", "ethernet";
+
+		rauc {
+			compatible = "u-boot,distro-rauc";
+		};
+
+		script {
+			compatible = "u-boot,script";
+		};
+	};
 };
 
 &pinctrl_i2c1 {

arch/arm/dts/imx8mm-phygate-tauri-l-u-boot.dtsi

@@ -11,6 +11,22 @@
 		wdt = <&wdog1>;
 		bootph-pre-ram;
 	};
+
+	bootstd {
+		bootph-verify;
+		compatible = "u-boot,boot-std";
+
+		filename-prefixes = "/", "/boot/";
+		bootdev-order = "mmc2", "mmc1", "ethernet";
+
+		rauc {
+			compatible = "u-boot,distro-rauc";
+		};
+
+		script {
+			compatible = "u-boot,script";
+		};
+	};
 };
 
 &pinctrl_uart3 {

arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi

@@ -3,52 +3,7 @@
  * Copyright 2021 Collabora Ltd.
  */
 
-#include "imx8mn-u-boot.dtsi"
-
-&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} {
-	bootph-pre-ram;
-};
-
-&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} {
-	bootph-pre-ram;
-};
-
-&eeprom_som {
-	#address-cells = <1>;
-	#size-cells = <1>;
-	eth_mac_address: eth-mac-address@19 {
-		reg = <0x19 0x06>;
-	};
-};
-
-&fec1 {
-	nvmem-cells = <&eth_mac_address>;
-	nvmem-cell-names = "mac-address";
-};
-
-&gpio1 {
-	bootph-pre-ram;
-};
-
-&gpio2 {
-	bootph-pre-ram;
-};
-
-&gpio4 {
-	bootph-pre-ram;
-};
-
-&i2c1 {
-	bootph-all;
-};
-
-&pinctrl_i2c1 {
-	bootph-all;
-};
-
-&pinctrl_pmic {
-	bootph-pre-ram;
-};
+#include "imx8mn-var-som-u-boot.dtsi"
 
 &pinctrl_reg_usdhc2_vmmc {
 	bootph-pre-ram;
@@ -62,14 +17,6 @@
 	bootph-pre-ram;
 };
 
-&pinctrl_usdhc3 {
-	bootph-pre-ram;
-};
-
-&pinctrl_wdog {
-	bootph-pre-ram;
-};
-
 &uart4 {
 	bootph-pre-ram;
 };
@@ -77,11 +24,3 @@
 &usdhc2 {
 	bootph-pre-ram;
 };
-
-&usdhc3 {
-	bootph-pre-ram;
-};
-
-&eeprom_som {
-	bootph-all;
-};

arch/arm/dts/imx8mn-var-som-symphony.dts

@@ -1,236 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2019-2020 Variscite Ltd.
- * Copyright (C) 2020 Krzysztof Kozlowski <krzk@kernel.org>
- */
-
-/dts-v1/;
-
-#include "imx8mn-var-som.dtsi"
-
-/ {
-	model = "Variscite VAR-SOM-MX8MN Symphony evaluation board";
-	compatible = "variscite,var-som-mx8mn-symphony", "variscite,var-som-mx8mn", "fsl,imx8mn";
-
-	reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
-		compatible = "regulator-fixed";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
-		regulator-name = "VSD_3V3";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		gpio = <&gpio4 22 GPIO_ACTIVE_HIGH>;
-		enable-active-high;
-	};
-
-	gpio-keys {
-		compatible = "gpio-keys";
-
-		key-back {
-			label = "Back";
-			gpios = <&pca9534 1 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_BACK>;
-		};
-
-		key-home {
-			label = "Home";
-			gpios = <&pca9534 2 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_HOME>;
-		};
-
-		key-menu {
-			label = "Menu";
-			gpios = <&pca9534 3 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_MENU>;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		led {
-			label = "Heartbeat";
-			gpios = <&pca9534 0 GPIO_ACTIVE_LOW>;
-			linux,default-trigger = "heartbeat";
-		};
-	};
-};
-
-&i2c2 {
-	clock-frequency = <400000>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_i2c2>;
-	status = "okay";
-
-	pca9534: gpio@20 {
-		compatible = "nxp,pca9534";
-		reg = <0x20>;
-		gpio-controller;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_pca9534>;
-		interrupt-parent = <&gpio1>;
-		interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
-		#gpio-cells = <2>;
-		wakeup-source;
-
-		/* USB 3.0 OTG (usbotg1) / SATA port switch, set to USB 3.0 */
-		usb3-sata-sel-hog {
-			gpio-hog;
-			gpios = <4 GPIO_ACTIVE_HIGH>;
-			output-low;
-			line-name = "usb3_sata_sel";
-		};
-
-		som-vselect-hog {
-			gpio-hog;
-			gpios = <6 GPIO_ACTIVE_HIGH>;
-			output-low;
-			line-name = "som_vselect";
-		};
-
-		enet-sel-hog {
-			gpio-hog;
-			gpios = <7 GPIO_ACTIVE_HIGH>;
-			output-low;
-			line-name = "enet_sel";
-		};
-	};
-
-	extcon_usbotg1: typec@3d {
-		compatible = "nxp,ptn5150";
-		reg = <0x3d>;
-		interrupt-parent = <&gpio1>;
-		interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_ptn5150>;
-		status = "okay";
-	};
-};
-
-&i2c3 {
-	/* Capacitive touch controller */
-	ft5x06_ts: touchscreen@38 {
-		compatible = "edt,edt-ft5406";
-		reg = <0x38>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_captouch>;
-		interrupt-parent = <&gpio5>;
-		interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
-
-		touchscreen-size-x = <800>;
-		touchscreen-size-y = <480>;
-		touchscreen-inverted-x;
-		touchscreen-inverted-y;
-	};
-
-	rtc@68 {
-		compatible = "dallas,ds1337";
-		reg = <0x68>;
-	};
-};
-
-/* Header */
-&uart1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_uart1>;
-	status = "okay";
-};
-
-/* Header */
-&uart3 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_uart3>;
-	status = "okay";
-};
-
-&usbotg1 {
-	disable-over-current;
-	extcon = <&extcon_usbotg1>, <&extcon_usbotg1>;
-};
-
-&pinctrl_fec1 {
-	fsl,pins = <
-		MX8MN_IOMUXC_ENET_MDC_ENET1_MDC			0x3
-		MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
-		MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
-		MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
-		MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
-		MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
-		MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
-		MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
-		MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
-		MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
-		MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
-		MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
-		MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
-		MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
-		/* Remove the MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 as not used */
-	>;
-};
-
-&pinctrl_fec1_sleep {
-	fsl,pins = <
-		MX8MN_IOMUXC_ENET_MDC_GPIO1_IO16		0x120
-		MX8MN_IOMUXC_ENET_MDIO_GPIO1_IO17		0x120
-		MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18		0x120
-		MX8MN_IOMUXC_ENET_TD2_GPIO1_IO19		0x120
-		MX8MN_IOMUXC_ENET_TD1_GPIO1_IO20		0x120
-		MX8MN_IOMUXC_ENET_TD0_GPIO1_IO21		0x120
-		MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29		0x120
-		MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28		0x120
-		MX8MN_IOMUXC_ENET_RD1_GPIO1_IO27		0x120
-		MX8MN_IOMUXC_ENET_RD0_GPIO1_IO26		0x120
-		MX8MN_IOMUXC_ENET_TXC_GPIO1_IO23		0x120
-		MX8MN_IOMUXC_ENET_RXC_GPIO1_IO25		0x120
-		MX8MN_IOMUXC_ENET_RX_CTL_GPIO1_IO24		0x120
-		MX8MN_IOMUXC_ENET_TX_CTL_GPIO1_IO22		0x120
-		/* Remove the MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 as not used */
-	>;
-};
-
-&iomuxc {
-	pinctrl_captouch: captouchgrp {
-		fsl,pins = <
-			MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4		0x16
-		>;
-	};
-
-	pinctrl_i2c2: i2c2grp {
-		fsl,pins = <
-			MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL		0x400001c3
-			MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA		0x400001c3
-		>;
-	};
-
-	pinctrl_pca9534: pca9534grp {
-		fsl,pins = <
-			MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7	0x16
-		>;
-	};
-
-	pinctrl_ptn5150: ptn5150grp {
-		fsl,pins = <
-			MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11	0x16
-		>;
-	};
-
-	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
-		fsl,pins = <
-			MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22	0x41
-		>;
-	};
-
-	pinctrl_uart1: uart1grp {
-		fsl,pins = <
-			MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX	0x140
-			MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX	0x140
-		>;
-	};
-
-	pinctrl_uart3: uart3grp {
-		fsl,pins = <
-			MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX	0x140
-			MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX	0x140
-		>;
-	};
-};

arch/arm/dts/imx8mn-var-som-u-boot.dtsi

@@ -0,0 +1,70 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2025 Dimonoff
+ */
+
+#include "imx8mn-u-boot.dtsi"
+
+/ {
+	aliases {
+		eeprom-som = &eeprom_som;
+	};
+};
+
+&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} {
+	bootph-pre-ram;
+};
+
+&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} {
+	bootph-pre-ram;
+};
+
+&eeprom_som {
+	bootph-all;
+	#address-cells = <1>;
+	#size-cells = <1>;
+	eth_mac_address: eth-mac-address@19 {
+		reg = <0x19 0x06>;
+	};
+};
+
+&fec1 {
+	nvmem-cells = <&eth_mac_address>;
+	nvmem-cell-names = "mac-address";
+};
+
+&gpio1 {
+	bootph-pre-ram;
+};
+
+&gpio2 {
+	bootph-pre-ram;
+};
+
+&gpio4 {
+	bootph-pre-ram;
+};
+
+&i2c1 {
+	bootph-all;
+};
+
+&usdhc3 {
+	bootph-pre-ram;
+};
+
+&pinctrl_i2c1 {
+	bootph-all;
+};
+
+&pinctrl_wdog {
+	bootph-pre-ram;
+};
+
+&pinctrl_pmic {
+	bootph-pre-ram;
+};
+
+&pinctrl_usdhc3 {
+	bootph-pre-ram;
+};

arch/arm/dts/imx8mn-var-som.dtsi

@@ -1,564 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2019 NXP
- * Copyright 2019-2020 Variscite Ltd.
- * Copyright (C) 2020 Krzysztof Kozlowski <krzk@kernel.org>
- */
-
-#include "imx8mn.dtsi"
-
-/ {
-	model = "Variscite VAR-SOM-MX8MN module";
-	compatible = "variscite,var-som-mx8mn", "fsl,imx8mn";
-
-	aliases {
-		eeprom-som = &eeprom_som;
-	};
-
-	chosen {
-		stdout-path = &uart4;
-	};
-
-	memory@40000000 {
-		device_type = "memory";
-		reg = <0x0 0x40000000 0 0x40000000>;
-	};
-
-	reg_eth_phy: regulator-eth-phy {
-		compatible = "regulator-fixed";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_reg_eth_phy>;
-		regulator-name = "eth_phy_pwr";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		gpio = <&gpio2 9 GPIO_ACTIVE_HIGH>;
-		enable-active-high;
-	};
-};
-
-&A53_0 {
-	cpu-supply = <&buck2_reg>;
-};
-
-&A53_1 {
-	cpu-supply = <&buck2_reg>;
-};
-
-&A53_2 {
-	cpu-supply = <&buck2_reg>;
-};
-
-&A53_3 {
-	cpu-supply = <&buck2_reg>;
-};
-
-&ecspi1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_ecspi1>;
-	cs-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>,
-		   <&gpio1  0 GPIO_ACTIVE_LOW>;
-	/delete-property/ dmas;
-	/delete-property/ dma-names;
-	status = "okay";
-
-	/* Resistive touch controller */
-	touchscreen@0 {
-		reg = <0>;
-		compatible = "ti,ads7846";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_restouch>;
-		interrupt-parent = <&gpio1>;
-		interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
-
-		spi-max-frequency = <1500000>;
-		pendown-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
-
-		ti,x-min = /bits/ 16 <125>;
-		touchscreen-size-x = <4008>;
-		ti,y-min = /bits/ 16 <282>;
-		touchscreen-size-y = <3864>;
-		ti,x-plate-ohms = /bits/ 16 <180>;
-		touchscreen-max-pressure = <255>;
-		touchscreen-average-samples = <10>;
-		ti,debounce-tol = /bits/ 16 <3>;
-		ti,debounce-rep = /bits/ 16 <1>;
-		ti,settle-delay-usec = /bits/ 16 <150>;
-		ti,keep-vref-on;
-		wakeup-source;
-	};
-};
-
-&fec1 {
-	pinctrl-names = "default", "sleep";
-	pinctrl-0 = <&pinctrl_fec1>;
-	pinctrl-1 = <&pinctrl_fec1_sleep>;
-	phy-mode = "rgmii";
-	phy-handle = <&ethphy>;
-	phy-supply = <&reg_eth_phy>;
-	fsl,magic-packet;
-	status = "okay";
-
-	mdio {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		ethphy: ethernet-phy@4 { /* AR8033 or ADIN1300 */
-			compatible = "ethernet-phy-ieee802.3-c22";
-			reg = <4>;
-			reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
-			reset-assert-us = <10000>;
-			/*
-			 * Deassert delay:
-			 * ADIN1300 requires 5ms.
-			 * AR8033   requires 1ms.
-			 */
-			reset-deassert-us = <20000>;
-		};
-	};
-};
-
-&i2c1 {
-	clock-frequency = <400000>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_i2c1>;
-	status = "okay";
-
-	pmic@4b {
-		compatible = "rohm,bd71847";
-		reg = <0x4b>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_pmic>;
-		interrupt-parent = <&gpio2>;
-		interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
-		rohm,reset-snvs-powered;
-
-		regulators {
-			buck1_reg: BUCK1 {
-				regulator-name = "buck1";
-				regulator-min-microvolt = <700000>;
-				regulator-max-microvolt = <1300000>;
-				regulator-boot-on;
-				regulator-always-on;
-				regulator-ramp-delay = <1250>;
-			};
-
-			buck2_reg: BUCK2 {
-				regulator-name = "buck2";
-				regulator-min-microvolt = <700000>;
-				regulator-max-microvolt = <1300000>;
-				regulator-boot-on;
-				regulator-always-on;
-				regulator-ramp-delay = <1250>;
-				rohm,dvs-run-voltage = <1000000>;
-				rohm,dvs-idle-voltage = <900000>;
-			};
-
-			buck3_reg: BUCK3 {
-				regulator-name = "buck3";
-				regulator-min-microvolt = <700000>;
-				regulator-max-microvolt = <1350000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			buck4_reg: BUCK4 {
-				regulator-name = "buck4";
-				regulator-min-microvolt = <2600000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			buck5_reg: BUCK5 {
-				regulator-name = "buck5";
-				regulator-min-microvolt = <1605000>;
-				regulator-max-microvolt = <1995000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			buck6_reg: BUCK6 {
-				regulator-name = "buck6";
-				regulator-min-microvolt = <800000>;
-				regulator-max-microvolt = <1400000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			ldo1_reg: LDO1 {
-				regulator-name = "ldo1";
-				regulator-min-microvolt = <1600000>;
-				regulator-max-microvolt = <1900000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			ldo2_reg: LDO2 {
-				regulator-name = "ldo2";
-				regulator-min-microvolt = <800000>;
-				regulator-max-microvolt = <900000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			ldo3_reg: LDO3 {
-				regulator-name = "ldo3";
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			ldo4_reg: LDO4 {
-				regulator-name = "ldo4";
-				regulator-min-microvolt = <900000>;
-				regulator-max-microvolt = <1800000>;
-				regulator-always-on;
-			};
-
-			ldo5_reg: LDO5 {
-				regulator-compatible = "ldo5";
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-				regulator-always-on;
-			};
-
-			ldo6_reg: LDO6 {
-				regulator-name = "ldo6";
-				regulator-min-microvolt = <900000>;
-				regulator-max-microvolt = <1800000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-		};
-	};
-
-	eeprom_som: eeprom@52 {
-		compatible = "atmel,24c04";
-		reg = <0x52>;
-		pagesize = <16>;
-	};
-};
-
-&i2c3 {
-	clock-frequency = <400000>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_i2c3>;
-	status = "okay";
-
-	/* TODO: configure audio, as of now just put a placeholder */
-	wm8904: codec@1a {
-		compatible = "wlf,wm8904";
-		reg = <0x1a>;
-		status = "disabled";
-	};
-};
-
-&snvs_pwrkey {
-	status = "okay";
-};
-
-/* Bluetooth */
-&uart2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_uart2>;
-	assigned-clocks = <&clk IMX8MN_CLK_UART2>;
-	assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
-	uart-has-rtscts;
-	status = "okay";
-};
-
-/* Console */
-&uart4 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_uart4>;
-	status = "okay";
-};
-
-&usbotg1 {
-	dr_mode = "otg";
-	usb-role-switch;
-	status = "okay";
-};
-
-/* WIFI */
-&usdhc1 {
-	#address-cells = <1>;
-	#size-cells = <0>;
-	pinctrl-names = "default", "state_100mhz", "state_200mhz";
-	pinctrl-0 = <&pinctrl_usdhc1>;
-	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
-	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
-	bus-width = <4>;
-	non-removable;
-	keep-power-in-suspend;
-	status = "okay";
-
-	brcmf: bcrmf@1 {
-		reg = <1>;
-		compatible = "brcm,bcm4329-fmac";
-	};
-};
-
-/* SD */
-&usdhc2 {
-	assigned-clocks = <&clk IMX8MN_CLK_USDHC2>;
-	assigned-clock-rates = <200000000>;
-	pinctrl-names = "default", "state_100mhz", "state_200mhz";
-	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
-	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
-	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
-	cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
-	bus-width = <4>;
-	vmmc-supply = <&reg_usdhc2_vmmc>;
-	status = "okay";
-};
-
-/* eMMC */
-&usdhc3 {
-	assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
-	assigned-clock-rates = <400000000>;
-	pinctrl-names = "default", "state_100mhz", "state_200mhz";
-	pinctrl-0 = <&pinctrl_usdhc3>;
-	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
-	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
-	bus-width = <8>;
-	non-removable;
-	status = "okay";
-};
-
-&wdog1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_wdog>;
-	fsl,ext-reset-output;
-	status = "okay";
-};
-
-&iomuxc {
-	pinctrl_ecspi1: ecspi1grp {
-		fsl,pins = <
-			MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK		0x13
-			MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI		0x13
-			MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO		0x13
-			MX8MN_IOMUXC_GPIO1_IO14_GPIO1_IO14		0x13
-			MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0		0x13
-		>;
-	};
-
-	pinctrl_fec1: fec1grp {
-		fsl,pins = <
-			MX8MN_IOMUXC_ENET_MDC_ENET1_MDC			0x3
-			MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
-			MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
-			MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
-			MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
-			MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
-			MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
-			MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
-			MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
-			MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
-			MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
-			MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
-			MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
-			MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
-			MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x19
-		>;
-	};
-
-	pinctrl_fec1_sleep: fec1sleepgrp {
-		fsl,pins = <
-			MX8MN_IOMUXC_ENET_MDC_GPIO1_IO16		0x120
-			MX8MN_IOMUXC_ENET_MDIO_GPIO1_IO17		0x120
-			MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18		0x120
-			MX8MN_IOMUXC_ENET_TD2_GPIO1_IO19		0x120
-			MX8MN_IOMUXC_ENET_TD1_GPIO1_IO20		0x120
-			MX8MN_IOMUXC_ENET_TD0_GPIO1_IO21		0x120
-			MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29		0x120
-			MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28		0x120
-			MX8MN_IOMUXC_ENET_RD1_GPIO1_IO27		0x120
-			MX8MN_IOMUXC_ENET_RD0_GPIO1_IO26		0x120
-			MX8MN_IOMUXC_ENET_TXC_GPIO1_IO23		0x120
-			MX8MN_IOMUXC_ENET_RXC_GPIO1_IO25		0x120
-			MX8MN_IOMUXC_ENET_RX_CTL_GPIO1_IO24		0x120
-			MX8MN_IOMUXC_ENET_TX_CTL_GPIO1_IO22		0x120
-			MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x120
-		>;
-	};
-
-	pinctrl_i2c1: i2c1grp {
-		fsl,pins = <
-			MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL		0x400001c3
-			MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA		0x400001c3
-		>;
-	};
-
-	pinctrl_i2c3: i2c3grp {
-		fsl,pins = <
-			MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL		0x400001c3
-			MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA		0x400001c3
-		>;
-	};
-
-	pinctrl_pmic: pmicirqgrp {
-		fsl,pins = <
-			MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8	0x141
-		>;
-	};
-
-	pinctrl_reg_eth_phy: regethphygrp {
-		fsl,pins = <
-			MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9	0x41
-		>;
-	};
-
-	pinctrl_restouch: restouchgrp {
-		fsl,pins = <
-			MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x1c0
-		>;
-	};
-
-	pinctrl_uart2: uart2grp {
-		fsl,pins = <
-			MX8MN_IOMUXC_SAI3_TXFS_UART2_DCE_RX	0x140
-			MX8MN_IOMUXC_SAI3_TXC_UART2_DCE_TX	0x140
-			MX8MN_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B	0x140
-			MX8MN_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B	0x140
-		>;
-	};
-
-	pinctrl_uart4: uart4grp {
-		fsl,pins = <
-			MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX	0x140
-			MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX	0x140
-		>;
-	};
-
-	pinctrl_usdhc1: usdhc1grp {
-		fsl,pins = <
-			MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK		0x190
-			MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d0
-			MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d0
-			MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d0
-			MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d0
-			MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d0
-		>;
-	};
-
-	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
-		fsl,pins = <
-			MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK		0x194
-			MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d4
-			MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d4
-			MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d4
-			MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d4
-			MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d4
-		>;
-	};
-
-	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
-		fsl,pins = <
-			MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK		0x196
-			MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d6
-			MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d6
-			MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d6
-			MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d6
-			MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d6
-		>;
-	};
-
-	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
-		fsl,pins = <
-			MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10	0x41
-		>;
-	};
-
-	pinctrl_usdhc2: usdhc2grp {
-		fsl,pins = <
-			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x190
-			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0
-			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0
-			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0
-			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0
-			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0
-			MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
-		>;
-	};
-
-	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
-		fsl,pins = <
-			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x194
-			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4
-			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4
-			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4
-			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4
-			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4
-			MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
-		>;
-	};
-
-	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
-		fsl,pins = <
-			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x196
-			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6
-			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6
-			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6
-			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6
-			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6
-			MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
-		>;
-	};
-
-	pinctrl_usdhc3: usdhc3grp {
-		fsl,pins = <
-			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK	0x190
-			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d0
-			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d0
-			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d0
-			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d0
-			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d0
-			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d0
-			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d0
-			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d0
-			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d0
-			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x190
-		>;
-	};
-
-	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
-		fsl,pins = <
-			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK	0x194
-			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d4
-			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d4
-			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d4
-			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d4
-			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d4
-			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d4
-			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d4
-			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d4
-			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d4
-			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x194
-		>;
-	};
-
-	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
-		fsl,pins = <
-			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK	0x196
-			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d6
-			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d6
-			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d6
-			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d6
-			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d6
-			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d6
-			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d6
-			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d6
-			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d6
-			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x196
-		>;
-	};
-
-	pinctrl_wdog: wdoggrp {
-		fsl,pins = <
-			MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0x166
-		>;
-	};
-};

arch/arm/dts/imx8mp-kontron-bl-osm-s-u-boot.dtsi

@@ -0,0 +1,124 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2022 Kontron Electronics GmbH
+ */
+
+#include "imx8mp-u-boot.dtsi"
+
+/ {
+	wdt-reboot {
+		compatible = "wdt-reboot";
+		wdt = <&wdog1>;
+		bootph-pre-ram;
+	};
+};
+
+&gpio1 {
+	bootph-pre-ram;
+};
+
+&gpio2 {
+	bootph-pre-ram;
+};
+
+&gpio3 {
+	bootph-pre-ram;
+};
+
+&gpio4 {
+	bootph-pre-ram;
+};
+
+&gpio5 {
+	bootph-pre-ram;
+};
+
+/* Enable I2C1 to probe for a touch controller on LVDS connector */
+&i2c1 {
+	status = "okay";
+};
+
+&i2c5 {
+	bootph-pre-ram;
+};
+
+&pinctrl_i2c5 {
+	bootph-pre-ram;
+};
+
+&pinctrl_i2c5_gpio {
+	bootph-pre-ram;
+};
+
+&pinctrl_pmic {
+	bootph-pre-ram;
+};
+
+&pinctrl_uart3 {
+	bootph-pre-ram;
+};
+
+&pinctrl_wdog {
+	bootph-pre-ram;
+};
+
+&pca9450 {
+	bootph-pre-ram;
+};
+
+&reg_vdd_soc {
+	bootph-pre-ram;
+};
+
+&reg_vdd_arm {
+	bootph-pre-ram;
+};
+
+&reg_vdd_3v3 {
+	bootph-pre-ram;
+};
+
+&reg_vdd_1v8 {
+	bootph-pre-ram;
+};
+
+&reg_nvcc_dram {
+	bootph-pre-ram;
+};
+
+&reg_nvcc_snvs {
+	bootph-pre-ram;
+};
+
+&reg_vdda {
+	bootph-pre-ram;
+};
+
+&reg_nvcc_sd {
+	bootph-pre-ram;
+};
+
+&uart3 {
+	bootph-pre-ram;
+};
+
+&usb_dwc3_0 {
+	/*
+	 * OTG role switching is currently not supported in U-Boot, use peripheral
+	 * as default.
+	 */
+	dr_mode = "peripheral";
+};
+
+&usb3_phy0 {
+	/*
+	 * Workaround to fix USB in U-Boot until the following commit from
+	 * linux-next-20251111 has landed and been synced to dts/upstream:
+	 * 6504297872c7 ("arm64: dts: imx8mp-kontron: Fix USB OTG role switching")
+	 */
+	/delete-property/ vbus-supply;
+};
+
+&wdog1 {
+	bootph-pre-ram;
+};

arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi

@@ -12,6 +12,26 @@
 		wdt = <&wdog1>;
 		bootph-pre-ram;
 	};
+
+	bootstd {
+		bootph-verify;
+		compatible = "u-boot,boot-std";
+
+		filename-prefixes = "/", "/boot/";
+		bootdev-order = "mmc2", "mmc1", "ethernet";
+
+		efi {
+			compatible = "u-boot,distro-efi";
+		};
+
+		rauc {
+			compatible = "u-boot,distro-rauc";
+		};
+
+		script {
+			compatible = "u-boot,script";
+		};
+	};
 };
 
 &reg_usdhc2_vmmc {

arch/arm/dts/imx8ulp-evk-u-boot.dtsi

@@ -22,6 +22,14 @@
 	bootph-all;
 };
 
+&mu {
+	status = "disabled";
+};
+
+&wdog3 {
+	status = "disabled";
+};
+
 &per_bridge4 {
 	bootph-pre-ram;
 };

arch/arm/dts/imx8ulp-evk.dts

@@ -1,125 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2021 NXP
- */
-
-/dts-v1/;
-
-#include "imx8ulp.dtsi"
-
-/ {
-	model = "NXP i.MX8ULP EVK";
-	compatible = "fsl,imx8ulp-evk", "fsl,imx8ulp";
-
-	chosen {
-		stdout-path = &lpuart5;
-	};
-
-	memory@80000000 {
-		device_type = "memory";
-		reg = <0x0 0x80000000 0 0x80000000>;
-	};
-
-	clock_ext_rmii: clock-ext-rmii {
-		compatible = "fixed-clock";
-		clock-frequency = <50000000>;
-		clock-output-names = "ext_rmii_clk";
-		#clock-cells = <0>;
-	};
-
-	clock_ext_ts: clock-ext-ts {
-		compatible = "fixed-clock";
-		/* External ts clock is 50MHZ from PHY on EVK board. */
-		clock-frequency = <50000000>;
-		clock-output-names = "ext_ts_clk";
-		#clock-cells = <0>;
-	};
-};
-
-&lpuart5 {
-	/* console */
-	pinctrl-names = "default", "sleep";
-	pinctrl-0 = <&pinctrl_lpuart5>;
-	pinctrl-1 = <&pinctrl_lpuart5>;
-	status = "okay";
-};
-
-&usdhc0 {
-	pinctrl-names = "default", "sleep";
-	pinctrl-0 = <&pinctrl_usdhc0>;
-	pinctrl-1 = <&pinctrl_usdhc0>;
-	non-removable;
-	bus-width = <8>;
-	status = "okay";
-};
-
-&fec {
-	pinctrl-names = "default", "sleep";
-	pinctrl-0 = <&pinctrl_enet>;
-	pinctrl-1 = <&pinctrl_enet>;
-	clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
-		 <&pcc4 IMX8ULP_CLK_ENET>,
-		 <&cgc1 IMX8ULP_CLK_ENET_TS_SEL>,
-		 <&clock_ext_rmii>;
-	clock-names = "ipg", "ahb", "ptp", "enet_clk_ref";
-	assigned-clocks = <&cgc1 IMX8ULP_CLK_ENET_TS_SEL>;
-	assigned-clock-parents = <&clock_ext_ts>;
-	phy-mode = "rmii";
-	phy-handle = <&ethphy>;
-	status = "okay";
-
-	mdio {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		ethphy: ethernet-phy@1 {
-			reg = <1>;
-			micrel,led-mode = <1>;
-		};
-	};
-};
-
-&iomuxc1 {
-	pinctrl_enet: enetgrp {
-		fsl,pins = <
-			MX8ULP_PAD_PTE15__ENET0_MDC     0x43
-			MX8ULP_PAD_PTE14__ENET0_MDIO    0x43
-			MX8ULP_PAD_PTE17__ENET0_RXER    0x43
-			MX8ULP_PAD_PTE18__ENET0_CRS_DV  0x43
-			MX8ULP_PAD_PTF1__ENET0_RXD0     0x43
-			MX8ULP_PAD_PTE20__ENET0_RXD1    0x43
-			MX8ULP_PAD_PTE16__ENET0_TXEN    0x43
-			MX8ULP_PAD_PTE23__ENET0_TXD0    0x43
-			MX8ULP_PAD_PTE22__ENET0_TXD1    0x43
-			MX8ULP_PAD_PTE19__ENET0_REFCLK  0x43
-			MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x43
-		>;
-	};
-
-	pinctrl_lpuart5: lpuart5grp {
-		fsl,pins = <
-			MX8ULP_PAD_PTF14__LPUART5_TX	0x3
-			MX8ULP_PAD_PTF15__LPUART5_RX	0x3
-		>;
-	};
-
-	pinctrl_usdhc0: usdhc0grp {
-		fsl,pins = <
-			MX8ULP_PAD_PTD1__SDHC0_CMD	0x43
-			MX8ULP_PAD_PTD2__SDHC0_CLK	0x10042
-			MX8ULP_PAD_PTD10__SDHC0_D0	0x43
-			MX8ULP_PAD_PTD9__SDHC0_D1	0x43
-			MX8ULP_PAD_PTD8__SDHC0_D2	0x43
-			MX8ULP_PAD_PTD7__SDHC0_D3	0x43
-			MX8ULP_PAD_PTD6__SDHC0_D4	0x43
-			MX8ULP_PAD_PTD5__SDHC0_D5	0x43
-			MX8ULP_PAD_PTD4__SDHC0_D6	0x43
-			MX8ULP_PAD_PTD3__SDHC0_D7	0x43
-			MX8ULP_PAD_PTD11__SDHC0_DQS	0x10042
-		>;
-	};
-};
-
-&wdog3 {
-	status = "disabled";
-};

arch/arm/dts/imx8ulp.dtsi

@@ -1,476 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2021 NXP
- */
-
-#include <dt-bindings/clock/imx8ulp-clock.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/power/imx8ulp-power.h>
-
-#include "imx8ulp-pinfunc.h"
-
-/ {
-	interrupt-parent = <&gic>;
-	#address-cells = <2>;
-	#size-cells = <2>;
-
-	aliases {
-		ethernet0 = &fec;
-		gpio0 = &gpiod;
-		gpio1 = &gpioe;
-		gpio2 = &gpiof;
-		mmc0 = &usdhc0;
-		mmc1 = &usdhc1;
-		mmc2 = &usdhc2;
-		serial0 = &lpuart4;
-		serial1 = &lpuart5;
-		serial2 = &lpuart6;
-		serial3 = &lpuart7;
-	};
-
-	cpus {
-		#address-cells = <2>;
-		#size-cells = <0>;
-
-		A35_0: cpu@0 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a35";
-			reg = <0x0 0x0>;
-			enable-method = "psci";
-			next-level-cache = <&A35_L2>;
-		};
-
-		A35_1: cpu@1 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a35";
-			reg = <0x0 0x1>;
-			enable-method = "psci";
-			next-level-cache = <&A35_L2>;
-		};
-
-		A35_L2: l2-cache0 {
-			compatible = "cache";
-		};
-	};
-
-	gic: interrupt-controller@2d400000 {
-		compatible = "arm,gic-v3";
-		reg = <0x0 0x2d400000 0 0x10000>, /* GIC Dist */
-		      <0x0 0x2d440000 0 0xc0000>; /* GICR (RD_base + SGI_base) */
-		#interrupt-cells = <3>;
-		interrupt-controller;
-		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	pmu {
-		compatible = "arm,cortex-a35-pmu";
-		interrupt-parent = <&gic>;
-		interrupts = <GIC_PPI 7
-			     (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
-		interrupt-affinity = <&A35_0>, <&A35_1>;
-	};
-
-	psci {
-		compatible = "arm,psci-1.0";
-		method = "smc";
-	};
-
-	timer {
-		compatible = "arm,armv8-timer";
-		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
-			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
-			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
-			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
-	};
-
-	frosc: clock-frosc {
-		compatible = "fixed-clock";
-		clock-frequency = <192000000>;
-		clock-output-names = "frosc";
-		#clock-cells = <0>;
-	};
-
-	lposc: clock-lposc {
-		compatible = "fixed-clock";
-		clock-frequency = <1000000>;
-		clock-output-names = "lposc";
-		#clock-cells = <0>;
-	};
-
-	rosc: clock-rosc {
-		compatible = "fixed-clock";
-		clock-frequency = <32768>;
-		clock-output-names = "rosc";
-		#clock-cells = <0>;
-	};
-
-	sosc: clock-sosc {
-		compatible = "fixed-clock";
-		clock-frequency = <24000000>;
-		clock-output-names = "sosc";
-		#clock-cells = <0>;
-	};
-
-	sram@2201f000 {
-		compatible = "mmio-sram";
-		reg = <0x0 0x2201f000 0x0 0x1000>;
-
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0 0x0 0x2201f000 0x1000>;
-
-		scmi_buf: scmi-sram-section@0 {
-			compatible = "arm,scmi-shmem";
-			reg = <0x0 0x400>;
-		};
-	};
-
-	firmware {
-		scmi {
-			compatible = "arm,scmi-smc";
-			arm,smc-id = <0xc20000fe>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			shmem = <&scmi_buf>;
-
-			scmi_devpd: protocol@11 {
-				reg = <0x11>;
-				#power-domain-cells = <1>;
-			};
-
-			scmi_sensor: protocol@15 {
-				reg = <0x15>;
-				#thermal-sensor-cells = <1>;
-			};
-		};
-	};
-
-	soc: soc@0 {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0x0 0x0 0x0 0x40000000>;
-
-		s4muap: mailbox@27020000 {
-			compatible = "fsl,imx8ulp-mu-s4";
-			reg = <0x27020000 0x10000>;
-			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
-			#mbox-cells = <2>;
-		};
-
-		per_bridge3: bus@29000000 {
-			compatible = "simple-bus";
-			reg = <0x29000000 0x800000>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges;
-
-			mu: mailbox@29220000 {
-				compatible = "fsl,imx8ulp-mu";
-				reg = <0x29220000 0x10000>;
-				interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
-				#mbox-cells = <2>;
-				status = "disabled";
-			};
-
-			mu3: mailbox@29230000 {
-				compatible = "fsl,imx8ulp-mu";
-				reg = <0x29230000 0x10000>;
-				interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&pcc3 IMX8ULP_CLK_MU3_A>;
-				#mbox-cells = <2>;
-				status = "disabled";
-			};
-
-			wdog3: watchdog@292a0000 {
-				compatible = "fsl,imx8ulp-wdt", "fsl,imx7ulp-wdt";
-				reg = <0x292a0000 0x10000>;
-				interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&pcc3 IMX8ULP_CLK_WDOG3>;
-				assigned-clocks = <&pcc3 IMX8ULP_CLK_WDOG3>;
-				assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SOSC_DIV2>;
-				timeout-sec = <40>;
-			};
-
-			cgc1: clock-controller@292c0000 {
-				compatible = "fsl,imx8ulp-cgc1";
-				reg = <0x292c0000 0x10000>;
-				#clock-cells = <1>;
-			};
-
-			pcc3: clock-controller@292d0000 {
-				compatible = "fsl,imx8ulp-pcc3";
-				reg = <0x292d0000 0x10000>;
-				#clock-cells = <1>;
-				#reset-cells = <1>;
-			};
-
-			tpm5: tpm@29340000 {
-				compatible = "fsl,imx8ulp-tpm", "fsl,imx7ulp-tpm";
-				reg = <0x29340000 0x1000>;
-				interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&pcc3 IMX8ULP_CLK_TPM5>,
-					 <&pcc3 IMX8ULP_CLK_TPM5>;
-				clock-names = "ipg", "per";
-				status = "disabled";
-			};
-
-			lpi2c4: i2c@29370000 {
-				compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
-				reg = <0x29370000 0x10000>;
-				interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>,
-					 <&pcc3 IMX8ULP_CLK_LPI2C4>;
-				clock-names = "per", "ipg";
-				assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>;
-				assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
-				assigned-clock-rates = <48000000>;
-				status = "disabled";
-			};
-
-			lpi2c5: i2c@29380000 {
-				compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
-				reg = <0x29380000 0x10000>;
-				interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>,
-					 <&pcc3 IMX8ULP_CLK_LPI2C5>;
-				clock-names = "per", "ipg";
-				assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>;
-				assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
-				assigned-clock-rates = <48000000>;
-				status = "disabled";
-			};
-
-			lpuart4: serial@29390000 {
-				compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
-				reg = <0x29390000 0x1000>;
-				interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&pcc3 IMX8ULP_CLK_LPUART4>;
-				clock-names = "ipg";
-				status = "disabled";
-			};
-
-			lpuart5: serial@293a0000 {
-				compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
-				reg = <0x293a0000 0x1000>;
-				interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&pcc3 IMX8ULP_CLK_LPUART5>;
-				clock-names = "ipg";
-				status = "disabled";
-			};
-
-			lpspi4: spi@293b0000 {
-				#address-cells = <1>;
-				#size-cells = <0>;
-				compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi";
-				reg = <0x293b0000 0x10000>;
-				interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>,
-					 <&pcc3 IMX8ULP_CLK_LPSPI4>;
-				clock-names = "per", "ipg";
-				assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>;
-				assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
-				assigned-clock-rates = <48000000>;
-				status = "disabled";
-			};
-
-			lpspi5: spi@293c0000 {
-				#address-cells = <1>;
-				#size-cells = <0>;
-				compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi";
-				reg = <0x293c0000 0x10000>;
-				interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>,
-					 <&pcc3 IMX8ULP_CLK_LPSPI5>;
-				clock-names = "per", "ipg";
-				assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>;
-				assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
-				assigned-clock-rates = <48000000>;
-				status = "disabled";
-			};
-		};
-
-		per_bridge4: bus@29800000 {
-			compatible = "simple-bus";
-			reg = <0x29800000 0x800000>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges;
-
-			pcc4: clock-controller@29800000 {
-				compatible = "fsl,imx8ulp-pcc4";
-				reg = <0x29800000 0x10000>;
-				#clock-cells = <1>;
-				#reset-cells = <1>;
-			};
-
-			lpi2c6: i2c@29840000 {
-				compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
-				reg = <0x29840000 0x10000>;
-				interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>,
-					 <&pcc4 IMX8ULP_CLK_LPI2C6>;
-				clock-names = "per", "ipg";
-				assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>;
-				assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
-				assigned-clock-rates = <48000000>;
-				status = "disabled";
-			};
-
-			lpi2c7: i2c@29850000 {
-				compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
-				reg = <0x29850000 0x10000>;
-				interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>,
-					 <&pcc4 IMX8ULP_CLK_LPI2C7>;
-				clock-names = "per", "ipg";
-				assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>;
-				assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
-				assigned-clock-rates = <48000000>;
-				status = "disabled";
-			};
-
-			lpuart6: serial@29860000 {
-				compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
-				reg = <0x29860000 0x1000>;
-				interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&pcc4 IMX8ULP_CLK_LPUART6>;
-				clock-names = "ipg";
-				status = "disabled";
-			};
-
-			lpuart7: serial@29870000 {
-				compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
-				reg = <0x29870000 0x1000>;
-				interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&pcc4 IMX8ULP_CLK_LPUART7>;
-				clock-names = "ipg";
-				status = "disabled";
-			};
-
-			iomuxc1: pinctrl@298c0000 {
-				compatible = "fsl,imx8ulp-iomuxc1";
-				reg = <0x298c0000 0x10000>;
-			};
-
-			usdhc0: mmc@298d0000 {
-				compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc";
-				reg = <0x298d0000 0x10000>;
-				interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
-					 <&cgc1 IMX8ULP_CLK_XBAR_AD_DIVPLAT>,
-					 <&pcc4 IMX8ULP_CLK_USDHC0>;
-				clock-names = "ipg", "ahb", "per";
-				power-domains = <&scmi_devpd IMX8ULP_PD_USDHC0>;
-				fsl,tuning-start-tap = <20>;
-				fsl,tuning-step = <2>;
-				bus-width = <4>;
-				status = "disabled";
-			};
-
-			usdhc1: mmc@298e0000 {
-				compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc";
-				reg = <0x298e0000 0x10000>;
-				interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
-					 <&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>,
-					 <&pcc4 IMX8ULP_CLK_USDHC1>;
-				clock-names = "ipg", "ahb", "per";
-				power-domains = <&scmi_devpd IMX8ULP_PD_USDHC1>;
-				fsl,tuning-start-tap = <20>;
-				fsl,tuning-step = <2>;
-				bus-width = <4>;
-				status = "disabled";
-			};
-
-			usdhc2: mmc@298f0000 {
-				compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc";
-				reg = <0x298f0000 0x10000>;
-				interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
-					 <&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>,
-					 <&pcc4 IMX8ULP_CLK_USDHC2>;
-				clock-names = "ipg", "ahb", "per";
-				power-domains = <&scmi_devpd IMX8ULP_PD_USDHC2_USB1>;
-				fsl,tuning-start-tap = <20>;
-				fsl,tuning-step = <2>;
-				bus-width = <4>;
-				status = "disabled";
-			};
-
-			fec: ethernet@29950000 {
-				compatible = "fsl,imx8ulp-fec", "fsl,imx6ul-fec", "fsl,imx6q-fec";
-				reg = <0x29950000 0x10000>;
-				interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
-				interrupt-names = "int0";
-				fsl,num-tx-queues = <1>;
-				fsl,num-rx-queues = <1>;
-				status = "disabled";
-			};
-		};
-
-		gpioe: gpio@2d000080 {
-				compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
-				reg = <0x2d000080 0x1000>, <0x2d000040 0x40>;
-				gpio-controller;
-				#gpio-cells = <2>;
-				interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				clocks = <&pcc4 IMX8ULP_CLK_RGPIOE>,
-					 <&pcc4 IMX8ULP_CLK_PCTLE>;
-				clock-names = "gpio", "port";
-				gpio-ranges = <&iomuxc1 0 32 24>;
-		};
-
-		gpiof: gpio@2d010080 {
-				compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
-				reg = <0x2d010080 0x1000>, <0x2d010040 0x40>;
-				gpio-controller;
-				#gpio-cells = <2>;
-				interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				clocks = <&pcc4 IMX8ULP_CLK_RGPIOF>,
-					 <&pcc4 IMX8ULP_CLK_PCTLF>;
-				clock-names = "gpio", "port";
-				gpio-ranges = <&iomuxc1 0 64 32>;
-		};
-
-		per_bridge5: bus@2d800000 {
-			compatible = "simple-bus";
-			reg = <0x2d800000 0x800000>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges;
-
-			cgc2: clock-controller@2da60000 {
-				compatible = "fsl,imx8ulp-cgc2";
-				reg = <0x2da60000 0x10000>;
-				#clock-cells = <1>;
-			};
-
-			pcc5: clock-controller@2da70000 {
-				compatible = "fsl,imx8ulp-pcc5";
-				reg = <0x2da70000 0x10000>;
-				#clock-cells = <1>;
-				#reset-cells = <1>;
-			};
-		};
-
-		gpiod: gpio@2e200080 {
-			compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
-			reg = <0x2e200080 0x1000>, <0x2e200040 0x40>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-controller;
-			#interrupt-cells = <2>;
-			clocks = <&pcc5 IMX8ULP_CLK_RGPIOD>,
-				 <&pcc5 IMX8ULP_CLK_RGPIOD>;
-			clock-names = "gpio", "port";
-			gpio-ranges = <&iomuxc1 0 0 24>;
-		};
-	};
-};

arch/arm/dts/imx91-11x11-frdm-u-boot.dtsi

@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2025 NXP
+ */
+
+#include "imx91-u-boot.dtsi"
+
+/ {
+	wdt-reboot {
+		compatible = "wdt-reboot";
+		wdt = <&wdog3>;
+		bootph-pre-ram;
+		bootph-some-ram;
+	};
+
+	firmware {
+		optee {
+			compatible = "linaro,optee-tz";
+			method = "smc";
+		};
+	};
+};
+
+&s4muap {
+	bootph-pre-ram;
+	bootph-some-ram;
+	status = "okay";
+};
+
+&clk {
+	/delete-property/ assigned-clocks;
+	/delete-property/ assigned-clock-rates;
+	/delete-property/ assigned-clock-parents;
+};

arch/arm/dts/imx91-11x11-frdm.dts

@@ -0,0 +1,773 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2025 NXP
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/usb/pd.h>
+#include "imx91.dtsi"
+
+/ {
+	compatible = "fsl,imx91-11x11-frdm", "fsl,imx91";
+	model = "NXP i.MX91 11X11 FRDM Board";
+
+	aliases {
+		ethernet0 = &fec;
+		ethernet1 = &eqos;
+		rtc0 = &pcf2131;
+	};
+
+	chosen {
+		stdout-path = &lpuart1;
+	};
+
+	reg_vref_1v8: regulator-adc-vref {
+		compatible = "regulator-fixed";
+		regulator-max-microvolt = <1800000>;
+		regulator-min-microvolt = <1800000>;
+		regulator-name = "vref_1v8";
+	};
+
+	reg_usdhc2_vmmc: regulator-usdhc2 {
+		compatible = "regulator-fixed";
+		off-on-delay-us = <12000>;
+		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
+		pinctrl-names = "default";
+		regulator-max-microvolt = <3300000>;
+		regulator-min-microvolt = <3300000>;
+		regulator-name = "VSD_3V3";
+		gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		bootph-pre-ram;
+		bootph-some-ram;
+	};
+
+	reg_vdd_12v: regulator-vdd-12v {
+		compatible = "regulator-fixed";
+		regulator-max-microvolt = <12000000>;
+		regulator-min-microvolt = <12000000>;
+		regulator-name = "reg_vdd_12v";
+		gpio = <&pcal6524 14 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	reg_vexp_3v3: regulator-vexp-3v3 {
+		compatible = "regulator-fixed";
+		regulator-max-microvolt = <3300000>;
+		regulator-min-microvolt = <3300000>;
+		regulator-name = "VEXP_3V3";
+		vin-supply = <&buck4>;
+		gpio = <&pcal6524 2 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	reg_vexp_5v: regulator-vexp-5v {
+		compatible = "regulator-fixed";
+		regulator-max-microvolt = <5000000>;
+		regulator-min-microvolt = <5000000>;
+		regulator-name = "VEXP_5V";
+		gpio = <&pcal6524 8 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	reserved-memory {
+		ranges;
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		linux,cma {
+			compatible = "shared-dma-pool";
+			alloc-ranges = <0 0x80000000 0 0x40000000>;
+			reusable;
+			size = <0 0x10000000>;
+			linux,cma-default;
+		};
+	};
+
+	soc@0 {
+		bootph-all;
+		bootph-pre-ram;
+	};
+};
+
+&adc1 {
+	vref-supply = <&reg_vref_1v8>;
+	status = "okay";
+};
+
+&aips1 {
+	bootph-pre-ram;
+	bootph-all;
+};
+
+&aips2 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&aips3 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&clk {
+	bootph-all;
+	bootph-pre-ram;
+};
+
+&clk_ext1 {
+	bootph-all;
+	bootph-pre-ram;
+};
+
+&eqos {
+	phy-handle = <&ethphy1>;
+	phy-mode = "rgmii-id";
+	pinctrl-0 = <&pinctrl_eqos>;
+	pinctrl-1 = <&pinctrl_eqos_sleep>;
+	pinctrl-names = "default", "sleep";
+	status = "okay";
+
+	mdio {
+		compatible = "snps,dwmac-mdio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clock-frequency = <5000000>;
+
+		ethphy1: ethernet-phy@1 {
+			reg = <1>;
+			eee-broken-1000t;
+			reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>;
+			reset-assert-us = <15000>;
+			reset-deassert-us = <100000>;
+		};
+	};
+};
+
+&fec {
+	phy-handle = <&ethphy2>;
+	phy-mode = "rgmii-id";
+	pinctrl-0 = <&pinctrl_fec>;
+	pinctrl-1 = <&pinctrl_fec_sleep>;
+	pinctrl-names = "default", "sleep";
+	fsl,magic-packet;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clock-frequency = <5000000>;
+
+		ethphy2: ethernet-phy@2 {
+			reg = <2>;
+			eee-broken-1000t;
+			reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>;
+			reset-assert-us = <15000>;
+			reset-deassert-us = <100000>;
+		};
+	};
+};
+
+&gpio1 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&gpio2 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&gpio3 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&gpio4 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&lpi2c1 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&lpi2c2 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	clock-frequency = <400000>;
+	pinctrl-0 = <&pinctrl_lpi2c2>;
+	pinctrl-names = "default";
+	status = "okay";
+	bootph-pre-ram;
+	bootph-some-ram;
+
+	pcal6524: gpio@22 {
+		compatible = "nxp,pcal6524";
+		reg = <0x22>;
+		#interrupt-cells = <2>;
+		interrupt-controller;
+		interrupt-parent = <&gpio3>;
+		interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		pinctrl-0 = <&pinctrl_pcal6524>;
+		pinctrl-names = "default";
+	};
+
+	pmic@25 {
+		compatible = "nxp,pca9451a";
+		reg = <0x25>;
+		interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
+		interrupt-parent = <&pcal6524>;
+		bootph-pre-ram;
+		bootph-some-ram;
+
+		regulators {
+			bootph-pre-ram;
+			bootph-some-ram;
+
+			buck1: BUCK1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-max-microvolt = <2237500>;
+				regulator-min-microvolt = <650000>;
+				regulator-name = "BUCK1";
+				regulator-ramp-delay = <3125>;
+			};
+
+			buck2: BUCK2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-max-microvolt = <2187500>;
+				regulator-min-microvolt = <600000>;
+				regulator-name = "BUCK2";
+				regulator-ramp-delay = <3125>;
+			};
+
+			buck4: BUCK4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-max-microvolt = <3400000>;
+				regulator-min-microvolt = <600000>;
+				regulator-name = "BUCK4";
+			};
+
+			buck5: BUCK5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-max-microvolt = <3400000>;
+				regulator-min-microvolt = <600000>;
+				regulator-name = "BUCK5";
+			};
+
+			buck6: BUCK6 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-max-microvolt = <3400000>;
+				regulator-min-microvolt = <600000>;
+				regulator-name = "BUCK6";
+			};
+
+			ldo1: LDO1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-max-microvolt = <3300000>;
+				regulator-min-microvolt = <1600000>;
+				regulator-name = "LDO1";
+			};
+
+			ldo4: LDO4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-max-microvolt = <3300000>;
+				regulator-min-microvolt = <800000>;
+				regulator-name = "LDO4";
+			};
+
+			ldo5: LDO5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-max-microvolt = <3300000>;
+				regulator-min-microvolt = <1800000>;
+				regulator-name = "LDO5";
+			};
+		};
+	};
+
+	eeprom: at24c256@50 {
+		compatible = "atmel,24c256";
+		reg = <0x50>;
+		pagesize = <64>;
+	};
+};
+
+&lpi2c3 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	clock-frequency = <400000>;
+	pinctrl-0 = <&pinctrl_lpi2c3>;
+	pinctrl-names = "default";
+	status = "okay";
+	bootph-pre-ram;
+	bootph-some-ram;
+
+	ptn5110: tcpc@50 {
+		compatible = "nxp,ptn5110", "tcpci";
+		reg = <0x50>;
+		interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
+		interrupt-parent = <&gpio3>;
+		status = "okay";
+
+		typec1_con: connector {
+			compatible = "usb-c-connector";
+			data-role = "dual";
+			label = "USB-C";
+			op-sink-microwatt = <15000000>;
+			power-role = "dual";
+			self-powered;
+			sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
+				     PDO_VAR(5000, 20000, 3000)>;
+			source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+			try-power-role = "sink";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					typec1_dr_sw: endpoint {
+						remote-endpoint = <&usb1_drd_sw>;
+					};
+				};
+			};
+		};
+	};
+
+	pcf2131: rtc@53 {
+		compatible = "nxp,pcf2131";
+		reg = <0x53>;
+		interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
+		interrupt-parent = <&pcal6524>;
+		status = "okay";
+	};
+};
+
+&lpuart1 {
+	pinctrl-0 = <&pinctrl_uart1>;
+	pinctrl-names = "default";
+	status = "okay";
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&lpuart5 {
+	pinctrl-0 = <&pinctrl_uart5>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&osc_32k {
+	bootph-all;
+	bootph-pre-ram;
+};
+
+&osc_24m {
+	bootph-all;
+	bootph-pre-ram;
+};
+
+&usbotg1 {
+	adp-disable;
+	disable-over-current;
+	dr_mode = "otg";
+	hnp-disable;
+	srp-disable;
+	usb-role-switch;
+	samsung,picophy-dc-vol-level-adjust = <7>;
+	samsung,picophy-pre-emp-curr-control = <3>;
+	status = "okay";
+
+	port {
+		usb1_drd_sw: endpoint {
+			remote-endpoint = <&typec1_dr_sw>;
+		};
+	};
+};
+
+&usbotg2 {
+	disable-over-current;
+	dr_mode = "host";
+	samsung,picophy-dc-vol-level-adjust = <7>;
+	samsung,picophy-pre-emp-curr-control = <3>;
+	status = "okay";
+};
+
+&usdhc1 {
+	bus-width = <8>;
+	non-removable;
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	status = "okay";
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&usdhc2 {
+	bus-width = <4>;
+	cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
+	no-mmc;
+	no-sdio;
+	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>;
+	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+	vmmc-supply = <&reg_usdhc2_vmmc>;
+	status = "okay";
+};
+
+&wdog3 {
+	fsl,ext-reset-output;
+	status = "okay";
+};
+
+&iomuxc {
+	bootph-pre-ram;
+	bootph-some-ram;
+
+	pinctrl_eqos: eqosgrp {
+		fsl,pins = <
+			MX91_PAD_ENET1_MDC__ENET1_MDC				0x57e
+			MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO			0x57e
+			MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0			0x57e
+			MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1			0x57e
+			MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2			0x57e
+			MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3			0x57e
+			MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC	0x5fe
+			MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL		0x57e
+			MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0			0x57e
+			MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1			0x57e
+			MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2			0x57e
+			MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3			0x57e
+			MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x5fe
+			MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL		0x57e
+		>;
+	};
+
+	pinctrl_eqos_sleep: eqossleepgrp {
+		fsl,pins = <
+			MX91_PAD_ENET1_MDC__GPIO4_IO0				0x31e
+			MX91_PAD_ENET1_MDIO__GPIO4_IO1				0x31e
+			MX91_PAD_ENET1_RD0__GPIO4_IO10				0x31e
+			MX91_PAD_ENET1_RD1__GPIO4_IO11				0x31e
+			MX91_PAD_ENET1_RD2__GPIO4_IO12				0x31e
+			MX91_PAD_ENET1_RD3__GPIO4_IO13				0x31e
+			MX91_PAD_ENET1_RXC__GPIO4_IO9				0x31e
+			MX91_PAD_ENET1_RX_CTL__GPIO4_IO8			0x31e
+			MX91_PAD_ENET1_TD0__GPIO4_IO5				0x31e
+			MX91_PAD_ENET1_TD1__GPIO4_IO4				0x31e
+			MX91_PAD_ENET1_TD2__GPIO4_IO3				0x31e
+			MX91_PAD_ENET1_TD3__GPIO4_IO2				0x31e
+			MX91_PAD_ENET1_TXC__GPIO4_IO7				0x31e
+			MX91_PAD_ENET1_TX_CTL__GPIO4_IO6			0x31e
+		>;
+	};
+
+	pinctrl_fec: fecgrp {
+		fsl,pins = <
+			MX91_PAD_ENET2_MDC__ENET2_MDC			0x57e
+			MX91_PAD_ENET2_MDIO__ENET2_MDIO			0x57e
+			MX91_PAD_ENET2_RD0__ENET2_RGMII_RD0		0x57e
+			MX91_PAD_ENET2_RD1__ENET2_RGMII_RD1		0x57e
+			MX91_PAD_ENET2_RD2__ENET2_RGMII_RD2		0x57e
+			MX91_PAD_ENET2_RD3__ENET2_RGMII_RD3		0x57e
+			MX91_PAD_ENET2_RXC__ENET2_RGMII_RXC		0x5fe
+			MX91_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL	0x57e
+			MX91_PAD_ENET2_TD0__ENET2_RGMII_TD0		0x57e
+			MX91_PAD_ENET2_TD1__ENET2_RGMII_TD1		0x57e
+			MX91_PAD_ENET2_TD2__ENET2_RGMII_TD2		0x57e
+			MX91_PAD_ENET2_TD3__ENET2_RGMII_TD3		0x57e
+			MX91_PAD_ENET2_TXC__ENET2_RGMII_TXC		0x5fe
+			MX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL	0x57e
+		>;
+	};
+
+	pinctrl_fec_sleep: fecsleepgrp {
+		fsl,pins = <
+			MX91_PAD_ENET2_MDC__GPIO4_IO14			0x51e
+			MX91_PAD_ENET2_MDIO__GPIO4_IO15			0x51e
+			MX91_PAD_ENET2_RD0__GPIO4_IO24			0x51e
+			MX91_PAD_ENET2_RD1__GPIO4_IO25			0x51e
+			MX91_PAD_ENET2_RD2__GPIO4_IO26			0x51e
+			MX91_PAD_ENET2_RD3__GPIO4_IO27			0x51e
+			MX91_PAD_ENET2_RXC__GPIO4_IO23			0x51e
+			MX91_PAD_ENET2_RX_CTL__GPIO4_IO22		0x51e
+			MX91_PAD_ENET2_TD0__GPIO4_IO19			0x51e
+			MX91_PAD_ENET2_TD1__GPIO4_IO18			0x51e
+			MX91_PAD_ENET2_TD2__GPIO4_IO17			0x51e
+			MX91_PAD_ENET2_TD3__GPIO4_IO16			0x51e
+			MX91_PAD_ENET2_TXC__GPIO4_IO21			0x51e
+			MX91_PAD_ENET2_TX_CTL__GPIO4_IO20		0x51e
+		>;
+	};
+
+	pinctrl_lcdif_gpio: lcdifgpiogrp {
+		fsl,pins = <
+			MX91_PAD_GPIO_IO00__GPIO2_IO0			0x51e
+			MX91_PAD_GPIO_IO01__GPIO2_IO1			0x51e
+			MX91_PAD_GPIO_IO02__GPIO2_IO2			0x51e
+			MX91_PAD_GPIO_IO03__GPIO2_IO3			0x51e
+		>;
+	};
+
+	pinctrl_lcdif: lcdifgrp {
+		fsl,pins = <
+			MX91_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK		0x31e
+			MX91_PAD_GPIO_IO01__MEDIAMIX_DISP_DE		0x31e
+			MX91_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC		0x31e
+			MX91_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC		0x31e
+			MX91_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA0		0x31e
+			MX91_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA1		0x31e
+			MX91_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA2		0x31e
+			MX91_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA3		0x31e
+			MX91_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA4		0x31e
+			MX91_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA5		0x31e
+			MX91_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA6		0x31e
+			MX91_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA7		0x31e
+			MX91_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA8		0x31e
+			MX91_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA9		0x31e
+			MX91_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10	0x31e
+			MX91_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11	0x31e
+			MX91_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12	0x31e
+			MX91_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13	0x31e
+			MX91_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14	0x31e
+			MX91_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15	0x31e
+			MX91_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16	0x31e
+			MX91_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17	0x31e
+			MX91_PAD_GPIO_IO27__GPIO2_IO27			0x31e
+		>;
+	};
+
+	pinctrl_lpi2c1: lpi2c1grp {
+		fsl,pins = <
+			MX91_PAD_I2C1_SCL__LPI2C1_SCL			0x40000b9e
+			MX91_PAD_I2C1_SDA__LPI2C1_SDA			0x40000b9e
+		>;
+		bootph-pre-ram;
+		bootph-some-ram;
+	};
+
+	pinctrl_lpi2c2: lpi2c2grp {
+		fsl,pins = <
+			MX91_PAD_I2C2_SCL__LPI2C2_SCL			0x40000b9e
+			MX91_PAD_I2C2_SDA__LPI2C2_SDA			0x40000b9e
+		>;
+		bootph-pre-ram;
+		bootph-some-ram;
+	};
+
+	pinctrl_lpi2c3: lpi2c3grp {
+		fsl,pins = <
+			MX91_PAD_GPIO_IO28__LPI2C3_SDA			0x40000b9e
+			MX91_PAD_GPIO_IO29__LPI2C3_SCL			0x40000b9e
+		>;
+		bootph-pre-ram;
+		bootph-some-ram;
+	};
+
+	pinctrl_pcal6524: pcal6524grp {
+		fsl,pins = <
+			MX91_PAD_CCM_CLKO2__GPIO3_IO27			0x31e
+		>;
+	};
+
+	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
+		fsl,pins = <
+			MX91_PAD_SD2_RESET_B__GPIO3_IO7	0x31e
+		>;
+		bootph-pre-ram;
+	};
+
+	pinctrl_uart1: uart1grp {
+		fsl,pins = <
+			MX91_PAD_UART1_RXD__LPUART1_RX			0x31e
+			MX91_PAD_UART1_TXD__LPUART1_TX			0x31e
+		>;
+		bootph-pre-ram;
+		bootph-some-ram;
+	};
+
+	pinctrl_uart5: uart5grp {
+		fsl,pins = <
+			MX91_PAD_DAP_TDO_TRACESWO__LPUART5_TX	0x31e
+			MX91_PAD_DAP_TDI__LPUART5_RX		0x31e
+			MX91_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B	0x31e
+			MX91_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B	0x31e
+		>;
+	};
+
+	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
+		fsl,pins = <
+			MX91_PAD_SD1_CLK__USDHC1_CLK		0x158e
+			MX91_PAD_SD1_CMD__USDHC1_CMD		0x138e
+			MX91_PAD_SD1_DATA0__USDHC1_DATA0	0x138e
+			MX91_PAD_SD1_DATA1__USDHC1_DATA1	0x138e
+			MX91_PAD_SD1_DATA2__USDHC1_DATA2	0x138e
+			MX91_PAD_SD1_DATA3__USDHC1_DATA3	0x138e
+			MX91_PAD_SD1_DATA4__USDHC1_DATA4	0x138e
+			MX91_PAD_SD1_DATA5__USDHC1_DATA5	0x138e
+			MX91_PAD_SD1_DATA6__USDHC1_DATA6	0x138e
+			MX91_PAD_SD1_DATA7__USDHC1_DATA7	0x138e
+			MX91_PAD_SD1_STROBE__USDHC1_STROBE	0x158e
+		>;
+	};
+
+	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
+		fsl,pins = <
+			MX91_PAD_SD1_CLK__USDHC1_CLK		0x15fe
+			MX91_PAD_SD1_CMD__USDHC1_CMD		0x13fe
+			MX91_PAD_SD1_DATA0__USDHC1_DATA0	0x13fe
+			MX91_PAD_SD1_DATA1__USDHC1_DATA1	0x13fe
+			MX91_PAD_SD1_DATA2__USDHC1_DATA2	0x13fe
+			MX91_PAD_SD1_DATA3__USDHC1_DATA3	0x13fe
+			MX91_PAD_SD1_DATA4__USDHC1_DATA4	0x13fe
+			MX91_PAD_SD1_DATA5__USDHC1_DATA5	0x13fe
+			MX91_PAD_SD1_DATA6__USDHC1_DATA6	0x13fe
+			MX91_PAD_SD1_DATA7__USDHC1_DATA7	0x13fe
+			MX91_PAD_SD1_STROBE__USDHC1_STROBE	0x15fe
+		>;
+	};
+
+	pinctrl_usdhc1: usdhc1grp {
+		fsl,pins = <
+			MX91_PAD_SD1_CLK__USDHC1_CLK		0x1582
+			MX91_PAD_SD1_CMD__USDHC1_CMD		0x1382
+			MX91_PAD_SD1_DATA0__USDHC1_DATA0	0x1382
+			MX91_PAD_SD1_DATA1__USDHC1_DATA1	0x1382
+			MX91_PAD_SD1_DATA2__USDHC1_DATA2	0x1382
+			MX91_PAD_SD1_DATA3__USDHC1_DATA3	0x1382
+			MX91_PAD_SD1_DATA4__USDHC1_DATA4	0x1382
+			MX91_PAD_SD1_DATA5__USDHC1_DATA5	0x1382
+			MX91_PAD_SD1_DATA6__USDHC1_DATA6	0x1382
+			MX91_PAD_SD1_DATA7__USDHC1_DATA7	0x1382
+			MX91_PAD_SD1_STROBE__USDHC1_STROBE	0x1582
+		>;
+		bootph-pre-ram;
+		bootph-some-ram;
+	};
+
+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+		fsl,pins = <
+			MX91_PAD_SD2_CLK__USDHC2_CLK		0x158e
+			MX91_PAD_SD2_CMD__USDHC2_CMD		0x138e
+			MX91_PAD_SD2_DATA0__USDHC2_DATA0	0x138e
+			MX91_PAD_SD2_DATA1__USDHC2_DATA1	0x138e
+			MX91_PAD_SD2_DATA2__USDHC2_DATA2	0x138e
+			MX91_PAD_SD2_DATA3__USDHC2_DATA3	0x138e
+			MX91_PAD_SD2_VSELECT__USDHC2_VSELECT	0x51e
+		>;
+	};
+
+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+		fsl,pins = <
+			MX91_PAD_SD2_CLK__USDHC2_CLK		0x15fe
+			MX91_PAD_SD2_CMD__USDHC2_CMD		0x13fe
+			MX91_PAD_SD2_DATA0__USDHC2_DATA0	0x13fe
+			MX91_PAD_SD2_DATA1__USDHC2_DATA1	0x13fe
+			MX91_PAD_SD2_DATA2__USDHC2_DATA2	0x13fe
+			MX91_PAD_SD2_DATA3__USDHC2_DATA3	0x13fe
+			MX91_PAD_SD2_VSELECT__USDHC2_VSELECT	0x51e
+		>;
+	};
+
+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+		fsl,pins = <
+			MX91_PAD_SD2_CD_B__GPIO3_IO0		0x31e
+		>;
+		bootph-pre-ram;
+		bootph-some-ram;
+	};
+
+	pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleepgrp {
+		fsl,pins = <
+			MX91_PAD_SD2_CD_B__GPIO3_IO0		0x51e
+		>;
+	};
+
+	pinctrl_usdhc2: usdhc2grp {
+		fsl,pins = <
+			MX91_PAD_SD2_CLK__USDHC2_CLK		0x1582
+			MX91_PAD_SD2_CMD__USDHC2_CMD		0x1382
+			MX91_PAD_SD2_DATA0__USDHC2_DATA0	0x1382
+			MX91_PAD_SD2_DATA1__USDHC2_DATA1	0x1382
+			MX91_PAD_SD2_DATA2__USDHC2_DATA2	0x1382
+			MX91_PAD_SD2_DATA3__USDHC2_DATA3	0x1382
+			MX91_PAD_SD2_VSELECT__USDHC2_VSELECT	0x51e
+		>;
+		bootph-pre-ram;
+		bootph-some-ram;
+	};
+
+	pinctrl_usdhc2_sleep: usdhc2sleepgrp {
+		fsl,pins = <
+			MX91_PAD_SD2_CLK__GPIO3_IO1		0x51e
+			MX91_PAD_SD2_CMD__GPIO3_IO2		0x51e
+			MX91_PAD_SD2_DATA0__GPIO3_IO3		0x51e
+			MX91_PAD_SD2_DATA1__GPIO3_IO4		0x51e
+			MX91_PAD_SD2_DATA2__GPIO3_IO5		0x51e
+			MX91_PAD_SD2_DATA3__GPIO3_IO6		0x51e
+			MX91_PAD_SD2_VSELECT__GPIO3_IO19	0x51e
+		>;
+	};
+
+	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
+		fsl,pins = <
+			MX91_PAD_SD3_CLK__USDHC3_CLK		0x158e
+			MX91_PAD_SD3_CMD__USDHC3_CMD		0x138e
+			MX91_PAD_SD3_DATA0__USDHC3_DATA0	0x138e
+			MX91_PAD_SD3_DATA1__USDHC3_DATA1	0x138e
+			MX91_PAD_SD3_DATA2__USDHC3_DATA2	0x138e
+			MX91_PAD_SD3_DATA3__USDHC3_DATA3	0x138e
+		>;
+	};
+
+	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
+		fsl,pins = <
+			MX91_PAD_SD3_CLK__USDHC3_CLK		0x15fe
+			MX91_PAD_SD3_CMD__USDHC3_CMD		0x13fe
+			MX91_PAD_SD3_DATA0__USDHC3_DATA0	0x13fe
+			MX91_PAD_SD3_DATA1__USDHC3_DATA1	0x13fe
+			MX91_PAD_SD3_DATA2__USDHC3_DATA2	0x13fe
+			MX91_PAD_SD3_DATA3__USDHC3_DATA3	0x13fe
+		>;
+	};
+
+	pinctrl_usdhc3: usdhc3grp {
+		fsl,pins = <
+			MX91_PAD_SD3_CLK__USDHC3_CLK		0x1582
+			MX91_PAD_SD3_CMD__USDHC3_CMD		0x1382
+			MX91_PAD_SD3_DATA0__USDHC3_DATA0	0x1382
+			MX91_PAD_SD3_DATA1__USDHC3_DATA1	0x1382
+			MX91_PAD_SD3_DATA2__USDHC3_DATA2	0x1382
+			MX91_PAD_SD3_DATA3__USDHC3_DATA3	0x1382
+		>;
+	};
+
+	pinctrl_usdhc3_sleep: usdhc3sleepgrp {
+		fsl,pins = <
+			MX91_PAD_SD3_CLK__GPIO3_IO20		0x31e
+			MX91_PAD_SD3_CMD__GPIO3_IO21		0x31e
+			MX91_PAD_SD3_DATA0__GPIO3_IO22		0x31e
+			MX91_PAD_SD3_DATA1__GPIO3_IO23		0x31e
+			MX91_PAD_SD3_DATA2__GPIO3_IO24		0x31e
+			MX91_PAD_SD3_DATA3__GPIO3_IO25		0x31e
+		>;
+	};
+};

arch/arm/dts/imx93-kontron-bl-osm-s-u-boot.dtsi

@@ -0,0 +1,153 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2024 Kontron Electronics GmbH
+ */
+
+#include "imx93-u-boot.dtsi"
+
+/ {
+	wdt-reboot {
+		compatible = "wdt-reboot";
+		wdt = <&wdog3>;
+		bootph-all;
+	};
+
+	firmware {
+		optee {
+			compatible = "linaro,optee-tz";
+			method = "smc";
+		};
+	};
+};
+
+&A55_0 {
+	clocks = <&clk IMX93_CLK_ARM_PLL>;
+};
+
+&A55_1 {
+	clocks = <&clk IMX93_CLK_ARM_PLL>;
+};
+
+&{/soc@0} {
+	bootph-all;
+};
+
+&reg_vdd_carrier {
+	bootph-all;
+};
+
+&pinctrl_reg_vdd_carrier {
+	bootph-all;
+};
+
+&aips1 {
+	bootph-all;
+};
+
+&aips2 {
+	bootph-all;
+};
+
+&aips3 {
+	bootph-all;
+};
+
+&iomuxc {
+	bootph-all;
+};
+
+&pinctrl_usdhc2_gpio {
+	bootph-all;
+};
+
+&pinctrl_usdhc2 {
+	bootph-all;
+};
+
+&gpio1 {
+	bootph-all;
+};
+
+&gpio2 {
+	bootph-all;
+};
+
+&gpio3 {
+	bootph-all;
+};
+
+&gpio4 {
+	bootph-all;
+};
+
+&lpuart1 {
+	bootph-all;
+};
+
+&pinctrl_lpuart1 {
+	bootph-all;
+};
+
+&usdhc1 {
+	bootph-all;
+};
+
+&usdhc2 {
+	bootph-all;
+	fsl,signal-voltage-switch-extra-delay-ms = <8>;
+};
+
+&lpi2c1 {
+	bootph-all;
+};
+
+/* Enable I2C2 to probe for a touch controller on LVDS connector */
+&lpi2c2 {
+	bootph-all;
+	status = "okay";
+};
+
+&pca9451 {
+	bootph-all;
+};
+
+&{/soc@0/bus@44000000/i2c@44340000/pmic@25/regulators} {
+	bootph-all;
+};
+
+&pinctrl_lpi2c1 {
+	bootph-all;
+};
+
+&s4muap {
+	bootph-all;
+	status = "okay";
+};
+
+&clk {
+	bootph-all;
+};
+
+&osc_32k {
+	bootph-all;
+};
+
+&osc_24m {
+	bootph-all;
+};
+
+&clk_ext1 {
+	bootph-all;
+};
+
+&wdog3 {
+	bootph-all;
+};
+
+&reg_vdd_3v3 {
+	bootph-all;
+};
+
+&reg_nvcc_sd {
+	bootph-all;
+};

arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi

@@ -30,6 +30,22 @@
 		ethernet1 = &eqos;
 	};
 
+	bootstd {
+		bootph-verify;
+		compatible = "u-boot,boot-std";
+
+		filename-prefixes = "/", "/boot/";
+		bootdev-order = "mmc0", "mmc1", "ethernet";
+
+		rauc {
+			compatible = "u-boot,distro-rauc";
+		};
+
+		script {
+			compatible = "u-boot,script";
+		};
+	};
+
 	firmware {
 		optee {
 			compatible = "linaro,optee-tz";

arch/arm/dts/imx93-u-boot.dtsi

@@ -6,6 +6,71 @@
 / {
 	binman: binman {
 		multiple-images;
+
+		u-boot-spl-ddr {
+			align = <4>;
+			align-size = <4>;
+			filename = "u-boot-spl-ddr.bin";
+			pad-byte = <0xff>;
+
+			u-boot-spl {
+				align-end = <4>;
+				filename = "u-boot-spl.bin";
+			};
+
+			ddr-1d-imem-fw {
+				filename = "lpddr4_imem_1d_v202201.bin";
+				align-end = <4>;
+				type = "blob-ext";
+			};
+
+			ddr-1d-dmem-fw {
+				filename = "lpddr4_dmem_1d_v202201.bin";
+				align-end = <4>;
+				type = "blob-ext";
+			};
+
+			ddr-2d-imem-fw {
+				filename = "lpddr4_imem_2d_v202201.bin";
+				align-end = <4>;
+				type = "blob-ext";
+			};
+
+			ddr-2d-dmem-fw {
+				filename = "lpddr4_dmem_2d_v202201.bin";
+				align-end = <4>;
+				type = "blob-ext";
+			};
+		};
+
+		imx-boot {
+			filename = "flash.bin";
+			pad-byte = <0x00>;
+
+			spl {
+				type = "nxp-imx9image";
+				cfg-path = "spl/u-boot-spl.cfgout";
+				args;
+
+				boot-from = "sd";
+				soc-type = "IMX9";
+				append = "mx93a1-ahab-container.img";
+				container;
+				image = "a55", "u-boot-spl-ddr.bin", "0x2049A000";
+			};
+
+			u-boot {
+				type = "nxp-imx9image";
+				cfg-path = "u-boot-container.cfgout";
+				args;
+
+				boot-from = "sd";
+				soc-type = "IMX9";
+				container;
+				image0 = "a55", "bl31.bin", "0x204E0000";
+				image1 = "a55", "u-boot.bin", "0x80200000";
+			};
+		};
 	};
 };
 
@@ -17,84 +82,6 @@
 	clocks = <&clk IMX93_CLK_ARM_PLL>;
 };
 
-&binman {
-	u-boot-spl-ddr {
-		align = <4>;
-		align-size = <4>;
-		filename = "u-boot-spl-ddr.bin";
-		pad-byte = <0xff>;
-
-		u-boot-spl {
-			align-end = <4>;
-			filename = "u-boot-spl.bin";
-		};
-
-		ddr-1d-imem-fw {
-			filename = "lpddr4_imem_1d_v202201.bin";
-			align-end = <4>;
-			type = "blob-ext";
-		};
-
-		ddr-1d-dmem-fw {
-			filename = "lpddr4_dmem_1d_v202201.bin";
-			align-end = <4>;
-			type = "blob-ext";
-		};
-
-		ddr-2d-imem-fw {
-			filename = "lpddr4_imem_2d_v202201.bin";
-			align-end = <4>;
-			type = "blob-ext";
-		};
-
-		ddr-2d-dmem-fw {
-			filename = "lpddr4_dmem_2d_v202201.bin";
-			align-end = <4>;
-			type = "blob-ext";
-		};
-	};
-
-	spl {
-		filename = "spl.bin";
-
-		mkimage {
-			args = "-n spl/u-boot-spl.cfgout -T imx8image -e 0x2049A000";
-
-			blob {
-				filename = "u-boot-spl-ddr.bin";
-			};
-		};
-	};
-
-	u-boot-container {
-		filename = "u-boot-container.bin";
-
-		mkimage {
-			args = "-n u-boot-container.cfgout -T imx8image -e 0x0";
-
-			blob {
-				filename = "u-boot.bin";
-			};
-		};
-	};
-
-	imx-boot {
-		filename = "flash.bin";
-		pad-byte = <0x00>;
-
-		spl: blob-ext@1 {
-			filename = "spl.bin";
-			offset = <0x0>;
-			align-size = <0x400>;
-			align = <0x400>;
-		};
-
-		uboot: blob-ext@2 {
-			filename = "u-boot-container.bin";
-		};
-	};
-};
-
 &tmu {
 	compatible = "fsl,imx93-tmu";
 	reg = <0x44482000 0x1000>;

arch/arm/dts/imx95-u-boot.dtsi

@@ -96,6 +96,10 @@
 			};
 		};
 	};
+
+	imx95-cm7 {
+		compatible = "fsl,imx95-cm7";
+	};
 };
 
 &A55_0 {

arch/arm/dts/k3-am62-lp4-50-800-800.dtsi

@@ -1,20 +1,21 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * This file was generated with the
- * AM623/AM625 SysConfig DDR Configuration Tool for AM64x, AM625, AM623, AM62Ax, AM62Px v0.10.02
- * Tue Sep 17 2024 13:07:19 GMT+0530 (India Standard Time)
+ * AM623/AM625 SysConfig DDR Configuration Tool for AM64x, AM625, AM623, AM62Ax, AM62Px, AM62Dx, AM62Lx v0.10.32
+ * Fri Jan 30 2026 13:45:31 GMT+0530 (India Standard Time)
  * DDR Type: LPDDR4
  * F0 = 50MHz    F1 = NA     F2 = 800MHz
  * Density (per channel): 16Gb
  * Write DBI: Enable
  * Number of Ranks: 1
- */
+*/
 
 #define DDRSS_PLL_FHS_CNT 3
 #define DDRSS_PLL_FREQUENCY_1 400000000
 #define DDRSS_PLL_FREQUENCY_2 400000000
 #define DDRSS_SDRAM_IDX 15
-#define DDRSS_REGION_IDX 16
+#define DDRSS_REGION_IDX 15
+#define DDRSS_TOOL_VERSION "0.10.32"
 
 #define DDRSS_CTL_0_DATA 0x00000B00
 #define DDRSS_CTL_1_DATA 0x00000000
@@ -646,8 +647,8 @@
 #define DDRSS_PI_204_DATA 0x00C90100
 #define DDRSS_PI_205_DATA 0x010000C9
 #define DDRSS_PI_206_DATA 0x00C900C9
-#define DDRSS_PI_207_DATA 0x32103200
-#define DDRSS_PI_208_DATA 0x01013210
+#define DDRSS_PI_207_DATA 0x321E3200
+#define DDRSS_PI_208_DATA 0x0101321E
 #define DDRSS_PI_209_DATA 0x0A070601
 #define DDRSS_PI_210_DATA 0x0D09070D
 #define DDRSS_PI_211_DATA 0x0D09070D

arch/arm/dts/k3-am62-r5-lp-sk.dts

@@ -9,84 +9,4 @@
 #include "k3-am62-ddr.dtsi"
 
 #include "k3-am62-lp-sk-u-boot.dtsi"
-
-/ {
-	aliases {
-		tick-timer = &main_timer0;
-		remoteproc0 = &sysctrler;
-		remoteproc1 = &a53_0;
-		serial0 = &wkup_uart0;
-		serial3 = &main_uart1;
-	};
-
-	a53_0: a53@0 {
-		compatible = "ti,am654-rproc";
-		reg = <0x00 0x00a90000 0x00 0x10>;
-		power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
-				<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
-				<&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
-		resets = <&k3_reset 135 0>;
-		clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
-		clock-names = "gtc", "core";
-		assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
-		assigned-clock-parents = <&k3_clks 61 2>;
-		assigned-clock-rates = <200000000>, <1200000000>;
-		ti,sci = <&dmsc>;
-		ti,sci-proc-id = <32>;
-		ti,sci-host-id = <10>;
-		bootph-pre-ram;
-	};
-
-	dm_tifs: dm-tifs {
-		compatible = "ti,j721e-dm-sci";
-		ti,host-id = <36>;
-		ti,secure-host;
-		mbox-names = "rx", "tx";
-		mboxes= <&secure_proxy_main 22>,
-			<&secure_proxy_main 23>;
-		bootph-pre-ram;
-	};
-};
-
-&dmsc {
-	mboxes= <&secure_proxy_main 0>,
-		<&secure_proxy_main 1>,
-		<&secure_proxy_main 0>;
-	mbox-names = "rx", "tx", "notify";
-	ti,host-id = <35>;
-	ti,secure-host;
-};
-
-&secure_proxy_sa3 {
-	/* We require this for boot handshake */
-	status = "okay";
-};
-
-&cbass_main {
-	sysctrler: sysctrler {
-		compatible = "ti,am654-tisci-rproc-r5";
-		mboxes= <&secure_proxy_main 1>,
-			<&secure_proxy_main 0>,
-			<&secure_proxy_sa3 0>;
-		mbox-names = "tx", "rx", "boot_notify";
-		bootph-pre-ram;
-	};
-};
-
-&main_timer0 {
-	/delete-property/ clocks;
-	/delete-property/ clocks-names;
-	/delete-property/ assigned-clocks;
-	/delete-property/ assigned-clock-parents;
-	clock-frequency = <25000000>;
-};
-
-/* WKUP UART0 is used for DM firmware logs */
-&wkup_uart0 {
-	status = "okay";
-};
-
-/* Main UART1 is used for TIFS firmware logs */
-&main_uart1 {
-	status = "okay";
-};
+#include "k3-am625-r5.dtsi"

arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi

@@ -19,36 +19,16 @@
 		mmc0 = &sdhci0;
 		mmc1 = &sdhci1;
 	};
-
-	memory@80000000 {
-		bootph-all;
-	};
-};
-
-&cpsw3g {
-	bootph-all;
-};
-
-&cpsw_port1 {
-	bootph-all;
 };
 
 &cpsw_port2 {
 	status = "disabled";
 };
 
-&cpsw3g_phy1 {
-	bootph-all;
-};
-
 &phy_gmii_sel {
 	bootph-all;
 };
 
-&fss {
-	bootph-all;
-};
-
 &main_bcdma {
 	bootph-all;
 	reg = <0x00 0x485c0100 0x00 0x100>,
@@ -63,38 +43,6 @@
 		    "ringrt" , "cfg", "tchan", "rchan";
 };
 
-&main_gpio0 {
-	bootph-all;
-};
-
-&main_mdio1_pins_default {
-	bootph-all;
-};
-
-&main_i2c0 {
-	bootph-all;
-};
-
-&main_i2c0_pins_default {
-	bootph-all;
-};
-
-&main_mmc0_pins_default {
-	bootph-all;
-};
-
-&main_mmc1_pins_default {
-	bootph-all;
-};
-
-&main_pktdma {
-	bootph-all;
-};
-
-&main_rgmii1_pins_default {
-	bootph-all;
-};
-
 &main_rti1 {
 	status = "disabled";
 };
@@ -111,27 +59,8 @@
 	status = "disabled";
 };
 
-&main_uart0 {
-	bootph-all;
-};
-
-&main_uart0_pins_default {
-	bootph-all;
-};
-
-&main_uart1 {
-	bootph-all;
-};
-
-&main_uart1_pins_default {
-	bootph-all;
-};
-
 &ospi0 {
-	bootph-all;
-
 	flash@0 {
-		bootph-all;
 		partitions {
 			compatible = "fixed-partitions";
 			#address-cells = <1>;
@@ -161,43 +90,14 @@
 	};
 };
 
-&ospi0_pins_default {
-	bootph-all;
-};
-
-&sdhci0 {
-	bootph-all;
-};
-
-&sdhci1 {
-	bootph-all;
-};
-
-&usbss0 {
-	bootph-all;
-};
-
 &usb0 {
 	dr_mode = "peripheral";
-	bootph-all;
 };
 
 &usb0_phy_ctrl {
 	bootph-all;
 };
 
-&vcc_3v3_mmc {
-	bootph-all;
-};
-
-&vcc_5v0_som {
-	bootph-all;
-};
-
-&vddshv5_sdio {
-	bootph-all;
-};
-
 &wkup_uart0 {
 	bootph-all;
 };

arch/arm/dts/k3-am625-phycore-som-binman.dtsi

@@ -215,6 +215,36 @@
 		fit {
 
 			images {
+				atf {
+					ti-secure {
+						auth-in-place = <0xa02>;
+
+						firewall-1-0 {
+							insert-template = <&firewall_bg_3>;
+							id = <1>;
+							region = <0>;
+						};
+
+						firewall-1-1 {
+							insert-template = <&firewall_armv8_atf_fg>;
+							id = <1>;
+							region = <1>;
+						};
+					};
+				};
+
+				tee {
+					ti-secure {
+						auth-in-place = <0xa02>;
+
+						firewall-1-2 {
+							insert-template = <&firewall_armv8_optee_fg>;
+							id = <1>;
+							region = <2>;
+						};
+					};
+				};
+
 				tifsstub-hs {
 					description = "TIFSSTUB";
 					type = "firmware";

arch/arm/dts/k3-am625-r5-beagleplay.dts

@@ -11,70 +11,14 @@
 #include "k3-am62-ddr.dtsi"
 
 #include "k3-am625-beagleplay-u-boot.dtsi"
+#include "k3-am625-r5.dtsi"
 
-/ {
-	aliases {
-		remoteproc0 = &sysctrler;
-		remoteproc1 = &a53_0;
-	};
-
-	a53_0: a53@0 {
-		compatible = "ti,am654-rproc";
-		reg = <0x00 0x00a90000 0x00 0x10>;
-		power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
-				<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>;
-		resets = <&k3_reset 135 0>;
-		clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
-		clock-names = "gtc", "core";
-		assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
-		assigned-clock-parents = <&k3_clks 61 2>;
-		assigned-clock-rates = <200000000>, <1250000000>;
-		ti,sci = <&dmsc>;
-		ti,sci-proc-id = <32>;
-		ti,sci-host-id = <10>;
-		bootph-pre-ram;
-	};
-
-	dm_tifs: dm-tifs {
-		compatible = "ti,j721e-dm-sci";
-		ti,host-id = <36>;
-		ti,secure-host;
-		mbox-names = "rx", "tx";
-		mboxes= <&secure_proxy_main 22>,
-			<&secure_proxy_main 23>;
-		bootph-pre-ram;
-	};
-};
-
-&main_timer0 {
-	/delete-property/ clocks;
-	/delete-property/ clocks-names;
-	/delete-property/ assigned-clocks;
-	/delete-property/ assigned-clock-parents;
-	clock-frequency = <25000000>;
-};
-
-&dmsc {
-	mboxes= <&secure_proxy_main 0>,
-		<&secure_proxy_main 1>,
-		<&secure_proxy_main 0>;
-	mbox-names = "rx", "tx", "notify";
-	ti,host-id = <35>;
-	ti,secure-host;
-};
-
-&secure_proxy_sa3 {
-	/* We require this for boot handshake */
-	status = "okay";
-};
-
-&cbass_main {
-	sysctrler: sysctrler {
-		compatible = "ti,am654-tisci-rproc-r5";
-		mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&secure_proxy_sa3 0>;
-		mbox-names = "tx", "rx", "boot_notify";
-		bootph-pre-ram;
-	};
+&a53_0 {
+	power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
+			<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>;
+	assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
+	assigned-clock-parents = <&k3_clks 61 2>;
+	assigned-clock-rates = <200000000>, <1250000000>;
 };
 
 &main_pktdma {

arch/arm/dts/k3-am625-r5-phycore-som-2gb.dts

@@ -10,42 +10,9 @@
 #include "k3-am62-ddr.dtsi"
 
 #include "k3-am625-phyboard-lyra-rdk-u-boot.dtsi"
+#include "k3-am625-r5.dtsi"
 
 / {
-	aliases {
-		remoteproc0 = &sysctrler;
-		remoteproc1 = &a53_0;
-		serial0 = &wkup_uart0;
-		serial3 = &main_uart1;
-	};
-
-	a53_0: a53@0 {
-		compatible = "ti,am654-rproc";
-		reg = <0x00 0x00a90000 0x00 0x10>;
-		power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
-				<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
-				<&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
-		resets = <&k3_reset 135 0>;
-		clocks = <&k3_clks 61 0>;
-		assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
-		assigned-clock-parents = <&k3_clks 61 2>;
-		assigned-clock-rates = <200000000>, <1200000000>;
-		ti,sci = <&dmsc>;
-		ti,sci-proc-id = <32>;
-		ti,sci-host-id = <10>;
-		bootph-pre-ram;
-	};
-
-	dm_tifs: dm-tifs {
-		compatible = "ti,j721e-dm-sci";
-		ti,host-id = <36>;
-		ti,secure-host;
-		mbox-names = "rx", "tx";
-		mboxes= <&secure_proxy_main 22>,
-			<&secure_proxy_main 23>;
-		bootph-pre-ram;
-	};
-
 	memory@80000000 {
 		device_type = "memory";
 		/* 2G RAM */
@@ -54,51 +21,17 @@
 	};
 };
 
-&main_timer0 {
-	/delete-property/ clocks;
-	/delete-property/ clocks-names;
-	/delete-property/ assigned-clocks;
-	/delete-property/ assigned-clock-parents;
-	clock-frequency = <25000000>;
-};
-
-&secure_proxy_sa3 {
-	/* We require this for boot handshake */
-	status = "okay";
-};
-
-&cbass_main {
-	sysctrler: sysctrler {
-		compatible = "ti,am654-tisci-rproc-r5";
-		mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&secure_proxy_sa3 0>;
-		mbox-names = "tx", "rx", "boot_notify";
-		bootph-pre-ram;
-	};
-};
-
-&dmsc {
-	mboxes= <&secure_proxy_main 0>,
-		<&secure_proxy_main 1>,
-		<&secure_proxy_main 0>;
-	mbox-names = "rx", "tx", "notify";
-	ti,host-id = <35>;
-	ti,secure-host;
-};
-
-&main_bcdma {
-	ti,sci = <&dm_tifs>;
+&a53_0 {
+	clock-names = "gtc";
+	clocks = <&k3_clks 61 0>;
 };
 
 &main_pktdma {
 	ti,sci = <&dm_tifs>;
 };
 
-/* Main UART1 is used for TIFS firmware logs */
-&main_uart1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&main_uart1_pins_default>;
-	status = "okay";
-	bootph-pre-ram;
+&main_bcdma {
+	ti,sci = <&dm_tifs>;
 };
 
 &mcu_pmx0 {
@@ -113,11 +46,6 @@
 	};
 };
 
-&ospi0 {
-	reg = <0x00 0x0fc40000 0x00 0x100>,
-	      <0x00 0x60000000 0x00 0x08000000>;
-};
-
 /* WKUP UART0 is used for DM firmware logs */
 &wkup_uart0 {
 	pinctrl-names = "default";

arch/arm/dts/k3-am625-r5-sk.dts

@@ -9,92 +9,8 @@
 #include "k3-am62-ddr.dtsi"
 
 #include "k3-am625-sk-u-boot.dtsi"
-
-/ {
-	aliases {
-		tick-timer = &main_timer0;
-		remoteproc0 = &sysctrler;
-		remoteproc1 = &a53_0;
-		serial0 = &wkup_uart0;
-		serial3 = &main_uart1;
-	};
-
-	a53_0: a53@0 {
-		compatible = "ti,am654-rproc";
-		reg = <0x00 0x00a90000 0x00 0x10>;
-		power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
-				<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
-				<&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
-		resets = <&k3_reset 135 0>;
-		clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
-		clock-names = "gtc", "core";
-		assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
-		assigned-clock-parents = <&k3_clks 61 2>;
-		assigned-clock-rates = <200000000>, <1200000000>;
-		ti,sci = <&dmsc>;
-		ti,sci-proc-id = <32>;
-		ti,sci-host-id = <10>;
-		bootph-pre-ram;
-	};
-
-	dm_tifs: dm-tifs {
-		compatible = "ti,j721e-dm-sci";
-		ti,host-id = <36>;
-		ti,secure-host;
-		mbox-names = "rx", "tx";
-		mboxes= <&secure_proxy_main 22>,
-			<&secure_proxy_main 23>;
-		bootph-pre-ram;
-	};
-};
-
-&dmsc {
-	mboxes= <&secure_proxy_main 0>,
-		<&secure_proxy_main 1>,
-		<&secure_proxy_main 0>;
-	mbox-names = "rx", "tx", "notify";
-	ti,host-id = <35>;
-	ti,secure-host;
-};
-
-&secure_proxy_sa3 {
-	/* We require this for boot handshake */
-	status = "okay";
-};
-
-&cbass_main {
-	sysctrler: sysctrler {
-		compatible = "ti,am654-tisci-rproc-r5";
-		mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&secure_proxy_sa3 0>;
-		mbox-names = "tx", "rx", "boot_notify";
-		bootph-pre-ram;
-	};
-};
-
-&main_timer0 {
-	/delete-property/ clocks;
-	/delete-property/ clocks-names;
-	/delete-property/ assigned-clocks;
-	/delete-property/ assigned-clock-parents;
-	clock-frequency = <25000000>;
-};
-
-/* WKUP UART0 is used for DM firmware logs */
-&wkup_uart0 {
-	status = "okay";
-};
-
-/* Main UART1 is used for TIFS firmware logs */
-&main_uart1 {
-	status = "okay";
-};
-
-&ospi0 {
-	reg = <0x00 0x0fc40000 0x00 0x100>,
-	      <0x00 0x60000000 0x00 0x08000000>;
-};
+#include "k3-am625-r5.dtsi"
 
 &main_pktdma {
 	ti,sci = <&dm_tifs>;
-	bootph-all;
 };

arch/arm/dts/k3-am625-r5.dtsi

@@ -0,0 +1,88 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2026 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/ {
+	aliases {
+		tick-timer = &main_timer0;
+		remoteproc0 = &sysctrler;
+		remoteproc1 = &a53_0;
+		serial0 = &wkup_uart0;
+		serial3 = &main_uart1;
+	};
+
+	a53_0: a53@0 {
+		compatible = "ti,am654-rproc";
+		reg = <0x00 0x00a90000 0x00 0x10>;
+		power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
+				<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
+				<&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
+		resets = <&k3_reset 135 0>;
+		clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
+		clock-names = "gtc", "core";
+		assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
+		assigned-clock-parents = <&k3_clks 61 2>;
+		assigned-clock-rates = <200000000>, <1200000000>;
+		ti,sci = <&dmsc>;
+		ti,sci-proc-id = <32>;
+		ti,sci-host-id = <10>;
+		bootph-pre-ram;
+	};
+
+	dm_tifs: dm-tifs {
+		compatible = "ti,j721e-dm-sci";
+		ti,host-id = <36>;
+		ti,secure-host;
+		mbox-names = "rx", "tx";
+		mboxes= <&secure_proxy_main 22>,
+			<&secure_proxy_main 23>;
+		bootph-pre-ram;
+	};
+};
+
+&dmsc {
+	mboxes= <&secure_proxy_main 0>,
+		<&secure_proxy_main 1>,
+		<&secure_proxy_main 0>;
+	mbox-names = "rx", "tx", "notify";
+	ti,host-id = <35>;
+	ti,secure-host;
+};
+
+&secure_proxy_sa3 {
+	/* We require this for boot handshake */
+	status = "okay";
+};
+
+&cbass_main {
+	sysctrler: sysctrler {
+		compatible = "ti,am654-tisci-rproc-r5";
+		mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&secure_proxy_sa3 0>;
+		mbox-names = "tx", "rx", "boot_notify";
+		bootph-pre-ram;
+	};
+};
+
+&main_timer0 {
+	/delete-property/ clocks;
+	/delete-property/ clocks-names;
+	/delete-property/ assigned-clocks;
+	/delete-property/ assigned-clock-parents;
+	clock-frequency = <25000000>;
+};
+
+/* WKUP UART0 is used for DM firmware logs */
+&wkup_uart0 {
+	status = "okay";
+};
+
+/* Main UART1 is used for TIFS firmware logs */
+&main_uart1 {
+	status = "okay";
+};
+
+&ospi0 {
+	reg = <0x00 0x0fc40000 0x00 0x100>,
+	      <0x00 0x60000000 0x00 0x08000000>;
+};

arch/arm/dts/k3-am625-sk-binman.dtsi

@@ -275,6 +275,35 @@
 
 		fit {
 			images {
+				atf {
+					ti-secure {
+						auth-in-place = <0xa02>;
+
+						firewall-1-0 {
+							insert-template = <&firewall_bg_3>;
+							id = <1>;
+							region = <0>;
+						};
+
+						firewall-1-1 {
+							insert-template = <&firewall_armv8_atf_fg>;
+							id = <1>;
+							region = <1>;
+						};
+					};
+				};
+
+				tee {
+					ti-secure {
+						auth-in-place = <0xa02>;
+
+						firewall-1-2 {
+							insert-template = <&firewall_armv8_optee_fg>;
+							id = <1>;
+							region = <2>;
+						};
+					};
+				};
 
 				tifsstub-hs {
 					description = "TIFSSTUB";

arch/arm/dts/k3-am625-verdin-r5.dts

@@ -9,75 +9,30 @@
 #include "k3-am62-ddr.dtsi"
 
 #include "k3-am625-verdin-wifi-dev-u-boot.dtsi"
+#include "k3-am625-r5.dtsi"
 
 / {
-	a53_0: a53@0 {
-		compatible = "ti,am654-rproc";
-		reg = <0x00 0x00a90000 0x00 0x10>;
-		/*
-		 * FIXME: Currently only the SPL running on the R5 has a clock
-		 * driver. As a workaround therefore move the assigned-clock
-		 * stuff required for our ETH_25MHz_CLK from the cpsw3g_mdio
-		 * node of the regular device tree to here (last one each in
-		 * below three lines, adding a <0> as spacing for parents).
-		 */
-		assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>, <&k3_clks 157 20>;
-		assigned-clock-parents = <&k3_clks 61 2>, <0>, <&k3_clks 157 22>;
-		assigned-clock-rates = <200000000>, <800000000>, <25000000>;
-		clocks = <&k3_clks 61 0>;
-		power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
-				<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
-				<&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
-		resets = <&k3_reset 135 0>;
-		ti,sci = <&dmsc>;
-		ti,sci-host-id = <10>;
-		ti,sci-proc-id = <32>;
-		bootph-pre-ram;
-	};
-
 	aliases {
+		serial0 = &main_uart1;
+		serial1 = &wkup_uart0;
+		serial2 = &main_uart0;
+		serial3 = &mcu_uart0;
+		serial4 = &main_uart5;
 		remoteproc0 = &sysctrler;
 		remoteproc1 = &a53_0;
 	};
-
-	dm_tifs: dm-tifs {
-		compatible = "ti,j721e-dm-sci";
-		mbox-names = "rx", "tx";
-		mboxes= <&secure_proxy_main 22>,
-			<&secure_proxy_main 23>;
-		ti,host-id = <36>;
-		ti,secure-host;
-		bootph-pre-ram;
-	};
 };
 
-&cbass_main {
-	sysctrler: sysctrler {
-		compatible = "ti,am654-tisci-rproc-r5";
-		mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&secure_proxy_sa3 0>;
-		mbox-names = "tx", "rx", "boot_notify";
-		bootph-pre-ram;
-	};
-};
-
-&dmsc {
-	mboxes= <&secure_proxy_main 0>,
-		<&secure_proxy_main 1>,
-		<&secure_proxy_main 0>;
-	mbox-names = "rx", "tx", "notify";
-	ti,host-id = <35>;
-	ti,secure-host;
-};
-
-&main_timer0 {
-	/delete-property/ clocks;
-	/delete-property/ clocks-names;
-	/delete-property/ assigned-clocks;
-	/delete-property/ assigned-clock-parents;
-	clock-frequency = <25000000>;
-};
-
-&secure_proxy_sa3 {
-	/* We require this for boot handshake */
-	status = "okay";
+&a53_0 {
+	clocks = <&k3_clks 61 0>;
+	/*
+	 * FIXME: Currently only the SPL running on the R5 has a clock
+	 * driver. As a workaround therefore move the assigned-clock
+	 * stuff required for our ETH_25MHz_CLK from the cpsw3g_mdio
+	 * node of the regular device tree to here (last one each in
+	 * below three lines, adding a <0> as spacing for parents).
+	 */
+	assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>, <&k3_clks 157 20>;
+	assigned-clock-parents = <&k3_clks 61 2>, <0>, <&k3_clks 157 22>;
+	assigned-clock-rates = <200000000>, <800000000>, <25000000>;
 };

arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi

@@ -200,6 +200,36 @@
 		fit {
 
 			images {
+				atf {
+					ti-secure {
+						auth-in-place = <0xa02>;
+
+						firewall-1-0 {
+							insert-template = <&firewall_bg_3>;
+							id = <1>;
+							region = <0>;
+						};
+
+						firewall-1-1 {
+							insert-template = <&firewall_armv8_atf_fg>;
+							id = <1>;
+							region = <1>;
+						};
+					};
+				};
+
+				tee {
+					ti-secure {
+						auth-in-place = <0xa02>;
+
+						firewall-1-2 {
+							insert-template = <&firewall_armv8_optee_fg>;
+							id = <1>;
+							region = <2>;
+						};
+					};
+				};
+
 				tifsstub-hs {
 					description = "TIFSSTUB";
 					type = "firmware";

arch/arm/dts/k3-am6254atl-r5-sk.dts

@@ -11,92 +11,8 @@
 #include "k3-am62-ddr.dtsi"
 
 #include "k3-am6254atl-sk-u-boot.dtsi"
-
-/ {
-	aliases {
-		tick-timer = &main_timer0;
-		remoteproc0 = &sysctrler;
-		remoteproc1 = &a53_0;
-		serial0 = &wkup_uart0;
-		serial3 = &main_uart1;
-	};
-
-	a53_0: a53@0 {
-		compatible = "ti,am654-rproc";
-		reg = <0x00 0x00a90000 0x00 0x10>;
-		power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
-				<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
-				<&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
-		resets = <&k3_reset 135 0>;
-		clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
-		clock-names = "gtc", "core";
-		assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
-		assigned-clock-parents = <&k3_clks 61 2>;
-		assigned-clock-rates = <200000000>, <1200000000>;
-		ti,sci = <&dmsc>;
-		ti,sci-proc-id = <32>;
-		ti,sci-host-id = <10>;
-		bootph-pre-ram;
-	};
-
-	dm_tifs: dm-tifs {
-		compatible = "ti,j721e-dm-sci";
-		ti,host-id = <36>;
-		ti,secure-host;
-		mbox-names = "rx", "tx";
-		mboxes= <&secure_proxy_main 22>,
-			<&secure_proxy_main 23>;
-		bootph-pre-ram;
-	};
-};
-
-&dmsc {
-	mboxes= <&secure_proxy_main 0>,
-		<&secure_proxy_main 1>,
-		<&secure_proxy_main 0>;
-	mbox-names = "rx", "tx", "notify";
-	ti,host-id = <35>;
-	ti,secure-host;
-};
-
-&secure_proxy_sa3 {
-	/* We require this for boot handshake */
-	status = "okay";
-};
-
-&cbass_main {
-	sysctrler: sysctrler {
-		compatible = "ti,am654-tisci-rproc-r5";
-		mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&secure_proxy_sa3 0>;
-		mbox-names = "tx", "rx", "boot_notify";
-		bootph-pre-ram;
-	};
-};
-
-&main_timer0 {
-	/delete-property/ clocks;
-	/delete-property/ clocks-names;
-	/delete-property/ assigned-clocks;
-	/delete-property/ assigned-clock-parents;
-	clock-frequency = <25000000>;
-};
-
-/* WKUP UART0 is used for DM firmware logs */
-&wkup_uart0 {
-	status = "okay";
-};
-
-/* Main UART1 is used for TIFS firmware logs */
-&main_uart1 {
-	status = "okay";
-};
-
-&ospi0 {
-	reg = <0x00 0x0fc40000 0x00 0x100>,
-	      <0x00 0x60000000 0x00 0x08000000>;
-};
+#include "k3-am625-r5.dtsi"
 
 &main_pktdma {
 	ti,sci = <&dm_tifs>;
-	bootph-all;
 };

arch/arm/dts/k3-am62a-ddr-1866mhz-32bit.dtsi

@@ -1,19 +1,20 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * This file was generated with the
- * AM62Ax SysConfig DDR Configuration Tool for AM64x, AM625, AM623, AM62Ax, AM62Px v0.10.02
- * Tue Sep 17 2024 10:55:17 GMT+0530 (India Standard Time)
+ * AM62Ax SysConfig DDR Configuration Tool for AM64x, AM625, AM623, AM62Ax, AM62Px, AM62Dx, AM62Lx v0.10.32
+ * Fri Jan 30 2026 13:49:36 GMT+0530 (India Standard Time)
  * DDR Type: LPDDR4
  * F0 = 50MHz    F1 = NA     F2 = 1866MHz
  * Density (per channel): 8Gb
  * Number of Ranks: 2
- */
+*/
 
 #define DDRSS_PLL_FHS_CNT 5
 #define DDRSS_PLL_FREQUENCY_1 933000000
 #define DDRSS_PLL_FREQUENCY_2 933000000
 #define DDRSS_SDRAM_IDX 16
 #define DDRSS_REGION_IDX 17
+#define DDRSS_TOOL_VERSION "0.10.32"
 
 #define DDRSS_CTL_0_DATA 0x00000B00
 #define DDRSS_CTL_1_DATA 0x00000000
@@ -358,7 +359,7 @@
 #define DDRSS_CTL_340_DATA 0x00000000
 #define DDRSS_CTL_341_DATA 0x00000000
 #define DDRSS_CTL_342_DATA 0x00000000
-#define DDRSS_CTL_343_DATA 0x00000000
+#define DDRSS_CTL_343_DATA 0x7FFFFFFF
 #define DDRSS_CTL_344_DATA 0x00000000
 #define DDRSS_CTL_345_DATA 0x00000000
 #define DDRSS_CTL_346_DATA 0x00000000
@@ -375,14 +376,14 @@
 #define DDRSS_CTL_357_DATA 0x00000000
 #define DDRSS_CTL_358_DATA 0x00000000
 #define DDRSS_CTL_359_DATA 0x00000000
-#define DDRSS_CTL_360_DATA 0x00000000
-#define DDRSS_CTL_361_DATA 0x00000000
+#define DDRSS_CTL_360_DATA 0xFFFFFFFF
+#define DDRSS_CTL_361_DATA 0xFFFF0000
 #define DDRSS_CTL_362_DATA 0x00000000
-#define DDRSS_CTL_363_DATA 0x00000000
+#define DDRSS_CTL_363_DATA 0xFFFFFFFF
 #define DDRSS_CTL_364_DATA 0x00000000
-#define DDRSS_CTL_365_DATA 0x00000000
-#define DDRSS_CTL_366_DATA 0x00000000
-#define DDRSS_CTL_367_DATA 0x00000000
+#define DDRSS_CTL_365_DATA 0x00FFFFFF
+#define DDRSS_CTL_366_DATA 0xFFFF00FF
+#define DDRSS_CTL_367_DATA 0x0000FFFF
 #define DDRSS_CTL_368_DATA 0x00000000
 #define DDRSS_CTL_369_DATA 0x00000000
 #define DDRSS_CTL_370_DATA 0x00000000
@@ -669,8 +670,8 @@
 #define DDRSS_PI_216_DATA 0x01D40100
 #define DDRSS_PI_217_DATA 0x010001D4
 #define DDRSS_PI_218_DATA 0x01D401D4
-#define DDRSS_PI_219_DATA 0x32103200
-#define DDRSS_PI_220_DATA 0x01013210
+#define DDRSS_PI_219_DATA 0x200B3200
+#define DDRSS_PI_220_DATA 0x0101200B
 #define DDRSS_PI_221_DATA 0x0A070601
 #define DDRSS_PI_222_DATA 0x1C11090D
 #define DDRSS_PI_223_DATA 0x1C110913

arch/arm/dts/k3-am62a-phycore-som-binman.dtsi

@@ -165,6 +165,36 @@
 
 		fit {
 			images {
+				atf {
+					ti-secure {
+						auth-in-place = <0xa02>;
+
+						firewall-1-0 {
+							insert-template = <&firewall_bg_3>;
+							id = <1>;
+							region = <0>;
+						};
+
+						firewall-1-1 {
+							insert-template = <&firewall_armv8_atf_fg>;
+							id = <1>;
+							region = <1>;
+						};
+					};
+				};
+
+				tee {
+					ti-secure {
+						auth-in-place = <0xa02>;
+
+						firewall-1-2 {
+							insert-template = <&firewall_armv8_optee_fg>;
+							id = <1>;
+							region = <2>;
+						};
+					};
+				};
+
 				tifsstub-hs {
 					description = "TIFSSTUB";
 					type = "firmware";

arch/arm/dts/k3-am62a-sk-binman.dtsi

@@ -200,6 +200,36 @@
 
 		fit {
 			images {
+				atf {
+					ti-secure {
+						auth-in-place = <0xa02>;
+
+						firewall-1-0 {
+							insert-template = <&firewall_bg_3>;
+							id = <1>;
+							region = <0>;
+						};
+
+						firewall-1-1 {
+							insert-template = <&firewall_armv8_atf_fg>;
+							id = <1>;
+							region = <1>;
+						};
+					};
+				};
+
+				tee {
+					ti-secure {
+						auth-in-place = <0xa02>;
+
+						firewall-1-2 {
+							insert-template = <&firewall_armv8_optee_fg>;
+							id = <1>;
+							region = <2>;
+						};
+					};
+				};
+
 				tifsstub-hs {
 					description = "TIFSSTUB";
 					type = "firmware";

arch/arm/dts/k3-am62a7-r5-phycore-som-2gb.dts

@@ -13,48 +13,18 @@
 #include "k3-am62a-ddr.dtsi"
 
 #include "k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi"
+#include "k3-am62a7-r5.dtsi"
 
 / {
 	aliases {
-		remoteproc0 = &sysctrler;
-		remoteproc1 = &a53_0;
 		serial0 = &wkup_uart0;
 		serial3 = &main_uart1;
 	};
+};
 
-	a53_0: a53@0 {
-		compatible = "ti,am654-rproc";
-		reg = <0x00 0x00a90000 0x00 0x10>;
-		power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
-				<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
-				<&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
-		resets = <&k3_reset 135 0>;
-		clocks = <&k3_clks 61 0>;
-		assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
-		assigned-clock-parents = <&k3_clks 61 2>;
-		assigned-clock-rates = <200000000>, <1200000000>;
-		ti,sci = <&dmsc>;
-		ti,sci-proc-id = <32>;
-		ti,sci-host-id = <10>;
-		bootph-pre-ram;
-	};
-
-	dm_tifs: dm-tifs {
-		compatible = "ti,j721e-dm-sci";
-		ti,host-id = <36>;
-		ti,secure-host;
-		mbox-names = "rx", "tx";
-		mboxes= <&secure_proxy_main 22>,
-			<&secure_proxy_main 23>;
-		bootph-pre-ram;
-	};
-
-	memory@80000000 {
-		device_type = "memory";
-		/* 2G RAM */
-		reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
-		bootph-pre-ram;
-	};
+&a53_0 {
+	clocks = <&k3_clks 61 0>;
+	clock-names = "gtc";
 };
 
 &cbass_main {
@@ -79,24 +49,6 @@
 	};
 };
 
-&dmsc {
-	mboxes= <&secure_proxy_main 0>,
-		<&secure_proxy_main 1>,
-		<&secure_proxy_main 0>;
-	mbox-names = "rx", "tx", "notify";
-	ti,host-id = <35>;
-	ti,secure-host;
-};
-
-&main_timer0 {
-	/delete-property/ clocks;
-	/delete-property/ clocks-names;
-	/delete-property/ assigned-clocks;
-	/delete-property/ assigned-clock-parents;
-	clock-frequency = <25000000>;
-	bootph-pre-ram;
-};
-
 &main_bcdma {
 	ti,sci = <&dm_tifs>;
 };

arch/arm/dts/k3-am62a7-r5-sk.dts

@@ -9,50 +9,12 @@
 #include "k3-am62a-ddr.dtsi"
 
 #include "k3-am62a7-sk-u-boot.dtsi"
+#include "k3-am62a7-r5.dtsi"
 
 / {
 	aliases {
 		tick-timer = &main_timer0;
-		remoteproc0 = &sysctrler;
-		remoteproc1 = &a53_0;
 	};
-
-	a53_0: a53@0 {
-		compatible = "ti,am654-rproc";
-		reg = <0x00 0x00a90000 0x00 0x10>;
-		power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
-				<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
-				<&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
-		resets = <&k3_reset 135 0>;
-		clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
-		clock-names = "gtc", "core";
-		assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
-		assigned-clock-parents = <&k3_clks 61 2>;
-		assigned-clock-rates = <200000000>, <1200000000>;
-		ti,sci = <&dmsc>;
-		ti,sci-proc-id = <32>;
-		ti,sci-host-id = <10>;
-		bootph-pre-ram;
-	};
-
-	dm_tifs: dm-tifs {
-		compatible = "ti,j721e-dm-sci";
-		ti,host-id = <36>;
-		ti,secure-host;
-		mbox-names = "rx", "tx";
-		mboxes= <&secure_proxy_main 22>,
-			<&secure_proxy_main 23>;
-		bootph-pre-ram;
-	};
-};
-
-&dmsc {
-	mboxes= <&secure_proxy_main 0>,
-		<&secure_proxy_main 1>,
-		<&secure_proxy_main 0>;
-	mbox-names = "rx", "tx", "notify";
-	ti,host-id = <35>;
-	ti,secure-host;
 };
 
 &secure_proxy_sa3 {
@@ -61,26 +23,6 @@
 	bootph-pre-ram;
 };
 
-&cbass_main {
-	sysctrler: sysctrler {
-		compatible = "ti,am654-tisci-rproc-r5";
-		mboxes= <&secure_proxy_main 1>,
-			<&secure_proxy_main 0>,
-			<&secure_proxy_sa3 0>;
-		mbox-names = "tx", "rx", "boot_notify";
-		bootph-pre-ram;
-	};
-};
-
-&main_timer0 {
-	/delete-property/ clocks;
-	/delete-property/ clocks-names;
-	/delete-property/ assigned-clocks;
-	/delete-property/ assigned-clock-parents;
-	clock-frequency = <25000000>;
-	bootph-pre-ram;
-};
-
 &wkup_uart0_pins_default {
 	bootph-pre-ram;
 };

arch/arm/dts/k3-am62a7-r5.dtsi

@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2026 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/ {
+	aliases {
+		remoteproc0 = &sysctrler;
+		remoteproc1 = &a53_0;
+	};
+
+	a53_0: a53@0 {
+		compatible = "ti,am654-rproc";
+		reg = <0x00 0x00a90000 0x00 0x10>;
+		power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
+				<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
+				<&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
+		resets = <&k3_reset 135 0>;
+		clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
+		clock-names = "gtc", "core";
+		assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
+		assigned-clock-parents = <&k3_clks 61 2>;
+		assigned-clock-rates = <200000000>, <1200000000>;
+		ti,sci = <&dmsc>;
+		ti,sci-proc-id = <32>;
+		ti,sci-host-id = <10>;
+		bootph-pre-ram;
+	};
+
+	dm_tifs: dm-tifs {
+		compatible = "ti,j721e-dm-sci";
+		ti,host-id = <36>;
+		ti,secure-host;
+		mbox-names = "rx", "tx";
+		mboxes= <&secure_proxy_main 22>,
+			<&secure_proxy_main 23>;
+		bootph-pre-ram;
+	};
+
+};
+
+&dmsc {
+	mboxes= <&secure_proxy_main 0>,
+		<&secure_proxy_main 1>,
+		<&secure_proxy_main 0>;
+	mbox-names = "rx", "tx", "notify";
+	ti,host-id = <35>;
+	ti,secure-host;
+};
+
+&cbass_main {
+	sysctrler: sysctrler {
+		compatible = "ti,am654-tisci-rproc-r5";
+		mboxes= <&secure_proxy_main 1>,
+			<&secure_proxy_main 0>,
+			<&secure_proxy_sa3 0>;
+		mbox-names = "tx", "rx", "boot_notify";
+		bootph-pre-ram;
+	};
+};
+
+&main_timer0 {
+	/delete-property/ clocks;
+	/delete-property/ clocks-names;
+	/delete-property/ assigned-clocks;
+	/delete-property/ assigned-clock-parents;
+	clock-frequency = <25000000>;
+	bootph-pre-ram;
+};

arch/arm/dts/k3-am62d-evm-binman.dtsi

@@ -3,7 +3,6 @@
  * Copyright (C) 2024-2025 Texas Instruments Incorporated - https://www.ti.com/
  */
 
-#include "k3-binman.dtsi"
 #include "k3-am62a-sk-binman.dtsi"
 
 #ifdef CONFIG_TARGET_AM62D2_R5_EVM
@@ -72,7 +71,7 @@
 	description = "k3-am62d2-evm";
 
 	ti-secure {
-		content = <&spl_am62a7_sk_dtb>;
+		content = <&spl_am62d2_evm_dtb>;
 		keyfile = "custMpk.pem";
 	};
 
@@ -101,4 +100,12 @@
 	description = "k3-am62d2-evm";
 };
 
+&dm_falcon {
+	filename = "ti-dm/am62dxx/ipc_echo_testb_mcu1_0_release_strip.xer5f";
+};
+
+&dm {
+	filename = "ti-dm/am62dxx/ipc_echo_testb_mcu1_0_release_strip.xer5f";
+};
+
 #endif

arch/arm/dts/k3-am62d2-r5-evm.dts

@@ -9,74 +9,4 @@
 #include "k3-am62a-ddr.dtsi"
 
 #include "k3-am62d2-evm-u-boot.dtsi"
-
-/ {
-	aliases {
-		tick-timer = &main_timer0;
-		remoteproc0 = &sysctrler;
-		remoteproc1 = &a53_0;
-	};
-
-	a53_0: a53@0 {
-		compatible = "ti,am654-rproc";
-		reg = <0x00 0x00a90000 0x00 0x10>;
-		power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
-				<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
-				<&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
-		resets = <&k3_reset 135 0>;
-		clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
-		clock-names = "gtc", "core";
-		assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
-		assigned-clock-parents = <&k3_clks 61 2>;
-		assigned-clock-rates = <200000000>, <1200000000>;
-		ti,sci = <&dmsc>;
-		ti,sci-proc-id = <32>;
-		ti,sci-host-id = <10>;
-		bootph-pre-ram;
-	};
-
-	dm_tifs: dm-tifs {
-		compatible = "ti,j721e-dm-sci";
-		ti,host-id = <36>;
-		ti,secure-host;
-		mbox-names = "rx", "tx";
-		mboxes= <&secure_proxy_main 22>,
-			<&secure_proxy_main 23>;
-		bootph-pre-ram;
-	};
-};
-
-&dmsc {
-	mboxes= <&secure_proxy_main 0>,
-		<&secure_proxy_main 1>,
-		<&secure_proxy_main 0>;
-	mbox-names = "rx", "tx", "notify";
-	ti,host-id = <35>;
-	ti,secure-host;
-};
-
-&secure_proxy_sa3 {
-	/* Needed for initial handshake with ROM */
-	status = "okay";
-	bootph-pre-ram;
-};
-
-&cbass_main {
-	sysctrler: sysctrler {
-		compatible = "ti,am654-tisci-rproc-r5";
-		mboxes= <&secure_proxy_main 1>,
-			<&secure_proxy_main 0>,
-			<&secure_proxy_sa3 0>;
-		mbox-names = "tx", "rx", "boot_notify";
-		bootph-pre-ram;
-	};
-};
-
-&main_timer0 {
-	/delete-property/ clocks;
-	/delete-property/ clocks-names;
-	/delete-property/ assigned-clocks;
-	/delete-property/ assigned-clock-parents;
-	clock-frequency = <25000000>;
-	bootph-pre-ram;
-};
+#include "k3-am62d2-r5.dtsi"

arch/arm/dts/k3-am62d2-r5.dtsi

@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2026 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/ {
+	aliases {
+		tick-timer = &main_timer0;
+		remoteproc0 = &sysctrler;
+		remoteproc1 = &a53_0;
+	};
+
+	a53_0: a53@0 {
+		compatible = "ti,am654-rproc";
+		reg = <0x00 0x00a90000 0x00 0x10>;
+		power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
+				<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
+				<&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
+		resets = <&k3_reset 135 0>;
+		clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
+		clock-names = "gtc", "core";
+		assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
+		assigned-clock-parents = <&k3_clks 61 2>;
+		assigned-clock-rates = <200000000>, <1200000000>;
+		ti,sci = <&dmsc>;
+		ti,sci-proc-id = <32>;
+		ti,sci-host-id = <10>;
+		bootph-pre-ram;
+	};
+
+	dm_tifs: dm-tifs {
+		compatible = "ti,j721e-dm-sci";
+		ti,host-id = <36>;
+		ti,secure-host;
+		mbox-names = "rx", "tx";
+		mboxes= <&secure_proxy_main 22>,
+			<&secure_proxy_main 23>;
+		bootph-pre-ram;
+	};
+};
+
+&dmsc {
+	mboxes= <&secure_proxy_main 0>,
+		<&secure_proxy_main 1>,
+		<&secure_proxy_main 0>;
+	mbox-names = "rx", "tx", "notify";
+	ti,host-id = <35>;
+	ti,secure-host;
+};
+
+&secure_proxy_sa3 {
+	/* Needed for initial handshake with ROM */
+	status = "okay";
+	bootph-pre-ram;
+};
+
+&cbass_main {
+	sysctrler: sysctrler {
+		compatible = "ti,am654-tisci-rproc-r5";
+		mboxes= <&secure_proxy_main 1>,
+			<&secure_proxy_main 0>,
+			<&secure_proxy_sa3 0>;
+		mbox-names = "tx", "rx", "boot_notify";
+		bootph-pre-ram;
+	};
+};
+
+&main_timer0 {
+	/delete-property/ clocks;
+	/delete-property/ clocks-names;
+	/delete-property/ assigned-clocks;
+	/delete-property/ assigned-clock-parents;
+	clock-frequency = <25000000>;
+	bootph-pre-ram;
+};

arch/arm/dts/k3-am62p-ddr-lp4-50-1600.dtsi

@@ -1,19 +1,20 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * This file was generated with the
- * AM62Px SysConfig DDR Configuration Tool for AM64x, AM625, AM623, AM62Ax, AM62Px v0.10.02
- * Tue Sep 17 2024 11:03:07 GMT+0530 (India Standard Time)
+ * AM62Px SysConfig DDR Configuration Tool for AM64x, AM625, AM623, AM62Ax, AM62Px, AM62Dx, AM62Lx v0.10.32
+ * Fri Jan 30 2026 13:50:37 GMT+0530 (India Standard Time)
  * DDR Type: LPDDR4
  * F0 = 50MHz    F1 = NA     F2 = 1600MHz
  * Density (per channel): 16Gb
  * Number of Ranks: 2
- */
+*/
 
 #define DDRSS_PLL_FHS_CNT 5
 #define DDRSS_PLL_FREQUENCY_1 800000000
 #define DDRSS_PLL_FREQUENCY_2 800000000
 #define DDRSS_SDRAM_IDX 17
 #define DDRSS_REGION_IDX 17
+#define DDRSS_TOOL_VERSION "0.10.32"
 
 #define DDRSS_CTL_0_DATA 0x00000B00
 #define DDRSS_CTL_1_DATA 0x00000000
@@ -358,7 +359,7 @@
 #define DDRSS_CTL_340_DATA 0x00000000
 #define DDRSS_CTL_341_DATA 0x00000000
 #define DDRSS_CTL_342_DATA 0x00000000
-#define DDRSS_CTL_343_DATA 0x00000000
+#define DDRSS_CTL_343_DATA 0x7FFFFFFF
 #define DDRSS_CTL_344_DATA 0x00000000
 #define DDRSS_CTL_345_DATA 0x00000000
 #define DDRSS_CTL_346_DATA 0x00000000
@@ -375,14 +376,14 @@
 #define DDRSS_CTL_357_DATA 0x00000000
 #define DDRSS_CTL_358_DATA 0x00000000
 #define DDRSS_CTL_359_DATA 0x00000000
-#define DDRSS_CTL_360_DATA 0x00000000
-#define DDRSS_CTL_361_DATA 0x00000000
+#define DDRSS_CTL_360_DATA 0xFFFFFFFF
+#define DDRSS_CTL_361_DATA 0xFFFF0000
 #define DDRSS_CTL_362_DATA 0x00000000
-#define DDRSS_CTL_363_DATA 0x00000000
+#define DDRSS_CTL_363_DATA 0xFFFFFFFF
 #define DDRSS_CTL_364_DATA 0x00000000
-#define DDRSS_CTL_365_DATA 0x00000000
-#define DDRSS_CTL_366_DATA 0x00000000
-#define DDRSS_CTL_367_DATA 0x00000000
+#define DDRSS_CTL_365_DATA 0x00FFFFFF
+#define DDRSS_CTL_366_DATA 0xFFFF00FF
+#define DDRSS_CTL_367_DATA 0x0000FFFF
 #define DDRSS_CTL_368_DATA 0x00000000
 #define DDRSS_CTL_369_DATA 0x00000000
 #define DDRSS_CTL_370_DATA 0x00000000
@@ -669,8 +670,8 @@
 #define DDRSS_PI_216_DATA 0x01910100
 #define DDRSS_PI_217_DATA 0x01000191
 #define DDRSS_PI_218_DATA 0x01910191
-#define DDRSS_PI_219_DATA 0x32103200
-#define DDRSS_PI_220_DATA 0x01013210
+#define DDRSS_PI_219_DATA 0x301B3200
+#define DDRSS_PI_220_DATA 0x0101301B
 #define DDRSS_PI_221_DATA 0x0A070601
 #define DDRSS_PI_222_DATA 0x180F090D
 #define DDRSS_PI_223_DATA 0x180F0911

arch/arm/dts/k3-am62p-sk-binman.dtsi

@@ -217,6 +217,38 @@
 
 		fit {
 			images {
+				atf {
+					ti-secure {
+						auth-in-place = <0xa02>;
+
+						firewall-1-0 {
+							insert-template = <&firewall_bg_3>;
+							id = <1>;
+							region = <0>;
+						};
+
+						firewall-1-1 {
+							insert-template = <&firewall_armv8_atf_fg>;
+							id = <1>;
+							region = <1>;
+						};
+
+					};
+				};
+
+				tee {
+					ti-secure {
+						auth-in-place = <0xa02>;
+
+						firewall-1-2 {
+							insert-template = <&firewall_armv8_optee_fg>;
+							id = <1>;
+							region = <2>;
+						};
+
+					};
+				};
+
 				tifsstub-hs {
 					description = "TIFSSTUB";
 					type = "firmware";

arch/arm/dts/k3-am62p5-r5-sk.dts

@@ -9,81 +9,14 @@
 
 #include "k3-am62p-ddr-lp4-50-1600.dtsi"
 #include "k3-am62a-ddr.dtsi"
+#include "k3-am62p5-r5.dtsi"
 
 / {
 	aliases {
-		remoteproc0 = &sysctrler;
-		remoteproc1 = &a53_0;
 		serial0 = &wkup_uart0;
 		serial2 = &main_uart0;
 		serial3 = &main_uart1;
 	};
-
-	a53_0: a53@0 {
-		compatible = "ti,am654-rproc";
-		reg = <0x00 0x00a90000 0x00 0x10>;
-		power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
-			<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
-			<&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
-		resets = <&k3_reset 135 0>;
-		clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
-		clock-names = "gtc", "core";
-		assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
-		assigned-clock-parents = <&k3_clks 61 2>;
-		assigned-clock-rates = <200000000>, <1200000000>;
-		ti,sci = <&dmsc>;
-		ti,sci-proc-id = <32>;
-		ti,sci-host-id = <10>;
-		bootph-all;
-	};
-
-	dm_tifs: dm-tifs {
-		compatible = "ti,j721e-dm-sci";
-		ti,host-id = <36>;
-		ti,secure-host;
-		mbox-names = "rx", "tx";
-		mboxes= <&secure_proxy_main 20>,
-			<&secure_proxy_main 21>;
-		bootph-all;
-	};
-};
-
-&dmsc {
-	mboxes= <&secure_proxy_main 0>,
-		<&secure_proxy_main 1>,
-		<&secure_proxy_main 0>;
-	mbox-names = "rx", "tx", "notify";
-	ti,host-id = <35>;
-	ti,secure-host;
-};
-
-&cbass_main {
-	sa3_secproxy: secproxy@44880000 {
-		compatible = "ti,am654-secure-proxy";
-		#mbox-cells = <1>;
-		reg = <0x00 0x44880000 0x00 0x20000>,
-		      <0x00 0x44860000 0x00 0x20000>,
-		      <0x00 0x43600000 0x00 0x10000>;
-		reg-names = "rt", "scfg", "target_data";
-		bootph-all;
-	};
-
-	sysctrler: sysctrler {
-		compatible = "ti,am654-tisci-rproc-r5";
-		mboxes= <&secure_proxy_main 1>,
-			<&secure_proxy_main 0>,
-			<&sa3_secproxy 0>;
-		mbox-names = "tx", "rx", "boot_notify";
-		bootph-all;
-	};
-};
-
-&main_timer0 {
-	/delete-property/ clocks;
-	/delete-property/ clocks-names;
-	/delete-property/ assigned-clocks;
-	/delete-property/ assigned-clock-parents;
-	clock-frequency = <25000000>;
 };
 
 /* WKUP UART0 is used for DM firmware logs */

arch/arm/dts/k3-am62p5-r5.dtsi

@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2026 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/ {
+	aliases {
+		remoteproc0 = &sysctrler;
+		remoteproc1 = &a53_0;
+	};
+
+	a53_0: a53@0 {
+		compatible = "ti,am654-rproc";
+		reg = <0x00 0x00a90000 0x00 0x10>;
+		power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
+			<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
+			<&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
+		resets = <&k3_reset 135 0>;
+		clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
+		clock-names = "gtc", "core";
+		assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
+		assigned-clock-parents = <&k3_clks 61 2>;
+		assigned-clock-rates = <200000000>, <1200000000>;
+		ti,sci = <&dmsc>;
+		ti,sci-proc-id = <32>;
+		ti,sci-host-id = <10>;
+		bootph-all;
+	};
+
+	dm_tifs: dm-tifs {
+		compatible = "ti,j721e-dm-sci";
+		ti,host-id = <36>;
+		ti,secure-host;
+		mbox-names = "rx", "tx";
+		mboxes= <&secure_proxy_main 20>,
+			<&secure_proxy_main 21>;
+		bootph-all;
+	};
+};
+
+&cbass_main {
+	sa3_secproxy: secproxy@44880000 {
+		compatible = "ti,am654-secure-proxy";
+		#mbox-cells = <1>;
+		reg = <0x00 0x44880000 0x00 0x20000>,
+		      <0x00 0x44860000 0x00 0x20000>,
+		      <0x00 0x43600000 0x00 0x10000>;
+		reg-names = "rt", "scfg", "target_data";
+		bootph-all;
+	};
+
+	sysctrler: sysctrler {
+		compatible = "ti,am654-tisci-rproc-r5";
+		mboxes= <&secure_proxy_main 1>,
+			<&secure_proxy_main 0>,
+			<&sa3_secproxy 0>;
+		mbox-names = "tx", "rx", "boot_notify";
+		bootph-all;
+	};
+};
+
+&dmsc {
+	mboxes= <&secure_proxy_main 0>,
+		<&secure_proxy_main 1>,
+		<&secure_proxy_main 0>;
+	mbox-names = "rx", "tx", "notify";
+	ti,host-id = <35>;
+	ti,secure-host;
+};
+
+&main_timer0 {
+	/delete-property/ clocks;
+	/delete-property/ clocks-names;
+	/delete-property/ assigned-clocks;
+	/delete-property/ assigned-clock-parents;
+	clock-frequency = <25000000>;
+};

arch/arm/dts/k3-am62p5-verdin-r5.dts

@@ -9,76 +9,10 @@
 #include "k3-am62a-ddr.dtsi"
 
 #include "k3-am62p5-verdin-wifi-dev-u-boot.dtsi"
+#include "k3-am62p5-r5.dtsi"
 
-/ {
-	aliases {
-		remoteproc0 = &sysctrler;
-		remoteproc1 = &a53_0;
-	};
-
-	a53_0: a53@0 {
-		compatible = "ti,am654-rproc";
-		reg = <0x00 0x00a90000 0x00 0x10>;
-		power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
-			<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
-			<&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
-		resets = <&k3_reset 135 0>;
-		clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
-		clock-names = "gtc", "core";
-		assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>, <&k3_clks 157 36>;
-		assigned-clock-parents = <&k3_clks 61 2>, <0>, <&k3_clks 157 38>;
-		assigned-clock-rates = <200000000>, <1200000000>, <25000000>;
-		ti,sci = <&dmsc>;
-		ti,sci-proc-id = <32>;
-		ti,sci-host-id = <10>;
-		bootph-all;
-	};
-
-	dm_tifs: dm-tifs {
-		compatible = "ti,j721e-dm-sci";
-		ti,host-id = <36>;
-		ti,secure-host;
-		mbox-names = "rx", "tx";
-		mboxes= <&secure_proxy_main 20>,
-			<&secure_proxy_main 21>;
-		bootph-all;
-	};
-};
-
-&cbass_main {
-	sa3_secproxy: secproxy@44880000 {
-		compatible = "ti,am654-secure-proxy";
-		#mbox-cells = <1>;
-		reg = <0x00 0x44880000 0x00 0x20000>,
-		      <0x00 0x44860000 0x00 0x20000>,
-		      <0x00 0x43600000 0x00 0x10000>;
-		reg-names = "rt", "scfg", "target_data";
-		bootph-all;
-	};
-
-	sysctrler: sysctrler {
-		compatible = "ti,am654-tisci-rproc-r5";
-		mboxes= <&secure_proxy_main 1>,
-			<&secure_proxy_main 0>,
-			<&sa3_secproxy 0>;
-		mbox-names = "tx", "rx", "boot_notify";
-		bootph-all;
-	};
-};
-
-&dmsc {
-	mboxes= <&secure_proxy_main 0>,
-		<&secure_proxy_main 1>,
-		<&secure_proxy_main 0>;
-	mbox-names = "rx", "tx", "notify";
-	ti,host-id = <35>;
-	ti,secure-host;
-};
-
-&main_timer0 {
-	/delete-property/ clocks;
-	/delete-property/ clocks-names;
-	/delete-property/ assigned-clocks;
-	/delete-property/ assigned-clock-parents;
-	clock-frequency = <25000000>;
+&a53_0 {
+	assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>, <&k3_clks 157 36>;
+	assigned-clock-parents = <&k3_clks 61 2>, <0>, <&k3_clks 157 38>;
+	assigned-clock-rates = <200000000>, <1200000000>, <25000000>;
 };

arch/arm/dts/k3-am62p5-verdin-wifi-dev-binman.dtsi

@@ -159,6 +159,38 @@
 
 		fit {
 			images {
+				atf {
+					ti-secure {
+						auth-in-place = <0xa02>;
+
+						firewall-1-0 {
+							insert-template = <&firewall_bg_3>;
+							id = <1>;
+							region = <0>;
+						};
+
+						firewall-1-1 {
+							insert-template = <&firewall_armv8_atf_fg>;
+							id = <1>;
+							region = <1>;
+						};
+
+					};
+				};
+
+				tee {
+					ti-secure {
+						auth-in-place = <0xa02>;
+
+						firewall-1-2 {
+							insert-template = <&firewall_armv8_optee_fg>;
+							id = <1>;
+							region = <2>;
+						};
+
+					};
+				};
+
 				tifsstub-hs {
 					description = "TIFSSTUB";
 					type = "firmware";

arch/arm/dts/k3-am62x-sk-ddr4-1600MTs.dtsi

@@ -1,19 +1,20 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * This file was generated with the
- * AM623/AM625 SysConfig DDR Configuration Tool for AM64x, AM625, AM623, AM62Ax, AM62Px v0.10.02
- * Tue Sep 17 2024 11:00:17 GMT+0530 (India Standard Time)
+ * AM623/AM625 SysConfig DDR Configuration Tool for AM64x, AM625, AM623, AM62Ax, AM62Px, AM62Dx, AM62Lx v0.10.32
+ * Fri Jan 30 2026 13:45:31 GMT+0530 (India Standard Time)
  * DDR Type: DDR4
  * Frequency = 800MHz (1600MTs)
  * Density: 16Gb
  * Number of Ranks: 1
- */
+*/
 
 #define DDRSS_PLL_FHS_CNT 6
 #define DDRSS_PLL_FREQUENCY_1 400000000
 #define DDRSS_PLL_FREQUENCY_2 400000000
 #define DDRSS_SDRAM_IDX 15
-#define DDRSS_REGION_IDX 17
+#define DDRSS_REGION_IDX 16
+#define DDRSS_TOOL_VERSION "0.10.32"
 
 #define DDRSS_CTL_0_DATA 0x00000A00
 #define DDRSS_CTL_1_DATA 0x00000000
@@ -53,12 +54,12 @@
 #define DDRSS_CTL_35_DATA 0x00000000
 #define DDRSS_CTL_36_DATA 0x00000000
 #define DDRSS_CTL_37_DATA 0x00000000
-#define DDRSS_CTL_38_DATA 0x0400091C
-#define DDRSS_CTL_39_DATA 0x1C1C1C1C
-#define DDRSS_CTL_40_DATA 0x0400091C
-#define DDRSS_CTL_41_DATA 0x1C1C1C1C
-#define DDRSS_CTL_42_DATA 0x0400091C
-#define DDRSS_CTL_43_DATA 0x1C1C1C1C
+#define DDRSS_CTL_38_DATA 0x0000091C
+#define DDRSS_CTL_39_DATA 0x18181818
+#define DDRSS_CTL_40_DATA 0x0000091C
+#define DDRSS_CTL_41_DATA 0x18181818
+#define DDRSS_CTL_42_DATA 0x0000091C
+#define DDRSS_CTL_43_DATA 0x18181818
 #define DDRSS_CTL_44_DATA 0x05050404
 #define DDRSS_CTL_45_DATA 0x00002706
 #define DDRSS_CTL_46_DATA 0x0602001D
@@ -71,13 +72,13 @@
 #define DDRSS_CTL_53_DATA 0x07001D0B
 #define DDRSS_CTL_54_DATA 0x00180807
 #define DDRSS_CTL_55_DATA 0x0400DB60
-#define DDRSS_CTL_56_DATA 0x07070009
+#define DDRSS_CTL_56_DATA 0x07070005
 #define DDRSS_CTL_57_DATA 0x00001808
 #define DDRSS_CTL_58_DATA 0x0400DB60
-#define DDRSS_CTL_59_DATA 0x07070009
+#define DDRSS_CTL_59_DATA 0x07070005
 #define DDRSS_CTL_60_DATA 0x00001808
 #define DDRSS_CTL_61_DATA 0x0400DB60
-#define DDRSS_CTL_62_DATA 0x03000009
+#define DDRSS_CTL_62_DATA 0x03000005
 #define DDRSS_CTL_63_DATA 0x0D0C0002
 #define DDRSS_CTL_64_DATA 0x0D0C0D0C
 #define DDRSS_CTL_65_DATA 0x01010000
@@ -102,8 +103,8 @@
 #define DDRSS_CTL_84_DATA 0x00000000
 #define DDRSS_CTL_85_DATA 0x00000000
 #define DDRSS_CTL_86_DATA 0x00000000
-#define DDRSS_CTL_87_DATA 0x00090009
-#define DDRSS_CTL_88_DATA 0x00000009
+#define DDRSS_CTL_87_DATA 0x00050005
+#define DDRSS_CTL_88_DATA 0x00000005
 #define DDRSS_CTL_89_DATA 0x00000000
 #define DDRSS_CTL_90_DATA 0x00000000
 #define DDRSS_CTL_91_DATA 0x00000000
@@ -171,8 +172,8 @@
 #define DDRSS_CTL_153_DATA 0x00000000
 #define DDRSS_CTL_154_DATA 0x00000000
 #define DDRSS_CTL_155_DATA 0x00000000
-#define DDRSS_CTL_156_DATA 0x080C0000
-#define DDRSS_CTL_157_DATA 0x080C080C
+#define DDRSS_CTL_156_DATA 0x08080000
+#define DDRSS_CTL_157_DATA 0x08080808
 #define DDRSS_CTL_158_DATA 0x08000000
 #define DDRSS_CTL_159_DATA 0x00000808
 #define DDRSS_CTL_160_DATA 0x000E0000
@@ -251,12 +252,12 @@
 #define DDRSS_CTL_233_DATA 0x00000000
 #define DDRSS_CTL_234_DATA 0x00000000
 #define DDRSS_CTL_235_DATA 0x00000000
-#define DDRSS_CTL_236_DATA 0x00001401
-#define DDRSS_CTL_237_DATA 0x00001401
-#define DDRSS_CTL_238_DATA 0x00001401
-#define DDRSS_CTL_239_DATA 0x00001401
-#define DDRSS_CTL_240_DATA 0x00001401
-#define DDRSS_CTL_241_DATA 0x00001401
+#define DDRSS_CTL_236_DATA 0x00001400
+#define DDRSS_CTL_237_DATA 0x00001400
+#define DDRSS_CTL_238_DATA 0x00001400
+#define DDRSS_CTL_239_DATA 0x00001400
+#define DDRSS_CTL_240_DATA 0x00001400
+#define DDRSS_CTL_241_DATA 0x00001400
 #define DDRSS_CTL_242_DATA 0x00000493
 #define DDRSS_CTL_243_DATA 0x00000493
 #define DDRSS_CTL_244_DATA 0x00000493
@@ -385,9 +386,9 @@
 #define DDRSS_CTL_367_DATA 0x00000000
 #define DDRSS_CTL_368_DATA 0x00000000
 #define DDRSS_CTL_369_DATA 0x00000000
-#define DDRSS_CTL_370_DATA 0x0C000000
-#define DDRSS_CTL_371_DATA 0x060C0606
-#define DDRSS_CTL_372_DATA 0x06060C06
+#define DDRSS_CTL_370_DATA 0x08000000
+#define DDRSS_CTL_371_DATA 0x06080606
+#define DDRSS_CTL_372_DATA 0x06060806
 #define DDRSS_CTL_373_DATA 0x00010101
 #define DDRSS_CTL_374_DATA 0x02000000
 #define DDRSS_CTL_375_DATA 0x05020101
@@ -407,8 +408,8 @@
 #define DDRSS_CTL_389_DATA 0x00000200
 #define DDRSS_CTL_390_DATA 0x0000DB60
 #define DDRSS_CTL_391_DATA 0x0001E780
-#define DDRSS_CTL_392_DATA 0x0C0D0302
-#define DDRSS_CTL_393_DATA 0x001E090A
+#define DDRSS_CTL_392_DATA 0x080D0302
+#define DDRSS_CTL_393_DATA 0x001E0506
 #define DDRSS_CTL_394_DATA 0x000030C0
 #define DDRSS_CTL_395_DATA 0x00000200
 #define DDRSS_CTL_396_DATA 0x00000200
@@ -416,8 +417,8 @@
 #define DDRSS_CTL_398_DATA 0x00000200
 #define DDRSS_CTL_399_DATA 0x0000DB60
 #define DDRSS_CTL_400_DATA 0x0001E780
-#define DDRSS_CTL_401_DATA 0x0C0D0302
-#define DDRSS_CTL_402_DATA 0x001E090A
+#define DDRSS_CTL_401_DATA 0x080D0302
+#define DDRSS_CTL_402_DATA 0x001E0506
 #define DDRSS_CTL_403_DATA 0x000030C0
 #define DDRSS_CTL_404_DATA 0x00000200
 #define DDRSS_CTL_405_DATA 0x00000200
@@ -425,8 +426,8 @@
 #define DDRSS_CTL_407_DATA 0x00000200
 #define DDRSS_CTL_408_DATA 0x0000DB60
 #define DDRSS_CTL_409_DATA 0x0001E780
-#define DDRSS_CTL_410_DATA 0x0C0D0302
-#define DDRSS_CTL_411_DATA 0x0000090A
+#define DDRSS_CTL_410_DATA 0x080D0302
+#define DDRSS_CTL_411_DATA 0x00000506
 #define DDRSS_CTL_412_DATA 0x00000000
 #define DDRSS_CTL_413_DATA 0x0302000A
 #define DDRSS_CTL_414_DATA 0x01000500
@@ -605,14 +606,14 @@
 #define DDRSS_PI_164_DATA 0x00007800
 #define DDRSS_PI_165_DATA 0x00780078
 #define DDRSS_PI_166_DATA 0x00141414
-#define DDRSS_PI_167_DATA 0x0000003A
-#define DDRSS_PI_168_DATA 0x0000003A
-#define DDRSS_PI_169_DATA 0x0004003A
+#define DDRSS_PI_167_DATA 0x00000036
+#define DDRSS_PI_168_DATA 0x00000036
+#define DDRSS_PI_169_DATA 0x00040036
 #define DDRSS_PI_170_DATA 0x04000400
-#define DDRSS_PI_171_DATA 0xC8040009
-#define DDRSS_PI_172_DATA 0x0400091C
+#define DDRSS_PI_171_DATA 0xC8000009
+#define DDRSS_PI_172_DATA 0x0000091C
 #define DDRSS_PI_173_DATA 0x00091CC8
-#define DDRSS_PI_174_DATA 0x001CC804
+#define DDRSS_PI_174_DATA 0x001CC800
 #define DDRSS_PI_175_DATA 0x00000118
 #define DDRSS_PI_176_DATA 0x00001860
 #define DDRSS_PI_177_DATA 0x00000118
@@ -622,8 +623,8 @@
 #define DDRSS_PI_181_DATA 0x01010404
 #define DDRSS_PI_182_DATA 0x00001901
 #define DDRSS_PI_183_DATA 0x00190019
-#define DDRSS_PI_184_DATA 0x010C010C
-#define DDRSS_PI_185_DATA 0x0000010C
+#define DDRSS_PI_184_DATA 0x01080108
+#define DDRSS_PI_185_DATA 0x00000108
 #define DDRSS_PI_186_DATA 0x00000000
 #define DDRSS_PI_187_DATA 0x05000000
 #define DDRSS_PI_188_DATA 0x01010505
@@ -631,9 +632,9 @@
 #define DDRSS_PI_190_DATA 0x00181818
 #define DDRSS_PI_191_DATA 0x00000000
 #define DDRSS_PI_192_DATA 0x00000000
-#define DDRSS_PI_193_DATA 0x0D000000
-#define DDRSS_PI_194_DATA 0x0A0A0D0D
-#define DDRSS_PI_195_DATA 0x0303030A
+#define DDRSS_PI_193_DATA 0x09000000
+#define DDRSS_PI_194_DATA 0x06060909
+#define DDRSS_PI_195_DATA 0x03030306
 #define DDRSS_PI_196_DATA 0x00000000
 #define DDRSS_PI_197_DATA 0x00000000
 #define DDRSS_PI_198_DATA 0x00000000
@@ -659,32 +660,32 @@
 #define DDRSS_PI_218_DATA 0x001600C8
 #define DDRSS_PI_219_DATA 0x001600C8
 #define DDRSS_PI_220_DATA 0x010100C8
-#define DDRSS_PI_221_DATA 0x00001B01
+#define DDRSS_PI_221_DATA 0x00001701
 #define DDRSS_PI_222_DATA 0x1F0F0053
 #define DDRSS_PI_223_DATA 0x05000001
-#define DDRSS_PI_224_DATA 0x001B0A0D
+#define DDRSS_PI_224_DATA 0x00170A09
 #define DDRSS_PI_225_DATA 0x1F0F0053
 #define DDRSS_PI_226_DATA 0x05000001
-#define DDRSS_PI_227_DATA 0x001B0A0D
+#define DDRSS_PI_227_DATA 0x00170A09
 #define DDRSS_PI_228_DATA 0x1F0F0053
 #define DDRSS_PI_229_DATA 0x05000001
-#define DDRSS_PI_230_DATA 0x00010A0D
+#define DDRSS_PI_230_DATA 0x00010A09
 #define DDRSS_PI_231_DATA 0x0C0B0700
 #define DDRSS_PI_232_DATA 0x000D0605
 #define DDRSS_PI_233_DATA 0x0000C570
 #define DDRSS_PI_234_DATA 0x0000001D
 #define DDRSS_PI_235_DATA 0x180A0800
-#define DDRSS_PI_236_DATA 0x0B071C1C
+#define DDRSS_PI_236_DATA 0x0B071818
 #define DDRSS_PI_237_DATA 0x0D06050C
 #define DDRSS_PI_238_DATA 0x0000C570
 #define DDRSS_PI_239_DATA 0x0000001D
 #define DDRSS_PI_240_DATA 0x180A0800
-#define DDRSS_PI_241_DATA 0x0B071C1C
+#define DDRSS_PI_241_DATA 0x0B071818
 #define DDRSS_PI_242_DATA 0x0D06050C
 #define DDRSS_PI_243_DATA 0x0000C570
 #define DDRSS_PI_244_DATA 0x0000001D
 #define DDRSS_PI_245_DATA 0x180A0800
-#define DDRSS_PI_246_DATA 0x00001C1C
+#define DDRSS_PI_246_DATA 0x00001818
 #define DDRSS_PI_247_DATA 0x000030C0
 #define DDRSS_PI_248_DATA 0x0001E780
 #define DDRSS_PI_249_DATA 0x000030C0
@@ -695,8 +696,8 @@
 #define DDRSS_PI_254_DATA 0x03030255
 #define DDRSS_PI_255_DATA 0x00025503
 #define DDRSS_PI_256_DATA 0x02550255
-#define DDRSS_PI_257_DATA 0x0C080C08
-#define DDRSS_PI_258_DATA 0x00000C08
+#define DDRSS_PI_257_DATA 0x08080808
+#define DDRSS_PI_258_DATA 0x00000808
 #define DDRSS_PI_259_DATA 0x000890B8
 #define DDRSS_PI_260_DATA 0x00000000
 #define DDRSS_PI_261_DATA 0x00000000
@@ -740,7 +741,7 @@
 #define DDRSS_PI_299_DATA 0x00000000
 #define DDRSS_PI_300_DATA 0x00000000
 #define DDRSS_PI_301_DATA 0x00000000
-#define DDRSS_PI_302_DATA 0x00001401
+#define DDRSS_PI_302_DATA 0x00001400
 #define DDRSS_PI_303_DATA 0x00000493
 #define DDRSS_PI_304_DATA 0x00000000
 #define DDRSS_PI_305_DATA 0x00000424
@@ -748,7 +749,7 @@
 #define DDRSS_PI_307_DATA 0x00000000
 #define DDRSS_PI_308_DATA 0x00000000
 #define DDRSS_PI_309_DATA 0x00000000
-#define DDRSS_PI_310_DATA 0x00001401
+#define DDRSS_PI_310_DATA 0x00001400
 #define DDRSS_PI_311_DATA 0x00000493
 #define DDRSS_PI_312_DATA 0x00000000
 #define DDRSS_PI_313_DATA 0x00000424
@@ -756,7 +757,7 @@
 #define DDRSS_PI_315_DATA 0x00000000
 #define DDRSS_PI_316_DATA 0x00000000
 #define DDRSS_PI_317_DATA 0x00000000
-#define DDRSS_PI_318_DATA 0x00001401
+#define DDRSS_PI_318_DATA 0x00001400
 #define DDRSS_PI_319_DATA 0x00000493
 #define DDRSS_PI_320_DATA 0x00000000
 #define DDRSS_PI_321_DATA 0x00000424
@@ -764,7 +765,7 @@
 #define DDRSS_PI_323_DATA 0x00000000
 #define DDRSS_PI_324_DATA 0x00000000
 #define DDRSS_PI_325_DATA 0x00000000
-#define DDRSS_PI_326_DATA 0x00001401
+#define DDRSS_PI_326_DATA 0x00001400
 #define DDRSS_PI_327_DATA 0x00000493
 #define DDRSS_PI_328_DATA 0x00000000
 #define DDRSS_PI_329_DATA 0x00000424
@@ -772,7 +773,7 @@
 #define DDRSS_PI_331_DATA 0x00000000
 #define DDRSS_PI_332_DATA 0x00000000
 #define DDRSS_PI_333_DATA 0x00000000
-#define DDRSS_PI_334_DATA 0x00001401
+#define DDRSS_PI_334_DATA 0x00001400
 #define DDRSS_PI_335_DATA 0x00000493
 #define DDRSS_PI_336_DATA 0x00000000
 #define DDRSS_PI_337_DATA 0x00000424
@@ -780,7 +781,7 @@
 #define DDRSS_PI_339_DATA 0x00000000
 #define DDRSS_PI_340_DATA 0x00000000
 #define DDRSS_PI_341_DATA 0x00000000
-#define DDRSS_PI_342_DATA 0x00001401
+#define DDRSS_PI_342_DATA 0x00001400
 #define DDRSS_PI_343_DATA 0x00000493
 #define DDRSS_PI_344_DATA 0x00000000
 #define DDRSS_PHY_0_DATA 0x04C00000
@@ -2102,7 +2103,7 @@
 #define DDRSS_PHY_1316_DATA 0x00000000
 #define DDRSS_PHY_1317_DATA 0x00000000
 #define DDRSS_PHY_1318_DATA 0x00000000
-#define DDRSS_PHY_1319_DATA 0x07070001
+#define DDRSS_PHY_1319_DATA 0x07030001
 #define DDRSS_PHY_1320_DATA 0x00005400
 #define DDRSS_PHY_1321_DATA 0x000040A2
 #define DDRSS_PHY_1322_DATA 0x00024410

arch/arm/dts/k3-am64-evm-ddr4-1600MTs.dtsi

@@ -1,19 +1,20 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * This file was generated with the
- * AM64x SysConfig DDR Configuration Tool for AM64x, AM625, AM623, AM62Ax, AM62Px v0.10.02
- * Tue Sep 17 2024 11:01:31 GMT+0530 (India Standard Time)
+ * AM64x SysConfig DDR Configuration Tool for AM64x, AM625, AM623, AM62Ax, AM62Px, AM62Dx, AM62Lx v0.10.32
+ * Fri Jan 30 2026 13:47:49 GMT+0530 (India Standard Time)
  * DDR Type: DDR4
  * Frequency = 800MHz (1600MTs)
  * Density: 16Gb
  * Number of Ranks: 1
- */
+*/
 
 #define DDRSS_PLL_FHS_CNT 6
 #define DDRSS_PLL_FREQUENCY_1 400000000
 #define DDRSS_PLL_FREQUENCY_2 400000000
 #define DDRSS_SDRAM_IDX 15
 #define DDRSS_REGION_IDX 15
+#define DDRSS_TOOL_VERSION "0.10.32"
 
 #define DDRSS_CTL_0_DATA 0x00000A00
 #define DDRSS_CTL_1_DATA 0x00000000
@@ -53,12 +54,12 @@
 #define DDRSS_CTL_35_DATA 0x00000000
 #define DDRSS_CTL_36_DATA 0x00000000
 #define DDRSS_CTL_37_DATA 0x00000000
-#define DDRSS_CTL_38_DATA 0x0400091C
-#define DDRSS_CTL_39_DATA 0x1C1C1C1C
-#define DDRSS_CTL_40_DATA 0x0400091C
-#define DDRSS_CTL_41_DATA 0x1C1C1C1C
-#define DDRSS_CTL_42_DATA 0x0400091C
-#define DDRSS_CTL_43_DATA 0x1C1C1C1C
+#define DDRSS_CTL_38_DATA 0x0000091C
+#define DDRSS_CTL_39_DATA 0x18181818
+#define DDRSS_CTL_40_DATA 0x0000091C
+#define DDRSS_CTL_41_DATA 0x18181818
+#define DDRSS_CTL_42_DATA 0x0000091C
+#define DDRSS_CTL_43_DATA 0x18181818
 #define DDRSS_CTL_44_DATA 0x05050404
 #define DDRSS_CTL_45_DATA 0x00002706
 #define DDRSS_CTL_46_DATA 0x0602001D
@@ -71,13 +72,13 @@
 #define DDRSS_CTL_53_DATA 0x07001D0B
 #define DDRSS_CTL_54_DATA 0x00180807
 #define DDRSS_CTL_55_DATA 0x0400DB60
-#define DDRSS_CTL_56_DATA 0x07070009
+#define DDRSS_CTL_56_DATA 0x07070005
 #define DDRSS_CTL_57_DATA 0x00001808
 #define DDRSS_CTL_58_DATA 0x0400DB60
-#define DDRSS_CTL_59_DATA 0x07070009
+#define DDRSS_CTL_59_DATA 0x07070005
 #define DDRSS_CTL_60_DATA 0x00001808
 #define DDRSS_CTL_61_DATA 0x0400DB60
-#define DDRSS_CTL_62_DATA 0x03000009
+#define DDRSS_CTL_62_DATA 0x03000005
 #define DDRSS_CTL_63_DATA 0x0D0C0002
 #define DDRSS_CTL_64_DATA 0x0D0C0D0C
 #define DDRSS_CTL_65_DATA 0x01010000
@@ -102,8 +103,8 @@
 #define DDRSS_CTL_84_DATA 0x00000000
 #define DDRSS_CTL_85_DATA 0x00000000
 #define DDRSS_CTL_86_DATA 0x00000000
-#define DDRSS_CTL_87_DATA 0x00090009
-#define DDRSS_CTL_88_DATA 0x00000009
+#define DDRSS_CTL_87_DATA 0x00050005
+#define DDRSS_CTL_88_DATA 0x00000005
 #define DDRSS_CTL_89_DATA 0x00000000
 #define DDRSS_CTL_90_DATA 0x00000000
 #define DDRSS_CTL_91_DATA 0x00000000
@@ -171,8 +172,8 @@
 #define DDRSS_CTL_153_DATA 0x00000000
 #define DDRSS_CTL_154_DATA 0x00000000
 #define DDRSS_CTL_155_DATA 0x00000000
-#define DDRSS_CTL_156_DATA 0x080C0000
-#define DDRSS_CTL_157_DATA 0x080C080C
+#define DDRSS_CTL_156_DATA 0x08080000
+#define DDRSS_CTL_157_DATA 0x08080808
 #define DDRSS_CTL_158_DATA 0x00000000
 #define DDRSS_CTL_159_DATA 0x07010A09
 #define DDRSS_CTL_160_DATA 0x000E0A09
@@ -251,12 +252,12 @@
 #define DDRSS_CTL_233_DATA 0x00000000
 #define DDRSS_CTL_234_DATA 0x00000000
 #define DDRSS_CTL_235_DATA 0x00000000
-#define DDRSS_CTL_236_DATA 0x00001401
-#define DDRSS_CTL_237_DATA 0x00001401
-#define DDRSS_CTL_238_DATA 0x00001401
-#define DDRSS_CTL_239_DATA 0x00001401
-#define DDRSS_CTL_240_DATA 0x00001401
-#define DDRSS_CTL_241_DATA 0x00001401
+#define DDRSS_CTL_236_DATA 0x00001400
+#define DDRSS_CTL_237_DATA 0x00001400
+#define DDRSS_CTL_238_DATA 0x00001400
+#define DDRSS_CTL_239_DATA 0x00001400
+#define DDRSS_CTL_240_DATA 0x00001400
+#define DDRSS_CTL_241_DATA 0x00001400
 #define DDRSS_CTL_242_DATA 0x00000493
 #define DDRSS_CTL_243_DATA 0x00000493
 #define DDRSS_CTL_244_DATA 0x00000493
@@ -385,9 +386,9 @@
 #define DDRSS_CTL_367_DATA 0x00000000
 #define DDRSS_CTL_368_DATA 0x00000000
 #define DDRSS_CTL_369_DATA 0x00000000
-#define DDRSS_CTL_370_DATA 0x0C000000
-#define DDRSS_CTL_371_DATA 0x060C0606
-#define DDRSS_CTL_372_DATA 0x06060C06
+#define DDRSS_CTL_370_DATA 0x08000000
+#define DDRSS_CTL_371_DATA 0x06080606
+#define DDRSS_CTL_372_DATA 0x06060806
 #define DDRSS_CTL_373_DATA 0x00010101
 #define DDRSS_CTL_374_DATA 0x02000000
 #define DDRSS_CTL_375_DATA 0x05020101
@@ -407,8 +408,8 @@
 #define DDRSS_CTL_389_DATA 0x00000200
 #define DDRSS_CTL_390_DATA 0x0000DB60
 #define DDRSS_CTL_391_DATA 0x0001E780
-#define DDRSS_CTL_392_DATA 0x0C0D0302
-#define DDRSS_CTL_393_DATA 0x001E090A
+#define DDRSS_CTL_392_DATA 0x080D0302
+#define DDRSS_CTL_393_DATA 0x001E0506
 #define DDRSS_CTL_394_DATA 0x000030C0
 #define DDRSS_CTL_395_DATA 0x00000200
 #define DDRSS_CTL_396_DATA 0x00000200
@@ -416,8 +417,8 @@
 #define DDRSS_CTL_398_DATA 0x00000200
 #define DDRSS_CTL_399_DATA 0x0000DB60
 #define DDRSS_CTL_400_DATA 0x0001E780
-#define DDRSS_CTL_401_DATA 0x0C0D0302
-#define DDRSS_CTL_402_DATA 0x001E090A
+#define DDRSS_CTL_401_DATA 0x080D0302
+#define DDRSS_CTL_402_DATA 0x001E0506
 #define DDRSS_CTL_403_DATA 0x000030C0
 #define DDRSS_CTL_404_DATA 0x00000200
 #define DDRSS_CTL_405_DATA 0x00000200
@@ -425,8 +426,8 @@
 #define DDRSS_CTL_407_DATA 0x00000200
 #define DDRSS_CTL_408_DATA 0x0000DB60
 #define DDRSS_CTL_409_DATA 0x0001E780
-#define DDRSS_CTL_410_DATA 0x0C0D0302
-#define DDRSS_CTL_411_DATA 0x0000090A
+#define DDRSS_CTL_410_DATA 0x080D0302
+#define DDRSS_CTL_411_DATA 0x00000506
 #define DDRSS_CTL_412_DATA 0x00000000
 #define DDRSS_CTL_413_DATA 0x0302000A
 #define DDRSS_CTL_414_DATA 0x01000500
@@ -605,14 +606,14 @@
 #define DDRSS_PI_164_DATA 0x00007800
 #define DDRSS_PI_165_DATA 0x00780078
 #define DDRSS_PI_166_DATA 0x00141414
-#define DDRSS_PI_167_DATA 0x0000003A
-#define DDRSS_PI_168_DATA 0x0000003A
-#define DDRSS_PI_169_DATA 0x0004003A
+#define DDRSS_PI_167_DATA 0x00000036
+#define DDRSS_PI_168_DATA 0x00000036
+#define DDRSS_PI_169_DATA 0x00040036
 #define DDRSS_PI_170_DATA 0x04000400
-#define DDRSS_PI_171_DATA 0xC8040009
-#define DDRSS_PI_172_DATA 0x0400091C
+#define DDRSS_PI_171_DATA 0xC8000009
+#define DDRSS_PI_172_DATA 0x0000091C
 #define DDRSS_PI_173_DATA 0x00091CC8
-#define DDRSS_PI_174_DATA 0x001CC804
+#define DDRSS_PI_174_DATA 0x001CC800
 #define DDRSS_PI_175_DATA 0x00000118
 #define DDRSS_PI_176_DATA 0x00001860
 #define DDRSS_PI_177_DATA 0x00000118
@@ -622,8 +623,8 @@
 #define DDRSS_PI_181_DATA 0x01010404
 #define DDRSS_PI_182_DATA 0x00001901
 #define DDRSS_PI_183_DATA 0x00190019
-#define DDRSS_PI_184_DATA 0x010C010C
-#define DDRSS_PI_185_DATA 0x0000010C
+#define DDRSS_PI_184_DATA 0x01080108
+#define DDRSS_PI_185_DATA 0x00000108
 #define DDRSS_PI_186_DATA 0x00000000
 #define DDRSS_PI_187_DATA 0x05000000
 #define DDRSS_PI_188_DATA 0x01010505
@@ -631,9 +632,9 @@
 #define DDRSS_PI_190_DATA 0x00181818
 #define DDRSS_PI_191_DATA 0x00000000
 #define DDRSS_PI_192_DATA 0x00000000
-#define DDRSS_PI_193_DATA 0x0D000000
-#define DDRSS_PI_194_DATA 0x0A0A0D0D
-#define DDRSS_PI_195_DATA 0x0303030A
+#define DDRSS_PI_193_DATA 0x09000000
+#define DDRSS_PI_194_DATA 0x06060909
+#define DDRSS_PI_195_DATA 0x03030306
 #define DDRSS_PI_196_DATA 0x00000000
 #define DDRSS_PI_197_DATA 0x00000000
 #define DDRSS_PI_198_DATA 0x00000000
@@ -659,32 +660,32 @@
 #define DDRSS_PI_218_DATA 0x001600C8
 #define DDRSS_PI_219_DATA 0x001600C8
 #define DDRSS_PI_220_DATA 0x010100C8
-#define DDRSS_PI_221_DATA 0x00001B01
+#define DDRSS_PI_221_DATA 0x00001701
 #define DDRSS_PI_222_DATA 0x1F0F0053
 #define DDRSS_PI_223_DATA 0x05000001
-#define DDRSS_PI_224_DATA 0x001B0A0D
+#define DDRSS_PI_224_DATA 0x00170A09
 #define DDRSS_PI_225_DATA 0x1F0F0053
 #define DDRSS_PI_226_DATA 0x05000001
-#define DDRSS_PI_227_DATA 0x001B0A0D
+#define DDRSS_PI_227_DATA 0x00170A09
 #define DDRSS_PI_228_DATA 0x1F0F0053
 #define DDRSS_PI_229_DATA 0x05000001
-#define DDRSS_PI_230_DATA 0x00010A0D
+#define DDRSS_PI_230_DATA 0x00010A09
 #define DDRSS_PI_231_DATA 0x0C0B0700
 #define DDRSS_PI_232_DATA 0x000D0605
 #define DDRSS_PI_233_DATA 0x0000C570
 #define DDRSS_PI_234_DATA 0x0000001D
 #define DDRSS_PI_235_DATA 0x180A0800
-#define DDRSS_PI_236_DATA 0x0B071C1C
+#define DDRSS_PI_236_DATA 0x0B071818
 #define DDRSS_PI_237_DATA 0x0D06050C
 #define DDRSS_PI_238_DATA 0x0000C570
 #define DDRSS_PI_239_DATA 0x0000001D
 #define DDRSS_PI_240_DATA 0x180A0800
-#define DDRSS_PI_241_DATA 0x0B071C1C
+#define DDRSS_PI_241_DATA 0x0B071818
 #define DDRSS_PI_242_DATA 0x0D06050C
 #define DDRSS_PI_243_DATA 0x0000C570
 #define DDRSS_PI_244_DATA 0x0000001D
 #define DDRSS_PI_245_DATA 0x180A0800
-#define DDRSS_PI_246_DATA 0x00001C1C
+#define DDRSS_PI_246_DATA 0x00001818
 #define DDRSS_PI_247_DATA 0x000030C0
 #define DDRSS_PI_248_DATA 0x0001E780
 #define DDRSS_PI_249_DATA 0x000030C0
@@ -695,8 +696,8 @@
 #define DDRSS_PI_254_DATA 0x03030255
 #define DDRSS_PI_255_DATA 0x00025503
 #define DDRSS_PI_256_DATA 0x02550255
-#define DDRSS_PI_257_DATA 0x0C080C08
-#define DDRSS_PI_258_DATA 0x00000C08
+#define DDRSS_PI_257_DATA 0x08080808
+#define DDRSS_PI_258_DATA 0x00000808
 #define DDRSS_PI_259_DATA 0x000890B8
 #define DDRSS_PI_260_DATA 0x00000000
 #define DDRSS_PI_261_DATA 0x00000000
@@ -740,7 +741,7 @@
 #define DDRSS_PI_299_DATA 0x00000000
 #define DDRSS_PI_300_DATA 0x00000000
 #define DDRSS_PI_301_DATA 0x00000000
-#define DDRSS_PI_302_DATA 0x00001401
+#define DDRSS_PI_302_DATA 0x00001400
 #define DDRSS_PI_303_DATA 0x00000493
 #define DDRSS_PI_304_DATA 0x00000000
 #define DDRSS_PI_305_DATA 0x00000424
@@ -748,7 +749,7 @@
 #define DDRSS_PI_307_DATA 0x00000000
 #define DDRSS_PI_308_DATA 0x00000000
 #define DDRSS_PI_309_DATA 0x00000000
-#define DDRSS_PI_310_DATA 0x00001401
+#define DDRSS_PI_310_DATA 0x00001400
 #define DDRSS_PI_311_DATA 0x00000493
 #define DDRSS_PI_312_DATA 0x00000000
 #define DDRSS_PI_313_DATA 0x00000424
@@ -756,7 +757,7 @@
 #define DDRSS_PI_315_DATA 0x00000000
 #define DDRSS_PI_316_DATA 0x00000000
 #define DDRSS_PI_317_DATA 0x00000000
-#define DDRSS_PI_318_DATA 0x00001401
+#define DDRSS_PI_318_DATA 0x00001400
 #define DDRSS_PI_319_DATA 0x00000493
 #define DDRSS_PI_320_DATA 0x00000000
 #define DDRSS_PI_321_DATA 0x00000424
@@ -764,7 +765,7 @@
 #define DDRSS_PI_323_DATA 0x00000000
 #define DDRSS_PI_324_DATA 0x00000000
 #define DDRSS_PI_325_DATA 0x00000000
-#define DDRSS_PI_326_DATA 0x00001401
+#define DDRSS_PI_326_DATA 0x00001400
 #define DDRSS_PI_327_DATA 0x00000493
 #define DDRSS_PI_328_DATA 0x00000000
 #define DDRSS_PI_329_DATA 0x00000424
@@ -772,7 +773,7 @@
 #define DDRSS_PI_331_DATA 0x00000000
 #define DDRSS_PI_332_DATA 0x00000000
 #define DDRSS_PI_333_DATA 0x00000000
-#define DDRSS_PI_334_DATA 0x00001401
+#define DDRSS_PI_334_DATA 0x00001400
 #define DDRSS_PI_335_DATA 0x00000493
 #define DDRSS_PI_336_DATA 0x00000000
 #define DDRSS_PI_337_DATA 0x00000424
@@ -780,7 +781,7 @@
 #define DDRSS_PI_339_DATA 0x00000000
 #define DDRSS_PI_340_DATA 0x00000000
 #define DDRSS_PI_341_DATA 0x00000000
-#define DDRSS_PI_342_DATA 0x00001401
+#define DDRSS_PI_342_DATA 0x00001400
 #define DDRSS_PI_343_DATA 0x00000493
 #define DDRSS_PI_344_DATA 0x00000000
 #define DDRSS_PHY_0_DATA 0x04C00000
@@ -2102,7 +2103,7 @@
 #define DDRSS_PHY_1316_DATA 0x00000000
 #define DDRSS_PHY_1317_DATA 0x00000000
 #define DDRSS_PHY_1318_DATA 0x00000000
-#define DDRSS_PHY_1319_DATA 0x07070001
+#define DDRSS_PHY_1319_DATA 0x07030001
 #define DDRSS_PHY_1320_DATA 0x00005400
 #define DDRSS_PHY_1321_DATA 0x000040A2
 #define DDRSS_PHY_1322_DATA 0x00024410

arch/arm/dts/k3-am64-phycore-som-ddr4-2gb.dtsi

@@ -1,8 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * This file was generated with the
- * AM64x SysConfig DDR Subsystem Register Configuration Tool v0.08.10
- * Wed Dec 15 2021 14:35:01 GMT-0800 (Pacific Standard Time)
+ * AM64x SysConfig DDR Subsystem Register Configuration Tool v0.09.05
+ * Fri Feb 03 2023 11:04:00 GMT+0100 (Mitteleuropäische Normalzeit)
  * DDR Type: DDR4
  * Frequency = 800MHz (1600MTs)
  * Density: 16Gb
@@ -13,6 +13,7 @@
 #define DDRSS_PLL_FREQUENCY_1 400000000
 #define DDRSS_PLL_FREQUENCY_2 400000000
 
+
 #define DDRSS_CTL_0_DATA 0x00000A00
 #define DDRSS_CTL_1_DATA 0x00000000
 #define DDRSS_CTL_2_DATA 0x00000000
@@ -58,39 +59,39 @@
 #define DDRSS_CTL_42_DATA 0x0400091C
 #define DDRSS_CTL_43_DATA 0x1C1C1C1C
 #define DDRSS_CTL_44_DATA 0x05050404
-#define DDRSS_CTL_45_DATA 0x00002806
+#define DDRSS_CTL_45_DATA 0x00002706
 #define DDRSS_CTL_46_DATA 0x0602001D
-#define DDRSS_CTL_47_DATA 0x05001D0C
-#define DDRSS_CTL_48_DATA 0x00280605
+#define DDRSS_CTL_47_DATA 0x05001D0B
+#define DDRSS_CTL_48_DATA 0x00270605
 #define DDRSS_CTL_49_DATA 0x0602001D
-#define DDRSS_CTL_50_DATA 0x05001D0C
-#define DDRSS_CTL_51_DATA 0x00280605
+#define DDRSS_CTL_50_DATA 0x05001D0B
+#define DDRSS_CTL_51_DATA 0x00270605
 #define DDRSS_CTL_52_DATA 0x0602001D
-#define DDRSS_CTL_53_DATA 0x07001D0C
+#define DDRSS_CTL_53_DATA 0x07001D0B
 #define DDRSS_CTL_54_DATA 0x00180807
-#define DDRSS_CTL_55_DATA 0x0400DB60
+#define DDRSS_CTL_55_DATA 0x04006DB0
 #define DDRSS_CTL_56_DATA 0x07070009
 #define DDRSS_CTL_57_DATA 0x00001808
-#define DDRSS_CTL_58_DATA 0x0400DB60
+#define DDRSS_CTL_58_DATA 0x04006DB0
 #define DDRSS_CTL_59_DATA 0x07070009
 #define DDRSS_CTL_60_DATA 0x00001808
-#define DDRSS_CTL_61_DATA 0x0400DB60
+#define DDRSS_CTL_61_DATA 0x04006DB0
 #define DDRSS_CTL_62_DATA 0x03000009
-#define DDRSS_CTL_63_DATA 0x0D0D0002
-#define DDRSS_CTL_64_DATA 0x0D0D0D0D
+#define DDRSS_CTL_63_DATA 0x0D0C0002
+#define DDRSS_CTL_64_DATA 0x0D0C0D0C
 #define DDRSS_CTL_65_DATA 0x01010000
-#define DDRSS_CTL_66_DATA 0x031A1A1A
-#define DDRSS_CTL_67_DATA 0x0C0C0C0C
-#define DDRSS_CTL_68_DATA 0x00000C0C
+#define DDRSS_CTL_66_DATA 0x03191919
+#define DDRSS_CTL_67_DATA 0x0B0B0B0B
+#define DDRSS_CTL_68_DATA 0x00000B0B
 #define DDRSS_CTL_69_DATA 0x00000101
 #define DDRSS_CTL_70_DATA 0x00000000
 #define DDRSS_CTL_71_DATA 0x01000000
 #define DDRSS_CTL_72_DATA 0x01180803
-#define DDRSS_CTL_73_DATA 0x00001860
+#define DDRSS_CTL_73_DATA 0x00000C30
 #define DDRSS_CTL_74_DATA 0x00000118
-#define DDRSS_CTL_75_DATA 0x00001860
+#define DDRSS_CTL_75_DATA 0x00000C30
 #define DDRSS_CTL_76_DATA 0x00000118
-#define DDRSS_CTL_77_DATA 0x00001860
+#define DDRSS_CTL_77_DATA 0x00000C30
 #define DDRSS_CTL_78_DATA 0x00000005
 #define DDRSS_CTL_79_DATA 0x00000000
 #define DDRSS_CTL_80_DATA 0x00000000
@@ -132,27 +133,27 @@
 #define DDRSS_CTL_116_DATA 0x00040003
 #define DDRSS_CTL_117_DATA 0x00040005
 #define DDRSS_CTL_118_DATA 0x00000000
-#define DDRSS_CTL_119_DATA 0x00061800
-#define DDRSS_CTL_120_DATA 0x00061800
-#define DDRSS_CTL_121_DATA 0x00061800
-#define DDRSS_CTL_122_DATA 0x00061800
-#define DDRSS_CTL_123_DATA 0x00061800
+#define DDRSS_CTL_119_DATA 0x00030C00
+#define DDRSS_CTL_120_DATA 0x00030C00
+#define DDRSS_CTL_121_DATA 0x00030C00
+#define DDRSS_CTL_122_DATA 0x00030C00
+#define DDRSS_CTL_123_DATA 0x00030C00
 #define DDRSS_CTL_124_DATA 0x00000000
-#define DDRSS_CTL_125_DATA 0x0000AAA0
-#define DDRSS_CTL_126_DATA 0x00061800
-#define DDRSS_CTL_127_DATA 0x00061800
-#define DDRSS_CTL_128_DATA 0x00061800
-#define DDRSS_CTL_129_DATA 0x00061800
-#define DDRSS_CTL_130_DATA 0x00061800
+#define DDRSS_CTL_125_DATA 0x00005550
+#define DDRSS_CTL_126_DATA 0x00030C00
+#define DDRSS_CTL_127_DATA 0x00030C00
+#define DDRSS_CTL_128_DATA 0x00030C00
+#define DDRSS_CTL_129_DATA 0x00030C00
+#define DDRSS_CTL_130_DATA 0x00030C00
 #define DDRSS_CTL_131_DATA 0x00000000
-#define DDRSS_CTL_132_DATA 0x0000AAA0
-#define DDRSS_CTL_133_DATA 0x00061800
-#define DDRSS_CTL_134_DATA 0x00061800
-#define DDRSS_CTL_135_DATA 0x00061800
-#define DDRSS_CTL_136_DATA 0x00061800
-#define DDRSS_CTL_137_DATA 0x00061800
+#define DDRSS_CTL_132_DATA 0x00005550
+#define DDRSS_CTL_133_DATA 0x00030C00
+#define DDRSS_CTL_134_DATA 0x00030C00
+#define DDRSS_CTL_135_DATA 0x00030C00
+#define DDRSS_CTL_136_DATA 0x00030C00
+#define DDRSS_CTL_137_DATA 0x00030C00
 #define DDRSS_CTL_138_DATA 0x00000000
-#define DDRSS_CTL_139_DATA 0x0000AAA0
+#define DDRSS_CTL_139_DATA 0x00005550
 #define DDRSS_CTL_140_DATA 0x00000000
 #define DDRSS_CTL_141_DATA 0x00000000
 #define DDRSS_CTL_142_DATA 0x00000000
@@ -178,7 +179,7 @@
 #define DDRSS_CTL_162_DATA 0x0E0A0907
 #define DDRSS_CTL_163_DATA 0x0A090000
 #define DDRSS_CTL_164_DATA 0x0A090701
-#define DDRSS_CTL_165_DATA 0x0000000E
+#define DDRSS_CTL_165_DATA 0x0000080E
 #define DDRSS_CTL_166_DATA 0x00040003
 #define DDRSS_CTL_167_DATA 0x00000007
 #define DDRSS_CTL_168_DATA 0x00000000
@@ -219,22 +220,22 @@
 #define DDRSS_CTL_203_DATA 0x00000000
 #define DDRSS_CTL_204_DATA 0x00042400
 #define DDRSS_CTL_205_DATA 0x00000301
-#define DDRSS_CTL_206_DATA 0x00000000
+#define DDRSS_CTL_206_DATA 0x000000C0
 #define DDRSS_CTL_207_DATA 0x00000424
 #define DDRSS_CTL_208_DATA 0x00000301
-#define DDRSS_CTL_209_DATA 0x00000000
+#define DDRSS_CTL_209_DATA 0x000000C0
 #define DDRSS_CTL_210_DATA 0x00000424
 #define DDRSS_CTL_211_DATA 0x00000301
-#define DDRSS_CTL_212_DATA 0x00000000
+#define DDRSS_CTL_212_DATA 0x000000C0
 #define DDRSS_CTL_213_DATA 0x00000424
 #define DDRSS_CTL_214_DATA 0x00000301
-#define DDRSS_CTL_215_DATA 0x00000000
+#define DDRSS_CTL_215_DATA 0x000000C0
 #define DDRSS_CTL_216_DATA 0x00000424
 #define DDRSS_CTL_217_DATA 0x00000301
-#define DDRSS_CTL_218_DATA 0x00000000
+#define DDRSS_CTL_218_DATA 0x000000C0
 #define DDRSS_CTL_219_DATA 0x00000424
 #define DDRSS_CTL_220_DATA 0x00000301
-#define DDRSS_CTL_221_DATA 0x00000000
+#define DDRSS_CTL_221_DATA 0x000000C0
 #define DDRSS_CTL_222_DATA 0x00000000
 #define DDRSS_CTL_223_DATA 0x00000000
 #define DDRSS_CTL_224_DATA 0x00000000
@@ -243,12 +244,12 @@
 #define DDRSS_CTL_227_DATA 0x00000000
 #define DDRSS_CTL_228_DATA 0x00000000
 #define DDRSS_CTL_229_DATA 0x00000000
-#define DDRSS_CTL_230_DATA 0x00000000
-#define DDRSS_CTL_231_DATA 0x00000000
-#define DDRSS_CTL_232_DATA 0x00000000
-#define DDRSS_CTL_233_DATA 0x00000000
-#define DDRSS_CTL_234_DATA 0x00000000
-#define DDRSS_CTL_235_DATA 0x00000000
+#define DDRSS_CTL_230_DATA 0x0000000C
+#define DDRSS_CTL_231_DATA 0x0000000C
+#define DDRSS_CTL_232_DATA 0x0000000C
+#define DDRSS_CTL_233_DATA 0x0000000C
+#define DDRSS_CTL_234_DATA 0x0000000C
+#define DDRSS_CTL_235_DATA 0x0000000C
 #define DDRSS_CTL_236_DATA 0x00001401
 #define DDRSS_CTL_237_DATA 0x00001401
 #define DDRSS_CTL_238_DATA 0x00001401
@@ -334,7 +335,7 @@
 #define DDRSS_CTL_318_DATA 0x3FFF0000
 #define DDRSS_CTL_319_DATA 0x000FFF00
 #define DDRSS_CTL_320_DATA 0xFFFFFFFF
-#define DDRSS_CTL_321_DATA 0x000FFF00
+#define DDRSS_CTL_321_DATA 0x00FFFF00
 #define DDRSS_CTL_322_DATA 0x0A000000
 #define DDRSS_CTL_323_DATA 0x0001FFFF
 #define DDRSS_CTL_324_DATA 0x01010101
@@ -343,7 +344,7 @@
 #define DDRSS_CTL_327_DATA 0x00000C01
 #define DDRSS_CTL_328_DATA 0x00000000
 #define DDRSS_CTL_329_DATA 0x00000000
-#define DDRSS_CTL_330_DATA 0x01000000
+#define DDRSS_CTL_330_DATA 0x00000000
 #define DDRSS_CTL_331_DATA 0x01000000
 #define DDRSS_CTL_332_DATA 0x00000100
 #define DDRSS_CTL_333_DATA 0x00010000
@@ -398,31 +399,31 @@
 #define DDRSS_CTL_382_DATA 0x00000000
 #define DDRSS_CTL_383_DATA 0x04000100
 #define DDRSS_CTL_384_DATA 0x1E000004
-#define DDRSS_CTL_385_DATA 0x000030C0
+#define DDRSS_CTL_385_DATA 0x00001860
 #define DDRSS_CTL_386_DATA 0x00000200
 #define DDRSS_CTL_387_DATA 0x00000200
 #define DDRSS_CTL_388_DATA 0x00000200
 #define DDRSS_CTL_389_DATA 0x00000200
-#define DDRSS_CTL_390_DATA 0x0000DB60
-#define DDRSS_CTL_391_DATA 0x0001E780
+#define DDRSS_CTL_390_DATA 0x00006DB0
+#define DDRSS_CTL_391_DATA 0x0000F3C0
 #define DDRSS_CTL_392_DATA 0x0C0D0302
 #define DDRSS_CTL_393_DATA 0x001E090A
-#define DDRSS_CTL_394_DATA 0x000030C0
+#define DDRSS_CTL_394_DATA 0x00001860
 #define DDRSS_CTL_395_DATA 0x00000200
 #define DDRSS_CTL_396_DATA 0x00000200
 #define DDRSS_CTL_397_DATA 0x00000200
 #define DDRSS_CTL_398_DATA 0x00000200
-#define DDRSS_CTL_399_DATA 0x0000DB60
-#define DDRSS_CTL_400_DATA 0x0001E780
+#define DDRSS_CTL_399_DATA 0x00006DB0
+#define DDRSS_CTL_400_DATA 0x0000F3C0
 #define DDRSS_CTL_401_DATA 0x0C0D0302
 #define DDRSS_CTL_402_DATA 0x001E090A
-#define DDRSS_CTL_403_DATA 0x000030C0
+#define DDRSS_CTL_403_DATA 0x00001860
 #define DDRSS_CTL_404_DATA 0x00000200
 #define DDRSS_CTL_405_DATA 0x00000200
 #define DDRSS_CTL_406_DATA 0x00000200
 #define DDRSS_CTL_407_DATA 0x00000200
-#define DDRSS_CTL_408_DATA 0x0000DB60
-#define DDRSS_CTL_409_DATA 0x0001E780
+#define DDRSS_CTL_408_DATA 0x00006DB0
+#define DDRSS_CTL_409_DATA 0x0000F3C0
 #define DDRSS_CTL_410_DATA 0x0C0D0302
 #define DDRSS_CTL_411_DATA 0x0000090A
 #define DDRSS_CTL_412_DATA 0x00000000
@@ -607,16 +608,16 @@
 #define DDRSS_PI_168_DATA 0x0000003A
 #define DDRSS_PI_169_DATA 0x0004003A
 #define DDRSS_PI_170_DATA 0x04000400
-#define DDRSS_PI_171_DATA 0x68040009
+#define DDRSS_PI_171_DATA 0xC8040009
 #define DDRSS_PI_172_DATA 0x0400091C
-#define DDRSS_PI_173_DATA 0x00091C68
-#define DDRSS_PI_174_DATA 0x001C6804
+#define DDRSS_PI_173_DATA 0x00091CC8
+#define DDRSS_PI_174_DATA 0x001CC804
 #define DDRSS_PI_175_DATA 0x00000118
-#define DDRSS_PI_176_DATA 0x00001860
+#define DDRSS_PI_176_DATA 0x00000C30
 #define DDRSS_PI_177_DATA 0x00000118
-#define DDRSS_PI_178_DATA 0x00001860
+#define DDRSS_PI_178_DATA 0x00000C30
 #define DDRSS_PI_179_DATA 0x00000118
-#define DDRSS_PI_180_DATA 0x04001860
+#define DDRSS_PI_180_DATA 0x04000C30
 #define DDRSS_PI_181_DATA 0x01010404
 #define DDRSS_PI_182_DATA 0x00001901
 #define DDRSS_PI_183_DATA 0x00190019
@@ -667,28 +668,28 @@
 #define DDRSS_PI_228_DATA 0x1F0F0053
 #define DDRSS_PI_229_DATA 0x05000001
 #define DDRSS_PI_230_DATA 0x00010A0D
-#define DDRSS_PI_231_DATA 0x0D0C0700
+#define DDRSS_PI_231_DATA 0x0C0B0700
 #define DDRSS_PI_232_DATA 0x000D0605
-#define DDRSS_PI_233_DATA 0x0000C570
+#define DDRSS_PI_233_DATA 0x000062B8
 #define DDRSS_PI_234_DATA 0x0000001D
 #define DDRSS_PI_235_DATA 0x180A0800
-#define DDRSS_PI_236_DATA 0x0C071C1C
-#define DDRSS_PI_237_DATA 0x0D06050D
-#define DDRSS_PI_238_DATA 0x0000C570
+#define DDRSS_PI_236_DATA 0x0B071C1C
+#define DDRSS_PI_237_DATA 0x0D06050C
+#define DDRSS_PI_238_DATA 0x000062B8
 #define DDRSS_PI_239_DATA 0x0000001D
 #define DDRSS_PI_240_DATA 0x180A0800
-#define DDRSS_PI_241_DATA 0x0C071C1C
-#define DDRSS_PI_242_DATA 0x0D06050D
-#define DDRSS_PI_243_DATA 0x0000C570
+#define DDRSS_PI_241_DATA 0x0B071C1C
+#define DDRSS_PI_242_DATA 0x0D06050C
+#define DDRSS_PI_243_DATA 0x000062B8
 #define DDRSS_PI_244_DATA 0x0000001D
 #define DDRSS_PI_245_DATA 0x180A0800
 #define DDRSS_PI_246_DATA 0x00001C1C
-#define DDRSS_PI_247_DATA 0x000030C0
-#define DDRSS_PI_248_DATA 0x0001E780
-#define DDRSS_PI_249_DATA 0x000030C0
-#define DDRSS_PI_250_DATA 0x0001E780
-#define DDRSS_PI_251_DATA 0x000030C0
-#define DDRSS_PI_252_DATA 0x0001E780
+#define DDRSS_PI_247_DATA 0x00001860
+#define DDRSS_PI_248_DATA 0x0000F3C0
+#define DDRSS_PI_249_DATA 0x00001860
+#define DDRSS_PI_250_DATA 0x0000F3C0
+#define DDRSS_PI_251_DATA 0x00001860
+#define DDRSS_PI_252_DATA 0x0000F3C0
 #define DDRSS_PI_253_DATA 0x02550255
 #define DDRSS_PI_254_DATA 0x03030255
 #define DDRSS_PI_255_DATA 0x00025503
@@ -735,49 +736,49 @@
 #define DDRSS_PI_296_DATA 0x00000000
 #define DDRSS_PI_297_DATA 0x00000424
 #define DDRSS_PI_298_DATA 0x00000301
-#define DDRSS_PI_299_DATA 0x00000000
+#define DDRSS_PI_299_DATA 0x000000C0
 #define DDRSS_PI_300_DATA 0x00000000
-#define DDRSS_PI_301_DATA 0x00000000
+#define DDRSS_PI_301_DATA 0x0000000C
 #define DDRSS_PI_302_DATA 0x00001401
 #define DDRSS_PI_303_DATA 0x00000493
 #define DDRSS_PI_304_DATA 0x00000000
 #define DDRSS_PI_305_DATA 0x00000424
 #define DDRSS_PI_306_DATA 0x00000301
-#define DDRSS_PI_307_DATA 0x00000000
+#define DDRSS_PI_307_DATA 0x000000C0
 #define DDRSS_PI_308_DATA 0x00000000
-#define DDRSS_PI_309_DATA 0x00000000
+#define DDRSS_PI_309_DATA 0x0000000C
 #define DDRSS_PI_310_DATA 0x00001401
 #define DDRSS_PI_311_DATA 0x00000493
 #define DDRSS_PI_312_DATA 0x00000000
 #define DDRSS_PI_313_DATA 0x00000424
 #define DDRSS_PI_314_DATA 0x00000301
-#define DDRSS_PI_315_DATA 0x00000000
+#define DDRSS_PI_315_DATA 0x000000C0
 #define DDRSS_PI_316_DATA 0x00000000
-#define DDRSS_PI_317_DATA 0x00000000
+#define DDRSS_PI_317_DATA 0x0000000C
 #define DDRSS_PI_318_DATA 0x00001401
 #define DDRSS_PI_319_DATA 0x00000493
 #define DDRSS_PI_320_DATA 0x00000000
 #define DDRSS_PI_321_DATA 0x00000424
 #define DDRSS_PI_322_DATA 0x00000301
-#define DDRSS_PI_323_DATA 0x00000000
+#define DDRSS_PI_323_DATA 0x000000C0
 #define DDRSS_PI_324_DATA 0x00000000
-#define DDRSS_PI_325_DATA 0x00000000
+#define DDRSS_PI_325_DATA 0x0000000C
 #define DDRSS_PI_326_DATA 0x00001401
 #define DDRSS_PI_327_DATA 0x00000493
 #define DDRSS_PI_328_DATA 0x00000000
 #define DDRSS_PI_329_DATA 0x00000424
 #define DDRSS_PI_330_DATA 0x00000301
-#define DDRSS_PI_331_DATA 0x00000000
+#define DDRSS_PI_331_DATA 0x000000C0
 #define DDRSS_PI_332_DATA 0x00000000
-#define DDRSS_PI_333_DATA 0x00000000
+#define DDRSS_PI_333_DATA 0x0000000C
 #define DDRSS_PI_334_DATA 0x00001401
 #define DDRSS_PI_335_DATA 0x00000493
 #define DDRSS_PI_336_DATA 0x00000000
 #define DDRSS_PI_337_DATA 0x00000424
 #define DDRSS_PI_338_DATA 0x00000301
-#define DDRSS_PI_339_DATA 0x00000000
+#define DDRSS_PI_339_DATA 0x000000C0
 #define DDRSS_PI_340_DATA 0x00000000
-#define DDRSS_PI_341_DATA 0x00000000
+#define DDRSS_PI_341_DATA 0x0000000C
 #define DDRSS_PI_342_DATA 0x00001401
 #define DDRSS_PI_343_DATA 0x00000493
 #define DDRSS_PI_344_DATA 0x00000000
@@ -901,7 +902,7 @@
 #define DDRSS_PHY_117_DATA 0x00800080
 #define DDRSS_PHY_118_DATA 0x00800080
 #define DDRSS_PHY_119_DATA 0x01000080
-#define DDRSS_PHY_120_DATA 0x01A00000
+#define DDRSS_PHY_120_DATA 0x01000000
 #define DDRSS_PHY_121_DATA 0x00000000
 #define DDRSS_PHY_122_DATA 0x00000000
 #define DDRSS_PHY_123_DATA 0x00080200
@@ -1157,7 +1158,7 @@
 #define DDRSS_PHY_373_DATA 0x00800080
 #define DDRSS_PHY_374_DATA 0x00800080
 #define DDRSS_PHY_375_DATA 0x01000080
-#define DDRSS_PHY_376_DATA 0x01A00000
+#define DDRSS_PHY_376_DATA 0x01000000
 #define DDRSS_PHY_377_DATA 0x00000000
 #define DDRSS_PHY_378_DATA 0x00000000
 #define DDRSS_PHY_379_DATA 0x00080200
@@ -2115,7 +2116,7 @@
 #define DDRSS_PHY_1331_DATA 0x00004410
 #define DDRSS_PHY_1332_DATA 0x00000000
 #define DDRSS_PHY_1333_DATA 0x00000046
-#define DDRSS_PHY_1334_DATA 0x00010000
+#define DDRSS_PHY_1334_DATA 0x00000400
 #define DDRSS_PHY_1335_DATA 0x00000008
 #define DDRSS_PHY_1336_DATA 0x00000000
 #define DDRSS_PHY_1337_DATA 0x00000000
@@ -2152,7 +2153,7 @@
 #define DDRSS_PHY_1368_DATA 0x00000002
 #define DDRSS_PHY_1369_DATA 0x00000100
 #define DDRSS_PHY_1370_DATA 0x00000000
-#define DDRSS_PHY_1371_DATA 0x0001F7C0
+#define DDRSS_PHY_1371_DATA 0x00000FC3
 #define DDRSS_PHY_1372_DATA 0x00020002
 #define DDRSS_PHY_1373_DATA 0x00000000
 #define DDRSS_PHY_1374_DATA 0x00001142
@@ -2186,4 +2187,4 @@
 #define DDRSS_PHY_1402_DATA 0x01990000
 #define DDRSS_PHY_1403_DATA 0x300D3F11
 #define DDRSS_PHY_1404_DATA 0x01990000
-#define DDRSS_PHY_1405_DATA 0x20040001
+#define DDRSS_PHY_1405_DATA 0x20040004

arch/arm/dts/k3-am642-evm-u-boot.dtsi

@@ -19,10 +19,6 @@
 	dr_mode="peripheral";
 };
 
-&main_mmc1_pins_default {
-	bootph-all;
-};
-
 &sdhci0 {
 	bootph-all;
 };

arch/arm/dts/k3-am642-phyboard-electra-rdk-u-boot.dtsi

@@ -17,34 +17,6 @@
 		stdout-path = "serial2:115200n8";
 		tick-timer = &main_timer0;
 	};
-
-	memory@80000000 {
-		bootph-all;
-	};
-};
-
-&cbass_main {
-	bootph-all;
-};
-
-&dmsc {
-	bootph-all;
-};
-
-&dmss {
-	bootph-all;
-};
-
-&k3_clks {
-	bootph-all;
-};
-
-&k3_pds {
-	bootph-all;
-};
-
-&k3_reset {
-	bootph-all;
 };
 
 &main_bcdma {
@@ -61,68 +33,16 @@
 		    "cfg", "tchan", "rchan";
 };
 
-&main_conf {
-	bootph-all;
-	chipid@14 {
-		bootph-all;
-	};
-};
-
-&main_gpio0 {
-	bootph-all;
-};
-
-&main_i2c0 {
-	bootph-all;
-};
-
-&main_i2c0_pins_default {
-	bootph-all;
-};
-
-&main_mmc1_pins_default {
-	bootph-all;
-};
-
 &main_pktdma {
 	bootph-all;
-	reg = <0x00 0x485c0000 0x00 0x100>,
-	      <0x00 0x4a800000 0x00 0x20000>,
-	      <0x00 0x4aa00000 0x00 0x40000>,
-	      <0x00 0x4b800000 0x00 0x400000>,
-	      <0x00 0x485e0000 0x00 0x20000>,
-	      <0x00 0x484a0000 0x00 0x4000>,
-	      <0x00 0x484c0000 0x00 0x2000>,
-	      <0x00 0x48430000 0x00 0x4000>;
-	reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt", "cfg",
-		    "tchan", "rchan", "rflow";
-};
-
-&main_pmx0 {
-	bootph-all;
 };
 
 &main_timer0 {
-	bootph-all;
 	clock-frequency = <200000000>;
 };
 
-&main_uart0 {
-	bootph-all;
-};
-
-&main_uart0_pins_default {
-	bootph-all;
-};
-
-&main_usb0_pins_default {
-	bootph-all;
-};
-
 &ospi0 {
-	bootph-all;
 	flash@0 {
-		bootph-all;
 		partitions {
 			compatible = "fixed-partitions";
 			#address-cells = <1>;
@@ -152,30 +72,6 @@
 	};
 };
 
-&ospi0_pins_default {
-	bootph-all;
-};
-
 &main_rti1 {
 	status = "disabled";
 };
-
-&sdhci0 {
-	bootph-all;
-};
-
-&sdhci1 {
-	bootph-all;
-};
-
-&secure_proxy_main {
-	bootph-all;
-};
-
-&usbss0 {
-	bootph-all;
-};
-
-&usb0 {
-	bootph-all;
-};

arch/arm/dts/k3-am642-phycore-som-binman.dtsi

@@ -141,6 +141,37 @@
 			#address-cells = <1>;
 
 			images {
+				atf {
+					ti-secure {
+						auth-in-place = <0xa02>;
+
+						firewall-24-5 {
+							insert-template = <&firewall_armv8_atf_fg>;
+							id = <24>;
+							region = <5>;
+						};
+					};
+				};
+
+				tee {
+					ti-secure {
+						auth-in-place = <0xa02>;
+
+						firewall-1-0 {
+							insert-template = <&firewall_bg_3>;
+							id = <1>;
+							region = <0>;
+						};
+
+
+						firewall-1-1 {
+							insert-template = <&firewall_armv8_optee_fg>;
+							id = <1>;
+							region = <1>;
+						};
+					};
+				};
+
 				dm {
 					blob-ext {
 						filename = "/dev/null";

arch/arm/dts/k3-am642-r5-evm.dts

@@ -8,56 +8,7 @@
 #include "k3-am64-ddr.dtsi"
 
 #include "k3-am642-evm-u-boot.dtsi"
-
-/ {
-	aliases {
-		remoteproc0 = &sysctrler;
-		remoteproc1 = &a53_0;
-	};
-
-	a53_0: a53@0 {
-		compatible = "ti,am654-rproc";
-		reg = <0x00 0x00a90000 0x00 0x10>;
-		power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
-				<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
-				<&k3_pds 137 TI_SCI_PD_EXCLUSIVE>;
-		resets = <&k3_reset 135 0>;
-		clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
-		clock-names = "gtc", "core";
-		assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
-		assigned-clock-parents = <&k3_clks 61 2>;
-		assigned-clock-rates = <200000000>, <1000000000>;
-		ti,sci = <&dmsc>;
-		ti,sci-proc-id = <32>;
-		ti,sci-host-id = <10>;
-		bootph-pre-ram;
-	};
-
-	clk_200mhz: dummy-clock-200mhz {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <200000000>;
-		bootph-pre-ram;
-	};
-};
-
-&cbass_main {
-	sysctrler: sysctrler {
-		compatible = "ti,am654-tisci-rproc-r5";
-		mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>;
-		mbox-names = "tx", "rx";
-		bootph-pre-ram;
-	};
-};
-
-&dmsc {
-	mboxes= <&secure_proxy_main 0>,
-		<&secure_proxy_main 1>,
-		<&secure_proxy_main 0>;
-	mbox-names = "rx", "tx", "notify";
-	ti,host-id = <35>;
-	ti,secure-host;
-};
+#include "k3-am642-r5.dtsi"
 
 &memorycontroller {
 	vtt-supply = <&vtt_supply>;
@@ -72,33 +23,3 @@
 	clocks = <&clk_200mhz>;
 	clock-names = "clk_xin";
 };
-
-/* UART is initialized before SYSFW is started
- * so we can't do any power-domain/clock operations.
- * Delete clock/power-domain properties to avoid
- * UART init failure
- */
-&main_uart0 {
-	/delete-property/ power-domains;
-	/delete-property/ clocks;
-	/delete-property/ clock-names;
-};
-
-/* timer init is called as part of rproc_start() while
- * starting System Firmware, so any clock/power-domain
- * operations will fail as SYSFW is not yet up and running.
- * Delete all clock/power-domain properties to avoid
- * timer init failure.
- * This is an always on timer at 20MHz.
- */
-&main_timer0 {
-	/delete-property/ clocks;
-	/delete-property/ assigned-clocks;
-	/delete-property/ assigned-clock-parents;
-	/delete-property/ power-domains;
-};
-
-&ospi0 {
-	reg = <0x00 0x0fc40000 0x00 0x100>,
-	      <0x00 0x60000000 0x00 0x8000000>;
-};

arch/arm/dts/k3-am642-r5-phycore-som-2gb.dts

@@ -14,127 +14,15 @@
 #include "k3-am64-ddr.dtsi"
 
 #include "k3-am642-phyboard-electra-rdk-u-boot.dtsi"
+#include "k3-am642-r5.dtsi"
 
 / {
 	aliases {
 		ethernet0 = &cpsw3g;
-		remoteproc0 = &sysctrler;
-		remoteproc1 = &a53_0;
-	};
-
-	a53_0: a53@0 {
-		compatible = "ti,am654-rproc";
-		reg = <0x00 0x00a90000 0x00 0x10>;
-		power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
-				<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
-				<&k3_pds 137 TI_SCI_PD_EXCLUSIVE>;
-		resets = <&k3_reset 135 0>;
-		clocks = <&k3_clks 61 0>;
-		assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
-		assigned-clock-parents = <&k3_clks 61 2>;
-		assigned-clock-rates = <200000000>, <1000000000>;
-		ti,sci = <&dmsc>;
-		ti,sci-proc-id = <32>;
-		ti,sci-host-id = <10>;
-		bootph-pre-ram;
-	};
-
-	clk_200mhz: dummy-clock-200mhz {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <200000000>;
-		bootph-pre-ram;
-	};
-
-	vtt_supply: vtt-supply {
-		compatible = "regulator-fixed";
-		regulator-name = "vtt";
-		pinctrl-names = "default";
-		pinctrl-0 = <&ddr_vtt_pins_default>;
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		gpios = <&main_gpio0 14 GPIO_ACTIVE_HIGH>;
-		enable-active-high;
-		regulator-always-on;
-		regulator-boot-on;
-		bootph-pre-ram;
 	};
 };
 
-&cbass_main {
-	sysctrler: sysctrler {
-		compatible = "ti,am654-tisci-rproc-r5";
-		mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>;
-		mbox-names = "tx", "rx";
-		bootph-pre-ram;
-	};
-};
-
-&cbass_mcu {
-	bootph-pre-ram;
-};
-
-&dmsc {
-	mboxes= <&secure_proxy_main 0>,
-		<&secure_proxy_main 1>,
-		<&secure_proxy_main 0>;
-	mbox-names = "rx", "tx", "notify";
-	ti,host-id = <35>;
-	ti,secure-host;
-};
-
-&main_esm {
-	bootph-pre-ram;
-};
-
-&main_gpio0 {
-	bootph-pre-ram;
-};
-
-&main_pmx0 {
-	bootph-pre-ram;
-	ddr_vtt_pins_default: ddr-vtt-default-pins {
-		bootph-pre-ram;
-		pinctrl-single,pins = <
-			AM64X_IOPAD(0x0038, PIN_OUTPUT_PULLUP, 7) /* (L18) OSPI0_CSN3.GPIO0_14 */
-		>;
-	};
-};
-
-/* timer init is called as part of rproc_start() while
- * starting System Firmware, so any clock/power-domain
- * operations will fail as SYSFW is not yet up and running.
- * Delete all clock/power-domain properties to avoid
- * timer init failure.
- * This is an always on timer at 20MHz.
- */
-&main_timer0 {
-	/delete-property/ clocks;
-	/delete-property/ assigned-clocks;
-	/delete-property/ assigned-clock-parents;
-	/delete-property/ power-domains;
-};
-
-/* UART is initialized before SYSFW is started
- * so we can't do any power-domain/clock operations.
- * Delete clock/power-domain properties to avoid
- * UART init failure
- */
-&main_uart0 {
-	/delete-property/ power-domains;
-	/delete-property/ clocks;
-	/delete-property/ clock-names;
-};
-
-&mcu_esm {
-	bootph-pre-ram;
-};
-
-&memorycontroller {
-	vtt-supply = <&vtt_supply>;
-};
-
-&ospi0 {
-	reg = <0x00 0x0fc40000 0x00 0x100>,
-	      <0x00 0x60000000 0x00 0x08000000>;
+&a53_0 {
+	clock-names = "gtc";
+	clocks = <&k3_clks 61 0>;
 };

arch/arm/dts/k3-am642-r5-sk.dts

@@ -8,56 +8,7 @@
 #include "k3-am64-ddr.dtsi"
 
 #include "k3-am642-sk-u-boot.dtsi"
-
-/ {
-	aliases {
-		remoteproc0 = &sysctrler;
-		remoteproc1 = &a53_0;
-	};
-
-	a53_0: a53@0 {
-		compatible = "ti,am654-rproc";
-		reg = <0x00 0x00a90000 0x00 0x10>;
-		power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
-				<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
-				<&k3_pds 137 TI_SCI_PD_EXCLUSIVE>;
-		resets = <&k3_reset 135 0>;
-		clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
-		clock-names = "gtc", "core";
-		assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
-		assigned-clock-parents = <&k3_clks 61 2>;
-		assigned-clock-rates = <200000000>, <1000000000>;
-		ti,sci = <&dmsc>;
-		ti,sci-proc-id = <32>;
-		ti,sci-host-id = <10>;
-		bootph-pre-ram;
-	};
-
-	clk_200mhz: dummy-clock-200mhz {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <200000000>;
-		bootph-pre-ram;
-	};
-};
-
-&cbass_main {
-	sysctrler: sysctrler {
-		compatible = "ti,am654-tisci-rproc-r5";
-		mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>;
-		mbox-names = "tx", "rx";
-		bootph-pre-ram;
-	};
-};
-
-&dmsc {
-	mboxes= <&secure_proxy_main 0>,
-		<&secure_proxy_main 1>,
-		<&secure_proxy_main 0>;
-	mbox-names = "rx", "tx", "notify";
-	ti,host-id = <35>;
-	ti,secure-host;
-};
+#include "k3-am642-r5.dtsi"
 
 &sdhci1 {
 	clocks = <&clk_200mhz>;
@@ -67,33 +18,3 @@
 &serdes_wiz0 {
 	status = "okay";
 };
-
-/* UART is initialized before SYSFW is started
- * so we can't do any power-domain/clock operations.
- * Delete clock/power-domain properties to avoid
- * UART init failure
- */
-&main_uart0 {
-	/delete-property/ power-domains;
-	/delete-property/ clocks;
-	/delete-property/ clock-names;
-};
-
-/* timer init is called as part of rproc_start() while
- * starting System Firmware, so any clock/power-domain
- * operations will fail as SYSFW is not yet up and running.
- * Delete all clock/power-domain properties to avoid
- * timer init failure.
- * This is an always on timer at 20MHz.
- */
-&main_timer0 {
-	/delete-property/ clocks;
-	/delete-property/ assigned-clocks;
-	/delete-property/ assigned-clock-parents;
-	/delete-property/ power-domains;
-};
-
-&ospi0 {
-	reg = <0x00 0x0fc40000 0x00 0x100>,
- 	      <0x00 0x60000000 0x00 0x8000000>;
-};

arch/arm/dts/k3-am642-r5.dtsi

@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2026 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/ {
+	aliases {
+		remoteproc0 = &sysctrler;
+		remoteproc1 = &a53_0;
+	};
+
+	a53_0: a53@0 {
+		compatible = "ti,am654-rproc";
+		reg = <0x00 0x00a90000 0x00 0x10>;
+		power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
+				<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
+				<&k3_pds 137 TI_SCI_PD_EXCLUSIVE>;
+		resets = <&k3_reset 135 0>;
+		clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
+		clock-names = "gtc", "core";
+		assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
+		assigned-clock-parents = <&k3_clks 61 2>;
+		assigned-clock-rates = <200000000>, <1000000000>;
+		ti,sci = <&dmsc>;
+		ti,sci-proc-id = <32>;
+		ti,sci-host-id = <10>;
+		bootph-pre-ram;
+	};
+
+	clk_200mhz: dummy-clock-200mhz {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <200000000>;
+		bootph-pre-ram;
+	};
+};
+
+&cbass_main {
+	sysctrler: sysctrler {
+		compatible = "ti,am654-tisci-rproc-r5";
+		mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>;
+		mbox-names = "tx", "rx";
+		bootph-pre-ram;
+	};
+};
+
+&dmsc {
+	mboxes= <&secure_proxy_main 0>,
+		<&secure_proxy_main 1>,
+		<&secure_proxy_main 0>;
+	mbox-names = "rx", "tx", "notify";
+	ti,host-id = <35>;
+	ti,secure-host;
+};
+
+/* UART is initialized before SYSFW is started
+ * so we can't do any power-domain/clock operations.
+ * Delete clock/power-domain properties to avoid
+ * UART init failure
+ */
+&main_uart0 {
+	/delete-property/ power-domains;
+	/delete-property/ clocks;
+	/delete-property/ clock-names;
+};
+
+/* timer init is called as part of rproc_start() while
+ * starting System Firmware, so any clock/power-domain
+ * operations will fail as SYSFW is not yet up and running.
+ * Delete all clock/power-domain properties to avoid
+ * timer init failure.
+ * This is an always on timer at 20MHz.
+ */
+&main_timer0 {
+	/delete-property/ clocks;
+	/delete-property/ assigned-clocks;
+	/delete-property/ assigned-clock-parents;
+	/delete-property/ power-domains;
+};
+
+&ospi0 {
+	reg = <0x00 0x0fc40000 0x00 0x100>,
+	      <0x00 0x60000000 0x00 0x8000000>;
+};

arch/arm/dts/k3-am64x-binman.dtsi

@@ -139,6 +139,37 @@
 			#address-cells = <1>;
 
 			images {
+				atf {
+					ti-secure {
+						auth-in-place = <0xa02>;
+
+						firewall-24-5 {
+							insert-template = <&firewall_armv8_atf_fg>;
+							id = <24>;
+							region = <5>;
+						};
+					};
+				};
+
+				tee {
+					ti-secure {
+						auth-in-place = <0xa02>;
+
+						firewall-1-0 {
+							insert-template = <&firewall_bg_3>;
+							id = <1>;
+							region = <0>;
+						};
+
+
+						firewall-1-1 {
+							insert-template = <&firewall_armv8_optee_fg>;
+							id = <1>;
+							region = <1>;
+						};
+					};
+				};
+
 				dm {
 					blob-ext {
 						filename = "/dev/null";

arch/arm/dts/k3-am654-r5-base-board.dts

@@ -9,74 +9,7 @@
 #include "k3-am654-base-board-u-boot.dtsi"
 #include "k3-am654-base-board-ddr4-1600MTs.dtsi"
 #include "k3-am654-ddr.dtsi"
-
-/ {
-	aliases {
-		remoteproc0 = &sysctrler;
-		remoteproc1 = &a53_0;
-	};
-
-	a53_0: a53@0 {
-		compatible = "ti,am654-rproc";
-		reg = <0x0 0x00a90000 0x0 0x10>;
-		power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
-				<&k3_pds 202 TI_SCI_PD_EXCLUSIVE>;
-		resets = <&k3_reset 202 0>;
-		clocks = <&k3_clks 61 0>, <&k3_clks 202 0>;
-		clock-names = "gtc", "core";
-		assigned-clocks = <&k3_clks 202 0>;
-		assigned-clock-rates = <800000000>;
-		ti,sci = <&dmsc>;
-		ti,sci-proc-id = <32>;
-		ti,sci-host-id = <10>;
-		bootph-pre-ram;
-	};
-
-	clk_200mhz: dummy_clock {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <200000000>;
-		bootph-pre-ram;
-	};
-};
-
-&secure_proxy_mcu {
-	status = "okay";
-	bootph-pre-ram;
-};
-
-&cbass_wakeup {
-	sysctrler: sysctrler {
-		compatible = "ti,am654-tisci-rproc-r5";
-		mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>;
-		mbox-names = "tx", "rx";
-		bootph-pre-ram;
-	};
-};
-
-/*
- * timer init is called as part of rproc_start() while
- * starting System Firmware, so any clock/power-domain
- * operations will fail as SYSFW is not yet up and running.
- * Delete all clock/power-domain properties to avoid
- * timer init failure.
- * This is an always on timer at 20MHz.
- */
-&mcu_timer0 {
-	/delete-property/ clocks;
-	/delete-property/ assigned-clocks;
-	/delete-property/ assigned-clock-parents;
-	/delete-property/ power-domains;
-};
-
-&dmsc {
-	mboxes = <&secure_proxy_mcu 8>,
-		 <&secure_proxy_mcu 6>,
-		 <&secure_proxy_mcu 5>;
-	mbox-names = "tx", "rx", "notify";
-	ti,host-id = <4>;
-	ti,secure-host;
-};
+#include "k3-am654-r5.dtsi"
 
 &wkup_uart0 {
 	status = "okay";
@@ -128,11 +61,6 @@
 	/delete-property/ power-domains;
 };
 
-&ospi0 {
-	reg = <0x0 0x47040000 0x0 0x100>,
-	      <0x0 0x50000000 0x0 0x8000000>;
-};
-
 &dwc3_0 {
 	status = "okay";
 	/delete-property/ clocks;

arch/arm/dts/k3-am654-r5.dtsi

@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2026 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/ {
+	aliases {
+		remoteproc0 = &sysctrler;
+		remoteproc1 = &a53_0;
+	};
+
+	a53_0: a53@0 {
+		compatible = "ti,am654-rproc";
+		reg = <0x0 0x00a90000 0x0 0x10>;
+		power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
+				<&k3_pds 202 TI_SCI_PD_EXCLUSIVE>;
+		resets = <&k3_reset 202 0>;
+		clocks = <&k3_clks 61 0>, <&k3_clks 202 0>;
+		clock-names = "gtc", "core";
+		assigned-clocks = <&k3_clks 202 0>;
+		assigned-clock-rates = <800000000>;
+		ti,sci = <&dmsc>;
+		ti,sci-proc-id = <32>;
+		ti,sci-host-id = <10>;
+		bootph-pre-ram;
+	};
+
+	clk_200mhz: dummy_clock {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <200000000>;
+		bootph-pre-ram;
+	};
+};
+
+&secure_proxy_mcu {
+	status = "okay";
+	bootph-pre-ram;
+};
+
+&cbass_wakeup {
+	sysctrler: sysctrler {
+		compatible = "ti,am654-tisci-rproc-r5";
+		mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>;
+		mbox-names = "tx", "rx";
+		bootph-pre-ram;
+	};
+};
+
+&dmsc {
+	mboxes = <&secure_proxy_mcu 8>,
+		 <&secure_proxy_mcu 6>,
+		 <&secure_proxy_mcu 5>;
+	mbox-names = "tx", "rx", "notify";
+	ti,host-id = <4>;
+	ti,secure-host;
+};
+
+&ospi0 {
+	reg = <0x0 0x47040000 0x0 0x100>,
+	      <0x0 0x50000000 0x0 0x8000000>;
+};
+
+/*
+ * timer init is called as part of rproc_start() while
+ * starting System Firmware, so any clock/power-domain
+ * operations will fail as SYSFW is not yet up and running.
+ * Delete all clock/power-domain properties to avoid
+ * timer init failure.
+ * This is an always on timer at 20MHz.
+ */
+&mcu_timer0 {
+	/delete-property/ clocks;
+	/delete-property/ assigned-clocks;
+	/delete-property/ assigned-clock-parents;
+	/delete-property/ power-domains;
+};

arch/arm/dts/k3-am67a-r5-beagley-ai.dts

@@ -11,72 +11,7 @@
 
 #include "k3-am67a-beagley-ddr-lp4.dtsi"
 #include "k3-am62a-ddr.dtsi"
-
-/ {
-	aliases {
-		remoteproc0 = &sysctrler;
-		remoteproc1 = &a53_0;
-		serial0 = &wkup_uart0;
-		serial2 = &main_uart0;
-	};
-
-	a53_0: a53@0 {
-		compatible = "ti,am654-rproc";
-		reg = <0x00 0x00a90000 0x00 0x10>;
-		power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
-			<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
-			<&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
-		resets = <&k3_reset 135 0>;
-		clocks = <&k3_clks 61 0>;
-		assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
-		assigned-clock-parents = <&k3_clks 61 2>;
-		assigned-clock-rates = <200000000>, <1200000000>;
-		ti,sci = <&dmsc>;
-		ti,sci-proc-id = <32>;
-		ti,sci-host-id = <10>;
-		bootph-all;
-	};
-
-	dm_tifs: dm-tifs {
-		compatible = "ti,j721e-dm-sci";
-		ti,host-id = <36>;
-		ti,secure-host;
-		mbox-names = "rx", "tx";
-		mboxes= <&secure_proxy_main 22>,
-			<&secure_proxy_main 23>;
-		bootph-all;
-	};
-};
-
-&dmsc {
-	mboxes= <&secure_proxy_main 0>,
-		<&secure_proxy_main 1>,
-		<&secure_proxy_main 0>;
-	mbox-names = "rx", "tx", "notify";
-	ti,host-id = <35>;
-	ti,secure-host;
-};
-
-&cbass_main {
-	sa3_secproxy: secproxy@44880000 {
-		compatible = "ti,am654-secure-proxy";
-		#mbox-cells = <1>;
-		reg = <0x00 0x44880000 0x00 0x20000>,
-		      <0x00 0x44860000 0x00 0x20000>,
-		      <0x00 0x43600000 0x00 0x10000>;
-		reg-names = "rt", "scfg", "target_data";
-		bootph-all;
-	};
-
-	sysctrler: sysctrler {
-		compatible = "ti,am654-tisci-rproc-r5";
-		mboxes= <&secure_proxy_main 1>,
-			<&secure_proxy_main 0>,
-			<&sa3_secproxy 0>;
-		mbox-names = "tx", "rx", "boot_notify";
-		bootph-all;
-	};
-};
+#include "k3-am67a-r5.dtsi"
 
 /* WKUP UART0 is used for DM firmware logs */
 &wkup_uart0 {

arch/arm/dts/k3-am67a-r5.dtsi

@@ -0,0 +1,70 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2026 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/ {
+	aliases {
+		remoteproc0 = &sysctrler;
+		remoteproc1 = &a53_0;
+		serial0 = &wkup_uart0;
+		serial2 = &main_uart0;
+	};
+
+	a53_0: a53@0 {
+		compatible = "ti,am654-rproc";
+		reg = <0x00 0x00a90000 0x00 0x10>;
+		power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
+			<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
+			<&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
+		resets = <&k3_reset 135 0>;
+		clocks = <&k3_clks 61 0>;
+		assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
+		assigned-clock-parents = <&k3_clks 61 2>;
+		assigned-clock-rates = <200000000>, <1200000000>;
+		ti,sci = <&dmsc>;
+		ti,sci-proc-id = <32>;
+		ti,sci-host-id = <10>;
+		bootph-all;
+	};
+
+	dm_tifs: dm-tifs {
+		compatible = "ti,j721e-dm-sci";
+		ti,host-id = <36>;
+		ti,secure-host;
+		mbox-names = "rx", "tx";
+		mboxes= <&secure_proxy_main 22>,
+			<&secure_proxy_main 23>;
+		bootph-all;
+	};
+};
+
+&dmsc {
+	mboxes= <&secure_proxy_main 0>,
+		<&secure_proxy_main 1>,
+		<&secure_proxy_main 0>;
+	mbox-names = "rx", "tx", "notify";
+	ti,host-id = <35>;
+	ti,secure-host;
+};
+
+&cbass_main {
+	sa3_secproxy: secproxy@44880000 {
+		compatible = "ti,am654-secure-proxy";
+		#mbox-cells = <1>;
+		reg = <0x00 0x44880000 0x00 0x20000>,
+		      <0x00 0x44860000 0x00 0x20000>,
+		      <0x00 0x43600000 0x00 0x10000>;
+		reg-names = "rt", "scfg", "target_data";
+		bootph-all;
+	};
+
+	sysctrler: sysctrler {
+		compatible = "ti,am654-tisci-rproc-r5";
+		mboxes= <&secure_proxy_main 1>,
+			<&secure_proxy_main 0>,
+			<&sa3_secproxy 0>;
+		mbox-names = "tx", "rx", "boot_notify";
+		bootph-all;
+	};
+};

arch/arm/dts/k3-am68-phyboard-izar-u-boot.dtsi

@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/*
+ * Copyright (C) 2025 PHYTEC Messtechnik GmbH
+ * Author: Dominik Haller <d.haller@phytec.de>
+ *
+ * https://www.phytec.eu/en/produkte/development-kits/phyboard-izar/
+ */
+
+#include "k3-am68-phycore-som-binman.dtsi"
+
+&cbass_main {
+	bootph-all;
+};
+
+&watchdog1 {
+	status = "disabled";
+};
+
+&mcu_uart0 {
+	bootph-all;
+};

arch/arm/dts/k3-am68-phycore-som-binman.dtsi

@@ -0,0 +1,430 @@
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/*
+ * Based on k3-j721s2-binman.dtsi
+ *
+ * Copyright (C) 2025 PHYTEC Messtechnik GmbH
+ * Author: Dominik Haller <d.haller@phytec.de>
+ */
+
+#include "k3-binman.dtsi"
+
+#ifdef CONFIG_TARGET_PHYCORE_AM68X_R5
+
+&binman {
+	tiboot3-am68x-hs-phycore-som.bin {
+		filename = "tiboot3-am68x-hs-phycore-som.bin";
+		ti-secure-rom {
+			content = <&u_boot_spl>, <&ti_fs_enc>, <&combined_tifs_cfg>,
+				<&combined_dm_cfg>, <&sysfw_inner_cert>;
+			combined;
+			dm-data;
+			sysfw-inner-cert;
+			keyfile = "custMpk.pem";
+			sw-rev = <1>;
+			content-sbl = <&u_boot_spl>;
+			content-sysfw = <&ti_fs_enc>;
+			content-sysfw-data = <&combined_tifs_cfg>;
+			content-sysfw-inner-cert = <&sysfw_inner_cert>;
+			content-dm-data = <&combined_dm_cfg>;
+			load = <CONFIG_SPL_TEXT_BASE>;
+			load-sysfw = <0x40000>;
+			load-sysfw-data = <0x67000>;
+			load-dm-data = <0x41c80000>;
+		};
+		u_boot_spl: u-boot-spl {
+			no-expanded;
+		};
+		ti_fs_enc: ti-fs-enc.bin {
+			filename = "ti-sysfw/ti-fs-firmware-j721s2-hs-enc.bin";
+			type = "blob-ext";
+		};
+		combined_tifs_cfg: combined-tifs-cfg.bin {
+			filename = "combined-tifs-cfg.bin";
+			type = "blob-ext";
+		};
+		sysfw_inner_cert: sysfw-inner-cert {
+			filename = "ti-sysfw/ti-fs-firmware-j721s2-hs-cert.bin";
+			type = "blob-ext";
+		};
+		combined_dm_cfg: combined-dm-cfg.bin {
+			filename = "combined-dm-cfg.bin";
+			type = "blob-ext";
+		};
+	};
+};
+
+&binman {
+	tiboot3-am68x-hs-fs-phycore-som.bin {
+		filename = "tiboot3-am68x-hs-fs-phycore-som.bin";
+		ti-secure-rom {
+			content = <&u_boot_spl_fs>, <&ti_fs_enc_fs>, <&combined_tifs_cfg_fs>,
+				<&combined_dm_cfg_fs>, <&sysfw_inner_cert_fs>;
+			combined;
+			dm-data;
+			sysfw-inner-cert;
+			keyfile = "custMpk.pem";
+			sw-rev = <1>;
+			content-sbl = <&u_boot_spl_fs>;
+			content-sysfw = <&ti_fs_enc_fs>;
+			content-sysfw-data = <&combined_tifs_cfg_fs>;
+			content-sysfw-inner-cert = <&sysfw_inner_cert_fs>;
+			content-dm-data = <&combined_dm_cfg_fs>;
+			load = <CONFIG_SPL_TEXT_BASE>;
+			load-sysfw = <0x40000>;
+			load-sysfw-data = <0x67000>;
+			load-dm-data = <0x41c80000>;
+		};
+		u_boot_spl_fs: u-boot-spl {
+			no-expanded;
+		};
+		ti_fs_enc_fs: ti-fs-enc.bin {
+			filename = "ti-sysfw/ti-fs-firmware-j721s2-hs-fs-enc.bin";
+			type = "blob-ext";
+		};
+		combined_tifs_cfg_fs: combined-tifs-cfg.bin {
+			filename = "combined-tifs-cfg.bin";
+			type = "blob-ext";
+		};
+		sysfw_inner_cert_fs: sysfw-inner-cert {
+			filename = "ti-sysfw/ti-fs-firmware-j721s2-hs-fs-cert.bin";
+			type = "blob-ext";
+		};
+		combined_dm_cfg_fs: combined-dm-cfg.bin {
+			filename = "combined-dm-cfg.bin";
+			type = "blob-ext";
+		};
+	};
+};
+
+&binman {
+	tiboot3-am68x-gp-phycore-som.bin {
+		filename = "tiboot3-am68x-gp-phycore-som.bin";
+		symlink = "tiboot3.bin";
+		ti-secure-rom {
+			content = <&u_boot_spl_unsigned>, <&ti_fs_gp>,
+				<&combined_tifs_cfg_gp>, <&combined_dm_cfg_gp>;
+			combined;
+			dm-data;
+			content-sbl = <&u_boot_spl_unsigned>;
+			load = <CONFIG_SPL_TEXT_BASE>;
+			content-sysfw = <&ti_fs_gp>;
+			load-sysfw = <0x40000>;
+			content-sysfw-data = <&combined_tifs_cfg_gp>;
+			load-sysfw-data = <0x67000>;
+			content-dm-data = <&combined_dm_cfg_gp>;
+			load-dm-data = <0x41c80000>;
+			sw-rev = <1>;
+			keyfile = "ti-degenerate-key.pem";
+		};
+		u_boot_spl_unsigned: u-boot-spl {
+			no-expanded;
+		};
+		ti_fs_gp: ti-fs-gp.bin {
+			filename = "ti-sysfw/ti-fs-firmware-j721s2-gp.bin";
+			type = "blob-ext";
+		};
+		combined_tifs_cfg_gp: combined-tifs-cfg-gp.bin {
+			filename = "combined-tifs-cfg.bin";
+			type = "blob-ext";
+		};
+		combined_dm_cfg_gp: combined-dm-cfg-gp.bin {
+			filename = "combined-dm-cfg.bin";
+			type = "blob-ext";
+		};
+
+	};
+};
+
+#endif
+
+#ifdef CONFIG_TARGET_PHYCORE_AM68X_A72
+#define SPL_AM68_PHYBOARD_IZAR_DTB "spl/dts/ti/k3-am68-phyboard-izar.dtb"
+#define AM68_PHYBOARD_IZAR_DTB "u-boot.dtb"
+
+&binman {
+	ti-spl {
+		insert-template = <&ti_spl_template>;
+
+		fit {
+			images {
+				atf {
+					ti-secure {
+						auth-in-place = <0xa02>;
+
+						firewall-257-0 {
+							/* cpu_0_cpu_0_msmc Background Firewall */
+							insert-template = <&firewall_bg_1>;
+							id = <257>;
+							region = <0>;
+						};
+
+						firewall-257-1 {
+							/* cpu_0_cpu_0_msmc Foreground Firewall */
+							insert-template = <&firewall_armv8_atf_fg>;
+							id = <257>;
+							region = <1>;
+						};
+
+						firewall-284-0 {
+							/* dru_0_msmc Background Firewall */
+							insert-template = <&firewall_bg_3>;
+							id = <284>;
+							region = <0>;
+						};
+
+						firewall-284-1 {
+							/* dru_0_msmc Foreground Firewall */
+							insert-template = <&firewall_armv8_atf_fg>;
+							id = <284>;
+							region = <1>;
+						};
+
+						/*	firewall-5140-0 {
+						 *		nb_slv0__mem0 Background Firewall
+						 *		Already configured by the secure entity
+						 *	};
+						 */
+
+						firewall-5140-1 {
+							/* nb_slv0__mem0 Foreground Firewall */
+							insert-template = <&firewall_armv8_atf_fg>;
+							id = <5140>;
+							region = <1>;
+						};
+
+						/*	firewall-5140-0 {
+						 *		nb_slv1__mem0 Background Firewall
+						 *		Already configured by the secure entity
+						 *	};
+						 */
+
+						firewall-5141-1 {
+							/* nb_slv1__mem0 Foreground Firewall */
+							insert-template = <&firewall_armv8_atf_fg>;
+							id = <5141>;
+							region = <1>;
+						};
+
+					};
+				};
+
+				tee {
+					ti-secure {
+						auth-in-place = <0xa02>;
+
+						firewall-257-2 {
+							/* cpu_0_cpu_0_msmc Foreground Firewall */
+							insert-template = <&firewall_armv8_optee_fg>;
+							id = <257>;
+							region = <2>;
+						};
+
+						firewall-284-2 {
+							/* dru_0_msmc Foreground Firewall */
+							insert-template = <&firewall_armv8_optee_fg>;
+							id = <284>;
+							region = <2>;
+						};
+
+						firewall-5142-0 {
+							/* nb_slv2__mem0 Background Firewall - 0 */
+							insert-template = <&firewall_bg_3>;
+							id = <5142>;
+							region = <0>;
+						};
+
+						firewall-5142-1 {
+							/* nb_slv2__mem0 Foreground Firewall */
+							insert-template = <&firewall_armv8_optee_fg>;
+							id = <5142>;
+							region = <1>;
+						};
+
+						firewall-5143-0 {
+							/* nb_slv3__mem0 Background Firewall - 0 */
+							insert-template = <&firewall_bg_3>;
+							id = <5143>;
+							region = <0>;
+						};
+
+						firewall-5143-1 {
+							/* nb_slv3__mem0 Foreground Firewall */
+							insert-template = <&firewall_armv8_optee_fg>;
+							id = <5143>;
+							region = <1>;
+						};
+
+						firewall-5144-0 {
+							/* nb_slv4__mem0 Background Firewall - 0 */
+							insert-template = <&firewall_bg_3>;
+							id = <5144>;
+							region = <0>;
+						};
+
+						firewall-5144-1 {
+							/* nb_slv4__mem0 Foreground Firewall */
+							insert-template = <&firewall_armv8_optee_fg>;
+							id = <5144>;
+							region = <1>;
+						};
+
+					};
+				};
+				dm {
+					ti-secure {
+						content = <&dm>;
+						keyfile = "custMpk.pem";
+					};
+					dm: ti-dm {
+						filename = "ti-dm/j721s2/ipc_echo_testb_mcu1_0_release_strip.xer5f";
+					};
+				};
+
+				fdt-0 {
+					description = "k3-am68-phyboard-izar";
+					type = "flat_dt";
+					arch = "arm";
+					compression = "none";
+					ti-secure {
+						content = <&spl_am68_phyboard_izar_dtb>;
+						keyfile = "custMpk.pem";
+					};
+					spl_am68_phyboard_izar_dtb: blob-ext {
+						filename = SPL_AM68_PHYBOARD_IZAR_DTB;
+					};
+
+				};
+			};
+
+			configurations {
+				default = "conf-0";
+
+				conf-0 {
+					description = "k3-am68-phyboard-izar";
+					firmware = "atf";
+					loadables = "tee", "dm", "spl";
+					fdt = "fdt-0";
+				};
+			};
+		};
+	};
+};
+
+&binman {
+	u-boot {
+		insert-template = <&u_boot_template>;
+
+		fit {
+			images {
+				uboot {
+					description = "U-Boot for phyBOARD Izar AM68x";
+				};
+
+				fdt-0 {
+					description = "k3-am68-phyboard-izar";
+					type = "flat_dt";
+					arch = "arm";
+					compression = "none";
+					ti-secure {
+						content = <&am68_phyboard_izar_dtb>;
+						keyfile = "custMpk.pem";
+					};
+					am68_phyboard_izar_dtb: blob-ext {
+						filename = AM68_PHYBOARD_IZAR_DTB;
+					};
+
+					hash {
+						algo = "crc32";
+					};
+				};
+			};
+
+			configurations {
+				default = "conf-0";
+
+				conf-0 {
+					description = "k3-am68-phyboard-izar";
+					firmware = "uboot";
+					loadables = "uboot";
+					fdt = "fdt-0";
+				};
+			};
+		};
+	};
+};
+
+&binman {
+	ti-spl_unsigned {
+		insert-template = <&ti_spl_unsigned_template>;
+
+		fit {
+			images {
+				dm {
+					ti-dm {
+						filename = "ti-dm/j721s2/ipc_echo_testb_mcu1_0_release_strip.xer5f";
+					};
+				};
+
+				fdt-0 {
+					description = "k3-am68-phyboard-izar";
+					type = "flat_dt";
+					arch = "arm";
+					compression = "none";
+					spl_am68_phyboard_izar_dtb_unsigned: blob {
+						filename = SPL_AM68_PHYBOARD_IZAR_DTB;
+					};
+				};
+			};
+
+			configurations {
+				default = "conf-0";
+
+				conf-0 {
+					description = "k3-am68-phyboard-izar";
+					firmware = "atf";
+					loadables = "tee", "dm", "spl";
+					fdt = "fdt-0";
+				};
+			};
+		};
+	};
+};
+
+&binman {
+	u-boot_unsigned {
+		insert-template = <&u_boot_unsigned_template>;
+
+		fit {
+			images {
+				uboot {
+					description = "U-Boot for phyBOARD Izar AM68x";
+				};
+
+				fdt-0 {
+					description = "k3-am68-phyboard-izar";
+					type = "flat_dt";
+					arch = "arm";
+					compression = "none";
+					am68_phyboard_izar_unsigned: blob {
+						filename = AM68_PHYBOARD_IZAR_DTB;
+					};
+					hash {
+						algo = "crc32";
+					};
+				};
+			};
+
+			configurations {
+				default = "conf-0";
+
+				conf-0 {
+					description = "k3-am68-phyboard-izar";
+					firmware = "uboot";
+					loadables = "uboot";
+					fdt = "fdt-0";
+				};
+			};
+		};
+	};
+};
+#endif

arch/arm/dts/k3-am68-r5-phycore-som-4gb.dts

@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/*
+ * Copyright (C) 2025 PHYTEC Messtechnik GmbH
+ * Author: Dominik Haller <d.haller@phytec.de>
+ *
+ * https://www.phytec.eu/en/produkte/development-kits/phyboard-izar/
+ */
+
+/dts-v1/;
+
+#include "k3-am68-phyboard-izar.dts"
+#include "k3-am68-ddr-phycore-som-lp4-4266-4gb.dtsi"
+#include "k3-j721s2-ddr.dtsi"
+#include "k3-am68-phyboard-izar-u-boot.dtsi"
+#include "k3-j721s2-r5.dtsi"
+
+&wkup_vtm0 {
+	bootph-pre-ram;
+	vdd-supply-2 = <&vdd_cpu_avs>;
+};

arch/arm/dts/k3-am69-aquila-dev-u-boot.dtsi

@@ -0,0 +1,158 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (C) 2025 Toradex - https://www.toradex.com/
+ */
+
+#define SPL_BOARD_DTB "spl/dts/k3-am69-aquila-dev.dtb"
+#define BOARD_DESCRIPTION "k3-am69-aquila"
+#define UBOOT_BOARD_DESCRIPTION "U-Boot for AM69 Aquila board"
+
+#include "k3-j784s4-binman.dtsi"
+
+#if defined(CONFIG_CPU_V7R)
+
+&binman {
+	tiboot3-am69-hs {
+		insert-template = <&tiboot3_j784s4_hs>;
+		filename = "tiboot3-am69-hs-aquila.bin";
+	};
+
+	tiboot3-am69-hs-fs {
+		insert-template = <&tiboot3_j784s4_hs_fs>;
+		filename = "tiboot3-am69-hs-fs-aquila.bin";
+		symlink = "tiboot3.bin";
+	};
+};
+
+&ti_fs_enc {
+	filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-enc.bin";
+};
+
+&sysfw_inner_cert {
+	filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-cert.bin";
+};
+
+&ti_fs_enc_fs {
+	filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-fs-enc.bin";
+};
+
+&sysfw_inner_cert_fs {
+	filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-fs-cert.bin";
+};
+
+#else // CONFIG_ARM64
+
+&binman {
+	tispl {
+		insert-template = <&ti_spl>;
+
+		fit {
+			images {
+				dm {
+					ti-dm {
+						filename = "ti-dm/j784s4/ipc_echo_testb_mcu1_0_release_strip.xer5f";
+					};
+				};
+			};
+		};
+	};
+
+	u-boot {
+		insert-template = <&u_boot>;
+	};
+
+	tispl-unsigned {
+		insert-template = <&ti_spl_unsigned>;
+
+		fit {
+			images {
+				dm {
+					ti-dm {
+						filename = "ti-dm/j784s4/ipc_echo_testb_mcu1_0_release_strip.xer5f";
+					};
+				};
+			};
+		};
+	};
+
+	u-boot-unsigned {
+		insert-template = <&u_boot_unsigned>;
+	};
+};
+
+#endif
+
+/ {
+	memory@80000000 {
+		bootph-all;
+	};
+
+	sysinfo {
+		compatible = "toradex,sysinfo";
+	};
+};
+
+&main_pmx0 {
+	bootph-pre-ram;
+};
+
+&main_sdhci0 {
+	bootph-pre-ram;
+};
+
+&main_uart8 {
+	bootph-pre-ram;
+};
+
+&mcu_udmap {
+	reg =   <0x0 0x285c0000 0x0 0x100>,
+		<0x0 0x284c0000 0x0 0x4000>,
+		<0x0 0x2a800000 0x0 0x40000>,
+		<0x0 0x284a0000 0x0 0x4000>,
+		<0x0 0x2aa00000 0x0 0x40000>,
+		<0x0 0x28400000 0x0 0x2000>;
+	reg-names = "gcfg", "rchan", "rchanrt", "tchan",
+		    "tchanrt", "rflow";
+	bootph-pre-ram;
+};
+
+&pinctrl_main_uart8 {
+	bootph-pre-ram;
+};
+
+&pinctrl_wkup_i2c0 {
+	bootph-pre-ram;
+};
+
+&pmic_tps6594 {
+	bootph-pre-ram;
+	regulators {
+		bootph-pre-ram;
+	};
+};
+
+&tps62873a {
+	bootph-pre-ram;
+};
+
+&usb0 {
+	/delete-property/ phys;
+	/delete-property/ phy-names;
+	dr_mode = "peripheral";
+	maximum-speed = "high-speed";
+	bootph-pre-ram;
+};
+
+&usbss0 {
+	ti,modestrap-peripheral;
+	ti,usb2-only;
+	bootph-pre-ram;
+};
+
+&wkup_gpio0 {
+	bootph-pre-ram;
+};
+
+&wkup_i2c0 {
+	bootph-pre-ram;
+};

arch/arm/dts/k3-am69-aquila-dev.dts

@@ -0,0 +1,576 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (C) 2025 Toradex
+ *
+ * https://www.toradex.com/computer-on-modules/aquila-arm-family/ti-am69
+ * https://www.toradex.com/products/carrier-board/aquila-development-board-kit
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/pwm/pwm.h>
+#include "k3-am69-aquila.dtsi"
+
+/ {
+	model = "Toradex Aquila AM69 on Aquila Development Board";
+	compatible = "toradex,aquila-am69-dev",
+		     "toradex,aquila-am69",
+		     "ti,j784s4";
+
+	aliases {
+		eeprom1 = &carrier_eeprom;
+	};
+
+	reg_1v8_sw: regulator-1v8-sw {
+		compatible = "regulator-fixed";
+		regulator-max-microvolt = <1800000>;
+		regulator-min-microvolt = <1800000>;
+		regulator-name = "Carrier_1V8";
+	};
+
+	reg_3v3_dp: regulator-3v3-dp {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_gpio_21_dp>;
+		/* Aquila GPIO_21_DP (AQUILA B57) */
+		gpio = <&main_gpio0 37 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		regulator-max-microvolt = <3300000>;
+		regulator-min-microvolt = <3300000>;
+		regulator-name = "DP_3V3";
+		startup-delay-us = <10000>;
+	};
+
+	dp0-connector {
+		compatible = "dp-connector";
+		dp-pwr-supply = <&reg_3v3_dp>;
+		label = "Display Port";
+		type = "full-size";
+
+		port {
+			dp0_connector_in: endpoint {
+				remote-endpoint = <&dp0_out>;
+			};
+		};
+	};
+
+	sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,bitclock-master = <&codec_dai>;
+		simple-audio-card,format = "i2s";
+		simple-audio-card,frame-master = <&codec_dai>;
+		simple-audio-card,name = "aquila-wm8904";
+		simple-audio-card,mclk-fs = <256>;
+		simple-audio-card,routing =
+			"Headphone Jack", "HPOUTL",
+			"Headphone Jack", "HPOUTR",
+			"IN2L", "Line In Jack",
+			"IN2R", "Line In Jack",
+			"Microphone Jack", "MICBIAS",
+			"IN1L", "Microphone Jack",
+			"IN1R", "Digital Mic";
+		simple-audio-card,widgets =
+			"Microphone", "Microphone Jack",
+			"Microphone", "Digital Mic",
+			"Headphone", "Headphone Jack",
+			"Line", "Line In Jack";
+
+		codec_dai: simple-audio-card,codec {
+			sound-dai = <&wm8904_1a>;
+		};
+
+		simple-audio-card,cpu {
+			sound-dai = <&mcasp4>;
+		};
+	};
+};
+
+/* Aquila CTRL_PWR_BTN_MICO# */
+&aquila_key_power {
+	status = "okay";
+};
+
+/* Aquila CTRL_WAKE1_MICO# */
+&aquila_key_wake {
+	status = "okay";
+};
+
+/* On-module ETH_1 MDIO */
+&davinci_mdio {
+	status = "okay";
+};
+
+&dp0_ports {
+	port@4 {
+		reg = <4>;
+		dp0_out: endpoint {
+			remote-endpoint = <&dp0_connector_in>;
+		};
+	};
+};
+
+&dss {
+	status = "okay";
+};
+
+&main0_thermal {
+	cooling-maps {
+		map0 {
+			cooling-device = <&fan 1 1>;
+			trip = <&main0_alert0>;
+		};
+
+		map1 {
+			cooling-device = <&fan 2 2>;
+			trip = <&main0_alert1>;
+		};
+	};
+};
+
+&main1_thermal {
+	cooling-maps {
+		map0 {
+			cooling-device = <&fan 1 1>;
+			trip = <&main1_alert0>;
+		};
+
+		map1 {
+			cooling-device = <&fan 2 2>;
+			trip = <&main1_alert1>;
+		};
+	};
+};
+
+&main2_thermal {
+	cooling-maps {
+		map0 {
+			cooling-device = <&fan 1 1>;
+			trip = <&main2_alert0>;
+		};
+
+		map1 {
+			cooling-device = <&fan 2 2>;
+			trip = <&main2_alert1>;
+		};
+	};
+};
+
+&main3_thermal {
+	cooling-maps {
+		map0 {
+			cooling-device = <&fan 1 1>;
+			trip = <&main3_alert0>;
+		};
+
+		map1 {
+			cooling-device = <&fan 2 2>;
+			trip = <&main3_alert1>;
+		};
+	};
+};
+
+&main4_thermal {
+	cooling-maps {
+		map0 {
+			cooling-device = <&fan 1 1>;
+			trip = <&main4_alert0>;
+		};
+
+		map1 {
+			cooling-device = <&fan 2 2>;
+			trip = <&main4_alert1>;
+		};
+	};
+};
+
+/* Aquila ETH_2 */
+&main_cpsw0 {
+	status = "okay";
+};
+
+/* Aquila ETH_2 SGMII PHY */
+&main_cpsw0_port8 {
+	phy-handle = <&cpsw0_port8_phy4>;
+	status = "okay";
+};
+
+/* Aquila ETH_2_XGMII_MDIO */
+&main_cpsw0_mdio {
+	status = "okay";
+
+	cpsw0_port8_phy4: ethernet-phy@4 {
+		reg = <4>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_eth2_int>;
+		interrupt-parent = <&main_gpio0>;
+		interrupts = <44 IRQ_TYPE_EDGE_FALLING>;
+	};
+};
+
+/* Aquila PWM_1 */
+&main_ehrpwm0 {
+	status = "okay";
+};
+
+/* Aquila PWM_4_DP */
+&main_ehrpwm2 {
+	status = "okay";
+};
+
+/* Aquila PWM_2 */
+&main_ehrpwm1 {
+	status = "okay";
+};
+
+/* Aquila PWM_3_DSI */
+&main_ehrpwm5 {
+	status = "okay";
+};
+
+&main_gpio0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gpio_01>,  /* Aquila GPIO_01 */
+		    <&pinctrl_gpio_02>,  /* Aquila GPIO_02 */
+		    <&pinctrl_gpio_03>;  /* Aquila GPIO_03 */
+};
+
+/* Aquila I2C_3_DSI1 */
+&main_i2c0 {
+	status = "okay";
+
+	i2c-mux@70 {
+		compatible = "nxp,pca9543";
+		reg = <0x70>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		/* I2C on DSI Connector Pin #4 and #6 */
+		i2c_dsi_0: i2c@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		/* I2C on DSI Connector Pin #52 and #54 */
+		i2c_dsi_1: i2c@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+	};
+};
+
+/* Aquila I2C_4_CSI1 */
+&main_i2c1 {
+	status = "okay";
+};
+
+/* Aquila I2C_5_CSI2 */
+&main_i2c2 {
+	status = "okay";
+};
+
+/* Aquila I2C_6 */
+&main_i2c5 {
+	status = "okay";
+};
+
+/* Aquila CAN_1 */
+&main_mcan10 {
+	status = "okay";
+};
+
+/* Aquila CAN_3 */
+&main_mcan13 {
+	status = "okay";
+};
+
+/* Aquila SD_1 */
+&main_sdhci1 {
+	status = "okay";
+};
+
+/* Aquila SPI_2 */
+&main_spi0 {
+	status = "okay";
+};
+
+/* Aquila SPI_1 */
+&main_spi2 {
+	status = "okay";
+};
+
+/* Aquila UART_1 */
+&main_uart4 {
+	status = "okay";
+};
+
+/* Aquila UART_3, used as the Linux console */
+&main_uart8 {
+	status = "okay";
+};
+
+/* Aquila I2S_1 */
+&mcasp4 {
+	status = "okay";
+};
+
+&mcu_cpsw {
+	status = "okay";
+};
+
+/* On-module ETH_1 RGMII */
+&mcu_cpsw_port1 {
+	status = "okay";
+};
+
+/* Aquila I2C_1 */
+&mcu_i2c0 {
+	clock-frequency = <100000>;
+	status = "okay";
+
+	fan_controller: fan@18 {
+		compatible = "ti,amc6821";
+		reg = <0x18>;
+		#pwm-cells = <2>;
+
+		fan: fan {
+			cooling-levels = <102 179 255>;
+			#cooling-cells = <2>;
+			pwms = <&fan_controller 40000 PWM_POLARITY_INVERTED>;
+		};
+	};
+
+	wm8904_1a: audio-codec@1a {
+		compatible = "wlf,wm8904";
+		reg = <0x1a>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_audio_extrefclk1>;
+		#sound-dai-cells = <0>;
+		clocks = <&audio_refclk1>;
+		clock-names = "mclk";
+		AVDD-supply = <&reg_1v8_sw>;
+		CPVDD-supply = <&reg_1v8_sw>;
+		DBVDD-supply = <&reg_1v8_sw>;
+		DCVDD-supply = <&reg_1v8_sw>;
+		MICVDD-supply = <&reg_1v8_sw>;
+
+		wlf,drc-cfg-names = "default", "peaklimiter";
+		/*
+		 * Config registers per name, respectively:
+		 * KNEE_IP = 0,   KNEE_OP = 0,     HI_COMP = 1,   LO_COMP = 1
+		 * KNEE_IP = -24, KNEE_OP = -6,    HI_COMP = 1/4, LO_COMP = 1
+		 */
+		wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>,
+				   /bits/ 16 <0x04af 0x324b 0x0010 0x0408>;
+
+		/* GPIO1 = DMIC_CLK, don't touch others */
+		wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>;
+
+		wlf,in1r-as-dmicdat2;
+	};
+
+	/* Current measurement into module VCC */
+	hwmon@41 {
+		compatible = "ti,ina226";
+		reg = <0x41>;
+		shunt-resistor = <5000>;
+	};
+
+	temperature-sensor@4f {
+		compatible = "ti,tmp1075";
+		reg = <0x4f>;
+	};
+
+	/* USB-C OTG (TCPC USB PD PHY) */
+	tcpc@52 {
+		compatible = "nxp,ptn5110", "tcpci";
+		reg = <0x52>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_usb1_int>;
+		interrupt-parent = <&main_gpio0>;
+		interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
+
+		connector {
+			compatible = "usb-c-connector";
+			data-role = "dual";
+			label = "USB-C OTG";
+			power-role = "dual";
+			try-power-role = "sink";
+			self-powered;
+			source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+			sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+			op-sink-microwatt = <1000000>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					usb_1_con_hs: endpoint {
+						remote-endpoint = <&usb0_hs>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					usb_1_con_ss: endpoint {
+						remote-endpoint = <&usb0_ss_mux>;
+					};
+				};
+			};
+		};
+	};
+
+	carrier_eeprom: eeprom@57 {
+		compatible = "st,24c02", "atmel,24c02";
+		reg = <0x57>;
+		pagesize = <16>;
+	};
+};
+
+/* Aquila I2C_2 */
+&mcu_i2c1 {
+	status = "okay";
+};
+
+/* Aquila CAN_2 */
+&mcu_mcan0 {
+	status = "okay";
+};
+
+/* Aquila CAN_4 */
+&mcu_mcan1 {
+	status = "okay";
+};
+
+/* Aquila UART_4 */
+&mcu_uart0 {
+	status = "okay";
+};
+
+&mhdp {
+	status = "okay";
+};
+
+/* Aquila QSPI_1 */
+&ospi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_mcu_ospi0_4bit>, <&pinctrl_mcu_ospi0_cs0>;
+	status = "okay";
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0x0>;
+		spi-max-frequency = <66000000>;
+		spi-rx-bus-width = <4>;
+		spi-tx-bus-width = <4>;
+		cdns,read-delay = <0>;
+		cdns,tchsh-ns = <3>;
+		cdns,tsd2d-ns = <10>;
+		cdns,tshsl-ns = <30>;
+		cdns,tslch-ns = <8>;
+	};
+};
+
+/* Aquila PCIE_1 */
+&pcie0_rc {
+	status = "okay";
+};
+
+/* Aquila PCIE_2 */
+&pcie1_rc {
+	status = "okay";
+};
+
+&serdes2 {
+	status = "okay";
+};
+
+&serdes4 {
+	status = "okay";
+};
+
+&serdes_wiz2 {
+	status = "okay";
+};
+
+&serdes_wiz4 {
+	status = "okay";
+};
+
+/* Aquila ADC_[1-4] */
+&tscadc0 {
+	status = "okay";
+};
+
+&usbss0 {
+	status = "okay";
+};
+
+&usb0ss_mux {
+	status = "okay";
+
+	port {
+		usb0_ss_mux: endpoint {
+			remote-endpoint = <&usb_1_con_ss>;
+		};
+	};
+};
+
+&usb0 {
+	status = "okay";
+
+	port {
+		usb0_hs: endpoint {
+			remote-endpoint = <&usb_1_con_hs>;
+		};
+	};
+};
+
+&wkup0_thermal {
+	cooling-maps {
+		map0 {
+			cooling-device = <&fan 1 1>;
+			trip = <&wkup0_alert0>;
+		};
+
+		map1 {
+			cooling-device = <&fan 2 2>;
+			trip = <&wkup0_alert1>;
+		};
+	};
+};
+
+&wkup1_thermal {
+	cooling-maps {
+		map0 {
+			cooling-device = <&fan 1 1>;
+			trip = <&wkup1_alert0>;
+		};
+
+		map1 {
+			cooling-device = <&fan 2 2>;
+			trip = <&wkup1_alert1>;
+		};
+	};
+};
+
+&wkup_gpio0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gpio_04>,       /* Aquila GPIO_04 */
+		    <&pinctrl_gpio_05>,       /* Aquila GPIO_05 */
+		    <&pinctrl_gpio_06>,       /* Aquila GPIO_06 */
+		    <&pinctrl_gpio_07>,       /* Aquila GPIO_07 */
+		    <&pinctrl_gpio_08>;       /* Aquila GPIO_08 */
+};
+
+/* Aquila UART_2, through RS485 transceiver */
+&wkup_uart0 {
+	linux,rs485-enabled-at-boot-time;
+	rs485-rx-during-tx;
+	status = "okay";
+};