CI: Sage: Drop rpi_arm64 lwIP variants

With commit 17ceb774a1 ("rpi_arm64: Enable MBEDTLS/LWIP/WGET and
WGET_HTTPS"), we can drop the tests for switching from the legacy stack
to lwIP.

Signed-off-by: Tom Rini <trini@konsulko.com>

.gitlab-ci-sage-lab.yml

@@ -153,20 +153,13 @@ Raspberry Pi 4 (rpi_arm64):
     LABGRID_EXPORTER: "sage-exporter-rpi4-1"
     LG_PLACE: "rpi4-1"
     TEST_PY_BD: "rpi_arm64"
-    OVERRIDE: "-a UNIT_TEST -a ~CMD_EFIDEBUG -a CMD_BOOTMENU -a CMD_LOG -a ~CMD_BOOTEFI_SELFTEST -a CMD_TFTPPUT -a FIT -a FIT_SIGNATURE -a FIT_BEST_MATCH -a SYS_BOOTM_LEN=0x4000000 -a BOOTSTAGE -a BOOTSTAGE_STASH -a CMD_BOOTSTAGE -a BOOTSTAGE_STASH_ADDR=0x02400000"
-
-Raspberry Pi 4 (rpi_arm64, lwIP):
-  <<: *sage_lab_dfn
-  needs: [ "Raspberry Pi 4 (rpi_arm64)" ]
-  variables:
-    LABGRID_EXPORTER: "sage-exporter-rpi4-1"
-    LG_PLACE: "rpi4-1"
-    TEST_PY_BD: "rpi_arm64"
-    OVERRIDE: "-a UNIT_TEST -a ~CMD_EFIDEBUG -a CMD_BOOTMENU -a CMD_LOG -a ~CMD_BOOTEFI_SELFTEST -a FIT -a FIT_SIGNATURE -a FIT_BEST_MATCH -a SYS_BOOTM_LEN=0x4000000 -a BOOTSTAGE -a BOOTSTAGE_STASH -a CMD_BOOTSTAGE -a BOOTSTAGE_STASH_ADDR=0x02400000 -a NET_LWIP"
+    # DHCP is not being run first, needs to be investigated.
+    TEST_PY_TEST_SPEC: "not test_efi_helloworld_net_http"
+    OVERRIDE: "-a UNIT_TEST -a ~CMD_EFIDEBUG -a CMD_BOOTMENU -a CMD_LOG -a ~CMD_BOOTEFI_SELFTEST -a FIT -a FIT_SIGNATURE -a FIT_BEST_MATCH -a SYS_BOOTM_LEN=0x4000000 -a BOOTSTAGE -a BOOTSTAGE_STASH -a CMD_BOOTSTAGE -a BOOTSTAGE_STASH_ADDR=0x02400000"
 
 Raspberry Pi 4 (rpi_4_32b):
   <<: *sage_lab_dfn
-  needs: [ "Raspberry Pi 4 (rpi_arm64, lwIP)" ]
+  needs: [ "Raspberry Pi 4 (rpi_arm64)" ]
   variables:
     LABGRID_EXPORTER: "sage-exporter-rpi4-1"
     LG_PLACE: "rpi4-1"
@@ -197,20 +190,13 @@ Raspberry Pi 3 (rpi_arm64):
     LABGRID_EXPORTER: "sage-exporter-rpi3-1"
     LG_PLACE: "rpi3-1"
     TEST_PY_BD: "rpi_arm64"
-    OVERRIDE: "-a UNIT_TEST -a ~CMD_EFIDEBUG -a CMD_BOOTMENU -a CMD_LOG -a ~CMD_BOOTEFI_SELFTEST -a CMD_TFTPPUT -a FIT -a FIT_SIGNATURE -a FIT_BEST_MATCH -a SYS_BOOTM_LEN=0x4000000 -a BOOTSTAGE -a BOOTSTAGE_STASH -a CMD_BOOTSTAGE -a BOOTSTAGE_STASH_ADDR=0x02400000"
-
-Raspberry Pi 3 (rpi_arm64, lwIP):
-  <<: *sage_lab_dfn
-  needs: [ "Raspberry Pi 3 (rpi_arm64)" ]
-  variables:
-    LABGRID_EXPORTER: "sage-exporter-rpi3-1"
-    LG_PLACE: "rpi3-1"
-    TEST_PY_BD: "rpi_arm64"
-    OVERRIDE: "-a UNIT_TEST -a ~CMD_EFIDEBUG -a CMD_BOOTMENU -a CMD_LOG -a ~CMD_BOOTEFI_SELFTEST -a FIT -a FIT_SIGNATURE -a FIT_BEST_MATCH -a SYS_BOOTM_LEN=0x4000000 -a BOOTSTAGE -a BOOTSTAGE_STASH -a CMD_BOOTSTAGE -a BOOTSTAGE_STASH_ADDR=0x02400000 -a NET_LWIP"
+    # DHCP is not being run first, needs to be investigated.
+    TEST_PY_TEST_SPEC: "not test_efi_helloworld_net_http"
+    OVERRIDE: "-a UNIT_TEST -a ~CMD_EFIDEBUG -a CMD_BOOTMENU -a CMD_LOG -a ~CMD_BOOTEFI_SELFTEST -a FIT -a FIT_SIGNATURE -a FIT_BEST_MATCH -a SYS_BOOTM_LEN=0x4000000 -a BOOTSTAGE -a BOOTSTAGE_STASH -a CMD_BOOTSTAGE -a BOOTSTAGE_STASH_ADDR=0x02400000"
 
 Raspberry Pi 3 (rpi_3_32b):
   <<: *sage_lab_dfn
-  needs: [ "Raspberry Pi 3 (rpi_arm64, lwIP)" ]
+  needs: [ "Raspberry Pi 3 (rpi_arm64)" ]
   variables:
     LABGRID_EXPORTER: "sage-exporter-rpi3-1"
     LG_PLACE: "rpi3-1"

MAINTAINERS

@@ -133,15 +133,22 @@ F:	drivers/mmc/snps_dw_mmc.c
 
 APPLE M1 SOC SUPPORT
 M:	Mark Kettenis <kettenis@openbsd.org>
+R:	Janne Grunau <j@jannau.net>
 S:	Maintained
 F:	arch/arm/include/asm/arch-apple/
 F:	arch/arm/mach-apple/
+F:	board/apple/
 F:	configs/apple_m1_defconfig
+F:	doc/board/apple/
+F:	drivers/input/apple_spi_kbd.c
 F:	drivers/iommu/apple_dart.c
+F:	drivers/mailbox/apple-mbox.c
 F:	drivers/nvme/nvme_apple.c
 F:	drivers/pci/pcie_apple.c
 F:	drivers/phy/phy-apple-atc.c
 F:	drivers/pinctrl/pinctrl-apple.c
+F:	drivers/power/domain/apple-pmgr.c
+F:	drivers/spi/apple_spi.c
 F:	drivers/watchdog/apple_wdt.c
 F:	include/configs/apple.h
 
@@ -1109,7 +1116,7 @@ EFI CLIENT
 M:	Simon Glass <sjg@chromium.org>
 M:	Heinrich Schuchardt <xypron.glpk@gmx.de>
 S:	Maintained
-W:	https://docs.u-boot.org/en/latest/develop/uefi/u-boot_on_efi.html
+W:	https://docs.u-boot-project.org/en/latest/develop/uefi/u-boot_on_efi.html
 F:	board/efi/efi-x86_app
 F:	configs/efi-x86_app*
 F:	doc/develop/uefi/u-boot_on_efi.rst
@@ -1499,6 +1506,7 @@ T:	git https://source.denx.de/u-boot/custodians/u-boot-nios.git
 F:	arch/nios2/
 
 NVMe
+M:	Neil Armstrong <neil.armstrong@linaro.org>
 M:	Bin Meng <bmeng.cn@gmail.com>
 S:	Maintained
 F:	drivers/nvme/

Makefile

@@ -3,7 +3,7 @@
 VERSION = 2026
 PATCHLEVEL = 07
 SUBLEVEL =
-EXTRAVERSION = -rc2
+EXTRAVERSION = -rc3
 NAME =
 
 # *DOCUMENTATION*
@@ -1578,6 +1578,9 @@ spl/u-boot-spl.srec: spl/u-boot-spl FORCE
 %.scif: %.srec
 	$(Q)$(MAKE) $(build)=arch/arm/mach-renesas $@
 
+%.shdr: %.srec
+	$(Q)$(MAKE) $(build)=arch/arm/mach-renesas $@
+
 OBJCOPYFLAGS_u-boot-nodtb.bin := -O binary \
 		$(if $(CONFIG_X86_16BIT_INIT),-R .start16 -R .resetvec) \
 		$(if $(CONFIG_MPC85XX_HAVE_RESET_VECTOR),$(if $(CONFIG_OF_SEPARATE),-R .bootpg -R .resetvec))
@@ -1682,7 +1685,7 @@ cmd_binman = $(srctree)/tools/binman/binman $(if $(BINMAN_DEBUG),-D) \
 		build -u -d $(binman_dtb) -O . -m \
 		--allow-missing --fake-ext-blobs \
 		$(if $(BINMAN_ALLOW_MISSING),--ignore-missing) \
-		-I . -I $(srctree) -I $(srctree)/board/$(BOARDDIR) \
+		-I . -I $(srctree)/board/$(BOARDDIR) -I $(srctree) \
 		$(foreach f,$(of_list_dirs),-I $(f)) -a of-list=$(of_list) \
 		$(foreach f,$(BINMAN_INDIRS),-I $(f)) \
 		-a atf-bl1-path=${BL1} \

README

@@ -628,98 +628,6 @@ The following options need to be configured:
 
 		If you do not have i2c muxes on your board, omit this define.
 
-- Legacy I2C Support:
-		If you use the software i2c interface (CONFIG_SYS_I2C_SOFT)
-		then the following macros need to be defined (examples are
-		from include/configs/lwmon.h):
-
-		I2C_INIT
-
-		(Optional). Any commands necessary to enable the I2C
-		controller or configure ports.
-
-		eg: #define I2C_INIT (immr->im_cpm.cp_pbdir |=	PB_SCL)
-
-		I2C_ACTIVE
-
-		The code necessary to make the I2C data line active
-		(driven).  If the data line is open collector, this
-		define can be null.
-
-		eg: #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |=  PB_SDA)
-
-		I2C_TRISTATE
-
-		The code necessary to make the I2C data line tri-stated
-		(inactive).  If the data line is open collector, this
-		define can be null.
-
-		eg: #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
-
-		I2C_READ
-
-		Code that returns true if the I2C data line is high,
-		false if it is low.
-
-		eg: #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
-
-		I2C_SDA(bit)
-
-		If <bit> is true, sets the I2C data line high. If it
-		is false, it clears it (low).
-
-		eg: #define I2C_SDA(bit) \
-			if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
-			else	immr->im_cpm.cp_pbdat &= ~PB_SDA
-
-		I2C_SCL(bit)
-
-		If <bit> is true, sets the I2C clock line high. If it
-		is false, it clears it (low).
-
-		eg: #define I2C_SCL(bit) \
-			if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
-			else	immr->im_cpm.cp_pbdat &= ~PB_SCL
-
-		I2C_DELAY
-
-		This delay is invoked four times per clock cycle so this
-		controls the rate of data transfer.  The data rate thus
-		is 1 / (I2C_DELAY * 4). Often defined to be something
-		like:
-
-		#define I2C_DELAY  udelay(2)
-
-		CONFIG_SOFT_I2C_GPIO_SCL / CONFIG_SOFT_I2C_GPIO_SDA
-
-		If your arch supports the generic GPIO framework (asm/gpio.h),
-		then you may alternatively define the two GPIOs that are to be
-		used as SCL / SDA.  Any of the previous I2C_xxx macros will
-		have GPIO-based defaults assigned to them as appropriate.
-
-		You should define these to the GPIO value as given directly to
-		the generic GPIO functions.
-
-		CFG_SYS_I2C_NOPROBES
-
-		This option specifies a list of I2C devices that will be skipped
-		when the 'i2c probe' command is issued.
-
-		e.g.
-			#define CFG_SYS_I2C_NOPROBES {0x50,0x68}
-
-		will skip addresses 0x50 and 0x68 on a board with one I2C bus
-
-		CONFIG_SOFT_I2C_READ_REPEATED_START
-
-		defining this will force the i2c_read() function in
-		the soft_i2c driver to perform an I2C repeated start
-		between writing the address pointer and reading the
-		data.  If this define is omitted the default behaviour
-		of doing a stop-start sequence will be used.  Most I2C
-		devices can use either method, but some require one or
-		the other.
-
 - SPI Support:	CONFIG_SPI
 
 		Enables SPI driver (so far only tested with
@@ -2373,5 +2281,5 @@ Contributing
 
 The U-Boot projects depends on contributions from the user community.
 If you want to participate, please, have a look at the 'General'
-section of https://docs.u-boot.org/en/latest/develop/index.html
+section of https://docs.u-boot-project.org/en/latest/develop/index.html
 where we describe coding standards and the patch submission process.

arch/arm/Kconfig

@@ -1082,6 +1082,7 @@ config ARCH_APPLE
 	imply CMD_GPT
 	imply BOOTSTD_FULL
 	imply OF_HAS_PRIOR_STAGE
+	imply OF_UPSTREAM
 
 config ARCH_OWL
 	bool "Actions Semi OWL SoCs"

arch/arm/cpu/armv8/cache_v8.c

@@ -810,8 +810,10 @@ __weak void mmu_setup(void)
 	el = current_el();
 	set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(NULL, NULL),
 			  MEMORY_ATTRIBUTES);
+}
 
-	/* enable the mmu */
+void mmu_enable(void)
+{
 	set_sctlr(get_sctlr() | CR_M);
 }
 
@@ -881,6 +883,7 @@ void dcache_enable(void)
 	if (!mmu_status()) {
 		__asm_invalidate_tlb_all();
 		mmu_setup();
+		mmu_enable();
 	}
 
 	/* Set up page tables only once (it is done also by mmu_setup()) */

arch/arm/cpu/armv8/fsl-layerscape/cpu.c

@@ -1143,7 +1143,7 @@ int arch_early_init_r(void)
 #ifdef CONFIG_SYS_HAS_SERDES
 	fsl_serdes_init();
 #endif
-#ifdef CONFIG_SYS_FSL_HAS_RGMII
+#if defined(CONFIG_SYS_FSL_HAS_RGMII) && defined(CONFIG_FSL_MC_ENET)
 	/* some dpmacs in armv8a based freescale layerscape SOCs can be
 	 * configured via both serdes(sgmii, 10gbase-r, xlaui etc) bits and via
 	 * EC*_PMUX(rgmii) bits in RCW.
@@ -1158,6 +1158,10 @@ int arch_early_init_r(void)
 	 * function of SOC, the dpmac will be enabled as RGMII even if it was
 	 * also enabled before as SGMII. If ECx_PMUX is not configured for
 	 * RGMII, DPMAC will remain configured as SGMII from fsl_serdes_init().
+	 *
+	 * fsl_rgmii_init() itself is only built under CONFIG_FSL_MC_ENET
+	 * (drivers/net/ldpaa_eth/); gate the call the same way so builds
+	 * without MC-ENET still link.
 	 */
 	fsl_rgmii_init();
 #endif

arch/arm/dts/Makefile

@@ -32,13 +32,6 @@ dtb-$(CONFIG_TARGET_A5Y17LTE) += exynos78x0-axy17lte.dtb
 dtb-$(CONFIG_TARGET_A3Y17LTE) += exynos78x0-axy17lte.dtb
 dtb-$(CONFIG_TARGET_A7Y17LTE) += exynos78x0-axy17lte.dtb
 
-dtb-$(CONFIG_ARCH_APPLE) += \
-	t8103-j274.dtb \
-	t8103-j293.dtb \
-	t8103-j313.dtb \
-	t8103-j456.dtb \
-	t8103-j457.dtb
-
 dtb-$(CONFIG_ARCH_DAVINCI) += \
 	da850-lcdk.dtb \
 	da850-lego-ev3.dtb
@@ -907,11 +900,7 @@ dtb-$(CONFIG_RZA1) += \
 	r7s72100-gr-peach.dtb
 
 dtb-$(CONFIG_RCAR_GEN5) += \
-	r8a78000-ironhide.dtb
-
-ifdef CONFIG_RCAR_GEN5
-DTC_FLAGS += -R 4 -p 0x1000
-endif
+	r8a78000-ironhide-cm33.dtb
 
 dtb-$(CONFIG_TARGET_AT91SAM9261EK) += at91sam9261ek.dtb
 

arch/arm/dts/k3-am69-aquila-dev-u-boot.dtsi

@@ -12,6 +12,11 @@
 #if defined(CONFIG_CPU_V7R)
 
 &binman {
+	tiboot3_am69_gp {
+		insert-template = <&tiboot3_j784s4_gp>;
+		filename = "tiboot3-am69-gp-aquila.bin";
+	};
+
 	tiboot3-am69-hs {
 		insert-template = <&tiboot3_j784s4_hs>;
 		filename = "tiboot3-am69-hs-aquila.bin";
@@ -28,6 +33,10 @@
 	filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-enc.bin";
 };
 
+&ti_fs_gp {
+	filename = "ti-sysfw/ti-fs-firmware-j784s4-gp.bin";
+};
+
 &sysfw_inner_cert {
 	filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-cert.bin";
 };
@@ -78,6 +87,72 @@
 	u-boot-unsigned {
 		insert-template = <&u_boot_unsigned>;
 	};
+
+	firmware-aquila-am69-gp.bin {
+		filename = "firmware-aquila-am69-gp.bin";
+
+		blob-ext@1 {
+			filename = "tiboot3-am69-gp-aquila.bin";
+		};
+
+		blob-ext@2 {
+			filename = "tispl.bin_unsigned";
+			/*
+			 * This value matches CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR
+			 * from R5 SPL config.
+			 */
+			offset = <0x80000>;
+		};
+
+		blob-ext@3 {
+			filename = "u-boot.img_unsigned";
+			offset = <(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)>;
+		};
+	};
+
+	firmware-aquila-am69-hs.bin {
+		filename = "firmware-aquila-am69-hs.bin";
+
+		blob-ext@1 {
+			filename = "tiboot3-am69-hs-aquila.bin";
+		};
+
+		blob-ext@2 {
+			filename = "tispl.bin";
+			/*
+			 * This value matches CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR
+			 * from R5 SPL config.
+			 */
+			offset = <0x80000>;
+		};
+
+		blob-ext@3 {
+			filename = "u-boot.img";
+			offset = <(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)>;
+		};
+	};
+
+	firmware-aquila-am69-hs-fs.bin {
+		filename = "firmware-aquila-am69-hs-fs.bin";
+
+		blob-ext@1 {
+			filename = "tiboot3-am69-hs-fs-aquila.bin";
+		};
+
+		blob-ext@2 {
+			filename = "tispl.bin";
+			/*
+			 * This value matches CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR
+			 * from R5 SPL config.
+			 */
+			offset = <0x80000>;
+		};
+
+		blob-ext@3 {
+			filename = "u-boot.img";
+			offset = <(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)>;
+		};
+	};
 };
 
 #endif

arch/arm/dts/r8a78000-ironhide-cm33-u-boot.dtsi

@@ -0,0 +1,130 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source extras for U-Boot for the Ironhide CM33 board
+ *
+ * Copyright (C) 2026 Renesas Electronics Corp.
+ */
+
+#include "r8a78000-ironhide-u-boot.dtsi"
+
+/ {
+	model = "Renesas Ironhide board CM33 based on r8a78000";
+	compatible = "renesas,ironhide-cm33", "renesas,r8a78000-cm33";
+
+	aliases {
+		serial1 = &hscif1;
+	};
+
+	chosen {
+		stdout-path = "serial1:1843200n8";
+	};
+
+	/delete-node/ firmware;
+	/delete-node/ memory@40000000;
+	/delete-node/ memory@60600000;
+	/delete-node/ memory@1080000000;
+	/delete-node/ memory@1200000000;
+	/delete-node/ memory@1400000000;
+	/delete-node/ memory@1600000000;
+	/delete-node/ memory@1800000000;
+	/delete-node/ memory@1a00000000;
+	/delete-node/ memory@1c00000000;
+	/delete-node/ memory@1e00000000;
+	/delete-node/ reserved-memory;
+
+	memory@b8400000 {
+		device_type = "memory";
+		reg = <0x0 0xb8400000 0x0 0x00200000>;
+	};
+
+	dummy_clk_rclk: dummy-clk-rclk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <32768>;
+	};
+
+	dummy_clk_sasyncd4_rt: dummy-clk-sasyncd4-rt {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <16660000>;
+	};
+
+	ctl: syscon@5fffd000 {
+		compatible = "renesas,r8a78000-ctl",
+			     "renesas,rcar-gen5-ctl",
+			     "syscon";
+		reg = <0 0x5fffd000 0 0xc4>;
+	};
+
+	watchdog@5fffd800 {
+		compatible = "renesas,r8a78000-wwdt",
+			     "renesas,rcar-gen5-wwdt";
+		clocks = <&dummy_clk_rclk>, <&dummy_clk_sasyncd4_rt>;
+		clock-names = "cnt", "bus";
+		reg = <0 0x5fffd800 0 0x10>;
+		syscon = <&ctl>;
+	};
+
+	scp@c1340000 {
+		compatible = "renesas,r8a78000-rproc";
+		reg = <0 0xc1340000 0 0x80000>;
+	};
+};
+
+&cpg {
+	/delete-property/ firmware;
+};
+
+&eth_pcs {
+	/* Stub clock */
+	clocks = <&dummy_clk_rclk>;
+};
+
+&hscif1 {
+	pinctrl-0 = <&hscif1_pins>;
+	pinctrl-names = "default";
+	uart-has-rtscts;
+	status = "okay";
+};
+
+&mdlc_hscn {
+	/delete-property/ firmware;
+};
+
+&mdlc_pere {
+	/delete-property/ firmware;
+};
+
+&mmc0 {
+	status = "disabled";
+};
+
+&mp_phy {
+	/* Stub clock */
+	clocks = <&dummy_clk_rclk>;
+};
+
+&pfc {
+	hscif1_pins: hscif1 {
+		groups = "hscif1_data", "hscif1_ctrl";
+		function = "hscif1";
+	};
+};
+
+&rswitch3 {
+	/* Stub clock */
+	clocks = <&dummy_clk_rclk>;
+};
+
+&soc {
+	dma-ranges = <0 0x00000000 0 0xa0000000 0 0x20000000>;
+};
+
+&ufs0 {
+	/delete-property/ power-domains;
+};
+
+&ufs1 {
+	/delete-property/ power-domains;
+	status = "disabled";
+};

arch/arm/dts/r8a78000-ironhide-cm33.dts

@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the Ironhide CM33 board
+ *
+ * Copyright (C) 2026 Renesas Electronics Corp.
+ */
+
+#include "../../../dts/upstream/src/arm64/renesas/r8a78000-ironhide.dts"

arch/arm/dts/r8a78000-ironhide-u-boot.dtsi

@@ -5,4 +5,190 @@
  * Copyright (C) 2025 Renesas Electronics Corp.
  */
 
+#include <dt-bindings/net/ti-dp83869.h>
 #include "r8a78000-u-boot.dtsi"
+
+/ {
+	aliases {
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		mmc0 = &mmc0;
+	};
+
+	reg_1p8v: regulator-1p8v {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-1.8V";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	reg_3p3v: regulator-3p3v {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-3.3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+};
+
+&cpg {
+	firmware = <&scmi>;
+};
+
+&eth_pcs {
+	phys = <&mp_phy 2 1>;
+	status = "okay";
+};
+
+&hscif0 {
+	pinctrl-0 = <&hscif0_pins>;
+	pinctrl-names = "default";
+};
+
+&i2c0 {
+	pinctrl-0 = <&i2c0_pins>;
+	pinctrl-names = "default";
+	clock-frequency = <400000>;
+	status = "okay";
+
+	eeprom@50 {
+		compatible = "rohm,br24g01", "atmel,24c01";
+		reg = <0x50>;
+		pagesize = <8>;
+	};
+};
+
+&i2c1 {
+	pinctrl-0 = <&i2c1_pins>;
+	pinctrl-names = "default";
+	clock-frequency = <400000>;
+	status = "okay";
+};
+
+&mdlc_hscn {
+	firmware = <&scmi>;
+};
+
+&mdlc_pere {
+	firmware = <&scmi>;
+};
+
+&mmc0 {
+	pinctrl-0 = <&mmc0_pins>;
+	pinctrl-1 = <&mmc0_pins>;
+	pinctrl-names = "default", "state_uhs";
+
+	bus-width = <8>;
+	full-pwr-cycle-in-suspend;
+	mmc-hs200-1_8v;
+	mmc-hs400-1_8v;
+	no-sd;
+	no-sdio;
+	non-removable;
+
+	vmmc-supply = <&reg_3p3v>;
+	vqmmc-supply = <&reg_1p8v>;
+
+	status = "okay";
+};
+
+&mp_phy {
+	status = "okay";
+};
+
+&pfc {
+	pinctrl-0 = <&scif_clk_pins>;
+	pinctrl-names = "default";
+
+	eth25g2_pins: eth25g2 {
+		groups = "eth25g2_mdio", "eth25g2_link", "eth25g2_phyint";
+		function = "eth25g2";
+		drive-strength = <24>;
+	};
+
+	ethes0_pins: ethes0 {
+		groups = "ethes0_match", "ethes0_capture", "ethes0_pps";
+		function = "ethes0";
+		drive-strength = <24>;
+	};
+
+	hscif0_pins: hscif0 {
+		groups = "hscif0_data", "hscif0_ctrl";
+		function = "hscif0";
+	};
+
+	i2c0_pins: i2c0 {
+		groups = "i2c0";
+		function = "i2c0";
+	};
+
+	i2c1_pins: i2c1 {
+		groups = "i2c1";
+		function = "i2c1";
+	};
+
+	mmc0_pins: mmc0 {
+		groups = "mmc0_data8", "mmc0_ctrl", "mmc0_ds";
+		function = "mmc0";
+		drive-strength = <24>;
+	};
+
+	rsw3_pins: rsw3 {
+		groups = "rsw3_match", "rsw3_capture", "rsw3_pps";
+		function = "rsw3";
+		drive-strength = <24>;
+	};
+
+	scif_clk_pins: scif-clk {
+		groups = "scif_clk";
+		function = "scif_clk";
+	};
+};
+
+&rswitch3 {
+	pinctrl-0 = <&rsw3_pins>, <&eth25g2_pins>, <&ethes0_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	ethernet-ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		/*
+		 * NOTE: Only port@4 is configured for R-Car X5H board.
+		 * Other ports (0-3, 5-12) are currently unused or not
+		 * connected.
+		 */
+		port@4 {
+			reg = <4>;
+			renesas,connect_to_xpcs;
+			phy-handle = <&dp83869_phy>;
+			phy-mode = "sgmii";
+			phys = <&eth_pcs 5>;
+
+			mdio {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				dp83869_phy: ethernet-phy@2 {
+					reg = <2>;
+					ti,sgmii-interface;
+					ti,max-output-impedance;
+					ti,refclk-output-enable;
+					ti,clk-output-sel = <DP83869_CLK_O_SEL_REF_CLK>;
+				};
+			};
+		};
+	};
+};
+
+&ufs0 {
+	status = "okay";
+};
+
+&ufs1 {
+	status = "okay";
+};

arch/arm/dts/r8a78000-ironhide.dts

@@ -1,257 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-/*
- * Device Tree Source for the Ironhide board
- *
- * Copyright (C) 2025 Renesas Electronics Corp.
- */
-
-/dts-v1/;
-#include "r8a78000.dtsi"
-#include <dt-bindings/net/ti-dp83869.h>
-
-/ {
-	model = "Renesas Ironhide board based on r8a78000";
-	compatible = "renesas,ironhide", "renesas,r8a78000";
-
-	aliases {
-		i2c0 = &i2c0;
-		i2c1 = &i2c1;
-		i2c2 = &i2c2;
-		i2c3 = &i2c3;
-		i2c4 = &i2c4;
-		i2c5 = &i2c5;
-		i2c6 = &i2c6;
-		i2c7 = &i2c7;
-		i2c8 = &i2c8;
-		mmc0 = &mmc0;
-		serial0 = &hscif0;
-	};
-
-	chosen {
-		stdout-path = "serial0:1843200n8";
-	};
-
-	memory@40000000 {
-		device_type = "memory";
-		reg = <0x0 0x40000000 0x0 0x80000000>;
-	};
-
-	memory@1080000000 {
-		device_type = "memory";
-		reg = <0x10 0x80000000 0x0 0x80000000>;
-	};
-
-	memory@1200000000 {
-		device_type = "memory";
-		reg = <0x12 0x00000000 0x1 0x00000000>;
-	};
-
-	memory@1400000000 {
-		device_type = "memory";
-		reg = <0x14 0x00000000 0x1 0x00000000>;
-	};
-
-	memory@1600000000 {
-		device_type = "memory";
-		reg = <0x16 0x00000000 0x1 0x00000000>;
-	};
-
-	memory@1800000000 {
-		device_type = "memory";
-		reg = <0x18 0x00000000 0x1 0x00000000>;
-	};
-
-	memory@1a00000000 {
-		device_type = "memory";
-		reg = <0x1a 0x00000000 0x1 0x00000000>;
-	};
-
-	memory@1c00000000 {
-		device_type = "memory";
-		reg = <0x1c 0x00000000 0x1 0x00000000>;
-	};
-
-	memory@1e00000000 {
-		device_type = "memory";
-		reg = <0x1e 0x00000000 0x1 0x00000000>;
-	};
-
-	reg_1p8v: regulator-1p8v {
-		compatible = "regulator-fixed";
-		regulator-name = "fixed-1.8V";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-
-	reg_3p3v: regulator-3p3v {
-		compatible = "regulator-fixed";
-		regulator-name = "fixed-3.3V";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-};
-
-&extal_clk {
-	clock-frequency = <16666600>;
-};
-
-&extalr_clk {
-	clock-frequency = <32768>;
-};
-
-&hscif0 {
-	pinctrl-0 = <&hscif0_pins>;
-	pinctrl-names = "default";
-	uart-has-rtscts;
-	status = "okay";
-};
-
-&i2c0 {
-	pinctrl-0 = <&i2c0_pins>;
-	pinctrl-names = "default";
-	clock-frequency = <400000>;
-	status = "okay";
-
-	eeprom@50 {
-		compatible = "rohm,br24g01", "atmel,24c01";
-		reg = <0x50>;
-		pagesize = <8>;
-	};
-};
-
-&i2c1 {
-	pinctrl-0 = <&i2c1_pins>;
-	pinctrl-names = "default";
-	clock-frequency = <400000>;
-	status = "okay";
-};
-
-&eth_pcs {
-	phys = <&mp_phy 2 1>;
-	status = "okay";
-};
-
-&mmc0 {
-	pinctrl-0 = <&mmc0_pins>;
-	pinctrl-1 = <&mmc0_pins>;
-	pinctrl-names = "default", "state_uhs";
-
-	bus-width = <8>;
-	full-pwr-cycle-in-suspend;
-	mmc-hs200-1_8v;
-	mmc-hs400-1_8v;
-	no-sd;
-	no-sdio;
-	non-removable;
-
-	vmmc-supply = <&reg_3p3v>;
-	vqmmc-supply = <&reg_1p8v>;
-
-	status = "okay";
-};
-
-&ufs0 {
-	status = "okay";
-};
-
-&ufs1 {
-	status = "okay";
-};
-
-&mp_phy {
-	status = "okay";
-};
-
-&pfc {
-	pinctrl-0 = <&scif_clk_pins>;
-	pinctrl-names = "default";
-
-	eth25g2_pins: eth25g2 {
-		groups = "eth25g2_mdio", "eth25g2_link", "eth25g2_phyint";
-		function = "eth25g2";
-		drive-strength = <24>;
-	};
-
-	ethes0_pins: ethes0 {
-		groups = "ethes0_match", "ethes0_capture", "ethes0_pps";
-		function = "ethes0";
-		drive-strength = <24>;
-	};
-
-	hscif0_pins: hscif0 {
-		groups = "hscif0_data", "hscif0_ctrl";
-		function = "hscif0";
-	};
-
-	i2c0_pins: i2c0 {
-		groups = "i2c0";
-		function = "i2c0";
-	};
-
-	i2c1_pins: i2c1 {
-		groups = "i2c1";
-		function = "i2c1";
-	};
-
-	mmc0_pins: mmc0 {
-		groups = "mmc0_data8", "mmc0_ctrl", "mmc0_ds";
-		function = "mmc0";
-		drive-strength = <24>;
-	};
-
-	rsw3_pins: rsw3 {
-		groups = "rsw3_match", "rsw3_capture", "rsw3_pps";
-		function = "rsw3";
-		drive-strength = <24>;
-	};
-
-	scif_clk_pins: scif-clk {
-		groups = "scif_clk";
-		function = "scif_clk";
-	};
-};
-
-&rswitch3 {
-	pinctrl-0 = <&rsw3_pins>, <&eth25g2_pins>, <&ethes0_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-
-	ethernet-ports {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		/*
-		 * NOTE: Only port@4 is configured for R-Car X5H board.
-		 * Other ports (0-3, 5-12) are currently unused or not
-		 * connected.
-		 */
-		port@4 {
-			reg = <4>;
-			renesas,connect_to_xpcs;
-			phy-handle = <&dp83869_phy>;
-			phy-mode = "sgmii";
-			phys = <&eth_pcs 5>;
-
-			mdio {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				dp83869_phy: ethernet-phy@2 {
-					reg = <2>;
-					ti,sgmii-interface;
-					ti,max-output-impedance;
-					ti,refclk-output-enable;
-					ti,clk-output-sel = <DP83869_CLK_O_SEL_REF_CLK>;
-				};
-			};
-		};
-	};
-};
-
-&scif_clk {
-	clock-frequency = <26000000>;
-};

arch/arm/dts/r8a78000-u-boot.dtsi

@@ -5,9 +5,41 @@
  * Copyright (C) 2025 Renesas Electronics Corp.
  */
 
+#include <dt-bindings/clock/r8a78000-clock-scmi.h>
+#include <dt-bindings/power/r8a78000-power-scmi.h>
+#include <dt-bindings/reset/r8a78000-reset-scmi.h>
+
 / {
-	soc {
-		bootph-all;
+	firmware {
+		scmi: scmi {
+			compatible = "arm,scmi";
+			arm,poll-transport;
+			mbox-names = "tx", "rx";
+			mboxes = <&mailbox 0>, <&mailbox 1>;
+			shmem = <&cpu_scp_lpri0>, <&cpu_scp_hpri0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			protocol@11 {
+				reg = <0x11>;
+				#power-domain-cells = <1>;
+			};
+
+			protocol@14 {
+				reg = <0x14>;
+				#clock-cells = <1>;
+			};
+
+			protocol@16 {
+				reg = <0x16>;
+				#reset-cells = <1>;
+			};
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-1.0", "arm,psci-0.2";
+		method = "smc";
 	};
 
 	/* Placeholder clock until the clock provider is in place */
@@ -32,16 +64,12 @@
 	clk_stub_mmc: clk-stub-mmc {
 		compatible = "renesas,compound-clock";
 		#clock-cells = <0>;
-		clocks = <&scmi_clk SCP_CLOCK_ID_MDLC_SDHI0>,
-			 <&scmi_clk 1691>;
+		clocks = <&cpg SCP_CLOCK_ID_MDLC_SDHI0>,
+			 <&cpg SCP_CLOCK_ID_CLK_S0D6_PERE_MAIN>;
 		clock-names = "mdlc", "per";
 	};
 };
 
-&cpg {
-	bootph-all;
-};
-
 &extal_clk {
 	bootph-all;
 };
@@ -50,90 +78,311 @@
 	bootph-all;
 };
 
-&gpio0 {
-	clocks = <&clk_stub_gpio>;
-};
-
-&gpio1 {
-	clocks = <&clk_stub_gpio>;
-};
-
-&gpio2 {
-	clocks = <&clk_stub_gpio>;
-};
-
-&gpio3 {
-	clocks = <&clk_stub_gpio>;
-};
-
-&gpio4 {
-	clocks = <&clk_stub_gpio>;
-};
-
-&gpio5 {
-	clocks = <&clk_stub_gpio>;
-};
-
-&gpio6 {
-	clocks = <&clk_stub_gpio>;
-};
-
-&gpio7 {
-	clocks = <&clk_stub_gpio>;
-};
-
-&gpio8 {
-	clocks = <&clk_stub_gpio>;
-};
-
-&gpio9 {
-	clocks = <&clk_stub_gpio>;
-};
-
-&gpio10 {
-	clocks = <&clk_stub_gpio>;
-};
-
-&i2c0 {
-	clocks = <&clk_stub_i2c0>;
-};
-
-&i2c1 {
-	clocks = <&clk_stub_i2c1>;
-};
-
-&i2c2 {
-	clocks = <&clk_stub_i2c1>;
-};
-
-&i2c3 {
-	clocks = <&clk_stub_i2c1>;
-};
-
-&i2c4 {
-	clocks = <&clk_stub_i2c1>;
-};
-
-&i2c5 {
-	clocks = <&clk_stub_i2c1>;
-};
-
-&i2c6 {
-	clocks = <&clk_stub_i2c1>;
-};
-
-&i2c7 {
-	clocks = <&clk_stub_i2c1>;
-};
-
-&i2c8 {
-	clocks = <&clk_stub_i2c1>;
-};
-
-&mmc0 {
-	clocks = <&clk_stub_mmc>;
-};
-
 &prr {
 	bootph-all;
 };
+
+&soc {
+	bootph-all;
+
+	mailbox: mfis_mbox@18842000 {
+		compatible = "renesas,mfis-mbox";
+		#mbox-cells = <1>;
+		reg = <0 0x18842004 0 0x8>;
+		interrupts = <GIC_SPI 4362 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	pfc: pinctrl@c0400000 {
+		compatible = "renesas,pfc-r8a78000";
+		reg = <0 0xc1080000 0 0x104>, <0 0xc1080800 0 0x104>,
+		      <0 0xc1081000 0 0x104>, <0 0xc0800000 0 0x104>,
+		      <0 0xc0800800 0 0x104>, <0 0xc0400000 0 0x104>,
+		      <0 0xc0400800 0 0x104>, <0 0xc0401000 0 0x104>,
+		      <0 0xc0401800 0 0x104>, <0 0xc9b00000 0 0x104>,
+		      <0 0xc9b00800 0 0x104>;
+	};
+
+	mmc0: mmc@c0880000 {
+		compatible = "renesas,rcar-gen5-sdhi";
+		reg = <0 0xc0880000 0 0x2000>;
+		clock-names = "core";
+		max-frequency = <200000000>;
+		clocks = <&clk_stub_mmc>;
+		status = "disabled";
+	};
+
+	mdlc_pere: system-controller@c08f0000 {
+		compatible = "renesas,r8a78000-mdlc";
+		reg = <0 0xc08f0000 0 0x1000>;
+		#power-domain-cells = <1>;
+		#reset-cells = <1>;
+		bootph-all;
+	};
+
+	ufs0: ufs@c0a80000 {
+		compatible = "renesas,r8a78000-ufs";
+		reg = <0 0xc0a80000 0 0x1100>, <0 0xc0a00000 0 0x40000>;
+		reg-names = "hcr", "phy";
+		interrupts = <GIC_SPI 4284 IRQ_TYPE_LEVEL_HIGH>;
+		power-domains = <&mdlc_pere X5H_POWER_DOMAIN_ID_UFS0>;
+		clocks = <&cpg SCP_CLOCK_ID_MDLC_UFS0>;
+		resets = <&mdlc_pere SCP_RESET_DOMAIN_ID_UFS0>;
+		freq-table-hz = <38400000 38400000>;
+		status = "disabled";
+	};
+
+	ufs1: ufs@c0a90000 {
+		compatible = "renesas,r8a78000-ufs";
+		reg = <0 0xc0a90000 0 0x1100>, <0 0xc0a40000 0 0x40000>;
+		reg-names = "hcr", "phy";
+		interrupts = <GIC_SPI 4285 IRQ_TYPE_LEVEL_HIGH>;
+		power-domains = <&mdlc_pere X5H_POWER_DOMAIN_ID_UFS1>;
+		clocks = <&cpg SCP_CLOCK_ID_MDLC_UFS1>;
+		resets = <&mdlc_pere SCP_RESET_DOMAIN_ID_UFS1>;
+		freq-table-hz = <38400000 38400000>;
+		status = "disabled";
+	};
+
+	scp: sram@c1000000 {
+		compatible = "arm,rcar-sram-ns", "mmio-sram";
+		reg = <0x0 0xc1000000 0x0 0x80000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x0 0xc1000000 0x80000>;
+
+		cpu_scp_lpri0: scp-shmem@60000 {
+			compatible = "arm,rcar-scp-shmem", "arm,scmi-shmem";
+			reg = <0x61200 0x0100>;
+		};
+
+		cpu_scp_hpri0: scp-shmem@60300 {
+			compatible = "arm,rcar-scp-shmem", "arm,scmi-shmem";
+			reg = <0x61300 0x100>;
+		};
+	};
+
+	cpg: clock-controller@c1320000 {
+		compatible = "renesas,r8a78000-cpg";
+		reg = <0 0xc1320000 0 0x10000>;
+		clocks = <&extal_clk>, <&extalr_clk>;
+		clock-names = "extal", "extalr";
+		#clock-cells = <1>;
+		bootph-all;
+	};
+
+	i2c0: i2c@c11d0000 {
+		compatible = "renesas,i2c-r8a78000",
+			     "renesas,rcar-gen5-i2c";
+		reg = <0 0xc11d0000 0 0x40>;
+		i2c-scl-internal-delay-ns = <110>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&clk_stub_i2c0>;
+		status = "disabled";
+	};
+
+	i2c1: i2c@c06c0000 {
+		compatible = "renesas,i2c-r8a78000",
+			     "renesas,rcar-gen5-i2c";
+		reg = <0 0xc06c0000 0 0x40>;
+		i2c-scl-internal-delay-ns = <110>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&clk_stub_i2c1>;
+		status = "disabled";
+	};
+
+	gpio0: gpio@c1080110 {
+		compatible = "renesas,gpio-r8a78000",
+			     "renesas,rcar-gen5-gpio";
+		reg = <0 0xc1080110 0 0xc0>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		gpio-ranges = <&pfc 0 0 28>;
+		clocks = <&clk_stub_gpio>;
+	};
+
+	gpio1: gpio@c1080910 {
+		compatible = "renesas,gpio-r8a78000",
+			     "renesas,rcar-gen5-gpio";
+		reg = <0 0xc1080910 0 0xc0>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		gpio-ranges = <&pfc 0 32 22>;
+		clocks = <&clk_stub_gpio>;
+	};
+
+	gpio2: gpio@c1081110 {
+		compatible = "renesas,gpio-r8a78000",
+			     "renesas,rcar-gen5-gpio";
+		reg = <0 0xc1081110 0 0xc0>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		gpio-ranges = <&pfc 0 64 29>;
+		clocks = <&clk_stub_gpio>;
+	};
+
+	gpio3: gpio@c0800110 {
+		compatible = "renesas,gpio-r8a78000",
+			     "renesas,rcar-gen5-gpio";
+		reg = <0 0xc0800110 0 0xc0>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		gpio-ranges = <&pfc 0 96 17>;
+		clocks = <&clk_stub_gpio>;
+	};
+
+	gpio4: gpio@c0800910 {
+		compatible = "renesas,gpio-r8a78000",
+			     "renesas,rcar-gen5-gpio";
+		reg = <0 0xc0800910 0 0xc0>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		gpio-ranges = <&pfc 0 128 16>;
+		clocks = <&clk_stub_gpio>;
+	};
+
+	gpio5: gpio@c0400110 {
+		compatible = "renesas,gpio-r8a78000",
+			     "renesas,rcar-gen5-gpio";
+		reg = <0 0xc0400110 0 0xc0>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		gpio-ranges = <&pfc 0 160 23>;
+		clocks = <&clk_stub_gpio>;
+	};
+
+	gpio6: gpio@c0400910 {
+		compatible = "renesas,gpio-r8a78000",
+			     "renesas,rcar-gen5-gpio";
+		reg = <0 0xc0400910 0 0xc0>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		gpio-ranges = <&pfc 0 192 31>;
+		clocks = <&clk_stub_gpio>;
+	};
+
+	gpio7: gpio@c0401110 {
+		compatible = "renesas,gpio-r8a78000",
+			     "renesas,rcar-gen5-gpio";
+		reg = <0 0xc0401110 0 0xc0>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		gpio-ranges = <&pfc 0 224 31>;
+		clocks = <&clk_stub_gpio>;
+	};
+
+	gpio8: gpio@c0401910 {
+		compatible = "renesas,gpio-r8a78000",
+			     "renesas,rcar-gen5-gpio";
+		reg = <0 0xc0401910 0 0xc0>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		gpio-ranges = <&pfc 0 256 32>;
+		gpio-reserved-ranges = <16 10>;
+		clocks = <&clk_stub_gpio>;
+	};
+
+	gpio9: gpio@c9b00110 {
+		compatible = "renesas,gpio-r8a78000",
+			     "renesas,rcar-gen5-gpio";
+		reg = <0 0xc9b00110 0 0xc0>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		gpio-ranges = <&pfc 0 288 17>;
+		clocks = <&clk_stub_gpio>;
+	};
+
+	gpio10: gpio@c9b00910 {
+		compatible = "renesas,gpio-r8a78000",
+			     "renesas,rcar-gen5-gpio";
+		reg = <0 0xc9b00910 0 0xc0>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		gpio-ranges = <&pfc 0 320 14>;
+		clocks = <&clk_stub_gpio>;
+	};
+
+	mp_phy: mp_phy@c9a00000 {
+		compatible = "renesas,r8a78000-multi-protocol-phy";
+		reg = <0 0xc9a00000 0 0x100000>;
+		#phy-cells = <2>;
+		clocks = <&cpg SCP_CLOCK_ID_MDLC_MPPHY01>,
+			 <&cpg SCP_CLOCK_ID_MDLC_MPPHY11>,
+			 <&cpg SCP_CLOCK_ID_MDLC_MPPHY21>,
+			 <&cpg SCP_CLOCK_ID_MDLC_MPPHY31>,
+			 <&cpg SCP_CLOCK_ID_MDLC_MPPHY02>;
+		clock-names = "mpphy01", "mpphy11", "mpphy21",
+			      "mpphy31", "mpphy02";
+		power-domains = <&mdlc_hscn X5H_POWER_DOMAIN_ID_MPP0>,
+				<&mdlc_hscn X5H_POWER_DOMAIN_ID_MPP1>,
+				<&mdlc_hscn X5H_POWER_DOMAIN_ID_MPP2>,
+				<&mdlc_hscn X5H_POWER_DOMAIN_ID_MPP3>;
+		resets = <&mdlc_hscn SCP_RESET_DOMAIN_ID_MPPHY01>,
+			 <&mdlc_hscn SCP_RESET_DOMAIN_ID_MPPHY11>,
+			 <&mdlc_hscn SCP_RESET_DOMAIN_ID_MPPHY21>,
+			 <&mdlc_hscn SCP_RESET_DOMAIN_ID_MPPHY31>,
+			 <&mdlc_hscn SCP_RESET_DOMAIN_ID_MPPHY02>;
+		status = "disabled";
+	};
+
+	rswitch3: ethernet@c9bc0000 {
+		compatible = "renesas,r8a78000-ether-switch3",
+				"renesas,etherswitch";
+		reg = <0 0xc9bc0000 0 0x40000>, <0 0xc9b80000 0 0x240000>;
+		reg-names = "base", "secure_base";
+		power-domains = <&mdlc_hscn X5H_POWER_DOMAIN_ID_RSW>;
+		clocks = <&cpg SCP_CLOCK_ID_MDLC_RSW3>,
+			 <&cpg SCP_CLOCK_ID_MDLC_RSW3TSN>,
+			 <&cpg SCP_CLOCK_ID_MDLC_RSW3AES>,
+			 <&cpg SCP_CLOCK_ID_MDLC_RSW3TSNTES0>,
+			 <&cpg SCP_CLOCK_ID_MDLC_RSW3TSNTES1>,
+			 <&cpg SCP_CLOCK_ID_MDLC_RSW3TSNTES2>,
+			 <&cpg SCP_CLOCK_ID_MDLC_RSW3TSNTES3>,
+			 <&cpg SCP_CLOCK_ID_MDLC_RSW3TSNTES4>,
+			 <&cpg SCP_CLOCK_ID_MDLC_RSW3TSNTES5>,
+			 <&cpg SCP_CLOCK_ID_MDLC_RSW3TSNTES6>,
+			 <&cpg SCP_CLOCK_ID_MDLC_RSW3TSNTES7>,
+			 <&cpg SCP_CLOCK_ID_MDLC_RSW3MFWD>;
+		clock-names = "rsw3", "rsw3tsn", "rsw3aes",
+			      "rsw3tsntes0", "rsw3tsntes1", "rsw3tsntes2",
+			      "rsw3tsntes3", "rsw3tsntes4", "rsw3tsntes5",
+			      "rsw3tsntes6", "rsw3tsntes7", "rsw3mfwd";
+		status = "disabled";
+	};
+
+	eth_pcs: phy@c9c50000 {
+		compatible = "renesas,r8a78000-ether-pcs";
+		reg = <0 0xc9c50000 0 0x4000>;
+		#phy-cells = <1>;
+		clocks = <&cpg SCP_CLOCK_ID_MDLC_XPCS0>,
+			 <&cpg SCP_CLOCK_ID_MDLC_XPCS1>,
+			 <&cpg SCP_CLOCK_ID_MDLC_XPCS2>,
+			 <&cpg SCP_CLOCK_ID_MDLC_XPCS3>,
+			 <&cpg SCP_CLOCK_ID_MDLC_XPCS4>,
+			 <&cpg SCP_CLOCK_ID_MDLC_XPCS5>,
+			 <&cpg SCP_CLOCK_ID_MDLC_XPCS6>,
+			 <&cpg SCP_CLOCK_ID_MDLC_XPCS7>;
+		clock-names = "xpcs0", "xpcs1", "xpcs2", "xpcs3",
+			      "xpcs4", "xpcs5", "xpcs6", "xpcs7";
+		resets = <&mdlc_hscn SCP_RESET_DOMAIN_ID_XPCS0>,
+			 <&mdlc_hscn SCP_RESET_DOMAIN_ID_XPCS1>,
+			 <&mdlc_hscn SCP_RESET_DOMAIN_ID_XPCS2>,
+			 <&mdlc_hscn SCP_RESET_DOMAIN_ID_XPCS3>,
+			 <&mdlc_hscn SCP_RESET_DOMAIN_ID_XPCS4>,
+			 <&mdlc_hscn SCP_RESET_DOMAIN_ID_XPCS5>,
+			 <&mdlc_hscn SCP_RESET_DOMAIN_ID_XPCS6>,
+			 <&mdlc_hscn SCP_RESET_DOMAIN_ID_XPCS7>;
+		reset-names = "xpcs0", "xpcs1", "xpcs2", "xpcs3",
+			      "xpcs4", "xpcs5", "xpcs6", "xpcs7";
+		status = "disabled";
+	};
+
+	mdlc_hscn: system-controller@c9c90000 {
+		compatible = "renesas,r8a78000-mdlc";
+		reg = <0 0xc9c90000 0 0x1000>;
+		#power-domain-cells = <1>;
+		#reset-cells = <1>;
+		bootph-all;
+	};
+};

arch/arm/dts/stm32mp15-scmi-u-boot.dtsi

@@ -21,6 +21,13 @@
 		pinctrl1 = &pinctrl_z;
 	};
 
+	arm_wdt: watchdog {
+		compatible = "arm,smc-wdt";
+		arm,smc-id = <0xbc000000>;
+		timeout-sec = <32>;
+		status = "okay";
+	};
+
 	binman: binman {
 		multiple-images;
 	};
@@ -103,7 +110,7 @@
 };
 
 &iwdg2 {
-	bootph-all;
+	status = "disabled";
 };
 
 /* pre-reloc probe = reserve video frame buffer in video_reserve() */

arch/arm/dts/t8103-j274-u-boot.dtsi

@@ -1 +0,0 @@
-#include "t8103-u-boot.dtsi"

arch/arm/dts/t8103-j274.dts

@@ -1,129 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR MIT
-/*
- * Apple Mac mini (M1, 2020)
- *
- * target-type: J274
- *
- * Copyright The Asahi Linux Contributors
- */
-
-/dts-v1/;
-
-#include "t8103.dtsi"
-#include "t8103-jxxx.dtsi"
-
-/ {
-	compatible = "apple,j274", "apple,t8103", "apple,arm-platform";
-	model = "Apple Mac mini (M1, 2020)";
-
-	aliases {
-		ethernet0 = &ethernet0;
-	};
-};
-
-&wifi0 {
-	brcm,board-type = "apple,atlantisb";
-};
-
-/*
- * Provide labels for the USB type C ports.
- */
-
-&typec0 {
-	label = "USB-C Back-left";
-};
-
-&typec1 {
-	label = "USB-C Back-right";
-};
-
-/*
- * Force the bus number assignments so that we can declare some of the
- * on-board devices and properties that are populated by the bootloader
- * (such as MAC addresses).
- */
-
-&port01 {
-	bus-range = <2 2>;
-};
-
-&port02 {
-	bus-range = <3 3>;
-	ethernet0: ethernet@0,0 {
-		reg = <0x30000 0x0 0x0 0x0 0x0>;
-		/* To be filled by the loader */
-		local-mac-address = [00 10 18 00 00 00];
-	};
-};
-
-&i2c1 {
-	clock-frequency = <50000>;
-
-	speaker_amp: codec@31 {
-		compatible = "ti,tas5770l", "ti,tas2770";
-		reg = <0x31>;
-		reset-gpios = <&pinctrl_ap 181 GPIO_ACTIVE_HIGH>;
-		#sound-dai-cells = <0>;
-	};
-};
-
-&i2c2 {
-	status = "okay";
-
-	clock-frequency = <50000>;
-
-	jack_codec: codec@48 {
-		compatible = "cirrus,cs42l83", "cirrus,cs42l42";
-		reg = <0x48>;
-		reset-gpios = <&pinctrl_nub 11 GPIO_ACTIVE_HIGH>;
-		interrupt-parent = <&pinctrl_ap>;
-		interrupts = <183 IRQ_TYPE_LEVEL_LOW>;
-		#sound-dai-cells = <0>;
-		cirrus,ts-inv = <1>;
-	};
-};
-
-/ {
-	sound {
-		compatible = "simple-audio-card";
-		simple-audio-card,name = "Mac mini integrated audio";
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		simple-audio-card,dai-link@0 {
-			reg = <0>;
-			format = "left_j";
-			tdm-slot-width = <32>;
-			mclk-fs = <64>;
-
-			link0_cpu: cpu {
-				sound-dai = <&mca 0>;
-				bitclock-master;
-				frame-master;
-			};
-
-			link0_codec: codec {
-				sound-dai = <&speaker_amp>;
-			};
-		};
-
-		simple-audio-card,dai-link@1 {
-			bitclock-inversion;
-			frame-inversion;
-			reg = <1>;
-			format = "i2s";
-			mclk-fs = <64>;
-			tdm-slot-width = <32>;
-
-			link1_cpu: cpu {
-				sound-dai = <&mca 2>;
-				bitclock-master;
-				frame-master;
-			};
-
-			link1_codec: codec {
-				sound-dai = <&jack_codec>;
-			};
-		};
-	};
-};

arch/arm/dts/t8103-j293-u-boot.dtsi

@@ -1 +0,0 @@
-#include "t8103-u-boot.dtsi"

arch/arm/dts/t8103-j293.dts

@@ -1,116 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR MIT
-/*
- * Apple MacBook Pro (13-inch, M1, 2020)
- *
- * target-type: J293
- *
- * Copyright The Asahi Linux Contributors
- */
-
-/dts-v1/;
-
-#include "t8103.dtsi"
-#include "t8103-jxxx.dtsi"
-
-/ {
-	compatible = "apple,j293", "apple,t8103", "apple,arm-platform";
-	model = "Apple MacBook Pro (13-inch, M1, 2020)";
-};
-
-&wifi0 {
-	brcm,board-type = "apple,honshu";
-};
-
-/*
- * Provide labels for the USB type C ports.
- */
-
-&typec0 {
-	label = "USB-C Left-back";
-};
-
-&typec1 {
-	label = "USB-C Left-front";
-};
-
-&spi3 {
-	status = "okay";
-
-	hid-transport@0 {
-		compatible = "apple,spi-hid-transport";
-		reg = <0>;
-		spi-max-frequency = <8000000>;
-		/*
-		 * cs-setup and cs-hold delays are derived from Apple's ADT
-		 * Mac OS driver meta data secify 45 us for 'cs to clock' and
-		 * 'clock to cs' delays.
-		 */
-		spi-cs-setup-delay-ns = <20000>;
-		spi-cs-hold-delay-ns = <20000>;
-		spi-cs-inactive-delay-ns = <250000>;
-		spien-gpios = <&pinctrl_ap 195 0>;
-		interrupts-extended = <&pinctrl_nub 13 IRQ_TYPE_LEVEL_LOW>;
-	};
-};
-
-/*
- * Remove unused PCIe ports and disable the associated DARTs.
- */
-
-&pcie0_dart_1 {
-	status = "disabled";
-};
-
-&pcie0_dart_2 {
-	status = "disabled";
-};
-
-/delete-node/ &port01;
-/delete-node/ &port02;
-
-&i2c2 {
-	status = "okay";
-	clock-frequency = <50000>;
-
-	jack_codec: codec@48 {
-		compatible = "cirrus,cs42l83", "cirrus,cs42l42";
-		reg = <0x48>;
-		reset-gpios = <&pinctrl_nub 11 GPIO_ACTIVE_HIGH>;
-		interrupt-parent = <&pinctrl_ap>;
-		interrupts = <183 IRQ_TYPE_LEVEL_LOW>;
-		#sound-dai-cells = <0>;
-		cirrus,ts-inv = <1>;
-	};
-};
-
-&i2c4 {
-	status = "okay";
-};
-
-/ {
-	sound {
-		compatible = "simple-audio-card";
-		simple-audio-card,name = "MacBook integrated audio";
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		simple-audio-card,dai-link@0 {
-			bitclock-inversion;
-			frame-inversion;
-			reg = <0>;
-			format = "i2s";
-			mclk-fs = <64>;
-			tdm-slot-width = <32>;
-
-			link0_cpu: cpu {
-				sound-dai = <&mca 2>;
-				bitclock-master;
-				frame-master;
-			};
-
-			link0_codec: codec {
-				sound-dai = <&jack_codec>;
-			};
-		};
-	};
-};

arch/arm/dts/t8103-j313-u-boot.dtsi

@@ -1 +0,0 @@
-#include "t8103-u-boot.dtsi"

arch/arm/dts/t8103-j313.dts

@@ -1,111 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR MIT
-/*
- * Apple MacBook Air (M1, 2020)
- *
- * target-type: J313
- *
- * Copyright The Asahi Linux Contributors
- */
-
-/dts-v1/;
-
-#include "t8103.dtsi"
-#include "t8103-jxxx.dtsi"
-
-/ {
-	compatible = "apple,j313", "apple,t8103", "apple,arm-platform";
-	model = "Apple MacBook Air (M1, 2020)";
-};
-
-&wifi0 {
-	brcm,board-type = "apple,shikoku";
-};
-
-/*
- * Provide labels for the USB type C ports.
- */
-
-&typec0 {
-	label = "USB-C Left-back";
-};
-
-&typec1 {
-	label = "USB-C Left-front";
-};
-
-&spi3 {
-	status = "okay";
-
-	hid-transport@0 {
-		compatible = "apple,spi-hid-transport";
-		reg = <0>;
-		spi-max-frequency = <8000000>;
-		/*
-		 * cs-setup and cs-hold delays are derived from Apple's ADT
-		 * Mac OS driver meta data secify 45 us for 'cs to clock' and
-		 * 'clock to cs' delays.
-		 */
-		spi-cs-setup-delay-ns = <20000>;
-		spi-cs-hold-delay-ns = <20000>;
-		spi-cs-inactive-delay-ns = <250000>;
-		spien-gpios = <&pinctrl_ap 195 0>;
-		interrupts-extended = <&pinctrl_nub 13 IRQ_TYPE_LEVEL_LOW>;
-	};
-};
-
-/*
- * Remove unused PCIe ports and disable the associated DARTs.
- */
-
-&pcie0_dart_1 {
-	status = "disabled";
-};
-
-&pcie0_dart_2 {
-	status = "disabled";
-};
-
-/delete-node/ &port01;
-/delete-node/ &port02;
-
-&i2c3 {
-	clock-frequency = <50000>;
-
-	jack_codec: codec@48 {
-		compatible = "cirrus,cs42l83", "cirrus,cs42l42";
-		reg = <0x48>;
-		reset-gpios = <&pinctrl_nub 11 GPIO_ACTIVE_HIGH>;
-		interrupt-parent = <&pinctrl_ap>;
-		interrupts = <183 IRQ_TYPE_LEVEL_LOW>;
-		#sound-dai-cells = <0>;
-		cirrus,ts-inv = <1>;
-	};
-};
-
-/ {
-	sound {
-		compatible = "simple-audio-card";
-		simple-audio-card,name = "MacBook integrated audio";
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		simple-audio-card,dai-link@0 {
-			bitclock-inversion;
-			frame-inversion;
-			reg = <0>;
-			format = "i2s";
-			mclk-fs = <64>;
-			tdm-slot-width = <32>;
-
-			link0_cpu: cpu {
-				sound-dai = <&mca 2>;
-				bitclock-master;
-				frame-master;
-			};
-
-			link0_codec: codec {
-				sound-dai = <&jack_codec>;
-			};
-		};
-	};
-};

arch/arm/dts/t8103-j456-u-boot.dtsi

@@ -1 +0,0 @@
-#include "t8103-u-boot.dtsi"

arch/arm/dts/t8103-j456.dts

@@ -1,117 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR MIT
-/*
- * Apple iMac (24-inch, 4x USB-C, M1, 2020)
- *
- * target-type: J456
- *
- * Copyright The Asahi Linux Contributors
- */
-
-/dts-v1/;
-
-#include "t8103.dtsi"
-#include "t8103-jxxx.dtsi"
-
-/ {
-	compatible = "apple,j456", "apple,t8103", "apple,arm-platform";
-	model = "Apple iMac (24-inch, 4x USB-C, M1, 2020)";
-
-	aliases {
-		ethernet0 = &ethernet0;
-	};
-};
-
-&wifi0 {
-	brcm,board-type = "apple,capri";
-};
-
-&i2c0 {
-	hpm2: usb-pd@3b {
-		compatible = "apple,cd321x";
-		reg = <0x3b>;
-		interrupt-parent = <&pinctrl_ap>;
-		interrupts = <106 IRQ_TYPE_LEVEL_LOW>;
-		interrupt-names = "irq";
-	};
-
-	hpm3: usb-pd@3c {
-		compatible = "apple,cd321x";
-		reg = <0x3c>;
-		interrupt-parent = <&pinctrl_ap>;
-		interrupts = <106 IRQ_TYPE_LEVEL_LOW>;
-		interrupt-names = "irq";
-	};
-};
-
-/*
- * Provide labels for the USB type C ports.
- */
-
-&typec0 {
-	label = "USB-C Back-right";
-};
-
-&typec1 {
-	label = "USB-C Back-right-middle";
-};
-
-/*
- * Force the bus number assignments so that we can declare some of the
- * on-board devices and properties that are populated by the bootloader
- * (such as MAC addresses).
- */
-
-&port01 {
-	bus-range = <2 2>;
-};
-
-&port02 {
-	bus-range = <3 3>;
-	ethernet0: ethernet@0,0 {
-		reg = <0x30000 0x0 0x0 0x0 0x0>;
-		/* To be filled by the loader */
-		local-mac-address = [00 10 18 00 00 00];
-	};
-};
-
-&i2c1 {
-	clock-frequency = <50000>;
-
-	jack_codec: codec@48 {
-		compatible = "cirrus,cs42l83", "cirrus,cs42l42";
-		reg = <0x48>;
-		reset-gpios = <&pinctrl_nub 11 GPIO_ACTIVE_HIGH>;
-		interrupt-parent = <&pinctrl_ap>;
-		interrupts = <183 IRQ_TYPE_LEVEL_LOW>;
-		#sound-dai-cells = <0>;
-		cirrus,ts-inv = <1>;
-	};
-};
-
-/ {
-	sound {
-		compatible = "simple-audio-card";
-		simple-audio-card,name = "iMac integrated audio";
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		simple-audio-card,dai-link@0 {
-			bitclock-inversion;
-			frame-inversion;
-			reg = <0>;
-			format = "i2s";
-			mclk-fs = <64>;
-			tdm-slot-width = <32>;
-
-			link0_cpu: cpu {
-				sound-dai = <&mca 2>;
-				bitclock-master;
-				frame-master;
-			};
-
-			link0_codec: codec {
-				sound-dai = <&jack_codec>;
-			};
-		};
-	};
-};

arch/arm/dts/t8103-j457-u-boot.dtsi

@@ -1 +0,0 @@
-#include "t8103-u-boot.dtsi"

arch/arm/dts/t8103-j457.dts

@@ -1,105 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR MIT
-/*
- * Apple iMac (24-inch, 2x USB-C, M1, 2020)
- *
- * target-type: J457
- *
- * Copyright The Asahi Linux Contributors
- */
-
-/dts-v1/;
-
-#include "t8103.dtsi"
-#include "t8103-jxxx.dtsi"
-
-/ {
-	compatible = "apple,j457", "apple,t8103", "apple,arm-platform";
-	model = "Apple iMac (24-inch, 2x USB-C, M1, 2020)";
-
-	aliases {
-		ethernet0 = &ethernet0;
-	};
-};
-
-&wifi0 {
-	brcm,board-type = "apple,santorini";
-};
-
-/*
- * Provide labels for the USB type C ports.
- */
-
-&typec0 {
-	label = "USB-C Back-right";
-};
-
-&typec1 {
-	label = "USB-C Back-left";
-};
-
-/*
- * Force the bus number assignments so that we can declare some of the
- * on-board devices and properties that are populated by the bootloader
- * (such as MAC addresses).
- */
-
-&port02 {
-	bus-range = <3 3>;
-	ethernet0: ethernet@0,0 {
-		reg = <0x30000 0x0 0x0 0x0 0x0>;
-		/* To be filled by the loader */
-		local-mac-address = [00 10 18 00 00 00];
-	};
-};
-
-/*
- * Remove unused PCIe port and disable the associated DART.
- */
-
-&pcie0_dart_1 {
-	status = "disabled";
-};
-
-/delete-node/ &port01;
-
-&i2c1 {
-	clock-frequency = <50000>;
-
-	jack_codec: codec@48 {
-		compatible = "cirrus,cs42l83", "cirrus,cs42l42";
-		reg = <0x48>;
-		reset-gpios = <&pinctrl_nub 11 GPIO_ACTIVE_HIGH>;
-		interrupt-parent = <&pinctrl_ap>;
-		interrupts = <183 IRQ_TYPE_LEVEL_LOW>;
-		#sound-dai-cells = <0>;
-		cirrus,ts-inv = <1>;
-	};
-};
-
-/ {
-	sound {
-		compatible = "simple-audio-card";
-		simple-audio-card,name = "iMac integrated audio";
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		simple-audio-card,dai-link@0 {
-			bitclock-inversion;
-			frame-inversion;
-			reg = <0>;
-			format = "i2s";
-			mclk-fs = <64>;
-			tdm-slot-width = <32>;
-
-			link0_cpu: cpu {
-				sound-dai = <&mca 2>;
-				bitclock-master;
-				frame-master;
-			};
-
-			link0_codec: codec {
-				sound-dai = <&jack_codec>;
-			};
-		};
-	};
-};

arch/arm/dts/t8103-jxxx.dtsi

@@ -1,143 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR MIT
-/*
- * Apple M1 Mac mini, MacBook Air/Pro, iMac 24" (M1, 2020/2021)
- *
- * This file contains parts common to all Apple M1 devices using the t8103.
- *
- * target-type: J274, J293, J313, J456, J457
- *
- * Copyright The Asahi Linux Contributors
- */
-
-#include <dt-bindings/spmi/spmi.h>
-
-/ {
-	aliases {
-		serial0 = &serial0;
-		serial2 = &serial2;
-		wifi0 = &wifi0;
-	};
-
-	chosen {
-		#address-cells = <2>;
-		#size-cells = <2>;
-		ranges;
-
-		stdout-path = "serial0";
-
-		framebuffer0: framebuffer@0 {
-			compatible = "apple,simple-framebuffer", "simple-framebuffer";
-			reg = <0 0 0 0>; /* To be filled by loader */
-			/* Format properties will be added by loader */
-			status = "disabled";
-		};
-	};
-
-	memory@800000000 {
-		device_type = "memory";
-		reg = <0x8 0 0x2 0>; /* To be filled by loader */
-	};
-};
-
-&serial0 {
-	status = "okay";
-};
-
-&serial2 {
-	status = "okay";
-};
-
-&i2c0 {
-	hpm0: usb-pd@38 {
-		compatible = "apple,cd321x";
-		reg = <0x38>;
-		interrupt-parent = <&pinctrl_ap>;
-		interrupts = <106 IRQ_TYPE_LEVEL_LOW>;
-		interrupt-names = "irq";
-
-		typec0: connector {
-			compatible = "usb-c-connector";
-			power-role = "dual";
-			data-role = "dual";
-
-			ports {
-				#address-cells = <1>;
-				#size-cells = <0>;
-				port@0 {
-					reg = <0>;
-					typec0_con_hs: endpoint {
-						remote-endpoint = <&typec0_usb_hs>;
-					};
-				};
-			};
-		};
-	};
-
-	hpm1: usb-pd@3f {
-		compatible = "apple,cd321x";
-		reg = <0x3f>;
-		interrupt-parent = <&pinctrl_ap>;
-		interrupts = <106 IRQ_TYPE_LEVEL_LOW>;
-		interrupt-names = "irq";
-
-		typec1: connector {
-			compatible = "usb-c-connector";
-			power-role = "dual";
-			data-role = "dual";
-
-			ports {
-				#address-cells = <1>;
-				#size-cells = <0>;
-				port@0 {
-					reg = <0>;
-					typec1_con_hs: endpoint {
-						remote-endpoint = <&typec1_usb_hs>;
-					};
-				};
-			};
-		};
-	};
-};
-
-/* USB controllers */
-&dwc3_0 {
-	port {
-		typec0_usb_hs: endpoint {
-			remote-endpoint = <&typec0_con_hs>;
-		};
-	};
-};
-
-&dwc3_1 {
-	port {
-		typec1_usb_hs: endpoint {
-			remote-endpoint = <&typec1_con_hs>;
-		};
-	};
-};
-
-/*
- * Force the bus number assignments so that we can declare some of the
- * on-board devices and properties that are populated by the bootloader
- * (such as MAC addresses).
- */
-&port00 {
-	bus-range = <1 1>;
-	pwren-gpios = <&smc 13 0>;
-	wifi0: network@0,0 {
-		compatible = "pci14e4,4425";
-		reg = <0x10000 0x0 0x0 0x0 0x0>;
-		/* To be filled by the loader */
-		local-mac-address = [00 00 00 00 00 00];
-		apple,antenna-sku = "XX";
-	};
-};
-
-&spmi {
-	status = "okay";
-
-	pmu@f {
-		compatible = "apple,sera-pmu";
-		reg = <0xf SPMI_USID>;
-	};
-};

arch/arm/dts/t8103-u-boot.dtsi

@@ -1,25 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR MIT
-
-&serial0 {
-	bootph-all;
-};
-
-&pmgr {
-	bootph-all;
-};
-
-&ps_sio_busif {
-	bootph-all;
-};
-
-&ps_sio {
-	bootph-all;
-};
-
-&ps_uart_p {
-	bootph-all;
-};
-
-&ps_uart0 {
-	bootph-all;
-};

arch/arm/dts/t8103.dtsi

@@ -1,696 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR MIT
-/*
- * Apple T8103 "M1" SoC
- *
- * Other names: H13G, "Tonga"
- *
- * Copyright The Asahi Linux Contributors
- */
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/apple-aic.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/pinctrl/apple.h>
-
-/ {
-	compatible = "apple,t8103", "apple,arm-platform";
-
-	#address-cells = <2>;
-	#size-cells = <2>;
-
-	cpus {
-		#address-cells = <2>;
-		#size-cells = <0>;
-
-		cpu0: cpu@0 {
-			compatible = "apple,icestorm";
-			device_type = "cpu";
-			reg = <0x0 0x0>;
-			enable-method = "spin-table";
-			cpu-release-addr = <0 0>; /* To be filled by loader */
-		};
-
-		cpu1: cpu@1 {
-			compatible = "apple,icestorm";
-			device_type = "cpu";
-			reg = <0x0 0x1>;
-			enable-method = "spin-table";
-			cpu-release-addr = <0 0>; /* To be filled by loader */
-		};
-
-		cpu2: cpu@2 {
-			compatible = "apple,icestorm";
-			device_type = "cpu";
-			reg = <0x0 0x2>;
-			enable-method = "spin-table";
-			cpu-release-addr = <0 0>; /* To be filled by loader */
-		};
-
-		cpu3: cpu@3 {
-			compatible = "apple,icestorm";
-			device_type = "cpu";
-			reg = <0x0 0x3>;
-			enable-method = "spin-table";
-			cpu-release-addr = <0 0>; /* To be filled by loader */
-		};
-
-		cpu4: cpu@10100 {
-			compatible = "apple,firestorm";
-			device_type = "cpu";
-			reg = <0x0 0x10100>;
-			enable-method = "spin-table";
-			cpu-release-addr = <0 0>; /* To be filled by loader */
-		};
-
-		cpu5: cpu@10101 {
-			compatible = "apple,firestorm";
-			device_type = "cpu";
-			reg = <0x0 0x10101>;
-			enable-method = "spin-table";
-			cpu-release-addr = <0 0>; /* To be filled by loader */
-		};
-
-		cpu6: cpu@10102 {
-			compatible = "apple,firestorm";
-			device_type = "cpu";
-			reg = <0x0 0x10102>;
-			enable-method = "spin-table";
-			cpu-release-addr = <0 0>; /* To be filled by loader */
-		};
-
-		cpu7: cpu@10103 {
-			compatible = "apple,firestorm";
-			device_type = "cpu";
-			reg = <0x0 0x10103>;
-			enable-method = "spin-table";
-			cpu-release-addr = <0 0>; /* To be filled by loader */
-		};
-	};
-
-	timer {
-		compatible = "arm,armv8-timer";
-		interrupt-parent = <&aic>;
-		interrupt-names = "phys", "virt", "hyp-phys", "hyp-virt";
-		interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>,
-			     <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>,
-			     <AIC_FIQ AIC_TMR_HV_PHYS IRQ_TYPE_LEVEL_HIGH>,
-			     <AIC_FIQ AIC_TMR_HV_VIRT IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	clkref: clock-ref {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <24000000>;
-		clock-output-names = "clkref";
-	};
-
-	clk_120m: clock-120m {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <120000000>;
-		clock-output-names = "clk_120m";
-	};
-
-	soc {
-		compatible = "simple-bus";
-		#address-cells = <2>;
-		#size-cells = <2>;
-
-		ranges;
-		nonposted-mmio;
-
-		i2c0: i2c@235010000 {
-			compatible = "apple,t8103-i2c", "apple,i2c";
-			reg = <0x2 0x35010000 0x0 0x4000>;
-			clocks = <&clkref>;
-			interrupt-parent = <&aic>;
-			interrupts = <AIC_IRQ 627 IRQ_TYPE_LEVEL_HIGH>;
-			pinctrl-0 = <&i2c0_pins>;
-			pinctrl-names = "default";
-			#address-cells = <0x1>;
-			#size-cells = <0x0>;
-			power-domains = <&ps_i2c0>;
-		};
-
-		i2c1: i2c@235014000 {
-			compatible = "apple,t8103-i2c", "apple,i2c";
-			reg = <0x2 0x35014000 0x0 0x4000>;
-			clocks = <&clkref>;
-			interrupt-parent = <&aic>;
-			interrupts = <AIC_IRQ 628 IRQ_TYPE_LEVEL_HIGH>;
-			pinctrl-0 = <&i2c1_pins>;
-			pinctrl-names = "default";
-			#address-cells = <0x1>;
-			#size-cells = <0x0>;
-			power-domains = <&ps_i2c1>;
-		};
-
-		i2c2: i2c@235018000 {
-			compatible = "apple,t8103-i2c", "apple,i2c";
-			reg = <0x2 0x35018000 0x0 0x4000>;
-			clocks = <&clkref>;
-			interrupt-parent = <&aic>;
-			interrupts = <AIC_IRQ 629 IRQ_TYPE_LEVEL_HIGH>;
-			pinctrl-0 = <&i2c2_pins>;
-			pinctrl-names = "default";
-			#address-cells = <0x1>;
-			#size-cells = <0x0>;
-			power-domains = <&ps_i2c2>;
-			status = "disabled"; /* not used in all devices */
-		};
-
-		i2c3: i2c@23501c000 {
-			compatible = "apple,t8103-i2c", "apple,i2c";
-			reg = <0x2 0x3501c000 0x0 0x4000>;
-			clocks = <&clkref>;
-			interrupt-parent = <&aic>;
-			interrupts = <AIC_IRQ 630 IRQ_TYPE_LEVEL_HIGH>;
-			pinctrl-0 = <&i2c3_pins>;
-			pinctrl-names = "default";
-			#address-cells = <0x1>;
-			#size-cells = <0x0>;
-			power-domains = <&ps_i2c3>;
-		};
-
-		i2c4: i2c@235020000 {
-			compatible = "apple,t8103-i2c", "apple,i2c";
-			reg = <0x2 0x35020000 0x0 0x4000>;
-			clocks = <&clkref>;
-			interrupt-parent = <&aic>;
-			interrupts = <AIC_IRQ 631 IRQ_TYPE_LEVEL_HIGH>;
-			pinctrl-0 = <&i2c4_pins>;
-			pinctrl-names = "default";
-			#address-cells = <0x1>;
-			#size-cells = <0x0>;
-			power-domains = <&ps_i2c4>;
-			status = "disabled"; /* only used in J293 */
-		};
-
-		spi3: spi@23510c000 {
-			compatible = "apple,t8103-spi", "apple,spi";
-			reg = <0x2 0x3510c000 0x0 0x4000>;
-			interrupt-parent = <&aic>;
-			interrupts = <AIC_IRQ 617 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&clk_120m>;
-			pinctrl-0 = <&spi3_pins>;
-			pinctrl-names = "default";
-			power-domains = <&ps_spi3>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "disabled"; /* only used in J293/J313 */
-		};
-
-		serial0: serial@235200000 {
-			compatible = "apple,s5l-uart";
-			reg = <0x2 0x35200000 0x0 0x1000>;
-			reg-io-width = <4>;
-			interrupt-parent = <&aic>;
-			interrupts = <AIC_IRQ 605 IRQ_TYPE_LEVEL_HIGH>;
-			/*
-			 * TODO: figure out the clocking properly, there may
-			 * be a third selectable clock.
-			 */
-			clocks = <&clkref>, <&clkref>;
-			clock-names = "uart", "clk_uart_baud0";
-			power-domains = <&ps_uart0>;
-			status = "disabled";
-		};
-
-		serial2: serial@235208000 {
-			compatible = "apple,s5l-uart";
-			reg = <0x2 0x35208000 0x0 0x1000>;
-			reg-io-width = <4>;
-			interrupt-parent = <&aic>;
-			interrupts = <AIC_IRQ 607 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&clkref>, <&clkref>;
-			clock-names = "uart", "clk_uart_baud0";
-			power-domains = <&ps_uart2>;
-			status = "disabled";
-		};
-
-		aic: interrupt-controller@23b100000 {
-			compatible = "apple,t8103-aic", "apple,aic";
-			#interrupt-cells = <3>;
-			interrupt-controller;
-			reg = <0x2 0x3b100000 0x0 0x8000>;
-			power-domains = <&ps_aic>;
-		};
-
-		pmgr: power-management@23b700000 {
-			compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			reg = <0x2 0x3b700000 0 0x14000>;
-		};
-
-		pinctrl_ap: pinctrl@23c100000 {
-			compatible = "apple,t8103-pinctrl", "apple,pinctrl";
-			reg = <0x2 0x3c100000 0x0 0x100000>;
-			power-domains = <&ps_gpio>;
-
-			gpio-controller;
-			#gpio-cells = <2>;
-			gpio-ranges = <&pinctrl_ap 0 0 212>;
-			apple,npins = <212>;
-
-			interrupt-controller;
-			#interrupt-cells = <2>;
-			interrupt-parent = <&aic>;
-			interrupts = <AIC_IRQ 190 IRQ_TYPE_LEVEL_HIGH>,
-				     <AIC_IRQ 191 IRQ_TYPE_LEVEL_HIGH>,
-				     <AIC_IRQ 192 IRQ_TYPE_LEVEL_HIGH>,
-				     <AIC_IRQ 193 IRQ_TYPE_LEVEL_HIGH>,
-				     <AIC_IRQ 194 IRQ_TYPE_LEVEL_HIGH>,
-				     <AIC_IRQ 195 IRQ_TYPE_LEVEL_HIGH>,
-				     <AIC_IRQ 196 IRQ_TYPE_LEVEL_HIGH>;
-
-			i2c0_pins: i2c0-pins {
-				pinmux = <APPLE_PINMUX(192, 1)>,
-					 <APPLE_PINMUX(188, 1)>;
-			};
-
-			i2c1_pins: i2c1-pins {
-				pinmux = <APPLE_PINMUX(201, 1)>,
-					 <APPLE_PINMUX(199, 1)>;
-			};
-
-			i2c2_pins: i2c2-pins {
-				pinmux = <APPLE_PINMUX(163, 1)>,
-					 <APPLE_PINMUX(162, 1)>;
-			};
-
-			i2c3_pins: i2c3-pins {
-				pinmux = <APPLE_PINMUX(73, 1)>,
-					 <APPLE_PINMUX(72, 1)>;
-			};
-
-			i2c4_pins: i2c4-pins {
-				pinmux = <APPLE_PINMUX(135, 1)>,
-					 <APPLE_PINMUX(134, 1)>;
-			};
-
-			spi3_pins: spi3-pins {
-				pinmux = <APPLE_PINMUX(46, 1)>,
-					<APPLE_PINMUX(47, 1)>,
-					<APPLE_PINMUX(48, 1)>,
-					<APPLE_PINMUX(49, 1)>;
-			};
-
-			pcie_pins: pcie-pins {
-				pinmux = <APPLE_PINMUX(150, 1)>,
-					 <APPLE_PINMUX(151, 1)>,
-					 <APPLE_PINMUX(32, 1)>;
-			};
-		};
-
-		spmi: spmi@23d0d9300 {
-			compatible = "apple,t8103-spmi", "apple,spmi";
-			reg = <0x2 0x3d0d9300 0x0 0x100>;
-			interrupt-parent = <&aic>;
-			interrupts = <AIC_IRQ 343 IRQ_TYPE_LEVEL_HIGH>;
-			#address-cells = <2>;
-			#size-cells = <0>;
-			status = "disabled";
-		};
-
-		pinctrl_nub: pinctrl@23d1f0000 {
-			compatible = "apple,t8103-pinctrl", "apple,pinctrl";
-			reg = <0x2 0x3d1f0000 0x0 0x4000>;
-			power-domains = <&ps_nub_gpio>;
-
-			gpio-controller;
-			#gpio-cells = <2>;
-			gpio-ranges = <&pinctrl_nub 0 0 23>;
-			apple,npins = <23>;
-
-			interrupt-controller;
-			#interrupt-cells = <2>;
-			interrupt-parent = <&aic>;
-			interrupts = <AIC_IRQ 330 IRQ_TYPE_LEVEL_HIGH>,
-				     <AIC_IRQ 331 IRQ_TYPE_LEVEL_HIGH>,
-				     <AIC_IRQ 332 IRQ_TYPE_LEVEL_HIGH>,
-				     <AIC_IRQ 333 IRQ_TYPE_LEVEL_HIGH>,
-				     <AIC_IRQ 334 IRQ_TYPE_LEVEL_HIGH>,
-				     <AIC_IRQ 335 IRQ_TYPE_LEVEL_HIGH>,
-				     <AIC_IRQ 336 IRQ_TYPE_LEVEL_HIGH>;
-		};
-
-		pmgr_mini: power-management@23d280000 {
-			compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			reg = <0x2 0x3d280000 0 0x4000>;
-		};
-
-		wdt: watchdog@23d2b0000 {
-			compatible = "apple,t8103-wdt", "apple,wdt";
-			reg = <0x2 0x3d2b0000 0x0 0x4000>;
-			clocks = <&clkref>;
-			interrupt-parent = <&aic>;
-			interrupts = <AIC_IRQ 338 IRQ_TYPE_LEVEL_HIGH>;
-		};
-
-		pinctrl_smc: pinctrl@23e820000 {
-			compatible = "apple,t8103-pinctrl", "apple,pinctrl";
-			reg = <0x2 0x3e820000 0x0 0x4000>;
-
-			gpio-controller;
-			#gpio-cells = <2>;
-			gpio-ranges = <&pinctrl_smc 0 0 16>;
-			apple,npins = <16>;
-
-			interrupt-controller;
-			#interrupt-cells = <2>;
-			interrupt-parent = <&aic>;
-			interrupts = <AIC_IRQ 391 IRQ_TYPE_LEVEL_HIGH>,
-				     <AIC_IRQ 392 IRQ_TYPE_LEVEL_HIGH>,
-				     <AIC_IRQ 393 IRQ_TYPE_LEVEL_HIGH>,
-				     <AIC_IRQ 394 IRQ_TYPE_LEVEL_HIGH>,
-				     <AIC_IRQ 395 IRQ_TYPE_LEVEL_HIGH>,
-				     <AIC_IRQ 396 IRQ_TYPE_LEVEL_HIGH>,
-				     <AIC_IRQ 397 IRQ_TYPE_LEVEL_HIGH>;
-		};
-
-		smc_mbox: mbox@23e408000 {
-			compatible = "apple,t8103-asc-mailbox", "apple,asc-mailbox-v4";
-			reg = <0x2 0x3e408000 0x0 0x4000>;
-			interrupt-parent = <&aic>;
-			interrupts = <AIC_IRQ 400 IRQ_TYPE_LEVEL_HIGH>,
-				     <AIC_IRQ 401 IRQ_TYPE_LEVEL_HIGH>,
-				     <AIC_IRQ 402 IRQ_TYPE_LEVEL_HIGH>,
-				     <AIC_IRQ 403 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "send-empty", "send-not-empty",
-					  "recv-empty", "recv-not-empty";
-			#mbox-cells = <0>;
-		};
-
-		smc: smc@23e050000 {
-			compatible = "apple,smc";
-			reg = <0x2 0x3e050000 0x0 0x4000>;
-			mboxes = <&smc_mbox>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			gpio-13 = <0x00800000>;
-		};
-
-		pinctrl_aop: pinctrl@24a820000 {
-			compatible = "apple,t8103-pinctrl", "apple,pinctrl";
-			reg = <0x2 0x4a820000 0x0 0x4000>;
-
-			gpio-controller;
-			#gpio-cells = <2>;
-			gpio-ranges = <&pinctrl_aop 0 0 42>;
-			apple,npins = <42>;
-
-			interrupt-controller;
-			#interrupt-cells = <2>;
-			interrupt-parent = <&aic>;
-			interrupts = <AIC_IRQ 268 IRQ_TYPE_LEVEL_HIGH>,
-				     <AIC_IRQ 269 IRQ_TYPE_LEVEL_HIGH>,
-				     <AIC_IRQ 270 IRQ_TYPE_LEVEL_HIGH>,
-				     <AIC_IRQ 271 IRQ_TYPE_LEVEL_HIGH>,
-				     <AIC_IRQ 272 IRQ_TYPE_LEVEL_HIGH>,
-				     <AIC_IRQ 273 IRQ_TYPE_LEVEL_HIGH>,
-				     <AIC_IRQ 274 IRQ_TYPE_LEVEL_HIGH>;
-		};
-
-		ans_mbox: mbox@277408000 {
-			compatible = "apple,t8103-asc-mailbox", "apple,asc-mailbox-v4";
-			reg = <0x2 0x77408000 0x0 0x4000>;
-			interrupt-parent = <&aic>;
-			interrupts = <AIC_IRQ 583 IRQ_TYPE_LEVEL_HIGH>,
-				<AIC_IRQ 584 IRQ_TYPE_LEVEL_HIGH>,
-				<AIC_IRQ 585 IRQ_TYPE_LEVEL_HIGH>,
-				<AIC_IRQ 586 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "send-empty", "send-not-empty",
-				"recv-empty", "recv-not-empty";
-			#mbox-cells = <0>;
-			power-domains = <&ps_ans2>;
-		};
-
-		sart: sart@27bc50000 {
-			compatible = "apple,t8103-sart", "apple,sart2";
-			reg = <0x2 0x7bc50000 0x0 0x10000>;
-			power-domains = <&ps_ans2>;
-		};
-
-		nvme@27bcc0000 {
-			compatible = "apple,t8103-nvme-ans2", "apple,nvme-ans2";
-			reg = <0x2 0x7bcc0000 0x0 0x40000>,
-				<0x2 0x77400000 0x0 0x4000>;
-			reg-names = "nvme", "ans";
-			interrupt-parent = <&aic>;
-			interrupts = <AIC_IRQ 590 IRQ_TYPE_LEVEL_HIGH>;
-			mboxes = <&ans_mbox>;
-			apple,sart = <&sart>;
-			power-domains = <&ps_ans2>;
-			resets = <&ps_ans2>;
-		};
-
-		dwc3_0: usb@382280000 {
-			compatible = "apple,t8103-dwc3", "apple,dwc3", "snps,dwc3";
-			reg = <0x3 0x82280000 0x0 0x100000>;
-			interrupt-parent = <&aic>;
-			interrupts = <AIC_IRQ 777 IRQ_TYPE_LEVEL_HIGH>;
-			usb-role-switch;
-			role-switch-default-mode = "host";
-			iommus = <&dwc3_0_dart_0 0>, <&dwc3_0_dart_1 1>;
-			power-domains = <&ps_atc0_usb>;
-		};
-
-		dwc3_0_dart_0: iommu@382f00000 {
-			compatible = "apple,t8103-dart";
-			reg = <0x3 0x82f00000 0x0 0x4000>;
-			interrupt-parent = <&aic>;
-			interrupts = <AIC_IRQ 781 IRQ_TYPE_LEVEL_HIGH>;
-			#iommu-cells = <1>;
-			power-domains = <&ps_atc0_usb>;
-		};
-
-		dwc3_0_dart_1: iommu@382f80000 {
-			compatible = "apple,t8103-dart";
-			reg = <0x3 0x82f80000 0x0 0x4000>;
-			interrupt-parent = <&aic>;
-			interrupts = <AIC_IRQ 781 IRQ_TYPE_LEVEL_HIGH>;
-			#iommu-cells = <1>;
-			power-domains = <&ps_atc0_usb>;
-		};
-
-		dwc3_1: usb@502280000 {
-			compatible = "apple,t8103-dwc3", "apple,dwc3", "snps,dwc3";
-			reg = <0x5 0x02280000 0x0 0x100000>;
-			interrupt-parent = <&aic>;
-			interrupts = <AIC_IRQ 857 IRQ_TYPE_LEVEL_HIGH>;
-			usb-role-switch;
-			role-switch-default-mode = "host";
-			iommus = <&dwc3_1_dart_0 0>, <&dwc3_1_dart_1 1>;
-			power-domains = <&ps_atc1_usb>;
-		};
-
-		dwc3_1_dart_0: iommu@502f00000 {
-			compatible = "apple,t8103-dart";
-			reg = <0x5 0x02f00000 0x0 0x4000>;
-			interrupt-parent = <&aic>;
-			interrupts = <AIC_IRQ 861 IRQ_TYPE_LEVEL_HIGH>;
-			#iommu-cells = <1>;
-			power-domains = <&ps_atc1_usb>;
-		};
-
-		dwc3_1_dart_1: iommu@502f80000 {
-			compatible = "apple,t8103-dart";
-			reg = <0x5 0x02f80000 0x0 0x4000>;
-			interrupt-parent = <&aic>;
-			interrupts = <AIC_IRQ 861 IRQ_TYPE_LEVEL_HIGH>;
-			#iommu-cells = <1>;
-			power-domains = <&ps_atc1_usb>;
-		};
-
-		pcie0_dart_0: dart@681008000 {
-			compatible = "apple,t8103-dart";
-			reg = <0x6 0x81008000 0x0 0x4000>;
-			#iommu-cells = <1>;
-			interrupt-parent = <&aic>;
-			interrupts = <AIC_IRQ 696 IRQ_TYPE_LEVEL_HIGH>;
-			power-domains = <&ps_apcie_gp>;
-		};
-
-		pcie0_dart_1: dart@682008000 {
-			compatible = "apple,t8103-dart";
-			reg = <0x6 0x82008000 0x0 0x4000>;
-			#iommu-cells = <1>;
-			interrupt-parent = <&aic>;
-			interrupts = <AIC_IRQ 699 IRQ_TYPE_LEVEL_HIGH>;
-			power-domains = <&ps_apcie_gp>;
-		};
-
-		pcie0_dart_2: dart@683008000 {
-			compatible = "apple,t8103-dart";
-			reg = <0x6 0x83008000 0x0 0x4000>;
-			#iommu-cells = <1>;
-			interrupt-parent = <&aic>;
-			interrupts = <AIC_IRQ 702 IRQ_TYPE_LEVEL_HIGH>;
-			power-domains = <&ps_apcie_gp>;
-		};
-
-		pcie0: pcie@690000000 {
-			compatible = "apple,t8103-pcie", "apple,pcie";
-			device_type = "pci";
-
-			reg = <0x6 0x90000000 0x0 0x1000000>,
-			      <0x6 0x80000000 0x0 0x100000>,
-			      <0x6 0x81000000 0x0 0x4000>,
-			      <0x6 0x82000000 0x0 0x4000>,
-			      <0x6 0x83000000 0x0 0x4000>;
-			reg-names = "config", "rc", "port0", "port1", "port2";
-
-			interrupt-parent = <&aic>;
-			interrupts = <AIC_IRQ 695 IRQ_TYPE_LEVEL_HIGH>,
-				     <AIC_IRQ 698 IRQ_TYPE_LEVEL_HIGH>,
-				     <AIC_IRQ 701 IRQ_TYPE_LEVEL_HIGH>;
-
-			msi-controller;
-			msi-parent = <&pcie0>;
-			msi-ranges = <&aic AIC_IRQ 704 IRQ_TYPE_EDGE_RISING 32>;
-
-
-			iommu-map = <0x100 &pcie0_dart_0 1 1>,
-				    <0x200 &pcie0_dart_1 1 1>,
-				    <0x300 &pcie0_dart_2 1 1>;
-			iommu-map-mask = <0xff00>;
-
-			bus-range = <0 3>;
-			#address-cells = <3>;
-			#size-cells = <2>;
-			ranges = <0x43000000 0x6 0xa0000000 0x6 0xa0000000 0x0 0x20000000>,
-				 <0x02000000 0x0 0xc0000000 0x6 0xc0000000 0x0 0x40000000>;
-
-			power-domains = <&ps_apcie_gp>;
-			pinctrl-0 = <&pcie_pins>;
-			pinctrl-names = "default";
-
-			port00: pci@0,0 {
-				device_type = "pci";
-				reg = <0x0 0x0 0x0 0x0 0x0>;
-				reset-gpios = <&pinctrl_ap 152 GPIO_ACTIVE_LOW>;
-
-				#address-cells = <3>;
-				#size-cells = <2>;
-				ranges;
-
-				interrupt-controller;
-				#interrupt-cells = <1>;
-
-				interrupt-map-mask = <0 0 0 7>;
-				interrupt-map = <0 0 0 1 &port00 0 0 0 0>,
-						<0 0 0 2 &port00 0 0 0 1>,
-						<0 0 0 3 &port00 0 0 0 2>,
-						<0 0 0 4 &port00 0 0 0 3>;
-			};
-
-			port01: pci@1,0 {
-				device_type = "pci";
-				reg = <0x800 0x0 0x0 0x0 0x0>;
-				reset-gpios = <&pinctrl_ap 153 GPIO_ACTIVE_LOW>;
-
-				#address-cells = <3>;
-				#size-cells = <2>;
-				ranges;
-
-				interrupt-controller;
-				#interrupt-cells = <1>;
-
-				interrupt-map-mask = <0 0 0 7>;
-				interrupt-map = <0 0 0 1 &port01 0 0 0 0>,
-						<0 0 0 2 &port01 0 0 0 1>,
-						<0 0 0 3 &port01 0 0 0 2>,
-						<0 0 0 4 &port01 0 0 0 3>;
-			};
-
-			port02: pci@2,0 {
-				device_type = "pci";
-				reg = <0x1000 0x0 0x0 0x0 0x0>;
-				reset-gpios = <&pinctrl_ap 33 GPIO_ACTIVE_LOW>;
-
-				#address-cells = <3>;
-				#size-cells = <2>;
-				ranges;
-
-				interrupt-controller;
-				#interrupt-cells = <1>;
-
-				interrupt-map-mask = <0 0 0 7>;
-				interrupt-map = <0 0 0 1 &port02 0 0 0 0>,
-						<0 0 0 2 &port02 0 0 0 1>,
-						<0 0 0 3 &port02 0 0 0 2>,
-						<0 0 0 4 &port02 0 0 0 3>;
-			};
-		};
-
-		dart_sio: iommu@235004000 {
-			compatible = "apple,t8103-dart", "apple,dart";
-			reg = <0x2 0x35004000 0x0 0x4000>;
-			interrupt-parent = <&aic>;
-			interrupts = <AIC_IRQ 635 IRQ_TYPE_LEVEL_HIGH>;
-			#iommu-cells = <1>;
-			power-domains = <&ps_sio_cpu>;
-		};
-
-		nco_inp: clock-ref {
-			compatible = "fixed-factor-clock";
-			clocks = <&clkref>;
-			#clock-cells = <0>;
-			clock-mult = <75>;
-			clock-div = <2>; // 24 MHz * (75/2) = 900 MHz
-			clock-output-names = "nco_inp";
-		};
-
-		nco: nco@23b044000 {
-			compatible = "apple,t8103-nco", "apple,nco";
-			reg = <0x2 0x3b044000 0x0 0x14000>;
-			clocks = <&nco_inp>;
-			#clock-cells = <1>;
-			apple,nchannels = <5>;
-		};
-
-		admac: dma-controller@238200000 {
-			compatible = "apple,t8103-admac", "apple,admac";
-			reg = <0x2 0x38200000 0x0 0x34000>;
-			dma-channels = <12>;
-			interrupt-parent = <&aic>;
-			interrupts = <AIC_IRQ 626 IRQ_TYPE_LEVEL_HIGH>;
-			#dma-cells = <1>;
-			iommus = <&dart_sio 2>;
-			power-domains = <&ps_sio_adma>;
-		};
-
-		mca: mca {
-			compatible = "apple,t8103-mca", "apple,mca";
-			reg = <0x2 0x38400000 0x0 0x18000>,
-				<0x2 0x38300000 0x0 0x30000>;
-			reg-names = "clusters", "switch";
-			clocks = <&nco 0>, <&nco 1>, <&nco 2>, <&nco 3>;
-			power-domains = <&ps_mca0>; //, <&ps_mca1>, <&ps_mca2>, <&ps_mca3>, <&ps_mca4>, <&ps_mca5>;
-			resets = <&ps_mca0>, <&ps_mca1>, <&ps_mca2>, <&ps_mca3>, <&ps_mca4>, <&ps_mca5>;
-
-			#sound-dai-cells = <1>;
-			apple,nclusters = <6>;
-			apple,mclk-range = <2600000 25000000>;
-
-			route {
-				dmas = <&admac 2>;
-				dma-names = "tx";
-				apple,serdes = <1>;
-				sound-dai = <&mca 0>;
-			};
-
-			route2 {
-				dmas = <&admac 6>;
-				dma-names = "tx";
-				apple,serdes = <3>;
-				sound-dai = <&mca 2>;
-			};
-		};
-	};
-};
-
-#include "t8103-pmgr.dtsi"

arch/arm/include/asm/armv8/mmu.h

@@ -222,6 +222,11 @@ u64 get_tcr(u64 *pips, u64 *pva_bits);
  * mmu_setup() - Sets up the mmu page tables as per mem_map
  */
 void mmu_setup(void);
+
+/**
+ * mmu_enable() - Enable the MMU by setting 'M' bit in SCTLR register
+ */
+void mmu_enable(void);
 #endif
 
 #endif /* _ASM_ARMV8_MMU_H_ */

arch/arm/mach-apple/Kconfig

@@ -3,12 +3,22 @@ if ARCH_APPLE
 config TEXT_BASE
 	default 0x00000000
 
-config SYS_CONFIG_NAME
-	default "apple"
-
 config SYS_SOC
 	default "apple"
 
+config SYS_VENDOR
+	default "apple"
+
+config SYS_BOARD
+	string "Board name"
+	default "mac"
+	help
+	  This option contains information about board name.
+	  Based on this option board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD> will
+	  be used.
+	  Apple silicon based devices are expected to use the generic board name
+	  "mac".
+
 config SYS_MALLOC_LEN
 	default 0x4000000
 

arch/arm/mach-apple/board.c

@@ -673,6 +673,83 @@ static struct mm_region t6022_mem_map[] = {
 	}
 };
 
+/* Apple M3 */
+
+static struct mm_region t8122_mem_map[] = {
+	{
+		/* I/O */
+		.virt = 0x200000000,
+		.phys = 0x200000000,
+		.size = 4UL * SZ_1G,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		/* NVMe */
+		.virt = 0x300000000,
+		.phys = 0x300000000,
+		.size = SZ_1G,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		/* PCIE */
+		.virt = 0x580000000,
+		.phys = 0x580000000,
+		.size = SZ_512M,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		/* PCIE */
+		.virt = 0x5a0000000,
+		.phys = 0x5a0000000,
+		.size = SZ_512M,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
+			 PTE_BLOCK_INNER_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		/* PCIE */
+		.virt = 0x5c0000000,
+		.phys = 0x5c0000000,
+		.size = SZ_1G,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
+			 PTE_BLOCK_INNER_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		/* I/O ATC0 */
+		.virt = 0x700000000,
+		.phys = 0x700000000,
+		.size = SZ_1G,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		/* I/O ATC1 */
+		.virt = 0xb00000000,
+		.phys = 0xb00000000,
+		.size = SZ_1G,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		/* RAM */
+		.virt = 0x10000000000,
+		.phys = 0x10000000000,
+		.size = 8UL * SZ_1G,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		/* Framebuffer */
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
+			 PTE_BLOCK_INNER_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		/* List terminator */
+		0,
+	}
+};
+
 struct mm_region *mem_map;
 
 int board_init(void)
@@ -720,6 +797,8 @@ void build_mem_map(void)
 		mem_map = t6020_mem_map;
 	else if (of_machine_is_compatible("apple,t6022"))
 		mem_map = t6022_mem_map;
+	else if (of_machine_is_compatible("apple,t8122"))
+		mem_map = t8122_mem_map;
 	else
 		panic("Unsupported SoC\n");
 

arch/arm/mach-apple/rtkit_helper.c

@@ -11,6 +11,7 @@
 #include <asm/io.h>
 #include <asm/arch/rtkit.h>
 #include <linux/iopoll.h>
+#include <linux/sizes.h>
 
 /* ASC registers */
 #define REG_CPU_CTRL		0x0044

arch/arm/mach-k3/common.c

@@ -294,6 +294,7 @@ void enable_caches(void)
 			       __func__, ret);
 	}
 
+	mmu_enable();
 	icache_enable();
 	dcache_enable();
 }

arch/arm/mach-renesas/Kconfig.rcar5

@@ -13,7 +13,9 @@ menu "Select Target SoC"
 config R8A78000
 	bool "Renesas SoC R8A78000"
 	select GICV3
+	imply CLK_R8A78000
 	imply PINCTRL_PFC_R8A78000
+	imply RENESAS_R8A78000_POWER_DOMAIN
 
 endmenu
 

arch/arm/mach-renesas/Makefile

@@ -40,6 +40,27 @@ else
 	srec_cat_le_cmd := "-l-e-constant"
 endif
 
+ifneq ($(CONFIG_RCAR_GEN5),)
+quiet_cmd_srec_cat = SRECCAT $@
+      cmd_srec_cat = srec_cat -output $@ -M 8 $< -M 8 \
+			-Output_Block_Size 16 \
+			-generate 0x18402010 0x18402014 $(srec_cat_le_cmd) $(CONFIG_SYS_UBOOT_START) 4 \
+			-generate 0x18402014 0x18402018 $(srec_cat_le_cmd) 0x1ef000 4
+
+quiet_cmd_srec_shdr_cat = SRECCAT $@
+      cmd_srec_shdr_cat = srec_cat -output $@ -M 8 \
+			-Output_Block_Size 16 \
+			-generate 0x18400000 0x18400004 $(srec_cat_le_cmd) 0x00000003 4 \
+			-generate 0x18400004 0x18400008 $(srec_cat_le_cmd) 0x0 4 \
+			-generate 0x18402000 0x18402004 $(srec_cat_le_cmd) 0x6b657963 4 \
+			-generate 0x18402004 0x18402008 $(srec_cat_le_cmd) 0x00010010 4 \
+			-generate 0x18402008 0x1840200c $(srec_cat_le_cmd) 0x0 4 \
+			-generate 0x1840200c 0x18402010 $(srec_cat_le_cmd) 0x34040000 4 \
+			-generate 0x18402010 0x18402014 $(srec_cat_le_cmd) $(CONFIG_SYS_UBOOT_START) 4 \
+			-generate 0x18402014 0x18402018 $(srec_cat_le_cmd) 0x1ef000 4 \
+			-generate 0x18402018 0x1840201c $(srec_cat_le_cmd) 0x0 4 \
+			-generate 0x1840201c 0x18402020 $(srec_cat_le_cmd) 0x0 4
+else
 ifneq ($(CONFIG_RCAR_GEN4),)
 quiet_cmd_srec_cat = SRECCAT $@
       cmd_srec_cat = srec_cat -output $@ -M 8 $< -M 8 \
@@ -106,10 +127,17 @@ quiet_cmd_srec_cat = SRECCAT $@
 			-generate 0xe6301264 0xe6301268 $(srec_cat_le_cmd) $2 4
 endif
 endif
+endif
 
 spl/u-boot-spl.scif: spl/u-boot-spl.srec spl/u-boot-spl.bin
 	$(call cmd,srec_cat,$(shell wc -c spl/u-boot-spl.bin | awk '{printf("0x%08x\n",$$1)}'))
 
+u-boot-elf.scif: u-boot-elf.srec u-boot.bin
+	$(call cmd,srec_cat,$(shell wc -c u-boot-dtb.bin | awk '{printf("0x%08x\n",$$1)}'))
+
+u-boot-elf.shdr: u-boot-elf.srec u-boot.bin
+	$(call cmd,srec_shdr_cat,$(shell wc -c u-boot-dtb.bin | awk '{printf("0x%08x\n",$$1)}'))
+
 # if srec_cat is present build u-boot-spl.scif by default
 has_srec_cat = $(call try-run,srec_cat -VERSion,y,n)
 INPUTS-$(has_srec_cat) += u-boot-spl.scif

arch/arm/mach-renesas/u-boot-rsip.lds

@@ -0,0 +1,203 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2004-2008 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ */
+
+#include <config.h>
+#include <asm/psci.h>
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+#if defined(CONFIG_ARMV7_SECURE_BASE) && defined(CONFIG_ARMV7_NONSEC)
+	/*
+	 * If CONFIG_ARMV7_SECURE_BASE is true, secure code will not
+	 * bundle with u-boot, and code offsets are fixed. Secure zone
+	 * only needs to be copied from the loading address to
+	 * CONFIG_ARMV7_SECURE_BASE, which is the linking and running
+	 * address for secure code.
+	 *
+	 * If CONFIG_ARMV7_SECURE_BASE is undefined, the secure zone will
+	 * be included in u-boot address space, and some absolute address
+	 * were used in secure code. The absolute addresses of the secure
+	 * code also needs to be relocated along with the accompanying u-boot
+	 * code.
+	 *
+	 * So DISCARD is only for CONFIG_ARMV7_SECURE_BASE.
+	 */
+	/DISCARD/ : { *(.rel._secure*) }
+#endif
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	__image_copy_start = ADDR(.text);
+	.text :
+	{
+		CPUDIR/start.o (.text*)
+		*(.vectors)
+	}
+
+	/* This needs to come before *(.text*) */
+	.efi_runtime : {
+		__efi_runtime_start = .;
+		*(.text.efi_runtime*)
+		*(.rodata.efi_runtime*)
+		*(.data.efi_runtime*)
+		__efi_runtime_stop = .;
+	}
+
+	.text_rest :
+	{
+		*(.text*)
+	}
+
+#ifdef CONFIG_ARMV7_NONSEC
+
+	/* Align the secure section only if we're going to use it in situ */
+	.__secure_start
+#ifndef CONFIG_ARMV7_SECURE_BASE
+		ALIGN(CONSTANT(COMMONPAGESIZE))
+#endif
+	: {
+		KEEP(*(.__secure_start))
+	}
+
+#ifndef CONFIG_ARMV7_SECURE_BASE
+#define __ARMV7_SECURE_BASE
+#define __ARMV7_PSCI_STACK_IN_RAM
+#else
+#define __ARMV7_SECURE_BASE	CONFIG_ARMV7_SECURE_BASE
+#endif
+
+	.secure_text __ARMV7_SECURE_BASE :
+		AT(ADDR(.__secure_start) + SIZEOF(.__secure_start))
+	{
+		*(._secure.text)
+	}
+
+	.secure_data : AT(LOADADDR(.secure_text) + SIZEOF(.secure_text))
+	{
+		*(._secure.data)
+	}
+
+#ifdef CONFIG_ARMV7_PSCI
+	.secure_stack ALIGN(ADDR(.secure_data) + SIZEOF(.secure_data),
+			    CONSTANT(COMMONPAGESIZE)) (NOLOAD) :
+#ifdef __ARMV7_PSCI_STACK_IN_RAM
+		AT(ADDR(.secure_stack))
+#else
+		AT(LOADADDR(.secure_data) + SIZEOF(.secure_data))
+#endif
+	{
+		KEEP(*(.__secure_stack_start))
+
+		/* Skip addresses for stack */
+		. = . + CONFIG_ARMV7_PSCI_NR_CPUS * ARM_PSCI_STACK_SIZE;
+
+		/* Align end of stack section to page boundary */
+		. = ALIGN(CONSTANT(COMMONPAGESIZE));
+
+		KEEP(*(.__secure_stack_end))
+
+#ifdef CONFIG_ARMV7_SECURE_MAX_SIZE
+		/*
+		 * We are not checking (__secure_end - __secure_start) here,
+		 * as these are the load addresses, and do not include the
+		 * stack section. Instead, use the end of the stack section
+		 * and the start of the text section.
+		 */
+		ASSERT((. - ADDR(.secure_text)) <= CONFIG_ARMV7_SECURE_MAX_SIZE,
+		       "Error: secure section exceeds secure memory size");
+#endif
+	}
+
+#ifndef __ARMV7_PSCI_STACK_IN_RAM
+	/* Reset VMA but don't allocate space if we have secure SRAM */
+	. = LOADADDR(.secure_stack);
+#endif
+
+#endif
+
+	.__secure_end : AT(ADDR(.__secure_end)) {
+		*(.__secure_end)
+		LONG(0x1d1071c);	/* Must output something to reset LMA */
+	}
+#endif
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : {
+		__data_start = .;
+		*(.data*)
+		__data_end = .;
+	}
+
+	. = ALIGN(4);
+
+	. = .;
+
+	. = ALIGN(4);
+	__u_boot_list : {
+		KEEP(*(SORT(__u_boot_list*)));
+	}
+
+	.efi_runtime_rel : {
+		__efi_runtime_rel_start = .;
+		*(.rel*.efi_runtime)
+		*(.rel*.efi_runtime.*)
+		__efi_runtime_rel_stop = .;
+	}
+
+	. = ALIGN(8);
+	__image_copy_end = .;
+
+	/*
+	 * if CONFIG_USE_ARCH_MEMSET is not selected __bss_end - __bss_start
+	 * needs to be a multiple of 8 and we overlay .bss with .rel.dyn
+	 */
+	.rel.dyn ALIGN(8) : {
+		__rel_dyn_start = .;
+		*(.rel*)
+		__rel_dyn_end = .;
+		. = ALIGN(8);
+	}
+
+	_end = .;
+	_image_binary_end = .;
+
+/*
+ * These sections occupy the same memory, but their lifetimes do
+ * not overlap: U-Boot initializes .bss only after applying dynamic
+ * relocations and therefore after it doesn't need .rel.dyn any more.
+ */
+
+	/* BSS goes to special read-write offset below U-Boot entry point */
+	. = 0xb8400000;
+	.bss (OVERLAY): {
+		__bss_start = .;
+		*(.bss*)
+		. = ALIGN(4);
+		__bss_end = .;
+	}
+
+	/DISCARD/ : { *(.dynsym) }
+	/DISCARD/ : { *(.dynbss) }
+	/DISCARD/ : { *(.dynstr*) }
+	/DISCARD/ : { *(.dynamic*) }
+	/DISCARD/ : { *(.plt*) }
+	/DISCARD/ : { *(.interp*) }
+	/DISCARD/ : { *(.gnu.hash) }
+	/DISCARD/ : { *(.gnu*) }
+	/DISCARD/ : { *(.ARM.exidx*) }
+	/DISCARD/ : { *(.gnu.linkonce.armexidx.*) }
+}
+
+ASSERT(_image_binary_end % 8 == 0, \
+       "_image_binary_end must be 8-byte aligned for device tree");

arch/arm/mach-stm32mp/Kconfig

@@ -114,7 +114,6 @@ config STM32MP23X
 	select OF_BOARD
 	select PINCTRL_STM32
 	select STM32_RCC
-	select STM32_RESET
 	select STM32_SERIAL
 	select STM32MP_TAMP_NVMEM
 	select SYS_ARCH_TIMER

arch/arm/mach-stm32mp/include/mach/sys_proto.h

@@ -61,20 +61,20 @@
 /* ID for STM32MP25x = Device Part Number (RPN) (bit31:0) */
 #define CPU_STM32MP257Cxx	0x00002000
 #define CPU_STM32MP255Cxx	0x00082000
-#define CPU_STM32MP253Cxx	0x000B2004
-#define CPU_STM32MP251Cxx	0x000B3065
+#define CPU_STM32MP253Cxx	0x000B300C
+#define CPU_STM32MP251Cxx	0x000B306D
 #define CPU_STM32MP257Axx	0x40002E00
 #define CPU_STM32MP255Axx	0x40082E00
-#define CPU_STM32MP253Axx	0x400B2E04
-#define CPU_STM32MP251Axx	0x400B3E65
+#define CPU_STM32MP253Axx	0x400B3E0C
+#define CPU_STM32MP251Axx	0x400B3E6D
 #define CPU_STM32MP257Fxx	0x80002000
 #define CPU_STM32MP255Fxx	0x80082000
-#define CPU_STM32MP253Fxx	0x800B2004
-#define CPU_STM32MP251Fxx	0x800B3065
+#define CPU_STM32MP253Fxx	0x800B300C
+#define CPU_STM32MP251Fxx	0x800B306D
 #define CPU_STM32MP257Dxx	0xC0002E00
 #define CPU_STM32MP255Dxx	0xC0082E00
-#define CPU_STM32MP253Dxx	0xC00B2E04
-#define CPU_STM32MP251Dxx	0xC00B3E65
+#define CPU_STM32MP253Dxx	0xC00B3E0C
+#define CPU_STM32MP251Dxx	0xC00B3E6D
 
 /* return CPU_STMP32MP...Xxx constants */
 u32 get_cpu_type(void);

arch/powerpc/cpu/mpc85xx/cpu_init.c

@@ -41,10 +41,12 @@
 #ifdef CONFIG_FSL_CAAM
 #include <fsl_sec.h>
 #endif
-#if defined(CONFIG_NXP_ESBC) && defined(CONFIG_FSL_CORENET)
+#if defined(CONFIG_FSL_CORENET)
 #include <asm/fsl_pamu.h>
+#if defined(CONFIG_NXP_ESBC)
 #include <fsl_secboot_err.h>
 #endif
+#endif
 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
 #include <nand.h>
 #include <errno.h>
@@ -899,6 +901,8 @@ int cpu_init_r(void)
 #if defined(CONFIG_NXP_ESBC) && defined(CONFIG_FSL_CORENET)
 	if (pamu_init() < 0)
 		fsl_secboot_handle_error(ERROR_ESBC_PAMU_INIT);
+#elif defined(CONFIG_FSL_CORENET)
+	pamu_init();
 #endif
 
 #ifdef CONFIG_FSL_CAAM

arch/powerpc/dts/Makefile

@@ -14,7 +14,6 @@ dtb-$(CONFIG_TARGET_P1010RDB_PB) += p1010rdb-pb.dtb p1010rdb-pb_36b.dtb
 dtb-$(CONFIG_TARGET_P1020RDB_PC) += p1020rdb-pc.dtb p1020rdb-pc_36b.dtb
 dtb-$(CONFIG_TARGET_P1020RDB_PD) += p1020rdb-pd.dtb
 dtb-$(CONFIG_TARGET_P2020RDB) += p2020rdb-pc.dtb p2020rdb-pc_36b.dtb
-dtb-$(CONFIG_TARGET_P2041RDB) += p2041rdb.dtb
 dtb-$(CONFIG_TARGET_P3041DS) += p3041ds.dtb
 dtb-$(CONFIG_TARGET_P4080DS) += p4080ds.dtb
 dtb-$(CONFIG_TARGET_P5040DS) += p5040ds.dtb

arch/powerpc/dts/p2041.dtsi

@@ -1,138 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
-/*
- * P2041 Silicon/SoC Device Tree Source (pre include)
- *
- * Copyright 2011 - 2015 Freescale Semiconductor Inc.
- * Copyright 2019-2020 NXP
- */
-
-/dts-v1/;
-
-/include/ "e500mc_power_isa.dtsi"
-
-/ {
-	compatible = "fsl,P2041";
-	#address-cells = <2>;
-	#size-cells = <2>;
-	interrupt-parent = <&mpic>;
-
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		cpu0: PowerPC,e500mc@0 {
-			device_type = "cpu";
-			reg = <0>;
-			fsl,portid-mapping = <0x80000000>;
-		};
-		cpu1: PowerPC,e500mc@1 {
-			device_type = "cpu";
-			reg = <1>;
-			fsl,portid-mapping = <0x40000000>;
-		};
-		cpu2: PowerPC,e500mc@2 {
-			device_type = "cpu";
-			reg = <2>;
-			fsl,portid-mapping = <0x20000000>;
-		};
-		cpu3: PowerPC,e500mc@3 {
-			device_type = "cpu";
-			reg = <3>;
-			fsl,portid-mapping = <0x10000000>;
-		};
-	};
-
-	soc: soc@ffe000000 {
-		ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
-		reg = <0xf 0xfe000000 0 0x00001000>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-		device_type = "soc";
-		compatible = "simple-bus";
-
-		mpic: pic@40000 {
-			interrupt-controller;
-			#address-cells = <0>;
-			#interrupt-cells = <4>;
-			reg = <0x40000 0x40000>;
-			compatible = "fsl,mpic", "chrp,open-pic";
-			device_type = "open-pic";
-			clock-frequency = <0x0>;
-		};
-
-		espi0: spi@110000 {
-			compatible = "fsl,mpc8536-espi";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <0x110000 0x1000>;
-			fsl,espi-num-chipselects = <4>;
-			status = "disabled";
-		};
-
-		usb0: usb@210000 {
-			compatible = "fsl-usb2-mph";
-			reg = <0x210000 0x1000>;
-			phy_type = "utmi";
-		};
-
-		usb1: usb@211000 {
-			compatible = "fsl-usb2-mph";
-			reg = <0x210000 0x1000>;
-			phy_type = "utmi";
-		};
-
-		sata: sata@220000 {
-			compatible = "fsl,pq-sata-v2";
-			reg = <0x220000 0x1000>;
-			interrupts = <68 0x2 0 0>;
-			sata-offset = <0x1000>;
-			sata-number = <2>;
-			sata-fpdma = <0>;
-		};
-
-		esdhc: esdhc@114000 {
-			compatible = "fsl,esdhc";
-			reg = <0x114000 0x1000>;
-			clock-frequency = <0>;
-		};
-
-		/include/ "qoriq-i2c-0.dtsi"
-		/include/ "qoriq-i2c-1.dtsi"
-	};
-
-	pcie@ffe200000 {
-		compatible = "fsl,pcie-p2041", "fsl,pcie-fsl-qoriq";
-		reg = <0xf 0xfe200000 0x0 0x1000>;   /* registers */
-		law_trgt_if = <0>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-		device_type = "pci";
-		bus-range = <0x0 0xff>;
-		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000   /* downstream I/O */
-			  0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
-	};
-
-	pcie@ffe201000 {
-		compatible = "fsl,pcie-p2041", "fsl,pcie-fsl-qoriq";
-		reg = <0xf 0xfe201000 0x0 0x1000>;   /* registers */
-		law_trgt_if = <1>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-		device_type = "pci";
-		bus-range = <0x0 0xff>;
-		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000   /* downstream I/O */
-			  0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
-	};
-
-	pcie@ffe202000 {
-		compatible = "fsl,pcie-p2041", "fsl,pcie-fsl-qoriq";
-		reg = <0xf 0xfe202000 0x0 0x1000>;   /* registers */
-		law_trgt_if = <2>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-		device_type = "pci";
-		bus-range = <0x0 0xff>;
-		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000   /* downstream I/O */
-			  0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */
-	};
-};

arch/powerpc/dts/p2041rdb-u-boot.dtsi

@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+&serial0 {
+	bootph-all;
+};
+
+&soc {
+	i2c@118000 {
+		bootph-all;
+	};
+
+	spi@110000 {
+		flash@0 {
+			spi-max-frequency = <10000000>;
+		};
+	};
+};
+
+#include "u-boot.dtsi"

arch/powerpc/dts/p2041rdb.dts

@@ -1,127 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
-/*
- * P2041RDB Device Tree Source
- *
- * Copyright 2011 - 2015 Freescale Semiconductor Inc.
- * Copyright 2019-2020 NXP
- */
-
-/include/ "p2041.dtsi"
-
-/ {
-	model = "fsl,P2041RDB";
-	compatible = "fsl,P2041RDB";
-	#address-cells = <2>;
-	#size-cells = <2>;
-	interrupt-parent = <&mpic>;
-
-	aliases {
-		phy_rgmii_0 = &phy_rgmii_0;
-		phy_rgmii_1 = &phy_rgmii_1;
-		phy_sgmii_2 = &phy_sgmii_2;
-		phy_sgmii_3 = &phy_sgmii_3;
-		phy_sgmii_4 = &phy_sgmii_4;
-		phy_sgmii_1c = &phy_sgmii_1c;
-		phy_sgmii_1d = &phy_sgmii_1d;
-		phy_sgmii_1e = &phy_sgmii_1e;
-		phy_sgmii_1f = &phy_sgmii_1f;
-		phy_xgmii_2 = &phy_xgmii_2;
-		spi0 = &espi0;
-	};
-
-	soc: soc@ffe000000 {
-		ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
-		reg = <0xf 0xfe000000 0 0x00001000>;
-
-		fman@400000 {
-			ethernet@e0000 {
-				phy-handle = <&phy_sgmii_2>;
-				phy-connection-type = "sgmii";
-			};
-
-			mdio@e1120 {
-				phy_rgmii_0: ethernet-phy@0 {
-					reg = <0x0>;
-				};
-
-				phy_rgmii_1: ethernet-phy@1 {
-					reg = <0x1>;
-				};
-
-				phy_sgmii_2: ethernet-phy@2 {
-					reg = <0x2>;
-				};
-
-				phy_sgmii_3: ethernet-phy@3 {
-					reg = <0x3>;
-				};
-
-				phy_sgmii_4: ethernet-phy@4 {
-					reg = <0x4>;
-				};
-
-				phy_sgmii_1c: ethernet-phy@1c {
-					reg = <0x1c>;
-				};
-
-				phy_sgmii_1d: ethernet-phy@1d {
-					reg = <0x1d>;
-				};
-
-				phy_sgmii_1e: ethernet-phy@1e {
-					reg = <0x1e>;
-				};
-
-				phy_sgmii_1f: ethernet-phy@1f {
-					reg = <0x1f>;
-				};
-			};
-
-			ethernet@e2000 {
-				phy-handle = <&phy_sgmii_3>;
-				phy-connection-type = "sgmii";
-			};
-
-			ethernet@e4000 {
-				phy-handle = <&phy_sgmii_4>;
-				phy-connection-type = "sgmii";
-			};
-
-			ethernet@e6000 {
-				phy-handle = <&phy_rgmii_1>;
-				phy-connection-type = "rgmii";
-			};
-
-			ethernet@e8000 {
-				phy-handle = <&phy_rgmii_0>;
-				phy-connection-type = "rgmii";
-			};
-
-			ethernet@f0000 {
-				phy-handle = <&phy_xgmii_2>;
-				phy-connection-type = "xgmii";
-			};
-
-			mdio@f1000 {
-				phy_xgmii_2: ethernet-phy@0 {
-					compatible = "ethernet-phy-ieee802.3-c45";
-					reg = <0x0>;
-				};
-			};
-		};
-	};
-};
-
-&espi0 {
-	status = "okay";
-	flash@0 {
-		compatible = "jedec,spi-nor";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		reg = <0>;
-		/* input clock */
-		spi-max-frequency = <10000000>;
-	};
-};
-
-/include/ "p2041si-post.dtsi"

arch/powerpc/dts/p2041si-post.dtsi

@@ -1,43 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * P2041/P2040 Silicon/SoC Device Tree Source (post include)
- *
- * Copyright 2011 - 2015 Freescale Semiconductor Inc.
- * Copyright 2020 NXP
- *
- */
-
-&soc {
-
-/include/ "qoriq-clockgen1.dtsi"
-/include/ "qoriq-gpio-0.dtsi"
-/include/ "qoriq-sec4.2-0.dtsi"
-
-/* include used FMan blocks */
-/include/ "qoriq-fman-0.dtsi"
-/include/ "qoriq-fman-0-1g-0.dtsi"
-/include/ "qoriq-fman-0-1g-1.dtsi"
-/include/ "qoriq-fman-0-1g-2.dtsi"
-/include/ "qoriq-fman-0-1g-3.dtsi"
-/include/ "qoriq-fman-0-1g-4.dtsi"
-/include/ "qoriq-fman-0-10g-0.dtsi"
-	fman@400000 {
-		enet0: ethernet@e0000 {
-		};
-
-		enet1: ethernet@e2000 {
-		};
-
-		enet2: ethernet@e4000 {
-		};
-
-		enet3: ethernet@e6000 {
-		};
-
-		enet4: ethernet@e8000 {
-		};
-
-		enet5: ethernet@f0000 {
-		};
-	};
-};

board/amd/versal2/board.c

@@ -81,12 +81,13 @@ char *soc_name_decode(void)
 	}
 
 	/*
-	 * --rev. are 6 chars
-	 * max platform name is qemu which is 4 chars
+	 * --rev.-el are 9 chars
+	 * max platform name is emu-mmd which is 7 chars
 	 * platform version number are 1+1
-	 * Plus 1 char for \n
+	 * el is 1 char
+	 * Plus 1 char for NULL byte
 	 */
-	name = calloc(1, strlen(CONFIG_SYS_BOARD) + 13);
+	name = calloc(1, strlen(CONFIG_SYS_BOARD) + 20);
 	if (!name)
 		return NULL;
 

board/apple/mac/mac.env

@@ -0,0 +1,4 @@
+stdin=serial,usbkbd,spikbd
+stdout=vidconsole,serial
+stderr=vidconsole,serial
+boot_targets=nvme usb

board/nxp/common/i2c_mux.h

@@ -10,6 +10,11 @@
 
 #ifdef CONFIG_FSL_USE_PCA9547_MUX
 int select_i2c_ch_pca9547(u8 ch, int bus);
+#else
+static inline int select_i2c_ch_pca9547(u8 ch, int bus)
+{
+	return -EOPNOTSUPP;
+}
 #endif
 
 #endif

board/nxp/ls1012afrdm/eth.c

@@ -7,16 +7,6 @@
 #include <dm.h>
 #include <net.h>
 #include <asm/io.h>
-#include <netdev.h>
-#include <fm_eth.h>
-#include <fsl_mdio.h>
-#include <malloc.h>
-#include <asm/types.h>
-#include <fsl_dtsec.h>
-#include <asm/arch/soc.h>
-#include <asm/arch-fsl-layerscape/config.h>
-#include <asm/arch-fsl-layerscape/immap_lsch2.h>
-#include <asm/arch/fsl_serdes.h>
 #include <linux/delay.h>
 #include <net/pfe_eth/pfe_eth.h>
 #include <dm/platform_data/pfe_dm_eth.h>

board/nxp/ls1012ardb/eth.c

@@ -6,18 +6,6 @@
 
 #include <config.h>
 #include <dm.h>
-#include <net.h>
-#include <asm/io.h>
-#include <netdev.h>
-#include <fm_eth.h>
-#include <fsl_mdio.h>
-#include <malloc.h>
-#include <asm/types.h>
-#include <fsl_dtsec.h>
-#include <asm/arch/soc.h>
-#include <asm/arch-fsl-layerscape/config.h>
-#include <asm/arch-fsl-layerscape/immap_lsch2.h>
-#include <asm/arch/fsl_serdes.h>
 #include <linux/delay.h>
 #include <net/pfe_eth/pfe_eth.h>
 #include <dm/platform_data/pfe_dm_eth.h>

board/nxp/ls1021atsn/ls1021atsn.c

@@ -123,11 +123,6 @@ int dram_init(void)
 	return 0;
 }
 
-int board_eth_init(struct bd_info *bis)
-{
-	return pci_eth_init(bis);
-}
-
 int board_early_init_f(void)
 {
 	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;

board/nxp/ls1021atwr/ls1021atwr.c

@@ -239,11 +239,6 @@ int dram_init(void)
 	return 0;
 }
 
-int board_eth_init(struct bd_info *bis)
-{
-	return pci_eth_init(bis);
-}
-
 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 static void convert_serdes_mux(int type, int need_reset)
 {

board/nxp/ls1028a/ls1028a.c

@@ -103,11 +103,6 @@ int board_init(void)
 	return 0;
 }
 
-int board_eth_init(struct bd_info *bis)
-{
-	return pci_eth_init(bis);
-}
-
 #ifdef CONFIG_MISC_INIT_R
 int misc_init_r(void)
 {

board/nxp/ls1043aqds/Makefile

@@ -5,7 +5,4 @@
 #
 
 obj-y += ddr.o
-ifndef CONFIG_XPL_BUILD
-obj-y += eth.o
-endif
 obj-y += ls1043aqds.o

board/nxp/ls1043aqds/eth.c

@@ -1,501 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2015 Freescale Semiconductor, Inc.
- * Copyright 2019 NXP
- */
-
-#include <config.h>
-#include <log.h>
-#include <net.h>
-#include <asm/io.h>
-#include <netdev.h>
-#include <fdt_support.h>
-#include <fm_eth.h>
-#include <fsl_mdio.h>
-#include <fsl_dtsec.h>
-#include <linux/libfdt.h>
-#include <malloc.h>
-#include <asm/arch/fsl_serdes.h>
-
-#include "../common/qixis.h"
-#include "../common/fman.h"
-#include "ls1043aqds_qixis.h"
-
-#define EMI_NONE	0xFF
-#define EMI1_RGMII1	0
-#define EMI1_RGMII2	1
-#define EMI1_SLOT1	2
-#define EMI1_SLOT2	3
-#define EMI1_SLOT3	4
-#define EMI1_SLOT4	5
-#define EMI2		6
-
-static const char * const mdio_names[] = {
-	"LS1043AQDS_MDIO_RGMII1",
-	"LS1043AQDS_MDIO_RGMII2",
-	"LS1043AQDS_MDIO_SLOT1",
-	"LS1043AQDS_MDIO_SLOT2",
-	"LS1043AQDS_MDIO_SLOT3",
-	"LS1043AQDS_MDIO_SLOT4",
-	"NULL",
-};
-
-/* Map SerDes1 4 lanes to default slot, will be initialized dynamically */
-#ifdef CONFIG_FMAN_ENET
-static int mdio_mux[NUM_FM_PORTS];
-
-static u8 lane_to_slot[] = {1, 2, 3, 4};
-#endif
-
-static const char *ls1043aqds_mdio_name_for_muxval(u8 muxval)
-{
-	return mdio_names[muxval];
-}
-
-struct mii_dev *mii_dev_for_muxval(u8 muxval)
-{
-	struct mii_dev *bus;
-	const char *name;
-
-	if (muxval > EMI2)
-		return NULL;
-
-	name = ls1043aqds_mdio_name_for_muxval(muxval);
-
-	if (!name) {
-		printf("No bus for muxval %x\n", muxval);
-		return NULL;
-	}
-
-	bus = miiphy_get_dev_by_name(name);
-
-	if (!bus) {
-		printf("No bus by name %s\n", name);
-		return NULL;
-	}
-
-	return bus;
-}
-
-#ifdef CONFIG_FMAN_ENET
-struct ls1043aqds_mdio {
-	u8 muxval;
-	struct mii_dev *realbus;
-};
-
-static void ls1043aqds_mux_mdio(u8 muxval)
-{
-	u8 brdcfg4;
-
-	if (muxval < 7) {
-		brdcfg4 = QIXIS_READ(brdcfg[4]);
-		brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
-		brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
-		QIXIS_WRITE(brdcfg[4], brdcfg4);
-	}
-}
-
-static int ls1043aqds_mdio_read(struct mii_dev *bus, int addr, int devad,
-			      int regnum)
-{
-	struct ls1043aqds_mdio *priv = bus->priv;
-
-	ls1043aqds_mux_mdio(priv->muxval);
-
-	return priv->realbus->read(priv->realbus, addr, devad, regnum);
-}
-
-static int ls1043aqds_mdio_write(struct mii_dev *bus, int addr, int devad,
-			       int regnum, u16 value)
-{
-	struct ls1043aqds_mdio *priv = bus->priv;
-
-	ls1043aqds_mux_mdio(priv->muxval);
-
-	return priv->realbus->write(priv->realbus, addr, devad,
-				    regnum, value);
-}
-
-static int ls1043aqds_mdio_reset(struct mii_dev *bus)
-{
-	struct ls1043aqds_mdio *priv = bus->priv;
-
-	return priv->realbus->reset(priv->realbus);
-}
-
-static int ls1043aqds_mdio_init(char *realbusname, u8 muxval)
-{
-	struct ls1043aqds_mdio *pmdio;
-	struct mii_dev *bus = mdio_alloc();
-
-	if (!bus) {
-		printf("Failed to allocate ls1043aqds MDIO bus\n");
-		return -1;
-	}
-
-	pmdio = malloc(sizeof(*pmdio));
-	if (!pmdio) {
-		printf("Failed to allocate ls1043aqds private data\n");
-		free(bus);
-		return -1;
-	}
-
-	bus->read = ls1043aqds_mdio_read;
-	bus->write = ls1043aqds_mdio_write;
-	bus->reset = ls1043aqds_mdio_reset;
-	strcpy(bus->name, ls1043aqds_mdio_name_for_muxval(muxval));
-
-	pmdio->realbus = miiphy_get_dev_by_name(realbusname);
-
-	if (!pmdio->realbus) {
-		printf("No bus with name %s\n", realbusname);
-		free(bus);
-		free(pmdio);
-		return -1;
-	}
-
-	pmdio->muxval = muxval;
-	bus->priv = pmdio;
-	return mdio_register(bus);
-}
-
-void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
-			      enum fm_port port, int offset)
-{
-	struct fixed_link f_link;
-
-	if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
-		if (port == FM1_DTSEC9) {
-			fdt_set_phy_handle(fdt, compat, addr,
-					   "sgmii-riser-s1-p1");
-		} else if (port == FM1_DTSEC2) {
-			fdt_set_phy_handle(fdt, compat, addr,
-					   "sgmii-riser-s2-p1");
-		} else if (port == FM1_DTSEC5) {
-			fdt_set_phy_handle(fdt, compat, addr,
-					   "sgmii-riser-s3-p1");
-		} else if (port == FM1_DTSEC6) {
-			fdt_set_phy_handle(fdt, compat, addr,
-					   "sgmii-riser-s4-p1");
-		}
-	} else if (fm_info_get_enet_if(port) ==
-		   PHY_INTERFACE_MODE_2500BASEX) {
-		/* 2.5G SGMII interface */
-		f_link.phy_id = cpu_to_fdt32(port);
-		f_link.duplex = cpu_to_fdt32(1);
-		f_link.link_speed = cpu_to_fdt32(1000);
-		f_link.pause = 0;
-		f_link.asym_pause = 0;
-		/* no PHY for 2.5G SGMII */
-		fdt_delprop(fdt, offset, "phy-handle");
-		fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
-		fdt_setprop_string(fdt, offset, "phy-connection-type",
-				   "2500base-x");
-	} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) {
-		switch (mdio_mux[port]) {
-		case EMI1_SLOT1:
-			switch (port) {
-			case FM1_DTSEC1:
-				fdt_set_phy_handle(fdt, compat, addr,
-						   "qsgmii-s1-p1");
-				break;
-			case FM1_DTSEC2:
-				fdt_set_phy_handle(fdt, compat, addr,
-						   "qsgmii-s1-p2");
-				break;
-			case FM1_DTSEC5:
-				fdt_set_phy_handle(fdt, compat, addr,
-						   "qsgmii-s1-p3");
-				break;
-			case FM1_DTSEC6:
-				fdt_set_phy_handle(fdt, compat, addr,
-						   "qsgmii-s1-p4");
-				break;
-			default:
-				break;
-			}
-			break;
-		case EMI1_SLOT2:
-			switch (port) {
-			case FM1_DTSEC1:
-				fdt_set_phy_handle(fdt, compat, addr,
-						   "qsgmii-s2-p1");
-				break;
-			case FM1_DTSEC2:
-				fdt_set_phy_handle(fdt, compat, addr,
-						   "qsgmii-s2-p2");
-				break;
-			case FM1_DTSEC5:
-				fdt_set_phy_handle(fdt, compat, addr,
-						   "qsgmii-s2-p3");
-				break;
-			case FM1_DTSEC6:
-				fdt_set_phy_handle(fdt, compat, addr,
-						   "qsgmii-s2-p4");
-				break;
-			default:
-				break;
-			}
-			break;
-		default:
-			break;
-		}
-		fdt_delprop(fdt, offset, "phy-connection-type");
-		fdt_setprop_string(fdt, offset, "phy-connection-type",
-				   "qsgmii");
-	} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII &&
-		   port == FM1_10GEC1) {
-		/* 10GBase-R interface */
-		f_link.phy_id = cpu_to_fdt32(port);
-		f_link.duplex = cpu_to_fdt32(1);
-		f_link.link_speed = cpu_to_fdt32(10000);
-		f_link.pause = 0;
-		f_link.asym_pause = 0;
-		/* no PHY for 10GBase-R */
-		fdt_delprop(fdt, offset, "phy-handle");
-		fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
-		fdt_setprop_string(fdt, offset, "phy-connection-type", "xgmii");
-	}
-}
-
-void fdt_fixup_board_enet(void *fdt)
-{
-	int i;
-	struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
-	u32 srds_s1;
-
-	srds_s1 = in_be32(&gur->rcwsr[4]) &
-			FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
-	srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
-
-	for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) {
-		switch (fm_info_get_enet_if(i)) {
-		case PHY_INTERFACE_MODE_SGMII:
-		case PHY_INTERFACE_MODE_QSGMII:
-			switch (mdio_mux[i]) {
-			case EMI1_SLOT1:
-				fdt_status_okay_by_alias(fdt, "emi1-slot1");
-				break;
-			case EMI1_SLOT2:
-				fdt_status_okay_by_alias(fdt, "emi1-slot2");
-				break;
-			case EMI1_SLOT3:
-				fdt_status_okay_by_alias(fdt, "emi1-slot3");
-				break;
-			case EMI1_SLOT4:
-				fdt_status_okay_by_alias(fdt, "emi1-slot4");
-				break;
-			default:
-				break;
-			}
-			break;
-		case PHY_INTERFACE_MODE_XGMII:
-			break;
-		default:
-			break;
-		}
-	}
-}
-
-int board_eth_init(struct bd_info *bis)
-{
-	int i, idx, lane, slot, interface;
-	struct memac_mdio_info dtsec_mdio_info;
-	struct memac_mdio_info tgec_mdio_info;
-	struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
-	u32 srds_s1;
-
-	srds_s1 = in_be32(&gur->rcwsr[4]) &
-			FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
-	srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
-
-	/* Initialize the mdio_mux array so we can recognize empty elements */
-	for (i = 0; i < NUM_FM_PORTS; i++)
-		mdio_mux[i] = EMI_NONE;
-
-	dtsec_mdio_info.regs =
-		(struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR;
-
-	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
-
-	/* Register the 1G MDIO bus */
-	fm_memac_mdio_init(bis, &dtsec_mdio_info);
-
-	tgec_mdio_info.regs =
-		(struct memac_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR;
-	tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
-
-	/* Register the 10G MDIO bus */
-	fm_memac_mdio_init(bis, &tgec_mdio_info);
-
-	/* Register the muxing front-ends to the MDIO buses */
-	ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
-	ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
-	ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
-	ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
-	ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
-	ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
-	ls1043aqds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
-
-	/* Set the two on-board RGMII PHY address */
-	fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
-	fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
-
-	switch (srds_s1) {
-	case 0x2555:
-		/* 2.5G SGMII on lane A, MAC 9 */
-		fm_info_set_phy_address(FM1_DTSEC9, 9);
-		break;
-	case 0x4555:
-	case 0x4558:
-		/* QSGMII on lane A, MAC 1/2/5/6 */
-		fm_info_set_phy_address(FM1_DTSEC1,
-					QSGMII_CARD_PORT1_PHY_ADDR_S1);
-		fm_info_set_phy_address(FM1_DTSEC2,
-					QSGMII_CARD_PORT2_PHY_ADDR_S1);
-		fm_info_set_phy_address(FM1_DTSEC5,
-					QSGMII_CARD_PORT3_PHY_ADDR_S1);
-		fm_info_set_phy_address(FM1_DTSEC6,
-					QSGMII_CARD_PORT4_PHY_ADDR_S1);
-		break;
-	case 0x1355:
-		/* SGMII on lane B, MAC 2*/
-		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
-		break;
-	case 0x2355:
-		/* 2.5G SGMII on lane A, MAC 9 */
-		fm_info_set_phy_address(FM1_DTSEC9, 9);
-		/* SGMII on lane B, MAC 2*/
-		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
-		break;
-	case 0x3335:
-		/* SGMII on lane C, MAC 5 */
-		fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
-	case 0x3355:
-	case 0x3358:
-		/* SGMII on lane B, MAC 2 */
-		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
-	case 0x3555:
-	case 0x3558:
-		/* SGMII on lane A, MAC 9 */
-		fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
-		break;
-	case 0x1455:
-		/* QSGMII on lane B, MAC 1/2/5/6 */
-		fm_info_set_phy_address(FM1_DTSEC1,
-					QSGMII_CARD_PORT1_PHY_ADDR_S2);
-		fm_info_set_phy_address(FM1_DTSEC2,
-					QSGMII_CARD_PORT2_PHY_ADDR_S2);
-		fm_info_set_phy_address(FM1_DTSEC5,
-					QSGMII_CARD_PORT3_PHY_ADDR_S2);
-		fm_info_set_phy_address(FM1_DTSEC6,
-					QSGMII_CARD_PORT4_PHY_ADDR_S2);
-		break;
-	case 0x2455:
-		/* 2.5G SGMII on lane A, MAC 9 */
-		fm_info_set_phy_address(FM1_DTSEC9, 9);
-		/* QSGMII on lane B, MAC 1/2/5/6 */
-		fm_info_set_phy_address(FM1_DTSEC1,
-					QSGMII_CARD_PORT1_PHY_ADDR_S2);
-		fm_info_set_phy_address(FM1_DTSEC2,
-					QSGMII_CARD_PORT2_PHY_ADDR_S2);
-		fm_info_set_phy_address(FM1_DTSEC5,
-					QSGMII_CARD_PORT3_PHY_ADDR_S2);
-		fm_info_set_phy_address(FM1_DTSEC6,
-					QSGMII_CARD_PORT4_PHY_ADDR_S2);
-		break;
-	case 0x2255:
-		/* 2.5G SGMII on lane A, MAC 9 */
-		fm_info_set_phy_address(FM1_DTSEC9, 9);
-		/* 2.5G SGMII on lane B, MAC 2 */
-		fm_info_set_phy_address(FM1_DTSEC2, 2);
-		break;
-	case 0x3333:
-		/* SGMII on lane A/B/C/D, MAC 9/2/5/6 */
-		fm_info_set_phy_address(FM1_DTSEC9,
-					SGMII_CARD_PORT1_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC2,
-					SGMII_CARD_PORT1_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC5,
-					SGMII_CARD_PORT1_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC6,
-					SGMII_CARD_PORT1_PHY_ADDR);
-		break;
-	default:
-		printf("Invalid SerDes protocol 0x%x for LS1043AQDS\n",
-		       srds_s1);
-		break;
-	}
-
-	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) {
-		idx = i - FM1_DTSEC1;
-		interface = fm_info_get_enet_if(i);
-		switch (interface) {
-		case PHY_INTERFACE_MODE_SGMII:
-		case PHY_INTERFACE_MODE_2500BASEX:
-		case PHY_INTERFACE_MODE_QSGMII:
-			if (interface == PHY_INTERFACE_MODE_SGMII) {
-				lane = serdes_get_first_lane(FSL_SRDS_1,
-						SGMII_FM1_DTSEC1 + idx);
-			} else if (interface == PHY_INTERFACE_MODE_2500BASEX) {
-				lane = serdes_get_first_lane(FSL_SRDS_1,
-						SGMII_2500_FM1_DTSEC1 + idx);
-			} else {
-				lane = serdes_get_first_lane(FSL_SRDS_1,
-						QSGMII_FM1_A);
-			}
-
-			if (lane < 0)
-				break;
-
-			slot = lane_to_slot[lane];
-			debug("FM1@DTSEC%u expects SGMII in slot %u\n",
-			      idx + 1, slot);
-			if (QIXIS_READ(present2) & (1 << (slot - 1)))
-				fm_disable_port(i);
-
-			switch (slot) {
-			case 1:
-				mdio_mux[i] = EMI1_SLOT1;
-				fm_info_set_mdio(i, mii_dev_for_muxval(
-						 mdio_mux[i]));
-				break;
-			case 2:
-				mdio_mux[i] = EMI1_SLOT2;
-				fm_info_set_mdio(i, mii_dev_for_muxval(
-						 mdio_mux[i]));
-				break;
-			case 3:
-				mdio_mux[i] = EMI1_SLOT3;
-				fm_info_set_mdio(i, mii_dev_for_muxval(
-						 mdio_mux[i]));
-				break;
-			case 4:
-				mdio_mux[i] = EMI1_SLOT4;
-				fm_info_set_mdio(i, mii_dev_for_muxval(
-						 mdio_mux[i]));
-				break;
-			default:
-				break;
-			}
-			break;
-		case PHY_INTERFACE_MODE_RGMII:
-		case PHY_INTERFACE_MODE_RGMII_TXID:
-		case PHY_INTERFACE_MODE_RGMII_RXID:
-		case PHY_INTERFACE_MODE_RGMII_ID:
-			if (i == FM1_DTSEC3)
-				mdio_mux[i] = EMI1_RGMII1;
-			else if (i == FM1_DTSEC4)
-				mdio_mux[i] = EMI1_RGMII2;
-			fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
-			break;
-		default:
-			break;
-		}
-	}
-
-	cpu_eth_init(bis);
-
-	return pci_eth_init(bis);
-}
-#endif /* CONFIG_FMAN_ENET */

board/nxp/ls1043aqds/ls1043aqds.c

@@ -550,10 +550,6 @@ int ft_board_setup(void *blob, struct bd_info *bd)
 	fdt_fixup_memory_banks(blob, base, size, 2);
 	ft_cpu_setup(blob, bd);
 
-#ifdef CONFIG_FMAN_ENET
-	fdt_fixup_board_enet(blob);
-#endif
-
 	fdt_fixup_icid(blob);
 
 	reg = QIXIS_READ(brdcfg[0]);

board/nxp/ls1043ardb/Makefile

@@ -5,6 +5,5 @@
 obj-y += ddr.o
 obj-y += ls1043ardb.o
 ifndef CONFIG_XPL_BUILD
-obj-$(CONFIG_NET_LEGACY) += eth.o
 obj-y += cpld.o
 endif

board/nxp/ls1043ardb/eth.c

@@ -1,77 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2015 Freescale Semiconductor, Inc.
- */
-#include <config.h>
-#include <net.h>
-#include <asm/io.h>
-#include <netdev.h>
-#include <fm_eth.h>
-#include <fsl_dtsec.h>
-#include <fsl_mdio.h>
-#include <malloc.h>
-
-#include "../common/fman.h"
-
-int board_eth_init(struct bd_info *bis)
-{
-#ifdef CONFIG_FMAN_ENET
-	int i;
-	struct memac_mdio_info dtsec_mdio_info;
-	struct memac_mdio_info tgec_mdio_info;
-	struct mii_dev *dev;
-	u32 srds_s1;
-	struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
-
-	srds_s1 = in_be32(&gur->rcwsr[4]) &
-			FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
-	srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
-
-	dtsec_mdio_info.regs =
-		(struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR;
-
-	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
-
-	/* Register the 1G MDIO bus */
-	fm_memac_mdio_init(bis, &dtsec_mdio_info);
-
-	tgec_mdio_info.regs =
-		(struct memac_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR;
-	tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
-
-	/* Register the 10G MDIO bus */
-	fm_memac_mdio_init(bis, &tgec_mdio_info);
-
-	/* Set the two on-board RGMII PHY address */
-	fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
-	fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
-
-	/* QSGMII on lane B, MAC 1/2/5/6 */
-	fm_info_set_phy_address(FM1_DTSEC1, QSGMII_PORT1_PHY_ADDR);
-	fm_info_set_phy_address(FM1_DTSEC2, QSGMII_PORT2_PHY_ADDR);
-	fm_info_set_phy_address(FM1_DTSEC5, QSGMII_PORT3_PHY_ADDR);
-	fm_info_set_phy_address(FM1_DTSEC6, QSGMII_PORT4_PHY_ADDR);
-
-	switch (srds_s1) {
-	case 0x1455:
-		break;
-	default:
-		printf("Invalid SerDes protocol 0x%x for LS1043ARDB\n",
-		       srds_s1);
-		break;
-	}
-
-	dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
-	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++)
-		fm_info_set_mdio(i, dev);
-
-	/* 10GBase-R on lane A, MAC 9 */
-	fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
-	dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
-	fm_info_set_mdio(FM1_10GEC1, dev);
-
-	cpu_eth_init(bis);
-#endif
-
-	return pci_eth_init(bis);
-}

board/nxp/ls1046afrwy/eth.c

@@ -4,64 +4,7 @@
  */
 #include <config.h>
 #include <fdt_support.h>
-#include <net.h>
 #include <asm/io.h>
-#include <netdev.h>
-#include <fm_eth.h>
-#include <fsl_dtsec.h>
-#include <fsl_mdio.h>
-#include <malloc.h>
-
-#include "../common/fman.h"
-
-int board_eth_init(struct bd_info *bis)
-{
-#ifdef CONFIG_FMAN_ENET
-	struct memac_mdio_info dtsec_mdio_info;
-	struct mii_dev *dev;
-	u32 srds_s1;
-	struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
-
-	srds_s1 = in_be32(&gur->rcwsr[4]) &
-			FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
-	srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
-
-	dtsec_mdio_info.regs =
-		(struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR;
-
-	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
-
-	/* Register the 1G MDIO bus */
-	fm_memac_mdio_init(bis, &dtsec_mdio_info);
-
-	/* QSGMII on lane B, MAC 6/5/10/1 */
-	fm_info_set_phy_address(FM1_DTSEC6, QSGMII_PORT1_PHY_ADDR);
-	fm_info_set_phy_address(FM1_DTSEC5, QSGMII_PORT2_PHY_ADDR);
-	fm_info_set_phy_address(FM1_DTSEC10, QSGMII_PORT3_PHY_ADDR);
-	fm_info_set_phy_address(FM1_DTSEC1, QSGMII_PORT4_PHY_ADDR);
-
-	switch (srds_s1) {
-	case 0x3040:
-		break;
-	default:
-		printf("Invalid SerDes protocol 0x%x for LS1046AFRWY\n",
-		       srds_s1);
-		break;
-	}
-
-	dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
-	fm_info_set_mdio(FM1_DTSEC6, dev);
-	fm_info_set_mdio(FM1_DTSEC5, dev);
-	fm_info_set_mdio(FM1_DTSEC10, dev);
-	fm_info_set_mdio(FM1_DTSEC1, dev);
-
-	fm_disable_port(FM1_DTSEC9);
-
-	cpu_eth_init(bis);
-#endif
-
-	return pci_eth_init(bis);
-}
 
 #ifdef CONFIG_FMAN_ENET
 int fdt_update_ethernet_dt(void *blob)

board/nxp/ls1046aqds/Makefile

@@ -5,7 +5,4 @@
 #
 
 obj-y += ddr.o
-ifndef CONFIG_XPL_BUILD
-obj-y += eth.o
-endif
 obj-y += ls1046aqds.o

board/nxp/ls1046aqds/eth.c

@@ -1,431 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2016 Freescale Semiconductor, Inc.
- * Copyright 2018-2020 NXP
- */
-
-#include <config.h>
-#include <log.h>
-#include <net.h>
-#include <asm/io.h>
-#include <netdev.h>
-#include <fdt_support.h>
-#include <fm_eth.h>
-#include <fsl_mdio.h>
-#include <fsl_dtsec.h>
-#include <malloc.h>
-#include <asm/arch/fsl_serdes.h>
-
-#include "../common/qixis.h"
-#include "../common/fman.h"
-#include "ls1046aqds_qixis.h"
-
-#define EMI_NONE	0xFF
-#define EMI1_RGMII1	0
-#define EMI1_RGMII2	1
-#define EMI1_SLOT1	2
-#define EMI1_SLOT2	3
-#define EMI1_SLOT4	4
-
-static const char * const mdio_names[] = {
-	"LS1046AQDS_MDIO_RGMII1",
-	"LS1046AQDS_MDIO_RGMII2",
-	"LS1046AQDS_MDIO_SLOT1",
-	"LS1046AQDS_MDIO_SLOT2",
-	"LS1046AQDS_MDIO_SLOT4",
-	"NULL",
-};
-
-/* Map SerDes 1 & 2 lanes to default slot. */
-#ifdef CONFIG_FMAN_ENET
-static int mdio_mux[NUM_FM_PORTS];
-
-static u8 lane_to_slot[] = {1, 1, 1, 1, 0, 4, 0 , 0};
-#endif
-
-static const char *ls1046aqds_mdio_name_for_muxval(u8 muxval)
-{
-	return mdio_names[muxval];
-}
-
-struct mii_dev *mii_dev_for_muxval(u8 muxval)
-{
-	struct mii_dev *bus;
-	const char *name;
-
-	if (muxval > EMI1_SLOT4)
-		return NULL;
-
-	name = ls1046aqds_mdio_name_for_muxval(muxval);
-
-	if (!name) {
-		printf("No bus for muxval %x\n", muxval);
-		return NULL;
-	}
-
-	bus = miiphy_get_dev_by_name(name);
-
-	if (!bus) {
-		printf("No bus by name %s\n", name);
-		return NULL;
-	}
-
-	return bus;
-}
-
-#ifdef CONFIG_FMAN_ENET
-struct ls1046aqds_mdio {
-	u8 muxval;
-	struct mii_dev *realbus;
-};
-
-static void ls1046aqds_mux_mdio(u8 muxval)
-{
-	u8 brdcfg4;
-
-	if (muxval < 7) {
-		brdcfg4 = QIXIS_READ(brdcfg[4]);
-		brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
-		brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
-		QIXIS_WRITE(brdcfg[4], brdcfg4);
-	}
-}
-
-static int ls1046aqds_mdio_read(struct mii_dev *bus, int addr, int devad,
-			      int regnum)
-{
-	struct ls1046aqds_mdio *priv = bus->priv;
-
-	ls1046aqds_mux_mdio(priv->muxval);
-
-	return priv->realbus->read(priv->realbus, addr, devad, regnum);
-}
-
-static int ls1046aqds_mdio_write(struct mii_dev *bus, int addr, int devad,
-			       int regnum, u16 value)
-{
-	struct ls1046aqds_mdio *priv = bus->priv;
-
-	ls1046aqds_mux_mdio(priv->muxval);
-
-	return priv->realbus->write(priv->realbus, addr, devad,
-				    regnum, value);
-}
-
-static int ls1046aqds_mdio_reset(struct mii_dev *bus)
-{
-	struct ls1046aqds_mdio *priv = bus->priv;
-
-	return priv->realbus->reset(priv->realbus);
-}
-
-static int ls1046aqds_mdio_init(char *realbusname, u8 muxval)
-{
-	struct ls1046aqds_mdio *pmdio;
-	struct mii_dev *bus = mdio_alloc();
-
-	if (!bus) {
-		printf("Failed to allocate ls1046aqds MDIO bus\n");
-		return -1;
-	}
-
-	pmdio = malloc(sizeof(*pmdio));
-	if (!pmdio) {
-		printf("Failed to allocate ls1046aqds private data\n");
-		free(bus);
-		return -1;
-	}
-
-	bus->read = ls1046aqds_mdio_read;
-	bus->write = ls1046aqds_mdio_write;
-	bus->reset = ls1046aqds_mdio_reset;
-	sprintf(bus->name, ls1046aqds_mdio_name_for_muxval(muxval));
-
-	pmdio->realbus = miiphy_get_dev_by_name(realbusname);
-
-	if (!pmdio->realbus) {
-		printf("No bus with name %s\n", realbusname);
-		free(bus);
-		free(pmdio);
-		return -1;
-	}
-
-	pmdio->muxval = muxval;
-	bus->priv = pmdio;
-	return mdio_register(bus);
-}
-
-void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
-			      enum fm_port port, int offset)
-{
-	struct fixed_link f_link;
-	const char *phyconn;
-
-	if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
-		switch (port) {
-		case FM1_DTSEC9:
-			fdt_set_phy_handle(fdt, compat, addr, "sgmii-s1-p1");
-			break;
-		case FM1_DTSEC10:
-			fdt_set_phy_handle(fdt, compat, addr, "sgmii-s1-p2");
-			break;
-		case FM1_DTSEC5:
-			fdt_set_phy_handle(fdt, compat, addr, "sgmii-s1-p3");
-			break;
-		case FM1_DTSEC6:
-			fdt_set_phy_handle(fdt, compat, addr, "sgmii-s1-p4");
-			break;
-		case FM1_DTSEC2:
-			fdt_set_phy_handle(fdt, compat, addr, "sgmii-s4-p1");
-			break;
-		default:
-			break;
-		}
-	} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_2500BASEX) {
-		/* 2.5G SGMII interface */
-		f_link.phy_id = cpu_to_fdt32(port);
-		f_link.duplex = cpu_to_fdt32(1);
-		f_link.link_speed = cpu_to_fdt32(1000);
-		f_link.pause = 0;
-		f_link.asym_pause = 0;
-		/* no PHY for 2.5G SGMII on QDS */
-		fdt_delprop(fdt, offset, "phy-handle");
-		fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
-		fdt_setprop_string(fdt, offset, "phy-connection-type",
-				   "2500base-x");
-	} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) {
-		switch (port) {
-		case FM1_DTSEC1:
-			fdt_set_phy_handle(fdt, compat, addr, "qsgmii-s2-p4");
-			break;
-		case FM1_DTSEC5:
-			fdt_set_phy_handle(fdt, compat, addr, "qsgmii-s2-p2");
-			break;
-		case FM1_DTSEC6:
-			fdt_set_phy_handle(fdt, compat, addr, "qsgmii-s2-p1");
-			break;
-		case FM1_DTSEC10:
-			fdt_set_phy_handle(fdt, compat, addr, "qsgmii-s2-p3");
-			break;
-		default:
-			break;
-		}
-		fdt_delprop(fdt, offset, "phy-connection-type");
-		fdt_setprop_string(fdt, offset, "phy-connection-type",
-				   "qsgmii");
-	} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII &&
-		   (port == FM1_10GEC1 || port == FM1_10GEC2)) {
-		phyconn = fdt_getprop(fdt, offset, "phy-connection-type", NULL);
-		if (is_backplane_mode(phyconn)) {
-			/* Backplane KR mode: skip fixups */
-			printf("Interface %d in backplane KR mode\n", port);
-		} else {
-			/* 10GBase-R interface */
-			f_link.phy_id = cpu_to_fdt32(port);
-			f_link.duplex = cpu_to_fdt32(1);
-			f_link.link_speed = cpu_to_fdt32(10000);
-			f_link.pause = 0;
-			f_link.asym_pause = 0;
-			/* no PHY for 10GBase-R */
-			fdt_delprop(fdt, offset, "phy-handle");
-			fdt_setprop(fdt, offset, "fixed-link", &f_link,
-				    sizeof(f_link));
-			fdt_setprop_string(fdt, offset, "phy-connection-type",
-					   "xgmii");
-		}
-	}
-}
-
-void fdt_fixup_board_enet(void *fdt)
-{
-	int i;
-
-	for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) {
-		switch (fm_info_get_enet_if(i)) {
-		case PHY_INTERFACE_MODE_SGMII:
-		case PHY_INTERFACE_MODE_QSGMII:
-			switch (mdio_mux[i]) {
-			case EMI1_SLOT1:
-				fdt_status_okay_by_alias(fdt, "emi1-slot1");
-				break;
-			case EMI1_SLOT2:
-				fdt_status_okay_by_alias(fdt, "emi1-slot2");
-				break;
-			case EMI1_SLOT4:
-				fdt_status_okay_by_alias(fdt, "emi1-slot4");
-				break;
-			default:
-				break;
-			}
-			break;
-		default:
-			break;
-		}
-	}
-}
-
-int board_eth_init(struct bd_info *bis)
-{
-	int i, idx, lane, slot, interface;
-	struct memac_mdio_info dtsec_mdio_info;
-	struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
-	u32 srds_s1, srds_s2;
-	u8 brdcfg12;
-
-	srds_s1 = in_be32(&gur->rcwsr[4]) &
-			FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
-	srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
-
-	srds_s2 = in_be32(&gur->rcwsr[4]) &
-			FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK;
-	srds_s2 >>= FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT;
-
-	/* Initialize the mdio_mux array so we can recognize empty elements */
-	for (i = 0; i < NUM_FM_PORTS; i++)
-		mdio_mux[i] = EMI_NONE;
-
-	dtsec_mdio_info.regs =
-		(struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR;
-
-	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
-
-	/* Register the 1G MDIO bus */
-	fm_memac_mdio_init(bis, &dtsec_mdio_info);
-
-	/* Register the muxing front-ends to the MDIO buses */
-	ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
-	ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
-	ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
-	ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
-	ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
-
-	/* Set the two on-board RGMII PHY address */
-	fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
-	fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
-
-	switch (srds_s1) {
-	case 0x3333:
-		/* SGMII on slot 1, MAC 9 */
-		fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
-	case 0x1333:
-	case 0x2333:
-		/* SGMII on slot 1, MAC 10 */
-		fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
-	case 0x1133:
-	case 0x2233:
-		/* SGMII on slot 1, MAC 5/6 */
-		fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
-		break;
-	case 0x1040:
-	case 0x2040:
-		/* QSGMII on lane B, MAC 6/5/10/1 */
-		fm_info_set_phy_address(FM1_DTSEC6,
-					QSGMII_CARD_PORT1_PHY_ADDR_S2);
-		fm_info_set_phy_address(FM1_DTSEC5,
-					QSGMII_CARD_PORT2_PHY_ADDR_S2);
-		fm_info_set_phy_address(FM1_DTSEC10,
-					QSGMII_CARD_PORT3_PHY_ADDR_S2);
-		fm_info_set_phy_address(FM1_DTSEC1,
-					QSGMII_CARD_PORT4_PHY_ADDR_S2);
-		break;
-	case 0x3363:
-		/* SGMII on slot 1, MAC 9/10 */
-		fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
-	case 0x1163:
-	case 0x2263:
-	case 0x2223:
-		/* SGMII on slot 1, MAC 6 */
-		fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
-		break;
-	default:
-		printf("Invalid SerDes protocol 0x%x for LS1046AQDS\n",
-		       srds_s1);
-		break;
-	}
-
-	if (srds_s2 == 0x5a59 || srds_s2 == 0x5a06)
-		/* SGMII on slot 4, MAC 2 */
-		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
-
-	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) {
-		idx = i - FM1_DTSEC1;
-		interface = fm_info_get_enet_if(i);
-		switch (interface) {
-		case PHY_INTERFACE_MODE_SGMII:
-		case PHY_INTERFACE_MODE_QSGMII:
-			if (interface == PHY_INTERFACE_MODE_SGMII) {
-				if (i == FM1_DTSEC5) {
-					/* route lane 2 to slot1 so to have
-					 * one sgmii riser card supports
-					 * MAC5 and MAC6.
-					 */
-					brdcfg12 = QIXIS_READ(brdcfg[12]);
-					QIXIS_WRITE(brdcfg[12],
-						    brdcfg12 | 0x80);
-				}
-				lane = serdes_get_first_lane(FSL_SRDS_1,
-						SGMII_FM1_DTSEC1 + idx);
-			} else {
-				/* clear the bit 7 to route lane B on slot2. */
-				brdcfg12 = QIXIS_READ(brdcfg[12]);
-				QIXIS_WRITE(brdcfg[12], brdcfg12 & 0x7f);
-
-				lane = serdes_get_first_lane(FSL_SRDS_1,
-						QSGMII_FM1_A);
-				lane_to_slot[lane] = 2;
-			}
-
-			if (i == FM1_DTSEC2)
-				lane = 5;
-
-			if (lane < 0)
-				break;
-
-			slot = lane_to_slot[lane];
-			debug("FM1@DTSEC%u expects SGMII in slot %u\n",
-			      idx + 1, slot);
-			if (QIXIS_READ(present2) & (1 << (slot - 1)))
-				fm_disable_port(i);
-
-			switch (slot) {
-			case 1:
-				mdio_mux[i] = EMI1_SLOT1;
-				fm_info_set_mdio(i, mii_dev_for_muxval(
-						 mdio_mux[i]));
-				break;
-			case 2:
-				mdio_mux[i] = EMI1_SLOT2;
-				fm_info_set_mdio(i, mii_dev_for_muxval(
-						 mdio_mux[i]));
-				break;
-			case 4:
-				mdio_mux[i] = EMI1_SLOT4;
-				fm_info_set_mdio(i, mii_dev_for_muxval(
-						 mdio_mux[i]));
-				break;
-			default:
-				break;
-			}
-			break;
-		case PHY_INTERFACE_MODE_RGMII:
-		case PHY_INTERFACE_MODE_RGMII_TXID:
-		case PHY_INTERFACE_MODE_RGMII_RXID:
-		case PHY_INTERFACE_MODE_RGMII_ID:
-			if (i == FM1_DTSEC3)
-				mdio_mux[i] = EMI1_RGMII1;
-			else if (i == FM1_DTSEC4)
-				mdio_mux[i] = EMI1_RGMII2;
-			fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
-			break;
-		default:
-			break;
-		}
-	}
-
-	cpu_eth_init(bis);
-
-	return pci_eth_init(bis);
-}
-#endif /* CONFIG_FMAN_ENET */

board/nxp/ls1046aqds/ls1046aqds.c

@@ -434,10 +434,6 @@ int ft_board_setup(void *blob, struct bd_info *bd)
 	fdt_fixup_memory_banks(blob, base, size, 2);
 	ft_cpu_setup(blob, bd);
 
-#ifdef CONFIG_FMAN_ENET
-	fdt_fixup_board_enet(blob);
-#endif
-
 	fdt_fixup_icid(blob);
 
 	reg = QIXIS_READ(brdcfg[0]);

board/nxp/ls1046ardb/eth.c

@@ -4,78 +4,7 @@
  */
 #include <config.h>
 #include <fdt_support.h>
-#include <net.h>
 #include <asm/io.h>
-#include <netdev.h>
-#include <fm_eth.h>
-#include <fsl_dtsec.h>
-#include <fsl_mdio.h>
-#include <malloc.h>
-
-#include "../common/fman.h"
-
-int board_eth_init(struct bd_info *bis)
-{
-#ifdef CONFIG_FMAN_ENET
-	int i;
-	struct memac_mdio_info dtsec_mdio_info;
-	struct memac_mdio_info tgec_mdio_info;
-	struct mii_dev *dev;
-	u32 srds_s1;
-	struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
-
-	srds_s1 = in_be32(&gur->rcwsr[4]) &
-			FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
-	srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
-
-	dtsec_mdio_info.regs =
-		(struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR;
-
-	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
-
-	/* Register the 1G MDIO bus */
-	fm_memac_mdio_init(bis, &dtsec_mdio_info);
-
-	tgec_mdio_info.regs =
-		(struct memac_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR;
-	tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
-
-	/* Register the 10G MDIO bus */
-	fm_memac_mdio_init(bis, &tgec_mdio_info);
-
-	/* Set the two on-board RGMII PHY address */
-	fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
-	fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
-
-	/* Set the two on-board SGMII PHY address */
-	fm_info_set_phy_address(FM1_DTSEC5, SGMII_PHY1_ADDR);
-	fm_info_set_phy_address(FM1_DTSEC6, SGMII_PHY2_ADDR);
-
-	/* Set the on-board AQ PHY address */
-	fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
-
-	switch (srds_s1) {
-	case 0x1133:
-		break;
-	default:
-		printf("Invalid SerDes protocol 0x%x for LS1046ARDB\n",
-		       srds_s1);
-		break;
-	}
-
-	dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
-	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++)
-		fm_info_set_mdio(i, dev);
-
-	/* 10GBase-R on lane A, MAC 9 */
-	dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
-	fm_info_set_mdio(FM1_10GEC1, dev);
-
-	cpu_eth_init(bis);
-#endif
-
-	return pci_eth_init(bis);
-}
 
 #ifdef CONFIG_FMAN_ENET
 int fdt_update_ethernet_dt(void *blob)

board/nxp/ls1088a/ls1088a.c

@@ -974,7 +974,7 @@ int ft_board_setup(void *blob, struct bd_info *bd)
 #endif
 
 	if (mc_memory_base != 0) {
-		for (i = 0; i <= total_memory_banks; i++) {
+		for (i = 0; i < total_memory_banks; i++) {
 			if (base[i] == 0 && size[i] == 0) {
 				base[i] = mc_memory_base;
 				size[i] = mc_memory_size;

board/nxp/ls2080ardb/eth_ls2080rdb.c

@@ -9,25 +9,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-int board_eth_init(struct bd_info *bis)
-{
-
-#if defined(CONFIG_PHY_AQUANTIA) && !defined(CONFIG_XPL_BUILD)
-	/*
-	 * Export functions to be used by AQ firmware
-	 * upload application
-	 */
-	gd->jt->strcpy = strcpy;
-	gd->jt->mdelay = mdelay;
-	gd->jt->mdio_get_current_dev = mdio_get_current_dev;
-	gd->jt->phy_find_by_mask = phy_find_by_mask;
-	gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
-	gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
-#endif
-
-	return 0;
-}
-
 #if defined(CONFIG_RESET_PHY_R)
 void reset_phy(void)
 {

board/nxp/ls2080ardb/ls2080ardb.c

@@ -503,7 +503,7 @@ int ft_board_setup(void *blob, struct bd_info *bd)
 #endif
 
 	if (mc_memory_base != 0) {
-		for (i = 0; i <= total_memory_banks; i++) {
+		for (i = 0; i < total_memory_banks; i++) {
 			if (base[i] == 0 && size[i] == 0) {
 				base[i] = mc_memory_base;
 				size[i] = mc_memory_size;

board/nxp/lx2160a/eth_lx2160aqds.c

@@ -11,24 +11,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-int board_eth_init(struct bd_info *bis)
-{
-#ifdef CONFIG_PHY_AQUANTIA
-	/*
-	 * Export functions to be used by AQ firmware
-	 * upload application
-	 */
-	gd->jt->strcpy = strcpy;
-	gd->jt->mdelay = mdelay;
-	gd->jt->mdio_get_current_dev = mdio_get_current_dev;
-	gd->jt->phy_find_by_mask = phy_find_by_mask;
-	gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
-	gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
-#endif
-
-	return 0;
-}
-
 #if defined(CONFIG_RESET_PHY_R)
 void reset_phy(void)
 {

board/nxp/lx2160a/eth_lx2160ardb.c

@@ -11,23 +11,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-int board_eth_init(struct bd_info *bis)
-{
-#ifdef CONFIG_PHY_AQUANTIA
-	/*
-	 * Export functions to be used by AQ firmware
-	 * upload application
-	 */
-	gd->jt->strcpy = strcpy;
-	gd->jt->mdelay = mdelay;
-	gd->jt->mdio_get_current_dev = mdio_get_current_dev;
-	gd->jt->phy_find_by_mask = phy_find_by_mask;
-	gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
-	gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
-#endif
-	return pci_eth_init(bis);
-}
-
 #if defined(CONFIG_RESET_PHY_R)
 void reset_phy(void)
 {

board/nxp/lx2160a/eth_lx2162aqds.c

@@ -11,24 +11,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-int board_eth_init(struct bd_info *bis)
-{
-#ifdef CONFIG_PHY_AQUANTIA
-	/*
-	 * Export functions to be used by AQ firmware
-	 * upload application
-	 */
-	gd->jt->strcpy = strcpy;
-	gd->jt->mdelay = mdelay;
-	gd->jt->mdio_get_current_dev = mdio_get_current_dev;
-	gd->jt->phy_find_by_mask = phy_find_by_mask;
-	gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
-	gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
-#endif
-
-	return 0;
-}
-
 #if defined(CONFIG_RESET_PHY_R)
 void reset_phy(void)
 {

board/nxp/lx2160a/lx2160a.c

@@ -242,13 +242,17 @@ int init_func_vid(void)
 
 	return 0;
 }
-#endif
 EVENT_SPY_SIMPLE(EVT_MISC_INIT_F, init_func_vid);
+#endif
 
 int checkboard(void)
 {
-	enum boot_src src = get_boot_src();
 	char buf[64];
+
+	cpu_name(buf);
+
+#if IS_ENABLED(CONFIG_FSL_QIXIS)
+	enum boot_src src = get_boot_src();
 	u8 sw;
 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
 	int clock;
@@ -258,7 +262,6 @@ int checkboard(void)
 					   "100 separate SSCG"};
 #endif
 
-	cpu_name(buf);
 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
 	printf("Board: %s-QDS, ", buf);
 #else
@@ -325,7 +328,10 @@ int checkboard(void)
 	clock = sw >> 4;
 	printf("Clock1 = %sMHz Clock2 = %sMHz\n", freq[clock], freq[clock]);
 #endif
-#endif
+#endif /* LX2160ARDB-inside-QIXIS switch */
+#else /* !CONFIG_FSL_QIXIS */
+	printf("Board: %s\n", buf);
+#endif /* CONFIG_FSL_QIXIS */
 	return 0;
 }
 
@@ -554,7 +560,7 @@ int board_init(void)
 	out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR107_IRQ_MASK);
 #endif
 
-#if !defined(CONFIG_SYS_EARLY_PCI_INIT)
+#if defined(CONFIG_PCI) && !defined(CONFIG_SYS_EARLY_PCI_INIT)
 	pci_init();
 #endif
 	return 0;
@@ -788,7 +794,9 @@ int ft_board_setup(void *blob, struct bd_info *bd)
 
 	ft_cpu_setup(blob, bd);
 
+#if IS_ENABLED(CONFIG_FSL_MC_ENET)
 	fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
+#endif
 
 	if (mc_memory_base != 0)
 		mc_memory_bank++;
@@ -818,7 +826,7 @@ int ft_board_setup(void *blob, struct bd_info *bd)
 #endif
 
 	if (mc_memory_base != 0) {
-		for (i = 0; i <= total_memory_banks; i++) {
+		for (i = 0; i < total_memory_banks; i++) {
 			if (base[i] == 0 && size[i] == 0) {
 				base[i] = mc_memory_base;
 				size[i] = mc_memory_size;

board/nxp/m5253demo/m5253demo.c

@@ -133,10 +133,3 @@ void ide_set_reset(int idereset)
 	}
 }
 #endif				/* CONFIG_IDE */
-
-#ifdef CONFIG_DRIVER_DM9000
-int board_eth_init(struct bd_info *bis)
-{
-	return dm9000_initialize(bis);
-}
-#endif

board/nxp/m53017evb/README

@@ -90,10 +90,6 @@ MCFFEC_TOUT_LOOP		-- set FEC timeout loop
 CONFIG_MCFTMR			-- define to use DMA timer
 
 CONFIG_SYS_I2C_FSL		-- define to use FSL common I2C driver
-CONFIG_SYS_I2C_SOFT		-- define for I2C bit-banged
-CONFIG_SYS_I2C_SPEED		-- define for I2C speed
-CONFIG_SYS_I2C_SLAVE		-- define for I2C slave address
-CONFIG_SYS_I2C_OFFSET		-- define for I2C base address offset
 CONFIG_SYS_IMMR			-- define for MBAR offset
 
 CFG_SYS_MBAR			-- define MBAR offset

board/nxp/m5373evb/README

@@ -89,10 +89,6 @@ MCFFEC_TOUT_LOOP	-- set FEC timeout loop
 CONFIG_MCFTMR		-- define to use DMA timer
 
 CONFIG_SYS_I2C_FSL	-- define to use FSL common I2C driver
-CONFIG_SYS_I2C_SOFT	-- define for I2C bit-banged
-CONFIG_SYS_I2C_SPEED		-- define for I2C speed
-CONFIG_SYS_I2C_SLAVE		-- define for I2C slave address
-CONFIG_SYS_I2C_OFFSET		-- define for I2C base address offset
 CONFIG_SYS_IMMR		-- define for MBAR offset
 
 CFG_SYS_MBAR		-- define MBAR offset

board/nxp/mx6sxsabreauto/mx6sxsabreauto.c

@@ -33,16 +33,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
-	PAD_CTL_SPEED_HIGH   |                                   \
-	PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST)
-
-#define ENET_CLK_PAD_CTRL  (PAD_CTL_SPEED_MED | \
-	PAD_CTL_DSE_120ohm   | PAD_CTL_SRE_FAST)
-
-#define ENET_RX_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |          \
-	PAD_CTL_SPEED_HIGH   | PAD_CTL_SRE_FAST)
-
 #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
 #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
 			PAD_CTL_SRE_FAST)
@@ -55,48 +45,6 @@ int dram_init(void)
 	return 0;
 }
 
-static iomux_v3_cfg_t const fec2_pads[] = {
-	MX6_PAD_ENET1_MDC__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET1_MDIO__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII2_RX_CTL__ENET2_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
-	MX6_PAD_RGMII2_RD0__ENET2_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
-	MX6_PAD_RGMII2_RD1__ENET2_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
-	MX6_PAD_RGMII2_RD2__ENET2_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
-	MX6_PAD_RGMII2_RD3__ENET2_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
-	MX6_PAD_RGMII2_RXC__ENET2_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
-	MX6_PAD_RGMII2_TX_CTL__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII2_TD0__ENET2_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII2_TD1__ENET2_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII2_TD2__ENET2_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII2_TD3__ENET2_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII2_TXC__ENET2_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
-};
-
-static int setup_fec(void)
-{
-	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
-
-	/* Use 125MHz anatop loopback REF_CLK1 for ENET2 */
-	clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, 0);
-
-	return enable_fec_anatop_clock(1, ENET_125MHZ);
-}
-
-int board_eth_init(struct bd_info *bis)
-{
-	int ret;
-
-	imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads));
-	setup_fec();
-
-	ret = fecmxc_initialize_multi(bis, 1,
-		CFG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
-	if (ret)
-		printf("FEC%d MXC: %s:failed\n", 1, __func__);
-
-	return ret;
-}
-
 int board_phy_config(struct phy_device *phydev)
 {
 	/*

board/nxp/mx6sxsabresd/mx6sxsabresd.c

@@ -40,16 +40,6 @@ DECLARE_GLOBAL_DATA_PTR;
 	PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |		\
 	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
-#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
-	PAD_CTL_SPEED_HIGH   |                                   \
-	PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST)
-
-#define ENET_CLK_PAD_CTRL  (PAD_CTL_SPEED_MED | \
-	PAD_CTL_DSE_120ohm   | PAD_CTL_SRE_FAST)
-
-#define ENET_RX_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |          \
-	PAD_CTL_SPEED_HIGH   | PAD_CTL_SRE_FAST)
-
 #define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
 	PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
 
@@ -71,84 +61,16 @@ static iomux_v3_cfg_t const uart1_pads[] = {
 static iomux_v3_cfg_t const wdog_b_pad = {
 	MX6_PAD_GPIO1_IO13__GPIO1_IO_13 | MUX_PAD_CTRL(WDOG_PAD_CTRL),
 };
-static iomux_v3_cfg_t const fec1_pads[] = {
-	MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
-	MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
-	MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
-	MX6_PAD_RGMII1_RD2__ENET1_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
-	MX6_PAD_RGMII1_RD3__ENET1_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
-	MX6_PAD_RGMII1_RXC__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
-	MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII1_TD2__ENET1_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII1_TD3__ENET1_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII1_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
-};
 
 static iomux_v3_cfg_t const peri_3v3_pads[] = {
 	MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 
-static iomux_v3_cfg_t const phy_control_pads[] = {
-	/* 25MHz Ethernet PHY Clock */
-	MX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
-
-	/* ENET PHY Power */
-	MX6_PAD_ENET2_COL__GPIO2_IO_6 | MUX_PAD_CTRL(NO_PAD_CTRL),
-
-	/* AR8031 PHY Reset */
-	MX6_PAD_ENET2_CRS__GPIO2_IO_7 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
 static void setup_iomux_uart(void)
 {
 	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 }
 
-static int setup_fec(void)
-{
-	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
-	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
-	int reg, ret;
-
-	/* Use 125MHz anatop loopback REF_CLK1 for ENET1 */
-	clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0);
-
-	ret = enable_fec_anatop_clock(0, ENET_125MHZ);
-	if (ret)
-		return ret;
-
-	imx_iomux_v3_setup_multiple_pads(phy_control_pads,
-					 ARRAY_SIZE(phy_control_pads));
-
-	/* Enable the ENET power, active low */
-	gpio_request(IMX_GPIO_NR(2, 6), "enet_rst");
-	gpio_direction_output(IMX_GPIO_NR(2, 6) , 0);
-
-	/* Reset AR8031 PHY */
-	gpio_request(IMX_GPIO_NR(2, 7), "phy_rst");
-	gpio_direction_output(IMX_GPIO_NR(2, 7) , 0);
-	mdelay(10);
-	gpio_set_value(IMX_GPIO_NR(2, 7), 1);
-
-	reg = readl(&anatop->pll_enet);
-	reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
-	writel(reg, &anatop->pll_enet);
-
-	return 0;
-}
-
-int board_eth_init(struct bd_info *bis)
-{
-	imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
-	setup_fec();
-
-	return cpu_eth_init(bis);
-}
-
 int power_init_board(void)
 {
 	struct udevice *dev;

board/nxp/p2041rdb/Makefile

@@ -7,4 +7,3 @@
 obj-y	+= p2041rdb.o
 obj-y	+= cpld.o
 obj-y	+= ddr.o
-obj-y	+= eth.o

board/nxp/p2041rdb/README

@@ -1,138 +0,0 @@
-Overview
-=========
-The P2041 Processor combines four Power Architecture processor cores
-with high-performance datapath acceleration architecture(DPAA), CoreNet
-fabric infrastructure, as well as network and peripheral bus interfaces
-required for networking, telecom/datacom, wireless infrastructure, and
-military/aerospace applications.
-
-P2041RDB board is a quad core platform supporting the P2041 processor
-of QorIQ DPAA series.
-
-Boot from NOR flash
-===================
-1. Build image
-	make P2041RDB_config
-	make all
-
-2. Program image
-	=> tftp 1000000 u-boot.bin
-	=> protect off all
-	=> erase eff40000 efffffff
-	=> cp.b 1000000 eff40000 c0000
-
-3. Program RCW
-	=> tftp 1000000 rcw.bin
-	=> protect off all
-	=> erase e8000000 e801ffff
-	=> cp.b 1000000 e8000000 50
-
-4. Program FMAN Firmware ucode
-	=> tftp 1000000 ucode.bin
-	=> protect off all
-	=> erase eff00000 eff3ffff
-	=> cp.b 1000000 eff00000 2000
-
-5. Change DIP-switch
-	SW1[1-5] = 10110
-	Note: 1 stands for 'on', 0 stands for 'off'
-
-Boot from SDCard
-===================
-1. Build image
-	make P2041RDB_SDCARD_config
-	make all
-
-2. Generate PBL imge
-   Use PE tool to produce a image used to be programed to
-   SDCard which contains RCW and U-Boot image.
-
-3. Program the PBL image to SDCard
-	=> tftp 1000000 pbl_sd.bin
-	=> mmcinfo
-	=> mmc write 1000000 8 672
-
-4. Program FMAN Firmware ucode
-	=> tftp 1000000 ucode.bin
-	=> mmc write 1000000 690 10
-
-5. Change DIP-switch
-	SW1[1-5] = 01100
-	Note: 1 stands for 'on', 0 stands for 'off'
-
-Boot from SPI flash
-===================
-1. Build image
-	make P2041RDB_SPIFLASH_config
-	make all
-
-2. Generate PBL imge
-   Use PE tool to produce a image used to be programed to
-   SPI flash which contains RCW and U-Boot image.
-
-3. Program the PBL image to SPI flash
-	=> tftp 1000000 pbl_spi.bin
-	=> spi probe 0
-	=> sf erase 0 100000
-	=> sf write 1000000 0 $filesize
-
-4. Program FMAN Firmware ucode
-	=> tftp 1000000 ucode.bin
-	=> sf erase 110000 10000
-	=> sf write 1000000 110000 $filesize
-
-5. Change DIP-switch
-	SW1[1-5] = 10100
-	Note: 1 stands for 'on', 0 stands for 'off'
-
-Device tree support and how to enable it for different configs
---------------------------------------------------------------
-Device tree support is available for p2041rdb for below mentioned boot,
-1. NOR Boot
-2. NAND Boot
-3. SD Boot
-4. SPIFLASH Boot
-
-To enable device tree support for other boot, below configs need to be
-enabled in relative defconfig file,
-1. CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" (Change default device tree name if required)
-2. CONFIG_OF_CONTROL
-3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at
-   CFG_RESET_VECTOR_ADDRESS - 0xffc
-
-CPLD command
-============
-The CPLD is used to control the power sequence and some serdes lane
-mux function.
-
-cpld reset			 - hard reset to default bank
-cpld reset altbank		 - reset to alternate bank
-cpld lane_mux <lane> <mux_value> - set multiplexed lane pin
-		lane 6: 0 -> slot1 (Default)
-			1 -> SGMII
-		lane a: 0 -> slot2 (Default)
-			1 -> AURORA
-		lane c: 0 -> slot2 (Default)
-			1 -> SATA0
-		lane d: 0 -> slot2 (Default)
-			1 -> SATA1
-
-Using the Device Tree Source File
-=================================
-To create the DTB (Device Tree Binary) image file, use a command
-similar to this:
-	dtc -O dtb -b 0 -p 1024 p2041rdb.dts > p2041rdb.dtb
-
-Or use the following command:
-	{linux-2.6}/make p2041rdb.dtb ARCH=powerpc
-
-then the dtb file will be generated under the following directory:
-	{linux-2.6}/arch/powerpc/boot/p2041rdb.dtb
-
-Booting Linux
-=============
-Place a linux uImage in the TFTP disk area.
-	tftp 1000000 uImage
-	tftp 2000000 rootfs.ext2.gz.uboot
-	tftp 3000000 p2041rdb.dtb
-	bootm 1000000 2000000 3000000

board/nxp/p2041rdb/README.rst

@@ -0,0 +1,147 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+P2041-RDB Board Overview
+========================
+
+The P2041 Processor combines four Power Architecture processor cores
+with high-performance datapath acceleration architecture(DPAA), CoreNet
+fabric infrastructure, as well as network and peripheral bus interfaces
+required for networking, telecom/datacom, wireless infrastructure, and
+military/aerospace applications.
+
+P2041RDB board is a quad core platform supporting the P2041 processor
+of QorIQ DPAA series.
+
+Boot from NOR flash
+===================
+
+1. Build image::
+
+    make P2041RDB_config
+    make all
+
+2. Program image::
+
+    => tftp 1000000 u-boot.bin
+    => protect off all
+    => erase eff40000 efffffff
+    => cp.b 1000000 eff40000 c0000
+
+3. Program RCW::
+
+    => tftp 1000000 rcw.bin
+    => protect off all
+    => erase e8000000 e801ffff
+    => cp.b 1000000 e8000000 50
+
+4. Program FMAN Firmware ucode::
+
+    => tftp 1000000 ucode.bin
+    => protect off all
+    => erase eff00000 eff3ffff
+    => cp.b 1000000 eff00000 2000
+
+5. Change DIP-switch to SW1[1-5] = 10110. Note: 1 stands for 'on', 0 stands for 'off'
+
+Boot from SDCard
+================
+
+1. Build image::
+
+    make P2041RDB_SDCARD_config
+    make all
+
+2. Program the PBL image to SDCard::
+
+    => tftp 1000000 u-boot.pbl
+    => mmc info
+    => mmc write 1000000 8 672
+
+3. Program FMAN Firmware ucode::
+
+    => tftp 1000000 ucode.bin
+    => mmc write 1000000 690 10
+
+4. Change DIP-switch to SW1[1-5] = 01100. Note: 1 stands for 'on', 0 stands for 'off'
+
+Boot from SPI flash
+===================
+
+1. Build image::
+
+    make P2041RDB_SPIFLASH_config
+    make all
+
+2. Program the PBL image to SPI flash::
+
+    => tftp 1000000 u-boot.pbl
+    => sf probe 0
+    => sf update $fileaddr 0 $filesize
+
+3. Program FMAN Firmware ucode::
+
+    => tftp 1000000 ucode.bin
+    => sf update $fileaddr 110000 $filesize
+
+4. Change DIP-switch SW1[1-5] = 10100. Note: 1 stands for 'on', 0 stands for 'off'
+
+Device tree support and how to enable it for different configs
+--------------------------------------------------------------
+
+Device tree support is available for p2041rdb for below mentioned boot,
+
+1. NOR Boot
+2. NAND Boot
+3. SD Boot
+4. SPIFLASH Boot
+
+To enable device tree support for other boot, below configs need to be
+enabled in relative defconfig file,
+
+1. CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" (Change default device tree name if required)
+2. CONFIG_OF_CONTROL
+3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at
+   CFG_RESET_VECTOR_ADDRESS - 0xffc
+
+CPLD command
+============
+
+The CPLD is used to control the power sequence and some serdes lane
+mux function::
+
+  cpld reset			 - hard reset to default bank
+  cpld reset altbank		 - reset to alternate bank
+  cpld lane_mux <lane> <mux_value> - set multiplexed lane pin
+                lane 6: 0 -> slot1 (Default)
+                        1 -> SGMII
+                lane a: 0 -> slot2 (Default)
+                        1 -> AURORA
+                lane c: 0 -> slot2 (Default)
+                        1 -> SATA0
+                lane d: 0 -> slot2 (Default)
+                        1 -> SATA1
+
+Using the Device Tree Source File
+=================================
+To create the DTB (Device Tree Binary) image file, use a command
+similar to this::
+
+  dtc -O dtb -b 0 -p 1024 p2041rdb.dts > p2041rdb.dtb
+
+Or use the following command::
+
+  {linux-2.6}/make p2041rdb.dtb ARCH=powerpc
+
+then the dtb file will be generated under the following directory::
+
+  {linux-2.6}/arch/powerpc/boot/p2041rdb.dtb
+
+Booting Linux
+=============
+
+Place a linux uImage in the TFTP disk area::
+
+ => tftp 1000000 uImage
+ => tftp 2000000 rootfs.ext2.gz.uboot
+ => tftp 3000000 p2041rdb.dtb
+ => bootm 1000000 2000000 3000000

board/nxp/p2041rdb/eth.c

@@ -1,210 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- * Author: Mingkai Hu <Mingkai.hu@freescale.com>
- */
-
-/*
- * The RGMII PHYs are provided by the two on-board PHY. The SGMII PHYs
- * are provided by the three on-board PHY or by the standard Freescale
- * four-port SGMII riser card. We need to change the phy-handle in the
- * kernel dts file to point to the correct PHY according to serdes mux
- * and serdes protocol selection.
- */
-
-#include <config.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/fsl_serdes.h>
-#include <fm_eth.h>
-#include <fsl_mdio.h>
-#include <malloc.h>
-#include <fsl_dtsec.h>
-
-#include "cpld.h"
-#include "../common/fman.h"
-
-#ifdef CONFIG_FMAN_ENET
-/*
- * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means
- * that the mapping must be determined dynamically, or that the lane maps to
- * something other than a board slot
- */
-static u8 lane_to_slot[] = {
-	0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 2, 2, 2, 2, 0, 0, 0, 0
-};
-
-static int riser_phy_addr[] = {
-	CFG_SYS_FM1_DTSEC1_RISER_PHY_ADDR,
-	CFG_SYS_FM1_DTSEC2_RISER_PHY_ADDR,
-	CFG_SYS_FM1_DTSEC3_RISER_PHY_ADDR,
-	CFG_SYS_FM1_DTSEC4_RISER_PHY_ADDR,
-};
-
-/*
- * Initialize the lane_to_slot[] array.
- *
- * On the P2040RDB board the mapping is controlled by CPLD register.
- */
-static void initialize_lane_to_slot(void)
-{
-	u8 mux = CPLD_READ(serdes_mux);
-
-	lane_to_slot[6] = (mux & SERDES_MUX_LANE_6_MASK) ? 0 : 1;
-	lane_to_slot[10] = (mux & SERDES_MUX_LANE_A_MASK) ? 0 : 2;
-	lane_to_slot[12] = (mux & SERDES_MUX_LANE_C_MASK) ? 0 : 2;
-	lane_to_slot[13] = (mux & SERDES_MUX_LANE_D_MASK) ? 0 : 2;
-}
-
-/*
- * Given the following ...
- *
- * 1) A pointer to an Fman Ethernet node (as identified by the 'compat'
- * compatible string and 'addr' physical address)
- *
- * 2) An Fman port
- *
- * ... update the phy-handle property of the Ethernet node to point to the
- * right PHY.  This assumes that we already know the PHY for each port.
- *
- * The offset of the Fman Ethernet node is also passed in for convenience, but
- * it is not used, and we recalculate the offset anyway.
- *
- * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC.
- * Inside the Fman, "ports" are things that connect to MACs.  We only call them
- * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs
- * and ports are the same thing.
- *
- */
-void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
-			      enum fm_port port, int offset)
-{
-	phy_interface_t intf = fm_info_get_enet_if(port);
-	char phy[16];
-	int lane;
-	u8 slot;
-
-	switch (intf) {
-	/* The RGMII PHY is identified by the MAC connected to it */
-	case PHY_INTERFACE_MODE_RGMII:
-	case PHY_INTERFACE_MODE_RGMII_TXID:
-	case PHY_INTERFACE_MODE_RGMII_RXID:
-	case PHY_INTERFACE_MODE_RGMII_ID:
-		sprintf(phy, "phy_rgmii_%u", port == FM1_DTSEC5 ? 0 : 1);
-		fdt_set_phy_handle(fdt, compat, addr, phy);
-		break;
-	/* The SGMII PHY is identified by the MAC connected to it */
-	case PHY_INTERFACE_MODE_SGMII:
-		lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + port);
-		if (lane < 0)
-			return;
-		slot = lane_to_slot[lane];
-		if (slot) {
-			sprintf(phy, "phy_sgmii_%x",
-					CFG_SYS_FM1_DTSEC1_RISER_PHY_ADDR
-					+ (port - FM1_DTSEC1));
-			fdt_set_phy_handle(fdt, compat, addr, phy);
-		} else {
-			sprintf(phy, "phy_sgmii_%x",
-					CFG_SYS_FM1_DTSEC1_PHY_ADDR
-					+ (port - FM1_DTSEC1));
-			fdt_set_phy_handle(fdt, compat, addr, phy);
-		}
-		break;
-	case PHY_INTERFACE_MODE_XGMII:
-		/* XAUI */
-		lane = serdes_get_first_lane(XAUI_FM1);
-		if (lane >= 0) {
-			/* The XAUI PHY is identified by the slot */
-			sprintf(phy, "phy_xgmii_%u", lane_to_slot[lane]);
-			fdt_set_phy_handle(fdt, compat, addr, phy);
-		}
-		break;
-	default:
-		break;
-	}
-}
-#endif /* #ifdef CONFIG_FMAN_ENET */
-
-int board_eth_init(struct bd_info *bis)
-{
-#ifdef CONFIG_FMAN_ENET
-	struct fsl_pq_mdio_info dtsec_mdio_info;
-	struct tgec_mdio_info tgec_mdio_info;
-	unsigned int i, slot;
-	int lane;
-
-	printf("Initializing Fman\n");
-
-	initialize_lane_to_slot();
-
-	dtsec_mdio_info.regs =
-		(struct tsec_mii_mng *)CFG_SYS_FM1_DTSEC1_MDIO_ADDR;
-	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
-
-	/* Register the real 1G MDIO bus */
-	fsl_pq_mdio_init(bis, &dtsec_mdio_info);
-
-	tgec_mdio_info.regs =
-		(struct tgec_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR;
-	tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
-
-	/* Register the real 10G MDIO bus */
-	fm_tgec_mdio_init(bis, &tgec_mdio_info);
-
-	/*
-	 * Program the three on-board SGMII PHY addresses. If the SGMII Riser
-	 * card used, we'll override the PHY address later. For any DTSEC that
-	 * is RGMII, we'll also override its PHY address later. We assume that
-	 * DTSEC4 and DTSEC5 are used for RGMII.
-	 */
-	fm_info_set_phy_address(FM1_DTSEC1, CFG_SYS_FM1_DTSEC1_PHY_ADDR);
-	fm_info_set_phy_address(FM1_DTSEC2, CFG_SYS_FM1_DTSEC2_PHY_ADDR);
-	fm_info_set_phy_address(FM1_DTSEC3, CFG_SYS_FM1_DTSEC3_PHY_ADDR);
-
-	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) {
-		int idx = i - FM1_DTSEC1;
-
-		switch (fm_info_get_enet_if(i)) {
-		case PHY_INTERFACE_MODE_SGMII:
-			lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
-			if (lane < 0)
-				break;
-			slot = lane_to_slot[lane];
-			if (slot)
-				fm_info_set_phy_address(i, riser_phy_addr[i]);
-			break;
-		case PHY_INTERFACE_MODE_RGMII:
-		case PHY_INTERFACE_MODE_RGMII_TXID:
-		case PHY_INTERFACE_MODE_RGMII_RXID:
-		case PHY_INTERFACE_MODE_RGMII_ID:
-			/* Only DTSEC4 and DTSEC5 can be routed to RGMII */
-			fm_info_set_phy_address(i, i == FM1_DTSEC5 ?
-					CFG_SYS_FM1_DTSEC5_PHY_ADDR :
-					CFG_SYS_FM1_DTSEC4_PHY_ADDR);
-			break;
-		default:
-			printf("Fman1: DTSEC%u set to unknown interface %i\n",
-			       idx + 1, fm_info_get_enet_if(i));
-			break;
-		}
-
-		fm_info_set_mdio(i,
-			miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
-	}
-
-	lane = serdes_get_first_lane(XAUI_FM1);
-	if (lane >= 0) {
-		slot = lane_to_slot[lane];
-		if (slot)
-			fm_info_set_phy_address(FM1_10GEC1,
-					CFG_SYS_FM1_10GEC1_PHY_ADDR);
-	}
-
-	fm_info_set_mdio(FM1_10GEC1,
-			miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME));
-	cpu_eth_init(bis);
-#endif
-
-	return pci_eth_init(bis);
-}

board/nxp/p2041rdb/p2041rdb_rcw_sd.cfg

@@ -0,0 +1,11 @@
+#
+# Default RCW for P2041RDB.
+#
+
+#PBL preamble and RCW header
+aa55aa55 010e0100
+#64 bytes RCW data
+12600000 00000000 241C0000 00000000
+649FA0C1 C3C02000 68000000 40000000
+00000000 00000000 00000000 D0030F07
+00000000 00000000 00000000 00000000

board/nxp/t102xrdb/Makefile

@@ -9,7 +9,6 @@ obj-y	+= spl.o
 else
 obj-y   += t102xrdb.o
 obj-$(CONFIG_TARGET_T1024RDB)   += cpld.o
-obj-y   += eth_t102xrdb.o
 endif
 obj-y   += ddr.o
 obj-y   += law.o

board/nxp/t102xrdb/eth_t102xrdb.c

@@ -1,149 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- *
- * Shengzhou Liu <Shengzhou.Liu@freescale.com>
- */
-
-#include <config.h>
-#include <command.h>
-#include <fdt_support.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/mmu.h>
-#include <asm/processor.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_law.h>
-#include <asm/fsl_serdes.h>
-#include <asm/fsl_portals.h>
-#include <asm/fsl_liodn.h>
-#include <malloc.h>
-#include <fm_eth.h>
-#include <fsl_mdio.h>
-#include <miiphy.h>
-#include <phy.h>
-#include <fsl_dtsec.h>
-#include <asm/fsl_serdes.h>
-#include "../common/fman.h"
-
-int board_eth_init(struct bd_info *bis)
-{
-#if defined(CONFIG_FMAN_ENET)
-	int i, interface;
-	struct memac_mdio_info dtsec_mdio_info;
-	struct memac_mdio_info tgec_mdio_info;
-	struct mii_dev *dev;
-	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
-	u32 srds_s1;
-
-	srds_s1 = in_be32(&gur->rcwsr[4]) &
-					FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
-	srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
-
-	dtsec_mdio_info.regs =
-		(struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR;
-
-	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
-
-	/* Register the 1G MDIO bus */
-	fm_memac_mdio_init(bis, &dtsec_mdio_info);
-
-	tgec_mdio_info.regs =
-		(struct memac_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR;
-	tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
-
-	/* Register the 10G MDIO bus */
-	fm_memac_mdio_init(bis, &tgec_mdio_info);
-
-	/* Set the on-board RGMII PHY address */
-	fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR);
-
-	switch (srds_s1) {
-#ifdef CONFIG_TARGET_T1024RDB
-	case 0x95:
-		/* set the on-board RGMII2  PHY */
-		fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR);
-
-		/* set 10GBase-R with Aquantia AQR105 PHY */
-		fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
-		break;
-#endif
-	case 0x6a:
-	case 0x6b:
-	case 0x77:
-	case 0x135:
-		/* set the on-board 2.5G SGMII AQR105 PHY */
-		fm_info_set_phy_address(FM1_DTSEC3, SGMII_AQR_PHY_ADDR);
-#ifdef CONFIG_TARGET_T1023RDB
-		/* set the on-board 1G SGMII RTL8211F PHY */
-		fm_info_set_phy_address(FM1_DTSEC1, SGMII_RTK_PHY_ADDR);
-#endif
-		break;
-	default:
-		printf("SerDes protocol 0x%x is not supported on T102xRDB\n",
-		       srds_s1);
-		break;
-	}
-
-	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) {
-		interface = fm_info_get_enet_if(i);
-		switch (interface) {
-		case PHY_INTERFACE_MODE_RGMII:
-		case PHY_INTERFACE_MODE_RGMII_TXID:
-		case PHY_INTERFACE_MODE_RGMII_RXID:
-		case PHY_INTERFACE_MODE_RGMII_ID:
-			dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
-			fm_info_set_mdio(i, dev);
-			break;
-		case PHY_INTERFACE_MODE_SGMII:
-#if defined(CONFIG_TARGET_T1023RDB)
-			dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
-#elif defined(CONFIG_TARGET_T1024RDB)
-			dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
-#endif
-			fm_info_set_mdio(i, dev);
-			break;
-		case PHY_INTERFACE_MODE_2500BASEX:
-			dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
-			fm_info_set_mdio(i, dev);
-			break;
-		default:
-			break;
-		}
-	}
-
-	for (i = FM1_10GEC1; i < FM1_10GEC1 + CFG_SYS_NUM_FM1_10GEC; i++) {
-		switch (fm_info_get_enet_if(i)) {
-		case PHY_INTERFACE_MODE_XGMII:
-			dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
-			fm_info_set_mdio(i, dev);
-			break;
-		default:
-			break;
-		}
-	}
-
-	cpu_eth_init(bis);
-#endif /* CONFIG_FMAN_ENET */
-
-	return pci_eth_init(bis);
-}
-
-void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
-			      enum fm_port port, int offset)
-{
-#if defined(CONFIG_TARGET_T1024RDB)
-	if (((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_2500BASEX) ||
-	     (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII)) &&
-			(port == FM1_DTSEC3)) {
-		fdt_set_phy_handle(fdt, compat, addr, "sg_2500_aqr105_phy4");
-		fdt_setprop_string(fdt, offset, "phy-connection-type",
-				   "2500base-x");
-		fdt_status_disabled_by_alias(fdt, "xg_aqr105_phy3");
-	}
-#endif
-}
-
-void fdt_fixup_board_enet(void *fdt)
-{
-}

board/nxp/t102xrdb/t102xrdb.c

@@ -207,7 +207,6 @@ int ft_board_setup(void *blob, struct bd_info *bd)
 #ifndef CONFIG_DM_ETH
 	fdt_fixup_fman_ethernet(blob);
 #endif
-	fdt_fixup_board_enet(blob);
 #endif
 
 #ifdef CONFIG_TARGET_T1023RDB

board/nxp/t102xrdb/t102xrdb.h

@@ -6,7 +6,6 @@
 #ifndef __T1024_RDB_H__
 #define __T1024_RDB_H__
 
-void fdt_fixup_board_enet(void *blob);
 void pci_of_setup(void *blob, struct bd_info *bd);
 #ifdef CONFIG_TARGET_T1023RDB
 static u32 t1023rdb_ctrl(u32 ctrl_type);

board/nxp/t104xrdb/Makefile

@@ -7,7 +7,6 @@ obj-y += spl.o
 else
 obj-y	+= t104xrdb.o
 obj-y	+= cpld.o
-obj-y	+= eth.o
 endif
 obj-y	+= ddr.o
 obj-y	+= law.o

board/nxp/t104xrdb/eth.c

@@ -1,91 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- */
-
-#include <config.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/fsl_serdes.h>
-#include <asm/immap_85xx.h>
-#include <fm_eth.h>
-#include <fsl_mdio.h>
-#include <malloc.h>
-#include <fsl_dtsec.h>
-#include <vsc9953.h>
-
-#include "../common/fman.h"
-
-int board_eth_init(struct bd_info *bis)
-{
-#ifdef CONFIG_FMAN_ENET
-	struct memac_mdio_info memac_mdio_info;
-	unsigned int i;
-	int phy_addr = 0;
-
-	printf("Initializing Fman\n");
-
-	memac_mdio_info.regs =
-		(struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR;
-	memac_mdio_info.name = DEFAULT_FM_MDIO_NAME;
-
-	/* Register the real 1G MDIO bus */
-	fm_memac_mdio_init(bis, &memac_mdio_info);
-
-	/*
-	 * Program on board RGMII, SGMII PHY addresses.
-	 */
-	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) {
-		int idx = i - FM1_DTSEC1;
-
-		switch (fm_info_get_enet_if(i)) {
-#ifdef CONFIG_TARGET_T1042D4RDB
-		case PHY_INTERFACE_MODE_SGMII:
-			/* T1042D4RDB supports SGMII on DTSEC1, DTSEC2
-			 *  & DTSEC3
-			 */
-			if (FM1_DTSEC1 == i)
-				phy_addr = CFG_SYS_SGMII1_PHY_ADDR;
-			if (FM1_DTSEC2 == i)
-				phy_addr = CFG_SYS_SGMII2_PHY_ADDR;
-			if (FM1_DTSEC3 == i)
-				phy_addr = CFG_SYS_SGMII3_PHY_ADDR;
-			fm_info_set_phy_address(i, phy_addr);
-			break;
-#endif
-		case PHY_INTERFACE_MODE_RGMII:
-		case PHY_INTERFACE_MODE_RGMII_TXID:
-		case PHY_INTERFACE_MODE_RGMII_RXID:
-		case PHY_INTERFACE_MODE_RGMII_ID:
-			if (FM1_DTSEC4 == i)
-				phy_addr = CFG_SYS_RGMII1_PHY_ADDR;
-			if (FM1_DTSEC5 == i)
-				phy_addr = CFG_SYS_RGMII2_PHY_ADDR;
-			fm_info_set_phy_address(i, phy_addr);
-			break;
-		case PHY_INTERFACE_MODE_QSGMII:
-			fm_info_set_phy_address(i, 0);
-			break;
-		case PHY_INTERFACE_MODE_NA:
-			fm_info_set_phy_address(i, 0);
-			break;
-		default:
-			printf("Fman1: DTSEC%u set to unknown interface %i\n",
-			       idx + 1, fm_info_get_enet_if(i));
-			fm_info_set_phy_address(i, 0);
-			break;
-		}
-		if (fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_QSGMII ||
-		    fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_NA)
-			fm_info_set_mdio(i, NULL);
-		else
-			fm_info_set_mdio(i,
-					 miiphy_get_dev_by_name(
-							DEFAULT_FM_MDIO_NAME));
-	}
-
-	cpu_eth_init(bis);
-#endif
-
-	return pci_eth_init(bis);
-}

board/nxp/t104xrdb/t104xrdb.h

@@ -6,7 +6,6 @@
 #ifndef __T104x_RDB_H__
 #define __T104x_RDB_H__
 
-void fdt_fixup_board_enet(void *blob);
 void pci_of_setup(void *blob, struct bd_info *bd);
 
 #endif

board/nxp/t208xqds/Makefile

@@ -7,7 +7,7 @@
 ifdef CONFIG_XPL_BUILD
 obj-y += spl.o
 else
-obj-$(CONFIG_TARGET_T2080QDS) += t208xqds.o eth_t208xqds.o
+obj-$(CONFIG_TARGET_T2080QDS) += t208xqds.o
 endif
 
 obj-y   += ddr.o

board/nxp/t208xqds/eth_t208xqds.c

@@ -1,723 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- * Copyright 2020 NXP
- *
- * Shengzhou Liu <Shengzhou.Liu@freescale.com>
- */
-
-#include <config.h>
-#include <command.h>
-#include <fdt_support.h>
-#include <log.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/mmu.h>
-#include <asm/processor.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_law.h>
-#include <asm/fsl_serdes.h>
-#include <asm/fsl_portals.h>
-#include <asm/fsl_liodn.h>
-#include <malloc.h>
-#include <fm_eth.h>
-#include <fsl_mdio.h>
-#include <miiphy.h>
-#include <phy.h>
-#include <fsl_dtsec.h>
-#include <asm/fsl_serdes.h>
-#include <hwconfig.h>
-#include "../common/qixis.h"
-#include "../common/fman.h"
-#include "t208xqds_qixis.h"
-#include <linux/libfdt.h>
-
-#define EMI_NONE	0xFFFFFFFF
-#define EMI1_RGMII1	0
-#define EMI1_RGMII2     1
-#define EMI1_SLOT1	2
-#if defined(CONFIG_TARGET_T2080QDS)
-#define EMI1_SLOT2	6
-#define EMI1_SLOT3	3
-#define EMI1_SLOT4	4
-#define EMI1_SLOT5	5
-#define EMI2            7
-#endif
-
-#define PCCR1_SGMIIA_KX_MASK		0x00008000
-#define PCCR1_SGMIIB_KX_MASK		0x00004000
-#define PCCR1_SGMIIC_KX_MASK		0x00002000
-#define PCCR1_SGMIID_KX_MASK		0x00001000
-#define PCCR1_SGMIIE_KX_MASK		0x00000800
-#define PCCR1_SGMIIF_KX_MASK		0x00000400
-#define PCCR1_SGMIIG_KX_MASK		0x00000200
-#define PCCR1_SGMIIH_KX_MASK		0x00000100
-
-static int mdio_mux[NUM_FM_PORTS];
-
-static const char * const mdio_names[] = {
-#if defined(CONFIG_TARGET_T2080QDS)
-	"T2080QDS_MDIO_RGMII1",
-	"T2080QDS_MDIO_RGMII2",
-	"T2080QDS_MDIO_SLOT1",
-	"T2080QDS_MDIO_SLOT3",
-	"T2080QDS_MDIO_SLOT4",
-	"T2080QDS_MDIO_SLOT5",
-	"T2080QDS_MDIO_SLOT2",
-	"T2080QDS_MDIO_10GC",
-#endif
-};
-
-/* Map SerDes1 8 lanes to default slot, will be initialized dynamically */
-#if defined(CONFIG_TARGET_T2080QDS)
-static u8 lane_to_slot[] = {3, 3, 3, 3, 1, 1, 1, 1};
-#endif
-
-static const char *t208xqds_mdio_name_for_muxval(u8 muxval)
-{
-	return mdio_names[muxval];
-}
-
-struct mii_dev *mii_dev_for_muxval(u8 muxval)
-{
-	struct mii_dev *bus;
-	const char *name = t208xqds_mdio_name_for_muxval(muxval);
-
-	if (!name) {
-		printf("No bus for muxval %x\n", muxval);
-		return NULL;
-	}
-
-	bus = miiphy_get_dev_by_name(name);
-
-	if (!bus) {
-		printf("No bus by name %s\n", name);
-		return NULL;
-	}
-
-	return bus;
-}
-
-struct t208xqds_mdio {
-	u8 muxval;
-	struct mii_dev *realbus;
-};
-
-static void t208xqds_mux_mdio(u8 muxval)
-{
-	u8 brdcfg4;
-	if (muxval < 8) {
-		brdcfg4 = QIXIS_READ(brdcfg[4]);
-		brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
-		brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
-		QIXIS_WRITE(brdcfg[4], brdcfg4);
-	}
-}
-
-static int t208xqds_mdio_read(struct mii_dev *bus, int addr, int devad,
-				int regnum)
-{
-	struct t208xqds_mdio *priv = bus->priv;
-
-	t208xqds_mux_mdio(priv->muxval);
-
-	return priv->realbus->read(priv->realbus, addr, devad, regnum);
-}
-
-static int t208xqds_mdio_write(struct mii_dev *bus, int addr, int devad,
-				int regnum, u16 value)
-{
-	struct t208xqds_mdio *priv = bus->priv;
-
-	t208xqds_mux_mdio(priv->muxval);
-
-	return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
-}
-
-static int t208xqds_mdio_reset(struct mii_dev *bus)
-{
-	struct t208xqds_mdio *priv = bus->priv;
-
-	return priv->realbus->reset(priv->realbus);
-}
-
-static int t208xqds_mdio_init(char *realbusname, u8 muxval)
-{
-	struct t208xqds_mdio *pmdio;
-	struct mii_dev *bus = mdio_alloc();
-
-	if (!bus) {
-		printf("Failed to allocate t208xqds MDIO bus\n");
-		return -1;
-	}
-
-	pmdio = malloc(sizeof(*pmdio));
-	if (!pmdio) {
-		printf("Failed to allocate t208xqds private data\n");
-		free(bus);
-		return -1;
-	}
-
-	bus->read = t208xqds_mdio_read;
-	bus->write = t208xqds_mdio_write;
-	bus->reset = t208xqds_mdio_reset;
-	strcpy(bus->name, t208xqds_mdio_name_for_muxval(muxval));
-
-	pmdio->realbus = miiphy_get_dev_by_name(realbusname);
-
-	if (!pmdio->realbus) {
-		printf("No bus with name %s\n", realbusname);
-		free(bus);
-		free(pmdio);
-		return -1;
-	}
-
-	pmdio->muxval = muxval;
-	bus->priv = pmdio;
-	return mdio_register(bus);
-}
-
-void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
-				enum fm_port port, int offset)
-{
-	int phy;
-	char alias[20];
-	char lane_mode[2][20] = {"1000BASE-KX", "10GBASE-KR"};
-	char buf[32] = "serdes-1,";
-	struct fixed_link f_link;
-	int media_type = 0;
-	const char *phyconn;
-	int off;
-
-	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
-#ifdef CONFIG_TARGET_T2080QDS
-	serdes_corenet_t *srds_regs =
-		(void *)CFG_SYS_FSL_CORENET_SERDES_ADDR;
-	u32 srds1_pccr1 = in_be32(&srds_regs->srdspccr1);
-#endif
-	u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
-				FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
-
-	srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
-
-	if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
-		phy = fm_info_get_phy_address(port);
-		switch (port) {
-#if defined(CONFIG_TARGET_T2080QDS)
-		case FM1_DTSEC1:
-			if (hwconfig_sub("fsl_1gkx", "fm1_1g1")) {
-				media_type = 1;
-				fdt_set_phy_handle(fdt, compat, addr,
-						   "phy_1gkx1");
-				fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio1");
-				strcat(buf, "lane-c,");
-				strcat(buf, (char *)lane_mode[0]);
-				out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
-					 PCCR1_SGMIIH_KX_MASK);
-				break;
-			}
-		case FM1_DTSEC2:
-			if (hwconfig_sub("fsl_1gkx", "fm1_1g2")) {
-				media_type = 1;
-				fdt_set_phy_handle(fdt, compat, addr,
-						   "phy_1gkx2");
-				fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio2");
-				strcat(buf, "lane-d,");
-				strcat(buf, (char *)lane_mode[0]);
-				out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
-					 PCCR1_SGMIIG_KX_MASK);
-				break;
-			}
-		case FM1_DTSEC9:
-			if (hwconfig_sub("fsl_1gkx", "fm1_1g9")) {
-				media_type = 1;
-				fdt_set_phy_handle(fdt, compat, addr,
-						   "phy_1gkx9");
-				fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio9");
-				strcat(buf, "lane-a,");
-				strcat(buf, (char *)lane_mode[0]);
-				out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
-					 PCCR1_SGMIIE_KX_MASK);
-				break;
-			}
-		case FM1_DTSEC10:
-			if (hwconfig_sub("fsl_1gkx", "fm1_1g10")) {
-				media_type = 1;
-				fdt_set_phy_handle(fdt, compat, addr,
-						   "phy_1gkx10");
-				fdt_status_okay_by_alias(fdt,
-							 "1gkx_pcs_mdio10");
-				strcat(buf, "lane-b,");
-				strcat(buf, (char *)lane_mode[0]);
-				out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
-					 PCCR1_SGMIIF_KX_MASK);
-				break;
-			}
-			if (mdio_mux[port] == EMI1_SLOT2) {
-				sprintf(alias, "phy_sgmii_s2_%x", phy);
-				fdt_set_phy_handle(fdt, compat, addr, alias);
-				fdt_status_okay_by_alias(fdt, "emi1_slot2");
-			} else if (mdio_mux[port] == EMI1_SLOT3) {
-				sprintf(alias, "phy_sgmii_s3_%x", phy);
-				fdt_set_phy_handle(fdt, compat, addr, alias);
-				fdt_status_okay_by_alias(fdt, "emi1_slot3");
-			}
-			break;
-		case FM1_DTSEC5:
-			if (hwconfig_sub("fsl_1gkx", "fm1_1g5")) {
-				media_type = 1;
-				fdt_set_phy_handle(fdt, compat, addr,
-						   "phy_1gkx5");
-				fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio5");
-				strcat(buf, "lane-g,");
-				strcat(buf, (char *)lane_mode[0]);
-				out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
-					 PCCR1_SGMIIC_KX_MASK);
-				break;
-			}
-		case FM1_DTSEC6:
-			if (hwconfig_sub("fsl_1gkx", "fm1_1g6")) {
-				media_type = 1;
-				fdt_set_phy_handle(fdt, compat, addr,
-						   "phy_1gkx6");
-				fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio6");
-				strcat(buf, "lane-h,");
-				strcat(buf, (char *)lane_mode[0]);
-				out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
-					 PCCR1_SGMIID_KX_MASK);
-				break;
-			}
-			if (mdio_mux[port] == EMI1_SLOT1) {
-				sprintf(alias, "phy_sgmii_s1_%x", phy);
-				fdt_set_phy_handle(fdt, compat, addr, alias);
-				fdt_status_okay_by_alias(fdt, "emi1_slot1");
-			} else if (mdio_mux[port] == EMI1_SLOT2) {
-				sprintf(alias, "phy_sgmii_s2_%x", phy);
-				fdt_set_phy_handle(fdt, compat, addr, alias);
-				fdt_status_okay_by_alias(fdt, "emi1_slot2");
-			}
-			break;
-#endif
-		default:
-			break;
-		}
-		if (media_type) {
-			/* set property for 1000BASE-KX in dtb */
-			off = fdt_node_offset_by_compat_reg(fdt,
-					"fsl,fman-memac-mdio", addr + 0x1000);
-			fdt_setprop_string(fdt, off, "lane-instance", buf);
-		}
-
-	} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) {
-		switch (srds_s1) {
-		case 0x66: /* 10GBase-R interface */
-		case 0x6b:
-		case 0x6c:
-		case 0x6d:
-		case 0x71:
-			/*
-			 * Check hwconfig to see what is the media type, there
-			 * are two types, fiber or copper, fix the dtb
-			 * accordingly.
-			 */
-			switch (port) {
-			case FM1_10GEC1:
-			if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g1")) {
-				/* it's MAC9 */
-				media_type = 1;
-				fdt_set_phy_handle(fdt, compat, addr,
-						"phy_xfi9");
-				fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio9");
-				strcat(buf, "lane-a,");
-				strcat(buf, (char *)lane_mode[1]);
-			}
-				break;
-			case FM1_10GEC2:
-			if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g2")) {
-				/* it's MAC10 */
-				media_type = 1;
-				fdt_set_phy_handle(fdt, compat, addr,
-						"phy_xfi10");
-				fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio10");
-				strcat(buf, "lane-b,");
-				strcat(buf, (char *)lane_mode[1]);
-			}
-				break;
-			case FM1_10GEC3:
-			if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g3")) {
-				/* it's MAC1 */
-				media_type = 1;
-				fdt_set_phy_handle(fdt, compat, addr,
-						"phy_xfi1");
-				fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio1");
-				strcat(buf, "lane-c,");
-				strcat(buf, (char *)lane_mode[1]);
-			}
-				break;
-			case FM1_10GEC4:
-			if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g4")) {
-				/* it's MAC2 */
-				media_type = 1;
-				fdt_set_phy_handle(fdt, compat, addr,
-						"phy_xfi2");
-				fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio2");
-				strcat(buf, "lane-d,");
-				strcat(buf, (char *)lane_mode[1]);
-			}
-				break;
-			default:
-				return;
-			}
-
-			if (!media_type) {
-				phyconn = fdt_getprop(fdt, offset,
-						      "phy-connection-type",
-						      NULL);
-				if (is_backplane_mode(phyconn)) {
-					/* Backplane KR mode: skip fixups */
-					printf("Interface %d in backplane KR mode\n",
-					       port);
-				} else {
-					/* fixed-link for 10GBase-R fiber cable */
-					f_link.phy_id = port;
-					f_link.duplex = 1;
-					f_link.link_speed = 10000;
-					f_link.pause = 0;
-					f_link.asym_pause = 0;
-					fdt_delprop(fdt, offset, "phy-handle");
-					fdt_setprop(fdt, offset, "fixed-link",
-						    &f_link, sizeof(f_link));
-				}
-			} else {
-				/* set property for copper cable */
-				off = fdt_node_offset_by_compat_reg(fdt,
-					"fsl,fman-memac-mdio", addr + 0x1000);
-				fdt_setprop_string(fdt, off,
-					"lane-instance", buf);
-			}
-			break;
-		default:
-			break;
-		}
-	}
-}
-
-void fdt_fixup_board_enet(void *fdt)
-{
-	return;
-}
-
-/*
- * This function reads RCW to check if Serdes1{A:H} is configured
- * to slot 1/2/3/4/5/6/7 and update the lane_to_slot[] array accordingly
- */
-static void initialize_lane_to_slot(void)
-{
-	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
-	u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
-				FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
-
-	srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
-
-	switch (srds_s1) {
-#if defined(CONFIG_TARGET_T2080QDS)
-	case 0x51:
-	case 0x5f:
-	case 0x65:
-	case 0x6b:
-	case 0x71:
-		lane_to_slot[5] = 2;
-		lane_to_slot[6] = 2;
-		lane_to_slot[7] = 2;
-		break;
-	case 0xa6:
-	case 0x8e:
-	case 0x8f:
-	case 0x82:
-	case 0x83:
-	case 0xd3:
-	case 0xd9:
-	case 0xcb:
-		lane_to_slot[6] = 2;
-		lane_to_slot[7] = 2;
-		break;
-	case 0xda:
-		lane_to_slot[4] = 3;
-		lane_to_slot[5] = 3;
-		lane_to_slot[6] = 3;
-		lane_to_slot[7] = 3;
-		break;
-#endif
-	default:
-		break;
-	}
-}
-
-int board_eth_init(struct bd_info *bis)
-{
-#if defined(CONFIG_FMAN_ENET)
-	int i, idx, lane, slot, interface;
-	struct memac_mdio_info dtsec_mdio_info;
-	struct memac_mdio_info tgec_mdio_info;
-	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
-	u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
-	u32 srds_s1;
-
-	srds_s1 = in_be32(&gur->rcwsr[4]) &
-					FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
-	srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
-
-	initialize_lane_to_slot();
-
-	/* Initialize the mdio_mux array so we can recognize empty elements */
-	for (i = 0; i < NUM_FM_PORTS; i++)
-		mdio_mux[i] = EMI_NONE;
-
-	dtsec_mdio_info.regs =
-		(struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR;
-
-	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
-
-	/* Register the 1G MDIO bus */
-	fm_memac_mdio_init(bis, &dtsec_mdio_info);
-
-	tgec_mdio_info.regs =
-		(struct memac_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR;
-	tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
-
-	/* Register the 10G MDIO bus */
-	fm_memac_mdio_init(bis, &tgec_mdio_info);
-
-	/* Register the muxing front-ends to the MDIO buses */
-	t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
-	t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
-	t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
-	t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
-	t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
-#if defined(CONFIG_TARGET_T2080QDS)
-	t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
-#endif
-	t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
-	t208xqds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
-
-	/* Set the two on-board RGMII PHY address */
-	fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
-	if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
-			FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII)
-		fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
-	else
-		fm_info_set_phy_address(FM1_DTSEC10, RGMII_PHY2_ADDR);
-
-	switch (srds_s1) {
-	case 0x1b:
-	case 0x1c:
-	case 0x95:
-	case 0xa2:
-	case 0x94:
-		/* T2080QDS: SGMII in Slot3;  T2081QDS: SGMII in Slot2 */
-		fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
-		/* T2080QDS: SGMII in Slot2;  T2081QDS: SGMII in Slot1 */
-		fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
-		break;
-	case 0x50:
-	case 0x51:
-	case 0x5e:
-	case 0x5f:
-	case 0x64:
-	case 0x65:
-		/* T2080QDS: XAUI/HiGig in Slot3;  T2081QDS: in Slot2 */
-		fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
-		/* T2080QDS: SGMII in Slot2;  T2081QDS: in Slot3 */
-		fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
-		break;
-	case 0x66:
-	case 0x67:
-		/*
-		 * 10GBase-R does not need a PHY to work, but to avoid U-Boot
-		 * use default PHY address which is zero to a MAC when it found
-		 * a MAC has no PHY address, we give a PHY address to 10GBase-R
-		 * MAC, and should not use a real XAUI PHY address, since
-		 * MDIO can access it successfully, and then MDIO thinks
-		 * the XAUI card is used for the 10GBase-R MAC, which will cause
-		 * error.
-		 */
-		fm_info_set_phy_address(FM1_10GEC1, 4);
-		fm_info_set_phy_address(FM1_10GEC2, 5);
-		fm_info_set_phy_address(FM1_10GEC3, 6);
-		fm_info_set_phy_address(FM1_10GEC4, 7);
-		break;
-	case 0x6a:
-	case 0x6b:
-		fm_info_set_phy_address(FM1_10GEC1, 4);
-		fm_info_set_phy_address(FM1_10GEC2, 5);
-		fm_info_set_phy_address(FM1_10GEC3, 6);
-		fm_info_set_phy_address(FM1_10GEC4, 7);
-		/* T2080QDS: SGMII in Slot2;  T2081QDS: in Slot3 */
-		fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
-		break;
-	case 0x6c:
-	case 0x6d:
-		fm_info_set_phy_address(FM1_10GEC1, 4);
-		fm_info_set_phy_address(FM1_10GEC2, 5);
-		/* T2080QDS: SGMII in Slot3;  T2081QDS: in Slot2 */
-		fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
-		break;
-	case 0x70:
-	case 0x71:
-		/* SGMII in Slot3 */
-		fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
-		/* SGMII in Slot2 */
-		fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
-		break;
-	case 0xa6:
-	case 0x8e:
-	case 0x8f:
-	case 0x82:
-	case 0x83:
-		/* SGMII in Slot3 */
-		fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
-		/* SGMII in Slot2 */
-		fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
-		break;
-	case 0xa4:
-	case 0x96:
-	case 0x8a:
-		/* SGMII in Slot3 */
-		fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
-		break;
-#if defined(CONFIG_TARGET_T2080QDS)
-	case 0xd9:
-	case 0xd3:
-	case 0xcb:
-		/* SGMII in Slot3 */
-		fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
-		/* SGMII in Slot2 */
-		fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
-		break;
-#endif
-	case 0xf2:
-		/* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot7 */
-		fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
-		break;
-	default:
-		break;
-	}
-
-	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) {
-		idx = i - FM1_DTSEC1;
-		interface = fm_info_get_enet_if(i);
-		switch (interface) {
-		case PHY_INTERFACE_MODE_SGMII:
-			lane = serdes_get_first_lane(FSL_SRDS_1,
-					SGMII_FM1_DTSEC1 + idx);
-			if (lane < 0)
-				break;
-			slot = lane_to_slot[lane];
-			debug("FM1@DTSEC%u expects SGMII in slot %u\n",
-			      idx + 1, slot);
-			if (QIXIS_READ(present2) & (1 << (slot - 1)))
-				fm_disable_port(i);
-
-			switch (slot) {
-			case 1:
-				mdio_mux[i] = EMI1_SLOT1;
-				fm_info_set_mdio(i, mii_dev_for_muxval(
-						 mdio_mux[i]));
-				break;
-			case 2:
-				mdio_mux[i] = EMI1_SLOT2;
-				fm_info_set_mdio(i, mii_dev_for_muxval(
-						 mdio_mux[i]));
-				break;
-			case 3:
-				mdio_mux[i] = EMI1_SLOT3;
-				fm_info_set_mdio(i, mii_dev_for_muxval(
-						 mdio_mux[i]));
-				break;
-			}
-			break;
-		case PHY_INTERFACE_MODE_RGMII:
-		case PHY_INTERFACE_MODE_RGMII_TXID:
-		case PHY_INTERFACE_MODE_RGMII_RXID:
-		case PHY_INTERFACE_MODE_RGMII_ID:
-			if (i == FM1_DTSEC3)
-				mdio_mux[i] = EMI1_RGMII1;
-			else if (i == FM1_DTSEC4 || FM1_DTSEC10)
-				mdio_mux[i] = EMI1_RGMII2;
-			fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
-			break;
-		default:
-			break;
-		}
-	}
-
-	for (i = FM1_10GEC1; i < FM1_10GEC1 + CFG_SYS_NUM_FM1_10GEC; i++) {
-		idx = i - FM1_10GEC1;
-		switch (fm_info_get_enet_if(i)) {
-		case PHY_INTERFACE_MODE_XGMII:
-			if (srds_s1 == 0x51) {
-				lane = serdes_get_first_lane(FSL_SRDS_1,
-						XAUI_FM1_MAC9 + idx);
-			} else if ((srds_s1 == 0x5f) || (srds_s1 == 0x65)) {
-				lane = serdes_get_first_lane(FSL_SRDS_1,
-						HIGIG_FM1_MAC9 + idx);
-			} else {
-				if (i == FM1_10GEC1 || i == FM1_10GEC2)
-					lane = serdes_get_first_lane(FSL_SRDS_1,
-						XFI_FM1_MAC9 + idx);
-				else
-					lane = serdes_get_first_lane(FSL_SRDS_1,
-						XFI_FM1_MAC1 + idx);
-			}
-
-			if (lane < 0)
-				break;
-			mdio_mux[i] = EMI2;
-			fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
-
-			if ((srds_s1 == 0x66) || (srds_s1 == 0x6b) ||
-			    (srds_s1 == 0x6a) || (srds_s1 == 0x70) ||
-			    (srds_s1 == 0x6c) || (srds_s1 == 0x6d) ||
-			    (srds_s1 == 0x71)) {
-				/* As 10GBase-R is in cage intead of a slot, so
-				 * ensure doesn't disable the corresponding port
-				 */
-				break;
-			}
-
-			slot = lane_to_slot[lane];
-			if (QIXIS_READ(present2) & (1 << (slot - 1)))
-				fm_disable_port(i);
-			break;
-		default:
-			break;
-		}
-	}
-
-	cpu_eth_init(bis);
-#endif /* CONFIG_FMAN_ENET */
-
-	return pci_eth_init(bis);
-}

board/nxp/t208xqds/t208xqds.c

@@ -419,7 +419,6 @@ int ft_board_setup(void *blob, struct bd_info *bd)
 #ifndef CONFIG_DM_ETH
 	fdt_fixup_fman_ethernet(blob);
 #endif
-	fdt_fixup_board_enet(blob);
 #endif
 
 	return 0;

board/nxp/t208xqds/t208xqds.h

@@ -6,7 +6,6 @@
 #ifndef __CORENET_DS_H__
 #define __CORENET_DS_H__
 
-void fdt_fixup_board_enet(void *blob);
 void pci_of_setup(void *blob, struct bd_info *bd);
 
 #endif

board/nxp/t208xrdb/eth_t208xrdb.c

@@ -93,8 +93,3 @@ void fdt_fixup_board_phy(void *fdt)
 		printf("Unable to rename node ethernet-phy@1: %s\n",
 		       fdt_strerror(ret));
 }
-
-void fdt_fixup_board_enet(void *fdt)
-{
-	return;
-}

board/nxp/t208xrdb/t208xrdb.c

@@ -160,7 +160,6 @@ int ft_board_setup(void *blob, struct bd_info *bd)
 
 #ifdef CONFIG_SYS_DPAA_FMAN
 	fdt_fixup_board_fman_ethernet(blob);
-	fdt_fixup_board_enet(blob);
 	fdt_fixup_board_phy(blob);
 #endif
 

board/nxp/t208xrdb/t208xrdb.h

@@ -10,7 +10,6 @@
 #define CORTINA_FW_ADDR_IFCNOR				0xefe00000
 #define CORTINA_FW_ADDR_IFCNOR_ALTBANK		0xebe00000
 
-void fdt_fixup_board_enet(void *blob);
 void pci_of_setup(void *blob, struct bd_info *bd);
 void fdt_fixup_board_fman_ethernet(void *blob);
 void fdt_fixup_board_phy(void *blob);

board/nxp/t4rdb/Makefile

@@ -9,7 +9,6 @@ obj-y	+= spl.o
 else
 obj-$(CONFIG_TARGET_T4240RDB)	+= t4240rdb.o
 obj-y			+= cpld.o
-obj-y			+= eth.o
 endif
 
 obj-y	+= ddr.o

board/nxp/t4rdb/eth.c

@@ -1,152 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- *
- * Chunhe Lan <Chunhe.Lan@freescale.com>
- */
-
-#include <config.h>
-#include <command.h>
-#include <fdt_support.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/mmu.h>
-#include <asm/processor.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_law.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/fsl_serdes.h>
-#include <asm/fsl_portals.h>
-#include <asm/fsl_liodn.h>
-#include <malloc.h>
-#include <fm_eth.h>
-#include <fsl_mdio.h>
-#include <miiphy.h>
-#include <phy.h>
-#include <fsl_dtsec.h>
-#include <asm/fsl_serdes.h>
-#include <hwconfig.h>
-
-#include "../common/fman.h"
-#include "t4rdb.h"
-
-void fdt_fixup_board_enet(void *fdt)
-{
-	return;
-}
-
-int board_eth_init(struct bd_info *bis)
-{
-#if defined(CONFIG_FMAN_ENET)
-	int i, interface;
-	struct memac_mdio_info dtsec_mdio_info;
-	struct memac_mdio_info tgec_mdio_info;
-	struct mii_dev *dev;
-	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
-	u32 srds_prtcl_s1, srds_prtcl_s2;
-
-	srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
-				FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
-	srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
-	srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
-				FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
-	srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
-
-	dtsec_mdio_info.regs =
-		(struct memac_mdio_controller *)CFG_SYS_FM2_DTSEC_MDIO_ADDR;
-
-	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
-
-	/* Register the 1G MDIO bus */
-	fm_memac_mdio_init(bis, &dtsec_mdio_info);
-
-	tgec_mdio_info.regs =
-		(struct memac_mdio_controller *)CFG_SYS_FM2_TGEC_MDIO_ADDR;
-	tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
-
-	/* Register the 10G MDIO bus */
-	fm_memac_mdio_init(bis, &tgec_mdio_info);
-
-	if ((srds_prtcl_s1 == 28) || (srds_prtcl_s1 == 27)) {
-		/* SGMII */
-		fm_info_set_phy_address(FM1_DTSEC1, SGMII_PHY_ADDR1);
-		fm_info_set_phy_address(FM1_DTSEC2, SGMII_PHY_ADDR2);
-		fm_info_set_phy_address(FM1_DTSEC3, SGMII_PHY_ADDR3);
-		fm_info_set_phy_address(FM1_DTSEC4, SGMII_PHY_ADDR4);
-	} else {
-		puts("Invalid SerDes1 protocol for T4240RDB\n");
-	}
-
-	fm_disable_port(FM1_DTSEC5);
-	fm_disable_port(FM1_DTSEC6);
-
-	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) {
-		interface = fm_info_get_enet_if(i);
-		switch (interface) {
-		case PHY_INTERFACE_MODE_SGMII:
-			dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
-			fm_info_set_mdio(i, dev);
-			break;
-		default:
-			break;
-		}
-	}
-
-	for (i = FM1_10GEC1; i < FM1_10GEC1 + CFG_SYS_NUM_FM1_10GEC; i++) {
-		switch (fm_info_get_enet_if(i)) {
-		case PHY_INTERFACE_MODE_XGMII:
-			dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
-			fm_info_set_mdio(i, dev);
-			break;
-		default:
-			break;
-		}
-	}
-
-#if (CFG_SYS_NUM_FMAN == 2)
-	if ((srds_prtcl_s2 == 56) || (srds_prtcl_s2 == 55)) {
-		/* SGMII && 10GBase-R */
-		fm_info_set_phy_address(FM2_DTSEC1, SGMII_PHY_ADDR5);
-		fm_info_set_phy_address(FM2_DTSEC2, SGMII_PHY_ADDR6);
-		fm_info_set_phy_address(FM2_DTSEC3, SGMII_PHY_ADDR7);
-		fm_info_set_phy_address(FM2_DTSEC4, SGMII_PHY_ADDR8);
-		fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
-		fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR);
-		fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC2_PHY_ADDR);
-		fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC1_PHY_ADDR);
-	} else {
-		puts("Invalid SerDes2 protocol for T4240RDB\n");
-	}
-
-	fm_disable_port(FM2_DTSEC5);
-	fm_disable_port(FM2_DTSEC6);
-	for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CFG_SYS_NUM_FM2_DTSEC; i++) {
-		interface = fm_info_get_enet_if(i);
-		switch (interface) {
-		case PHY_INTERFACE_MODE_SGMII:
-			dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
-			fm_info_set_mdio(i, dev);
-			break;
-		default:
-			break;
-		}
-	}
-
-	for (i = FM2_10GEC1; i < FM2_10GEC1 + CFG_SYS_NUM_FM2_10GEC; i++) {
-		switch (fm_info_get_enet_if(i)) {
-		case PHY_INTERFACE_MODE_XGMII:
-			dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
-			fm_info_set_mdio(i, dev);
-			break;
-		default:
-			break;
-		}
-	}
-#endif /* CFG_SYS_NUM_FMAN */
-
-	cpu_eth_init(bis);
-#endif /* CONFIG_FMAN_ENET */
-
-	return pci_eth_init(bis);
-}

board/nxp/t4rdb/t4240rdb.c

@@ -128,7 +128,6 @@ int ft_board_setup(void *blob, struct bd_info *bd)
 #ifndef CONFIG_DM_ETH
 	fdt_fixup_fman_ethernet(blob);
 #endif
-	fdt_fixup_board_enet(blob);
 #endif
 
 	return 0;

board/nxp/t4rdb/t4rdb.h

@@ -14,7 +14,6 @@
 #define CORTINA_FW_ADDR_IFCNOR				0xefe00000
 #define CORTINA_FW_ADDR_IFCNOR_ALTBANK		0xebf00000
 
-void fdt_fixup_board_enet(void *blob);
 void pci_of_setup(void *blob, struct bd_info *bd);
 
 #endif