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Author SHA1 Message Date
Tom Rini
31af00bdc6 Merge tag 'net-next-20260603' of https://source.denx.de/u-boot/custodians/u-boot-net into next
Pull request net-next-20260603

- eth, phy: Convert several drivers to use the dev APIs
- Guard SYS_RX_ETH_BUFFER with NET
- phy: Kconfig: use bool instead of tristate
2026-06-03 10:49:11 -06:00
Tom Rini
e255cf65a9 Merge branch 'next' of git://source.denx.de/u-boot-usb into next
- Add "static" and "const" keywords to structs where they are missing
  and would be useful to have in the DWC3 framework.
2026-06-03 10:48:46 -06:00
Peng Fan
dafa6a3603 net: mvpp2: convert FDT access to ofnode API
Convert mvpp2 driver from legacy fdtdec/fdt_* APIs to the ofnode-based
interfaces.

Replace usage of dev_of_offset(), fdtdec_lookup_phandle(),
fdtdec_get_int(), fdt_parent_offset(), and related helpers with their
ofnode equivalents, including dev_ofnode(), ofnode_parse_phandle(),
ofnode_read_s32_default(), ofnode_get_parent(), and
ofnode_for_each_subnode().

Remove direct dependencies on gd->fdt_blob.

Main changes:
- Use ofnode_valid() instead of integer checks for node presence
- Switch fixed-link detection to ofnode_find_subnode()
- Replace uclass_get_device_by_of_offset() with
  uclass_get_device_by_ofnode()
- Update subnode iteration and device binding to use ofnode

No functional changes.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-06-03 16:55:55 +02:00
Peng Fan
f603d10d72 net: mvpp2: Use dev_read_addr_index_ptr()
Use dev_read_addr_index_ptr() which supports both live device tree and
flat DT backends, avoiding direct dependency on devfdt_* helpers.

No functional changes.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-06-03 16:55:55 +02:00
Peng Fan
23532fcb7d net: dc2114x: Use dev_remap_addr()
Use dev_remap_addr() to simplify code.

dev_remap_addr() does same thing as dev_read_addr() + map_physmem(). And
it supports both live device tree and flat DT backends, avoiding direct
dependency on devfdt_* helpers.

No functional changes.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-06-03 16:55:55 +02:00
Peng Fan
0e2ba59bc5 net: calxedaxgmac: Use dev_read_addr()
Use dev_read_addr() which supports both live device tree and flat DT
backends, avoiding direct dependency on devfdt_* helpers.

No functional changes.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-06-03 16:55:55 +02:00
Peng Fan
c174c1f7f1 net: qe: dm_qe_uec: Use dev_read_addr()
Use dev_read_addr() which supports both live device tree and flat DT
backends, avoiding direct dependency on devfdt_* helpers.

No functional changes.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Heiko Schocher <hs@nabladev.com>
2026-06-03 16:55:55 +02:00
Peng Fan
45e5625d71 net: ethoc: Use dev_read_addr_index()
Use dev_read_addr_index() which supports both live device tree and flat DT
backends, avoiding direct dependency on devfdt_* helpers.

No functional changes.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-06-03 16:55:55 +02:00
Peng Fan
b9469df60e phy: cadence: Use device API
Use dev_remap_addr_index() and dev_read_addr_size_index() which support
both live device tree and flat DT backends, avoiding direct dependency on
devfdt_* helpers.

No functional changes.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Stefan Roese <stefan.roese@mailbox.org>
2026-06-03 16:55:55 +02:00
Peng Fan
dde8b3b7e1 phy: marvell: comphy: Use dev_read_addr_index_ptr()
Use dev_read_addr_index_ptr() which supports both live device tree and flat
DT backends, avoiding direct dependency on devfdt_* helpers.

No functional changes.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Stefan Roese <stefan.roese@mailbox.org>
2026-06-03 16:55:55 +02:00
Peng Fan
6184a9b106 phy: ti-pipe3: Use device API for DT parsing
Replace legacy FDT parsing in get_reg() with the device API
dev_read_phandle_with_args() which removes direct access to gd->fdt_blob
and aligns the driver with modern U-Boot DT handling.

The offset is retrieved from the phandle argument instead of manually
parsing the property cells. Add validation for the argument
count to avoid out-of-bounds access on malformed DTs.

Also switch from devfdt_get_addr_size_index() to dev_read_addr_size_index()
for consistency with the DM API.

No functional changes.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Stefan Roese <stefan.roese@mailbox.org>
2026-06-03 16:55:55 +02:00
David Lechner
3518bf17ba phy: Kconfig: use bool instead of tristate
Change all uses of tristate in the PHY Kconfigs to bool. U-Boot does
not support modules, so tristate does not make sense here.

Signed-off-by: David Lechner <dlechner@baylibre.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Macpaul Lin <macpaul.lin@mediatek.com>
Reviewed-by: Anshul Dalal <anshuld@ti.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
2026-06-03 16:55:55 +02:00
Quentin Schulz
d172512690 net: SYS_RX_ETH_BUFFER defaults to 8 when CONFIG_FSL_ENETC=y
drivers/net/fsl_enetc.h specifies ENETC_BD_CNT "buffer descriptors count
must be a multiple of 8". This constant is set to
CONFIG_SYS_RX_ETH_BUFFER which defaults to 4.

All defconfigs enabling CONFIG_FSL_ENETC fortunately have it set to 8,
according to
./tools/qconfig.py -l -f CONFIG_FSL_ENETC '~CONFIG_SYS_RX_ETH_BUFFER=8'.

Let's make sure the default is sane by having it set to 8 when this
driver is enabled. Note that originally[1] it was said EEPRO100 and 405
EMAC should be 8 or higher. 405 (PPC405?) support seems to have been
dropped in commit b5e7c84f72 ("ppc4xx: remove ASH405 board"), 11 years
ago. Maybe there's something we can do for EEPRO100 though?

Start all lines with a tab instead of spaces.

Specify limitation for FSL_ENETC in the help text.

[1] commit 53cf9435cc ("- CFG_RX_ETH_BUFFER added.")
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
2026-06-03 16:55:55 +02:00
Quentin Schulz
77cc22b809 net: guard SYS_RX_ETH_BUFFER with NET
SYS_RX_ETH_BUFFER represents the number of Ethernet receive packet
buffers. It therefore doesn't make sense it's reachable if NET isn't
enabled.

Direct users of SYS_RX_ETH_BUFFER are:
- drivers/net/rtl8169.c, only compiled if CONFIG_RTL8169=y, depends on
  CONFIG_NETDEVICES=y, depends on CONFIG_NET=y,
- drivers/net/fsl_enetc.h, via ENETC_BD_CNT, included in
    drivers/net/{fsl_enetc.c,fsl_enetc_mdio.c,mscc_eswitch/felix_switch.c}
  First two only compiled if CONFIG_FSL_ENETC=y, latter with
  CONFIG_MSCC_FELIX_SWITCH=y. Both symbols depends on
  CONFIG_NETDEVICES=y, depends on CONFIG_NET=y.
- include/net-common.h via PKTBUFSRX,

Indirect users via PKTBUFSRX:
- arch/sandbox/include/asm/eth.h
  - according to ./tools/qconfig.py -l -f CONFIG_SANDBOX CONFIG_NO_NET,
    all sandbox defconfigs have network enabled so ignore this for now,
- drivers/dma/ti/k3-udma.c
  - sets UDMA_RX_DESC_NUM to that if defined, else 4. PKTBUFSRX is
    CONFIG_SYS_RX_ETH_BUFFER which defaults to 4. According to
    ./tools/qconfig.py -l -f CONFIG_TI_K3_NAVSS_UDMA '~CONFIG_SYS_RX_ETH_BUFFER=4'
    no defconfig enabling this DMA driver sets CONFIG_SYS_RX_ETH_BUFFER
    to anything but the default of 4, so regardless of NET being built
    UDMA_RX_DESC_NUM will always be 4 with current defconfigs.
- drivers/net/{airoha_eth.c,bcm6348-eth.c,bcm6368-eth.c,cortina_ni.c,
	dc2114x.c,eepro100.c,essedma.c,ethoc.c,ftgmac100.c,ftmac100.c,
	hifemac.c,mcffec.c,mpc8xx_fec.c,pic32_eth.c,sandbox.c,sni_ave.c,
	sni_netsec.c,ti/am65-cpsw-nuss.c,ti/cpsw.c,ti/icssg_prueth.c,
	tsec.c} all depends on CONFIG_NETDEVICES=y, depends on
  CONFIG_NET=y,
- net/lwip/net-lwip.c, only compiled if CONFIG_NET_LWIP=y, depends on
  CONFIG_NET=y,
- net/{net.c,tcp.c}, only compiled if CONFIG_NET_LEGACY=y, depends on
  CONFIG_NET=y,
- net/net-common.c, only compiled if CONFIG_NET=y,
- test/cmd/wget.c, only compiled if CONFIG_NET_LEGACY=y, depends on
  CONFIG_NET=y,
- test/image/spl_load_net.c, only compiled if CONFIG_SPL_UT_LOAD_NET=y,
  depends on CONFIG_SPL_ETH=y, depends on CONFIG_SPL_NET=y, depends on
  CONFIG_NET_LEGACY=y, depends on CONFIG_NET=y,

Indirect users via net_rx_packets[PKTBUFSRX]. This array is only
externally defined in net/net-common.c which is only compiled if
CONFIG_NET=y.

Users of net_rx_packets are:
- drivers/net/{airoha_eth.c,bcm6348-eth.c,bcm6368-eth.c,cortina_ni.c,
	dc2114x.c,dm9000x.c,essedma.c,ethoc.c,fsl_enetc.c,ftgmac100.c,
	ftmac100.c,hifemac.c,ks8851_mll.c,macb.c,mcffec.c,mpc8xx_fec.c,
        mscc_eswitch/jr2_switch.c,mscc_eswitch/luton_switch.c,
        mscc_eswitch/ocelot_switch.c,mscc_eswitch/serval_switch.c,
        mscc_eswitch/servalt_switch.c,pic32_eth.c,sandbox-raw.c,
	sandbox.c,smc911x.c,sni_ave.c,sni_netsec.c,ti/am65-cpsw-nuss.c,
	ti/cpsw.c,ti/icssg_prueth.c,tsec.c,xilinx_axi_mrmac.c} all
	depends on CONFIG_NETDEVICES=y, depends on CONFIG_NET=y,
- drivers/usb/gadget/ether.c only built if CONFIG_$(PHASE_)USB_ETHER=y,
  depends on CONFIG_NET=y/CONFIG_SPL_NET=y,
- net/lwip/net-lwip.c only compiled if CONFIG_NET_LWIP=y, depends on
  CONFIG_NET=y,
- net/net.c, only compiled if CONFIG_NET_LEGACY=y, depends on
  CONFIG_NET=y,
- net/net-common.c, only compiled if CONFIG_NET=y,

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
2026-06-03 16:55:55 +02:00
Quentin Schulz
987b5eabc3 net: tsec: make tsec_private a private structure
Move the definition of tsec_private within the only file that makes use
of it.

This adds the benefit of include/tsec.h not referencing PKTBUFSRX (which
is set to CONFIG_SYS_RX_ETH_BUFFER, which we're trying to move to be
under CONFIG_NET dependency) anymore. Considering drivers/net/tsec.c is
only built if CONFIG_NET=y, this is fine.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
2026-06-03 16:55:55 +02:00
Quentin Schulz
4cbd0faab8 arm: ls102xa: use platform data to check Ethernet interface is not SGMII
tsec_private should, as its name suggests, be private. In the next
commit, it'll be moved from a publicly available header file to the C
file that requires it. ls102xa currently does not allow us to do that
because it uses the structure.

The flag is actually set if the Ethernet PHY interface is SGMII in
drivers/net/tsec.c, so simply replace the current check with the same
check made in drivers/net/tsec.c to set the flag.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
2026-06-03 16:55:55 +02:00
Quentin Schulz
081ffe9b3f ls1028a: only include drivers/net/fsl_enetc.h when driver is compiled
As hinted by its path, it's not really meant to be included outside of
the driver itself. This header uses CONFIG_SYS_RX_ETH_BUFFER which we
are trying to move under CONFIG_NET dependency. This file here can be
compiled without network support so make sure this only gets included
when needed.

The function from that header (fdt_fixup_enetc_mac) is already guarded
by CONFIG_FSL_ENETC so simply guard the inclusion of the header the same
way.

This was tested by building ls1028aqds_tfa_defconfig with
CONFIG_MSCC_FELIX_SWITCH and CONFIG_FSL_ENETC disabled.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
2026-06-03 16:55:55 +02:00
Marek Vasut
2e9e891561 usb: dwc3: generic: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
2026-06-03 02:00:59 +02:00
Marek Vasut
f0dccb21eb usb: dwc3: sti: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
2026-06-03 02:00:59 +02:00
Marek Vasut
d86b3a753f usb: dwc3: am62: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
2026-06-03 02:00:59 +02:00
Tom Rini
4674475760 Merge patch series "Enable splashscreen functionality on AM62X"
Swamil Jain <s-jain1@ti.com> says:

This patch series introduces splashscreen support for
AM62x platforms by adding configuration fragments and implementing
selective splashscreen enablement across different boot configurations.

The series adds two configuration fragments: am62x_a53_splashscreen.config
and am62x_evm_prune_splashscreen.config. These fragments allow platforms
to selectively enable or disable splashscreen functionality based on
their specific requirements. The prune fragment is particularly useful
for platforms like AM62P where splashscreen must be disabled when using
TI-DM firmware with display sharing features.

The series enables splashscreen on AM62X.

Link: https://lore.kernel.org/r/20260519141716.1346635-1-s-jain1@ti.com
2026-06-02 13:49:16 -06:00
Swamil Jain
abd948e542 configs: am62x_evm_a53_defconfig: Enable A53 splashscreen at u-boot SPL
Enable A53 splashscreen at u-boot SPL stage. SPL_MAX_SIZE is bumped up
to 0x80000 to accommodate splash related code. Include
splashscreen.config to enable splashscreen.

Signed-off-by: Swamil Jain <s-jain1@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
2026-06-02 13:49:16 -06:00
Swamil Jain
83f3e2c30b configs: am62x_evm_a53_ethboot_defconfig: Disable splashscreen
The ethboot configuration inherits splashscreen settings from
am62x_evm_a53_defconfig. Use the prune fragment to disable this
functionality as a baseline before adding targeted splashscreen support
in follow-up commits.

Signed-off-by: Swamil Jain <s-jain1@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
2026-06-02 13:49:16 -06:00
Devarsh Thakkar
e853b26d0c configs: am62x: Add splashscreen prune config fragment
Add config fragment to disable splashscreen. This is especially useful
for platforms such as AM62P as splash needs to be disabled while using
TI-DM firmware with display sharing feature enabled.

Signed-off-by: Devarsh Thakkar <devarsht@ti.com>
Signed-off-by: Swamil Jain <s-jain1@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
2026-06-02 13:49:16 -06:00
Devarsh Thakkar
6c164d51d6 configs: am62x: Add splashscreen config fragment
Add config fragment to enable splashscreen functionality for AM62x
platforms. This fragment can be included by defconfigs that require
splashscreen support.

Signed-off-by: Devarsh Thakkar <devarsht@ti.com>
Signed-off-by: Swamil Jain <s-jain1@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
2026-06-02 13:49:16 -06:00
Francois Berder
9c04852e59 timer: sp804: Fix dev_read_addr error check
dev_read_addr returns FDT_ADDR_T_NONE (-1) in case of error
and not 0.

Signed-off-by: Francois Berder <fberder@outlook.fr>
2026-06-02 13:47:48 -06:00
Tom Rini
b5f2880261 Merge patch series "Clean up bloblist initialization"
Tom Rini <trini@konsulko.com> says:

This series does a few small but important cleanups to how we check for,
and initialize a bloblist. The first thing is that the way things are
done today, our HANDOFF code can only work with a fixed bloblist
location, so express that requirement in Kconfig. Next, we demote the
scary message about "Bloblist at ... not found" to a debug because we
most often see that because the bloblist doesn't (and can't) exist yet.
Finally, we remove bloblist_maybe_init and split this in to an exists
and a real init. This results in practically no growth (between 8 bytes
growth to 12 bytes saved, with some outliers saving much more thanks to
knowing it's impossible to have been passed a bloblist yet). This also
cleans up some of the code around checking for / knowing about a
bloblist existing.

Link: https://lore.kernel.org/r/20260519162225.770071-1-trini@konsulko.com
2026-06-02 09:30:33 -06:00
Tom Rini
5ab1600213 bloblist: Rework bloblist_init and bloblist_maybe_init
With bloblist, we need to both see if one already exists as well as
create one if it does not. However, the current implementation leads to
odd cases where we attempt to create a bloblist before this is possible
and have things be overly complicated when we are given one to work
with.

This reworks things to instead have a bloblist_exists function, which as
the name implies checks for an existing bloblist. This is used in
the case of booting, to see if we have one and in turn if we have a
device tree there as well as in the bloblist_init function to see if we
need to do anything.

In practical details, we move the logic from bloblist_init that was
checking for a bloblist to the new bloblist_exists function and then can
clarify the logic as it is much easier to state when we know we do not
have one rather than all the ways we might have one. Then we have the
locations that set gd->bloblist now also set the GD_FLG_BLOBLIST_READY
flag.

Reviewed-by: Raymond Mao <raymondmaoca@gmail.com>
Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2026-06-02 09:30:28 -06:00
Tom Rini
b4858d2afc bloblist: Demote not finding a bloblist to a debug
The message about not finding a bloblist will quite often be seen at
least once, and is non-fatal. Demote this to a log_debug message from a
log_warning message.

Reviewed-by: Raymond Mao <raymondmaoca@gmail.com>
Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2026-06-02 09:30:28 -06:00
Tom Rini
679eb25fb8 bloblist / handoff: Make this depend on BLOBLIST_FIXED
Currently, the only way we support passing a bloblist from one stage to
the next is via the BLOBLIST_FIXED mechanism. Update the Kconfig logic
to express this constraint.

Reviewed-by: Raymond Mao <raymondmaoca@gmail.com>
Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2026-06-02 09:30:28 -06:00
Tom Rini
0a46055d96 Merge patch series "video: bridge: anx6345: Staticize and constify driver ops"
This series from Marek Vasut <marek.vasut+renesas@mailbox.org> adds
"static" and "const" keywords to structs where they are missing and
would be useful to have.

Link: https://lore.kernel.org/r/20260510171723.56866-1-marek.vasut+renesas@mailbox.org
2026-05-30 07:44:08 -06:00
Alexey Charkov
5cf4b14284 video console: add 6x8 console font from linux
Small screens on the order of 256x144 pixels can't fit much text at 8x16,
and 4x6 is virtually illegible, so add an in-between 6x8 font from Linux.

Font data obtained from lib/fonts/font_6x8.c in the Linux kernel at commit
db65872b38dc ("lib/fonts: Remove internal symbols and macros from public
header file")

Link: db65872b38/lib/fonts/font_6x8.c
Signed-off-by: Alexey Charkov <alchark@flipper.net>
2026-05-30 07:44:08 -06:00
Dario Binacchi
5f5b8ae293 video: kconfig: replace tristate with bool for LCD panel drivers
U-Boot does not support loadable modules, therefore using 'tristate'
in Kconfig is incorrect since the 'm' option cannot be selected.

Replace tristate with bool for the affected LCD panel drivers to
reflect the U-Boot build model and avoid misleading configuration
options.

No functional change intended.

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Svyatoslav Ryhel <clamor95@gmail.com>
2026-05-30 07:44:08 -06:00
Dario Binacchi
2be4b2269e video: Kconfig: fix indentation of help text
Fix the indentation of the help text for VIDEO_LCD_NOVATEK_NT35510 and
VIDEO_LCD_ORISETECH_OTM8009A to align with the standard Kconfig format.

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2026-05-30 07:44:08 -06:00
Aelin Reidel
258310ab39 video: simplefb: Parse memory region from memory-region property
Linux' simplefb driver allows setting the memory-region property to a
phandle to a node that describes the memory to be used for the
framebuffer. If it is present, it will override the "reg" property.

This adds support for parsing the property and prefers it if present.

Signed-off-by: Aelin Reidel <aelin@mainlining.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2026-05-30 07:44:08 -06:00
Luca Weiss
1c8b592611 video: simplefb: Map framebuffer region on probe on ARM64
The framebuffer buffer might not be mapped on some devices.

This is #ifdef'ed for ARM64 since mmu_map_region() is not defined for
any other architecture.

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Acked-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
2026-05-30 07:44:08 -06:00
Tom Rini
df08b27590 video: Correct dependencies for VIDEO_TIDSS
The VIDEO_TIDSS functionality can only work with PANEL enabled, so
express this dependency in Kconfig for all phases.

Signed-off-by: Tom Rini <trini@konsulko.com>
2026-05-30 07:44:08 -06:00
Tom Rini
ff3bece92f video: Correct dependencies for VIDEO_LCD_RAYDIUM_RM68200
The VIDEO_LCD_RAYDIUM_RM68200 functionality can only work with BACKLIGHT
enabled, so express this dependency in Kconfig.

Signed-off-by: Tom Rini <trini@konsulko.com>
2026-05-30 07:44:08 -06:00
Tom Rini
6033096d3c video: Correct dependencies of LOGICORE_DP_TX
In order to build LOGICORE_DP_TX we must also have enabled AXI, so add
that as a dependency as well.

Signed-off-by: Tom Rini <trini@konsulko.com>
2026-05-30 07:44:08 -06:00
Anshul Dalal
3c32572a27 common: splash_source: fix cryptic error messages
Some error messages emitted while loading the splash image are too
cryptic and don't provide any insights into the failure being a splash
related issue, such as 'Error (-2): cannot determine file size' etc.

This patch fixes the error codes by adding the function name to the
error print.

Signed-off-by: Anshul Dalal <anshuld@ti.com>
[trini: Add missing ',' and wrap to 80-width]
Signed-off-by: Tom Rini <trini@konsulko.com>
2026-05-30 07:43:41 -06:00
Marek Vasut
674afbcf6e video: tegra: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2026-05-29 17:10:46 -06:00
Marek Vasut
16185d7ff3 video: tda19988: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2026-05-29 17:10:46 -06:00
Marek Vasut
dd2f4d967f video: stm32: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Raphaël Gallais-Pou <rgallaispou@gmail.com>
2026-05-29 17:10:46 -06:00
Marek Vasut
7e7b3106a5 video: imx: ldb: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2026-05-29 17:10:46 -06:00
Marek Vasut
b2f7404fd8 video: dw_mipi_dsi: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2026-05-29 17:10:46 -06:00
Marek Vasut
8f7717c756 video: console: truetype: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2026-05-29 17:10:46 -06:00
Marek Vasut
c6266daa1e video: console: rotate: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2026-05-29 17:10:46 -06:00
Marek Vasut
3ddd78074e video: console: normal: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2026-05-29 17:10:46 -06:00
Marek Vasut
772ef8b089 video: bridge: ptn3460: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2026-05-29 17:10:46 -06:00
Marek Vasut
af65e247e7 video: bridge: ps862x: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2026-05-29 17:10:46 -06:00
Marek Vasut
6da8ecc518 video: bridge: anx6345: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2026-05-29 17:10:46 -06:00
Francois Berder
c39e0e257c boot: cedit: Check ofnode_read_prop return value
In h_read_settings, val variable could be NULL due to
ofnode_read_prop returning an error. This variable
would then be used as the src in strcpy.

Add a NULL check after calling ofnode_read_prop.

Signed-off-by: Francois Berder <fberder@outlook.fr>
Reviewed-by: Simon Glass <sjg@chromium.org>
2026-05-29 14:23:11 -06:00
Tom Rini
9f00cec3d8 Merge patch series "board: phytec: Update rm-cfgs, env and docs"
Wadim Egorov <w.egorov@phytec.de> says:

This is a small updates across all K3 based phytec SoMs.
Update docs, rm-cfg yaml files and drop rauc environment.

Link: https://lore.kernel.org/r/20260513071905.83522-1-w.egorov@phytec.de
2026-05-29 14:23:01 -06:00
Wadim Egorov
6e8d82b9e9 doc: board: phytec: Document DDR size override Kconfigs
The phyCORE-AM62x and phyCORE-AM64x R5 SPL detects the populated DDR
size from the SoM EEPROM and falls back to 2 GB if detection fails. For
boards without a populated EEPROM or if no detection needed, the detection
can be bypassed via CONFIG_PHYCORE_AM6{2,4}X_RAM_SIZE_FIX and one of
the CONFIG_PHYCORE_AM6{2,4}X_RAM_SIZE_<size> choices.

Add a "DDR RAM Size" section to both board docs describing this
behaviour and listing the available size options (1/2/4 GB for AM62x,
1/2 GB for AM64x).

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
2026-05-29 14:22:38 -06:00
Wadim Egorov
14ba26ebdd doc: board: phytec: k3: Document boot flow and watchdog
Add two short sections to the common K3 phyCORE docs.
Describe the default boot flow and its deprecated version.
And write down the use of the watchdog.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
2026-05-29 14:22:38 -06:00
Wadim Egorov
86f4f05ad8 doc: board: phytec: Fix typos and copy-paste errors in K3 docs
A handful of small inaccuracies had crept into the phyCORE-AM6x docs.
Mostly typos and formatting Issues. Fix them. While at it, update the
am62a board to use the correct product link.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
2026-05-29 14:22:38 -06:00
Wadim Egorov
ef5b4a7eae include: env: phytec: Drop legacy RAUC boot logic
RAUC slot selection is now handled by the RAUC bootmeth, which all
phytec K3 boards use. Remove the unused env-based logic.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Reviewed-by: Martin Schwan <m.schwan@phytec.de>
2026-05-29 14:22:38 -06:00
Wadim Egorov
68532aab6d board: phytec: phycore_am68x: Update rm-cfg
Mirror the j721s2 changes from commit c4fcf9b806 ("board: ti: j7*:
Update rm-cfg and tifs-rm-cfg") to repurpose allocated resources with
version V11.02.07 of k3-resource-partition.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Acked-by: Dominik Haller <d.haller@phytec.de>
2026-05-29 14:22:38 -06:00
Wadim Egorov
c2edb9cb2b arm: dts: k3-am625-phycore-som-binman: Enable tifs-rm-cfg
Add rcfg_yaml_tifs node override to use tifs-rm-cfg.yaml instead of
the default rm-cfg.yaml for the phyCORE-AM62x SoM.

This enables binman to include the tifs-rm-cfg.yaml configuration
when building tiboot3 images, bringing the phyCORE-AM62x SoM in line
with other K3 devices that already use tifs-rm-cfg.yaml.

This builds on the tifs-rm-cfg file added earlier in this series.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
2026-05-29 14:22:38 -06:00
Wadim Egorov
6edb2e1ce2 board: phytec: phycore_am62x: Add tifs-rm-cfg
Add a separate tifs-rm-cfg.yaml so the TIFS bundle uses the trimmed
TIFS view instead of reusing rm-cfg.yaml, matching the rest of the
AM62 boards.

Mirrors commit 964bda9e80 ("board: ti: am62x: tifs-rm-cfg: Add the
missing tifs-rm-cfg:") for the phyCORE-AM62x SoM.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
2026-05-29 14:22:38 -06:00
Tom Rini
b40fee4d6d Merge patch series "board: toradex: k3: Sync rm-cfg with TIFS v12.00.00 firmware"
Ernest Van Hoecke <ernestvanhoecke@gmail.com> says:

This series updates the Resource Management configuration for Toradex
K3-based boards and makes sure the TIFS-specific RM configuration is
used where applicable.

For Verdin AM62P, the tifs-rm-cfg.yaml file is refreshed with
k3-resource-partition V12.00.00 so that it stays in sync with the
existing rm-cfg.yaml update for the v11.02.09 and v12.00.00 TIFS
firmware resource reservation.

For Verdin AM62, the missing tifs-rm-cfg.yaml file is added. The file
matches the TI AM62x configuration, and rm-cfg.yaml was verified to
remain unchanged when regenerated with the same tool version.

For Aquila AM69, both rm-cfg.yaml and tifs-rm-cfg.yaml are updated to
match the resource allocation changes already present in the TI J784S4
configuration files.

Finally, the Verdin AM62 and Verdin AM62P binman descriptions are
updated to use tifs-rm-cfg.yaml for the TIFS RM fragment when building
tiboot3 images, following the same pattern used by the corresponding TI
AM62x/AM62Px platforms.

The generated/updated files were compared against the matching TI board
configuration files where applicable.

Link: https://lore.kernel.org/r/20260508-v1-update-rm-cfg-v1-0-ec9d033f8ec1@toradex.com
2026-05-29 14:22:20 -06:00
Ernest Van Hoecke
927e4880f2 arm: dts: k3: k3-am62*5-verdin-binman: Enable tifs-rm-cfg in binman
Add rcfg_yaml_tifs node overrides to use tifs-rm-cfg.yaml instead of
the default rm-cfg.yaml for Verdin AM62 and Verdin AM62P platforms.

This enables binman to include the tifs-rm-cfg.yaml configuration when
building tiboot3 images in line with other K3 devices that already use
tifs-rm-cfg.yaml.

This follows the changes done by TI to their am62x/am62px platforms. [1]

[1] commit 41814276f0 ("arm: dts: k3: am62x/am62px: Enable tifs-rm-cfg in binman")

Signed-off-by: Ernest Van Hoecke <ernest.vanhoecke@toradex.com>
Acked-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
2026-05-29 14:22:00 -06:00
Ernest Van Hoecke
78dff83dd7 board: toradex: aquila-am69: update rm-cfg.yaml and tifs-rm-cfg.yaml
Repurpose the allocated resources with version V12.00.00 of
k3-resource-partition, matching the update made for the TI J784S4
configuration files. [1]

The Aquila AM69 rm-cfg.yaml and tifs-rm-cfg.yaml remain aligned with
board/ti/j784s4/*-rm-cfg.yaml.

[1] commit c4fcf9b806 ("board: ti: j7*: Update rm-cfg and tifs-rm-cfg")

Signed-off-by: Ernest Van Hoecke <ernest.vanhoecke@toradex.com>
Acked-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
2026-05-29 14:22:00 -06:00
Ernest Van Hoecke
4fd5302675 board: toradex: verdin-am62: add missing tifs-rm-cfg.yaml
Add the previously missing TIFS RM configuration, generated with
V12.00.00 of k3-resource-partition.

This file is exactly the same as board/ti/am62x/tifs-rm-cfg.yaml.

rm-cfg.yaml and tifs-rm-cfg.yaml need to be in sync, this was already
taken care of by TI. [1]

It was verified that rm-cfg.yaml also remained unchanged with V12.00.00
of the tool.

[1] commit 64ebab10b5 ("toradex: verdin-am62: rm-cfg: Update rm-cfg to reflect new resource reservation")

Signed-off-by: Ernest Van Hoecke <ernest.vanhoecke@toradex.com>
Acked-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
2026-05-29 14:22:00 -06:00
Ernest Van Hoecke
7920dc90dd board: toradex: verdin-am62p: update tifs-rm-cfg
TI updated rm-cfg for v11.02.09 of the TIFS firmware. [1]

Refresh the tifs-rm-cfg.yaml as well, with version V12.00.00 of
k3-resource-partition, so that it remains in sync with rm-cfg.yaml.

rm-cfg.yaml was also updated with V12.00.00 of the tool and noted to
have no changes.

[1] commit a66704e9a1 ("board: toradex: verdin-am62p: rm-cfg: Update rm-cfg to reflect new resource reservation")

Signed-off-by: Ernest Van Hoecke <ernest.vanhoecke@toradex.com>
Acked-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
2026-05-29 14:22:00 -06:00
Abhash Kumar Jha
59d52a9975 board: ti: j722s: add processor ACL entry for wkup_r5
On the j722s platform, the DM firmware resets the wkup_r5 core at boot to
enable both of its TCM memories.

This reset sequence involves three steps:
- Acquiring processor ownership of wkup_r5
- Configuring the core and requesting a reset via TIFS
- Releasing ownership.

When the Linux remoteproc driver comes up, it acquires ownership of wkup_r5
to query its state, making A53_2 the new owner.
During system suspend, TIFS saves the processor ACL[1] table to DDR as
part of its context.

On resume, TIFS restores the ACL table, leaving A53_2 as the owner of
wkup_r5. At this point, DM (WKUP_0_R5_0 host[2]) no longer has ownership
and is therefore unable to perform the reset sequence it needs,
causing it to crash.

To fix this, configure the wkup_r5[3] processor with dual ownership:
- WKUP_0_R5_0 (Secure) as primary owner.
- A53_2 (Non-Secure) as secondary owner.

[1] https://software-dl.ti.com/tisci/esd/latest/3_boardcfg/BOARDCFG_SEC.html#pub-boardcfg-proc-acl
[2] https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/j722s/hosts.html
[3] https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/j722s/processors.html

Signed-off-by: Abhash Kumar Jha <a-kumar2@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
2026-05-29 14:17:14 -06:00
Tom Rini
ddd1f2192d Merge patch series "Update envs to use Kconfig values"
Anshul Dalal <anshuld@ti.com> says:

Some minor fixes to K3's env to avoid using hardcoded addresses but
instead move to Kconfig symbols.

Link: https://lore.kernel.org/r/20260518-env_to_kconfig_migration-v1-0-24c8fba75ad3@ti.com
2026-05-29 14:04:00 -06:00
Anshul Dalal
1ea8b3e8e2 env: ti: k3_dfu: use Kconfig options for addresses
The load addresses for DFU download binaries were hardcoded for K3
devices which required redefinition of such env for boards that deviated
from the expected K3 memory map (such as AM6254atl EMV).

This patch replaces the hardcoded addresses with their corresponding
Kconfig options making the k3_dfu.env more general.

Signed-off-by: Anshul Dalal <anshuld@ti.com>
2026-05-29 14:02:18 -06:00
Anshul Dalal
2b6d243be2 env: ti: k3_dfu: load only the next stage binary
In the TI's K3 bootflow of tiboot3.bin -> tispl.bin -> u-boot.img:
                             (R5 SPL)      (A53 SPL)

We currently provide a common dfu_alt_info_ram for both R5 SPL and A53
SPL which is not intuitive in a regular bootflow where each binary
should only request it's immediate next stage.

This patch updates dfu_alt_info_ram such that the R5 SPL would only
request for tispl.bin and A53 SPL would only request u-boot.img.

Signed-off-by: Anshul Dalal <anshuld@ti.com>
2026-05-29 14:02:18 -06:00
Jeremy Kerr
5151c208b5 am33xx: don't assume we have a UCLASS_MISC device present
Boot on am33xx without CONFIG_USB will currently fail, as we error-out
of arch_misc_init() if no UCLASS_MISC device is found. This requirement
was introduced in commit 3aec264869 ("am33xx: board: probe misc
drivers to register musb devices").

Instead, only attempt the UCLASS_MISC init if we would expect the MUSB
TI device to be present. Add a comment to explain why we're doing the
device lookup (which we immediately discard).

Fixes: 3aec264869 ("am33xx: board: probe misc drivers to register musb devices")
Signed-off-by: Jeremy Kerr <jk@codeconstruct.com.au>
Reviewed-by: Tom Rini <trini@konsulko.com>
2026-05-27 17:59:19 -06:00
Adam Lackorzynski
8429766a7f common/command.c: Avoid NULL pointer use in cmd_auto_complete
Avoid using ps_prompt having a NULL pointer. For that, use the same
approach as in uboot_cli_readline().

Suggested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Adam Lackorzynski <adam@l4re.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2026-05-27 17:59:16 -06:00
Heinrich Schuchardt
7af4196d9e fs: fat: fix seconds in timestamp
The FAT time format stores seconds/2 in bits 4:0. The expression
'tm.tm_sec > 1' is a boolean comparison (yields 0 or 1) where a
right-shift 'tm.tm_sec >> 1' was intended.  As a result every
file timestamp written by U-Boot has its seconds field set to
either 0 or 1, depending on whether tm_sec is greater than 1.

Also fix the indentation of the tm_hour line.

Fixes: ba23c378c5 ("fs: fat: fill creation and change date")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2026-05-27 17:59:12 -06:00
Tom Rini
746a986fe2 Merge patch series "fit: dm-verity support"
Daniel Golle <daniel@makrotopia.org> says:

This series adds dm-verity support to U-Boot's FIT image infrastructure.
It is the first logical subset of the larger OpenWrt boot method series
posted as an RFC in February 2026 [1], extracted here for independent
review and merging.

OpenWrt's firmware model embeds a read-only squashfs or erofs root
filesystem directly inside a uImage.FIT container as a FILESYSTEM-type
loadable FIT image. At boot the kernel maps this sub-image directly from
the underlying block device via the fitblk driver (/dev/fit0, /dev/fit1,
...), the goal is that the bootloader never even copies it to RAM.

dm-verity enables the kernel to verify the integrity of those mapped
filesystems at read time, with a Merkle hash tree stored contiguously in
the same sub-image just after the data. Two kernel command-line
parameters are required:

  dm-mod.create=   -- the device-mapper target table for the verity device
  dm-mod.waitfor=  -- a comma-separated list of block devices to wait for
                      before dm-init sets up the targets (needed when fitblk
                      probes late, e.g. because it depends on NVMEM
                      calibration data)

The FIT dm-verity node schema was upstreamed into the flat-image-tree
specification [2], which this implementation tries to follow exactly.

The runtime feature is guarded behind CONFIG_FIT_VERITY. If not
enabled the resulting binary size remains unchanged. If enabled the
binary size increases by about 3kB.

[1] previous submissions:
    RFC: https://www.mail-archive.com/u-boot@lists.denx.de/msg565945.html
    v1:  https://www.mail-archive.com/u-boot@lists.denx.de/msg569472.html
    v2:  https://www.mail-archive.com/u-boot@lists.denx.de/msg570599.html
    v3:  https://www.mail-archive.com/u-boot@lists.denx.de/msg573223.html
    v4:  https://www.mail-archive.com/u-boot@lists.denx.de/msg574000.html

[2] flat-image-tree dm-verity node spec:
    795fd5fd7f

Link: https://lore.kernel.org/r/cover.1778887196.git.daniel@makrotopia.org
2026-05-27 13:44:20 -06:00
Daniel Golle
89d3c1fe1b configs: sandbox: enable CONFIG_FIT_VERITY
Enable FIT_VERITY in the sandbox configs that build a full U-Boot
binary so CI may exercise the new dm-verity unit test
(test/boot/fit_verity.c) and the mkimage pytest
(test/py/tests/test_fit_verity.py) introduced earlier in this series.

The SPL/VPL/noinst variants only load U-Boot proper, never an OS, so
dm-verity is meaningless there and is not enabled.

Suggested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
2026-05-27 13:41:33 -06:00
Daniel Golle
e52b2c6e7f test: py: add mkimage dm-verity round-trip test
Add test/py/tests/test_fit_verity.py covering:
 - mkimage writes correct dm-verity properties for matched and
   mismatched block sizes (4096/4096 and 4096/1024);
 - veritysetup verify re-checks the digest against the .itb's
   external data section;
 - mkimage rejects dm-verity images built without -E.

All tests are skipped if veritysetup is not installed on the host.

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2026-05-27 13:41:33 -06:00
Daniel Golle
e7ee728ace test: boot: add runtime unit test for fit_verity_build_cmdline()
Add test/boot/fit_verity.c with four tests that construct FIT blobs
in memory and exercise fit_verity_build_cmdline().

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2026-05-27 13:41:33 -06:00
Daniel Golle
f34597790e doc: fit: add dm-verity boot parameter documentation
Add documentation for CONFIG_FIT_VERITY which allows U-Boot to
construct dm-mod.create= and dm-mod.waitfor= kernel command-line
parameters from dm-verity metadata embedded in FIT filesystem
sub-images.

The new document covers the relationship between FIT loadable indices
and the /dev/fitN block devices that the Linux uImage.FIT block driver
creates, provides a complete .its example with a dm-verity-protected
SquashFS root filesystem, describes all required and optional dm-verity
subnode properties and explains how mkimage generates the verity
metadata automatically.

dm-verity is only supported for external-data FIT images (mkimage -E);
mkimage aborts with an error if the flag is omitted.

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2026-05-27 13:41:33 -06:00
Daniel Golle
1e48298552 tools: mkimage: add dm-verity Merkle-tree generation
When mkimage encounters a dm-verity subnode inside a component image
node it now automatically invokes veritysetup(8) with --no-superblock
to generate the Merkle hash tree, screen-scrapes the Root hash and Salt
from the tool output, and writes the computed properties back into the
FIT blob.

The user only needs to specify algorithm, data-block-size, and
hash-block-size in the ITS; mkimage fills in digest, salt,
num-data-blocks, and hash-start-block. Because --no-superblock is
used, hash-start-block equals num-data-blocks with no off-by-one.

The image data property is replaced with the expanded content (original
data followed directly by the hash tree) so that subsequent hash and
signature subnodes operate on the complete image.

fit_image_add_verification_data() is restructured into two passes:
dm-verity first (may grow data), then hashes and signatures.

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2026-05-27 13:41:33 -06:00
Daniel Golle
96e180d354 include: hexdump: make hex2bin() usable from host tools
Make hexdump.h work in host-tool builds by using 'uint8_t' instead
of 'u8', and including either user-space libc <ctype.h> for host-tools
or <linux/ctype.h> when building U-Boot itself.

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2026-05-27 13:41:33 -06:00
Daniel Golle
cafe3d6e90 boot: fit: support generating DM verity cmdline parameters
Add fit_verity_build_cmdline(): when a FILESYSTEM loadable carries a
dm-verity subnode, construct the dm-mod.create= kernel cmdline parameter
from the verity metadata (block-size, data-blocks, algo, root-hash,
salt) and append it to bootargs.

Also add dm-mod.waitfor=/dev/fit0[,/dev/fitN] for each dm-verity device
so the kernel waits for the underlying FIT block device to appear before
setting up device-mapper targets. This is needed when the block driver
probes late, e.g. because it depends on NVMEM calibration data.

The dm-verity target references /dev/fitN where N is the loadable's
index in the configuration -- matching the order Linux's FIT block
driver assigns block devices.  hash-start-block is read directly from
the FIT dm-verity node; mkimage ensures its value equals num-data-blocks
by invoking veritysetup with --no-superblock.

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2026-05-27 13:41:33 -06:00
Daniel Golle
d3eee4d3b1 image: fit: add dm-verity property name constants
Add FIT_VERITY_NODENAME and the complete set of FIT_VERITY_*_PROP
constants for the dm-verity child node of filesystem-type images, plus
the five optional boolean error-handling property names aligned with the
flat-image-tree specification.

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2026-05-27 13:41:33 -06:00
Tom Rini
8d5f30b52f Merge patch series "env: migrate static flags list to Kconfig"
This series from James Hilliard <james.hilliard1@gmail.com> converts the
static flags list for the environment to be configured via Kconfig and
updates the documentation.

Link: https://lore.kernel.org/r/20260511182036.50453-1-james.hilliard1@gmail.com
2026-05-25 13:44:45 -06:00
James Hilliard
e11b0c5cab doc: remove configuration settings from README
The remaining configuration settings section is legacy README content.
Its details belong in Kconfig help or the rST documentation.

Remove the section instead of keeping partial stale configuration
documentation in README.

Suggested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: James Hilliard <james.hilliard1@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2026-05-25 13:44:40 -06:00
James Hilliard
5e41a5deb4 env: migrate static flags list to Kconfig
Environment callbacks can already be configured from Kconfig with
CONFIG_ENV_CALLBACK_LIST_STATIC, but static environment flags still
require board headers to define CFG_ENV_FLAGS_LIST_STATIC.

Add CONFIG_ENV_FLAGS_LIST_STATIC and use it as the only board-provided
static environment flags list. Convert the remaining default-config users
from CFG_ENV_FLAGS_LIST_STATIC to defconfig settings and drop the legacy
header macro from ENV_FLAGS_LIST_STATIC.

Move the environment flags format documentation out of README and into
the developer environment documentation. Include the format in the
Kconfig help as well.

This lets boards configure writeable-list policy and type validation
from defconfig without adding a config header solely for env flags.

This preserves the behavior of default configs. Header-only cases that
were inactive in upstream defconfigs are not converted into defconfig
entries: iot2050 can add its list when enabling ENV_WRITEABLE_LIST, and
smegw01 can add mmcdev:dw support if the unlocked SYS_BOOT_LOCKED=n
configuration is needed.

Signed-off-by: James Hilliard <james.hilliard1@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Alexander Sverdlin <alexander.sverdlin@siemens.com>
Reviewed-by: Walter Schweizer <walter.schweizer@siemens.com>
2026-05-25 13:44:40 -06:00
Tom Rini
77efd55f89 Merge patch series "boot/fit: use fdt_for_each_subnode() in image-fit.c"
Aristo Chen <aristo.chen@canonical.com> says:

This series ends with replacing the verbose fdt_next_node() + ndepth
idiom in boot/image-fit.c with fdt_for_each_subnode(), bringing the
file in line with boot/image-fit-sig.c. Six of the seven sites in
image-fit.c predate the macro by 2-6 years; the seventh was
copy-pasted from a neighbour in 2015 just after the macro landed.
The old idiom is legacy, not a deliberate technical choice.

Converting straight to the macro turned out to need a prerequisite,
which is patch 1. fit_print_contents() reads the default-config
property using the loop variable left over after iterating /images
children. With /images defined first in the source (the conventional
layout) libfdt's walker happens to leave that variable pointing at
/configurations and the read works. With /configurations defined
first the read returns NULL and the "Default Configuration" line is
silently omitted. fdt_for_each_subnode()'s post-loop value is
unconditionally a negative error code, so a naive conversion would
have made the missing line the unconditional behaviour. Patch 1
reads the property from confs_noffset directly and removes the
layout dependency.

Patch 2 adds a regression test for the configs-before-images
layout, which had no coverage.

Patch 3 is the mechanical conversion at all seven sites,
equivalence-preserving as described in the per-patch message.

Link: https://lore.kernel.org/r/20260508213217.3807786-1-aristo.chen@canonical.com
2026-05-25 13:44:28 -06:00
Aristo Chen
2c9b117aa4 boot/fit: use fdt_for_each_subnode() in image-fit.c
Replace the verbose fdt_next_node() + ndepth pattern with the
fdt_for_each_subnode() macro at all seven sites in boot/image-fit.c
where the loop only ever processes direct children. The macro is
already defined in <linux/libfdt.h> and used in boot/image-fit-sig.c,
so this brings image-fit.c in line with the rest of the FIT code.

The conversions are equivalence-preserving:

  - fit_get_subimage_count(): the depth-1 filter and the macro are
    both restricted to direct children.
  - fit_conf_print(): the parameter is named noffset, so the loop
    now uses sub_noffset to keep the parent reference stable.
  - fit_print_contents(): the count reset that lived inside the for
    initialiser is moved out as an explicit assignment before each
    loop, so the second loop still starts from zero.
  - fit_image_print(): straightforward replacement.
  - fit_all_image_verify(): same shape as the print loops, with the
    count reset moved out as an explicit assignment before the loop.
  - fit_conf_find_compat(): the body's "if (ndepth > 1) continue"
    guard is redundant once the macro is in use, and is dropped.

No behaviour changes outside of these mechanical reductions. Local
ndepth declarations that are no longer referenced are removed.

Signed-off-by: Aristo Chen <aristo.chen@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2026-05-25 13:44:11 -06:00
Aristo Chen
b31f551bfc test: fit: regression test for default-config print with reversed node order
Add a test that builds a FIT whose /configurations node is defined
before /images in the source, runs iminfo, and asserts that the
"Default Configuration: '<name>'" line appears in the output.

Before the fix in the preceding commit ("boot/fit: read default-config
property from the configurations node"), fit_print_contents() read the
default-config property using the loop variable left over from iterating
/images children. With /images defined first that variable accidentally
pointed at /configurations and the line printed correctly; with
/configurations defined first the read returned NULL and the line was
silently omitted. The new test exercises the latter layout, which had
no coverage.

iminfo and the fit_print_contents() path had no test coverage at all
before this commit.

Signed-off-by: Aristo Chen <aristo.chen@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2026-05-25 13:44:10 -06:00
Aristo Chen
646be6d5cd boot/fit: read default-config property from the configurations node
In fit_print_contents() the default configuration's unit name is read by
calling fdt_getprop() with noffset rather than confs_noffset. Today this
happens to work by coincidence: the preceding loop walks /images using
fdt_next_node(), and when iteration leaves the subtree libfdt returns
the offset of the next sibling in DFS order, which by FIT layout
convention is /configurations. The depth counter then drops below zero
and the loop exits with noffset still pointing at /configurations.

This relies on /images and /configurations being adjacent siblings and
on the implementation detail of fdt_next_node()'s post-exhaustion
return value. It also blocks a follow-up conversion to
fdt_for_each_subnode(), whose post-loop loop variable is a negative
error code rather than a valid offset.

Use confs_noffset directly, which the comment immediately above the
call already names as the source.

Signed-off-by: Aristo Chen <aristo.chen@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2026-05-25 13:44:10 -06:00
Simon Glass
a219f64c27 cros_ec: Sync ec_commands.h from upstream Chrome OS EC
Sync include/ec_commands.h from upstream commit 4f3d17aa34
("skywalker: set SLEEP_TIMEOUT_MS to 50 seconds"). The new file makes
two build assumptions that do not hold for U-Boot.

It hides '<stdint.h>' from __KERNEL__ builds, leaving UINT16_MAX
(used by EC_RES_MAX) undefined for U-Boot; widen the gate to
'!defined(__KERNEL__) || defined(__UBOOT__)'

It gates '<linux/limits.h>' on '#ifdef __KERNEL__'; the matching
'#else' branch defines BIT()/BIT_ULL()/GENMASK()/GENMASK_ULL()
locally, assuming kernel headers provide those macros otherwise.
U-Boot defines __KERNEL__ too but has no <linux/limits.h>. Nest a
'!defined(__UBOOT__)' check around the include so the __UBOOT__ path
stays in the __KERNEL__ branch (no local BIT/GENMASK defines), which
avoids redefinition warnings against U-Boot's linux/bitops.h. Pull
in linux/bitops.h up front for U-Boot so the file's own BIT() and
GENMASK() uses still resolve.

Adapt callers to two interface changes. The 'ec_current_image' enum
tag is now 'ec_image' (EC_IMAGE_* constants unchanged); rename it in
affected files to match. The VBNV-context interface was dropped
upstream, but it still used in lab Chromebooks; keep those constants and
structs in cros_ec.h

Likewise, MEC_EMI_BASE and MEC_EMI_SIZE are a U-Boot-local addition to
ec_commands.h that the upstream sync removes; preserve them in cros_ec.h
next to the VBNV block, and switch the only consumer
(arch/x86/cpu/apollolake/cpu_spl.c) to include cros_ec.h

Signed-off-by: Simon Glass <sjg@chromium.org>
2026-05-25 13:43:31 -06:00
Francois Berder
422024172f led: Fix toggling LED on initial SW blink
If the LED is in the ON state, it is briefly set to OFF
then to ON immediately due to falling-through in the default
case.
This commit ensures that no fall-through occurs and thus
a LED initially in the ON state is turned off before blinking.

Signed-off-by: Francois Berder <fberder@outlook.fr>
Fixes: 9e3d83301e ("led: toggle LED on initial SW blink")
Acked-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2026-05-25 13:43:28 -06:00
Vincent Jardin
ed5d719bc2 gpio: uclass: show DT gpio-line-names
gpio status -a does not have labels: the existing path walks
the per-bank requested label table.
Issue: The boards that populate the standard gpio-line-names
property in their device tree end up with anonymous entries,
which is not logic with the purpose of having those names in the DT.

No impact with boards that does not set gpio-line-names.

Signed-off-by: Vincent Jardin <vjardin@free.fr>
2026-05-25 13:43:24 -06:00
Aristo Chen
e9848e30bd test: fs: Use shared generate_file from utils
test_fs/test_erofs.py and test_fs/test_squashfs/sqfs_common.py both
defined a generate_file() helper that writes a file of a given size
filled with 'x'. The two functions were functionally identical and
differed only in parameter names and docstrings.

Move the helper into the existing test/py/utils.py module, which is
the established home for generic test utilities (md5sum_file,
PersistentRandomFile, attempt_to_open_file). Update both call sites
to use it.

Signed-off-by: Aristo Chen <aristo.chen@canonical.com>
Reviewed-by: joaomarcos.costa@bootlin.com
Reviewed-by: Simon Glass <sjg@chromium.org>
2026-05-25 13:43:21 -06:00
Tom Rini
7bb1917b15 Merge tag 'v2026.07-rc3' into next
Prepare v2026.07-rc3
2026-05-25 11:35:35 -06:00
Tom Rini
76d62273bc Prepare v2026.07-rc3
Signed-off-by: Tom Rini <trini@konsulko.com>
2026-05-25 11:05:37 -06:00
Wadim Egorov
a208934801 Makefile: binman: Search board directory before srctree
A file like rm-cfg.yaml accidentally left in the source tree root
shadows the board-specific copy. binman builds the wrong YAML, the
resulting rm-cfg.bin may match a different SoC, and we end up with
the following error:

  k3_system_controller sysctrler: k3_sysctrler_start:
      Boot Notification response failed. ret = -110

Move the board directory ahead of the srctree root so that the
most-specific match wins.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2026-05-25 09:48:35 -06:00
Tom Rini
97208cb762 Merge tag 'xilinx-for-v2026.07-rc3' of https://source.denx.de/u-boot/custodians/u-boot-microblaze
AMD/Xilinx/FPGA changes for v2026.07-rc3

versal/fpga:
- Fix unaligned buffer handling

versal2:
- Fix buffer overflow in SOC name array
2026-05-25 09:43:44 -06:00
Tom Rini
ba932756ca configs: Resync with savedefconfig
Resync all defconfig files using qconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2026-05-25 09:37:02 -06:00
Tom Rini
7c419d4b57 global: Update URL for U-Boot project
Our official domain is now u-boot-project.org, so update all in-tree
references to use the correct domain.

Reviewed-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Peter Robinson <pbrobinson@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2026-05-25 09:30:47 -06:00
Tom Rini
e875c10c6f Merge patch series "Fix speculative access to firewalled regions on AM62 SoCs"
Anshul Dalal <anshuld@ti.com> says:

This patch series fixes firewall exceptions observed on AM62 family of
devices due to speculative accesses made by the A53 core to secure DDR
regions.

Link: https://lore.kernel.org/r/20260520-am62_firewall_exception_fix-v3-0-9ca3dc40aea4@ti.com
2026-05-25 09:29:54 -06:00
Anshul Dalal
37e6b640ef mach-k3: enable mmu after reserved memory is unmapped
Currently the sequence to enable caches for the A53/A72 core on K3
devices looks as follows:

 1. Map entire DDR banks
 2. Setup page tables (done by mmu_setup)
 3. Enable MMU
 4. Unmap reserved-memory regions
 5. Enable caches

However there is a brief period of execution between #3 and #4 where the
core can issue speculative accesses to the entire DDR space (including
the reserved-memory regions) despite the caches being disabled.

A firewall exception is triggered whenever such speculative access is
made to secure DDR region of TFA or OP-TEE. This patch fixes the issue
by re-ordering the sequence as follows:

 1. Map entire DDR banks
 2. Setup page tables
 3. Unmap reserved-memory regions
 4. Enable MMU
 5. Enable caches

Fixes: f1c694b8fd ("mach-k3: map all banks using mem_map_from_dram_banks")
Reported-by: Suhaas Joshi <s-joshi@ti.com>
Signed-off-by: Anshul Dalal <anshuld@ti.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2026-05-25 09:29:50 -06:00
Anshul Dalal
b53128d528 arm: armv8: mmu: move mmu enablement out of mmu_setup
Currently mmu_setup for ARMv8 performs two functions, first it sets up
the page tables based the memory map provided by the board and then it
enables the MMU.

However for some platforms runtime fixes to the generated page tables
are required before the MMU can be enabled, such as K3 family of SoCs.

Therefore this patch moves the enablement of the MMU out of mmu_setup
and to a standalone mmu_enable function to give more granular control to
the platforms.

Note that no functional changes are intended from this patch.

Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Anshul Dalal <anshuld@ti.com>
2026-05-25 09:29:50 -06:00
Moteen Shah
7e11adf054 am57xx: restore bootm_size for ARMv7 HighMem constraint
babae80169 removed bootm_size from ti_common.env to allow K3 boards
to process images larger than 256MB, but preserved it in
ti_armv7_keystone2.env for ARMv7 Keystone2 boards. AM57xx (also ARMv7)
was not covered by that preservation.

Without bootm_size, env_get_bootm_size() falls back to gd->ram_size,
causing initrd_high to be computed as the top of all RAM. On ARM32
boards with more RAM than the DMA zone (e.g. AM572x IDK with 2GiB),
this places the ramdisk above 0xafe00000 (HighMem), which is not
directly accessible by the kernel after MMU setup, causing a silent
crash.

With bootm_size=0x10000000, initrd_high is constrained to
0x80000000 + 0x10000000 = 0x90000000, keeping the ramdisk in the
DMA zone and allowing the kernel to access it correctly.

Fixes: babae80169 ("include: env: ti_common: remove bootm_size")

Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Signed-off-by: Moteen Shah <m-shah@ti.com>
2026-05-25 09:29:30 -06:00
Francois Berder
8a5989acc6 arm64: versal2: Fix buffer overflow in soc_name_decode
The size of name buffer was not computed correctly.
The suffix format is "--rel.-el" (9 chars instead of 6),
and the longest platform name is "emu-mmd" (7 chars instead of 4).
Fix comment and name size.

Fixes: 40f5046c22 ("arm64: versal2: Add support for AMD Versal Gen 2")
Signed-off-by: Francois Berder <fberder@outlook.fr>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/BESP194MB280513B376D54A815F3FD507DA0E2@BESP194MB2805.EURP194.PROD.OUTLOOK.COM
2026-05-25 15:14:05 +02:00
Pranav Tilak
9793931f36 fpga: versalpl: Fix unaligned buffer handling
When fpga load is called with a misaligned buffer address, the
versal_align_dma_buffer() function shifts the pointer forward to the
next aligned boundary and uses memcpy() to copy the data. Since the
destination is ahead of the source and the regions overlap, memcpy()
produces undefined behavior; in practice U-Boot's generic memcpy()
copies forward, repeating the first ARCH_DMA_MINALIGN-aligned chunk
throughout the buffer.

Replace memcpy() with memmove() which correctly handles overlapping
regions by copying backwards when the destination is ahead of the
source.

Fixes: 26e054c943 ("arm64: versal: fpga: Add PL bit stream load support")
Signed-off-by: Pranav Tilak <pranav.vinaytilak@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20260507113359.3665220-1-pranav.vinaytilak@amd.com
2026-05-25 15:14:05 +02:00
Tom Rini
bb354d0445 Merge patch series "Add virtio-mmio support to m68k virt machine"
Daniel Palmer <daniel@thingy.jp> says:

Lets start making the m68k virt machine support useful.

First we need to fix some m68k endian issues.

Then allow virtio mmio driver instances to be created with
platform data and fix a minor endian issue.

Finally, add the code for the board to create the instances.

Link: https://lore.kernel.org/r/20260516074016.885146-1-daniel@thingy.jp
2026-05-22 16:47:54 -06:00
Daniel Palmer
3dc2761d63 board: qemu: m68k: Create virtio mmio instances
So that you can use virtio network, block etc create the virtio mmio
instances. There are 128 of these even if they are not all used, a
single mmio base value is passed via bootinfo.

Reviewed-by: Angelo Dureghello <angelo@kernel-space.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kuan-Wei Chiu <visitorckw@gmail.com>
Tested-by: Kuan-Wei Chiu <visitorckw@gmail.com>
Signed-off-by: Daniel Palmer <daniel@thingy.jp>
2026-05-22 16:47:54 -06:00
Daniel Palmer
ddba15ab72 virtio: blk: Fix converting the vendor id to a string
Currently we are trying to work out if the vendor id is from
a virtio-mmio device and then casting a u32 to a char* and using
it as a C-string. By chance there is usually a zero after the u32
and it works.

Since the vendor id we are trying to convert to a string is QEMU's
just define a value for the QEMU vendor id, check if the vendor
id matches and then use a predefined string for "QEMU".

I don't think we should have been assumming all virtio-mmio vendor
ids are printable ASCII chars in the first place so do this special
casing just for QEMU. If the vendor id isn't QEMU print the hex
value of it.

Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kuan-Wei Chiu <visitorckw@gmail.com>
Signed-off-by: Daniel Palmer <daniel@thingy.jp>
2026-05-22 16:47:54 -06:00
Daniel Palmer
b781017fb6 virtio: cmd: Depend on VIRTIO_BLK
The virtio command is calling virtio blk functions but currently
depends on CONFIG_VIRTIO only. This means disabling CONFIG_VIRTIO_BLK
causes the final link to fail.

Since CONFIG_VIRTIO_BLK depends on CONFIG_VIRTIO switch to depending
on just CONFIG_VIRTIO_BLK

Reviewed-by: Kuan-Wei Chiu <visitorckw@gmail.com>
Reviewed-by: Angelo Dureghello <angelo@kernel-space.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Daniel Palmer <daniel@thingy.jp>
2026-05-22 16:47:54 -06:00
Daniel Palmer
009cd5b56d virtio: mmio: Allow instantiation via platform data
The m68k QEMU virt machine doesn't use devicetree, yet, so
allow it to create virtio-mmio instances via platform data.

Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kuan-Wei Chiu <visitorckw@gmail.com>
Reviewed-by: Angelo Dureghello <angelo@kernel-space.org>
Signed-off-by: Daniel Palmer <daniel@thingy.jp>
2026-05-22 16:47:54 -06:00
Daniel Palmer
3e2b261647 m68k: Fix writew(), writel(), readw(), readl() endianness for classic m68k
In Linux these are meant to read a little-endian value and swap
to the CPU endian.

In u-boot for m68k this is currently broken and prevents
virtio-mmio from functioning.

This change is only for classic m68k. Coldfire has read big-endian,
no swap for these in u-boot and Linux and existing drivers probably
depend on this.

Tested-by: Angelo Dureghello <angelo@kernel-space.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Kuan-Wei Chiu <visitorckw@gmail.com>
Acked-by: Angelo Dureghello <angelo@kernel-space.org>
Signed-off-by: Daniel Palmer <daniel@thingy.jp>
2026-05-22 16:47:54 -06:00
Kuan-Wei Chiu
75a1d7280a timer: goldfish: Use __raw_readl()
The Goldfish timer registers are native endian, so they act as
big-endian on the m68k virt machine. Currently, this driver uses
readl(), which works by luck because it's currently broken on m68k.

Use __raw_readl() instead to avoid breaking this driver when the
endianness of readl() is fixed.

Signed-off-by: Kuan-Wei Chiu <visitorckw@gmail.com>
Tested-by: Daniel Palmer <daniel@thingy.jp>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Daniel Palmer <daniel@thingy.jp>
2026-05-22 16:47:54 -06:00
Kuan-Wei Chiu
5116fed77d rtc: goldfish: Use __raw_readl() and __raw_writel()
In QEMU, the Goldfish RTC is explicitly instantiated as a big-endian
device on the m68k virt machine (via the 'big-endian=true' property).
Currently, this driver uses ioread32() and iowrite32(), which works
by luck because the underlying readl() and writel() are currently
broken on m68k.

Use __raw_readl() and __raw_writel() instead to avoid breaking this
driver when the endianness of readl() and writel() is fixed.

Signed-off-by: Kuan-Wei Chiu <visitorckw@gmail.com>
Tested-by: Daniel Palmer <daniel@thingy.jp>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Daniel Palmer <daniel@thingy.jp>
2026-05-22 16:47:54 -06:00
Daniel Palmer
0bcd158db3 sysreset: qemu virt: Use __raw_writel()
The virt ctrl register seems to be native endian, currently this driver
uses writel(), which works by luck because its currently broken on m68k.

Use __raw_writel() instead to avoid breaking this driver when the
endianness of writel() is fixed.

Acked-by: Kuan-Wei Chiu <visitorckw@gmail.com>
Reviewed-by: Angelo Dureghello <angelo@kernel-space.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Daniel Palmer <daniel@thingy.jp>
2026-05-22 16:47:54 -06:00
Daniel Palmer
ccec4ce2ee sysreset: qemu virt: Use map_sysmem()
In the platform data there is a phys_addr_t (an integer) for the address
of the register and we pass that as-is into writel() which is fine in most
places because we don't need to do any mapping and the macro for writel()
does a cast to a pointer.

If writel() is a static inline function the address argument is a pointer
so passing it in as an integer without casting it first causes warnings or
build failure.

map_sysmem() handles the casting part and if phys_addr_t is 32bits when
on a 64bit machine.

Signed-off-by: Daniel Palmer <daniel@thingy.jp>
Acked-by: Kuan-Wei Chiu <visitorckw@gmail.com>
2026-05-22 16:47:54 -06:00
Tom Rini
987c93fc68 Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sh
This is Renesas R-Car X5H support for U-Boot on its RSIP Cortex-M33 core
in addition to already support U-Boot on Cortex-A720AE core. The first
two patches also switch X5H to OF_UPSTREAM.
2026-05-22 13:30:42 -06:00
Marek Vasut
9d47a5a4d5 arm: renesas: Add Renesas R-Car R8A78000 X5H Cortex-M33 RSIP port
Add support for building U-Boot for Cortex-M33 RSIP core in Renesas
R-Car Gen5 R8A78000 X5H SoC. The main goal is to start U-Boot on the
Cortex-M33 RSIP core, which initializes the hardware and then starts
the Cortex-M33 SCP and Cortex-A720 cores which run the SCP firmware
and applications software respectively. The SCP is responsible for
platform resource management, and is used to start other CPU cores.

The Cortex-M33 build contains its own r8a78000_ironhide_cm33_defconfig
which configures the build for aarch32 instruction set compatible with
the ARMv8M core. The build also uses -cm33 DT and -u-boot.dtsi which
are derived from their non-CM33 counterparts, and add CM33 specifics.

The arch/arm/mach-renesas/u-boot-rsip.lds is derived from generic
arch/arm/cpu/u-boot.lds with adjustments to cater to the RSIP core,
those are entrypoint before vectors, __data_start/__data_end symbols
for data-only relocation, and placement of BSS into read-write SRAM
area.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2026-05-21 21:48:05 +02:00
Marek Vasut
3b2ce3743c arm: renesas: Generate u-boot-elf.shdr for R-Car Gen5 RSIP
Add target to generate u-boot-elf.shdr for R-Car Gen5 Cortex-M33
RSIP core. The resulting .shdr SREC file can be written into the
HF at offset 0.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2026-05-21 21:48:05 +02:00
Marek Vasut
3bcee350f0 arm: renesas: Generate u-boot-elf.scif for R-Car Gen5 RSIP
Add target to generate u-boot-elf.scif for R-Car Gen5 Cortex-M33
RSIP core. The resulting .scif SREC file can be loaded using the
SCIF loader to start U-Boot on the RSIP core.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2026-05-21 21:48:05 +02:00
Marek Vasut
5fa536f698 arm64: dts: renesas: Update reset IDs on R-Car Gen5 R8A78000 X5H
The current DT reset ID encoding in R-Car Gen5 R8A78000 X5H U-Boot DTs
is inherited from downstream BSP. New reset bindings for this SoC are
now submitted and under review [1]. Replace the DT reset IDs with the
ones used in the new bindings.

[1] https://lore.kernel.org/all/053c312d07445517d8f9c84bfe3cc8fb72d4cd9a.1776793163.git.geert+renesas@glider.be/

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2026-05-21 21:48:05 +02:00
Marek Vasut
3681df4f34 arm64: dts: renesas: Switch to remap drivers on R-Car Gen5 R8A78000 X5H
Point every direct user of SCMI clock protocol at CPG node instead
of SCMI clock protocol node. Point every direct user of SCMI reset
and power domain protocol at a matching newly introduced MDLC node
instead of the SCMI reset and power domain protocol nodes.

This allows the CPG and MDLC remap drivers bound to CPG node and MDLC
nodes to remap between DT clock, reset and power domain IDs and SCMI
clock, reset and power domain IDs. This makes U-Boot on R-Car X5H
compatible with multiple SCP firmware versions. Currently supported
versions of SCP firmware are 4.28, 4.31 and 4.32.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2026-05-21 21:48:05 +02:00
Marek Vasut
2d0ec0891b arm64: renesas: Select R-Car Gen5 R8A78000 X5H MDLC power domain and reset driver
Select the R8A78000 power domain and reset driver on R-Car Gen5 X5H
SoC by default. The power domain and reset driver is used to remap
DT power domain and reset IDs to SCMI power domain and reset IDs,
which is necessary to support multiple SCP firmware versions with
varying SCMI clock IDs across versions.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2026-05-21 21:48:05 +02:00
Marek Vasut
53297db126 power: domain: Add Renesas R-Car R8A78000 X5H MDLC power domain and reset driver
Add Renesas R-Car R8A78000 X5H MDLC power domain and reset driver,
which serves as a remap driver between DT power domain and reset IDs
and SCMI power domain and reset IDs in case U-Boot runs on Cortex-A,
and as a direct hardware access driver for RSIP.

The R-Car X5H SCP firmware uses different SCMI power domain and
reset IDs in different versions of the SCP firmware, which makes
this remapping necessary. The SCMI base protocol version is updated
for each new SCP firmware version, it is therefore possible to
determine which SCP firmware version is running on the platform
from the base protocol and then determine which remapping table to
use for DT power domain and reset ID to SCMI power domain and reset
ID remapping.

Currently supported versions are SCP 4.28, 4.31, 4.32 .

The DT power domain and reset ID to SCMI power domain and reset ID
remap and call mechanism is simple. Unlike SCMI clock protocol driver,
the SCMI reset and power domain protocol drivers register only a single
device. This driver looks up that single device, obtains its reset or
power domain ops, sets up struct reset_ctl or struct power_domain with
remapped SCMI ID, and invokes operations directly on the device.

In case of RSIP, all power domains are already enabled by BootROM or
early SoC initialization code, the driver therefore only acts as a
stub for the power domain part. The reset part operates as a direct
hardware access reset driver.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2026-05-21 21:48:05 +02:00
Marek Vasut
567a4cdd14 arm64: renesas: Select R-Car Gen5 R8A78000 X5H CPG clock driver
Select the R8A78000 clock driver on R-Car Gen5 X5H SoC by default.
The clock driver is used to remap DT clock IDs to SCMI clock IDs,
which is necessary to support multiple SCP firmware versions with
varying SCMI clock IDs across versions.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2026-05-21 21:48:05 +02:00
Marek Vasut
24039ffefb clk: renesas: Add Renesas R-Car R8A78000 X5H CPG clock driver
Add Renesas R-Car R8A78000 X5H CPG clock driver, which serves as a
remap driver between DT clock IDs and SCMI clock IDs in case U-Boot
runs on the Cortex-A, and as a trivial clock driver for RSIP.

The R-Car X5H SCP firmware uses different SCMI clock IDs in different
versions of the SCP firmware, which makes this remapping necessary.
The SCMI base protocol version is updated for each new SCP firmware
version, it is therefore possible to determine which SCP firmware
version is running on the platform from the base protocol and then
determine which remapping table to use for DT clock ID to SCMI clock
ID remapping.

Currently supported versions are SCP 4.28, 4.31, 4.32 .

The DT clock ID to SCMI clock ID remap and call mechanism is a bit
complex. The driver looks up the SCMI clock protocol device on probe
and stores pointer to it in private data. On each clock request which
has to be remapped, the device sequence ID of this SCMI clock protocol
device is incremented by the remapped SCMI clock ID + 1 and used to
look up matching clock device by sequence number. If the device is
found, it is converted to clock, which can be used in regular clock
operations. This look up has to be done because the SCMI clock driver
registers a subdevice for each clock, and this look up is the only way
to find the correct SCMI clock subdevice. Since the SCMI device and
the clock subdevices are registered in the same function, we can depend
on the device sequence numbers to be monotonically incrementing, with
SCMI clock protocol device being sequence number N, the first SCMI
clock subdevice being sequence number N+1 and so on.

In case of RSIP, all clocks are already enabled by BootROM or early
SoC initialization code, the driver therefore only acts as a stub.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2026-05-21 21:48:05 +02:00
Marek Vasut
3e24519d6f arm64: renesas: Select HSCIF for DEBUG UART on R-Car Gen5 R8A78000 X5H
The R-Car Gen5 R8A78000 X5H uses HSCIF as default serial console
interface. Select CFG_HSCIF to make debug UART code also configure
serial console interface as HSCIF instead of SCIF in case the
CONFIG_DEBUG_UART would be enabled.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2026-05-21 21:48:05 +02:00
Marek Vasut
9692469b18 arm64: dts: renesas: Use SCP_CLOCK_ID_CLK_S0D6_PERE_MAIN on R-Car X5H
Use macro SCP_CLOCK_ID_CLK_S0D6_PERE_MAIN for SCMI clock 1691
instead of hardcoding the number in DT. No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2026-05-21 21:48:05 +02:00
Marek Vasut
d77f8443c7 arm64: dts: renesas: Switch to upstream DT on Renesas R-Car X5H R8A78000
Enable OF_UPSTREAM to use upstream Linux kernel DT source as a base
for U-Boot control DT. Retain currently present parts of the DT which
are not yet part of upstream Linux kernel DT in -u-boot.dtsi files
until they get replaced by upstream equivalents. Add renesas/ prefix
to the DEFAULT_DEVICE_TREE as part of the switch.

Unused i2c2..i2c8 nodes have been removed, and will become available
once upstream Linux kernel DT adds those nodes.

The DRAM_RSV_SIZE has been updated to cover first 518 MiB of DRAM,
which are reserved for firmware and other use.

Note that all DT parts in -u-boot.dtsi are not considered stable DT
bindings and may change before they land in Linux kernel and become
stable DT ABI.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2026-05-21 21:48:05 +02:00
Tom Rini
744cf5d4e3 Merge tag 'u-boot-dfu-20260521' of https://source.denx.de/u-boot/custodians/u-boot-dfu
u-boot-dfu-20260521

CI: https://source.denx.de/u-boot/custodians/u-boot-dfu/-/pipelines/30195

Usb Gadget:
* f_acm: Fix memory leak in acm_add()
* atmel: Fix gadget support on bus reset
2026-05-21 10:26:29 -06:00
Tom Rini
46b29a7d12 Merge tag 'u-boot-nvme-fixes-20260521' of https://source.denx.de/u-boot/custodians/u-boot-ufs
- Add myself as Maintainer of NVMe
- fix command ID wraparound handling
- apple: Check memalign return value
- Staticize and constify driver ops
- Fix PRP list pointer arithmetic for chained transfers
2026-05-21 08:16:56 -06:00
Zixun LI
7f34bb50a5 usb: gadget: atmel: do not disable endpoints in reset_all_endpoints()
Endpoints should not be disabled on bus reset inside UDC driver,
otherwise a race condition will happen between gadget driver. Gadget
driver will free the requests and disable endpoints in disconnect ops.

Also remove outdated comment about it in usba_ep_disable().

Signed-off-by: Zixun LI <admin@hifiphile.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Fixes: 59310d1ecb ("usb: gadget: introduce 'enabled' flag in struct usb_ep")
Link: https://patch.msgid.link/20260515-udc_ep-v2-1-cd335b4e62e4@hifiphile.com
[mkorpershoek: removed empty newline between Fixes: and sob]
Signed-off-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
2026-05-20 12:09:29 +02:00
Prashant Kamble
4f51050598 nvme: Fix PRP list pointer arithmetic for chained transfers
The PRP setup code advances prp_pool using u64 pointer
arithmetic:

        prp_pool += page_size;

This increments the pointer by page_size * sizeof(u64)
bytes instead of page_size bytes, resulting in invalid
PRP list addresses when multiple PRP list pages are
required.

The issue becomes visible for large transfers, typically
above 2 MiB when MDTS > 9.

Fix it by using byte-wise pointer arithmetic when
advancing to the next PRP list page.

Signed-off-by: Prashant Kamble <prashant.kamble223@gmail.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://patch.msgid.link/20260518022535.17197-1-prashant.kamble223@gmail.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2026-05-20 09:51:44 +02:00
Marek Vasut
4e91d9ff33 nvme: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://patch.msgid.link/20260508122128.512798-1-marek.vasut+renesas@mailbox.org
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2026-05-20 09:44:37 +02:00
Francois Berder
63f0f19803 nvme: apple: Check memalign return value
memalign returns NULL if it fails.
This commit ensures that we handle this failure before
filling the buffer with 0s.

Signed-off-by: Francois Berder <fberder@outlook.fr>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://patch.msgid.link/BESP194MB280542535B098A33C8A815EEDA3A2@BESP194MB2805.EURP194.PROD.OUTLOOK.COM
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2026-05-20 09:44:37 +02:00
Prashant Kamble
d6eb327828 nvme: fix command ID wraparound handling
nvme_get_cmd_id() returns 0 after cmdid reaches USHRT_MAX,
but fails to reset cmdid itself. As a result, all subsequent
calls keep returning 0 indefinitely.

Reset cmdid when wraparound occurs so command IDs continue
incrementing correctly.

Signed-off-by: Prashant Kamble <prashant.kamble223@gmail.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://patch.msgid.link/20260518060915.45607-1-prashant.kamble223@gmail.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2026-05-20 09:44:37 +02:00
Neil Armstrong
49f8b8de4e MAINTAINERS: Add myself to the list of NVMe maintainers
Adding myself to continue Bin's work to help maintain the
NVMe support in U-boot.

Acked-by: Tom Rini <trini@konsulko.com>
Link: https://patch.msgid.link/20260519-u-boot-pci-nvme-maintainer-v1-1-363593cbbfdc@linaro.org
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2026-05-20 09:44:37 +02:00
Tom Rini
e81c552171 virtio: Drop empty bootdev_ops structure
We don't need to provide an empty struct here now that the caller can
handle this being empty.

Signed-off-by: Tom Rini <trini@konsulko.com>
2026-05-19 08:18:54 -06:00
Tom Rini
e84d147bd3 scsi: Drop empty bootdev_ops structure
We don't need to provide an empty struct here now that the caller can
handle this being empty.

Signed-off-by: Tom Rini <trini@konsulko.com>
2026-05-19 08:18:44 -06:00
Tom Rini
ce12ad70b8 ata: sata: Drop empty bootdev_ops structure
We don't need to provide an empty struct here now that the caller can
handle this being empty.

Signed-off-by: Tom Rini <trini@konsulko.com>
2026-05-19 08:18:29 -06:00
Tom Rini
83cf74a01a block: ide: Drop empty bootdev_ops structure
We don't need to provide an empty struct here now that the caller can
handle this being empty.

Signed-off-by: Tom Rini <trini@konsulko.com>
2026-05-19 08:17:23 -06:00
Tom Rini
15cc283d1b bootdev: Fix the case where the driver ops field is null.
In the case where a bootdev does not have a custom get_bootflow function
but instead relies on default_get_bootflow to provide one,
bootdev_get_bootflow was not handling the case where ops was simply not
set. Restructure the function to check for "ops && ops->get_bootflow"
and add appropriate log_debug calls for both cases.

Signed-off-by: Tom Rini <trini@konsulko.com>
2026-05-19 07:53:50 -06:00
Marek Vasut
21a3b9f03b arm: Fix typo in linker script
Fix typo, addreses -> addresses. No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2026-05-18 16:56:07 -06:00
Tom Rini
85b643b7d0 Merge branch 'staticize-constify-drivers' into next
This brings in a number of patches from Marek Vasut to clean up cases
tree-wide where a struct should be marked as static and const (in some
cases only one of these was needed, but the majority are both).
2026-05-18 16:56:07 -06:00
Marek Vasut
05f76ca898 spi: apple: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Mark Kettenis <kettenis@openbsd.org>
2026-05-18 16:56:07 -06:00
Marek Vasut
50e6cda6b6 scsi: sandbox: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2026-05-18 16:56:07 -06:00
Marek Vasut
a504ad9e68 rtc: emul: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2026-05-18 16:56:07 -06:00
Marek Vasut
c97fbda5fa reset: tegra186: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Svyatoslav Ryhel <clamor95@gmail.com>
2026-05-18 16:56:07 -06:00
Marek Vasut
6f69da0d0f reset: tegra-car: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Svyatoslav Ryhel <clamor95@gmail.com>
2026-05-18 16:56:07 -06:00
Marek Vasut
9c631c5dbb reset: sti: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2026-05-18 16:56:07 -06:00
Marek Vasut
1e38a363c2 reset: sandbox: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2026-05-18 16:56:07 -06:00
Marek Vasut
ce830106bf reset: sunxi: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2026-05-18 16:56:07 -06:00
Marek Vasut
2a7e739c04 reset: raspberrypi: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2026-05-18 16:56:07 -06:00
Marek Vasut
35cd9d8636 reset: npcm: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2026-05-18 16:56:07 -06:00
Marek Vasut
4020549f9b reset: meson: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2026-05-18 16:56:07 -06:00
Marek Vasut
85be3b9287 reset: mediatek: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2026-05-18 16:56:07 -06:00
Marek Vasut
1fe34ada73 reset: dra7: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2026-05-18 16:56:07 -06:00
Marek Vasut
6333bec332 reset: bcm6345: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2026-05-18 16:56:07 -06:00
Marek Vasut
432749b1a3 reset: at91: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2026-05-18 16:56:07 -06:00
Marek Vasut
cecdc51a46 reset: ast2600: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2026-05-18 16:56:07 -06:00
Marek Vasut
c2912fa76b reset: ast2500: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2026-05-18 16:56:07 -06:00
Marek Vasut
1f1ec618f2 cpu: armv8: Staticize driver ops
Set the ops structure as static. The structure is not accessible
from outside of this driver.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2026-05-18 16:56:07 -06:00
Marek Vasut
da1ac763c9 mtd: spi: bootstd: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Takahiro Kuwano <takahiro.kuwano@infineon.com>
2026-05-18 16:56:07 -06:00
Marek Vasut
9ef7c13308 misc: x86: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2026-05-18 16:56:07 -06:00
Marek Vasut
d6a87d042e misc: i2c: eeprom-emul: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2026-05-18 16:56:07 -06:00
Marek Vasut
0bda59b1fa misc: cros_ec: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Quentin Schulz <quentin.schulz@cherry.de>
2026-05-18 16:56:07 -06:00
Marek Vasut
e253640e3f mailbox: stm32-ipcc: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2026-05-18 16:56:07 -06:00
Marek Vasut
0a1347f0a1 mailbox: sandbox: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2026-05-18 16:56:07 -06:00
Marek Vasut
85f4b08691 mailbox: renesas: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2026-05-18 16:56:07 -06:00
Marek Vasut
b2961202a7 mailbox: k3-sec-proxy: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2026-05-18 16:56:07 -06:00
Marek Vasut
44f6ca49e9 mailbox: imx: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2026-05-18 16:56:07 -06:00
Marek Vasut
499cb93dec mailbox: apple: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Mark Kettenis <kettenis@openbsd.org>
2026-05-18 16:56:07 -06:00
Marek Vasut
31df5fc7d4 clk: sunxi: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2026-05-18 16:56:07 -06:00
Marek Vasut
368255a9a0 clk: sunxi: Drop the extern
The struct clk_ops sunxi_clk_ops is private to the clock driver
and there are no external users, no need to expose it this way.
Drop the extern.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2026-05-18 16:56:07 -06:00
Marek Vasut
f23324e49e clk: ast2600: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2026-05-18 16:56:07 -06:00
Marek Vasut
a8f49cc193 clk: ast2500: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2026-05-18 16:56:07 -06:00
Marek Vasut
64abe3cfcc block: rockchip: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2026-05-18 16:56:07 -06:00
Marek Vasut
2908a3f35b ata: sata_mv: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <stefan.roese@mailbox.org>
2026-05-18 16:56:07 -06:00
Marek Vasut
06bf459570 ata: fsl_sata: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2026-05-18 14:26:36 -06:00
Tom Rini
11e1be868c Merge tag 'qcom-next-18May2026' of https://source.denx.de/u-boot/custodians/u-boot-snapdragon into next
- SM6125 gains initial support
- The qcom clock drivers get better support for configuring UFS clocks
- ufetch gets some aesthetic improvements
- A minor bug in the qcm2290 clock driver is fixed
- A few qcom drivers get static/constified
- The GENI serial driver has the RX watermark register properly set
2026-05-18 10:48:20 -06:00
Tom Rini
38dbe637c9 Merge tag 'efi-2026-07-rc3' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request efi-2026-07-rc3

CI: https://source.denx.de/u-boot/custodians/u-boot-efi/-/pipelines/30152

Documentation:

* For reset command describe when the -edl option is available and fix a
  typo.

UEFI:

* If efi_allocate_pages() is with EFI_ALLOCATE_ADDRESS fails, return
  EFI_NOT_FOUND.
* Fix HII keyboard layout pointer computation and extend HII keyboard
  layout tests.

Others:

* In reset command online help show -edl option only when enabled.
2026-05-18 09:12:11 -06:00
Tom Rini
78319e074d Merge tag 'ubi-updates-for-2026.07-rc3' of https://source.denx.de/u-boot/custodians/u-boot-ubi
UBI updates for 2026.07-rc3

Fix from Peter:
- fs: ubifs: remove dead code
  Fixes: d5888d509c ("fs: ubifs: fix bugs involving symlinks in ubifs_findfile")
  (hs. correct the commit ID)
2026-05-18 08:57:51 -06:00
Biswapriyo Nath
0d131b3b06 board/qualcomm: qcom-phone: Add poweroff command
This command helps to shutdown the device directly from serial command
line. Or, the phone has to be booted into recovery mode to power off.

Signed-off-by: Biswapriyo Nath <nathbappai@gmail.com>
Link: https://patch.msgid.link/20260515-ufs-sm61x5-v2-3-0a35d083d2da@gmail.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2026-05-18 11:06:53 +02:00
Biswapriyo Nath
bf6de81367 clk/qcom: qcm2290: Fix vote_bit of gpll6 clock
This changes the vote_bit same as enable_mask in Linux clock driver.

Fixes: 3ddc67573f ("clk/qcom: qcm2290: Add SDCC1 apps clock frequency table")
Signed-off-by: Biswapriyo Nath <nathbappai@gmail.com>
Link: https://patch.msgid.link/20260515-ufs-sm61x5-v2-2-0a35d083d2da@gmail.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2026-05-18 11:06:02 +02:00
Biswapriyo Nath
d54d2ec651 phy: qcom: Add SM6115 and SM6125 to QMP UFS PHY driver
The UFS on SM6125 can reuse SM6115 configuration, just like Linux.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Biswapriyo Nath <nathbappai@gmail.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://patch.msgid.link/20260515-ufs-sm61x5-v2-1-0a35d083d2da@gmail.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2026-05-18 11:06:02 +02:00
Marek Vasut
5a995c2fe0 pci: pcie_dw_qcom: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://patch.msgid.link/20260508122144.512818-1-marek.vasut+renesas@mailbox.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2026-05-18 11:04:47 +02:00
Marek Vasut
bc28119288 gpio: qcom: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://patch.msgid.link/20260507220549.209113-2-marek.vasut+renesas@mailbox.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2026-05-18 11:04:21 +02:00
Marek Vasut
246b0f185a gpio: qcom_pmic: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://patch.msgid.link/20260507220549.209113-1-marek.vasut+renesas@mailbox.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2026-05-18 11:04:21 +02:00
Biswapriyo Nath
60bc1eb8c2 drivers: pinctrl: Add Qualcomm SM6125 TLMM driver
Add support for TLMM pin controller block (Top Level Mode Multiplexer)
on SM6125 SoC, with support for special pins.

Signed-off-by: Biswapriyo Nath <nathbappai@gmail.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
soc98: input: 1 [x] mmc@4784000.cd-gpios
soc98: input: 0 [x] mmc@4784000.cd-gpios
Link: https://patch.msgid.link/20260204-sm6125-clk-pinctrl-v1-3-9cf4c556557a@gmail.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2026-05-18 11:04:14 +02:00
Biswapriyo Nath
b6470f662a qcom_defconfig: Enable SM6125 clock driver
Enable the driver so that SM6125 devices can boot with qcom_defconfig.

Signed-off-by: Biswapriyo Nath <nathbappai@gmail.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
soc98: input: 1 [x] mmc@4784000.cd-gpios
soc98: input: 0 [x] mmc@4784000.cd-gpios
Link: https://patch.msgid.link/20260204-sm6125-clk-pinctrl-v1-2-9cf4c556557a@gmail.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2026-05-18 11:04:14 +02:00
Biswapriyo Nath
140f248556 clk/qcom: Add SM6125 clock driver
Add clock driver for the GCC block found in the SM6125 SoC.

Signed-off-by: Biswapriyo Nath <nathbappai@gmail.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
soc98: input: 1 [x] mmc@4784000.cd-gpios
soc98: input: 0 [x] mmc@4784000.cd-gpios
Link: https://patch.msgid.link/20260204-sm6125-clk-pinctrl-v1-1-9cf4c556557a@gmail.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2026-05-18 11:04:14 +02:00
Quentin Schulz
218cbc4b12 cmd: ufetch: only show comma separator if there was a previous feature
Currently, if NET is disabled, the next feature to be printed will start
with a comma and a space which is not pretty. Add the comma and
whitespace only when a previous feature has already been shown.

Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://patch.msgid.link/20260505-ufetch-net-v3-2-eee5eb9ca5ce@cherry.de
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2026-05-18 11:04:14 +02:00
Quentin Schulz
53e6ccc0c1 cmd: ufetch: show net feature when NET_LWIP is selected
We've had a new lwIP networking stack for a couple of years already, so
let's show there is a "net" feature if it's selected. Since NET_LEGACY
|| NET_LWIP is the same as NET, let's check on NET.

Reported-by: Simon Glass <sjg@chromium.org>
Closes: https://lore.kernel.org/u-boot/CAFLszTgZC1FGy8965pHiG-u=FhrguftRv41ghQ_Qb_RRXx6tyg@mail.gmail.com/
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Link: https://patch.msgid.link/20260505-ufetch-net-v3-1-eee5eb9ca5ce@cherry.de
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2026-05-18 11:04:14 +02:00
Timple Raj M
8fce24a418 serial: msm-geni: configure RX watermark register
The SE_GENI_RX_WATERMARK_REG was not being programmed in the RX
setup paths. Set it to DEF_RX_WM (2) in qcom_geni_serial_start_rx(),
msm_geni_serial_setup_rx() and _debug_uart_init() to align with the
Linux kernel driver behaviour.

Without this, the RX FIFO watermark interrupt threshold is left at
its hardware reset value, which may differ from the expected value
and can cause RX data loss or missed watermark interrupts.

Link: https://lore.kernel.org/all/20200227132223.864425794@linuxfoundation.org/
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
Signed-off-by: Gurumoorthy Santhakumar <gurumoorthy.santhakumar@oss.qualcomm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Csey Connolly <casey.connolly@linaro.org>
Link: https://patch.msgid.link/20260421044555.368486-1-gurumoorthy.santhakumar@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2026-05-18 11:04:14 +02:00
Aswin Murugan
c9eb2d64e2 dts: lemans-evk-u-boot: add override dtsi
Add initial support for the lemans EVK platform based on lemans SoC.
Define memory layout statically.

Signed-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Link: https://patch.msgid.link/20260424104237.968195-1-sumit.garg@kernel.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2026-05-18 11:04:14 +02:00
Balaji Selvanathan
6d2bcb6398 ufs: qcom: Remove redundant POST_CHANGE clock setup call
The ufs_qcom_init() function was calling ufs_qcom_setup_clocks() with
POST_CHANGE twice. The first call after setting PA_TXHSADAPTTYPE
correctly enables the device reference clock. The second call after
ufs_qcom_advertise_quirks() is redundant as the clock is already
enabled.

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://patch.msgid.link/20260427-ufs_clk-v2-7-36e10a7c0ef6@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2026-05-18 11:04:14 +02:00
Balaji Selvanathan
83edbe9426 drivers: ufs: qcom: Initialize and enable clocks before hardware access
Move UFS clock initialization and enabling before hardware setup
to ensure clocks are running when accessing UFS registers.

Previously, U-Boot depended on earlier bootloader stages to
initialize UFS clocks. When these bootloaders failed to do so,
UFS registers became inaccessible, causing initialization to fail.
This change makes U-Boot initialize and enable UFS clocks early
in the init sequence, removing the dependency on previous
bootloaders.

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://patch.msgid.link/20260427-ufs_clk-v2-6-36e10a7c0ef6@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2026-05-18 11:04:14 +02:00
Balaji Selvanathan
7e670b7d6e clk: qcom: sc7280: Add UFS clock support
Add UFS clock support for sc7280 including register definitions,
rate configuration, and gate clocks.

Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://patch.msgid.link/20260427-ufs_clk-v2-5-36e10a7c0ef6@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2026-05-18 11:04:13 +02:00
Balaji Selvanathan
213edfd645 clk: qcom: qcs615: Add UFS clock support
Add UFS clock support for qcs615 including register definitions,
rate configuration, and gate clocks.

Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://patch.msgid.link/20260427-ufs_clk-v2-4-36e10a7c0ef6@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2026-05-18 11:04:13 +02:00
Balaji Selvanathan
4b1580e060 clk: qcom: sa8775p: Add UFS clock support
Add UFS clock support for SA8775P including register definitions,
rate configuration, and gate clocks.

Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://patch.msgid.link/20260427-ufs_clk-v2-3-36e10a7c0ef6@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2026-05-18 11:04:13 +02:00
Balaji Selvanathan
be1dc88b4a clk: qcom: clk-stub: Add compatibles for QCS615/SA8775P
Add RPMH clock compatible strings for QCS615 and SA8775P
SoCs to enable clock framework support on these platforms.

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://patch.msgid.link/20260427-ufs_clk-v2-2-36e10a7c0ef6@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2026-05-18 11:04:13 +02:00
Balaji Selvanathan
40b43c94d2 clk: stub: Sort compatible strings alphabetically
Reorder compatible strings in stub_clk_ids to maintain alphabetical
order for easier maintenance.

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://patch.msgid.link/20260427-ufs_clk-v2-1-36e10a7c0ef6@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2026-05-18 11:04:13 +02:00
Peter Collingbourne
0646ee0ed8 fs: ubifs: remove dead code
This code is dead because it appears after an infinite loop; remove it.

Fixes: d5888d509c ("fs: ubifs: fix bugs involving symlinks in ubifs_findfile")
Signed-off-by: Peter Collingbourne <peter@pcc.me.uk>
Reviewed-by: Heiko Schocher <hs@nabladev.com>

hs: corrected the commit ID
2026-05-18 09:19:56 +02:00
Vincent Stehlé
5824ed13bc efi_selftest: test hii keyboard layouts more
The HII database test for keyboard layouts register two package lists with
two keyboard layouts each, but the test verifies only the GUID of the first
keyboard layout.
This does not catch the bugs happening with the keyboard layouts after the
first one in a package.

Verify all the keyboard layout GUIDs in the unit test to prevent this.

Signed-off-by: Vincent Stehlé <vincent.stehle@arm.com>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Cc: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Cc: Tom Rini <trini@konsulko.com>
2026-05-18 08:38:16 +02:00
Vincent Stehlé
ec95a60d9d efi_loader: fix hii keyboard layout pointer computation
The EFI_HII_KEYBOARD_LAYOUT field `layout_length' is expressed in bytes,
but we add it to the `layout' pointer with (scaled) pointer arithmetic.
When adding an HII keyboard package with multiple keyboard layouts, this
results in only the first layout being added correctly; fix it.

Fixes: 8d3b77e36e ("efi: hii: add keyboard layout package support")
Signed-off-by: Vincent Stehlé <vincent.stehle@arm.com>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Cc: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Cc: Tom Rini <trini@konsulko.com>
Cc: AKASHI Takahiro <akashi.tkhro@gmail.com>
2026-05-18 08:38:16 +02:00
Quentin Schulz
e49c84f7bb doc: usage: cmd: reset: specify when the -edl option is available
The option is only available when CONFIG_SYSRESET_QCOM_PSCI is enabled,
so let's make that explicit in the boot cmd documentation.

Due to the implementation in drivers/sysreset/sysreset-uclass.c
do_reset() function, all options to the reset command are passed to all
sysreset drivers' sysreset_ops.request_arg callback (including -w) which
is only available when CONFIG_SYSRESET_CMD_RESET_ARGS=y. -w, however,
works also without this option.

Fixes: ef06c5d76f ("cmd: boot: Add '-edl' option to reset command documentation")
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2026-05-18 08:37:13 +02:00
Quentin Schulz
fe725640ec doc: usage: cmd: reset: fix typo
"Do warm WARM" doesn't mean anything, I'm assuming the intent was to say
"Do WARM reset" so reword.

Fixes: 34e452dd02 ("doc: usage: Group all shell command docs into cmd/ sub-directory")
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2026-05-18 08:37:13 +02:00
Quentin Schulz
1076feb8a3 cmd: boot: fix edl being shown when not supported
edl is implemented in the sysreset_ops.request_arg callback of the
qcom-psci sysreset driver. That callback is only called from
sysreset_request_arg() which is compiled only when
CONFIG_SYSRESET_CMD_RESET_ARGS=y.

Therefore, only show the edl option if that symbol is enabled.

It is in a separate if block because any option but -w will only be
handled when CONFIG_SYSRESET_CMD_RESET_ARGS=y as seen with the
implementation in do_reset() in drivers/sysreset/sysreset-uclass.c.

Fixes: ef06c5d76f ("cmd: boot: Add '-edl' option to reset command documentation")
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2026-05-18 08:37:13 +02:00
Harsimran Singh Tungal
d0d1c4a4f5 efi_loader: fix AllocatePages overlap status
Return EFI_NOT_FOUND for EFI_ALLOCATE_ADDRESS overlap

When efi_allocate_pages() is called with EFI_ALLOCATE_ADDRESS, UEFI
expects EFI_NOT_FOUND if the requested address range is already
allocated or unavailable. U-Boot currently returns
EFI_OUT_OF_RESOURCES when efi_update_memory_map() detects an overlap
after a successful lmb_alloc_mem(), which does not match
EFI_ALLOCATE_ADDRESS semantics.

Return EFI_NOT_FOUND for EFI_ALLOCATE_ADDRESS requests that fail due
to an overlapping EFI memory descriptor, while keeping
EFI_OUT_OF_RESOURCES for other allocation types.

The UEFI specification [1] specifies that
EFI_BOOT_SERVICES.AllocatePages must return EFI_NOT_FOUND when the
requested address range is unavailable or already allocated;
EFI_OUT_OF_RESOURCES applies to non‑address‑specific allocation
failures.

[1] https://uefi.org/specs/UEFI/2.10_A/07_Services_Boot_Services.html

Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>

The UEFI specification does not clearly specify the behavior.
But let's follow the EDK II precedent here.

Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2026-05-18 08:32:58 +02:00
Tom Rini
dc4dd58926 Merge tag 'u-boot-imx-next-20260515' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx into next
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/30134

- Several conversions to OF_UPSTREAM.
- Added i.MX9 Quickboot support.
- Added support for i.MX952 in the fsl_enetc driver.
- Update i.MX91 part number detection.
2026-05-15 17:32:13 -06:00
Tom Rini
9704971031 Merge patch series "configs: airoha: an7581: defconfig fixes & improvements"
Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> says:

This patch series fixes an7581_evb_defconfig.

Link: https://lore.kernel.org/r/20260427135326.773903-1-mikhail.kshevetskiy@iopsys.eu
2026-05-15 17:08:16 -06:00
Mikhail Kshevetskiy
0fcbe38192 configs: airoha: an7581: disable ENV_IS_IN_MTD to avoid boot panic
Booting image generated with

  make an7581_evb_defconfig

will results in

  U-Boot 2026.04-00924-gfb815bd8793b (Apr 27 2026 - 15:08:30 +0300)

  CPU:   Airoha AN7581
  DRAM:  512 MiB
  Core:  35 devices, 19 uclasses, devicetree: separate
  MMC:   mmc@1fa0e000: 0
  Loading Environment from MMC... *** Warning - No block device, using default environment

  Loading Environment from MTD... *** Warning - get_mtd_device_nm() failed, using default environment

  BUG at drivers/mtd/mtdcore.c:898/__put_mtd_device()!
  BUG!
  resetting ...

This happens because no any mtd partition defined in dts/mtdparts.
Disabling of ENV_IS_IN_MTD fixes an issue.

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
2026-05-15 17:08:11 -06:00
Mikhail Kshevetskiy
7bb8c707b1 configs: airoha: an7581: enable position independent code
This enables U-Boot loading from any 4K aligned address.
It makes U-Boot debugging a bit simpler.

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
2026-05-15 17:08:11 -06:00
Ye Li
9e46861a01 net: fsl_enetc: Add support for i.MX952
Extend ENETC driver to support i.MX952 platform where 2 ENETC
controllers are located on different PCIe buses.

Key changes:
- Add enetc_dev_id_imx() to derive device ID from device tree "reg"
  property for i.MX952, mapping bus_devfn values 0x0 and 0x100 to device
  IDs 0 and 1 respectively
- Implement imx952_netcmix_init() to configure MII protocol and PCS
  settings based on PHY mode parsed from device tree
- Add i.MX952 to FSL_ENETC_NETC_BLK_CTRL Kconfig dependencies

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2026-05-15 17:31:40 -03:00
Clark Wang
11af22cd1e net: fsl_enetc: fix the duplex setting on the iMX platform
The iMX and LS platforms use different bits in the same register to
set duplex, but their logics are opposite.
The current settings will result in unexpected configurations in
RGMII mode.

Fixes: e6df2f5e22 ("net: fsl_enetc: Update enetc driver to support i.MX95")
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Reviewed-by: Tim Harvey <tharvey@gateworks.com>
2026-05-15 17:31:40 -03:00
Ye Li
a8684df5ed arm: imx9: Update i.MX91 part number detection
Change to not use NXP_RECOG fuse, but detect part number according
to feature disable fuses and SPEED fuse.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2026-05-15 17:31:40 -03:00
Ye Li
3ebee64e81 imx: priblob: Fix build break
Add config.h to fix CAAM_BASE_ADDR undeclared build error when
CONFIG_CMD_PRIBLOB enabled.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2026-05-15 17:31:39 -03:00
Francois Berder
1b0c1407d8 power: regulator: pfuze100: Fix unchecked pmic_reg_read, return value
pmic_reg_read returns a negative value if an error occurs. This
commit adds a missing check after calling pmic_reg_read.

Signed-off-by: Francois Berder <fberder@outlook.fr>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2026-05-15 17:31:39 -03:00
Peng Fan
cbd2dc2bdd arm: mx6: module_fuse: update node path for Linux 6.13
Update node path for 5.10 Kernel.
 - aips-bus renamed to bus
 - gpmi-nand renamed to nand-controller

cherry picked from https://github.com/nxp-imx/uboot-imx,
tag lf-6.12.3-1.0.0,
commit feb8178e97d4 ("LF-2637 mx6: fuse: update node path")

add changes node path for Linux 6.13

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Max Merchel <Max.Merchel@ew.tq-group.com>
2026-05-15 17:31:39 -03:00
Marek Vasut
5efdfae304 arm: mx6: cm-fx6: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2026-05-15 17:31:39 -03:00
Antoine Gouby
454e72874f board: toradex: verdin-imx95: remove gpio1 reg
The RGPIO2P driver contains legacy handling for compatible combinations
that expose two reg ranges (dual base) for i.MX8ULP and i.MX93.

The i.MX95 GPIO controller exposes a single register range, so the
dual-base handling is unnecessary.

Additionally, the second address of the gpio1 reg property was wrong.
When used, it needs to be offsetted by 0x40 to start at the Port Data
Output register.

Fixes: 60d8255d8d ("board: toradex: add Toradex Verdin iMX95")
Signed-off-by: Antoine Gouby <antoine.gouby@toradex.com>
2026-05-15 17:31:39 -03:00
Antoine Gouby
85319b2e67 board: toradex: smarc-imx95: remove gpio1 reg
The RGPIO2P driver contains legacy handling for compatible combinations
that expose two reg ranges (dual base) for i.MX8ULP and i.MX93.

The i.MX95 GPIO controller exposes a single register range, so the
dual-base handling is unnecessary.

Signed-off-by: Antoine Gouby <antoine.gouby@toradex.com>
2026-05-15 17:31:39 -03:00
Simona Toaca
dffae7d2a6 doc: board: nxp: Add Quickboot documentation
Add instructions on how to use U-Boot to save
DDR training data to NVM and explain the saving
process.

Signed-off-by: Simona Toaca <simona.toaca@nxp.com>
2026-05-15 17:31:39 -03:00
Simona Toaca
b37fa572ad board: nxp: imx9{4, 5, 52}_evk: Add qb save option in SPL
Call qb save automatically in the board-specific
spl_board_init(), if SPL_IMX_QB option is enabled.
This makes sure qb_save is called before any image
loading is done by the SPL. This option is also
suitable for the case where U-Boot proper is
missing (Falcon mode).

qb save refers to saving DDR training data to NVM,
so that OEI runs Quickboot flow on next reboot,
skipping full training and achieveing a lower boot
time.

Signed-off-by: Simona Toaca <simona.toaca@nxp.com>
2026-05-15 17:31:39 -03:00
Simona Toaca
36755f64b3 arm: mach-imx: Add command to expose QB functionality
This command exposes 3 methods:
- check -> checks if the data in volatile memory is valid
	   (integrity check)
- save  -> saves the data to non-volatile memory and
	   erases the data in volatile memory
- erase	-> erases the data in non-volatile memory

cmd_qb can be used either directly in the U-Boot console
or in an uuu script to save the QB data during flashing.
It supports specifying a different boot medium than the
current boot device for saving the data.

Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Simona Toaca <simona.toaca@nxp.com>
2026-05-15 17:31:39 -03:00
Simona Toaca
c9a8f673e0 imx9: Add support for saving DDR training data to NVM
DDR training data can be saved to NVM and be available
to OEI at boot time, which will trigger QuickBoot flow.

U-Boot only checks for data integrity (CRC32), while
OEI is in charge of authentication when it tries to
load the data from NVM.

On iMX95 A0/A1, 'authentication' is done via another
CRC32. On the other SoCs, authentication is done by
using ELE to check the MAC stored in the ddrphy_qb_state
structure.

Supported platforms: iMX94, iMX95, iMX952 (using OEI)
Supported storage types: eMMC, SD, SPI flash.

Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Simona Toaca <simona.toaca@nxp.com>
2026-05-15 17:31:39 -03:00
Ye Li
84a17fea21 imx: ahab: Use authenticated header for images loading
When loading container image, the container header is loaded into
heap memory. If ahab is enabled, the header is be copied to another
fixed RAM for authentication in ahab_auth_cntr_hdr. The better method
is using container header memory being authenticated for following
image loading.
So update ahab_auth_cntr_hdr to return the address of container header
being authenticated. Caller uses this header for following parsing
and image loading.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2026-05-15 17:31:39 -03:00
Ye Li
6b9813ff88 imx9: clock: Fix missing break in get_clk_src_rate
The break is missed for ARM_PLL_CLK in get_clk_src_rate.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2026-05-15 17:31:39 -03:00
Jacky Bai
5841eff4d2 imx8mp_evk: Fix the ND mode VDD_SOC voltage
The 'CONFIG_IS_ENBLAED' check only works when there is a
CONFIG_SPL_IMX8M_VDD_SOC_850MV config a option is defined and enabled.
So use the 'IS_ENABLED' macro instead to fix the ND mode VDD_SOC voltage.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2026-05-15 17:31:39 -03:00
Ye Li
6bc840568f i2c: imx_lpi2c: Fix MSR status check issue in STOP
In bus_i2c_stop, the MSR SDF is checked in a loop after stop command
is sent. Meanwhile, some error status in MSR is also checked by
imx_lpci2c_check_clear_error. But the imx_lpci2c_check_clear_error
will clear the MSR.

It causes problem in below situation:
In current loop, SDF does not set, but error status is found by
imx_lpci2c_check_clear_error (for example, NDF), then NDF will be cleared
and result has NDF error. However, because SDF does not set in this loop,
it goes not next loop. When SDF is set in next loop,
imx_lpci2c_check_clear_error is re-executed, but as the MSR is cleared,
the result is 0. Then the stop return 0. But it should return NDF error.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2026-05-15 17:31:39 -03:00
Ye Li
39f52b7c29 net: phy: nxp-c45-tja11xx: Fix incorrect usage of devm_kzalloc
devm_kzalloc needs to pass udevice for first parameter, this phy driver
wrongly pass the priv in phy_device. And because the dev in phy_device
is only valid after phy_connect, in probe phase this dev is NULL, so
we can't use devm_kzalloc, replace it with kzalloc.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2026-05-15 17:31:39 -03:00
Ye Li
f745c1ab4e imx9: scmi: Support iMX95/94/952 secondary boot
When ROM boots from secondary container set, SPL should select
correct offset to load u-boot-atf container.
The implementation uses ROM passover information:
1) For non-eMMC boot partition device, use image offset in ROM
   passover data to get u-boot-atf container offset.
2) For eMMC boot partition device, use boot stage (secondary)
   in ROM passover data to select correct eMMC boot partition
   for u-boot-atf container.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2026-05-15 17:31:39 -03:00
Fedor Ross
9dd6b95453 imx9: scmi: soc: Add support for detecting primary/secondary bmode on MX95
Implement the 'getprisec' subcommand of 'bmode' command for i.MX95 by
reading out the ROM log events. This event is set by the BootROM if it
switched to the secondary copy due to primary copy being corrupted.

Signed-off-by: Fedor Ross <fedor.ross@ifm.com>
Reviewed-by: Marek Vasut <marex@nabladev.com>
2026-05-15 17:31:39 -03:00
Marek Vasut
c8ca3314f2 imx: Add SPI NOR A/B switching support
Query the SM via SCMI, obtain rom_passover_t->img_set_sel and based on
that, add 0 or 0x400000 offset (A or B copy offset) to boot container
read address.

Signed-off-by: Marek Vasut <marex@nabladev.com>
Signed-off-by: Fedor Ross <fedor.ross@ifm.com>
2026-05-15 17:31:39 -03:00
Peng Fan
e1a7afcf92 imx8mm/n: Drop unused dtsi
imx8m[m,n]-beacon-baseboard.dtsi was missed to be deleted in
commit f5585124c9 ("arm64: imx: imx8mm-beacon: Migrate to OF_UPSTREAM")
commit a64feb974f ("arm64: imx: imx8mn-beacon: Migrate to OF_UPSTREAM")

arch/arm/dts/imx8mn-evk.dtsi was missed to be deleted in
commit 73d57e0aa4 ("imx: imx8mn-evk: convert to OF_UPSTREAM")

Drop them.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-05-15 17:31:39 -03:00
Peng Fan
d4817ba78e imx8mq: Drop arch/arm/dts/imx8mq.dtsi
scripts/Makefile.lib already handles the including path for imx8mq.dtsi
from dts/upstream. No need to keep a copy in arch/arm/dts/, and there
is very minimal changes compared with the one in dts/upstream, so remove
the copy.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-05-15 17:31:39 -03:00
Peng Fan
d91270ae82 imx8mq: kontron-pitx-imx8m: Switch OF_UPSTREAM
arch/arm/dts/imx8mq-kontron-pitx-imx8m.dts is almost same as upstream Linux
dts, so switch to OF_UPSTREAM by dropping the U-Boot copy of the dts,
enabling OF_UPSTREAM and updating CONFIG_DEFAULT_DEVICE_TREE.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-05-15 17:31:39 -03:00
Peng Fan
aef4690324 imx8mq: librem5: Switch to OF_UPSTREAM
arch/arm/dts/imx8mq-librem5-r[4,3].dts is almost same as upstream Linux dts,
and arch/arm/dts/imx8mq-librem5.dtsi is out of sync with upstream linux
dts, but it should not break U-Boot after using OF_UPSTREAM. So switch to
OF_UPSTREAM by dropping the U-Boot copy of the dts, enabling OF_UPSTREAM and
updating CONFIG_DEFAULT_DEVICE_TREE.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-05-15 17:31:39 -03:00
Peng Fan
3893fdcf63 imx8mq: pico: Switch OF_UPSTREAM
arch/arm/dts/imx8mq-pico-pi.dts is almost same as upstream Linux dts,
so switch to OF_UPSTREAM by dropping the U-Boot copy of the dts,
enabling OF_UPSTREAM and updating CONFIG_DEFAULT_DEVICE_TREE.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-05-15 17:31:39 -03:00
Peng Fan
f80ec8cfd7 imx8mq: phanbell: Switch OF_UPSTREAM
arch/arm/dts/imx8mq-phanbell.dts is almost same as upstream Linux dts,
so switch to OF_UPSTREAM by dropping the U-Boot copy of the dts,
enabling OF_UPSTREAM and updating CONFIG_DEFAULT_DEVICE_TREE.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-05-15 17:31:39 -03:00
Peng Fan
1eb024281f imx8mq: reform2: Switch to OF_UPSTREAM
arch/arm/dts/imx8mq-mnt-reform2.dts are almost same as upstream Linux
imx8mq-mnt-reform2.dts, so switch to OF_USPTREAM for this board, with
only updating imx8mq-mnt-reform2-u-boot.dtsi to keep "simple-panel"
compatible string for display panel.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-05-15 17:31:39 -03:00
Jacky Cao
ba80ed218d nitrogen6x: Fix compile error if VIDEO_IPUV3 is disabled
Following compile error happens for mx6qsabrelite when disable
CONFIG_VIDEO_IPUV3.

board/boundary/nitrogen6x/nitrogen6x.c: In function 'misc_init_r':
board/boundary/nitrogen6x/nitrogen6x.c:912:22: error: 'RGB_BACKLIGHT_GP' undeclared (first use in this function)
  912 |         gpio_request(RGB_BACKLIGHT_GP, "lvds backlight");
      |                      ^~~~~~~~~~~~~~~~
board/boundary/nitrogen6x/nitrogen6x.c:912:22: note: each undeclared identifier is reported only once for each function it appears in
  CC      cmd/bind.o
  CC      drivers/gpio/gpio-uclass.o
  CC      boot/bootmeth_extlinux.o
board/boundary/nitrogen6x/nitrogen6x.c:913:22: error: 'LVDS_BACKLIGHT_GP' undeclared (first use in this function)
  913 |         gpio_request(LVDS_BACKLIGHT_GP, "lvds backlight");
      |                      ^~~~~~~~~~~~~~~~~
  AR      arch/arm/lib/lib.a
make[1]: *** [scripts/Makefile.build:271: board/boundary/nitrogen6x/nitrogen6x.o] Error 1
  CC      boot/bootmeth_pxe.o
make: *** [Makefile:2205: board/boundary/nitrogen6x] Error 2
make: *** Waiting for unfinished jobs....

To fix this, use reported macros included in CONFIG_VIDEO_IPUV3.

Fixes: 1b51e5f4cd ("nitrogen6x: reserve used gpios")

Signed-off-by: Jacky Cao <Jacky.Cao@sony.com>
Reviewed-by:  Simon Gaynor <simon.gaynor@ezurio.com>
2026-05-15 17:31:39 -03:00
Marek Vasut
94a9680b62 MAINTAINERS: Use N: for NXP entry
Reduce the NXP MAINTAINERS entry by using N: entry glob.

Signed-off-by: Marek Vasut <marex@nabladev.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2026-05-15 17:31:38 -03:00
Tom Rini
a6f6947e43 Merge tag 'mmc-next-2026-05-15' of https://source.denx.de/u-boot/custodians/u-boot-mmc into next
CI: https://source.denx.de/u-boot/custodians/u-boot-mmc/-/pipelines/30112

- Staticize and constify driver ops patches from Marek
- Check 'no-1-8-v' property in cv1800b_sdhci driver
- Drop unecessary timer initialization for sdhci
2026-05-15 08:18:49 -06:00
Mark Kettenis
215496fec5 smbios: Do not fall back on devicetree without valid mapping
The smbios_get_val_si() function may get called for a sysinfo
property for which there is no mapping to a devicetree property.
Avoid a NULL pointer dereference in this case by skipping the
read of the mapped property from the device tree.

Fixes: 83b28b55d7 ("smbios: add support for dynamic generation of Type 9 system slot tables")
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Raymond Mao <raymondmaoca@gmail.com>
2026-05-15 08:18:11 -06:00
Tom Rini
f3af40cff9 Merge tag 'fsl-qoriq-for-2026.07-rc3' of https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq
CI: https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq/-/pipelines/30120

- Various fix/improvments for powerpc
- Correct usage of number of memory banks for nxp and ten64
- Staticize and constify scmi sandbox driver ops
2026-05-15 08:15:32 -06:00
Marek Vasut
8bd84cca34 firmware: scmi: sandbox: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-05-15 19:28:31 +08:00
Vincent Jardin
43257fa9e3 board: nxp: common: support CONFIG_FSL_USE_PCA9547_MUX
Use select_i2c_ch_pca9547() only when CONFIG_FSL_USE_PCA9547_MUX
is set, but several call in board/nxp/lx2160a/lx2160a.c invoke
it unconditionally,
or using unrelated Kconfigs (CONFIG_EMC2305, CONFIG_VID).

Compilation with LX2160A target that omits the mux therefore fails with

  error: implicit declaration of function 'select_i2c_ch_pca9547'

Add a static inline stub with -EOPNOTSUPP for the
!CONFIG_FSL_USE_PCA9547_MUX case so all cases compile cleanly.

Adapted from the convention used by include/scmi_nxp_protocols.h for
SCMI subprotocol stubs.

There is no functional change for NXP boards: all eight upstream
LX2160A defconfigs (lx2160ardb / lx2160aqds / lx2162aqds and their
secure / stmm / verified_boot variants) already set
CONFIG_FSL_USE_PCA9547_MUX=y, so the real declaration wins.

The purpose is to support new boards that do not use the PCA9547.

Signed-off-by: Vincent Jardin <vjardin@free.fr>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-05-15 19:28:31 +08:00
Vincent Jardin
7252890625 board: nxp: lx2160a: without QIXIS, MC-ENET, PCI, LTC3882
The shared LX2160A board file calls helpers that only exist when
their subsystem is enabled. Gate them on the matching CONFIG_*:
 - pci_init() under CONFIG_PCI.
 - fdt_fixup_mc_ddr() and fsl_rgmii_init() under CONFIG_FSL_MC_ENET.
 - qixis_*() and the QIXIS branch of checkboard() under
   CONFIG_FSL_QIXIS; cpu_name(buf) moves out so the non-QIXIS path
   still prints "Board: <name>".
 - EVENT_SPY_SIMPLE on init_func_vid moves inside the
   CONFIG_VOL_MONITOR_LTC3882_READ guard (was outside, dangling
   symbol when LTC3882 off).

 #if / #ifdef, not IS_ENABLED(), because the helpers are themselves
conditionally compiled.

While here, lx2160a_common.h: fix BOOT_TARGET_DEVICES_MMC
1 arg vs 2 args and gate the MMC target on CONFIG_CMD_MMC,
not CONFIG_MMC.

No functional change for NXP boards: LX2160ARDB, LX2160AQDS, or
LX2162AQDS, but mainly build clean up in order to support
other NXP lx2160a boards without those HW dependencies.

Signed-off-by: Vincent Jardin <vjardin@free.fr>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-05-15 19:28:31 +08:00
Francois Berder
12cf77821d board: ten64: Fix OOB read in ft_board_setup
base and size arrays can both contain up to total_memory_banks
elements.
This commit fixes the for loop condition to ensure that it does
not attempt to read past the end of both arrays.

Signed-off-by: Francois Berder <fberder@outlook.fr>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-05-15 19:28:31 +08:00
Francois Berder
408cab5f9d board: nxp: Fix OOB read in ft_board_setup
base and size arrays can both contain up to total_memory_banks
elements.
This commit fixes the for loop condition to ensure that it does
not attempt to read past the end of both arrays.

Signed-off-by: Francois Berder <fberder@outlook.fr>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-05-15 19:28:31 +08:00
Michael Walle
9a621ea635 p2041rdb: convert README to rst
Convert the README to reST format.

Signed-off-by: Michael Walle <mwalle@kernel.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-05-15 19:28:31 +08:00
Peng Fan
b8124202d7 p2041rdb: remove NAND defconfig
The RDB doesn't support NAND boot at all, remove the config for it.
Apparently, it was introduced by commit dd84058d24 ("kconfig: add
board Kconfig and defconfig files") which ran some scripts. Maybe that
script was wrong or the source boards.cfg was wrong. In any case, there
is no NAND flash on the RDB.

Signed-off-by: Michael Walle <mwalle@kernel.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-05-15 19:28:31 +08:00
Michael Walle
f0e57510cf p2041rdb: update README and fix typos
Nowadays, u-boot can build the pbl image itself. Refer to that image in
the documentation. Also fix some typos.

Signed-off-by: Michael Walle <mwalle@kernel.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-05-15 19:28:30 +08:00
Michael Walle
656dc03812 p2041rdb: support SDcard boot
The RCW was just supporting SPI boot. Add a second one for the SDcard
boot. While at it, use the same naming scheme as for the other NXP
boards.

Signed-off-by: Michael Walle <mwalle@kernel.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-05-15 19:28:30 +08:00
Michael Walle
4839ba9045 p2041rdb: use the upstream device tree
Switch to the upstream device tree, which already includes the UART
nodes we need for the DM.

We also need to increase malloc area before relocation otherwise you'll
get the following error and the board panics:

	DRAM:  Initializing....using SPD
	alloc space exhausted ptr 414 limit 400

Signed-off-by: Michael Walle <mwalle@kernel.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-05-15 19:28:30 +08:00
Michael Walle
e742f676e5 boards/nxp: remove empty fdt_fixup_board_enet()
Remove any empty function which is just called by the board code. There
is no need to define this function at all.

Signed-off-by: Michael Walle <mwalle@kernel.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-05-15 19:28:30 +08:00
Michael Walle
6af1851cb6 boards/nxp: remove board_eth_init()
board_eth_init() is dead code since commit e524f3a449 ("net: Remove
eth_legacy.c"). Remove it.

I'm not sure, all the shenanigans are covered by the new DM-version. The
MDIO mux and iomux controls probably are. The fman configuration
probably isn't. OTOH, nobody cared for years and the called
fm_info_set_phy_address() was also removed years ago.

This also removes fdt_fixup_board_enet() for the ls1043a and ls1046a
because it relies on the local variable "mdio_mux" being initialized by
the board_eth_init().

Signed-off-by: Michael Walle <mwalle@kernel.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-05-15 19:28:30 +08:00
Michael Walle
5a39262a4a boards: remove dead fman code
Commit cc2bf624eb ("net: fm: Remove non-DM_ETH code") removed the call
to board_ft_fman_fixup_port(). Thus remove the dead code in the board
files.

I'm not sure, all that DT shenanigans are covered by the new DM-version
of the fman code, but it seems no one complained for the past 4 years.

Signed-off-by: Michael Walle <mwalle@kernel.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-05-15 19:28:30 +08:00
Michael Walle
cae1cfe2ca spi: fsl_espi: fix read transactions
Since commit 7917c2e356 ("spi: fsl_espi: fix din offset") MTD is
basically broken because any read transaction will get wrong data. While
the commit in question will fix simple transfers (where both
SPI_XFER_BEGIN and SPI_XFER_END is set), it will break the most common
case, where opcode and address is send first and then data comes as a
second transfer.

This basically reverts commit 7917c2e356 ("spi: fsl_espi: fix din
offset") and make the fix particular for this simple case. Instead of
providing two buffers for reading and writing, just malloc one which is
used for both. This will work because the data is first written on the
SPI bus and then it will be read (and overwite the written data) into
the same buffer.

Suggested-by: Tomas Alvarez Vanoli <tomas.alvarez-vanoli@hitachienergy.com>
Fixes: 7917c2e356 ("spi: fsl_espi: fix din offset")
Signed-off-by: Michael Walle <mwalle@kernel.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-05-15 19:28:30 +08:00
Michael Walle
09bc47cc33 caam: don't write memory at 0 on PPC
For non-secure boot environments pamu_init() isn't called but the CAAM
will still call sec_config_pamu_table() -> config_pamu() which then uses
an uninitialized ppaact variable. In fact, that variable is initialized
with 0, so the config_pamu() will happily assume the structure is there
and will operate on that memory. Call pamu_init() in the non-secure boot
case, too.

Signed-off-by: Michael Walle <mwalle@kernel.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-05-15 19:28:29 +08:00
Michael Walle
674f35a884 powerpc: fix call to cpu_init_r
Commit 6c171f7a18 ("common: board: make initcalls static") broke the
call to cpu_init_r. That is because PPC is already defined to 1, see:

  powerpc-linux-gnu-gcc -dM -E - < /dev/null

This will conflict with the CONFIG_IS_ENABLED(PPC). Change it to
IS_ENABLED(CONFIG_PPC).

Fixes: 6c171f7a18 ("common: board: make initcalls static")
Signed-off-by: Michael Walle <mwalle@kernel.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-05-15 19:28:29 +08:00
Marek Vasut
77fa442ff5 power: domain: zynqmp: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-05-15 11:47:23 +08:00
Marek Vasut
f89d17c360 power: domain: tegra186: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-05-15 11:47:23 +08:00
Marek Vasut
1aea809ba2 power: domain: scmi: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-05-15 11:47:23 +08:00
Marek Vasut
d82d49e1a6 power: domain: sandbox: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-05-15 11:47:23 +08:00
Marek Vasut
b51735a38a power: domain: mtk: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: David Lechner <dlechner@baylibre.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-05-15 11:47:22 +08:00
Marek Vasut
2e59c9fa4f power: domain: meson-secure-pwrc: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-05-15 11:47:22 +08:00
Marek Vasut
4f87439ed4 power: domain: meson-gx-pwrc: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-05-15 11:47:22 +08:00
Marek Vasut
ad9ca3e776 power: domain: meson-ee-pwrc: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-05-15 11:47:22 +08:00
Marek Vasut
f82c349b91 power: domain: imx8mp-mediamix: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-05-15 11:47:22 +08:00
Marek Vasut
10c5b89e21 power: domain: imx8m: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-05-15 11:47:22 +08:00
Marek Vasut
77a8a30ef8 power: domain: imx8: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-05-15 11:47:22 +08:00
Marek Vasut
2e8078e5d5 power: domain: imx8-legacy: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-05-15 11:47:21 +08:00
Marek Vasut
e6c69731c9 power: domain: bcm6328: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-05-15 11:47:21 +08:00
Marek Vasut
0e7a86e0cf power: domain: apple: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-05-15 11:47:21 +08:00
Hiago De Franco
3a4a8963aa mmc: cv1800b_sdhci: honor 'no-1-8-v' DT property
CV1800B SDHCI controller does support 1.8V, however, boards like
MilkV-Duo 256M do not have a VCCIO 1.8V regulator (the bus is wired for
3.3V only).

These boards set 'no-1-8-v' in their device tree, and mmc_of_parse()
does respect this property. Later, when sdhci_setup_cfg() is called, it
reads SDHCI_CAPABILITIES_1 from the hardware and unconditionally adds
the UHS caps again based on what the controller advertises. Since the
board cannot switch to 1.8V, the host issues CMD11 (voltage switch
request), the card transitions, but the bus stays at 3.3V. The SD card
stops responding until the next power cycle.

Before calling sdhci_setup_cfg(), set the SDHCI_QUIRK_NO_1_8_V quirk
when 'no-1-8-v' is present. The quirk causes the SDR104/SDR50/DDR50 bits
to be masked out of the caps, allowing the card to initialize properly.

This matches the pattern used by zynq_sdhci.

Fixes: eb36f28ff7 ("mmc: cv1800b: Add sdhci driver support for cv1800b SoC")
Signed-off-by: Hiago De Franco <hfranco@baylibre.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-05-15 11:46:39 +08:00
Marek Vasut
993c405ed7 power: pmic: emul: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-05-15 11:46:04 +08:00
Marek Vasut
b487d05633 mmc: bootstd: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-05-15 11:45:40 +08:00
Tanmay Kathpalia
731a875ae7 mmc: sdhci: Start status timeout after command issue
The status polling timeout in sdhci_send_command() should measure the
time spent waiting for the command interrupt after the command has been
issued.

Do not initialize the timer at function entry, since the command inhibit
wait and setup path can consume time before SDHCI_COMMAND is written.
Start the timer immediately after issuing the command instead.

Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-05-15 11:44:58 +08:00
Charles Perry
88338f9d14 gpio: Correct dependencies for MCP230xx
This driver depends on DM_I2C and DM_SPI, add it.

Fixes: 3b639f6438 ("gpio: mcp230xx: Add support for models with SPI interface.")
Signed-off-by: Charles Perry <charles.perry@microchip.com>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
2026-05-14 15:54:17 -06:00
Parvathi Pudi
55e767426e board: ti: am335x: Conditional MDIO PAD configuration instead of static for AM335_ICE
This patch removes the static MDIO pinmux configuration from
rmii1_pin_mux[] and instead configures the MDIO pins conditionally
during board_init(). Previously, the MDIO_CLK and MDIO_DATA pins
were always configured for CPSW in mux.c, which could lead to
unnecessary pin ownership and conflicts in scenarios where CPSW
is not used.

With this change, the MDIO pins are configured only when required,
ensuring that CPSW Ethernet functionality in U-Boot remains unaffected.
This approach keeps Ethernet boot behavior intact and provides cleaner
separation between CPSW and other Ethernet use cases.

Reviewed-by: Markus Schneider-Pargmann (TI) <msp@baylibre.com>
Signed-off-by: Parvathi Pudi <parvathi@couthit.com>
2026-05-14 15:41:07 -06:00
Ronan Dalton
4660602522 rtc: ds1307: Handle oscillator stop flag set on ds1339 chip
Currently the oscillator stop flag (OSF) bit is never checked or cleared
on the DS1339 RTC chip.

On getting the time from the RTC, check if the OSF bit is set, log a
warning, and clear the flag. This matches the behavior of the DS1337
chip.

Note that the `date` command always reads from the RTC even when
setting or resetting the date, so the OSF flag is cleared in those cases
as well.

Signed-off-by: Ronan Dalton <ronan.dalton@alliedtelesis.co.nz>
Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Francesco Dolcini <francesco.dolcini@toradex.com>
Cc: Mark Tomlinson <mark.tomlinson@alliedtelesis.co.nz>
Cc: Chris Packham <chris.packham@alliedtelesis.co.nz>
Reviewed-by: Simon Glass <sjg@chromium.org>
2026-05-14 15:40:52 -06:00
Tom Rini
9a13d08732 Merge patch series "test: Quote variables in 'test -n' expressions across boards"
Simon Glass <sjg@chromium.org> says:

Several boards use 'test -n ${var}' (unquoted) in env scripts to detect
an empty variable and trigger a fallback or skip a hook. That works only
because of a U-Boot 'test' quirk where calls with argc < 3 returned
false; an empty variable made the expression 'test -n' (one operand) and
hit that path.

Commit 8b0619579b ("cmd: test: fix handling of single-argument form of
test") aligned 'test' with POSIX so those expressions flipped to true.
f7e7c55e53 ("cmd: test: add bug-compatibility special case for 'test
-n'") restored the old behaviour for the exact 'test -n' (one arg) case,
so the boards are not broken at runtime today, but the reliance on a
bug-compat path isn't great.

This series updates various boards to quote each affected variable so
the emptiness check is explicit and does not depend on the
special-case path.

Each commit carries a Fixes: tag pointing at 8b0619579b

Link: https://lore.kernel.org/r/20260503204936.3151124-1-sjg@chromium.org
2026-05-14 15:39:22 -06:00
Simon Glass
93d7dc20e8 aristainetos2: Quote rescue_reason in rescueboot test
The rescueboot script optionally runs a per-board rescue_reason hook
with:

    if test -n ${rescue_reason}; then run rescue_reason; fi;

The default state is "no rescue reason script", i.e. rescue_reason
unset.  The expression then expands to 'test -n' with no operand and
relies on a U-Boot 'test' quirk that treats a missing operand as
false to skip the run.

Quote the variable so an unset rescue_reason expands to 'test -n ""'
and the emptiness check is explicit.

Fixes: 8b0619579b ("cmd: test: fix handling of single-argument form of test")
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@nabladev.com>
2026-05-14 15:39:09 -06:00
Simon Glass
9458e39c65 mccmon6: Quote recovery_status in bootcmd test
The mccmon6 bootcmd starts with:

    if test -n ${recovery_status}; then run boot_recovery; ...

The default state is "no recovery requested", i.e. recovery_status
unset.  The expression then expands to 'test -n' with no operand and
relies on a U-Boot 'test' quirk that treats a missing operand as
false to skip recovery.

Quote the variable so an unset recovery_status expands to 'test -n ""'
and the emptiness check is explicit.

Fixes: 8b0619579b ("cmd: test: fix handling of single-argument form of test")
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Łukasz Majewski <lukma@nabladev.com>
2026-05-14 15:39:09 -06:00
Simon Glass
2120834c25 beaglev_fire: Quote no_of_overlays in design test
On beaglev_fire, design_overlays gates an overlay-application loop
on:

    if test -n ${no_of_overlays}; then ...

The default state is "no overlays", i.e. no_of_overlays unset. The
expression then expands to 'test -n' with no operand and relies on a
U-Boot 'test' quirk that treats a missing operand as false to skip
the loop.

Quote the variable so an unset no_of_overlays expands to 'test -n ""'
and the emptiness check is explicit.

Fixes: 8b0619579b ("cmd: test: fix handling of single-argument form of test")
Signed-off-by: Simon Glass <sjg@chromium.org>
2026-05-14 15:39:09 -06:00
Simon Glass
6b109a1304 siemens: Quote A/B flags in env tests
The Siemens am33x-common, env-common and draco-etamin headers gate
boot-partition selection logic on:

    if test -n ${A}; then ...
    if test -n ${B}; then ...

A and B are flags that the upgrade machinery sets to mark "the other
partition just became active".  The default state is unset, in which
case the expression expands to 'test -n' with no operand and relies
on a U-Boot 'test' quirk that treats a missing operand as false to
skip the branch.

Quote each variable so an unset A or B expands to 'test -n ""' and
the emptiness check is explicit.

Fixes: 8b0619579b ("cmd: test: fix handling of single-argument form of test")
Signed-off-by: Simon Glass <sjg@chromium.org>
2026-05-14 15:39:09 -06:00
Simon Glass
825f8ee2fc ti: Quote board_init in ti_common.env
bootcmd_ti_mmc skips a per-board init hook with:

    if test -n ${board_init}; then run board_init; fi;

The default case is "no board override", i.e. board_init unset. The
expression then expands to 'test -n' with no operand and relies on a
U-Boot 'test' quirk that treats a missing operand as false to skip the
run.

Quote the variable so an unset board_init expands to 'test -n ""' and
the emptiness check is explicit.

Fixes: 8b0619579b ("cmd: test: fix handling of single-argument form of test")
Signed-off-by: Simon Glass <sjg@chromium.org>
2026-05-14 15:39:09 -06:00
Emanuele Ghidoli
03d70a9220 arm: dts: k3-am69-aquila: fix combined boot firmware image build
The combined boot firmware firmware-aquila-am69-gp.bin depends on
tiboot3-am69-gp-aquila.bin, which in turn requires the GP variant
of the TI system firmware blob (ti-fs-firmware-j784s4-gp.bin).

Fix the combined boot firmware image build by adding the missing binman
nodes.

Fixes: f62d4535cf ("arm: dts: k3-am69-aquila: add combined boot firmware image")
Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
2026-05-14 07:58:14 -06:00
Tom Rini
f020dfd9bf Merge tag 'i2c-updates-for-2026.07-rc3' of https://source.denx.de/u-boot/custodians/u-boot-i2c
updates for 2026.07-rc3

- designware_i2c: Staticize driver ops from Marek
- i2c: Remove legacy CONFIG_SYS_I2C_SOFT
-
2026-05-14 07:56:53 -06:00
Tom Rini
0c464b6cc3 i2c: Remove legacy CONFIG_SYS_I2C_SOFT
The last users of this legacy i2c stack have been removed or converted
to a modern part of the stack instead. Remove this code and references
to it.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@nabladev.com>
2026-05-14 11:17:20 +02:00
Marek Vasut
5f82b15958 i2c: designware_i2c: Staticize driver ops
Set the ops structure as static. The structure is not accessible
from outside of this driver.

Reviewed-by: Heiko Schocher <hs@nabladev.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2026-05-14 11:12:56 +02:00
Tom Rini
1a0fac05c3 Merge tag 'ab-master-12052026' of https://source.denx.de/u-boot/custodians/u-boot-tpm
- A single UAF fix from Kory for out fwumdata tool
2026-05-13 07:57:51 -06:00
Tom Rini
944427c3da Merge tag 'u-boot-stm32-20260512' of https://source.denx.de/u-boot/custodians/u-boot-stm
CI: https://source.denx.de/u-boot/custodians/u-boot-stm/-/pipelines/30081

- reset: stm32: Fix compilation error
- Remove remaining non-existant STM32_RESET flag
- configs: stm32mp13: Add SPI-NAND UBI boot support
- Support metadata-driven A/B boot for STM32MP25
2026-05-13 07:54:10 -06:00
Francois Berder
c8f6823442 usb: gadget: f_acm: Fix memory leak in acm_add
If udc_device_get_by_index fails, the f_acm struct was not released.
Free it before returning the error.

Signed-off-by: Francois Berder <fberder@outlook.fr>
Reviewed-by: Marek Vasut <marek.vasut+usb@mailbox.org>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Link: https://patch.msgid.link/BESP194MB2805271AD5DBE47B322F8DC3DA3A2@BESP194MB2805.EURP194.PROD.OUTLOOK.COM
Signed-off-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
2026-05-13 13:11:07 +02:00
Tom Rini
e3e651c480 Merge patch series "add memdup_nul(), use it and memdup() in a few places"
Rasmus Villemoes <ravi@prevas.dk> says:

There are quite a few places where we allocate X+1 bytes, initialize
the first X bytes via memcpy() and then set the last byte to 0.

The kernel has a helper for that, kmemdup_nul(). Introduce a similar
one, and start making use of it in a few places. Also the existing
memdup() helper can be put to more use.

There are lots more places one could modify. But for code shared with
host tools, one would need to do some refactoring, putting memdup()
and memdup_nul() in their own str-util.c TU which could then also be
included in the tools build.

Link: https://lore.kernel.org/r/20260421075439.16696-1-ravi@prevas.dk
2026-05-12 15:41:52 -06:00
Rasmus Villemoes
8d209186a1 test: lib: add test of memdup_nul()
Add a very basic test of the new memdup_nul() helper.

Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
Reviewed-by: Simon Glass <sjg@chromium.org>
2026-05-12 15:38:00 -06:00
Rasmus Villemoes
4ef201e607 drivers/core: use memdup() instead of malloc()+memcpy()
Use memdup() instead of open-coding it.

In the dm_setup_inst() case, there was never any reason to use
calloc(), as the whole allocation is definitely initialized via the
immediately following memcpy().

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
2026-05-12 15:38:00 -06:00
Rasmus Villemoes
11168813bf common/cli.c: use memdup_nul() in run_command_list()
Use memdup_nul() instead of open-coding it.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
2026-05-12 15:38:00 -06:00
Rasmus Villemoes
b87ff4878d lib/hashtable.c: use memdup_nul() in himport_r
We have memdup_nul() for exactly this pattern of duplicating a block
of memory and ensuring there's a nul byte after the copy.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
2026-05-12 15:38:00 -06:00
Rasmus Villemoes
ee8be5d4a1 lib/string.c: implement strdup() and strndup() in terms of memdup_nul()
With the addition of memdup_nul(), strdup() and strndup() can be
implemented as one-liners.

While not required by POSIX or C, do keep the behaviour of gracefully
accepting a NULL source and simply return NULL.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
2026-05-12 15:38:00 -06:00
Rasmus Villemoes
8c664d2135 lib/string.c: introduce memdup_nul() helper
This is completely analogous to the linux kernel's kmemdup_nul()
helper, apart from the lack of the gfp_t argument: Allocate a buffer
of size {len}+1, copy {len} bytes from the given buffer, and add a
final nul byte.

This pattern exists in a number of places, so this helper can reduce
some boilerplate code.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
2026-05-12 15:38:00 -06:00
Rasmus Villemoes
349d148f16 lib/string.c: drop pointless __HAVE_ARCH_STRDUP
There has never been an arch-specific optimized implementation of
str[n]dup, nor is there likely to ever be one, because unlike their
cousins strlen(), strcpy() and similar that simply read/write the
src/dst, the dup functions by definition involve memory allocation. So
drop this irrelevant cpp guard.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
2026-05-12 15:38:00 -06:00
Rasmus Villemoes
719cacb92e stdio: drop stdio_clone
The helper stdio_clone only has a single caller, so it certainly
doesn't need to be public. But in fact, it is merely an open-coded
memdup() - which for some reason uses calloc() even if the whole
allocation is obviously immediately overwritten.

Drop it and just use memdup() directly.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
2026-05-12 15:38:00 -06:00
Rasmus Villemoes
ca1c292d2e string: fix prototype of memdup()
It doesn't make sense to restrict memdup() to only return char*
pointers, especially when it is already defined to accept void*. This
makes it uglier to use to e.g. duplicate a struct.

Make it return void*, just as kmemdup() does in the kernel (and which
our kmemdup() in fact also does).

While in here, make a small optimization: memcpy() is defined to
return the destination register, so we write this in a way that the
compiler may do a tail call.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
2026-05-12 15:38:00 -06:00
Christian Pötzsch
36d4c65358 virtio: fix return value check
The virtio_blk_do_single_req function returns ulong, which normally is
the processed size, but in an error case can be the actual error. Use
the special IS_ERR_VALUE macro to test for error.

Addresses-Coverity-ID: CID 645833 (DEADCODE) & CID 645834 (NO_EFFECT)
Signed-off-by: Christian Pötzsch <christian.poetzsch@kernkonzept.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2026-05-12 12:38:49 -06:00
Janne Grunau
a1a47eee67 arm: apple: Add Apple M3 (t8122) support
Apple's M3 SoC is similar to M1 and M2 but uses a different memory map.
The main difference is that RAM starts at 0x100_0000_0000 like on t600x
and t602x (M1 and M2 Pro/Max/Ultra). Otherwise IO blocks have been
rearranged.
U-boot's existing drivers are compatible with the hardware and M3 device
trees will carry "apple,t8103-*" compatible strings. Only
apple-atcphy-reset might need a new compatible due to USB4 / DisplayPort
changes the Linux driver has to deal with.

Signed-off-by: Janne Grunau <j@jannau.net>
Acked-by: Mark Kettenis <kettenis@openbsd.org>
2026-05-12 12:11:36 -06:00
Tom Rini
bdf4d12fc2 Merge patch series "Switch Apple silicon boards to upstream device trees"
Janne Grunau <j@jannau.net> says:

The Linux device trees for Apple silicon devices cover now most of the
hardware as u-boot's internal device trees for M1 devices. Linux has in
addition device trees M2 and M1 and M2 Pro/Max/Ultra devices which were
never added in u-boot.
The most common use case for u-boot on Apple silicon devices does not
use DTBs from u-boot but passes runtime modified device trees from an
earlier boot loader (m1n1).
This change regresses support for the SPI on M1 and M1 Pro/Max notebooks
as SPI keyboard support is not in upstream Linux. This regression is in
my opinion acceptable due to the limited use of u-boot's DTBs for these
targets.

Link: https://lore.kernel.org/r/20260507-apple-dt-upstream-v2-0-35181f2b0509@jannau.net
2026-05-12 12:11:17 -06:00
Janne Grunau
5aec4e746f arm: dts: Switch Apple silicon devices to dts/upstream
The device tree on Apple silicon devices is passed from a previous
bootloader stage. The bootloader fills in dynamic information so
u-boot can not use its own device tree.
As documented in doc/board/apple/m1.rst it is possible to build boot
bundles (bootloader + device tree + gzipped u-boot binary). These are
useful for testing.
Instead of using u-boot's own device trees for M1 (t8103) devices use
upstream device trees from dts/upstream/src/arm64/apple. The u-boot
device trees have not seen updates since 2022. The upstream linux device
trees have feature parity for the M1 devices. In addition linux has
device trees for M1 Pro/Max/Ultra, M2 and M2 Pro/Max/Ultra devices.
Keep t8103-j274 as default device tree to avoid further updates.

Signed-off-by: Janne Grunau <j@jannau.net>
Acked-by: Mark Kettenis <kettenis@openbsd.org>
2026-05-12 12:11:08 -06:00
Janne Grunau
fad7b438f0 doc: device-tree-bindings: Remove apple,pinctrl.yaml
Remove outdated apple,pinctrl.yaml. The dts/upstream contains the
current version of this binding.

Signed-off-by: Janne Grunau <j@jannau.net>
Acked-by: Mark Kettenis <kettenis@openbsd.org>
2026-05-12 12:11:08 -06:00
Janne Grunau
4587d7180b doc: board: apple: Mention M2 and M2 Pro/Max/Ultra SoCs
These SoCs are supported since 2022/2023 but were never added to the
documentation. The devices very similar to the equivalent M1 devices.
The biggest difference is that the M2 and M2 Pro/Max based laptops no
longer use SPI for the keyboard.

Signed-off-by: Janne Grunau <j@jannau.net>
Acked-by: Mark Kettenis <kettenis@openbsd.org>
2026-05-12 12:11:08 -06:00
Janne Grunau
0f0ff73bac arm: apple: Switch to board based text env
The main use case for u-boot on Apple silicon based devices is to
provide an EFI based bootloader for operating systems. This uses a
generic u-boot image with DTBs passed from an earlier boot loader
(m1n1). Use the generic board name "mac" for this purpose.

Signed-off-by: Janne Grunau <j@jannau.net>
2026-05-12 12:08:15 -06:00
Janne Grunau
1b5500cefe MAINTAINERS: Add Janne Grunau as reviewer for Apple M1 SoC support
I'm one of the co-maintainers of Apple silicon support in the Linux
kernel and have contributed to u-boot's Apple SoC support.

Signed-off-by: Janne Grunau <j@jannau.net>
Acked-by: Mark Kettenis <kettenis@openbsd.org>
2026-05-12 12:08:08 -06:00
Janne Grunau
60c6065df1 MAINTAINERS: Add missing Apple M1 specific files
The files weren't added to MAINTAINERS but clearly belong to Apple
silicon (M1) support.

Signed-off-by: Janne Grunau <j@jannau.net>
Acked-by: Mark Kettenis <kettenis@openbsd.org>
2026-05-12 12:08:08 -06:00
Janne Grunau
74471e0e18 watchdog: apple: Add "apple,t8103-wdt" compatible
After discussion with the devicetree maintainers we agreed to not extend
lists with the generic compatible "apple,wdt" anymore [1]. Use
"apple,t8103-wdt" as base compatible as it is the SoC driver and
bindings were originally written for.
The t602x (M2 Pro/Max/Ultra) devicetrees submitted in [2] use this
compatible as fallback instead of "apple,wdt".

Link: https://lore.kernel.org/asahi/12ab93b7-1fc2-4ce0-926e-c8141cfe81bf@kernel.org/ [1]
Link: https://lore.kernel.org/asahi/20250828-dt-apple-t6020-v1-0-507ba4c4b98e@jannau.net/ [2]
Signed-off-by: Janne Grunau <j@jannau.net>
Reviewed-by: Stefan Roese <stefan.roese@mailbox.org>
Acked-by: Mark Kettenis <kettenis@openbsd.org>
2026-05-12 12:08:05 -06:00
Janne Grunau
6df6f97431 spi: apple: Add "apple,t8103-spi" compatible
After discussion with the devicetree maintainers we agreed to not extend
lists with the generic compatible "apple,spi" anymore [1]. Use
"apple,t8103-spi" as base compatible as it is the SoC driver and
bindings were originally written for.
The t602x (M2 Pro/Max/Ultra) devicetrees submitted in [2] use this
compatible as fallback instead of "apple,spi".

Link: https://lore.kernel.org/asahi/12ab93b7-1fc2-4ce0-926e-c8141cfe81bf@kernel.org/ [1]
Link: https://lore.kernel.org/asahi/20250828-dt-apple-t6020-v1-0-507ba4c4b98e@jannau.net/ [2]
Signed-off-by: Janne Grunau <j@jannau.net>
Acked-by: Mark Kettenis <kettenis@openbsd.org>
2026-05-12 12:08:01 -06:00
Janne Grunau
39117feb21 power: domain: apple: Add "apple,t8103-pmgr-pwrstate" compatible
After discussion with the devicetree maintainers we agreed to not extend
lists with the generic compatible "apple,pmgr-pwrstate" anymore [1]. Use
"apple,t8103-pmgr-pwrstate" as base compatible as it is the SoC driver
and bindings were originally written for.
The t602x (M2 Pro/Max/Ultra) devicetrees submitted in [2] use this
compatible as fallback instead of "apple,pmgr-pwrstate".

Link: https://lore.kernel.org/asahi/12ab93b7-1fc2-4ce0-926e-c8141cfe81bf@kernel.org/ [1]
Link: https://lore.kernel.org/asahi/20250828-dt-apple-t6020-v1-0-507ba4c4b98e@jannau.net/ [2]
Signed-off-by: Janne Grunau <j@jannau.net>
Acked-by: Mark Kettenis <kettenis@openbsd.org>
2026-05-12 12:07:57 -06:00
Janne Grunau
1588f7b8a3 pinctrl: apple: Add "apple,t8103-pinctrl" compatible
After discussion with the devicetree maintainers we agreed to not extend
lists with the generic compatible "apple,pinctrl" anymore [1]. Use
"apple,t8103-pinctrl" as fallback compatible as it is the SoC driver and
bindings were originally written for.
The t602x (M2 Pro/Max/Ultra) devicetrees submitted in [2] use this
compatible as fallback instead of "apple,t8103-pinctrl".

Link: https://lore.kernel.org/asahi/12ab93b7-1fc2-4ce0-926e-c8141cfe81bf@kernel.org/ [1]
Link: https://lore.kernel.org/asahi/20250828-dt-apple-t6020-v1-0-507ba4c4b98e@jannau.net/ [2]
Signed-off-by: Janne Grunau <j@jannau.net>
Acked-by: Mark Kettenis <kettenis@openbsd.org>
2026-05-12 12:07:54 -06:00
Janne Grunau
29080b2a99 nvme: apple: add "apple,t8103-nvme-ans2" compatible
After discussion with the devicetree maintainers we agreed to not extend
lists with the generic compatible "apple,nvme-ans2" anymore [1]. Add
"apple,t8103-nvme-ans2" as fallback compatible as this is the SoC the
driver and bindings were originally written for.
The t602x (M2 Pro/Max/Ultra) devicetrees submitted in [2] use this
compatible as fallback instead of "apple,t8103-nvme-ans2".

Link: https://lore.kernel.org/asahi/12ab93b7-1fc2-4ce0-926e-c8141cfe81bf@kernel.org/ [1]
Link: https://lore.kernel.org/asahi/20250828-dt-apple-t6020-v1-0-507ba4c4b98e@jannau.net/ [2]
Signed-off-by: Janne Grunau <j@jannau.net>
Acked-by: Mark Kettenis <kettenis@openbsd.org>
2026-05-12 12:07:49 -06:00
Ernest Van Hoecke
f62d4535cf arm: dts: k3-am69-aquila: add combined boot firmware image
Add nodes to the binman configuration to create single binaries that
combine tiboot3-am69-*-aquila.bin, tispl.bin and u-boot.img into
firmware-aquila-am69-*.bin, with the proper offsets.

These binaries can be used to flash U-Boot via a single binary of three,
as it is done now.

Signed-off-by: Ernest Van Hoecke <ernest.vanhoecke@toradex.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Acked-by: Francesco Dolcini <francesco.dolcini@toradex.com>
2026-05-12 11:43:36 -06:00
Tze Yee Ng
b42c67188c mmc: sdhci-cadence: trigger tuning for SD HS mode on SD6HC (v6) PHY
The Cadence SD6HC (SDHCI spec v4.20+) controller uses a soft PHY whose
DLL delay characteristics vary with PVT (Process, Voltage, Temperature)
and board-level trace routing.

A static delay value programmed via device tree for SD High Speed mode is
insufficient because the optimal sampling point varies per board, SD card,
and operating conditions. Runtime calibration is required.

While the SD Physical Layer Specification does not mandate tuning for
SD HS mode (only for UHS-I SDR50/SDR104), the Cadence SD6HC PHY
requires runtime calibration of its receive data delay line to find a
valid sampling window under constrained clock conditions.

The tuning is triggered from the set_ios_post callback because at that
moment hardware has committed the new bus width, clock frequency, and speed
mode to the controller registers. This ensuring the tuning sequence runs
at the correct SD HS operating conditions.

The tuning is gated by a device tree property "cdns,sd-hs-tuning" so
that only boards requiring runtime calibration opt in. When enabled,
the driver performs a 40-tap DLL sweep using CMD19 to find the largest
consecutive passing window, then programs the midpoint into
PHY_DLL_SLAVE_CTRL_REG.

To enable on a board, add to the MMC node in device tree:

    &mmc {
        cdns,sd-hs-tuning;
    };

Signed-off-by: Tze Yee Ng <tze.yee.ng@altera.com>
2026-05-12 11:42:41 -06:00
Patrice Chotard
612256838a reset: stm32: Fix compilation error
The following compilation error occurs when environment variable
KBUILD_OUTPUT is not set :

drivers/reset/stm32/stm32-reset-mp21.c:8:10: fatal error: stm32-reset-core.h: No such file or directory
    8 | #include <stm32-reset-core.h>
      |          ^~~~~~~~~~~~~~~~~~~~

As stm32-reset-core.h is located in same directory than stm32-reset-mp21.c,
we should use #include "stm32-reset-core.h".

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Raphaël Gallais-Pou <rgallaispou@gmail.com>
2026-05-12 15:52:53 +02:00
Patrice Chotard
43ba37376b arm/mach-stm32: Remove remaining non-existent STM32_RESET
Symbol CONFIG_STM32_RESET does not exist.
Don't select it.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
2026-05-12 15:52:36 +02:00
Dario Binacchi
4300f9f4c5 board: st: stm32mp25: support dynamic A/B bank bootup
Enable automatic detection of the active A/B bank by retrieving
partition GUIDs from FWU metadata.

This ensures the system correctly identifies the bootable partitions
even in multi-bank scenarios, falling back to a standard bootable flag
scan if the UUIDs are missing.

To enable A/B bank bootup on stm32mp25 boards, add the following Kconfig
options to the stm32mp25_defconfig:

 CONFIG_FWU_MULTI_BANK_UPDATE=y
 CONFIG_FWU_MDATA=y
 CONFIG_FWU_NUM_BANKS=2
 CONFIG_FWU_NUM_IMAGES_PER_BANK=3
 CONFIG_CMD_FWU_METADATA=y
 CONFIG_FWU_MDATA_V2=y

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2026-05-12 15:52:01 +02:00
Dario Binacchi
63fc73ff31 test: dm: fwu_mdata: add test for fwu_mdata_get_image_guid
Add a new unit test for the fwu_mdata_get_image_guid() function.

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2026-05-12 15:52:01 +02:00
Dario Binacchi
97cdde6dfa fwu: add helper to get image GUID by type and bank index
Introduce fwu_mdata_get_image_guid() to retrieve a specific image GUID
from the FWU metadata based on the bank index and image type GUID.

This allows identifying the correct partition in multi-bank (A/B)
scenarios, ensuring the correct image is targeted depending on the
current bank.

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2026-05-12 15:52:01 +02:00
Dario Binacchi
2dc71c48bf test: cmd: part: add UUID lookup tests
Extend the 'part' command unit tests to include partition lookup via
UUID.

This ensures that the 'number', 'start', and 'size' subcommands
consistently handle UUIDs as partition identifiers, maintaining
parity with the name-based lookup functionality.

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2026-05-12 15:52:01 +02:00
Dario Binacchi
703f8c313d cmd: part: support lookup by UUID
The 'part' command currently allows looking up a partition only by its
number or name.

Extend the 'number', 'start', and 'size' subcommands to support looking
up the partition via its UUID. Unlike names, UUIDs guarantee unique
partition identification, avoiding ambiguity.

The logic is updated to check if the provided string is a valid UUID
before falling back to a name-based search. The help strings for these
subcommands are updated accordingly.

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2026-05-12 15:52:01 +02:00
Dario Binacchi
a392450189 test: cmd: add unit tests for part command
Add unit tests for the 'part' command, specifically for the 'number',
'start', and 'size' subcommands.

These tests establish a baseline for the current partition lookup
functionality by name. This foundation will be used by subsequent
patches to extend the command, ensuring consistent behavior as new
features are introduced.

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2026-05-12 15:52:01 +02:00
Dario Binacchi
27a928553a test: dm: part: add test for part_get_info_by_uuid
Add a new unit test for the part_get_info_by_uuid() function.

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2026-05-12 15:52:01 +02:00
Dario Binacchi
2a55938b42 lib: uuid: add partition type GUID for extended bootloader
The Extended Boot Loader Partition (XBOOTLDR) is a standard defined by
the Discoverable Partitions Specification (DPS) to host boot loader
resources outside of the EFI System Partition ([1], [2]).

Defining this GUID (bc13c2ff-59e6-4262-a352-b275fd6f7172) allows U-Boot
to correctly identify and label these partitions using the "xbootldr"
shorthand.

[1] https://uapi-group.org/specifications/specs/discoverable_partitions_specification/#extended-boot-loader-partition:~:text=UEFI%20Specification.-,Extended%20Boot%20Loader%20Partition,-bc13c2ff%2D59e6%2D4262
[2] https://uapi-group.org/specifications/specs/boot_loader_specification/
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2026-05-12 15:52:01 +02:00
Austin Shirley
467dc9a44b configs: stm32mp13: add SPI-NAND UBI boot support
The STM32MP13 default environment only handles MMC and serial/USB boot.
When TF-A reports BOOT_FLASH_SPINAND the boot_device variable is set to
'spi-nand' but bootcmd_stm32mp never redirects boot_targets to ubifs0,
so distro_bootcmd falls through to MMC/USB.

This change mirrors the STM32MP15 logic:
 - Add a BOOT_TARGET_UBIFS entry to BOOT_TARGET_DEVICES so that
   bootcmd_ubifs0 is defined (ubi part UBI; ubifsmount ubi0:boot).
 - Add the 'spi-nand' / 'nand' clause to bootcmd_stm32mp so that
   boot_targets is set to 'ubifs0' when booting from NAND.

Signed-off-by: Austin Shirley <austin@deadband.dev>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: uboot-stm32@st-md-mailman.stormreply.com
2026-05-12 15:50:47 +02:00
Kory Maincent
d5ea30b233 tools: fwumdata: Fix use-after-free in parse_config()
In parse_config(), devname is dynamically allocated by sscanf().
When sscanf() fails to fill enough fields (rc < 3), devname is freed and
the loop continues to the next line. However, if the next call to sscanf()
fails to match (rc == 0), devname is not written and still holds the stale
freed pointer. The subsequent free(devname) then operates on
already-freed memory.

Fix this by resetting devname to NULL before each sscanf() call, so
that a non-matching call leaves a NULL pointer and the subsequent
free() becomes a harmless no-op.

Reported-by: Coverity Scan
Link: https://lists.denx.de/pipermail/u-boot/2026-April/614161.html
Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2026-05-12 09:31:51 +03:00
464 changed files with 21893 additions and 17776 deletions

View File

@@ -133,15 +133,22 @@ F: drivers/mmc/snps_dw_mmc.c
APPLE M1 SOC SUPPORT
M: Mark Kettenis <kettenis@openbsd.org>
R: Janne Grunau <j@jannau.net>
S: Maintained
F: arch/arm/include/asm/arch-apple/
F: arch/arm/mach-apple/
F: board/apple/
F: configs/apple_m1_defconfig
F: doc/board/apple/
F: drivers/input/apple_spi_kbd.c
F: drivers/iommu/apple_dart.c
F: drivers/mailbox/apple-mbox.c
F: drivers/nvme/nvme_apple.c
F: drivers/pci/pcie_apple.c
F: drivers/phy/phy-apple-atc.c
F: drivers/pinctrl/pinctrl-apple.c
F: drivers/power/domain/apple-pmgr.c
F: drivers/spi/apple_spi.c
F: drivers/watchdog/apple_wdt.c
F: include/configs/apple.h
@@ -310,26 +317,13 @@ M: Fabio Estevam <festevam@gmail.com>
R: NXP i.MX U-Boot Team <uboot-imx@nxp.com>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-imx.git
F: arch/Kconfig.nxp
N: imx
N: mxc
N: nxp
N: vf610
F: arch/arm/cpu/arm1136/mx*/
F: arch/arm/cpu/arm926ejs/mx*/
F: arch/arm/cpu/armv7/vf610/
F: arch/arm/dts/*imx*
F: arch/arm/mach-imx/
F: arch/arm/include/asm/arch-imx*/
F: arch/arm/include/asm/arch-mx*/
F: arch/arm/include/asm/arch-vf610/
F: arch/arm/include/asm/mach-imx/
F: board/nxp/*mx*/
F: board/nxp/common/
F: common/spl/spl_imx_container.c
F: doc/board/nxp/
F: doc/imx/
F: drivers/mailbox/imx-mailbox.c
F: drivers/remoteproc/imx*
F: drivers/serial/serial_mxc.c
F: drivers/spi/nxp_xspi.c
F: include/imx_container.h
ARM HISILICON
M: Peter Griffin <peter.griffin@linaro.org>
@@ -1109,7 +1103,7 @@ EFI CLIENT
M: Simon Glass <sjg@chromium.org>
M: Heinrich Schuchardt <xypron.glpk@gmx.de>
S: Maintained
W: https://docs.u-boot.org/en/latest/develop/uefi/u-boot_on_efi.html
W: https://docs.u-boot-project.org/en/latest/develop/uefi/u-boot_on_efi.html
F: board/efi/efi-x86_app
F: configs/efi-x86_app*
F: doc/develop/uefi/u-boot_on_efi.rst
@@ -1499,6 +1493,7 @@ T: git https://source.denx.de/u-boot/custodians/u-boot-nios.git
F: arch/nios2/
NVMe
M: Neil Armstrong <neil.armstrong@linaro.org>
M: Bin Meng <bmeng.cn@gmail.com>
S: Maintained
F: drivers/nvme/

View File

@@ -3,7 +3,7 @@
VERSION = 2026
PATCHLEVEL = 07
SUBLEVEL =
EXTRAVERSION = -rc2
EXTRAVERSION = -rc3
NAME =
# *DOCUMENTATION*
@@ -1578,6 +1578,9 @@ spl/u-boot-spl.srec: spl/u-boot-spl FORCE
%.scif: %.srec
$(Q)$(MAKE) $(build)=arch/arm/mach-renesas $@
%.shdr: %.srec
$(Q)$(MAKE) $(build)=arch/arm/mach-renesas $@
OBJCOPYFLAGS_u-boot-nodtb.bin := -O binary \
$(if $(CONFIG_X86_16BIT_INIT),-R .start16 -R .resetvec) \
$(if $(CONFIG_MPC85XX_HAVE_RESET_VECTOR),$(if $(CONFIG_OF_SEPARATE),-R .bootpg -R .resetvec))
@@ -1682,7 +1685,7 @@ cmd_binman = $(srctree)/tools/binman/binman $(if $(BINMAN_DEBUG),-D) \
build -u -d $(binman_dtb) -O . -m \
--allow-missing --fake-ext-blobs \
$(if $(BINMAN_ALLOW_MISSING),--ignore-missing) \
-I . -I $(srctree) -I $(srctree)/board/$(BOARDDIR) \
-I . -I $(srctree)/board/$(BOARDDIR) -I $(srctree) \
$(foreach f,$(of_list_dirs),-I $(f)) -a of-list=$(of_list) \
$(foreach f,$(BINMAN_INDIRS),-I $(f)) \
-a atf-bl1-path=${BL1} \

263
README
View File

@@ -628,98 +628,6 @@ The following options need to be configured:
If you do not have i2c muxes on your board, omit this define.
- Legacy I2C Support:
If you use the software i2c interface (CONFIG_SYS_I2C_SOFT)
then the following macros need to be defined (examples are
from include/configs/lwmon.h):
I2C_INIT
(Optional). Any commands necessary to enable the I2C
controller or configure ports.
eg: #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
I2C_ACTIVE
The code necessary to make the I2C data line active
(driven). If the data line is open collector, this
define can be null.
eg: #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
I2C_TRISTATE
The code necessary to make the I2C data line tri-stated
(inactive). If the data line is open collector, this
define can be null.
eg: #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
I2C_READ
Code that returns true if the I2C data line is high,
false if it is low.
eg: #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
I2C_SDA(bit)
If <bit> is true, sets the I2C data line high. If it
is false, it clears it (low).
eg: #define I2C_SDA(bit) \
if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
else immr->im_cpm.cp_pbdat &= ~PB_SDA
I2C_SCL(bit)
If <bit> is true, sets the I2C clock line high. If it
is false, it clears it (low).
eg: #define I2C_SCL(bit) \
if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
else immr->im_cpm.cp_pbdat &= ~PB_SCL
I2C_DELAY
This delay is invoked four times per clock cycle so this
controls the rate of data transfer. The data rate thus
is 1 / (I2C_DELAY * 4). Often defined to be something
like:
#define I2C_DELAY udelay(2)
CONFIG_SOFT_I2C_GPIO_SCL / CONFIG_SOFT_I2C_GPIO_SDA
If your arch supports the generic GPIO framework (asm/gpio.h),
then you may alternatively define the two GPIOs that are to be
used as SCL / SDA. Any of the previous I2C_xxx macros will
have GPIO-based defaults assigned to them as appropriate.
You should define these to the GPIO value as given directly to
the generic GPIO functions.
CFG_SYS_I2C_NOPROBES
This option specifies a list of I2C devices that will be skipped
when the 'i2c probe' command is issued.
e.g.
#define CFG_SYS_I2C_NOPROBES {0x50,0x68}
will skip addresses 0x50 and 0x68 on a board with one I2C bus
CONFIG_SOFT_I2C_READ_REPEATED_START
defining this will force the i2c_read() function in
the soft_i2c driver to perform an I2C repeated start
between writing the address pointer and reading the
data. If this define is omitted the default behaviour
of doing a stop-start sequence will be used. Most I2C
devices can use either method, but some require one or
the other.
- SPI Support: CONFIG_SPI
Enables SPI driver (so far only tested with
@@ -799,7 +707,7 @@ The following options need to be configured:
The same can be accomplished in a more flexible way
for any variable by configuring the type of access
to allow for those variables in the ".flags" variable
or define CFG_ENV_FLAGS_LIST_STATIC.
or by setting CONFIG_ENV_FLAGS_LIST_STATIC.
- Protected RAM:
CFG_PRAM
@@ -1033,173 +941,6 @@ typically in board_init_f() and board_init_r().
- CONFIG_BOARD_EARLY_INIT_R: Call board_early_init_r()
- CONFIG_BOARD_LATE_INIT: Call board_late_init()
Configuration Settings:
-----------------------
- CONFIG_SYS_LONGHELP: Defined when you want long help messages included;
undefine this when you're short of memory.
- CFG_SYS_HELP_CMD_WIDTH: Defined when you want to override the default
width of the commands listed in the 'help' command output.
- CONFIG_SYS_PROMPT: This is what U-Boot prints on the console to
prompt for user input.
- CFG_SYS_BAUDRATE_TABLE:
List of legal baudrate settings for this board.
- CFG_SYS_MEM_RESERVE_SECURE
Only implemented for ARMv8 for now.
If defined, the size of CFG_SYS_MEM_RESERVE_SECURE memory
is substracted from total RAM and won't be reported to OS.
This memory can be used as secure memory. A variable
gd->arch.secure_ram is used to track the location. In systems
the RAM base is not zero, or RAM is divided into banks,
this variable needs to be recalcuated to get the address.
- CFG_SYS_SDRAM_BASE:
Physical start address of SDRAM. _Must_ be 0 here.
- CFG_SYS_FLASH_BASE:
Physical start address of Flash memory.
- CONFIG_SYS_MALLOC_LEN:
Size of DRAM reserved for malloc() use.
- CFG_SYS_BOOTMAPSZ:
Maximum size of memory mapped by the startup code of
the Linux kernel; all data that must be processed by
the Linux kernel (bd_info, boot arguments, FDT blob if
used) must be put below this limit, unless "bootm_low"
environment variable is defined and non-zero. In such case
all data for the Linux kernel must be between "bootm_low"
and "bootm_low" + CFG_SYS_BOOTMAPSZ. The environment
variable "bootm_mapsize" will override the value of
CFG_SYS_BOOTMAPSZ. If CFG_SYS_BOOTMAPSZ is undefined,
then the value in "bootm_size" will be used instead.
- CONFIG_SYS_BOOT_GET_CMDLINE:
Enables allocating and saving kernel cmdline in space between
"bootm_low" and "bootm_low" + BOOTMAPSZ.
- CONFIG_SYS_BOOT_GET_KBD:
Enables allocating and saving a kernel copy of the bd_info in
space between "bootm_low" and "bootm_low" + BOOTMAPSZ.
- CONFIG_SYS_FLASH_PROTECTION
If defined, hardware flash sectors protection is used
instead of U-Boot software protection.
- CONFIG_SYS_FLASH_CFI:
Define if the flash driver uses extra elements in the
common flash structure for storing flash geometry.
- CONFIG_FLASH_CFI_DRIVER
This option also enables the building of the cfi_flash driver
in the drivers directory
- CONFIG_FLASH_CFI_MTD
This option enables the building of the cfi_mtd driver
in the drivers directory. The driver exports CFI flash
to the MTD layer.
- CONFIG_SYS_FLASH_USE_BUFFER_WRITE
Use buffered writes to flash.
- CONFIG_ENV_FLAGS_LIST_DEFAULT
- CFG_ENV_FLAGS_LIST_STATIC
Enable validation of the values given to environment variables when
calling env set. Variables can be restricted to only decimal,
hexadecimal, or boolean. If CONFIG_CMD_NET is also defined,
the variables can also be restricted to IP address or MAC address.
The format of the list is:
type_attribute = [s|d|x|b|i|m]
access_attribute = [a|r|o|c]
attributes = type_attribute[access_attribute]
entry = variable_name[:attributes]
list = entry[,list]
The type attributes are:
s - String (default)
d - Decimal
x - Hexadecimal
b - Boolean ([1yYtT|0nNfF])
i - IP address
m - MAC address
The access attributes are:
a - Any (default)
r - Read-only
o - Write-once
c - Change-default
- CONFIG_ENV_FLAGS_LIST_DEFAULT
Define this to a list (string) to define the ".flags"
environment variable in the default or embedded environment.
- CFG_ENV_FLAGS_LIST_STATIC
Define this to a list (string) to define validation that
should be done if an entry is not found in the ".flags"
environment variable. To override a setting in the static
list, simply add an entry for the same variable name to the
".flags" variable.
If CONFIG_REGEX is defined, the variable_name above is evaluated as a
regular expression. This allows multiple variables to define the same
flags without explicitly listing them for each variable.
The following definitions that deal with the placement and management
of environment data (variable area); in general, we support the
following configurations:
BE CAREFUL! The first access to the environment happens quite early
in U-Boot initialization (when we try to get the setting of for the
console baudrate). You *MUST* have mapped your NVRAM area then, or
U-Boot will hang.
Please note that even with NVRAM we still use a copy of the
environment in RAM: we could work on NVRAM directly, but we want to
keep settings there always unmodified except somebody uses "saveenv"
to save the current settings.
BE CAREFUL! For some special cases, the local device can not use
"saveenv" command. For example, the local device will get the
environment stored in a remote NOR flash by SRIO or PCIE link,
but it can not erase, write this NOR flash by SRIO or PCIE interface.
- CONFIG_NAND_ENV_DST
Defines address in RAM to which the nand_spl code should copy the
environment. If redundant environment is used, it will be copied to
CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE.
Please note that the environment is read-only until the monitor
has been relocated to RAM and a RAM copy of the environment has been
created; also, when using EEPROM you will have to use env_get_f()
until then to read environment variables.
The environment is protected by a CRC32 checksum. Before the monitor
is relocated into RAM, as a result of a bad CRC you will be working
with the compiled-in default environment - *silently*!!! [This is
necessary, because the first environment variable we need is the
"baudrate" setting for the console - if we have a bad CRC, we don't
have any device yet where we could complain.]
Note: once the monitor has been relocated, then it will complain if
the default environment is used; a new CRC is computed as soon as you
use the "saveenv" command to store a valid environment.
- CONFIG_DISPLAY_BOARDINFO
Display information about the board that U-Boot is running on
when U-Boot starts up. The board function checkboard() is called
to do this.
- CONFIG_DISPLAY_BOARDINFO_LATE
Similar to the previous option, but display this information
later, once stdio is running and output goes to the LCD, if
present.
Low Level (hardware related) configuration options:
---------------------------------------------------
@@ -2373,5 +2114,5 @@ Contributing
The U-Boot projects depends on contributions from the user community.
If you want to participate, please, have a look at the 'General'
section of https://docs.u-boot.org/en/latest/develop/index.html
section of https://docs.u-boot-project.org/en/latest/develop/index.html
where we describe coding standards and the patch submission process.

View File

@@ -1082,6 +1082,7 @@ config ARCH_APPLE
imply CMD_GPT
imply BOOTSTD_FULL
imply OF_HAS_PRIOR_STAGE
imply OF_UPSTREAM
config ARCH_OWL
bool "Actions Semi OWL SoCs"

View File

@@ -16,7 +16,6 @@
#ifdef CONFIG_FSL_ESDHC
#include <fsl_esdhc.h>
#endif
#include <tsec.h>
#include <asm/arch/immap_ls102xa.h>
#include <fsl_sec.h>
#include <dm.h>
@@ -26,7 +25,7 @@ DECLARE_GLOBAL_DATA_PTR;
void ft_fixup_enet_phy_connect_type(void *fdt)
{
struct udevice *dev;
struct tsec_private *priv;
struct eth_pdata *pdata;
const char *enet_path, *phy_path;
char enet[16];
char phy[16];
@@ -45,8 +44,8 @@ void ft_fixup_enet_phy_connect_type(void *fdt)
continue;
}
priv = dev_get_priv(dev);
if (priv->flags & TSEC_SGMII)
pdata = dev_get_plat(dev);
if (pdata->phy_interface == PHY_INTERFACE_MODE_SGMII)
continue;
enet_path = fdt_get_alias(fdt, enet);

View File

@@ -810,8 +810,10 @@ __weak void mmu_setup(void)
el = current_el();
set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(NULL, NULL),
MEMORY_ATTRIBUTES);
}
/* enable the mmu */
void mmu_enable(void)
{
set_sctlr(get_sctlr() | CR_M);
}
@@ -881,6 +883,7 @@ void dcache_enable(void)
if (!mmu_status()) {
__asm_invalidate_tlb_all();
mmu_setup();
mmu_enable();
}
/* Set up page tables only once (it is done also by mmu_setup()) */

View File

@@ -1143,7 +1143,7 @@ int arch_early_init_r(void)
#ifdef CONFIG_SYS_HAS_SERDES
fsl_serdes_init();
#endif
#ifdef CONFIG_SYS_FSL_HAS_RGMII
#if defined(CONFIG_SYS_FSL_HAS_RGMII) && defined(CONFIG_FSL_MC_ENET)
/* some dpmacs in armv8a based freescale layerscape SOCs can be
* configured via both serdes(sgmii, 10gbase-r, xlaui etc) bits and via
* EC*_PMUX(rgmii) bits in RCW.
@@ -1158,6 +1158,10 @@ int arch_early_init_r(void)
* function of SOC, the dpmac will be enabled as RGMII even if it was
* also enabled before as SGMII. If ECx_PMUX is not configured for
* RGMII, DPMAC will remain configured as SGMII from fsl_serdes_init().
*
* fsl_rgmii_init() itself is only built under CONFIG_FSL_MC_ENET
* (drivers/net/ldpaa_eth/); gate the call the same way so builds
* without MC-ENET still link.
*/
fsl_rgmii_init();
#endif

View File

@@ -96,7 +96,7 @@ SECTIONS
{
KEEP(*(.__secure_stack_start))
/* Skip addreses for stack */
/* Skip addresses for stack */
. = . + CONFIG_ARMV7_PSCI_NR_CPUS * ARM_PSCI_STACK_SIZE;
/* Align end of stack section to page boundary */

View File

@@ -32,13 +32,6 @@ dtb-$(CONFIG_TARGET_A5Y17LTE) += exynos78x0-axy17lte.dtb
dtb-$(CONFIG_TARGET_A3Y17LTE) += exynos78x0-axy17lte.dtb
dtb-$(CONFIG_TARGET_A7Y17LTE) += exynos78x0-axy17lte.dtb
dtb-$(CONFIG_ARCH_APPLE) += \
t8103-j274.dtb \
t8103-j293.dtb \
t8103-j313.dtb \
t8103-j456.dtb \
t8103-j457.dtb
dtb-$(CONFIG_ARCH_DAVINCI) += \
da850-lcdk.dtb \
da850-lego-ev3.dtb
@@ -879,8 +872,6 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mm-mx8menlo.dtb \
imx8mm-phg.dtb \
imx8mq-cm.dtb \
imx8mq-mnt-reform2.dtb \
imx8mq-phanbell.dtb \
imx8mp-data-modul-edm-sbc.dtb \
imx8mp-dhcom-som-overlay-rev100.dtbo \
imx8mp-dhcom-som-overlay-eth1xfast.dtbo \
@@ -890,10 +881,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mp-dhcom-pdk3-overlay-rev100.dtbo \
imx8mp-dhcom-picoitx.dtb \
imx8mp-icore-mx8mp-edimm2.2.dtb \
imx8mp-msc-sm2s.dtb \
imx8mq-pico-pi.dtb \
imx8mq-kontron-pitx-imx8m.dtb \
imx8mq-librem5-r4.dtb
imx8mp-msc-sm2s.dtb
dtb-$(CONFIG_ARCH_IMX9) += \
imx93-11x11-frdm.dtb \
@@ -907,11 +895,7 @@ dtb-$(CONFIG_RZA1) += \
r7s72100-gr-peach.dtb
dtb-$(CONFIG_RCAR_GEN5) += \
r8a78000-ironhide.dtb
ifdef CONFIG_RCAR_GEN5
DTC_FLAGS += -R 4 -p 0x1000
endif
r8a78000-ironhide-cm33.dtb
dtb-$(CONFIG_TARGET_AT91SAM9261EK) += at91sam9261ek.dtb

View File

@@ -1,437 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2020 Compass Electronics Group, LLC
*/
#include <dt-bindings/phy/phy-imx8-pcie.h>
/ {
leds {
compatible = "gpio-leds";
led0 {
label = "gen_led0";
gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led1 {
label = "gen_led1";
gpios = <&pca6416_1 5 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led2 {
label = "gen_led2";
gpios = <&pca6416_1 6 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_led3>;
label = "heartbeat";
gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
pcie0_refclk: pcie0-refclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
pcie0_refclk_gated: pcie0-refclk-gated {
compatible = "gpio-gate-clock";
clocks = <&pcie0_refclk>;
#clock-cells = <0>;
enable-gpios = <&pca6416_1 2 GPIO_ACTIVE_LOW>;
};
reg_audio: regulator-audio {
compatible = "regulator-fixed";
regulator-name = "3v3_aud";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&pca6416_1 11 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usbotg1: regulator-usbotg1 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usb_otg1>;
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_camera: regulator-camera {
compatible = "regulator-fixed";
regulator-name = "mipi_pwr";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
gpio = <&pca6416_1 0 GPIO_ACTIVE_HIGH>;
enable-active-high;
startup-delay-us = <100000>;
};
reg_pcie0: regulator-pcie {
compatible = "regulator-fixed";
regulator-name = "pci_pwr_en";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
enable-active-high;
gpio = <&pca6416_1 1 GPIO_ACTIVE_HIGH>;
startup-delay-us = <100000>;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
sound {
compatible = "fsl,imx-audio-wm8962";
model = "wm8962-audio";
audio-cpu = <&sai3>;
audio-codec = <&wm8962>;
audio-routing =
"Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
"Ext Spk", "SPKOUTL",
"Ext Spk", "SPKOUTR",
"AMIC", "MICBIAS",
"IN3R", "AMIC";
};
};
&csi {
status = "okay";
};
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_espi2>;
cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
status = "okay";
eeprom@0 {
compatible = "microchip,at25160bn", "atmel,at25";
reg = <0>;
spi-max-frequency = <5000000>;
spi-cpha;
spi-cpol;
pagesize = <32>;
size = <2048>;
address-width = <16>;
};
};
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
camera@3c {
compatible = "ovti,ov5640";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ov5640>;
reg = <0x3c>;
clocks = <&clk IMX8MM_CLK_CLKO1>;
clock-names = "xclk";
assigned-clocks = <&clk IMX8MM_CLK_CLKO1>;
assigned-clock-parents = <&clk IMX8MM_CLK_24M>;
assigned-clock-rates = <24000000>;
AVDD-supply = <&reg_camera>; /* 2.8v */
powerdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
port {
/* MIPI CSI-2 bus endpoint */
ov5640_to_mipi_csi2: endpoint {
remote-endpoint = <&imx8mm_mipi_csi_in>;
clock-lanes = <0>;
data-lanes = <1 2>;
};
};
};
};
&i2c4 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
status = "okay";
wm8962: audio-codec@1a {
compatible = "wlf,wm8962";
reg = <0x1a>;
clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
DCVDD-supply = <&reg_audio>;
DBVDD-supply = <&reg_audio>;
AVDD-supply = <&reg_audio>;
CPVDD-supply = <&reg_audio>;
MICVDD-supply = <&reg_audio>;
PLLVDD-supply = <&reg_audio>;
SPKVDD1-supply = <&reg_audio>;
SPKVDD2-supply = <&reg_audio>;
gpio-cfg = <
0x0000 /* 0:Default */
0x0000 /* 1:Default */
0x0000 /* 2:FN_DMICCLK */
0x0000 /* 3:Default */
0x0000 /* 4:FN_DMICCDAT */
0x0000 /* 5:Default */
>;
};
pca6416_0: gpio@20 {
compatible = "nxp,pcal6416";
reg = <0x20>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcal6414>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gpio4>;
interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
};
pca6416_1: gpio@21 {
compatible = "nxp,pcal6416";
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gpio4>;
interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
};
};
&mipi_csi {
status = "okay";
ports {
port@0 {
imx8mm_mipi_csi_in: endpoint {
remote-endpoint = <&ov5640_to_mipi_csi2>;
data-lanes = <1 2>;
};
};
};
};
&pcie_phy {
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
fsl,tx-deemph-gen1 = <0x2d>;
fsl,tx-deemph-gen2 = <0xf>;
fsl,clkreq-unsupported;
clocks = <&pcie0_refclk_gated>;
clock-names = "ref";
status = "okay";
};
&pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0>;
reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
<&pcie0_refclk_gated>;
clock-names = "pcie", "pcie_aux", "pcie_bus";
assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
<&clk IMX8MM_CLK_PCIE1_CTRL>;
assigned-clock-rates = <10000000>, <250000000>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
<&clk IMX8MM_SYS_PLL2_250M>;
vpcie-supply = <&reg_pcie0>;
status = "okay";
};
&sai3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
assigned-clock-rates = <24576000>;
fsl,sai-mclk-direction-output;
status = "okay";
};
&snvs_pwrkey {
status = "okay";
};
&uart2 { /* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
assigned-clocks = <&clk IMX8MM_CLK_UART3>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
uart-has-rtscts;
status = "okay";
};
&usbotg1 {
vbus-supply = <&reg_usbotg1>;
disable-over-current;
dr_mode = "otg";
status = "okay";
};
&usbotg2 {
pinctrl-names = "default";
disable-over-current;
dr_mode = "host";
status = "okay";
};
&usbphynop2 {
reset-gpios = <&pca6416_1 7 GPIO_ACTIVE_HIGH>;
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
bus-width = <4>;
vmmc-supply = <&reg_usdhc2_vmmc>;
status = "okay";
};
&iomuxc {
pinctrl_espi2: espi2grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82
MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82
MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82
MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x41
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
>;
};
pinctrl_led3: led3grp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x41
>;
};
pinctrl_ov5640: ov5640grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19
MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19
MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59
>;
};
pinctrl_pcal6414: pcal6414-gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x19
>;
};
pinctrl_reg_usb_otg1: usbotg1grp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19
>;
};
pinctrl_pcie0: pcie0grp {
fsl,pins = <
MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x41
>;
};
pinctrl_sai3: sai3grp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x40
MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x40
MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x40
MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x40
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x41
MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
};

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@@ -1,309 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2020 Compass Electronics Group, LLC
*/
/ {
leds {
compatible = "gpio-leds";
led-0 {
label = "gen_led0";
gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led-1 {
label = "gen_led1";
gpios = <&pca6416_1 5 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led-2 {
label = "gen_led2";
gpios = <&pca6416_1 6 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led-3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_led3>;
label = "heartbeat";
gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
reg_audio: regulator-audio {
compatible = "regulator-fixed";
regulator-name = "3v3_aud";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&pca6416_1 11 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
regulator-name = "vsd_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usb_otg_vbus: regulator-usb {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usb_otg>;
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
sound {
compatible = "fsl,imx-audio-wm8962";
model = "wm8962-audio";
audio-cpu = <&sai3>;
audio-codec = <&wm8962>;
audio-routing =
"Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
"Ext Spk", "SPKOUTL",
"Ext Spk", "SPKOUTR",
"AMIC", "MICBIAS",
"IN3R", "AMIC";
};
};
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_espi2>;
cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
status = "okay";
eeprom@0 {
compatible = "microchip,at25160bn", "atmel,at25";
reg = <0>;
spi-max-frequency = <5000000>;
spi-cpha;
spi-cpol;
pagesize = <32>;
size = <2048>;
address-width = <16>;
};
};
&i2c4 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
status = "okay";
pca6416_0: gpio@20 {
compatible = "nxp,pcal6416";
reg = <0x20>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcal6414>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gpio4>;
interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
};
pca6416_1: gpio@21 {
compatible = "nxp,pcal6416";
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gpio4>;
interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
};
wm8962: audio-codec@1a {
compatible = "wlf,wm8962";
reg = <0x1a>;
clocks = <&clk IMX8MN_CLK_SAI3_ROOT>;
DCVDD-supply = <&reg_audio>;
DBVDD-supply = <&reg_audio>;
AVDD-supply = <&reg_audio>;
CPVDD-supply = <&reg_audio>;
MICVDD-supply = <&reg_audio>;
PLLVDD-supply = <&reg_audio>;
SPKVDD1-supply = <&reg_audio>;
SPKVDD2-supply = <&reg_audio>;
gpio-cfg = <
0x0000 /* 0:Default */
0x0000 /* 1:Default */
0x0000 /* 2:FN_DMICCLK */
0x0000 /* 3:Default */
0x0000 /* 4:FN_DMICCDAT */
0x0000 /* 5:Default */
>;
};
};
&easrc {
fsl,asrc-rate = <48000>;
status = "okay";
};
&sai3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
assigned-clocks = <&clk IMX8MN_CLK_SAI3>;
assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
assigned-clock-rates = <24576000>;
fsl,sai-mclk-direction-output;
status = "okay";
};
&snvs_pwrkey {
status = "okay";
};
&uart2 { /* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
assigned-clocks = <&clk IMX8MN_CLK_UART3>;
assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
uart-has-rtscts;
status = "okay";
};
&usbotg1 {
vbus-supply = <&reg_usb_otg_vbus>;
disable-over-current;
dr_mode = "otg";
status = "okay";
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
bus-width = <4>;
vmmc-supply = <&reg_usdhc2_vmmc>;
status = "okay";
};
&iomuxc {
pinctrl_espi2: espi2grp {
fsl,pins = <
MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82
MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82
MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82
MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x41
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
>;
};
pinctrl_led3: led3grp {
fsl,pins = <
MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x41
>;
};
pinctrl_pcal6414: pcal6414-gpiogrp {
fsl,pins = <
MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x19
>;
};
pinctrl_reg_usb_otg: reg-otggrp {
fsl,pins = <
MX8MN_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19
>;
};
pinctrl_sai3: sai3grp {
fsl,pins = <
MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
MX8MN_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x40
MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x40
MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x40
MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x40
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX8MN_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x41
MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
};

View File

@@ -1,533 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2019 NXP
*/
#include <dt-bindings/usb/pd.h>
#include "imx8mn.dtsi"
/ {
chosen {
stdout-path = &uart2;
};
gpio-leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_led>;
status {
label = "yellow:status";
gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
};
memory@40000000 {
device_type = "memory";
reg = <0x0 0x40000000 0 0x80000000>;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
ir-receiver {
compatible = "gpio-ir-receiver";
gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ir>;
linux,autosuspend-period = <125>;
};
audio_codec_bt_sco: audio-codec-bt-sco {
compatible = "linux,bt-sco";
#sound-dai-cells = <1>;
};
wm8524: audio-codec {
#sound-dai-cells = <0>;
compatible = "wlf,wm8524";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_wlf>;
wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MN_CLK_SAI3_ROOT>;
clock-names = "mclk";
};
sound-bt-sco {
compatible = "simple-audio-card";
simple-audio-card,name = "bt-sco-audio";
simple-audio-card,format = "dsp_a";
simple-audio-card,bitclock-inversion;
simple-audio-card,frame-master = <&btcpu>;
simple-audio-card,bitclock-master = <&btcpu>;
btcpu: simple-audio-card,cpu {
sound-dai = <&sai2>;
dai-tdm-slot-num = <2>;
dai-tdm-slot-width = <16>;
};
simple-audio-card,codec {
sound-dai = <&audio_codec_bt_sco 1>;
};
};
sound-wm8524 {
compatible = "fsl,imx-audio-wm8524";
model = "wm8524-audio";
audio-cpu = <&sai3>;
audio-codec = <&wm8524>;
audio-asrc = <&easrc>;
audio-routing =
"Line Out Jack", "LINEVOUTL",
"Line Out Jack", "LINEVOUTR";
};
sound-spdif {
compatible = "fsl,imx-audio-spdif";
model = "imx-spdif";
spdif-controller = <&spdif1>;
spdif-out;
spdif-in;
};
};
&easrc {
fsl,asrc-rate = <48000>;
status = "okay";
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
qca,disable-smarteee;
vddio-supply = <&vddio>;
vddio: vddio-regulator {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
};
};
};
&flexspi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexspi>;
status = "okay";
flash0: flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <166000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
};
};
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
};
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
ptn5110: tcpc@50 {
compatible = "nxp,ptn5110";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_typec1>;
reg = <0x50>;
interrupt-parent = <&gpio2>;
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
status = "okay";
port {
typec1_dr_sw: endpoint {
remote-endpoint = <&usb1_drd_sw>;
};
};
typec1_con: connector {
compatible = "usb-c-connector";
label = "USB-C";
power-role = "dual";
data-role = "dual";
try-power-role = "sink";
source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
PDO_VAR(5000, 20000, 3000)>;
op-sink-microwatt = <15000000>;
self-powered;
};
};
};
&i2c3 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
pca6416: gpio@20 {
compatible = "ti,tca6416";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
};
};
&sai2 {
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai2>;
assigned-clocks = <&clk IMX8MN_CLK_SAI2>;
assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
assigned-clock-rates = <24576000>;
status = "okay";
};
&sai3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
assigned-clocks = <&clk IMX8MN_CLK_SAI3>;
assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
assigned-clock-rates = <24576000>;
fsl,sai-mclk-direction-output;
status = "okay";
};
&snvs_pwrkey {
status = "okay";
};
&spdif1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spdif1>;
assigned-clocks = <&clk IMX8MN_CLK_SPDIF1>;
assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
assigned-clock-rates = <24576000>;
status = "okay";
};
&uart2 { /* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
assigned-clocks = <&clk IMX8MN_CLK_UART3>;
assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
uart-has-rtscts;
status = "okay";
};
&usbotg1 {
dr_mode = "otg";
hnp-disable;
srp-disable;
adp-disable;
usb-role-switch;
disable-over-current;
samsung,picophy-pre-emp-curr-control = <3>;
samsung,picophy-dc-vol-level-adjust = <7>;
status = "okay";
port {
usb1_drd_sw: endpoint {
remote-endpoint = <&typec1_dr_sw>;
};
};
};
&usdhc2 {
assigned-clocks = <&clk IMX8MN_CLK_USDHC2>;
assigned-clock-rates = <200000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
bus-width = <4>;
vmmc-supply = <&reg_usdhc2_vmmc>;
status = "okay";
};
&usdhc3 {
assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
assigned-clock-rates = <400000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
>;
};
pinctrl_flexspi: flexspigrp {
fsl,pins = <
MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2
MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
>;
};
pinctrl_gpio_led: gpioledgrp {
fsl,pins = <
MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
>;
};
pinctrl_gpio_wlf: gpiowlfgrp {
fsl,pins = <
MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21 0xd6
>;
};
pinctrl_ir: irgrp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x4f
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
>;
};
pinctrl_pmic: pmicirqgrp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141
>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
>;
};
pinctrl_sai2: sai2grp {
fsl,pins = <
MX8MN_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
MX8MN_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
MX8MN_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
MX8MN_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6
>;
};
pinctrl_sai3: sai3grp {
fsl,pins = <
MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
>;
};
pinctrl_spdif1: spdif1grp {
fsl,pins = <
MX8MN_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6
MX8MN_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6
>;
};
pinctrl_typec1: typec1grp {
fsl,pins = <
MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x140
MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x140
MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x140
MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x140
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190
MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
>;
};
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <
MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194
MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
>;
};
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196
MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166
>;
};
};

View File

@@ -1,613 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree File for the Kontron pitx-imx8m board.
*
* Copyright (C) 2021 Heiko Thiery <heiko.thiery@gmail.com>
*/
/dts-v1/;
#include "imx8mq.dtsi"
#include <dt-bindings/net/ti-dp83867.h>
/ {
model = "Kontron pITX-imx8m";
compatible = "kontron,pitx-imx8m", "fsl,imx8mq";
aliases {
i2c0 = &i2c1;
i2c1 = &i2c2;
i2c2 = &i2c3;
mmc0 = &usdhc1;
mmc1 = &usdhc2;
serial0 = &uart1;
serial1 = &uart2;
serial2 = &uart3;
spi0 = &qspi0;
spi1 = &ecspi2;
};
chosen {
stdout-path = "serial2:115200n8";
};
pcie0_refclk: pcie0-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
pcie1_refclk: pcie1-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2>;
regulator-name = "V_3V3_SD";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
off-on-delay-us = <20000>;
enable-active-high;
};
};
&ecspi2 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
status = "okay";
tpm@0 {
compatible = "infineon,slb9670";
reg = <0>;
spi-max-frequency = <43000000>;
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
reset-assert-us = <10>;
reset-deassert-us = <280>;
};
};
};
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
pmic@8 {
compatible = "fsl,pfuze100";
fsl,pfuze-support-disable-sw;
reg = <0x8>;
regulators {
sw1a_reg: sw1ab {
regulator-name = "V_0V9_GPU";
regulator-min-microvolt = <825000>;
regulator-max-microvolt = <1100000>;
};
sw1c_reg: sw1c {
regulator-name = "V_0V9_VPU";
regulator-min-microvolt = <825000>;
regulator-max-microvolt = <1100000>;
};
sw2_reg: sw2 {
regulator-name = "V_1V1_NVCC_DRAM";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-always-on;
};
sw3a_reg: sw3ab {
regulator-name = "V_1V0_DRAM";
regulator-min-microvolt = <825000>;
regulator-max-microvolt = <1100000>;
regulator-always-on;
};
sw4_reg: sw4 {
regulator-name = "V_1V8_S0";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
swbst_reg: swbst {
regulator-name = "NC";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5150000>;
};
snvs_reg: vsnvs {
regulator-name = "V_0V9_SNVS";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <3000000>;
regulator-always-on;
};
vref_reg: vrefddr {
regulator-name = "V_0V55_VREF_DDR";
regulator-always-on;
};
vgen1_reg: vgen1 {
regulator-name = "V_1V5_CSI";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
};
vgen2_reg: vgen2 {
regulator-name = "V_0V9_PHY";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <975000>;
regulator-always-on;
};
vgen3_reg: vgen3 {
regulator-name = "V_1V8_PHY";
regulator-min-microvolt = <1675000>;
regulator-max-microvolt = <1975000>;
regulator-always-on;
};
vgen4_reg: vgen4 {
regulator-name = "V_1V8_VDDA";
regulator-min-microvolt = <1625000>;
regulator-max-microvolt = <1875000>;
regulator-always-on;
};
vgen5_reg: vgen5 {
regulator-name = "V_3V3_PHY";
regulator-min-microvolt = <3075000>;
regulator-max-microvolt = <3625000>;
regulator-always-on;
};
vgen6_reg: vgen6 {
regulator-name = "V_2V8_CAM";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
};
fan-controller@1b {
compatible = "maxim,max6650";
reg = <0x1b>;
maxim,fan-microvolt = <5000000>;
};
rtc@32 {
compatible = "microcrystal,rv8803";
reg = <0x32>;
};
sensor@4b {
compatible = "national,lm75b";
reg = <0x4b>;
};
eeprom@51 {
compatible = "atmel,24c32";
reg = <0x51>;
pagesize = <32>;
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
};
/* M.2 B-key slot */
&pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0>;
reset-gpio = <&gpio1 9 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
<&clk IMX8MQ_CLK_PCIE1_AUX>,
<&clk IMX8MQ_CLK_PCIE1_PHY>,
<&pcie0_refclk>;
clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
status = "okay";
};
/* Intel Ethernet Controller I210/I211 */
&pcie1 {
clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
<&clk IMX8MQ_CLK_PCIE2_AUX>,
<&clk IMX8MQ_CLK_PCIE2_PHY>,
<&pcie1_refclk>;
clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
fsl,max-link-speed = <1>;
status = "okay";
};
&pgc_gpu {
power-supply = <&sw1a_reg>;
};
&pgc_vpu {
power-supply = <&sw1c_reg>;
};
&qspi0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi>;
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
m25p,fast-read;
spi-max-frequency = <50000000>;
};
};
&snvs_pwrkey {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
assigned-clocks = <&clk IMX8MQ_CLK_UART1>;
assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
assigned-clocks = <&clk IMX8MQ_CLK_UART2>;
assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
uart-has-rtscts;
assigned-clocks = <&clk IMX8MQ_CLK_UART3>;
assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
status = "okay";
};
&usb3_phy0 {
status = "okay";
};
&usb3_phy1 {
status = "okay";
};
&usb_dwc3_0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0>;
dr_mode = "otg";
hnp-disable;
srp-disable;
adp-disable;
maximum-speed = "high-speed";
status = "okay";
};
&usb_dwc3_1 {
dr_mode = "host";
status = "okay";
};
&usdhc1 {
assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
assigned-clock-rates = <400000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
vqmmc-supply = <&sw4_reg>;
bus-width = <8>;
non-removable;
no-sd;
no-sdio;
status = "okay";
};
&usdhc2 {
assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
assigned-clock-rates = <200000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
bus-width = <4>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
vmmc-supply = <&reg_usdhc2_vmmc>;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl_hog: hoggrp {
fsl,pins = <
MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19 /* TPM Reset */
MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x19 /* USB2 Hub Reset */
>;
};
pinctrl_gpio: gpiogrp {
fsl,pins = <
MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x19 /* GPIO0 */
MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x19 /* GPIO1 */
MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x19 /* GPIO2 */
MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x19 /* GPIO3 */
MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 /* GPIO4 */
MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x19 /* GPIO5 */
MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x19 /* GPIO6 */
MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x19 /* GPIO7 */
>;
};
pinctrl_pcie0: pcie0grp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x16 /* PCIE_PERST */
MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x16 /* W_DISABLE */
>;
};
pinctrl_reg_usdhc2: regusdhc2gpiogrp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x16
MX8MQ_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x16
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f
MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f
MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f
>;
};
pinctrl_qspi: qspigrp {
fsl,pins = <
MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
>;
};
pinctrl_ecspi2: ecspi2grp {
fsl,pins = <
MX8MQ_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x19
MX8MQ_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x19
MX8MQ_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x19
>;
};
pinctrl_ecspi2_cs: ecspi2csgrp {
fsl,pins = <
MX8MQ_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x19
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49
MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49
MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49
MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x49
MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x49
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100grp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>;
};
pinctrl_usdhc1_200mhz: usdhc1-200grp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x19
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100grp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200grp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xdf
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xdf
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xdf
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xdf
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xdf
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>;
};
pinctrl_usb0: usb0grp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x19
MX8MQ_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x19
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
>;
};
};

View File

@@ -1,45 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
// Copyright (C) 2021 Purism SPC <kernel@puri.sm>
/dts-v1/;
/*
* This file describes hardware that is shared among r3 ("Dogwood") and
* later revisions of the Librem 5 so it has to be included in dts there.
*/
#include "imx8mq-librem5.dtsi"
/ {
model = "Purism Librem 5r3";
compatible = "purism,librem5r3", "purism,librem5", "fsl,imx8mq";
};
&accel_gyro {
mount-matrix = "1", "0", "0",
"0", "1", "0",
"0", "0", "-1";
};
&bq25895 {
ti,battery-regulation-voltage = <4200000>; /* uV */
ti,charge-current = <1500000>; /* uA */
ti,termination-current = <144000>; /* uA */
};
&camera_front {
pinctrl-0 = <&pinctrl_csi1>, <&pinctrl_r3_camera_pwr>;
shutdown-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>;
};
&iomuxc {
pinctrl_r3_camera_pwr: r3camerapwrgrp {
fsl,pins = <
MX8MQ_IOMUXC_SPDIF_RX_GPIO5_IO4 0x83
>;
};
};
&proximity {
proximity-near-level = <25>;
};

View File

@@ -1,27 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
// Copyright (C) 2021 Purism SPC <kernel@puri.sm>
/dts-v1/;
#include "imx8mq-librem5-r3.dtsi"
/ {
model = "Purism Librem 5r4";
compatible = "purism,librem5r4", "purism,librem5", "fsl,imx8mq";
};
&bat {
maxim,rsns-microohm = <1667>;
};
&led_backlight {
led-max-microamp = <25000>;
};
&lcd_panel {
compatible = "ys,ys57pss36bh5gq";
};
&proximity {
proximity-near-level = <10>;
};

File diff suppressed because it is too large Load Diff

View File

@@ -9,3 +9,7 @@
&uart1 { /* console */
bootph-pre-ram;
};
&{/panel} {
compatible = "innolux,n125hce-gn1", "simple-panel";
};

View File

@@ -1,354 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2019-2021 MNT Research GmbH
* Copyright 2021 Lucas Stach <dev@lynxeye.de>
*/
/dts-v1/;
#include "imx8mq-nitrogen-som.dtsi"
/ {
model = "MNT Reform 2";
compatible = "mntre,reform2", "boundary,imx8mq-nitrogen8m-som", "fsl,imx8mq";
chassis-type = "laptop";
backlight: backlight {
compatible = "pwm-backlight";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_backlight>;
pwms = <&pwm2 0 10000 0>;
power-supply = <&reg_main_usb>;
enable-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
brightness-levels = <0 32 64 128 160 200 255>;
default-brightness-level = <6>;
};
panel {
compatible = "innolux,n125hce-gn1", "simple-panel";
power-supply = <&reg_main_3v3>;
backlight = <&backlight>;
no-hpd;
port {
panel_in: endpoint {
remote-endpoint = <&edp_bridge_out>;
};
};
};
pcie1_refclk: clock-pcie1-refclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
reg_main_5v: regulator-main-5v {
compatible = "regulator-fixed";
regulator-name = "5V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
reg_main_3v3: regulator-main-3v3 {
compatible = "regulator-fixed";
regulator-name = "3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
reg_main_usb: regulator-main-usb {
compatible = "regulator-fixed";
regulator-name = "USB_PWR";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&reg_main_5v>;
};
reg_main_1v8: regulator-main-1v8 {
compatible = "regulator-fixed";
regulator-name = "1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&reg_main_3v3>;
};
reg_main_1v2: regulator-main-1v2 {
compatible = "regulator-fixed";
regulator-name = "1V2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
vin-supply = <&reg_main_5v>;
};
sound {
compatible = "fsl,imx-audio-wm8960";
audio-cpu = <&sai2>;
audio-codec = <&wm8960>;
audio-routing =
"Headphone Jack", "HP_L",
"Headphone Jack", "HP_R",
"Ext Spk", "SPK_LP",
"Ext Spk", "SPK_LN",
"Ext Spk", "SPK_RP",
"Ext Spk", "SPK_RN",
"LINPUT1", "Mic Jack",
"Mic Jack", "MICB",
"LINPUT2", "Line In Jack",
"RINPUT2", "Line In Jack";
model = "wm8960-audio";
};
};
&dphy {
assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>;
assigned-clock-rates = <25000000>;
status = "okay";
};
&fec1 {
status = "okay";
};
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
wm8960: codec@1a {
compatible = "wlf,wm8960";
reg = <0x1a>;
clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
clock-names = "mclk";
#sound-dai-cells = <0>;
};
rtc@68 {
compatible = "nxp,pcf8523";
reg = <0x68>;
};
};
&i2c4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
clock-frequency = <400000>;
status = "okay";
edp_bridge: bridge@2c {
compatible = "ti,sn65dsi86";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_edp_bridge>;
reg = <0x2c>;
enable-gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
vccio-supply = <&reg_main_1v8>;
vpll-supply = <&reg_main_1v8>;
vcca-supply = <&reg_main_1v2>;
vcc-supply = <&reg_main_1v2>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
edp_bridge_in: endpoint {
remote-endpoint = <&mipi_dsi_out>;
};
};
port@1 {
reg = <1>;
edp_bridge_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
};
};
&lcdif {
assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>;
assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>;
/delete-property/assigned-clock-rates;
status = "okay";
};
&mipi_dsi {
status = "okay";
ports {
port@1 {
reg = <1>;
mipi_dsi_out: endpoint {
remote-endpoint = <&edp_bridge_in>;
};
};
};
};
&pcie1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie1>;
reset-gpio = <&gpio3 23 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
<&clk IMX8MQ_CLK_PCIE2_AUX>,
<&clk IMX8MQ_CLK_PCIE2_PHY>,
<&pcie1_refclk>;
clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
status = "okay";
};
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>;
status = "okay";
};
&reg_1p8v {
vin-supply = <&reg_main_5v>;
};
&reg_snvs {
vin-supply = <&reg_main_5v>;
};
&reg_arm_dram {
vin-supply = <&reg_main_5v>;
};
&reg_dram_1p1v {
vin-supply = <&reg_main_5v>;
};
&reg_soc_gpu_vpu {
vin-supply = <&reg_main_5v>;
};
&sai2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai2>;
assigned-clocks = <&clk IMX8MQ_CLK_SAI2>;
assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
assigned-clock-rates = <25000000>;
fsl,sai-mclk-direction-output;
fsl,sai-asynchronous;
status = "okay";
};
&snvs_rtc {
status = "disabled";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&usb3_phy0 {
vbus-supply = <&reg_main_usb>;
status = "okay";
};
&usb3_phy1 {
vbus-supply = <&reg_main_usb>;
status = "okay";
};
&usb_dwc3_0 {
dr_mode = "host";
status = "okay";
};
&usb_dwc3_1 {
dr_mode = "host";
status = "okay";
};
&usdhc2 {
assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
assigned-clock-rates = <200000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
vqmmc-supply = <&reg_main_3v3>;
vmmc-supply = <&reg_main_3v3>;
bus-width = <4>;
status = "okay";
};
&iomuxc {
pinctrl_backlight: backlightgrp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x3
>;
};
pinctrl_edp_bridge: edpbridgegrp {
fsl,pins = <
MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x1
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000022
MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000022
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000022
MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000022
>;
};
pinctrl_pcie1: pcie1grp {
fsl,pins = <
MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x16
>;
};
pinctrl_pwm2: pwm2grp {
fsl,pins = <
MX8MQ_IOMUXC_SPDIF_RX_PWM2_OUT 0x3
>;
};
pinctrl_sai2: sai2grp {
fsl,pins = <
MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6
MX8MQ_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0xd6
MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
MX8MQ_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0xd6
MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6
MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x45
MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x45
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
>;
};
};

View File

@@ -1,278 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2018 Boundary Devices
* Copyright 2021 Lucas Stach <dev@lynxeye.de>
*/
#include "imx8mq.dtsi"
/ {
model = "Boundary Devices i.MX8MQ Nitrogen8M";
compatible = "boundary,imx8mq-nitrogen8m-som", "fsl,imx8mq";
chosen {
stdout-path = &uart1;
};
reg_1p8v: regulator-fixed-1v8 {
compatible = "regulator-fixed";
regulator-name = "1P8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
reg_snvs: regulator-fixed-snvs {
compatible = "regulator-fixed";
regulator-name = "VDD_SNVS";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
&{/opp-table/opp-800000000} {
opp-microvolt = <1000000>;
};
&{/opp-table/opp-1000000000} {
opp-microvolt = <1000000>;
};
&A53_0 {
cpu-supply = <&reg_arm_dram>;
};
&A53_1 {
cpu-supply = <&reg_arm_dram>;
};
&A53_2 {
cpu-supply = <&reg_arm_dram>;
};
&A53_3 {
cpu-supply = <&reg_arm_dram>;
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
fsl,magic-packet;
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <4>;
interrupt-parent = <&gpio1>;
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <300>;
};
};
};
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
i2c-mux@70 {
compatible = "nxp,pca9546";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_pca9546>;
reg = <0x70>;
reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
#address-cells = <1>;
#size-cells = <0>;
i2c1a: i2c@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
reg_arm_dram: regulator@60 {
compatible = "fcs,fan53555";
reg = <0x60>;
regulator-name = "VDD_ARM_DRAM_1V";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
};
};
i2c1b: i2c@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
reg_dram_1p1v: regulator@60 {
compatible = "fcs,fan53555";
reg = <0x60>;
regulator-name = "NVCC_DRAM_1P1V";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-always-on;
};
};
i2c1c: i2c@2 {
reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
reg_soc_gpu_vpu: regulator@60 {
compatible = "fcs,fan53555";
reg = <0x60>;
regulator-name = "VDD_SOC_GPU_VPU";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-always-on;
};
};
i2c1d: i2c@3 {
reg = <3>;
#address-cells = <1>;
#size-cells = <0>;
};
};
};
&pgc_gpu {
power-supply = <&reg_soc_gpu_vpu>;
};
&pgc_vpu {
power-supply = <&reg_soc_gpu_vpu>;
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&usdhc1 {
assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
assigned-clock-rates = <400000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
vqmmc-supply = <&reg_1p8v>;
vmmc-supply = <&reg_snvs>;
bus-width = <8>;
non-removable;
no-mmc-hs400;
no-sdio;
no-sd;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0xd1
MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0xd1
MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x1
MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x41
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000022
MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000022
>;
};
pinctrl_i2c1_pca9546: i2c1-pca9546grp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x49
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x45
MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x45
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
>;
};
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
>;
};
};

View File

@@ -1,481 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2017-2019 NXP
*/
/dts-v1/;
#include "imx8mq.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>
/ {
model = "Google i.MX8MQ Phanbell";
compatible = "google,imx8mq-phanbell", "fsl,imx8mq";
chosen {
stdout-path = &uart1;
};
memory@40000000 {
device_type = "memory";
reg = <0x00000000 0x40000000 0 0x40000000>;
};
pmic_osc: clock-pmic {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "pmic_osc";
};
reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
compatible = "regulator-fixed";
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
fan: gpio-fan {
compatible = "gpio-fan";
gpio-fan,speed-map = <0 0 8600 1>;
gpios = <&gpio3 5 GPIO_ACTIVE_HIGH>;
#cooling-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_fan>;
status = "okay";
};
};
&A53_0 {
cpu-supply = <&buck2>;
};
&A53_1 {
cpu-supply = <&buck2>;
};
&A53_2 {
cpu-supply = <&buck2>;
};
&A53_3 {
cpu-supply = <&buck2>;
};
&cpu_thermal {
trips {
cpu_alert0: trip0 {
temperature = <75000>;
hysteresis = <2000>;
type = "passive";
};
cpu_alert1: trip1 {
temperature = <80000>;
hysteresis = <2000>;
type = "passive";
};
cpu_crit0: trip3 {
temperature = <90000>;
hysteresis = <2000>;
type = "critical";
};
fan_toggle0: trip4 {
temperature = <65000>;
hysteresis = <10000>;
type = "active";
};
};
cooling-maps {
map0 {
trip = <&cpu_alert0>;
cooling-device =
<&A53_0 0 1>; /* Exclude highest OPP */
};
map1 {
trip = <&cpu_alert1>;
cooling-device =
<&A53_0 0 2>; /* Exclude two highest OPPs */
};
map4 {
trip = <&fan_toggle0>;
cooling-device = <&fan 0 1>;
};
};
};
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
pmic: pmic@4b {
compatible = "rohm,bd71837";
reg = <0x4b>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
#clock-cells = <0>;
clocks = <&pmic_osc>;
clock-output-names = "pmic_clk";
interrupt-parent = <&gpio1>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
regulators {
buck1: BUCK1 {
regulator-name = "buck1";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <1250>;
rohm,dvs-run-voltage = <900000>;
rohm,dvs-idle-voltage = <900000>;
rohm,dvs-suspend-voltage = <800000>;
};
buck2: BUCK2 {
regulator-name = "buck2";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1000000>;
regulator-boot-on;
regulator-always-on;
rohm,dvs-run-voltage = <1000000>;
rohm,dvs-idle-voltage = <900000>;
};
buck3: BUCK3 {
regulator-name = "buck3";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
rohm,dvs-run-voltage = <900000>;
};
buck4: BUCK4 {
regulator-name = "buck4";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
regulator-always-on;
rohm,dvs-run-voltage = <900000>;
};
buck5: BUCK5 {
regulator-name = "buck5";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1350000>;
regulator-boot-on;
regulator-always-on;
};
buck6: BUCK6 {
regulator-name = "buck6";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
buck7: BUCK7 {
regulator-name = "buck7";
regulator-min-microvolt = <1605000>;
regulator-max-microvolt = <1995000>;
regulator-boot-on;
regulator-always-on;
};
buck8: BUCK8 {
regulator-name = "buck8";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1400000>;
regulator-boot-on;
regulator-always-on;
};
ldo1: LDO1 {
regulator-name = "ldo1";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo2: LDO2 {
regulator-name = "ldo2";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-boot-on;
regulator-always-on;
};
ldo3: LDO3 {
regulator-name = "ldo3";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo4: LDO4 {
regulator-name = "ldo4";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
ldo5: LDO5 {
regulator-name = "ldo5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo6: LDO6 {
regulator-name = "ldo6";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
ldo7: LDO7 {
regulator-name = "ldo7";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <50000>;
};
};
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
bus-width = <4>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_usdhc2_vmmc>;
status = "okay";
};
&usb3_phy0 {
status = "okay";
};
&usb_dwc3_0 {
dr_mode = "otg";
status = "okay";
};
&usb3_phy1 {
status = "okay";
};
&usb_dwc3_1 {
dr_mode = "host";
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
>;
};
pinctrl_gpio_fan: gpiofangrp {
fsl,pins = <
MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x16
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
>;
};
pinctrl_pmic: pmicirqgrp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>;
};
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
>;
};
};

View File

@@ -1,418 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018 Wandboard, Org.
* Copyright 2017 NXP
*
* Author: Richard Hu <hakahu@gmail.com>
*/
/dts-v1/;
#include "imx8mq.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>
/ {
model = "TechNexion PICO-PI-8M";
compatible = "technexion,pico-pi-imx8m", "fsl,imx8mq";
chosen {
stdout-path = &uart1;
};
pmic_osc: clock-pmic {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "pmic_osc";
};
reg_usb_otg_vbus: regulator-usb-otg-vbus {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_otg_vbus>;
compatible = "regulator-fixed";
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio3 14 GPIO_ACTIVE_LOW>;
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1 &pinctrl_enet_3v3>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
pmic: pmic@4b {
reg = <0x4b>;
compatible = "rohm,bd71837";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
clocks = <&pmic_osc>;
clock-names = "osc";
clock-output-names = "pmic_clk";
interrupt-parent = <&gpio1>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "irq";
regulators {
buck1: BUCK1 {
regulator-name = "buck1";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
regulator-ramp-delay = <1250>;
rohm,dvs-run-voltage = <900000>;
rohm,dvs-idle-voltage = <850000>;
rohm,dvs-suspend-voltage = <800000>;
};
buck2: BUCK2 {
regulator-name = "buck2";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
regulator-ramp-delay = <1250>;
rohm,dvs-run-voltage = <1000000>;
rohm,dvs-idle-voltage = <900000>;
};
buck3: BUCK3 {
regulator-name = "buck3";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
rohm,dvs-run-voltage = <1000000>;
};
buck4: BUCK4 {
regulator-name = "buck4";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
rohm,dvs-run-voltage = <1000000>;
};
buck5: BUCK5 {
regulator-name = "buck5";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1350000>;
regulator-boot-on;
};
buck6: BUCK6 {
regulator-name = "buck6";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
};
buck7: BUCK7 {
regulator-name = "buck7";
regulator-min-microvolt = <1605000>;
regulator-max-microvolt = <1995000>;
regulator-boot-on;
};
buck8: BUCK8 {
regulator-name = "buck8";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1400000>;
regulator-boot-on;
};
ldo1: LDO1 {
regulator-name = "ldo1";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo2: LDO2 {
regulator-name = "ldo2";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-boot-on;
regulator-always-on;
};
ldo3: LDO3 {
regulator-name = "ldo3";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
};
ldo4: LDO4 {
regulator-name = "ldo4";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
};
ldo5: LDO5 {
regulator-name = "ldo5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
};
ldo6: LDO6 {
regulator-name = "ldo6";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
};
ldo7: LDO7 {
regulator-name = "ldo7";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
};
};
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
};
&uart1 { /* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&usdhc1 {
assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
assigned-clock-rates = <400000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};
&usdhc2 {
assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
assigned-clock-rates = <200000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
bus-width = <4>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
status = "okay";
};
&usb3_phy0 {
status = "okay";
};
&usb3_phy1 {
status = "okay";
};
&usb_dwc3_1 {
dr_mode = "host";
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl_enet_3v3: enet3v3grp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x19
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f
MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f
>;
};
pinctrl_otg_vbus: otgvbusgrp {
fsl,pins = <
MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x19 /* USB OTG VBUS Enable */
>;
};
pinctrl_pmic: pmicirqgrp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49
MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49
MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x49
MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x49
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85
>;
};
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
>;
};
};

File diff suppressed because it is too large Load Diff

View File

@@ -10,7 +10,6 @@
};
&gpio1 {
reg = <0 0x47400000 0 0x1000>, <0 0x47400040 0 0x40>;
bootph-pre-ram;
};

View File

@@ -26,7 +26,6 @@
};
&gpio1 {
reg = <0 0x47400000 0 0x1000>, <0 0x47400000 0 0x40>;
bootph-pre-ram;
ctrl-sleep-moci-hog {

View File

@@ -9,6 +9,11 @@
#include "k3-binman.dtsi"
#ifdef CONFIG_TARGET_PHYCORE_AM62X_R5
&rcfg_yaml_tifs {
config = "tifs-rm-cfg.yaml";
};
&binman {
tiboot3-am62x-hs-phycore-som.bin {
filename = "tiboot3-am62x-hs-phycore-som.bin";

View File

@@ -7,6 +7,10 @@
#ifdef CONFIG_TARGET_VERDIN_AM62_R5
&rcfg_yaml_tifs {
config = "tifs-rm-cfg.yaml";
};
&binman {
tiboot3-am62x-hs-verdin.bin {
filename = "tiboot3-am62x-hs-verdin.bin";

View File

@@ -7,6 +7,10 @@
#if IS_ENABLED(CONFIG_TARGET_VERDIN_AM62P_R5)
&rcfg_yaml_tifs {
config = "tifs-rm-cfg.yaml";
};
&binman {
tiboot3-am62px-hs-fs-verdin.bin {
filename = "tiboot3-am62px-hs-fs-verdin.bin";

View File

@@ -12,6 +12,11 @@
#if defined(CONFIG_CPU_V7R)
&binman {
tiboot3_am69_gp {
insert-template = <&tiboot3_j784s4_gp>;
filename = "tiboot3-am69-gp-aquila.bin";
};
tiboot3-am69-hs {
insert-template = <&tiboot3_j784s4_hs>;
filename = "tiboot3-am69-hs-aquila.bin";
@@ -28,6 +33,10 @@
filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-enc.bin";
};
&ti_fs_gp {
filename = "ti-sysfw/ti-fs-firmware-j784s4-gp.bin";
};
&sysfw_inner_cert {
filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-cert.bin";
};
@@ -78,6 +87,72 @@
u-boot-unsigned {
insert-template = <&u_boot_unsigned>;
};
firmware-aquila-am69-gp.bin {
filename = "firmware-aquila-am69-gp.bin";
blob-ext@1 {
filename = "tiboot3-am69-gp-aquila.bin";
};
blob-ext@2 {
filename = "tispl.bin_unsigned";
/*
* This value matches CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR
* from R5 SPL config.
*/
offset = <0x80000>;
};
blob-ext@3 {
filename = "u-boot.img_unsigned";
offset = <(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)>;
};
};
firmware-aquila-am69-hs.bin {
filename = "firmware-aquila-am69-hs.bin";
blob-ext@1 {
filename = "tiboot3-am69-hs-aquila.bin";
};
blob-ext@2 {
filename = "tispl.bin";
/*
* This value matches CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR
* from R5 SPL config.
*/
offset = <0x80000>;
};
blob-ext@3 {
filename = "u-boot.img";
offset = <(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)>;
};
};
firmware-aquila-am69-hs-fs.bin {
filename = "firmware-aquila-am69-hs-fs.bin";
blob-ext@1 {
filename = "tiboot3-am69-hs-fs-aquila.bin";
};
blob-ext@2 {
filename = "tispl.bin";
/*
* This value matches CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR
* from R5 SPL config.
*/
offset = <0x80000>;
};
blob-ext@3 {
filename = "u-boot.img";
offset = <(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)>;
};
};
};
#endif

View File

@@ -0,0 +1,19 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2026, Qualcomm Innovation Center, Inc. All rights reserved.
*/
/ {
/* Will be removed when bootloader updates later */
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x3ee00000>,
<0x0 0xc0000000 0x0 0x0fd00000>,
<0xD 0x00000000 0x2 0x54100000>,
<0xA 0x80000000 0x1 0x80000000>,
<0x9 0x00000000 0x1 0x80000000>,
<0x1 0x00000000 0x3 0x00000000>,
<0x0 0xd0000000 0x0 0x01900000>,
<0x0 0xd3500000 0x0 0x2cb00000>;
};
};

View File

@@ -0,0 +1,130 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source extras for U-Boot for the Ironhide CM33 board
*
* Copyright (C) 2026 Renesas Electronics Corp.
*/
#include "r8a78000-ironhide-u-boot.dtsi"
/ {
model = "Renesas Ironhide board CM33 based on r8a78000";
compatible = "renesas,ironhide-cm33", "renesas,r8a78000-cm33";
aliases {
serial1 = &hscif1;
};
chosen {
stdout-path = "serial1:1843200n8";
};
/delete-node/ firmware;
/delete-node/ memory@40000000;
/delete-node/ memory@60600000;
/delete-node/ memory@1080000000;
/delete-node/ memory@1200000000;
/delete-node/ memory@1400000000;
/delete-node/ memory@1600000000;
/delete-node/ memory@1800000000;
/delete-node/ memory@1a00000000;
/delete-node/ memory@1c00000000;
/delete-node/ memory@1e00000000;
/delete-node/ reserved-memory;
memory@b8400000 {
device_type = "memory";
reg = <0x0 0xb8400000 0x0 0x00200000>;
};
dummy_clk_rclk: dummy-clk-rclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
};
dummy_clk_sasyncd4_rt: dummy-clk-sasyncd4-rt {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <16660000>;
};
ctl: syscon@5fffd000 {
compatible = "renesas,r8a78000-ctl",
"renesas,rcar-gen5-ctl",
"syscon";
reg = <0 0x5fffd000 0 0xc4>;
};
watchdog@5fffd800 {
compatible = "renesas,r8a78000-wwdt",
"renesas,rcar-gen5-wwdt";
clocks = <&dummy_clk_rclk>, <&dummy_clk_sasyncd4_rt>;
clock-names = "cnt", "bus";
reg = <0 0x5fffd800 0 0x10>;
syscon = <&ctl>;
};
scp@c1340000 {
compatible = "renesas,r8a78000-rproc";
reg = <0 0xc1340000 0 0x80000>;
};
};
&cpg {
/delete-property/ firmware;
};
&eth_pcs {
/* Stub clock */
clocks = <&dummy_clk_rclk>;
};
&hscif1 {
pinctrl-0 = <&hscif1_pins>;
pinctrl-names = "default";
uart-has-rtscts;
status = "okay";
};
&mdlc_hscn {
/delete-property/ firmware;
};
&mdlc_pere {
/delete-property/ firmware;
};
&mmc0 {
status = "disabled";
};
&mp_phy {
/* Stub clock */
clocks = <&dummy_clk_rclk>;
};
&pfc {
hscif1_pins: hscif1 {
groups = "hscif1_data", "hscif1_ctrl";
function = "hscif1";
};
};
&rswitch3 {
/* Stub clock */
clocks = <&dummy_clk_rclk>;
};
&soc {
dma-ranges = <0 0x00000000 0 0xa0000000 0 0x20000000>;
};
&ufs0 {
/delete-property/ power-domains;
};
&ufs1 {
/delete-property/ power-domains;
status = "disabled";
};

View File

@@ -0,0 +1,8 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the Ironhide CM33 board
*
* Copyright (C) 2026 Renesas Electronics Corp.
*/
#include "../../../dts/upstream/src/arm64/renesas/r8a78000-ironhide.dts"

View File

@@ -5,4 +5,190 @@
* Copyright (C) 2025 Renesas Electronics Corp.
*/
#include <dt-bindings/net/ti-dp83869.h>
#include "r8a78000-u-boot.dtsi"
/ {
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
mmc0 = &mmc0;
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
&cpg {
firmware = <&scmi>;
};
&eth_pcs {
phys = <&mp_phy 2 1>;
status = "okay";
};
&hscif0 {
pinctrl-0 = <&hscif0_pins>;
pinctrl-names = "default";
};
&i2c0 {
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
clock-frequency = <400000>;
status = "okay";
eeprom@50 {
compatible = "rohm,br24g01", "atmel,24c01";
reg = <0x50>;
pagesize = <8>;
};
};
&i2c1 {
pinctrl-0 = <&i2c1_pins>;
pinctrl-names = "default";
clock-frequency = <400000>;
status = "okay";
};
&mdlc_hscn {
firmware = <&scmi>;
};
&mdlc_pere {
firmware = <&scmi>;
};
&mmc0 {
pinctrl-0 = <&mmc0_pins>;
pinctrl-1 = <&mmc0_pins>;
pinctrl-names = "default", "state_uhs";
bus-width = <8>;
full-pwr-cycle-in-suspend;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
no-sd;
no-sdio;
non-removable;
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
status = "okay";
};
&mp_phy {
status = "okay";
};
&pfc {
pinctrl-0 = <&scif_clk_pins>;
pinctrl-names = "default";
eth25g2_pins: eth25g2 {
groups = "eth25g2_mdio", "eth25g2_link", "eth25g2_phyint";
function = "eth25g2";
drive-strength = <24>;
};
ethes0_pins: ethes0 {
groups = "ethes0_match", "ethes0_capture", "ethes0_pps";
function = "ethes0";
drive-strength = <24>;
};
hscif0_pins: hscif0 {
groups = "hscif0_data", "hscif0_ctrl";
function = "hscif0";
};
i2c0_pins: i2c0 {
groups = "i2c0";
function = "i2c0";
};
i2c1_pins: i2c1 {
groups = "i2c1";
function = "i2c1";
};
mmc0_pins: mmc0 {
groups = "mmc0_data8", "mmc0_ctrl", "mmc0_ds";
function = "mmc0";
drive-strength = <24>;
};
rsw3_pins: rsw3 {
groups = "rsw3_match", "rsw3_capture", "rsw3_pps";
function = "rsw3";
drive-strength = <24>;
};
scif_clk_pins: scif-clk {
groups = "scif_clk";
function = "scif_clk";
};
};
&rswitch3 {
pinctrl-0 = <&rsw3_pins>, <&eth25g2_pins>, <&ethes0_pins>;
pinctrl-names = "default";
status = "okay";
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
/*
* NOTE: Only port@4 is configured for R-Car X5H board.
* Other ports (0-3, 5-12) are currently unused or not
* connected.
*/
port@4 {
reg = <4>;
renesas,connect_to_xpcs;
phy-handle = <&dp83869_phy>;
phy-mode = "sgmii";
phys = <&eth_pcs 5>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
dp83869_phy: ethernet-phy@2 {
reg = <2>;
ti,sgmii-interface;
ti,max-output-impedance;
ti,refclk-output-enable;
ti,clk-output-sel = <DP83869_CLK_O_SEL_REF_CLK>;
};
};
};
};
};
&ufs0 {
status = "okay";
};
&ufs1 {
status = "okay";
};

View File

@@ -1,257 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the Ironhide board
*
* Copyright (C) 2025 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r8a78000.dtsi"
#include <dt-bindings/net/ti-dp83869.h>
/ {
model = "Renesas Ironhide board based on r8a78000";
compatible = "renesas,ironhide", "renesas,r8a78000";
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
i2c6 = &i2c6;
i2c7 = &i2c7;
i2c8 = &i2c8;
mmc0 = &mmc0;
serial0 = &hscif0;
};
chosen {
stdout-path = "serial0:1843200n8";
};
memory@40000000 {
device_type = "memory";
reg = <0x0 0x40000000 0x0 0x80000000>;
};
memory@1080000000 {
device_type = "memory";
reg = <0x10 0x80000000 0x0 0x80000000>;
};
memory@1200000000 {
device_type = "memory";
reg = <0x12 0x00000000 0x1 0x00000000>;
};
memory@1400000000 {
device_type = "memory";
reg = <0x14 0x00000000 0x1 0x00000000>;
};
memory@1600000000 {
device_type = "memory";
reg = <0x16 0x00000000 0x1 0x00000000>;
};
memory@1800000000 {
device_type = "memory";
reg = <0x18 0x00000000 0x1 0x00000000>;
};
memory@1a00000000 {
device_type = "memory";
reg = <0x1a 0x00000000 0x1 0x00000000>;
};
memory@1c00000000 {
device_type = "memory";
reg = <0x1c 0x00000000 0x1 0x00000000>;
};
memory@1e00000000 {
device_type = "memory";
reg = <0x1e 0x00000000 0x1 0x00000000>;
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
&extal_clk {
clock-frequency = <16666600>;
};
&extalr_clk {
clock-frequency = <32768>;
};
&hscif0 {
pinctrl-0 = <&hscif0_pins>;
pinctrl-names = "default";
uart-has-rtscts;
status = "okay";
};
&i2c0 {
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
clock-frequency = <400000>;
status = "okay";
eeprom@50 {
compatible = "rohm,br24g01", "atmel,24c01";
reg = <0x50>;
pagesize = <8>;
};
};
&i2c1 {
pinctrl-0 = <&i2c1_pins>;
pinctrl-names = "default";
clock-frequency = <400000>;
status = "okay";
};
&eth_pcs {
phys = <&mp_phy 2 1>;
status = "okay";
};
&mmc0 {
pinctrl-0 = <&mmc0_pins>;
pinctrl-1 = <&mmc0_pins>;
pinctrl-names = "default", "state_uhs";
bus-width = <8>;
full-pwr-cycle-in-suspend;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
no-sd;
no-sdio;
non-removable;
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
status = "okay";
};
&ufs0 {
status = "okay";
};
&ufs1 {
status = "okay";
};
&mp_phy {
status = "okay";
};
&pfc {
pinctrl-0 = <&scif_clk_pins>;
pinctrl-names = "default";
eth25g2_pins: eth25g2 {
groups = "eth25g2_mdio", "eth25g2_link", "eth25g2_phyint";
function = "eth25g2";
drive-strength = <24>;
};
ethes0_pins: ethes0 {
groups = "ethes0_match", "ethes0_capture", "ethes0_pps";
function = "ethes0";
drive-strength = <24>;
};
hscif0_pins: hscif0 {
groups = "hscif0_data", "hscif0_ctrl";
function = "hscif0";
};
i2c0_pins: i2c0 {
groups = "i2c0";
function = "i2c0";
};
i2c1_pins: i2c1 {
groups = "i2c1";
function = "i2c1";
};
mmc0_pins: mmc0 {
groups = "mmc0_data8", "mmc0_ctrl", "mmc0_ds";
function = "mmc0";
drive-strength = <24>;
};
rsw3_pins: rsw3 {
groups = "rsw3_match", "rsw3_capture", "rsw3_pps";
function = "rsw3";
drive-strength = <24>;
};
scif_clk_pins: scif-clk {
groups = "scif_clk";
function = "scif_clk";
};
};
&rswitch3 {
pinctrl-0 = <&rsw3_pins>, <&eth25g2_pins>, <&ethes0_pins>;
pinctrl-names = "default";
status = "okay";
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
/*
* NOTE: Only port@4 is configured for R-Car X5H board.
* Other ports (0-3, 5-12) are currently unused or not
* connected.
*/
port@4 {
reg = <4>;
renesas,connect_to_xpcs;
phy-handle = <&dp83869_phy>;
phy-mode = "sgmii";
phys = <&eth_pcs 5>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
dp83869_phy: ethernet-phy@2 {
reg = <2>;
ti,sgmii-interface;
ti,max-output-impedance;
ti,refclk-output-enable;
ti,clk-output-sel = <DP83869_CLK_O_SEL_REF_CLK>;
};
};
};
};
};
&scif_clk {
clock-frequency = <26000000>;
};

View File

@@ -5,9 +5,41 @@
* Copyright (C) 2025 Renesas Electronics Corp.
*/
#include <dt-bindings/clock/r8a78000-clock-scmi.h>
#include <dt-bindings/power/r8a78000-power-scmi.h>
#include <dt-bindings/reset/r8a78000-reset-scmi.h>
/ {
soc {
bootph-all;
firmware {
scmi: scmi {
compatible = "arm,scmi";
arm,poll-transport;
mbox-names = "tx", "rx";
mboxes = <&mailbox 0>, <&mailbox 1>;
shmem = <&cpu_scp_lpri0>, <&cpu_scp_hpri0>;
#address-cells = <1>;
#size-cells = <0>;
protocol@11 {
reg = <0x11>;
#power-domain-cells = <1>;
};
protocol@14 {
reg = <0x14>;
#clock-cells = <1>;
};
protocol@16 {
reg = <0x16>;
#reset-cells = <1>;
};
};
};
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
};
/* Placeholder clock until the clock provider is in place */
@@ -32,16 +64,12 @@
clk_stub_mmc: clk-stub-mmc {
compatible = "renesas,compound-clock";
#clock-cells = <0>;
clocks = <&scmi_clk SCP_CLOCK_ID_MDLC_SDHI0>,
<&scmi_clk 1691>;
clocks = <&cpg SCP_CLOCK_ID_MDLC_SDHI0>,
<&cpg SCP_CLOCK_ID_CLK_S0D6_PERE_MAIN>;
clock-names = "mdlc", "per";
};
};
&cpg {
bootph-all;
};
&extal_clk {
bootph-all;
};
@@ -50,90 +78,311 @@
bootph-all;
};
&gpio0 {
clocks = <&clk_stub_gpio>;
};
&gpio1 {
clocks = <&clk_stub_gpio>;
};
&gpio2 {
clocks = <&clk_stub_gpio>;
};
&gpio3 {
clocks = <&clk_stub_gpio>;
};
&gpio4 {
clocks = <&clk_stub_gpio>;
};
&gpio5 {
clocks = <&clk_stub_gpio>;
};
&gpio6 {
clocks = <&clk_stub_gpio>;
};
&gpio7 {
clocks = <&clk_stub_gpio>;
};
&gpio8 {
clocks = <&clk_stub_gpio>;
};
&gpio9 {
clocks = <&clk_stub_gpio>;
};
&gpio10 {
clocks = <&clk_stub_gpio>;
};
&i2c0 {
clocks = <&clk_stub_i2c0>;
};
&i2c1 {
clocks = <&clk_stub_i2c1>;
};
&i2c2 {
clocks = <&clk_stub_i2c1>;
};
&i2c3 {
clocks = <&clk_stub_i2c1>;
};
&i2c4 {
clocks = <&clk_stub_i2c1>;
};
&i2c5 {
clocks = <&clk_stub_i2c1>;
};
&i2c6 {
clocks = <&clk_stub_i2c1>;
};
&i2c7 {
clocks = <&clk_stub_i2c1>;
};
&i2c8 {
clocks = <&clk_stub_i2c1>;
};
&mmc0 {
clocks = <&clk_stub_mmc>;
};
&prr {
bootph-all;
};
&soc {
bootph-all;
mailbox: mfis_mbox@18842000 {
compatible = "renesas,mfis-mbox";
#mbox-cells = <1>;
reg = <0 0x18842004 0 0x8>;
interrupts = <GIC_SPI 4362 IRQ_TYPE_LEVEL_HIGH>;
};
pfc: pinctrl@c0400000 {
compatible = "renesas,pfc-r8a78000";
reg = <0 0xc1080000 0 0x104>, <0 0xc1080800 0 0x104>,
<0 0xc1081000 0 0x104>, <0 0xc0800000 0 0x104>,
<0 0xc0800800 0 0x104>, <0 0xc0400000 0 0x104>,
<0 0xc0400800 0 0x104>, <0 0xc0401000 0 0x104>,
<0 0xc0401800 0 0x104>, <0 0xc9b00000 0 0x104>,
<0 0xc9b00800 0 0x104>;
};
mmc0: mmc@c0880000 {
compatible = "renesas,rcar-gen5-sdhi";
reg = <0 0xc0880000 0 0x2000>;
clock-names = "core";
max-frequency = <200000000>;
clocks = <&clk_stub_mmc>;
status = "disabled";
};
mdlc_pere: system-controller@c08f0000 {
compatible = "renesas,r8a78000-mdlc";
reg = <0 0xc08f0000 0 0x1000>;
#power-domain-cells = <1>;
#reset-cells = <1>;
bootph-all;
};
ufs0: ufs@c0a80000 {
compatible = "renesas,r8a78000-ufs";
reg = <0 0xc0a80000 0 0x1100>, <0 0xc0a00000 0 0x40000>;
reg-names = "hcr", "phy";
interrupts = <GIC_SPI 4284 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&mdlc_pere X5H_POWER_DOMAIN_ID_UFS0>;
clocks = <&cpg SCP_CLOCK_ID_MDLC_UFS0>;
resets = <&mdlc_pere SCP_RESET_DOMAIN_ID_UFS0>;
freq-table-hz = <38400000 38400000>;
status = "disabled";
};
ufs1: ufs@c0a90000 {
compatible = "renesas,r8a78000-ufs";
reg = <0 0xc0a90000 0 0x1100>, <0 0xc0a40000 0 0x40000>;
reg-names = "hcr", "phy";
interrupts = <GIC_SPI 4285 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&mdlc_pere X5H_POWER_DOMAIN_ID_UFS1>;
clocks = <&cpg SCP_CLOCK_ID_MDLC_UFS1>;
resets = <&mdlc_pere SCP_RESET_DOMAIN_ID_UFS1>;
freq-table-hz = <38400000 38400000>;
status = "disabled";
};
scp: sram@c1000000 {
compatible = "arm,rcar-sram-ns", "mmio-sram";
reg = <0x0 0xc1000000 0x0 0x80000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x0 0xc1000000 0x80000>;
cpu_scp_lpri0: scp-shmem@60000 {
compatible = "arm,rcar-scp-shmem", "arm,scmi-shmem";
reg = <0x61200 0x0100>;
};
cpu_scp_hpri0: scp-shmem@60300 {
compatible = "arm,rcar-scp-shmem", "arm,scmi-shmem";
reg = <0x61300 0x100>;
};
};
cpg: clock-controller@c1320000 {
compatible = "renesas,r8a78000-cpg";
reg = <0 0xc1320000 0 0x10000>;
clocks = <&extal_clk>, <&extalr_clk>;
clock-names = "extal", "extalr";
#clock-cells = <1>;
bootph-all;
};
i2c0: i2c@c11d0000 {
compatible = "renesas,i2c-r8a78000",
"renesas,rcar-gen5-i2c";
reg = <0 0xc11d0000 0 0x40>;
i2c-scl-internal-delay-ns = <110>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clk_stub_i2c0>;
status = "disabled";
};
i2c1: i2c@c06c0000 {
compatible = "renesas,i2c-r8a78000",
"renesas,rcar-gen5-i2c";
reg = <0 0xc06c0000 0 0x40>;
i2c-scl-internal-delay-ns = <110>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clk_stub_i2c1>;
status = "disabled";
};
gpio0: gpio@c1080110 {
compatible = "renesas,gpio-r8a78000",
"renesas,rcar-gen5-gpio";
reg = <0 0xc1080110 0 0xc0>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 0 28>;
clocks = <&clk_stub_gpio>;
};
gpio1: gpio@c1080910 {
compatible = "renesas,gpio-r8a78000",
"renesas,rcar-gen5-gpio";
reg = <0 0xc1080910 0 0xc0>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 32 22>;
clocks = <&clk_stub_gpio>;
};
gpio2: gpio@c1081110 {
compatible = "renesas,gpio-r8a78000",
"renesas,rcar-gen5-gpio";
reg = <0 0xc1081110 0 0xc0>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 64 29>;
clocks = <&clk_stub_gpio>;
};
gpio3: gpio@c0800110 {
compatible = "renesas,gpio-r8a78000",
"renesas,rcar-gen5-gpio";
reg = <0 0xc0800110 0 0xc0>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 96 17>;
clocks = <&clk_stub_gpio>;
};
gpio4: gpio@c0800910 {
compatible = "renesas,gpio-r8a78000",
"renesas,rcar-gen5-gpio";
reg = <0 0xc0800910 0 0xc0>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 128 16>;
clocks = <&clk_stub_gpio>;
};
gpio5: gpio@c0400110 {
compatible = "renesas,gpio-r8a78000",
"renesas,rcar-gen5-gpio";
reg = <0 0xc0400110 0 0xc0>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 160 23>;
clocks = <&clk_stub_gpio>;
};
gpio6: gpio@c0400910 {
compatible = "renesas,gpio-r8a78000",
"renesas,rcar-gen5-gpio";
reg = <0 0xc0400910 0 0xc0>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 192 31>;
clocks = <&clk_stub_gpio>;
};
gpio7: gpio@c0401110 {
compatible = "renesas,gpio-r8a78000",
"renesas,rcar-gen5-gpio";
reg = <0 0xc0401110 0 0xc0>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 224 31>;
clocks = <&clk_stub_gpio>;
};
gpio8: gpio@c0401910 {
compatible = "renesas,gpio-r8a78000",
"renesas,rcar-gen5-gpio";
reg = <0 0xc0401910 0 0xc0>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 256 32>;
gpio-reserved-ranges = <16 10>;
clocks = <&clk_stub_gpio>;
};
gpio9: gpio@c9b00110 {
compatible = "renesas,gpio-r8a78000",
"renesas,rcar-gen5-gpio";
reg = <0 0xc9b00110 0 0xc0>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 288 17>;
clocks = <&clk_stub_gpio>;
};
gpio10: gpio@c9b00910 {
compatible = "renesas,gpio-r8a78000",
"renesas,rcar-gen5-gpio";
reg = <0 0xc9b00910 0 0xc0>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 320 14>;
clocks = <&clk_stub_gpio>;
};
mp_phy: mp_phy@c9a00000 {
compatible = "renesas,r8a78000-multi-protocol-phy";
reg = <0 0xc9a00000 0 0x100000>;
#phy-cells = <2>;
clocks = <&cpg SCP_CLOCK_ID_MDLC_MPPHY01>,
<&cpg SCP_CLOCK_ID_MDLC_MPPHY11>,
<&cpg SCP_CLOCK_ID_MDLC_MPPHY21>,
<&cpg SCP_CLOCK_ID_MDLC_MPPHY31>,
<&cpg SCP_CLOCK_ID_MDLC_MPPHY02>;
clock-names = "mpphy01", "mpphy11", "mpphy21",
"mpphy31", "mpphy02";
power-domains = <&mdlc_hscn X5H_POWER_DOMAIN_ID_MPP0>,
<&mdlc_hscn X5H_POWER_DOMAIN_ID_MPP1>,
<&mdlc_hscn X5H_POWER_DOMAIN_ID_MPP2>,
<&mdlc_hscn X5H_POWER_DOMAIN_ID_MPP3>;
resets = <&mdlc_hscn SCP_RESET_DOMAIN_ID_MPPHY01>,
<&mdlc_hscn SCP_RESET_DOMAIN_ID_MPPHY11>,
<&mdlc_hscn SCP_RESET_DOMAIN_ID_MPPHY21>,
<&mdlc_hscn SCP_RESET_DOMAIN_ID_MPPHY31>,
<&mdlc_hscn SCP_RESET_DOMAIN_ID_MPPHY02>;
status = "disabled";
};
rswitch3: ethernet@c9bc0000 {
compatible = "renesas,r8a78000-ether-switch3",
"renesas,etherswitch";
reg = <0 0xc9bc0000 0 0x40000>, <0 0xc9b80000 0 0x240000>;
reg-names = "base", "secure_base";
power-domains = <&mdlc_hscn X5H_POWER_DOMAIN_ID_RSW>;
clocks = <&cpg SCP_CLOCK_ID_MDLC_RSW3>,
<&cpg SCP_CLOCK_ID_MDLC_RSW3TSN>,
<&cpg SCP_CLOCK_ID_MDLC_RSW3AES>,
<&cpg SCP_CLOCK_ID_MDLC_RSW3TSNTES0>,
<&cpg SCP_CLOCK_ID_MDLC_RSW3TSNTES1>,
<&cpg SCP_CLOCK_ID_MDLC_RSW3TSNTES2>,
<&cpg SCP_CLOCK_ID_MDLC_RSW3TSNTES3>,
<&cpg SCP_CLOCK_ID_MDLC_RSW3TSNTES4>,
<&cpg SCP_CLOCK_ID_MDLC_RSW3TSNTES5>,
<&cpg SCP_CLOCK_ID_MDLC_RSW3TSNTES6>,
<&cpg SCP_CLOCK_ID_MDLC_RSW3TSNTES7>,
<&cpg SCP_CLOCK_ID_MDLC_RSW3MFWD>;
clock-names = "rsw3", "rsw3tsn", "rsw3aes",
"rsw3tsntes0", "rsw3tsntes1", "rsw3tsntes2",
"rsw3tsntes3", "rsw3tsntes4", "rsw3tsntes5",
"rsw3tsntes6", "rsw3tsntes7", "rsw3mfwd";
status = "disabled";
};
eth_pcs: phy@c9c50000 {
compatible = "renesas,r8a78000-ether-pcs";
reg = <0 0xc9c50000 0 0x4000>;
#phy-cells = <1>;
clocks = <&cpg SCP_CLOCK_ID_MDLC_XPCS0>,
<&cpg SCP_CLOCK_ID_MDLC_XPCS1>,
<&cpg SCP_CLOCK_ID_MDLC_XPCS2>,
<&cpg SCP_CLOCK_ID_MDLC_XPCS3>,
<&cpg SCP_CLOCK_ID_MDLC_XPCS4>,
<&cpg SCP_CLOCK_ID_MDLC_XPCS5>,
<&cpg SCP_CLOCK_ID_MDLC_XPCS6>,
<&cpg SCP_CLOCK_ID_MDLC_XPCS7>;
clock-names = "xpcs0", "xpcs1", "xpcs2", "xpcs3",
"xpcs4", "xpcs5", "xpcs6", "xpcs7";
resets = <&mdlc_hscn SCP_RESET_DOMAIN_ID_XPCS0>,
<&mdlc_hscn SCP_RESET_DOMAIN_ID_XPCS1>,
<&mdlc_hscn SCP_RESET_DOMAIN_ID_XPCS2>,
<&mdlc_hscn SCP_RESET_DOMAIN_ID_XPCS3>,
<&mdlc_hscn SCP_RESET_DOMAIN_ID_XPCS4>,
<&mdlc_hscn SCP_RESET_DOMAIN_ID_XPCS5>,
<&mdlc_hscn SCP_RESET_DOMAIN_ID_XPCS6>,
<&mdlc_hscn SCP_RESET_DOMAIN_ID_XPCS7>;
reset-names = "xpcs0", "xpcs1", "xpcs2", "xpcs3",
"xpcs4", "xpcs5", "xpcs6", "xpcs7";
status = "disabled";
};
mdlc_hscn: system-controller@c9c90000 {
compatible = "renesas,r8a78000-mdlc";
reg = <0 0xc9c90000 0 0x1000>;
#power-domain-cells = <1>;
#reset-cells = <1>;
bootph-all;
};
};

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#include "t8103-u-boot.dtsi"

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// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Apple Mac mini (M1, 2020)
*
* target-type: J274
*
* Copyright The Asahi Linux Contributors
*/
/dts-v1/;
#include "t8103.dtsi"
#include "t8103-jxxx.dtsi"
/ {
compatible = "apple,j274", "apple,t8103", "apple,arm-platform";
model = "Apple Mac mini (M1, 2020)";
aliases {
ethernet0 = &ethernet0;
};
};
&wifi0 {
brcm,board-type = "apple,atlantisb";
};
/*
* Provide labels for the USB type C ports.
*/
&typec0 {
label = "USB-C Back-left";
};
&typec1 {
label = "USB-C Back-right";
};
/*
* Force the bus number assignments so that we can declare some of the
* on-board devices and properties that are populated by the bootloader
* (such as MAC addresses).
*/
&port01 {
bus-range = <2 2>;
};
&port02 {
bus-range = <3 3>;
ethernet0: ethernet@0,0 {
reg = <0x30000 0x0 0x0 0x0 0x0>;
/* To be filled by the loader */
local-mac-address = [00 10 18 00 00 00];
};
};
&i2c1 {
clock-frequency = <50000>;
speaker_amp: codec@31 {
compatible = "ti,tas5770l", "ti,tas2770";
reg = <0x31>;
reset-gpios = <&pinctrl_ap 181 GPIO_ACTIVE_HIGH>;
#sound-dai-cells = <0>;
};
};
&i2c2 {
status = "okay";
clock-frequency = <50000>;
jack_codec: codec@48 {
compatible = "cirrus,cs42l83", "cirrus,cs42l42";
reg = <0x48>;
reset-gpios = <&pinctrl_nub 11 GPIO_ACTIVE_HIGH>;
interrupt-parent = <&pinctrl_ap>;
interrupts = <183 IRQ_TYPE_LEVEL_LOW>;
#sound-dai-cells = <0>;
cirrus,ts-inv = <1>;
};
};
/ {
sound {
compatible = "simple-audio-card";
simple-audio-card,name = "Mac mini integrated audio";
#address-cells = <1>;
#size-cells = <0>;
simple-audio-card,dai-link@0 {
reg = <0>;
format = "left_j";
tdm-slot-width = <32>;
mclk-fs = <64>;
link0_cpu: cpu {
sound-dai = <&mca 0>;
bitclock-master;
frame-master;
};
link0_codec: codec {
sound-dai = <&speaker_amp>;
};
};
simple-audio-card,dai-link@1 {
bitclock-inversion;
frame-inversion;
reg = <1>;
format = "i2s";
mclk-fs = <64>;
tdm-slot-width = <32>;
link1_cpu: cpu {
sound-dai = <&mca 2>;
bitclock-master;
frame-master;
};
link1_codec: codec {
sound-dai = <&jack_codec>;
};
};
};
};

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#include "t8103-u-boot.dtsi"

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// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Apple MacBook Pro (13-inch, M1, 2020)
*
* target-type: J293
*
* Copyright The Asahi Linux Contributors
*/
/dts-v1/;
#include "t8103.dtsi"
#include "t8103-jxxx.dtsi"
/ {
compatible = "apple,j293", "apple,t8103", "apple,arm-platform";
model = "Apple MacBook Pro (13-inch, M1, 2020)";
};
&wifi0 {
brcm,board-type = "apple,honshu";
};
/*
* Provide labels for the USB type C ports.
*/
&typec0 {
label = "USB-C Left-back";
};
&typec1 {
label = "USB-C Left-front";
};
&spi3 {
status = "okay";
hid-transport@0 {
compatible = "apple,spi-hid-transport";
reg = <0>;
spi-max-frequency = <8000000>;
/*
* cs-setup and cs-hold delays are derived from Apple's ADT
* Mac OS driver meta data secify 45 us for 'cs to clock' and
* 'clock to cs' delays.
*/
spi-cs-setup-delay-ns = <20000>;
spi-cs-hold-delay-ns = <20000>;
spi-cs-inactive-delay-ns = <250000>;
spien-gpios = <&pinctrl_ap 195 0>;
interrupts-extended = <&pinctrl_nub 13 IRQ_TYPE_LEVEL_LOW>;
};
};
/*
* Remove unused PCIe ports and disable the associated DARTs.
*/
&pcie0_dart_1 {
status = "disabled";
};
&pcie0_dart_2 {
status = "disabled";
};
/delete-node/ &port01;
/delete-node/ &port02;
&i2c2 {
status = "okay";
clock-frequency = <50000>;
jack_codec: codec@48 {
compatible = "cirrus,cs42l83", "cirrus,cs42l42";
reg = <0x48>;
reset-gpios = <&pinctrl_nub 11 GPIO_ACTIVE_HIGH>;
interrupt-parent = <&pinctrl_ap>;
interrupts = <183 IRQ_TYPE_LEVEL_LOW>;
#sound-dai-cells = <0>;
cirrus,ts-inv = <1>;
};
};
&i2c4 {
status = "okay";
};
/ {
sound {
compatible = "simple-audio-card";
simple-audio-card,name = "MacBook integrated audio";
#address-cells = <1>;
#size-cells = <0>;
simple-audio-card,dai-link@0 {
bitclock-inversion;
frame-inversion;
reg = <0>;
format = "i2s";
mclk-fs = <64>;
tdm-slot-width = <32>;
link0_cpu: cpu {
sound-dai = <&mca 2>;
bitclock-master;
frame-master;
};
link0_codec: codec {
sound-dai = <&jack_codec>;
};
};
};
};

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#include "t8103-u-boot.dtsi"

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@@ -1,111 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Apple MacBook Air (M1, 2020)
*
* target-type: J313
*
* Copyright The Asahi Linux Contributors
*/
/dts-v1/;
#include "t8103.dtsi"
#include "t8103-jxxx.dtsi"
/ {
compatible = "apple,j313", "apple,t8103", "apple,arm-platform";
model = "Apple MacBook Air (M1, 2020)";
};
&wifi0 {
brcm,board-type = "apple,shikoku";
};
/*
* Provide labels for the USB type C ports.
*/
&typec0 {
label = "USB-C Left-back";
};
&typec1 {
label = "USB-C Left-front";
};
&spi3 {
status = "okay";
hid-transport@0 {
compatible = "apple,spi-hid-transport";
reg = <0>;
spi-max-frequency = <8000000>;
/*
* cs-setup and cs-hold delays are derived from Apple's ADT
* Mac OS driver meta data secify 45 us for 'cs to clock' and
* 'clock to cs' delays.
*/
spi-cs-setup-delay-ns = <20000>;
spi-cs-hold-delay-ns = <20000>;
spi-cs-inactive-delay-ns = <250000>;
spien-gpios = <&pinctrl_ap 195 0>;
interrupts-extended = <&pinctrl_nub 13 IRQ_TYPE_LEVEL_LOW>;
};
};
/*
* Remove unused PCIe ports and disable the associated DARTs.
*/
&pcie0_dart_1 {
status = "disabled";
};
&pcie0_dart_2 {
status = "disabled";
};
/delete-node/ &port01;
/delete-node/ &port02;
&i2c3 {
clock-frequency = <50000>;
jack_codec: codec@48 {
compatible = "cirrus,cs42l83", "cirrus,cs42l42";
reg = <0x48>;
reset-gpios = <&pinctrl_nub 11 GPIO_ACTIVE_HIGH>;
interrupt-parent = <&pinctrl_ap>;
interrupts = <183 IRQ_TYPE_LEVEL_LOW>;
#sound-dai-cells = <0>;
cirrus,ts-inv = <1>;
};
};
/ {
sound {
compatible = "simple-audio-card";
simple-audio-card,name = "MacBook integrated audio";
#address-cells = <1>;
#size-cells = <0>;
simple-audio-card,dai-link@0 {
bitclock-inversion;
frame-inversion;
reg = <0>;
format = "i2s";
mclk-fs = <64>;
tdm-slot-width = <32>;
link0_cpu: cpu {
sound-dai = <&mca 2>;
bitclock-master;
frame-master;
};
link0_codec: codec {
sound-dai = <&jack_codec>;
};
};
};
};

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#include "t8103-u-boot.dtsi"

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// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Apple iMac (24-inch, 4x USB-C, M1, 2020)
*
* target-type: J456
*
* Copyright The Asahi Linux Contributors
*/
/dts-v1/;
#include "t8103.dtsi"
#include "t8103-jxxx.dtsi"
/ {
compatible = "apple,j456", "apple,t8103", "apple,arm-platform";
model = "Apple iMac (24-inch, 4x USB-C, M1, 2020)";
aliases {
ethernet0 = &ethernet0;
};
};
&wifi0 {
brcm,board-type = "apple,capri";
};
&i2c0 {
hpm2: usb-pd@3b {
compatible = "apple,cd321x";
reg = <0x3b>;
interrupt-parent = <&pinctrl_ap>;
interrupts = <106 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "irq";
};
hpm3: usb-pd@3c {
compatible = "apple,cd321x";
reg = <0x3c>;
interrupt-parent = <&pinctrl_ap>;
interrupts = <106 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "irq";
};
};
/*
* Provide labels for the USB type C ports.
*/
&typec0 {
label = "USB-C Back-right";
};
&typec1 {
label = "USB-C Back-right-middle";
};
/*
* Force the bus number assignments so that we can declare some of the
* on-board devices and properties that are populated by the bootloader
* (such as MAC addresses).
*/
&port01 {
bus-range = <2 2>;
};
&port02 {
bus-range = <3 3>;
ethernet0: ethernet@0,0 {
reg = <0x30000 0x0 0x0 0x0 0x0>;
/* To be filled by the loader */
local-mac-address = [00 10 18 00 00 00];
};
};
&i2c1 {
clock-frequency = <50000>;
jack_codec: codec@48 {
compatible = "cirrus,cs42l83", "cirrus,cs42l42";
reg = <0x48>;
reset-gpios = <&pinctrl_nub 11 GPIO_ACTIVE_HIGH>;
interrupt-parent = <&pinctrl_ap>;
interrupts = <183 IRQ_TYPE_LEVEL_LOW>;
#sound-dai-cells = <0>;
cirrus,ts-inv = <1>;
};
};
/ {
sound {
compatible = "simple-audio-card";
simple-audio-card,name = "iMac integrated audio";
#address-cells = <1>;
#size-cells = <0>;
simple-audio-card,dai-link@0 {
bitclock-inversion;
frame-inversion;
reg = <0>;
format = "i2s";
mclk-fs = <64>;
tdm-slot-width = <32>;
link0_cpu: cpu {
sound-dai = <&mca 2>;
bitclock-master;
frame-master;
};
link0_codec: codec {
sound-dai = <&jack_codec>;
};
};
};
};

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#include "t8103-u-boot.dtsi"

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// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Apple iMac (24-inch, 2x USB-C, M1, 2020)
*
* target-type: J457
*
* Copyright The Asahi Linux Contributors
*/
/dts-v1/;
#include "t8103.dtsi"
#include "t8103-jxxx.dtsi"
/ {
compatible = "apple,j457", "apple,t8103", "apple,arm-platform";
model = "Apple iMac (24-inch, 2x USB-C, M1, 2020)";
aliases {
ethernet0 = &ethernet0;
};
};
&wifi0 {
brcm,board-type = "apple,santorini";
};
/*
* Provide labels for the USB type C ports.
*/
&typec0 {
label = "USB-C Back-right";
};
&typec1 {
label = "USB-C Back-left";
};
/*
* Force the bus number assignments so that we can declare some of the
* on-board devices and properties that are populated by the bootloader
* (such as MAC addresses).
*/
&port02 {
bus-range = <3 3>;
ethernet0: ethernet@0,0 {
reg = <0x30000 0x0 0x0 0x0 0x0>;
/* To be filled by the loader */
local-mac-address = [00 10 18 00 00 00];
};
};
/*
* Remove unused PCIe port and disable the associated DART.
*/
&pcie0_dart_1 {
status = "disabled";
};
/delete-node/ &port01;
&i2c1 {
clock-frequency = <50000>;
jack_codec: codec@48 {
compatible = "cirrus,cs42l83", "cirrus,cs42l42";
reg = <0x48>;
reset-gpios = <&pinctrl_nub 11 GPIO_ACTIVE_HIGH>;
interrupt-parent = <&pinctrl_ap>;
interrupts = <183 IRQ_TYPE_LEVEL_LOW>;
#sound-dai-cells = <0>;
cirrus,ts-inv = <1>;
};
};
/ {
sound {
compatible = "simple-audio-card";
simple-audio-card,name = "iMac integrated audio";
#address-cells = <1>;
#size-cells = <0>;
simple-audio-card,dai-link@0 {
bitclock-inversion;
frame-inversion;
reg = <0>;
format = "i2s";
mclk-fs = <64>;
tdm-slot-width = <32>;
link0_cpu: cpu {
sound-dai = <&mca 2>;
bitclock-master;
frame-master;
};
link0_codec: codec {
sound-dai = <&jack_codec>;
};
};
};
};

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@@ -1,143 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Apple M1 Mac mini, MacBook Air/Pro, iMac 24" (M1, 2020/2021)
*
* This file contains parts common to all Apple M1 devices using the t8103.
*
* target-type: J274, J293, J313, J456, J457
*
* Copyright The Asahi Linux Contributors
*/
#include <dt-bindings/spmi/spmi.h>
/ {
aliases {
serial0 = &serial0;
serial2 = &serial2;
wifi0 = &wifi0;
};
chosen {
#address-cells = <2>;
#size-cells = <2>;
ranges;
stdout-path = "serial0";
framebuffer0: framebuffer@0 {
compatible = "apple,simple-framebuffer", "simple-framebuffer";
reg = <0 0 0 0>; /* To be filled by loader */
/* Format properties will be added by loader */
status = "disabled";
};
};
memory@800000000 {
device_type = "memory";
reg = <0x8 0 0x2 0>; /* To be filled by loader */
};
};
&serial0 {
status = "okay";
};
&serial2 {
status = "okay";
};
&i2c0 {
hpm0: usb-pd@38 {
compatible = "apple,cd321x";
reg = <0x38>;
interrupt-parent = <&pinctrl_ap>;
interrupts = <106 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "irq";
typec0: connector {
compatible = "usb-c-connector";
power-role = "dual";
data-role = "dual";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
typec0_con_hs: endpoint {
remote-endpoint = <&typec0_usb_hs>;
};
};
};
};
};
hpm1: usb-pd@3f {
compatible = "apple,cd321x";
reg = <0x3f>;
interrupt-parent = <&pinctrl_ap>;
interrupts = <106 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "irq";
typec1: connector {
compatible = "usb-c-connector";
power-role = "dual";
data-role = "dual";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
typec1_con_hs: endpoint {
remote-endpoint = <&typec1_usb_hs>;
};
};
};
};
};
};
/* USB controllers */
&dwc3_0 {
port {
typec0_usb_hs: endpoint {
remote-endpoint = <&typec0_con_hs>;
};
};
};
&dwc3_1 {
port {
typec1_usb_hs: endpoint {
remote-endpoint = <&typec1_con_hs>;
};
};
};
/*
* Force the bus number assignments so that we can declare some of the
* on-board devices and properties that are populated by the bootloader
* (such as MAC addresses).
*/
&port00 {
bus-range = <1 1>;
pwren-gpios = <&smc 13 0>;
wifi0: network@0,0 {
compatible = "pci14e4,4425";
reg = <0x10000 0x0 0x0 0x0 0x0>;
/* To be filled by the loader */
local-mac-address = [00 00 00 00 00 00];
apple,antenna-sku = "XX";
};
};
&spmi {
status = "okay";
pmu@f {
compatible = "apple,sera-pmu";
reg = <0xf SPMI_USID>;
};
};

File diff suppressed because it is too large Load Diff

View File

@@ -1,25 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
&serial0 {
bootph-all;
};
&pmgr {
bootph-all;
};
&ps_sio_busif {
bootph-all;
};
&ps_sio {
bootph-all;
};
&ps_uart_p {
bootph-all;
};
&ps_uart0 {
bootph-all;
};

View File

@@ -1,696 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Apple T8103 "M1" SoC
*
* Other names: H13G, "Tonga"
*
* Copyright The Asahi Linux Contributors
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/apple-aic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/apple.h>
/ {
compatible = "apple,t8103", "apple,arm-platform";
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "apple,icestorm";
device_type = "cpu";
reg = <0x0 0x0>;
enable-method = "spin-table";
cpu-release-addr = <0 0>; /* To be filled by loader */
};
cpu1: cpu@1 {
compatible = "apple,icestorm";
device_type = "cpu";
reg = <0x0 0x1>;
enable-method = "spin-table";
cpu-release-addr = <0 0>; /* To be filled by loader */
};
cpu2: cpu@2 {
compatible = "apple,icestorm";
device_type = "cpu";
reg = <0x0 0x2>;
enable-method = "spin-table";
cpu-release-addr = <0 0>; /* To be filled by loader */
};
cpu3: cpu@3 {
compatible = "apple,icestorm";
device_type = "cpu";
reg = <0x0 0x3>;
enable-method = "spin-table";
cpu-release-addr = <0 0>; /* To be filled by loader */
};
cpu4: cpu@10100 {
compatible = "apple,firestorm";
device_type = "cpu";
reg = <0x0 0x10100>;
enable-method = "spin-table";
cpu-release-addr = <0 0>; /* To be filled by loader */
};
cpu5: cpu@10101 {
compatible = "apple,firestorm";
device_type = "cpu";
reg = <0x0 0x10101>;
enable-method = "spin-table";
cpu-release-addr = <0 0>; /* To be filled by loader */
};
cpu6: cpu@10102 {
compatible = "apple,firestorm";
device_type = "cpu";
reg = <0x0 0x10102>;
enable-method = "spin-table";
cpu-release-addr = <0 0>; /* To be filled by loader */
};
cpu7: cpu@10103 {
compatible = "apple,firestorm";
device_type = "cpu";
reg = <0x0 0x10103>;
enable-method = "spin-table";
cpu-release-addr = <0 0>; /* To be filled by loader */
};
};
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&aic>;
interrupt-names = "phys", "virt", "hyp-phys", "hyp-virt";
interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>,
<AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>,
<AIC_FIQ AIC_TMR_HV_PHYS IRQ_TYPE_LEVEL_HIGH>,
<AIC_FIQ AIC_TMR_HV_VIRT IRQ_TYPE_LEVEL_HIGH>;
};
clkref: clock-ref {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
clock-output-names = "clkref";
};
clk_120m: clock-120m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <120000000>;
clock-output-names = "clk_120m";
};
soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
nonposted-mmio;
i2c0: i2c@235010000 {
compatible = "apple,t8103-i2c", "apple,i2c";
reg = <0x2 0x35010000 0x0 0x4000>;
clocks = <&clkref>;
interrupt-parent = <&aic>;
interrupts = <AIC_IRQ 627 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
#address-cells = <0x1>;
#size-cells = <0x0>;
power-domains = <&ps_i2c0>;
};
i2c1: i2c@235014000 {
compatible = "apple,t8103-i2c", "apple,i2c";
reg = <0x2 0x35014000 0x0 0x4000>;
clocks = <&clkref>;
interrupt-parent = <&aic>;
interrupts = <AIC_IRQ 628 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&i2c1_pins>;
pinctrl-names = "default";
#address-cells = <0x1>;
#size-cells = <0x0>;
power-domains = <&ps_i2c1>;
};
i2c2: i2c@235018000 {
compatible = "apple,t8103-i2c", "apple,i2c";
reg = <0x2 0x35018000 0x0 0x4000>;
clocks = <&clkref>;
interrupt-parent = <&aic>;
interrupts = <AIC_IRQ 629 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&i2c2_pins>;
pinctrl-names = "default";
#address-cells = <0x1>;
#size-cells = <0x0>;
power-domains = <&ps_i2c2>;
status = "disabled"; /* not used in all devices */
};
i2c3: i2c@23501c000 {
compatible = "apple,t8103-i2c", "apple,i2c";
reg = <0x2 0x3501c000 0x0 0x4000>;
clocks = <&clkref>;
interrupt-parent = <&aic>;
interrupts = <AIC_IRQ 630 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&i2c3_pins>;
pinctrl-names = "default";
#address-cells = <0x1>;
#size-cells = <0x0>;
power-domains = <&ps_i2c3>;
};
i2c4: i2c@235020000 {
compatible = "apple,t8103-i2c", "apple,i2c";
reg = <0x2 0x35020000 0x0 0x4000>;
clocks = <&clkref>;
interrupt-parent = <&aic>;
interrupts = <AIC_IRQ 631 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&i2c4_pins>;
pinctrl-names = "default";
#address-cells = <0x1>;
#size-cells = <0x0>;
power-domains = <&ps_i2c4>;
status = "disabled"; /* only used in J293 */
};
spi3: spi@23510c000 {
compatible = "apple,t8103-spi", "apple,spi";
reg = <0x2 0x3510c000 0x0 0x4000>;
interrupt-parent = <&aic>;
interrupts = <AIC_IRQ 617 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_120m>;
pinctrl-0 = <&spi3_pins>;
pinctrl-names = "default";
power-domains = <&ps_spi3>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled"; /* only used in J293/J313 */
};
serial0: serial@235200000 {
compatible = "apple,s5l-uart";
reg = <0x2 0x35200000 0x0 0x1000>;
reg-io-width = <4>;
interrupt-parent = <&aic>;
interrupts = <AIC_IRQ 605 IRQ_TYPE_LEVEL_HIGH>;
/*
* TODO: figure out the clocking properly, there may
* be a third selectable clock.
*/
clocks = <&clkref>, <&clkref>;
clock-names = "uart", "clk_uart_baud0";
power-domains = <&ps_uart0>;
status = "disabled";
};
serial2: serial@235208000 {
compatible = "apple,s5l-uart";
reg = <0x2 0x35208000 0x0 0x1000>;
reg-io-width = <4>;
interrupt-parent = <&aic>;
interrupts = <AIC_IRQ 607 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkref>, <&clkref>;
clock-names = "uart", "clk_uart_baud0";
power-domains = <&ps_uart2>;
status = "disabled";
};
aic: interrupt-controller@23b100000 {
compatible = "apple,t8103-aic", "apple,aic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x2 0x3b100000 0x0 0x8000>;
power-domains = <&ps_aic>;
};
pmgr: power-management@23b700000 {
compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x2 0x3b700000 0 0x14000>;
};
pinctrl_ap: pinctrl@23c100000 {
compatible = "apple,t8103-pinctrl", "apple,pinctrl";
reg = <0x2 0x3c100000 0x0 0x100000>;
power-domains = <&ps_gpio>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl_ap 0 0 212>;
apple,npins = <212>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&aic>;
interrupts = <AIC_IRQ 190 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 191 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 192 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 193 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 194 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 195 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 196 IRQ_TYPE_LEVEL_HIGH>;
i2c0_pins: i2c0-pins {
pinmux = <APPLE_PINMUX(192, 1)>,
<APPLE_PINMUX(188, 1)>;
};
i2c1_pins: i2c1-pins {
pinmux = <APPLE_PINMUX(201, 1)>,
<APPLE_PINMUX(199, 1)>;
};
i2c2_pins: i2c2-pins {
pinmux = <APPLE_PINMUX(163, 1)>,
<APPLE_PINMUX(162, 1)>;
};
i2c3_pins: i2c3-pins {
pinmux = <APPLE_PINMUX(73, 1)>,
<APPLE_PINMUX(72, 1)>;
};
i2c4_pins: i2c4-pins {
pinmux = <APPLE_PINMUX(135, 1)>,
<APPLE_PINMUX(134, 1)>;
};
spi3_pins: spi3-pins {
pinmux = <APPLE_PINMUX(46, 1)>,
<APPLE_PINMUX(47, 1)>,
<APPLE_PINMUX(48, 1)>,
<APPLE_PINMUX(49, 1)>;
};
pcie_pins: pcie-pins {
pinmux = <APPLE_PINMUX(150, 1)>,
<APPLE_PINMUX(151, 1)>,
<APPLE_PINMUX(32, 1)>;
};
};
spmi: spmi@23d0d9300 {
compatible = "apple,t8103-spmi", "apple,spmi";
reg = <0x2 0x3d0d9300 0x0 0x100>;
interrupt-parent = <&aic>;
interrupts = <AIC_IRQ 343 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <2>;
#size-cells = <0>;
status = "disabled";
};
pinctrl_nub: pinctrl@23d1f0000 {
compatible = "apple,t8103-pinctrl", "apple,pinctrl";
reg = <0x2 0x3d1f0000 0x0 0x4000>;
power-domains = <&ps_nub_gpio>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl_nub 0 0 23>;
apple,npins = <23>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&aic>;
interrupts = <AIC_IRQ 330 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 331 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 332 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 333 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 334 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 335 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 336 IRQ_TYPE_LEVEL_HIGH>;
};
pmgr_mini: power-management@23d280000 {
compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x2 0x3d280000 0 0x4000>;
};
wdt: watchdog@23d2b0000 {
compatible = "apple,t8103-wdt", "apple,wdt";
reg = <0x2 0x3d2b0000 0x0 0x4000>;
clocks = <&clkref>;
interrupt-parent = <&aic>;
interrupts = <AIC_IRQ 338 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_smc: pinctrl@23e820000 {
compatible = "apple,t8103-pinctrl", "apple,pinctrl";
reg = <0x2 0x3e820000 0x0 0x4000>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl_smc 0 0 16>;
apple,npins = <16>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&aic>;
interrupts = <AIC_IRQ 391 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 392 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 393 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 394 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 395 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 396 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 397 IRQ_TYPE_LEVEL_HIGH>;
};
smc_mbox: mbox@23e408000 {
compatible = "apple,t8103-asc-mailbox", "apple,asc-mailbox-v4";
reg = <0x2 0x3e408000 0x0 0x4000>;
interrupt-parent = <&aic>;
interrupts = <AIC_IRQ 400 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 401 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 402 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 403 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "send-empty", "send-not-empty",
"recv-empty", "recv-not-empty";
#mbox-cells = <0>;
};
smc: smc@23e050000 {
compatible = "apple,smc";
reg = <0x2 0x3e050000 0x0 0x4000>;
mboxes = <&smc_mbox>;
gpio-controller;
#gpio-cells = <2>;
gpio-13 = <0x00800000>;
};
pinctrl_aop: pinctrl@24a820000 {
compatible = "apple,t8103-pinctrl", "apple,pinctrl";
reg = <0x2 0x4a820000 0x0 0x4000>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl_aop 0 0 42>;
apple,npins = <42>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&aic>;
interrupts = <AIC_IRQ 268 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 269 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 270 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 271 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 272 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 273 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 274 IRQ_TYPE_LEVEL_HIGH>;
};
ans_mbox: mbox@277408000 {
compatible = "apple,t8103-asc-mailbox", "apple,asc-mailbox-v4";
reg = <0x2 0x77408000 0x0 0x4000>;
interrupt-parent = <&aic>;
interrupts = <AIC_IRQ 583 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 584 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 585 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 586 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "send-empty", "send-not-empty",
"recv-empty", "recv-not-empty";
#mbox-cells = <0>;
power-domains = <&ps_ans2>;
};
sart: sart@27bc50000 {
compatible = "apple,t8103-sart", "apple,sart2";
reg = <0x2 0x7bc50000 0x0 0x10000>;
power-domains = <&ps_ans2>;
};
nvme@27bcc0000 {
compatible = "apple,t8103-nvme-ans2", "apple,nvme-ans2";
reg = <0x2 0x7bcc0000 0x0 0x40000>,
<0x2 0x77400000 0x0 0x4000>;
reg-names = "nvme", "ans";
interrupt-parent = <&aic>;
interrupts = <AIC_IRQ 590 IRQ_TYPE_LEVEL_HIGH>;
mboxes = <&ans_mbox>;
apple,sart = <&sart>;
power-domains = <&ps_ans2>;
resets = <&ps_ans2>;
};
dwc3_0: usb@382280000 {
compatible = "apple,t8103-dwc3", "apple,dwc3", "snps,dwc3";
reg = <0x3 0x82280000 0x0 0x100000>;
interrupt-parent = <&aic>;
interrupts = <AIC_IRQ 777 IRQ_TYPE_LEVEL_HIGH>;
usb-role-switch;
role-switch-default-mode = "host";
iommus = <&dwc3_0_dart_0 0>, <&dwc3_0_dart_1 1>;
power-domains = <&ps_atc0_usb>;
};
dwc3_0_dart_0: iommu@382f00000 {
compatible = "apple,t8103-dart";
reg = <0x3 0x82f00000 0x0 0x4000>;
interrupt-parent = <&aic>;
interrupts = <AIC_IRQ 781 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <1>;
power-domains = <&ps_atc0_usb>;
};
dwc3_0_dart_1: iommu@382f80000 {
compatible = "apple,t8103-dart";
reg = <0x3 0x82f80000 0x0 0x4000>;
interrupt-parent = <&aic>;
interrupts = <AIC_IRQ 781 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <1>;
power-domains = <&ps_atc0_usb>;
};
dwc3_1: usb@502280000 {
compatible = "apple,t8103-dwc3", "apple,dwc3", "snps,dwc3";
reg = <0x5 0x02280000 0x0 0x100000>;
interrupt-parent = <&aic>;
interrupts = <AIC_IRQ 857 IRQ_TYPE_LEVEL_HIGH>;
usb-role-switch;
role-switch-default-mode = "host";
iommus = <&dwc3_1_dart_0 0>, <&dwc3_1_dart_1 1>;
power-domains = <&ps_atc1_usb>;
};
dwc3_1_dart_0: iommu@502f00000 {
compatible = "apple,t8103-dart";
reg = <0x5 0x02f00000 0x0 0x4000>;
interrupt-parent = <&aic>;
interrupts = <AIC_IRQ 861 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <1>;
power-domains = <&ps_atc1_usb>;
};
dwc3_1_dart_1: iommu@502f80000 {
compatible = "apple,t8103-dart";
reg = <0x5 0x02f80000 0x0 0x4000>;
interrupt-parent = <&aic>;
interrupts = <AIC_IRQ 861 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <1>;
power-domains = <&ps_atc1_usb>;
};
pcie0_dart_0: dart@681008000 {
compatible = "apple,t8103-dart";
reg = <0x6 0x81008000 0x0 0x4000>;
#iommu-cells = <1>;
interrupt-parent = <&aic>;
interrupts = <AIC_IRQ 696 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&ps_apcie_gp>;
};
pcie0_dart_1: dart@682008000 {
compatible = "apple,t8103-dart";
reg = <0x6 0x82008000 0x0 0x4000>;
#iommu-cells = <1>;
interrupt-parent = <&aic>;
interrupts = <AIC_IRQ 699 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&ps_apcie_gp>;
};
pcie0_dart_2: dart@683008000 {
compatible = "apple,t8103-dart";
reg = <0x6 0x83008000 0x0 0x4000>;
#iommu-cells = <1>;
interrupt-parent = <&aic>;
interrupts = <AIC_IRQ 702 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&ps_apcie_gp>;
};
pcie0: pcie@690000000 {
compatible = "apple,t8103-pcie", "apple,pcie";
device_type = "pci";
reg = <0x6 0x90000000 0x0 0x1000000>,
<0x6 0x80000000 0x0 0x100000>,
<0x6 0x81000000 0x0 0x4000>,
<0x6 0x82000000 0x0 0x4000>,
<0x6 0x83000000 0x0 0x4000>;
reg-names = "config", "rc", "port0", "port1", "port2";
interrupt-parent = <&aic>;
interrupts = <AIC_IRQ 695 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 698 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 701 IRQ_TYPE_LEVEL_HIGH>;
msi-controller;
msi-parent = <&pcie0>;
msi-ranges = <&aic AIC_IRQ 704 IRQ_TYPE_EDGE_RISING 32>;
iommu-map = <0x100 &pcie0_dart_0 1 1>,
<0x200 &pcie0_dart_1 1 1>,
<0x300 &pcie0_dart_2 1 1>;
iommu-map-mask = <0xff00>;
bus-range = <0 3>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x43000000 0x6 0xa0000000 0x6 0xa0000000 0x0 0x20000000>,
<0x02000000 0x0 0xc0000000 0x6 0xc0000000 0x0 0x40000000>;
power-domains = <&ps_apcie_gp>;
pinctrl-0 = <&pcie_pins>;
pinctrl-names = "default";
port00: pci@0,0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
reset-gpios = <&pinctrl_ap 152 GPIO_ACTIVE_LOW>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &port00 0 0 0 0>,
<0 0 0 2 &port00 0 0 0 1>,
<0 0 0 3 &port00 0 0 0 2>,
<0 0 0 4 &port00 0 0 0 3>;
};
port01: pci@1,0 {
device_type = "pci";
reg = <0x800 0x0 0x0 0x0 0x0>;
reset-gpios = <&pinctrl_ap 153 GPIO_ACTIVE_LOW>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &port01 0 0 0 0>,
<0 0 0 2 &port01 0 0 0 1>,
<0 0 0 3 &port01 0 0 0 2>,
<0 0 0 4 &port01 0 0 0 3>;
};
port02: pci@2,0 {
device_type = "pci";
reg = <0x1000 0x0 0x0 0x0 0x0>;
reset-gpios = <&pinctrl_ap 33 GPIO_ACTIVE_LOW>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &port02 0 0 0 0>,
<0 0 0 2 &port02 0 0 0 1>,
<0 0 0 3 &port02 0 0 0 2>,
<0 0 0 4 &port02 0 0 0 3>;
};
};
dart_sio: iommu@235004000 {
compatible = "apple,t8103-dart", "apple,dart";
reg = <0x2 0x35004000 0x0 0x4000>;
interrupt-parent = <&aic>;
interrupts = <AIC_IRQ 635 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <1>;
power-domains = <&ps_sio_cpu>;
};
nco_inp: clock-ref {
compatible = "fixed-factor-clock";
clocks = <&clkref>;
#clock-cells = <0>;
clock-mult = <75>;
clock-div = <2>; // 24 MHz * (75/2) = 900 MHz
clock-output-names = "nco_inp";
};
nco: nco@23b044000 {
compatible = "apple,t8103-nco", "apple,nco";
reg = <0x2 0x3b044000 0x0 0x14000>;
clocks = <&nco_inp>;
#clock-cells = <1>;
apple,nchannels = <5>;
};
admac: dma-controller@238200000 {
compatible = "apple,t8103-admac", "apple,admac";
reg = <0x2 0x38200000 0x0 0x34000>;
dma-channels = <12>;
interrupt-parent = <&aic>;
interrupts = <AIC_IRQ 626 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
iommus = <&dart_sio 2>;
power-domains = <&ps_sio_adma>;
};
mca: mca {
compatible = "apple,t8103-mca", "apple,mca";
reg = <0x2 0x38400000 0x0 0x18000>,
<0x2 0x38300000 0x0 0x30000>;
reg-names = "clusters", "switch";
clocks = <&nco 0>, <&nco 1>, <&nco 2>, <&nco 3>;
power-domains = <&ps_mca0>; //, <&ps_mca1>, <&ps_mca2>, <&ps_mca3>, <&ps_mca4>, <&ps_mca5>;
resets = <&ps_mca0>, <&ps_mca1>, <&ps_mca2>, <&ps_mca3>, <&ps_mca4>, <&ps_mca5>;
#sound-dai-cells = <1>;
apple,nclusters = <6>;
apple,mclk-range = <2600000 25000000>;
route {
dmas = <&admac 2>;
dma-names = "tx";
apple,serdes = <1>;
sound-dai = <&mca 0>;
};
route2 {
dmas = <&admac 6>;
dma-names = "tx";
apple,serdes = <3>;
sound-dai = <&mca 2>;
};
};
};
};
#include "t8103-pmgr.dtsi"

View File

@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2022 NXP
* Copyright 2022-2026 NXP
*/
#ifndef __ASM_ARCH_IMX8M_DDR_H
@@ -100,6 +100,52 @@ struct dram_timing_info {
extern struct dram_timing_info dram_timing;
/* Quick Boot related */
#define DDRPHY_QB_CSR_SIZE 5168
#define DDRPHY_QB_ACSM_SIZE (4 * 1024)
#define DDRPHY_QB_MSB_SIZE 0x200
#define DDRPHY_QB_PSTATES 0
#define DDRPHY_QB_PST_SIZE (DDRPHY_QB_PSTATES * 4 * 1024)
/**
* This structure needs to be aligned with the one in OEI.
*/
struct ddrphy_qb_state {
u32 crc; /* Used for ensuring integrity in DRAM */
#define MAC_LENGTH 8 /* 256 bits, 32-bit aligned */
u32 mac[MAC_LENGTH]; /* For 95A0/1 use mac[0] to keep CRC32 value */
u8 trained_vrefca_a0;
u8 trained_vrefca_a1;
u8 trained_vrefca_b0;
u8 trained_vrefca_b1;
u8 trained_vrefdq_a0;
u8 trained_vrefdq_a1;
u8 trained_vrefdq_b0;
u8 trained_vrefdq_b1;
u8 trained_vrefdqu_a0;
u8 trained_vrefdqu_a1;
u8 trained_vrefdqu_b0;
u8 trained_vrefdqu_b1;
u8 trained_dramdfe_a0;
u8 trained_dramdfe_a1;
u8 trained_dramdfe_b0;
u8 trained_dramdfe_b1;
u8 trained_dramdca_a0;
u8 trained_dramdca_a1;
u8 trained_dramdca_b0;
u8 trained_dramdca_b1;
u16 qb_pll_upll_prog0;
u16 qb_pll_upll_prog1;
u16 qb_pll_upll_prog2;
u16 qb_pll_upll_prog3;
u16 qb_pll_ctrl1;
u16 qb_pll_ctrl4;
u16 qb_pll_ctrl5;
u16 csr[DDRPHY_QB_CSR_SIZE];
u16 acsm[DDRPHY_QB_ACSM_SIZE];
u16 pst[DDRPHY_QB_PST_SIZE];
};
void ddr_load_train_firmware(enum fw_type type);
int ddr_init(struct dram_timing_info *timing_info);
int ddr_cfg_phy(struct dram_timing_info *timing_info);

View File

@@ -23,6 +23,10 @@ int low_drive_freq_update(void *blob);
enum imx9_soc_voltage_mode soc_target_voltage_mode(void);
int get_reset_reason(bool sys, bool lm);
int scmi_get_boot_device_offset(unsigned long *img_off);
int scmi_get_boot_stage(u8 *stage);
u8 scmi_get_imgset_sel(void);
#define is_voltage_mode(mode) (soc_target_voltage_mode() == (mode))
#endif

View File

@@ -222,6 +222,11 @@ u64 get_tcr(u64 *pips, u64 *pva_bits);
* mmu_setup() - Sets up the mmu page tables as per mem_map
*/
void mmu_setup(void);
/**
* mmu_enable() - Enable the MMU by setting 'M' bit in SCTLR register
*/
void mmu_enable(void);
#endif
#endif /* _ASM_ARMV8_MMU_H_ */

View File

@@ -8,7 +8,7 @@
#include <imx_container.h>
int ahab_auth_cntr_hdr(struct container_hdr *container, u16 length);
void *ahab_auth_cntr_hdr(struct container_hdr *container, u16 length);
int ahab_auth_release(void);
int ahab_verify_cntr_image(struct boot_img_t *img, int image_index);

View File

@@ -0,0 +1,15 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2026 NXP
*/
#ifndef __IMX_QB_H__
#define __IMX_QB_H__
#include <stdbool.h>
bool imx_qb_check(void);
int imx_qb(const char *ifname, const char *dev, bool save);
void spl_imx_qb_save(void);
#endif

View File

@@ -3,12 +3,22 @@ if ARCH_APPLE
config TEXT_BASE
default 0x00000000
config SYS_CONFIG_NAME
default "apple"
config SYS_SOC
default "apple"
config SYS_VENDOR
default "apple"
config SYS_BOARD
string "Board name"
default "mac"
help
This option contains information about board name.
Based on this option board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD> will
be used.
Apple silicon based devices are expected to use the generic board name
"mac".
config SYS_MALLOC_LEN
default 0x4000000

View File

@@ -673,6 +673,83 @@ static struct mm_region t6022_mem_map[] = {
}
};
/* Apple M3 */
static struct mm_region t8122_mem_map[] = {
{
/* I/O */
.virt = 0x200000000,
.phys = 0x200000000,
.size = 4UL * SZ_1G,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* NVMe */
.virt = 0x300000000,
.phys = 0x300000000,
.size = SZ_1G,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* PCIE */
.virt = 0x580000000,
.phys = 0x580000000,
.size = SZ_512M,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* PCIE */
.virt = 0x5a0000000,
.phys = 0x5a0000000,
.size = SZ_512M,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
PTE_BLOCK_INNER_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* PCIE */
.virt = 0x5c0000000,
.phys = 0x5c0000000,
.size = SZ_1G,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
PTE_BLOCK_INNER_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* I/O ATC0 */
.virt = 0x700000000,
.phys = 0x700000000,
.size = SZ_1G,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* I/O ATC1 */
.virt = 0xb00000000,
.phys = 0xb00000000,
.size = SZ_1G,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* RAM */
.virt = 0x10000000000,
.phys = 0x10000000000,
.size = 8UL * SZ_1G,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
/* Framebuffer */
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
PTE_BLOCK_INNER_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* List terminator */
0,
}
};
struct mm_region *mem_map;
int board_init(void)
@@ -720,6 +797,8 @@ void build_mem_map(void)
mem_map = t6020_mem_map;
else if (of_machine_is_compatible("apple,t6022"))
mem_map = t6022_mem_map;
else if (of_machine_is_compatible("apple,t8122"))
mem_map = t8122_mem_map;
else
panic("Unsupported SoC\n");

View File

@@ -11,6 +11,7 @@
#include <asm/io.h>
#include <asm/arch/rtkit.h>
#include <linux/iopoll.h>
#include <linux/sizes.h>
/* ASC registers */
#define REG_CPU_CTRL 0x0044

View File

@@ -71,10 +71,38 @@ config CSF_SIZE
Define the maximum size for Command Sequence File (CSF) binary
this information is used to define the image boot data.
config IMX_QB
bool "Support Quickboot flow for Synopsis DDR PHY on iMX platforms"
default y
depends on IMX94 || IMX95 || IMX952
help
Enable the logic for saving DDR training data from volatile
memory to non-volatile storage. OEI uses the saved data to
run Quickboot flow and skip re-training the DDR PHY.
config SPL_IMX_QB
bool "Run qb save during SPL"
depends on SPL && IMX_QB
help
Automatically save DDR training data (Quickboot data)
to current boot device when needed (when OEI runs Training
flow and saves qb data to volatile memory).
config CMD_IMX_QB
bool "Support the 'qb' command"
default y
depends on IMX_QB
help
Enable qb command to write/erase DDR quick boot training
data to/from a chosen boot device. Using 'qb save/erase'
without arguments implies using the current boot device's
first bootable partition (e.g. boot0 for eMMC). For use in
uuu scripts, the boot device must be specified explicitly.
config CMD_BMODE
bool "Support the 'bmode' command"
default y
depends on ARCH_IMX8M || ARCH_MX7 || ARCH_MX6 || ARCH_MX5
depends on IMX95 || ARCH_IMX8M || ARCH_MX7 || ARCH_MX6 || ARCH_MX5
help
This enables the 'bmode' (bootmode) command for forcing
a boot from specific media.

View File

@@ -80,6 +80,7 @@ endif
ifneq ($(CONFIG_XPL_BUILD),y)
obj-$(CONFIG_CMD_BMODE) += cmd_bmode.o
obj-$(CONFIG_CMD_HDMIDETECT) += cmd_hdmidet.o
obj-$(CONFIG_CMD_IMX_QB) += cmd_qb.o
obj-$(CONFIG_CMD_DEKBLOB) += cmd_dek.o
obj-$(CONFIG_CMD_NANDBCB) += cmd_nandbcb.o
endif

102
arch/arm/mach-imx/cmd_qb.c Normal file
View File

@@ -0,0 +1,102 @@
// SPDX-License-Identifier: GPL-2.0+
/**
* Copyright 2024-2026 NXP
*/
#include <command.h>
#include <spl.h>
#include <stdlib.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/sys_proto.h>
#include <asm/mach-imx/qb.h>
static void parse_qb_args(int argc, char * const argv[],
const char **ifname, const char **dev)
{
/* qb save/erase -> use boot device */
if (argc < 2) {
*ifname = "auto";
return;
}
*ifname = argv[1];
if (argc == 3)
*dev = argv[2];
}
static int do_qb(struct cmd_tbl *cmdtp, int flag, int argc,
char * const argv[], bool save)
{
const char *ifname, *dev;
parse_qb_args(argc, argv, &ifname, &dev);
if (imx_qb(ifname, dev, save))
return CMD_RET_FAILURE;
return CMD_RET_SUCCESS;
}
static int do_qb_check(struct cmd_tbl *cmdtp, int flag,
int argc, char * const argv[])
{
return imx_qb_check() ? CMD_RET_SUCCESS : CMD_RET_FAILURE;
}
static int do_qb_save(struct cmd_tbl *cmdtp, int flag,
int argc, char * const argv[])
{
return do_qb(cmdtp, flag, argc, argv, true);
}
static int do_qb_erase(struct cmd_tbl *cmdtp, int flag,
int argc, char * const argv[])
{
return do_qb(cmdtp, flag, argc, argv, false);
}
static struct cmd_tbl cmd_qb[] = {
U_BOOT_CMD_MKENT(check, 1, 1, do_qb_check, "", ""),
U_BOOT_CMD_MKENT(save, 3, 1, do_qb_save, "", ""),
U_BOOT_CMD_MKENT(erase, 3, 1, do_qb_erase, "", ""),
};
static int do_qbops(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
struct cmd_tbl *cp;
cp = find_cmd_tbl(argv[1], cmd_qb, ARRAY_SIZE(cmd_qb));
/* Drop the qb command */
argc--;
argv++;
if (!cp) {
printf("qb: %s: command not found\n", argv[0] ? argv[0] : " ");
return CMD_RET_USAGE;
}
if (argc > cp->maxargs) {
printf("qb %s: too many arguments: %d > %d\n", cp->name,
argc - 1, cp->maxargs - 1);
return CMD_RET_USAGE;
}
if (flag == CMD_FLAG_REPEAT && !cmd_is_repeatable(cp)) {
printf("qb %s: repeat flag set but command is not repeatable\n",
cp->name);
return CMD_RET_SUCCESS;
}
return cp->cmd(cmdtp, flag, argc, argv);
}
U_BOOT_CMD(
qb, 4, 1, do_qbops,
"DDR Quick Boot sub system",
"check - check if quick boot data is stored in mem by training flow\n"
"qb save [interface] [dev] - save quick boot data in NVM => trigger quick boot flow\n"
"qb erase [interface] [dev] - erase quick boot data from NVM => trigger training flow\n"
);

View File

@@ -255,7 +255,7 @@ static void display_ahab_auth_ind(u32 event)
printf("%s\n", ele_ind_str[get_idx(ele_ind, resp_ind, ARRAY_SIZE(ele_ind))]);
}
int ahab_auth_cntr_hdr(struct container_hdr *container, u16 length)
void *ahab_auth_cntr_hdr(struct container_hdr *container, u16 length)
{
int err;
u32 resp;
@@ -271,9 +271,10 @@ int ahab_auth_cntr_hdr(struct container_hdr *container, u16 length)
printf("Authenticate container hdr failed, return %d, resp 0x%x\n",
err, resp);
display_ahab_auth_ind(resp);
return NULL;
}
return err;
return (void *)IMG_CONTAINER_BASE; /* Return authenticated container header */
}
int ahab_auth_release(void)
@@ -327,7 +328,6 @@ int authenticate_os_container(ulong addr)
{
struct container_hdr *phdr;
int i, ret = 0;
int err;
u16 length;
struct boot_img_t *img;
unsigned long s, e;
@@ -357,8 +357,8 @@ int authenticate_os_container(ulong addr)
debug("container length %u\n", length);
err = ahab_auth_cntr_hdr(phdr, length);
if (err) {
phdr = ahab_auth_cntr_hdr(phdr, length);
if (!phdr) {
ret = -EIO;
goto exit;
}
@@ -367,7 +367,7 @@ int authenticate_os_container(ulong addr)
/* Copy images to dest address */
for (i = 0; i < phdr->num_images; i++) {
img = (struct boot_img_t *)(addr +
img = (struct boot_img_t *)((ulong)phdr +
sizeof(struct container_hdr) +
i * sizeof(struct boot_img_t));

View File

@@ -240,6 +240,14 @@ static unsigned long get_boot_device_offset(void *dev, int dev_type)
return offset;
}
#if IS_ENABLED(CONFIG_ARCH_IMX9) && IS_ENABLED(CONFIG_SCMI_FIRMWARE)
int ret;
ret = scmi_get_boot_device_offset(&offset);
if (!ret)
return offset;
/* fall back to boot from primary set if get rom passover failed */
#endif
sec_boot = check_secondary_cnt_set(&sec_set_off);
if (sec_boot)
printf("Secondary set selected\n");
@@ -366,10 +374,17 @@ int spl_mmc_emmc_boot_partition(struct mmc *mmc)
part = EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config);
if (part == EMMC_BOOT_PART_BOOT1 || part == EMMC_BOOT_PART_BOOT2) {
unsigned long sec_set_off = 0;
bool sec_boot = false;
#if IS_ENABLED(CONFIG_ARCH_IMX9) && IS_ENABLED(CONFIG_SCMI_FIRMWARE)
u8 stage;
int ret;
ret = scmi_get_boot_stage(&stage);
if (!ret)
sec_boot = (stage == 0x9);
#else
unsigned long sec_set_off = 0;
sec_boot = check_secondary_cnt_set(&sec_set_off);
#endif
if (sec_boot)
part = (part == EMMC_BOOT_PART_BOOT1) ? EMMC_HWPART_BOOT2 : EMMC_HWPART_BOOT1;
} else if (part == EMMC_BOOT_PART_USER) {

View File

@@ -28,7 +28,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define AHAB_HASH_TYPE_MASK 0x00000700
#define AHAB_HASH_TYPE_SHA256 0
int ahab_auth_cntr_hdr(struct container_hdr *container, u16 length)
void *ahab_auth_cntr_hdr(struct container_hdr *container, u16 length)
{
int err;
@@ -37,10 +37,12 @@ int ahab_auth_cntr_hdr(struct container_hdr *container, u16 length)
err = sc_seco_authenticate(-1, SC_SECO_AUTH_CONTAINER,
SECO_LOCAL_SEC_SEC_SECURE_RAM_BASE);
if (err)
if (err) {
printf("Authenticate container hdr failed, return %d\n", err);
return NULL;
}
return err;
return (void *)SEC_SECURE_RAM_BASE; /* Return authenticated container header */
}
int ahab_auth_release(void)
@@ -126,7 +128,7 @@ int authenticate_os_container(ulong addr)
{
struct container_hdr *phdr;
int i, ret = 0;
int err;
__maybe_unused int err;
u16 length;
struct boot_img_t *img;
unsigned long s, e;
@@ -159,15 +161,15 @@ int authenticate_os_container(ulong addr)
debug("container length %u\n", length);
err = ahab_auth_cntr_hdr(phdr, length);
if (err) {
phdr = ahab_auth_cntr_hdr(phdr, length);
if (!phdr) {
ret = -EIO;
goto exit;
}
/* Copy images to dest address */
for (i = 0; i < phdr->num_images; i++) {
img = (struct boot_img_t *)(addr +
img = (struct boot_img_t *)((ulong)phdr +
sizeof(struct container_hdr) +
i * sizeof(struct boot_img_t));

View File

@@ -79,11 +79,13 @@ config TARGET_IMX8MQ_PHANBELL
bool "imx8mq_phanbell"
select IMX8MQ
select IMX8M_LPDDR4
imply OF_UPSTREAM
config TARGET_IMX8MQ_REFORM2
bool "imx8mq_reform2"
select IMX8MQ
select IMX8M_LPDDR4
imply OF_UPSTREAM
config TARGET_IMX8MM_DATA_MODUL_EDM_SBC
bool "Data Modul eDM SBC i.MX8M Mini"
@@ -308,6 +310,7 @@ config TARGET_PICO_IMX8MQ
bool "Support Technexion Pico iMX8MQ"
select IMX8MQ
select IMX8M_LPDDR4
imply OF_UPSTREAM
config TARGET_IMX8MN_VAR_SOM
bool "Variscite imx8mn_var_som"
@@ -324,6 +327,7 @@ config TARGET_KONTRON_PITX_IMX8M
bool "Support Kontron pITX-imx8m"
select IMX8MQ
select IMX8M_LPDDR4
imply OF_UPSTREAM
config TARGET_TORADEX_SMARC_IMX8MP
bool "Support Toradex SMARC iMX8M Plus module"
@@ -426,6 +430,7 @@ config TARGET_LIBREM5
select IMX8MQ
select SUPPORT_SPL
select IMX8M_LPDDR4
imply OF_UPSTREAM
endchoice

View File

@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright 2022 NXP
# Copyright 2022,2026 NXP
obj-y += lowlevel_init.o
@@ -12,4 +12,6 @@ endif
ifneq ($(CONFIG_SPL_BUILD),y)
obj-y += imx_bootaux.o
endif
endif
obj-$(CONFIG_$(PHASE_)IMX_QB) += qb.o

View File

@@ -478,6 +478,7 @@ u32 get_clk_src_rate(enum ccm_clk_src source)
switch (source) {
case ARM_PLL_CLK:
ctrl = readl(&ana_regs->arm_pll.ctrl.reg);
break;
case AUDIO_PLL_CLK:
ctrl = readl(&ana_regs->audio_pll.ctrl.reg);
break;

403
arch/arm/mach-imx/imx9/qb.c Normal file
View File

@@ -0,0 +1,403 @@
// SPDX-License-Identifier: GPL-2.0+
/**
* Copyright 2024-2026 NXP
*/
#include <dm/device-internal.h>
#include <dm/uclass.h>
#include <errno.h>
#include <imx_container.h>
#include <linux/bitfield.h>
#include <mmc.h>
#include <spi_flash.h>
#include <spl.h>
#include <stdlib.h>
#include <u-boot/crc.h>
#include <asm/arch/ddr.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/sys_proto.h>
#define QB_STATE_LOAD_SIZE SZ_64K
#define BLK_DEV 0
#define SPI_DEV 1
#define IMG_FLAGS_IMG_TYPE_MASK 0xF
#define IMG_FLAGS_IMG_TYPE(x) FIELD_GET(IMG_FLAGS_IMG_TYPE_MASK, (x))
#define IMG_TYPE_DDR_TDATA_DUMMY 0xD /* dummy DDR training data image */
static const struct {
const char *ifname;
const char *dev;
} imx_boot_devs[] = {
[BOOT_DEVICE_MMC1] = { "mmc", "0" },
[BOOT_DEVICE_MMC2] = { "mmc", "1" },
[BOOT_DEVICE_SPI] = { "spi", "" },
};
static int imx_qb_get_board_boot_device(void)
{
switch (get_boot_device()) {
case SD1_BOOT:
case MMC1_BOOT:
return BOOT_DEVICE_MMC1;
case SD2_BOOT:
case MMC2_BOOT:
return BOOT_DEVICE_MMC2;
case USB_BOOT:
return BOOT_DEVICE_BOARD;
case QSPI_BOOT:
return BOOT_DEVICE_SPI;
default:
return BOOT_DEVICE_NONE;
}
}
static int imx_qb_get_boot_dev_str(const char **ifname, const char **dev)
{
int boot_dev;
if (IS_ENABLED(CONFIG_XPL_BUILD))
boot_dev = spl_boot_device();
else
boot_dev = imx_qb_get_board_boot_device();
if (boot_dev == BOOT_DEVICE_NONE || boot_dev == BOOT_DEVICE_BOARD)
return -EINVAL;
*ifname = imx_boot_devs[boot_dev].ifname;
*dev = imx_boot_devs[boot_dev].dev;
return 0;
}
bool imx_qb_check(void)
{
struct ddrphy_qb_state *qb_state;
u32 size, crc;
/**
* Ensure CRC is not empty, the reason is that
* the data is invalidated after first save run
* or after it is overwritten.
*/
qb_state = (struct ddrphy_qb_state *)CONFIG_QB_SAVED_STATE_BASE;
size = sizeof(struct ddrphy_qb_state) - sizeof(qb_state->crc);
crc = crc32(0, (u8 *)qb_state->mac, size);
if (!qb_state->crc || crc != qb_state->crc)
return false;
return true;
}
static int imx_qb_get_blk_boot_part(const char * const ifname,
const char * const dev,
struct blk_desc **bdesc)
{
struct udevice *udev;
struct disk_partition info;
struct mmc *mmc;
int part;
int ret;
if (!IS_ENABLED(CONFIG_XPL_BUILD))
return blk_get_device_part_str(ifname, dev, bdesc, &info, 1);
/**
* SPL does not have access to part_get_info,
* so get the partition manually. Currently only
* supporting MMC devices.
*/
ret = blk_get_device_by_str(ifname, dev, bdesc);
if (ret < 0)
return -ENODEV;
if ((*bdesc)->uclass_id != UCLASS_MMC)
return -EOPNOTSUPP;
udev = dev_get_parent((*bdesc)->bdev);
mmc = mmc_get_mmc_dev(udev);
if (IS_SD(mmc) || mmc->part_config == MMCPART_NOAVAILABLE)
return 0;
part = EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config);
if (part == EMMC_BOOT_PART_BOOT1 || part == EMMC_BOOT_PART_BOOT2)
return part;
return 0;
}
static ulong imx_qb_get_boot_device_offset(void *dev, int dev_type)
{
struct blk_desc *bdesc;
switch (dev_type) {
case BLK_DEV:
bdesc = dev;
/* eMMC boot partition */
if (bdesc->hwpart)
return CONTAINER_HDR_EMMC_OFFSET;
return CONTAINER_HDR_MMCSD_OFFSET;
case SPI_DEV:
return CONTAINER_HDR_QSPI_OFFSET;
default:
return -EOPNOTSUPP;
}
}
static int imx_qb_parse_container(void *addr, u64 *qb_data_off)
{
struct container_hdr *phdr;
struct boot_img_t *img_entry;
u32 img_type, img_end;
int i;
phdr = addr;
if (phdr->tag != 0x87 || (phdr->version != 0x0 && phdr->version != 0x2))
return -EINVAL;
img_entry = addr + sizeof(struct container_hdr);
for (i = 0; i < phdr->num_images; i++) {
img_type = IMG_FLAGS_IMG_TYPE(img_entry->hab_flags);
if (img_type == IMG_TYPE_DDR_TDATA_DUMMY && img_entry->size == 0) {
/* Image entry pointing to DDR Training Data */
*qb_data_off = img_entry->offset;
return 0;
}
img_end = img_entry->offset + img_entry->size;
if (i + 1 < phdr->num_images) {
img_entry++;
if (img_end + QB_STATE_LOAD_SIZE == img_entry->offset) {
/* hole detected */
*qb_data_off = img_end;
return 0;
}
}
}
return -EINVAL;
}
static int imx_qb_get_dev_qbdata_offset(void *dev, int dev_type, ulong offset,
u64 *qbdata_offset)
{
struct blk_desc *bdesc;
u8 *buf;
ulong count;
int ret;
buf = malloc(CONTAINER_HDR_ALIGNMENT);
if (!buf)
return -ENOMEM;
switch (dev_type) {
case BLK_DEV:
bdesc = dev;
count = blk_dread(bdesc,
offset / bdesc->blksz,
CONTAINER_HDR_ALIGNMENT / bdesc->blksz,
buf);
if (count == 0) {
printf("Read container image from MMC/SD failed\n");
ret = -EIO;
goto imx_qb_get_dev_qbdata_offset_exit;
}
break;
case SPI_DEV:
if (!CONFIG_IS_ENABLED(SPI)) {
ret = -EOPNOTSUPP;
goto imx_qb_get_dev_qbdata_offset_exit;
}
ret = spi_flash_read_dm(dev, offset,
CONTAINER_HDR_ALIGNMENT, buf);
if (ret) {
printf("Read container header from SPI failed\n");
ret = -EIO;
goto imx_qb_get_dev_qbdata_offset_exit;
}
break;
default:
printf("Support for device %d not enabled\n", dev_type);
ret = -EOPNOTSUPP;
goto imx_qb_get_dev_qbdata_offset_exit;
}
ret = imx_qb_parse_container(buf, qbdata_offset);
imx_qb_get_dev_qbdata_offset_exit:
free(buf);
return ret;
}
static int imx_qb_get_qbdata_offset(void *dev, int dev_type,
u64 *qbdata_offset)
{
u64 cont_offset;
int ret, i;
cont_offset = imx_qb_get_boot_device_offset(dev, dev_type);
for (i = 0; i < 3; i++) {
ret = imx_qb_get_dev_qbdata_offset(dev, dev_type, cont_offset,
qbdata_offset);
if (ret == 0) {
(*qbdata_offset) += cont_offset;
break;
}
cont_offset += CONTAINER_HDR_ALIGNMENT;
}
return ret;
}
static int imx_qb_blk(const char * const ifname,
const char * const dev, bool save)
{
struct blk_desc *bdesc;
u64 offset;
u64 load_size;
int part, orig_part;
int ret;
part = imx_qb_get_blk_boot_part(ifname, dev, &bdesc);
if (part < 0) {
printf("Failed to find %s %s\n", ifname, dev);
return -ENODEV;
}
orig_part = bdesc->hwpart;
ret = blk_dselect_hwpart(bdesc, part);
if (ret && ret != -EMEDIUMTYPE) {
printf("Failed to select hwpart, ret %d\n", ret);
return ret;
}
ret = imx_qb_get_qbdata_offset(bdesc, BLK_DEV, &offset);
if (ret) {
printf("get_qbdata_offset failed, ret = %d\n", ret);
return ret;
}
offset /= bdesc->blksz;
load_size = QB_STATE_LOAD_SIZE / bdesc->blksz;
if (save) {
/* QB data is stored in DDR -> can use it as buf */
ret = blk_dwrite(bdesc, offset, load_size,
(const void *)CONFIG_QB_SAVED_STATE_BASE);
} else {
/* erase */
ret = blk_derase(bdesc, offset, load_size);
}
if (!ret) {
printf("Failed to write to block device\n");
return -EIO;
}
/* Return to original partition */
ret = blk_dselect_hwpart(bdesc, orig_part);
if (ret && ret != -EMEDIUMTYPE) {
printf("Failed to select hwpart, ret %d\n", ret);
return ret;
}
return 0;
}
static int imx_qb_spi(bool save)
{
struct udevice *flash;
u64 offset;
int ret;
if (!CONFIG_IS_ENABLED(SPI)) {
printf("SPI not enabled\n");
return -EOPNOTSUPP;
}
ret = uclass_first_device_err(UCLASS_SPI_FLASH, &flash);
if (ret) {
printf("SPI flash not found.\n");
return -ENODEV;
}
ret = imx_qb_get_qbdata_offset(flash, SPI_DEV, &offset);
if (ret) {
printf("get_qbdata_offset failed, ret = %d\n", ret);
return ret;
}
ret = spi_flash_erase_dm(flash, offset, QB_STATE_LOAD_SIZE);
if (ret)
return ret;
if (!save)
return 0;
/* QB data is stored in DDR -> can use it as buf */
ret = spi_flash_write_dm(flash, offset,
QB_STATE_LOAD_SIZE,
(const void *)CONFIG_QB_SAVED_STATE_BASE);
return ret;
}
int imx_qb(const char *ifname, const char *dev, bool save)
{
int ret;
ret = 0;
/* Try to use boot device */
if (!strcmp(ifname, "auto"))
ret = imx_qb_get_boot_dev_str(&ifname, &dev);
if (ret)
return ret;
if (save && !imx_qb_check())
return -EINVAL;
if (!strcmp(ifname, "spi"))
ret = imx_qb_spi(save);
else
ret = imx_qb_blk(ifname, dev, save);
if (ret)
return ret;
if (!save)
return 0;
/**
* invalidate qb_state mem so that at next boot
* the check function will fail and save won't happen
*/
memset((void *)CONFIG_QB_SAVED_STATE_BASE, 0,
sizeof(struct ddrphy_qb_state));
return 0;
}
void spl_imx_qb_save(void)
{
/* Save QB data on current boot device */
if (imx_qb("auto", "", true))
printf("QB save failed\n");
}

View File

@@ -310,6 +310,13 @@ static struct mm_region imx9_mem_map[] = {
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* QB data */
.virt = CONFIG_QB_SAVED_STATE_BASE,
.phys = CONFIG_QB_SAVED_STATE_BASE,
.size = 0x200000UL, /* 2M */
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE
}, {
/* empty entry to split table entry 5 if needed when TEEs are used */
0,
@@ -745,6 +752,46 @@ void build_info(void)
puts("\n");
}
int scmi_get_boot_device_offset(unsigned long *img_off)
{
int ret;
rom_passover_t rom_data = {0};
ret = scmi_get_rom_data(&rom_data);
if (!ret)
*img_off = rom_data.img_ofs;
return 0;
}
int scmi_get_boot_stage(u8 *stage)
{
int ret;
rom_passover_t rom_data = {0};
ret = scmi_get_rom_data(&rom_data);
if (!ret)
*stage = rom_data.boot_stage;
return ret;
}
u8 scmi_get_imgset_sel(void)
{
rom_passover_t rdata = { 0 };
int ret = scmi_get_rom_data(&rdata);
if (!ret)
return rdata.img_set_sel;
return 0;
}
int boot_mode_getprisec(void)
{
return !!scmi_get_imgset_sel();
}
int arch_misc_init(void)
{
build_info();

View File

@@ -198,26 +198,15 @@ static u32 get_cpu_variant_type(u32 type)
bool npu_disable = !!(val & BIT(13));
bool core1_disable = !!(val & BIT(15));
u32 pack_9x9_fused = BIT(4) | BIT(5) | BIT(17) | BIT(19) | BIT(24);
u32 nxp_recog = (val & GENMASK(23, 16)) >> 16;
u32 speed = (val & GENMASK(11, 6)) >> 6;
/* For iMX91 */
if (type == MXC_CPU_IMX91) {
switch (nxp_recog) {
case 0x9:
case 0xA:
if ((val2 & pack_9x9_fused) == pack_9x9_fused)
type = MXC_CPU_IMX9111;
break;
case 0xD:
case 0xE:
type = MXC_CPU_IMX9121;
break;
case 0xF:
case 0x10:
type = MXC_CPU_IMX9101;
break;
default:
break; /* 9131 as default */
}
if (speed == 0xf) /* 800Mhz arm */
type += 1;
return type;
}

View File

@@ -12,6 +12,54 @@
static struct fuse_entry_desc mx6_fuse_descs[] = {
#if defined(CONFIG_MX6ULL)
{MODULE_TSC, "/soc/bus@2000000/touchscreen@2040000", 0x430, 22},
{MODULE_TSC, "/soc/bus@2000000/tsc@2040000", 0x430, 22},
{MODULE_ADC2, "/soc/bus@2100000/adc@219c000", 0x430, 23},
{MODULE_EPDC, "/soc/bus@2200000/epdc@228c000", 0x430, 24},
{MODULE_ESAI, "/soc/bus@2000000/spba-bus@2000000/esai@2024000", 0x430, 25},
{MODULE_FLEXCAN1, "/soc/bus@2000000/can@2090000", 0x430, 26},
{MODULE_FLEXCAN2, "/soc/bus@2000000/can@2094000", 0x430, 27},
{MODULE_SPDIF, "/soc/bus@2000000/spba-bus@2000000/spdif@2004000", 0x440, 2},
{MODULE_EIM, "/soc/bus@2100000/memory-controller@21b8000", 0x440, 3},
{MODULE_EIM, "/soc/bus@2100000/weim@21b8000", 0x440, 3},
{MODULE_SD1, "/soc/bus@2100000/mmc@2190000", 0x440, 4},
{MODULE_SD1, "/soc/bus@2100000/usdhc@2190000", 0x440, 4},
{MODULE_SD2, "/soc/bus@2100000/mmc@2194000", 0x440, 5},
{MODULE_SD2, "/soc/bus@2100000/usdhc@2194000", 0x440, 5},
{MODULE_QSPI1, "/soc/bus@2100000/spi@21e0000", 0x440, 6},
{MODULE_QSPI1, "/soc/bus@2100000/qspi@21e0000", 0x440, 6},
{MODULE_GPMI, "/soc/nand-controller@1806000", 0x440, 7},
{MODULE_APBHDMA, "/soc/dma-controller@1804000", 0x440, 7},
{MODULE_APBHDMA, "/soc/dma-apbh@1804000", 0x440, 7},
{MODULE_LCDIF, "/soc/bus@2100000/lcdif@21c8000", 0x440, 8},
{MODULE_PXP, "/soc/bus@2100000/pxp@21cc000", 0x440, 9},
{MODULE_CSI, "/soc/bus@2100000/csi@21c4000", 0x440, 10},
{MODULE_ADC1, "/soc/bus@2100000/adc@2198000", 0x440, 11},
{MODULE_ENET1, "/soc/bus@2100000/ethernet@2188000", 0x440, 12},
{MODULE_ENET2, "/soc/bus@2000000/ethernet@20b4000", 0x440, 13},
{MODULE_DCP, "/soc/bus@2200000/dcp@2280000", 0x440, 14},
{MODULE_USB_OTG2, "/soc/bus@2100000/usb@2184200", 0x440, 15},
{MODULE_SAI2, "/soc/bus@2000000/spba-bus@2000000/sai@202c000", 0x440, 24},
{MODULE_SAI3, "/soc/bus@2000000/spba-bus@2000000/sai@2030000", 0x440, 24},
{MODULE_DCP_CRYPTO, "/soc/bus@2200000/dcp@2280000", 0x440, 25},
{MODULE_UART5, "/soc/bus@2100000/serial@21f4000", 0x440, 26},
{MODULE_UART6, "/soc/bus@2100000/serial@21fc000", 0x440, 26},
{MODULE_UART7, "/soc/bus@2000000/spba-bus@2000000/serial@2018000", 0x440, 26},
{MODULE_UART8, "/soc/bus@2200000/serial@2288000", 0x440, 26},
{MODULE_PWM5, "/soc/bus@2000000/pwm@20f0000", 0x440, 27},
{MODULE_PWM6, "/soc/bus@2000000/pwm@20f4000", 0x440, 27},
{MODULE_PWM7, "/soc/bus@2000000/pwm@20f8000", 0x440, 27},
{MODULE_PWM8, "/soc/bus@2000000/pwm@20fc000", 0x440, 27},
{MODULE_ECSPI3, "/soc/bus@2000000/spba-bus@2000000/spi@2010000", 0x440, 28},
{MODULE_ECSPI3, "/soc/bus@2000000/spba-bus@2000000/ecspi@2010000", 0x440, 28},
{MODULE_ECSPI4, "/soc/bus@2000000/spba-bus@2000000/spi@2014000", 0x440, 28},
{MODULE_ECSPI4, "/soc/bus@2000000/spba-bus@2000000/ecspi@2014000", 0x440, 28},
{MODULE_I2C3, "/soc/bus@2100000/i2c@21a8000", 0x440, 29},
{MODULE_I2C4, "/soc/bus@2100000/i2c@21f8000", 0x440, 29},
{MODULE_GPT2, "/soc/bus@2000000/timer@20e8000", 0x440, 30},
{MODULE_GPT2, "/soc/bus@2000000/gpt@20e8000", 0x440, 30},
{MODULE_EPIT2, "/soc/bus@2000000/epit@20d4000", 0x440, 31},
{MODULE_TSC, "/soc/aips-bus@2000000/tsc@2040000", 0x430, 22},
{MODULE_ADC2, "/soc/aips-bus@2100000/adc@219c000", 0x430, 23},
{MODULE_EPDC, "/soc/aips-bus@2200000/epdc@228c000", 0x430, 24},
@@ -90,6 +138,55 @@ static struct fuse_entry_desc mx6_fuse_descs[] = {
{MODULE_GPT2, "/soc/aips-bus@02000000/gpt@020e8000", 0x440, 30},
{MODULE_EPIT2, "/soc/aips-bus@02000000/epit@020d4000", 0x440, 31},
#elif defined(CONFIG_MX6UL)
{MODULE_TSC, "/soc/bus@2000000/touchscreen@2040000", 0x430, 22},
{MODULE_TSC, "/soc/bus@2000000/tsc@2040000", 0x430, 22},
{MODULE_ADC2, "/soc/bus@2100000/adc@219c000", 0x430, 23},
{MODULE_SIM1, "/soc/bus@2100000/sim@218c000", 0x430, 24},
{MODULE_SIM2, "/soc/bus@2100000/sim@21b4000", 0x430, 25},
{MODULE_FLEXCAN1, "/soc/bus@2000000/can@2090000", 0x430, 26},
{MODULE_FLEXCAN2, "/soc/bus@2000000/can@2094000", 0x430, 27},
{MODULE_SPDIF, "/soc/bus@2000000/spba-bus@2000000/spdif@2004000", 0x440, 2},
{MODULE_EIM, "/soc/bus@2100000/memory-controller@21b8000", 0x440, 3},
{MODULE_EIM, "/soc/bus@2100000/weim@21b8000", 0x440, 3},
{MODULE_SD1, "/soc/bus@2100000/mmc@2190000", 0x440, 4},
{MODULE_SD1, "/soc/bus@2100000/usdhc@2190000", 0x440, 4},
{MODULE_SD2, "/soc/bus@2100000/mmc@2194000", 0x440, 5},
{MODULE_SD2, "/soc/bus@2100000/usdhc@2194000", 0x440, 5},
{MODULE_QSPI1, "/soc/bus@2100000/spi@21e0000", 0x440, 6},
{MODULE_QSPI1, "/soc/bus@2100000/qspi@21e0000", 0x440, 6},
{MODULE_GPMI, "/soc/nand-controller@1806000", 0x440, 7},
{MODULE_APBHDMA, "/soc/dma-controller@1804000", 0x440, 7},
{MODULE_APBHDMA, "/soc/dma-apbh@1804000", 0x440, 7},
{MODULE_LCDIF, "/soc/bus@2100000/lcdif@21c8000", 0x440, 8},
{MODULE_PXP, "/soc/bus@2100000/pxp@21cc000", 0x440, 9},
{MODULE_CSI, "/soc/bus@2100000/csi@21c4000", 0x440, 10},
{MODULE_ADC1, "/soc/bus@2100000/adc@2198000", 0x440, 11},
{MODULE_ENET1, "/soc/bus@2100000/ethernet@2188000", 0x440, 12},
{MODULE_ENET2, "/soc/bus@2000000/ethernet@20b4000", 0x440, 13},
{MODULE_CAAM, "/soc/bus@2100000/crypto@2140000", 0x440, 14},
{MODULE_CAAM, "/soc/bus@2100000/caam@2140000", 0x440, 14},
{MODULE_USB_OTG2, "/soc/bus@2100000/usb@2184200", 0x440, 15},
{MODULE_SAI2, "/soc/bus@2000000/spba-bus@2000000/sai@202c000", 0x440, 24},
{MODULE_SAI3, "/soc/bus@2000000/spba-bus@2000000/sai@2030000", 0x440, 24},
{MODULE_BEE, "/soc/bus@2000000/bee@2044000", 0x440, 25},
{MODULE_UART5, "/soc/bus@2100000/serial@21f4000", 0x440, 26},
{MODULE_UART6, "/soc/bus@2100000/serial@21fc000", 0x440, 26},
{MODULE_UART7, "/soc/bus@2000000/spba-bus@2000000/serial@2018000", 0x440, 26},
{MODULE_UART8, "/soc/bus@2000000/spba-bus@2000000/serial@2024000", 0x440, 26},
{MODULE_PWM5, "/soc/bus@2000000/pwm@20f0000", 0x440, 27},
{MODULE_PWM6, "/soc/bus@2000000/pwm@20f4000", 0x440, 27},
{MODULE_PWM7, "/soc/bus@2000000/pwm@20f8000", 0x440, 27},
{MODULE_PWM8, "/soc/bus@2000000/pwm@20fc000", 0x440, 27},
{MODULE_ECSPI3, "/soc/bus@2000000/spba-bus@2000000/spi@2010000", 0x440, 28},
{MODULE_ECSPI3, "/soc/bus@2000000/spba-bus@2000000/ecspi@2010000", 0x440, 28},
{MODULE_ECSPI4, "/soc/bus@2000000/spba-bus@2000000/spi@2014000", 0x440, 28},
{MODULE_ECSPI4, "/soc/bus@2000000/spba-bus@2000000/ecspi@2014000", 0x440, 28},
{MODULE_I2C3, "/soc/bus@2100000/i2c@21a8000", 0x440, 29},
{MODULE_I2C4, "/soc/bus@2100000/i2c@21f8000", 0x440, 29},
{MODULE_GPT2, "/soc/bus@2000000/timer@20e8000", 0x440, 30},
{MODULE_GPT2, "/soc/bus@2000000/gpt@20e8000", 0x440, 30},
{MODULE_EPIT2, "/soc/bus@2000000/epit@20d4000", 0x440, 31},
{MODULE_TSC, "/soc/aips-bus@2000000/tsc@2040000", 0x430, 22},
{MODULE_ADC2, "/soc/aips-bus@2100000/adc@219c000", 0x430, 23},
{MODULE_SIM1, "/soc/aips-bus@2100000/sim@218c000", 0x430, 24},

View File

@@ -10,6 +10,7 @@
* to decrypt an encrypted boot image.
*/
#include <config.h>
#include <asm/io.h>
#include <command.h>
#include <fsl_sec.h>

View File

@@ -294,6 +294,7 @@ void enable_caches(void)
__func__, ret);
}
mmu_enable();
icache_enable();
dcache_enable();
}

View File

@@ -266,9 +266,15 @@ int arch_misc_init(void)
struct udevice *dev;
int ret;
ret = uclass_first_device_err(UCLASS_MISC, &dev);
if (ret)
return ret;
/*
* The MUSB wrapper driver is bound as a MISC device, so probe here
* to register the musb device early.
*/
if (IS_ENABLED(CONFIG_USB_MUSB_TI)) {
ret = uclass_first_device_err(UCLASS_MISC, &dev);
if (ret)
return ret;
}
#if defined(CONFIG_DM_ETH) && defined(CONFIG_USB_ETHER)
usb_ether_init();

View File

@@ -13,7 +13,9 @@ menu "Select Target SoC"
config R8A78000
bool "Renesas SoC R8A78000"
select GICV3
imply CLK_R8A78000
imply PINCTRL_PFC_R8A78000
imply RENESAS_R8A78000_POWER_DOMAIN
endmenu

View File

@@ -40,6 +40,27 @@ else
srec_cat_le_cmd := "-l-e-constant"
endif
ifneq ($(CONFIG_RCAR_GEN5),)
quiet_cmd_srec_cat = SRECCAT $@
cmd_srec_cat = srec_cat -output $@ -M 8 $< -M 8 \
-Output_Block_Size 16 \
-generate 0x18402010 0x18402014 $(srec_cat_le_cmd) $(CONFIG_SYS_UBOOT_START) 4 \
-generate 0x18402014 0x18402018 $(srec_cat_le_cmd) 0x1ef000 4
quiet_cmd_srec_shdr_cat = SRECCAT $@
cmd_srec_shdr_cat = srec_cat -output $@ -M 8 \
-Output_Block_Size 16 \
-generate 0x18400000 0x18400004 $(srec_cat_le_cmd) 0x00000003 4 \
-generate 0x18400004 0x18400008 $(srec_cat_le_cmd) 0x0 4 \
-generate 0x18402000 0x18402004 $(srec_cat_le_cmd) 0x6b657963 4 \
-generate 0x18402004 0x18402008 $(srec_cat_le_cmd) 0x00010010 4 \
-generate 0x18402008 0x1840200c $(srec_cat_le_cmd) 0x0 4 \
-generate 0x1840200c 0x18402010 $(srec_cat_le_cmd) 0x34040000 4 \
-generate 0x18402010 0x18402014 $(srec_cat_le_cmd) $(CONFIG_SYS_UBOOT_START) 4 \
-generate 0x18402014 0x18402018 $(srec_cat_le_cmd) 0x1ef000 4 \
-generate 0x18402018 0x1840201c $(srec_cat_le_cmd) 0x0 4 \
-generate 0x1840201c 0x18402020 $(srec_cat_le_cmd) 0x0 4
else
ifneq ($(CONFIG_RCAR_GEN4),)
quiet_cmd_srec_cat = SRECCAT $@
cmd_srec_cat = srec_cat -output $@ -M 8 $< -M 8 \
@@ -106,10 +127,17 @@ quiet_cmd_srec_cat = SRECCAT $@
-generate 0xe6301264 0xe6301268 $(srec_cat_le_cmd) $2 4
endif
endif
endif
spl/u-boot-spl.scif: spl/u-boot-spl.srec spl/u-boot-spl.bin
$(call cmd,srec_cat,$(shell wc -c spl/u-boot-spl.bin | awk '{printf("0x%08x\n",$$1)}'))
u-boot-elf.scif: u-boot-elf.srec u-boot.bin
$(call cmd,srec_cat,$(shell wc -c u-boot-dtb.bin | awk '{printf("0x%08x\n",$$1)}'))
u-boot-elf.shdr: u-boot-elf.srec u-boot.bin
$(call cmd,srec_shdr_cat,$(shell wc -c u-boot-dtb.bin | awk '{printf("0x%08x\n",$$1)}'))
# if srec_cat is present build u-boot-spl.scif by default
has_srec_cat = $(call try-run,srec_cat -VERSion,y,n)
INPUTS-$(has_srec_cat) += u-boot-spl.scif

View File

@@ -0,0 +1,203 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (c) 2004-2008 Texas Instruments
*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
*/
#include <config.h>
#include <asm/psci.h>
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(_start)
SECTIONS
{
#if defined(CONFIG_ARMV7_SECURE_BASE) && defined(CONFIG_ARMV7_NONSEC)
/*
* If CONFIG_ARMV7_SECURE_BASE is true, secure code will not
* bundle with u-boot, and code offsets are fixed. Secure zone
* only needs to be copied from the loading address to
* CONFIG_ARMV7_SECURE_BASE, which is the linking and running
* address for secure code.
*
* If CONFIG_ARMV7_SECURE_BASE is undefined, the secure zone will
* be included in u-boot address space, and some absolute address
* were used in secure code. The absolute addresses of the secure
* code also needs to be relocated along with the accompanying u-boot
* code.
*
* So DISCARD is only for CONFIG_ARMV7_SECURE_BASE.
*/
/DISCARD/ : { *(.rel._secure*) }
#endif
. = 0x00000000;
. = ALIGN(4);
__image_copy_start = ADDR(.text);
.text :
{
CPUDIR/start.o (.text*)
*(.vectors)
}
/* This needs to come before *(.text*) */
.efi_runtime : {
__efi_runtime_start = .;
*(.text.efi_runtime*)
*(.rodata.efi_runtime*)
*(.data.efi_runtime*)
__efi_runtime_stop = .;
}
.text_rest :
{
*(.text*)
}
#ifdef CONFIG_ARMV7_NONSEC
/* Align the secure section only if we're going to use it in situ */
.__secure_start
#ifndef CONFIG_ARMV7_SECURE_BASE
ALIGN(CONSTANT(COMMONPAGESIZE))
#endif
: {
KEEP(*(.__secure_start))
}
#ifndef CONFIG_ARMV7_SECURE_BASE
#define __ARMV7_SECURE_BASE
#define __ARMV7_PSCI_STACK_IN_RAM
#else
#define __ARMV7_SECURE_BASE CONFIG_ARMV7_SECURE_BASE
#endif
.secure_text __ARMV7_SECURE_BASE :
AT(ADDR(.__secure_start) + SIZEOF(.__secure_start))
{
*(._secure.text)
}
.secure_data : AT(LOADADDR(.secure_text) + SIZEOF(.secure_text))
{
*(._secure.data)
}
#ifdef CONFIG_ARMV7_PSCI
.secure_stack ALIGN(ADDR(.secure_data) + SIZEOF(.secure_data),
CONSTANT(COMMONPAGESIZE)) (NOLOAD) :
#ifdef __ARMV7_PSCI_STACK_IN_RAM
AT(ADDR(.secure_stack))
#else
AT(LOADADDR(.secure_data) + SIZEOF(.secure_data))
#endif
{
KEEP(*(.__secure_stack_start))
/* Skip addresses for stack */
. = . + CONFIG_ARMV7_PSCI_NR_CPUS * ARM_PSCI_STACK_SIZE;
/* Align end of stack section to page boundary */
. = ALIGN(CONSTANT(COMMONPAGESIZE));
KEEP(*(.__secure_stack_end))
#ifdef CONFIG_ARMV7_SECURE_MAX_SIZE
/*
* We are not checking (__secure_end - __secure_start) here,
* as these are the load addresses, and do not include the
* stack section. Instead, use the end of the stack section
* and the start of the text section.
*/
ASSERT((. - ADDR(.secure_text)) <= CONFIG_ARMV7_SECURE_MAX_SIZE,
"Error: secure section exceeds secure memory size");
#endif
}
#ifndef __ARMV7_PSCI_STACK_IN_RAM
/* Reset VMA but don't allocate space if we have secure SRAM */
. = LOADADDR(.secure_stack);
#endif
#endif
.__secure_end : AT(ADDR(.__secure_end)) {
*(.__secure_end)
LONG(0x1d1071c); /* Must output something to reset LMA */
}
#endif
. = ALIGN(4);
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
. = ALIGN(4);
.data : {
__data_start = .;
*(.data*)
__data_end = .;
}
. = ALIGN(4);
. = .;
. = ALIGN(4);
__u_boot_list : {
KEEP(*(SORT(__u_boot_list*)));
}
.efi_runtime_rel : {
__efi_runtime_rel_start = .;
*(.rel*.efi_runtime)
*(.rel*.efi_runtime.*)
__efi_runtime_rel_stop = .;
}
. = ALIGN(8);
__image_copy_end = .;
/*
* if CONFIG_USE_ARCH_MEMSET is not selected __bss_end - __bss_start
* needs to be a multiple of 8 and we overlay .bss with .rel.dyn
*/
.rel.dyn ALIGN(8) : {
__rel_dyn_start = .;
*(.rel*)
__rel_dyn_end = .;
. = ALIGN(8);
}
_end = .;
_image_binary_end = .;
/*
* These sections occupy the same memory, but their lifetimes do
* not overlap: U-Boot initializes .bss only after applying dynamic
* relocations and therefore after it doesn't need .rel.dyn any more.
*/
/* BSS goes to special read-write offset below U-Boot entry point */
. = 0xb8400000;
.bss (OVERLAY): {
__bss_start = .;
*(.bss*)
. = ALIGN(4);
__bss_end = .;
}
/DISCARD/ : { *(.dynsym) }
/DISCARD/ : { *(.dynbss) }
/DISCARD/ : { *(.dynstr*) }
/DISCARD/ : { *(.dynamic*) }
/DISCARD/ : { *(.plt*) }
/DISCARD/ : { *(.interp*) }
/DISCARD/ : { *(.gnu.hash) }
/DISCARD/ : { *(.gnu*) }
/DISCARD/ : { *(.ARM.exidx*) }
/DISCARD/ : { *(.gnu.linkonce.armexidx.*) }
}
ASSERT(_image_binary_end % 8 == 0, \
"_image_binary_end must be 8-byte aligned for device tree");

View File

@@ -114,7 +114,6 @@ config STM32MP23X
select OF_BOARD
select PINCTRL_STM32
select STM32_RCC
select STM32_RESET
select STM32_SERIAL
select STM32MP_TAMP_NVMEM
select SYS_ARCH_TIMER

View File

@@ -196,12 +196,14 @@ config TARGET_STMARK2
select M54418
config TARGET_QEMU_M68K
bool "Support QEMU m68k virt"
select M68040
imply CMD_DM
help
This target supports the QEMU m68k virtual machine (-M virt).
It simulates a Motorola 68040 CPU with Goldfish peripherals.
bool "Support QEMU m68k virt"
select M68040
select BOARD_EARLY_INIT_R
select VIRTIO_MMIO
imply CMD_DM
help
This target supports the QEMU m68k virtual machine (-M virt).
It simulates a Motorola 68040 CPU with Goldfish peripherals.
endchoice

View File

@@ -23,18 +23,27 @@
#define __raw_writew(w,addr) ((*(volatile u16 *) (addr)) = (w))
#define __raw_writel(l,addr) ((*(volatile u32 *) (addr)) = (l))
#define readb(addr) in_8((volatile u8 *)(addr))
#define writeb(b,addr) out_8((volatile u8 *)(addr), (b))
#if !defined(__BIG_ENDIAN)
#define readw(addr) (*(volatile u16 *) (addr))
#define readl(addr) (*(volatile u32 *) (addr))
#define writew(b,addr) ((*(volatile u16 *) (addr)) = (b))
#define writel(b,addr) ((*(volatile u32 *) (addr)) = (b))
#define readb(addr) in_8((volatile u8 *)(addr))
#define writeb(b, addr) out_8((volatile u8 *)(addr), (b))
#ifdef CONFIG_M680x0
/*
* For classic m68k these work the same way as Linux:
* Read a little endian value, swap to the CPU endian.
*/
#define readw(addr) in_le16((volatile u16 *)(addr))
#define readl(addr) in_le32((volatile u32 *)(addr))
#define writew(b, addr) out_le16((volatile u16 *)(addr), (b))
#define writel(b, addr) out_le32((volatile u32 *)(addr), (b))
#else
#define readw(addr) in_be16((volatile u16 *)(addr))
#define readl(addr) in_be32((volatile u32 *)(addr))
#define writew(b,addr) out_be16((volatile u16 *)(addr),(b))
#define writel(b,addr) out_be32((volatile u32 *)(addr),(b))
/*
* For coldfire these read a big endian value and use it
* as-is. This means that for little endian devices on the
* bus like PCI device these won't work as expected currently.
*/
#define readw(addr) in_be16((volatile u16 *)(addr))
#define readl(addr) in_be32((volatile u32 *)(addr))
#define writew(b, addr) out_be16((volatile u16 *)(addr), (b))
#define writel(b, addr) out_be32((volatile u32 *)(addr), (b))
#endif
/*

View File

@@ -41,10 +41,12 @@
#ifdef CONFIG_FSL_CAAM
#include <fsl_sec.h>
#endif
#if defined(CONFIG_NXP_ESBC) && defined(CONFIG_FSL_CORENET)
#if defined(CONFIG_FSL_CORENET)
#include <asm/fsl_pamu.h>
#if defined(CONFIG_NXP_ESBC)
#include <fsl_secboot_err.h>
#endif
#endif
#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
#include <nand.h>
#include <errno.h>
@@ -899,6 +901,8 @@ int cpu_init_r(void)
#if defined(CONFIG_NXP_ESBC) && defined(CONFIG_FSL_CORENET)
if (pamu_init() < 0)
fsl_secboot_handle_error(ERROR_ESBC_PAMU_INIT);
#elif defined(CONFIG_FSL_CORENET)
pamu_init();
#endif
#ifdef CONFIG_FSL_CAAM

View File

@@ -14,7 +14,6 @@ dtb-$(CONFIG_TARGET_P1010RDB_PB) += p1010rdb-pb.dtb p1010rdb-pb_36b.dtb
dtb-$(CONFIG_TARGET_P1020RDB_PC) += p1020rdb-pc.dtb p1020rdb-pc_36b.dtb
dtb-$(CONFIG_TARGET_P1020RDB_PD) += p1020rdb-pd.dtb
dtb-$(CONFIG_TARGET_P2020RDB) += p2020rdb-pc.dtb p2020rdb-pc_36b.dtb
dtb-$(CONFIG_TARGET_P2041RDB) += p2041rdb.dtb
dtb-$(CONFIG_TARGET_P3041DS) += p3041ds.dtb
dtb-$(CONFIG_TARGET_P4080DS) += p4080ds.dtb
dtb-$(CONFIG_TARGET_P5040DS) += p5040ds.dtb

View File

@@ -1,138 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* P2041 Silicon/SoC Device Tree Source (pre include)
*
* Copyright 2011 - 2015 Freescale Semiconductor Inc.
* Copyright 2019-2020 NXP
*/
/dts-v1/;
/include/ "e500mc_power_isa.dtsi"
/ {
compatible = "fsl,P2041";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&mpic>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: PowerPC,e500mc@0 {
device_type = "cpu";
reg = <0>;
fsl,portid-mapping = <0x80000000>;
};
cpu1: PowerPC,e500mc@1 {
device_type = "cpu";
reg = <1>;
fsl,portid-mapping = <0x40000000>;
};
cpu2: PowerPC,e500mc@2 {
device_type = "cpu";
reg = <2>;
fsl,portid-mapping = <0x20000000>;
};
cpu3: PowerPC,e500mc@3 {
device_type = "cpu";
reg = <3>;
fsl,portid-mapping = <0x10000000>;
};
};
soc: soc@ffe000000 {
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
reg = <0xf 0xfe000000 0 0x00001000>;
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
compatible = "simple-bus";
mpic: pic@40000 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <4>;
reg = <0x40000 0x40000>;
compatible = "fsl,mpic", "chrp,open-pic";
device_type = "open-pic";
clock-frequency = <0x0>;
};
espi0: spi@110000 {
compatible = "fsl,mpc8536-espi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x110000 0x1000>;
fsl,espi-num-chipselects = <4>;
status = "disabled";
};
usb0: usb@210000 {
compatible = "fsl-usb2-mph";
reg = <0x210000 0x1000>;
phy_type = "utmi";
};
usb1: usb@211000 {
compatible = "fsl-usb2-mph";
reg = <0x210000 0x1000>;
phy_type = "utmi";
};
sata: sata@220000 {
compatible = "fsl,pq-sata-v2";
reg = <0x220000 0x1000>;
interrupts = <68 0x2 0 0>;
sata-offset = <0x1000>;
sata-number = <2>;
sata-fpdma = <0>;
};
esdhc: esdhc@114000 {
compatible = "fsl,esdhc";
reg = <0x114000 0x1000>;
clock-frequency = <0>;
};
/include/ "qoriq-i2c-0.dtsi"
/include/ "qoriq-i2c-1.dtsi"
};
pcie@ffe200000 {
compatible = "fsl,pcie-p2041", "fsl,pcie-fsl-qoriq";
reg = <0xf 0xfe200000 0x0 0x1000>; /* registers */
law_trgt_if = <0>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */
0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
};
pcie@ffe201000 {
compatible = "fsl,pcie-p2041", "fsl,pcie-fsl-qoriq";
reg = <0xf 0xfe201000 0x0 0x1000>; /* registers */
law_trgt_if = <1>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */
0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
};
pcie@ffe202000 {
compatible = "fsl,pcie-p2041", "fsl,pcie-fsl-qoriq";
reg = <0xf 0xfe202000 0x0 0x1000>; /* registers */
law_trgt_if = <2>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */
0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */
};
};

View File

@@ -0,0 +1,19 @@
// SPDX-License-Identifier: GPL-2.0+
&serial0 {
bootph-all;
};
&soc {
i2c@118000 {
bootph-all;
};
spi@110000 {
flash@0 {
spi-max-frequency = <10000000>;
};
};
};
#include "u-boot.dtsi"

View File

@@ -1,127 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* P2041RDB Device Tree Source
*
* Copyright 2011 - 2015 Freescale Semiconductor Inc.
* Copyright 2019-2020 NXP
*/
/include/ "p2041.dtsi"
/ {
model = "fsl,P2041RDB";
compatible = "fsl,P2041RDB";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&mpic>;
aliases {
phy_rgmii_0 = &phy_rgmii_0;
phy_rgmii_1 = &phy_rgmii_1;
phy_sgmii_2 = &phy_sgmii_2;
phy_sgmii_3 = &phy_sgmii_3;
phy_sgmii_4 = &phy_sgmii_4;
phy_sgmii_1c = &phy_sgmii_1c;
phy_sgmii_1d = &phy_sgmii_1d;
phy_sgmii_1e = &phy_sgmii_1e;
phy_sgmii_1f = &phy_sgmii_1f;
phy_xgmii_2 = &phy_xgmii_2;
spi0 = &espi0;
};
soc: soc@ffe000000 {
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
reg = <0xf 0xfe000000 0 0x00001000>;
fman@400000 {
ethernet@e0000 {
phy-handle = <&phy_sgmii_2>;
phy-connection-type = "sgmii";
};
mdio@e1120 {
phy_rgmii_0: ethernet-phy@0 {
reg = <0x0>;
};
phy_rgmii_1: ethernet-phy@1 {
reg = <0x1>;
};
phy_sgmii_2: ethernet-phy@2 {
reg = <0x2>;
};
phy_sgmii_3: ethernet-phy@3 {
reg = <0x3>;
};
phy_sgmii_4: ethernet-phy@4 {
reg = <0x4>;
};
phy_sgmii_1c: ethernet-phy@1c {
reg = <0x1c>;
};
phy_sgmii_1d: ethernet-phy@1d {
reg = <0x1d>;
};
phy_sgmii_1e: ethernet-phy@1e {
reg = <0x1e>;
};
phy_sgmii_1f: ethernet-phy@1f {
reg = <0x1f>;
};
};
ethernet@e2000 {
phy-handle = <&phy_sgmii_3>;
phy-connection-type = "sgmii";
};
ethernet@e4000 {
phy-handle = <&phy_sgmii_4>;
phy-connection-type = "sgmii";
};
ethernet@e6000 {
phy-handle = <&phy_rgmii_1>;
phy-connection-type = "rgmii";
};
ethernet@e8000 {
phy-handle = <&phy_rgmii_0>;
phy-connection-type = "rgmii";
};
ethernet@f0000 {
phy-handle = <&phy_xgmii_2>;
phy-connection-type = "xgmii";
};
mdio@f1000 {
phy_xgmii_2: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x0>;
};
};
};
};
};
&espi0 {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
/* input clock */
spi-max-frequency = <10000000>;
};
};
/include/ "p2041si-post.dtsi"

View File

@@ -1,43 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* P2041/P2040 Silicon/SoC Device Tree Source (post include)
*
* Copyright 2011 - 2015 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*
*/
&soc {
/include/ "qoriq-clockgen1.dtsi"
/include/ "qoriq-gpio-0.dtsi"
/include/ "qoriq-sec4.2-0.dtsi"
/* include used FMan blocks */
/include/ "qoriq-fman-0.dtsi"
/include/ "qoriq-fman-0-1g-0.dtsi"
/include/ "qoriq-fman-0-1g-1.dtsi"
/include/ "qoriq-fman-0-1g-2.dtsi"
/include/ "qoriq-fman-0-1g-3.dtsi"
/include/ "qoriq-fman-0-1g-4.dtsi"
/include/ "qoriq-fman-0-10g-0.dtsi"
fman@400000 {
enet0: ethernet@e0000 {
};
enet1: ethernet@e2000 {
};
enet2: ethernet@e4000 {
};
enet3: ethernet@e6000 {
};
enet4: ethernet@e8000 {
};
enet5: ethernet@f0000 {
};
};
};

View File

@@ -6,7 +6,7 @@
*/
#include <dm.h>
#include <ec_commands.h>
#include <cros_ec.h>
#include <init.h>
#include <log.h>
#include <spi_flash.h>

View File

@@ -81,12 +81,13 @@ char *soc_name_decode(void)
}
/*
* --rev. are 6 chars
* max platform name is qemu which is 4 chars
* --rev.-el are 9 chars
* max platform name is emu-mmd which is 7 chars
* platform version number are 1+1
* Plus 1 char for \n
* el is 1 char
* Plus 1 char for NULL byte
*/
name = calloc(1, strlen(CONFIG_SYS_BOARD) + 13);
name = calloc(1, strlen(CONFIG_SYS_BOARD) + 20);
if (!name)
return NULL;

4
board/apple/mac/mac.env Normal file
View File

@@ -0,0 +1,4 @@
stdin=serial,usbkbd,spikbd
stdout=vidconsole,serial
stderr=vidconsole,serial
boot_targets=nvme usb

View File

@@ -909,8 +909,10 @@ static const struct boot_mode board_boot_modes[] = {
int misc_init_r(void)
{
#if defined(CONFIG_VIDEO_IPUV3)
gpio_request(RGB_BACKLIGHT_GP, "lvds backlight");
gpio_request(LVDS_BACKLIGHT_GP, "lvds backlight");
#endif
gpio_request(GP_USB_OTG_PWR, "usbotg power");
gpio_request(IMX_GPIO_NR(7, 12), "usbh1 hub reset");
gpio_request(IMX_GPIO_NR(2, 2), "back");

View File

@@ -778,7 +778,7 @@ static int sata_imx_remove(struct udevice *dev)
return 0;
}
struct ahci_ops sata_imx_ops = {
static const struct ahci_ops sata_imx_ops = {
.port_status = dwc_ahsata_port_status,
.reset = dwc_ahsata_bus_reset,
.scan = dwc_ahsata_scan,

View File

@@ -14,9 +14,14 @@
#include <asm/bootinfo.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <dm.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
#include <dm/platdata.h>
#include <dm/root.h>
#include <linux/errno.h>
#include <linux/sizes.h>
#include <virtio_mmio.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -25,6 +30,38 @@ static struct goldfish_rtc_plat rtc_plat;
static struct goldfish_timer_plat timer_plat;
static struct qemu_virt_ctrl_plat reset_plat;
#define VIRTIO_MMIO_NUM 128
#define VIRTIO_MMIO_SZ 0x200
static struct virtio_mmio_plat virtio_mmio_plat[VIRTIO_MMIO_NUM];
static char virtio_mmio_names[VIRTIO_MMIO_NUM][11];
static phys_addr_t virtio_mmio_base;
static int create_virtio_mmios(void)
{
struct driver *drv;
int i, ret;
if (!virtio_mmio_base)
return -ENODEV;
drv = lists_driver_lookup_name("virtio-mmio");
if (!drv)
return -ENOENT;
for (i = 0; i < VIRTIO_MMIO_NUM; i++) {
virtio_mmio_plat[i].base = virtio_mmio_base + (VIRTIO_MMIO_SZ * i);
sprintf(virtio_mmio_names[i], "virtio-%d", i);
ret = device_bind(dm_root(), drv, virtio_mmio_names[i],
&virtio_mmio_plat[i], ofnode_null(), NULL);
if (ret)
return ret;
}
return 0;
}
/*
* Theoretical limit derivation:
* Max Bootinfo Size (Standard Page) = 4096 bytes
@@ -65,6 +102,9 @@ static void parse_bootinfo(void)
case BI_VIRT_CTRL_BASE:
reset_plat.reg = base;
break;
case BI_VIRT_VIRTIO_BASE:
virtio_mmio_base = base;
break;
case BI_MEMCHUNK:
gd->ram_size = record->data[1];
break;
@@ -80,6 +120,11 @@ int board_early_init_f(void)
return 0;
}
int board_early_init_r(void)
{
return create_virtio_mmios();
}
int checkboard(void)
{
puts("Board: QEMU m68k virt\n");

View File

@@ -1,7 +1,6 @@
Kontron pITX-imx8m Board
M: Heiko Thiery <heiko.thiery@gmail.com>
S: Maintained
F: arch/arm/dts/imx8mq-kontron-pitx-imx8m*
F: board/kontron/pitx_imx8m/*
F: include/configs/kontron_pitx_imx8m.h
F: configs/kontron_pitx_imx8m_defconfig

View File

@@ -10,6 +10,11 @@
#ifdef CONFIG_FSL_USE_PCA9547_MUX
int select_i2c_ch_pca9547(u8 ch, int bus);
#else
static inline int select_i2c_ch_pca9547(u8 ch, int bus)
{
return -EOPNOTSUPP;
}
#endif
#endif

View File

@@ -65,7 +65,7 @@ int power_init_board(void)
* Enable DVS control through PMIC_STBY_REQ and
* set B1_ENMODE=1 (ON by PMIC_ON_REQ=H)
*/
if (CONFIG_IS_ENABLED(IMX8M_VDD_SOC_850MV))
if (IS_ENABLED(CONFIG_IMX8M_VDD_SOC_850MV))
pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14);
else
pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C);

View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2025 NXP
* Copyright 2025-2026 NXP
*/
#include <hang.h>
@@ -14,6 +14,7 @@
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/ele_api.h>
#include <asm/mach-imx/qb.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -44,6 +45,9 @@ void spl_board_init(void)
ret = ele_start_rng();
if (ret)
printf("Fail to start RNG: %d\n", ret);
if (IS_ENABLED(CONFIG_SPL_IMX_QB))
spl_imx_qb_save();
}
static void xspi_nor_reset(void)

View File

@@ -8,6 +8,7 @@
#include <asm/gpio.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/ele_api.h>
#include <asm/mach-imx/qb.h>
#include <asm/sections.h>
#include <hang.h>
#include <init.h>
@@ -44,6 +45,9 @@ void spl_board_init(void)
ret = ele_start_rng();
if (ret)
printf("Fail to start RNG: %d\n", ret);
if (IS_ENABLED(CONFIG_SPL_IMX_QB))
spl_imx_qb_save();
}
static void xspi_nor_reset(void)

View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2025 NXP
* Copyright 2025-2026 NXP
*/
#include <hang.h>
@@ -13,6 +13,7 @@
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/ele_api.h>
#include <asm/mach-imx/qb.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -41,6 +42,9 @@ void spl_board_init(void)
ret = ele_start_rng();
if (ret)
printf("Fail to start RNG: %d\n", ret);
if (IS_ENABLED(CONFIG_SPL_IMX_QB))
spl_imx_qb_save();
}
void board_init_f(ulong dummy)

View File

@@ -7,16 +7,6 @@
#include <dm.h>
#include <net.h>
#include <asm/io.h>
#include <netdev.h>
#include <fm_eth.h>
#include <fsl_mdio.h>
#include <malloc.h>
#include <asm/types.h>
#include <fsl_dtsec.h>
#include <asm/arch/soc.h>
#include <asm/arch-fsl-layerscape/config.h>
#include <asm/arch-fsl-layerscape/immap_lsch2.h>
#include <asm/arch/fsl_serdes.h>
#include <linux/delay.h>
#include <net/pfe_eth/pfe_eth.h>
#include <dm/platform_data/pfe_dm_eth.h>

View File

@@ -6,18 +6,6 @@
#include <config.h>
#include <dm.h>
#include <net.h>
#include <asm/io.h>
#include <netdev.h>
#include <fm_eth.h>
#include <fsl_mdio.h>
#include <malloc.h>
#include <asm/types.h>
#include <fsl_dtsec.h>
#include <asm/arch/soc.h>
#include <asm/arch-fsl-layerscape/config.h>
#include <asm/arch-fsl-layerscape/immap_lsch2.h>
#include <asm/arch/fsl_serdes.h>
#include <linux/delay.h>
#include <net/pfe_eth/pfe_eth.h>
#include <dm/platform_data/pfe_dm_eth.h>

View File

@@ -123,11 +123,6 @@ int dram_init(void)
return 0;
}
int board_eth_init(struct bd_info *bis)
{
return pci_eth_init(bis);
}
int board_early_init_f(void)
{
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;

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