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785 Commits

Author SHA1 Message Date
Tom Rini
23987e1090 Prepare v2026.01-rc1
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-10-27 16:10:23 -06:00
Tom Rini
f17f11880a configs: Resync with savedefconfig
Resync all defconfig files using qconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-10-27 09:57:45 -06:00
Tom Rini
c95334515f Merge https://source.denx.de/u-boot/custodians/u-boot-sunxi
No big features this time, mostly a collection of patches that have been
lying around for a bit.  There are some DT updates, for those SoCs that
do not use OF_UPSTREAM yet, hopefully that's the last time we need to do
this exercise. And that's offset by switching over two more SoCs to
OF_UPSTREAM.  Two new boards get a defconfig, and some improvements for
the sun8i-emac Ethernet driver. Finally a patch that fixes occassional
DRAM size misdetection for new A523 boards.

There are a few outstanding patches that just wait for getting some
details confirmed, which I might send then later.

CI passed, and I tested this briefly on affected boards.
2025-10-27 09:46:51 -06:00
Andre Przywara
fa4dfe870c sunxi: dts: arm: update devicetree files from Linux kernel tree
Sync the kernel devicetree source files for the Allwinner SoCs with
32-bit cores that do not use OF_UPSTREAM yet. The files were taken
from a v6.18-rc1 tree.

To maintain ABI compatibility with existing LTS kernels, one change
moving some IP blocks to the r_intc interrupt controller is excluded.
This effectively reverts Linux commits 994e5818392c and 9fdef3c3d8c2.

This commit also adds a new board devicetree for the A33 Vstar board,
plus one DT overlay for the OrangePi Zero interface board.

This update should not impact any existing U-Boot functionality.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2025-10-27 11:12:57 +00:00
Andre Przywara
e828295c90 sunxi: dts: arm64: update devicetree files from Linux kernel tree
Sync the devicetree files from the official Linux kernel tree, v6.18-rc1.
This is covering Allwinner SoCs with 64-bit ARM cores.

The bulk is cosmetic changes: board model name changes, DT node renames,
whitespace fixes.
The actual changes are not dramatic: the CPU cores get their caches
described properly, some A64 video clocks get fixed, some A64 boards
describe the header pins for the WiFi module, the Pinephone adds an
alternative magnetometer used on some board revisions.
On the H5 side the microSD slots get marked as having no write-protect
detection, and the NanoPi Neo Plus2 board describes its regulators better.
The H6 boards switch from RSB to I2C for their PMIC connection.

As before, this omits the non-backwards compatible changes to the R_INTC
controller, to remain compatible with older kernels.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2025-10-27 11:12:57 +00:00
Andre Przywara
993c48bd41 sunxi: switch Allwinner A80 boards to OF_UPSTREAM
In contrast to some other Allwinner SoCs, there is no difference between
the DTs for the Allwinner A80 SoCs (sun9i) between the U-Boot and the
Linux kernel repository.

Remove the old copies of the A80 related .dts and .dtsi files, and switch
most of sun9i boards over to use OF_UPSTREAM.

There is the Sunchip CX-A99 (family of) board(s) for which we don't have
a DT in the kernel tree. Keep the .dts file in the legacy U-Boot DT
directory, and let the board's defconfig opt out of OF_UPSTREAM.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2025-10-27 11:12:57 +00:00
Andre Przywara
15e158ccd9 sunxi: switch the Allwinner T113 SoC to OF_UPSTREAM
In contrast to some other Allwinner SoCs, there is no difference between
the DTs for the Allwinner T113-s3 SoC (sun20i) between the U-Boot and the
Linux kernel repository.

Remove the old copies of the T113-s3 related .dts and .dtsi files, and
switch the whole SoC (represented by just one board) over to use
OF_UPSTREAM.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2025-10-27 11:12:57 +00:00
Paul Kocialkowski
48293ab19a net: sun8i-emac: Add support for active-low leds with internal PHY
A device-tree property is already defined to indicate that the internal
PHY should be used with active-low leds, which corresponds to a
specific bit in the dedicated syscon register.

Add support for setting this bit when the property is present.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2025-10-27 11:12:56 +00:00
Paul Kocialkowski
8513f7e78a net: sun8i-emac: Remove internal PHY config default value
We know about all the relevant fields in the syscon register so there
is no reason to read it first and modify it.

Build the register from scratch instead, with all relevant fields set.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
2025-10-27 11:12:56 +00:00
Lukas Schmid
bf9636ef36 sunxi: add support for NetCube Systems Kumquat
NetCube Systems Kumquat is a board based on the Allwinner V3s SoC,
including:

- 64MB DDR2 included in SoC
- 10/100 Mbps Ethernet
- USB-C DRD
- Audio Codec
- Isolated CAN-FD
- ESP32 over SDIO
- 8MB SPI-NOR Flash for bootloader
- I2C EEPROM for MAC addresses
- SDIO Connector for eMMC or SD-Card
- 8x 12/24V IOs, 4x normally open relays
- DS3232 RTC with Battery Backup
- QWIIC connectors for external I2C devices

Signed-off-by: Lukas Schmid <lukas.schmid@netcube.li>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2025-10-27 11:12:01 +00:00
James Hilliard
951c5a2964 Makefile: pass KEYDIR when set to sunxi-spl.bin mkimage
Currently we pass this for u-boot-spl.kwb targets, however when
building sunxi-spl.bin in the TOC0 format we may also need to
specify a KEYDIR, as such we should also pass this when set
to mkimage for the sunxi-spl.bin target.

Signed-off-by: James Hilliard <james.hilliard1@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2025-10-27 00:44:53 +00:00
Andre Przywara
fb48e8760e sunxi: a523: Re-use H6/H616 DRAM size detection method
The H6 and H616 DRAM initialisation code recently gained a joint and
improved size detection routine, which helped to avoid the occasional
DRAM size misdetection.

Use the same code for the A523 DRAM initialisation as well, which
suffers from the same misdetection at times.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Tested-by: Chen-Yu Tsai <wens@kernel.org>
2025-10-27 00:44:53 +00:00
Chen-Yu Tsai
4e203ee0ce sunxi: a523: Add OrangePi 4A defconfig
The OrangePi 4A is a typical Raspberry Pi model B sized development
board from Xunlong designed around an Allwinner T527 SoC.

The board has the following features:
- Allwinner T527 SoC
- AXP717B + AXP323 PMICs
- Up to 4GB LPDDR4 DRAM
- micro SD slot
- optional eMMC module
- M.2 slot for PCIe 2.0 x1
- 16 MB SPI-NOR flash
- 4x USB 2.0 type-A ports (one can be used in gadget mode)
- 1x Gigabit ethernet w/ Motorcomm PHY (through yet to be supported GMAC200)
- 3.5mm audio jack via internal audio codec
- HDMI 2.0 output
- eDP, MIPI CSI (2-lane and 4-lane) and MIPI DSI (4-lane) connectors
- USB type-C port purely for power
- AP6256 (Broadcom BCM4345) WiFi 5.0 + BT 5.0
- unsoldered headers for ADC and an additional USB 2.0 host port
- 40-pin GPIO header

Add defconfig for it.

Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2025-10-27 00:44:53 +00:00
Tom Rini
9094482ca7 Merge tag 'efi-2026-01-rc1-2' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request efi-2026-01-rc1-2

CI:

* https://source.denx.de/u-boot/custodians/u-boot-efi/-/pipelines/28024

Documentation:

* develop: virtio: Fix qemu example (true/false -> on/off)
* separate read and write command documentation
* usage: Add general rule for `$?`
* askenv: Reword and remove return value
* seama: Reword return value section
* usage: Use glob for all commands
* Fix typos and formatting

UEFI:

* console: support editable input fields
2025-10-26 09:03:36 -06:00
Tom Rini
5335f8d25b doc/usage: Add a reference to General rules for commands
For clarity, add a reference link to the start of the section on command
documentation that all commands follow some general rules.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-10-26 09:03:36 -06:00
Tom Rini
ab9080820e doc: usage: Use glob for all commands
Make use of the glob syntax to automatically include all command
documents.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-10-26 09:03:36 -06:00
Tom Rini
dbdf60b7aa doc: seama: Reword return value section
With the addition of general text about how the return value is handled,
reference that while retaining the additional information about setting
$seama_image_size

Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-10-26 09:03:36 -06:00
Tom Rini
ddc7a60cc7 doc: askenv: Reword and remove return value
With the addition of general text about how the return value is handled,
remove the examples from the askenv documentation as they are all normal
expected results.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
2025-10-26 09:03:36 -06:00
Tom Rini
11da3403e9 doc: usage: Add general rule for $?
For nearly all commands in U-Boot the '?' variable is handled the same
way with 0 meaning success, 1 meaning any failure.  Explain this in the
general rules section of the cmdline documentation (with a link to a
counter example) and then remove the redundant wording from most
commands. We retain a section about the return value in a number of
places where we are doing something such as always returning a specific
value or we have useful additional information to go along with the
normal return codes.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2025-10-26 09:03:35 -06:00
Wolfgang Wallner
1f6da608c3 doc: develop: virtio: Fix qemu example (true/false -> on/off)
The given qemu examples use true/false, while qemu actually on/off.

Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2025-10-26 09:03:35 -06:00
Wolfgang Wallner
72ec263403 doc: Fix whitespace in devicetree example in overlay-fdt-boot.rst
Fix the whitespace and add a missing quotation mark
(default = "foo-reva.dtb") in overlay-fdt-boot.rst.

Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2025-10-26 09:03:35 -06:00
Wolfgang Wallner
296f9eac9f boot: Fix typo
Fix a typo in image-fit.c.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2025-10-26 09:03:34 -06:00
Wolfgang Wallner
4661eb33a4 bootm: Fix typo in bootm.h
Fix a typo in include/bootm.h.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2025-10-26 09:03:32 -06:00
Wolfgang Wallner
e9386ec1d7 image: Fix typos in image.h
Fix some typos in include/image.h.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2025-10-26 09:03:30 -06:00
Wolfgang Wallner
c8637b7496 boot: kconfig: Fix typos
Fix typos in boot/Kconfig.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2025-10-26 09:03:27 -06:00
Wolfgang Wallner
ed00d12c01 doc: Fix typos
Fix typos/wording in various files in doc/.

Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: E Shattow <e@freeshell.de>
2025-10-26 09:03:27 -06:00
Wolfgang Wallner
66f7574ddd doc: develop: Change formatting to make binman doc more readable
Change the formatting of binman.rst so that the compiled HTML output
becomes more readable. Changes include enumerations and the escaping of
arguments starting with a double dash (e.g. --debug).

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2025-10-26 09:03:26 -06:00
Wolfgang Wallner
e87130e071 doc: develop: Fix typos in binman/binman.rst
Fix some typos in binman.rst.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2025-10-26 08:40:54 -06:00
Casey Connolly
419cc25aa1 efi_loader: efi_console: support editable input fields
When editing eficonfig "optional data" (typically cmdline arguments)
it's useful to be able to edit the string rather than having to re-type
the entire thing. Implement support for editing buffers to make this a
whole lot nicer. Specifically, add support for moving the cursor with
the arrow keys and End key as well as deleting backwards with the delete
key.

Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Tested-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2025-10-26 10:15:21 +00:00
Heinrich Schuchardt
3cb97f9293 doc: separate read and write command documentation
* Avoid two step navigation to get to the description of the write command.
* Add missing index entries
* Correct formatting of the examples.
* Describe configuration and return value.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2025-10-26 10:15:21 +00:00
Tom Rini
fd976ff3a2 Merge patch series "firmware: scmi: Support SCMI LMM/CPU protocol for i.MX95"
Peng Fan (OSS) <peng.fan@oss.nxp.com> says:

i.MX95 System Manager(SM) implements Logical Machine Management(LMM) and
CPU protocol to manage Logical Machine(LM) and CPUs(eg, M7).

To manage M7 in a separate LM or in same LM as U-Boot/Linux itself. LMM
APIs and CPU APIs are needed.

When M7 is in LM 'lm-m7', and this LM is managable by 'uboot-lm', U-Boot
could use LMM_BOOT, LMM_SHUTDOWN and etc to manage 'lm-m7'.

If in same LM, use CPU_START, CPU_STOP, CPU_RESET_VECTOR_SET and etc to
manage M7.

Both LMM/CPU APIs will be used by remoteproc driver.

The documentation could be found in Linux Kernel:
drivers/firmware/arm_scmi/vendors/imx/imx95.rst

Link: https://lore.kernel.org/r/20251017-scmi-lmm-v1-0-9fd41e7a5ac0@nxp.com
2025-10-24 13:47:50 -06:00
Benjamin Hahn
fae6c54d23 bootstd: make it possible to use tftp for netboot with standardboot
Add the option to load the bootscript with the tftp command (static IP)
instead of the dhcp command (dynamic IP). For this a new function
tftpb_run similar to dhcp_run, is needed. The selection of which command
to use can be done with the ip_dyn environment variable, which can be
set to yes or no. The ip_dyn variable was chosen as it is already in use
on the imx platforms.
Also edit the bootstd doc.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Benjamin Hahn <B.Hahn@phytec.de>
2025-10-24 13:47:50 -06:00
Peng Fan
ac9b02dd10 firmware: scmi: Add i.MX95 SCMI CPU Protocol
This protocol allows an agent to start, stop a CPU or set reset vector.
It is used to manage auxiliary CPUs in an LM (e.g. additional cores in an
AP cluster).

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Alice Guo <alice.guo@nxp.com>
2025-10-24 13:47:50 -06:00
Hrushikesh Salunke
8506cf58ff phy: ti: phy-j721e-wiz: Allow reinitialization when SERDES is pre-configured
Move the SERDES configuration check after clock and reset initialization
and change it from a hard failure to a skip of WIZ initialization. This
allows the driver to probe successfully when the SERDES has been
pre-configured by a previous boot stage (e.g., ROM or SPL).

This approach aligns with how the Linux kernel handles pre-configured
SERDES, where the driver gracefully skips reinitialization rather than
failing to probe.

Signed-off-by: Hrushikesh Salunke <h-salunke@ti.com>
2025-10-24 13:47:50 -06:00
Peng Fan
3f20ea3675 firmware: scmi: Add i.MX95 SCMI LMM protocol driver
Add Logical Machine Management(LMM) protocol which is intended for boot,
shutdown, and reset of other logical machines (LM). It is usually used to
allow one LM to manager another used as an offload or accelerator engine.

Following Linux Kernel, created a separate folder for holding vendor
protocol drivers.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Alice Guo <alice.guo@nxp.com>
2025-10-24 13:47:50 -06:00
Ilias Apalodimas
104a0de784 arm: armv8: Make save_boot_params simpler
The idiom used in save_boot_params is common for armv7.
In armv8 is much easier to do the same thing with adr/adrp.

So let's simplify the code a bit.

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-10-24 13:47:50 -06:00
Peng Fan
7830ccc77a firmware: scmi: Support probe vendor ID 0x80 and 0x82
Preparing to add i.MX LMM and CPU protocol driver, support probe SCMI
vendor ID 0x80(i.MX SCMI LMM ID) and 0x82(i.MX SCMI CPU ID). And use
Kconfig option to support conditional compilation.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Alice Guo <alice.guo@nxp.com>
2025-10-24 13:47:50 -06:00
Tom Rini
cf262e1608 env: fat, ubi: Fix gd->env_valid for the first write
As resolved and explained in detail in commit e589d5822c ("env: spi:
Fix gd->env_valid for the first write") and archived discussion there is
a corner case where we don't do the right thing with redundant
environments. This same exact check was present in the mmc code and
resolved with commit 813a0df27a ("env: Invert gd->env_valid for
env_mmc_save") and in the discussion of that patch, I noted that both
fat and ubi (and at the time, sf) were doing the same thing. Take the
time now to correct fat and ubi environment.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-10-24 13:47:50 -06:00
Peng Fan
d1f1c98d84 firmware: scmi: Cleanup the SCMI MISC ID
SCMI_IMX_PROTOCOL_ID_MISC was never used, so drop it. And move
SCMI_PROTOCOL_ID_IMX_MISC out of enum scmi_std_protocol to
scmi_nxp_protocols.h, because it is i.MX specific and following Linux
Kernel style, use macro definition.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Alice Guo <alice.guo@nxp.com>
2025-10-24 13:47:50 -06:00
Peng Fan
251dd6bf0e firmware: scmi: Conditionally compile protocol support
Add conditional compilation for SCMI protocol support in scmi_get_protocol()
and scmi_add_protocol() based on corresponding Kconfig options. This ensures
that only the enabled protocols are compiled and accessed, and reducing binary
size.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Alice Guo <alice.guo@nxp.com>
2025-10-24 13:47:50 -06:00
Ilias Apalodimas
38f40e6de6 makefile: Fix recursive makes
Since the Kbuild bump to 5.1 and specifically
commit af1a993570 ("kbuild: make -r/-R effective in top Makefile for old Make versions")
the recursion rules have changed.

'make O=/output/dir/' as well as './test/py/test.py --bd sandbox --build'
is working fine but anything that recursively called the makefile was
failing e.g 'make tests', 'make qcheck' etc, which calls a bash script
that ends up calling the makefile again.

The reason is that the internal 'sub_make_done' variable of the makefile
was set after the first pass and the output dir was never evaluated
properly.  Reset the variable value if we are executing any of these
tests.

Fixes: af1a993570 ("kbuild: make -r/-R effective in top Makefile for old Make versions")
Reported-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Test-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2025-10-24 13:47:10 -06:00
Tom Rini
b10c055d4e Merge patch series "boot: Support priority for global bootmeths"
Simon Glass <sjg@chromium.org> says:

At present global bootmeths always run first, before all other
bootmeths. Optimisations in the code take advantage of this, putting
them at the end, so they can be used once and then forgotten.

In some cases it is useful to run global bootmeths later in the boot.
For example, the EFI-bootmgr bootmeth may itself scan devices and the
network, so running it first can hold up the boot significantly for
boards not actually relying on EFI-bootmgr to boot.

This series introduces a new field in global bootmeths which indicates
the priority, using the same scheme as is used with bootdev hunters.
Thus it is possible to insert the EFI-bootmgr bootmeth just before the
hunter for network bootdevs is invoked.

Despite the simplicity of the concept and the relatively small series,
this is a fairly significant enhancement. It is also quite tricky to
implement, largely due to the way the original code was written, with
global bootmeths being a small, size-optimised add-on to the original
bootstd implementation.

For now we only allow each global bootmeth to run at most once, but this
implementation is written in a way that we could relax that if needed.
Then the bootmeth itself could decide whether to run at any particular
point in the bootflow iteration.

Link: https://lore.kernel.org/r/20251015154423.908468-1-sjg@chromium.org
2025-10-22 16:16:31 -06:00
Simon Glass
6a56d10fdc boot: Run the EFI bootmgr just before network devices
At present the EFI bootmgr scans all devices in the system before
deciding which one to boot. Ideally it would use the bootstd iterator
for this, but in the meantime, give it a lower priority, so it runs
just before the network devices.

Note that if there are no hunted network devices hunted, then it will
run at the end, after all bootdevs are exhausted. In other words, it
will always run.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-10-22 14:16:56 -06:00
Simon Glass
060ce66b83 boot: Run global bootmeths after all bootdevs are exhausted
When there are no more bootdevs we should still go through the global
bootmeths, since some may not have yet been used, if their priority has
not yet come up.

Add a final check for this at the end of the iterator.

Update the documentation to match the new behaviour of global bootmeths.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-10-22 14:16:56 -06:00
Simon Glass
eff1dca963 boot: Don't change the method count after global bootmeths
At present before scanning global bootmeths, the iterator sets the
method count to the index of the first global bootmeth. Now that we
support scanning the global bootmeths multiple times, we must leave this
count alone.

Check against have_global and first_glob_method instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-10-22 14:16:56 -06:00
Simon Glass
4ce78089b2 boot: Implement a priority for global bootmeths
Allow bootmeths to select when they want to run, using the bootdev
priority. Provide a new bootmeth_glob_allowed() function which checks if
a bootmeth is ready to use.

Fix a comment in bootflow_system() which is a test for global bootmeths.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-10-22 14:16:56 -06:00
Simon Glass
e52053c93c boot: Only run global bootmeths once each
Use the methods_done flags to make sure that each global bootmeth is
only used once. For now this has no effect, since they are all processed
at the start.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-10-22 14:16:56 -06:00
Simon Glass
8e31093dbc boot: Support rescanning the global bootmeths
Add the logic to scan through the global bootmeths for every new
bootdev, in preparation for allowing global bootmeths to select where in
the hunter ordering they go.

Use a new bootmeth_glob_allowed() function to check if a bootmeth is
allowed, ensuring that each can run at most once.

For now this has no actual effect, since the global bootmeths are
unconditionally processed at the start, with iter->methods_done being
updated to include all of them. Therefore when scanning again, no
unprocessed global bootmeths will be found.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-10-22 14:16:56 -06:00
Simon Glass
bef963cb75 boot: Keep track of which bootmeths have been used
Add a bitfield which tracks when bootmeths have been used. This will be
needed when global bootmeths can be used later in the iteration.

Fix a missing bootflow_free() while here.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-10-22 14:16:56 -06:00
Simon Glass
0fe6de0dc5 boot: Add a flag for whether there are global bootmeths
The current 'doing_global' refers to being in the state of processing
global bootmeths. Since global bootmeths are currently used once at the
start, it becomes false once the last global bootmeth has been used.

In preparation for allowing bootmeths to run at other points in the
bootstd interation, add a new 'have_global' flag which tracks whether
there are any global bootmeths in the method_order[] list. It is set up
when iteration starts. Unlike doing_global which resets back to false
after the global bootmeths have been handled, once have_global is set to
true, it remains true for the entire iteration process. This provides a
quick check as to whether global-bootmeth processing is needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-10-22 14:16:56 -06:00
Simon Glass
eca985905d boot: Update first_glob_method when dropping a bootmeth
For now we only support dropping non-global bootmeths from the
iteration. Update first_glob_method in that case and add a few checks
that things are correct.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-10-22 14:16:56 -06:00
Simon Glass
a2301201e3 boot: Add a new test for global bootmeths
These have different behaviour from normal bootmeths and we are about to
enhance it. So add a test and also an extra check in bootflow_iter()

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-10-22 14:16:56 -06:00
Simon Glass
396c9b5964 boot: Try all bootmeths on the final partition
At present, normally when one bootmeth fails on a partition, we move on
and try the next bootmeth. However, this was not the case for the final
partition due to a bug. Rework the logic so that all partitions are
treated the same.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-10-22 14:16:56 -06:00
Tom Rini
8bc918ed97 Merge patch series "Add support for dynamic MMU configuration"
Anshul Dalal <anshuld@ti.com> says:

In U-Boot, TI only provides a single memory map for all k3 platforms, this
does not scale for devices where atf and optee lie outside the range 0x80000000
- 0x80080000 and 0x9e780000 - 0xa0000000 respectively.

There are also issues for devices with < 2GiB of memory (eg am62SiP with 512MiB
of RAM) as the maximum size for the first DRAM bank is hardcoded to 2GiB in the
current memory map. Furthermore the second DRAM bank is mapped even for devices
that only have a single bank.

Therefore this patch set adds the required functionality to create the MMU table
at runtime based on the device-tree.

The patch set has been build tested on all effected platforms but boot-tested
only on TI's K3 EVMs, the beagleplay and phytec's phycore-am6* platforms.

The following effected boards have not been boot tested:
 - verdin-am62
 - iot2050

Link: https://lore.kernel.org/r/20251017131540.3636067-1-anshuld@ti.com
2025-10-22 12:23:48 -06:00
Anshul Dalal
342fd918b1 arm: mach-k3: reserve space for page table entries
With the memory map configuration being done dynamically, reserve extra
space during U-Boot relocation to ensure we have enough for the fixups.

Reviewed-by: Dhruva Gole <d-gole@ti.com>
Signed-off-by: Anshul Dalal <anshuld@ti.com>
2025-10-22 12:05:53 -06:00
Anshul Dalal
4f5285f0e6 mach-k3: add carveouts for TFA and optee
K3 platforms have reserved memory regions for TFA and OPTEE which should
be unmapped for U-Boot. While other "no-map" memory regions like the
memory pools for remote cores should not be unmapped to allow U-Boot to
load firmware during remoteproc.

Therefore this patch adds the necessary fdt fixups to properly set the
load address for TFA/OPTEE and unmaps both by mmu_unmap_reserved_mem.

Reviewed-by: Dhruva Gole <d-gole@ti.com>
Signed-off-by: Anshul Dalal <anshuld@ti.com>
Tested-by: Wadim Egorov <w.egorov@phytec.de>
2025-10-22 12:05:52 -06:00
Anshul Dalal
859f68ed2e mach-k3: add reserved memory fixups for next boot stage
The boot flow in K3 platforms requires the subsequent boot stages to be
aware of the memory reserved for previous boot binaries. In the regular
boot sequence of:

R5 SPL -> ATF -> OP-TEE -> A-core SPL -> U-Boot -> Kernel,

Both A-core SPL and U-Boot should be made aware of the memory reserved
for ATF and OP-TEE from their device-tree. Currently this information is
absent.

Therefore this patch adds the reserved-memory regions as part of
spl_perform_arch_fixups for the next stage's DT. This is called during
both R5 and A-core SPL which fixes up the DT for their respective next
stages: A-core SPL and U-Boot proper.

Reviewed-by: Dhruva Gole <d-gole@ti.com>
Signed-off-by: Anshul Dalal <anshuld@ti.com>
Tested-by: Wadim Egorov <w.egorov@phytec.de>
2025-10-22 12:05:52 -06:00
Anshul Dalal
16ffcff028 spl: split spl_board_fixups to arch/board specific
The current spl_board_fixups API allows for modification of spl_image
before the SPL jumps to it. This can be used to modify the DT for the
next boot stage, however the current API only allows either the machine
arch or the board to use it.

This limits the utility of the API as there might be certain fixups that
should be applied to all boards sharing the same machine architecture
with others being board specific.

For TI's K3 specifically, this prevents us from performing architecture
level fixups since a lot of TI boards are already making use of the
spl_board_fixups API.

Therefore this patch splits the API into two to allow both board and the
architecture specific fixups. The order is kept as arch then board to
give board specific fixups the precedence.

Reviewed-by: Dhruva Gole <d-gole@ti.com>
Signed-off-by: Anshul Dalal <anshuld@ti.com>
Tested-by: Wadim Egorov <w.egorov@phytec.de>
2025-10-22 12:05:52 -06:00
Anshul Dalal
856480eef0 arm: armv8: mmu: add mmu_unmap_reserved_mem
For armv8, U-Boot uses a static map defined as 'mem_map' for configuring
the MMU's page tables, done by mmu_setup.

Though this works well for simpler platforms, it makes creating runtime
carveouts by modifying the static array at runtime exceedingly complex
like in mach-snapdragon/board.c.

Creation of such carveouts are much better handled by APIs such as
mmu_change_region_attr once the page tables are configured. Usually such
carveouts are configured via the device-tree's reserved-memory node
which provides the address and size for the carveout.

Therefore this patch adds mmu_unmap_reserved_mem which acts as a wrapper
over mmu_change_region_attr, helping unmap a reserved-memory region.

Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Anshul Dalal <anshuld@ti.com>
Tested-by: Wadim Egorov <w.egorov@phytec.de>
2025-10-22 12:05:52 -06:00
Anshul Dalal
f1c694b8fd mach-k3: map all banks using mem_map_from_dram_banks
The static memory map for K3 (k3_mem_map) only maps the first DRAM bank
and therefore doesn't scale for platforms with multiple memory banks.

This patch modifies enable_caches to add mem_map_from_dram_banks which
appends all the memory banks to k3_mem_map before calling mmu_setup.

Signed-off-by: Anshul Dalal <anshuld@ti.com>
Tested-by: Wadim Egorov <w.egorov@phytec.de>
2025-10-22 12:05:52 -06:00
Anshul Dalal
fe2647f2a0 arm: armv8: mmu: add mem_map_from_dram_banks
For armv8, U-Boot uses a static map defined as 'mem_map' for configuring
the MMU as part of mmu_setup.

But since the exact configuration of memory banks might not be known at
build time, many platforms such as imx9, versal2 etc. utilize
gd->bd->bi_dram to configure the static map at runtime.

Therefore this patch adds a new API mem_map_from_dram_banks that
modifies the static map in a similar way. Allowing the caller to map all
dram banks by just passing the index to last entry in their mem_map and
it's length.

Reviewed-by: Dhruva Gole <d-gole@ti.com>
Signed-off-by: Anshul Dalal <anshuld@ti.com>
Tested-by: Wadim Egorov <w.egorov@phytec.de>
2025-10-22 12:05:52 -06:00
Anshul Dalal
9ebdbbc43e arm: armv8: invalidate dcache entries on dcache_enable
In dcache_enable, currently the dcache entries are only invalidated when
the MMU is not enabled. This causes issues when dcache_enable is called
with the MMU already configured, in such cases the existing dcache
entries are not flushed which might result in un-expected behavior.

This patch invalidates the cache entries on every call of dcache_enable
before enabling dcache (by setting CR_C). This makes dcache_enable
behave similar to icache_enable as well.

Reviewed-by: Dhruva Gole <d-gole@ti.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Anshul Dalal <anshuld@ti.com>
Tested-by: Wadim Egorov <w.egorov@phytec.de>
2025-10-22 12:05:52 -06:00
Anshul Dalal
567a683e8c arm: armv8: mmu: export mmu_setup
The mmu_setup function configures the page tables based on the board
supplied mem_map struct array. It is called implicitly as part of
dcache_enable but this limits us to only be able to use APIs such as
mmu_change_region_attr only after caches are enabled.

This might lead to speculative accesses before we can unmap a region
that is marked as cacheable in the static memory map.

Therefore this patch exports the mmu_setup function in mmu.h allowing
users to have more control over when the mmu is configured.

For K3 specifically this allows for the following configuration sequence
as part of enable_caches:

static mem_map fixups (TODO) -> mmu_setup -> carveouts using
mmu_change_region_attr (TODO) -> icache/dcache enable

Reviewed-by: Dhruva Gole <d-gole@ti.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Anshul Dalal <anshuld@ti.com>
Tested-by: Wadim Egorov <w.egorov@phytec.de>
2025-10-22 12:05:52 -06:00
Anshul Dalal
e55e57d240 mach-k3: use custom enable_cache
U-Boot's provided enable_caches enforces the following sequence:
icache_enable -> mmu_setup (as part of dcache_enable) -> dcache_enable

Whereas for K3 devices, we would like to add entries to the provided
static array (k3_mem_map) as per gd->bd->bi_dram and then call mmu_setup
to configure the MMU but also create carveouts for TFA/TEE before we
enable caches to prevent speculative accesses to the region. Thus the
following desired sequence:

add dram banks -> mmu_setup -> carveout TFA/TEE -> icache/dcache enable

Therefore this patch adds K3's own implementation of enable_cache for
ARM64, allowing for greater control over the cache enablement sequence.

Reviewed-by: Dhruva Gole <d-gole@ti.com>
Signed-off-by: Anshul Dalal <anshuld@ti.com>
Tested-by: Wadim Egorov <w.egorov@phytec.de>
2025-10-22 12:05:52 -06:00
Anshul Dalal
4673c8dcb4 mach-k3: use minimal memory map for all K3
The K3 family of SoCs encompasses a wide variety of devices with varying
DDR configurations and memory carveout requirements, the current static
memory map provides basic support for TI EVMs but does not scale well
for newer platforms (such as AM62SiP with 512MiB of RAM).

Therefore this patch replaces the existing memory map with a minimal
one, that could be more easily modified at runtime.

Reviewed-by: Dhruva Gole <d-gole@ti.com>
Signed-off-by: Anshul Dalal <anshuld@ti.com>
Tested-by: Wadim Egorov <w.egorov@phytec.de>
2025-10-22 12:05:52 -06:00
Tom Rini
29a96acaa3 Merge tag 'net-20251022' of https://source.denx.de/u-boot/custodians/u-boot-net
Pull request net-20251022

net:
- airoha: improvements
- Tighten a few more driver dependencies
- designware: fix bitbang init error
- phy: Make driver overloading get_phy_id depend on !COMPILE_TEST
- phy: add paged PHY register accessors
- make dhcp_run() common for NET and NET_LWIP
- dwc_eth_ops: Correct check for FDT_64BIT
- mediatek: mt7988: various fixup + MDIO detach
- phy: aquantia: switch to use phy_get_ofnode(), fix bindings typo

net-legacy:
- bootp: Prevent buffer overflow to avoid leaking the RAM content
- tftp: make TFTP ports unconditionally configurable

misc:
- uthreads: Make use of CONFIG_IS_ENABLED consistently
2025-10-22 09:07:56 -06:00
Tom Rini
b21ba014a9 Merge tag 'u-boot-at91-2026.01-a' of https://source.denx.de/u-boot/custodians/u-boot-at91
First set of u-boot-at91 features for the 2026.01 cycle:

This small fixes set includes a change on clocks register value and a
fix for the sam9x60ek default timer.
2025-10-22 09:06:11 -06:00
Jim Liu
ed6ec8d1ca net: designware: fix bitbang init error
The Synchronous Abort and reset errors occurred due
to incorrect parameter passing during initialization.

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
[jf: add missing #if IS_ENABLED(CONFIG_BITBANGMII)]
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
2025-10-22 14:28:33 +02:00
Tom Rini
85c2c2c517 net: phy: Make driver overloading get_phy_id depend on !COMPILE_TEST
With commit 597fe041a8 ("net/phy: enable get_phy_id redefinable") we
made get_phy_id a public but weak function, so that PHY drivers that had
required non-standard ways of getting the PHY ID could be supported.
However, overloading a weak function multiple times is (rightly) a link
error. At this point, we have two PHYs which make use of this feature,
so make both of them only available when COMPILE_TEST is unset, as part
of being able to support "allyesconfig" in the future.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-10-22 14:28:33 +02:00
Paul HENRYS
81e5708cc2 net: bootp: Prevent buffer overflow to avoid leaking the RAM content
CVE-2024-42040 describes a possible buffer overflow when calling
bootp_process_vendor() in bootp_handler() since the total length
of the packet is passed to bootp_process_vendor() without being
reduced to len-(offsetof(struct bootp_hdr,bp_vend)+4).

The packet length is also checked against its minimum size to avoid
reading data from struct bootp_hdr outside of the packet length.

Signed-off-by: Paul HENRYS <paul.henrys_ext@softathome.com>
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2025-10-22 14:28:33 +02:00
Lucien.Jheng
34369d34e4 net: phy: add paged PHY register accessors
Synchronize paged PHY helpers with Linux v6.17.

Add support for PHY devices that use paged register access by
implementing the following functions:
- phy_save_page(): Save current page number
- phy_select_page(): Switch to a specific page and return previous page
- phy_restore_page(): Restore previously saved page

Also adds read_page and write_page callbacks to the phy_driver
structure to enable driver-specific page handling.

These helpers allow safe access to paged PHY registers by ensuring
proper page selection and restoration,
even in error conditions, which will be used by the Airoha PHY driver.

Signed-off-by: Lucien.Jheng <lucienzx159@gmail.com>
2025-10-22 14:28:33 +02:00
Mikhail Kshevetskiy
648d2ade0b net: airoha: increase the number of rx network buffers
According to commit 997786bbf4 ("drivers/net/airoha_eth: fix stalling
in package receiving") the minimal possible value of SYS_RX_ETH_BUFFER
is 4. Unfortunately it's too small for reliable ping.

Observations shows that SYS_RX_ETH_BUFFER must be at least 8.

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
2025-10-22 14:28:33 +02:00
Mikhail Kshevetskiy
ec12793719 net: airoha: simplify rx/free packet logic a bit
The commit 997786bbf4 ("drivers/net/airoha_eth: fix stalling in package
receiving") can be improved. Instead of returning previous descriptor
it's possible:
 * do nothing in even descriptor case
 * return 2 descriptor to the queue (current and previous) in the odd
   descriptor case.

This patch:
 * implements above approach
 * remove logic not required within new approach
 * adds note that PKTBUFSRX must be even and larger than 7
   for reliable driver operations

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
2025-10-22 14:28:33 +02:00
Jerome Forissier
4b8e785851 net: make dhcp_run() common for NET and NET_LWIP
There are currently two implementations of dhcp_run(): one in cmd/net.c
for NET and one in net/lwip/dhcp.c for NET_LWIP. There is no
justification for that. Therefore, move the NET version into
net/net-common.c to be used by both stacks, and drop the NET_LWIP
version which by the way does not look totally correct.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Suggested-by: Tom Rini <trini@konsulko.com>
Acked-by: Benjamin Hahn <B.Hahn@phytec.de>
2025-10-22 14:28:33 +02:00
Christian Marangi
b24268d151 net: mediatek: move MT7531 MMIO MDIO to dedicated driver
In preparation for support of MDIO on AN7581, move the MT7531 MMIO logic
to a dedicated driver and permit usage of the mdio read/write function
to the mtk_eth driver.

This only affect MT7988 that can use MMIO operation to access the Switch
register. The MT7988 code is updated to make use of the external driver.

This permits Airoha driver to make use of DM_MDIO to bind for the MT7531
driver that have the same exact register.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2025-10-22 11:16:10 +02:00
Christian Marangi
ca4264db44 net: mediatek: mt7988: free allocated MDIO bus on cleanup
Correctly free the MDIO Bus on calling cleanup function. While at it
also fix a copy-paste error and rename the cleanup function name to the
more specific name.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2025-10-22 11:16:10 +02:00
Christian Marangi
85f3d070e2 net: mediatek: mt7988: restore PHY page on PHY setting exit
On exiting the phy_setting function for MT7988, the PHY page is never
restored to Page 0. This can cause all kind of problem with reading the
status of the PHY at runtime.

Correctly restore PHY page on exiting the PHY setting function.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2025-10-22 11:16:10 +02:00
Christian Marangi
9b2e1079e7 net: mediatek: mt7531/7988: fix broken PHY turn ON/OFF
The PHY for MT7531/MT7988 are never actully turned ON/OFF for the
affected PHY as we are read/writing to the wrong PHY address.

This is caused by the fact that we use the MT753X_PHY_ADDR macro 2
times offsetting the address multiple times.

One in the _setup() function and one in the mt7531_mii_read/write.

Drop the additional usage of MT753X_PHY_ADDR in setup() to correctly
set the PHY.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2025-10-22 11:16:10 +02:00
Beiyan Yun
efaadc02b7 doc: bindings: fix aquantia-phy.txt typo
Fix typo: "weays" -> "ways"

Signed-off-by: Beiyan Yun <root@infi.wang>
2025-10-22 11:16:10 +02:00
Beiyan Yun
83633e5774 net: phy: aquantia: switch to use phy_get_ofnode()
Use PHY API phy_get_ofnode() helper to get PHY DT node.

Signed-off-by: Beiyan Yun <root@infi.wang>
2025-10-22 11:16:09 +02:00
Tom Rini
772703b77e net: Tighten more driver dependencies
In this case, the mediatek network drivers cannot build outside of
ARCH_MEDIATEK or ARCH_MTMIPS, and so express this requirement in Kconfig
as well. In the case of DWC_ETH_XGMAC / DWC_ETH_XGMAC_SOCFPGA, the file
controlled by the DWC_ETH_XGMAC option references a socfpga-specific
array defined in the file controlled by DWC_ETH_XGMAC_SOCFPGA. Rework
these options in Kconfig to handle this dependency.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-10-22 11:16:09 +02:00
Tom Rini
99707a0baa net: Remove BOOTP_VENDOREX support
It has been over a decade since we had a platform that implemented the
bootp vendor extension support hook. Remove this option due to lack of
use.

Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
2025-10-22 11:16:09 +02:00
Tom Rini
f822046037 net: Add SYS_FAULT_MII_ADDR to Kconfig
The support found under SYS_FAULT_ECHO_LINK_DOWN requires that the
SYS_FAULT_MII_ADDR symbol also be set. This wasn't previously found in
Kconfig, so add it now.

Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
2025-10-22 11:16:09 +02:00
Tom Rini
4cc1fe3f56 arm: socfpga: Tighten a few more driver dependencies
Some drivers which depend on SoCFPGA specific headers had not had
appropriate dependencies list in Kconfig. Add ARCH_SOCFPGA or
TARGET_SOCFPGA_SOC64 where appropriate.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-10-22 11:09:24 +02:00
Tom Rini
efe1d6303f uthreads: Make use of CONFIG_IS_ENABLED consistently
We do not yet support UTHREADS in xPL phases. However, we have the need
to dummy out certain functions so that xPL can build when full U-Boot
has UTHREADS enabled. Update the few places that need to use
CONFIG_IS_ENABLED so that we have the correct dummy in xPL.

Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
2025-10-22 11:09:24 +02:00
Alvin Šipraga
caa2ad6f8c tftp: make TFTP ports unconditionally configurable
A few lines of code being guarded by the CONFIG_TFTP_PORT option seems
an unnecessary restriction on the TFTP support provided by a vanilla
U-Boot image. In cases where the TFTP server cannot run as superuser -
and hence cannot run on the well-known port 69 - this quirk incurs a
full reconfiguration and rebuild of the bootloader only in order to
select the appropriate destination port.

Remove the CONFIG_TFTP_PORT option entirely and make the tftpdstp and
tftpsrcp variables always have an effect. Their being unset will mean
that U-Boot behaves the same as if CONFIG_TFTP_PORT was unset. Update
the documentation accordingly. And fix up the single board which was
originally enabling this option.

Signed-off-by: Alvin Šipraga <alvin@pqrs.dk>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
2025-10-22 11:09:24 +02:00
Chen-Yu Tsai
b27705b909 .mailmap: update email address for Chen-Yu Tsai
The email forwarder I'm using has run into severe problems with Gmail
lately. Switch over to my kernel.org address.

Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2025-10-21 16:07:49 -06:00
Jasper Orschulko
813a0df27a env: Invert gd->env_valid for env_mmc_save
The A/B update strategy of the env's has a gap in the first 2 calls of saveenv.
The env's are stored twice on the first memory area if:
gd->env_valid == ENV_INVALID.

u-boot=> saveenv
Saving Environment to MMC... Writing to MMC(1)... OK
u-boot=> saveenv
Saving Environment to MMC... Writing to MMC(1)... OK  <-- !!!
u-boot=> saveenv
Saving Environment to MMC... Writing to redundant MMC(1)... OK
u-boot=> saveenv
Saving Environment to MMC... Writing to MMC(1)... OK

This is the same issue as resolved in commit e589d5822c ("env: spi:
Fix gd->env_valid for the first write")

Signed-off-by: Michael Glembotzki <Michael.Glembotzki@iris-sensing.com>
Signed-off-by: Jasper Orschulko <jasper@fancydomain.eu>
Signed-off-by: Michael Heimpold <mhei@heimpold.de>
[trini: Amend the commit message]
---
Changes in v2:
- Rebase to current master
- Amend the commit message to reference the SPI version of this fix,
  which had significant follow-up discussion.
2025-10-21 13:18:46 -06:00
Tom Rini
0f865ab5d6 spl: Restore args file being default in falcon mode
When falcon mode is enabled and SPL_OS_BOOT_SECURE is not enabled,
restore the previous default behavior of having an args file be
expected. Platforms which are using a FIT image here and do not need
this can update at their convenience to disable this option now.

Fixes: b1a3ed0688 ("spl: make args file optional in falcon mode")
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-10-20 13:55:37 -06:00
Tom Rini
7674ac9c82 Merge patch series "Add support for secure falcon mode: disable args file"
Anshul Dalal <anshuld@ti.com> says:

Continuing from the last series[1], this patch series addresses the requirement
to disable the args file in falcon mode.

The args file is used in falcon mode for loading the device-tree for the kernel.
However in secure falcon mode, the expected payload is a FIT containing a signed
device-tree and kernel image. Thus removing the need to load the extra args
file in the first place. Also, loading the extra file without any authentication
mechanism exposes an attack vector and should therefore be disabled to keep the
boot secure.

This patch set builds on the last few to first optionally allow for loading the
args file in non-secure falcon boot flow [1/3] and then disable them altogether
in the next patch [2/3] for secure falcon mode.

[1]: https://lore.kernel.org/u-boot/20251006101057.4172248-1-anshuld@ti.com/
Link: https://lore.kernel.org/r/20251009115846.897186-1-anshuld@ti.com
2025-10-20 11:54:43 -06:00
Anshul Dalal
f851171e14 spl: set fdt address as spl_image arg in falcon mode
The arg field of `struct spl_image_info` is used by jump_to_image_linux
as the argument for the kernel in falcon mode.

Since commit 601cebc29d ("cmd: spl: Remove ATAG support from this
command"), fdt is the only valid argument for kernel in falcon mode.

However fdt was only being set as the argument in nor and xip boot
modes, this patch fixes it for all boot modes and removes the now
redundant code from spl_nor and spl_xip.

Signed-off-by: Anshul Dalal <anshuld@ti.com>
2025-10-20 11:54:35 -06:00
Anshul Dalal
82e04e768f spl: prevent loading args file in secure falcon mode
The expected payload for the SPL in secure falcon mode is a fitImage
that contains the kernel image and the DT. This removes the need to load
an additional args file, which exposes an additional attack vector since
it can not be verified.

Therefore this patch disables loading of the arg file when
SPL_OS_BOOT_SECURE is set.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Anshul Dalal <anshuld@ti.com>
2025-10-20 11:54:33 -06:00
Anshul Dalal
b1a3ed0688 spl: make args file optional in falcon mode
Falcon mode loads a kernel file and an args file which is the
device-tree. However in the case of kernel file being a FIT that
contains the device-tree within it, loading the args file is not
required.

Therefore, this patch introduces a new SPL_OS_BOOT_ARGS config options
that allows us to enable or disable loading of the args file in falcon
mode.

Signed-off-by: Anshul Dalal <anshuld@ti.com>
2025-10-20 11:54:29 -06:00
Tom Rini
d5996409ce Merge patch series "Add support for secure falcon mode: disable fallback"
Anshul Dalal <anshuld@ti.com> says:

Continuing from the last series[1], this patch series addresses the requirement of
allowing no fallbacks in secure falcon mode.

To do this in a clean way, all the falcon mode logic for each boot media was
refactored to a corresponding *_load_image_os function whereas the regular
boot is implemented in *_load_image, this allows us to easily return early in
case the *_load_image_os function fails with secure mode enabled.

The series also introduces the new SPL_OS_BOOT_SECURE config symbol which
enables secure falcon boot flow.

The generic flow after the patch series looks as follows:

	static int spl_<bootmedia>_load_image(...) {
		if (CONFIG_IS_ENABLED(OS_BOOT)) {

			ret = spl_<bootmedia>_load_image_os(...);

			puts("Failcon mode failed\n");
			if (CONFIG_IS_ENABLED(OS_BOOT_SECURE)) {
				puts("no fallback allowed!\n");
				return ret;
			}

			puts("Falling back to U-Boot\n");
		}

		/* Regular boot flow */
	}

[1]: https://lore.kernel.org/u-boot/20250923124639.667718-1-anshuld@ti.com/
Link: https://lore.kernel.org/r/20251017193318.4124997-1-anshuld@ti.com
2025-10-20 10:17:54 -06:00
Anshul Dalal
d3ac0d60da spl: falcon: disable fallback to U-Boot on failure
Instead of falling back to the standard U-Boot boot flow, we should just
halt boot if the expected boot flow in falcon mode fails.

This prevents a malicious actor from accessing U-Boot proper if they can
cause a boot failure on falcon mode.

Signed-off-by: Anshul Dalal <anshuld@ti.com>
2025-10-20 10:14:00 -06:00
Anshul Dalal
d9a50f8f14 spl: nand: refactor spl_nand_load_image for falcon mode
This patch moves the falcon mode handling logic out of
spl_ubi_load_image to spl_ubi_load_image_os, this allows for cleaner
handling for fallback to U-Boot in case falcon mode fails.

Signed-off-by: Anshul Dalal <anshuld@ti.com>
2025-10-20 10:14:00 -06:00
Anshul Dalal
b5446fd478 spl: nor: refactor spl_nor_load_image for falcon mode
This patch moves the falcon mode handling logic out of
spl_nor_load_image to spl_nor_load_image_os, this allows for cleaner
handling for fallback to U-Boot in case falcon mode fails.

Signed-off-by: Anshul Dalal <anshuld@ti.com>
2025-10-20 10:14:00 -06:00
Anshul Dalal
a6a801fcd6 spl: spi: refactor spl_spi_load_image for falcon mode
This patch moves the falcon mode handling logic out of
spl_spi_load_image to spl_spi_load_image_os, this allows for cleaner
handling for fallback to U-Boot in case falcon mode fails.

Signed-off-by: Anshul Dalal <anshuld@ti.com>
2025-10-20 10:14:00 -06:00
Anshul Dalal
81951cfffd spl: ubi: refactor spl_ubi_load_image for falcon mode
This patch moves the falcon mode handling logic out of
spl_ubi_load_image to spl_ubi_load_image_os, this allows for cleaner
handling for fallback to U-Boot in case falcon mode fails.

Signed-off-by: Anshul Dalal <anshuld@ti.com>
2025-10-20 10:14:00 -06:00
Anshul Dalal
2909b3bff0 spl: mmc: split spl_mmc_do_fs_boot into regular/os_boot
Currently the logic to handle falcon mode as well as the regular boot is
inside spl_mmc_do_fs_boot, this prevents us from cleanly extending
falcon mode functionality like toggleable fallback to U-Boot proper.

Therefore this patch splits the logic into spl_mmc_fs_load and
spl_mmc_fs_load_os to handle the regular boot and falcon mode use case.

Signed-off-by: Anshul Dalal <anshuld@ti.com>
2025-10-20 10:14:00 -06:00
Anshul Dalal
a3e67a9645 spl: Kconfig: add SPL_OS_BOOT_SECURE config symbol
This patch adds the new SPL_OS_BOOT_SECURE symbol that enables secure
boot flow in falcon mode. This symbol can be used to disable certain
inherently insecure options during falcon boot.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Anshul Dalal <anshuld@ti.com>
2025-10-20 10:14:00 -06:00
Michal Simek
aabda5407f Revert "spi: cadence-qspi: Remove cdns, is-dma property handling"
This reverts commit a040578d82.

Based on feedback other SOCs (for example Star64) are using driver in non
DMA mode which is causing issues that's why revert this patch.
cdns,is-dma should be removed differently.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Reported-by: E Shattow <e@freeshell.de>
2025-10-20 08:28:00 -06:00
Tom Rini
45e02b3fc6 Merge tag 'efi-2026-01-rc1' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request efi-2026-01-rc1

CI:

  * https://source.denx.de/u-boot/custodians/u-boot-efi/-/pipelines/27944

Documentation:

 * samsung: Extend E850-96 documentation to be comprehensive
 * environment: fix links to Linux kernel documentation
 * sandbox: fix typos
 * document dmareset command
 * ti: j722s_evm: drop outdated boot note

UEFI:

 * Prevent leak of memory from tmp_files
 * Correctly check if the HTTP protocol is found
 * Use ESRT_FW_TYPE_SYSTEMFIRMWARE instead of ESRT_FW_TYPE_UNKNOWN
 * dbginfodump: use guid definition

Others:

 * lib/uuid: add support for efi debug image info table guid
2025-10-20 08:27:19 -06:00
Peter Robinson
dbac24b713 doc: ti: j722s_evm: drop outdated boot note
The j722s_evm support is now largely complete and is certainly
not limited to UART boot so drop the confusing note from the docs.

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
2025-10-18 12:01:16 +02:00
Vincent Stehlé
841a68788b lib: uuid: add efi debug image info table guid
Add the EFI Debug Image Info Table GUID to the translation table used by
uuid_guid_get_str().

This allows to print a human readable table name with `efidebug tables'
instead of "(unknown)".

Signed-off-by: Vincent Stehlé <vincent.stehle@arm.com>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2025-10-18 12:00:16 +02:00
Vincent Stehlé
ac59ac1b7c efi_loader: dbginfodump: use guid definition
Use the Debug Image Info Table GUID definition from efi_api.h instead or
redefining it locally.

Signed-off-by: Vincent Stehlé <vincent.stehle@arm.com>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Cc: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2025-10-18 11:59:53 +02:00
Mattia Narducci
3e865cfffc doc: environment: fix links to Linux kernel documentation
Architecture-specific documentation in the Linux kernel was moved to
the arch/ subdirectory.

Signed-off-by: Mattia Narducci <mattianarducci1@gmail.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2025-10-18 11:54:37 +02:00
Ilias Apalodimas
186b2d2407 efi_loader: Use ESRT_FW_TYPE_SYSTEMFIRMWARE instead of ESRT_FW_TYPE_UNKNOWN
We currently set the firmware image type to ESRT_FW_TYPE_UNKNOWN.

The spec defines the following:
ESRT_FW_TYPE_UNKNOWN 0x00000000
ESRT_FW_TYPE_SYSTEMFIRMWARE 0x00000001
ESRT_FW_TYPE_DEVICEFIRMWARE 0x00000002
ESRT_FW_TYPE_UEFIDRIVER 0x00000003

Since we don't support updating DEVICEFIRMWARE or UEFIDRIVER types,
let's switch over to SYSTEMFIRMWARE which seems more appropriate.

Suggested-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2025-10-18 11:52:28 +02:00
Lukas Zirpel
a7762037d2 doc: sandbox: fix typos
Fix two typos in the sandbox docs.

Signed-off-by: Lukas Zirpel <lukas@zirpel.de>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2025-10-18 11:50:08 +02:00
Brian Sune
38f60e1621 cmd/dma: documentation
This explains how
to use the new U-Boot command 'dmareset'.

Signed-off-by: Brian Sune <briansune@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2025-10-18 11:48:58 +02:00
Heinrich Schuchardt
163f9d04fb efi_loader: correctly check if the HTTP protocol is found
In function efi_http_service_binding_destroy_child() phandler is created as
as a local variable. If efi_search_protocol() fails, phandler will hold a
random value from the stack. Even it is not zero, we must not use it.

If efi_search_protocol() succeeds, the pointer has already be dereferenced,
so checking against NULL makes not sense here.

If ChildHandle is not a valid UEFI handle, we must return
EFI_INVALID_PARAMETER.

Use a single location for EFI_EXIT().

Addresses-Coverity-ID: CID 531974 (Unchecked return value)
Fixes: 5753dc3f65 ("efi_loader: Prevent dereference of uninitialised variable")
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2025-10-18 11:41:32 +02:00
Andrew Goodbody
11a64138f5 efi_loader: Prevent leak of memory from tmp_files
After the malloc of tmp_files and before its value is recorded an early
exit will need to free tmp_files to prevent leaking that memory.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2025-10-18 11:41:31 +02:00
Sam Protsenko
bd87ec920d doc: samsung: Extend E850-96 documentation to be comprehensive
Add more bootloading details for E850-96 board. New sections cover next
topics:

  - Hardware configuration of the boot device
  - Flashing and updating the software (multiple methods)
  - Booting with Standard Boot (multiple methods)
  - EFI System Partition structure for E850-96
  - Loadable firmware (LDFW) note
  - Ethernet and USB Host Support

That documents all recently enabled U-Boot features for E850-96, which
can hopefully make U-Boot more useful for the users and developers of
this platform.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
2025-10-18 11:41:31 +02:00
Andrew Goodbody
a58089ad2e fs: semihosting: Use correct variable for error check
After calling a function that can return an error, the test to detect
that error should use the return value not a different variable. Fix it.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Sean Anderson <sean.anderson@seco.com>
Fixes: f676b45151 ("fs: Add semihosting filesystem")
2025-10-17 18:07:20 -06:00
Tom Rini
64a4645c4e Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sh
SH HSCIF FIFO fixes, R-Car V4H/V4M DT corrections, R-Car V4H Sparrow
Hawk PCIe shutdown support before booting Linux.
2025-10-17 18:07:06 -06:00
Nguyen Tran
b9efaf6729 ARM: dts: renesas: Disable RPC driver on R8A779H0 V4M Gray Hawk board
As requirement of CR side, QSPI Flash usage via RPC driver shall
be disabled and leaving the control of this module to CR side.
Perform DT modification to disable the RPC SPI.

Signed-off-by: Nguyen Tran <nguyen.tran.pz@bp.renesas.com>
Reviewed-by: Khanh Le <khanh.le.xr@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Do not modify defconfig, modify the DT instead, this way
        the RPC SPI can be enabled without recompiling the U-Boot
        itself. Update commit message accordingly.]
2025-10-18 00:19:03 +02:00
Marek Vasut
81e050250c ARM: dts: renesas: Reinstate R8A779H0 V4M U-Boot DTs
Commit 63da3a795e ("ARM: dts: renesas: Drop R8A779H0 V4M DTs with OF_UPSTREAM counterparts")
removed unnecessary V4H DTs from arch/arm/dts , but in the process
also incorrectly dropped the -u-boot.dtsi U-Boot extras. Reinstate
those extras.

Due to DT file name change for the R8A779H0 V4M Gray Hawk, update
the r8a779h0-gray-hawk-u-boot.dtsi filename to newly matching
r8a779h0-gray-hawk-single-u-boot.dtsi .

Align r8a779h0-u-boot.dtsi with clean up commits
1487c34efa ("arm64: dts: renesas: Deduplicate extalr_clk bootph-all")
dd8f57ed2f ("ARM: dts: renesas: Drop most of bootph-* tags")

Fixes: 63da3a795e ("ARM: dts: renesas: Drop R8A779H0 V4M DTs with OF_UPSTREAM counterparts")
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-10-18 00:19:03 +02:00
Marek Vasut
1d94364c7f ARM: dts: renesas: Disable R8A779G0 V4H White Hawk RPC SPI DT node again
Commit 3faeb78378 ("ARM: dts: renesas: Minimize R8A779G0 V4H RPC SPI DT node")
incorrectly re-enabled the RPC SPI DT node, which was disabled in commit
13bdb6a269 ("ARM: dts: renesas: Disable RPC driver on R8A779G0 V4H White Hawk board")
Reinstate the disablement.

Fixes: 3faeb78378 ("ARM: dts: renesas: Minimize R8A779G0 V4H RPC SPI DT node")
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-10-18 00:19:03 +02:00
Marek Vasut
92b779cd9f serial: sh: Handle HSCIF RX FIFO overflow
The HSCIF RX FIFO may overflow when data are streaming from remote end
into the HSCIF while U-Boot is still starting up. In that case, HSFSR
bit RDF is set, but HSFDR field R is zero. This confuses .tstc callback
into considering RX FIFO to be empty, which leads to .getc to be never
invoked, even when user attempts to pass more input onto the command
line.

Fix this by considering the RDF flag in serial_rx_fifo_level(), which
is called from .tstc in case of no errors. If RDF flag is set, trigger
the .getc callback and let it clear the RX FIFO.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-10-17 21:53:52 +02:00
Marek Vasut
a1a898588c arm64: renesas: r8a779g3: Reset PCIe before next stage on Retronix R-Car V4H Sparrow Hawk
Fully reset both PCIe controllers before booting the next stage on
Retronix R-Car V4H Sparrow Hawk board. This is necessary especially
in case U-Boot brought up the PCIe controllers, at which point the
next stage might be confused by the state of the PCIe controller.
The reset has to happen this late and not in the PCIe controller
driver, because the SRCR11 bits seem to affect both controllers.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-10-17 21:53:52 +02:00
Marek Vasut
2b634a80b5 pci: pcie-rcar-gen4: Shut down controller on link down and remove
In case the link is down, or the controller driver is removed before
booting the next stage, shut down the PCIe link, put both the remote
PCIe device and the controller into reset, and disable clock. This
way, the hardware is not left active when not in use.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-10-17 21:53:52 +02:00
Yegor Yefremov
5340dc6fe7 .gitignore: ignore more image files
This expression covers various images files like, for example:

mkimage-out.spl-stm32.mkimage
mkimage.spl-stm32.mkimage

Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2025-10-17 08:59:37 -06:00
Tom Rini
a46a2e2227 Merge patch series "led: fixes"
Patrice Chotard <patrice.chotard@foss.st.com> says:

  - Update led_get_by_label()
  - Fix led Kconfig

Link: https://lore.kernel.org/r/20251009130844.11703-1-patrice.chotard@foss.st.com
2025-10-17 08:58:10 -06:00
Patrice Chotard
827ccb84ff led: Add LED dependency for LED_ACTIVITY and LED_BOOT
Add LED dependency for LED_ACTIVITY and LED_BOOT.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Yegor Yefremov <yegorslists@googlemail.com>
Reviewed-by: Yegor Yefremov <yegorslists@googlemail.com>
2025-10-17 08:57:45 -06:00
Patrice Chotard
d9915318b5 led: Update led_get_by_label()
During led_init() execution, led_get_label() returns either the label
property (which is an obsolete property [1]) or the LED's node name.
It can't be the function name as dev parameter is NULL.

Later, during led_post_bind() execution, for the same LED, the attributed
label by led_get_label() can be the function name, as led_get_label()
dev's parameter is set.

During call sequence led_boot_on() => led_boot_get() => led_get_by_label()
with label given in parameter (priv->boot_led_label which is either the
label or node's name set previously in led_init()) can be different to
to uc_plat->label and returns -ENODEV.

Update led_get_by_label() to allow to retrieve LED also by its node name.

[1] https://www.kernel.org/doc/Documentation/devicetree/bindings/leds/common.yaml

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Yegor Yefremov <yegorslists@googlemail.com>
2025-10-17 08:57:45 -06:00
Dharma Balasubiramani
68b1f2aeb8 ARM: dts: sam9x60ek: select PIT as tick-timer
U-Boot currently enables the UPLL during boot, which triggers a udelay()
call that depends on the system tick timer. Since no explicit tick source
is defined in the device tree, boot stalls on this board.

Define the "tick-timer" property under /chosen and point it to the PIT
node, ensuring U-Boot uses the PIT as the tick source.

Fixes: ac30d90f33 ("clk: Ensure the parent clocks are enabled while reparenting")
Signed-off-by: Dharma Balasubiramani <dharma.b@microchip.com>
2025-10-17 12:34:02 +03:00
Manikandan Muralidharan
7885969610 clk: at91: remove default values for PMC_PLL_ACR
Remove default values for PMC PLL Analog Control Register(ACR) as the
values are specific for each SoC and PLL, so load them from PLL
characteristics structure

Signed-off-by: Manikandan Muralidharan <manikandan.m@microchip.com>
Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
2025-10-17 12:33:46 +03:00
Manikandan Muralidharan
57d88e78a8 clk: at91: Add ACR in all PLL setting.
Add ACR in all PLL setting. Add correct ACR value for each PLL used in
different SoCs.

Signed-off-by: Manikandan Muralidharan <manikandan.m@microchip.com>
Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
2025-10-17 12:32:28 +03:00
Tom Rini
bf1d8c1fec test/py: Update to a newer pytest release
Our pytest package was pinned to a release from 2021. The minimum
compatible with labgrid v25.0.x is pytest 7.0.0. Update to the current
relase which is currently 8.4.2

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-10-16 18:03:27 -06:00
Heinrich Schuchardt
ede1186f20 test: uninstall PK after secboot tests
The EFI secure boot tests install a security data base.
Other EFI tests assume that secure boot is not enabled.
Add the missing tear-down at the end of each secboot test sequence.

Reported-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Tested-by: Tom Rini <trini@konsulko.com>
2025-10-16 18:02:19 -06:00
Heinrich Schuchardt
7e65d29b66 virito: blk: fix logic to determine block sizes
With commit c85b8071e7 ("virtio: blk: support block sizes exceeding 512
bytes") logic was added to detect the VIRTIO_BLK_F_BLK_SIZE capability and
to copy the block size reported by QEMU to the block device descriptor.

The logical block size can be set when invoking QEMU:

    -drive if=none,file=4096.img,format=raw,id=vda \
    -device virtio-blk-device,drive=vda,physical_block_size=4096,logical_block_size=4096

In U-Boot the logical block size is shown by command `virtio info`:

    => virtio info
    Device 0: QEMU VirtIO Block Device
                Type: Hard Disk
                Capacity: 1024.0 MB = 1.0 GB (262144 x 4096)

There where two flaws which together hid that the logic was incorrect:

* VIRTIO_BLK_F_BLK_SIZE was missing in the driver capabilities and the bit
  was filtered out.
* The result of the call to virtio_has_feature() was negated.

The problem became apparent when using ARM FVP as emulator which does not set
VIRTIO_BLK_F_BLK_SIZE.

Fixes: c85b8071e7 ("virtio: blk: support block sizes exceeding 512 bytes")
Reported-by: Debbie Horsfall <debbie.horsfall@arm.com>
Tested-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2025-10-16 18:01:42 -06:00
Raymond Mao
f6c01ec151 ci: rename conf.qemu_arm64_na to conf.qemu_arm64
The test-hooks config file has been renamed by [1], thus update the
name where it is used by the script.

[1] https://lore.kernel.org/u-boot/20251003191918.767698-2-raymond.mao@linaro.org/

Signed-off-by: Raymond Mao <raymond.mao@linaro.org>
2025-10-16 15:02:45 -06:00
Anshul Dalal
1e470ddd07 env: Kconfig: disable external env in secure os boot
Falcon mode uses falcon_image_file from the env during mmc fs boot, but
external env can be compromised. Therefore disable access to external
env by setting SPL_ENV_IS_NOWHERE when SPL_OS_BOOT_SECURE is set.

Signed-off-by: Anshul Dalal <anshuld@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2025-10-16 15:02:14 -06:00
Tom Rini
3a71bae9af Merge patch series "ti_sci: Address some issues found by Smatch"
Andrew Goodbody <andrew.goodbody@linaro.org> says:

Prevent a memory leak from a non-freed malloc.
Return an error code on an error path.
Assign a value to a pointer before it is dereferenced.

Link: https://lore.kernel.org/r/20251008-ti_sci-v3-0-5866bf84adc6@linaro.org
2025-10-16 15:02:14 -06:00
Andrew Goodbody
5b9125746d ti_sci: Pointer is never assigned to valid value
The pointer resp is declared but never assigned a value but is then
dereferenced. Fix this by assigning the pointer to the message buffer.

This issue was found by Smatch.

Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Nishanth Menon <nm@ti.com>
Tested-by: Anshul Dalal <anshuld@ti.com>
2025-10-16 15:02:14 -06:00
Andrew Goodbody
4602fa9220 ti_sci: Provide error code on error exit
In ti_sci_get_response the check for message sequence will return ret
on a fail but ret will be 0 at that point. Instead return -EINVAL.
Also change dev_dbg call to dev_err to be consistent with other error
detection code in the same function.

This issue was found by Smatch.

Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Nishanth Menon <nm@ti.com>
Tested-by: Anshul Dalal <anshuld@ti.com>
2025-10-16 15:02:14 -06:00
Andrew Goodbody
4b8bc5af80 ti_sci: Prevent memory leak
temp is assigned the pointer returned by malloc which is used without a
NULL check and then never freed. Add a NULL check and ensure temp is
freed on all return paths.

This issue was found by Smatch.

Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Nishanth Menon <nm@ti.com>
Tested-by: Anshul Dalal <anshuld@ti.com>
2025-10-16 15:02:14 -06:00
Tom Rini
a157a73720 Merge tag 'u-boot-watchdog-20251016' of https://source.denx.de/u-boot/custodians/u-boot-watchdog
CI: https://dev.azure.com/sr0718/u-boot/_build/results?buildId=400&view=results

- watchdog: Tighten some driver dependencies in Kconfig (Tom)
2025-10-16 09:59:24 -06:00
Tom Rini
7fa9e29a3a Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-riscv
CI: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/27926

- Revert "riscv: Add a Zalrsc-only alternative for synchronization in
  start.S" to fix regression
- clk: sophgo: Fix a warning about void returns value
2025-10-16 09:52:14 -06:00
Tom Rini
0ab7710a06 clk: sophgo: Fix a warning about void returns value
The cv1800b_clk_setfield function returns void, but was doing "return
writel(...);" and while seemingly having a void function return a void
function is not a warning, when readl is a macro this problem is shown.
Correct the code to instead simply call writel.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Yao Zi <ziyao@disroot.org>
2025-10-16 16:44:49 +08:00
Yao Zi
e6646b35f4 Revert "riscv: Add a Zalrsc-only alternative for synchronization in start.S"
This reverts commit a681cfecb4.

It has been reported that the commit causes boot regression for SPL on
StarFive VisionFive 2 or compatible boards. Inspecting the code, I did
spot one logic error for deciding whether Zaamo or Zalrsc is used, and
it's still unclear what exactly causes the regression, let's revert it
for now.

Reported-by: E Shattow <e@freeshell.de>
Link: https://lore.kernel.org/u-boot/1871663e-b918-4351-9e9e-97f9a4c73733@freeshell.de/
Signed-off-by: Yao Zi <ziyao@disroot.org>
Acked-by: E Shattow <e@freeshell.de>
Acked-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-10-16 16:36:37 +08:00
Tom Rini
df2220c946 watchdog: Tighten dependencies on WDT_DAVINCI
The WDT_DAVINCI driver is not safe to compile on 64bit platforms such as
allyesconfig on a 64bit host. Tighten the dependencies here to the
platforms which could use it today.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-10-16 09:16:36 +02:00
Tom Rini
71a535c7ad watchdog: Tighten some watchdog driver dependencies
A few watchdog drivers cannot build without access to some platform
specific header files. Express those requirements in Kconfig as well.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Stefan Roese <stefan.roese@mailbox.org>
2025-10-16 09:16:36 +02:00
Tom Rini
2ba64e303b Merge patch series "fix an7581 panic caused by attempt to support multiple RAM size"
Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> says:

The commit 726404a66c ("airoha: rework RAM size handling to support
multiple RAM size") is not good enougth. It results in pacnic during
determining of memory size amount.

This patch series partly fix and partly revert the above commit.
Unfortunately for now we have no a good way to determine the an7581
memory size.

Link: https://lore.kernel.org/r/20251008070903.370974-1-mikhail.kshevetskiy@iopsys.eu
2025-10-15 15:08:27 -06:00
Abbarapu Venkatesh Yadav
f21920f7e7 .mailmap: update e-mail address for Abbarapu Venkatesh Yadav
Update e-mail address.

Signed-off-by: Abbarapu Venkatesh Yadav <venkyada@qti.qualcomm.com>
2025-10-15 15:08:27 -06:00
Mikhail Kshevetskiy
ce175fa9f0 arm/airoha: partly revert support of multiple RAM size for an7581
Partly revert commit 726404a66c ("airoha: rework RAM size handling
to support multiple RAM size").

The general idea is good, but the call of

  get_ram_size((void *)gd->ram_base, SZ_8G);

produces the following result on my an7581 board with only 1Gb of
memory:

  "Synchronous Abort" handler, esr 0x96000004
  elr: 0000000081e201c8 lr : 0000000081e20160 (reloc)
  elr: 00000000bff501c8 lr : 00000000bff50160
  x0 : 0000000180000000 x1 : 0000000100000000
  x2 : 000000000000002e x3 : 0000000000000002
  x4 : 000000001fbf0000 x5 : 0060000000000401
  x6 : 0000000000000000 x7 : 00000000bffdb268
  x8 : 0000000000000060 x9 : 00000000bffdb2c8
  x10: 0000000000000000 x11: 0000000000000060
  x12: 00000000bffdb268 x13: 00000000841c56d0
  x14: 00000000841c56d0 x15: 0000000000000000
  x16: 00000000841506e4 x17: dd7fe29aec3b07e8
  x18: 00000000bf710e00 x19: 0000000080000000
  x20: 0000000000000000 x21: 0000000020000000
  x22: 0000000200000000 x23: 0000000000000001
  x24: 0000000040000000 x25: 00000000bf708e78
  x26: 00000000bf7bdca0 x27: 0000000000000000
  x28: 0000000000000000 x29: 00000000bf708e20

  Code: 910943ff d65f03c0 d37df2a1 8b150e60 (f8616a62)
  Resetting CPU ...

So just not call get_ram_size() and use the value from dtb.

Fixes: 726404a66c ("airoha: rework RAM size handling to support multiple RAM size")
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
2025-10-15 15:08:27 -06:00
Georgi Vlaev
4e4bbb49f9 cmd: ti: Add DDRSS Inline ECC Error Injection command
Introduce a new version of the Keystone-II "ddr" command for testing the
inline ECC support in the DDRSS bridge available on K3 devices. The ECC
hardware support in K3's DDRSS and the test method differ substantially
from what we support in the K2 variant of the command. This K3 DDRSS
command currently supports only single controller testing.

The ECC error injection procedure follows these steps:
1) Flush and disable the data cache.
2) Disable the protected ECC Rx range.
3) Flip a bit in the address.
4) Restore the range to original.
5) Read the modified value (corrected).
6) Re-enable the data cache.

This will cause the 1-bit ECC error count to increase while the read
will return the corrected value.

The K3 version of the command extends the syntax for the "ecc_err"
argument by also introducing an argument for range which specifies which
range (0, 1, 2) the address is located in.

Multi-bit ECC errors are uncorrectable and will lead to a synchronous
abort.

Signed-off-by: Georgi Vlaev <g-vlaev@ti.com>
Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
[n-francis@ti.com: Add J7 and multiple-region support, simplify logic]
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
2025-10-15 15:08:27 -06:00
Mikhail Kshevetskiy
40f57b571c arm/airoha: an7581 ignores CFG_MAX_MEM_MAPPED value
This partly fix commit 726404a66c ("airoha: rework RAM size handling
to support multiple RAM size")

The function get_effective_memsize() do not see non-global defines
of CFG_MAX_MEM_MAPPED, so the effective memory size will not be changed.

Fix the issue by putting definition of CFG_MAX_MEM_MAPPED to the proper
place.

Fixes: 726404a66c ("airoha: rework RAM size handling to support multiple RAM size")
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
2025-10-15 15:08:27 -06:00
Kory Maincent
00ed9753c8 test: Do not build expo and cedit test if no SDL
expo and cedit tests depend on the host having the SDL library.
Build these tests only if VIDEO_SANDBOX_SDL config is enabled.

Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2025-10-15 14:17:13 -06:00
Ernest Van Hoecke
77d11d2f7a arm: dts: k3-am62p-verdin: migrate to OF_UPSTREAM
Enable CONFIG_OF_UPSTREAM to receive automatic
device tree updates for the Verdin AM62P.

Remove the now-obsolete device tree files:
- k3-am62p-verdin.dtsi
- k3-am62p-verdin-dev.dtsi
- k3-am62p-verdin-wifi.dtsi
- k3-am62p5-verdin-wifi-dev.dts

Signed-off-by: Ernest Van Hoecke <ernest.vanhoecke@toradex.com>
2025-10-15 14:17:09 -06:00
Andrew Goodbody
aebf3a98bf test: Remove not needed null check
In ut_report() there is a null check for stats but stats was already
dereferenced on the line before and is again dereferenced later in the
same function. Also the two places where ut_report() is called from will
have initialised the parameter so there is no chance that stats will be
null. So to prevent static analysis complaining of a use before check
just remove the check.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-10-15 14:17:06 -06:00
Simon Glass
996ded5463 boot: Move preparing bootdev into a function
We will want to use this same logic in another place within iter_inc(),
so split it out into its own function.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2025-10-14 16:12:50 -06:00
Simon Glass
f6cd0a36ce boot: Improve comments related to global bootmeths
Add a few comments about global bootmeths and first_glob_method

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
2025-10-14 16:12:50 -06:00
Tom Rini
b1cc9a53d7 Merge tag 'xilinx-for-v2026.01-rc1-v2' of https://source.denx.de/u-boot/custodians/u-boot-microblaze
AMD/Xilinx/FPGA changes for v2026.01-rc1 v2

zynqmp:
- DT updates
- Enable new commands

mbv:
- Simplify defconfigs

clk:
- Separate legacy handler and use SMC handler

misc:
- Tighten TTC Kconfig dependency

net:
- Add 10GBE support to Gem

pwm:
- cadence-ttc: Fix array sizes

fwu:
- Add platform hook support

spi:
- Remove undocumented cdns,is-dma property

video:
- Fix DPSUB RGB handling
2025-10-14 09:48:02 -06:00
Tom Rini
14d36cd8da Merge tag 'mix-next-14102025' of https://source.denx.de/u-boot/custodians/u-boot-tpm
TPM changes:
Make all drive names defined with U_BOOT_DRIVER unique

TEE changes:
Rework things such that sandbox will also traverse the optee directory
when SANDBOX_TEE is enabled, but only build one of the optee-specific
files when OPTEE is enabled.

EFI changes:
Up to now we were relying on the file extension to accept and load
an image over HTTP. We expected images to be either .iso or .img.

By wiring up internal existing functions we can try to mount any
file extension and reject it only if mounting fails.
part_driver_lookup_type
2025-10-14 08:27:01 -06:00
Tom Rini
78406dda99 Merge tag 'u-boot-marvell-20251014' of https://source.denx.de/u-boot/custodians/u-boot-marvell
CI: https://dev.azure.com/sr0718/u-boot/_build/results?buildId=398&view=results

- sata_mv / octeontx_hsmmc: Smatch fixes / patches (Andrew)
- dts: pxa1908: convert to OF_UPSTREAM (Duje)
- phy: marvell: Tighten MVEBU_COMPHY_SUPPORT dependencies (Tom)
- pci: mvebu: Unable to assign mbus windows for 2nd pcie controller (Tony)
2025-10-14 08:24:35 -06:00
Viorel Suman
865f665422 cmd: sf: align erase and write on erase block boundary
Align erase and write on erase block boundary in line with how read was
aligned in commit 622b5d3561 ("cmd: sf: Handle unaligned 'update' start
offset").

Fixes: 622b5d3561 ("cmd: sf: Handle unaligned 'update' start offset")
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Tested-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # R-Car V4H
2025-10-14 08:19:43 -06:00
Michal Simek
a040578d82 spi: cadence-qspi: Remove cdns,is-dma property handling
Remove cdns,is-dma DT property handling. Property is not the part of DT
binding and it is also hardcoded to value 1 in all DTs that's why remove it
because none is also testing value 0.
If there is any use case when this configuration should be supported this
patch can be reverted.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/6205c6585589b423692b6ed063506b4c51c04c77.1760006086.git.michal.simek@amd.com
2025-10-14 16:00:45 +02:00
Tom Rini
377bc19fd9 tpm: Make U_BOOT_DRIVER entries unique
All instances of the U_BOOT_DRIVER must use a unique name or they will
lead to link time failures due to name space conflicts when both are
present. In this case the driver was reusing the tpm_tis_i2c name.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-10-14 10:42:27 +03:00
Tom Rini
398f988410 tee: Rework Makefile logic
The intention of how this Makefile was written was to allow for sandbox
to build and test drivers still while otherwise requiring OPTEE to be
enabled. This however didn't work quite right in practice as sandbox
could enable some drivers which would then fail to link. Rework things
such that sandbox will also traverse the optee directory when
SANDBOX_TEE is enabled, but only build one of the optee-specific files
when OPTEE is enabled.

Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-10-14 10:42:27 +03:00
Javier Tia
038ca2c803 efi_loader: Improve disk image detection in efi_bootmgr
Enhances the process for identifying disk images within the EFI boot
manager. Utilize part_driver_lookup_type() to verify the validity of a
downloaded file as a disk image, rather than depending on file
extensions.

part_driver_lookup_type() is now used in the prepare_loaded_image()
function in the EFI boot manager to detect partitions on a block device
created from a downloaded image. This allows the boot manager to boot
from any disk image that can be recognized by a partition driver, not
just ISO and IMG images.

Update prepare_loaded_image() to create the ramdisk block device
internally, obtain the blk_desc and use part_driver_lookup_type() to
detect a valid partition table.

In try_load_from_uri_path(), try prepare_loaded_image() first to detect
disk images, and fall back to PE-COFF detection only if that fails.

Signed-off-by: Javier Tia <javier.tia@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-10-14 10:30:56 +03:00
Javier Tia
28c341ca07 part: Export part_driver_lookup_type for external use
Make part_driver_lookup_type non-static so it can be used outside
part.c. This allows external callers to determine the appropriate
partition driver for a block device, enabling more flexible handling of
partition types.

Add a prototype and kernel-doc comment in part.h to document the
function contract. Provide a stub inline implementation returning NULL
when partition support is disabled, ensuring build consistency across
configurations.

Signed-off-by: Javier Tia <javier.tia@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-10-14 10:29:30 +03:00
Sam Protsenko
3b278dd9e6 bootstd: Fix bootflow info for efi_mgr
A "Synchronous Abort" CPU exception happens on an attempt to run the
"bootflow info" command for a global boot method (e.g. efi_mgr):

    => bootflow select 0
    => bootflow info

    "Synchronous Abort" handler, esr 0x96000006, far 0x8

It happens because do_bootflow_info() tries to dereference bflow->dev,
which is NULL in case of efi_mgr. Add the corresponding check to prevent
this NULL pointer dereference and make "bootflow info" command work
properly for global boot methods.

Fixes: 2d653f686b ("bootstd: Add a bootflow command")
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
2025-10-13 14:54:33 -06:00
Tom Rini
ee7d07f9d0 global: Disable xPL phases when we have enabled COMPILE_TEST
Due to how we implement the logic for selecting what should/shouldn't be
built in a given phase it becomes extremely cumbersome to make these
phases link when configured by "allyesconfig". As a starting point for
being able to enable "allyesconfig" and expand our static coverage,
disable all other phases in this case.

Future work can be done to enable other phases as time and interest
permit.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-10-13 14:54:32 -06:00
Tom Rini
16b0482a74 sandbox: Make SANDBOX_xPL depend on !COMPILE_TEST
Given how these options are used in the code, it doesn't make sense to
enable them for COMPILE_TEST. Make them depend on !COMPILE_TEST.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-10-13 14:54:32 -06:00
Tom Rini
6822583672 global: Make REMAKE_ELF depend on !COMPILE_TEST
The REMAKE_ELF flag is something that should be selected by the
platforms which need it, and not prompted for. Start by making this
depend on !COMPILE_TEST.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-10-13 14:54:32 -06:00
Tom Rini
ec90518ee6 spl: FIT: Make SPL_LOAD_FIT_FULL depend on SPL_LOAD_FIT
Today, only a few platforms enable SPL_LOAD_FIT_FULL, and all enable
SPL_LOAD_FIT. As can be seen in usage, the FULL symbol is a superset of
the first symbol, not an alternative. Update Kconfig entries based on
this and simplify the only code which checks for either being set.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-10-13 14:54:32 -06:00
Tom Rini
66873b9ef0 SPL: Make SPL_OS depend on supported architectures
We can only enable Falcon Mode (aka SPL_OS) on architectures which
implement certain hooks. Express these dependencies in Kconfig.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-10-13 14:54:32 -06:00
Tom Rini
768b5167bd Merge patch series "bootstd: rauc: fix doc and info msg to reflect real flow"
Andreas Pretzsch <apr@cn-eng.de> says:

For the RAUC bootmethod, newly introduced in U-Boot 2025.10, both code
and documentation contain some incorrect (maybe outdated) statements,
so they do not reflect the real behaviour.
This series corrects both the docs and one log_info in the code, to now
reflect the real flow. Beside being visible in the code, all of it was
tested on a real machine.

Despite the very late time in RC cycle, I suggest inclusion before release
of U-Boot 2025.10, as the current statements are simply incorrect. Also I
do not see any risk in these non-functional changes.
Thanks to Martin Schwan for the review and esp. the initial code!

Link: https://lore.kernel.org/r/20251002162506.3908711-1-apr@cn-eng.de
2025-10-13 14:54:32 -06:00
Andreas Pretzsch
1c3687782f bootstd: rauc: extend and fix doc to reflect real flow
The documentation of bootmeth rauc in some aspects does not reflect the
real program flow. Specifically the reset of boot tries in case of "no
more slots found" is incorrect (it won't change BOOT_ORDER).
Also the search sequence for boot scripts was mixed and incomplete.
Fix these points in the documentation.

Explain the initial setup of any missing BOOT_ORDER and BOOT_x_LEFT
environment variables, and inform about BOOT_x_LEFT decrementing.

Signed-off-by: Andreas Pretzsch <apr@cn-eng.de>
Reviewed-by: Martin Schwan <m.schwan@phytec.de>
2025-10-13 14:54:32 -06:00
Andreas Pretzsch
d6277523e5 bootstd: rauc: no valid slot fallback: fix info msg to reflect real flow
If there is no more active slot found in find_active_slot(), like when
all slots in BOOT_ORDER have a count of 0, the counters are reset to their
default value CONFIG_BOOTMETH_RAUC_DEFAULT_TRIES. The BOOT_ORDER is _not_
changed, which is logically correct (especially for the case when there is
only one (active) slot set, e.g. BOOT_ORDER only contains 'B', probably due
to RAUC option prevent-late-fallback being set). Resetting the counters of
inactive slots also does not harm here, and is fine as a generic solution.

But the log_info statement in this scenario
  INFO: Resetting boot order and all slot tries
is incorrect. Change this to
  INFO: Resetting all slot tries to 3
with the 3 being inserted by CONFIG_BOOTMETH_RAUC_DEFAULT_TRIES.

Signed-off-by: Andreas Pretzsch <apr@cn-eng.de>
Reviewed-by: Martin Schwan <m.schwan@phytec.de>
2025-10-13 14:54:32 -06:00
Tony Dinh
81598d19ca pci: mvebu: Unable to assign mbus windows for 2nd pcie controller
Correct the memory and IO mbus windows size increments in mvebu_pcie_bind.

Currently, pcie1 controller resource_size(&mem) and resource_size(&io)
checks result in a failure. This is because mem.end and io.end must be
incremented at the end of pcie0 windows assignment.

Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Stefan Roese <stefan.roese@mailbox.org>
2025-10-13 16:13:21 +02:00
Tom Rini
b44f18923b phy: marvell: Tighten MVEBU_COMPHY_SUPPORT dependencies
This driver cannot link without access to functions that are defined in
files that are only build on some platforms.  Express those requirements
in Kconfig as well.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Stefan Roese <stefan.roese@mailbox.org>
2025-10-13 16:13:21 +02:00
Duje Mihanović
80f3568995 ARM: dts: pxa1908: convert to OF_UPSTREAM
Convert the PXA1908 platform and its coreprimevelte board to OF_UPSTREAM
and enable the few drivers found in the upstream DTS.

Signed-off-by: Duje Mihanović <duje@dujemihanovic.xyz>
2025-10-13 16:13:21 +02:00
Andrew Goodbody
bde84072d0 mmc: octeontx_hsmmc: Remove impossible test
In octeontx_mmc_io_drive_setup drive and slew are tested for being less
than 0 but they are declared as uint fields so this test must always
fail. Just remove the test.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-10-13 16:13:21 +02:00
Andrew Goodbody
4b1b035e74 mmc: octeontx_hsmmc: Need parens in expression
The check for no response expected in octeontx_mmc_send_cmd needs parens
adding for proper interpretation.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-10-13 16:13:21 +02:00
Andrew Goodbody
ae7fea1b37 sata: sata_mv: Remove always true test
Smatch reported an issue with a test that was always true in that an
unsigned variable will always be >= to zero. This led to a closer look
at the code which showed that some static functions returned values that
were always discarded so make those functions return void. Also make
the passing of block counts in those functions always use lbaint_t.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Stefan Roese <stefan.roese@mailbox.org>
2025-10-13 16:13:21 +02:00
Andrew Goodbody
48f21e66e3 fs: jffs2: Remove always true test
Testing an unsigned variable to be >= 0 will always be true so remove
this redundant test.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
2025-10-10 14:27:59 -06:00
Andrew Goodbody
87b7eaf324 fs/squashfs: Ensure memory is freed by using unwind goto
Returning immediately from sqfs_read_nest is not consistent with other
error checks in this function and can lead to memory leaks. Instead use
the unwind goto used elsewhere to ensure that the memory is freed.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Acked-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Joao Marcos Costa <joaomarcos.costa@bootlin.com>
2025-10-10 14:27:49 -06:00
Tom Rini
42b3534125 fs: Rework filesystem guards for xPL phases
When adding filesystems to the table in fs/fs.c we need to use
CONFIG_IS_ENABLED(FS_xxx) so that we only include references to a given
filesystem when CONFIG_FS_xxx or CONFIG_SPL_FS_xxx or similar are
enabled. Update the filesystems which weren't doing this to follow that
pattern.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-10-10 14:25:35 -06:00
Tom Rini
dde1515be5 lz4: Do not disable LZ4_decompress_safe* for xPL
We should compile the LZ4_decompress_safe and
LZ4_decompress_safe_partial functions in SPL and they will be discarded
if unused.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-10-10 14:25:33 -06:00
Tom Rini
16bbc225fe iotrace: Finish migrating this to Kconfig
When I migrated this to Kconfig in commit 68e54040cc ("sandbox: Move
CONFIG_IO_TRACE to Kconfig") I didn't look hard enough for other
details. As explained in the README, this is valid for ARM too. So start
by making this be a prompted question and CMD_IOTRACE depend on IO_TRACE
being enabled.  Next, migrate the information out of README and in to
the appropriate help text for existing options in Kconfig. Finally, make
this option be default y on SANDBOX but not selected as it's valid to
build without it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-10-10 14:25:24 -06:00
Tom Rini
b30155c08e sandbox: Rework readX/writeX macros to be more like ARM
The way that the current readX/writeX macros are implemented on sandbox
means that when IO_TRACE is not enabled some code will throw up
incorrect warnings due to how sandbox_{read,write} is implemented. We
instead need to do the "uX __v; __v = sandbox..(..v); __v;" trick that
ARM does.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-10-10 13:58:49 -06:00
Tom Rini
9de2fc9878 arm: v7m: Allow SYS_ARCH_TIMER here
We have had an implementation of the generic timer found in many v7m
chips since 2017, but as part of the Kconfig migration forgot to allow
it as it wasn't being used at the time. Allow it to be built.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-10-10 13:29:34 -06:00
Tom Rini
cd01a8164d Merge patch series "mkimage: fit: various fixes in fit_{import,extract}_data"
Quentin Schulz <foss+uboot@0leil.net> says:

I had to hunt down a difference between the FIT after running mkimage
once and after running it twice. The use-case is typically U-Boot
generating an unsigned FIT and then calling mkimage manually to sign it
outside any build system.

The issue can be reproduced with the following

make CROSS_COMPILE=aarch64-linux-gnu- BUILD_TAG= SOURCE_DATE_EPOCH=0 O=build/ringneck ringneck-px30_defconfig
make CROSS_COMPILE=aarch64-linux-gnu- BUILD_TAG= SOURCE_DATE_EPOCH=0 O=build/ringneck -j`nproc`
cd build/ringneck
cp ./simple-bin.fit.itb ./simple-bin.foo.fit
cp ./simple-bin.fit.itb ./simple-bin.foo2.fit
BUILD_TAG= SOURCE_DATE_EPOCH=0 ./tools/mkimage -E -t -B 200 -F ./simple-bin.foo.fit
BUILD_TAG= SOURCE_DATE_EPOCH=0 ./tools/mkimage -E -t -B 200 -F ./simple-bin.foo2.fit
BUILD_TAG= SOURCE_DATE_EPOCH=0 ./tools/mkimage -E -t -B 200 -F ./simple-bin.foo2.fit

then compare the output of

dtc -I dtb -O dts simple-bin.foo.fit
dtc -I dtb -O dts simple-bin.foo2.fit

data-size and data-offset properties are swapped.

While going through the code, I identified a few theoretical issues
possibly triggered by not checking the return code of fdt_setprop so
those are added. Not tested outside of building.

Link: https://lore.kernel.org/r/20250923-mkimage-2-runs-data-size-v1-0-ef3fa57e9645@cherry.de
2025-10-10 13:28:42 -06:00
Quentin Schulz
b3ab77345e mkimage: fit: erase data-size property when importing data
When importing data, the data-offset property is removed and the data
content is imported inside the data property of the node.

When mkimage is run twice on the same FIT, data-size property is already
set in the second run, from the first run (via the fit_export_data
function). If we don't remove the data-size property, nothing guarantees
it matches the actual size of data within the data property. To avoid
possible mistakes when handling the data property, let's simply remove
the data-size property as well.

This also fixes an ordering issue of the data-size and data-offset
properties in FIT when comparing the FIT after one run of mkimage and a
second run. This is due to fit_export_data setting data-offset property
first (it doesn't exist so it's added) and then data-size (it doesn't
exist so it's added) for the first run, while it sets data-offset
property first (removed in fit_import_data, so it doesn't exist so it's
added) and then data-size (it exists already from the first run, so it's
simply modified) for the second run.

Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
2025-10-10 13:28:36 -06:00
Quentin Schulz
abab733fc2 mkimage: fit: do not ignore fdt_setprop return code
All explicit calls to fdt_setprop* in tools/ are checked except those
three. Let's add a check for the return code of fdt_setprop_u32() calls.

Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
2025-10-10 13:28:36 -06:00
Quentin Schulz
6209ce58c3 mkimage: fit: do not overwrite fdt_setprop return value
The return code of fdt_setprop is overwritten by the one from
fdt_delprop meaning we could very well have an issue when setting the
property that would be ignored if the deletion of the property that
comes right after passes.

Let's add a separate check for each.

Fixes: 4860ee9b09 ("mkimage: allow internalization of data-position")
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
2025-10-10 13:28:36 -06:00
Tom Rini
8c42f534d7 Merge patch series "configs: toradex: enable USB Gadget OS Descriptors"
Emanuele Ghidoli <emanuele.ghidoli@toradex.com> says:

USB OS Descriptors are used to install and configure the device without
requiring any user interaction on OS which support them (e.g. Windows).
Enable them in order to improve the user experience when fastboot is used.

Link: https://lore.kernel.org/r/20251001132111.1490516-1-ghidoliemanuele@gmail.com
2025-10-10 11:07:45 -06:00
Tom Rini
33b16e0043 Merge patch series "configs: verdin-am*: enable USB Gadget OS Descriptors"
Emanuele Ghidoli <ghidoliemanuele@gmail.com> says:

From: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>

USB OS Descriptors are used to install and configure the device without
requiring any user interaction on OS which support them (e.g. Windows).
Enable them in order to improve the user experience when fastboot is used.

Toradex Easy Installer takes advantage of USB OS Descriptors to load
itself via USB recovery.

Link: https://lore.kernel.org/r/20251001131839.1488633-1-ghidoliemanuele@gmail.com
2025-10-10 11:07:44 -06:00
Emanuele Ghidoli
6052e225fa configs: toradex-smarc-imx8mp: enable USB Gadget OS Descriptors for fastboot
USB OS Descriptors are used to install and configure the device without
requiring any user interaction on OS which support them (e.g. Windows).
Enable them in order to improve the user experience when fastboot is used.

Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
2025-10-10 11:07:44 -06:00
Tom Rini
a073d3d37c Merge patch series "am65-cpsw-nuss phy_interface_t fixup for fixed TX delay"
Matthias Schiffer <matthias.schiffer@ew.tq-group.com> says:

Following a discussion on the LKML [1], there has been a clarification
of the correct use of the rgmii(/-rxid/-txid/-it) phy-modes [2] - namely,
that they don't describe the interface at the MAC or PHY boundary, but
whether the PCB traces add delays or not (where it is
implementation-defined whether the delays are added on the MAC or PHY
side in the latter case).

Accordingly, a fixup has been implemented in the am65-cpsw-nuss driver
to make it follow the clarified rules [3]; apply the same change to
U-Boot. Backwards compatibility is preserved: using an old DTB with
the wrong phy-mode only results in a warning message, but keeps the
Ethernet working. With a new DTB from Linux 6.17+ that sets the mode to
rgmii-id, these changes are necessary to avoid using an unsupported/
reserved configuration. See the commit message of patch 2/2 for some
additional detail.

[1] https://lore.kernel.org/lkml/d25b1447-c28b-4998-b238-92672434dc28@lunn.ch/
[2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=c360eb0c3ccb95306704fd221442283ee82f1f58
[3] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=ca13b249f291f4920466638d1adbfb3f9c8db6e9

Link: https://lore.kernel.org/r/cover.1759218200.git.matthias.schiffer@ew.tq-group.com
2025-10-10 11:07:44 -06:00
Emanuele Ghidoli
6a22d03164 configs: verdin-am62p: enable USB Gadget OS Descriptors for fastboot
USB OS Descriptors are used to install and configure the device without
requiring any user interaction on OS which support them (e.g. Windows).
Enable them in order to improve the user experience when fastboot is used.

Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
2025-10-10 11:07:44 -06:00
Emanuele Ghidoli
86901e0749 configs: verdin-imx8m[mp]: enable USB Gadget OS Descriptors for fastboot
USB OS Descriptors are used to install and configure the device without
requiring any user interaction on OS which support them (e.g. Windows).
Enable them in order to improve the user experience when fastboot is used.

Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
2025-10-10 11:07:44 -06:00
Matthias Schiffer
4b10bcfdef net: ethernet: ti: am65-cpsw: fix up PHY mode for fixed RGMII TX delay
The am65-cpsw driver currently sets the SEL_RGMII_IDMODE flag in a MAC's
mode register to enable or disable the TX delay. While this was supported
for earlier generations of the CPSW controller, the datasheets of all
modern TI SoCs using the am65-cpsw MAC state that the TX delay is fixed,
and the SEL_RGMII_IDMODE bit is documented as reserved in most of them.
Furthermore, while it was found that this bit does in fact disable the TX
delay, [1] states that this setting is truly unsupported by TI and not
just undocumented.

Following the clarification of the rgmii* phy-mode values in the Linux
DT bindings in [2], the Linux am65-cpsw driver was changed in [3] to
account for the fixed TX delay by fixing up the mode passed to the PHY
driver; a similar fixup already existed in the TI icssg-prueth driver.
[4] followed up on this by explicitly clearing the SEL_RGMII_IDMODE flag
to handle the case where it is set by the bootloader or other firmware
before Linux.

With the above changes, Device Trees that set the recommended "rgmii-id"
mode are now appearing in Linux 6.17+. Avoid setting the unsupported
SEL_RGMII_IDMODE flag for such Device Trees, and instead fix up the PHY
interface mode, thus aligning the U-Boot driver with the Linux kernel.

[1] https://www.spinics.net/lists/netdev/msg1112647.html
[2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=c360eb0c3ccb95306704fd221442283ee82f1f58
[3] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=ca13b249f291f4920466638d1adbfb3f9c8db6e9
[4] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=a22d3b0d49d411e64ed07e30c2095035ecb30ed2

Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
2025-10-10 11:07:44 -06:00
Emanuele Ghidoli
5e1e08549b configs: verdin-am62: enable USB Gadget OS Descriptors for fastboot
USB OS Descriptors are used to install and configure the device without
requiring any user interaction on OS which support them (e.g. Windows).
Enable them in order to improve the user experience when fastboot is used.

Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
2025-10-10 11:07:44 -06:00
Emanuele Ghidoli
4580222b87 configs: colibri-*: enable USB Gadget OS Descriptors for fastboot
USB OS Descriptors are used to install and configure the device without
requiring any user interaction on OS which support them (e.g. Windows).
Enable them in order to improve the user experience when fastboot is used.

Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
2025-10-10 11:07:44 -06:00
Matthias Schiffer
8db554dcbb net: mdio-uclass: introduce dm_eth_phy_connect_interface()
dm_eth_phy_connect_interface() is a variant of dm_eth_phy_connect() that
allows to set the used PHY mode, in case the MAC driver needs to fix it
up. The previously static dm_eth_connect_phy_handle() is renamed and
extended for this purpose.

Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
2025-10-10 11:07:44 -06:00
Emanuele Ghidoli
d748154ff1 configs: apalis-imx6: enable USB Gadget OS Descriptors for fastboot
USB OS Descriptors are used to install and configure the device without
requiring any user interaction on OS which support them (e.g. Windows).
Enable them in order to improve the user experience when fastboot is used.

Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
2025-10-10 11:07:44 -06:00
Tom Rini
a574f8a3e5 spl: spl_sata: Add __maybe_unused decorator
It is possible that we will not have enabled the options to call
spl_sata_load_image_raw so use the __maybe_unused decorator to silence
the compiler warning.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-10-10 10:27:13 -06:00
Tom Rini
3da6f00af3 dts: Set a default value for DEFAULT_DEVICE_TREE for SANDBOX
As part of building with "allyesconfig" we need to have the correct
default value for the sandbox architecture provided here.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-10-10 10:27:04 -06:00
Tom Rini
1d34d80881 timer: Tighten dependencies on MCHP_PIT64B_TIMER
The MCHP_PIT64B_TIMER driver is not safe to compile on 64bit platforms
such as allyesconfig on a 64bit host. Tighten the dependencies here to
the platforms which use it today.

Acked-by: Eugen Hristev <eugen.hristev@linaro.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-10-10 10:26:58 -06:00
Tom Rini
0ceea8b721 gpio: Remove FTGPIO0010 driver
This driver has never been enabled and currently has build problems
related in part to incorrect out_le32 calls. Remove it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-10-10 10:26:53 -06:00
Tom Rini
8ea8487da0 include: completion.h: Convert the rest of the dummy functions to macros
While we declare some of our dummy functions as "inline" we do not also
declare them as "static" and so it is possible for the compiler to
decide to make these as global functions instead. This can lead to link
time failures in some cases, such as "allyesconfig". As these are just
dummy functions, convert them to a macro instead.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-10-10 10:26:47 -06:00
Siddharth Vadapalli
0a71fe2805 configs: j7200_evm_a72_defconfig: Enable DP83867 Ethernet PHY
The MCU Ethernet Interface on J7200-EVM uses the DP83867 Ethernet PHY as
described in the section '4.9 MCU Ethernet Interface' of the J7200-EVM
User-Guide [0]. Since the config corresponding to the DP83867 PHY has not
been enabled, the Generic PHY driver is used. As a result, the RGMII delays
do not take effect leading to packet losses.

Fix this by enabling the config for the DP83867 Ethernet PHY.

[0]: https://www.ti.com/lit/ug/spruiw7a/spruiw7a.pdf

Fixes: f8c1e893c8 ("configs: j7200_evm_a72: Add Initial support")
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
2025-10-10 10:26:44 -06:00
Tom Rini
361731fc39 Merge branch 'uboot-05102025' of https://source.denx.de/u-boot/custodians/u-boot-nand-flash
This series adds significant and valuable work by Mikhail Kshevetskiy to
align spi-mem with Linux 6.16. It also includes contributions to the mtd
performance patches, a work started by Miquel Raynal and improved by
Mikhail Kshevetskiy. Additionally, two patches tighten dependencies on
the Atmel driver.

The patches pass the pipeline CI:
https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/pipelines/27873
2025-10-10 08:24:45 -06:00
Tom Rini
e0516d3807 Merge tag 'fsl-qoriq-master-2025-10-10' of https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq
CI: https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq/-/pipelines/27882

- crypto/rng: double the entropy delay interval for retry
- Make RAMBOOT_PBL only be valid for PowerPC or ls1021AI
2025-10-10 08:23:04 -06:00
Tom Rini
824236dd60 Merge tag 'mmc-power-master-2025-10-10' of https://source.denx.de/u-boot/custodians/u-boot-mmc
CI: https://source.denx.de/u-boot/custodians/u-boot-mmc/-/pipelines/27881

- Use dev_read_u32() for sdhciA-cadence6
- Misc compilation/Kconfig fix
2025-10-10 08:21:50 -06:00
Tom Rini
b1ca952b48 NXP: Make RAMBOOT_PBL only be valid for PowerPC or ls1021A
Only PowerPC and LS1021A platforms can make use of RAMBOOT_PBL. Add the
dependencies to the symbol.

Signed-off-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-10-10 11:45:07 +08:00
Gaurav Jain
524d637bb9 crypto/rng: double the entropy delay interval for retry
During entropy evaluation, if the generated samples fail any statistical test,
then, all of the bits will be discarded, and a second set of samples will be
generated and tested.

Double the ent_delay to give more chance to pass before performing retry.

Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-10-10 11:44:27 +08:00
Tom Rini
63bce69047 mmc: cv1800b_sdhci: Fix possible warning with MMC_SUPPORTS_TUNING=n
The function cv1800b_set_tap_delay is only called by
cv1800b_execute_tuning. The latter is where we currently have the #if
guard around MMC_SUPPORTS_TUNING, and so with the option disabled we
have an unused function warning. Move the guard to cover both functions.

Signed-off-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-10-10 11:06:00 +08:00
Tom Rini
2a846e04c6 power: regulator: Correct dependencies on SPL_REGULATOR_PWM
In order to enable and build with SPL_REGULATOR_PWM we need to have both
SPL_DM_REGULATOR and SPL_DM_PWM enabled. Build-wise, we can have SPL
have PWM regulator support without enabling it in U-Boot itself so drop
that dependency.

Signed-off-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-10-10 10:59:41 +08:00
Tom Rini
6304cfa5a7 mmc: Fix a potential warning in xPL
When xPL_MMC_WRITE is set but also xPL_MMC_TINY is set, the function
sd_read_ssr may be unused. Guard it appropriately.

Signed-off-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-10-10 10:46:40 +08:00
Tanmay Kathpalia
0524f40947 mmc: sdhci-cadence6: Use dev_read_u32() for device tree property parsing
Convert device tree property parsing to use dev_read_u32(), which
handles endianness and simplifies the code.

Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@altera.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-10-10 10:45:56 +08:00
Tom Rini
ecdc3872a7 Merge patch series "firmware: scmi: various update"
Peng Fan (OSS) <peng.fan@oss.nxp.com> says:

Misc update on firmware scmi:
 - Typo fix
 - Use io helpers
 - Use PAGE_SIZE for arm64
 - Add IN_USE error code
 - Add more error info
 - Support scmi max rx timeout in mailbox
 - Add myself as scmi maintainer, AKASHI contributed most code, but
   seems he is not invovled in the developement anymore, I volunteer to
   help here.

Some items on list that I am thinking to add:
- align with linux kernel to use cpu_to_le32 and le32_to_cpu, but have not find
  a good way to use the helpers.
- Add SCMI version negotiation as Linux Kernel

Link: https://lore.kernel.org/r/20250927-scmi-v1-0-5e9354fb3bff@nxp.com
2025-10-09 14:30:02 -06:00
Peng Fan
7828597f54 MAINTAINERS: Add an entry for SCMI
Add an entry for SCMI and add myself as maintainer

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-10-09 14:16:11 -06:00
Peng Fan
5ea37da298 cmd: scmi: Add pin control protocol name
Pin control protocol name was not added into 'protocol_name' array,
however Pin control was supported on i.MX95. So add it.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-10-09 14:16:11 -06:00
Peng Fan
0d71bc3a1b clk: scmi: Replace log_debug with dev_dbg
Use dev_dbg to dump device name, dev_dbg also a encapsulation call
to log() and print(). So it is ok to use dev_dbg.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-10-09 14:16:11 -06:00
Peng Fan
5e9fb0e583 firmware: scmi: mailbox: Support arm,max_rx_timeout_ms
Per devicetree bindings:
arm,max-rx-timeout-ms indicates an optional time value, expressed in
milliseconds, representing the transport maximum timeout value for the
receive channel. The value should be a non-zero value if set.

Support this property if platform set it to a non-default value. This
property is a per SCMI property, so all channels share same value.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2025-10-09 14:16:11 -06:00
Peng Fan
f116ec5b91 firmware: scmi: mailbox: Update timeout to 30ms
Following Linux Kernel drivers/firmware/arm_scmi/transports/mailbox.c to
set the default timeout to 30ms.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-10-09 14:16:11 -06:00
Peng Fan
b2ae10970d firmware: scmi: use PAGE_SIZE alignment for ARM64
For ARMv7, the alignment could be SECTION size. But for ARM64, use
PAGE_SIZE.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-10-09 14:16:11 -06:00
Peng Fan
eb7469eb1a firmware: scmi: Add error code IN_USE
In SCMI spec 3.2, there is an update:
Add IN_USE error code for usage with Pin control protocol

So add the error decoding for IN_USE.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-10-09 14:16:11 -06:00
Peng Fan
23e2b76922 firmware: scmi: smt: Dump more info
"Buffer too small" is too vague, dump more info to make it easier to
debug issues.
Change dev_dbg to dev_err when buffer is too small.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-10-09 14:16:11 -06:00
Peng Fan
8c48bae4f5 firmware: scmi: smt: Use io helpers
It is not good practice to directly use "hdr->x" to read/write the hdr,
because the SCMI buffer may not mapped as normal memory. Following Linux
Kernel, using ioread32/iowrite32/memcpy_[from,to]io for smt header read,
write.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-10-09 14:16:11 -06:00
Peng Fan
92fe41caad firmware: scmi: Typo fix
Typo: 'to' -> 'too'

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-10-09 14:16:11 -06:00
Tom Rini
8cc77c78b0 Merge patch series "fw_loader: Split from fs_loader into separate library file"
This series from Marek Vasut <marek.vasut+renesas@mailbox.org> splits
the fw_loader "script" code out from the fs_loader code as the former
does not require the latter.

Link: https://lore.kernel.org/r/20250922114926.51984-1-marek.vasut+renesas@mailbox.org
2025-10-09 13:50:59 -06:00
Marek Vasut
50fc929386 fw_loader: Prefix the FW loader variables with the script prefix
Add the script name as a prefix to fw_addr and fw_size variables
to make sure they are always unique and won't easily conflict with
user variables.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-10-09 13:50:40 -06:00
Marek Vasut
8aa57934e5 fw_loader: Split from fs_loader into separate library file
The script based firmware loader does not use anything from the
fs_loader implementation. Separate it into its own library source
file and convert the mediatek PHY to use this separate code. This
should reduce the amount of code that is pulled in alongside the
firmware loader, as the FS loader is no longer included.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-10-09 13:50:40 -06:00
Tom Rini
a1fd7a9589 Merge tag 'u-boot-imx-master-20251009' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/27872

- Several improvements for kontron-sl-mx8mm.
- Add rauc to bootmeths to phycore_imx8mp.
- Fix imx93_frdm USB vendor ID.
2025-10-09 13:47:28 -06:00
Tom Rini
ef0f6e7a99 nand: atmel: Rework ATMEL_EBI and DM_NAND_ATMEL interaction
The way that the NAND driver under DM_NAND_ATMEL is probed is by the
dummy memory driver controlled by ATMEL_EBI. Rather than require that
for NAND to work both be enabled, make NAND select ATMEL_EBI and do not
prompt for ATMEL_EBI as it only triggers the probe for NAND.

Signed-off-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2025-10-09 20:57:27 +02:00
Tom Rini
178d18862a mtd: Tighten some mtd driver dependencies
A large number of mtd drivers cannot build without access to some
platform specific header files. Express those requirements in Kconfig as
well.

Signed-off-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2025-10-09 20:57:21 +02:00
Ernest Van Hoecke
15bed125d7 arm: dts: imx8mp-toradex-smarc: migrate to OF_UPSTREAM
Enable CONFIG_OF_UPSTREAM to receive automatic device tree updates for
the Toradex SMARC iMX8MP.

Remove the now obsolete device tree files:
- imx8mp-toradex-smarc-dev.dts
- imx8mp-toradex-smarc.dtsi

Signed-off-by: Ernest Van Hoecke <ernest.vanhoecke@toradex.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2025-10-09 14:57:09 -03:00
Tom Rini
4463376302 Merge tag 'ubi-for-2026.01-rc1' of https://source.denx.de/u-boot/custodians/u-boot-ubi
UBI updates for 2025.10

- ubi fixes found by Andrew with Smatch
  - mtd: ubi: Remove test that always fails
  - fs: ubifs: Ensure buf is freed before return
  - fs: ubifs: Need to check return for being an error pointer
  -fs: ubifs: Fix and rework error handling in ubifs_finddir

- fix: limit copy size in ubispl found by Benedikt

- extend support for LED activity (use the LED activity also on ubi reads)
  from Yegor
2025-10-09 09:54:18 -06:00
Mathieu Dubois-Briand
5d5d4c6bc7 imx93_frdm: Fix USB vendor ID
NXP manufacturing tools expect the device to have the NXP 0x1fc9 vendor
ID instead of 0x0525. This is the value already used by other i.MX8 and
i.MX9 boards.

Signed-off-by: Mathieu Dubois-Briand <mathieu.dubois-briand@bootlin.com>
2025-10-09 08:53:15 -03:00
Michal Simek
0cb6970639 xilinx: Enable SNTP/DATE commands and RTC
Enable SNTP/DATE commands on all Xilinx boards.
Also enable RTC_EMULATION driver for platforms which don't have physical
RTC. Enabling DM_RTC is enabling by default also CMD_DATE.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/2605b1618a311efe4f35442c34e7cec973060630.1759393175.git.michal.simek@amd.com
2025-10-09 12:31:09 +02:00
Padmarao Begari
d413e228ed xilinx: mbv: Remove redundancy in MB-V defconfigs
Removes redundant configuration options from MB-V platform defconfigs
targeting both modes. Common settings are now placed in
xilinx_mbv32_defconfig, which is included via the #include <configs/...>.
This approach centralizes configuration management, reduces duplication,
and makes future maintenance easier.

Signed-off-by: Padmarao Begari <padmarao.begari@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/585f96d85b656803bd382ac25425d68998f24ed5.1759393175.git.michal.simek@amd.com
2025-10-09 12:31:09 +02:00
Andrew Goodbody
4c606b165b video: zynqmp: Prevent use of uninitialised variables
The variables 'offset_matrix' and 'csc_matrix' will be used
uninitialised if video->is_rgb is false. Correct the logic so the
attempt to use uninitialised variables is not made. Also remove the use
of these variables as they seem to serve no useful purpose just being
aliases for arrays.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Link: https://lore.kernel.org/r/20251001-video_zynqmp-v1-1-34f1e59b9c34@linaro.org
Signed-off-by: Michal Simek <michal.simek@amd.com>
2025-10-09 12:31:09 +02:00
Michal Simek
ed5b149b81 xilinx: Replace PHY_VITESSE by PHY_MSCC
Enable MSCC phy driver instead of VITESSE. Vitesse driver is much older and
is on the way out that's why switch to MSCC driver which covers VSC8531
which is used on one Versal board.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/0a441e488a29bd1c93677a6f63a4a04a3cc1c9f5.1759216164.git.michal.simek@amd.com
2025-10-09 12:31:09 +02:00
Tom Rini
a3861c71d5 timer: Tighten CADENCE_TTC_TIMER dependencies
This driver implements timer_get_boot_us() which is global namespace and
can conflict with other implementations of the function for example in
"allyesconfig". Start by limiting this driver to platforms which use it.

Signed-off-by: Tom Rini <trini@konsulko.com>
Link: https://lore.kernel.org/r/20250926153146.3680952-1-trini@konsulko.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2025-10-09 09:07:04 +02:00
Michal Simek
145645a9f2 arm64: zynqmp: Fix DTOVL warning about graphs in kv/kr260
DTC is generating warnings about missing port like:
DTOVL   arch/arm/dts/zynqmp-smk-k24-revA-sck-kv-g-revB.dtb
 arch/arm/dts/zynqmp-sck-kv-g-revA.dtbo: Warning (graph_port):
 /fragment@5/__overlay__: graph port node name should be 'port'
...

That's why change description and add it directly to dpsub mode to contain
full description with also port.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/576630cc9696e21bef15bd1f0ca35e396adc4eca.1758529693.git.michal.simek@amd.com
2025-10-09 09:07:04 +02:00
Padmarao Begari
68dc66d7e0 board: xilinx: update guid based on metadata
The generated GUID applies to all Xilinx platforms but is not
specific to any individual board. For FWU multi bank update,
use the image UUID (GUID) from the FWU metadata structure
rather than embedding a generated GUID into the U-Boot build.

Signed-off-by: Padmarao Begari <padmarao.begari@amd.com>
Link: https://lore.kernel.org/r/20250912100539.4127378-3-padmarao.begari@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2025-10-09 09:07:04 +02:00
Padmarao Begari
aa4e7f7083 FWU: Add platform hook support for fwu metata
FWU metadata information is unavailable for platform-specific
operations since FWU initialization has not yet occurred.
The initialization function is invoked as part of the main
loop event. To address this, the FWU platform hook function
is introduced during FWU initialization, allowing metadata
processing with platform-specific operations.

Signed-off-by: Padmarao Begari <padmarao.begari@amd.com>
Link: https://lore.kernel.org/r/20250912100539.4127378-2-padmarao.begari@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2025-10-09 09:07:04 +02:00
Michal Simek
9b68682d1c arm64: zynqmp: Add pmw_fan label to k26
Some boards/designs with System Controller which are using SOMs need to
change PWM signal polarity that's why create label to be able to reference
them.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/7a392d79685e5b122528e8fe7617475c4f6fabab.1756803198.git.michal.simek@amd.com
2025-10-09 09:07:04 +02:00
Michal Simek
8651f2a50a arm64: zynqmp: Enable DP for kr260, kv260, zcu100, zcu102, zcu104, zcu111
Upstream DP DT binding enforcing dp-connector and port description to
operate properly.

Co-developed-by: Rohit Visavalia <rohit.visavalia@amd.com>
Signed-off-by: Rohit Visavalia <rohit.visavalia@amd.com>
Co-developed-by: Nithish Kumar Naroju <nithishkumar.naroju@amd.com>
Signed-off-by: Nithish Kumar Naroju <nithishkumar.naroju@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/15e863adca11431f68d37d732cd8a453e508ad91.1756803198.git.michal.simek@amd.com
2025-10-09 09:07:04 +02:00
Michal Simek
8e27bd3a7a arm64: zynqmp: Introduce DP port labels
Describe every port by unique label for easier wiring with DT overlays.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/933151f48f236f64ec9e91b9da4f174460a269e6.1756803198.git.michal.simek@amd.com
2025-10-09 09:07:04 +02:00
Michal Simek
b852fece84 arm64: zynqmp: Update compatible string for tps546X24
ti,tps546d24 is already described in DT binding and ti,tps546b24 should be
described in the same way that's why update compatible string to match
them.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/a247b2b57ebe52e9d23525bf4f96c4872288025d.1756803198.git.michal.simek@amd.com
2025-10-09 09:07:04 +02:00
Michal Simek
4bd2183984 arm64: zynqmp: Enable PSCI 1.0
TF-A is using PSCI 1.0 version for quite a long time but it was never
reflected in DT.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/a3372ee9cce7fade7c9f707727e33d1cf569b607.1756803198.git.michal.simek@amd.com
2025-10-09 09:07:04 +02:00
Michal Simek
5fc47ae48e arm64: zynqmp: Fix incomplete comment in zynqmp-sc-vn-p-b2197-00-revA.dtso
Fix comment inside comment by closing the first one properly.

Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202501111756.IcKlG6rs-lkp@intel.com/
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/779be02a8f0cfa1deab86dbfe8e575ab152d43f3.1756803198.git.michal.simek@amd.com
2025-10-09 09:07:04 +02:00
Radhey Shyam Pandey
09311c8a38 arm64: zynqmp: Revert usb node drive strength and slew rate for zcu106
On a few zcu106 boards USB devices (Dell MS116 USB Optical Mouse, Dell USB
Entry Keyboard) are not enumerated on linux boot due to commit
'b8745e7eb488 ("arm64: zynqmp: Fix usb node drive strength and slew
rate")'.

To fix it as a workaround revert to working version and then investigate
at board level why drive strength from 12mA to 4mA and slew from fast to
slow is not working.

Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/14d3408cf547ac188c07c10abb0ddfaac9d915c4.1756803198.git.michal.simek@amd.com
2025-10-09 09:07:04 +02:00
Padmarao Begari
5b13a280b4 arm64: xilinx: Add i2c mux idle disconnect property
Add i2c-mux-idle-disconnect property to an i2c mux node.
It is used to configure an i2c mux to disconnect all
its channels when idle.

Signed-off-by: Padmarao Begari <padmarao.begari@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/d75f31d72cadf6d98c0faa51239bf2b239797d2d.1756803198.git.michal.simek@amd.com
2025-10-09 09:07:04 +02:00
Michal Simek
4640051cdf arm64: zynqmp: Remove "ti,tps53679" property
Linux driver has been updated that only ti,tps53681 dt property is needed
and there is no need to provide second compatible string.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/609ee957931242ab6cde93e75eb3bd8afa769f12.1756803198.git.michal.simek@amd.com
2025-10-09 09:07:04 +02:00
Michal Simek
e2aaac3f6b arm64: zynqmp: Remove RTC calibration from sm-k26
Default calibration is already in zynqmp.dtsi that's why make no sense to
describe it again.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/6331bf84d7afaf8031d9cbb64354fcd8ca343d45.1756803198.git.michal.simek@amd.com
2025-10-09 09:07:04 +02:00
Michal Simek
09c862aca4 arm64: zynqmp: Remove undocumented arasan, has-mdma property
Property was used long ago by internal Xilinx Linux driver but it is not
documented in DT binding that's why remove it.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/546788df1a64c41e332463411ad99b1f3b40bc96.1756803198.git.michal.simek@amd.com
2025-10-09 09:07:04 +02:00
Quanyang Wang
733f2de332 arm64: zynqmp: Disable coresight by default
When secure-boot mode of bootloader is enabled, the registers of
coresight are not permitted to access that's why disable it by default.

Signed-off-by: Quanyang Wang <quanyang.wang@windriver.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/1ea8e5bdb9bfdcc1fc6670bf4b4e13c40fbdc00c.1756803198.git.michal.simek@amd.com
2025-10-09 09:07:04 +02:00
Andrew Goodbody
fe8d071c49 pwm: cadence-ttc: Insufficient elements in array
The Cadence TTC has 3 channels that can each be used for PWM functions.
Ensure that the array has sufficient elements to avoid a possible memory
access overrun. Use a macro to keep the array size and limit checks in
sync so adjust checks to work with this.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Link: https://lore.kernel.org/r/20250901-cadence_pwm-v1-1-140b04cd73a9@linaro.org
Signed-off-by: Michal Simek <michal.simek@amd.com>
2025-10-09 09:07:03 +02:00
Naman Trivedi
4146a31dce drivers: firmware: update xilinx_pm_request to support max payload
Currently xilinx_pm_request API supports four u32 payloads. However the
legacy SMC format supports five u32 request payloads and extended SMC
format supports six u32 request payloads. Add support for the same in
xilinx_pm_request API. Also add two dummy arguments to all the callers
of xilinx_pm_request.

The TF-A always fills seven u32 return payload so add support
for the same in xilinx_pm_request API.

Signed-off-by: Naman Trivedi <naman.trivedimanojbhai@amd.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Acked-by: Senthil Nathan Thangaraj <senthilnathan.thangaraj@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/5ae6b560741f3ca8b89059c4ebb87acf75b4718e.1756388537.git.michal.simek@amd.com
2025-10-09 09:07:03 +02:00
Michal Simek
e7fe2c7bc6 clk: xilinx: Separate legacy format to own handler
It is a preparation for adding enhacement format support that's why there
is a need to separate current support to own function.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/c4d546553d4f0d69ef75fb1132b7121f36dd306c.1756388537.git.michal.simek@amd.com
2025-10-09 09:07:03 +02:00
Michal Simek
f791695685 clk: xilinx: Call generic smc_call_handler()
There is no reason to call SMC from clock driver directly when clock driver
is a child of firmware driver which is providing it.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/d383d5fea680b33d2eddbca108c452cee97e98ea.1756388537.git.michal.simek@amd.com
2025-10-09 09:07:03 +02:00
Venkatesh Yadav Abbarapu
038580206d drivers: net: Add versal2 10GBE device support
Add 10GBE high-speed Mac support, it supports 10G, 5G, 2.5G and 1G speeds.
10GBE high speed Mac is an extension of the current 1G Mac in versal,
inheriting all its current features.

MMI 10GBE ip has two internal PCS's.
1)10GBASER PCS is used for higher speeds 10G and 5G.
2)1000BASEX PCS is used for slower speeds 1G and 2.5G.

Both PCS's speed and rate configuration is done with same
usx registers. ENABLE_HS_MAC bit in NCR is the toggle switch
between the PCS's.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20250828045807.426542-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2025-10-09 09:07:03 +02:00
Kory Maincent
ddde9ac63d scripts/checkpatch.pl: Resync with v6.17
This resyncs us with the version found in v6.17 of the Linux kernel with
the following exceptions:
- Keep our u-boot specific tests / code area.
- Keep the location of our checkpatch.rst
- Change the "use strscpy" test as we don't have that to strlcpy
- Keep debug/printf in the list for $logFunctions
- Keep checks to "env" files
- Keep our tests for strncpy/strncat

This also syncs the spdxcheck.py tool and all the associated
documentation.

Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
[trini: Keep our strlcpy/cat check]
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-10-08 17:18:36 -06:00
Tom Rini
7781f1d832 w1-eeprom: Make use of static keyword in drivers
Both the ds24xxx and ds2502 have a family_supported array which is local
to the driver but was not marked as static. Mark this as static as both
best practice and to allow both to be built in "allyesconfig" for
example.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-10-08 16:13:11 -06:00
Tom Rini
7c2e4487e4 timer: Tighten CADENCE_TTC_TIMER dependencies
This driver implements timer_get_boot_us() which is global namespace and
can conflict with other implementations of the function for example in
"allyesconfig". Start by limiting this driver to platforms which use it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-10-08 16:13:08 -06:00
Tom Rini
af4acc7186 rng: Tighten some rng driver dependencies
In this case, the NPCM RNG driver also provides some of the functions
that are implemented in the generic LIB_RAND file, so only allow this to
be built when that is disabled. The exynos RNG driver depends on ARM
SMCCC calls and so cannot be built outside of that. Express these
requirements in Kconfig as well.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-10-08 16:13:06 -06:00
Tom Rini
1d77a98b3d misc: ti: k3: Tighten K3_FUSE dependencies
This driver cannot build without access to some platform specific header
files. Express those requirements in Kconfig as well.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-10-08 16:13:02 -06:00
Tom Rini
f34a86c1ef led: Mark LED_STATUS as depending on LED being disabled
The LED_STATUS functionality is part of the legacy LED framework. This
cannot be enabled at the same time as the new LED API is. Make the text
prompt be clear this is legacy and add a dependency on LED being
disabled.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-10-08 16:13:00 -06:00
Tom Rini
0cdca862cb common: Make MMU_PGPROT depend on !SANDBOX
While MMU_PGPROT is currently only functional for arm64 it can be
extended for other real platforms as well. It does not however make
sense for sandbox to enable and create dummy functions for. Make this
depend on !SANDBOX.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-10-08 16:12:56 -06:00
Yegor Yefremov
f03601e369 arm: baltos: remove obsolete GPMC_NAND_ECC_LP_x8_LAYOUT macro
This define is obsolete, and bus width is now handled via
CONFIG_SYS_NAND_BUSWIDTH_16BIT option.

Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
2025-10-08 16:12:53 -06:00
Tom Rini
9d42a06019 cmd: Update dependencies on CMD_IRQ
For CMD_IRQ to function, we need enable/disable_interrupt functions as
well as do_irqinfo functions to be defined. Only NIOS2, PowerPC and X86
implement the latter, so correct dependencies to be opt-in not out-out
here.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-10-08 16:12:50 -06:00
Tom Rini
583a45c33f cmd: Make CMD_MP depend on the CPU framework being disabled
The CMD_MP (and cmd/mp.c) command provide a "cpu" command which is
mutually exclusive from the "cpu" command provided by cmd/cpu.c and the
CPU framework. Make CMD_MP depend on CPU not being enabled.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-10-08 16:12:48 -06:00
Tom Rini
e5fea3f3b9 sandbox: Add more dummy cache functions
In order for cmd/cache.c to link we need to add dummy icache functions
to mirror the dummy dcache functions as well as another dcache flush
function.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-10-08 16:12:46 -06:00
Tom Rini
93dbdf3898 spl: Correct dependency for SPL_SYS_REPORT_STACK_F_USAGE
In Kconfig syntax, "!=" is a string and not numerical comparison. This
means that to check for a non-zero SPL_SIZE_LIMIT_PROVIDE_STACK value we
need to test that it is "> 0" rather than "!=" 0. This is because "0x0 >
0" is false while "0x0 != 0" is true.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-10-08 16:12:43 -06:00
Tom Rini
2d11e5ba4e Kconfig: Make further use of testing for !COMPILE_TEST
We have a large number of library symbols that should not be prompted
for by the user really but rather selected by the platform (or SoC) as
needed. To start with however, make these depend on !COMPILE_TEST.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-10-08 16:12:41 -06:00
Tom Rini
f293019b6b test: syslog: Add missing include of <env.h>
These files was making environment calls without including <env.h> and so
relying on an indirect inclusion from elsewhere. Add the missing include
directly.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-10-08 16:12:36 -06:00
Tom Rini
9b937cdaa3 test: led: Add missing ';'
Some tests here had not been compile tested before submission and were
missing a ';' on the end of declaring struct udevice *dev. Add it.

Fixes: 9046279d92 ("test: dm: Add tests for LED boot and activity")
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-10-08 16:12:36 -06:00
Paresh Bhagat
14dfa6b861 Add initial support for AM62D2-EVM
Add initial support for AM62D2-EVM, Kconfig entries for binman, SPL,
base DTS files for u-boot and SPL, HS-SE and HS-FS support and initial
configs with SD-MMC, UART, eMMC and OSPI boot providing a baseline for
further enablement.

Also add labels and targets to AM62A-SK binman to enable AM62D2-EVM
builds to reuse existing binman infrastructure.

Technical Reference Manual - https://www.ti.com/lit/pdf/sprujd4
Schematics Link - https://www.ti.com/lit/zip/sprcal5

Signed-off-by: Paresh Bhagat <p-bhagat@ti.com>
2025-10-08 16:10:11 -06:00
Tom Rini
eea470fd7f Subtree merge tag 'v6.17-dts' of dts repo [1] into dts/upstream
[1] https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git
2025-10-08 15:01:20 -06:00
Tom Rini
b7abe4d77a Squashed 'dts/upstream/' changes from d08867ef8f12..4d52919c55f4
4d52919c55f4 Merge tag 'v6.17-dts-raw'
38fc28fcd6fe Merge tag 'i2c-for-6.17-rc8' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux
5df2896cdbcd Merge tag 'soc-fixes-6.17-3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
501d5fac4d3e Merge tag 'v6.17-rockchip-dtsfixes2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/fixes
388d0d237317 Merge tag 'sunxi-fixes-for-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/fixes
9c1a1aa76d6a dt-bindings: i2c: spacemit: extend and validate all properties
f88821c169f7 Merge tag 'hid-for-linus-2025092201' of git://git.kernel.org/pub/scm/linux/kernel/git/hid/hid
7bb1f59ee85e Merge tag 'v6.17-rc6-dts-raw'
785f4a41a7a7 Merge tag 'phy-fix-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy
b72de0ae4a0d Merge tag 'dmaengine-fix-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine
f1de2f274990 Merge tag 'tty-6.17-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty
8dd5e1884a5c Merge tag 'imx-fixes-6.17-2' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixes
c0c7a4135951 Merge tag 'socfpga_dts_fix_for_v6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into arm/fixes
5f5117ff540a Merge tag 'mvebu-fixes-6.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into arm/fixes
affba3242b22 Merge commit '89c5214639294' into for-6.17/upstream-fixes
5c5133a89684 arm64: dts: marvell: cn9132-clearfog: fix multi-lane pci x2 and x4 ports
a30edc781685 arm64: dts: marvell: cn9132-clearfog: disable eMMC high-speed modes
4818551bb6d9 arm64: dts: marvell: cn913x-solidrun: fix sata ports status
e0499b5c331f ARM: dts: kirkwood: Fix sound DAI cells for OpenRD clients
b43e7c1e6d2d arm64: dts: imx8mp: Correct thermal sensor index
eaf6bab64a58 riscv: dts: allwinner: rename devterm i2c-gpio node to comply with binding
faf49552868d Merge tag 'v6.17-rc5-dts-raw'
b16ee588d71b arm64: dts: rockchip: Fix the headphone detection on the orangepi 5
e183eb884e5c arm64: dts: rockchip: Add vcc supply for SPI Flash on NanoPC-T6
d5396f16c37f ARM: dts: socfpga: sodia: Fix mdio bus probe and PHY address
ebd92f3a59b2 Merge tag 'spi-fix-v6.17-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
a526c9ef1b67 Merge tag 'soc-fixes-6.17-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
5d8ba326d104 Merge tag 'at91-fixes-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into arm/fixes
509dee1b7e66 ARM: dts: microchip: sama7d65: Force SDMMC Legacy mode
9e763cb3d1b4 Merge tag 'v6.17-rockchip-dtsfixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/fixes
a41fd927377f arm64: dts: rockchip: fix second M.2 slot on ROCK 5T
18d0194799e5 dt-bindings: lpspi: Document support for S32G
c9fac75c65f2 arm64: dts: rockchip: fix USB on RADXA ROCK 5T
63ef95420b13 arm64: dts: axiado: Add missing UART aliases
b2a21e821e2c Merge tag 'imx-fixes-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixes
58056a8dbfc9 Merge tag 'v6.17-rc4-dts-raw'
3e7b84751e93 Merge tag 'drm-fixes-2025-08-29' of https://gitlab.freedesktop.org/drm/kernel
ea89dcf2416c Merge tag 'drm-msm-fixes-2025-08-26' of https://gitlab.freedesktop.org/drm/msm into drm-fixes
6309b9b1efc4 arm64: dts: rockchip: Add vcc-supply to SPI flash on Pinephone Pro
e22da6a63ced Merge tag 'devicetree-fixes-for-6.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
f25e8f3f3e67 dt-bindings: display/msm: qcom,mdp5: drop lut clock
0b54cf7dc8d3 Merge tag 'v6.17-rc3-dts-raw'
0264ca32989f Merge tag 'mips-fixes_6.17_1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux
302d05793211 arm64: dts: rockchip: fix es8388 address on rk3588s-roc-pc
0704a97d3469 arm64: dts: rockchip: Fix Bluetooth interrupts flag on Neardi LBA3368
f1a75d0e9267 arm64: dts: rockchip: correct network description on Sige5
4212fbb0acb5 arm64: dts: rockchip: Minor whitespace cleanup
a52498f55fed ARM: dts: rockchip: Minor whitespace cleanup
2b74ca5ff951 arm64: dts: rockchip: Add supplies for eMMC on rk3588-orangepi-5
5135047db7f2 arm64: dts: rockchip: Fix the headphone detection on the orangepi 5 plus
510af76983ed mips: lantiq: xway: sysctrl: rename the etop node
2ff76939eff1 mips: dts: lantiq: danube: add missing burst length property
5c17501f659d ARM64: dts: mcbin: fix SATA ports on Macchiatobin
6f440931507f ARM: dts: armada-370-db: Fix stereo audio input routing on Armada 370
140d6b3980c3 arm64: dts: imx95: Fix JPEG encoder node assigned clock
c384581e7d6f arm64: dts: imx95-19x19-evk: correct the phy setting for flexcan1/2
e2edf4aaafbf arm64: dts: imx8mp: Fix missing microSD slot vqmmc on Data Modul i.MX8M Plus eDM SBC
4ea5d96804b4 arm64: dts: imx8mp: Fix missing microSD slot vqmmc on DH electronics i.MX8M Plus DHCOM
2789604fc218 arm64: dts: imx8mp-tqma8mpql: remove virtual 3.3V regulator
a573a81d351e arm64: dts: imx8mp-tqma8mpql: fix LDO5 power off
e96897446ad9 Merge tag 'regulator-fix-v6.17-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator
694d45a2f761 dt-bindings: vendor-prefixes: add eswin
f16c7cbc671f ARM: dts: allwinner: Minor whitespace cleanup
9e29f1c5986c Merge tag 'v6.17-rc2-dts-raw'
43c415b40654 Merge tag 'net-6.17-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
e24d016dedd9 dt-bindings: serial: 8250: allow "main" and "uart" as clock names
93772d487e42 dt-bindings: serial: 8250: move a constraint
fa1b88e6663a dt-bindings: serial: brcm,bcm7271-uart: Constrain clocks
4982fdb2c306 dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Update pcie phy bindings
23a1689d9a68 dt-bindings: phy: marvell,comphy-cp110: Fix clock and child node constraints
d57c7d5cb3fe riscv: dts: thead: Add APB clocks for TH1520 GMACs
32097674787b dt-bindings: net: thead,th1520-gmac: Describe APB interface clock
25370078d056 regulator: dt-bindings: infineon,ir38060: Add Guenter as maintainer from IBM
5b650c7a3387 Merge tag 'v6.17-rc1-dts-raw'
f579ec5f89fe arm64: dts: rockchip: Add vcc-supply to SPI flash on rk3399-pinebook-pro
401adf630a1b arm64: dts: rockchip: mark eeprom as read-only for Radxa E52C
f6fe1e119a05 dt-bindings: dma: qcom: bam-dma: Add missing required properties
6eb6301028f5 Merge tag 'mailbox-v6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/jassibrar/mailbox
7beab77fbc66 Merge tag 'soc-fixes-6.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
9c15d4d232b9 Merge tag 'tegra-for-6.17-arm64-dt-v3' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/fixes
d818fcb1ce10 Merge tag 'net-6.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
c669bebbe274 Merge tag 'loongarch-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
d25371e88f49 Merge tag 'input-for-v6.17-rc0' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
b225444b125e dt-bindings: mailbox: Add ASPEED AST2700 series SoC
4022f68499d8 dt-bindings: mailbox: Drop consumers example DTS
08a32727c5e5 dt-bindings: mailbox: nvidia,tegra186-hsp: Use generic node name
3ed8929022ea dt-bindings: mailbox: Correct example indentation
08534e6d0a28 dt-bindings: mailbox: ti,secure-proxy: Add missing reg maxItems
c26f859e6afe dt-bindings: mailbox: amlogic,meson-gxbb-mhu: Add missing interrupts maxItems
a98189806d7f dt-bindings: mailbox: qcom-ipcc: document the Milos Inter-Processor Communication Controller
bcdf210f6039 dt-bindings: mailbox: Add support for bcm74110
7861e592add4 Merge branch 'next' into for-linus
e6595131966d Merge tag 'scsi-misc' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi
a317294a0141 dt-bindings: net: Replace bouncing Alexandru Tachici emails
9177d7f279b3 Input: add keycode for performance mode key
5bd774b49823 LoongArch: dts: Add eMMC/SDIO controller support to Loongson-2K2000
d2b50965e07c LoongArch: dts: Add SDIO controller support to Loongson-2K1000
20c7a872f5fd LoongArch: dts: Add SDIO controller support to Loongson-2K0500
65a3167b6e72 Merge tag 'i2c-for-6.17-rc1-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux
8deaba69701b Merge tag 'ib-mfd-gpio-input-pwm-v6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd into next
5927e9980011 Merge tag 'rtc-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux
9b82ded0a5a8 Merge tag 'i3c/for-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/i3c/linux
74cfe0883b3c Merge tag 'i2c-host-6.17-pt2' of git://git.kernel.org/pub/scm/linux/kernel/git/andi.shyti/linux into i2c/for-mergewindow
a29a05ff2d8d Merge tag 'pinctrl-v6.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
f43f3f8a2149 Merge tag 'rproc-v6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/remoteproc/linux
06484243d8ee Merge tag 'pci-v6.17-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci
38d94dc8574d Merge tag 'linux-watchdog-6.17-rc1' of git://www.linux-watchdog.org/linux-watchdog
81e6b5eb1307 Merge tag 'dmaengine-6.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine
912ad91d462a Merge tag 'phy-for-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy
fc1b311a55ee Merge tag 'sound-6.17-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound
f898700a53a9 Merge tag 'for-v6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/sre/linux-power-supply
19d393592c86 Merge branch 'pci/controller/sophgo'
522b974af253 Merge branch 'pci/controller/qcom'
b6336c96a490 Merge branch 'pci/controller/brcmstb'
eaddf7ef5e04 dt-bindings: PCI: qcom,pcie-sa8775p: Document 'link_down' reset
b61473b60b3f dt-bindings: PCI: Remove 83xx-512x-pci.txt
95e7dfd2b09c dt-bindings: PCI: Convert amazon,al-alpine-v[23]-pcie to DT schema
d855db32b1d6 dt-bindings: PCI: Convert marvell,armada-3700-pcie to DT schema
faa8038a538e dt-bindings: PCI: Convert apm,xgene-pcie to DT schema
b64147052a31 dt-bindings: PCI: Convert axis,artpec6-pcie to DT schema
89b27dfc989f dt-bindings: PCI: Convert st,spear1340-pcie to DT schema
761305253c7f Merge tag 'mtd/for-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux
7f4c60d44458 Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
d2166900176e Merge tag 'hwmon-for-v6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging
f654a4cffc8e Merge tag 'media/v6.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media
c68e5f5d8510 Merge tag 'leds-next-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/leds
5fa7da3742d2 Merge tag 'mfd-next-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd
d48c5718d931 Merge tag 'gnss-6.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/johan/gnss
f19dc807ef82 Merge tag 'mips_6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux
88ef88367045 Merge tag 'nand/for-6.17' into mtd/next
77ce7c807f31 Merge tag 'spi-nor/for-6.17' into mtd/next
617063dc7992 Merge tag 'v6.17-p1' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6
fb35ad6772e3 arm64: tegra: Remove numa-node-id properties
5d5d47c2898d Merge branch 'clk-fixes' into clk-next
1810b29ee894 Merge tag 'drm-next-2025-07-30' of https://gitlab.freedesktop.org/drm/kernel
672251f07f5f Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm
1c4c35171c77 dt-bindings: i3c: Add Renesas I3C controller
acc6ad02daf0 Merge tag 'iommu-updates-v6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/iommu/linux
913a827d8026 Merge tag 'arm-soc/for-6.16/devicetree-fixes' of https://github.com/Broadcom/stblinux into for-next
ce735da13c91 Merge tag 'net-next-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next
23ad1dd8a0f2 mfd: dt-bindings: Convert TPS65910 to DT schema
ebcd01abab45 Merge tag 'powerpc-6.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux
fabc9eb3b96b dt-bindings: i2c: apple,i2c: Document Apple A7-A11, T2 compatibles
f08139dcfa69 Merge branches 'clk-rockchip', 'clk-thead', 'clk-microchip', 'clk-imx' and 'clk-qcom' into clk-next
fe77e800d26c Merge branches 'clk-renesas', 'clk-samsung', 'clk-spacemit', 'clk-allwinner' and 'clk-amlogic' into clk-next
f9a15ab8af76 Merge branches 'clk-bindings', 'clk-cleanup', 'clk-pwm', 'clk-hw-device', 'clk-xilinx' and 'clk-adi' into clk-next
84946f9433bb Merge tag 'irq-drivers-2025-07-27' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
11f0d2c420f3 Merge tag 'mmc-v6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc
7dff1db3c967 Merge tag 'pmdomain-v6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/linux-pm
7a67b758e4c6 Merge tag 'i2c-for-6.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux
059f314983b4 Merge tag 'soc-newsoc-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
935ca70fe88a Merge tag 'soc-drivers-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
f210f652efaa Merge tag 'soc-dt-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
33c1d430f189 Merge tag 'devicetree-for-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
ca819c3ba978 Merge tag 'usb-6.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb
86157d6ef538 Merge tag 'tty-6.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty
638f234e9940 Merge tag 'char-misc-6.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc
206f073acf2c Merge tag 'kvmarm-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into HEAD
f1208bcf4c31 Merge tag 'pwm/for-6.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/ukleinek/linux
60c278df97a4 Merge tag 'spi-v6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
06e9819c6572 Merge tag 'regulator-v6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator
6094cd275fea Merge tag 'gpio-updates-for-v6.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux
fe3cebf87ff8 Merge tag 'sound-6.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound
ccd9a5c60b97 Merge tag 'thermal-6.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
1ed339a1dd9b Merge tag 'pm-6.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
dbfbda98c7fa dt-bindings: Correct indentation and style in DTS example
1c1a12439958 MIPS: mobileye: dts: eyeq5,eyeq6h: rename the emmc controller
2d80b8cff673 dt-bindings: hwmon: Replace bouncing Alexandru Tachici emails
a9536c4a533e dt-bindings: Add INA228 to ina2xx devicetree bindings
ba8204028427 dt-bindings: input: touchscreen: st1232: add touch-overlay example
1633cb20b256 dt-bindings: touchscreen: add touch-overlay property
06b06ef8f47d Input: Add and document BTN_GRIP*
59ae00fd8e64 dt-bindings: input: syna,rmi4: Document F1A function
cc47e10c64b0 dt-bindings: ieee802154: Convert at86rf230.txt yaml format
b966613384a2 Merge tag 'sunxi-fixes-for-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into soc/dt
3849b529499b dt-bindings: net: dsa: microchip: Add KSZ8463 switch support
6979cbfbf41e dt-bindings: net: altr,socfpga-stmmac: Add compatible string for Agilex5
6b627bb260fd Merge tag 'qcom-drivers-for-6.17-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers
233d517c1884 dt-bindings: i2c: i2c-rk3x: Allow use of a power-domain
7049499f9e5a dt-bindings: i2c: exynos5: add samsung,exynos2200-hsi2c compatible
fc7ae9ba5fb2 dt-bindings: net: dsa: b53: Document brcm,gpio-ctrl property
3c4710ce3e81 dt-bindings: display: mediatek,dp: Allow DisplayPort AUX bus
646525defa14 dt-bindings: fsl: convert fsl,vf610-mscm-ir.txt to yaml format
137ad9b12805 dt-bindings: interrupt-controller: Add fsl,icoll.yaml
648b651777b1 dt-bindings: interrupt-controller: Add missing Xilinx INTC binding
b41b883df97c scsi: arm64: dts: mediatek: mt8195: Add UFSHCI node
8523d45b2495 scsi: dt-bindings: mediatek,ufs: add MT8195 compatible and update clock nodes
3f060c24c171 scsi: dt-bindings: mediatek,ufs: Add ufs-disable-mcq flag for UFS host
711056c3ae41 Merge tag 'for-net-next-2025-07-23' of git://git.kernel.org/pub/scm/linux/kernel/git/bluetooth/bluetooth-next
dd1b4057dd88 Merge tag 'wireless-next-2025-07-24' of https://git.kernel.org/pub/scm/linux/kernel/git/wireless/wireless-next
155dc9a613a6 spi: sophgo: Add SPI NOR controller for SG2042
bb7c1194a99d Add RSPI support for RZ/V2H
50fd75a061ed dt-bindings: clock: convert lpc1850-cgu.txt to yaml format
24140d806f08 dt-bindings: clock: Convert qca,ath79-pll to DT schema
6e04ef32ef38 dt-bindings: clock: Convert nuvoton,npcm750-clk to DT schema
2db6f9a1da8f dt-bindings: clock: Convert moxa,moxart-clock to DT schema
001cac37e6e6 dt-bindings: clock: Convert microchip,pic32mzda-clk to DT schema
0cd4ab636909 dt-bindings: clock: Convert maxim,max9485 to DT schema
1c33570f5d22 support for amlogic the new SPI IP
a14fec537070 dt-bindings: clock: Convert qcom,krait-cc to DT schema
fa19909f10d5 dt-bindings: clock: qcom: Remove double colon from description
b039af46152a Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
a162ca77489e spi: dt-bindings: Document the RZ/V2H(P) RSPI
3d1aedbd9343 ASoC: dt-bindings: atmel,at91-ssc: add microchip,sam9x7-ssc
0bdf06c97664 spi: dt-bindings: Add binding document of Amlogic SPISG controller
4e1353cbd1b1 spi: dt-bindings: spi-sg2044-nor: Change SOPHGO SG2042
9707aa6ab611 Merge tag 'ib-mfd-gpio-power-soc-v6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd into gpio/for-next
8ee72356e984 dt-bindings: mfd: rk806: Allow to customize PMIC reset mode
28d9430f0964 dt-bindings: mfd: samsung,s2mps11: Add comment about interrupts properties
4563fdbc72d2 dt-bindings: mfd: fsl,imx8qxp-csr: Remove binding documentation
8f9f74c9d030 dt-bindings: mfd: Convert lpc1850-creg-clk, pc1850-dmamux and phy-lpc18xx-usb-otg to YAML format
75a11ccc6567 dt-bindings: mfd: convert mxs-lradc bindings to json-schema
8978eadc5578 Merge branches 'ib-mfd-gpio-input-pwm-6.17', 'ib-mfd-gpio-power-soc-6.17' and 'ib-mfd-misc-pinctrl-6.17' into ibs-for-mfd-merged
4e0a772975ea dt-bindings: gpio: rockchip: Allow use of a power-domain
f5cd2bf1e8fb dt-bindings: serial: snps-dw-apb-uart: Allow use of a power-domain
5d324bdff50d dt-bindings: serial: samsung: add samsung,exynos2200-uart compatible
0a9a83ae140d dt-bindings: mfd: Add Apple Mac System Management Controller
c7fa9a3843ab dt-bindings: power: reboot: Add Apple Mac SMC Reboot Controller
f4eddbec1946 dt-bindings: gpio: Add Apple Mac SMC GPIO block
09c00fdd331c Merge tag 'icc-6.17-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/djakov/icc into char-misc-next
ff8150e0b0f2 dt-bindings: i2c: nxp,pnx-i2c: allow clocks property
83fafeb193c6 dt-bindings: i2c: renesas,riic: Document RZ/T2H and RZ/N2H support
bd1edaf90e4d dt-bindings: i2c: renesas,riic: Move ref for i2c-controller.yaml to the end
4fb79a323ffa dt-bindings: rtc: amlogic,a4-rtc: Add compatible string for C3
6911acf4bf27 Merge tag 'riscv-dt-for-v6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt
d6c5bd06ba88 Merge tag 'samsung-drivers-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt
5335c6dec4f1 Merge tag 'arm-sophgo-dt-for-v6.17' of https://github.com/sophgo/linux into soc/newsoc
36beceecc031 Merge tag 'riscv-sophgo-dt-for-v6.17' of https://github.com/sophgo/linux into soc/dt
a94a0024593d dt-bindings: rtc: pcf85063: add binding for RV8063
355ece2bba05 dt-bindings: net: bluetooth: nxp: add support for supply and reset
c94c0ee603b8 dt-bindings: net: bluetooth: nxp: Add support for 4M baudrate
da422e2fd590 ASoC: dt-bindings: qcom,sm8250: Add Fairphone 4 sound card
d443d69fe59a ASoC: dt-bindings: qcom,q6afe: Document q6usb subnode
e1dc5fef731a dt-bindings: dma: fsl-mxs-dma: allow interrupt-names for fsl,imx23-dma-apbx
831ba7ce88cf dt-bindings: dma: Convert marvell,orion-xor to DT schema
d809488a383f dt-bindings: dma: Convert brcm,iproc-sba to DT schema
102be241c4b4 dt-bindings: dma: qcom,gpi: document the Milos GPI DMA Engine
57e8d0f51565 dt-bindings: pinctrl: mediatek: Add support for mt8189
143c71ae555f dt-bindings: net: wireless: rt2800: add SOC Wifi
3b69bcbd0f88 MIPS: dts: ralink: mt7620a: add wifi
b2e237f8d950 dt-bindings: power: rpmpd: Add Glymur power domains
ecb488880deb dt-bindings: leds: ncp5623: Add 0x39 as a valid I2C address
a4e266b64b63 dt-bindings: display: sprd,sharkl3-dsi-host: Fix missing clocks constraints
a4902ad760ba dt-bindings: display: sprd,sharkl3-dpu: Fix missing clocks constraints
9871ccfc7c82 dt-bindings: display: imx: convert fsl,dcu.txt to yaml format
cb3eab704df6 dt-bindings: timer: via,vt8500-timer: Convert to YAML
02bc5b47191f dt-bindings: net: Convert Marvell Armada NETA and BM to DT schema
d2cb17b16fcd arm64: dts: sophgo: Add Duo Module 01 Evaluation Board
e9a69b5764c5 arm64: dts: sophgo: Add Duo Module 01
d46c534cd1a4 arm64: dts: sophgo: Add initial SG2000 SoC device tree
ecee37b0c732 riscv: dts: sophgo: fix mdio node name for CV180X
edeb5fb8a57f riscv: dts: sophgo: sophgo-srd3-10: reserve uart0 device
39cea134a435 riscv: dts: sophgo: add Sophgo SG2042_EVB_V2.0 board device tree
3af1443caa87 riscv: dts: sophgo: add Sophgo SG2042_EVB_V1.X board device tree
d95438e9cc23 dt-bindings: riscv: add Sophgo SG2042_EVB_V1.X/V2.0 bindings
97ff3450b45b riscv: dts: sophgo: add ethernet GMAC device for sg2042
6523097f467e riscv: dts: sophgo: Enable ethernet device for Huashan Pi
9d7ba84277ac riscv: dts: sophgo: Add mdio multiplexer device for cv18xx
5ad41c12bb04 riscv: dts: sophgo: Add ethernet device for cv18xx
9c62ec1b061f riscv: dts: sophgo: sg2044: add pmu configuration
e204a42647dc riscv: dts: sophgo: sg2044: add ziccrse extension
e64ca04dfa1a riscv: dts: sophgo: add zfh for sg2042
af70f42b8563 riscv: dts: sophgo: add ziccrse for sg2042
341c9d72df4f riscv: dts: sophgo: Add xtheadvector to the sg2042 devicetree
867de304b18d riscv: dts: sophgo: sg2044: add PCIe device support for SG2044
084dbab95812 riscv: dts: sophgo: sg2044: add MSI device support for SG2044
f3f305412cd9 riscv: dts: sophgo: add reset configuration for Sophgo CV1800 series SoC
d4c78bf20a68 riscv: dts: sophgo: add reset generator for Sophgo CV1800 series SoC
ca25c70f2e20 dt-bindings: soc: sophgo: Move SoCs/boards from riscv into soc, add SG2000
b116c2ce6c9e riscv: dts: sophgo: sg2044: Add missing riscv,cbop-block-size property
a7465701ba1b riscv: dts: sophgo: add pwm controller for SG2044
2d4c469f3e0c riscv: dts: sophgo: add SG2044 SPI NOR controller driver
6ed1d5df4964 riscv: dts: sophgo: sg2044: Add pinctrl device
0e92ebbc7780 riscv: dts: sophgo: sg2044: Add ethernet control device
f20278d13b83 riscv: dts: sophgo: sophgo-srd3-10: add HWMON MCU device
1ab417f2c6d5 riscv: dts: sophgo: sg2044: Add MMC controller device
5234c1aec3a0 riscv: dts: sophgo: sg2044: add DMA controller device
72423eef988d riscv: dts: sophgo: sg2044: Add I2C device
a82a340b1d6b riscv: dts: sophgo: sg2044: Add GPIO device
733f28e2c1dc riscv: dts: sophgo: sg2044: Add clock controller device
8fa3d034a693 riscv: dts: sophgo: sg2044: Add system controller device
0adb6607aa87 riscv: dts: sophgo: cv18xx: Add RTCSYS device node
551dd312e065 Merge tag 'apple-soc-dt-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/sven/linux into soc/dt
0c7b9e2e286d Merge tag 'at91-dt-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into soc/dt
bd42c1ae49a9 Merge tag 'thead-dt-for-v6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/fustini/linux into soc/dt
773cec14b76e Merge tag 'v6.17-rockchip-dts64-2' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
6daf8e447699 ARM: dts: st: spear: Use generic "ethernet" as node name
515a597ed8c8 Merge tag 'qcom-drivers-for-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers
a7a24115ee9b Merge tag 'memory-controller-drv-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into soc/drivers
3c035ea894fb dt-bindings: riscv: cpus: Add AMD MicroBlaze V 64bit compatible
564f3f7a8a9d Merge tag 'tegra-for-6.17-memory' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/drivers
90505e583326 Merge branch 'newsoc/axiado' into soc/newsoc
d2c0ccccbebb arm64: dts: axiado: Add initial support for AX3000 SoC and eval board
676074106b8d dt-bindings: i3c: cdns: add Axiado AX3000 I3C controller
6ac4d3ce41ab dt-bindings: serial: cdns: add Axiado AX3000 UART controller
007d178e28db dt-bindings: gpio: cdns: add Axiado AX3000 GPIO variant
c2b4468d9adc dt-bindings: gpio: cdns: convert to YAML
5a5a1053ea3b dt-bindings: arm: axiado: add AX3000 EVK compatible strings
10f07517af93 dt-bindings: vendor-prefixes: Add Axiado Corporation
5583ebf434fb Merge tag 'mvebu-dt-6.17-1' of https://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into soc/dt
502759c762d2 Merge tag 'amlogic-arm64-dt-for-v6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux into soc/dt
c839bab293d1 Merge tag 'qcom-arm64-for-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
3fccb04b054a Merge tag 'sunxi-dt-for-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into soc/dt
5507affeb4ce Merge tag 'ti-k3-dt-for-v6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into soc/dt
0390f8569044 Merge tag 'qcom-arm32-for-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
82b6193bcad3 Merge tag 'spacemit-dt-for-6.17-1' of https://github.com/spacemit-com/linux into soc/dt
048993d6cfca Merge tag 'imx-bindings-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt
16c8d6c0186c Merge tag 'imx-dt-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt
200442757655 Merge tag 'imx-dt64-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt
5dbe4280d749 Merge tag 'socfpga_dts_updates_for_v6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into soc/dt
df2b1b31d3ab Merge tag 'tegra-for-6.17-arm64-dt' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt
92326a333c76 Merge tag 'tegra-for-6.17-arm-dt' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt
2e35e6c04a0e Merge tag 'tegra-for-6.17-dt-bindings' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt
0b4b59ce9c57 dt-bindings: qcom: geni-se: describe SA8255p
32ebdce75966 dt-bindings: serial: describe SA8255p
c5b78d58092e Merge branches 'pm-misc' and 'pm-tools'
cb4c9d49e8ae dt-bindings: phy: Convert brcm,sr-usb-combo-phy to DT schema
b71d5d92eed1 dt-bindings: phy: Convert ti,da830-usb-phy to DT schema
7113f012a446 dt-bindings: phy: marvell,mmp2-usb-phy: Drop status from the example
b8380346183a dt-bindings: phy: mixel, mipi-dsi-phy: Allow assigned-clock* properties
bc9f6c56ebf6 dt-bindings: phy: qcom,snps-eusb2: document the Milos Synopsys eUSB2 PHY
e8bf211ef002 dt-bindings: usb: qcom,snps-dwc3: Add Milos compatible
b1b5a102a159 dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Update pcie phy bindings for QCS615
4793916c4605 Merge branch 'icc-milos' into icc-next
ca79b1e41699 Merge tag 'ath-next-20250721' of git://git.kernel.org/pub/scm/linux/kernel/git/ath/ath into wireless-next
4a7813db0edd dt-bindings: thermal: tegra: Document Tegra210B01
647d14815aa7 dt-bindings: thermal: mediatek: Add fallback compatible string for MT7981 and MT8516
8cbb6e090113 dt-bindings: interconnect: document the RPMh Network-On-Chip Interconnect in Qualcomm Milos SoC
c75e65fa1a7a dt-bindings: serial: 8250: spacemit: set clocks property as required
3d801ddabd51 dt-bindings: serial: renesas: Document RZ/V2N SCIF
8004034be86b arm64: dts: apple: Add Apple SoC GPU
372bb0a9270c dt-bindings: gpu: Add Apple SoC GPU
0fd845e2039f arm64: dts: apple: t8012-j132: Include touchbar framebuffer node
def9acb229f9 arm64: dts: apple: Add bit offset to PMIC NVMEM node names
dc4bff407bcd Merge branch 'newsoc/cix-p1' into soc/newsoc
c9853b29c44c arm64: dts: cix: Add sky1 base dts initial support
566f7b29d383 dt-bindings: clock: cix: Add CIX sky1 scmi clock id
2d860dd2a924 dt-bindings: mailbox: add cix,sky1-mbox
4c129f674cb4 dt-bindings: arm: add CIX P1 (SKY1) SoC
ec61ee7dfba5 dt-bindings: vendor-prefixes: Add CIX Technology Group Co., Ltd.
7ebb5edbb224 Merge branch 'newsoc/andes' into soc/newsoc
629e67c23eef Merge tag 'mtk-dts64-for-v6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/dt
d845a9c7f436 Merge tag 'mtk-dts32-for-v6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/dt
8b47485f6798 Merge tag 'omap-for-v6.17/dt-signed' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap into soc/dt
866ff7150b56 Merge tag 'stm32-dt-for-v6.17-1' of https://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into soc/dt
ea5f4eb45cdb Merge tag 'v6.17-rockchip-dts64-1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
09a326b741de arm64: dts: nuvoton: npcm8xx: Drop the GIC "ppi-partitions" node
ca6ab3278201 Merge tag 'aspeed-6.17-devicetree-1' of https://git.kernel.org/pub/scm/linux/kernel/git/bmc/linux into soc/dt
12f66471cea2 Merge tag 'renesas-dts-for-v6.17-tag2' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
ce29d48849d5 Merge tag 'renesas-dt-bindings-for-v6.17-tag2' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
d5a3aec241ba Merge tag 'samsung-dt64-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt
61ffff1eadc1 Merge tag 'samsung-dt-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt
c241df52dbd4 Merge tag 'dt-vt8500-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt into soc/dt
5a97ca254d34 Merge tag 'arm-soc/for-6.17/drivers' of https://github.com/Broadcom/stblinux into soc/drivers
615e5dd1026f Merge tag 'v6.16-rc7' into tty-next
bfb15af09263 riscv: dts: andes: add Voyager board device tree
e75c75ca51e1 riscv: dts: andes: add QiLai SoC device tree
40e05487b65c dt-bindings: timer: add Andes machine timer
96e291cff48a dt-bindings: interrupt-controller: add Andes machine-level software interrupt controller
5a070b8aab00 dt-bindings: interrupt-controller: add Andes QiLai PLIC
23b07e5175ad dt-bindings: riscv: add Andes QiLai SoC and the Voyager board bindings
6f6f2755eb71 Merge tag 'reset-for-v6.17' of https://git.pengutronix.de/git/pza/linux into soc/drivers
d0eccdbd78de spidev: introduce trivial abb sensor device
e899273b9ee5 dt-bindings: trivial-devices: Document ABB sensors
39715dac45f4 PM: docs: Use my kernel.org address in ABI docs and DT bindings
9f70470351fe Merge tag 'v6.16-rc7' into usb-next
4d4776db387d dt-bindings: clock: Add support for i.MX94 LVDS/DISPLAY CSR
9a7abe6a0109 dt-bindings: hwmon: adt7475: Allow and recommend #pwm-cells = <3>
8e0e30e58cfa dt-bindings: trivial: Add tps53685 support
0ba69b597265 dt-bindings: hwmon: pmbus/adp1050: Add adp1051, adp1055 and ltp8800
5538f47fb83b dt-bindings: hwmon: pmbus: ti,ucd90320: Add missing compatibles
70a810c569f2 dt-bindings: hwmon: maxim,max20730: Add maxim,max20710 compatible
684ed1fcb89b dt-bindings: hwmon: lltc,ltc2978: Add lltc,ltc713 compatible
ceb2f4ae7231 dt-bindings: hwmon: ti,lm87: Add adi,adm1024 compatible
6fda8eb1d30f dt-bindings: hwmon: national,lm90: Add missing Dallas max6654 and onsemi nct72, nct214, and nct218
fec5aa716025 dt-bindings: hwmon: amc6821: Add cooling levels
2a3bb1bc029e dt-bindings: hwmon: (pmbus/isl68137) Add RAA229621 support
df9399258d45 dt-bindings: clock: qcom,sm4450-dispcc: Reference qcom,gcc.yaml
a21d5e131452 dt-bindings: clock: qcom,sm4450-camcc: Reference qcom,gcc.yaml
c26aa209d9af dt-bindings: clock: qcom,mmcc: Reference qcom,gcc.yaml
101385caa206 dt-bindings: clock: qcom,sm8150-camcc: Reference qcom,gcc.yaml
bf0ad3272a8d dt-bindings: clock: qcom: Remove double colon from description
5e0de7d92ba1 Merge tag 'iio-for-6.17a' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/jic23/iio into char-misc-next
ed2c0a3539b9 dt-bindings: interconnect: qcom,msm8998-bwmon: Allow 'nonposted-mmio'
16222f5add7f dt-bindings: interconnect: Add EPSS L3 compatible for QCS8300 SoC
26e8a1a26a63 dt-bindings: interconnect: qcom: Remove double colon from description
f3990f2988aa dt-bindings: gpio: Convert qca,ar7100-gpio to DT schema
f4169e8902ba dt-bindings: gpio: Convert maxim,max3191x to DT schema
cc96527c4361 dt-bindings: gpio: fsl,qoriq-gpio: Add missing mpc8xxx compatibles
234beb04554a dt-bindings: gpio: Create a trivial GPIO schema
d5b6bbdd5ea6 dt-bindings: gpio: Convert st,spear-spics-gpio to DT schema
57d91fffc5cb dt-bindings: gpio: Convert abilis,tb10x-gpio to DT schema
baf1be13c404 dt-bindings: gpio: Convert apm,xgene-gpio-sb to DT schema
bb01ffde4219 dt-bindings: gpio: Convert ti,twl4030-gpio to DT schema
7c869e945c1d dt-bindings: gpio: Convert lantiq,gpio-mm-lantiq to DT schema
2d351d673ed0 dt-bindings: gpio: Convert ti,keystone-dsp-gpio to DT schema
d1caee930967 dt-bindings: gpio: Convert altr,pio-1.0 to DT schema
f6b6f6538c88 dt-bindings: gpio: Convert cirrus,clps711x-mctrl-gpio to DT schema
f5b06d065b65 dt-bindings: gpio: Convert cavium,octeon-3860-gpio to DT schema
6ebb1a828301 dt-bindings: gpio: Convert exar,xra1403 to DT schema
2785b36e35cc dt-bindings: gpio: Convert microchip,pic32mzda-gpio to DT schema
b56e20fc40d7 dt-bindings: gpio: Convert lacie,netxbig-gpio-ext to DT schema
3ccc1ca7e0ba Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
8f379560c370 dt-bindings: trivial-devices: Add undocumented hwmon devices
39de5984956e dt-bindings: arm-smmu: Remove sdm845-cheza specific entry
a1ac450f3634 arm64: dts: rockchip: Add maskrom button to NanoPi R5S + R5C
af0325e129ae dt-bindings: thermal: qcom-tsens: document the Milos Temperature Sensor
49cc1296037b dt-bindings: clock: qcom: document the Milos Video Clock Controller
16340601924b dt-bindings: clock: qcom: document the Milos GPU Clock Controller
573f59c35a7e dt-bindings: clock: qcom: document the Milos Display Clock Controller
da3d8ec933a1 dt-bindings: clock: qcom: document the Milos Camera Clock Controller
108d90ed45b5 dt-bindings: clock: qcom: document the Milos Global Clock Controller
b1a99cb677d8 dt-bindings: clock: qcom,x1e80100-gcc: Add missing video resets
9e4ffed3ade8 dt-bindings: clock: qcom,sm8450-videocc: Document X1E80100 compatible
741514539768 dt-bindings: clock: qcom: document the Milos TCSR Clock Controller
97ec633f5480 dt-bindings: clock: qcom: Document the Milos RPMH Clock Controller
6d406a229797 dt-bindings: clock: Add Qualcomm QCS615 Video clock controller
8b50d3c9c410 dt-bindings: clock: Add Qualcomm QCS615 Graphics clock controller
d0090474f382 dt-bindings: clock: Add Qualcomm QCS615 Display clock controller
942ecba2c8f9 dt-bindings: clock: Add Qualcomm QCS615 Camera clock controller
82a322763a4f Merge branch '20250516-ipq5018-cmn-pll-v4-2-389a6b30e504@outlook.com' into clk-for-6.17
9eefab0dfdd5 dt-bindings: clock: qcom: Add CMN PLL support for IPQ5018 SoC
a1b9cfc98bd3 dt-bindings: soc: qcom: qcom,pmic-glink: document Milos compatible
d5da90eccdff dt-bindings: soc: qcom,aoss-qmp: document the Milos Always-On Subsystem side channel
34786aba9ba7 dt-bindings: firmware: qcom,scm: document Milos SCM Firmware Interface
6e113c99e893 dt-bindings: arm: qcom,ids: Add SoC IDs for SM7635 family
fd8cea27d9ae dt-bindings: net: cdns,macb: Add external REFCLK property
aec48256a2ff dt-bindings: thermal: rockchip: document otp thermal trim
328772974a15 dt-bindings: rockchip-thermal: Add RK3576 compatible
19f989a5bd1d MIPS: mobileye: eyeq5: add two GPIO bank nodes
6b4ac8add716 MIPS: mobileye: eyeq5: add evaluation board I2C temp sensor
4fd343c406b0 MIPS: mobileye: eyeq5: add 5 I2C controller nodes
e68a2aba902d dt-bindings: watchdog: nxp,pnx4008-wdt: allow clocks property
9c8255dc203b riscv: dts: starfive: jh7110-common: add status power led node
22723d632890 riscv: dts: starfive: jh7110-milkv-mars sort properties
e455f730d5b8 dt-bindings: nvmem: convert vf610-ocotp.txt to yaml format
5e169c37d95c dt-bindings: nvmem: mediatek: efuse: split MT8186/MT8188 from base version
7a10c41bf9e8 dt-bindings: nvmem: SID: Add binding for A523 SID controller
cbc42a476e75 dt-bindings: nvmem: convert lpc1857-eeprom.txt to yaml format
abc73f36bf9d dt-bindings: nvmem: fixed-layout: Allow optional bit positions
813b29da2d55 ASoC: dt-bindings: qcom,lpass-va-macro: Define clock-names in top-level
c33c7fb45109 dt-bindings: display: Add Sitronix ST7567 LCD Controller
c9198fbc442e dt-bindings: soc: samsung: exynos-sysreg: add hsi2 for ExynosAutov920
8cd3784e53b6 spi: dt-bindings: spi-mux: Drop "spi-max-frequency" as required
a08ba8cf59b0 dt-bindings: PCI: qcom: Move PHY & reset GPIO to Root Port node
8ab2a8849856 dt-bindings: PCI: qcom,pcie-sa8255p: Document ECAM compliant PCIe root complex
e7eea35f2725 arm64: dts: rockchip: Drop regulator-compatible property on rk3399
1fd0e3d44d5a arm64: dts: rockchip: Drop unneeded address+size-cells on px30
43cbc3eb401a arm64: dts: rockchip: Fix LCD panel port on rk3566-pinetab2
d654d06cfa41 arm64: dts: rockchip: Move mipi_out node on rk3399 haikou demo dtso
2e4252d482d0 arm64: dts: rockchip: Simplify mipi_out endpoint on rk3399 RP64 dtso
34b2c6e27343 arm64: dts: rockchip: Simplify edp endpoints on several rk3399 boards
c824fe70648a arm64: dts: rockchip: Simplify VOP port definition on rk3328
fa7552a02970 dt-bindings: usb: convert lpc32xx-udc.txt to yaml format
c80a7e0d3ea3 ARM: dts: broadcom: Fix bcm7445 memory controller compatible
1ef58d48a6ef dt-bindings: display: panel: samsung,atna30dw01: document ATNA30DW01
e77e4c64d3aa arm64: dts: allwinner: a523: enable Mali GPU for all boards
bf3f984838fb arm64: dts: allwinner: a523: add Mali GPU node
497e5ea363fe arm64: dts: allwinner: a523: Add power controller device nodes
9467e9442c85 Merge branch 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/linux-pm into sunxi/dt-for-6.17
cc2d2d0d56f2 dt-bindings: mmc: sdhci-msm: document the Milos SDHCI Controller
b028e9e71dbc dt-bindings: power: Add A523 PPU and PCK600 power controllers
a266236fefcb arm64: dts: rockchip: Move dsi address+size-cells from SoC to rk3399 boards
ab7cf99a1f4a arm64: dts: rockchip: Move dsi address+size-cells from SoC to px30 boards
f8d95046048f dt-bindings: display: rockchip,dw-mipi-dsi: Drop address/size cells
597bb0d8411a dt-bindings: arm-smmu: document the support on Milos
ee596924f1a1 arm64: dts: rockchip: Fix UART DMA support for RK3528
01647aa1b636 arm64: dts: rockchip: Add reset button to NanoPi R5S
a74d4de252fd arm64: dts: rockchip: Add rtc0 alias for NanoPi R5S + R5C
46a8ca674cfa dt-bindings: interrupt-controller: Convert apm,xgene1-msi to DT schema
e07aac30910c dt-bindings: gpu: mali-bifrost: Add Allwinner A523 compatible
609204d3eec9 docs: dt: writing-schema: Document preferred order of properties
91dffad70433 docs: dt: writing-bindings: Document discouraged instance IDs
7d0a75ec87a1 docs: dt: writing-bindings: Document compatible and filename naming
ce2424aea4e8 docs: dt: submitting-patches: Avoid 'YAML' in the subject and add an example
cfcbcd138f50 dt-bindings: iio: proximity: Add Nicera D3-323-AA PIR sensor
1dc1537a1cfc dt-bindings: vendor-prefixes: Add Nicera
50d9d6206314 dt-bindings: iio: adc: Add support for MT7981
e3979d4e5a71 dt-bindings: iio: adc: Add AD4170-4
d56febcf05e4 dt-bindings: pinctrl: stm32: Introduce HDP
fad75c97710c Add RPMh regulator support for PM7550 & PMR735B
02ea21d540c3 ASoC: codec: Convert to GPIO descriptors for
89d0b8fce36f regulator: dt-bindings: qcom,rpmh: Add PMR735B compatible
c8bd9fcae9a0 regulator: dt-bindings: qcom,rpmh: Add PM7550 compatible
d4e6b1fb0783 dt-bindings: iio: adc: mt6359: Add MT6373 PMIC AuxADC
098202eec4e1 dt-bindings: iio: adc: mt6359: Add MT6363 PMIC AuxADC
1697eb314369 arm64: dts: imx8q: add camera ov5640 support for imx8qm-mek and imx8qxp-mek
28dbe992a899 arm64: dts: altera: socfpga_stratix10: update internal oscillators
df7e566fd9d3 arm64: dts: socfpga: swvp: remove phy-addr in the GMAC node
58018d66ed16 arm64: dts: socfpga: swvp: remove cpu1-start-addr
ed76c055b420 arm64: dts: socfpga: swvp: remove altr,modrst-offset
aec88103429c arm64: dts: socfpga: stratix10: fix dtbs_check for rstmgr
39d9a2cbc5e5 arm64: dts: socfpga: agilex: fix dtbs_check warning for f2s-free-clk
ef70c327c3f6 arm64: dts: allwinner: A523: Add SID controller node
752c7e4e2720 arm64: dts: allwinner: a133-liontron-h-a133l: Add Ethernet support
fae71aaf339e arm64: dts: allwinner: a100: Add EMAC support
b38274d492ca arm64: dts: allwinner: a100: Add pin definitions for RGMII/RMII
ed798b2f7978 media: dt-bindings: rockchip: Add RK3576 Video Decoder bindings
8a915333fc1e media: dt-bindings: rockchip: Document RK3588 Video Decoder bindings
9b65179d600c dt-bindings: pinctrl: document the Milos Top Level Mode Multiplexer
fb32a87d3875 dt-bindings: pinctrl: qcom,pmic-gpio: Add PM7550 support
9391657b90c6 dt-bindings: pinctrl: qcom,pmic-gpio: Add PMIV0104 support
d655238fffbd ARM: tegra: chagall: Add embedded controller node
8f97653e1318 ARM: tegra: Add device-tree for Asus Portable AiO P1801-T
800285ab20bb dt-bindings: arm: tegra: Add Asus Portable AiO P1801-T
2a2952b67a2e arm64: tegra: Add p3971-0089+p3834-0008 support
ce7e69af42ca arm64: tegra: Add memory controller on Tegra264
a81e86db62db arm64: tegra: Add Tegra264 support
a6689e2bd732 dt-bindings: arm: tegra: Add Asus VivoTab RT TF600T
776d06cf806e dt-bindings: Add Tegra264 clock and reset definitions
536f700e61e8 dt-bindings: tegra: Document P3971-0089+P3834-0008 Platform
c9998640b0fc dt-bindings: rtc: tegra: Document Tegra264 RTC
9aacfd76da1d dt-bindings: dma: Add Tegra264 compatible string
7def90ff5f38 dt-bindings: misc: Document Tegra264 APBMISC compatible
a59edbcea209 dt-bindings: firmware: Document Tegra264 BPMP
26008a3fa73f dt-bindings: mailbox: tegra-hsp: Properly sort compatible string list
ac67362457ac dt-bindings: mailbox: tegra-hsp: Bump number of shared interrupts
88181419846e dt-bindings: memory: tegra: Add Tegra264 support
80cb84e4d5a7 dt-bindings: tegra: pmc: Add Tegra264 compatible
44788ad15192 arm64: dts: rockchip: describe the OV8858 user camera on PinePhone Pro
f48d16bc01ed arm64: dts: rockchip: describe I2c Bus 1 and IMX258 world camera on PinePhone Pro
624791f8d74a arm64: dts: rockchip: Fix pinctrl node names for RK3528
2a7b4ab8ef90 arm64: dts: rockchip: Add FriendlyElec NanoPi M5 support
75ac9bbd660a dt-bindings: arm: rockchip: add FriendlyElec NanoPi M5 board
d9c568906be1 arm64: dts: rockchip: force PMIC reset behavior to restart PMU on RK3588 Tiger
8bd14566b75f arm64: dts: rockchip: force PMIC reset behavior to restart PMU on RK3588 Jaguar
0e417bfcbc38 arm64: dts: rockchip: add header for RK8XX PMIC constants
5cdc97a0faf8 arm64: dts: rockchip: add HDMI audio on ROCK 4D
d2defdc9b0c3 arm64: dts: rockchip: theoretically enable Wi-Fi on ROCK 4D
7200ec33cb56 arm64: dts: rockchip: complete USB nodes on ROCK 4D
ac5675c9dfae arm64: dts: rockchip: adjust dcin regulator on ROCK 4D
71bbd4df5a38 arm64: dts: Add DTS for Marvell PXA1908 and samsung,coreprimevelte
c3eb8bf27be6 dt-bindings: marvell: Document PXA1908 SoC and samsung,coreprimevelte
3dbe8d040691 dt-bindings: mmc: sdhci-pxa: restrict pinctrl to pxav1
256a25acb085 arm64: dts: freescale: imx8mp-toradex-smarc: remove gpio hog
4875356dd0d1 arm64: dts: freescale: imx8mp-toradex-smarc: fix lvds dsi mux gpio
7e16a47c774f arm64: dts: imx8mm-venice-gw7904: Increase HS400 USDHC clock speed
958eae2d29ea arm64: dts: imx8mm-venice-gw7903: Increase HS400 USDHC clock speed
3b94e93f86e6 arm64: dts: imx8mn-venice-gw7902: Increase HS400 USDHC clock speed
a81c22fbb48a arm64: dts: imx8mm-venice-gw7902: Increase HS400 USDHC clock speed
59d34e1fa7de arm64: dts: imx8mm-venice-gw7901: Increase HS400 USDHC clock speed
e1cf73b27bcb arm64: dts: imx8mp-venice-gw702x: Increase HS400 USDHC clock speed
0edd7bba0263 arm64: dts: imx8mm-venice-gw700x: Increase HS400 USDHC clock speed
9820a07342b0 arm64: dts: lx2160a-qds: add the two on-board RGMII PHYs
16382fa39594 arm64: dts: add imx95-libra-rdk-fpsc board
8a6f28dab39c arm64: dts: imx8q: add linux,cma node for imx8qm-mek and imx8qxp-mek
ba73343b8812 arm64: dts: imx8: add capture controller for i.MX8's img subsystem
ea6b32baf520 arm64: dts: imx95: add jpeg encode and decode nodes
2a4634dc728b arm64: dts: imx93-phyboard-nash: Add PEB-WLBT-07 overlay
c080e7b9ddda arm64: dts: imx93-phyboard-segin: Add PEB-WLBT-05 overlay
1f7892023ef4 arm64: dts: imx93-phyboard-segin: Add PEB-EVAL-01 overlay
faa5aade74a9 arm64: dts: imx93-phycore-som: Add RPMsg overlay
07780fa4aed1 arm64: dts: freescale: tqmls10xx: Add vdd-supply for spi-nor flash
8e3492338e8b arm64: dts: freescale: tqmls10xx-mbls10xxa: Add vdd-supply for i2c mux
271103d977c9 arm64: dts: tqmls1046a: Enable SFP interfaces
25f7bd3b4a47 arm64: dts: tqmls1043a: Enable SFP interface
54f5caa98df8 arm64: dts: tqmls10xxa: Move SFP cage definition to common place
e715bb94e263 arm64: dts: fsl-ls1088a: Remove superfluous address and size cells
c82c1751f804 arm64: dts: fsl-ls1046a: Remove superfluous address and size cells
ebcd19d6347a arm64: dts: fsl-ls1043a: Remove superfluous address and size cells
17c7cc47affb arm64: dts: imx94: add missing clock related properties to flexcan1
d60633ab78a3 arm64: dts: imx8mn: Configure DMA on UART2
7d4ebc6b315b arm64: dts: imx8mm: Configure DMA on UART2
6d1fccdc8f60 arm64: dts: fsl-ls1046a: Add missing DMA entries for I2C & LPUART
7495eeebbd34 arm64: dts: fsl-ls1043a: Add missing DMA entries for I2C & LPUART
e06f4e76e905 arm64: dts: freescale: imx93-phycore-som: Add watchdog ext-reset-output pin
d58bd9b4a79b arm64: dts: imx8mn-beacon: Fix HS400 USDHC clock speed
c694a7bc8cf3 arm64: dts: imx8mm-beacon: Fix HS400 USDHC clock speed
6743b8d488e1 arm64: dts: tqma8mpql-mba8mpxl-lvds: Rename overlay to include display name
a37af13d15c8 arm64: dts: imx8qm-mek: support revd board's wm8962 codec
7a3fbd740ca5 arm64: dts: imx8qxp-mek: support wcpu board's wm8962 codec
7e34086585b9 arm64: dts: imx8mp-evk: Use fsl-asoc-card to replace simple card
83f3bf720be9 arm64: dts: imx93: add edma error interrupt support
ebf5c781f77d arm64: dts: freescale: imx8mp-toradex-smarc: add fan cooling levels
181479b67e8a arm64: dts: imx8mp: Configure VPU clocks for overdrive
59f683a9ab68 arm64: dts: imx8mp-nominal: Explicitly configure nominal VPU clocks
8a232cb5a7fa arm64: dts: imx8mp: fix VPU_BUS clock setting
eb10431b8e66 arm64: dts: imx8mp: drop gpcv2 vpu power-domains and clocks
60e50a08da9b arm64: dts: freescale: imx8qxp/imx8qm: Add CAAM support
a248219a8875 ARM: dts: mediatek: add basic support for Lenovo A369i board
bfd569da9873 ARM: dts: mediatek: add basic support for JTY D101 board
2a4d4ef273b2 ARM: dts: mediatek: add basic support for MT6572 SoC
23404121bdd4 dt-bindings: arm: mediatek: add boards based on the MT6572 SoC
a4c8dd9520f6 dt-bindings: vendor-prefixes: add JTY
e0c23527ba98 dt-bindings: watchdog: mediatek,mtk-wdt: add MT6572
b2b61a2db095 dt-bindings: interrupt-controller: mediatek,mt6577-sysirq: add MT6572
804ab7c7d85d ARM: dts: imx6-gw: Replace license text comment with SPDX identifier
03bac12b32b2 ARM: dts: imx6ul-kontron-sl-common: Fix QSPI NAND node name
ad2593118243 ARM: dts: imx6ul-kontron-sl-common: Add SPI NOR partitions
4885f805e158 ARM: dts: imx6ul-kontron-bl-common: Fix RTS polarity for RS485 interface
d1b91e76690e dt-bindings: add imx95-libra-rdk-fpsc
a0409bf40ae5 arm64: dts: ti: k3-am69-sk: Add idle-states for remaining SERDES instances
673bf0fe91bc arm64: dts: ti: k3-am62a7-sk: add boot phase tags
0b61c356e6ad arm64: dts: ti: k3-am654-base-board: add boot phase tags
7d711c316bdb arm64: dts: ti: k3-am65: add boot phase tags
e177b1c9de01 dt-bindings: clock: ast2600: Add reset definitions for MAC1 and MAC2
1c5060689b34 dt-bindings: net: ftgmac100: Add resets property
5193dd5fa141 dt-bindings: net: sophgo,sg2044-dwmac: Add support for Sophgo SG2042 dwmac
5ce5f07b5508 dt-bindings: net: dsa: mediatek,mt7530: add internal mdio bus
583ebba08917 dt-bindings: net: dsa: mediatek,mt7530: add dsa-port definition for mt7988
0f557ac7ccfe dt-bindings: net: mediatek,net: add sram property
cffbaf9b81e2 dt-bindings: net: mediatek,net: allow irq names
a76ffe63b15c dt-bindings: net: mediatek,net: allow up to 8 IRQs
6bb228560999 dt-bindings: net: mediatek,net: update mac subnode pattern for mt7988
97de60cfbce0 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
b9da9213ade8 arm64: dts: st: remove empty line in stm32mp251.dtsi
64063fff5ffb arm64: dts: st: fix timer used for ticks
4c7a19b4cb33 regulator: Merge tps6594 driver changes
daad99af0822 dt-bindings: mfd: ti,tps6594: Add TI TPS652G1 PMIC
8386b729544f dt-bindings: media: cdns,csi2rx.yaml: Add optional interrupts for cdns-csi2rx
b29392c6d2f8 arm64: dts: rockchip: Enable HDMI receiver on RK3588 EVB1
d54023e2d503 arm64: dts: rockchip: fix PHY handling for ROCK 4D
a3f230874d3a arm64: dts: rockchip: Enable mipi dsi on rk3568-evb1-v10
cf9888548489 arm64: dts: rockchip: Add UFS support on the ROCK 4D
7903089bd476 arm64: dts: ti: k3-am69-sk: Add bootph-all property to enable Ethernet boot
24844a9efccd arm64: dts: ti: k3-j722s-evm: Add bootph-all property to enable Ethernet boot
f4fdd87dbb41 arm64: dts: ti: k3-am62p5-sk: Add bootph-all property to enable Ethernet boot
3939a611e8bc arm64: dts: ti: k3-am68-sk-base-board: Add bootph-all property to enable Ethernet boot
a3f5e9fa0441 arm64: dts: ti: Add support for AM62D2-EVM
7a38d687cc98 arm64: dts: ti: Add pinctrl entries for AM62D2 family of SoCs
f2166a890cbb dt-bindings: arm: ti: Add AM62D2 SoC and Boards
aa589db3ac8e arm64: dts: ti: Add bootph property to nodes at source for am62a
24acc0cda0ca dt-bindings: ethernet-phy: add MII-Lite phy interface type
de5faa29496a dt-bindings: dpll: Add support for Microchip Azurite chip family
be3edb0ba9c7 dt-bindings: dpll: Add DPLL device and pin
6951965726e3 dt-bindings: net: Add support for Sophgo CV1800 dwmac
57ec540c0009 dt-bindings: memory: renesas,rzg3e-xspi: Document RZ/V2H(P) and RZ/V2N support
397d62e38e6d dt-bindings: arm: sunxi: Combine board variants into enums
94f9ccddf8d2 ARM: tegra: Add device-tree for ASUS VivoTab RT TF600T
966adacf22f9 dt-bindings: serial: rsci: Update maintainer entry
311412a89e25 dt-bindings: serial: renesas,rsci: Add optional secondary clock input
107315cef7f1 dt-bindings: serial: sh-sci: Document r8a78000 bindings
49773b5da84b dt-bindings: power: qcom,rpmpd: document the Milos RPMh Power Domains
89e711f0ab70 arm64: dts: ti: k3-am62p-verdin: Adjust temperature trip points
6d8d2fd35d79 arm64: dts: ti: k3-am62p-j722s: Enable freq throttling on thermal alert
96816c0c1cda Merge tag 'pm-runtime-6.17-rc1' of https://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
4c2695cf19b3 arm64: dts: ti: k3-j784s4-j742s2-main-common: Add PBIST_14 node
8d9287a162e7 dt-bindings: soc: ti: bist: Add BIST for K3 devices
2708025daa67 arm64: dts: ti: k3-am62-main: Remove eMMC High Speed DDR support
3112e1658091 arm64: dts: ti: k3-am62*: Move eMMC pinmux to top level board file
6dfe3e70a454 arm64: dts: ti: k3-am62a7-sk: fix pinmux for main_uart1
b74625437e2b riscv: dts: spacemit: Move eMMC under storage-bus for K1
106a2d7182d9 riscv: dts: spacemit: Move UARTs under dma-bus for K1
37db9248d762 riscv: dts: spacemit: Add DMA translation buses for K1
d9accb54a587 riscv: dts: spacemit: add pwm14_1 pinctrl setting
0603708cb366 riscv: dts: spacemit: add PWM support for K1 SoC
23afee5fb806 arm64: dts: ti: k3-am62p-verdin: fix PWM_3_DSI GPIO direction
e05ddcb61514 arm64: dts: ti: k3-pinctrl: Enable Schmitt Trigger by default
d8f96fe1e4b5 dt-bindings: net: altr,socfpga-stmmac.yaml: add minItems to iommus
e38f508615bd net: dt-bindings: ixp4xx-ethernet: Support fixed links
75d68220cfff dt-bindings: interrupt-controller: Add Arm GICv5
33b7328bd67b Merge tag 'drm-msm-next-2025-07-05' of https://gitlab.freedesktop.org/drm/msm into drm-next
10794b789986 docs: dt: writing-bindings: Consistently use single-whitespace
86a9bf4c4443 docs: dt: writing-bindings: Express better expectations of "specific"
0c8f9e02cd3b docs: dt: writing-bindings: Rephrase typical fallback (superset) usage
0f6503d69ae6 arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable serial NOR FLASH
add55fc9ed19 arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Enable serial NOR FLASH
7cd8bb1dc1cc arm64: dts: renesas: r9a09g057: Add XSPI node
531f2d9725b7 arm64: dts: renesas: r9a09g056: Add XSPI node
84f1df18dc5f Merge tag 'renesas-r9a09g057-dt-binding-defs-tag4' into renesas-dts-for-v6.17
a4a0bc4dc3e9 arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Fix pinctrl node name for GBETH1
8b67347d881d arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Fix pinctrl node name for GBETH1
66af74e1aa4d arm64: dts: renesas: rzg3e-smarc-som: Enable eth{0-1} (GBETH) interfaces
c813a6ce829d arm64: dts: renesas: r9a09g047e57-smarc: Add gpio keys
eb1e7e4e9e6e dt-bindings: rtc: nxp,lpc1788-rtc: add compatible string nxp,lpc1850-rtc
d9c9432709dc dt-bindings: rtc: move nxp,lpc3220-rtc to separated file from trivial-rtc.yaml
f7e641cf0882 dt-bindings: Move sophgo,cv1800b-rtc to rtc directory
c2ccc8724b7a arm: dts: ti: omap: Fixup pinheader typo
e6a0b772cb05 ARM: dts: am335x-pdu001: Fix RS-485 transceiver switching
40e9787d1816 ASoC: soc-dapm: cleanups
01c983755f54 ARM: dts: marvell: kirkwood: use recent scl/sda gpio bindings
75df38d090a6 arm64: dts: mediatek: mt8395-genio-1200-evk: Add MT6359 PMIC key support
3a6357e27ba7 arm64: dts: mediatek: mt8390-genio-common: Add Home MT6359 PMIC key support
6a3deb51c9b5 arm64: dts: mediatek: mt7988a-bpi-r4: add gpio leds
c7292550d3ab ARM: dts: imx6-karo: Replace license text comment with SPDX identifier
c134c3be2c58 arm64: dts: s32g: Add USB device tree information for s32g2/s32g3
8faccf139224 dt-bindings: usb: Add compatible strings for s32g2/s32g3
32caa97af9bf dt-bindings: gpio: pca95xx: add TI TCA6418
7158638bb3cd arm64: dts: mediatek: mt7988a-bpi-r4: drop unused pins
a2a08c044349 arm64: dts: mediatek: mt7988a-bpi-r4: add proc-supply for cci
240182754e31 arm64: dts: mediatek: mt7988: add cci node
6e93e2385a19 dt-bindings: interconnect: add mt7988-cci compatible
74844cb5275e arm64: dts: airoha: en7581: Add ethernet nodes to EN7581 SoC evaluation board
8289107f1c92 arm64: dts: mediatek: mt8192-asurada-spherion: Mark trackpads as fail-needs-probe
e4519cc918c5 arm64: dts: mediatek: mt8186: Add Squirtle Chromebooks
f8de516be111 arm64: dts: mediatek: mt8186: Merge Voltorb device trees
034615aac7eb arm64: dts: mediatek: mt8186-steelix: Mark second source components for probing
b0b73c2d7ae7 dt-bindings: arm: mediatek: Add MT8186 Squirtle Chromebooks
6b59c9ae290e dt-bindings: arm: mediatek: Merge MT8186 Voltorb entries
ae2638c7d641 Merge tag 'pm-runtime-6.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm into gpio/for-next
bc9b5bf851b3 dt-bindings: pwm: Convert lpc32xx-pwm.txt to yaml format
56458f97f58d dt-bindings: pwm: argon40,fan-hat: Document Argon40 Fan HAT
5ec6557630fd dt-bindings: vendor-prefixes: Document Argon40
71c5a4bb4e89 dt-bindings: pwm: mediatek,mt2712-pwm: Add support for MT6991/MT8196
6240e06fc3e5 dt-bindings: pwm: convert lpc1850-sct-pwm.txt to yaml format
b535e7088d2f dt-bindings: pwm: adi,axi-pwmgen: Update documentation link
69d7e2a442d2 dt-bindings: pwm: sophgo: Add pwm controller for SG2044
af64f85f74b4 riscv: dts: sifive: unleashed/unmatched: Remove PWM controlled LED's active-low properties
e0be156f6035 dt-bindings: pwm: marvell,pxa-pwm: Add SpacemiT K1 PWM support
e49654c2f279 Merge tag 'pm-runtime-6.17-rc1'
b24aeebf87a0 arm64: dts: allwinner: t527: Add OrangePi 4A board
7f5a1f6e1eb9 arm64: dts: allwinner: a523: Add UART1 pins
952f9cbd7af1 arm64: dts: allwinner: a523: Move rgmii0 pins to correct location
ad8576fad7d4 arm64: dts: allwinner: a523: Move mmc nodes to correct position
15e4d9212ce3 dt-bindings: arm: sunxi: Add Xunlong OrangePi 4A board
12336bf96c72 dt-bindings: iio: adc: nxp,lpc3220-adc: allow clocks property
e65cbadc0548 dt-bindings: iio: adc: ad4851: add spi-3wire
4d9c51edc9b9 arm64: dts: exynos7870-j6lte: reduce memory ranges to base amount
e086fd8876f5 arm64: dts: exynos7870-on7xelte: reduce memory ranges to base amount
9d9c6611c451 arm64: dts: exynos7870: add quirk to disable USB2 LPM in gadget mode
208cce5857c4 ARM: dts: microchip: sama7g5: Add cache configuration for cpu node
509b99826913 ARM: dts: microchip: sama7d65: Add cache configuration for cpu node
f3d0e33299fd ARM: dts: microchip: sama5d4: Update the cache configuration for CPU
8941fbf6ba5b ARM: dts: microchip: sama5d3: Update the cache configuration for CPU
2eff3303da8d ARM: dts: microchip: sama5d2: Update the cache configuration for CPU
e7b18d4c2364 Merge merge point of tag 'usb-6.16-rc5' into usb-next
c38da1ad3c4f dt-bindings: opp: adreno: Update regex of OPP entry
677b04f5438a dt-bindings: power: qcom,rpmpd: add Turbo L5 corner
e31a0e2df6d3 arm64: dts: amlogic: Enable the npu node for Alta and VIM3
607ef22a465f dts: arm64: amlogic: add S6 pinctrl node
9211f8207ece dts: arm64: amlogic: add S7D pinctrl node
ab5a66e09833 dts: arm64: amlogic: add S7 pinctrl node
15aac295b6bc arm64: dts: amlogic: Add Ugoos AM3
79c971501356 dt-bindings: arm: amlogic: Add Ugoos AM3
a6dec074934f arm64: dts: amlogic: Align wifi node name with bindings
a21c94e943cb dt-bindings: display/msm: qcom,sm8750-mdss: Add SM8750
109b054c5d62 dt-bindings: display/msm: qcom,sm8650-dpu: Add SM8750
d58d7037c611 dt-bindings: display/msm: dp-controller: Add SM8750
79c555201895 dt-bindings: display/msm: dsi-controller-main: Add SM8750
02e87e911953 dt-bindings: display/msm: dsi-phy-7nm: Add SM8750
792e2ba64bb0 ARM: dts: stm32: add stm32mp157f-dk2 board support
69778818ec62 dt-bindings: arm: stm32: add STM32MP157F-DK2 board compatible
7643ccce963f ARM: dts: stm32: optee async notif interrupt for MP15 scmi variants
5b0e91604398 ARM: dts: stm32: use internal regulators bindings for MP15 scmi variants
bf70ebd8ffe1 dt-bindings: regulator: Add STM32MP15 SCMI regulator identifiers
c76df445d8e2 ARM: dts: stm32: use 'typec' generic name for stusb1600 on stm32mp15xx-dkx
475d705400c1 ARM: dts: stm32: fullfill diversity with OPP for STM32M15xF SOCs
4bb10d43e4dc ARM: dts: stm32: add system-clock-direction-out on stm32mp15xx-dkx
b0cec331ce90 arm64: dts: st: add timer nodes on stm32mp257f-ev1
3784048145a5 arm64: dts: st: add timer pins for stm32mp257f-ev1
2030d965c281 arm64: dts: st: add timer nodes on stm32mp251
5e0382c920e9 ARM: dts: stm32: Add nvmem-cells to ethernet nodes for constant mac-addresses
7f41efee603f Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
1210620aaa38 arm64: dts: ti: k3-am62p-verdin: add SD_1 CD pull-up
49fb938f2aa0 ARM: dts: aspeed: yosemite4: add gpio name for uart mux sel
f80c1ece0727 ARM: dts: aspeed: santabarbara: Add Meta Santabarbara BMC
5739123deb47 dt-bindings: arm: aspeed: add Meta Santabarbara board
17e841eb8a01 ARM: dts: aspeed: bletchley: enable USB PD negotiation
6c20b3c5da78 ARM: dts: aspeed: lanyang: Fix 'lable' typo in LED nodes
ac274dd83da4 ARM: dts: aspeed: harma: add mmc health
5f776e456b95 ARM: dts: aspeed: Harma: revise gpio bride pin for battery
285c16da7d59 ARM: dts: aspeed: harma: add ADC128D818 for voltage monitoring
707670385616 ARM: dts: aspeed: harma: add fan board I/O expander
5cdab6370fb5 ARM: dts: aspeed: harma: add E1.S power monitor
4ac3caeab4d6 ARM: dts: aspeed: catalina: Enable MCTP for frontend NIC management
4acc31107f44 Merge tag 'drm-misc-next-2025-07-03' of https://gitlab.freedesktop.org/drm/misc/kernel into drm-next
3dfcfb15f3a4 riscv: dts: spacemit: add reset support for the K1 SoC
b1de41ddb12c Merge tag 'spacemit-reset-binding-for-6.17-1' of https://github.com/spacemit-com/linux
990c4c25e751 dt-bindings: pinctrl: stm32: Add missing blank lines
e6da1f46eb46 dt-bindings: pinctrl: convert nxp,lpc1850-scu.txt to yaml format
bfffde04584b arm64: dts: qcom: sm8150: Drop unrelated clocks from PCIe hosts
bccba5ad2d5e arm64: dts: qcom: sc8180x: Drop unrelated clocks from PCIe hosts
7d4d5736e895 dt-bindings: watchdog: fsl-imx-wdt: add compatible string fsl,ls1046a-wdt
3bd76858e231 Merge tag 'arm-soc/for-6.17/devicetree-arm64' of https://github.com/Broadcom/stblinux into soc/dt
e5d755023dc6 ARM: dts: lpc32xx: Add #pwm-cells property to the two SoC PWMs
5c1cfc4da7e7 Merge tag 'arm-soc/for-6.17/devicetree' of https://github.com/Broadcom/stblinux into soc/dt
376d0636861a dt-bindings: mtd: jedec,spi-nor: Add atmel,at26* compatible string
fe2b22926763 Merge tag 'renesas-dts-for-v6.17-tag1' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
5aaa6a166e8d Merge tag 'renesas-dt-bindings-for-v6.17-tag1' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
7a374a9fc8f9 arm64: dts: cavium: thunder2: Add missing PL011 "uartclk"
9b8b632ab773 arm64: dts: lg: Add missing PL011 "uartclk"
1840478bd82c arm64: dts: lg: Refactor common LG1312 and LG1313 parts
da6dbfcc7301 dt-bindings: soc: spacemit: define spacemit,k1-ccu resets
bb90348d29a9 dt-bindings: mmc: Add sdhci compatible for qcs8300
0414ba944436 spi: dt-bindings: Convert marvell,orion-spi to DT schema
a56bc205230f dt-bindings: mmc: loongson,ls2k0500-mmc: Add compatible for Loongson-2K2000
3cc034e85df9 dt-bindings: mmc: Add Loongson-2K SD/SDIO/eMMC controller binding
dcdc40b6d229 mips: dts: qca: add wmac support
c66d6090a834 MIPS: mobileye: dts: eyeq5: add the emmc controller
cec254c8523d MIPS: mobileye: dts: eyeq6h: add the emmc controller
611c15d5e513 dt-bindings: mmc: renesas,sdhi: Document RZ/T2H and RZ/N2H support
c824773bddb3 dt-bindings: reset: Convert snps,dw-reset to DT schema
86485ac1b19d dt-bindings: media: qcom,x1e80100-camss: Fix isp unit address
728f8edb14ff dt-bindings: media: qcom,x1e80100-camss: Remove clock-lanes port property
7a573d543274 dt-bindings: media: qcom,x1e80100-camss: Add optional bus-type property
775c0a28cdd1 dt-bindings: media: qcom,x1e80100-camss: Tighten the property regex pattern
e73fc4fe22c1 Merge tag 'ib-mfd-gpio-input-pwm-v6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd into gpio/for-next
2cdc59469372 dt-bindings: net: Convert socfpga-dwmac bindings to yaml
03396f2ec6d3 arm64: dts: renesas: Add CN15 eMMC and SD overlays for RZ/V2H and RZ/V2N EVKs
b581622620e9 arm64: dts: renesas: r8a779h2: Add Gray Hawk Single support
8c9f5b0429a2 arm64: dts: renesas: Add Renesas R8A779H2 SoC support
2b6093a18f87 arm64: dts: renesas: Factor out Gray Hawk Single board support
c8fc0b439820 dt-bindings: soc: renesas: Document R-Car V4M-7 Gray Hawk Single
ec22ed6659ed Merge tag 'renesas-r9a09g057-dt-binding-defs-tag4' into renesas-clk-for-v6.17
64c19295dba9 Merge tag 'renesas-r9a09g087-dt-binding-defs-tag2' into renesas-clk-for-v6.17
8fef4f6b3495 dt-bindings: clock: renesas,r9a09g077/87: Add SDHI_CLKHS clock ID
0f1bcc2d243a dt-bindings: clock: renesas,r9a09g056/57-cpg: Add XSPI core clock
4380d39a0bfd ARM: dts: sun8i: v3: Add RGB666 LCD PD pins definition
d4241e745089 ARM: dts: sun8i: v3s: Add RGB666 LCD PE pins definition
6b354c7e0cba mips: dts: realtek: Add gpio block
c0d0aedd3de9 mips: dts: realtek: Add watchdog
dae2bc5616a8 mips: dts: realtek: Add switch interrupts
38394a11dfec mips: dts: cameo-rtl9302c: Add switch block
e4d0f8f0b485 MIPS: dts: ralink: gardena_smart_gateway_mt7688: Fix power LED
53804508fc88 MIPS: dts: ralink: mt7628a: Update watchdog node according to bindings
96b1d8882b30 MIPS: dts: ralink: mt7628a: Fix sysc's compatible property for MT7688
3a5d39e27fb7 dt-bindings: clock: mediatek,mtmips-sysc: Adapt compatible for MT7688 boards
e2714b69d705 ASoC: dt-bindings: qcom,sm8250: Add QCS8275 sound card
93001f7dcb85 ARM: dts: imx6ul: support Engicam MicroGEA GTW board
9ea985f294fc ARM: dts: imx6ul: support Engicam MicroGEA RMM board
b0e34d5a967c ARM: dts: imx6ul: support Engicam MicroGEA BMM board
acf9f66533f6 ARM: dts: imx6ul: support Engicam MicroGEA-MX6UL SoM
d23e9ea1eaac dt-bindings: arm: fsl: support Engicam MicroGEA GTW board
e50303295b76 dt-bindings: arm: fsl: support Engicam MicroGEA RMM board
aec517ade0f4 dt-bindings: arm: fsl: support Engicam MicroGEA BMM board
98ba73c32158 dt-bindings: net: convert nxp,lpc1850-dwmac.txt to yaml format
0f4043ab479c iio: adc: ad7173: add SPI offload support
d7b8723e5cc9 dt-bindings: trigger-source: add ADI Util Sigma-Delta SPI
84d8f9c362fd dt-bindings: mfd: adp5585: document reset gpio
362f91ed9a71 dt-bindings: mfd: adp5585: add properties for input events
a8629f7b1c76 dt-bindings: mfd: adp5585: document adp5589 I/O expander
56126147cf7f dt-bindings: mfd: adp5585: ease on the required properties
e89612b694cf dt-bindings: input: touchscreen: edt-ft5x06: Document FT8716 support
fcb3290cc9aa dt-bindings: input: touchscreen: convert tsc2007.txt to yaml format
2aa354161f52 dt-bindings: dsp: fsl,dsp: document 'access-controllers' property
6e293da49ad9 dt-bindings: bus: document the IMX AIPSTZ bridge
56370e58513a arm64: dts: imx93-11x11-evk: remove the duplicated pinctrl_lpi2c3 node
b2cf0ac6473f arm64: dts: imx93-11x11-evk: reduce the driving strength of net RXC/TXC
1f8f5eb35b99 arm64: dts: imx93-11x11-evk: disable all realtek ethernet phy CLKOUT
3f439f3e0847 arm64: dts: imx93-qsb/evk: add usdhc3 and lpuart5
c288a6c72f58 arm64: dts: imx93: remove eee-broken-1000t for eqos node
28a0f520481d arm64: dts: imx93-9x9-qsb: add IMU sensor support
bdbdeea06674 arm64: dts: freescale: imx8mp-var-som: Add EQoS support with MaxLinear PHY
fef47da29940 arm64: dts: imx8qm: add system controller watchdog support
43a9c5204a71 arm64: dts: imx95-19x19-evk: add GPIO reset for ethphy0
cfbae9c05739 arm64: dts: imx95-19x19-evk: adjust pinctrl settings for usdhc2
2d2d317cda64 arm64: dts: imx95-evk: add USB3 PHY tuning properties
e2984acda327 arm64: dts: imx95-19x19-evk: add adc0 flexcan[1,2] i2c[2,3] uart5 spi3 and tpm3
1b516b64f709 arm64: dts: freescale: imx93-var-som: update eqos support for MaxLinear PHY
236b3b5fa844 arm64: dts: imx8mp-venice-gw74xx: update name of M2SKT_WDIS2# gpio
ee2949900e0f arm64: dts: freescale: imx93-tqma9352: add memory node
a8cfb47ba83a arm64: dts: freescale: imx93-phyboard-nash: Move ADC vref to SoM
b4ab5602f093 dt-bindings: arm: fsl: add i.MX28 Amarula rmm board
58732bd8328b ARM: dts: mxs: support i.MX28 Amarula rmm board
54dad17c1416 ARM: dts: imx28: add pwm7 muxing options
7826f7be97d7 dt-bindings: serial: mediatek,uart: add MT6572
a6870cdf2262 dt-bindings: interrupt-controller: Convert fsl,mpic-msi to YAML
a39baf2874e1 riscv: dts: thead: Add PVT node
59dcbcb5dbe8 riscv: dts: thead: th1520: Add GPU clkgen reset to AON node
b7064204c34a arm: dts: omap: Add support for BeagleBone Green Eco board
97e7316298d4 dt-bindings: omap: Add Seeed BeagleBone Green Eco
1fc23c040c64 arm: dts: omap: am335x-bone-common: Rename tps to generic pmic node
d6a683de0144 dt-bindings: display: panel: Make reset-gpio as optional for Raydium RM67200
c7b79f4c60ea dt-bindings: display: panel: Add Himax HX83112B
287b9ff3a30a dt-bindings: vendor-prefixes: document Shenzhen DJN Optronics Technology
5b00d9d7cef3 arm64: dts: rockchip: Enable eMMC HS200 mode on Radxa E20C
f493d4244fb4 arm64: dts: rockchip: Add bluetooth support to ArmSoM Sige7
2c6901d159a6 arm64: dts: rockchip: enable PCIe on ROCK 4D
c3fcd8d33101 arm64: dts: rockchip: Enable HDMI receiver on CM3588
c0c64cb2bea6 arm64: dts: rockchip: Add HDMI PHY PLL clock source to VOP2 on rk3576
271c1ecee280 arm64: dts: rockchip: Enable HDMI PHY clk provider on rk3576
b347f6353796 dt-bindings: display: vop2: Add optional PLL clock property for rk3576
0ec19b976d2f dt-bindings: media: imx258: inherit video-interface-devices properties
32656f2dd7f7 dt-bindings: media: ov8858: inherit video-interface-devices properties
0a479200fad0 media: dt-bindings: mt9m114: Add slew-rate DT-binding
afcd87416700 media: dt-bindings: sony,imx214: Deprecate property clock-frequency
8c02f74a820d media: dt-bindings: mipi-ccs: Refer to video-interface-devices.yaml
21dd16fda6ae arm64: dts: exynos: gs101: switch to gs101 specific reboot
692223514aae arm64: dts: exynos: gs101-pixel-common: add main PMIC node
92a8f685b654 arm64: dts: exynos: gs101: ufs: add dma-coherent property
221da32f58b1 Merge 6.16-rc4 into tty-next
c0f052a89615 arm64: dts: imx95: add SMMU support for NETC
b5ed179c47d0 arm64: dts: imx943-evk: Add PDM microphone sound card support
bd71324d2afc arm64: dts: imx943-evk: add bt-sco sound card support
e22973f9644c arm64: dts: imx943-evk: add sound-wm8962 support
ba65c43c3568 arm64: dts: imx943-evk: add i2c io expander support
2364aebb71bb arm64: dts: imx943-evk: add lpi2c support
0b36a8496df3 arm64: dts: imx94: Add micfil and mqs device nodes
47f22e04693c dt-bindings: serial: 8250: allow clock 'uartclk' and 'reg' for nxp,lpc1850-uart
bb6fa1f5823a dt-bindings: usb: genesys,gl850g: add downstream facing ports
fe67c5983537 dt-bindings: usb: genesys,gl850g: use usb-hub.yaml
9d866d360be9 dt-bindings: input: touchscreen: convert lpc32xx-tsc.txt to yaml format
d9e86831c9e7 ARM: dts: Fix up wrv54g device tree
c88d144e4ee0 dt-bindings: dsa: Rewrite Micrel KS8995 in schema
721733928299 dt-bindings: net: sun8i-emac: Add A100 EMAC compatible
26d787d538c0 dt-bindings: net/nfc: ti,trf7970a: Add ti,rx-gain-reduction-db option
c4e889a39fbe dt-bindings: net: convert lpc-eth.txt yaml format
9d619f67ea06 dt-bindings: reset: sophgo: Add CV1800B support
390a51a896e0 dt-bindings: reset: renesas,rzv2h-usb2phy: Document RZ/V2N SoC support
1ab195547189 dt-bindings: reset: convert nxp,lpc1850-rgu.txt to yaml format
74f427003123 dt-bindings: reset: add support for canaan,k230-rst
bdfa6cf09cc8 dt-bindings: leds: lp50xx: Document child reg, fix example
0481e0a9c242 arm64: dts: exynos: gs101: add dm-verity-device-corrupted syscon-reboot-mode
d358bcfbc85a arm64: dts: exynos: gs101-pixel-common: add nvmem-reboot-mode
3b48424bb12d arm64: dts: exynos: gs101-pixel-common: add Maxim MAX77759 PMIC
1067406bccda dt-bindings: net: Document support for Airoha AN7583 MDIO Controller
5d19097df3ab dt-bindings: memory-controller: Define fallback compatible
3a12dc8d7019 dt-bindings: interrupt-controller: Add arm,armv7m-nvic and fix #interrupt-cells
977be08b2098 dt-bindings: trivial-devices: add compatible string nxp,isp1301 from isp1301.txt
faae60a9136d dt-bindings: net: Rename renesas,r9a09g057-gbeth.yaml
acc53bb0cab4 Merge tag 'drm-misc-next-2025-06-26' of https://gitlab.freedesktop.org/drm/misc/kernel into drm-next
253782c324ed dt-bindings: phy: qcom,snps-eusb2-repeater: Remove default tuning values
0ba1a407aad6 dt-bindings: phy: apm,xgene-phy: Remove trailing whitespace
29f6bd159cad spi: dt-bindings: add nxp,lpc3220-spi.yaml
563a067ae378 dt-bindings: net: wireless: ath11k-pci: describe firmware-name property
3dafddbf2214 dt-bindings: net: wireless: ath9k: add WIFI bindings
5a46d78c27c7 arm64: dts: qcom: x1-asus-zenbook: support sound
4820d1a59ead arm64: dts: qcom: x1-asus-zenbook: fixup GPU nodes
17d54e8cff64 dt-bindings: iio: adc: ad7768-1: add trigger-sources property
f1a36c705c57 dt-bindings: iio: adc: ad7768-1: Document GPIO controller
6d62b06711b2 dt-bindings: iio: adc: ad7768-1: document regulator provider property
f94145ede4c6 dt-bindings: trigger-source: add generic GPIO trigger source
b5103f279f65 dt-bindings: iio: adc: add ad7405
72d91eb75105 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
4a0d83820fdf arm64: dts: renesas: r9a09g047: Add GBETH nodes
3485db855114 arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Rename fixed regulator node names
66a9960e5871 arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Add RAA215300 PMIC
062f9e2c026a arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Add RAA215300 PMIC
3cfe736f1e40 dt-bindings: interrupt-controller: Add MIPS P8700 aclint-sswi
3cd935575bee dt-bindings: net: ti: k3-am654-cpsw-nuss: update phy-mode in example
669d2c02c393 dt-bindings: display: ti: Add schema for AM625 OLDI Transmitter
7b4c77851db5 dt-bindings: display: ti,am65x-dss: Re-indent the example
7fe4a35ce8ca arm64: dts: ti: k3-j784s4-j742s2-main-common: Add ACSPCIE1 node
c6a9ae83e762 arm64: dts: ti: k3-j722s-evm: Fix USB gpio-hog level for Type-C
a0ad301286a9 arm64: dts: qcom: sm6115: add debug UART pins
2c030b5460a9 dt-bindings: trivial-devices: Add Analog Devices ADT7411
34cb86fcdff2 Add few updates to the STM32 SPI driver
d16f0509fbae ARM: dts: microchip: sam9x7: Add LVDS controller
dc59315540b6 ASoC: Standardize ASoC menu
717b4dc30bb3 arm64: dts: exynos5433: Align i2c-gpio node names with dtschema
0d47606fb8d9 ARM: dts: s5pv210: Align i2c-gpio node names with dtschema
ae5dcb68953b ARM: dts: exynos: Align i2c-gpio node names with dtschema
fc41e79c8d7c dt-bindings: reset: sun55i-a523-r-ccu: Add missing PPU0 reset
97166fd1f53d dt-bindings: firmware: thead,th1520: Add resets for GPU clkgen
9c5a0a7d84d4 dt-bindings: net: cdns,macb: add sama7d65 ethernet interface
989c7d86c01f spi: dt-bindings: stm32: deprecate `st,spi-midi-ns` property
65f0c52f9155 spi: dt-bindings: stm32: update bindings with SPI Rx DMA-MDMA chaining
3b18f58612bb dt-bindings: usb: dwc2: rename sophgo usb compatible string
37b9182375b9 dt-bindings: gnss: u-blox: add u-blox,neo-9m compatible
aeb89b24ad7e dt-bindings: mmc: cdns: add Mobileye EyeQ MMC/SDHCI controller
eb7dca9a7276 dt-bindings: mmc: mxs-mmc: change ref to mmc-controller-common.yaml from mmc-controller.yaml
d3ef944175aa dt-bindings: pse: tps23881: Clarify channels property description
54965f2a3351 dt-bindings: soc: renesas: Document RZ/T2H Evaluation Board part number
4e1c8311bf0d ARM: dts: microchip: sama5d2_icp: rename spi-cs-setup-ns property to spi-cs-setup-delay-ns
f6e4727e66e0 ARM: dts: microchip: sama5d27_wlsom1: rename spi-cs-setup-ns property to spi-cs-setup-delay-ns
1025e2432dc1 ARM: dts: microchip: sama5d27_som1: rename spi-cs-setup-ns property to spi-cs-setup-delay-ns
346177955338 ARM: dts: microchip: sam9x60ek: rename spi-cs-setup-ns property to spi-cs-setup-delay-ns
040ecf520251 dt-bindings: net: convert qca,qca7000.txt yaml format
da41efa1472c Revert "ARM: dts: Update pcie ranges for dra7"
86e3aa4733ed ARM: dts: omap: am335x: Use non-deprecated rts-gpios
dcc259a92bf1 spi: microchip-core-qspi: Add regular transfers
689d9094a731 dt-bindings: net: qca,ar803x: Add IPQ5018 Internal GE PHY support
795bfa427a40 regulator: dvfsrc: Add support for MT8196 and
0c92dc5fb726 dt-bindings: regulator: mediatek-dvfsrc: Add MT8196 support
40062b24de96 dt-bindings: regulator: mediatek-dvfsrc: Add MT6893 support
3ea17e80490b dt-bindings: PCI: brcm,stb-pcie: Add num-lanes property
1a3a8073faf0 dt-bindings: PCI: qcom,pcie-sm8150: Drop unrelated clocks from PCIe hosts
ead3a65c4352 dt-bindings: PCI: qcom,pcie-sc8180x: Drop unrelated clocks from PCIe hosts
23ba48ce4f3d dt-bindings: crypto: Convert ti,omap4-des to DT schema
f3dc660ef7dd dt-bindings: crypto: Convert ti,omap2-aes to DT schema
b339218b8279 dt-bindings: rng: atmel,at91-trng: add sama7d65 TRNG
ff643bb28541 dt-bindings: crypto: add sama7d65 in Atmel TDES
0f0c72dc98dc dt-bindings: crypto: add sama7d65 in Atmel SHA
8462bd595120 dt-bindings: crypto: add sama7d65 in Atmel AES
76b9ac22e92f dt-bindings: crypto: fsl,sec-v4.0: Add power domains for iMX8QM and iMX8QXP
8639cd6d493b powerpc/microwatt: Correct ISA version number in device tree
5a69b5d0f9d4 ARM: dts: at91-sama5d27_wlsom1: Improve the Wifi compatible
b38f516e544a ARM: dts: microchip: gardena-smart-gateway: Fix power LED
a7efef227924 ARM: dts: microchip: sam9x7: Add clock name property
0c5aec276273 ARM: dts: microchip: sama7d65: Add clock name property
6fe4b2852827 ARM: dts: microchip: sama7g5: Adjust clock xtal phandle
3f1852d5065d ARM: dts: microchip: sam9x7: Add HLCD controller
5e5f78f26a1c ARM: dts: microchip: sama7d65: Enable CAN bus
9f891644a466 ARM: dts: microchip: sama7d65: Clean up extra space
e458631c8156 ARM: dts: microchip: sama7d65: Add CAN bus support
a2d173f4f06a ARM: dts: microchip: sama7d65: Add PWM support
e8cb36704dcf ARM: dts: microchip: sama7d65: Add crypto support
fad2776b7baf ARM: dts: microchip: use recent scl/sda gpio bindings
cfa530559e94 dt-bindings: power: supply: Drop redundant monitored-battery ref
4a278ae395fb dt-bindings: power: supply: summit,smb347: Add missing power-supply ref
1b193da31601 dt-bindings: power: supply: richtek,rt5033: Add missing power-supply ref
5b64ac18febc dt-bindings: power: supply: qcom,pmi8998: Add missing power-supply ref
f09e89e71f18 dt-bindings: power: supply: bq256xx: Add missing power-supply ref
561c50eeff1b dt-bindings: power: supply: bq2515x: Add missing power-supply ref
1c2a6f716763 arm64: dts: rockchip: add DTs for Firefly ROC-RK3588S-PC
6e8c6721786a dt-bindings: arm: rockchip: Add Firefly ROC-RK3588S-PC
d788cdf18afe arm64: dts: rockchip: Enable GPU on Radxa E20C
16d867f13e38 arm64: dts: rockchip: Add GPU node for RK3528
c3a10091d51d arm64: dts: ti: k3-am642-evm-pcie0-ep: Add boot phase tag to "pcie0_ep"
a2ef24e102ed arm64: dts: ti: k3-j722s-main: Add audio-refclk0 node
1d53c6646d99 arm64: dts: ti: k3-am62p-j722s: fix pinctrl-single size
307b8ee66245 arm64: dts: ti: k3-am62a7-sk: Describe the SPI NAND
e0da88bbe5dc arm64: dts: ti: k3-j721s2-main: Add McASP nodes
f72c8b39a660 arm64: dts: ti: k3-am62p-verdin: Enable pull-ups on I2C_3_HDMI
4228071de8ea arm64: dts: ti: k3-am62-verdin: Enable pull-ups on I2C buses
9f3a0581be0a arm64: dts: ti: k3-am642-phyboard-electra: Fix PRU-ICSSG Ethernet ports
0067f17cbb71 arm64: dts: mediatek: mt8370: Enable gpu support
fd8a8a611df3 dt-bindings: gpu: mali-bifrost: Add compatible for MT8370 SoC
8a87dd54887f media: dt-bindings: nxp,imx8-jpeg: Add compatible strings for IMX95 JPEG
a811534390f1 dt-bindings: media: convert fsl-vdoa.txt to yaml format
7c1831c97562 arm64: dts: rockchip: support camera module on Haikou Video Demo on PX30 Ringneck
e65d94e8c6e4 arm64: dts: rockchip: add label to first port of ISP on px30
49bd59bda613 arm64: dts: rockchip: fix endpoint dtc warning for PX30 ISP
8f0855aaa6a1 dt-bindings: dma: qcom,gpi: Document the sc8280xp GPI DMA engine
de8e8cacccbf arm64: dts: s32g: add RTC node
2eff8e3eb821 arm64: dts: Add DSPI entries for S32G platforms
527d37438b73 arm64: dts: freescale: imx93-phyboard-segin: Set ethernet1 alias
e9c4ed1380e5 arm64: dts: freescale: imx93-phycore-som: Move ethernet0 alias to SoM
19fc892ae830 arm64: dts: tqma8mpql: Add EASRC support
10d58add28d4 arm64: dts: tqma8mnql: Add EASRC support
9684884f9cc2 arm64: dts: freescale: Add the BOE av123z7m-n17 variant of the Moduline Display
36d39a81979d arm64: dts: freescale: Add the BOE av101hdt-a10 variant of the Moduline Display
0ab9cec49c0a arm64: dts: freescale: Add the GOcontroll Moduline Display baseboard
96478662ba59 arm64: dts: freescale: add Ka-Ro Electronics tx8p-ml81 COM
a54ff893e9e6 arm64: dts: imx8mp: Add pinctrl config definitions
b0356e47aa51 arm64: dts: rockchip: Add power controller for RK3528
fa630610e626 arm64: dts: rockchip: enable USB on Sige5
32d30cc2bfc3 arm64: dts: rockchip: add overlay for the WiFi/BT module on Sige5 v1.2
c7f61653a73d arm64: dts: rockchip: add version-independent WiFi/BT nodes on Sige5
d5edb6dfb78c arm64: dts: rockchip: add SDIO controller on RK3576
a22bac5ead32 arm64: dts: rockchip: Enable gpu on rk3576-evb1-v10
4e9c9ee05c23 dt-bindings: clock: convert lpc1850-ccu.txt to yaml format
5dab6d0666f8 arm64: dts: rockchip: Update the PinePhone Pro panel description
eaa75b56dcfb Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
64842d8e059f Merge tag 'renesas-r9a09g087-dt-binding-defs-tag1' into renesas-clk-for-v6.17
07f1f3844c5d Merge tag 'renesas-r9a09g077-dt-binding-defs-tag2' into renesas-clk-for-v6.17
e0ebadb2045d dt-bindings: clock: renesas,cpg-mssr: Document RZ/N2H support
949d0cfc7c44 dt-bindings: soc: renesas: Document RZ/N2H (R9A09G087) SoC
51071ab402e3 dt-bindings: clock: renesas,r9a09g077: Add PCLKL core clock ID
3ec018584fa1 arm64: dts: renesas: rcar-gen3: Add bootph-all to sysinfo EEPROMs
fc5f0def788b arm64: dts: renesas: sparrow-hawk: Describe split PCIe clock
3a8905aac211 arm64: dts: renesas: r8a779g0: Describe PCIe root ports
6887bc8543b4 arm64: dts: renesas: ebisu: Add CAN0 support
fd8b44404cb0 ARM: dts: renesas: r9a06g032: Add second clock input to RTC
2371c2df77ea arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Enable USB2.0 support
b1400fa1ae46 arm64: dts: renesas: r9a09g056: Add USB2.0 support
1e6055b1bfba arm64: dts: renesas: r8a779g3-sparrow-hawk: Sort DTS
e46668c89ed4 ARM: dts: renesas: r9a06g032-rzn1d400-db: Describe debug LEDs
b65d84ca5033 arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable USB2.0 support
5105a55fda27 dt-bindings: serial: renesas,rsci: Document RZ/N2H support
717942ab9fdf dt-bindings: usb: renesas,usbhs: Add RZ/V2N SoC support
51e5237dc82f ARM: dts: vf: vf610-zii-cfu1: rename node name *-gpio to *-gpios
39b627463c2b ARM: dts: vf: vf-colibri-eval-v3: add power-supply for edt,et057090dhu
fd302676921b ARM: dts: vf: rename io-expander@20 to pinctrl@20
9bea7c6d261c ARM: dts: vf: remove redundant layer under iomux
e139807952b1 ARM: dts: vf: remove redundant pinctrl-names
d2e638640e96 ARM: dts: vf: remove reg property for arm pmu
8f8e41560419 ARM: dts: vfxxx: Correctly use two tuples for timer address
f98b63e7e4d4 dt-bindings: arm: fsl: Add GOcontroll Moduline Display
2c61daf98d93 arm64: dts: add ngpios for vf610 compatible gpio controllers
063fd6175ada ARM: dts: add ngpios for vf610 compatible gpio controllers
19c622072a55 dt-bindings: net: pse-pd: ti,tps23881: Add interrupt description
a956323691dc dt-bindings: net: pse-pd: microchip,pd692x0: Add manager regulator supply
49faac7c9fd8 dt-bindings: clock: Convert alphascale,asm9260-clock-controller to DT schema
2d92d14e9eef dt-bindings: clock: Convert marvell,armada-370-corediv-clock to DT schema
d2ce3c47d404 dt-bindings: clock: Convert marvell,armada-3700-periph-clock to DT schema
e37e069f8b0f dt-bindings: clock: Convert marvell,mvebu-core-clock to DT schema
9cf6d0ba0fdf dt-bindings: clock: Convert marvell,berlin2-clk to DT schema
bb06131b2ecc dt-bindings: clock: Convert marvell,dove-divider-clock to DT schema
1fd176774ea2 dt-bindings: clock: Convert marvell,armada-3700-tbg-clock to DT schema
a06036f72ced dt-bindings: clock: Convert marvell-armada-370-gating-clock to DT schema
45f94b0de650 dt-bindings: clock: Convert marvell,armada-xp-cpu-clock to DT schema
5a9f538c0e6b dt-bindings: clock: Convert TI-NSPIRE clocks to DT schema
5a62a028d23b dt-bindings: clock: Convert lsi,axm5516-clks to DT schema
bb7d222956f9 dt-bindings: clock: Convert img,pistachio-clk to DT schema
763873a48189 dt-bindings: clock: Convert brcm,bcm2835-cprman to DT schema
cee9659816b4 dt-bindings: clock: Convert cirrus,ep7209-clk to DT schema
f10c6670b7e2 dt-bindings: clock: Convert APM XGene clocks to DT schema
bff50be25ecd dt-bindings: clock: Convert axis,artpec6-clkctrl to DT schema
7debe9917c80 dt-bindings: clock: Convert brcm,bcm53573-ilp to DT schema
37248ce61324 Merge branch '20250610-qcom_ipq5424_cmnpll-v3-1-ceada8165645@quicinc.com' into clk-for-6.17
945db09189dc dt-bindings: clock: qcom: Add CMN PLL support for IPQ5424 SoC
71f2de4a034f arm64: dts: qcom: sm8650: add iris DT node
d496cf29098a arm64: dts: qcom: msm8976-longcheer-l9360: Add initial device tree
ab1f53f63414 arm64: dts: qcom: msm8976: Add sdc2 GPIOs
b003f5c6b91d dt-bindings: arm: qcom: Add MSM8976 BQ Aquaris X5 Plus
a260177d0411 arm64: dts: qcom: msm8976: Make blsp_dma controlled-remotely
6de07b6f15ca ASoC: dt-bindings: cirrus,cs42xx8: add 'port' property
fb3447bb3b35 arm64: dts: qcom: sa8775p: Correct the interrupt for remoteproc
3058275a342c dt-bindings: rockchip: pmu: Add compatible for RK3528
50db66235f2b dt-bindings: power: rockchip: Add support for RK3528
33ceeabccc61 dt-bindings: pinctrl: eswin: Document for EIC7700 SoC
64e88c0fed96 arm64: dts: exynos: gs101: Add 'local-timer-stop' to cpuidle nodes
b10142d10119 dt-bindings: gpio: arm,pl061: Drop interrupt properties as required
469d40ff1fc6 arm64: dts: exynosautov920: Add DT node for all SPI ports
d6e199e49db3 dt-bindings: pinctrl: stm32: Add RSVD mux function
fcd55a37ae62 dt-bindings: mtd: convert nxp-spifi.txt to yaml format
b88ae50b4a3f media: dt-bindings: nxp,imx8mq-mipi-csi2: Add i.MX8QM(QXP) compatible strings
5ea6161f602d media: dt-bindings: Add binding doc for i.MX8QXP and i.MX8QM ISI
12f918ab5174 arm64: dts: qcom: sm8550: Add support for camss
3b8507884db9 arm64: dts: qcom: qcs615: disable the CTI device of the camera block
f605900d6de0 arm64: dts: qcom: qcs615-ride: enable remoteprocs
8093aa08d5a7 arm64: dts: qcom: qcs615: add ADSP and CDSP nodes
cff0cbfd4ffc arm64: dts: qcom: qcs615: Add IMEM and PIL info region
1454cb2395b1 arm64: dts: qcom: qcs615: Add mproc node for SEMP2P
d41393450043 arm64: dts: qcom: Add support for X1-based Asus Zenbook A14
455400158e35 arm64: dts: qcom: sc7180: Expand IMEM region
b73a5a409b33 arm64: dts: qcom: sdm845: Expand IMEM region
ed819d4948e0 dt-bindings: sram: qcom,imem: Add a number of missing compatibles
46d41941b590 arm64: dts: qcom: qcs615: fix a crash issue caused by infinite loop for Coresight
bcd405d4605c arm64: dts: qcom: sm6350: add APR and some audio-related services
cf84790a7bc1 arm64: dts: qcom: qcm2290: Add CAMSS node
71de0b13f5f4 arm64: dts: qcom: sa8775p-ride: enable video
f3c905ddb143 arm64: dts: qcom: sa8775p: add support for video node
2ea4d1a862e7 arm64: dts: qcom: sa8775p: Add CPU OPP tables to scale DDR/L3
f57f90da02fd arm64: dts: qcom: sa8775p: add EPSS l3 interconnect provider
484acd85064e arm64: dts: qcom: sm8750: Add UFS nodes for SM8750 QRD board
08d016ce62b5 arm64: dts: qcom: sm8750: Add UFS nodes for SM8750 MTP
21f3bb719d06 arm64: dts: qcom: sm8750: Add UFS nodes for SM8750 SoC
a4f170b96c2b arm64: dts: qcom: apq8016-sbc-d3-camera: Convert to DT overlay
96ffdf9514de arm64: dts: qcom: x1e80100-dell-xps-9345: Add WiFi/BT pwrseq
81e24b484d8f Merge tag 'drm-misc-next-2025-06-12' of https://gitlab.freedesktop.org/drm/misc/kernel into drm-next
7c6c4e986b5e dt-bindings: arm: cpus: Add Kryo 470 CPUs
c3e977592183 dt-bindings: sram: qcom,imem: Add the SM7150 compatible
ff4ba6b971ae dt-bindings: soc: qcom: aoss-qmp: Add the SM7150 compatible
3b86b00b2868 dt-bindings: soc: qcom,dcc: Add the SM7150 compatible
47cee050ea05 dt-bindings: soc: qcom: add qcom,qcs615-imem compatible
73bee717137b dt-bindings: PCI: pci-ep: Extend max-link-speed to PCIe Gen5/Gen6
6ad7e7635ff2 dt-bindings: PCI: qcom,pcie-sa8775p: Document QCS8300
fe9760407d9e dt-bindings: PCI: qcom,pcie-sm8150: Document QCS615
279926cf824c arm64: dts: qcom: Add QMP handle for qcom_stats
33b6b81327b2 arm64: dts: qcom: qrb5165-rb5-vision-mezzanine: remove camcc status property
4dcdeb9e373b arm64: dts: qcom: sm8250: enable camcc clock controller by default
986337f7125b dt-bindings: remoteproc: qcom,sa8775p-pas: Correct the interrupt number
87d25536e261 dt-bindings: gpio: gpio-xilinx: Mark clocks as required property
7d9619784d4c dt-bindings: dmaengine: Add dma multiplexer for CV18XX/SG200X series SoC
949eaeb96a7b dt-bindings: clock: Add RaspberryPi RP1 clock bindings
d37ab6d3737b media: dt-bindings: media: renesas,vsp1: Document RZ/V2N SoC
c999498941a3 media: dt-bindings: media: renesas,fcp: Document RZ/V2N SoC
17e3b9892493 dt-bindings: phy: Add the M31 based eUSB2 PHY bindings
bc371e92d06e dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: Add SM8750 to QMP PHY
335d8d9ff6e9 dt-bindings: phy: renesas,usb2-phy: Document RZ/V2N SoC support
b6272058c2ee dt-bindings: phy: Convert Marvell MVEBU PHYs to DT schema
3e6965af3886 dt-bindings: phy: Convert marvell,armada-380-comphy to DT schema
87f3979709df dt-bindings: phy: Convert ti,keystone-usbphy to DT schema
09d69b51d927 dt-bindings: phy: Convert ti,dm816x-usb-phy to DT schema
844acf2c998f dt-bindings: phy: Convert st,spear1310-miphy to DT schema
4bce5936846a dt-bindings: phy: Convert qca,ar7100-usb-phy to DT schema
ac5ef382d934 dt-bindings: phy: Convert motorola,mapphone-mdm6600 to DT schema
85e480d5fc84 dt-bindings: phy: Convert motorola,cpcap-usb-phy to DT schema
fe17837b8d9b dt-bindings: phy: Convert marvell,mmp2-usb-phy to DT schema
b126307f27dc dt-bindings: phy: Convert marvell,comphy-cp110 to DT schema
9bcbff3bd9d7 dt-bindings: phy: Convert marvell,berlin2-usb-phy to DT schema
0c82a7e3b08d dt-bindings: phy: Convert marvell,berlin2-sata-phy to DT schema
dc17572110df dt-bindings: phy: Convert lantiq,ase-usb2-phy to DT schema
b10685a3371a dt-bindings: phy: Convert img,pistachio-usb-phy to DT schema
408705e5a1ad dt-bindings: phy: Convert hisilicon,inno-usb2-phy to DT schema
727e67e12857 dt-bindings: phy: Convert hisilicon,hi6220-usb-phy to DT schema
1723ae98c198 dt-bindings: phy: Convert hisilicon,hix5hd2-sata-phy to DT schema
1dc8e1978b35 dt-bindings: phy: Convert brcm,sr-pcie-phy to DT schema
7cff50883378 dt-bindings: phy: Convert brcm,ns2-drd-phy to DT schema
93a177a9b1e9 dt-bindings: phy: Convert apm,xgene-phy to DT schema
55252481b031 dt-bindings: phy: samsung,mipi-video-phy: document exynos7870 MIPI phy
2b521ba242d3 dt-bindings: phy: samsung,usb3-drd-phy: Add exynos990 compatible
249194d3dfb7 dt-bindings: pci: Add Sophgo SG2044 PCIe host
88df97c059e6 arm64: dts: freescale: imx93-tqma9352: Remove unneeded GPIO hog
a73858b8f497 arm64: dts: freescale: imx93-tqma9352: Limit BUCK2 to 600mV
74609a3fb4f4 dt-bindings: net: renesas-gbeth: Add support for RZ/G3E (R9A09G047) SoC
ecbe9ffa03ea ARM: dts: imx7s-warp: Improve the Wifi description
b3cead4032a5 ARM: dts: imx7s-warp: Improve the Bluetooth description
d826170f23a8 arm64: dts: exynosautov920: add CMU_HSI2 clock DT nodes
892f6f8d54b1 dt-bindings: clock: exynosautov920: add hsi2 clock definitions
fc73efed87ea dt-bindings: clock: exynosautov920: sort clock definitions
a698889e0340 ARM: dts: vt8500: Add L2 cache controller on WM8850/WM8950
cc0cd2f62fba ARM: dts: vt8500: Fix the unit address of the VT8500 LCD controller
ba6b8fbd8f10 ARM: dts: vt8500: Use generic node name for the SD/MMC controller
4c2bee5a57aa ARM: dts: vt8500: Move memory nodes to board dts and fix addr/size
618840988c7d ARM: dts: vt8500: Add node address and reg in CPU nodes
638f4396159a arm64: dts: exynos: add initial support for Samsung Galaxy S22+
cda58ddae028 arm64: dts: exynos: add initial support for exynos2200 SoC
ba78ccfb85f1 dt-bindings: arm: samsung: document g0s board binding
928cf7b4db3d ASoC: dt-bindings: mt8192-afe-pcm: Allow specifying reserved memory region
7f82922e67a2 ASoC: dt-bindings: mt8186-afe-pcm: Allow specifying reserved memory region
7b4cfbf9cb43 ASoC: dt-bindings: mt8173-afe-pcm: Allow specifying reserved memory region
76cd57f4055e ASoC: dt-bindings: mt8173-afe-pcm: Add power domain
e8ba4d8d36e5 ASoC: dt-bindings: Convert MT8173 AFE binding to dt-schema
f9ab470b7216 ARM: dts: qcom: msm8974-sony-xperia-rhine: Add alias for mmc0 & mmc1
9a441a5e784a ARM: dts: qcom: msm8974-hammerhead: Add alias for mmc0
ab2a3af6930a ARM: dts: qcom: msm8974-oneplus-bacon: Add alias for mmc0
13bab98ae230 ARM: dts: qcom: Add initial support for Sony Xperia Z Ultra (togari)
830c3bb76487 dt-bindings: arm: qcom: Add Sony Xperia Z Ultra (togari)
65ca47d47e86 ARM: dts: qcom: msm8974-sony-xperia-rhine: Move camera buttons to amami & honami
658cf0eaccff ARM: dts: qcom: msm8974-sony-xperia-rhine: Enable USB charging
23712e8754a3 arm64: dts: qcom: x1p42100: Fix thermal sensor configuration
aa97b937223a arm64: dts: qcom: sm8650: remove unused reg
822ac62b57ee arm64: dts: qcom: sm8750-qrd: Add sound (speakers, headset codec, dmics)
6a7ae2443826 arm64: dts: qcom: sm8750-mtp: Add sound (speakers, headset codec, dmics)
6f4d1bf469a1 arm64: dts: qcom: sm8750: Add Soundwire nodes
dd1d6dea4bb1 arm64: dts: qcom: x1e80100-hp-x14: amend order of nodes
9eeffdf93012 arm64: dts: qcom: x1e80100-hp-x14: remove unused i2c buses
87e775221157 arm64: dts: qcom: x1e80100-hp-x14: add usb-1-ss1-sbu-mux
22c3ee0b6723 dt-bindings: clock: Convert brcm,bcm63xx-clocks to DT schema
5959214b449a dt-bindings: clock: ti: add ti,autoidle.yaml reference
be74285c8495 dt-bindings: clock: ti: Convert fixed-factor-clock to yaml
795aeb632bcf dt-bindings: clock: ti: Convert autoidle binding to yaml
81cf11f33bdc ARM: dts: qcom: msm8960: use macros for interrupts
b8acdc312e48 spi: dt-bindings: mediatek,spi-mt65xx: Add support for MT6991/MT8196 SPI
b27e030826ed arm64: dts: mediatek: mt8395-genio-1200-evk: Enable Audio DSP and sound card
f1bdce636304 arm64: dts: mediatek: mt8192-asurada: Reserve memory for audio frontend
4c6cbd4937e7 arm64: dts: mediatek: mt8186-corsola: Reserve memory for audio frontend
0bbc5f383e6f arm64: dts: mediatek: mt8183-kukui: Reserve memory for audio frontend
459a4687b473 arm64: dts: mediatek: mt8173: Reserve memory for audio frontend
bcfa2c4f812f arm64: dts: imx8mp: Enable gpu passive throttling
4bee3e87ff2b arm64: dts: imx95: correct i3c node in imx95
f4253a424db7 Merge drm/drm-next into drm-misc-next
67be89b70d90 ARM: dts: aspeed: Add device tree for Nvidia's GB200NVL BMC
b38511e07580 dt-bindings: arm: aspeed: add Nvidia's GB200NVL BMC
c9ef33bddfd0 ARM: dts: aspeed: catalina: Enable MCTP support for NIC management
5bea70972e95 ARM: dts: aspeed: catalina: Update CBC FRU EEPROM I2C bus and address
5340d8724879 ARM: dts: aspeed: catalina: Enable multi-master on additional I2C buses
917b91ebae04 ARM: dts: aspeed: catalina: Remove INA238 and INA230 nodes
0872eae37927 ARM: dts: aspeed: catalina: Add second source HSC node support
30621d6376f4 ARM: dts: aspeed: catalina: Add second source fan controller support
23a5060692bc ARM: dts: aspeed: catalina: Add fan controller support
c9680d1b9907 ARM: dts: aspeed: catalina: Add MP5990 power sensor node
43d4786d6d8d ARM: dts: aspeed: catalina: Add Front IO board remote thermal sensor
084d47454493 ARM: dts: aspeed: catalina: Add IO Mezz board thermal sensor nodes
5038976dd89a ARM: dts: aspeed: system1: Disable gpio pull down
a50225982fba ARM: dts: aspeed: system1: Mark GPIO line high/low
50fd31ea857a ARM: dts: aspeed: system1: Remove VRs max8952
907d0214bef2 ARM: dts: aspeed: system1: Update LED gpio name
7a218d1c5197 ARM: dts: aspeed: system1: Reduce sgpio speed
9d816c14e2c1 ARM: dts: aspeed: system1: Add GPIO line name
b78c314eda75 ARM: dts: aspeed: system1: Add IPMB device
4dbb7162e72d dt-bindings: ipmi: Add binding for IPMB device
58cf50957126 ARM: dts: aspeed: bletchley: remove unused ethernet-phy node
e2d77b735d13 ARM: dts: aspeed: Align GPIO hog name with bindings
7827afbe3914 ARM: dts: aspeed: Remove swift machine
a888a5efe1c2 dt-bindings: remoteproc: qcom,sm8150-pas: Document QCS615 remoteproc
69d13fabcaaf arm64: dts: qcom: Add camera clock controller for sc8180x
a9d6cb6c0fbe Merge branch '20250512-sc8180x-camcc-support-v4-2-8fb1d3265f52@quicinc.com' into arm64-for-6.17
531ad909582b Merge branch '20250512-sc8180x-camcc-support-v4-2-8fb1d3265f52@quicinc.com' into clk-for-6.17
db7047b5c166 dt-bindings: clock: Add Qualcomm SC8180X Camera clock controller
85694e07d677 dt-bindings: clock: qcom: Add missing bindings on gcc-sc8180x
0b4116099b60 arm64: dts: qcom: sm6350: Add video clock controller
c685c753be9d arm64: dts: qcom: qcs8300-ride: enable video
b80f475be983 arm64: dts: qcom: qcs8300: add video node
e08e7b76aa1e dt-bindings: clock: qcom,sm8450-camcc: Move sc8280xp camcc to sa8775p camcc
4d05467482c8 dt-bindings: clock: qcom,sm8450-camcc: Allow to specify two power domains
895f435e10e9 dt-bindings: clock: qcom,sm8450-videocc: Add MXC power domain
bc791dcd8483 arm64: dts: qcom: sa8775p-ride: add anx7625 DSI to DP bridge nodes
4098c5a2bf59 arm64: dts: qcom: sa8775p: add Display Serial Interface device nodes
0e31d061c9c0 arm64: dts: broadcom: northstar2: Drop GIC V2M "interrupt-parent"
ea1885c9fd30 arm64: dts: qcom: x1e80100: Add missing 'global' PCIe interrupt
14ad59d4559f arm64: dts: qcom: sar2130p: Add 'global' PCIe interrupt
0a47f45ad43a arm64: dts: qcom: sc8180x: Add 'global' PCIe interrupt
94ff2d21c06d arm64: dts: qcom: ipq6018: Add missing MSI and 'global' IRQs
420964cc89e0 arm64: dts: qcom: ipq8074: Add missing MSI and 'global' IRQs
6d1521f0fc17 arm64: dts: qcom: msm8998: Add missing MSI and 'global' IRQs
9da0fdcbce25 arm64: dts: qcom: msm8996: Add missing MSI SPI interrupts
275a1383fcdf arm64: dts: qcom: sdm845: Add missing MSI and 'global' IRQs
22e63cea7b60 arm64: dts: qcom: sc7280: Add 'global' PCIe interrupt
28bef8454e3d arm64: dts: qcom: sa8775p: Add 'global' PCIe interrupt
c18c33f1c365 arm64: dts: qcom: sm8350: Add 'global' PCIe interrupt
30dd461fe360 arm64: dts: qcom: sm8250: Add 'global' PCIe interrupt
5c8dac48ba74 arm64: dts: qcom: sm8150: Add 'global' PCIe interrupt
bb38e4d566a8 ARM: dts: qcom: Align wifi node name with bindings
0b05f902b191 dt-bindings: pinctrl: rockchip: increase max amount of device functions
e09ea8c6b2f4 dt-bindings: ili9881c: Document 7" Raspberry Pi 720x1280
d8786b38477d dt-bindings: pinctl: amlogic,pinctrl-a4: Add compatible string for S7/S7D/S6
ac3bc668fd07 dt-bindings: display: st7701: Add Winstar wf40eswaa6mnn0 panel
998a197154ea dt-bindings: display: visionox-rm69299: document new compatible string
8f0d68ed872a arm64: dts: rockchip: convert rk3562 to their dt-binding constants
509e0c2fabe8 arm64: dts: rockchip: Add Luckfox Omni3576 Board support
28cf288916a0 dt-bindings: arm: rockchip: Add Luckfox Omni3576 and Core3576 bindings
9c61e9d15269 dt-bindings: vendor-prefixes: Add luckfox prefix
2ab598cbc1ba arm64: dts: rockchip: Remove workaround that prevented Turing RK1 GPU power regulator control
68888e37d9fb arm64: dts: rockchip: add overlay for RockPro64 screen
f1ab980e061c Revert "dt-bindings: clock: renesas,rzg2l-cpg: Update #power-domain-cells = <1> for RZ/G3S"
d5b5838ba286 dt-bindings: clock: rzg2l: Drop power domain IDs
eb2482bd3a71 Merge tag 'renesas-r9a09g077-dt-binding-defs-tag' into renesas-clk-for-v6.17
c80e0b36f0b1 dt-bindings: memory-controllers: convert arm,pl172.txt to yaml format
6cf75590b12d dt-bindings: soc: samsung: exynos-pmu: Constrain google,pmu-intr-gen-syscon
9505fc5dd862 dt-bindings: gpio: convert nxp,lpc1850-gpio.txt to yaml format
54fb0929cc99 dt-bindings: gpio: convert gpio-74xx-mmio.txt to yaml format
a3e905523cd5 dt-bindings: gpio: convert gpio-pisosr.txt to yaml format
1040128bb18a arm64: dts: renesas: r9a09g057: Add USB2.0 support
a2a9c525081e arm64: dts: renesas: r9a09g047e57-smarc: Enable CRU, CSI support
21b5186a7f3e arm64: dts: renesas: renesas-smarc2: Enable I2C0 node
313bfdd58194 arm64: dts: renesas: r9a09g047e57-smarc: Add I2C0 pincontrol
c4a0b4786c56 arm64: dts: renesas: r9a09g047: Add CRU, CSI2 nodes
942d44d91446 arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Enable Mali-G31 GPU
df4a18da3850 arm64: dts: renesas: r9a09g056: Add Mali-G31 GPU node
97126d793150 arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Enable WDT1
aa49b82d292a arm64: dts: renesas: r9a09g056: Add WDT0-WDT3 nodes
0fd2a920a15b arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Enable RIIC controllers
a9e1b1c51a2e arm64: dts: renesas: r9a09g056: Add RIIC controllers
8620f503d15b arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Enable OSTM timers on RZ/V2N EVK
7edd14aa50b6 arm64: dts: renesas: r9a09g056: Add OSTM0-OSTM7 nodes
694ebe54d549 arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Enable GBETH
4b6db87a7c10 arm64: dts: renesas: r9a09g056: Add GBETH nodes
46869466a047 arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable GBETH
7fd2951fbfb5 arm64: dts: renesas: r9a09g057: Add GBETH nodes
d2a7f6061328 arm64: dts: renesas: rzg3e-smarc-som: Enable serial NOR FLASH
ca067cd873d2 arm64: dts: renesas: r9a09g047: Add XSPI node
6afb981042a9 dt-bindings: soc: renesas: Document RZ/V2H EVK board part number
47e339df4236 arm64: dts: qcom: sdm850-lenovo-yoga-c630: enable sensors DSP
3eb07ee1199c arm64: dts: qcom: x1e80100-dell-xps13-9345: Enable fingerprint sensor
2369c0a8d811 spi: spi-fsl-dspi: DSPI support for NXP S32G
519d961ebee1 ARM: dts: bcm958625-meraki-mx6x: Use #pwm-cells = <3>
364569526281 ARM: dts: bcm63178: Add BCMBCA peripherals
a8aa7adbe86e ARM: dts: bcm63148: Add BCMBCA peripherals
72b55d5589da ARM: dts: bcm63138: Add BCMBCA peripherals
40f65eebdc16 ARM: dts: bcm6878: Add BCMBCA peripherals
4db474ab76b1 ARM: dts: bcm6855: Add BCMBCA peripherals
c1fa2261ce24 ARM: dts: bcm6846: Add interrupt to RNG
cfb95bca76c8 dt-bindings: rng: r200: Add interrupt property
8f5c0556e851 ARM: dts: bcm6878: Correct UART0 IRQ number
756cdb1f3650 arm64: dts: broadcom: Add overlay for RP1 device
f3e865c8518c arm64: dts: broadcom: Add board DTS for Rpi5 which includes RP1 node
f07526de4e4d arm64: dts: bcm2712: Add external clock for RP1 chipset on Rpi5
82e6696b5c5c arm64: dts: rp1: Add support for RaspberryPi's RP1 device
e4470510ff94 dt-bindings: misc: Add device specific bindings for RaspberryPi RP1
36ec48d1dd05 dt-bindings: pinctrl: Add RaspberryPi RP1 gpio/pinctrl/pinmux bindings
5bae359ddb89 dt-bindings: clock: Add RaspberryPi RP1 clock bindings
7311a83b9240 ARM64: dts: bcm63158: Add BCMBCA peripherals
c820a00e2552 ARM64: dts: bcm6858: Add BCMBCA peripherals
2a6681b31935 ARM64: dts: bcm6856: Add BCMBCA peripherals
f6d523dc2308 ARM64: dts: bcm4908: Add BCMBCA peripherals
cfb6a63d41fe riscv: dts: spacemit: enable eMMC for K1 SoC
274a9a682e34 dt-bindings: display: convert himax,hx8357d.txt to yaml format
99b29e7ccd61 dt-bindings: display: arm,pl11x: Allow resets property
e13ecc320126 dt-bindings: display: convert sitronix,st7586 to YAML
1e04213799d5 dt-bindings: lcdif: add lcd panel related property for imx28
11b1b6e24edd dt-bindings: soc: Add fsl,imx23-digctl.yaml for i.MX23 and i.MX28
9c5a32bcb7b7 ASoC: Add Richtek RTQ9124 support
d57db601e6b0 ASoC: tas571x: add support for tas5753
caa03026f5ef ASoC: codecs: wcd93xx: Few simplifications of code and
baa572592b2c regulator: dt-bindings: rpi-panel: Add regulator for 7" Raspberry Pi 720x1280
504cdf1cd54f ASoC: dt-bindings: rt9123: Append RTQ9124 description
3174278d792f arm64: dts: rockchip: drop touch panel display from rockpro64
873fbebb9c18 arm64: dts: rockchip: Use standard PHY reset properties for RK3576 ArmSoM Sige5
1222a7f24b9f arm64: dts: rockchip: add ROCK 5T device tree
0f79e5a028f1 arm64: dts: rockchip: move common ROCK 5B/+ nodes into own tree
0562055bfc3a arm64: dts: rockchip: rename rk3588-rock-5b.dtsi
9c200495868c dt-bindings: arm: rockchip: add RADXA ROCK 5T
7bcc6969adbc arm64: dts: rockchip: Add spi nodes for RK3528
45b18dd32d6a arm64: dts: rockchip: add DTs for Sakura Pi RK3308B
bfca6dc90f2b dt-bindings: arm: rockchip: Add Sakura Pi RK3308B
6d2e9d5b069d dt-bindings: vendor-prefixes: Add SakuraPi prefix
99295ef16891 arm64: dts: rockchip: Fix cover detection on PineNote
c13e5de9b3a4 arm64: dts: rockchip: Document unused device on i2c1
718ca7a2529e arm64: dts: rockchip: support Ethernet Switch adapter for RK3588 Jaguar
f6310c860d5d arm64: dts: rockchip: Add DSI panel support for gameforce-ace
e53018a1ec5b dt-bindings: iio: adc: adi,ad7606: add gain calibration support
14dc2df77a84 dt-bindings: iio: gyroscope: invensense,itg3200: add binding
2f573d87f578 dt-bindings: iio: adc: st,spear600-adc: txt to yaml format conversion.
ed7d4c99dbc3 dt-bindings: iio: adc: add ad4080
61b12aa8b66f dt-bindings: iio: adc: add ad408x axi variant
05db8b79a0b6 arm64: dts: qcom: sm8750: Trivial stray lines removal
1576a89b79e8 spi: dt-bindings: mxs-spi: allow clocks properpty
feffdd266d46 dt-bindings: spi: dspi: Add S32G support
d87d1c2d9447 dt-bindings: regulator: add pca9450: Add regulator-allowed-modes
fa5cfb1fe890 ASoC: dt-bindings: covert mxs-audio-sgtl5000.txt to yaml format
1a0738c10fdd ASoC: dt-bindings: tas57xx: add tas5753 compatibility
90f889cf60f4 ASoC: dt-bindings: qcom,wcd939x: Document missing VDD_PX supply
36269efd9ee8 dt-bindings: display: himax-hx8394: Add Huiling hl055fhav028c
8cd51ffc1367 dt-bindings: vendor-prefixes: Add prefix for Huiling
534b0f65825d dt-bindings: display: simple: add AUO P238HAN01 panel
158a6f7c3376 Merge drm-next-2025-05-28 into drm-misc-next
af3871ba3627 dt-bindings: allwinner: add H616 DE33 mixer binding
2124a6a99b66 dt-bindings: clock: renesas,cpg-mssr: Document RZ/T2H support
f5efe4f4902d dt-bindings: display: renesas,rzg2l-du: Add support for RZ/V2H(P) SoC
c625b4924743 dt-bindings: display: panel: Document Renesas R69328 based DSI panel
36ea865fae13 dt-bindings: display: panel: Document Renesas R61307 based DSI panel
0d28beee9809 dt-bindings: display: ti,am65x-dss: Add support for AM62L DSS
a0e2388af079 dt-bindings: gpu: mali-utgard: Add Rockchip RK3528 compatible
ac5d1cdc0275 dt-bindings: display: imx: Add i.MX8qxp Display Controller
963333f8371f dt-bindings: interrupt-controller: Add i.MX8qxp Display Controller interrupt controller
2889c661fb91 dt-bindings: display: imx: Add i.MX8qxp Display Controller command sequencer
57051a9f0a4c dt-bindings: display: imx: Add i.MX8qxp Display Controller AXI performance counter
cf04f0c00267 dt-bindings: display: imx: Add i.MX8qxp Display Controller pixel engine
0940d6bd8421 dt-bindings: display: imx: Add i.MX8qxp Display Controller display engine
6454e207cfe6 dt-bindings: display: imx: Add i.MX8qxp Display Controller blit engine
8300a1f4ca66 dt-bindings: display: imx: Add i.MX8qxp Display Controller processing units

git-subtree-dir: dts/upstream
git-subtree-split: 4d52919c55f45d027062baf25ebe1c24730699bd
2025-10-08 15:01:20 -06:00
Marek Vasut
0ee639ff5a thermal: Convert .get_temp() return value to millicelsius
Linux kernel .get_temp() callback reports values in millicelsius,
U-Boot currently reports them in celsius. Align the two and report
in millicelsius. Update drivers accordingly. Update callsites that
use thermal_get_temp() as well.

The 'temperature' command now reports temperature in millicelsius
as well, with additional accuracy. This changes command line ABI
slightly.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: David Zang <davidzangcs@gmail.com>
[trini: Update test/cmd/temperature.c]
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-10-08 13:54:59 -06:00
Marek Vasut
79fe4655d6 arm64: renesas: Enable thermal driver on R-Car Gen3 and Gen4
Enable thermal driver and 'temperature' command on R-Car Gen3 and Gen4
to allow reading out the SoC temperature sensors.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-10-08 13:54:58 -06:00
Marek Vasut
0581328b58 thermal: rcar_gen3: Add Renesas R-Car Gen3/Gen4 and RZ/G2 thermal driver
Add support for R-Car Gen3/Gen4 and RZ/G2 thermal sensors.
Fuse readout support is present, including fallback trimming.

Example usage using the 'temperature' command on R-Car V4H Sparrow Hawk:

"
=> temperature list
| Device                        | Driver                        | Parent
| thermal-rcar-gen3-tsc.0       | thermal-rcar-gen3-tsc         | thermal@e6198000
| thermal-rcar-gen3-tsc.1       | thermal-rcar-gen3-tsc         | thermal@e6198000
| thermal-rcar-gen3-tsc.2       | thermal-rcar-gen3-tsc         | thermal@e6198000
| thermal-rcar-gen3-tsc.3       | thermal-rcar-gen3-tsc         | thermal@e6198000

=> for i in 0 1 2 3 ; do temperature get thermal-rcar-gen3-tsc.$i ; done
thermal-rcar-gen3-tsc.0: 56 C
thermal-rcar-gen3-tsc.1: 50 C
thermal-rcar-gen3-tsc.2: 48 C
thermal-rcar-gen3-tsc.3: 52 C
"

Ported from Linux 6.16-rc6 commit
9e1dc0360fcf ("thermal/drivers/rcar_gen3: Add support for R-Car V4H default trim values")

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-10-08 13:54:58 -06:00
Tom Rini
78849ecc18 thermal: Make U_BOOT_DRIVER entries unique
All instances of the U_BOOT_DRIVER must use a unique name or they will
lead to link time failures due to name space conflicts when both are
present. In this case the driver was reusing the ti_bandgap name.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-10-08 13:54:58 -06:00
Tom Rini
6e04cc321f spmi: sandbox: Make U_BOOT_DRIVER entries unique
All instances of the U_BOOT_DRIVER must use a unique name or they will
lead to link time failures due to name space conflicts when both are
present. In this case the driver was reusing the msm name.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-10-08 13:54:58 -06:00
Tom Rini
b7f35d3015 rtc: Make U_BOOT_DRIVER entries unique
All instances of the U_BOOT_DRIVER must use a unique name or they will
lead to link time failures due to name space conflicts when both are
present. In this case the driver was reusing the max313xx name.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-10-08 13:54:58 -06:00
Tom Rini
da93f8a078 gpio: aspeed: Make U_BOOT_DRIVER entries unique
All instances of the U_BOOT_DRIVER must use a unique name or they will
lead to link time failures due to name space conflicts when both are
present. In this case gpio-aspeed-g7 was using the same name as
gpio-aspeed.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-10-08 13:54:58 -06:00
Tom Rini
d40eae0e27 pci: Remove pcie_intel_fpga driver
This driver has never been enabled by a platform since introduction and
does not currently compile. Remove it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-10-08 13:54:58 -06:00
Bryan Brattlof
8a9f2c19d4 arm: dts: k3-am654: add vin-supply regulators for DDR
As of commit f98d812e53 ("power: regulator: Add vin-supply for GPIO
and Fixed regulators") we must ensure the parent nodes of a regulator
are present in DT if they are described in the vin-supply property

For the am65x reference board the DRAM chips are fed by the 3v3 rail
which is fed by the main 12v rail. Add the bootph properties to these DT
nodes to prevent them from being pruned during the SPL build so we can
enable power to the DRAM chips

Signed-off-by: Bryan Brattlof <bb@ti.com>
Tested-by: Nishanth Menon <nm@ti.com>
2025-10-08 13:34:14 -06:00
Andrew Goodbody
0cab29ff46 fs: ubifs: Fix and rework error handling in ubifs_finddir
Add a null check for 'file' before dereferencing it and also rework the
error handling to be a bit more sane.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-10-08 11:36:05 +02:00
Andrew Goodbody
51615eb4f7 fs: ubifs: Need to check return for being an error pointer
The return value from alloc_super can be an error pointer so the error
check needs to detect this as well as checking the pointer for being
NULL.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-10-08 11:36:00 +02:00
Andrew Goodbody
d23ddd5dee fs: ubifs: Ensure buf is freed before return
Returning directly after buf has been allocated will result in a memory
leak. Instead set the error code and goto the common unwind code to
ensure that buf will be freed before returning.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-10-08 11:35:47 +02:00
Yegor Yefremov
2bc0837ce1 ubi: extend support for LED activity
Add LED activity for ubi_dev_scan() and ubi_volume_read() routines.

Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
2025-10-08 11:34:54 +02:00
Benedikt Spranger
88e7a462f0 drivers/mtd/ubispl/ubispl.c: limit copy size
The fastmap VID header is embedded in struct ubi_scan_info. During fastmap
scan, the header is copied into struct ubi_scan_info, if valid. The former
code mixed up the amount of copied bytes and copied more bytes than
nessesary. This had no side effect, since the affected struct members are
uninitialized at that point and overwritten later.

Limit the copied bytes to the VID header size.

Signed-off-by: Benedikt Spranger <b.spranger@linutronix.de>
Reported-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-10-08 11:34:39 +02:00
Andrew Goodbody
75b7ef1caf mtd: ubi: Remove test that always fails
When checking the VID header of a static volume there is an early test
for data_size == 0 so testing for that condition again is guaranteed to
fail. Just remove this piece of code.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-10-08 11:34:12 +02:00
briansune
92dcb3ad5d cmd/dma: implement dmareset command
This adds a new U-Boot command 'c5_pl330_dma' for Cyclone V SoCDK
boards. It provides access to the Reset Manager's Per2ModRst register
to release the reset for ARM PrimeCell PL330 DMA channels. This allows
software to initialize and use the PL330 DMA controller properly after
reset.

Signed-off-by: Brian Sune <briansune@gmail.com>
[trini: Minor style fixes]
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-10-07 17:49:15 -06:00
Marek Vasut
e560735558 mkimage: Add help text for bundling TFA BL31 in mkimage -f auto
Add missing help text for the -y and -Y parameters of mkimage.

Fixes: 6dfd14e122 ("mkimage: Add support for bundling TFA BL31 in mkimage -f auto")
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-10-07 17:49:15 -06:00
Maarten Brock
0b9ff08515 board: ti: am335x: Do not call disabled PMIC functions
When PMIC drivers are disabled their undefined functions cannot be called.

Signed-off-by: Maarten Brock <maarten.brock@sttls.nl>
2025-10-07 17:12:28 -06:00
Marek Vasut
863502de82 misc: fs_loader: Use buffer pointer in request_firmware_into_buf_via_script()
Use plain buffer pointer in request_firmware_into_buf_via_script()
instead of a pointer to pointer. The later is not necessary as the
request_firmware_into_buf_via_script() does not modify the buffer
pointer. Update the mediatek driver to match.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
2025-10-07 17:12:24 -06:00
Christian Marangi
726404a66c airoha: rework RAM size handling to support multiple RAM size
There are multiple version of the same reference board with different
RAM size and it's not enough to base the RAM size entirely from DT. To
better support it use the get_ram_size way to scan for the actual RAM
size of Airoha SoC and increase the size of the memory map.

Also rework the memory map to account for 2 memory map. The first one of
2GB for 32bit DMA and for safe usage of U-Boot. The second one for the
rest of the RAM since up to 8GB are supported.

Reviewed-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2025-10-07 17:11:49 -06:00
Tom Rini
6f18098470 Merge patch series "Add support for secure falcon mode: load kernel image before args"
Anshul Dalal <anshuld@ti.com> says:

During the implementation of falcon mode for TI's K3 devices [1], I encountered
several limitations in regards to the current falcon mode support in U-Boot
especially in ensuring a secure boot flow.

Although the current implementation allows for loading of a signed fitImage as
the SPL payload, there are still a few edge cases that might allow bypassing the
verified boot path.

The following issues with current falcon mode need to be resolved:

1) No fallback:
    We currently fallback to regular boot flow if falcon mode fails,
    this might not be secure.

2) No arguments file:
    We currently load a kernel file (which could be a raw image or FIT)
    alongside an args file (usually the DT). The args file here doesn't have
    any verification mechanism, so should be skipped altogether as the FIT can
    contain the DT.

3) No access to env:
    In ext and fat fs boot, currently we also reads the environment to get the
    names of the kernel and the arg file. This should be disabled in secure
    falcon flow as the env might not be secure.

4) No raw image boot:
    Boot should fail when the kernel file is a raw kernel image, only FIT should
    be allowed.

As per the recommendation of maintainers[2], I have decided to split the above
set of tasks into multiple patch series. This is the first one which fixes the
load order of kernel image and the args file in falcon mode. Along with some
minor cleanup.

[1]: https://lore.kernel.org/u-boot/20250603142452.2707171-1-anshuld@ti.com/
[2]: https://lore.kernel.org/u-boot/20250911172313.GT124814@bill-the-cat/

Link: https://lore.kernel.org/r/20250923124639.667718-1-anshuld@ti.com
2025-10-07 13:02:52 -06:00
Anshul Dalal
d0b5b33c4f spl: ext, fat: cleanup use of CONFIG_SPL_LIBCOMMON_SUPPORT
Minor cleanup of spl_ext and spl_fat files, removing the outdated
CONFIG_SPL_LIBCOMMON_SUPPORT symbols similar to the commit 1847129025
("spl: mmc: Drop checks for CONFIG_SPL_LIBCOMMON_SUPPORT") and adding a
few extra failure reports.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Anshul Dalal <anshuld@ti.com>
2025-10-07 13:02:18 -06:00
Anshul Dalal
00edec55f3 spl: mmc: load kernel image before args in falcon
Load the kernel image before args in falcon mode to be consistent with
the load order for other boot media.

Signed-off-by: Anshul Dalal <anshuld@ti.com>
2025-10-07 13:02:18 -06:00
Anshul Dalal
50953dd5cd spl: ext: load kernel image before args in falcon
Load the kernel image before args in falcon mode to be consistent with
the load order for other boot media.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Anshul Dalal <anshuld@ti.com>
2025-10-07 13:02:17 -06:00
Anshul Dalal
6b8e03a958 spl: fat: load kernel image before args in falcon
Currently in falcon mode, the FS and raw mmc boot loads the args file
first followed by the kernel image whereas others load in the opposite
order. This inconsistency means falcon boot doesn't behave the same
across various boot media.

For example, in the case where the kernel file is a FIT with the kernel
image present alongside the dtb and the args file is another DT, which
DT should be picked? The one form the FIT or the one set by the args
file? Currently this depends entirely on how the boot media handles
falcon mode.

Therefore, this patch enforces the load order of the kernel image first
followed by the args file in FAT FS boot. So in the above example, the
args file would take precedence.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Anshul Dalal <anshuld@ti.com>
2025-10-07 13:02:17 -06:00
Frieder Schrempf
7f9362ef7f imx: kontron-sl-mx8mm: Convert to OF_UPSTREAM
Switch to OF_UPSTREAM to make use of the upstream devicetree.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2025-10-07 08:58:28 -03:00
Eberhard Stoll
228f7f2e26 imx: kontron-sl-mx8mm: Force default environment for serial loader boot
Enable CONFIG_ENV_IS_NOWHERE and force default environment when SoC
boots from serial loader. In this case the U-Boot environment cannot
be stored to flash with the 'saveenv' command.

This makes serial loader boot completely independent from any
environment stored in flash.

Signed-off-by: Eberhard Stoll <eberhard.stoll@kontron.de>
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2025-10-07 08:58:28 -03:00
Frieder Schrempf
c5ab46695c imx: kontron-sl-mx8mm: Autostart fastboot if booted from USB
This is useful for development and manufacturing setups as fastboot
can be used without requiring any user input on the device.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2025-10-07 08:58:28 -03:00
Frieder Schrempf
de704144ff imx: kontron-sl-mx8mm: Enable USB hub on BL i.MX8MM OSM-S board
Probe the USB hub on the BL i.MX8MM OSM-S board.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2025-10-07 08:58:28 -03:00
Frieder Schrempf
16ead099eb imx: kontron-sl-mx8mm: Enable standard boot and disable legacy distro boot
The bootstd framework is the new way to support various bootflows
and media. Use it instead of legacy distro boot.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2025-10-07 08:58:28 -03:00
Frieder Schrempf
194c747442 imx: kontron-sl-mx8mm: Enable multiple useful commands, drivers and features
Enable a bunch of useful features such as:

* Linux devicetree fixups
* devicetree overlay support
* secure boot dependencies
* commands (filesystems, disks, etc.)
* fastboot support
* USB storage/ethernet

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2025-10-07 08:58:28 -03:00
Frieder Schrempf
d31ca9e259 imx: kontron-sl-mx8mm: Export current env config to devicetree
This allows userspace tools like libubootenv to determine the
location of the currently used environment and select a
matching config.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2025-10-07 08:58:28 -03:00
Frieder Schrempf
83a18f8241 imx: kontron-sl-mx8mm: Use eMMC boot part for environment if booting from eMMC
Depending on the MMC boot device, select the proper location for the
environment.

* SD card and eMMC main partition: use offsets from CONFIG_ENV_OFFSET
  and CONFIG_ENV_OFFSET_REDUND.
* eMMC boot partition: use offset -2*ENV_SIZE and -ENV_SIZE from the
  end of the partition.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2025-10-07 08:58:28 -03:00
Frieder Schrempf
6679a94040 imx: kontron-sl-mx8mm: Add support for EEPROM on OSM-S module
Enable config options to access the EEPROM on the OSM-S i.MX8MM
SoM module.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2025-10-07 08:58:28 -03:00
Frieder Schrempf
0d0c00ace4 imx: kontron-sl-mx8mm: Enable fixed regulators
Enable support for using fixed regulators from the devicetree and
auto enable them if requested.

This way U-Boot will enable the CARRIER_PWR_EN signal of the OSM
module automatically while initializing the board.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2025-10-07 08:58:28 -03:00
Frieder Schrempf
a9b865dd46 imx: kontron-sl-mx8mm: Remove deprecation warning for old modules
The module version this warning is referring to never really existed
except for in-house development and there is a conflict with the
I2C address used for detecting it and the I2C EEPROM of the latest
OSM-S module. Remove the check.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2025-10-07 08:58:28 -03:00
Frieder Schrempf
c1cd4f3806 imx: kontron-sl-mx8mm: Enable SDP support for loading via USB
Enable everything that is required to load via USB. The SPL needs
SDP support so it can load the U-Boot proper image via USB after
it has been loaded via serial loader mode of the i.MX.

This way we can use the uuu tool for loading SPL and U-Boot
proper like this:

  uuu -brun flash.bin

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2025-10-07 08:58:28 -03:00
Frieder Schrempf
4d5a28e4f9 imx: kontron-sl-mx8mm: Increase CONFIG_SPL_MAX_SIZE
The limit of 0x27000 (156 KiB) was valid at times the DDR firmware
required a fixed amount of 96 KiB of space. Now that we use binman
to include the DDR firmware it only needs around 57 KiB of space and
there is more room for the SPL.

Increase the max SPL size to 196 KiB so there is still 60 KiB for DDR
firmware. This allows us to enable USB and SDP support in SPL.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2025-10-07 08:58:28 -03:00
Martin Schwan
fcddf2fc7e board: phytec: phycore_imx8mp: Add rauc to bootmeths
Add rauc to bootmeths variable if BOOTMETH_RAUC is enabled. This is
setting a proper default for RAUC enabled systems.

Signed-off-by: Martin Schwan <m.schwan@phytec.de>
2025-10-07 08:57:52 -03:00
Tom Rini
0eaa4b3373 Merge branch 'next'
Merge the outstanding changes from the 'next' branch to master.
2025-10-06 13:20:24 -06:00
Mikhail Kshevetskiy
eeae89cd35 cmd: mtd: add benchmark option to the help
The patch adds benchmark option to the help of mtd command. For the
'mtd write' case the help line exceed 80 characters. Ignore this issue
as modern terminals are capable to handle more characters.

The patch also formats other command to make sure all device names
starts on the same collumn.

Fixes: d246e70cf8 ("cmd: mtd: Enable speed benchmarking")
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2025-10-05 20:26:51 +02:00
Mikhail Kshevetskiy
e700a84292 cmd: mtd: fix speed measurement in the speed benchmark
The shown speed is inversely proportional to the data size.
See the output:

  spi-nand: spi_nand nand@0: Micron SPI NAND was found.
  spi-nand: spi_nand nand@0: 256 MiB, block size: 128 KiB, page size: 2048, OOB size: 128
  ...
  => mtd read.benchmark spi-nand0 $loadaddr 0 0x40000
  Reading 262144 byte(s) (128 page(s)) at offset 0x00000000
  Read speed: 63kiB/s
  => mtd read.benchmark spi-nand0 $loadaddr 0 0x20000
  Reading 131072 byte(s) (64 page(s)) at offset 0x00000000
  Read speed: 127kiB/s
  => mtd read.benchmark spi-nand0 $loadaddr 0 0x10000
  Reading 65536 byte(s) (32 page(s)) at offset 0x00000000
  Read speed: 254kiB/s

In the spi-nand case 'io_op.len' is not always the same as 'len', thus
we are using the wrong amount of data to derive the speed.

Also make sure we are using 64-bit calculation to get a more precise
results.

Fixes: d246e70cf8 ("cmd: mtd: Enable speed benchmarking")
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2025-10-05 20:26:49 +02:00
Mikhail Kshevetskiy
642f150bcd cmd: mtd: add nand_read_test command support
This patch implements read-only test of nand flash devices.

Test reads blocks of NAND flash in normal and raw modes and compares
results. The following statuses can be returned for a block:
 * non-ecc reading failed,
 * ecc reading failed,
 * block is bad,
 * bitflips is above maximum,
 * actual number of biflips above reported one,
 * bitflips reached it maximum value,
 * bitflips above threshold,
 * block is ok.

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2025-10-05 20:26:46 +02:00
Mikhail Kshevetskiy
b89b0f3c47 cmd: mtd: add nand_write_test command support
Some nand flashes (like spi-nand one) are registered with mtd
subsystem only, thus nand command can't be used to work with
such flashes. As result some functionality is missing.

This patch implements 'nand torture' functionality for mtd command.

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2025-10-05 20:26:43 +02:00
Mikhail Kshevetskiy
21c1098cf4 cmd: mtd: add markbad command support
Some nand flashes (like spi-nand one) are registered with mtd
subsystem only, thus nand command can't be used to work with
such flashes. As result some functionality is missing.

This patch implements 'nand markbad' functionality for mtd command.

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2025-10-05 20:26:40 +02:00
Mikhail Kshevetskiy
e55069fab4 mtd: spinand: repeat reading in regular mode if continuous reading fails
Continuous reading may result in multiple flash pages reading in one
operation. Unfortunately, not all spinand controllers support such
large reading. They will read less data. Unfortunately, the operation
can't be continued.

In this case:
 * disable continuous reading on this (not good enough) spi controller
 * repeat reading in regular mode.

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2025-10-05 20:26:38 +02:00
Mikhail Kshevetskiy
5ded13d1e2 mtd: spinand: try a regular dirmap if creating a dirmap for continuous reading fails
Continuous reading may result in multiple flash pages reading in one
operation. Typically only one flash page has read/written (a little bit
more than 2-4 Kb), but continuous reading requires the spi controller
to read up to 512 Kb in one operation without toggling CS in beetween.

Roughly speaking spi controllers can be divided on 2 categories:
 * spi controllers without dirmap acceleration support
 * spi controllers with dirmap acceleration support

Firt of them will have issues with continuous reading if restriction on
the transfer length is implemented in the adjust_op_size() handler.
Second group often supports acceleration of single page only reading.
Thus enabling of continuous reading can break flash reading.

This patch tries to create dirmap for continuous reading first and
fallback to regular reading if spi controller refuses to create it.

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2025-10-05 20:26:35 +02:00
Mikhail Kshevetskiy
e74f706334 mtd: spinand: fix direct mapping creation sizes
Continuous mode is only supported for data reads, thus writing
requires only single flash page mapping.

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2025-10-05 20:26:33 +02:00
Mikhail Kshevetskiy
2cbdd3e449 mtd: spinand: Sync core code and device support with Linux 6.17-rc1
This makes the U-Boot SPI NAND driver almost the same as in Linux
6.17-rc1. The only major differences are:
 * support of ECC engines. The Linux driver supports different ECC
   engines while U-Boot uses on-die ECC only.
 * per operation maximum SPI bus frequency

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2025-10-05 20:26:30 +02:00
Miquel Raynal
1e103284a5 mtd: spinand: Add a ->configure_chip() hook
There is already a manufacturer hook, which is manufacturer specific but
not chip specific. We no longer have access to the actual NAND identity
at this stage so let's add a per-chip configuration hook to align the
chip configuration (if any) with the core's setting.

This is a port of linux commit
da55809ebb45 ("mtd: spinand: Add a ->configure_chip() hook")

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> # U-Boot port
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2025-10-05 20:26:27 +02:00
Gabor Juhos
f61362c24f mtd: spinand: propagate spinand_wait() errors from spinand_write_page()
Since commit 3d1f08b032dc ("mtd: spinand: Use the external ECC engine
logic") the spinand_write_page() function ignores the errors returned
by spinand_wait(). Change the code to propagate those up to the stack
as it was done before the offending change.

This is a port of linux commit
091d9e35b85b ("mtd: spinand: propagate spinand_wait() errors from spinand_write_page()")

Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> # U-Boot port
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2025-10-05 20:26:24 +02:00
Mikhail Kshevetskiy
ccc6b42adc mtd: spinand: Enhance the logic when picking a variant
Currently the best variant picked in the first one in the list provided
in the manufacturer driver. This worked well while all operations where
performed at the same speed, but with the introduction of DTR transfers
this no longer works correctly.

Let's continue iterating over all the alternatives, even if we find a
match, keeping a reference over the theoretically fastest
operation. Only at the end we can tell which variant is the best.

This logic happening only once at boot.

The patch is based on linux commit
666c299be696 (mtd: spinand: Enhance the logic when picking a variant)
created by Miquel Raynal <miquel.raynal@bootlin.com>

The code was a bit restricted in the functionality since not all
required functionality is supported in the u-boot.

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2025-10-05 20:26:22 +02:00
Mikhail Kshevetskiy
37f0fc45f5 mtd: spinand: add OTP support
The code was ported from linux-6.15

based on a linux commit c06b1f753bea (mtd: spinand: add OTP support)
created by Martin Kurbanov <mmkurbanov@salutedevices.com>

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2025-10-05 20:26:19 +02:00
Cheng Ming Lin
49b855662f mtd: spinand: Add read retry support
When the host ECC fails to correct the data error of NAND device,
there's a special read for data recovery method which can be setup
by the host for the next read. There are several retry levels that
can be attempted until the lost data is recovered or definitely
assumed lost.

This is the port of linux commit
f2cb43c98010 (mtd: spinand: Add read retry support)

Signed-off-by: Cheng Ming Lin <chengminglin@mxic.com.tw>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> # U-Boot port
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2025-10-05 20:26:17 +02:00
Mikhail Kshevetskiy
90772e4503 mtd: spinand: add support of continuous reading mode
The code was ported from linux-6.12. The original continuous reading
support was implemented by Miquel Raynal <miquel.raynal@bootlin.com>
in linux commit 631cfdd0520d (mtd: spi-nand: Add continuous read support).

Here is an original patch description:
--------------------------------------
A regular page read consist in:
- Asking one page of content from the NAND array to be loaded in the
  chip's SRAM,
- Waiting for the operation to be done,
- Retrieving the data (I/O phase) from the chip's SRAM.

When reading several sequential pages, the above operation is repeated
over and over. There is however a way to optimize these accesses, by
enabling continuous reads. The feature requires the NAND chip to have a
second internal SRAM area plus a bit of additional internal logic to
trigger another internal transfer between the NAND array and the second
SRAM area while the I/O phase is ongoing. Once the first I/O phase is
done, the host can continue reading more data, continuously, as the chip
will automatically switch to the second SRAM content (which has already
been loaded) and in turns trigger the next load into the first SRAM area
again.

From an instruction perspective, the command op-codes are different, but
the same cycles are required. The only difference is that after a
continuous read (which is stopped by a CS deassert), the host must
observe a delay of tRST. However, because there is no guarantee in Linux
regarding the actual state of the CS pin after a transfer (in order to
speed-up the next transfer if targeting the same device), it was
necessary to manually end the continuous read with a configuration
register write operation.

Continuous reads have two main drawbacks:
* They only work on full pages (column address ignored)
* Only the main data area is pulled, out-of-band bytes are not
  accessible. Said otherwise, the feature can only be useful with on-die
  ECC engines.

Performance wise, measures have been performed on a Zynq platform using
Macronix SPI-NAND controller with a Macronix chip (based on the
flash_speed tool modified for testing sequential reads):
- 1-1-1 mode: performances improved from +3% (2-pages) up to +10% after
              a dozen pages.
- 1-1-4 mode: performances improved from +15% (2-pages) up to +40% after
              a dozen pages.

This series is based on a previous work from Macronix engineer Jaime
Liao.
--------------------------------------

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2025-10-05 20:26:15 +02:00
Takahiro Kuwano
042a78d9bb mtd: spinand: Introduce a way to avoid raw access
SkyHigh spinand device has ECC enable bit in configuration register but
it must be always enabled. If ECC is disabled, read and write ops
results in undetermined state. For such devices, a way to avoid raw
access is needed.

Introduce SPINAND_NO_RAW_ACCESS flag to advertise the device does not
support raw access. In such devices, the on-die ECC engine ops returns
error to I/O request in raw mode.

Checking and marking BBM need to be cared as special case, by adding
fallback mechanism that tries read/write OOB with ECC enabled.

This is a port of linux commit
6d9d6ab3a82a (mtd: spinand: Introduce a way to avoid raw access)

Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> # U-Boot port
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2025-10-05 20:26:13 +02:00
Takahiro Kuwano
4d135d8a85 mtd: spinand: Remove write_enable_op() in markbad()
We don't have to call spinand_write_enable_op() in spinand_markbad() as
it is called in spinand_write_page().

This is the port of linux commit
c6858779f1f5 (mtd: spinand: Remove write_enable_op() in markbad())

Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> # U-Boot port
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2025-10-05 20:26:10 +02:00
Cheng Ming Lin
b4c502a286 mtd: spinand: Add support for setting plane select bits
Add two flags for inserting the Plane Select bit into the column
address during the write_to_cache and the read_from_cache operation.

Add the SPINAND_HAS_PROG_PLANE_SELECT_BIT flag for serial NAND flash
that require inserting the Plane Select bit into the column address
during the write_to_cache operation.

Add the SPINAND_HAS_READ_PLANE_SELECT_BIT flag for serial NAND flash
that require inserting the Plane Select bit into the column address
during the read_from_cache operation.

This is a port of linux commit
ca229bdbef29 (mtd: spinand: Add support for setting plane select bits)

Signed-off-by: Cheng Ming Lin <chengminglin@mxic.com.tw>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20240909092643.2434479-2-linchengming884@gmail.com
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> # U-Boot port
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2025-10-05 20:26:08 +02:00
Daniel Golle
d488490abd mtd: spinand: set bitflip_threshold to 75% of ECC strength
Reporting an unclean read from SPI-NAND only when the maximum number
of correctable bitflip errors has been hit seems a bit late.
UBI LEB scrubbing, which depends on the lower MTD device reporting
correctable bitflips, then only kicks in when it's almost too late.

Set bitflip_threshold to 75% of the ECC strength, which is also the
default for raw NAND.

This is a port of linux commit
1824520e7477 (mtd: spinand: set bitflip_threshold to 75% of ECC strength)

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/2117e387260b0a96f95b8e1652ff79e0e2d71d53.1723427450.git.daniel@makrotopia.org
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> # U-Boot port
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2025-10-05 20:26:06 +02:00
Mikhail Kshevetskiy
2a0f8e7da0 mtd: spinand: Sync core code and device support with Linux 6.10
This makes the U-Boot SPI NAND driver almost the same as in Linux 6.10.
The only major difference is support of ECC engines. The Linux driver
supports different ECC engines while U-Boot uses on-die ECC only.

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2025-10-05 20:26:03 +02:00
Mikhail Kshevetskiy
e644bb73da mtd: spinand: Refactor ECC/OOB functions
changes:
 * Move spinand_check_ecc_status(), spinand_noecc_ooblayout_ecc(),
   spinand_noecc_ooblayout_free() and spinand_noecc_ooblayout close
   to each other.
 * some code formatting
 * remove comments not present in linux driver

This aligns the code with Linux 6.10.

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2025-10-05 20:26:00 +02:00
Mikhail Kshevetskiy
a3770a6325 mtd: spinand: Refactor spinand_init* functions
No functional changes, just some refactoring to better match linux
kernel driver.

changes:
 * move spinand configuration reading out from spinand_init_cfg_cache()
   to separate function spinand_read_cfg()
 * move spinand flash initialization to separate function
   spinand_init_flash()
 * move direct mapping initialization to the end of spinand_init()

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2025-10-05 20:25:58 +02:00
Mikhail Kshevetskiy
4254ed38ec mtd: spinand: Align logic for enabling ECC to match Linux kernel
This aligns the logic to match the Linux kernel implementation.

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2025-10-05 20:25:56 +02:00
Mikhail Kshevetskiy
5faba88f98 mtd: spinand: Make use of spinand_to_[mtd/nand]() helpers
Use spinand_to_nand() and spinand_to_mtd() helpers instead of
nanddev_to_mtd() and direct access to spinand structure fields.

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2025-10-05 20:25:54 +02:00
Mikhail Kshevetskiy
64b7865c72 mtd: spinand: Extend spinand_wait() to match Linux kernel implementation
This aligns spinand_wait() with the linux kernel. Instead of calling into
spi_mem_poll_status() which is not implemented in U-Boot, we code the
polling logic and make sure that schedule() is called periodically.

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2025-10-05 20:25:51 +02:00
Alexander Lobakin
bae27e402d mtd: spinand: core: add missing MODULE_DEVICE_TABLE()
The module misses MODULE_DEVICE_TABLE() for both SPI and OF ID tables
and thus never autoloads on ID matches.
Add the missing declarations.
Present since day-0 of spinand framework introduction.

This is a port of linux commit
25fefc88c71f ("mtd: spinand: core: add missing MODULE_DEVICE_TABLE()")

Signed-off-by: Alexander Lobakin <alobakin@pm.me>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20210323173714.317884-1-alobakin@pm.me
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> # U-Boot port
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2025-10-05 20:25:49 +02:00
Miquel Raynal
9ce01e0ada mtd: nand: Add a NAND page I/O request type
Use an enum to differentiate the type of I/O (reading or writing a
page). Also update the request iterator.

This is a port of linux commit
701981cab016 ("mtd: nand: Add a NAND page I/O request type")

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Link: https://lore.kernel.org/linux-mtd/20200827085208.16276-5-miquel.raynal@bootlin.com
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> # U-Boot port
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2025-10-05 20:25:47 +02:00
Mikhail Kshevetskiy
aecd0bd412 mtd: spinand: Use the spi-mem dirmap API
Make use of the spi-mem direct mapping API to let advanced controllers
optimize read/write operations when they support direct mapping.

Based on a linux commit 981d1aa0697c ("mtd: spinand: Use the spi-mem dirmap API")
created by Boris Brezillon <bbrezillon@kernel.org> with additional
fixes taken from Linux 6.10.

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2025-10-05 20:25:44 +02:00
Mikhail Kshevetskiy
ce6a23e7e8 spi: spi-mem: Extend SPI MEM ops to match Linux 6.16
This pulls in multiple changes from the Linux kernel in order to keep
the code in sync. This also fixes octal mode support.

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2025-10-05 20:25:37 +02:00
Tom Rini
4e4a9de31d Merge branch 'next' of git://source.denx.de/u-boot-usb into next
- Make the i2c-bus property for an onboard USB hub optional
2025-10-05 09:50:57 -06:00
Michal Simek
f4dd112a38 usb: onboard-hub: Make i2c-bus optional
DT binding doesn't mandate i2c-bus as required property because hub itself
doesn't need to have i2c connected.
It can be in standalone mode that only power regulator and reset should be
handled.
Or hub should be configured via spi interface.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Marek Vasut <marek.vasut@mailbox.org>
2025-10-05 06:11:44 +02:00
Tom Rini
eede1fccec Merge patch series "Drop ATAGS for B&R boards"
Wolfgang Wallner <wolfgang.wallner@br-automation.com> says:

There was recently a discussion on which boards need ATAGS support.
The B&R boards which have this support enabled actualyl don't need it.
This patch series drops the settings from the relevant defconfigs.

Link: https://lore.kernel.org/r/20250919134308.122437-1-wolfgang.wallner@br-automation.com
2025-10-03 16:55:44 -06:00
Tom Rini
601cebc29d cmd: spl: Remove ATAG support from this command
While we continue to have some systems which support extremely legacy
OS booting methods, we do not have use cases for supporting this in
Falcon mode anymore. Remove this support and references from the
documentation.

Co-developed-by: Anshul Dalal <anshuld@ti.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-10-03 16:55:44 -06:00
Marek Vasut
70ae44f371 linux/kernel.h: Update upper_NN_bits() and lower_NN_bits() macros
Synchronize upper_NN_bits() and lower_NN_bits() macros with Linux 6.16
commit 118d777c4cb4 ("wordpart.h: Add REPEAT_BYTE_U32()"). This fixes the
lower_32_bits() macros and assures it works with 64bit systems correctly.
This also adds 16bit variants of these macros, which will be used by the
Airoha PHY driver.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2025-10-03 16:55:18 -06:00
Wolfgang Wallner
de8f386810 configs: brcp170: Drop CONFIG_SUPPORT_PASSING_ATAGS
CONFIG_SUPPORT_PASSING_ATAGS is not needed for this board.

Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2025-10-03 15:19:08 -06:00
Wolfgang Wallner
92c2effbbf configs: brcp150: Drop CONFIG_SUPPORT_PASSING_ATAGS
CONFIG_SUPPORT_PASSING_ATAGS is not needed for this board.

Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2025-10-03 15:19:07 -06:00
Wolfgang Wallner
5c9dffa405 configs: brcp1: Drop CONFIG_SUPPORT_PASSING_ATAGS
CONFIG_SUPPORT_PASSING_ATAGS is not needed for these boards.

Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2025-10-03 15:19:07 -06:00
Anshul Dalal
8fd3768ca1 arm: armv8: remove redundant definition of mmu_status
mmu_status is used in io memcpy functions to prevent accesses to non
8-byte aligned addresses when the mmu is disabled. Though there is a
redundant definition enabled when icaches is turned off by setting
SYS_ICACHE_OFF.

This patch removes the redundant definition, allowing mmu_status to
properly report the status regardless of config settings. This shouldn't
be a problem since access to non 8-byte aligned data can be done
irrespective of icache state.

Fixes: 268f6ac1f9 ("arm64: Update memcpy_{from, to}io() helpers")

Signed-off-by: Anshul Dalal <anshuld@ti.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-10-03 15:13:58 -06:00
Michal Simek
e589d5822c env: spi: Fix gd->env_valid for the first write
When both SPI environment locations are invalid (gd->env_valid ==
ENV_INVALID), the first call to saveenv writes to the primary location and
sets the active flag. However, the logic for updating gd->env_valid
incorrectly sets it to ENV_REDUND, which does not match the actual location
written. This causes the first two writes to target the same location, and
alternation only begins after the second write.

Update the logic to alternate gd->env_valid based on whether the last write
was to the primary or redundant location, ensuring the first write sets
ENV_VALID and subsequent writes alternate as expected. This aligns
env_valid with the actual storage location and fixes the alternation
sequence from the first write.

With this change, the "Valid environment" printout correctly reflects the
active location after each save, and the alternation between primary and
redundant locations works as intended from the start.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Marek Vasut <marek.vasut@mailbox.org>
Acked-by: E Shattow <e@freeshell.de>
2025-10-02 11:32:34 -06:00
Tom Rini
a14253b15c Merge tag 'u-boot-dfu-next-20251001' of https://source.denx.de/u-boot/custodians/u-boot-dfu into next
u-boot-dfu-next-20251001

CI:
- https://source.denx.de/u-boot/custodians/u-boot-dfu/-/pipelines/27791

Fastboot:
- Fix has-slot command when using nand back-end.

USB gadget:
- Add missing null checks to atmel, dwc2 drivers (smatch)
- Remove redundant check in dwc3 gadget (smatch)
2025-10-02 11:20:01 -06:00
Tom Rini
aff68c8514 Merge tag 'u-boot-socfpga-next-20250930' of https://source.denx.de/u-boot/custodians/u-boot-socfpga into next
SoCFPGA updates for v2025.10:

CI: https://source.denx.de/u-boot/custodians/u-boot-socfpga/-/pipelines/27762

This pull request brings a set of updates across SoCFPGA platforms
covering Agilex5, Agilex7, N5X, and Stratix10. The changes include:

* Agilex5 enhancements:
  - USB3.1 enablement and DWC3 host driver support
  - System Manager register configuration for USB3
  - Watchdog timeout increase and SDMMC clock API integration
  - dcache handling improvements in SMC mailbox path
  - Enable SPL_SYS_DCACHE_OFF in defconfig

* Clock driver improvements:
  - Introduce dt-bindings header for Agilex clocks
  - Add enable/disable API and EMAC clock selection fixes
  - Replace manual shifts with FIELD_GET usage

* DDR updates:
  - IOSSM mailbox compatibility check
  - Correct DDR calibration status handling

* Device tree changes:
  - Agilex5: disable cache allocation for reads
  - Stratix10: add NAND IP node
  - Enable driver model watchdog
  - Enable USB3.1 node for Agilex5

* Config cleanups:
  - Simplify Agilex7 VAB defconfig
  - Remove obsolete SYS_BOOTM_LEN from N5X VAB config
  - Enable CRC32 support for SoCFPGA
  - Increase USB hub debounce timeout

Overall this set improves reliability of DDR and cache flows,
adds missing USB and MMC features for Agilex5, and refines clock
and configuration handling across platforms.

This patch set has been tested on Agilex 5 devkit, and Agilex devkit.
2025-09-30 16:11:23 -06:00
Tom Rini
667b9ef5b0 Merge tag 'u-boot-amlogic-next-20250930' of https://source.denx.de/u-boot/custodians/u-boot-amlogic into next
- set reversed bit when using internal phy on GXL SoCs
- support gpio toggle command for amlogic gpio
- fix saradc
- remove unreachable in meson clk driver
- Stop premature exit from for loop in meson pwm driver
- fix JetHub D1 eth mac fallback generation
2025-09-30 16:01:05 -06:00
Viacheslav Bocharov
d521fa32cc ARM: amlogic: fix JetHub D1 eth mac fallback generation
JetHome has allocated a special range for MAC fallback on JetHub D1/D1+
devices.

Signed-off-by: Viacheslav Bocharov <adeep@lexina.in>
Link: https://lore.kernel.org/r/20250903110726.546083-1-adeep@lexina.in
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2025-09-30 20:32:15 +02:00
Andrew Goodbody
b1e2cbd65c pwm: meson: Stop premature exit from for loop
In meson_pwm_probe the for loop attempts to get the name of a clock but
the following if..else statements only perform useful work if -ENODATA
is returned from clk_get_by_name. If clk_get_by_name simply succeeds
then this results in a premature exit from the for loop and the
following code can never be reached. Make the else clause only apply for
an error return from clk_get_by_name.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250808-pwm_meson-v1-1-cddb7e5f76bd@linaro.org
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2025-09-30 20:32:15 +02:00
Andrew Goodbody
bb2d7ea6f2 clk: meson: Remove unreachable code
A second return following the first return is unreachable code so remove
it.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250723-clk_meson-v1-1-8cd6e73145a4@linaro.org
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2025-09-30 20:32:15 +02:00
Andrew Goodbody
b332723882 adc: meson-saradc: uint cannot be less than zero
timeout is declared as a uint but then tested for being less than zero
which must always fail. Change the while loop for a pre-decrement on
timeout and test timeout for being zero.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250722-meson_saradc-v1-1-1ab45d53da9d@linaro.org
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2025-09-30 20:32:15 +02:00
Yang Xiwen
033dbc7f9e pinctrl: meson: support gpio toggle command
meson_gpio_get() always assumes gpio is configured to input mode. This
is incorrect and breaks `gpio toggle` command:

gpio: pin aobus-banks2 (gpio 2) value is 0
   Warning: value of pin is still 1

Fix it by adding the logic to handle both input and output mode.

Fixes: 2009a8d03f ("pinctrl: meson: add GPIO support")
Signed-off-by: Yang Xiwen <forbidden405@outlook.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250617-meson_ppinctrl-v3-1-218d9321a8d2@outlook.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2025-09-30 20:32:15 +02:00
Neil Armstrong
1a367adfd6 net: mdio: mux-meson-gxl: set reversed bit when using internal phy
This bit is necessary to receive packets from the internal PHY.
Without this bit set, no activity occurs on the interface.

Normally u-boot sets this bit, but if u-boot is compiled without
net support, the interface will be up but without any activity.

The vendor SDK sets this bit along with the PHY_ID bits.

Ported from the Linux change at [1] from Da Xu merged in
commit [2].

[1] https://lore.kernel.org/all/20250425192009.1439508-1-da@libre.computer/
[2] b23285e93bef ("net: mdio: mux-meson-gxl: set reversed bit when using internal phy")

Suggested-by: Da Xue <da@libre.computer>
Link: https://lore.kernel.org/r/20250502-u-boot-topic-mdio-mux-gxl-bit28-v1-1-399f6c3db154@linaro.org
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2025-09-30 20:32:15 +02:00
Andrew Goodbody
8cd4a5e94b usb: dwc3: Remove redundant test
In dwc3_ep0_complete_data there is a test for 'r' being null and the
code will return at that point if so. After that point 'r' is guaranteed
to not be null and testing for that is redundant. Remove the test for
'r' being non-null.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Reviewed-by: Marek Vasut <marek.vasut@mailbox.org>
Link: https://lore.kernel.org/r/20250929-dwc3_ep0-v1-1-1d5c58933bde@linaro.org
Signed-off-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
2025-09-30 11:55:23 +02:00
Andrew Goodbody
5ac61383b2 usb: dwc2: Add missing null check
Add in the missing null check for dev->driver that is present at other
points in the function before it is dereferenced.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Reviewed-by: Marek Vasut <marek.vasut@mailbox.org>
Link: https://lore.kernel.org/r/20250929-usb_dwc2-v1-1-863133dcbcde@linaro.org
Signed-off-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
2025-09-30 11:53:10 +02:00
Andrew Goodbody
f586675872 usb: gadget: atmel: Add missing null check
Add in the missing null check for udc->driver that is present at other
points in the function before it is dereferenced.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Reviewed-by: Marek Vasut <marek.vasut@mailbox.org>
Link: https://lore.kernel.org/r/20250929-atmel_usba_udc-v1-1-e1426271e12a@linaro.org
Signed-off-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
2025-09-30 11:51:17 +02:00
Chance Yang
3ce8a0e911 fastboot: Fix has-slot command always returning yes for fb_nand
The issue was a mismatch in return value conventions between functions:
- getvar_get_part_info() expects >= 0 for success
- fb_nand_lookup() returns 0 on success, 1 on failure (from
mtdparts_init and find_dev_and_part)

When partition didn't exist, fb_nand_lookup returned 1, but
fastboot_nand_get_part_info passed it directly to getvar_get_part_info,
which treated 1 >= 0 as success, causing has-slot to always return yes.

Fix by converting positive return values to -ENOENT in
fastboot_nand_get_part_info to match the expected error convention.

Signed-off-by: Chance Yang <chance.yang@kneron.us>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Link: https://lore.kernel.org/r/20250826-master-v2-1-30b787a2f9fd@kneron.us
Signed-off-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
2025-09-30 11:48:51 +02:00
Naresh Kumar Ravulapalli
da57acb4c3 arch: arm: socfpga: Configure USB3 System Manager registers
For successful reset staggering pulse operation, reset pulse
override bit is set. Port overcurrent bit 1, which in reality
reflects PIPE power present signal is set to avoid giving
false information of Vbus status to HPS controller.

Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-09-30 14:45:37 +08:00
Naresh Kumar Ravulapalli
060ed1bbbe configs: Increase USB Hub debounce timeout in Agilex5
Some legacy USB mass storage devices during connection were
observed to have debounce issues. Hence, increasing the default
USB Hub debounce timeout value to handle this issue for devices
connected to Agilex5 boards.

Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-09-30 14:29:57 +08:00
Naresh Kumar Ravulapalli
61c4768d83 configs: Enable USB DWC3 host drivers for Agilex5
Required USB DWC3 host driver configurations are enabled
for Agilex5.

Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-09-30 14:29:56 +08:00
Naresh Kumar Ravulapalli
e3a11a240a arch: arm: dts: Enable USB3.1 for Agilex5
USB 3.1 node is enabled for Agilex5.

Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-09-30 14:29:56 +08:00
Naresh Kumar Ravulapalli
2ff686bcfd drivers: clk: agilex: Use FIELD_GET during EMAC clock selection
FIELD_GET() macro is used during EMAC clock source selection
for better code readability and maintainability.

Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-09-30 14:29:56 +08:00
Naresh Kumar Ravulapalli
924a9fc402 drivers: clk: agilex: Fix EMAC clock source selection
Fix the incorrect bit masking and bit shift used to compute EMAC
control which in turn is used to select EMAC clock from EMAC
source A or B.

Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-09-30 14:29:56 +08:00
Alif Zakuan Yuslaimi
ab27182cac mmc: socfpga_dw_mmc: Enable/disable SDMMC clock via API
Update the driver to enable or disable the SDMMC clock via
clock driver model API instead of doing it in the driver itself.

This allows for scalability of the driver for various SoCFPGA
devices.

Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-09-30 14:29:55 +08:00
Boon Khai Ng
190a339ae3 configs: agilex5: Enable config SPL_SYS_DCACHE_OFF
Add SPL_SYS_DCACHE_OFF to Agilex5 defconfig to disable data cache for SPL

Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@altera.com>
Signed-off-by: Boon Khai Ng <boon.khai.ng@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-09-30 14:29:55 +08:00
Alif Zakuan Yuslaimi
022b2159b5 drivers: clk: agilex: Support for enable/disable API
Update Agilex clock driver to support enabling or disabling
the peripheral clocks via clock driver model APIs.

The caller will pass the clock ID to this driver and the driver
will then proceed to manipulate the desired bit in the Agilex clock
manager peripheral PLL register based on the given clock ID.

Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-09-30 14:29:55 +08:00
Boon Khai Ng
38d49808d4 cache: Check dcache availability before calling cache functions
When the data cache (dcache) is disabled, calling related
status functions can lead to compilation errors due to
undefined references.

Adding a !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) check before
invoking dcache_status() (used in common/memsize.c:get_ram_size())
and mmu_status() (from arch/arm/include/asm/io.h).

Without this check, builds with dcache disabled will fail to compile.

Signed-off-by: Boon Khai Ng <boon.khai.ng@altera.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2025-09-30 14:29:55 +08:00
Alif Zakuan Yuslaimi
c4e9554015 include: dt-bindings: clk: agilex: Add Agilex clock definitions header file
Introduce header file to define the clock indexes for the Agilex
platform.

Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-09-30 14:29:54 +08:00
Boon Khai Ng
8d28f121d3 arch: arm: mach-socfpga: smc: Add dcache flushing and invalidation in smc_send_mailbox()
Adding the dcache flushing and invalidation in the smc_send_mailbox()
At the same time replace the use of u64 with uintptr_t to ensure
compatibility across different architectures and correct the
pointer arithmetic for buffer end address calculation.

Signed-off-by: Mahesh Rao <mahesh.rao@altera.com>
Signed-off-by: Boon Khai Ng <boon.khai.ng@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-09-30 14:29:54 +08:00
Alif Zakuan Yuslaimi
36e013490e configs: agilex5: Increase watchdog timeout
Linux kernel will fail to boot due to exceeding timeout trying to
probe I3C device.

Increasing the watchdog timeout 30 seconds will give enough time for
Linux to probe the I3C device and will be able to boot up successfully.

User is expected to fine tune the watchdog timeout for the complete
boot in production.

Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-09-30 14:29:54 +08:00
Alif Zakuan Yuslaimi
f4db066455 arm: socfpga: mailbox: Remove CONFIG_CADENCE_QSPI guard from QSPI mailbox API declarations
The QSPI mailbox API function declarations (mbox_qspi_close and
mbox_qspi_open) in mailbox_s10.h were guarded by CONFIG_CADENCE_QSPI
preprocessor conditional. This prevented their prototypes from being
visible to code that may use the stub implementations when
CONFIG_CADENCE_QSPI is disabled.

Remove the CONFIG_CADENCE_QSPI preprocessor conditional so these functions
are always declared, regardless of the configuration. This avoids potential
build or linkage errors when stubs are used.

Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-09-30 14:29:54 +08:00
Alif Zakuan Yuslaimi
fb7aa75561 arm: socfpga: Define Use FPGA switch handoff section size for Agilex5
Agilex5 FPGA switch section in the handoff data is larger by 32 bytes
than the default value as these extra sections contains I3C0 and I3C1
register offsets and values with 4 bytes each.

This requires 4 more times of reading the FPGA switch section of the
handoff data to fully populate the handoff data table in the memory
during runtime.

Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-09-30 14:29:53 +08:00
Naresh Kumar Ravulapalli
63ef1c7a73 drivers: ddr: altera: Correct DDR calibration status check
Bit 3 of the seq2core register is no longer set to indicate
calibration completion. Instead, added polling of the seq2core
register until it reads 0b00000111, signaling that the Nios
processor has started the calibration process.

Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-09-30 14:29:53 +08:00
Naresh Kumar Ravulapalli
5d2ef97c66 drivers: ddr: altera: Check IOSSM mailbox compatibility
Compatibility check of IOSSM mailbox with U-Boot is performed
by verifying the mailbox specification version. If check fails,
appropriate error message is displayed.

Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-09-30 14:29:53 +08:00
Naresh Kumar Ravulapalli
3d084d91ed configs: socfpga: Remove SYS_BOOTM_LEN from N5X VAB config
Remove the current CONFIG_SYS_BOOTM_LEN in N5X VAB defconfig.
Previously, the size was set to 32MB, but due to larger kernel image,
64MB size is required. This 64MB configuration has been set as
default in the Kconfig.

Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-09-30 14:29:53 +08:00
Naresh Kumar Ravulapalli
65261e83f3 configs: socfpga: Add CRC32 support
CRC32 support for SoC64 devices is added.

Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-09-30 14:29:52 +08:00
Naresh Kumar Ravulapalli
2a7771166e configs: Simplify Agilex7 VAB defconfig
To ensure unintentional bugs occurring because of config changes
in master defconfig and its VAB variants, VAB defconfig files now
include the master defconfig and enable config values specific to
VAB functionality only.

Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-09-30 14:29:52 +08:00
Naresh Kumar Ravulapalli
26ffc37787 arm: dts: socfpga: Enable driver model for watchdog timer
All SoCFPGA platforms are switching to CONFIG_WDT (driver
model for watchdog timer drivers) from CONFIG_HW_WATCHDOG. Status
of watchdog is enabled to assist with this switching.

Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-09-30 14:29:52 +08:00
Naresh Kumar Ravulapalli
27e13c9c8d arch: arm: socfpga: Remove speed and mode from flash probe
Change is to allow the user to choose speed and mode values
from dts or the default ones.

Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-09-30 14:29:51 +08:00
Naresh Kumar Ravulapalli
f6dbe41638 arch: arm: dts: stratix10: Add NAND IP to base dtsi
Add NAND node to the base stratix10 dtsi file.

Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-09-30 14:06:57 +08:00
Naresh Kumar Ravulapalli
f0e722def6 arch: arm: dts: agilex5: Disable cache allocation for reads
In order to circumvent CCU NOC issue in Agilex5, it is recommended
to disable cache allocation for reads. This prevents hang issues
caused by CCP (Common Cache Pipe) Fill Done FIFO overflow.

Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-09-30 12:30:12 +08:00
Tom Rini
9710d98e89 Merge tag 'doc-next-2025-09-27' of https://source.denx.de/u-boot/custodians/u-boot-efi into next
Pull request doc-next-2025-09-27

CI:

* https://source.denx.de/u-boot/custodians/u-boot-efi/-/pipelines/27746

Documentation:

* Move ext4 documentation to HTML.
* Describe configuration option EXT4_MAX_JOURNAL_ENTRIES and
  memory ext4 journal memory requirements.
2025-09-27 09:49:01 -06:00
Tony Dinh
1998334d5a doc: usage: Add File System section and Ext4 documentation
Create doc/usage/filesystems/ section.
Convert doc/README.ext4 to rST format and move it to the new section.
Update documentation to add configuration instruction for Ext4 Write
when using large partitions.

Note that this patch depends on this previous patch:
https://patchwork.ozlabs.org/project/uboot/patch/20250910215702.15576-1-mibodhi@gmail.com/

Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Anshul Dalal <anshuld@ti.com>
2025-09-27 09:09:47 +02:00
Tony Dinh
6578475a96 doc: ext4fs: update documentation for Ext4 Write configuration
Update documentation for how to configure Ext4 Write when using large
partitions.

Signed-off-by: Tony Dinh <mibodhi@gmail.com>
2025-09-27 09:03:50 +02:00
Tom Rini
6190036e23 Merge patch series "vexpress63: Set the DM_RNG property"
This series from Debbie Horsfall <debbie.horsfall@arm.com> enhances the
Vexpress64 platform in a few ways.

Link: https://lore.kernel.org/r/20250917162222.1061111-1-debbie.horsfall@arm.com
2025-09-26 16:49:37 -06:00
Debbie Horsfall
1f3f1e090a arm: vexpress64: Enable SYSRESET and SYSRESET_PSCI
Select SYSRESET on Vexpress64 to enable system reset to support other
features, such as capsule-on-disk. Select SYSRESET_PSCI if PSCI is
inferred from the firmware (via ARM_PSCI_FW).
Select ARM_SMCCC for Vexpress64 boards which in turn selects
ARM_PSCI_FW.

The sysreset uclass unconditionally implements a reset_cpu() function.
Remove the empty reset_cpu() in vexpress64 board code.

Signed-off-by: Debbie Horsfall <debbie.horsfall@arm.com>
2025-09-26 16:49:37 -06:00
Debbie Horsfall
2767386806 vexpress64: Set the DM_RNG property
Enable the DM_RNG virtio random number generator driver in order to
consume entropy within U-Boot. This allows U-Boot to inject entropy to the
kernel via UEFI, so the kernel can use that early, for instance for
address layout randomisation, or when the kernel does not provide an
entropy driver itself.

Signed-off-by: Debbie Horsfall <debbie.horsfall@arm.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2025-09-26 16:49:30 -06:00
Vishnu Singh
b6d9aa6aaf bootstage: stash boot records to reserved mem before kernel handoff
U-Boot now stashes its bootstage buffer into a reserved memory region
whenever CONFIG_BOOTSTAGE_STASH is enabled, just before exiting to the
kernel. This allows a post boot parser to read a unified timeline
(SPL→U-Boot→Kernel→MCU/DSP) directly from DDR, enabling standardized
and repeatable boot-time profiling across releases and SoCs.

Change summary:
 Call bootstage_stash_default() in announce_and_cleanup()
  when CONFIG_BOOTSTAGE_STASH is set.

Reference boot-time parser utility:
 https://github.com/v-singh1/boot-time-parser

Sample boot time report:
    +--------------------------------------------------------------------+
                     am62xx-evm Boot Time Report
    +--------------------------------------------------------------------+
    Device Power On         : 0 ms
    SPL Time                : 843 ms
    U-Boot Time             : 2173 ms
    Kernel handoff time     : 462 ms
    Kernel Time             : 2522 ms
    Total Boot Time         : 6000 ms
    +--------------------------------------------------------------------+

    +--------------------------------------------------------------------+
                     Bootloader and Kernel Boot Records
    +--------------------------------------------------------------------+
    BOOTSTAGE_AWAKE                =      0 ms (+  0 ms)
    BOOTSTAGE_START_UBOOT_F        =    843 ms (+  0 ms)
    BOOTSTAGE_ACCUM_DM_F           =    843 ms (+  0 ms)
    BOOTSTAGE_START_UBOOT_R        =   1951 ms (+1108 ms)
    BOOTSTAGE_ACCUM_DM_R           =   1951 ms (+  0 ms)
    BOOTSTAGE_NET_ETH_START        =   2032 ms (+ 81 ms)
    BOOTSTAGE_NET_ETH_INIT         =   2053 ms (+ 21 ms)
    BOOTSTAGE_MAIN_LOOP            =   2055 ms (+  2 ms)
    BOOTSTAGE_START_MCU            =   2661 ms (+606 ms)
    BOOTSTAGE_BOOTM_START          =   2959 ms (+298 ms)
    BOOTSTAGE_RUN_OS               =   3016 ms (+ 57 ms)
    BOOTSTAGE_BOOTM_HANDOFF        =   3016 ms (+  0 ms)
    BOOTSTAGE_KERNEL_START         =   3478 ms (+462 ms)
    BOOTSTAGE_KERNEL_END           =   6000 ms (+2522 ms)
    +--------------------------------------------------------------------+

    +--------------------------------------------------------------------+
                     MCU Boot Records
    +--------------------------------------------------------------------+
    MCU_AWAKE                      =   2661 ms (+  0 ms)
    BOARD_PERIPHERALS_INIT         =   2661 ms (+  0 ms)
    MAIN_TASK_CREATE               =   2661 ms (+  0 ms)
    FIRST_TASK                     =   2662 ms (+  1 ms)
    DRIVERS_OPEN                   =   2662 ms (+  0 ms)
    BOARD_DRIVERS_OPEN             =   2662 ms (+  0 ms)
    IPC_SYNC_FOR_LINUX             =   6636 ms (+3974 ms)
    IPC_REGISTER_CLIENT            =   6636 ms (+  0 ms)
    IPC_SUSPEND_TASK               =   6636 ms (+  0 ms)
    IPC_RECEIVE_TASK               =   6636 ms (+  0 ms)
    IPC_SYNC_ALL                   =   6787 ms (+151 ms)
    +--------------------------------------------------------------------+

Signed-off-by: Vishnu Singh <v-singh1@ti.com>
2025-09-26 16:48:10 -06:00
Marek Vasut
7c0f1c46f8 arm64: Add MIDR entry for Cortex-A720
Add MIDR entry for Cortex-A720 core.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-09-26 16:47:48 -06:00
Tom Rini
40888b1e4c scripts: checkpatch.pl: Extend some checks to "env" files
In order for the U-Boot specific tests we've added (along with the long
line test) to be run on ".env" files as well, we need to update the line
in the process function that starts to limit the file extensions that we
test on.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-09-26 16:47:06 -06:00
Michal Simek
c8a74db0cd arm: Change SYS_INIT_SP_BSS_OFFSET from int to hex
The most of OFFSET values are in hex instead of int which is easier for
layout description.

Signed-off-by: Michal Simek <michal.simek@amd.com>
2025-09-26 16:46:26 -06:00
Tom Rini
14b784aaf2 Merge patch series "exports overhaul"
Rasmus Villemoes <ravi@prevas.dk> says:

This all started from me wondering "why does this standalone app end
up being so huge"? Oh, it essentially links in its own standard C
library to get strlen() and snprintf(). Which then led to asking "why
don't we export all those standard C functions when we have them
anyway?".

CI has chewed on these and seem happy - it was CI which told me about
the necessity of [1/9]: https://github.com/u-boot/u-boot/pull/813

Link: https://lore.kernel.org/r/20250919101002.568488-1-ravi@prevas.dk
2025-09-26 11:55:55 -06:00
Rasmus Villemoes
07588f4ad9 exports.h: bump XF_VERSION
There have been quite a few changes to _exports.h since the last
update of XF_VERSION, also before the previous patches in this series.

I doubt the mechanism is actually being used in practice, it is simply
too fragile: Not only does the list of exported functions depend on
.config, so with the same XF_VERSION the jump table entries could have
different offsets. But getting to the jump table itself from gd to
even call the ->get_version() is fragile, since offsetof(gd_t, jt)
can, and does, change. For example, as recently as commit
d990210702 ("global_data: Remove jump table in SPL").

One really must build one's standalone app against the proper U-Boot
version and config.h. But for good measure, do bump it now.

Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
Reviewed-by: Tom Rini <trini@konsulko.com>
2025-09-26 11:55:13 -06:00
Rasmus Villemoes
d957061582 _exports.h: export standard memory/string handling functions
The current list of exported functions lacks quite a few bog-standard C
library functions that we might as well expose, since U-Boot certainly
has them implemented anyway. There's no reason a standalone
application should have its own strlen() implementation or link in a
copy from some tiny libc.

For a customer's standalone app, this means it goes from 95K to 10K.
More importantly, we can ditch the custom toolchain including a
newlibc used to build the standalone app and just use the same
toolchain as used to build u-boot itself.

Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
Reviewed-by: Tom Rini <trini@konsulko.com>
2025-09-26 11:55:13 -06:00
Rasmus Villemoes
2ef6c17f7f _exports.h: reorganize a bit
The current list of exported functions is somewhat of a
mess. Reorganize them so that related functionality is kept together:

- console I/O: move vprintf next to printf and the getc/putc functions

- integer parsing: move the *strto* functions together

- standard string.h stuff: move memset() and strcpy() next to strcmp()

- time: move mdelay() next to udelay() and get_timer()

Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
Reviewed-by: Tom Rini <trini@konsulko.com>
2025-09-26 11:55:13 -06:00
Rasmus Villemoes
bdbaaee65c exports.h: make sure declarations are in sync with the actual exports
After finishing a later patch in this series, I discovered I had
neglected to update the list of declarations in exports.h to
match. But then I realized I wasn't the first to do that.

Use the existing mechanism and DRY it out.

Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
Reviewed-by: Tom Rini <trini@konsulko.com>
2025-09-26 11:55:13 -06:00
Rasmus Villemoes
a78941bc7f exports.c: drop unused dummy function
The !CONFIG_PHY_AQUANTIA defines were already superfluous since
_exports.h does have a CONFIG_PHY_AQUANTIA, so the entries never
existed. In fact, it couldn't have worked, because the defines would
affect both occurences of the mdio_get_current_dev identifier in the

	EXPORT_FUNC(mdio_get_current_dev, struct mii_dev *,
		    mdio_get_current_dev, void)

so the C code would end up containing four copies of

  gd->jt->dummy = dummy

but struct jt_funcs would not and does not have any 'dummy' member.

Now that nothing in _exports.h refers to dummy(), remove the empty
function.

Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
Reviewed-by: Tom Rini <trini@konsulko.com>
2025-09-26 11:55:13 -06:00
Rasmus Villemoes
eb178c849c _exports.h: drop the last dummy entries
Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
Reviewed-by: Tom Rini <trini@konsulko.com>
2025-09-26 11:55:13 -06:00
Rasmus Villemoes
475a72f647 _exports.h: simplify condition for including spi functions
As for the i2c functions, drop the dummy entries that, if ever used,
would just have the standalone app get some random content in the
return register.

While deprecated, the spi_{setup,free}_slave functions do exist even
with CONFIG_DM_SPI - and a standalone app can't really do anything but
refer to a spi device via a (bus, cs) pair.

Eventually, one should probably export some function that could allow
a standalone app to get a struct udevice* corresponding to either a
full DT path, an alias, or perhaps a label (provided one builds with
-@), and then export functions that can operate on that.

Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
Reviewed-by: Tom Rini <trini@konsulko.com>
2025-09-26 11:55:13 -06:00
Rasmus Villemoes
0933358163 _exports.h: drop creating dummy i2c entries and fixup config dependency
There's really no good reason to create stub entries that would call a
function that doesn't even return anything sensible.

The existence of these two i2c_* functions depends on
CONFIG_IS_ENABLED(SYS_I2C_LEGACY), which does depend on !DM_I2C, but
is not equivalent to it. They are probably rather hard to use unless
CMD_I2C and something in U-Boot has called "i2c dev foo" to set the
current i2c bus before calling the standalone app, so keep that
dependency.

Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
Reviewed-by: Tom Rini <trini@konsulko.com>
2025-09-26 11:55:13 -06:00
Rasmus Villemoes
e54bf98c3a malloc.h: be a bit more consistent with macro definitions
Currrently, malloc and free are function-like macros, while calloc,
realloc and memalign are object-like macros.

Usually, this doesn't matter, but it does when the identifiers appear
without a following open parenthesis, such as when their address is
taken for building the export table. Adding calloc or realloc to that
table breaks the build on sandbox due to this inconsistency.

Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
Reviewed-by: Tom Rini <trini@konsulko.com>
2025-09-26 11:55:13 -06:00
Tom Rini
edce3c2905 Merge tag 'u-boot-imx-next-20250926' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx into next
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/27737

- Add support for i.MX94 EVK.
- Set CONFIG_ETHPRIME to eth0 on phycore-imx93.
- Expand the nxp_fspi support to i.MX8QXP/8DXL/8ULP.
2025-09-26 11:36:52 -06:00
Ye Li
1566f803bf imx9: scmi: Add PCIE ECAM and outbound space to MMU
Add PCIE1 and PCIE2 ECAM space and outbound space to MMU pagetable,
so A55 can access them.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2025-09-26 09:52:54 -03:00
Ye Li
320b191ec8 spi: nxp_fspi: Support i.MX8ULP flexspi
Add i.MX8ULP flexspi compatible string and driver data.
The flexspi on i.MX8ULP only has 16 LUT sequences and uses 1KB RX FIFO.

Signed-off-by: Ye Li <ye.li@nxp.com>
2025-09-26 09:52:23 -03:00
Ye Li
8e8fdb6681 spi: nxp_fspi: Support i.MX8DXL flexspi
According to i.MX8DXL A1 errata ERR050601, concurrent read accesses
from the A35 cores to the peripherals within the LSIO subsystem
(region 0_5DXX_XXXX) and address spaces in the regions
[0_0000_0000 – 0_1BFF_FFFF] and [4_0000_0000 – 4_3FFF_FFFF] can collide
and cause data corruption in the returned data, with no failure report.
Even a single A35 core accessing both these regions can trigger the issue
because an A35 core can have more than one parallel read operation in
progress.

The flexspi0 AHB memory is in LSIO region mentioned in above errata.
So we can't use AHB read, only can read data from FIFO.
Add the compatible string for 8DXL and use a flag for the IPS read.

Signed-off-by: Ye Li <ye.li@nxp.com>
2025-09-26 09:52:23 -03:00
Ye Li
2866c33218 spi: nxp_fspi: Support i.MX8QXP flexspi
Add the compatible string and driver data for i.MX8QXP.

Signed-off-by: Ye Li <ye.li@nxp.com>
2025-09-26 09:52:23 -03:00
Ye Li
c320edc9c0 spi: nxp_fspi: Use second last LUT entry for AHB read
Use a dedicated LUT (second last) for AHB read command, so we can
directly read from the AHB memory-mapped address and booting M core
for XIP on Flexspi NOR.

Signed-off-by: Ye Li <ye.li@nxp.com>
2025-09-26 09:52:23 -03:00
Primoz Fiser
89bae6ea2d board: phytec: phycore-imx93: Set CONFIG_ETHPRIME to eth0
Set ethprime to eth0 since FEC interface is considered the primary IF on
phyCORE-i.MX93 SoM based boards. This comes from the fact that the same
bootloader is reused for both carrier boards, that is phyBOARD-Segin and
phyBOARD-Nash which both use different Ethernet PHYs on the EQOS (eth1)
interface and thus eth1 cannot be used as a prime.

Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
2025-09-26 09:51:44 -03:00
Ye Li
3d4e14f4c9 imx94_evk: Add i.MX943 EVK board support
Add board-level code and defconfig for the i.MX943 EVK board, supporting
multiple SOM variants: 19x19 LPDDR5, 19x19 LPDDR4 and 15x15 LPDDR4.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
2025-09-26 09:51:21 -03:00
Ye Li
88c5ed4aa0 arm: dts: Add i.MX943 EVK board dtsi files
Introduce the base dtsi files for the i.MX943 EVK board. These files
define the essential components such as messaging units, uSDHC, GPIOs
and lpuart for board bring-up.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
2025-09-26 09:51:21 -03:00
Ye Li
8824aa432c imx: ele_ahab: Add i.MX94 support to display_life_cycle()
Extend display_life_cycle() to support i.MX94.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
2025-09-26 09:51:21 -03:00
Ye Li
226a606c10 imx: ele_ahab: Implement display_life_cycle() for i.MX95
The register reflects lifecycle and some lifecycle-derived state of
i.MX95 has new offset address and layout, so display_life_cycle() is
added specifically for it.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2025-09-26 09:51:21 -03:00
Ye Li
54e4b1c36b imx9: Change container header temp buffer address
Due to i.MX95 has reserved first 256MB DDR, change to use the DDR
start address in u-boot as the container header buffer.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2025-09-26 09:51:21 -03:00
Alice Guo
3661d4dc6d pinctrl: nxp: Add i.MX94 daisy register offset
Define the daisy register offset for i.MX94 at 0x608 within the iomuxc
register space. This enables correct pad selection for daisy chain
configuration on i.MX94 platforms.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
2025-09-26 09:51:21 -03:00
Ye Li
6fc3934db5 imx: container: Add i.MX94 support to get_imageset_end()
Extend get_imageset_end() to handle i.MX94 family.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
2025-09-26 09:51:21 -03:00
Ye Li
f9c4fd3871 imx9: scmi: Update the files under arch/arm/mach-imx/imx9/scmi/ to support i.MX94
- Add base addresses for WDG3, WDG4, GPIO6, and GPIO7 for i.MX94.
- Introduce common.h with macros of clock IDs, power domains, and CPU
  types for platform-specific replacement (e.g., i.MX94, i.MX95).
- Extend imx_get_mac_from_fuse() to support i.MX94.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
2025-09-26 09:51:21 -03:00
Ye Li
1588c243b9 imx9: scmi: Add i.MX94 support to get_reset_reason()
Update get_reset_reason() to support i.MX94 to send message to the
System Manager to retrieve the LM/system last booted/shutdown reasons.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2025-09-26 09:51:21 -03:00
Peng Fan
998c6cc450 imx95: Add get_reset_reason() to retrieve the LM/system last booted/shutdown reasons
System Manager provides the last booted and shutdown reasons of the
logical machines (LM) and system using the SCMI misc protocol (Protocol
ID: 0x84, Message ID: 0xA). This path adds get_reset_reason() to query
and print these reasons in SPL and U-Boot.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
2025-09-26 09:51:21 -03:00
Alice Guo
a2d62d3b1d cpu: imx94: Add support for i.MX94 in get_imx_type_str()
Add a case for i.MX94 to return the correct string identifier in the
get_imx_type_str() function. This ensures proper CPU type reporting for
i.MX94 platforms.

Signed-off-by: Alice Guo <alice.guo@nxp.com>
2025-09-26 09:51:21 -03:00
Ye Li
a87b928326 imx9: Add i.MX94 CPU type and SoC-level Kconfig
Introduce support for the new i.MX94 processor, including its CPU type
and SoC-level Kconfig entry.

The i.MX94 is a new member of the i.MX9 family. It uses a System Manager
to handle system-level functions such as power, clock, sensor and pin
control. The System Manager runs on a Cortex-M processor, while the
Cortex-A processor communicates with it via the ARM SCMI protocol and a
messaging unit.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
2025-09-26 09:51:21 -03:00
Tom Rini
97f2f941e7 Merge branch 'next' of git://source.denx.de/u-boot-usb into next
- Tighten some USB dependencies and remove some unused code.
2025-09-25 18:54:45 -06:00
Tom Rini
3285584429 usb: host: Tighten USB musb-new host glue driver dependencies
A few of the USB musb-new host glue drivers cannot build without access
to some platform specific header files. Express those requirements in
Kconfig as well.

Reviewed-by: Marek Vasut <marek.vasut@mailbox.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-09-26 00:06:00 +02:00
Tom Rini
be8c07b606 usb: host: Tighten USB host driver dependencies
A few of the USB host drivers cannot build without access to some
platform specific header files. Express those requirements in Kconfig as
well.

Reviewed-by: Marek Vasut <marek.vasut@mailbox.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-09-26 00:06:00 +02:00
Tom Rini
56edb1cc76 usb: gadget: max3420_udc: Remove unused driver
This driver was never enabled by any platforms after being added to the
tree over 5 years ago. Remove it.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Marek Vasut <marek.vasut@mailbox.org>
2025-09-26 00:06:00 +02:00
Tom Rini
219751e8c7 usb: gadget: bcm_udc_otg: Remove unused driver
This driver is unused since the removal of the bcm28155_ap board in
commit 0f6807e77b ("arm: Remove bcm28155_ap board"). Remove it.

Fixes: 0f6807e77b ("arm: Remove bcm28155_ap board")
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Marek Vasut <marek.vasut@mailbox.org>
2025-09-26 00:06:00 +02:00
Tom Rini
70553ec85f usb: gadget: Tighten requirements on USB_GADGET_ATMEL_USBA
This driver requires some mach-at91 specific header files in order to build.
Express that requirement in Kconfig as well.

Reviewed-by: Marek Vasut <marek.vasut@mailbox.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-09-26 00:06:00 +02:00
Tom Rini
f83a9e5df4 usb: dwc3: Tighten driver glue dependencies
A few of the platform specific DWC3 host glue drivers cannot build
without access to some platform specific header files. Express those
requirements in Kconfig as well.

Reviewed-by: Marek Vasut <marek.vasut@mailbox.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-09-26 00:06:00 +02:00
Jan Kiszka
44c4919e9d test: Fix optee unit test
This was apparently not built for several years: Since a2535243e0,
optee_copy_fdt_nodes implicitly works against the U-Boot dt. We
therefore have to tweak its reference before using the function and
restore things afterwards.

If it had been built, actually trying it out would have failed next: We
need CONFIG_OPTEE_LIB to actually build the function that is primarily
being tested here. And we need to re-initialize target fdt, now that the
tests may run in random order.

Fixes: a2535243e0 ("lib: optee: migration optee_copy_fdt_nodes for OF_LIVE support")
Fixes: ba2feaf414 ("test: Split optee tests into three functions")
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
2025-09-24 11:04:11 -06:00
Jan Kiszka
7cae89bac4 lib: optee: Add line ending to debug() outputs
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
2025-09-24 11:04:04 -06:00
Osama Abdelkader
5d0b813d6e imls: remove return parentheses
return is not a function, parentheses are not required

Signed-off-by: Osama Abdelkader <osama.abdelkader@gmail.com>
2025-09-24 11:03:43 -06:00
Osama Abdelkader
8558aaa3cf sandbox: use env_get() for time offset instead of getenv()
The sandbox time offset is intended to be controlled via the U-Boot
environment, not the host process environment. Update os_get_time_offset()
to use env_get() instead of the libc getenv().

Leave other getenv() uses (e.g. U_BOOT_PERSISTENT_DATA_DIR,
UBOOT_SB_FUZZ_TEST) unchanged, since those refer to host environment
variables needed by sandbox tests.

Signed-off-by: Osama Abdelkader <osama.abdelkader@gmail.com>
2025-09-24 11:03:24 -06:00
Guillaume Ranquet
5289b6e554 android: boot: fix wrong end of header in v3/v4 parsing
The android boot header is page aligned but the current code made the
assumption that the header was always smaller than the current header
format.

When the page_size is defined as 2048, as this is the case with the
cuttlefish target, the current code sets the end of the header in the
middle of it as the v3 and v4 headers are respectively 2112 and 2128
bytes long.

Fix that by aligning to page_size

Fixes: 1115027d2f ("android: boot: update android_image_get_data to support v3, v4")
Signed-off-by: Guillaume Ranquet <ranquet.guillaume@gmail.com>
2025-09-24 11:03:16 -06:00
Tom Rini
1e8592e0ec Merge tag 'mmc-power-next-2025-09-24' of https://source.denx.de/u-boot/custodians/u-boot-mmc into next
CI: https://source.denx.de/u-boot/custodians/u-boot-mmc/-/pipelines/27712

- Correct error value check in regulator_list_autoset
- Minor style fixes in mmc
2025-09-24 09:28:58 -06:00
Bhimeswararao Matsa
3cabc6bf7e mmc: core: style fixes in mmc.c
Fix a couple of style issues reported by checkpatch.pl:

- Replace `#ifdef CONFIG_MMC_TRACE` with `#if IS_ENABLED(CONFIG_MMC_TRACE)`
  to follow the preferred kernel style for config-dependent branches.
- Drop explicit zero initialization of a static variable.

No functional change intended.

Signed-off-by: Bhimeswararao Matsa <bhimeswararao.matsa@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-09-25 00:06:27 +08:00
Andrew Goodbody
6c98e6014b power: regulator: Fix incorrect use of binary and
In regulator_list_autoset there is a test for ret being non-zero and
error being zero but it uses the binary '&' instead of the logical '&&'
which could well lead to unexpected results. Correct this to use the
logical '&&' instead.

This issue found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-09-25 00:04:02 +08:00
Tom Rini
e482fdbbca Revert "Merge patch series "mkimage: Detect FIT image load address overlaps and fix related test/DTS issues""
This reverts commit 4d84fa1261, reversing
changes made to b82a1fa7dd.

I had missed some feedback on this series from earlier, and we have
since had reports of regressions due to this as well. For now, revert
this.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-09-24 07:50:44 -06:00
Tom Rini
4d84fa1261 Merge patch series "mkimage: Detect FIT image load address overlaps and fix related test/DTS issues"
Aristo Chen <jj251510319013@gmail.com> says:

This patch series enhances FIT image robustness by adding **memory
region overlap detection** to `mkimage` and fixing existing overlaps
in DTS files and `binman` tests.

The primary goal is to prevent runtime memory corruption from
conflicting load addresses in FIT images.

Key Changes:

1.  `mkimage` Overlap Detection: A new validation in
    `tools/fit_image.c` checks for overlapping load addresses
    within FIT configurations. `mkimage` now errors out with
    detailed info on conflicts, preventing bad FIT image creation.

2.  New Test Case: A Python test verifies the new detection.
    It intentionally creates an overlap (kernel and FDT)
    to confirm correct error handling.

3.  Fixes for Existing Overlaps:
    * Board DTS (k3-am6xx): Adjusted load addresses for TI
      firmware stubs to prevent conflicts. This resolves
      previously undetected overlaps.
    * `binman` Tests: Fixed several tests. U-Boot load
      addresses were shifted to avoid ATF conflicts. A new
      linker script for TEE ELF sections ensures distinct
      memory layouts.

4.  Documentation: Added guidance for developers on how to
    determine ELF load addresses using readelf, linker scripts,
    and objdump when working with binman FIT images.

Impact:

This series improves FIT image reliability by catching overlaps
at build time, helping developers resolve issues before runtime
failures.

Link: https://lore.kernel.org/r/20250914110021.4103-1-aristo.chen@canonical.com
2025-09-23 13:41:16 -06:00
Aristo Chen
4907a920e8 doc: binman: Add guidance for determining ELF load addresses
Add documentation to help users understand how to determine where ELF
files will be loaded when using binman's 'fit,load' property. This
addresses the common confusion about how load addresses are determined
from ELF files.

The documentation explains three methods:
1. Using readelf to examine program headers
2. Checking the linker script (.lds file)
3. Using objdump to see section addresses

Also includes a specific example from binman tests showing how
elf_sections.lds sets ATF load address to 0x00000010 and
elf_sections_tee.lds sets TEE load address to 0x00100010 to avoid
memory overlap conflicts.

This helps users debug memory layout conflicts more efficiently when
working with FIT images containing multiple ELF components.

Signed-off-by: Aristo Chen <aristo.chen@canonical.com>
2025-09-23 13:35:22 -06:00
Aristo Chen
8f3d3510e3 test: Add test case for FIT image load address overlap detection
Add a new test case to verify that mkimage properly detects and reports
memory region overlaps in FIT image configurations.

The test creates a FIT image with kernel and FDT components that have
the same load address (0x40000), which should trigger the overlap
detection logic and cause mkimage to fail with an appropriate error
message.

Test verifies:
- mkimage returns non-zero exit code when overlap is detected
- Error message contains "Error: Overlap detected:"
- Error message identifies the specific overlapping components
  (kernel@1 and fdt@1)

This test ensures the overlap detection feature works correctly and
prevents deployment of FIT images with conflicting memory layouts
that could cause runtime failures.

Signed-off-by: Aristo Chen <aristo.chen@canonical.com>
2025-09-23 13:35:22 -06:00
Aristo Chen
588094f2c8 tools: mkimage: detect overlapping load regions in FIT configurations
This patch adds a validation step in mkimage to detect memory region
overlaps between images specified in the same configuration of a
FIT image. If any overlaps are found, the tool prints an error and
aborts the build.

This helps prevent runtime memory corruption caused by conflicting
load addresses between images.

Signed-off-by: Aristo Chen <aristo.chen@canonical.com>
2025-09-23 13:35:22 -06:00
Aristo Chen
cbc4da1dce arm: dts: k3-am6xx: Fix FIT image memory overlap in binman configurations
Fix memory overlaps in FIT image configurations for TI AM62x and AM64x
PHYCore and SK boards.

The overlaps occurred in two categories:

1. TI firmware stub images (tifsstub-hs, tifsstub-fs, tifsstub-gp):
   These mutually exclusive firmware variants were incorrectly assigned
   the same load address within FIT configurations, causing overlap
   detection to fail. Adjust addresses with 64KB spacing:
   - tifsstub-hs: Keep original address
   - tifsstub-fs: Move to +64KB offset
   - tifsstub-gp: Move to +128KB offset

2. Device tree overlay images (som-no-rtc, som-no-spi, som-no-eth):
   These overlay files had insufficient spacing between load addresses,
   causing actual memory overlaps. Increase spacing to 8KB boundaries
   to accommodate overlay sizes safely.

An upcoming commit will validate if the memory region is overlapped

Signed-off-by: Aristo Chen <aristo.chen@canonical.com>
2025-09-23 13:35:22 -06:00
Aristo Chen
a06733fc83 binman: Fix FIT image overlap issues for testFitSplitElf
Fix one binman test that has memory region overlap issue, the test case
needed to be updated to use non-overlapping memory layouts.

* Tests fixed:
  - testFitSplitElf

* Changes made:
  1. ELF section layouts: added elf_sections_tee.lds with different
     address for TEE to avoid overlap with ATF address defined in
     elf_sections.lds
  2. Makefile to properly build elf_sections_tee binary
  3. Updat ftest.py to use separate ELF files for TEE vs ATF components
     in split-elf operations.

An upcoming commit will validate if the memory region is overlapped

Signed-off-by: Aristo Chen <aristo.chen@canonical.com>
2025-09-23 13:35:22 -06:00
Aristo Chen
dade54edaf binman: Fix FIT image overlap issues
Fix three binman tests that has memory region overlap issue, the test
cases needed to be updated to use non-overlapping memory layouts.

* Tests fixed:
  - testFitFirmwareLoadables
  - testFitSignSimple
  - testFitSignNoSignatureNodes

* Changes made:
  Updated DTB test files to change U-Boot load addresses from 0x0 to
  0x2000 to avoid overlapping with ATF in the 0x10-0xfc range:
  - 276_fit_firmware_loadables.dts
  - 340_fit_signature.dts
  - 342_fit_signature.dts

An upcoming commit will validate if the memory region is overlapped

Signed-off-by: Aristo Chen <aristo.chen@canonical.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
2025-09-23 13:35:22 -06:00
Aristo Chen
88392a59bf binman: Fix typo for the test case name
Fix typo from `Singature` to `Signature`

Signed-off-by: Aristo Chen <aristo.chen@canonical.com>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
2025-09-23 13:35:22 -06:00
Tom Rini
b82a1fa7dd Merge tag 'v2025.10-rc5' into next
Prepare v2025.10-rc5
2025-09-23 08:24:59 -06:00
Tom Rini
d81c111858 Merge tag 'u-boot-imx-next-20250922' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx into next
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/27684

- Add i.MX8 ahab-commit command.
- Add support for flashing board with UUU on imx93_frdm.
- Fix the acces of PFUZE100 regulator desc.
- Add more i.MX6 PWM clock definitions.
- Enable OP-TEE on phytec-imx8m and update documentation.
- Enable PCI host controller on iMX95 19x19 EVK.

[trini: Fixup spacing issues]
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-09-22 09:57:39 -06:00
Yannic Moog
db6487861a doc: phytec: imx8m: Style and firmware update
Use single make command for compiling blobs and U-Boot.
Update the imx firmware version.

Signed-off-by: Yannic Moog <y.moog@phytec.de>
2025-09-22 09:57:00 -06:00
Yannic Moog
cb1292450d doc: phytec: update imx8m docs for optee builds
OP-TEE configs are enabled by default, change the doc to no longer
declare OP-TEE as optional. Also remove CFG_TEE_BENCHMARK as it is no
longer present in optee_os.
Further, phycore-imx8mm and imx8mm-phygate-tauri-l use different build
instructions, so dissolve the common file for building OP-TEE.

Reviewed-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Yannic Moog <y.moog@phytec.de>
2025-09-22 09:57:00 -06:00
Yannic Moog
f7857695c9 phytec-imx8m boards: enable OP-TEE for KASLR
Enable OP-TEE config and RNG by default.
Set OP-TEE load address to end of 1GiB RAM for phycore-imx8mp and
phycore-imx8mm as the boards support a 1GiB RAM variant (although not
yet upstreamed for phycore-imx8mm).
The imx8mm-phygate-tauri-l board only supports 2GiB, so the default at
the end of 2GiB is sufficient.

Reviewed-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Yannic Moog <y.moog@phytec.de>
2025-09-22 09:57:00 -06:00
Ricardo Simoes
edc666f1cf clk: imx6q: Add definition for missing PWM clocks
Following the work done in commit 7f39ad5a ("clk: imx6q: Add definition
for IMX6QDL_CLK_PWM1"), this commit adds definitions for PWM2, PWM3, and
PWM4 clocks. Allowing one to use these PWM modules together with DM_CLK.

Note that the solution was verified only against PWM3.

Signed-off-by: Ricardo Simoes <ricardo.simoes@pt.bosch.com>
Signed-off-by: Mark Jonas <mark.jonas@de.bosch.com>
2025-09-22 09:56:39 -06:00
Peng Fan
2727de799a power: regulator: pfuze100: Fix accessing the regulator desc
se_desc loop check is wrong, it relies on the desc always has
the expected name to end of the loop. It works because the device tree
has the expected name as of now, but this may not be always true.

Drop se_desc by moving the check into probe and fix the loop check.

Reported-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Cc: Tom Rini <trini@konsulko.com>
Cc: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-09-20 17:47:08 -03:00
Mathieu Dubois-Briand
8918b60e33 imx93_frdm: Add support for flashing board with UUU
Allow to flash a board using NXP UUU utility:
- Enable fastboot support on USB.
- Add fastboot partition aliases with names used by UUU. Also add extra
  environment variables used by UUU.
- Set 'dofastboot' environment variable based on boot device
  configuration, allowing to automatically enter fastboot when booting
  from USB.

Signed-off-by: Mathieu Dubois-Briand <mathieu.dubois-briand@bootlin.com>
2025-09-20 17:46:40 -03:00
Ye Li
9f90e39d1c imx95_evk: Enable PCI host controller on iMX95 19x19 EVK
Enable DW IMX PCI driver and iMX95 BLKCTRL clock driver in defconfig,
so PCI controller can work.

Signed-off-by: Ye Li <ye.li@nxp.com>
2025-09-20 17:46:15 -03:00
Ye Li
5c4e28e52f arm: dts: imx95-evk: set alias for enetc PCI buses
Use fixed seq 0 and 1 for enetc PCI buses, then the seq for PCI controllers
could start after them.

Signed-off-by: Ye Li <ye.li@nxp.com>
2025-09-20 17:46:15 -03:00
Ye Li
749f6762b4 arm: dts: imx95: Assign HSIOPLL_VCO as HSIOPLL parent clock
We have to explicitly assign HSIOPLL_VCO as HSIOPLL parent. So when
enabling HSIOPLL, its parent HSIOPLL_VCO will be enabled firstly.

Signed-off-by: Ye Li <ye.li@nxp.com>
2025-09-20 17:46:15 -03:00
Ye Li
87119e0f79 clk: clk-uclass: Fix clk_set_default_rates issue
clk_set_rate returns the actual clock rate, When assigned clock rate is
higher than 0x7FFFFFFF, the return value will be recognized as error.
Change to IS_ERR_VALUE to check the return value.

Signed-off-by: Ye Li <ye.li@nxp.com>
2025-09-20 17:46:15 -03:00
Ye Li
f98d812e53 power: regulator: Add vin-supply for GPIO and Fixed regulators
Enable the vin-supply when probing the regulator device.

Signed-off-by: Ye Li <ye.li@nxp.com>
2025-09-20 17:46:15 -03:00
Ye Li
d680ac6cfd clk: imx: Add imx95 blkctrl clock driver
Add iMX95 blkctrl clock driver which implements clocks for HSIOMIX
blkctrl and LVDS blkctrl.
Since multiple blkctrl device for different blkctrl may be enabled,
and each has dedicated clock id from 0. We must enable CLK_AUTO_ID
to avoid conflict on clock id.

Signed-off-by: Ye Li <ye.li@nxp.com>
2025-09-20 17:46:15 -03:00
Ye Li
f8b1883508 pci: pcie_dw_imx: Add iMX9 support to the driver
Adding iMX95/iMX94 support to the dw driver. Follow kernel driver
stype to use flags to distinguish the characteristic of different
platforms.

Signed-off-by: Ye Li <ye.li@nxp.com>
2025-09-20 17:46:15 -03:00
Ye Li
00ef795981 pci: dw: Fix wrong register used for PCI_COMMAND
Wirting to command register should use PCI_COMMAND not PCI_PRIMARY_BUS

Signed-off-by: Ye Li <ye.li@nxp.com>
2025-09-20 17:46:15 -03:00
John Ripple
b717a4090f imx8: Add ahab_commit command
The ahab_commit command allows the user to commit into the SECO fuses
that control the SRK key revocation information. This is used to Revoke
compromised SRK keys.

To use ahab_commit, the boot container must be built with an SRK
revocation bit mask that is not 0x0. For the SPSDK provided by NXP, this
means setting the 'srk_revoke_mask' option in the config file used to
sign the boot container. The 'ahab_commit 0x10' can then be used to commit
the SRK revocation information into the SECO fuses.

Signed-off-by: John Ripple <john.ripple@keysight.com>
2025-09-20 17:45:39 -03:00
Tom Rini
464800d91b Merge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-riscv into next
CI: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/27673

- Switch to upstream devicetree for TH1520 platform
- Remove fdt_high env variable
- Support SMP on RISC-V cores with Zalrsc only
- Make MPFS Generic
- riscv: dts: starfive: prune redundant jh7110-common
2025-09-20 10:02:00 -06:00
Tom Rini
31eee7d42b Merge patch series "configs: phycore_am62ax_r5_defconfig: eMMC boot from raw offsets"
This series from Wadim Egorov <w.egorov@phytec.de> changes the
phycore_am62ax platform to use raw offsets for eMMC boot.

Link: https://lore.kernel.org/r/20250909103654.3341398-1-w.egorov@phytec.de
2025-09-19 11:57:00 -06:00
Daniel Schultz
be5715f9aa configs: phycore_am62ax_a53_defconfig: eMMC boot from raw offsets
Enable CONFIG_SPL_SYS_MMCSD_RAW_MODE and set the offset address to
boot from raw addresses instead of a FAT partition.

Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Acked-by: Anshul Dalal <anshuld@ti.com>
2025-09-19 11:56:52 -06:00
Daniel Schultz
6f79e80079 configs: phycore_am62ax_r5_defconfig: eMMC boot from raw offsets
Enable CONFIG_SPL_SYS_MMCSD_RAW_MODE and set the offset address to
boot from raw addresses instead of a FAT partition.

Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Acked-by: Anshul Dalal <anshuld@ti.com>
2025-09-19 11:56:52 -06:00
Tom Rini
8c4430fc52 Merge patch series "qemu-sbsa: Fix GIC enablement"
Kunihiko Hayashi <hayashi.kunihiko@socionext.com> says:

In the qemu-sbsa configuration, the GICv3 definition is disabled due to
a typo. After fixing the typo, GICv3 is enabled, however, the GIC register
base address definitions are missing, resulting in a build failure.

This series enables GICv3 and resolves this build error.
Confirming that U-Boot successfully starts up in QEMU SBSA environment
after the fix.

Link: https://lore.kernel.org/r/20250910092327.279749-1-hayashi.kunihiko@socionext.com
2025-09-19 11:56:24 -06:00
Kunihiko Hayashi
edaaedb5dd board: qemu-sbsa: Fix mistyped GICV3 definition
The config "GIC_V3" seems to be typo, and currently "GICV3" remains
disabled. Since "GIC_V3_ITS" is enabled in qemu-sbsa, "GICV3" should
also be enabled.

Fixes: 6d722894fd ("board: emulation: Add QEMU sbsa support")
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
2025-09-19 11:55:29 -06:00
Kunihiko Hayashi
e246e2b658 configs: qemu-sbsa: Define GIC register base address
If GICV3 is enabled, GICD_BASE and GICR_BASE are needed at
arch/arm/cpu/armv8/start.S.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
2025-09-19 11:55:29 -06:00
Simon Glass
ecced05f67 lib: Tidy up comments for vsprintf functions
Some of the functions in this file do not follow the normal style. Fix
this so that things are more consistent.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2025-09-19 11:54:27 -06:00
Tom Rini
a5de15f44d Merge tag 'u-boot-stm32-20250919' of https://source.denx.de/u-boot/custodians/u-boot-stm into next
CI:
  - https://source.denx.de/u-boot/custodians/u-boot-stm/-/pipelines/27668

STM32MP2:
  - Add SPI flashes support
  - Add RIFSC system bus driver fixes
2025-09-19 08:08:11 -06:00
E Shattow
10fdc2735d configs: starfive: Use visionfive2 DEVICE_TREE_INCLUDES dtsi named similar to defconfig
Add SYS_CPU automatic inclusion jh7110-u-boot.dtsi to item of config list
DEVICE_TREE_INCLUDES as starfive-visionfive2-u-boot.dtsi and rename file.

Signed-off-by: E Shattow <e@freeshell.de>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-09-19 19:23:32 +08:00
E Shattow
b8732d30a4 riscv: dts: starfive: visionfive2 depend on SYS_CPU automatic dtsi inclusion
Drop visionfive2 per-board -u-boot.dtsi stubs and instead rely on
automatic inclusion of jh7110-u-boot.dtsi

Signed-off-by: E Shattow <e@freeshell.de>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-09-19 19:23:32 +08:00
E Shattow
3e6d5b205d riscv: dts: starfive: sync visionfive2 overrides with upstream Linux for-next
Sync automatic dtsi inclusion overrides for JH7110 CPU with upstream
"riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot
loader" from upstream Linux conor/riscv-dt-for-next commit 8181cc2f3f21

Signed-off-by: E Shattow <e@freeshell.de>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-09-19 19:23:32 +08:00
E Shattow
27f617019d riscv: dts: starfive: prune redundant jh7110-common overrides
Prune jh7110-common-u-boot.dtsi (clocks, qspi flash, eeprom, and
bootph-pre-ram hints now upstream since devicetree-rebasing v6.16).

In preparation for removal of per-dts jh7110-*-u-boot.dtsi replace include
by next dependency jh7110-u-boot.dtsi in automatic dtsi inclusion order.

Signed-off-by: E Shattow <e@freeshell.de>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-09-19 19:23:32 +08:00
Greentime Hu
36d9587fa8 arch/riscv: Remove unused macro in encoding.h
This patch remove the unused macro DRAM_BASE.

Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-09-19 19:23:17 +08:00
Vivian Wang
62f1afbe7a riscv: qemu: Remove fdt_high default
Setting fdt_high to all ones is discouraged and does not appear to be
useful for RISC-V QEMU. Moreover, it causes a boot failure when the FDT
generated internally by QEMU is used while booting. Remove it to allow
U-Boot to pick a suitable address and relocate the FDT.

Closes: https://lore.kernel.org/u-boot/8397369a-9b0b-4798-9c30-3a81165657d6@iscas.ac.cn
Signed-off-by: Vivian Wang <wangruikang@iscas.ac.cn>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-09-19 19:23:04 +08:00
Eoin Dickson
133c6acdac gpio: mpfs_gpio: fix compilation warnings
mchp_gpio_get_value() should return int instead of bool, and some casts
are needed.

Signed-off-by: Eoin Dickson <eoin.dickson@microchip.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-09-19 19:22:52 +08:00
Jamie Gibbons
41e5a6520b board: microchip: mpfs_generic: include processing of dtbos
Include the use of the process dtbo functionality added in the MPFS
system controller driver.

Signed-off-by: Jamie Gibbons <jamie.gibbons@microchip.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-09-19 19:22:42 +08:00
Jamie Gibbons
7fa1ee7fb9 misc: mpfs_syscontroller: add functions to read device tree overlays
Include functions to use the system controller to read the device tree
overlays which supports auto update functionality.

Signed-off-by: Jamie Gibbons <jamie.gibbons@microchip.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-09-19 19:22:42 +08:00
Jamie Gibbons
39eda3f037 doc: microchip: add mpfs_video.rst
Add documentation to support the addition of the MPFS Video Kit.

Signed-off-by: Jamie Gibbons <jamie.gibbons@microchip.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-09-19 19:22:42 +08:00
Jamie Gibbons
bd44736100 doc: microchip: introduce common sections
With the upcoming additions of new MPFS boards, separate common
documentation to allow this to be reused appropriately and avoid
duplication.

Signed-off-by: Jamie Gibbons <jamie.gibbons@microchip.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-09-19 19:22:42 +08:00
Jamie Gibbons
9b3a0ab138 configs/microchip_mpfs_generic_defconfig: add board
Add board support for MPFS video kit.

Signed-off-by: Jamie Gibbons <jamie.gibbons@microchip.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-09-19 19:22:42 +08:00
Jamie Gibbons
d141a41feb board: microchip: icicle: rename all icicle files to generic
Make all Icicle Kit files generic. This supports the addition of
upcoming support for other MPFS boards.

Signed-off-by: Jamie Gibbons <jamie.gibbons@microchip.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-09-19 19:22:42 +08:00
Yao Zi
a681cfecb4 riscv: Add a Zalrsc-only alternative for synchronization in start.S
Add an alternative implementation that use Zalrsc extension only for
HART lottery and SMP locking to support SMP on cores without "Zaamo"
extension available. The Zaamo implementation is still prioritized if
both of them are available, since it takes fewer instructions.

Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-09-19 19:22:29 +08:00
Yao Zi
06b22f38af configs: ibex-ast2700: Explicitly disable Zaamo and Zalrsc extension
This board supports neither Zaamo nor Zalrsc extension, thus we want to
build it without "a" specified in the ISA string passed to compiler in
case of misused A-extension instructions. With RISCV_ISA_ZAAMO and
RISCV_ISA_ZALRSC Kconfig options introduced, we must explicitly disable
both of them to achieve this.

Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-09-19 19:22:29 +08:00
Yao Zi
fde7702c9b riscv: Add Kconfig options to distinguish Zaamo and Zalrsc
Ratified on Apr. 2024, the original RISC-V "A" extension is now split
into two separate extensions, "Zaamo" for atomic operations and "Zalrsc"
for load-reserved/store-conditional instructions.

For now, we've already seen real-world designs implement the Zalrsc
extension only[2]. As U-Boot mainly runs with only one HART, we could
easily support these designs by not using AMO instructions in the
hard-written assembly if necessary, for which this patch introduces two
new Kconfig options to indicate the availability of "Zaamo" and "Zalrsc".

Note that even with this patch, "A" extension is specified in the ISA
string passed to the compiler as long as one of "Zaamo" or "Zalrsc" is
available, since they're only recognized with a quite recent version of
GCC/Clang. The compiler usually doesn't automatically generate atomic
instructions unless the source explicitly instructs it to do so, thus
this should be safe.

Link: d94c64c63e # [1]
Link: https://lore.kernel.org/u-boot/20250729162035.209849-9-uros.stajic@htecgroup.com/ # [2]
Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-09-19 19:22:29 +08:00
Hal Feng
cb1a70a856 pcie: starfive: Remove the redundant print of probe success
The dev_err() is used incorrectly and we don't need the driver
to state probe success.

Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-09-19 19:12:19 +08:00
Heinrich Schuchardt
686b48af6d starfive: avoid NULL dereference in fdt_check_header()
If the u-boot.itb read from SD-card is invalid, fdt_check_header() may be
called with a NULL pointer.

This was observed on an StarFive VisionFive Lite when trying to revover the
board via UART.

Add a missing check in the starfive board code.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: E Shattow <e@freeshell.de>
2025-09-19 19:11:18 +08:00
Randolph Lin
409c73ef63 include: configs: andes: Remove fdt_high env variable
Remove the fdt_high environment variable, as a value of all ones
indicates using the FDT in place. This setting is incorrect for the
current board.

Signed-off-by: Randolph Lin <randolph@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-09-19 19:08:18 +08:00
Yao Zi
0d74bbfda3 dts: th1520: Switch to upstream devicetree
Imply OF_UPSTREAM in platform Kconfig option and adapt existing boards
to use the correct upstream devicetree paths.

Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-09-19 19:03:57 +08:00
Yao Zi
9d8a4728e1 pinctrl: th1520: Mark driver as DM_FLAG_PRE_RELOC
It's common that UARTs are bound and probed before U-Boot relocation, in
which case the UART's pincontroller and pinconfig must be probed first.
Let's apply DM_FLAG_PRE_RELOC to the driver, allow it to bind before
relocation.

Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-09-19 19:03:57 +08:00
Yao Zi
fbcf53680b clk: thead: th1520-ap: Mark drivers as DM_FLAG_PRE_RELOC
It's common that UARTs are bound and probed before U-Boot relocation,
in which case the clocks of UART and UART's pincontroller must be
registered first. Let's apply DM_FLAG_PRE_RELOC to the driver, allowing
it to bind before relocation.

Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-09-19 19:03:57 +08:00
Yao Zi
707e465cb1 configs: th1520_lpi4a: Enlarge SYS_MALLOC_F_LEN to 0x10000
For TH1520, we want clock and pinctrl drivers to bind before relocation
along with the UART which makes use of them, since upstream devicetree
specifies pinctrl properties for the UART.

This requires a large malloc pool before relocation, let's enlarge it.

Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-09-19 19:03:57 +08:00
Jim Liu
30fbbde2cd arm: nuvoton: remove unused parameter
remove CFG_SYS_BOOTM_LEN parameter

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2025-09-18 18:10:11 -06:00
Marek Vasut
e18a0dec6e boot: Increase kernel size limit to 128 MiB on ARM64/PPC/RV
The ARM64 kernel Image size with LOCKDEP enabled is now around 80 MiB, which
makes it unbootable due to "Image too large: increase CONFIG_SYS_BOOTM_LEN".
Increase the image size limit to 128 MiB to future proof the limit.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-09-18 15:44:43 -06:00
Tom Rini
44ac43c01b Merge patch series "Add support for MediaTek MT7987/MT7988 built-in 2.5Gb ethernet PHY (v4)"
Weijie Gao <weijie.gao@mediatek.com> says:

This patch adds PHY driver for MediaTek MT7987/MT7988 built-in 2.5Gb
ethernet PHY.

[trini: Change 'tristate' Kconfig to 'bool']

Link: https://lore.kernel.org/r/cover.1757315849.git.weijie.gao@mediatek.com
2025-09-18 15:43:56 -06:00
Weijie Gao
32b4c88ff2 MAINTAINERS: update ethernet-related file list for MediaTek ARM platform
Update ethernet-related files for MediaTek ARM platform

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2025-09-18 15:43:05 -06:00
Weijie Gao
b4b266fc13 net: phy: Add MediaTek built-in 2.5Gb ethernet PHY driver
The MediaTek MT7987/MT7988 SoCs features a built-in 2.5Gb PHY
connected to GMAC1. The PHY supports 10/100/1000/2500 Mbps
full-duplex only.

The PHY requires one or two firmware files. Firmware for MT7988 has
already been added to upstream: mediatek/mt7988/i2p5ge-phy-pmb.bin.
MT7987 has two firmware files which will be add to upstream later:
i2p5ge-phy-pmb.bin and i2p5ge-phy-DSPBitTb.bin.

Environment variable can be set for firmware data loading:
mt7987_i2p5ge_load_pmb_firmware for i2p5ge-phy-pmb.bin
mt7987_i2p5ge_load_dspbit_firmware for i2p5ge-phy-DSPBitTb.bin
mt7988_i2p5ge_load_pmb_firmware for i2p5ge-phy-pmb.bin

This driver allows dedicated weak functions to be overridden by
board to provide the firmware data:
mt7987_i2p5ge_get_fw() for MT7987
mt7988_i2p5ge_get_fw() for MT7988

To enable the PHY, add the following not to device tree:
&eth1 {
	status = "okay";
	phy-mode = "xgmii";
	phy-handle = <&phy15>;

	phy15: ethernet-phy@15 {
		compatible = "ethernet-phy-ieee802.3-c45";
		reg = <15>;
		phy-mode = "xgmii";
	};
};

Signed-off-by: Sky Huang <SkyLake.Huang@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2025-09-18 15:43:05 -06:00
Weijie Gao
465d76a038 net: mediatek: associate PHY device with dts node specified by phy-handle
Associate PHY device with its device node specified by phy-handle
property. This makes it possible for PHY drivers to read dedicated
information to configure the PHY device.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2025-09-18 15:43:05 -06:00
Weijie Gao
5b1d3d83d6 misc: fs_loader: allow using long script name in request_firmware_into_buf_via_script()
Use cmd_process() to remove the length limit of script name used for
run_command().

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2025-09-18 15:43:05 -06:00
Weijie Gao
6358568968 misc: fs_loader: allow returning actual firmware data size in request_firmware_into_buf_via_script()
It's important to return the actual firmware data size as some
firmware files may have no checksum and need the size as the only
way for firmware validation check.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2025-09-18 15:43:05 -06:00
Patrice Chotard
b8edd54d60 ARM: dts: Add flash0 partitions for stm32mp257f-ev1-u-boot
Add flash0 partitions for stm32mp257f-ev1-u-boot.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2025-09-18 17:20:39 +02:00
Patrice Chotard
df80866312 configs: stm32mp25: Enable configs flags related to SPI flashes.
Enable configs flags related to SPI flashes.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2025-09-18 17:20:39 +02:00
Patrice Chotard
01eb0a5838 spi: Add STM32MP2 Octo-SPI driver support
Add STM32 OSPI driver, it supports :
  - support sNOR / sNAND devices.
  - Two functional modes: indirect (read/write) and memory-mapped (read).
  - Single-, dual-, quad-, and octal-SPI communication.
  - Single data rate (SDR).

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2025-09-18 17:20:39 +02:00
Patrice Chotard
b7328e2f39 memory: Add STM32 Octo Memory Manager driver
Octo Memory Manager driver (OMM) manages:
  - the muxing between 2 OSPI busses and 2 output ports.
    There are 4 possible muxing configurations:
      - direct mode (no multiplexing): OSPI1 output is on port 1 and OSPI2
        output is on port 2
      - OSPI1 and OSPI2 are multiplexed over the same output port 1
      - swapped mode (no multiplexing), OSPI1 output is on port 2,
        OSPI2 output is on port 1
      - OSPI1 and OSPI2 are multiplexed over the same output port 2
  - the split of the memory area shared between the 2 OSPI instances.
  - chip select selection override.
  - the time between 2 transactions in multiplexed mode.
  - check firewall access.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2025-09-18 17:20:39 +02:00
Patrice Chotard
08ccc1f56c ioport: Add resource check helpers
Add resource_overlaps() and resource_contains() helpers.
Code copied from kernel source.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2025-09-18 17:20:39 +02:00
Gatien Chevallier
0b5ae33eb3 ARM: stm32mp: replace RIFSC check access APIs
Replace RIFSC check access APIs by grant/release access ones that handle
the RIF semaphores.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2025-09-18 17:20:34 +02:00
Gatien Chevallier
bb947665f5 ARM: stm32mp: fix RIFSC semaphores acquisition
Fix RIFSC semaphores acquisition by not returning an error when the
current CID already possess the semaphore. Also fix an incorrect mask
for the CID value in the SEMCR register.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2025-09-18 17:20:30 +02:00
Tom Rini
a209627ed7 Merge patch series "board: dhelectronics: Check pointer before access in dh_get_value_from_eeprom_buffer()"
This series from Marek Vasut <marek.vasut@mailbox.org> cleans up some of
the common code between dhelectronics platforms.

Link: https://lore.kernel.org/r/20250907010103.667681-1-marek.vasut@mailbox.org
2025-09-16 16:14:30 -06:00
Marek Vasut
fd39631643 board: dhelectronics: Use isascii() before isprint() in dh_read_eeprom_id_page()
The isprint() checks printability across all 256 characters, some of the
upper 128 characters are printable and produce artifacts on UART. Call
isascii() first to only consider the bottom 7bit ASCII characters as
printable, and then check their printability using isprint(). This fixes
a rare misprint in case the ID page content is uninitialized or corrupted.

Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
Reviewed-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
2025-09-16 16:14:18 -06:00
Marek Vasut
1c735620e1 board: dhelectronics: Check pointer before access in dh_get_value_from_eeprom_buffer()
The eip pointer in dh_get_value_from_eeprom_buffer() might be NULL.
The current NULL pointer check happens too late, after the eip was
accessed in variable assignment. Reorder the two, so the NULL pointer
check happens first, and any access second, otherwise the access may
trigger a hang or other undefined behavior.

Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
Reviewed-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
2025-09-16 16:14:18 -06:00
Marek Vasut
c6a4b44cdc phy: Reset init count on phy exit failure
In case the PHY exit callback reports failure, reset init_count to 0 anyway,
so the next attempt at PHY initialization might try to reinitialize the PHY
and restore it to normal operation.

Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
2025-09-16 16:14:03 -06:00
Marek Vasut
27fc6a67a4 thermal: sandbox: Staticize sandbox_thermal_get_temp()
Make sandbox_thermal_get_temp() static, since this is not called
outside of the driver. No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-09-16 16:13:05 -06:00
Marek Vasut
7be74f63f7 thermal: Sort the Makefile
Sort the Makefile alphabetically. No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-09-16 16:12:54 -06:00
Tom Rini
ab11aca3a1 Merge patch series "Modernize U-Boot code formatting with clang-format"
Javier Tia <javier.tia@linaro.org> says:

This patch series modernizes U-Boot's code formatting infrastructure by
with current Linux kernel practices and providing a more robust and
comprehensive formatting solution.

Link: https://lore.kernel.org/r/20250905205349.127333-1-javier.tia@linaro.org
2025-09-16 13:45:08 -06:00
Javier Tia
a9d997685a doc: Update U-Boot coding style guide with clang-format usage
The U-Boot coding style guide has been updated to include information
about using the `.clang-format` configuration file for automatic code
formatting. This ensures consistent formatting across the entire
codebase and aligns with Linux kernel coding standards. The goal with
introducing a predefined coding style is consistency rather than
personal preference.

The .clang-format file is copied directly from the Linux kernel without
any modifications, ensuring complete compatibility with kernel coding
standards.

Include comprehensive best practices for using clang-format,
specifically guidance on formatting only changed blocks versus entire
files, creating separate formatting-only commits for better code review,
and leveraging git clang-format for targeted formatting. Add examples of
editor integrations. This enhancement will help maintainers and
contributors to easily adhere to U-Boot coding standards.

Signed-off-by: Javier Tia <javier.tia@linaro.org>
2025-09-16 13:45:00 -06:00
Javier Tia
1b5a8ff3fd Lindent: Remove wrapper around indent tool
The Linux kernel has not maintained the same script since 2017-11-01,
and with clang-format included in U-Boot, it is not required anymore.

Signed-off-by: Javier Tia <javier.tia@linaro.org>
2025-09-16 13:45:00 -06:00
Javier Tia
aa711ac815 tools: zynqmp_psu_init_minimize.sh: Switch to clang-format
Replace the use of scripts/Lindent with clang-format in
zynqmp_psu_init_minimize.sh. This change is made to align with the rest
of the codebase that uses clang-format for code formatting. This ensures
consistency across all scripts in terms of code style and formatting.

Tested-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Javier Tia <javier.tia@linaro.org>
2025-09-16 13:45:00 -06:00
Javier Tia
29f6db89ad clang-format: Add configuration file
Introduce .clang-format configuration file to U-Boot, providing
significant improvements over the existing scripts/Lindent approach for
C code formatting.

Benefits of clang-format over scripts/Lindent:

- More comprehensive formatting rules: While Lindent relies on the basic
  'indent' tool with limited options, clang-format provides extensive
  control over code formatting with 800+ configuration options

- Better handling of complex code structures: clang-format understands
  modern C constructs and handles nested structures, macros, and complex
  expressions more intelligently

- IDE and editor integration: Native support in major development
  environments (VS Code, Vim, Emacs, etc.) enables real-time formatting

- Consistent results across environments: Eliminates variations between
  different versions of 'indent' tool and system configurations

- Active maintenance: clang-format is actively developed and updated,
  unlike the aging 'indent' tool

Alignment with Linux kernel practices:

Continues U-Boot alignment with Linux kernel development practices,
maintaining consistency between these closely related projects. The
Linux kernel adopted clang-format to modernize its code formatting
infrastructure and improve developer experience.

The .clang-format file is based on the Linux kernel configuration,
specifically copied from Linux kernel v6.16 tag, which itself builds
upon the initial introduction in commit d4ef8d3ff005c ("clang-format:
add configuration file").

Signed-off-by: Javier Tia <javier.tia@linaro.org>
2025-09-16 13:45:00 -06:00
Tom Rini
84b4ad629f Merge patch series "Fix ADI driver header dependencies"
Greg Malysa <malysagreg@gmail.com> says:

Between 2025.07 and 2025.10 many header dependency chains were improved,
but this exposed implicit header usage in several of our drivers. This
wasn't discovered before or included in the original fixes because our
drivers are not yet used by any mainline-supported boards, so build
tests did not find them. This series addresses the two build failures
I've encountered while rebasing our work onto 2025.10 and continuing to
prepare the next submission of our board files.

Link: https://lore.kernel.org/r/20250903234205.26787-1-malysagreg@gmail.com
2025-09-16 13:44:39 -06:00
Greg Malysa
2941e4c047 mmc: adi_sdhci: Update headers
As part of the header dependency cleanup between 2025.07 and 2025.10, an
implicit route to obtain SZ_128M from linux/sizes.h was removed. This
adds an explicit reference to linux/sizes.h to fix build failures for
this driver.

Signed-off-by: Greg Malysa <malysagreg@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2025-09-16 13:44:07 -06:00
Greg Malysa
56aa947c2a net: dwc_eth_qos_adi: Add missing header
Following header dependency cleanups, an implicit dependence on env.h
was exposed in dwc_eth_qos_adi. However because this driver is not (yet)
enabled in any defconfigs, build tests did not identify the missing
header. This adds the missing #include so that the driver builds
correctly when enabled.

Signed-off-by: Greg Malysa <malysagreg@gmail.com>
2025-09-16 13:44:07 -06:00
Aditya Dutt
bbc9347a98 cmd: terminal: avoid serial_reinit_all() with DM_SERIAL enabled
serial_reinit_all() is only available when CONFIG DM_SERIAL is disabled
and CONFIG_SERIAL is enabled.

Signed-off-by: Aditya Dutt <duttaditya18@gmail.com>
2025-09-16 13:43:33 -06:00
Philip Molloy
41d9ac1025 gpio: adp5588: Add ADP5587 as compatible
The ADP5587 is a simpler version of the ADP5588. The ADP5588 can
configure two pins, C8 and C9, as GPIOs or light sensors. The ADP5587
does not include the light sensors.

Signed-off-by: Philip Molloy <philip@philipmolloy.com>
2025-09-16 13:41:31 -06:00
Marek Vasut
8db442e1a0 env: Remove usb_ignorelist and env_fdt_path from ifdef CONFIG_ENV_VARS_UBOOT_CONFIG
The CONFIG_ENV_VARS_UBOOT_CONFIG should protect only U-Boot
configuration variables in environment, those are arch, cpu,
board, board_name, vendor, soc. It should certainly not hide
usb_ignorelist or env_fdt_path from the environment. Fix it.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2025-09-16 13:41:24 -06:00
Anshul Dalal
7aa5271def mach-k3: fix reading size and addr from fdt on R5
fdtdec_get_addr_size uses architecture dependent datatypes which causes
the 32-bit R5 to fail when reading the 64-bit size and addr fields of
reg nodes from the fdt.

Therefore change it to a common api for both 64 and 32 bit platforms to
allow for fdt fixups from R5.

Fixes: 8b0fc29de0 ("arm: mach-k3: am62: Fixup TF-A/OP-TEE reserved-memory node in FDT")
Signed-off-by: Anshul Dalal <anshuld@ti.com>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
2025-09-15 17:08:02 -06:00
Anshul Dalal
83bb1c4384 board: ti: common: Kconfig: add CMD_MEMINFO
Add CMD_MEMINFO and CMD_MEMINFO_MAP to list of configs implied by
TI_COMMON_CMD_OPTIONS. This allows users to easily view the memory
configuration and the memory maps at runtime.

Signed-off-by: Anshul Dalal <anshuld@ti.com>
2025-09-15 17:07:06 -06:00
Tom Rini
f0c1704f56 Revert "sandbox: replace deprecated getenv() with env_get()"
While testing changes, I missed that Gitlab had failed CI with pytest
failures due to this change.

This reverts commit 4c822970d3.

Cc: Osama Abdelkader <osama.abdelkader@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-09-12 16:57:39 -06:00
Osama Abdelkader
4c822970d3 sandbox: replace deprecated getenv() with env_get()
use env_get() instead of getenv() for consistency.

Signed-off-by: Osama Abdelkader <osama.abdelkader@gmail.com>
2025-09-12 14:35:46 -06:00
Marek Vasut
6dfd14e122 mkimage: Add support for bundling TFA BL31 in mkimage -f auto
Introduce two new parameters to be used with mkimage -f auto to bundle
TFA BL31 image into fitImage, using auto-generated fitImage. Add -y to
specify TFA BL31 file name and -Y to specify TFA BL31 load and entry
point address. This is meant to be used with systems which boot all of
TFA BL31, Linux and its DT from a single fitImage, all booted by U-Boot.

Example invocation:
"
$ mkimage -E -A arm64 -C none -e 0x50200000 -a 0x50200000 -f auto \
          -d arch/arm64/boot/Image \
	  -b arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dtb \
	  -y ../tfa/build/rcar_gen4/release/bl31.bin -Y 0x46400000 \
	  /path/to/output/fitImage
"

Documentation update and test are also included, the test validates
both positive and negative test cases, where fitImage does not include
TFA BL31 and does include TFA BL31 blobs.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-09-12 14:35:36 -06:00
Heinrich Schuchardt
559f11e66c bloblist: adjust default bloblist size after reloc
If neither CONFIG_BLOBLIST_FIXED NOR CONFIG_BLOBLIST_ALLOC is set,
currently CONFIG_BLOBLIST_SIZE_RELOC defaults to 0 except if
* CONFIG_ARM=y && CONFIG_EFI_LOADER=y && GENERATE_ACPI_TABLE=y.

A size of zero never makes sense for a bloblist.

When using QFW we need more than 64 KiB to host the ACPI table.
In this case CONFIG_BLOBLIST_ALLOC is used.

Set a reasonable default.

Remove the CONFIG_BLOBLIST_SIZE_RELOC in ARM QEMU defconfigs which are
not compatible with ACPI tables passed from QEMU.

Reported-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Fixes: 6f9b015c13 ("common: Enable BLOBLIST_TABLES on arm")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-09-12 13:49:34 -06:00
Heinrich Schuchardt
7e2c23eacd bloblist: use correct types for physical addresses
It is expected that bloblists are stored in high memory beyond 2 GiB.
We must not use int as data type for these addresses but phys_addr_t.

Fixes: f9ef9fb033 ("bloblist: Handle alignment with a void entry")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-09-12 13:49:34 -06:00
Tom Rini
5cd1b21bf6 Merge patch series "arm: mach-k3: am64x: Add reset cause for cpuinfo"
Steffen Kothe <steffen.kothe@skothe.net> says:

AM64X hereby receives support for reset reason printing during boot.

Unfortunately does the AM64X register mapping slighlty differ from
the AM62X. WDT and PORZ are not part of the reset source register, but
the mapping remains the same for all other causes.

To prevent ifdef/else constructs, I decided to follow a simple
copy/paste approach and adjusted the logic accordingly.

Link: https://lore.kernel.org/r/20250831151706.404373-1-steffen.kothe@skothe.net
2025-09-12 13:49:34 -06:00
Steffen Kothe
3d9bd76b07 arm: mach-k3: am64x: Implement get_reset_reason()
Implement get_reset_reason() for AM64x to enable reporting of the reset
cause in the cpuinfo output.

Notice that the AM64x does not support dedicated reset cause bits for
WDT and PORZ as the AM62x does.

An explanation of this difference is not part of the technical reference
manual and remains unclear.

Signed-off-by: Steffen Kothe <steffen.kothe@skothe.net>
Reviewed-by: Bryan Brattlof <bb@ti.com>
2025-09-12 12:30:08 -06:00
Steffen Kothe
49a3ad7a5e arm: mach-k3: am64_hardware.h: Add CTRLMMR_MCU_RST_SRC reset cause bit mappings
AM64X SoCs use similar but not identical bit mappings like the AM62X
family.

In detail does the AM64X not support PORZ and WDT as reset caused.

Add the mapping according to the technical reference manual into the
SoC specific header.

Signed-off-by: Steffen Kothe <steffen.kothe@skothe.net>
Reviewed-by: Bryan Brattlof <bb@ti.com>
2025-09-12 12:30:08 -06:00
Bhimeswararao Matsa
4d1caf58d2 board: ti: fdt_ops: make ti_set_fdt_env() const-correct
Make the fdt_map parameter a pointer to const, since the function only
reads the mapping table. This improves API correctness and allows maps
to live in read-only data.

No functional change intended

Signed-off-by: Bhimeswararao Matsa <bhimeswararao.matsa@gmail.com>
2025-09-11 13:14:17 -06:00
Judith Mendez
8633643769 board: ti: am65x: Overwrite get_overlay_mmc
Unlike other K3 SoC's, am65 SoC has the capability to detect daughter
cards and automatically generate a list of white-space separated overlays
in name_overlays environment variable.

When applied during boot with get_overlay_mmc, the path to overlays with
default distribution is incorrect where path is currently: boot/dtb and
the overlays exist in boot/dtb/ti.

Fix the path in get_overlay_mmc so that overlays are automatically applied
correctly during boot time.

Signed-off-by: Judith Mendez <jm@ti.com>
2025-09-11 13:14:17 -06:00
Udit Kumar
e3e7d0d29a arm: mach-k3: increase max resasg_entries
Increase max resasg_entries to accommodate max size of
largest device J784S4.

Link: https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/j784s4/resasg_types.html
Reported-by: Jared McArthur <j-mcarthur@ti.com>
Signed-off-by: Udit Kumar <u-kumar1@ti.com>
2025-09-11 13:14:00 -06:00
Judith Mendez
6fd45dd488 mach-k3: am62*: Fix backup from eMMC boot mode
Currently logic in spl_mmc_boot_mode only lookes at main devstat
to determine the bootmode to return. Thus, when using: 'eMMC boot'
as primary boot mode and 'MMCSD boot from eMMC UDA' as backup
boot mode, 'eMMC boot' is always selected. Add check for bootindex
to determine if ROM boot via backup boot mode and return MMCSD_MODE_FS
which is the only supported backup bootmode with eMMC device.

Signed-off-by: Judith Mendez <jm@ti.com>
Reviewed-by: Anshul Dalal <anshuld@ti.com>
Reviewed-by: Moteen Shah <m-shah@ti.com>
2025-09-11 11:59:35 -06:00
Heinrich Schuchardt
c85b8071e7 virtio: blk: support block sizes exceeding 512 bytes
QEMU allows to specify the logical block size via parameter
logical_block_size of a virtio-blk-device.

The communication channel via virtqueues remains based on 512 byte blocks
even if the logical_block_size is larger.

Consider the logical block size in the block device driver.

Reported-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Tested-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
2025-09-10 11:02:23 -06:00
Bhimeswararao Matsa
5964c6f4ef i2c: davinci: prefer kernel types (u8/u32)
Replace uint8_t/uint32_t with u8/u32 to match U-Boot style
(checkpatch PREFER_KERNEL_TYPES). No functional change.

Signed-off-by: Bhimeswararao Matsa <bhimeswararao.matsa@gmail.com>
2025-09-10 11:02:20 -06:00
Tom Rini
320d1d04eb checkpatch.pl: Ignore mdelay instead of udelay
Whereas in Linux, on ARM there is the notion of delay operations and
mdelay and udelay are not the same, here we just have udelay and mdelay
is a trivial wrapper. Tell checkpatch to not complain here.

Reported-by: Bhimeswararao Matsa <bhimeswararao.matsa@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-09-10 10:39:24 -06:00
Tony Dinh
8c599da506 fs: ext4fs: add CONFIG_EXT4_MAX_JOURNAL_ENTRIES to Kconfig
Add maximum ext4 journal entries to Kconfig. It is necessary since the
number of journal entries is proportional to disk capacity. For example,
an ext4 4TB HDD partition could require approximately 500 entries.

Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2025-09-10 10:39:09 -06:00
Tony Dinh
1f8fd9d37d fs: ext4fs: Add initialization failure recovery path in ext4fs_write
Don't invoke ext4fs_deinit() in ext4fs_write() if the failure occurs
during initialization. It would result in a crash since ext4fs_init()
has already done that.

Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2025-09-10 10:38:56 -06:00
Jan Kiszka
371a76e845 tools: Do not generate logo when cross-building
This cannot work (unless qemu-user is registered in binfmt_misc) as the
tools will be for a different architecture.

Fixes "make cross_tools" in case CONFIG_VIDEO_LOGO is enabled.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2025-09-10 10:38:50 -06:00
Tom Rini
7d921410ef Merge patch series "tools: fdtgrep: Mark util_version() as static"
This series from Ilias Apalodimas <ilias.apalodimas@linaro.org> lays
some of the groundwork for being able to enable the -Wmissing-prototypes
compiler flag while building U-Boot by fixing the obvious problems in
the tools directory.

Link: https://lore.kernel.org/r/20250829081628.2327372-1-ilias.apalodimas@linaro.org
2025-09-09 12:44:23 -06:00
Ilias Apalodimas
1e73651a71 tools: imx8image: Mark imx8mimage_check_params() as static
The function is only used locally. Enabling -Wmissing-prototypes
triggers a warning. Mark it as static.

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-09-09 12:44:07 -06:00
Ilias Apalodimas
f006837ead tools: imx8mimage: Mark build_image() as static
The function is only used locally. Enabling -Wmissing-prototypes
triggers a warning. Mark it as static.

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-09-09 12:44:07 -06:00
Ilias Apalodimas
39f7af39bb tools: fit_check_sign: Mark usage() as static
The function is only used locally. Enabling -Wmissing-prototypes
triggers a warning. Mark it as static.

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-09-09 12:44:07 -06:00
Ilias Apalodimas
5ab15814e8 tool: fit_info: Mark usage() as static
The function is only used locally. Enabling -Wmissing-prototypes
triggers a warning. Mark it as static.

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-09-09 12:44:07 -06:00
Ilias Apalodimas
3ae031135d tools: rkcommon: Mark rkcommon_is_header_v2() as static
The function is only used locally. Enabling -Wmissing-prototypes
triggers a warning. Mark it as static.

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
2025-09-09 12:44:07 -06:00
Ilias Apalodimas
867d762bc5 tools: mkimage: Mark copy_datafile() as static
The function is only used locally. Enabling -Wmissing-prototypes
triggers a warning. Mark it as static.

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-09-09 12:44:07 -06:00
Ilias Apalodimas
9fe4e088f3 tools: fdtgrep: Mark util_usage() as static
The function is only used locally. Enabling -Wmissing-prototypes
triggers a warning. Mark it as static.

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-09-09 12:44:07 -06:00
Ilias Apalodimas
3c34fd46b6 tools: fdtgrep: Mark util_version() as static
The function is only used locally. Enabling -Wmissing-prototypes
triggers a warning. Mark it as static.

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-09-09 12:44:07 -06:00
Marek Vasut
c9d4e82670 env: Fix up indent
Replace #define<TAB> with #define<space> to be consistent in
the entire file. No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2025-09-09 12:43:34 -06:00
Ilias Apalodimas
5d01a97180 arm64: Properly clear BSS
Brock reports a breakage on an RK3568 SoC. His patch is
correct but he never followed up on the requested changes.

We currently use ldr to calculate the address of __bss_start and
__bss_end. However the absolute addresses of the literal pool are never
relocated and we end up clearing the wrong memory section. Use
PC-relative addressing instead.

Link: https://lore.kernel.org/u-boot/zfknlzcemnnaka5w2er5wjwefwoidrpndc4gjhx6d5xr6nlcjr@pasfayjiutii/

Suggested-by: brock_zheng <yzheng@techyauld.com>
Reported-by: brock_zheng <yzheng@techyauld.com>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-09-09 12:43:26 -06:00
Mark Kettenis
a5b483a52a pci: apple: Fix use of uninitialized variable
Replace use of uninitialized variable with the PCI device number
in an error message as this is what we use elsewhere to derive
the PCIe port number.  Use ofnode_read_pci_addr() to read the
PCI address of the node and derive the device number from that.

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reported-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-09-09 11:04:16 -06:00
Jan Kiszka
ae84ef8c62 tools: Drop meaningless comment from Makefile
Introduced by 245b1029e1, probably a debug left-over.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Heiko Schocher <hs@nabladev.com>
2025-09-09 11:04:16 -06:00
Rasmus Villemoes
122c25c00a common/spl: use memmove() in load_simple_fit()
I had trouble booting some am335x boards (both
beagleboneblack and a custom board). SPL would start just fine, and
apparently load U-Boot proper, but it would hang when jumping to
U-Boot.

While debugging, I stumbled on this memcpy() which from code
inspection very much looked to have overlapping src and dst, and
indeed a simple printf revealed

  calling memcpy(0x8087bf68, 0x8087bf80, 0xf7f8)

Now, it will always be with src > dst, our memcpy()
implementations "most likely" do forward-copying, and in the end it
turned out that this wasn't the culprit after all [*].

But to avoid me or others barking up the wrong tree in the future, and
because this use of memcpy() is technically undefined, use memmove()
instead.

[*] That was 358d1cc232 ("spl: Align FDT load address"), which has
since been fixed in master but not the v2025.07 I worked of by
52caad0d14 ("ARM: Align image end to 8 bytes to fit DT alignment").

Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@gmx.de>
2025-09-09 10:35:59 -06:00
Tom Rini
aff7f1314a boot: Add LEGACY_IMAGE_FORMAT to DISTRO_DEFAULTS
At this time there are still major Linux distributions which by default
boot using LEGACY_IMAGE_FORMAT type scripts. Add this option to
DISTRO_DEFAULTS to ensure these platforms can still boot.

Fixes: d780965927 ("Drop the special am335x_boneblack_vboot target")
Reported-by: Sascha Silbe <sascha-pgp@silbe.org>
Tested-By: Sascha Silbe <sascha-pgp@silbe.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-09-09 10:30:57 -06:00
Alif Zakuan Yuslaimi
a3f0a8e7a1 misc: fs_loader: Initialize actread variable
Initialize the actread variable to prevent undefined behavior
that can occur if the variable is used before being assigned a
value.

This will help to prevent potential issues, especially if
actread is used (e.g., read, incremented, or returned) before
being explicitly set elsewhere in the code.

Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
2025-09-09 10:30:51 -06:00
Ben Hoelker
e0f9a4fb57 drivers: rtc: max313xx: Add delay after setting date
The MAX31331 was not correctly updating the seconds when
setting the time and would return the seconds previously set.

Like the MAX31343, a delay needs to be added after setting the
time. Wait one second after writing so that the date command shows the
correct time.

Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Reviewed-by: Bruce Adams <bruce.adams@alliedtelesis.co.nz>
Signed-off-by: Ben Hoelker <ben.hoelker@alliedtelesis.co.nz>
2025-09-09 10:30:41 -06:00
Tom Rini
d4a106f005 Merge tag 'v2025.10-rc4' into next
Prepare v2025.10-rc4
2025-09-08 10:37:22 -06:00
Tom Rini
1116d91596 Merge tag 'u-boot-imx-next-20250905a' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx into next
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/27573

- Several improvements for kontron-sl-mx6ul.
- Add Phytec imx8mp-libra-fpsc board
- Add redundant environment support for imx8m evk boards.
- Several improvements for phycore-imx93.
2025-09-05 10:48:05 -06:00
Benjamin Hahn
28d6f787b0 Add imx8mp-libra-fpsc board
Add new imx8mp-libra-fpsc board.
Bootph tags as well as USB device tree nodes are in u-boot.dtsi for now
and will be removed when upstreamed.
The Libra i.MX 8M Plus FPSC is a single board computer. It uses an i.MX
8M Plus FPSC [1] System on Module which utilizes the FPSC standard [2].

[1] https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-8m-plus-fpsc
[2] https://www.phytec.eu/en/produkte/system-on-modules/fpsc

Signed-off-by: Benjamin Hahn <B.Hahn@phytec.de>
Reviewed-by: Teresa Remmet <t.remmet@phytec.de>
Tested-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Yannic Moog <y.moog@phytec.de>
2025-09-05 09:04:59 -03:00
Fabio Estevam
5d75b4f876 imx8m[m,n,p]_evk: Add redundant environment support
For reliable Over The Air update, it is recommended that redundant
environment is used.

Add redundant environment support for the i.MX8M EVK boards.

While at it, increase the environment size and adjust the offset.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
2025-09-05 09:04:43 -03:00
Primoz Fiser
b4ab315a0a board: phytec: phycore-imx93: Use CONFIG_PHYTEC_EEPROM_BUS
Switch to use CONFIG_PHYTEC_EEPROM_BUS instead of the hard coded value
of 2 for the EEPROM I2C bus for both SPL and U-Boot proper. Possible
since commit 88a1816a9b ("board: phytec: common: Add PHYTEC_EEPROM_BUS
to Kconfig").

Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
Reviewed-by: Wadim Egorov <w.egorov@phytec.de>
2025-09-05 09:04:20 -03:00
Primoz Fiser
d271a01dbe configs: imx93-phycore_defconfig: Disable CONFIG_AHAB_BOOT
By default, lets disable configuration option CONFIG_AHAB_BOOT=y on the
phyCORE-i.MX93 based boards. This option is only used in the secureboot
context which is not provided by default anyway. Lets remove it from the
defconfig to not give false impressions it is supported out of the box
for this board.

On the other hand, in the context of PHYTEC secureboot, this option is
selected by the distro which enables CONFIG_AHAB_BOOT among other secure
boot related options and tweaks needed to properly support it.

Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
Reviewed-by: Martin Schwan <m.schwan@phytec.de>
2025-09-05 09:04:20 -03:00
Primoz Fiser
8c690095b8 arm: dts: imx93-phyboard-segin-u-boot: Clean-up already upstream nodes
Clean-up "imx93-phyboard-segin-u-boot.dtsi" internal device-tree from
nodes already part of the upstream device-tree since commit 79f3e77133
("Subtree merge tag 'v6.16-dts' of dts repo [1] into dts/upstream"). No
functional change is made with this commit.

Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
2025-09-05 09:04:01 -03:00
Ilias Apalodimas
d95c4bebf4 tools: imx8image: Make imx8image_check_params() static
We are trying to enable -Wmissing-prototypes and this functiion is only
used locally. Mark it as static.

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Acked-by: Peng Fan <peng.fan@nxp.com>
2025-09-05 09:03:45 -03:00
Frieder Schrempf
1f87a8ac6b imx: kontron-sl-mx6ul: Switch to OF_UPSTREAM
Use the upstream devicetrees instead of the local ones.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
[fabio: Remove imx6ul-kontron-bl.dtb and imx6ull-kontron-bl.dtb from Makefile]
2025-09-05 09:03:28 -03:00
Eberhard Stoll
6bfd81c339 imx: kontron-sl-mx6ul: Force default environment for serial loader boot
In case of booting from serial loader (USB) we want to always use the
default environment in order to get a defined state that is
independent of any environment stored in persistent memory.

This way we can avoid corruption of the boot process during
development and manufacturing by existing environment settings in
flash.

Signed-off-by: Eberhard Stoll <eberhard.stoll@kontron.de>
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2025-09-05 09:03:28 -03:00
Eberhard Stoll
827e45f28f imx: kontron-sl-mx6ul: Enable CONFIG_ENV_IS_NOWHERE
For some cases it is beneficial to not store the environment in
persistent memory, but instead use the default environment and
keep it in volatile RAM only. Allow this by enabling
CONFIG_ENV_IS_NOWHERE.

Signed-off-by: Eberhard Stoll <eberhard.stoll@kontron.de>
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2025-09-05 09:03:28 -03:00
Frieder Schrempf
9e26426ceb imx: kontron-sl-mx6ul: Enable watchdog and sysreset
Enable the watchdog and sysreset drivers and the wdt command.
This also fixes the non-working 'reset' command.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2025-09-05 09:03:28 -03:00
Annette Kobou
410d9ccc03 imx: kontron-sl-mx6ul: Autostart fastboot if booted from USB
For booting via USB we want to automatically start the fastboot
command in order to access the board via uuu or other tools.

This allows for easier bringup of new boards during development
and manufacturing.

Signed-off-by: Annette Kobou <annette.kobou@kontron.de>
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2025-09-05 09:03:28 -03:00
Oualid Derouiche
6bd59313e0 imx: kontron-sl-mx6ul: Enable redundant environment
This aligns the MTD partitions on the SPI NOR with the kernel
devicetree and enables the redundant environment.

Signed-off-by: Oualid Derouiche <oualid.derouiche@kontron.de>
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2025-09-05 09:03:28 -03:00
Annette Kobou
f3406a2364 imx: kontron-sl-mx6ul: Enable fastboot support
Enable support for fastboot commands via USB.

Signed-off-by: Annette Kobou <annette.kobou@kontron.de>
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2025-09-05 09:03:28 -03:00
Frieder Schrempf
048fdda977 imx: kontron-sl-mx6ul: Enable second ethernet interface
This ensures both interfaces can be used in U-Boot and both MAC addresses
are exported to the Linux kernel devicetree.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2025-09-05 09:03:28 -03:00
Frieder Schrempf
8addeb94c7 imx: kontron-sl-mx6ul: Set CONFIG_SDP_LOADADDR to fix SDP boot
We need to set CONFIG_SDP_LOADADDR to a valid RAM address to make
SDP boot work. Use the end of the DDR (256 MiB minimum) as other
boards do.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2025-09-05 09:03:28 -03:00
Frieder Schrempf
7118d961cc imx: kontron-sl-mx6ul: Enable standard boot and disable legacy distro boot
Disable the legacy distro boot and use bootstd instead.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2025-09-05 09:03:28 -03:00
Frieder Schrempf
eb314cb566 imx: kontron-sl-mx6ul: Fix include statements for local header
The header from the local directory should use double quotes instead
of brackets. Otherwise the compiler might not search the local
directory.

Fixes: 93935acc6f ("imx: imx6ul: kontron-sl-mx6ul: Select correct boot and env device")
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2025-09-05 09:03:28 -03:00
Tom Rini
e31947724f Merge patch series "memtest performance improvements"
Rasmus Villemoes <ravi@prevas.dk> says:

The first two patches make memtest run ~40x faster (when, as it should
be, dcache is disabled), with the second patch being responsible for
most of that. At least on the beagleboneblack which I used for
testing; other boards and configurations will likely see different
numbers.

This is for CONFIG_SYS_ALT_MEMTEST=y and
CONFIG_SYS_ALT_MEMTEST_BITFLIP=n; one could probably get a similar
improvement in the bitflip case since that also has a schedule() call
in the inner loop.

Link: https://lore.kernel.org/r/20250822181848.3325832-1-ravi@prevas.dk
2025-09-02 14:11:45 -06:00
Rasmus Villemoes
42529beba5 memtest: remove use of vu_long typedef in mem_test_alt
Hiding a qualifier such as "volatile" inside a typedef makes the code
much harder to understand. Since addr and dummy being
volatile-qualified are important for the correctness of the test code,
make it more obvious by spelling it out as "volatile ulong".

Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
Tested-by: Anshul Dalal <anshuld@ti.com>
2025-09-02 14:11:36 -06:00
Rasmus Villemoes
835915bb7d memtest: only call schedule() once for every 256 words
A function call itself for every word written or read+written in these
loops is bad enough. But since the memory test must be run with dcache
disabled, the schedule() call, traversing the linked list of
registered cyclic clients, and accessing the 'struct cyclic_info' for
each to see if any are due for a callback, is quite expensive. On a
beagleboneblack, testing a modest 16MiB region takes 2.5 minutes:

  => dcache off
  => time mtest 0x81000000 0x82000000 0 1
  Testing 81000000 ... 82000000:
  Iteration:      1
  Tested 1 iteration(s) with 0 errors.

  time: 2 minutes, 28.946 seconds

There is really no need for calling schedule() so frequently. It is
quite easy to limit the calls to once for every 256 words by using a
u8 variable. With that, the same test as above becomes 37 times
faster:

  => dcache off
  => time mtest 0x81000000 0x82000000 0 1
  Testing 81000000 ... 82000000:
  Iteration:      1
  Tested 1 iteration(s) with 0 errors.

  time: 4.052 seconds

Note that we are still making a total of

  3 loops * (4 * 2^20 words/loop) / (256 words/call) = 49152 calls

during those ~4000 milliseconds, so the schedule() calls are still
done less than 0.1ms apart.

These numbers are just for a beagleboneblack, other boards may have a
slower memory, but we are _two orders of magnitude_ away from
schedule() "only" being called at 100Hz, which is still more than
enough to ensure any watchdog is kept happy.

Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
Tested-by: Anshul Dalal <anshuld@ti.com>
2025-09-02 14:11:36 -06:00
Rasmus Villemoes
86c5c25b6c memtest: don't volatile-qualify local variables
It is obviously important that the addr pointer used to access the
memory region being tested is volatile-qualified, to prevent the
compiler from optimizing out the "write this value, read it back,
check that it is what we expect".

However, none of these auxiliary variables have any such need for,
effectively, being forced to live on the stack and cause each and
every reference to them to do a memory access.

This makes the memtest about 15% faster on a beagleboneblack.

Before:

  => dcache off
  => time mtest 0x81000000 0x81100000 0 1
  Testing 81000000 ... 81100000:
  Iteration:      1
  Tested 1 iteration(s) with 0 errors.

  time: 10.868 seconds

After:

  => dcache off
  => time mtest 0x81000000 0x81100000 0 1
  Testing 81000000 ... 81100000:
  Iteration:      1
  Tested 1 iteration(s) with 0 errors.

  time: 9.209 seconds

[Without the 'dcache off', there's no difference in the time, about
0.6s, but the memtest cannot usefully be done with dcache enabled.]

Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
Tested-by: Anshul Dalal <anshuld@ti.com>
2025-09-02 14:11:36 -06:00
Tom Rini
185aa00a4f Merge tag 'mmc-power-next-2025-09-01' of https://source.denx.de/u-boot/custodians/u-boot-mmc into next
CI: https://source.denx.de/u-boot/custodians/u-boot-mmc/-/pipelines/27536

- Update compatibles for PMICs used by exynos devices
- Support system reset and reset status for pca9450
- Fix for pca9450 LDO5 registers and drop deprecated sd-vsel-gpios
- Two minor fixes found by smatch
2025-09-01 14:32:00 -06:00
Bhimeswararao Matsa
140562d3a2 mmc: core: drop space before newline in trace printf
Remove unnecessary whitespace before '\n' in trace printf
format strings (checkpatch warning QUOTED_WHITESPACE_BEFORE_NEWLINE).

No functional change intended.

Signed-off-by: Bhimeswararao Matsa <bhimeswararao.matsa@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-09-01 10:33:10 +08:00
Andrew Goodbody
95994d4e59 mmc: iproc_sdhci: Cannot test unsigned variable for negative
In sdhci_iproc_execute_tuning the variable tuning_loop_counter is
unsigned and therefore will always fail the test for it being less than
0. Fix this by changing the variable type to be s8.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-09-01 10:33:09 +08:00
Primoz Fiser
ad197b31b3 power: pmic: pca9450: Add support for reset status
PCA9450 PMIC supports reading the reset status from the PWRON_STAT
register. Bits 7-4 give indication of the PMIC reset cause:

 - PWRON (BIT7) - Power ON triggered by PMIC_ON_REQ input line,
 - WDOGB (BIT6) - Boot after cold reset by WDOGB pin (watchdog reset),
 - SW_RST (BIT5) - Boot after cold reset initiated by the software,
 - PMIC_RST (BIT4) - Boot after PMIC_RST_B input line trigger.

Add support for reading reset status via the sysreset framework in a
convenient printable format.

Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
Reviewed-by: Paul Geurts <paul.geurts@prodrive-technologies.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-09-01 10:33:09 +08:00
Primoz Fiser
9065b87f35 power: pmic: pca9450: Add support for system reset
The family of PCA9450 PMICs have the ability to perform system resets.
Restarting via PMIC is preferred method of restarting the system as all
the peripherals are brought to a know state after a power-cycle. The
PCA9450 features a cold restart procedure which is initiated by an I2C
command 0x14 to the SW_RST register.

Support in Linux for restarting via PCA9450 PMIC has been added by
Linux commit 6157e62b07d9 ("regulator: pca9450: Add restart handler").

Now add support for it also in the U-Boot via sysreset framework.

Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
Reviewed-by: Paul Geurts <paul.geurts@prodrive-technologies.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-09-01 10:33:09 +08:00
Henrik Grimler
a65798ddbb board: samsung: odroid: drop exynos_power_init
exynos_power_init sets up regulators for the emmc and sdcard, but
these regulators are already marked as always-on and boot-on and hence
are handled already by the regulator-uclass. Since we currently try to
set them up twice we get error -114 (EALREADY) from exynos_power_init
on every boot:

    LDO20@VDDQ_EMMC_1.8V: set 1800000 uV; enabling (ret: -114)
    LDO22@VDDQ_EMMC_2.8V: set 2800000 uV; enabling (ret: -114)
    LDO21@TFLASH_2.8V: set 2800000 uV; enabling (ret: -114)

Remove the superfluous exynos_power_init to silence these errors.

Signed-off-by: Henrik Grimler <henrik@grimler.se>
Reviewed-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-09-01 10:33:09 +08:00
Henrik Grimler
cec29c00bc ARM: dts: trats: rename max8997-pmic regulators node
Linux uses just regulators { }; instead of voltage-regulators { };, so
this change aligns the DTSes found in the two projects.

The max8997 driver does not yet parse the regulators node, so we can
safely change its name without breaking anything.

Signed-off-by: Henrik Grimler <henrik@grimler.se>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-09-01 10:33:08 +08:00
Henrik Grimler
31c376cf4f power: pmic: max8997: drop maxim,max8997 compatible
All u-boot users now use maxim,max8997-pmic instead, as does Linux's
DTSes, so we can now safely drop the maxim,max8997 compatible.

Signed-off-by: Henrik Grimler <henrik@grimler.se>
Reviewed-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-09-01 10:33:08 +08:00
Henrik Grimler
1ca245d1c5 ARM: dts: exynos4210-trats: use maxim,max8997-pmic compatible
Instead of maxim,max8997. Linux uses maxim,max8997-pmic, so with this
change we align the trats DTS with its linux counterpart.

Signed-off-by: Henrik Grimler <henrik@grimler.se>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-09-01 10:33:08 +08:00
Henrik Grimler
920404409c power: pmic: max8997: support maxim,max8997-pmic compatible as well
Linux's DTSes uses maxim,max8997-pmic, so check for this compatible
as well so that max8997 pmic driver can support both u-boot and
Linux's DTSes.

Signed-off-by: Henrik Grimler <henrik@grimler.se>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-09-01 10:33:07 +08:00
Henrik Grimler
0fdd3b4243 power: pmic: fix typo and capitalisation in max8997 Kconfig help msg
To make the help message slightly easier to understand.

Signed-off-by: Henrik Grimler <henrik@grimler.se>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-09-01 10:33:07 +08:00
Henrik Grimler
e64d1a0317 ARM: dts: s5c1xx-goni: rename max8998-pmic regulators node
Linux uses just regulators { }; instead of voltage-regulators { };, so
this change aligns the DTSes found in the two projects.

The max8998 driver does not yet parse the regulators node, so we can
safely change its name without breaking anything.

Signed-off-by: Henrik Grimler <henrik@grimler.se>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-09-01 10:33:07 +08:00
Henrik Grimler
89cad7ed6f ARM: dts: exynos4210-universal_c210: rename max8998 regulators node
Linux uses just regulators { }; instead of voltage-regulators { };, so
this change aligns the DTSes found in the two projects.

The max8998 driver does not yet parse the regulators node, so we can
safely change its name without breaking anything.

Signed-off-by: Henrik Grimler <henrik@grimler.se>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-09-01 10:33:07 +08:00
Henrik Grimler
983a16f386 power: pmic: s2mps11: remove check for voltage-regulators node
All devicetrees that use s2mps11 driver have been converted to use
regulators { };, so we can safely drop the voltage-regulators fallback
check.

Signed-off-by: Henrik Grimler <henrik@grimler.se>
Reviewed-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-09-01 10:33:06 +08:00
Henrik Grimler
8575c09a42 ARM: dts: exynos5422-odroidxu3: rename s2mps11 regulators node
With this both linux and u-boot uses the same node name, which
simplifies devicetree parsing in s2mps11 driver.

Signed-off-by: Henrik Grimler <henrik@grimler.se>
Reviewed-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-09-01 10:33:06 +08:00
Henrik Grimler
38443338c7 power: pmic: s2mps11: look for both {voltage-,}regulators
Linux's DTSes uses regulators { }; while u-boot's DTSes uses
voltage-regulators { };.  Look for regulators, and fallback to
voltage-regulators if not found, so that both type of DTSes can be
used with the driver.

Signed-off-by: Henrik Grimler <henrik@grimler.se>
Reviewed-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-09-01 10:33:06 +08:00
Frieder Schrempf
dc0a12fece arm: dts: imx8mp-dhcom-som: Remove deprecated sd-vsel-gpios
The sd-vsel-gpios property in the root of the PMIC node is deprecated
and therefore not parsed by the driver anymore. We can safely remove
this as it wasn't used anyway due to the pad not having the correct
pinmux settings.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Marek Vasut <marek.vasut@mailbox.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-09-01 10:33:06 +08:00
Frieder Schrempf
925f63b020 arm: dts: imx8mp-data-modul-edm-sbc: Remove deprecated sd-vsel-gpios
The sd-vsel-gpios property in the root of the PMIC node is deprecated
and therefore not parsed by the driver anymore. We can safely remove
this as it wasn't used anyway due to the pad not having the correct
pinmux settings.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Marek Vasut <marek.vasut@mailbox.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-09-01 10:33:05 +08:00
Frieder Schrempf
281829f5ca pmic: pca9450: Handle hardware with fixed SD_VSEL for LDO5
There are two ways to set the output voltage of the LD05
regulator. First by writing to the voltage selection registers
and second by toggling the SD_VSEL signal.

Usually board designers connect SD_VSEL to the VSELECT signal
controlled by the USDHC controller, but in some cases the
signal is hardwired to a fixed low level (therefore selecting
3.3V as initial value for allowing to boot from the SD card).

In these cases, the voltage is only determined by the value
of the LDO5CTRL_L register. Introduce a property
nxp,sd-vsel-fixed-low to let the driver know that SD_VSEL
is low and there is no GPIO to actually get that
information from dynamically.

This is equivalent to the following change in Linux:

c8c1ab2c5cb7 ("regulator: pca9450: Handle hardware with fixed SD_VSEL for LDO5")

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-09-01 10:33:05 +08:00
Frieder Schrempf
addfe45446 pmic: pca9450: Fix control register for LDO5
For LDO5 we need to be able to check the status of the SD_VSEL input in
order to know which control register is used. Read the status of the
SD_VSEL signal via GPIO and use the correct register accordingly.

To use this, the LDO5 node in the devicetree needs the sd-vsel-gpios
property to reference the GPIO that is used to read back the SD_VSEL
status internally. Please note that the SION bit in the IOMUX must be
set if the signal is muxed as VSELECT and controlled by the USDHC
controller.

This is equivalent to the following change in Linux:

3ce6f4f943dd ("regulator: pca9450: Fix control register for LDO5")

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-09-01 10:33:05 +08:00
Frieder Schrempf
8a04fbd9af pmic: pca9450: Fix enable register for LDO5
The LDO5 regulator has two configuration registers, but only
LDO5CTRL_L contains the bits for enabling/disabling the regulator.

This is equivalent to the following change in Linux:

f5aab0438ef1 ("regulator: pca9450: Fix enable register for LDO5")

Fixes: 326337fb00 ("pmic: pca9450: Add regulator driver")
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-09-01 10:33:05 +08:00
Frieder Schrempf
b7360bd9e8 Revert "pmic: pca9450: Add optional SD_VSEL GPIO for LDO5"
This reverts commit 2add051175.

It turns out that all boards using the PCA9450 actually have the
SD_VSEL input connected to the VSELECT signal of the SoCs SD/MMC
interface. Therefore we don't need manual control for this signal
via GPIO and there aren't any users.

This is equivalent to the following change in Linux:

c73be62caabb ("Revert "regulator: pca9450: Add SD_VSEL GPIO for LDO5"")

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-09-01 10:33:05 +08:00
Andrew Goodbody
58b8ff0b66 power: regulator: tps65910: Cannot test unsigned for being negative
The code in tps65910_regulator.c treats the field supply in struct
tps65910_regulator_pdata as an int and even tests the value for being
negative so change it from a u32 to int so that the code all works as
expected.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-09-01 10:33:04 +08:00
Tom Rini
c9ffeefeb3 test: Update logic for video test
The video test here is specific to the sandbox SDL video driver, so only
build it when that is enabled rather than VIDEO is enabled.

Reported-by: Alison Chaiken <alison@she-devel.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-08-31 09:32:17 -06:00
Tom Rini
f90f10a933 Merge patch series "power: regulator: Fix some Smatch reported issues"
Andrew Goodbody <andrew.goodbody@linaro.org> says:

Smatch reported some issues in the regulator drivers, mostly repeated
instances of testing an unsigned variable for being negative but also an
expression needing parenthesis to be interpreted as expected.

[trini: Drop 5/6 for now due to changes being requested on review]

Link: https://lore.kernel.org/r/20250807-pwr_regulator-v1-0-42a4105336ec@linaro.org
2025-08-31 09:32:17 -06:00
Tom Rini
230e8dbc39 Merge patch series "power: Address two Smatch reported issues"
Andrew Goodbody <andrew.goodbody@linaro.org> says:

Smatch reported issues with two power drivers due to redundant code and
an unitialised variable.

Link: https://lore.kernel.org/r/20250807-power_misc-v1-0-2ac672f15461@linaro.org
2025-08-31 09:32:17 -06:00
Tom Rini
384079802a power: Tighten some power driver dependencies
The MediaTek mt6323 power driver cannot build without access to some
platform specific header files. Express that requirements in Kconfig as
well.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-08-31 09:32:17 -06:00
Tom Rini
9d875d674f power: Split *POWER_LEGACY portion of <power/pmic.h> out to new header
The commends in include/power/pmic.h say that once SPL_DM_PMIC exists we
should update things. This has been true for some time, so let us update
this to have the legacy portions in their own header, which should not
be directly included. This cleans up the logic within the file too
slightly.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-08-31 09:32:17 -06:00
Tom Rini
31a309ff3e power: Correct dependencies on POWER_LEGACY
The POWER_LEGACY option functionally depends on not having DM_PMIC
enabled, so add that here.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-08-31 09:32:17 -06:00
Andrew Goodbody
c18435e648 power: regulator: tps65941: Cannot test unsigned for being negative
In tps65941_buck_val and tps65941_ldo_val hex is an unsigned variable
being assigned the return value from a function that returns int. Change
hex to be an int so that the following test for an error as a negative
value will work as expected.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2025-08-29 16:45:19 -06:00
Andrew Goodbody
cdc0e32e9c power: regulator: rzg2l-usbphy: Add parenthesis to return expression
In order to get the expected result from
rzg2l_usbphy_regulator_get_enable the return expression needs
parenthesis so that the binary and is performed before the double
logical not.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2025-08-29 16:45:19 -06:00
Andrew Goodbody
96312ed796 power: regulator: palmas: Cannot test unsigned for being negative
In palmas_smps_val and palmas_ldo_val hex is an unsigned variable being
assigned the return value from a function that returns int. Change hex
to be an int so that the following test for an error as a negative value
will work as expected.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2025-08-29 16:45:19 -06:00
Andrew Goodbody
8f90028ccd power: regulator: lp87565: Cannot test unsigned for being negative
In lp87565_buck_val hex is an unsigned variable being assigned the return
value from a function that returns int. Change hex to be an int so that
the following test for an error as a negative value will work as expected.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2025-08-29 16:45:19 -06:00
Andrew Goodbody
42f959d0b0 power: regulator: lp873x: Cannot test unsigned for being negative
In lp873x_buck_val and lp873x_ldo_val hex is an unsigned variable being
assigned the return value from a function that returns int. Change hex
to be an int so that the following test for an error as a negative value
will work as expected.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2025-08-29 16:45:19 -06:00
Andrew Goodbody
aa136393c8 power: power_i2c: ret is uninitialised if not DM_I2C
In pmic_reg_read ret is only assigned to inside #if
CONFIG_IS_ENABLED(DM_I2C) so move the test and return ret inside as well
and also guard the declaration of ret with CONFIG_IS_ENABLED(DM_I2C) to
prevent a warning about an unused variable.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
2025-08-29 16:44:46 -06:00
Andrew Goodbody
446b7b8f2d power: axp: Remove redundant code
In axp_init after checking the chip ID there is an else clause that
returns ret. ret is guaranteed to be 0 at this point as the code would
have returned above if not. The next statement is a return 0 so the
return ret is redundant, remove it.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
2025-08-29 16:44:46 -06:00
Tom Rini
59d1ce83dd Merge tag 'xilinx-for-v2026.01-rc1' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next
AMD/Xilinx/FPGA changes for v2026.01-rc1

mbv:
- Add it to CI loop

versal2:
- Wire UFS driver

serial:
- Add support for OF_PLATDATA in uartlite

misc:
- Mark some structures as const
2025-08-28 07:54:38 -06:00
Tom Rini
88938be302 Merge tag 'fsl-qoriq-next-2025-08-27' of https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq into next
CI: https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq/-/pipelines/27490

- Various patches from Andrew to address issues found by Smatch
- Reinitialize job ring in crypto fsl rng
- Set scaler values for fsl dspi CS-SCK and SCK-CS
2025-08-27 08:49:38 -06:00
Anthony Pighin (Nokia)
8b97d7569a drivers: crypto: fsl: rng: Reinitialize job ring
u-boot internals were being corrupted following an EFI callback to
get_rng(). One of the many footprints was a corruption of the EFI
protocols linked list.

A request for >16 bytes of random data is broken into smaller requests.
Those requests are fed in a loop to the CAAM RNG, which uses a job
queue ring for interaction.

However, the job queue descriptor is created only at probe time. That
descriptor may end up needing an endian swap (LS1046A) before being fed
to the CAAM RNG. This corrupts the descriptor for the next iteration,
since it will be blindly endian swapped yet again.

Two issues arise. The number of words to endian swap is taken from the
input descriptor itself. So on the second iteration, the length has been
corrupted. This results in a corruption past the end of the descriptor:
whatever is after in memory is endian swapped too. Second, some of the
entries in the descriptor are DMA addresses. If the descriptor is still
somehow considered valid after swapping, the data at the corrupted DMA
address is now trampled.

Linux properly initializes the descriptor for each iteration. This is
what is now done with this commit.

Signed-off-by: Anthony Pighin <anthony.pighin@nokia.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-08-27 16:12:21 +08:00
Tomas Alvarez Vanoli
1363f9c1a0 fsl_dspi: set scaler values for CS-SCK and SCK-CS delays
These values were calculated but not set.
They are required for the calculation of the delays, as stated in the
"QorIQ LS1043A Reference Manual, Rev. 6, 07/2020" page 2172.

The delays are calculated as (1/freq)*PCSSCK*CSSCK and
(1/freq)*PASC*ASC.

Signed-off-by: Tomas Alvarez Vanoli <tomas.alvarez-vanoli@hitachienergy.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-08-27 15:53:25 +08:00
Andrew Goodbody
4d3183723f serial: lpuart: Return value from correct variable
In get_lpuart_clk_rate if the call to clk_get_rate returns an error then
the call to return should pass the value of the error which is in rate
rather than ret which will be 0 as its value is not affected by this
error.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-08-27 15:52:20 +08:00
Andrew Goodbody
dc37adfc04 drivers: qe: avoid double free()
Avoid calling free(addr) twice if the device for ucode is not found.
This patch repeats a similar fix but that only applied to code without
CONFIG_TFABOOT enabled. This patch applies to the code with
CONFIG_TFABOOT enabled.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-08-27 15:49:59 +08:00
Andrew Goodbody
05b1114636 net: fsl-mc: Incorrect variable used in error path
In mc_fixup_dpc_mac_addr noff is assigned the return value from
fdt_add_subnode so that is the variable that should be passed to
fdt_strerror and returned when negative.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-08-27 15:42:09 +08:00
Andrew Goodbody
010a4c5c55 net: fsl-mc: NULL check dflt_dpni before dereference
In dpni_exit there is a NULL check for dflt_dpni after it is
dereferenced a number of times. Instead move the NULL check to early in
the function. Also assign NULL to dflt_dpni after free in both dpni_init
and dpni_exit.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-08-27 15:42:08 +08:00
Andrew Goodbody
9ca756cee7 net: fsl-mc: NULL check dflt_dpbp before dereference
In dpbp_exit there is a NULL check for dflt_dpbp after it is
dereferenced a number of times. Instead move the NULL check to early in
the function. Also assign NULL to dflt_dpbp after free in both dpbp_init
and dpbp_exit.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-08-27 15:42:08 +08:00
Andrew Goodbody
756580d090 net: fsl-mc: NULL check dflt_dpio before dereference
In dpio_exit there is a NULL check for dflt_dpio but it happens after
dpio_dflt has been dereferenced a number of times already. Instead move
the NULL check to first thing in the function. Also assign NULL to
dflt_dpio after free in both dpio_init and dpio_exit.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-08-27 15:42:08 +08:00
Andrew Goodbody
f4c2a12611 net: fsl_enetc: Fix copy/paste error
In netc_blk_ctrl_probe the test for failure of the function
clk_prepare_enable should not return PTR_ERR(ipg_clk) as it does not
check IS_ERR(ipg_clk) instead it should return err as that is what is
holding the error code in this case.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-08-27 15:42:07 +08:00
Andrew Goodbody
5b95f666fb net: fm: Correct test for timeout
In memac_wait_until_free and memac_wait_until_done the use of
post-decrement on the test in the while loop for a timeout means that
timeout will be equal to -1 on exit in that case. Adjust the test for
this expected value.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-08-27 15:39:58 +08:00
Andrew Goodbody
270798a420 net: fm: NULL check dev before dereference
In fm_eth_bind there is a dereference of dev before it is NULL checked.
Add a NULL check before the first dereference and remove a later NULL
check that is now redundant.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-08-27 15:39:57 +08:00
Andrew Goodbody
44d321f009 net: fm: Correct test for timeout
In bmi_rx_port_disable and bmi_tx_port_disable the use of post-decrement
on the test in the while loop for a timeout means that timeout will be
equal to -1 on exit in that case. Adjust the test for this expected
value.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-08-27 15:39:57 +08:00
Andrew Goodbody
377159bfb8 ddr: fsl: Provide initial value for zqcs_init
In the case of !zq_en zqcs_init is never assigned to although its value
is used. Correct by initialising zqcs_init to 0.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-08-27 15:39:05 +08:00
Lucien.Jheng
b5da53046c misc: fs_loader: Add request_firmware_into_buf_via_script() for flexible firmware loading via U-Boot script
This commit introduces a new API,
request_firmware_into_buf_via_script(), to the fs_loader framework.
This function allows firmware to be loaded into memory using
a user-defined U-Boot script, providing greater flexibility for
firmware loading scenarios that cannot be handled by static file
paths or device/partition selection alone.

Key features:
- The API runs a specified U-Boot script (by name), which is responsible
  for loading the firmware into memory by any means (e.g., load from MMC, USB, network, etc.).
- The script must set two environment variables: 'fw_addr'
  (the memory address where the firmware is loaded) and
  'fw_size' (the size of the firmware in bytes).
- The function validates these variables, copies the firmware into a newly
  allocated buffer (using memdup), and returns the pointer
  via the provided double pointer argument.
- The maximum allowed firmware size is checked to prevent buffer overflows.
- The environment variables are cleared after use to avoid stale data.
- Detailed error messages are provided for all failure conditions to aid debugging.

Usage example:
1. Define a U-Boot script in the environment that loads the firmware
   and sets the required variables:
   => env set my_fw_script 'load mmc 0:1 ${loadaddr} firmware.bin &&
   env set fw_addr ${loadaddr} && env set fw_size ${filesize}'

2. In your code, call the new API:
   void *fw_buf = NULL;
   int ret = request_firmware_into_buf_via_script(&fw_buf, 0x46000000, "my_fw_script");
   if (ret < 0)
		return ret;

This approach allows board integrators and users to customize the firmware
loading process without modifying the source code,
simply by changing the script in the U-Boot environment.

Signed-off-by: Lucien.Jheng <lucienzx159@gmail.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[trini: Fix printf of size_t needing to use %zx]
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-08-26 14:39:15 -06:00
Tom Rini
b4ae292606 Merge patch series "Update SoM detection related code and configs"
Wadim Egorov <w.egorov@phytec.de> says:

Update Kconfig options for phyCORE-AM62Ax to align with other boards and
prepare common board code for the upcoming phyCORE-AM62L which has the
SoM EEPROM connected on a different bus.

Link: https://lore.kernel.org/r/20250815111051.2277173-1-w.egorov@phytec.de
2025-08-26 14:37:02 -06:00
Wadim Egorov
9cf4f522fc board: phytec: phycore-am62a: Update SoM detection Kconfig options
Drop SUPPORT_EXTENSION_SCAN and enable PHYTEC_SOM_DETECTION_BLOCKS
to align with other PHYTEC platforms. These options were missed when
phyCORE-AM62Ax support was added.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
2025-08-26 12:49:21 -06:00
Wadim Egorov
7e86c8f1dc configs: phycore_am62ax_a53_defconfig: Resync after savedefconfig
Remove PHYTEC_SOM_DETECTION_BLOCKS after it was enabled per default
for this platform.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
2025-08-26 12:49:21 -06:00
Dominik Haller
437f663e6c board: phytec: common: k3: Use CONFIG_PHYTEC_EEPROM_BUS
Use CONFIG_PHYTEC_EEPROM_BUS instead of the hard coded value for the i2c bus.

Signed-off-by: Dominik Haller <d.haller@phytec.de>
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
2025-08-26 12:49:20 -06:00
Dominik Haller
88a1816a9b board: phytec: common: Add PHYTEC_EEPROM_BUS to Kconfig
Add the option to choose a different bus number than 0 for the i2c eeprom
based som detection.

Signed-off-by: Dominik Haller <d.haller@phytec.de>
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
2025-08-26 12:49:20 -06:00
Tom Rini
25fd8a1bc4 Merge tag 'tpm-next-25082025' of https://source.denx.de/u-boot/custodians/u-boot-tpm into next
CI: https://source.denx.de/u-boot/custodians/u-boot-tpm/-/pipelines/27461

Tom removed an unused TPM driver and fixed a few prints to include
the 'z' prefix for size_t declaratiuons. Andrew fixed an unsigned int
comparision against < 0 in the tpm infineon driver.
2025-08-26 11:25:11 -06:00
Venkatesh Yadav Abbarapu
a51b7dfc6f ufs: amd-versal2: Configure RMMI and M-PHY registers for HS mode
Configure RMMI and M-PHY registers for HS mode required for selection of
bit rate series A or B. If it is not a calibrated part, then switch back
to SLOWAUTO_MODE and skip all these configurations.
Implemented below sequence as per the DWC RMMI databook.
1. Override RMMI CBRATESEL with the desired rate.
2. Set TX_CFGUPDT_0 to 1'b1 for one TX_CFGCLK_0 cycle.
3. Override PHY rx_req to 1, then poll on PHY rx_ack register till it
goes 1(both lanes).
4. Override PHY rx_req to 0, then poll on PHY rx_ack register till it
goes 0(both lanes).
5. Remove PHY rx_req override(both lanes).
6. Start the LS PMC.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250724044402.260149-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2025-08-26 07:30:10 +02:00
Michal Simek
029f26eb5f CI: Wire mbv32 combinations
After upgrading to QEMU 10 by commit 1d782a3f22 ("Docker, CI: Update to
latest Ubuntu and Dockerfile") let's wire mbv32 which is the part of QEMU
to have it under regression.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/02e5c14552b05200ece94136db0077cbdd47738c.1753945577.git.michal.simek@amd.com
2025-08-26 07:30:09 +02:00
Michal Simek
25801ef2d4 dm: core: Mark root_info as const
root_info driver structure is not changing that's why mark them as const
which ensure that structure will be moved from .data section to .rodata
section.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/18d92a93a9863ed0452e82a1f8e0ff9205adb4f9.1753444878.git.michal.simek@amd.com
2025-08-26 07:30:09 +02:00
Michal Simek
4b2679efc5 mailbox: zynqmp-ipi: Mark zynqmp_ipi_dest_mbox_ops as const
Operations are not changing that's why mark them as const which ensure that
structure will be moved from .data section to .rodata section.
Also mark them as static because they are not used out of this file.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/b7e5dc8841f6e904a7365f2ed45248609c007ddd.1753444878.git.michal.simek@amd.com
2025-08-26 07:30:09 +02:00
Michal Simek
6d491e8913 clk: zynqmp: Mark zynqmp_clk_ops as const
Operations are not changing that's why mark them as const which ensure that
structure will be moved from .data section to .rodata section.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/92eb9e90189d8b96246966633478662076da7185.1753444878.git.michal.simek@amd.com
2025-08-26 07:30:09 +02:00
Michal Simek
3a85a27e34 serial: uartlite: Add support for OF_PLATDATA
The first change is to list DM_DRIVER_ALIAS for compatible string to be
able to match the driver. Only xps one is listed because opb one is likely
unused for quite a long time.

The second change is to add dtplat structure to plat data and fill register
base in probe.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/b494dbad529e919d33977b8ea6e6dbcd14e78907.1753261604.git.michal.simek@amd.com
2025-08-26 07:30:09 +02:00
Michal Simek
d0e8a208f6 serial: uartlite: Use private data instead of platform
plat data should be used only in probe or of_to_plat to fill it information
from DT. Then in probe platform data should be stored in private structure
which should be used by the other driver functions.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/8d32af596f80a2220d9f5d7fb98476e6d2b5f303.1753261604.git.michal.simek@amd.com
2025-08-26 07:30:09 +02:00
Michal Simek
1fa3409329 xilinx: Make XILINX_OF_BOARD_DTB_ADDR depending on OF_BOARD only
board_fdt_blob_setup() is guarded by OF_BOARD already that's why make no
sense to depend also on OF_SEPARATE.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/063b2e618afb05a32d66218f3631a5f23b30ea3e.1753172103.git.michal.simek@amd.com
2025-08-26 07:30:09 +02:00
Tom Rini
fceb37d802 Merge tag 'v2025.10-rc3' into next
Prepare v2025.10-rc3
2025-08-25 13:28:49 -06:00
Andrew Goodbody
73b23838c4 tpm: tis_infineon: Cannot test unsigned for being negative
tpm_tis_i2c_get_burstcount returns a size_t but also returns -EBUSY if
the TPM is surrently busy. As size_t is an unsigned type simply testing
for < 0 will not work so change the test for being equal to -EBUSY which
will work. Also remove the trivial comments.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-08-25 13:04:21 +03:00
Tom Rini
83b1c7fd71 tpm: tpm_tis_infineon: Make use of 'z' for printing size_t
When printing the contents of an size_t variable we need to use z prefix
to the format character in order to get the correct format type
depending on 32 or 64bit-ness.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-08-25 13:04:21 +03:00
Tom Rini
80afd60d9c tpm: cr50_i2c: Make use of 'z' for printing size_t
When printing the contents of an size_t variable we need to use z prefix
to the format character in order to get the correct format type
depending on 32 or 64bit-ness.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-08-25 13:04:21 +03:00
Tom Rini
5727df8750 tpm: tpm_tis_st33zp24: Remove unused drivers
The tpm_tis_st33zp24_i2c and tpm_tis_st33zp24_spi drivers are unused.
Remove them.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-08-25 13:04:21 +03:00
Rasmus Villemoes
91595c96a5 i2c: omap24xx_i2c: remove unused members of struct omap_i2c
The clk and clk_id members of struct omap_i2c are not used anywhere,
and AFAICT never have been.

Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
Reviewed-by: Aniket Limaye <a-limaye@ti.com>
2025-08-22 09:26:45 -06:00
Fabio Estevam
51214ffcc5 qemu_arm: Select CONFIG_SYS_EARLY_PCI_INIT
Select CONFIG_SYS_EARLY_PCI_INIT so that eMMC emulation can
work.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Tested-by: Jan Kiszka <jan.kiszka@siemens.com>
2025-08-21 13:27:59 -06:00
Fabio Estevam
0b0641470b Kconfig: Convert SYS_EARLY_PCI_INIT to Kconfig
The CONFIG_SYS_EARLY_PCI_INIT symbol is currently not supported
by Kconfig.

Make it a Kconfig symbol so that users could select it via defconfig.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2025-08-21 13:27:57 -06:00
Anshul Dalal
2792cbf5d2 remoteproc: k3: update compatible for am654 syscon
The existing compatible name for U-Boot's k3 system controller driver
i.e "ti,am625-system-controller" has been added to linux[1] device-tree.
This compatible in kernel is meant for configuring the Control Module
registers (CTRL_MMR0).

However in U-Boot, the matching driver was being used to load the system
firmware on the secure M-cores by the R5 SPL and therefore must be
updated to a different compatible to avoid conflicts.

Therefore, this patch renames all references of the compatible to
"ti,am654-tisci-rproc-r5". The "-r5" is appended so as to avoid any
future conflicts since r5 specific compatibles should only be useful for
U-Boot.

[1]: 5959618631fe ("dt-bindings: mfd: ti,j721e-system-controller: Add compatible string for AM654")
     https://lore.kernel.org/r/20250421214620.3770172-2-afd@ti.com

Signed-off-by: Anshul Dalal <anshuld@ti.com>
2025-08-21 13:27:53 -06:00
Philip Molloy
55014ce40e mach-sc5xx: generate U-Boot proper in ADI ldr format
Generating an ldr boot stream containing U-Boot Proper was never added
to U-Boot because it is done by the ADI Yocto layer. Add it to U-Boot to
support projects that do not use that layer.

Signed-off-by: Philip Molloy <philip.molloy@analog.com>
2025-08-21 13:27:46 -06:00
Hari Nagalla
1564282912 remoteproc: k3-r5: Add support for single cpu mode
Add early boot support for AM64 single cpu mode configuration.
In single CPU mode the 2nd core of the R5F cluster can't be used or
unavailable.

Signed-off-by: Hari Nagalla <hnagalla@ti.com>
2025-08-21 10:02:52 -06:00
John Ma
29ce50acbb board: phytec: common: k3: Making setup_mac_from_eeprom optional
Making the setup_mac_from_eeprom optional for boards without
CONFIG_PHYTEC_SOM_DETECTION_BLOCKS.

Signed-off-by: John Ma <jma@phytec.com>
Reviewed-by: Wadim Egorov <w.egorov@phytec.de>
2025-08-21 10:02:49 -06:00
Leo Yu-Chi Liang
18d0cee4e0 common: spl: fix compilation warning
Explicitly specify the type by replacing macro with variable
to fix the possible compilation warning.

Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-08-21 10:02:45 -06:00
Maxim Kochetkov
e4507f4a0a serial-uclass: set GD_FLG_SERIAL_READY only when cur_serial_dev is assigned
serial_find_console_or_panic() may left cur_serial_dev unassigned if
REQUIRE_SERIAL_CONSOLE is not set. Setting GD_FLG_SERIAL_READY in
this situation confuses serial console code. It tries to use
unassigned driver instead of debug port and stops printing.
So check cur_serial_dev before setting GD_FLG_SERIAL_READY to allow
console to keep printing via debug port.

Signed-off-by: Maxim Kochetkov <fido_max@inbox.ru>
2025-08-21 10:02:43 -06:00
Andrew Goodbody
2b751d42c3 sound: maxim_codec: Fix coding mistake
In maxim_i2c_read the code mistakenly just returned the return value
from dm_i2c_read leaving the following code unreachable. Instead assign
ret to be the return value from dm_i2c_read so that the following code
can operate as expected.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-08-21 10:02:40 -06:00
Tom Rini
b436af0641 Merge patch series "env: fat: Add support for NVME"
This series from Fabio Estevam <festevam@gmail.com> adds support for
having the environment be found on an NVMe device that contains a FAT
filesystem.

Link: https://lore.kernel.org/r/20250812174612.1159634-1-festevam@gmail.com
2025-08-20 15:05:31 -06:00
Fabio Estevam
82444e3ecd env: fat: Standardize the interface type check
Make the interface type check consistent among the other interface types
by checking it agains the ifname string.

The ifname string contains the string returned by env_fat_get_intf(), which
returns the CONFIG_ENV_FAT_INTERFACE value.

No functional change.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
2025-08-20 15:05:31 -06:00
Fabio Estevam
7b21bf0860 env: ext4: Add support for NVME
Add support for retrieving the EXT4 environment from an NVME device, the
same way it can be retrieved from MMC, SCSI, or VIRTIO.

To use the EXT4 environment from an NVME device, pass
CONFIG_ENV_EXT4_INTERFACE="nvme" in the defconfig.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
2025-08-20 15:05:31 -06:00
Fabio Estevam
afbed1ba2f env: fat: Add support for NVME
Add support for retrieving the FAT environment from an NVME device, the
same way it can be retrieved from MMC, SCSI, or VIRTIO.

To use the FAT environment from an NVME device, pass
CONFIG_ENV_FAT_INTERFACE="nvme" in the defconfig.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
2025-08-20 15:05:31 -06:00
Tom Rini
0572f7cad1 Merge patch series "Add support for Ethernet boot"
Chintan Vankar <c-vankar@ti.com> says:

This series adds bind method for CPSW to avoid explicit probing, removes
explicit probing of CPSW, adds support for Ethernet boot on SK-AM68,
SK-AM62P-LP, J722S, SK-AM69.

Link: https://lore.kernel.org/r/20250731075956.605474-1-c-vankar@ti.com
2025-08-20 11:37:59 -06:00
Chintan Vankar
841d3d06ce configs: am69_sk_a72_ethboot: Add configs to enable Ethernet boot
Add configs required to enable Ethernet boot for SK-AM69.

Signed-off-by: Chintan Vankar <c-vankar@ti.com>
2025-08-20 11:06:19 -06:00
Chintan Vankar
02b2a32771 configs: am69_sk_r5_ethboot: Add configs to enable Ethernet boot in R5SPL
Add configs required to enable Ethernet boot for SK-AM69.

Signed-off-by: Chintan Vankar <c-vankar@ti.com>
2025-08-20 11:06:19 -06:00
Chintan Vankar
721d5c30f5 arm: mach-k3: j784s4_spl: Alias Ethernet boot to CPGMAC
This is required to enable spl_net boot on SK-AM69.

Signed-off-by: Chintan Vankar <c-vankar@ti.com>
2025-08-20 11:06:19 -06:00
Chintan Vankar
8eecd9edb5 arm: mach-k3: j784s4: Update SoC auto-gen data to enable Ethernet boot
Update dev-data and clk-data to include CPSW device which is required to
enable Ethernet boot for SK-AM69.

Signed-off-by: Chintan Vankar <c-vankar@ti.com>
2025-08-20 11:06:19 -06:00
Chintan Vankar
9def2b0fc1 configs: j722s_evm_a53_ethboot: Enable configs required for Ethernet boot
Enable configs required to support Ethernet boot for J722S.

Signed-off-by: Chintan Vankar <c-vankar@ti.com>
2025-08-20 11:06:19 -06:00
Chintan Vankar
d449db6cd7 configs: j722s_evm_r5_ethboot: Add configs to enable Ethernet boot in R5SPL
Add configs to enable Ethernet boot in R5SPL, also disable not required
configs to avoid memory limitation.

Signed-off-by: Chintan Vankar <c-vankar@ti.com>
2025-08-20 11:06:19 -06:00
Chintan Vankar
80b529d877 board: ti: j722s: evm: Enable cache for J722s
Enable cache for J722s to optimize performance of CPU to access data from
memory.

Reviewed-by: Alexander Sverdlin <alexander.sverdlin@siemens.com>
Signed-off-by: Chintan Vankar <c-vankar@ti.com>
2025-08-20 11:06:19 -06:00
Chintan Vankar
a02009f3a8 arm: mach-k3: j722s: Update SoC autogenerated data to enable Ethernet boot
Update dev-data and clk-data to include CPSW device which is required to
enable Ethernet boot.

Signed-off-by: Chintan Vankar <c-vankar@ti.com>
2025-08-20 11:06:19 -06:00
Chintan Vankar
c1f1d28c44 configs: am62px_evm_a53_ethboot: Enable configs required for Ethboot
Enable config options needed to support Ethernet boot on SK-AM62P-LP.

Signed-off-by: Chintan Vankar <c-vankar@ti.com>
2025-08-20 11:06:19 -06:00
Andreas Dannenberg
c8c2da2ab8 configs: am62px_evm_r5_ethboot: Add configs to enable Ethernet boot in R5SPL
Add configs for enabling Ethernet boot in R5SPL, also disable not required
configs to avoid memory limitation.

Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Chintan Vankar <c-vankar@ti.com>
2025-08-20 11:06:19 -06:00
Andreas Dannenberg
3bab8f17fb board: ti: am62px: evm: Enable cache for AM62p
Enable cache for AM62p to optimize performance of CPU to access data from
memory.

Reviewed-by: Alexander Sverdlin <alexander.sverdlin@siemens.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Chintan Vankar <c-vankar@ti.com>
2025-08-20 11:06:19 -06:00
Andreas Dannenberg
6fc2a6a971 arm: mach-k3: am62p: Update SoC auto-gen data to enable Ethernet boot
Update dev-data and clk-data to enable Ethernet boot using CPSW on
SK-AM62P-LP.

Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Chintan Vankar <c-vankar@ti.com>
2025-08-20 11:06:19 -06:00
Chintan Vankar
3325b13d53 configs: am68_sk_a72_ethboot: Enable configs required for Ethernet boot
Enable config options needed to support Ethernet boot on AM68-SK.

Signed-off-by: Chintan Vankar <c-vankar@ti.com>
2025-08-20 11:06:19 -06:00
Chintan Vankar
07774020f7 configs: am68_sk_r5_ethboot: Add configs for enabling Ethernet boot in R5SPL
Add configs for enabling Ethernet boot in R5SPL, also disable not required
configs to avoid memory limitation.

Signed-off-by: Chintan Vankar <c-vankar@ti.com>
2025-08-20 11:06:19 -06:00
Chintan Vankar
333b50d32d net: ti: Kconfig: Enable SPL_SYSCON config for CPSW
TI's Ethernet switch needs system controllers enabled in R5SPL stage while
booting via Ethernet. Enable SPL_SYSCON config for
CONFIG_TI_AM65_CPSW_NUSS.

Reviewed-by: Alexander Sverdlin <alexander.sverdlin@siemens.com>
Signed-off-by: Chintan Vankar <c-vankar@ti.com>
2025-08-20 11:06:18 -06:00
Chintan Vankar
e85b090165 arm: mach-k3: j721s2_spl: Alias Ethernet boot to CPGMAC
This is required to enable spl_net boot on SK-AM68.

Signed-off-by: Chintan Vankar <c-vankar@ti.com>
2025-08-20 11:06:18 -06:00
Chintan Vankar
0b092a2aa8 arm: mach-k3: j721s2: Update SoC auto-gen data to enable Ethernet boot
Update dev-data and clk-data to include CPSW device which is required to
enable Ethernet boot.

Reviewed-by: Bryan Brattlof <bb@ti.com>
Signed-off-by: Chintan Vankar <c-vankar@ti.com>
2025-08-20 11:06:18 -06:00
Chintan Vankar
b4a0702c92 Revert "arm: mach-k3: am62x: am625_init: Probe AM65 CPSW NUSS"
This reverts commit 35bddf8896.

Bind method of "am65_cpsw_nuss" driver will ensure binding of it's child
driver "am65_cpsw_nuss_ports", and there is no need to probe CPSW driver
explicitly.

Signed-off-by: Chintan Vankar <c-vankar@ti.com>
2025-08-20 11:06:18 -06:00
Chintan Vankar
3967d64740 Revert "mach-k3: am642_init: Probe AM65 CPSW NUSS for R5/A53 SPL"
This reverts commit 93c43a8365.

Bind method of "am65_cpsw_nuss" driver will ensure binding of it's child
driver "am65_cpsw_nuss_ports", and there is no need to probe CPSW driver
explicitly.

Signed-off-by: Chintan Vankar <c-vankar@ti.com>
2025-08-20 11:06:18 -06:00
Chintan Vankar
50ededad32 arch: mach-k3: common: Remove explicit probing of CPSW driver
This reverts commit e58d928485.

Bind method of am65_cpsw_nuss driver will ensure binding of it's child
driver am65_cpsw_nuss_ports, and there is no need to call CPSW driver
explicitly. Remove explicit probing of CPSW driver for AM62x.

Signed-off-by: Chintan Vankar <c-vankar@ti.com>
2025-08-20 11:06:18 -06:00
Chintan Vankar
3943531a54 net: ti: am65-cpsw-nuss: Define bind method for CPSW driver
CPSW driver is defined as UCLASS_MISC driver which needs to be probed
explicitly. Define bind method for CPSW driver to scan and bind
ethernet-ports with UCLASS_ETH driver which will eventually probe CPSW
driver and avoid probing CPSW driver explicitly.

Signed-off-by: Chintan Vankar <c-vankar@ti.com>
2025-08-20 11:06:18 -06:00
Tom Rini
1ad89bfe1a Merge patch series "ram: k3-ddrss: Support partial inline ECC"
Neha Malcom Francis <n-francis@ti.com> says:

Currently, the inline ECC implementation enables inline ECC across the
entire DDR space. However this is not always required and a more common
ask is to have only a portion of the DDR protected as enabling ECC
impacts read/write performance metrics.

This series aims to modify the logic to firstly support partial inline
ECC in its' most basic form which works for single controllers. Then it
introduces an algorithm to support multi DDR controllers where
interleaving plays a role. Since interleaving is handled by the MSMC, it
only makes sense to have the MSMC decide the inline ECC ranges for each
DDR.

This series also introduces support for multiple partial regions of inline
ECC however due to complexity only support for single DDR is present now.

WIP: A commandline test case patch for verifying the correct behaviour
of inline ECC including partial case. Was targeted for v2 however a little
tricky to make it a general test case especially for multi-DDR cases, so
have not combined it in this series for now.

Testing:
- Memtester runs for J721S2 and J784S4 platforms with and without ECC
  enablement runs fine.
- Along with patches that add support for the commandline test (see WIP
  note above) J784S4 shows expected behavior for three sets of partial
  inline ECC regions (non-overlapping, and after modifying J784S4 to
  have single DDR instead of multi-DDR):
  https://gist.github.com/nehamalcom/bde7e14e96485e4a188c3af3af6d75d6

Link: https://lore.kernel.org/r/20250812124324.124306-1-n-francis@ti.com
2025-08-19 11:26:39 -06:00
Neha Malcom Francis
0824703fb2 ram: k3-ddrss: Support multiple ECC regions for a single controller
K3 Inline ECC mechanism can support up to 3 regions of inline ECC, add
this support for single controller.

Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
2025-08-19 11:26:20 -06:00
Neha Malcom Francis
d1efbc8d65 ram: k3-ddrss: Add support for partial inline ECC in multi-DDR systems
The existing approach does not account for interleaving in the DDRs when
setting up regions. There is support for MSMC to calculate the regions
for each DDR, so modify k3_ddrss_probe to set the regions accordingly
for multi-DDR systems.

Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
2025-08-19 11:26:20 -06:00
Neha Malcom Francis
c32ac5b3b9 ram: k3-ddrss: Add support for MSMC calculation of DDR inline ECC regions
Add support for calculation of the protected regions for each DDR in
multi-DDR systems. Since MSMC is the parent node of the individual DDRs
as well as responsible for their interleaving, it only makes sense for
MSMC to contain the logic for dividing the regions.

Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
2025-08-19 11:26:20 -06:00
Neha Malcom Francis
2310aac8ae ram: k3-ddrss: Add support for number of controllers under MSMC
In K3 multi-DDR systems, the MSMC is responsible for the interleave
mechanism across all the DDR controllers. Add support for MSMC to obtain
the number of controllers it's responsible for using the DT.

Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
2025-08-19 11:26:20 -06:00
Neha Malcom Francis
3a0793fe9b ram: k3-ddrss: Add CONFIG_K3_MULTI_DDR
As we increase the functionalities that the K3 DDRSS sub-system support,
it is becoming more evident that the same logic cannot apply to both
single as well as multiple DDR controller devices. Add
CONFIG_K3_MULTI_DDR to be used to differentiate between the two.

Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
2025-08-19 11:26:20 -06:00
Neha Malcom Francis
f43f710122 ram: k3-ddrss: Add support for a partial inline ECC region
Instead of defaulting to choosing the entire DDR region when enabling
inline ECC, allow picking of a range within the DDR space using DT to
enable.

It expects such a node within the memory node, in the absence of which
we resort to enabling inline ECC for the entire DDR region:

inline_ecc: protected@9e780000 {
        device_type = "ecc";
        reg = <0x9e780000 0x0080000>;
        bootph-all;
};

Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
2025-08-19 11:26:19 -06:00
Neha Malcom Francis
1c70e33b0a ram: k3-ddrss: Add comment about ecc_reserved_space
The reserved space needed for storing the parity remains the same no
matter the size of the region that is being protected. Add this as a
comment for better code understanding.

Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
2025-08-19 11:26:19 -06:00
Neha Malcom Francis
e511c651f6 ram: k3-ddrss: s/K3_DDRSS_MAX_ECC_REGIONS/K3_DDRSS_MAX_ECC_REG
To prevent checkpatch warning once we start using this macro more
frequently, shorten the length of it. While at it, also move the
structure k3_ddrss_ecc_region above k3_msmc so that future patches can
have it as a member of k3_msmc.

Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
2025-08-19 11:26:19 -06:00
Neha Malcom Francis
520d9c2521 ram: k3-ddrss: Use DDR address instead of system address for ecc_regions
Let ecc_regions[x].start reflect the start of the ECC region in terms of
DDR addressing rather than system addressing. This will make it easier
to extend the usage of the same ecc_regions structure for multi-DDR
systems as well.

Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
2025-08-19 11:26:19 -06:00
Tom Rini
5b2c3a3ea1 Merge patch series "soc: ti: k3-navss-ringacc: Fix Smatch reported issues"
Andrew Goodbody <andrew.goodbody@linaro.org> says:

Smatch reported issues including a derference of a pointer before its
NULL check and the use of an uninitialised variable.

Link: https://lore.kernel.org/r/20250812-k3-navss-v1-0-a88f7db58998@linaro.org
2025-08-19 11:26:16 -06:00
Andrew Goodbody
13ca68b104 soc: ti: k3-navss-ringacc: Do not use uninitialised variable
In k3_nav_ringacc_probe_dt there can be no error code returned from
dev_read_u32_default so ret is not assigned to and should not be used.
Remove the use of ret from the dev_err call as it is unitialised.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-08-19 11:26:07 -06:00
Andrew Goodbody
b90927bd0d soc: ti: k3-navss-ringacc: NULL check before dereference
Move the first dereference of ring to after the NULL check has occurred.
This will prevent any possible dereference of NULL.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-08-19 11:26:07 -06:00
Tom Rini
cf11b98f13 Merge patch series "remoteproc: k3: Fix two Smatch issue reports"
Andrew Goodbody <andrew.goodbody@linaro.org> says:

Smatch reported two issues, firstly attempting to compare a u8 to a 16
bit macro and secondly a potentially uninitialised variable.

Link: https://lore.kernel.org/r/20250808-remoteproc_tik3-v1-0-f7dae0b177b2@linaro.org
2025-08-19 11:26:03 -06:00
Andrew Goodbody
c9cd480b5c remoteproc: k3-r5: Ensure ret is initialised
In k3_r5f_split_reset and k3_r5f_unprepare ret may not have been
assigned to before the code reaches the return ret at the function exit.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-08-19 11:25:56 -06:00
Andrew Goodbody
f780ad4be9 remoteproc: ti_k3_arm64: Cannot set or compare u8 to 16bits
In the struct ti_sci_proc the fields proc_id and host_id are declared as
u8 so cannot be set to nor compared with a macro defined with a value
using 16 bits. Change the macro to only use 8 bits to make the code work
as expected.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-08-19 11:25:56 -06:00
Tom Rini
66ff673a8e sandbox: Add generic asm/atomic.h
In order to compile code that uses <asm/atomic.h> on sandbox, we must
provide this header. RISC-V shows us today how to do so with the generic
header implementation, so copy that.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-08-19 11:25:28 -06:00
Tom Rini
58998fed9e sandbox: Improve dummy local_irq_save implementation
Normally, local_save_flags is used as part of the local_irq_* macros, so
remove that as it's unused. Make local_irq_save do something to the
passed variable so that it won't trigger unused variable warnings later.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-08-19 11:25:28 -06:00
Andrew Goodbody
da938a4254 sound: rt5677: Cannot test unsigned for being negative
In rt5677_bic_or the call to rt5677_i2c_read returns an int so old
should also be an int to receive that value and then be able to test it
for being negative which would indicate an error.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-08-19 11:25:25 -06:00
Ilias Apalodimas
544bf0aa59 tools: aisimage: Make aisimage_check_params() static
We are trying to enable -Wmissing-prototypes and this functiion is only
used locally. Mark it as static.

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-08-19 11:25:23 -06:00
Ilias Apalodimas
6139d5f252 tools: fit_info: Make usage() static
The function is only used locally so declare it as static.

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-08-19 11:25:20 -06:00
Andrew Goodbody
e416d16572 pinctrl: nexell: Cannot test unsigned to be negative
In s5pxx18_pinctrl_set_state testing count to be negative will always
fail as count is unsigned despite receiving the return value of a
function that returns an int. Change count and idx to be of type int to
allow the test to work as expected and remove the need for any implicit
casts. Also change pin to be u32 which is what all called functions
expect.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-08-19 11:25:10 -06:00
Tom Rini
fedbb7a338 Merge patch series "test/py: Correctly restore the DT after capsule tests"
This series from Ilias Apalodimas <ilias.apalodimas@linaro.org> fixes a
number of issues with running the EFI capsule tests in CI.

Link: https://lore.kernel.org/r/20250807080819.1058411-1-ilias.apalodimas@linaro.org
2025-08-18 16:42:13 -06:00
Ilias Apalodimas
fc2686d2a8 test/py: Fix capsule update tests
Capsule updates tests have been skipped since
commit 659f97eb1f ("scripts/Makefile.lib: EFI: Use capsule CRT instead of ESL file")

Remove that check since it's not needed anymore and re-enable the tests.

Fixes: 659f97eb1f ("scripts/Makefile.lib: EFI: Use capsule CRT instead of ESL file")
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-08-18 16:42:04 -06:00
Ilias Apalodimas
fa2a2e20d0 test/py: Fix race conditions on EFI capsule tests
efi_capsule_data() is called in each of the EFI tests to create and
setup the files we need. However, it also recreates the spi.bin file
that holds the SPI flash contents we rely on for the test validation.

This leads to weird errors since reading from the flash returns 0,
instead of the expected value if the file has been recreated.

Always restart our sandbox instance if the files are recreated.

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-08-18 16:42:04 -06:00
Ilias Apalodimas
5096f81bda test/py: Read from the correct offset when initializing capsules
The current code writes values to a flash offset defined by a function
argument. However, when reading it back we always read from a static
offset. Adjust the reads to use the correct offset.

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2025-08-18 16:42:04 -06:00
Ilias Apalodimas
b0465eb88f test/py: Correctly restore the DT after capsule tests
Some capsule tests are changing the sandbox DT to test various features,
e.g authenticated capsule updates, versioning support etc. However, no one
restores the original DT and the CI pops errors looking like

/u-boot
Bloblist at 100 not found (err=-2)
Failed to find FDT file '/tmp/sandbox/persistent-data/scratch/EFI/CapsuleTestData/test_ver.dtb'
initcall_run_f(): initcall fdtdec_setup() failed

if sandbox is restarted.

So let's restore the proper DT after done with the capsule testing.

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2025-08-18 16:42:04 -06:00
Tom Rini
bb21c0b8d8 Merge patch series "modify npcm7xx/8xx feature and bug fixed"
Jim Liu <jim.t90615@gmail.com> says:

modify npcm7xx/8xx feature and bug fixed

Link: https://lore.kernel.org/r/20250807053224.2169557-1-JJLIU0@nuvoton.com
2025-08-18 16:41:50 -06:00
Jim Liu
58fa3b5159 configs: npcm: remove CONFIG_SYS_SKIP_UART_INIT
Set the uart clock frequency according to dts by default.
If CONFIG_SYS_SKIP_UART_INIT is not enabled, no need to
do board_set_console to change the console bootarg.

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2025-08-18 16:40:24 -06:00
Jim Liu
9878805816 misc: npcm_host_intf: Disable pending KCS/BPC interrupts
If there is an unhandled KCS/BPC pending interrupt after reboot,
the KCS/BPC Linux driver may trigger interrupts immediately upon
registering the irq. However, since the driver is not yet initialized
to handle them, this can lead to unexpected behavior.

To prevent this, disable KCS/BPC interrupts in u-boot to avoid pending
interrupts from being raised before the Linux driver is fully initialized.

Signed-off-by: Stanley Chu <yschu@nuvoton.com>
Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2025-08-18 16:40:24 -06:00
Jim Liu
121927e37b misc: npcm_host_intf: Add Arbel eSPI workaround
Enabling an eSPI channel(e.g. Peripheral Channel) during
an eSPI transaction might cause the BMC eSPI module to
transition to a wrong state and therefore respond with
FATAL_ERROR on incoming transaction.
Add workaround to avoid the module getting into the wrong
state.

Signed-off-by: Stanley Chu <yschu@nuvoton.com>
Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2025-08-18 16:40:23 -06:00
Jim Liu
59a1c28755 arm: dts: nuvoton: Change timer node
npcm_timer driver is changed to use SECCNT counter.

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2025-08-18 16:40:23 -06:00
Stanley Chu
3c632fc090 i2c: npcm: fix consecutive dm_i2c_read/write error
When doing a dm_i2c_read followed by a dm_i2c_write, the subsequent
transaction may get npcm_i2c_check_sda error because the module is
still busy in STOP condition in previous dm_i2c_read.
Always check and wait for module to be out of busy before starting
an i2c transaction.

Signed-off-by: Stanley Chu <yschu@nuvoton.com>
Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2025-08-18 16:40:23 -06:00
Stanley Chu
ad3a33e577 pinctrl: npcm8xx: add support for setting VCD input source
Add pinmux for the VCD input to use the HSYNC signal.

Signed-off-by: Stanley Chu <yschu@nuvoton.com>
Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2025-08-18 16:40:23 -06:00
Stanley Chu
6e212f32aa arm: dts: npcm8xx: add pinmux for VCD input
Add pinmux to select the HSYNC signal as the VCD input.

Signed-off-by: Stanley Chu <yschu@nuvoton.com>
Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2025-08-18 16:40:23 -06:00
Andrew Goodbody
4a2f360bd2 pinctrl: stmfx: Remove duplicated code
In stmfx_read_reg there is duplicated code to detect ret < 0 and return
ret if so. Remove one version of it.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-08-15 14:17:30 -06:00
Andrew Goodbody
64204ab107 pinctrl: single: Remove unreachable code
In single_read there is a switch block with a default label. All cases
in the switch block, including the default, return directly. So any code
following the switch block is unreachable. Remove the unreachable code.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-08-15 14:17:30 -06:00
Andrew Goodbody
460db5b44d ram: k3-ddrss: Use logical and not bitwise
The test for the interrupt LPDDR4_INTR_BIST_DONE is using a bitwise and
but the test is simple logic so use the more appropriate logical and.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-08-15 14:17:30 -06:00
Andrew Goodbody
fc96c1de5b phy: ti: j721e-wiz: Set error code before goto
In j721e_wiz_probe the test for too many lanes jumps to the error exit
path without assigning an error code which could lead to calling code
silently ignoring the failure. Set the error code.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-08-15 14:17:30 -06:00
Andrew Goodbody
26d9bd1ccd phy: keystone-usb: Do not negate return code
In keystone_usb_init the return code from psc_enable_module should be
returned as is rather than being negated.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-08-15 14:17:30 -06:00
Tom Rini
3f486367bc timer: Tighten some timer driver dependencies
A few timer drivers cannot build without access to some platform
specific header files. Express those requirements in Kconfig as well.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-08-15 14:17:30 -06:00
Tom Rini
cb76b20839 timer: fttmr010_timer: Remove unused driver
This driver is unused. Remove it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-08-15 14:17:30 -06:00
Andrew Goodbody
2a61c56dea net: ti: icssg: Remove impossible test
port_id is an unsigned variable so cannot be negative. Remove the test
checking for port_id being less than 0.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-08-15 13:00:35 -06:00
Andrew Goodbody
1edd1fd539 net: ti: am65-cpsw-nuss: Initialise ret
In am65_cpsw_phy_init it is not certain that ret will be assigned to
before it reaches the 'return ret' statement. Initialise ret to ensure
that ret is valid.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-08-15 13:00:03 -06:00
Andrew Goodbody
145a6f447e net: phy: cortina: Ensure memory allocated is freed
In cs4340_upload_firmware a buffer is allocated with malloc but this is
never freed. The pointer to this buffer, addr, is not even kept
unchanged. But in some cases addr is not a buffer allocated by malloc.
Introduce the use of another pointer to keep track of the buffer and to
know if it needs to be freed.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-08-15 12:59:50 -06:00
Tom Rini
c39a8001ca ram: Tighten some ram driver dependencies
A few ram drivers cannot build without access to some platform
specific header files. Express those requirements in Kconfig as well.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-08-14 11:04:25 -06:00
Tom Rini
546be69f05 serial: linflexuart: Remove unused driver
This driver is unused. Remove it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-08-14 11:03:12 -06:00
Tom Rini
37f0a8b8cb serial: Tighten some serial driver dependencies
A few serial drivers cannot build without access to some platform
specific header files. Express those requirements in Kconfig as well.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-08-14 11:03:09 -06:00
Tom Rini
91122ea8f0 rtc: pl031: Correct function type of pl031_write_reg
When calling writel we do not have a return value to check or pass
along. This function should therefore be void and not return what writel
gives us.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-08-14 11:03:05 -06:00
Tom Rini
d7daa9274b rtc: mc146818: Fix building on more architectures
This driver makes calls to in8/out8(). On PowerPC these are separate and
real calls but elsewhere they are able to simply be wrappers to
inb/outb. Rework this logic to be able to build this driver on more
platforms.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-08-14 11:03:03 -06:00
Tom Rini
b86ace06d3 rtc: Tighten some rtc driver dependencies
The Marvell RTC rtc driver cannot build without access to some
platform specific header files. Express that requirements in Kconfig as
well.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-08-14 11:02:58 -06:00
Tom Rini
38931172ed sysreset: Tighten some sysreset driver dependencies
The MPC83xx sysreset driver cannot build without access to some
architecture specific header files. Express that requirements in Kconfig
as well.

Reviewed-by: Peter Robinson <pbrobinson@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-08-14 10:59:35 -06:00
Tom Rini
8b0eac68e5 sound: Tighten some sound driver dependencies
A few sound drivers cannot build without access to some platform
specific header files. Express those requirements in Kconfig as well.

Reviewed-by: Peter Robinson <pbrobinson@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-08-14 10:59:19 -06:00
Tom Rini
01bc65a0e9 soc: Tighten some soc driver dependencies
The Qualcomm Snapdragon "SoC" driver cannot build without access to some
ARM64 specific functionality. Express that requirements in Kconfig as
well.

Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-08-14 10:59:16 -06:00
Tom Rini
548ae9d1a5 remoteproc: Tighten some remoteproc driver dependencies
The TI IPU remoteproc driver cannot build without access to some
platform specific header files. Express that requirements in Kconfig as
well.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-08-14 10:59:12 -06:00
Tom Rini
0ae7725e87 reset: Tighten some reset driver dependencies
A few reset drivers cannot build without access to some platform
specific header files. Express those requirements in Kconfig as well.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-08-14 10:59:09 -06:00
Tom Rini
00ad9ed4a7 pwm: pwm-aspeed: Add missing <linux/log2.h> to pwm-aspeed.c
This driver references the logarithmic macros while relying on an
indirection inclusion of <linux/log2.h>. Add the missing include
directly.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-08-14 10:59:05 -06:00
Tom Rini
678be99d56 pwm: Tighten some pwm driver dependencies
A few pwm drivers cannot build without access to some platform
specific header files. Express those requirements in Kconfig as well.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-08-14 10:59:05 -06:00
Tom Rini
e7a95ee2b5 pinctrl: Tighten some pinctrl driver dependencies
A few pinctrl drivers cannot build without access to some platform
specific header files. Express those requirements in Kconfig as well.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-08-14 10:58:48 -06:00
Tom Rini
e2837ecddc sm: Rework the Kconfig logic here
The symbol "SM" is a library symbol and should not be prompted for. It
should be selected by the drivers that use it. In this case we need to
add a SANDBOX_SM symbol for the sandbox driver. The meson SM driver
cannot build on other platforms, so add the appropriate dependency.

Reviewed-by: Peter Robinson <pbrobinson@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-08-14 10:58:46 -06:00
Tom Rini
d68db76b95 sandbox: Add an additional dummy sync macro
There are some drivers which call a "dmb" for a type of sync. Add that
as well to sandbox.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-08-14 10:58:43 -06:00
Andrew Goodbody
4266b8a283 net: e1000: Free temporary buffer on exit
In do_e1000_spi_checksum a temporary buffer is allocated but never
freed. Add code to free on exit. Also refactor the code to make the exit
code common.

This issue found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-08-14 10:58:40 -06:00
Quentin Schulz
28a87c8e9b rockchip: add /chosen/bootsource to U-Boot proper DT
U-Boot typically can be loaded from different storage media, such as
eMMC, SD card, SPI flash, but also from non-persistent media such as USB
(via proprietary protocols loading directly into SRAM, or fastboot, DFU,
 etc..), JTAG, ...

This information is usually reported by the BootROM via some proprietary
mechanism (some specific address in registers/DRAM for example). For
Rockchip, that information is stored in a register
(BROM_BOOTSOURCE_ID_ADDR).

While we already have the information about which medium was used to
load U-Boot proper from SPL (via /chosen/u-boot,spl-boot-device), this
new property represents the medium used to load U-Boot first phase
(depending on configuration, can be VPL/TPL/SPL) which absolutely may
differ from the one used to load U-Boot proper!

It would be useful to know which medium was used to load the first phase
of U-Boot, for example to check fallback mechanisms (proper loaded from
a different medium than first phase) are actually working.

For now, this only applies to Rockchip's U-Boot proper DT but could be
applied to the kernel's as well and possibly for other architectures or
vendors.

Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
2025-08-13 12:42:05 -06:00
Neil Armstrong
7807ed9213 pinctrl: sx150x: reformat and fixup Copyright header
The Linux pinctrl-sx150 was originally written as a GPIO driver
and fully rewritten by me as a Pinctrl driver and extended by
other contributors.

Fixup the Copyright header style and correctly report the
Copyright headers from the Linux driver.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2025-08-11 15:11:22 -06:00
Chali Anis
814ddd7824 pinctrl: gpio: sx150x: fix compilation warnings.
Fixes: 5451504256 ("pinctrl: gpio: sx150x: add Semtech SX150x I2C GPIO expander and pinctrl driver")

Signed-off-by: Chali Anis <chalianis1@gmail.com>
2025-08-11 15:11:22 -06:00
Shiji Yang
d78130ac5a arm: dts: mediatek: remove useless SPI property must_tx
This property is not documented. And the "mediatek,ipm-spi" SPI
driver doesn't check it.

Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
2025-08-11 15:11:22 -06:00
Andrew Goodbody
916f4337d1 gpio: dwapb_gpio: Using wrong function to free memory
In gpio_dwapb_bind plat is used to reference memory allocated by
devm_kcalloc but it is attempted to be freed using kfree. Instead free
this memory using the correct devm_kfree function.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Acked-by: Quentin Schulz <quentin.schulz@cherry.de>
2025-08-11 15:11:22 -06:00
Andrew Goodbody
bd644d9613 clk: cdce9xx: Fix use of dev_read_u32_default
The function dev_read_u32_default does not return an error and the
variable 'val' is unsigned so testing for >= 0 will always be true. It
looks like the code was attempting to return -1 if xtal-load-pf was not
present but that cannot work. Instead use dev_read_u32 which returns an
error code separately from writing the value into the passed pointer.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Fixes: 260777fc23 ("clk: cdce9xx: add support for cdce9xx clock  synthesizer")
Acked-by: Quentin Schulz <quentin.schulz@cherry.de>
2025-08-11 15:11:22 -06:00
Tom Rini
493c3da3ac sandbox: Add more dummy functions to mimic other architectures
This adds more common functions found on other architectures that will
allow for more compile-testing of drivers. These are either dummy
functions as we do not need them or mappings to existing functions,
similar to how other architectures handle it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-08-11 15:11:19 -06:00
Tom Rini
26f857f1e3 arm: bcm235xx: Remove this SoC
As there are no platforms for this SoC, remove the code.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-08-11 15:00:33 -06:00
Tom Rini
f057260351 nvme: Tighten requirements on NVME_APPLE driver
This driver requires Apple rtkit headers in order to build.  Express
that requirement in Kconfig as well.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-08-11 15:00:30 -06:00
Tom Rini
cb8e572708 pci: Tighten some PCI controller dependencies
A large number of PCI controllers cannot build without access to some
platform specific header files. Express those requirements in Kconfig as
well.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-08-11 15:00:28 -06:00
Tom Rini
5bad0bc4f7 pci: Add missing <linux/sizes.h> to pcie_iproc.c
This driver references the SZ_ macros while relying on an indirection
inclusion of <linux/sizes.h>. Add the missing include directly.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-08-11 15:00:23 -06:00
Tom Rini
92c54936fe Merge patch series "arch: arm: dts: k3-am625-phyboard-lyra: Disable unused watchdogs in U-Boot"
This series from Wadim Egorov <w.egorov@phytec.de> cleans up how
watchdogs are handled on some phytec TI K3 platforms.

Link: https://lore.kernel.org/r/20250730154217.1116751-1-w.egorov@phytec.de
2025-08-11 14:54:10 -06:00
Wadim Egorov
9de098a9f8 board: phytec: phycore-am64x: Add watchdog start to bootcmd
Allows run-time control over watchdog auto-start and the timeout via
setting the environment variable watchdog_timeout_ms. A value of zero
means "do not start". Use CONFIG_WATCHDOG_TIMEOUT_MSECS as initial value.
Users can enable the watchdog to monitor the boot process until userspace
or OS takes over to serve the watchdog.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
2025-08-11 14:53:56 -06:00
Wadim Egorov
e8eab15d14 include: env: phytec: k3: Add deprecation warning to legacy boot flow
We switched towards standard boot with still keeping a fallback
using legacy boot command alive. Add a deprecation warning to
make it more clear that we will remove it in future versions.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
2025-08-11 14:53:56 -06:00
Wadim Egorov
d27b7a1c77 board: phytec: phycore-am62x: Add watchdog start to bootcmd
Allows run-time control over watchdog auto-start and the timeout via
setting the environment variable watchdog_timeout_ms. A value of zero
means "do not start". Use CONFIG_WATCHDOG_TIMEOUT_MSECS as initial value.
Users can enable the watchdog to monitor the boot process until userspace
or OS takes over to serve the watchdog.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
2025-08-11 14:53:56 -06:00
Wadim Egorov
cc6291e3b4 board: phytec: phycore-am62ax: Add watchdog start to bootcmd
Allows run-time control over watchdog auto-start and the timeout via
setting the environment variable watchdog_timeout_ms. A value of zero
means "do not start". Use CONFIG_WATCHDOG_TIMEOUT_MSECS as initial value.
Users can enable the watchdog to monitor the boot process until userspace
or OS takes over to serve the watchdog.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
2025-08-11 14:53:56 -06:00
Wadim Egorov
dcc85e9aba arch: arm: dts: k3-am642-phyboard-electra: Disable unused watchdogs in U-Boot
The watchdog driver probes all available watchdog devices.
This causes SMP boot errors when bringing up secondary CPUs.
In our setup, only a single watchdog is needed to monitor the
boot process until userspace or the OS takes over. Disable all
unnecessary watchdog devices in U-Boot to avoid conflicts
during CPU bring-up.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
2025-08-11 14:53:56 -06:00
Wadim Egorov
dfd185939d arch: arm: dts: k3-am62a7-phyboard-lyra: Disable unused watchdogs in U-Boot
The watchdog driver probes all available watchdog devices.
This causes SMP boot errors when bringing up secondary CPUs.
In our setup, only a single watchdog is needed to monitor the
boot process until userspace or the OS takes over. Disable all
unnecessary watchdog devices in U-Boot to avoid conflicts
during CPU bring-up.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
2025-08-11 14:53:56 -06:00
Wadim Egorov
b17c594ac4 arch: arm: dts: k3-am625-phyboard-lyra: Disable unused watchdogs in U-Boot
The watchdog driver probes all available watchdog devices.
This causes SMP boot errors when bringing up secondary CPUs.
In our setup, only a single watchdog is needed to monitor the
boot process until userspace or the OS takes over. Disable all
unnecessary watchdog devices in U-Boot to avoid conflicts
during CPU bring-up.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
2025-08-11 14:53:56 -06:00
2359 changed files with 92365 additions and 35202 deletions

View File

@@ -254,15 +254,15 @@ stages:
git clone --depth=1 https://github.com/u-boot/u-boot-test-hooks /tmp/uboot-test-hooks
# qemu_arm64_lwip_defconfig is the same as qemu_arm64 but with NET_LWIP enabled.
# The test config and the boardenv file from qemu_arm64 can be re-used so create symlinks
ln -s conf.qemu_arm64_na /tmp/uboot-test-hooks/bin/travis-ci/conf.qemu_arm64_lwip_na
ln -s conf.qemu_arm64 /tmp/uboot-test-hooks/bin/travis-ci/conf.qemu_arm64_lwip_na
ln -s u_boot_boardenv_qemu_arm64_na.py /tmp/uboot-test-hooks/py/travis-ci/u_boot_boardenv_qemu_arm64_lwip_na.py
ln -s travis-ci /tmp/uboot-test-hooks/bin/\`hostname\`
ln -s travis-ci /tmp/uboot-test-hooks/py/\`hostname\`
if [[ "\${TEST_PY_BD}" == "qemu-riscv32_spl" ]]; then
if [[ "\${TEST_PY_BD}" == "qemu-riscv32_spl" ]] || [[ "\${TEST_PY_BD}" == "xilinx_mbv32_smode" ]]; then
wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.3.1/opensbi-1.3.1-rv-bin.tar.xz | tar -C /tmp -xJ;
export OPENSBI=/tmp/opensbi-1.3.1-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin;
fi
if [[ "\${TEST_PY_BD}" == "qemu-riscv64_spl" ]] || [[ "\${TEST_PY_BD}" == "sifive_unleashed" ]]; then
if [[ "\${TEST_PY_BD}" == "qemu-riscv64_spl" ]] || [[ "\${TEST_PY_BD}" == "sifive_unleashed" ]] || [[ "\${TEST_PY_BD}" == "xilinx_mbv64_smode" ]]; then
wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.3.1/opensbi-1.3.1-rv-bin.tar.xz | tar -C /tmp -xJ;
export OPENSBI=/tmp/opensbi-1.3.1-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin;
fi
@@ -540,6 +540,22 @@ stages:
TEST_PY_BD: "sifive_unleashed"
TEST_PY_ID: "--id spi-nor_qemu"
TEST_PY_TEST_SPEC: "not sleep"
xilinx_mbv32:
TEST_PY_BD: "xilinx_mbv32"
TEST_PY_ID: "--id qemu"
TEST_PY_TEST_SPEC: "not sleep"
xilinx_mbv32_smode test.py:
TEST_PY_BD: "xilinx_mbv32_smode"
TEST_PY_ID: "--id qemu"
TEST_PY_TEST_SPEC: "not sleep"
xilinx_mbv64 test.py:
TEST_PY_BD: "xilinx_mbv64"
TEST_PY_ID: "--id qemu"
TEST_PY_TEST_SPEC: "not sleep"
xilinx_mbv64_smode test.py:
TEST_PY_BD: "xilinx_mbv64_smode"
TEST_PY_ID: "--id qemu"
TEST_PY_TEST_SPEC: "not sleep"
xilinx_zynq_virt:
TEST_PY_BD: "xilinx_zynq_virt"
TEST_PY_ID: "--id qemu"

View File

@@ -19,6 +19,9 @@
# Not Linux, so we don't recommend usleep_range() over udelay()
--ignore USLEEP_RANGE
# We also do not have a functionally different mdelay() and udelay()
--ignore LONG_UDELAY
# Ignore networking block comment style
--ignore NETWORKING_BLOCK_COMMENT_STYLE

804
.clang-format Normal file
View File

@@ -0,0 +1,804 @@
# SPDX-License-Identifier: GPL-2.0
#
# clang-format configuration file. Intended for clang-format >= 11.
#
# For more information, see:
#
# Documentation/dev-tools/clang-format.rst
# https://clang.llvm.org/docs/ClangFormat.html
# https://clang.llvm.org/docs/ClangFormatStyleOptions.html
#
---
AccessModifierOffset: -4
AlignAfterOpenBracket: Align
AlignConsecutiveAssignments: false
AlignConsecutiveDeclarations: false
AlignEscapedNewlines: Left
AlignOperands: true
AlignTrailingComments: false
AllowAllParametersOfDeclarationOnNextLine: false
AllowShortBlocksOnASingleLine: false
AllowShortCaseLabelsOnASingleLine: false
AllowShortFunctionsOnASingleLine: None
AllowShortIfStatementsOnASingleLine: false
AllowShortLoopsOnASingleLine: false
AlwaysBreakAfterDefinitionReturnType: None
AlwaysBreakAfterReturnType: None
AlwaysBreakBeforeMultilineStrings: false
AlwaysBreakTemplateDeclarations: false
BinPackArguments: true
BinPackParameters: true
BraceWrapping:
AfterClass: false
AfterControlStatement: false
AfterEnum: false
AfterFunction: true
AfterNamespace: true
AfterObjCDeclaration: false
AfterStruct: false
AfterUnion: false
AfterExternBlock: false
BeforeCatch: false
BeforeElse: false
IndentBraces: false
SplitEmptyFunction: true
SplitEmptyRecord: true
SplitEmptyNamespace: true
BreakBeforeBinaryOperators: None
BreakBeforeBraces: Custom
BreakBeforeInheritanceComma: false
BreakBeforeTernaryOperators: false
BreakConstructorInitializersBeforeComma: false
BreakConstructorInitializers: BeforeComma
BreakAfterJavaFieldAnnotations: false
BreakStringLiterals: false
ColumnLimit: 80
CommentPragmas: '^ IWYU pragma:'
CompactNamespaces: false
ConstructorInitializerAllOnOneLineOrOnePerLine: false
ConstructorInitializerIndentWidth: 8
ContinuationIndentWidth: 8
Cpp11BracedListStyle: false
DerivePointerAlignment: false
DisableFormat: false
ExperimentalAutoDetectBinPacking: false
FixNamespaceComments: false
# Taken from:
# git grep -h '^#define [^[:space:]]*for_each[^[:space:]]*(' include/ tools/ \
# | sed "s,^#define \([^[:space:]]*for_each[^[:space:]]*\)(.*$, - '\1'," \
# | LC_ALL=C sort -u
ForEachMacros:
- '__ata_qc_for_each'
- '__bio_for_each_bvec'
- '__bio_for_each_segment'
- '__evlist__for_each_entry'
- '__evlist__for_each_entry_continue'
- '__evlist__for_each_entry_from'
- '__evlist__for_each_entry_reverse'
- '__evlist__for_each_entry_safe'
- '__for_each_mem_range'
- '__for_each_mem_range_rev'
- '__for_each_thread'
- '__hlist_for_each_rcu'
- '__map__for_each_symbol_by_name'
- '__pci_bus_for_each_res0'
- '__pci_bus_for_each_res1'
- '__pci_dev_for_each_res0'
- '__pci_dev_for_each_res1'
- '__perf_evlist__for_each_entry'
- '__perf_evlist__for_each_entry_reverse'
- '__perf_evlist__for_each_entry_safe'
- '__rq_for_each_bio'
- '__shost_for_each_device'
- '__sym_for_each'
- '_for_each_counter'
- 'apei_estatus_for_each_section'
- 'ata_for_each_dev'
- 'ata_for_each_link'
- 'ata_qc_for_each'
- 'ata_qc_for_each_raw'
- 'ata_qc_for_each_with_internal'
- 'ax25_for_each'
- 'ax25_uid_for_each'
- 'bio_for_each_bvec'
- 'bio_for_each_bvec_all'
- 'bio_for_each_folio_all'
- 'bio_for_each_integrity_vec'
- 'bio_for_each_segment'
- 'bio_for_each_segment_all'
- 'bio_list_for_each'
- 'bip_for_each_vec'
- 'bond_for_each_slave'
- 'bond_for_each_slave_rcu'
- 'bpf_for_each'
- 'bpf_for_each_reg_in_vstate'
- 'bpf_for_each_reg_in_vstate_mask'
- 'bpf_for_each_spilled_reg'
- 'bpf_object__for_each_map'
- 'bpf_object__for_each_program'
- 'btree_for_each_safe128'
- 'btree_for_each_safe32'
- 'btree_for_each_safe64'
- 'btree_for_each_safel'
- 'card_for_each_dev'
- 'cgroup_taskset_for_each'
- 'cgroup_taskset_for_each_leader'
- 'cpu_aggr_map__for_each_idx'
- 'cpufreq_for_each_efficient_entry_idx'
- 'cpufreq_for_each_entry'
- 'cpufreq_for_each_entry_idx'
- 'cpufreq_for_each_valid_entry'
- 'cpufreq_for_each_valid_entry_idx'
- 'css_for_each_child'
- 'css_for_each_descendant_post'
- 'css_for_each_descendant_pre'
- 'damon_for_each_region'
- 'damon_for_each_region_from'
- 'damon_for_each_region_safe'
- 'damon_for_each_scheme'
- 'damon_for_each_scheme_safe'
- 'damon_for_each_target'
- 'damon_for_each_target_safe'
- 'damos_for_each_filter'
- 'damos_for_each_filter_safe'
- 'damos_for_each_ops_filter'
- 'damos_for_each_ops_filter_safe'
- 'damos_for_each_quota_goal'
- 'damos_for_each_quota_goal_safe'
- 'data__for_each_file'
- 'data__for_each_file_new'
- 'data__for_each_file_start'
- 'def_for_each_cpu'
- 'device_for_each_child_node'
- 'device_for_each_child_node_scoped'
- 'dma_fence_array_for_each'
- 'dma_fence_chain_for_each'
- 'dma_fence_unwrap_for_each'
- 'dma_resv_for_each_fence'
- 'dma_resv_for_each_fence_unlocked'
- 'do_for_each_ftrace_op'
- 'drm_atomic_crtc_for_each_plane'
- 'drm_atomic_crtc_state_for_each_plane'
- 'drm_atomic_crtc_state_for_each_plane_state'
- 'drm_atomic_for_each_plane_damage'
- 'drm_client_for_each_connector_iter'
- 'drm_client_for_each_modeset'
- 'drm_connector_for_each_possible_encoder'
- 'drm_exec_for_each_locked_object'
- 'drm_exec_for_each_locked_object_reverse'
- 'drm_for_each_bridge_in_chain'
- 'drm_for_each_connector_iter'
- 'drm_for_each_crtc'
- 'drm_for_each_crtc_reverse'
- 'drm_for_each_encoder'
- 'drm_for_each_encoder_mask'
- 'drm_for_each_fb'
- 'drm_for_each_legacy_plane'
- 'drm_for_each_plane'
- 'drm_for_each_plane_mask'
- 'drm_for_each_privobj'
- 'drm_gem_for_each_gpuvm_bo'
- 'drm_gem_for_each_gpuvm_bo_safe'
- 'drm_gpusvm_for_each_range'
- 'drm_gpuva_for_each_op'
- 'drm_gpuva_for_each_op_from_reverse'
- 'drm_gpuva_for_each_op_reverse'
- 'drm_gpuva_for_each_op_safe'
- 'drm_gpuvm_bo_for_each_va'
- 'drm_gpuvm_bo_for_each_va_safe'
- 'drm_gpuvm_for_each_va'
- 'drm_gpuvm_for_each_va_range'
- 'drm_gpuvm_for_each_va_range_safe'
- 'drm_gpuvm_for_each_va_safe'
- 'drm_mm_for_each_hole'
- 'drm_mm_for_each_node'
- 'drm_mm_for_each_node_in_range'
- 'drm_mm_for_each_node_safe'
- 'dsa_switch_for_each_available_port'
- 'dsa_switch_for_each_cpu_port'
- 'dsa_switch_for_each_cpu_port_continue_reverse'
- 'dsa_switch_for_each_port'
- 'dsa_switch_for_each_port_continue_reverse'
- 'dsa_switch_for_each_port_safe'
- 'dsa_switch_for_each_user_port'
- 'dsa_switch_for_each_user_port_continue_reverse'
- 'dsa_tree_for_each_cpu_port'
- 'dsa_tree_for_each_user_port'
- 'dsa_tree_for_each_user_port_continue_reverse'
- 'dso__for_each_symbol'
- 'elf_hash_for_each_possible'
- 'elf_symtab__for_each_symbol'
- 'evlist__for_each_cpu'
- 'evlist__for_each_entry'
- 'evlist__for_each_entry_continue'
- 'evlist__for_each_entry_from'
- 'evlist__for_each_entry_reverse'
- 'evlist__for_each_entry_safe'
- 'flow_action_for_each'
- 'for_each_acpi_consumer_dev'
- 'for_each_acpi_dev_match'
- 'for_each_active_dev_scope'
- 'for_each_active_drhd_unit'
- 'for_each_active_iommu'
- 'for_each_active_irq'
- 'for_each_active_route'
- 'for_each_aggr_pgid'
- 'for_each_alloc_capable_rdt_resource'
- 'for_each_and_bit'
- 'for_each_andnot_bit'
- 'for_each_available_child_of_node'
- 'for_each_available_child_of_node_scoped'
- 'for_each_bench'
- 'for_each_bio'
- 'for_each_board_func_rsrc'
- 'for_each_btf_ext_rec'
- 'for_each_btf_ext_sec'
- 'for_each_bvec'
- 'for_each_capable_rdt_resource'
- 'for_each_card_auxs'
- 'for_each_card_auxs_safe'
- 'for_each_card_components'
- 'for_each_card_dapms'
- 'for_each_card_pre_auxs'
- 'for_each_card_prelinks'
- 'for_each_card_rtds'
- 'for_each_card_rtds_safe'
- 'for_each_card_widgets'
- 'for_each_card_widgets_safe'
- 'for_each_cgroup_storage_type'
- 'for_each_child_of_node'
- 'for_each_child_of_node_scoped'
- 'for_each_child_of_node_with_prefix'
- 'for_each_clear_bit'
- 'for_each_clear_bit_from'
- 'for_each_clear_bitrange'
- 'for_each_clear_bitrange_from'
- 'for_each_cmd'
- 'for_each_cmsghdr'
- 'for_each_collection'
- 'for_each_comp_order'
- 'for_each_compatible_node'
- 'for_each_component_dais'
- 'for_each_component_dais_safe'
- 'for_each_conduit'
- 'for_each_console'
- 'for_each_console_srcu'
- 'for_each_cpu'
- 'for_each_cpu_and'
- 'for_each_cpu_andnot'
- 'for_each_cpu_from'
- 'for_each_cpu_or'
- 'for_each_cpu_wrap'
- 'for_each_dapm_widgets'
- 'for_each_dedup_cand'
- 'for_each_dev_addr'
- 'for_each_dev_scope'
- 'for_each_dma_cap_mask'
- 'for_each_dpcm_be'
- 'for_each_dpcm_be_rollback'
- 'for_each_dpcm_be_safe'
- 'for_each_dpcm_fe'
- 'for_each_drhd_unit'
- 'for_each_dss_dev'
- 'for_each_efi_memory_desc'
- 'for_each_efi_memory_desc_in_map'
- 'for_each_element'
- 'for_each_element_extid'
- 'for_each_element_id'
- 'for_each_enabled_cpu'
- 'for_each_endpoint_of_node'
- 'for_each_event'
- 'for_each_event_tps'
- 'for_each_evictable_lru'
- 'for_each_fib6_node_rt_rcu'
- 'for_each_fib6_walker_rt'
- 'for_each_file_lock'
- 'for_each_free_mem_pfn_range_in_zone_from'
- 'for_each_free_mem_range'
- 'for_each_free_mem_range_reverse'
- 'for_each_func_rsrc'
- 'for_each_gpiochip_node'
- 'for_each_group_evsel'
- 'for_each_group_evsel_head'
- 'for_each_group_member'
- 'for_each_group_member_head'
- 'for_each_hstate'
- 'for_each_hwgpio'
- 'for_each_hwgpio_in_range'
- 'for_each_if'
- 'for_each_inject_fn'
- 'for_each_insn'
- 'for_each_insn_op_loc'
- 'for_each_insn_prefix'
- 'for_each_intid'
- 'for_each_iommu'
- 'for_each_ip_tunnel_rcu'
- 'for_each_irq_desc'
- 'for_each_irq_nr'
- 'for_each_lang'
- 'for_each_link_ch_maps'
- 'for_each_link_codecs'
- 'for_each_link_cpus'
- 'for_each_link_platforms'
- 'for_each_lru'
- 'for_each_matching_node'
- 'for_each_matching_node_and_match'
- 'for_each_media_entity_data_link'
- 'for_each_mem_pfn_range'
- 'for_each_mem_range'
- 'for_each_mem_range_rev'
- 'for_each_mem_region'
- 'for_each_member'
- 'for_each_memory'
- 'for_each_migratetype_order'
- 'for_each_missing_reg'
- 'for_each_mle_subelement'
- 'for_each_mod_mem_type'
- 'for_each_mon_capable_rdt_resource'
- 'for_each_mp_bvec'
- 'for_each_net'
- 'for_each_net_continue_reverse'
- 'for_each_net_rcu'
- 'for_each_netdev'
- 'for_each_netdev_continue'
- 'for_each_netdev_continue_rcu'
- 'for_each_netdev_continue_reverse'
- 'for_each_netdev_dump'
- 'for_each_netdev_feature'
- 'for_each_netdev_in_bond_rcu'
- 'for_each_netdev_rcu'
- 'for_each_netdev_reverse'
- 'for_each_netdev_safe'
- 'for_each_new_connector_in_state'
- 'for_each_new_crtc_in_state'
- 'for_each_new_mst_mgr_in_state'
- 'for_each_new_plane_in_state'
- 'for_each_new_plane_in_state_reverse'
- 'for_each_new_private_obj_in_state'
- 'for_each_new_reg'
- 'for_each_nhlt_endpoint'
- 'for_each_nhlt_endpoint_fmtcfg'
- 'for_each_nhlt_fmtcfg'
- 'for_each_node'
- 'for_each_node_by_name'
- 'for_each_node_by_type'
- 'for_each_node_mask'
- 'for_each_node_numadist'
- 'for_each_node_state'
- 'for_each_node_with_cpus'
- 'for_each_node_with_property'
- 'for_each_nonreserved_multicast_dest_pgid'
- 'for_each_numa_hop_mask'
- 'for_each_of_allnodes'
- 'for_each_of_allnodes_from'
- 'for_each_of_cpu_node'
- 'for_each_of_graph_port'
- 'for_each_of_graph_port_endpoint'
- 'for_each_of_pci_range'
- 'for_each_old_connector_in_state'
- 'for_each_old_crtc_in_state'
- 'for_each_old_mst_mgr_in_state'
- 'for_each_old_plane_in_state'
- 'for_each_old_private_obj_in_state'
- 'for_each_oldnew_connector_in_state'
- 'for_each_oldnew_crtc_in_state'
- 'for_each_oldnew_mst_mgr_in_state'
- 'for_each_oldnew_plane_in_state'
- 'for_each_oldnew_plane_in_state_reverse'
- 'for_each_oldnew_private_obj_in_state'
- 'for_each_online_cpu'
- 'for_each_online_cpu_wrap'
- 'for_each_online_node'
- 'for_each_online_pgdat'
- 'for_each_or_bit'
- 'for_each_page_ext'
- 'for_each_path'
- 'for_each_pci_bridge'
- 'for_each_pci_dev'
- 'for_each_pcm_streams'
- 'for_each_physmem_range'
- 'for_each_populated_zone'
- 'for_each_possible_cpu'
- 'for_each_possible_cpu_wrap'
- 'for_each_present_blessed_reg'
- 'for_each_present_cpu'
- 'for_each_present_section_nr'
- 'for_each_prime_number'
- 'for_each_prime_number_from'
- 'for_each_probe_cache_entry'
- 'for_each_process'
- 'for_each_process_thread'
- 'for_each_prop_codec_conf'
- 'for_each_prop_dai_codec'
- 'for_each_prop_dai_cpu'
- 'for_each_prop_dlc_codecs'
- 'for_each_prop_dlc_cpus'
- 'for_each_prop_dlc_platforms'
- 'for_each_property_of_node'
- 'for_each_rdt_resource'
- 'for_each_reg'
- 'for_each_reg_filtered'
- 'for_each_reloc'
- 'for_each_reloc_from'
- 'for_each_requested_gpio'
- 'for_each_requested_gpio_in_range'
- 'for_each_reserved_child_of_node'
- 'for_each_reserved_mem_range'
- 'for_each_reserved_mem_region'
- 'for_each_rtd_ch_maps'
- 'for_each_rtd_codec_dais'
- 'for_each_rtd_components'
- 'for_each_rtd_cpu_dais'
- 'for_each_rtd_dais'
- 'for_each_rtd_dais_reverse'
- 'for_each_sband_iftype_data'
- 'for_each_script'
- 'for_each_sec'
- 'for_each_set_bit'
- 'for_each_set_bit_from'
- 'for_each_set_bit_wrap'
- 'for_each_set_bitrange'
- 'for_each_set_bitrange_from'
- 'for_each_set_clump8'
- 'for_each_sg'
- 'for_each_sg_dma_page'
- 'for_each_sg_page'
- 'for_each_sgtable_dma_page'
- 'for_each_sgtable_dma_sg'
- 'for_each_sgtable_page'
- 'for_each_sgtable_sg'
- 'for_each_sibling_event'
- 'for_each_sta_active_link'
- 'for_each_subelement'
- 'for_each_subelement_extid'
- 'for_each_subelement_id'
- 'for_each_sublist'
- 'for_each_subsystem'
- 'for_each_suite'
- 'for_each_supported_activate_fn'
- 'for_each_supported_inject_fn'
- 'for_each_sym'
- 'for_each_thread'
- 'for_each_token'
- 'for_each_unicast_dest_pgid'
- 'for_each_valid_link'
- 'for_each_vif_active_link'
- 'for_each_vma'
- 'for_each_vma_range'
- 'for_each_vsi'
- 'for_each_wakeup_source'
- 'for_each_zone'
- 'for_each_zone_zonelist'
- 'for_each_zone_zonelist_nodemask'
- 'func_for_each_insn'
- 'fwnode_for_each_available_child_node'
- 'fwnode_for_each_child_node'
- 'fwnode_for_each_parent_node'
- 'fwnode_graph_for_each_endpoint'
- 'gadget_for_each_ep'
- 'genradix_for_each'
- 'genradix_for_each_from'
- 'genradix_for_each_reverse'
- 'hash_for_each'
- 'hash_for_each_possible'
- 'hash_for_each_possible_rcu'
- 'hash_for_each_possible_rcu_notrace'
- 'hash_for_each_possible_safe'
- 'hash_for_each_rcu'
- 'hash_for_each_safe'
- 'hashmap__for_each_entry'
- 'hashmap__for_each_entry_safe'
- 'hashmap__for_each_key_entry'
- 'hashmap__for_each_key_entry_safe'
- 'hctx_for_each_ctx'
- 'hists__for_each_format'
- 'hists__for_each_sort_list'
- 'hlist_bl_for_each_entry'
- 'hlist_bl_for_each_entry_rcu'
- 'hlist_bl_for_each_entry_safe'
- 'hlist_for_each'
- 'hlist_for_each_entry'
- 'hlist_for_each_entry_continue'
- 'hlist_for_each_entry_continue_rcu'
- 'hlist_for_each_entry_continue_rcu_bh'
- 'hlist_for_each_entry_from'
- 'hlist_for_each_entry_from_rcu'
- 'hlist_for_each_entry_rcu'
- 'hlist_for_each_entry_rcu_bh'
- 'hlist_for_each_entry_rcu_notrace'
- 'hlist_for_each_entry_safe'
- 'hlist_for_each_entry_srcu'
- 'hlist_for_each_safe'
- 'hlist_nulls_for_each_entry'
- 'hlist_nulls_for_each_entry_from'
- 'hlist_nulls_for_each_entry_rcu'
- 'hlist_nulls_for_each_entry_safe'
- 'i3c_bus_for_each_i2cdev'
- 'i3c_bus_for_each_i3cdev'
- 'idr_for_each_entry'
- 'idr_for_each_entry_continue'
- 'idr_for_each_entry_continue_ul'
- 'idr_for_each_entry_ul'
- 'iio_for_each_active_channel'
- 'in_dev_for_each_ifa_rcu'
- 'in_dev_for_each_ifa_rtnl'
- 'in_dev_for_each_ifa_rtnl_net'
- 'inet_bind_bucket_for_each'
- 'interval_tree_for_each_span'
- 'intlist__for_each_entry'
- 'intlist__for_each_entry_safe'
- 'kcore_copy__for_each_phdr'
- 'key_for_each'
- 'key_for_each_safe'
- 'klp_for_each_func'
- 'klp_for_each_func_safe'
- 'klp_for_each_func_static'
- 'klp_for_each_object'
- 'klp_for_each_object_safe'
- 'klp_for_each_object_static'
- 'kunit_suite_for_each_test_case'
- 'kvm_for_each_memslot'
- 'kvm_for_each_memslot_in_gfn_range'
- 'kvm_for_each_vcpu'
- 'libbpf_nla_for_each_attr'
- 'list_for_each'
- 'list_for_each_codec'
- 'list_for_each_codec_safe'
- 'list_for_each_continue'
- 'list_for_each_entry'
- 'list_for_each_entry_continue'
- 'list_for_each_entry_continue_rcu'
- 'list_for_each_entry_continue_reverse'
- 'list_for_each_entry_from'
- 'list_for_each_entry_from_rcu'
- 'list_for_each_entry_from_reverse'
- 'list_for_each_entry_lockless'
- 'list_for_each_entry_rcu'
- 'list_for_each_entry_reverse'
- 'list_for_each_entry_safe'
- 'list_for_each_entry_safe_continue'
- 'list_for_each_entry_safe_from'
- 'list_for_each_entry_safe_reverse'
- 'list_for_each_entry_srcu'
- 'list_for_each_from'
- 'list_for_each_prev'
- 'list_for_each_prev_safe'
- 'list_for_each_rcu'
- 'list_for_each_safe'
- 'llist_for_each'
- 'llist_for_each_entry'
- 'llist_for_each_entry_safe'
- 'llist_for_each_safe'
- 'lwq_for_each_safe'
- 'map__for_each_symbol'
- 'map__for_each_symbol_by_name'
- 'mas_for_each'
- 'mas_for_each_rev'
- 'mci_for_each_dimm'
- 'media_device_for_each_entity'
- 'media_device_for_each_intf'
- 'media_device_for_each_link'
- 'media_device_for_each_pad'
- 'media_entity_for_each_pad'
- 'media_pipeline_for_each_entity'
- 'media_pipeline_for_each_pad'
- 'mlx5_lag_for_each_peer_mdev'
- 'mptcp_for_each_subflow'
- 'msi_domain_for_each_desc'
- 'msi_for_each_desc'
- 'mt_for_each'
- 'nanddev_io_for_each_block'
- 'nanddev_io_for_each_page'
- 'neigh_for_each_in_bucket'
- 'neigh_for_each_in_bucket_rcu'
- 'neigh_for_each_in_bucket_safe'
- 'netdev_for_each_lower_dev'
- 'netdev_for_each_lower_private'
- 'netdev_for_each_lower_private_rcu'
- 'netdev_for_each_mc_addr'
- 'netdev_for_each_synced_mc_addr'
- 'netdev_for_each_synced_uc_addr'
- 'netdev_for_each_uc_addr'
- 'netdev_for_each_upper_dev_rcu'
- 'netdev_hw_addr_list_for_each'
- 'nft_rule_for_each_expr'
- 'nla_for_each_attr'
- 'nla_for_each_attr_type'
- 'nla_for_each_nested'
- 'nla_for_each_nested_type'
- 'nlmsg_for_each_attr'
- 'nlmsg_for_each_msg'
- 'nr_neigh_for_each'
- 'nr_neigh_for_each_safe'
- 'nr_node_for_each'
- 'nr_node_for_each_safe'
- 'of_for_each_phandle'
- 'of_property_for_each_string'
- 'of_property_for_each_u32'
- 'pci_bus_for_each_resource'
- 'pci_dev_for_each_resource'
- 'pcl_for_each_chunk'
- 'pcl_for_each_segment'
- 'pcm_for_each_format'
- 'perf_config_items__for_each_entry'
- 'perf_config_sections__for_each_entry'
- 'perf_config_set__for_each_entry'
- 'perf_cpu_map__for_each_cpu'
- 'perf_cpu_map__for_each_cpu_skip_any'
- 'perf_cpu_map__for_each_idx'
- 'perf_evlist__for_each_entry'
- 'perf_evlist__for_each_entry_reverse'
- 'perf_evlist__for_each_entry_safe'
- 'perf_evlist__for_each_evsel'
- 'perf_evlist__for_each_mmap'
- 'perf_evsel_for_each_per_thread_period_safe'
- 'perf_hpp_list__for_each_format'
- 'perf_hpp_list__for_each_format_safe'
- 'perf_hpp_list__for_each_sort_list'
- 'perf_hpp_list__for_each_sort_list_safe'
- 'plist_for_each'
- 'plist_for_each_continue'
- 'plist_for_each_entry'
- 'plist_for_each_entry_continue'
- 'plist_for_each_entry_safe'
- 'plist_for_each_safe'
- 'pnp_for_each_card'
- 'pnp_for_each_dev'
- 'protocol_for_each_card'
- 'protocol_for_each_dev'
- 'queue_for_each_hw_ctx'
- 'radix_tree_for_each_slot'
- 'radix_tree_for_each_tagged'
- 'rb_for_each'
- 'rbtree_postorder_for_each_entry_safe'
- 'rdma_for_each_block'
- 'rdma_for_each_port'
- 'rdma_umem_for_each_dma_block'
- 'resource_list_for_each_entry'
- 'resource_list_for_each_entry_safe'
- 'rhl_for_each_entry_rcu'
- 'rhl_for_each_rcu'
- 'rht_for_each'
- 'rht_for_each_entry'
- 'rht_for_each_entry_from'
- 'rht_for_each_entry_rcu'
- 'rht_for_each_entry_rcu_from'
- 'rht_for_each_entry_safe'
- 'rht_for_each_from'
- 'rht_for_each_rcu'
- 'rht_for_each_rcu_from'
- 'rq_for_each_bvec'
- 'rq_for_each_segment'
- 'rq_list_for_each'
- 'rq_list_for_each_safe'
- 'sample_read_group__for_each'
- 'scsi_for_each_prot_sg'
- 'scsi_for_each_sg'
- 'sctp_for_each_hentry'
- 'sctp_skb_for_each'
- 'sec_for_each_insn'
- 'sec_for_each_insn_continue'
- 'sec_for_each_insn_from'
- 'sec_for_each_sym'
- 'shdma_for_each_chan'
- 'shost_for_each_device'
- 'sk_for_each'
- 'sk_for_each_bound'
- 'sk_for_each_bound_safe'
- 'sk_for_each_entry_offset_rcu'
- 'sk_for_each_from'
- 'sk_for_each_rcu'
- 'sk_for_each_safe'
- 'sk_nulls_for_each'
- 'sk_nulls_for_each_from'
- 'sk_nulls_for_each_rcu'
- 'snd_array_for_each'
- 'snd_pcm_group_for_each_entry'
- 'snd_soc_dapm_widget_for_each_path'
- 'snd_soc_dapm_widget_for_each_path_safe'
- 'snd_soc_dapm_widget_for_each_sink_path'
- 'snd_soc_dapm_widget_for_each_source_path'
- 'sparsebit_for_each_set_range'
- 'strlist__for_each_entry'
- 'strlist__for_each_entry_safe'
- 'sym_for_each_insn'
- 'sym_for_each_insn_continue_reverse'
- 'symbols__for_each_entry'
- 'tb_property_for_each'
- 'tcf_act_for_each_action'
- 'tcf_exts_for_each_action'
- 'test_suite__for_each_test_case'
- 'tool_pmu__for_each_event'
- 'ttm_bo_lru_for_each_reserved_guarded'
- 'ttm_resource_manager_for_each_res'
- 'udp_lrpa_for_each_entry_rcu'
- 'udp_portaddr_for_each_entry'
- 'udp_portaddr_for_each_entry_rcu'
- 'usb_hub_for_each_child'
- 'v4l2_device_for_each_subdev'
- 'v4l2_m2m_for_each_dst_buf'
- 'v4l2_m2m_for_each_dst_buf_safe'
- 'v4l2_m2m_for_each_src_buf'
- 'v4l2_m2m_for_each_src_buf_safe'
- 'virtio_device_for_each_vq'
- 'vkms_config_for_each_connector'
- 'vkms_config_for_each_crtc'
- 'vkms_config_for_each_encoder'
- 'vkms_config_for_each_plane'
- 'vkms_config_connector_for_each_possible_encoder'
- 'vkms_config_encoder_for_each_possible_crtc'
- 'vkms_config_plane_for_each_possible_crtc'
- 'while_for_each_ftrace_op'
- 'workloads__for_each'
- 'xa_for_each'
- 'xa_for_each_marked'
- 'xa_for_each_range'
- 'xa_for_each_start'
- 'xas_for_each'
- 'xas_for_each_conflict'
- 'xas_for_each_marked'
- 'xbc_array_for_each_value'
- 'xbc_for_each_key_value'
- 'xbc_node_for_each_array_value'
- 'xbc_node_for_each_child'
- 'xbc_node_for_each_key_value'
- 'xbc_node_for_each_subkey'
- 'ynl_attr_for_each'
- 'ynl_attr_for_each_nested'
- 'ynl_attr_for_each_payload'
- 'zorro_for_each_dev'
IncludeBlocks: Preserve
IncludeCategories:
- Regex: '.*'
Priority: 1
IncludeIsMainRegex: '(Test)?$'
IndentCaseLabels: false
IndentGotoLabels: false
IndentPPDirectives: None
IndentWidth: 8
IndentWrappedFunctionNames: false
JavaScriptQuotes: Leave
JavaScriptWrapImports: true
KeepEmptyLinesAtTheStartOfBlocks: false
MacroBlockBegin: ''
MacroBlockEnd: ''
MaxEmptyLinesToKeep: 1
NamespaceIndentation: None
ObjCBinPackProtocolList: Auto
ObjCBlockIndentWidth: 8
ObjCSpaceAfterProperty: true
ObjCSpaceBeforeProtocolList: true
# Taken from git's rules
PenaltyBreakAssignment: 10
PenaltyBreakBeforeFirstCallParameter: 30
PenaltyBreakComment: 10
PenaltyBreakFirstLessLess: 0
PenaltyBreakString: 10
PenaltyExcessCharacter: 100
PenaltyReturnTypeOnItsOwnLine: 60
PointerAlignment: Right
ReflowComments: false
SortIncludes: false
SortUsingDeclarations: false
SpaceAfterCStyleCast: false
SpaceAfterTemplateKeyword: true
SpaceBeforeAssignmentOperators: true
SpaceBeforeCtorInitializerColon: true
SpaceBeforeInheritanceColon: true
SpaceBeforeParens: ControlStatementsExceptForEachMacros
SpaceBeforeRangeBasedForLoopColon: true
SpaceInEmptyParentheses: false
SpacesBeforeTrailingComments: 1
SpacesInAngles: false
SpacesInContainerLiterals: false
SpacesInCStyleCastParentheses: false
SpacesInParentheses: false
SpacesInSquareBrackets: false
Standard: Cpp03
TabWidth: 8
UseTab: Always
...

2
.gitignore vendored
View File

@@ -50,6 +50,7 @@ fit-dtb.blob*
/SPL*
/System.map
/boards.cfg
/mkimage*mkimage
/mkimage-in-simple-bin*
/simple-bin*
/u-boot*
@@ -58,6 +59,7 @@ fit-dtb.blob*
#
# We don't want to ignore the following even if they are dot-files
#
!.clang-format
!.get_maintainer.*
!.gitattributes
!.gitignore

View File

@@ -39,15 +39,15 @@ stages:
- git clone --depth=1 https://source.denx.de/u-boot/u-boot-test-hooks /tmp/uboot-test-hooks
# qemu_arm64_lwip_defconfig is the same as qemu_arm64 but with NET_LWIP enabled.
# The test config and the boardenv file from qemu_arm64 can be re-used so create symlinks
- ln -s conf.qemu_arm64_na /tmp/uboot-test-hooks/bin/travis-ci/conf.qemu_arm64_lwip_na
- ln -s conf.qemu_arm64 /tmp/uboot-test-hooks/bin/travis-ci/conf.qemu_arm64_lwip_na
- ln -s u_boot_boardenv_qemu_arm64_na.py /tmp/uboot-test-hooks/py/travis-ci/u_boot_boardenv_qemu_arm64_lwip_na.py
- ln -s travis-ci /tmp/uboot-test-hooks/bin/`hostname`
- ln -s travis-ci /tmp/uboot-test-hooks/py/`hostname`
- if [[ "${TEST_PY_BD}" == "qemu-riscv32_spl" ]]; then
- if [[ "${TEST_PY_BD}" == "qemu-riscv32_spl" ]] || [[ "${TEST_PY_BD}" == "xilinx_mbv32_smode" ]]; then
wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.3.1/opensbi-1.3.1-rv-bin.tar.xz | tar -C /tmp -xJ;
export OPENSBI=/tmp/opensbi-1.3.1-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin;
fi
- if [[ "${TEST_PY_BD}" == "qemu-riscv64_spl" ]] || [[ "${TEST_PY_BD}" == "sifive_unleashed" ]]; then
- if [[ "${TEST_PY_BD}" == "qemu-riscv64_spl" ]] || [[ "${TEST_PY_BD}" == "sifive_unleashed" ]] || [[ "${TEST_PY_BD}" == "xilinx_mbv64_smode" ]]; then
wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.3.1/opensbi-1.3.1-rv-bin.tar.xz | tar -C /tmp -xJ;
export OPENSBI=/tmp/opensbi-1.3.1-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin;
fi
@@ -550,6 +550,34 @@ vexpress_fvp_bloblist test.py:
- ${DEFAULT_AMD64_TAG}
<<: *buildman_and_testpy_dfn
xilinx_mbv32 test.py:
variables:
TEST_PY_BD: "xilinx_mbv32"
TEST_PY_TEST_SPEC: "not sleep"
TEST_PY_ID: "--id qemu"
<<: *buildman_and_testpy_dfn
xilinx_mbv32_smode test.py:
variables:
TEST_PY_BD: "xilinx_mbv32_smode"
TEST_PY_TEST_SPEC: "not sleep"
TEST_PY_ID: "--id qemu"
<<: *buildman_and_testpy_dfn
xilinx_mbv64 test.py:
variables:
TEST_PY_BD: "xilinx_mbv64"
TEST_PY_TEST_SPEC: "not sleep"
TEST_PY_ID: "--id qemu"
<<: *buildman_and_testpy_dfn
xilinx_mbv64_smode test.py:
variables:
TEST_PY_BD: "xilinx_mbv64_smode"
TEST_PY_TEST_SPEC: "not sleep"
TEST_PY_ID: "--id qemu"
<<: *buildman_and_testpy_dfn
xilinx_zynq_virt test.py:
variables:
TEST_PY_BD: "xilinx_zynq_virt"

View File

@@ -36,6 +36,7 @@ Bin Meng <bmeng.cn@gmail.com> <bin.meng@windriver.com>
Boris Brezillon <bbrezillon@kernel.org> <boris.brezillon@bootlin.com>
Boris Brezillon <bbrezillon@kernel.org> <boris.brezillon@free-electrons.com>
Casey Connolly <casey.connolly@linaro.org> <caleb.connolly@linaro.org>
Chen-Yu Tsai <wens@kernel.org> <wens@csie.org>
Christian Kohn <chris.kohn@amd.com> <christian.kohn@xilinx.com>
Christopher Obbard <christopher.obbard@linaro.org> <chris.obbard@collabora.com>
Dirk Behme <dirk.behme@googlemail.com>
@@ -140,7 +141,7 @@ Tom Rini <trini@konsulko.com> <trini@ti.com>
Tomas Thoresen <tomas.thoresen@amd.com> <tomast@xilinx.com>
TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Varalaxmi Bingi <varalaxmi.bingi@amd.com> <varalaxmi.bingi@xilinx.com>
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> <venkatesh.abbarapu@xilinx.com>
Abbarapu Venkatesh Yadav <venkyada@qti.qualcomm.com>
Vikhyat Goyal <vikhyat.goyal@amd.com> <vikhyat.goyal@xilinx.com>
Vishal Patel <vishal.patel@amd.com> <vishal.patel@xilinx.com>
Wolfgang Denk <wd@denx.de> <wd@atlas.denx.de>

View File

@@ -511,6 +511,7 @@ config SPL_IMAGE
config REMAKE_ELF
bool "Recreate an ELF image from raw U-Boot binary"
depends on !COMPILE_TEST
help
Enable this to recreate an ELF image (u-boot.elf) from the raw
U-Boot binary (u-boot.bin), which may already have been statically
@@ -720,6 +721,7 @@ config TPL_SYS_MONITOR_BASE
config DYNAMIC_SYS_CLK_FREQ
bool "Determine CPU clock frequency at run-time"
depends on !COMPILE_TEST
help
Implement a get_board_sys_clk function that will determine the CPU
clock frequency at run time, rather than define it statically.

View File

@@ -422,6 +422,8 @@ F: drivers/clk/mediatek/
F: drivers/cpu/mtk_cpu.c
F: drivers/i2c/mtk_i2c.c
F: drivers/mmc/mtk-sd.c
F: drivers/net/mtk_eth/
F: drivers/net/phy/mediatek/
F: drivers/phy/phy-mtk-*
F: drivers/pinctrl/mediatek/
F: drivers/power/domain/mtk-power-domain.c
@@ -436,8 +438,6 @@ F: drivers/timer/mtk_timer.c
F: drivers/usb/host/xhci-mtk.c
F: drivers/usb/mtu3/
F: drivers/watchdog/mtk_wdt.c
F: drivers/net/mtk_eth.c
F: drivers/net/mtk_eth.h
F: drivers/reset/reset-mediatek.c
F: drivers/serial/serial_mtk.c
F: include/dt-bindings/clock/mediatek,*
@@ -708,6 +708,7 @@ F: drivers/gpio/stm32_gpio.c
F: drivers/hwspinlock/stm32_hwspinlock.c
F: drivers/i2c/stm32f7_i2c.c
F: drivers/mailbox/stm32-ipcc.c
F: drivers/memory/stm32-omm.c
F: drivers/misc/stm32mp_fuse.c
F: drivers/misc/stm32_rcc.c
F: drivers/mmc/stm32_sdmmc2.c
@@ -724,6 +725,7 @@ F: drivers/rng/optee_rng.c
F: drivers/rng/stm32_rng.c
F: drivers/rtc/stm32_rtc.c
F: drivers/serial/serial_stm32.*
F: drivers/spi/stm32_ospi.c
F: drivers/spi/stm32_qspi.c
F: drivers/spi/stm32_spi.c
F: drivers/video/stm32/stm32_ltdc.c
@@ -1624,6 +1626,13 @@ F: drivers/*/*sandbox*.c
F: include/dt-bindings/*/sandbox*.h
F: include/os.h
SCMI
M: Peng Fan <peng.fan@nxp.com>
S: Maintained
F: drivers/firmware/scmi/
F: include/scmi*
N: scmi
SEAMA
M: Linus Walleij <linus.walleij@linaro.org>
S: Maintained

View File

@@ -1,9 +1,9 @@
# SPDX-License-Identifier: GPL-2.0+
VERSION = 2025
PATCHLEVEL = 10
VERSION = 2026
PATCHLEVEL = 01
SUBLEVEL =
EXTRAVERSION =
EXTRAVERSION = -rc1
NAME =
# *DOCUMENTATION*
@@ -2666,6 +2666,10 @@ help:
@echo 'Execute "make" or "make all" to build all targets marked with [*] '
@echo 'For further info see the ./README file'
ifneq ($(filter tests pcheck qcheck tcheck,$(MAKECMDGOALS)),)
export sub_make_done := 0
endif
tests check:
$(srctree)/test/run

36
README
View File

@@ -300,28 +300,6 @@ The following options need to be configured:
Note that if the GPIO device uses I2C, then the I2C interface
must also be configured. See I2C Support, below.
- I/O tracing:
When CONFIG_IO_TRACE is selected, U-Boot intercepts all I/O
accesses and can checksum them or write a list of them out
to memory. See the 'iotrace' command for details. This is
useful for testing device drivers since it can confirm that
the driver behaves the same way before and after a code
change. Currently this is supported on sandbox and arm. To
add support for your architecture, add '#include <iotrace.h>'
to the bottom of arch/<arch>/include/asm/io.h and test.
Example output from the 'iotrace stats' command is below.
Note that if the trace buffer is exhausted, the checksum will
still continue to operate.
iotrace is enabled
Start: 10000000 (buffer start address)
Size: 00010000 (buffer size)
Offset: 00000120 (current buffer offset)
Output: 10000120 (start + offset)
Count: 00000018 (number of trace records)
CRC32: 9526fb66 (CRC32 of all trace records)
- Timestamp Support:
When CONFIG_TIMESTAMP is selected, the timestamp
@@ -390,17 +368,6 @@ The following options need to be configured:
CONFIG_TPM_TIS_I2C_BURST_LIMITATION
Define the burst count bytes upper limit
CONFIG_TPM_ST33ZP24
Support for STMicroelectronics TPM devices. Requires DM_TPM support.
CONFIG_TPM_ST33ZP24_I2C
Support for STMicroelectronics ST33ZP24 I2C devices.
Requires TPM_ST33ZP24 and I2C.
CONFIG_TPM_ST33ZP24_SPI
Support for STMicroelectronics ST33ZP24 SPI devices.
Requires TPM_ST33ZP24 and SPI.
CONFIG_TPM_ATMEL_TWI
Support for Atmel TWI TPM device. Requires I2C support.
@@ -1249,9 +1216,6 @@ Note: once the monitor has been relocated, then it will complain if
the default environment is used; a new CRC is computed as soon as you
use the "saveenv" command to store a valid environment.
- CONFIG_SYS_FAULT_MII_ADDR:
MII address of the PHY to check for the Ethernet link state.
- CONFIG_DISPLAY_BOARDINFO
Display information about the board that U-Boot is running on
when U-Boot starts up. The board function checkboard() is called

View File

@@ -202,7 +202,6 @@ config SANDBOX
select DM_SPI
select DM_SPI_FLASH
select GZIP_COMPRESSED
select IO_TRACE
select LZO
select MMC
select MTD

View File

@@ -68,10 +68,10 @@ config INIT_SP_RELATIVE
SYS_INIT_SP_BSS_OFFSET.
config SYS_INIT_SP_BSS_OFFSET
int "Early stack offset from the .bss base address"
hex "Early stack offset from the .bss base address"
depends on ARM64
depends on INIT_SP_RELATIVE
default 524288
default 0x80000
help
This option's value is the offset added to &_bss_start in order to
calculate the stack pointer. This offset should be large enough so
@@ -445,7 +445,7 @@ config ARCH_CPU_INIT
config SYS_ARCH_TIMER
bool "ARM Generic Timer support"
depends on CPU_V7A || ARM64
depends on CPU_V7A || CPU_V7M || ARM64
default y if ARM64
help
The ARM Generic Timer (aka arch-timer) provides an architected
@@ -883,6 +883,7 @@ config ARCH_MMP
select OF_CONTROL
select SAVE_PREV_BL_FDT_ADDR
select SAVE_PREV_BL_INITRAMFS_START_ADDR
imply OF_UPSTREAM
config ARCH_LPC32XX
bool "NXP LPC32xx platform"
@@ -1418,6 +1419,8 @@ config ARCH_VEXPRESS64
select MTD_NOR_FLASH if MTD
select FLASH_CFI_DRIVER if MTD
select ENV_IS_IN_FLASH if MTD
select SYSRESET
select SYSRESET_PSCI if ARM_PSCI_FW
imply DISTRO_DEFAULTS
config TARGET_CORSTONE1000

View File

@@ -32,7 +32,6 @@ ifneq (,$(filter s5pc1xx exynos,$(SOC)))
obj-y += s5p-common/
endif
obj-$(if $(filter bcm235xx,$(SOC)),y) += bcm235xx/
obj-$(if $(filter bcm281xx,$(SOC)),y) += bcm281xx/
obj-$(if $(filter bcmcygnus,$(SOC)),y) += bcmcygnus/
obj-$(if $(filter bcmnsp,$(SOC)),y) += bcmnsp/

View File

@@ -1,10 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright 2013 Broadcom Corporation.
obj-y += clk-core.o
obj-y += clk-bcm235xx.o
obj-y += clk-sdio.o
obj-y += clk-bsc.o
obj-$(CONFIG_BCM_SF2_ETH) += clk-eth.o
obj-y += clk-usb-otg.o

View File

@@ -1,567 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2013 Broadcom Corporation.
*/
/*
*
* bcm235xx-specific clock tables
*
*/
#include <asm/io.h>
#include <linux/errno.h>
#include <asm/arch/sysmap.h>
#include <asm/kona-common/clk.h>
#include "clk-core.h"
#define CLOCK_1K 1000
#define CLOCK_1M (CLOCK_1K * 1000)
/* declare a reference clock */
#define DECLARE_REF_CLK(clk_name, clk_parent, clk_rate, clk_div) \
static struct refclk clk_name = { \
.clk = { \
.name = #clk_name, \
.parent = clk_parent, \
.rate = clk_rate, \
.div = clk_div, \
.ops = &ref_clk_ops, \
}, \
}
/*
* Reference clocks
*/
/* Declare a list of reference clocks */
DECLARE_REF_CLK(ref_crystal, 0, 26 * CLOCK_1M, 1);
DECLARE_REF_CLK(var_96m, 0, 96 * CLOCK_1M, 1);
DECLARE_REF_CLK(ref_96m, 0, 96 * CLOCK_1M, 1);
DECLARE_REF_CLK(ref_312m, 0, 312 * CLOCK_1M, 0);
DECLARE_REF_CLK(ref_104m, &ref_312m.clk, 104 * CLOCK_1M, 3);
DECLARE_REF_CLK(ref_52m, &ref_104m.clk, 52 * CLOCK_1M, 2);
DECLARE_REF_CLK(ref_13m, &ref_52m.clk, 13 * CLOCK_1M, 4);
DECLARE_REF_CLK(var_312m, 0, 312 * CLOCK_1M, 0);
DECLARE_REF_CLK(var_104m, &var_312m.clk, 104 * CLOCK_1M, 3);
DECLARE_REF_CLK(var_52m, &var_104m.clk, 52 * CLOCK_1M, 2);
DECLARE_REF_CLK(var_13m, &var_52m.clk, 13 * CLOCK_1M, 4);
struct refclk_lkup {
struct refclk *procclk;
const char *name;
};
/* Lookup table for string to clk tranlation */
#define MKSTR(x) {&x, #x}
static struct refclk_lkup refclk_str_tbl[] = {
MKSTR(ref_crystal), MKSTR(var_96m), MKSTR(ref_96m),
MKSTR(ref_312m), MKSTR(ref_104m), MKSTR(ref_52m),
MKSTR(ref_13m), MKSTR(var_312m), MKSTR(var_104m),
MKSTR(var_52m), MKSTR(var_13m),
};
int refclk_entries = sizeof(refclk_str_tbl)/sizeof(refclk_str_tbl[0]);
/* convert ref clock string to clock structure pointer */
struct refclk *refclk_str_to_clk(const char *name)
{
int i;
struct refclk_lkup *tblp = refclk_str_tbl;
for (i = 0; i < refclk_entries; i++, tblp++) {
if (!(strcmp(name, tblp->name)))
return tblp->procclk;
}
return NULL;
}
/* frequency tables indexed by freq_id */
unsigned long master_axi_freq_tbl[8] = {
26 * CLOCK_1M,
52 * CLOCK_1M,
104 * CLOCK_1M,
156 * CLOCK_1M,
156 * CLOCK_1M,
208 * CLOCK_1M,
312 * CLOCK_1M,
312 * CLOCK_1M
};
unsigned long master_ahb_freq_tbl[8] = {
26 * CLOCK_1M,
52 * CLOCK_1M,
52 * CLOCK_1M,
52 * CLOCK_1M,
78 * CLOCK_1M,
104 * CLOCK_1M,
104 * CLOCK_1M,
156 * CLOCK_1M
};
unsigned long slave_axi_freq_tbl[8] = {
26 * CLOCK_1M,
52 * CLOCK_1M,
78 * CLOCK_1M,
104 * CLOCK_1M,
156 * CLOCK_1M,
156 * CLOCK_1M
};
unsigned long slave_apb_freq_tbl[8] = {
26 * CLOCK_1M,
26 * CLOCK_1M,
39 * CLOCK_1M,
52 * CLOCK_1M,
52 * CLOCK_1M,
78 * CLOCK_1M
};
unsigned long esub_freq_tbl[8] = {
78 * CLOCK_1M,
156 * CLOCK_1M,
156 * CLOCK_1M,
156 * CLOCK_1M,
208 * CLOCK_1M,
208 * CLOCK_1M,
208 * CLOCK_1M
};
static struct bus_clk_data bsc1_apb_data = {
.gate = HW_SW_GATE_AUTO(0x0458, 16, 0, 1),
};
static struct bus_clk_data bsc2_apb_data = {
.gate = HW_SW_GATE_AUTO(0x045c, 16, 0, 1),
};
static struct bus_clk_data bsc3_apb_data = {
.gate = HW_SW_GATE_AUTO(0x0484, 16, 0, 1),
};
/* * Master CCU clocks */
static struct peri_clk_data sdio1_data = {
.gate = HW_SW_GATE(0x0358, 18, 2, 3),
.clocks = CLOCKS("ref_crystal",
"var_52m",
"ref_52m",
"var_96m",
"ref_96m"),
.sel = SELECTOR(0x0a28, 0, 3),
.div = DIVIDER(0x0a28, 4, 14),
.trig = TRIGGER(0x0afc, 9),
};
static struct peri_clk_data sdio2_data = {
.gate = HW_SW_GATE(0x035c, 18, 2, 3),
.clocks = CLOCKS("ref_crystal",
"var_52m",
"ref_52m",
"var_96m",
"ref_96m"),
.sel = SELECTOR(0x0a2c, 0, 3),
.div = DIVIDER(0x0a2c, 4, 14),
.trig = TRIGGER(0x0afc, 10),
};
static struct peri_clk_data sdio3_data = {
.gate = HW_SW_GATE(0x0364, 18, 2, 3),
.clocks = CLOCKS("ref_crystal",
"var_52m",
"ref_52m",
"var_96m",
"ref_96m"),
.sel = SELECTOR(0x0a34, 0, 3),
.div = DIVIDER(0x0a34, 4, 14),
.trig = TRIGGER(0x0afc, 12),
};
static struct peri_clk_data sdio4_data = {
.gate = HW_SW_GATE(0x0360, 18, 2, 3),
.clocks = CLOCKS("ref_crystal",
"var_52m",
"ref_52m",
"var_96m",
"ref_96m"),
.sel = SELECTOR(0x0a30, 0, 3),
.div = DIVIDER(0x0a30, 4, 14),
.trig = TRIGGER(0x0afc, 11),
};
static struct peri_clk_data sdio1_sleep_data = {
.clocks = CLOCKS("ref_32k"),
.gate = SW_ONLY_GATE(0x0358, 20, 4),
};
static struct peri_clk_data sdio2_sleep_data = {
.clocks = CLOCKS("ref_32k"),
.gate = SW_ONLY_GATE(0x035c, 20, 4),
};
static struct peri_clk_data sdio3_sleep_data = {
.clocks = CLOCKS("ref_32k"),
.gate = SW_ONLY_GATE(0x0364, 20, 4),
};
static struct peri_clk_data sdio4_sleep_data = {
.clocks = CLOCKS("ref_32k"),
.gate = SW_ONLY_GATE(0x0360, 20, 4),
};
static struct bus_clk_data usb_otg_ahb_data = {
.gate = HW_SW_GATE_AUTO(0x0348, 16, 0, 1),
};
static struct bus_clk_data sdio1_ahb_data = {
.gate = HW_SW_GATE_AUTO(0x0358, 16, 0, 1),
};
static struct bus_clk_data sdio2_ahb_data = {
.gate = HW_SW_GATE_AUTO(0x035c, 16, 0, 1),
};
static struct bus_clk_data sdio3_ahb_data = {
.gate = HW_SW_GATE_AUTO(0x0364, 16, 0, 1),
};
static struct bus_clk_data sdio4_ahb_data = {
.gate = HW_SW_GATE_AUTO(0x0360, 16, 0, 1),
};
/* * Slave CCU clocks */
static struct peri_clk_data bsc1_data = {
.gate = HW_SW_GATE(0x0458, 18, 2, 3),
.clocks = CLOCKS("ref_crystal",
"var_104m",
"ref_104m",
"var_13m",
"ref_13m"),
.sel = SELECTOR(0x0a64, 0, 3),
.trig = TRIGGER(0x0afc, 23),
};
static struct peri_clk_data bsc2_data = {
.gate = HW_SW_GATE(0x045c, 18, 2, 3),
.clocks = CLOCKS("ref_crystal",
"var_104m",
"ref_104m",
"var_13m",
"ref_13m"),
.sel = SELECTOR(0x0a68, 0, 3),
.trig = TRIGGER(0x0afc, 24),
};
static struct peri_clk_data bsc3_data = {
.gate = HW_SW_GATE(0x0484, 18, 2, 3),
.clocks = CLOCKS("ref_crystal",
"var_104m",
"ref_104m",
"var_13m",
"ref_13m"),
.sel = SELECTOR(0x0a84, 0, 3),
.trig = TRIGGER(0x0b00, 2),
};
/*
* CCU clocks
*/
static struct ccu_clock kpm_ccu_clk = {
.clk = {
.name = "kpm_ccu_clk",
.ops = &ccu_clk_ops,
.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
},
.num_policy_masks = 1,
.policy_freq_offset = 0x00000008,
.freq_bit_shift = 8,
.policy_ctl_offset = 0x0000000c,
.policy0_mask_offset = 0x00000010,
.policy1_mask_offset = 0x00000014,
.policy2_mask_offset = 0x00000018,
.policy3_mask_offset = 0x0000001c,
.lvm_en_offset = 0x00000034,
.freq_id = 2,
.freq_tbl = master_axi_freq_tbl,
};
static struct ccu_clock kps_ccu_clk = {
.clk = {
.name = "kps_ccu_clk",
.ops = &ccu_clk_ops,
.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
},
.num_policy_masks = 1,
.policy_freq_offset = 0x00000008,
.freq_bit_shift = 8,
.policy_ctl_offset = 0x0000000c,
.policy0_mask_offset = 0x00000010,
.policy1_mask_offset = 0x00000014,
.policy2_mask_offset = 0x00000018,
.policy3_mask_offset = 0x0000001c,
.lvm_en_offset = 0x00000034,
.freq_id = 2,
.freq_tbl = slave_axi_freq_tbl,
};
#ifdef CONFIG_BCM_SF2_ETH
static struct ccu_clock esub_ccu_clk = {
.clk = {
.name = "esub_ccu_clk",
.ops = &ccu_clk_ops,
.ccu_clk_mgr_base = ESUB_CLK_BASE_ADDR,
},
.num_policy_masks = 1,
.policy_freq_offset = 0x00000008,
.freq_bit_shift = 8,
.policy_ctl_offset = 0x0000000c,
.policy0_mask_offset = 0x00000010,
.policy1_mask_offset = 0x00000014,
.policy2_mask_offset = 0x00000018,
.policy3_mask_offset = 0x0000001c,
.lvm_en_offset = 0x00000034,
.freq_id = 2,
.freq_tbl = esub_freq_tbl,
};
#endif
/*
* Bus clocks
*/
/* KPM bus clocks */
static struct bus_clock usb_otg_ahb_clk = {
.clk = {
.name = "usb_otg_ahb_clk",
.parent = &kpm_ccu_clk.clk,
.ops = &bus_clk_ops,
.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
},
.freq_tbl = master_ahb_freq_tbl,
.data = &usb_otg_ahb_data,
};
static struct bus_clock sdio1_ahb_clk = {
.clk = {
.name = "sdio1_ahb_clk",
.parent = &kpm_ccu_clk.clk,
.ops = &bus_clk_ops,
.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
},
.freq_tbl = master_ahb_freq_tbl,
.data = &sdio1_ahb_data,
};
static struct bus_clock sdio2_ahb_clk = {
.clk = {
.name = "sdio2_ahb_clk",
.parent = &kpm_ccu_clk.clk,
.ops = &bus_clk_ops,
.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
},
.freq_tbl = master_ahb_freq_tbl,
.data = &sdio2_ahb_data,
};
static struct bus_clock sdio3_ahb_clk = {
.clk = {
.name = "sdio3_ahb_clk",
.parent = &kpm_ccu_clk.clk,
.ops = &bus_clk_ops,
.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
},
.freq_tbl = master_ahb_freq_tbl,
.data = &sdio3_ahb_data,
};
static struct bus_clock sdio4_ahb_clk = {
.clk = {
.name = "sdio4_ahb_clk",
.parent = &kpm_ccu_clk.clk,
.ops = &bus_clk_ops,
.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
},
.freq_tbl = master_ahb_freq_tbl,
.data = &sdio4_ahb_data,
};
static struct bus_clock bsc1_apb_clk = {
.clk = {
.name = "bsc1_apb_clk",
.parent = &kps_ccu_clk.clk,
.ops = &bus_clk_ops,
.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
},
.freq_tbl = slave_apb_freq_tbl,
.data = &bsc1_apb_data,
};
static struct bus_clock bsc2_apb_clk = {
.clk = {
.name = "bsc2_apb_clk",
.parent = &kps_ccu_clk.clk,
.ops = &bus_clk_ops,
.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
},
.freq_tbl = slave_apb_freq_tbl,
.data = &bsc2_apb_data,
};
static struct bus_clock bsc3_apb_clk = {
.clk = {
.name = "bsc3_apb_clk",
.parent = &kps_ccu_clk.clk,
.ops = &bus_clk_ops,
.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
},
.freq_tbl = slave_apb_freq_tbl,
.data = &bsc3_apb_data,
};
/* KPM peripheral */
static struct peri_clock sdio1_clk = {
.clk = {
.name = "sdio1_clk",
.parent = &ref_52m.clk,
.ops = &peri_clk_ops,
.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
},
.data = &sdio1_data,
};
static struct peri_clock sdio2_clk = {
.clk = {
.name = "sdio2_clk",
.parent = &ref_52m.clk,
.ops = &peri_clk_ops,
.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
},
.data = &sdio2_data,
};
static struct peri_clock sdio3_clk = {
.clk = {
.name = "sdio3_clk",
.parent = &ref_52m.clk,
.ops = &peri_clk_ops,
.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
},
.data = &sdio3_data,
};
static struct peri_clock sdio4_clk = {
.clk = {
.name = "sdio4_clk",
.parent = &ref_52m.clk,
.ops = &peri_clk_ops,
.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
},
.data = &sdio4_data,
};
static struct peri_clock sdio1_sleep_clk = {
.clk = {
.name = "sdio1_sleep_clk",
.parent = &kpm_ccu_clk.clk,
.ops = &bus_clk_ops,
.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
},
.data = &sdio1_sleep_data,
};
static struct peri_clock sdio2_sleep_clk = {
.clk = {
.name = "sdio2_sleep_clk",
.parent = &kpm_ccu_clk.clk,
.ops = &bus_clk_ops,
.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
},
.data = &sdio2_sleep_data,
};
static struct peri_clock sdio3_sleep_clk = {
.clk = {
.name = "sdio3_sleep_clk",
.parent = &kpm_ccu_clk.clk,
.ops = &bus_clk_ops,
.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
},
.data = &sdio3_sleep_data,
};
static struct peri_clock sdio4_sleep_clk = {
.clk = {
.name = "sdio4_sleep_clk",
.parent = &kpm_ccu_clk.clk,
.ops = &bus_clk_ops,
.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
},
.data = &sdio4_sleep_data,
};
/* KPS peripheral clock */
static struct peri_clock bsc1_clk = {
.clk = {
.name = "bsc1_clk",
.parent = &ref_13m.clk,
.rate = 13 * CLOCK_1M,
.div = 1,
.ops = &peri_clk_ops,
.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
},
.data = &bsc1_data,
};
static struct peri_clock bsc2_clk = {
.clk = {
.name = "bsc2_clk",
.parent = &ref_13m.clk,
.rate = 13 * CLOCK_1M,
.div = 1,
.ops = &peri_clk_ops,
.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
},
.data = &bsc2_data,
};
static struct peri_clock bsc3_clk = {
.clk = {
.name = "bsc3_clk",
.parent = &ref_13m.clk,
.rate = 13 * CLOCK_1M,
.div = 1,
.ops = &peri_clk_ops,
.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
},
.data = &bsc3_data,
};
/* public table for registering clocks */
struct clk_lookup arch_clk_tbl[] = {
/* Peripheral clocks */
CLK_LK(sdio1),
CLK_LK(sdio2),
CLK_LK(sdio3),
CLK_LK(sdio4),
CLK_LK(sdio1_sleep),
CLK_LK(sdio2_sleep),
CLK_LK(sdio3_sleep),
CLK_LK(sdio4_sleep),
CLK_LK(bsc1),
CLK_LK(bsc2),
CLK_LK(bsc3),
/* Bus clocks */
CLK_LK(usb_otg_ahb),
CLK_LK(sdio1_ahb),
CLK_LK(sdio2_ahb),
CLK_LK(sdio3_ahb),
CLK_LK(sdio4_ahb),
CLK_LK(bsc1_apb),
CLK_LK(bsc2_apb),
CLK_LK(bsc3_apb),
#ifdef CONFIG_BCM_SF2_ETH
CLK_LK(esub_ccu),
#endif
};
/* public array size */
unsigned int arch_clk_tbl_array_size = ARRAY_SIZE(arch_clk_tbl);

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@@ -1,50 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2013 Broadcom Corporation.
*/
#include <asm/io.h>
#include <linux/errno.h>
#include <asm/arch/sysmap.h>
#include <asm/kona-common/clk.h>
#include "clk-core.h"
/* Enable appropriate clocks for a BSC/I2C port */
int clk_bsc_enable(void *base)
{
int ret;
char *bscstr, *apbstr;
switch ((u32) base) {
case PMU_BSC_BASE_ADDR:
/* PMU clock is always enabled */
return 0;
case BSC1_BASE_ADDR:
bscstr = "bsc1_clk";
apbstr = "bsc1_apb_clk";
break;
case BSC2_BASE_ADDR:
bscstr = "bsc2_clk";
apbstr = "bsc2_apb_clk";
break;
case BSC3_BASE_ADDR:
bscstr = "bsc3_clk";
apbstr = "bsc3_apb_clk";
break;
default:
printf("%s: base 0x%p not found\n", __func__, base);
return -EINVAL;
}
/* Note that the bus clock must be enabled first */
ret = clk_get_and_enable(apbstr);
if (ret)
return ret;
ret = clk_get_and_enable(bscstr);
if (ret)
return ret;
return 0;
}

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@@ -1,512 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2013 Broadcom Corporation.
*/
/*
*
* bcm235xx architecture clock framework
*
*/
#include <log.h>
#include <asm/io.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <bitfield.h>
#include <asm/arch/sysmap.h>
#include <asm/kona-common/clk.h>
#include "clk-core.h"
#define CLK_WR_ACCESS_PASSWORD 0x00a5a501
#define WR_ACCESS_OFFSET 0 /* common to all clock blocks */
#define POLICY_CTL_GO 1 /* Load and refresh policy masks */
#define POLICY_CTL_GO_ATL 4 /* Active Load */
/* Helper function */
int clk_get_and_enable(char *clkstr)
{
int ret = 0;
struct clk *c;
debug("%s: %s\n", __func__, clkstr);
c = clk_get(clkstr);
if (c) {
ret = clk_enable(c);
if (ret)
return ret;
} else {
printf("%s: Couldn't find %s\n", __func__, clkstr);
return -EINVAL;
}
return ret;
}
/*
* Poll a register in a CCU's address space, returning when the
* specified bit in that register's value is set (or clear). Delay
* a microsecond after each read of the register. Returns true if
* successful, or false if we gave up trying.
*
* Caller must ensure the CCU lock is held.
*/
#define CLK_GATE_DELAY_USEC 2000
static inline int wait_bit(void *base, u32 offset, u32 bit, bool want)
{
unsigned int tries;
u32 bit_mask = 1 << bit;
for (tries = 0; tries < CLK_GATE_DELAY_USEC; tries++) {
u32 val;
bool bit_val;
val = readl(base + offset);
bit_val = (val & bit_mask) ? 1 : 0;
if (bit_val == want)
return 0; /* success */
udelay(1);
}
debug("%s: timeout on addr 0x%p, waiting for bit %d to go to %d\n",
__func__, base + offset, bit, want);
return -ETIMEDOUT;
}
/* Enable a peripheral clock */
static int peri_clk_enable(struct clk *c, int enable)
{
int ret = 0;
u32 reg;
struct peri_clock *peri_clk = to_peri_clk(c);
struct peri_clk_data *cd = peri_clk->data;
struct bcm_clk_gate *gate = &cd->gate;
void *base = (void *)c->ccu_clk_mgr_base;
debug("%s: %s\n", __func__, c->name);
clk_get_rate(c); /* Make sure rate and sel are filled in */
/* enable access */
writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET);
if (enable) {
debug("%s %s set rate %lu div %lu sel %d parent %lu\n",
__func__, c->name, c->rate, c->div, c->sel,
c->parent->rate);
/*
* clkgate - only software controllable gates are
* supported by u-boot which includes all clocks
* that matter. This avoids bringing in a lot of extra
* complexity as done in the kernel framework.
*/
if (gate_exists(gate)) {
reg = readl(base + cd->gate.offset);
reg |= (1 << cd->gate.en_bit);
writel(reg, base + cd->gate.offset);
}
/* div and pll select */
if (divider_exists(&cd->div)) {
reg = readl(base + cd->div.offset);
bitfield_replace(reg, cd->div.shift, cd->div.width,
c->div - 1);
writel(reg, base + cd->div.offset);
}
/* frequency selector */
if (selector_exists(&cd->sel)) {
reg = readl(base + cd->sel.offset);
bitfield_replace(reg, cd->sel.shift, cd->sel.width,
c->sel);
writel(reg, base + cd->sel.offset);
}
/* trigger */
if (trigger_exists(&cd->trig)) {
writel((1 << cd->trig.bit), base + cd->trig.offset);
/* wait for trigger status bit to go to 0 */
ret = wait_bit(base, cd->trig.offset, cd->trig.bit, 0);
if (ret)
return ret;
}
/* wait for running (status_bit = 1) */
ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 1);
if (ret)
return ret;
} else {
debug("%s disable clock %s\n", __func__, c->name);
/* clkgate */
reg = readl(base + cd->gate.offset);
reg &= ~(1 << cd->gate.en_bit);
writel(reg, base + cd->gate.offset);
/* wait for stop (status_bit = 0) */
ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 0);
}
/* disable access */
writel(0, base + WR_ACCESS_OFFSET);
return ret;
}
/* Set the rate of a peripheral clock */
static int peri_clk_set_rate(struct clk *c, unsigned long rate)
{
int ret = 0;
int i;
unsigned long diff;
unsigned long new_rate = 0, div = 1;
struct peri_clock *peri_clk = to_peri_clk(c);
struct peri_clk_data *cd = peri_clk->data;
const char **clock;
debug("%s: %s\n", __func__, c->name);
diff = rate;
i = 0;
for (clock = cd->clocks; *clock; clock++, i++) {
struct refclk *ref = refclk_str_to_clk(*clock);
if (!ref) {
printf("%s: Lookup of %s failed\n", __func__, *clock);
return -EINVAL;
}
/* round to the new rate */
div = ref->clk.rate / rate;
if (div == 0)
div = 1;
new_rate = ref->clk.rate / div;
/* get the min diff */
if (abs(new_rate - rate) < diff) {
diff = abs(new_rate - rate);
c->sel = i;
c->parent = &ref->clk;
c->rate = new_rate;
c->div = div;
}
}
debug("%s %s set rate %lu div %lu sel %d parent %lu\n", __func__,
c->name, c->rate, c->div, c->sel, c->parent->rate);
return ret;
}
/* Get the rate of a peripheral clock */
static unsigned long peri_clk_get_rate(struct clk *c)
{
struct peri_clock *peri_clk = to_peri_clk(c);
struct peri_clk_data *cd = peri_clk->data;
void *base = (void *)c->ccu_clk_mgr_base;
int div = 1;
const char **clock;
struct refclk *ref;
u32 reg;
debug("%s: %s\n", __func__, c->name);
if (selector_exists(&cd->sel)) {
reg = readl(base + cd->sel.offset);
c->sel = bitfield_extract(reg, cd->sel.shift, cd->sel.width);
} else {
/*
* For peri clocks that don't have a selector, the single
* reference clock will always exist at index 0.
*/
c->sel = 0;
}
if (divider_exists(&cd->div)) {
reg = readl(base + cd->div.offset);
div = bitfield_extract(reg, cd->div.shift, cd->div.width);
div += 1;
}
clock = cd->clocks;
ref = refclk_str_to_clk(clock[c->sel]);
if (!ref) {
printf("%s: Can't lookup %s\n", __func__, clock[c->sel]);
return 0;
}
c->parent = &ref->clk;
c->div = div;
c->rate = c->parent->rate / c->div;
debug("%s parent rate %lu div %d sel %d rate %lu\n", __func__,
c->parent->rate, div, c->sel, c->rate);
return c->rate;
}
/* Peripheral clock operations */
struct clk_ops peri_clk_ops = {
.enable = peri_clk_enable,
.set_rate = peri_clk_set_rate,
.get_rate = peri_clk_get_rate,
};
/* Enable a CCU clock */
static int ccu_clk_enable(struct clk *c, int enable)
{
struct ccu_clock *ccu_clk = to_ccu_clk(c);
void *base = (void *)c->ccu_clk_mgr_base;
int ret = 0;
u32 reg;
debug("%s: %s\n", __func__, c->name);
if (!enable)
return -EINVAL; /* CCU clock cannot shutdown */
/* enable access */
writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET);
/* config enable for policy engine */
writel(1, base + ccu_clk->lvm_en_offset);
/* wait for bit to go to 0 */
ret = wait_bit(base, ccu_clk->lvm_en_offset, 0, 0);
if (ret)
return ret;
/* freq ID */
if (!ccu_clk->freq_bit_shift)
ccu_clk->freq_bit_shift = 8;
/* Set frequency id for each of the 4 policies */
reg = ccu_clk->freq_id |
(ccu_clk->freq_id << (ccu_clk->freq_bit_shift)) |
(ccu_clk->freq_id << (ccu_clk->freq_bit_shift * 2)) |
(ccu_clk->freq_id << (ccu_clk->freq_bit_shift * 3));
writel(reg, base + ccu_clk->policy_freq_offset);
/* enable all clock mask */
writel(0x7fffffff, base + ccu_clk->policy0_mask_offset);
writel(0x7fffffff, base + ccu_clk->policy1_mask_offset);
writel(0x7fffffff, base + ccu_clk->policy2_mask_offset);
writel(0x7fffffff, base + ccu_clk->policy3_mask_offset);
if (ccu_clk->num_policy_masks == 2) {
writel(0x7fffffff, base + ccu_clk->policy0_mask2_offset);
writel(0x7fffffff, base + ccu_clk->policy1_mask2_offset);
writel(0x7fffffff, base + ccu_clk->policy2_mask2_offset);
writel(0x7fffffff, base + ccu_clk->policy3_mask2_offset);
}
/* start policy engine */
reg = readl(base + ccu_clk->policy_ctl_offset);
reg |= (POLICY_CTL_GO + POLICY_CTL_GO_ATL);
writel(reg, base + ccu_clk->policy_ctl_offset);
/* wait till started */
ret = wait_bit(base, ccu_clk->policy_ctl_offset, 0, 0);
if (ret)
return ret;
/* disable access */
writel(0, base + WR_ACCESS_OFFSET);
return ret;
}
/* Get the CCU clock rate */
static unsigned long ccu_clk_get_rate(struct clk *c)
{
struct ccu_clock *ccu_clk = to_ccu_clk(c);
debug("%s: %s\n", __func__, c->name);
c->rate = ccu_clk->freq_tbl[ccu_clk->freq_id];
return c->rate;
}
/* CCU clock operations */
struct clk_ops ccu_clk_ops = {
.enable = ccu_clk_enable,
.get_rate = ccu_clk_get_rate,
};
/* Enable a bus clock */
static int bus_clk_enable(struct clk *c, int enable)
{
struct bus_clock *bus_clk = to_bus_clk(c);
struct bus_clk_data *cd = bus_clk->data;
void *base = (void *)c->ccu_clk_mgr_base;
int ret = 0;
u32 reg;
debug("%s: %s\n", __func__, c->name);
/* enable access */
writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET);
/* enable gating */
reg = readl(base + cd->gate.offset);
if (!!(reg & (1 << cd->gate.status_bit)) == !!enable)
debug("%s already %s\n", c->name,
enable ? "enabled" : "disabled");
else {
int want = (enable) ? 1 : 0;
reg |= (1 << cd->gate.hw_sw_sel_bit);
if (enable)
reg |= (1 << cd->gate.en_bit);
else
reg &= ~(1 << cd->gate.en_bit);
writel(reg, base + cd->gate.offset);
ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit,
want);
if (ret)
return ret;
}
/* disable access */
writel(0, base + WR_ACCESS_OFFSET);
return ret;
}
/* Get the rate of a bus clock */
static unsigned long bus_clk_get_rate(struct clk *c)
{
struct bus_clock *bus_clk = to_bus_clk(c);
struct ccu_clock *ccu_clk;
debug("%s: %s\n", __func__, c->name);
ccu_clk = to_ccu_clk(c->parent);
c->rate = bus_clk->freq_tbl[ccu_clk->freq_id];
c->div = ccu_clk->freq_tbl[ccu_clk->freq_id] / c->rate;
return c->rate;
}
/* Bus clock operations */
struct clk_ops bus_clk_ops = {
.enable = bus_clk_enable,
.get_rate = bus_clk_get_rate,
};
/* Enable a reference clock */
static int ref_clk_enable(struct clk *c, int enable)
{
debug("%s: %s\n", __func__, c->name);
return 0;
}
/* Reference clock operations */
struct clk_ops ref_clk_ops = {
.enable = ref_clk_enable,
};
/*
* clk.h implementation follows
*/
/* Initialize the clock framework */
int clk_init(void)
{
debug("%s:\n", __func__);
return 0;
}
/* Get a clock handle, give a name string */
struct clk *clk_get(const char *con_id)
{
int i;
struct clk_lookup *clk_tblp;
debug("%s: %s\n", __func__, con_id);
clk_tblp = arch_clk_tbl;
for (i = 0; i < arch_clk_tbl_array_size; i++, clk_tblp++) {
if (clk_tblp->con_id) {
if (!con_id || strcmp(clk_tblp->con_id, con_id))
continue;
return clk_tblp->clk;
}
}
return NULL;
}
/* Enable a clock */
int clk_enable(struct clk *c)
{
int ret = 0;
debug("%s: %s\n", __func__, c->name);
if (!c->ops || !c->ops->enable)
return -1;
/* enable parent clock first */
if (c->parent)
ret = clk_enable(c->parent);
if (ret)
return ret;
if (!c->use_cnt)
ret = c->ops->enable(c, 1);
c->use_cnt++;
return ret;
}
/* Disable a clock */
void clk_disable(struct clk *c)
{
debug("%s: %s\n", __func__, c->name);
if (!c->ops || !c->ops->enable)
return;
if (c->use_cnt > 0) {
c->use_cnt--;
if (c->use_cnt == 0)
c->ops->enable(c, 0);
}
/* disable parent */
if (c->parent)
clk_disable(c->parent);
}
/* Get the clock rate */
unsigned long clk_get_rate(struct clk *c)
{
unsigned long rate;
if (!c || !c->ops || !c->ops->get_rate)
return 0;
debug("%s: %s\n", __func__, c->name);
rate = c->ops->get_rate(c);
debug("%s: rate = %ld\n", __func__, rate);
return rate;
}
/* Set the clock rate */
int clk_set_rate(struct clk *c, unsigned long rate)
{
int ret;
if (!c || !c->ops || !c->ops->set_rate)
return -EINVAL;
debug("%s: %s rate=%ld\n", __func__, c->name, rate);
if (c->use_cnt)
return -EINVAL;
ret = c->ops->set_rate(c, rate);
return ret;
}
/* Not required for this arch */
/*
long clk_round_rate(struct clk *clk, unsigned long rate);
int clk_set_parent(struct clk *clk, struct clk *parent);
struct clk *clk_get_parent(struct clk *clk);
*/

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@@ -1,491 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2013 Broadcom Corporation.
*/
#include <linux/stddef.h>
#include <linux/stringify.h>
#ifdef CONFIG_CLK_DEBUG
#undef writel
#undef readl
static inline void writel(u32 val, void *addr)
{
printf("Write [0x%p] = 0x%08x\n", addr, val);
*(u32 *)addr = val;
}
static inline u32 readl(void *addr)
{
u32 val = *(u32 *)addr;
printf("Read [0x%p] = 0x%08x\n", addr, val);
return val;
}
#endif
struct clk;
struct clk_lookup {
const char *dev_id;
const char *con_id;
struct clk *clk;
};
extern struct clk_lookup arch_clk_tbl[];
extern unsigned int arch_clk_tbl_array_size;
/**
* struct clk_ops - standard clock operations
* @enable: enable/disable clock, see clk_enable() and clk_disable()
* @set_rate: set the clock rate, see clk_set_rate().
* @get_rate: get the clock rate, see clk_get_rate().
* @round_rate: round a given clock rate, see clk_round_rate().
* @set_parent: set the clock's parent, see clk_set_parent().
*
* Group the common clock implementations together so that we
* don't have to keep setting the same fiels again. We leave
* enable in struct clk.
*
*/
struct clk_ops {
int (*enable)(struct clk *c, int enable);
int (*set_rate)(struct clk *c, unsigned long rate);
unsigned long (*get_rate)(struct clk *c);
unsigned long (*round_rate)(struct clk *c, unsigned long rate);
int (*set_parent)(struct clk *c, struct clk *parent);
};
struct clk {
struct clk *parent;
const char *name;
int use_cnt;
unsigned long rate; /* in HZ */
/* programmable divider. 0 means fixed ratio to parent clock */
unsigned long div;
struct clk_src *src;
struct clk_ops *ops;
unsigned long ccu_clk_mgr_base;
int sel;
};
struct refclk *refclk_str_to_clk(const char *name);
/* The common clock framework uses u8 to represent a parent index */
#define PARENT_COUNT_MAX ((u32)U8_MAX)
#define BAD_CLK_INDEX U8_MAX /* Can't ever be valid */
#define BAD_CLK_NAME ((const char *)-1)
#define BAD_SCALED_DIV_VALUE U64_MAX
/*
* Utility macros for object flag management. If possible, flags
* should be defined such that 0 is the desired default value.
*/
#define FLAG(type, flag) BCM_CLK_ ## type ## _FLAGS_ ## flag
#define FLAG_SET(obj, type, flag) ((obj)->flags |= FLAG(type, flag))
#define FLAG_CLEAR(obj, type, flag) ((obj)->flags &= ~(FLAG(type, flag)))
#define FLAG_FLIP(obj, type, flag) ((obj)->flags ^= FLAG(type, flag))
#define FLAG_TEST(obj, type, flag) (!!((obj)->flags & FLAG(type, flag)))
/* Clock field state tests */
#define gate_exists(gate) FLAG_TEST(gate, GATE, EXISTS)
#define gate_is_enabled(gate) FLAG_TEST(gate, GATE, ENABLED)
#define gate_is_hw_controllable(gate) FLAG_TEST(gate, GATE, HW)
#define gate_is_sw_controllable(gate) FLAG_TEST(gate, GATE, SW)
#define gate_is_sw_managed(gate) FLAG_TEST(gate, GATE, SW_MANAGED)
#define gate_is_no_disable(gate) FLAG_TEST(gate, GATE, NO_DISABLE)
#define gate_flip_enabled(gate) FLAG_FLIP(gate, GATE, ENABLED)
#define divider_exists(div) FLAG_TEST(div, DIV, EXISTS)
#define divider_is_fixed(div) FLAG_TEST(div, DIV, FIXED)
#define divider_has_fraction(div) (!divider_is_fixed(div) && \
(div)->frac_width > 0)
#define selector_exists(sel) ((sel)->width != 0)
#define trigger_exists(trig) FLAG_TEST(trig, TRIG, EXISTS)
/* Clock type, used to tell common block what it's part of */
enum bcm_clk_type {
bcm_clk_none, /* undefined clock type */
bcm_clk_bus,
bcm_clk_core,
bcm_clk_peri
};
/*
* Gating control and status is managed by a 32-bit gate register.
*
* There are several types of gating available:
* - (no gate)
* A clock with no gate is assumed to be always enabled.
* - hardware-only gating (auto-gating)
* Enabling or disabling clocks with this type of gate is
* managed automatically by the hardware. Such clocks can be
* considered by the software to be enabled. The current status
* of auto-gated clocks can be read from the gate status bit.
* - software-only gating
* Auto-gating is not available for this type of clock.
* Instead, software manages whether it's enabled by setting or
* clearing the enable bit. The current gate status of a gate
* under software control can be read from the gate status bit.
* To ensure a change to the gating status is complete, the
* status bit can be polled to verify that the gate has entered
* the desired state.
* - selectable hardware or software gating
* Gating for this type of clock can be configured to be either
* under software or hardware control. Which type is in use is
* determined by the hw_sw_sel bit of the gate register.
*/
struct bcm_clk_gate {
u32 offset; /* gate register offset */
u32 status_bit; /* 0: gate is disabled; 0: gatge is enabled */
u32 en_bit; /* 0: disable; 1: enable */
u32 hw_sw_sel_bit; /* 0: hardware gating; 1: software gating */
u32 flags; /* BCM_CLK_GATE_FLAGS_* below */
};
/*
* Gate flags:
* HW means this gate can be auto-gated
* SW means the state of this gate can be software controlled
* NO_DISABLE means this gate is (only) enabled if under software control
* SW_MANAGED means the status of this gate is under software control
* ENABLED means this software-managed gate is *supposed* to be enabled
*/
#define BCM_CLK_GATE_FLAGS_EXISTS ((u32)1 << 0) /* Gate is valid */
#define BCM_CLK_GATE_FLAGS_HW ((u32)1 << 1) /* Can auto-gate */
#define BCM_CLK_GATE_FLAGS_SW ((u32)1 << 2) /* Software control */
#define BCM_CLK_GATE_FLAGS_NO_DISABLE ((u32)1 << 3) /* HW or enabled */
#define BCM_CLK_GATE_FLAGS_SW_MANAGED ((u32)1 << 4) /* SW now in control */
#define BCM_CLK_GATE_FLAGS_ENABLED ((u32)1 << 5) /* If SW_MANAGED */
/*
* Gate initialization macros.
*
* Any gate initially under software control will be enabled.
*/
/* A hardware/software gate initially under software control */
#define HW_SW_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \
{ \
.offset = (_offset), \
.status_bit = (_status_bit), \
.en_bit = (_en_bit), \
.hw_sw_sel_bit = (_hw_sw_sel_bit), \
.flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \
FLAG(GATE, SW_MANAGED)|FLAG(GATE, ENABLED)| \
FLAG(GATE, EXISTS), \
}
/* A hardware/software gate initially under hardware control */
#define HW_SW_GATE_AUTO(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \
{ \
.offset = (_offset), \
.status_bit = (_status_bit), \
.en_bit = (_en_bit), \
.hw_sw_sel_bit = (_hw_sw_sel_bit), \
.flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \
FLAG(GATE, EXISTS), \
}
/* A hardware-or-enabled gate (enabled if not under hardware control) */
#define HW_ENABLE_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \
{ \
.offset = (_offset), \
.status_bit = (_status_bit), \
.en_bit = (_en_bit), \
.hw_sw_sel_bit = (_hw_sw_sel_bit), \
.flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \
FLAG(GATE, NO_DISABLE)|FLAG(GATE, EXISTS), \
}
/* A software-only gate */
#define SW_ONLY_GATE(_offset, _status_bit, _en_bit) \
{ \
.offset = (_offset), \
.status_bit = (_status_bit), \
.en_bit = (_en_bit), \
.flags = FLAG(GATE, SW)|FLAG(GATE, SW_MANAGED)| \
FLAG(GATE, ENABLED)|FLAG(GATE, EXISTS), \
}
/* A hardware-only gate */
#define HW_ONLY_GATE(_offset, _status_bit) \
{ \
.offset = (_offset), \
.status_bit = (_status_bit), \
.flags = FLAG(GATE, HW)|FLAG(GATE, EXISTS), \
}
/*
* Each clock can have zero, one, or two dividers which change the
* output rate of the clock. Each divider can be either fixed or
* variable. If there are two dividers, they are the "pre-divider"
* and the "regular" or "downstream" divider. If there is only one,
* there is no pre-divider.
*
* A fixed divider is any non-zero (positive) value, and it
* indicates how the input rate is affected by the divider.
*
* The value of a variable divider is maintained in a sub-field of a
* 32-bit divider register. The position of the field in the
* register is defined by its offset and width. The value recorded
* in this field is always 1 less than the value it represents.
*
* In addition, a variable divider can indicate that some subset
* of its bits represent a "fractional" part of the divider. Such
* bits comprise the low-order portion of the divider field, and can
* be viewed as representing the portion of the divider that lies to
* the right of the decimal point. Most variable dividers have zero
* fractional bits. Variable dividers with non-zero fraction width
* still record a value 1 less than the value they represent; the
* added 1 does *not* affect the low-order bit in this case, it
* affects the bits above the fractional part only. (Often in this
* code a divider field value is distinguished from the value it
* represents by referring to the latter as a "divisor".)
*
* In order to avoid dealing with fractions, divider arithmetic is
* performed using "scaled" values. A scaled value is one that's
* been left-shifted by the fractional width of a divider. Dividing
* a scaled value by a scaled divisor produces the desired quotient
* without loss of precision and without any other special handling
* for fractions.
*
* The recorded value of a variable divider can be modified. To
* modify either divider (or both), a clock must be enabled (i.e.,
* using its gate). In addition, a trigger register (described
* below) must be used to commit the change, and polled to verify
* the change is complete.
*/
struct bcm_clk_div {
union {
struct { /* variable divider */
u32 offset; /* divider register offset */
u32 shift; /* field shift */
u32 width; /* field width */
u32 frac_width; /* field fraction width */
u64 scaled_div; /* scaled divider value */
};
u32 fixed; /* non-zero fixed divider value */
};
u32 flags; /* BCM_CLK_DIV_FLAGS_* below */
};
/*
* Divider flags:
* EXISTS means this divider exists
* FIXED means it is a fixed-rate divider
*/
#define BCM_CLK_DIV_FLAGS_EXISTS ((u32)1 << 0) /* Divider is valid */
#define BCM_CLK_DIV_FLAGS_FIXED ((u32)1 << 1) /* Fixed-value */
/* Divider initialization macros */
/* A fixed (non-zero) divider */
#define FIXED_DIVIDER(_value) \
{ \
.fixed = (_value), \
.flags = FLAG(DIV, EXISTS)|FLAG(DIV, FIXED), \
}
/* A divider with an integral divisor */
#define DIVIDER(_offset, _shift, _width) \
{ \
.offset = (_offset), \
.shift = (_shift), \
.width = (_width), \
.scaled_div = BAD_SCALED_DIV_VALUE, \
.flags = FLAG(DIV, EXISTS), \
}
/* A divider whose divisor has an integer and fractional part */
#define FRAC_DIVIDER(_offset, _shift, _width, _frac_width) \
{ \
.offset = (_offset), \
.shift = (_shift), \
.width = (_width), \
.frac_width = (_frac_width), \
.scaled_div = BAD_SCALED_DIV_VALUE, \
.flags = FLAG(DIV, EXISTS), \
}
/*
* Clocks may have multiple "parent" clocks. If there is more than
* one, a selector must be specified to define which of the parent
* clocks is currently in use. The selected clock is indicated in a
* sub-field of a 32-bit selector register. The range of
* representable selector values typically exceeds the number of
* available parent clocks. Occasionally the reset value of a
* selector field is explicitly set to a (specific) value that does
* not correspond to a defined input clock.
*
* We register all known parent clocks with the common clock code
* using a packed array (i.e., no empty slots) of (parent) clock
* names, and refer to them later using indexes into that array.
* We maintain an array of selector values indexed by common clock
* index values in order to map between these common clock indexes
* and the selector values used by the hardware.
*
* Like dividers, a selector can be modified, but to do so a clock
* must be enabled, and a trigger must be used to commit the change.
*/
struct bcm_clk_sel {
u32 offset; /* selector register offset */
u32 shift; /* field shift */
u32 width; /* field width */
u32 parent_count; /* number of entries in parent_sel[] */
u32 *parent_sel; /* array of parent selector values */
u8 clk_index; /* current selected index in parent_sel[] */
};
/* Selector initialization macro */
#define SELECTOR(_offset, _shift, _width) \
{ \
.offset = (_offset), \
.shift = (_shift), \
.width = (_width), \
.clk_index = BAD_CLK_INDEX, \
}
/*
* Making changes to a variable divider or a selector for a clock
* requires the use of a trigger. A trigger is defined by a single
* bit within a register. To signal a change, a 1 is written into
* that bit. To determine when the change has been completed, that
* trigger bit is polled; the read value will be 1 while the change
* is in progress, and 0 when it is complete.
*
* Occasionally a clock will have more than one trigger. In this
* case, the "pre-trigger" will be used when changing a clock's
* selector and/or its pre-divider.
*/
struct bcm_clk_trig {
u32 offset; /* trigger register offset */
u32 bit; /* trigger bit */
u32 flags; /* BCM_CLK_TRIG_FLAGS_* below */
};
/*
* Trigger flags:
* EXISTS means this trigger exists
*/
#define BCM_CLK_TRIG_FLAGS_EXISTS ((u32)1 << 0) /* Trigger is valid */
/* Trigger initialization macro */
#define TRIGGER(_offset, _bit) \
{ \
.offset = (_offset), \
.bit = (_bit), \
.flags = FLAG(TRIG, EXISTS), \
}
struct bus_clk_data {
struct bcm_clk_gate gate;
};
struct core_clk_data {
struct bcm_clk_gate gate;
};
struct peri_clk_data {
struct bcm_clk_gate gate;
struct bcm_clk_trig pre_trig;
struct bcm_clk_div pre_div;
struct bcm_clk_trig trig;
struct bcm_clk_div div;
struct bcm_clk_sel sel;
const char *clocks[]; /* must be last; use CLOCKS() to declare */
};
#define CLOCKS(...) { __VA_ARGS__, NULL, }
#define NO_CLOCKS { NULL, } /* Must use of no parent clocks */
struct refclk {
struct clk clk;
};
struct peri_clock {
struct clk clk;
struct peri_clk_data *data;
};
struct ccu_clock {
struct clk clk;
int num_policy_masks;
unsigned long policy_freq_offset;
int freq_bit_shift; /* 8 for most CCUs */
unsigned long policy_ctl_offset;
unsigned long policy0_mask_offset;
unsigned long policy1_mask_offset;
unsigned long policy2_mask_offset;
unsigned long policy3_mask_offset;
unsigned long policy0_mask2_offset;
unsigned long policy1_mask2_offset;
unsigned long policy2_mask2_offset;
unsigned long policy3_mask2_offset;
unsigned long lvm_en_offset;
int freq_id;
unsigned long *freq_tbl;
};
struct bus_clock {
struct clk clk;
struct bus_clk_data *data;
unsigned long *freq_tbl;
};
struct ref_clock {
struct clk clk;
};
static inline int is_same_clock(struct clk *a, struct clk *b)
{
return a == b;
}
#define to_clk(p) (&((p)->clk))
#define name_to_clk(name) (&((name##_clk).clk))
/* declare a struct clk_lookup */
#define CLK_LK(name) \
{.con_id = __stringify(name##_clk), .clk = name_to_clk(name),}
static inline struct refclk *to_refclk(struct clk *clock)
{
return container_of(clock, struct refclk, clk);
}
static inline struct peri_clock *to_peri_clk(struct clk *clock)
{
return container_of(clock, struct peri_clock, clk);
}
static inline struct ccu_clock *to_ccu_clk(struct clk *clock)
{
return container_of(clock, struct ccu_clock, clk);
}
static inline struct bus_clock *to_bus_clk(struct clk *clock)
{
return container_of(clock, struct bus_clock, clk);
}
static inline struct ref_clock *to_ref_clk(struct clk *clock)
{
return container_of(clock, struct ref_clock, clk);
}
extern struct clk_ops peri_clk_ops;
extern struct clk_ops ccu_clk_ops;
extern struct clk_ops bus_clk_ops;
extern struct clk_ops ref_clk_ops;
int clk_get_and_enable(char *clkstr);

View File

@@ -1,142 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Broadcom Corporation.
*/
#include <asm/io.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <asm/arch/sysmap.h>
#include <asm/kona-common/clk.h>
#include "clk-core.h"
#define WR_ACCESS_ADDR ESUB_CLK_BASE_ADDR
#define WR_ACCESS_PASSWORD 0xA5A500
#define PLLE_POST_RESETB_ADDR (ESUB_CLK_BASE_ADDR + 0x00000C00)
#define PLLE_RESETB_ADDR (ESUB_CLK_BASE_ADDR + 0x00000C58)
#define PLLE_RESETB_I_PLL_RESETB_PLLE_MASK 0x00010000
#define PLLE_POST_RESETB_I_POST_RESETB_PLLE_MASK 0x00000001
#define PLL_LOCK_ADDR (ESUB_CLK_BASE_ADDR + 0x00000C38)
#define PLL_LOCK_PLL_LOCK_PLLE_MASK 0x00000001
#define ESW_SYS_DIV_ADDR (ESUB_CLK_BASE_ADDR + 0x00000A04)
#define ESW_SYS_DIV_PLL_SELECT_MASK 0x00000300
#define ESW_SYS_DIV_DIV_MASK 0x0000001C
#define ESW_SYS_DIV_PLL_VAR_208M_CLK_SELECT 0x00000100
#define ESW_SYS_DIV_DIV_SELECT 0x4
#define ESW_SYS_DIV_TRIGGER_MASK 0x00000001
#define ESUB_AXI_DIV_DEBUG_ADDR (ESUB_CLK_BASE_ADDR + 0x00000E04)
#define ESUB_AXI_DIV_DEBUG_PLL_SELECT_MASK 0x0000001C
#define ESUB_AXI_DIV_DEBUG_PLL_SELECT_OVERRIDE_MASK 0x00000040
#define ESUB_AXI_DIV_DEBUG_PLL_VAR_208M_CLK_SELECT 0x0
#define ESUB_AXI_DIV_DEBUG_TRIGGER_MASK 0x00000001
#define PLL_MAX_RETRY 100
/* Enable appropriate clocks for Ethernet */
int clk_eth_enable(void)
{
int rc = -1;
int retry_count = 0;
rc = clk_get_and_enable("esub_ccu_clk");
/* Enable Access to CCU registers */
writel((1 | WR_ACCESS_PASSWORD), WR_ACCESS_ADDR);
writel(readl(PLLE_POST_RESETB_ADDR) &
~PLLE_POST_RESETB_I_POST_RESETB_PLLE_MASK,
PLLE_POST_RESETB_ADDR);
/* Take PLL out of reset and put into normal mode */
writel(readl(PLLE_RESETB_ADDR) | PLLE_RESETB_I_PLL_RESETB_PLLE_MASK,
PLLE_RESETB_ADDR);
/* Wait for PLL lock */
rc = -1;
while (retry_count < PLL_MAX_RETRY) {
udelay(100);
if (readl(PLL_LOCK_ADDR) & PLL_LOCK_PLL_LOCK_PLLE_MASK) {
rc = 0;
break;
}
retry_count++;
}
if (rc == -1) {
printf("%s: ETH-PLL lock timeout, Ethernet is not enabled!\n",
__func__);
return -1;
}
writel(readl(PLLE_POST_RESETB_ADDR) |
PLLE_POST_RESETB_I_POST_RESETB_PLLE_MASK,
PLLE_POST_RESETB_ADDR);
/* Switch esw_sys_clk to use 104MHz(208MHz/2) clock */
writel((readl(ESW_SYS_DIV_ADDR) &
~(ESW_SYS_DIV_PLL_SELECT_MASK | ESW_SYS_DIV_DIV_MASK)) |
ESW_SYS_DIV_PLL_VAR_208M_CLK_SELECT | ESW_SYS_DIV_DIV_SELECT,
ESW_SYS_DIV_ADDR);
writel(readl(ESW_SYS_DIV_ADDR) | ESW_SYS_DIV_TRIGGER_MASK,
ESW_SYS_DIV_ADDR);
/* Wait for trigger complete */
rc = -1;
retry_count = 0;
while (retry_count < PLL_MAX_RETRY) {
udelay(100);
if (!(readl(ESW_SYS_DIV_ADDR) & ESW_SYS_DIV_TRIGGER_MASK)) {
rc = 0;
break;
}
retry_count++;
}
if (rc == -1) {
printf("%s: SYS CLK Trigger timeout, Ethernet is not enabled!\n",
__func__);
return -1;
}
/* switch Esub AXI clock to 208MHz */
writel((readl(ESUB_AXI_DIV_DEBUG_ADDR) &
~(ESUB_AXI_DIV_DEBUG_PLL_SELECT_MASK |
ESUB_AXI_DIV_DEBUG_PLL_SELECT_OVERRIDE_MASK |
ESUB_AXI_DIV_DEBUG_TRIGGER_MASK)) |
ESUB_AXI_DIV_DEBUG_PLL_VAR_208M_CLK_SELECT |
ESUB_AXI_DIV_DEBUG_PLL_SELECT_OVERRIDE_MASK,
ESUB_AXI_DIV_DEBUG_ADDR);
writel(readl(ESUB_AXI_DIV_DEBUG_ADDR) |
ESUB_AXI_DIV_DEBUG_TRIGGER_MASK,
ESUB_AXI_DIV_DEBUG_ADDR);
/* Wait for trigger complete */
rc = -1;
retry_count = 0;
while (retry_count < PLL_MAX_RETRY) {
udelay(100);
if (!(readl(ESUB_AXI_DIV_DEBUG_ADDR) &
ESUB_AXI_DIV_DEBUG_TRIGGER_MASK)) {
rc = 0;
break;
}
retry_count++;
}
if (rc == -1) {
printf("%s: AXI CLK Trigger timeout, Ethernet is not enabled!\n",
__func__);
return -1;
}
/* Disable Access to CCU registers */
writel(WR_ACCESS_PASSWORD, WR_ACCESS_ADDR);
return rc;
}

View File

@@ -1,71 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2013 Broadcom Corporation.
*/
#include <asm/io.h>
#include <linux/errno.h>
#include <asm/arch/sysmap.h>
#include <asm/kona-common/clk.h>
#include "clk-core.h"
/* Enable appropriate clocks for an SDIO port */
int clk_sdio_enable(void *base, u32 rate, u32 *actual_ratep)
{
int ret;
struct clk *c;
char *clkstr;
char *slpstr;
char *ahbstr;
switch ((u32) base) {
case CONFIG_SYS_SDIO_BASE0:
clkstr = CONFIG_SYS_SDIO0 "_clk";
ahbstr = CONFIG_SYS_SDIO0 "_ahb_clk";
slpstr = CONFIG_SYS_SDIO0 "_sleep_clk";
break;
case CONFIG_SYS_SDIO_BASE1:
clkstr = CONFIG_SYS_SDIO1 "_clk";
ahbstr = CONFIG_SYS_SDIO1 "_ahb_clk";
slpstr = CONFIG_SYS_SDIO1 "_sleep_clk";
break;
case CONFIG_SYS_SDIO_BASE2:
clkstr = CONFIG_SYS_SDIO2 "_clk";
ahbstr = CONFIG_SYS_SDIO2 "_ahb_clk";
slpstr = CONFIG_SYS_SDIO2 "_sleep_clk";
break;
case CONFIG_SYS_SDIO_BASE3:
clkstr = CONFIG_SYS_SDIO3 "_clk";
ahbstr = CONFIG_SYS_SDIO3 "_ahb_clk";
slpstr = CONFIG_SYS_SDIO3 "_sleep_clk";
break;
default:
printf("%s: base 0x%p not found\n", __func__, base);
return -EINVAL;
}
ret = clk_get_and_enable(ahbstr);
if (ret)
return ret;
ret = clk_get_and_enable(slpstr);
if (ret)
return ret;
c = clk_get(clkstr);
if (c) {
ret = clk_set_rate(c, rate);
if (ret)
return ret;
ret = clk_enable(c);
if (ret)
return ret;
} else {
printf("%s: Couldn't find %s\n", __func__, clkstr);
return -EINVAL;
}
*actual_ratep = rate;
return 0;
}

View File

@@ -1,25 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Broadcom Corporation.
*/
#include <linux/errno.h>
#include <asm/arch/sysmap.h>
#include "clk-core.h"
/* Enable appropriate clocks for the USB OTG port */
int clk_usb_otg_enable(void *base)
{
char *ahbstr;
switch ((u32) base) {
case HSOTG_BASE_ADDR:
ahbstr = "usb_otg_ahb_clk";
break;
default:
printf("%s: base 0x%p not found\n", __func__, base);
return -EINVAL;
}
return clk_get_and_enable(ahbstr);
}

View File

@@ -57,7 +57,7 @@ void reset_cpu(void)
| V7M_AIRCR_SYSRESET, &V7M_SCB->aircr);
}
void spl_perform_fixups(struct spl_image_info *spl_image)
void spl_perform_arch_fixups(struct spl_image_info *spl_image)
{
spl_image->entry_point |= 0x1;
}

View File

@@ -58,6 +58,60 @@ static int get_effective_el(void)
return el;
}
int mem_map_from_dram_banks(unsigned int index, unsigned int len, u64 attrs)
{
unsigned int i;
int ret = fdtdec_setup_memory_banksize();
if (ret) {
log_err("%s: Failed to setup dram banks\n", __func__);
return ret;
}
if (index + CONFIG_NR_DRAM_BANKS >= len) {
log_err("%s: Provided mem_map array has insufficient size for DRAM entries\n",
__func__);
return -ENOMEM;
}
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
mem_map[index].virt = gd->bd->bi_dram[i].start;
mem_map[index].phys = gd->bd->bi_dram[i].start;
mem_map[index].size = gd->bd->bi_dram[i].size;
mem_map[index].attrs = attrs;
index++;
}
memset(&mem_map[index], 0, sizeof(mem_map[index]));
return 0;
}
int mmu_unmap_reserved_mem(const char *name, bool check_nomap)
{
void *fdt = (void *)gd->fdt_blob;
char node_path[128];
fdt_addr_t addr;
fdt_size_t size;
int ret;
snprintf(node_path, sizeof(node_path), "/reserved-memory/%s", name);
ret = fdt_path_offset(fdt, node_path);
if (ret < 0)
return ret;
if (check_nomap && !fdtdec_get_bool(fdt, ret, "no-map"))
return -EINVAL;
addr = fdtdec_get_addr_size(fdt, ret, "reg", &size);
if (addr == FDT_ADDR_T_NONE)
return -1;
mmu_change_region_attr_nobreak(addr, size, PTE_TYPE_FAULT);
return 0;
}
u64 get_tcr(u64 *pips, u64 *pva_bits)
{
int el = get_effective_el();
@@ -830,16 +884,15 @@ void flush_dcache_range(unsigned long start, unsigned long stop)
void dcache_enable(void)
{
/* The data cache is not active unless the mmu is enabled */
if (!(get_sctlr() & CR_M)) {
invalidate_dcache_all();
__asm_invalidate_tlb_all();
if (!mmu_status())
mmu_setup();
}
/* Set up page tables only once (it is done also by mmu_setup()) */
if (!gd->arch.tlb_fillptr)
setup_all_pgtables();
invalidate_dcache_all();
__asm_invalidate_tlb_all();
set_sctlr(get_sctlr() | CR_C);
}
@@ -1134,11 +1187,6 @@ int icache_status(void)
return (get_sctlr() & CR_I) != 0;
}
int mmu_status(void)
{
return (get_sctlr() & CR_M) != 0;
}
void invalidate_icache_all(void)
{
__asm_invalidate_icache_all();
@@ -1160,17 +1208,17 @@ int icache_status(void)
return 0;
}
int mmu_status(void)
{
return 0;
}
void invalidate_icache_all(void)
{
}
#endif /* !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) */
int mmu_status(void)
{
return (get_sctlr() & CR_M) != 0;
}
/*
* Enable dCache & iCache, whether cache is actually enabled
* depend on CONFIG_SYS_DCACHE_OFF and CONFIG_SYS_ICACHE_OFF

View File

@@ -387,23 +387,18 @@ ENDPROC(c_runtime_cpu_setup)
WEAK(save_boot_params)
#if (IS_ENABLED(CONFIG_BLOBLIST))
/* Calculate the PC-relative address of saved_args */
adr x9, saved_args_offset
ldr w10, saved_args_offset
add x9, x9, w10, sxtw
stp x0, x1, [x9]
stp x2, x3, [x9, #16]
adrp x9, saved_args
add x9, x9, :lo12:saved_args
stp x0, x1, [x9]
stp x2, x3, [x9, #16]
#endif
b save_boot_params_ret /* back to my caller */
ENDPROC(save_boot_params)
#if (IS_ENABLED(CONFIG_BLOBLIST))
saved_args_offset:
.long saved_args - . /* offset from current code to save_args */
.section .data
.align 2
.global saved_args
.section .data
.align 2
.global saved_args
saved_args:
.rept 4
.dword 0

View File

@@ -650,8 +650,6 @@ dtb-$(CONFIG_MACH_SUN8I_R40) += \
sun8i-r40-oka40i-c.dtb \
sun8i-t3-cqa3t-bv3.dtb \
sun8i-v40-bananapi-m2-berry.dtb
dtb-$(CONFIG_MACH_SUN8I_R528) += \
sun8i-t113s-mangopi-mq-r-t113.dtb
dtb-$(CONFIG_MACH_SUN50I_H5) += \
sun50i-h5-bananapi-m2-plus.dtb \
sun50i-h5-emlid-neutis-n5-devboard.dtb \
@@ -693,8 +691,6 @@ dtb-$(CONFIG_MACH_SUN50I) += \
sun50i-a64-sopine-baseboard.dtb \
sun50i-a64-teres-i.dtb
dtb-$(CONFIG_MACH_SUN9I) += \
sun9i-a80-optimus.dtb \
sun9i-a80-cubieboard4.dtb \
sun9i-a80-cx-a99.dtb
dtb-$(CONFIG_VF610) += vf610-colibri-eval-v3.dtb \
@@ -835,9 +831,7 @@ dtb-$(CONFIG_MX6UL) += \
imx6ul-liteboard.dtb \
imx6ul-phytec-segin-ff-rdk-nand.dtb \
imx6ul-pico-hobbit.dtb \
imx6ul-pico-pi.dtb \
imx6ul-kontron-bl.dtb \
imx6ull-kontron-bl.dtb
imx6ul-pico-pi.dtb
dtb-$(CONFIG_MX6ULL) += \
imx6ull-14x14-evk.dtb \
@@ -893,8 +887,6 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mm-data-modul-edm-sbc.dtb \
imx8mm-icore-mx8mm-ctouch2.dtb \
imx8mm-icore-mx8mm-edimm2.2.dtb \
imx8mm-kontron-bl.dtb \
imx8mm-kontron-bl-osm-s.dtb \
imx8mm-mx8menlo.dtb \
imx8mm-phg.dtb \
imx8mq-cm.dtb \
@@ -1111,9 +1103,10 @@ dtb-$(CONFIG_SOC_K3_AM62A7) += \
k3-am62a7-r5-sk.dtb \
k3-am62a7-r5-phycore-som-2gb.dtb
dtb-$(CONFIG_SOC_K3_AM62D2) += k3-am62d2-r5-evm.dtb
dtb-$(CONFIG_SOC_K3_AM62P5) += k3-am62p5-r5-sk.dtb \
k3-am62p5-verdin-r5.dtb \
k3-am62p5-verdin-wifi-dev.dtb
k3-am62p5-verdin-r5.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt7622-rfb.dtb \

View File

@@ -102,9 +102,9 @@
status = "okay";
max8997-pmic@66 {
compatible = "maxim,max8997";
compatible = "maxim,max8997-pmic";
reg = <0x66 0 0>;
voltage-regulators {
regulators {
valive_reg: LDO2 {
regulator-name = "VALIVE_1.1V_C210";
regulator-min-microvolt = <1100000>;

View File

@@ -77,7 +77,7 @@
max8998-pmic@66 {
compatible = "maxim,max8998";
reg = <0x66 0 0>;
voltage-regulators {
regulators {
ldo2_reg: LDO2 {
regulator-name = "VALIVE_1.2V";
regulator-min-microvolt = <1200000>;

View File

@@ -40,7 +40,7 @@
s2mps11_pmic@66 {
compatible = "samsung,s2mps11-pmic";
reg = <0x66>;
voltage-regulators {
regulators {
ldo1_reg: LDO1 {
regulator-name = "vdd_ldo1";
regulator-min-microvolt = <1000000>;

View File

@@ -1,103 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2017 exceet electronics GmbH
* Copyright (C) 2018 Kontron Electronics GmbH
* Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
*/
#include "imx6ul-kontron-bl.dts"
/ {
model = "Kontron BL i.MX6UL 43 (N631X S 43)";
compatible = "kontron,bl-imx6ul-43", "kontron,bl-imx6ul",
"kontron,sl-imx6ul", "fsl,imx6ul";
backlight {
compatible = "pwm-backlight";
pwms = <&pwm7 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <6>;
status = "okay";
};
};
&i2c4 {
touchscreen@5d {
compatible = "goodix,gt928";
reg = <0x5d>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_cap_touch>;
interrupt-parent = <&gpio5>;
interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>;
irq-gpios = <&gpio5 6 GPIO_ACTIVE_HIGH>;
};
};
&lcdif {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcdif_dat &pinctrl_lcdif_ctrl>;
/* Leave status disabled because of missing display panel node */
};
&pwm7 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm7>;
status = "okay";
};
&iomuxc {
pinctrl_cap_touch: captouchgrp {
fsl,pins = <
MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x1b0b0 /* Touch Interrupt */
MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x1b0b0 /* Touch Reset */
MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x1b0b0 /* Touch Wake */
>;
};
pinctrl_lcdif_ctrl: lcdifctrlgrp {
fsl,pins = <
MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
MX6UL_PAD_LCD_RESET__LCDIF_RESET 0x79
>;
};
pinctrl_lcdif_dat: lcdifdatgrp {
fsl,pins = <
MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79
MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79
MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79
MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79
MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79
MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79
>;
};
pinctrl_pwm7: pwm7grp {
fsl,pins = <
MX6UL_PAD_CSI_VSYNC__PWM7_OUT 0x110b0
>;
};
};

View File

@@ -30,9 +30,6 @@
* in Linux we can't assign the shared reset GPIO to the PHYs, as this
* would cause Linux to reset both PHYs every time one of them gets
* reinitialized.
*
* Also we disable the second ethernet as it currently doesn't work with
* the devicetree setup in U-Boot.
*/
&fec1 {
@@ -53,11 +50,16 @@
clocks = <&clks IMX6UL_CLK_ENET_REF>;
clock-names = "rmii-ref";
};
ethphy2: ethernet-phy@2 {
reg = <2>;
micrel,led-mode = <0>;
clocks = <&clks IMX6UL_CLK_ENET2_REF>;
clock-names = "rmii-ref";
};
};
};
&fec2 {
status = "disabled";
/delete-property/ phy-handle;
/delete-node/ mdio;
};

View File

@@ -1,406 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2017 exceet electronics GmbH
* Copyright (C) 2018 Kontron Electronics GmbH
* Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
*/
#include <dt-bindings/gpio/gpio.h>
/ {
gpio-leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
led1 {
label = "debug-led1";
gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
default-state = "off";
linux,default-trigger = "heartbeat";
};
led2 {
label = "debug-led2";
gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
default-state = "off";
};
led3 {
label = "debug-led3";
gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
default-state = "off";
};
};
pwm-beeper {
compatible = "pwm-beeper";
pwms = <&pwm8 0 5000>;
};
reg_3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
reg_5v: regulator-5v {
compatible = "regulator-fixed";
regulator-name = "5v";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_otg1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_vref_adc: regulator-vref-adc {
compatible = "regulator-fixed";
regulator-name = "vref-adc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
&adc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_adc1>;
num-channels = <3>;
vref-supply = <&reg_vref_adc>;
status = "okay";
};
&can2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
status = "okay";
};
&ecspi1 {
cs-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
eeprom@0 {
compatible = "anvo,anv32e61w", "atmel,at25";
reg = <0>;
spi-max-frequency = <20000000>;
spi-cpha;
spi-cpol;
pagesize = <1>;
size = <8192>;
address-width = <16>;
};
};
&fec1 {
pinctrl-0 = <&pinctrl_enet1>;
/delete-node/ mdio;
};
&fec2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio>;
phy-mode = "rmii";
phy-handle = <&ethphy2>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy1: ethernet-phy@1 {
reg = <1>;
micrel,led-mode = <0>;
clocks = <&clks IMX6UL_CLK_ENET_REF>;
clock-names = "rmii-ref";
};
ethphy2: ethernet-phy@2 {
reg = <2>;
micrel,led-mode = <0>;
clocks = <&clks IMX6UL_CLK_ENET2_REF>;
clock-names = "rmii-ref";
};
};
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
};
&i2c4 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
status = "okay";
rtc@32 {
compatible = "epson,rx8900";
reg = <0x32>;
};
};
&pwm8 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm8>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
linux,rs485-enabled-at-boot-time;
rs485-rx-during-tx;
rs485-rts-active-low;
uart-has-rtscts;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
uart-has-rtscts;
status = "okay";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
status = "okay";
};
&usbotg1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg1>;
dr_mode = "otg";
srp-disable;
hnp-disable;
adp-disable;
over-current-active-low;
vbus-supply = <&reg_usb_otg1_vbus>;
status = "okay";
};
&usbotg2 {
dr_mode = "host";
disable-over-current;
vbus-supply = <&reg_5v>;
status = "okay";
};
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
keep-power-in-suspend;
wakeup-source;
vmmc-supply = <&reg_3v3>;
voltage-ranges = <3300 3300>;
no-1-8-v;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
non-removable;
keep-power-in-suspend;
wakeup-source;
vmmc-supply = <&reg_3v3>;
voltage-ranges = <3300 3300>;
no-1-8-v;
status = "okay";
};
&iomuxc {
pinctrl-0 = <&pinctrl_reset_out &pinctrl_gpio>;
pinctrl_adc1: adc1grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0xb0
>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x100b1
MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x100b1
MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x100b1
MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x100b1 /* ECSPI1-CS1 */
>;
};
pinctrl_enet2: enet2grp {
fsl,pins = <
MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b009
>;
};
pinctrl_enet2_mdio: enet2mdiogrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
>;
};
pinctrl_flexcan2: flexcan2grp{
fsl,pins = <
MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
>;
};
pinctrl_gpio: gpiogrp {
fsl,pins = <
MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* DOUT1 */
MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* DIN1 */
MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x1b0b0 /* DOUT2 */
MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* DIN2 */
>;
};
pinctrl_gpio_leds: gpioledsgrp {
fsl,pins = <
MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b0b0 /* LED H14 */
MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x1b0b0 /* LED H15 */
MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* LED H16 */
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0
MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x4001f8b0
MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x4001f8b0
>;
};
pinctrl_pwm8: pwm8grp {
fsl,pins = <
MX6UL_PAD_CSI_HSYNC__PWM8_OUT 0x110b0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6UL_PAD_NAND_DATA04__UART2_DCE_TX 0x1b0b1
MX6UL_PAD_NAND_DATA05__UART2_DCE_RX 0x1b0b1
MX6UL_PAD_NAND_DATA06__UART2_DCE_CTS 0x1b0b1
/*
* mux unused RTS to make sure it doesn't cause
* any interrupts when it is undefined
*/
MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS 0x1b0b1
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1
MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1
MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b1
MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x1b0b1
MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x1b0b1
>;
};
pinctrl_usbotg1: usbotg1 {
fsl,pins = <
MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x1b0b0
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x100b1 /* SD1_CD */
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
>;
};
};

View File

@@ -1,16 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2017 exceet electronics GmbH
* Copyright (C) 2018 Kontron Electronics GmbH
* Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
*/
/dts-v1/;
#include "imx6ul-kontron-sl.dtsi"
#include "imx6ul-kontron-bl-common.dtsi"
/ {
model = "Kontron BL i.MX6UL (N631X S)";
compatible = "kontron,bl-imx6ul", "kontron,sl-imx6ul", "fsl,imx6ul";
};

View File

@@ -1,137 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2017 exceet electronics GmbH
* Copyright (C) 2018 Kontron Electronics GmbH
* Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
*/
#include <dt-bindings/gpio/gpio.h>
/ {
chosen {
stdout-path = &uart4;
};
memory@80000000 {
reg = <0x80000000 0x10000000>;
device_type = "memory";
};
};
&ecspi2 {
cs-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
status = "okay";
flash@0 {
compatible = "mxicy,mx25v8035f", "jedec,spi-nor";
spi-max-frequency = <50000000>;
reg = <0>;
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio>;
phy-mode = "rmii";
phy-handle = <&ethphy1>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy1: ethernet-phy@1 {
reg = <1>;
micrel,led-mode = <0>;
clocks = <&clks IMX6UL_CLK_ENET_REF>;
clock-names = "rmii-ref";
};
};
};
&fec2 {
phy-mode = "rmii";
status = "disabled";
};
&qspi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi>;
status = "okay";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-nand";
spi-max-frequency = <104000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
reg = <0>;
};
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reset_out>;
pinctrl_ecspi2: ecspi2grp {
fsl,pins = <
MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x100b1
MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x100b1
MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x100b1
MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x100b1
>;
};
pinctrl_enet1: enet1grp {
fsl,pins = <
MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b009
>;
};
pinctrl_enet1_mdio: enet1mdiogrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
>;
};
pinctrl_qspi: qspigrp {
fsl,pins = <
MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1
MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1
MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1
MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1
MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1
>;
};
pinctrl_reset_out: rstoutgrp {
fsl,pins = <
MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY 0x18b0
>;
};
};

View File

@@ -1,14 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2017 exceet electronics GmbH
* Copyright (C) 2018 Kontron Electronics GmbH
* Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
*/
#include "imx6ul.dtsi"
#include "imx6ul-kontron-sl-common.dtsi"
/ {
model = "Kontron SL i.MX6UL (N631X SOM)";
compatible = "kontron,sl-imx6ul", "fsl,imx6ul";
};

View File

@@ -1,15 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2017 exceet electronics GmbH
* Copyright (C) 2019 Kontron Electronics GmbH
*/
/dts-v1/;
#include "imx6ull-kontron-sl.dtsi"
#include "imx6ul-kontron-bl-common.dtsi"
/ {
model = "Kontron BL i.MX6ULL (N641X S)";
compatible = "kontron,bl-imx6ull", "kontron,sl-imx6ull", "fsl,imx6ull";
};

View File

@@ -1,13 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2017 exceet electronics GmbH
* Copyright (C) 2018 Kontron Electronics GmbH
*/
#include "imx6ull.dtsi"
#include "imx6ul-kontron-sl-common.dtsi"
/ {
model = "Kontron SL i.MX6ULL (N641X SOM)";
compatible = "kontron,sl-imx6ull", "fsl,imx6ull";
};

View File

@@ -18,6 +18,10 @@
};
};
&aips4 {
bootph-pre-ram;
};
&i2c1 {
bootph-pre-ram;
bootph-all;
@@ -108,6 +112,18 @@
bootph-all;
};
&usbmisc1 {
bootph-pre-ram;
};
&usbphynop1 {
bootph-pre-ram;
};
&usbotg1 {
bootph-pre-ram;
};
&usdhc1 {
bootph-pre-ram;
};

View File

@@ -1,376 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright (C) 2022 Kontron Electronics GmbH
*/
/dts-v1/;
#include "imx8mm-kontron-osm-s.dtsi"
/ {
model = "Kontron BL i.MX8MM OSM-S (N802X S)";
compatible = "kontron,imx8mm-bl-osm-s", "kontron,imx8mm-osm-s", "fsl,imx8mm";
aliases {
ethernet1 = &usbnet;
};
/* fixed crystal dedicated to mcp2542fd */
osc_can: clock-osc-can {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <40000000>;
clock-output-names = "osc-can";
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_led>;
led1 {
label = "led1";
gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
};
led2 {
label = "led2";
gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
};
led3 {
label = "led3";
gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
};
};
pwm-beeper {
compatible = "pwm-beeper";
pwms = <&pwm2 0 5000 0>;
};
reg_rst_eth2: regulator-rst-eth2 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_eth2>;
gpio = <&gpio3 2 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
regulator-name = "rst-usb-eth2";
};
reg_usb1_vbus: regulator-usb1-vbus {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usb1_vbus>;
gpio = <&gpio3 25 GPIO_ACTIVE_LOW>;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-name = "usb1-vbus";
};
reg_vdd_5v: regulator-5v {
compatible = "regulator-fixed";
regulator-always-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-name = "vdd-5v";
};
};
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
status = "okay";
can@0 {
compatible = "microchip,mcp251xfd";
reg = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can>;
clocks = <&osc_can>;
interrupts-extended = <&gpio4 28 IRQ_TYPE_LEVEL_LOW>;
/*
* Limit the SPI clock to 15 MHz to prevent issues
* with corrupted data due to chip errata.
*/
spi-max-frequency = <15000000>;
vdd-supply = <&reg_vdd_3v3>;
xceiver-supply = <&reg_vdd_5v>;
};
};
&ecspi3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi3>;
cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
status = "okay";
eeram@0 {
compatible = "microchip,48l640";
reg = <0>;
spi-max-frequency = <20000000>;
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-connection-type = "rgmii-rxid";
phy-handle = <&ethphy>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy: ethernet-phy@0 {
reg = <0>;
reset-assert-us = <1>;
reset-deassert-us = <15000>;
reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
};
};
};
&gpio1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio1>;
gpio-line-names = "", "", "", "dio1-out", "", "", "dio1-in", "dio2-out",
"dio2-in", "dio3-out", "dio3-in", "dio4-out", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
};
&gpio5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio5>;
gpio-line-names = "", "", "dio4-in", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
};
&i2c4 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
status = "okay";
};
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
uart-has-rtscts;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
linux,rs485-enabled-at-boot-time;
uart-has-rtscts;
status = "okay";
};
&usbotg1 {
dr_mode = "otg";
disable-over-current;
vbus-supply = <&reg_usb1_vbus>;
status = "okay";
};
&usbotg2 {
dr_mode = "host";
disable-over-current;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
usb1@1 {
compatible = "usb424,9514";
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
usbnet: ethernet@1 {
compatible = "usb424,ec00";
reg = <1>;
local-mac-address = [ 00 00 00 00 00 00 ];
};
};
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
vmmc-supply = <&reg_vdd_3v3>;
vqmmc-supply = <&reg_nvcc_sd>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
status = "okay";
};
&iomuxc {
pinctrl_can: cangrp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19
>;
};
pinctrl_ecspi2: ecspi2grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82
MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82
MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82
MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x19
>;
};
pinctrl_ecspi3: ecspi3grp {
fsl,pins = <
MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x82
MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x82
MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x82
MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x19
>;
};
pinctrl_enet: enetgrp {
fsl,pins = <
MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x19 /* PHY RST */
MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 /* ETH IRQ */
>;
};
pinctrl_gpio_led: gpioledgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x19
MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19
MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x19
>;
};
pinctrl_gpio1: gpio1grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19
MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19
MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19
MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19
MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19
MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19
>;
};
pinctrl_gpio5: gpio5grp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
>;
};
pinctrl_pwm2: pwm2grp {
fsl,pins = <
MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x19
>;
};
pinctrl_reg_usb1_vbus: regusb1vbusgrp {
fsl,pins = <
MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x140
MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x140
MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x140
MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x140
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140
MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140
MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140
MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140
>;
};
pinctrl_usb_eth2: usbeth2grp {
fsl,pins = <
MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
};

View File

@@ -1,355 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright (C) 2019 Kontron Electronics GmbH
*/
/dts-v1/;
#include "imx8mm-kontron-sl.dtsi"
/ {
model = "Kontron BL i.MX8MM (N801X S)";
compatible = "kontron,imx8mm-bl", "kontron,imx8mm-sl", "fsl,imx8mm";
aliases {
ethernet1 = &usbnet;
rtc0 = &rx8900;
rtc1 = &snvs_rtc;
};
/* fixed crystal dedicated to mcp2515 */
osc_can: clock-osc-can {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <16000000>;
clock-output-names = "osc-can";
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_led>;
led1 {
label = "led1";
gpios = <&gpio4 17 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
};
led2 {
label = "led2";
gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
};
led3 {
label = "led3";
gpios = <&gpio4 18 GPIO_ACTIVE_LOW>;
};
led4 {
label = "led4";
gpios = <&gpio4 8 GPIO_ACTIVE_LOW>;
};
led5 {
label = "led5";
gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
};
led6 {
label = "led6";
gpios = <&gpio4 7 GPIO_ACTIVE_LOW>;
};
};
pwm-beeper {
compatible = "pwm-beeper";
pwms = <&pwm2 0 5000 0>;
};
reg_rst_eth2: regulator-rst-eth2 {
compatible = "regulator-fixed";
regulator-name = "rst-usb-eth2";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_eth2>;
gpio = <&gpio3 2 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
};
reg_vdd_5v: regulator-5v {
compatible = "regulator-fixed";
regulator-name = "vdd-5v";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
};
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
status = "okay";
can0: can@0 {
compatible = "microchip,mcp2515";
reg = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can>;
clocks = <&osc_can>;
interrupt-parent = <&gpio4>;
interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
spi-max-frequency = <10000000>;
vdd-supply = <&reg_vdd_3v3>;
xceiver-supply = <&reg_vdd_5v>;
};
};
&ecspi3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi3>;
cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
status = "okay";
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-connection-type = "rgmii-rxid";
phy-handle = <&ethphy>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy: ethernet-phy@0 {
reg = <0>;
reset-assert-us = <1>;
reset-deassert-us = <15000>;
reset-gpios = <&gpio4 27 GPIO_ACTIVE_LOW>;
};
};
};
&i2c4 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
status = "okay";
rx8900: rtc@32 {
compatible = "epson,rx8900";
reg = <0x32>;
};
};
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
uart-has-rtscts;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
linux,rs485-enabled-at-boot-time;
uart-has-rtscts;
status = "okay";
};
&usbotg1 {
dr_mode = "otg";
over-current-active-low;
status = "okay";
};
&usbotg2 {
dr_mode = "host";
disable-over-current;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
usb1@1 {
compatible = "usb424,9514";
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
usbnet: ethernet@1 {
compatible = "usb424,ec00";
reg = <1>;
local-mac-address = [ 00 00 00 00 00 00 ];
};
};
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
vmmc-supply = <&reg_vdd_3v3>;
vqmmc-supply = <&reg_nvcc_sd>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio>;
pinctrl_can: cangrp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19
>;
};
pinctrl_ecspi2: ecspi2grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82
MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82
MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82
MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x19
>;
};
pinctrl_ecspi3: ecspi3grp {
fsl,pins = <
MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x82
MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x82
MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x82
MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x19
>;
};
pinctrl_enet: enetgrp {
fsl,pins = <
MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x19 /* PHY RST */
MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x19 /* ETH IRQ */
>;
};
pinctrl_gpio_led: gpioledgrp {
fsl,pins = <
MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x19
MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x19
MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x19
MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x19
MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x19
MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x19
>;
};
pinctrl_gpio: gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19
MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19
MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19
MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19
MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19
MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19
MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
>;
};
pinctrl_pwm2: pwm2grp {
fsl,pins = <
MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x19
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x140
MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x140
MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x140
MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x140
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140
MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140
MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140
MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140
>;
};
pinctrl_usb_eth2: usbeth2grp {
fsl,pins = <
MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
};

View File

@@ -1,335 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright (C) 2022 Kontron Electronics GmbH
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include "imx8mm.dtsi"
/ {
model = "Kontron OSM-S i.MX8MM (N802X SOM)";
compatible = "kontron,imx8mm-osm-s", "fsl,imx8mm";
aliases {
rtc0 = &rv3028;
rtc1 = &snvs_rtc;
};
memory@40000000 {
device_type = "memory";
/*
* There are multiple SoM flavors with different DDR sizes.
* The smallest is 1GB. For larger sizes the bootloader will
* update the reg property.
*/
reg = <0x0 0x40000000 0 0x80000000>;
};
chosen {
stdout-path = &uart3;
};
};
&A53_0 {
cpu-supply = <&reg_vdd_arm>;
};
&A53_1 {
cpu-supply = <&reg_vdd_arm>;
};
&A53_2 {
cpu-supply = <&reg_vdd_arm>;
};
&A53_3 {
cpu-supply = <&reg_vdd_arm>;
};
&ddrc {
operating-points-v2 = <&ddrc_opp_table>;
ddrc_opp_table: opp-table {
compatible = "operating-points-v2";
opp-100M {
opp-hz = /bits/ 64 <100000000>;
};
opp-750M {
opp-hz = /bits/ 64 <750000000>;
};
};
};
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
status = "okay";
flash@0 {
compatible = "mxicy,mx25r1635f", "jedec,spi-nor";
spi-max-frequency = <80000000>;
reg = <0>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "u-boot";
reg = <0x0 0x1e0000>;
};
partition@1e0000 {
label = "env";
reg = <0x1e0000 0x10000>;
};
partition@1f0000 {
label = "env_redundant";
reg = <0x1f0000 0x10000>;
};
};
};
};
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
pca9450: pmic@25 {
compatible = "nxp,pca9450a";
reg = <0x25>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
interrupt-parent = <&gpio1>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
regulators {
reg_vdd_soc: BUCK1 {
regulator-name = "+0V8_VDD_SOC (BUCK1)";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <850000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
nxp,dvs-run-voltage = <850000>;
nxp,dvs-standby-voltage = <800000>;
};
reg_vdd_arm: BUCK2 {
regulator-name = "+0V9_VDD_ARM (BUCK2)";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <950000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
nxp,dvs-run-voltage = <950000>;
nxp,dvs-standby-voltage = <850000>;
};
reg_vdd_dram: BUCK3 {
regulator-name = "+0V9_VDD_DRAM&PU (BUCK3)";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <950000>;
regulator-boot-on;
regulator-always-on;
};
reg_vdd_3v3: BUCK4 {
regulator-name = "+3V3 (BUCK4)";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
reg_vdd_1v8: BUCK5 {
regulator-name = "+1V8 (BUCK5)";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_nvcc_dram: BUCK6 {
regulator-name = "+1V1_NVCC_DRAM (BUCK6)";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-boot-on;
regulator-always-on;
};
reg_nvcc_snvs: LDO1 {
regulator-name = "+1V8_NVCC_SNVS (LDO1)";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_vdd_snvs: LDO2 {
regulator-name = "+0V8_VDD_SNVS (LDO2)";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <900000>;
regulator-boot-on;
regulator-always-on;
};
reg_vdda: LDO3 {
regulator-name = "+1V8_VDDA (LDO3)";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_vdd_phy: LDO4 {
regulator-name = "+0V9_VDD_PHY (LDO4)";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-boot-on;
regulator-always-on;
};
reg_nvcc_sd: LDO5 {
regulator-name = "NVCC_SD (LDO5)";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
};
};
rv3028: rtc@52 {
compatible = "microcrystal,rv3028";
reg = <0x52>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rtc>;
interrupts-extended = <&gpio4 1 IRQ_TYPE_LEVEL_HIGH>;
trickle-diode-disable;
};
};
&uart3 { /* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
vmmc-supply = <&reg_vdd_3v3>;
vqmmc-supply = <&reg_vdd_1v8>;
bus-width = <8>;
non-removable;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
>;
};
pinctrl_pmic: pmicgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x141
>;
};
pinctrl_rtc: rtcgrp {
fsl,pins = <
MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x19
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0
MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0
MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0
MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0
MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019
MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4
MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4
MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4
MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4
MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019
MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194
>;
};
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6
MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6
MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6
MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6
MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019
MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
>;
};
};

View File

@@ -1,314 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright (C) 2019 Kontron Electronics GmbH
*/
#include "imx8mm.dtsi"
/ {
model = "Kontron SL i.MX8MM (N801X SOM)";
compatible = "kontron,imx8mm-sl", "fsl,imx8mm";
memory@40000000 {
device_type = "memory";
/*
* There are multiple SoM flavors with different DDR sizes.
* The smallest is 1GB. For larger sizes the bootloader will
* update the reg property.
*/
reg = <0x0 0x40000000 0 0x80000000>;
};
chosen {
stdout-path = &uart3;
};
};
&A53_0 {
cpu-supply = <&reg_vdd_arm>;
};
&A53_1 {
cpu-supply = <&reg_vdd_arm>;
};
&A53_2 {
cpu-supply = <&reg_vdd_arm>;
};
&A53_3 {
cpu-supply = <&reg_vdd_arm>;
};
&ddrc {
operating-points-v2 = <&ddrc_opp_table>;
ddrc_opp_table: opp-table {
compatible = "operating-points-v2";
opp-100M {
opp-hz = /bits/ 64 <100000000>;
};
opp-750M {
opp-hz = /bits/ 64 <750000000>;
};
};
};
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
status = "okay";
flash@0 {
compatible = "mxicy,mx25r1635f", "jedec,spi-nor";
spi-max-frequency = <80000000>;
reg = <0>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "u-boot";
reg = <0x0 0x1e0000>;
};
partition@1e0000 {
label = "env";
reg = <0x1e0000 0x10000>;
};
partition@1f0000 {
label = "env_redundant";
reg = <0x1f0000 0x10000>;
};
};
};
};
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
pca9450: pmic@25 {
compatible = "nxp,pca9450a";
reg = <0x25>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
interrupt-parent = <&gpio1>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
regulators {
reg_vdd_soc: BUCK1 {
regulator-name = "+0V8_VDD_SOC (BUCK1)";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <850000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
nxp,dvs-run-voltage = <850000>;
nxp,dvs-standby-voltage = <800000>;
};
reg_vdd_arm: BUCK2 {
regulator-name = "+0V9_VDD_ARM (BUCK2)";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <950000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
nxp,dvs-run-voltage = <950000>;
nxp,dvs-standby-voltage = <850000>;
};
reg_vdd_dram: BUCK3 {
regulator-name = "+0V9_VDD_DRAM&PU (BUCK3)";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <950000>;
regulator-boot-on;
regulator-always-on;
};
reg_vdd_3v3: BUCK4 {
regulator-name = "+3V3 (BUCK4)";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
reg_vdd_1v8: BUCK5 {
regulator-name = "+1V8 (BUCK5)";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_nvcc_dram: BUCK6 {
regulator-name = "+1V1_NVCC_DRAM (BUCK6)";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-boot-on;
regulator-always-on;
};
reg_nvcc_snvs: LDO1 {
regulator-name = "+1V8_NVCC_SNVS (LDO1)";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_vdd_snvs: LDO2 {
regulator-name = "+0V8_VDD_SNVS (LDO2)";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <900000>;
regulator-boot-on;
regulator-always-on;
};
reg_vdda: LDO3 {
regulator-name = "+1V8_VDDA (LDO3)";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_vdd_phy: LDO4 {
regulator-name = "+0V9_VDD_PHY (LDO4)";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-boot-on;
regulator-always-on;
};
reg_nvcc_sd: LDO5 {
regulator-name = "NVCC_SD (LDO5)";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
};
};
};
&uart3 { /* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
vmmc-supply = <&reg_vdd_3v3>;
vqmmc-supply = <&reg_vdd_1v8>;
bus-width = <8>;
non-removable;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
>;
};
pinctrl_pmic: pmicgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x141
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0
MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0
MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0
MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0
MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019
MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4
MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4
MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4
MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4
MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019
MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194
>;
};
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6
MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6
MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6
MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6
MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019
MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
>;
};
};

View File

@@ -344,7 +344,6 @@
pinctrl-0 = <&pinctrl_pmic>;
interrupt-parent = <&gpio1>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
/*
* i.MX 8M Plus Data Sheet for Consumer Products

View File

@@ -245,7 +245,6 @@
pinctrl-0 = <&pinctrl_pmic>;
interrupt-parent = <&gpio1>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
/*
* i.MX 8M Plus Data Sheet for Consumer Products

View File

@@ -0,0 +1,131 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2025 PHYTEC Messtechnik GmbH
*/
#include "imx8mp-u-boot.dtsi"
/ {
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
bootph-pre-ram;
};
bootstd {
bootph-verify;
compatible = "u-boot,boot-std";
filename-prefixes = "/", "/boot/";
bootdev-order = "mmc2", "mmc1", "ethernet";
efi {
compatible = "u-boot,distro-efi";
};
rauc {
compatible = "u-boot,distro-rauc";
};
script {
compatible = "u-boot,script";
};
};
};
&reg_usdhc2_vmmc {
bootph-pre-ram;
};
&pinctrl_uart4 {
bootph-pre-ram;
};
&pinctrl_usdhc2 {
bootph-pre-ram;
};
&pinctrl_usdhc3 {
bootph-pre-ram;
};
&pinctrl_wdog {
bootph-pre-ram;
};
&gpio1 {
bootph-pre-ram;
};
&gpio2 {
bootph-pre-ram;
};
&gpio3 {
bootph-pre-ram;
};
&gpio4 {
bootph-pre-ram;
};
&gpio5 {
bootph-pre-ram;
};
&uart4 {
bootph-pre-ram;
};
&i2c1 {
bootph-pre-ram;
};
&pmic {
bootph-pre-ram;
};
/* USB1 Type-C */
&usb3_phy0 {
status = "okay";
};
&usb3_0 {
fsl,over-current-active-low;
fsl,power-active-low;
status = "okay";
};
&usb_dwc3_0 {
dr_mode = "peripheral";
status = "okay";
};
/* USB2 4-port USB3.0 HUB */
&usb3_phy1 {
vbus-supply = <&reg_vdd_5v0>;
status = "okay";
};
&usb3_1 {
fsl,permanently-attached;
fsl,disable-port-power-control;
status = "okay";
};
&usb_dwc3_1 {
dr_mode = "host";
status = "okay";
};
&usdhc2 {
bootph-pre-ram;
};
&usdhc3 {
bootph-pre-ram;
};
&wdog1 {
bootph-pre-ram;
};

View File

@@ -1,297 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/* Copyright (C) 2025 Toradex */
/dts-v1/;
#include "imx8mp-toradex-smarc.dtsi"
/ {
model = "Toradex SMARC iMX8M Plus on Toradex SMARC Development Board";
compatible = "toradex,smarc-imx8mp-dev",
"toradex,smarc-imx8mp",
"fsl,imx8mp";
hdmi-connector {
compatible = "hdmi-connector";
label = "J64";
type = "a";
port {
native_hdmi_connector_in: endpoint {
remote-endpoint = <&hdmi_tx_out>;
};
};
};
reg_carrier_1p8v: regulator-carrier-1p8v {
compatible = "regulator-fixed";
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <1800000>;
regulator-name = "On-carrier 1V8";
};
sound {
compatible = "simple-audio-card";
simple-audio-card,bitclock-master = <&codec_dai>;
simple-audio-card,format = "i2s";
simple-audio-card,frame-master = <&codec_dai>;
simple-audio-card,mclk-fs = <256>;
simple-audio-card,name = "tdx-smarc-wm8904";
simple-audio-card,routing =
"Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
"IN2L", "Line In Jack",
"IN2R", "Line In Jack",
"Microphone Jack", "MICBIAS",
"IN1L", "Microphone Jack";
simple-audio-card,widgets =
"Microphone", "Microphone Jack",
"Headphone", "Headphone Jack",
"Line", "Line In Jack";
codec_dai: simple-audio-card,codec {
clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1>;
sound-dai = <&wm8904_1a>;
};
simple-audio-card,cpu {
sound-dai = <&sai1>;
};
};
};
&aud2htx {
status = "okay";
};
/* SMARC SPI0 */
&ecspi1 {
status = "okay";
};
/* SMARC GBE0 */
&eqos {
status = "okay";
};
/* SMARC GBE1 */
&fec {
status = "okay";
};
/* SMARC CAN1 */
&flexcan1 {
status = "okay";
};
/* SMARC CAN0 */
&flexcan2 {
status = "okay";
};
&gpio1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio7>,
<&pinctrl_gpio8>,
<&pinctrl_gpio9>,
<&pinctrl_gpio10>,
<&pinctrl_gpio11>,
<&pinctrl_gpio12>,
<&pinctrl_gpio13>;
};
&gpio3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lvds_dsi_sel>;
};
&gpio4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio4>, <&pinctrl_gpio6>;
};
&hdmi_pvi {
status = "okay";
};
/* SMARC HDMI */
&hdmi_tx {
status = "okay";
ports {
port@1 {
hdmi_tx_out: endpoint {
remote-endpoint = <&native_hdmi_connector_in>;
};
};
};
};
&hdmi_tx_phy {
status = "okay";
};
/* SMARC I2C_LCD */
&i2c2 {
status = "okay";
i2c-mux@70 {
compatible = "nxp,pca9543";
reg = <0x70>;
#address-cells = <1>;
#size-cells = <0>;
/* I2C on DSI Connector Pins 4/6 */
i2c_dsi_0: i2c@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
};
/* I2C on DSI Connector Pins 52/54 */
i2c_dsi_1: i2c@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
};
};
};
/* SMARC I2C_CAM0 */
&i2c3 {
status = "okay";
};
/* SMARC I2C_GP */
&i2c4 {
/* Audio Codec */
wm8904_1a: audio-codec@1a {
compatible = "wlf,wm8904";
reg = <0x1a>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai1>, <&pinctrl_sai1_mclk>;
#sound-dai-cells = <0>;
clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1>;
clock-names = "mclk";
AVDD-supply = <&reg_carrier_1p8v>;
CPVDD-supply = <&reg_carrier_1p8v>;
DBVDD-supply = <&reg_carrier_1p8v>;
DCVDD-supply = <&reg_carrier_1p8v>;
MICVDD-supply = <&reg_carrier_1p8v>;
};
/* On-Carrier Temperature Sensor */
temperature-sensor@4f {
compatible = "ti,tmp1075";
reg = <0x4f>;
};
/* On-Carrier EEPROM */
eeprom@57 {
compatible = "st,24c02", "atmel,24c02";
reg = <0x57>;
pagesize = <16>;
};
};
/* SMARC I2C_CAM1 */
&i2c5 {
status = "okay";
};
/* SMARC I2C_PM */
&i2c6 {
clock-frequency = <100000>;
status = "okay";
/* Fan controller */
fan@18 {
compatible = "ti,amc6821";
reg = <0x18>;
};
/* Current measurement into module VDD */
hwmon@40 {
compatible = "ti,ina226";
reg = <0x40>;
shunt-resistor = <5000>;
};
};
&lcdif3 {
status = "okay";
};
/* SMARC PCIE_A, M2 Key B */
&pcie {
status = "okay";
};
&pcie_phy {
status = "okay";
};
/* SMARC LCD1_BKLT_PWM */
&pwm1 {
status = "okay";
};
/* SMARC LCD0_BKLT_PWM */
&pwm2 {
status = "okay";
};
/* SMARC I2S0 */
&sai1 {
assigned-clocks = <&clk IMX8MP_CLK_SAI1>;
assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
assigned-clock-rates = <24576000>;
fsl,sai-mclk-direction-output;
status = "okay";
};
/* SMARC HDMI Audio */
&sound_hdmi {
status = "okay";
};
/* SMARC SER0, RS485. Optional M.2 KEY E */
&uart1 {
linux,rs485-enabled-at-boot-time;
rs485-rts-active-low;
rs485-rx-during-tx;
status = "okay";
};
/* SMARC SER2 */
&uart2 {
status = "okay";
};
/* SMARC SER1, used as the Linux Console */
&uart4 {
status = "okay";
};
/* SMARC USB0 */
&usb3_0 {
status = "okay";
};
/* SMARC USB1..4 */
&usb3_1 {
status = "okay";
};
&usb3_phy0 {
status = "okay";
};
&usb3_phy1 {
status = "okay";
};
/* SMARC SDIO */
&usdhc2 {
status = "okay";
};

File diff suppressed because it is too large Load Diff

View File

@@ -69,6 +69,16 @@
bootph-some-ram;
};
&pinctrl_lpi2c3 {
bootph-pre-ram;
bootph-some-ram;
};
&pinctrl_pmic {
bootph-pre-ram;
bootph-some-ram;
};
&pinctrl_reg_usdhc2_vmmc {
bootph-pre-ram;
};
@@ -83,6 +93,16 @@
bootph-some-ram;
};
&pinctrl_usdhc1_100mhz {
bootph-pre-ram;
bootph-some-ram;
};
&pinctrl_usdhc1_200mhz {
bootph-pre-ram;
bootph-some-ram;
};
&pinctrl_usdhc2_cd {
bootph-pre-ram;
bootph-some-ram;
@@ -128,31 +148,9 @@
bootph-some-ram;
};
/*
* Remove once USB support is added to imx93-phyboard-segin.dts upstream.
*/
&usbotg1 {
disable-over-current;
dr_mode = "otg";
status = "okay";
};
&usbotg2 {
disable-over-current;
dr_mode = "host";
status = "okay";
};
&usdhc1 {
bootph-pre-ram;
bootph-some-ram;
/*
* Remove pinctrl assignments once they are added to imx93-phycore-som.dtsi
*/
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
};
&usdhc2 {
@@ -174,6 +172,21 @@
&lpi2c3 {
bootph-pre-ram;
bootph-some-ram;
pmic@25 {
bootph-pre-ram;
bootph-some-ram;
regulators {
bootph-pre-ram;
bootph-some-ram;
};
};
eeprom@50 {
bootph-pre-ram;
bootph-some-ram;
};
};
&s4muap {
@@ -209,165 +222,3 @@
bootph-all;
bootph-pre-ram;
};
/*
* The two nodes below won't be needed once nxp,pca9451a
* support is added to the Linux kernel.
*/
&iomuxc {
pinctrl_lpi2c3: lpi2c3grp {
bootph-pre-ram;
fsl,pins = <
MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e
MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e
>;
};
pinctrl_pmic: pmicgrp {
bootph-pre-ram;
fsl,pins = <
MX93_PAD_ENET2_RD3__GPIO4_IO27 0x31e
>;
};
/*
* Remove pinctrl_usdhc1_100mhz and pinctrl_usdhc1_200mhz once they
* are added to imx93-phycore-som.dtsi
*/
/* need to config the SION for data and cmd pad, refer to ERR052021 */
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
bootph-pre-ram;
bootph-some-ram;
fsl,pins = <
MX93_PAD_SD1_CLK__USDHC1_CLK 0x17be
MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000139e
MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e
MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000139e
MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013be
MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000139e
MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000139e
MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000139e
MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000139e
MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000139e
MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e
>;
};
/* need to config the SION for data and cmd pad, refer to ERR052021 */
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
bootph-pre-ram;
bootph-some-ram;
fsl,pins = <
MX93_PAD_SD1_CLK__USDHC1_CLK 0x17be
MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000139e
MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000139e
MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013be
MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013be
MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013be
MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013be
MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013be
MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013be
MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013be
MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e
>;
};
};
&lpi2c3 {
bootph-pre-ram;
bootph-some-ram;
clock-frequency = <400000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_lpi2c3>;
pinctrl-1 = <&pinctrl_lpi2c3>;
status = "okay";
pmic@25 {
bootph-pre-ram;
bootph-some-ram;
compatible = "nxp,pca9451a";
reg = <0x25>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
interrupt-parent = <&gpio4>;
interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
regulators {
bootph-pre-ram;
bootph-some-ram;
buck1: BUCK1 {
regulator-name = "VDD_SOC";
regulator-min-microvolt = <610000>;
regulator-max-microvolt = <950000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
};
buck2: BUCK2 {
regulator-name = "VDDQ_0V6";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <600000>;
regulator-boot-on;
regulator-always-on;
};
buck4: BUCK4 {
regulator-name = "VDD_3V3_BUCK";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
buck5: BUCK5 {
regulator-name = "VDD_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
buck6: BUCK6 {
regulator-name = "VDD_1V1";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-boot-on;
regulator-always-on;
};
ldo1: LDO1 {
regulator-name = "PMIC_SNVS_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
ldo4: LDO4 {
regulator-name = "VDD_0V8";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <800000>;
regulator-boot-on;
regulator-always-on;
};
ldo5: LDO5 {
regulator-name = "NVCC_SD2";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
};
eeprom@50 {
bootph-pre-ram;
bootph-some-ram;
compatible = "atmel,24c32";
reg = <0x50>;
pagesize = <32>;
vcc-supply = <&buck4>;
};
};

View File

@@ -0,0 +1,62 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2025 NXP
*/
#include "imx943-u-boot.dtsi"
&lpuart1 {
bootph-pre-ram;
};
&reg_usdhc2_vmmc {
bootph-pre-ram;
};
&usdhc1 {
bootph-pre-ram;
};
&usdhc2 {
bootph-pre-ram;
};
&wdog3 {
status = "disabled";
};
&pinctrl_reg_usdhc2_vmmc {
bootph-pre-ram;
};
&pinctrl_uart1 {
bootph-pre-ram;
};
&pinctrl_usdhc1 {
bootph-pre-ram;
};
&pinctrl_usdhc1_100mhz {
bootph-pre-ram;
};
&pinctrl_usdhc1_200mhz {
bootph-pre-ram;
};
&pinctrl_usdhc2 {
bootph-pre-ram;
};
&pinctrl_usdhc2_100mhz {
bootph-pre-ram;
};
&pinctrl_usdhc2_200mhz {
bootph-pre-ram;
};
&pinctrl_usdhc2_gpio {
bootph-pre-ram;
};

View File

@@ -0,0 +1,212 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2025 NXP
*/
/ {
binman {
multiple-images;
m33-oei-ddrfw {
pad-byte = <0x00>;
align-size = <0x8>;
filename = "m33-oei-ddrfw.bin";
oei-m33-ddr {
align-size = <0x4>;
filename = "oei-m33-ddr.bin";
type = "blob-ext";
};
imx-lpddr {
type = "nxp-header-ddrfw";
imx-lpddr-imem {
filename = "lpddr5_imem_v202409.bin";
type = "blob-ext";
};
imx-lpddr-dmem {
filename = "lpddr5_dmem_v202409.bin";
type = "blob-ext";
};
};
imx-lpddr-qb {
type = "nxp-header-ddrfw";
imx-lpddr-imem-qb {
filename = "lpddr5_imem_qb_v202409.bin";
type = "blob-ext";
};
imx-lpddr-dmem-qb {
filename = "lpddr5_dmem_qb_v202409.bin";
type = "blob-ext";
};
};
};
imx-boot {
filename = "flash.bin";
pad-byte = <0x00>;
spl {
type = "nxp-imx9image";
cfg-path = "spl/u-boot-spl.cfgout";
args;
cntr-version = <2>;
boot-from = "sd";
soc-type = "IMX9";
append = "mx943a0-ahab-container.img";
container;
dummy-ddr;
image0 = "oei", "m33-oei-ddrfw.bin", "0x1ffc0000";
hold = <0x10000>;
image1 = "m33", "m33_image.bin", "0x1ffc0000";
image2 = "a55", "spl/u-boot-spl.bin", "0x20480000";
dummy-v2x = <0x8b000000>;
};
u-boot {
type = "nxp-imx9image";
cfg-path = "u-boot-container.cfgout";
args;
cntr-version = <2>;
boot-from = "sd";
soc-type = "IMX9";
container;
image0 = "a55", "bl31.bin", "0x8a200000";
image1 = "a55", "u-boot.bin", "0x90200000";
};
};
};
};
&cpu0 {
clocks = <&scmi_clk IMX94_CLK_ARMPLL_PFD0>;
/delete-property/ power-domains;
};
&cpu1 {
clocks = <&scmi_clk IMX94_CLK_ARMPLL_PFD0>;
/delete-property/ power-domains;
};
&cpu2 {
clocks = <&scmi_clk IMX94_CLK_ARMPLL_PFD0>;
/delete-property/ power-domains;
};
&cpu3 {
clocks = <&scmi_clk IMX94_CLK_ARMPLL_PFD0>;
/delete-property/ power-domains;
};
&aips1 {
bootph-all;
};
&aips2 {
bootph-all;
};
&aips3 {
bootph-all;
};
&clk_ext1 {
bootph-all;
};
&dummy {
bootph-all;
};
&{/firmware} {
bootph-all;
};
&{/firmware/scmi} {
bootph-all;
};
&{/firmware/scmi/protocol@11} {
bootph-all;
};
&{/firmware/scmi/protocol@13} {
bootph-all;
};
&{/firmware/scmi/protocol@14} {
bootph-all;
};
&{/firmware/scmi/protocol@19} {
bootph-all;
};
&gpio2 {
bootph-pre-ram;
};
&gpio3 {
bootph-pre-ram;
};
&gpio4 {
bootph-pre-ram;
};
&gpio5 {
bootph-pre-ram;
};
&gpio6 {
bootph-pre-ram;
};
&gpio7 {
bootph-pre-ram;
};
&mu2 {
bootph-all;
};
&osc_24m {
bootph-all;
};
&scmi_buf0 {
bootph-all;
};
&scmi_buf1 {
bootph-all;
};
&{/soc} {
bootph-all;
elemu1: mailbox@47530000 {
compatible = "fsl,imx93-mu-s4";
reg = <0x0 0x47530000 0x0 0x10000>;
bootph-all;
status = "okay";
};
elemu3: mailbox@47550000 {
compatible = "fsl,imx93-mu-s4";
reg = <0x0 0x47550000 0x0 0x10000>;
bootph-all;
status = "okay";
};
};
&sram0 {
bootph-all;
};

View File

@@ -5,6 +5,13 @@
#include "imx95-u-boot.dtsi"
/ {
aliases {
pci0 = &netc_bus0;
pci1 = &netc_bus1;
};
};
&lpuart1 {
bootph-pre-ram;
};

View File

@@ -202,6 +202,22 @@
bootph-all;
};
&pcie0 {
assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
<&scmi_clk IMX95_CLK_HSIOPLL>,
<&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
assigned-clock-parents = <0>, <&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
<&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
};
&pcie1 {
assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
<&scmi_clk IMX95_CLK_HSIOPLL>,
<&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
assigned-clock-parents = <0>, <&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
<&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
};
&{/soc} {
bootph-all;
};

View File

@@ -95,6 +95,22 @@
bootph-all;
};
&main_rti1 {
status = "disabled";
};
&main_rti2 {
status = "disabled";
};
&main_rti3 {
status = "disabled";
};
&main_rti15 {
status = "disabled";
};
&main_uart0 {
bootph-all;
};

View File

@@ -5,7 +5,7 @@
#include "k3-binman.dtsi"
#ifdef CONFIG_TARGET_AM62A7_R5_EVM
#if defined(CONFIG_TARGET_AM62A7_R5_EVM) || defined(CONFIG_TARGET_AM62D2_R5_EVM)
&rcfg_yaml_tifs {
config = "tifs-rm-cfg.yaml";
@@ -100,7 +100,7 @@
#endif
#ifdef CONFIG_TARGET_AM62A7_A53_EVM
#if defined(CONFIG_TARGET_AM62A7_A53_EVM) || defined(CONFIG_TARGET_AM62D2_A53_EVM)
#define SPL_AM62A7_SK_DTB "spl/dts/ti/k3-am62a7-sk.dtb"
#define AM62A7_SK_DTB "u-boot.dtb"
@@ -185,7 +185,7 @@
};
};
fdt-0 {
ti_spl_fdt_0: fdt-0 {
description = "k3-am62a7-sk";
type = "flat_dt";
arch = "arm";
@@ -205,7 +205,7 @@
configurations {
default = "conf-0";
conf-0 {
ti_spl_conf_0: conf-0 {
description = "k3-am62a7-sk";
firmware = "atf";
loadables = "tee", "dm", "spl",
@@ -227,7 +227,7 @@
description = "U-Boot for AM62Ax Board";
};
fdt-0 {
u_boot_fdt_0: fdt-0 {
description = "k3-am62a7-sk";
type = "flat_dt";
arch = "arm";
@@ -248,7 +248,7 @@
configurations {
default = "conf-0";
conf-0 {
u_boot_conf_0: conf-0 {
description = "k3-am62a7-sk";
firmware = "uboot";
loadables = "uboot";

View File

@@ -156,6 +156,22 @@
bootph-all;
};
&main_rti1 {
status = "disabled";
};
&main_rti2 {
status = "disabled";
};
&main_rti3 {
status = "disabled";
};
&main_rti4 {
status = "disabled";
};
&main_uart0 {
bootph-all;
};

File diff suppressed because it is too large Load Diff

View File

@@ -0,0 +1,104 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2024-2025 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "k3-binman.dtsi"
#include "k3-am62a-sk-binman.dtsi"
#ifdef CONFIG_TARGET_AM62D2_R5_EVM
&bcfg_yaml {
config = "board/ti/am62ax/board-cfg.yaml";
};
&rcfg_yaml {
config = "board/ti/am62ax/rm-cfg.yaml";
};
&scfg_yaml {
config = "board/ti/am62ax/sec-cfg.yaml";
};
&pcfg_yaml {
config = "board/ti/am62ax/pm-cfg.yaml";
};
&bcfg_yaml_tifs {
config = "board/ti/am62ax/board-cfg.yaml";
};
&scfg_yaml_tifs {
config = "board/ti/am62ax/sec-cfg.yaml";
};
&pcfg_yaml_tifs {
config = "board/ti/am62ax/pm-cfg.yaml";
};
&rcfg_yaml_tifs {
config = "board/ti/am62ax/tifs-rm-cfg.yaml";
};
&pcfg_yaml_dm {
config = "board/ti/am62ax/pm-cfg.yaml";
};
&rcfg_yaml_dm {
config = "board/ti/am62ax/rm-cfg.yaml";
};
&bcfg_yaml_sysfw {
config = "board/ti/am62ax/board-cfg.yaml";
};
&scfg_yaml_sysfw {
config = "board/ti/am62ax/sec-cfg.yaml";
};
&pcfg_yaml_sysfw {
config = "board/ti/am62ax/pm-cfg.yaml";
};
&rcfg_yaml_sysfw {
config = "board/ti/am62ax/rm-cfg.yaml";
};
#endif
#ifdef CONFIG_TARGET_AM62D2_A53_EVM
&ti_spl_fdt_0 {
description = "k3-am62d2-evm";
ti-secure {
content = <&spl_am62a7_sk_dtb>;
keyfile = "custMpk.pem";
};
spl_am62d2_evm_dtb: blob-ext {
filename = "spl/dts/ti/k3-am62d2-evm.dtb";
};
};
&ti_spl_conf_0 {
description = "k3-am62d2-evm";
};
&u_boot_fdt_0 {
description = "k3-am62d2-evm";
ti-secure {
content = <&am62d2_evm_dtb>;
keyfile = "custMpk.pem";
};
am62d2_evm_dtb: blob-ext {
filename = AM62A7_SK_DTB;
};
};
&u_boot_conf_0 {
description = "k3-am62d2-evm";
};
#endif

View File

@@ -0,0 +1,13 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Common AM62D EVM dts file for SPLs
* Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "k3-am62d-evm-binman.dtsi"
/ {
chosen {
stdout-path = "serial2:115200n8";
};
};

View File

@@ -0,0 +1,82 @@
// SPDX-License-Identifier: GPL-2.0
/*
* AM62D2 EVM dts file for R5 SPL
* Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "k3-am62d2-evm.dts"
#include "k3-am62d-ddr-1866mhz-32bit.dtsi"
#include "k3-am62a-ddr.dtsi"
#include "k3-am62d2-evm-u-boot.dtsi"
/ {
aliases {
tick-timer = &main_timer0;
remoteproc0 = &sysctrler;
remoteproc1 = &a53_0;
};
a53_0: a53@0 {
compatible = "ti,am654-rproc";
reg = <0x00 0x00a90000 0x00 0x10>;
power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 135 0>;
clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
clock-names = "gtc", "core";
assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
assigned-clock-parents = <&k3_clks 61 2>;
assigned-clock-rates = <200000000>, <1200000000>;
ti,sci = <&dmsc>;
ti,sci-proc-id = <32>;
ti,sci-host-id = <10>;
bootph-pre-ram;
};
dm_tifs: dm-tifs {
compatible = "ti,j721e-dm-sci";
ti,host-id = <36>;
ti,secure-host;
mbox-names = "rx", "tx";
mboxes= <&secure_proxy_main 22>,
<&secure_proxy_main 23>;
bootph-pre-ram;
};
};
&dmsc {
mboxes= <&secure_proxy_main 0>,
<&secure_proxy_main 1>,
<&secure_proxy_main 0>;
mbox-names = "rx", "tx", "notify";
ti,host-id = <35>;
ti,secure-host;
};
&secure_proxy_sa3 {
/* Needed for initial handshake with ROM */
status = "okay";
bootph-pre-ram;
};
&cbass_main {
sysctrler: sysctrler {
compatible = "ti,am654-tisci-rproc-r5";
mboxes= <&secure_proxy_main 1>,
<&secure_proxy_main 0>,
<&secure_proxy_sa3 0>;
mbox-names = "tx", "rx", "boot_notify";
bootph-pre-ram;
};
};
&main_timer0 {
/delete-property/ clocks;
/delete-property/ clocks-names;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
clock-frequency = <25000000>;
bootph-pre-ram;
};

View File

@@ -1,243 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2025 Toradex
*
* Common dtsi for Verdin AM62P SoM on Development carrier board
*
* https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62p
* https://www.toradex.com/products/carrier-board/verdin-development-board-kit
*/
/ {
aliases {
eeprom1 = &carrier_eeprom;
};
sound {
compatible = "simple-audio-card";
simple-audio-card,bitclock-master = <&codec_dai>;
simple-audio-card,format = "i2s";
simple-audio-card,frame-master = <&codec_dai>;
simple-audio-card,mclk-fs = <256>;
simple-audio-card,name = "verdin-nau8822";
simple-audio-card,routing =
"Headphones", "LHP",
"Headphones", "RHP",
"Speaker", "LSPK",
"Speaker", "RSPK",
"Line Out", "AUXOUT1",
"Line Out", "AUXOUT2",
"LAUX", "Line In",
"RAUX", "Line In",
"LMICP", "Mic In",
"RMICP", "Mic In";
simple-audio-card,widgets =
"Headphones", "Headphones",
"Line Out", "Line Out",
"Speaker", "Speaker",
"Microphone", "Mic In",
"Line", "Line In";
codec_dai: simple-audio-card,codec {
sound-dai = <&nau8822_1a>;
};
simple-audio-card,cpu {
sound-dai = <&mcasp0>;
};
};
};
/* Verdin ETHs */
&cpsw3g {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rgmii1>, <&pinctrl_rgmii2>;
status = "okay";
};
/* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */
&cpsw3g_mdio {
status = "okay";
carrier_eth_phy: ethernet-phy@7 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eth2_rgmii_int>;
interrupt-parent = <&main_gpio0>;
interrupts = <42 IRQ_TYPE_EDGE_FALLING>;
micrel,led-mode = <0>;
};
};
/* Verdin ETH_1 (On-module PHY) */
&cpsw_port1 {
status = "okay";
};
/* Verdin ETH_2_RGMII */
&cpsw_port2 {
phy-handle = <&carrier_eth_phy>;
phy-mode = "rgmii-rxid";
status = "okay";
};
/* Verdin PWM_3_DSI */
&epwm0 {
status = "okay";
};
/* Verdin PWM_1, PWM_2 */
&epwm2 {
status = "okay";
};
&main_gpio0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie_1_reset>,
<&pinctrl_gpio_5>,
<&pinctrl_gpio_6>,
<&pinctrl_gpio_7>,
<&pinctrl_gpio_8>;
};
/* Verdin I2C_1 */
&main_i2c0 {
status = "okay";
nau8822_1a: audio-codec@1a {
compatible = "nuvoton,nau8822";
reg = <0x1a>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2s1_mclk>;
#sound-dai-cells = <0>;
};
carrier_gpio_expander: gpio@21 {
compatible = "nxp,pcal6416";
reg = <0x21>;
#gpio-cells = <2>;
gpio-controller;
};
/* Current measurement into module VCC */
hwmon@40 {
compatible = "ti,ina219";
reg = <0x40>;
shunt-resistor = <10000>;
};
temperature-sensor@4f {
compatible = "ti,tmp75c";
reg = <0x4f>;
};
carrier_eeprom: eeprom@57 {
compatible = "st,24c02", "atmel,24c02";
reg = <0x57>;
pagesize = <16>;
};
};
/* Verdin I2C_2_DSI */
&main_i2c1 {
status = "okay";
};
/* Verdin I2C_4_CSI */
&main_i2c3 {
status = "okay";
};
/* Verdin CAN_1 */
&main_mcan0 {
status = "okay";
};
/* Verdin SPI_1 */
&main_spi1 {
status = "okay";
};
/* Verdin UART_3, used as the Linux console */
&main_uart0 {
status = "okay";
};
/* Verdin UART_1, connector X50 through RS485 transceiver */
&main_uart1 {
rs485-rx-during-tx;
linux,rs485-enabled-at-boot-time;
status = "okay";
};
/* Verdin I2S_1 */
&mcasp0 {
status = "okay";
};
&mcu_gpio0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_1>,
<&pinctrl_gpio_2>,
<&pinctrl_gpio_3>,
<&pinctrl_gpio_4>;
};
/* Verdin I2C_3_HDMI */
&mcu_i2c0 {
status = "okay";
};
/* Verdin CAN_2 */
&mcu_mcan0 {
status = "okay";
};
/* Verdin UART_4 */
&mcu_uart0 {
status = "okay";
};
/* Verdin QSPI_1 */
&ospi0 {
status = "okay";
};
/* Verdin SD_1 */
&sdhci1 {
status = "okay";
};
/* Verdin USB_1 */
&usbss0 {
status = "okay";
};
&usb0 {
status = "okay";
};
/* Verdin USB_2 */
&usbss1 {
status = "okay";
};
&usb1 {
status = "okay";
};
/* Verdin CTRL_WAKE1_MICO# */
&verdin_gpio_keys {
status = "okay";
};
/* Verdin PCIE_1_RESET# */
&verdin_pcie_1_reset_hog {
status = "okay";
};
/* Verdin UART_2 */
&wkup_uart0 {
status = "okay";
};

View File

@@ -1,31 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2025 Toradex
*
* Common dtsi for Verdin AM62P SoM WB variant
*
* https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62p
*/
/* On-module Bluetooth */
&main_uart6 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart6>;
uart-has-rtscts;
status = "okay";
bluetooth {
compatible = "nxp,88w8987-bt";
fw-init-baudrate = <3000000>;
};
};
/* On-module Wi-Fi */
&sdhci2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdhci2>;
keep-power-in-suspend;
non-removable;
ti,fails-without-test-cd;
status = "okay";
};

File diff suppressed because it is too large Load Diff

View File

@@ -112,7 +112,7 @@
#if IS_ENABLED(CONFIG_TARGET_VERDIN_AM62P_A53)
#define SPL_VERDIN_AM62P_DTB "spl/dts/k3-am62p5-verdin-wifi-dev.dtb"
#define SPL_VERDIN_AM62P_DTB "spl/dts/ti/k3-am62p5-verdin-wifi-dev.dtb"
#define VERDIN_AM62P_DTB "u-boot.dtb"
&binman {

View File

@@ -1,22 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2025 Toradex
*
* https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62p
* https://www.toradex.com/products/carrier-board/verdin-development-board-kit
*/
/dts-v1/;
#include "k3-am62p5.dtsi"
#include "k3-am62p-verdin.dtsi"
#include "k3-am62p-verdin-wifi.dtsi"
#include "k3-am62p-verdin-dev.dtsi"
/ {
model = "Toradex Verdin AM62P WB on Verdin Development Board";
compatible = "toradex,verdin-am62p-wifi-dev",
"toradex,verdin-am62p-wifi",
"toradex,verdin-am62p",
"ti,am62p5";
};

View File

@@ -156,6 +156,10 @@
bootph-all;
};
&main_rti1 {
status = "disabled";
};
&sdhci0 {
bootph-all;
};

View File

@@ -17,6 +17,14 @@
bootph-all;
};
&evm_12v0 {
bootph-all;
};
&vcc3v3_io {
bootph-all;
};
&vtt_supply {
bootph-all;
};

View File

@@ -139,7 +139,6 @@
pinctrl-names = "default";
pinctrl-0 = <&spi_flash_pins>;
status = "okay";
must_tx;
enhance_timing;
dma_ext;
ipm_design;
@@ -162,7 +161,6 @@
pinctrl-names = "default";
pinctrl-0 = <&spi2_flash_pins>;
status = "okay";
must_tx;
enhance_timing;
dma_ext;
ipm_design;

View File

@@ -173,7 +173,6 @@
pinctrl-names = "default";
pinctrl-0 = <&spi_flash_pins>;
status = "okay";
must_tx;
enhance_timing;
dma_ext;
ipm_design;

View File

@@ -178,7 +178,6 @@
pinctrl-names = "default";
pinctrl-0 = <&spi_flash_pins>;
status = "okay";
must_tx;
enhance_timing;
dma_ext;
ipm_design;

View File

@@ -138,7 +138,6 @@
pinctrl-names = "default";
pinctrl-0 = <&spi_flash_pins>;
status = "okay";
must_tx;
enhance_timing;
dma_ext;
ipm_design;

View File

@@ -165,7 +165,6 @@
pinctrl-names = "default";
pinctrl-0 = <&spi_flash_pins>;
status = "okay";
must_tx;
enhance_timing;
dma_ext;
ipm_design;

View File

@@ -134,7 +134,6 @@
pinctrl-names = "default";
pinctrl-0 = <&spi_flash_pins>;
status = "okay";
must_tx;
enhance_timing;
dma_ext;
ipm_design;

View File

@@ -42,7 +42,6 @@
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
must_tx;
enhance_timing;
dma_ext;
ipm_design;

View File

@@ -28,7 +28,6 @@
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
must_tx;
enhance_timing;
dma_ext;
ipm_design;
@@ -52,7 +51,6 @@
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
must_tx;
enhance_timing;
dma_ext;
ipm_design;

View File

@@ -40,7 +40,6 @@
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
must_tx;
enhance_timing;
dma_ext;
ipm_design;

View File

@@ -181,7 +181,6 @@
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
must_tx;
enhance_timing;
dma_ext;
ipm_design;
@@ -204,7 +203,6 @@
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
must_tx;
enhance_timing;
dma_ext;
ipm_design;

View File

@@ -108,7 +108,6 @@
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
must_tx;
enhance_timing;
dma_ext;
ipm_design;

View File

@@ -62,6 +62,11 @@
reg = <0x0 0xf0801000 0x0 0x1000>;
};
timer0: timer@f0801068 {
compatible = "nuvoton,npcm845-timer";
reg = <0x0 0xf0801068 0x0 0x8>;
};
sdhci0: sdhci@f0842000 {
compatible = "nuvoton,npcm845-sdhci";
reg = <0x0 0xf0842000 0x0 0x100>;
@@ -136,7 +141,7 @@
host_intf: host_intf@9f000 {
compatible = "nuvoton,npcm845-host-intf";
reg = <0x9f000 0x1000>;
reg = <0x9f000 0x1000>, <0x7000 0x40>;
type = "espi";
ioaddr = <0x4e>;
channel-support = <0xf>;
@@ -157,14 +162,6 @@
status = "disabled";
};
timer0: timer@8000 {
compatible = "nuvoton,npcm845-timer";
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x8000 0x1C>;
clocks = <&clk NPCM8XX_CLK_REFCLK>;
clock-names = "refclk";
};
serial0: serial@0 {
compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
reg = <0x0 0x1000>;

View File

@@ -1056,5 +1056,9 @@
groups = "jtag2";
function = "jtag2";
};
vcdhs_pins: vcdhs-pins {
groups = "vcdhs";
function = "vcdhs";
};
};
};

View File

@@ -0,0 +1,20 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2025 Duje Mihanović <duje@dujemihanovic.xyz>
*/
/ {
pxa,rev-id = <3928 0>, <3928 1>, <3928 2>;
memory@0 {
reg = <0 0x1000000 0 0x3f000000>;
};
};
&uart0 {
clock-frequency = <14745600>;
};
&pmx {
compatible = "marvell,pxa1908-padconf", "pinctrl-single";
};

View File

@@ -1,74 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
#include "pxa1908.dtsi"
/ {
pxa,rev-id = <3928 2>;
model = "Samsung Galaxy Core Prime VE LTE";
compatible = "samsung,coreprimevelte", "marvell,pxa1908";
aliases {
serial0 = &uart0;
};
chosen {
#address-cells = <2>;
#size-cells = <2>;
ranges;
stdout-path = "serial0:115200n8";
/* S-Boot places the initramfs here */
linux,initrd-start = <0x4d70000>;
linux,initrd-end = <0x5000000>;
fb0: framebuffer@17177000 {
compatible = "simple-framebuffer";
reg = <0 0x17177000 0 (480 * 800 * 4)>;
width = <480>;
height = <800>;
stride = <(480 * 4)>;
format = "a8r8g8b8";
};
};
memory {
device_type = "memory";
reg = <0 0x1000000 0 0x3f000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
framebuffer@17000000 {
reg = <0 0x17000000 0 0x1800000>;
no-map;
};
gpu@9000000 {
reg = <0 0x9000000 0 0x1000000>;
};
/* Communications processor, aka modem */
cp@5000000 {
reg = <0 0x5000000 0 0x3000000>;
};
cm3@a000000 {
reg = <0 0xa000000 0 0x80000>;
};
seclog@8000000 {
reg = <0 0x8000000 0 0x100000>;
};
ramoops@8100000 {
compatible = "ramoops";
reg = <0 0x8100000 0 0x40000>;
record-size = <0x8000>;
console-size = <0x20000>;
max-reason = <5>;
};
};
};

View File

@@ -1,106 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/dts-v1/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
model = "Marvell Armada PXA1908";
compatible = "marvell,pxa1908";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0 0>;
enable-method = "psci";
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0 1>;
enable-method = "psci";
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0 2>;
enable-method = "psci";
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0 3>;
enable-method = "psci";
};
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
gic: interrupt-controller@d1df9000 {
compatible = "arm,gic-400";
reg = <0 0xd1df9000 0 0x1000>,
<0 0xd1dfa000 0 0x2000>,
/* The subsequent registers are guesses. */
<0 0xd1dfc000 0 0x2000>,
<0 0xd1dfe000 0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
interrupt-controller;
#interrupt-cells = <3>;
};
apb@d4000000 {
compatible = "simple-bus";
reg = <0 0xd4000000 0 0x200000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0xd4000000 0x200000>;
uart0: serial@17000 {
compatible = "mrvl,mmp-uart", "intel,xscale-uart";
reg = <0x17000 0x1000>;
clock-frequency = <14745600>;
reg-shift = <2>;
};
uart1: serial@18000 {
compatible = "mrvl,mmp-uart", "intel,xscale-uart";
reg = <0x18000 0x1000>;
clock-frequency = <14745600>;
reg-shift = <2>;
};
uart2: serial@36000 {
compatible = "mrvl,mmp-uart", "intel,xscale-uart";
reg = <0x36000 0x1000>;
clock-frequency = <117000000>;
reg-shift = <2>;
};
};
};
};

View File

@@ -23,6 +23,8 @@
&rpc {
bootph-all;
status = "disabled";
flash@0 {
bootph-all;
spi-tx-bus-width = <1>;

View File

@@ -0,0 +1,41 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source extras for U-Boot for the Gray Hawk board
*
* Copyright (C) 2025 Renesas Electronics Corp.
*/
#include "r8a779h0-u-boot.dtsi"
/ {
aliases {
spi0 = &rpc;
};
};
&pfc {
qspi0_pins: qspi0 {
groups = "qspi0_ctrl", "qspi0_data4";
function = "qspi0";
};
};
&rpc {
pinctrl-0 = <&qspi0_pins>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
spi-max-frequency = <40000000>;
status = "disabled";
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "s25fs512s", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <40000000>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
};
};

View File

@@ -0,0 +1,11 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source extras for U-Boot on R-Car R8A779H0 SoC
*
* Copyright (C) 2025 Renesas Electronics Corp.
*/
&rpc {
bank-width = <2>;
num-cs = <1>;
};

View File

@@ -45,7 +45,7 @@
compatible = "maxim,max8998";
reg = <0x66 0 0>;
voltage-regulators {
regulators {
ldo2_reg: LDO2 {
regulator-compatible = "LDO2";
regulator-name = "VALIVE_1.1V";

View File

@@ -8,6 +8,7 @@
/ {
chosen {
bootph-all;
tick-timer = &pit;
};
ahb {

View File

@@ -209,7 +209,7 @@
/* DMIUSMCTCR */
<0x00000300 0x00000001 0x00000003>,
<0x00000300 0x00000003 0x00000003>,
<0x00000308 0x00000004 0x0000001F>;
<0x00000308 0x0000000C 0x0000001F>;
bootph-all;
};
@@ -220,7 +220,7 @@
/* DMIUSMCTCR */
<0x00000300 0x00000001 0x00000003>,
<0x00000300 0x00000003 0x00000003>,
<0x00000308 0x00000004 0x0000001F>;
<0x00000308 0x0000000C 0x0000001F>;
bootph-all;
};
};

View File

@@ -87,6 +87,10 @@
disable-over-current;
};
&usb31 {
status = "okay";
};
&watchdog0 {
status = "okay";
};

View File

@@ -232,6 +232,18 @@
status = "disabled";
};
nand: nand@ffb90000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "altr,socfpga-denali-nand";
reg = <0xffb90000 0x10000>,
<0xffb80000 0x1000>;
reg-names = "nand_data", "denali_reg";
interrupts = <0 97 4>;
resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>;
status = "disabled";
};
ocram: sram@ffe00000 {
compatible = "mmio-sram";
reg = <0xffe00000 0x100000>;

View File

@@ -137,3 +137,7 @@
&usb0 {
status = "okay";
};
&watchdog0 {
status = "okay";
};

View File

@@ -12,6 +12,47 @@
};
};
&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "fsbla1";
reg = <0x00000000 0x00040000>;
};
partition@40000 {
label = "fsbla2";
reg = <0x00040000 0x00040000>;
};
partition@80000 {
label = "metadata1";
reg = <0x00080000 0x00040000>;
};
partition@C0000 {
label = "metadata2";
reg = <0x000C0000 0x00040000>;
};
partition@100000 {
label = "fip-a";
reg = <0x00100000 0x00400000>;
};
partition@500000 {
label = "fip-b";
reg = <0x00500000 0x00400000>;
};
partition@900000 {
label = "u-boot-env";
reg = <0x00900000 0x00080000>;
};
partition@980000 {
label = "nor-user";
reg = <0x00980000 0x03680000>;
};
};
};
&usart2 {
bootph-all;
};

View File

@@ -5,7 +5,7 @@
#include "sun50i-a64-sopine-baseboard.dts"
/ {
model = "Pine64 LTS";
model = "Pine64 PINE A64 LTS";
compatible = "pine64,pine64-lts", "allwinner,sun50i-r18",
"allwinner,sun50i-a64";

View File

@@ -4,7 +4,7 @@
#include "sun50i-a64-pine64.dts"
/ {
model = "Pine64+";
model = "Pine64 PINE A64+";
compatible = "pine64,pine64-plus", "allwinner,sun50i-a64";
/* TODO: Camera, touchscreen, etc. */

View File

@@ -9,7 +9,7 @@
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Pine64";
model = "Pine64 PINE A64";
compatible = "pine64,pine64", "allwinner,sun50i-a64";
aliases {
@@ -124,6 +124,17 @@
status = "okay";
};
/* On Wifi/BT connector */
&mmc1 {
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
vmmc-supply = <&reg_dldo4>;
vqmmc-supply = <&reg_eldo1>;
bus-width = <4>;
non-removable;
status = "disabled";
};
&ohci0 {
status = "okay";
};
@@ -286,6 +297,7 @@
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
uart-has-rtscts;
status = "disabled";
};

View File

@@ -13,7 +13,7 @@
#include <dt-bindings/pwm/pwm.h>
/ {
model = "Pinebook";
model = "Pine64 Pinebook";
compatible = "pine64,pinebook", "allwinner,sun50i-a64";
chassis-type = "laptop";
@@ -390,6 +390,8 @@
&tcon0 {
pinctrl-names = "default";
pinctrl-0 = <&lcd_rgb666_pins>;
assigned-clocks = <&ccu CLK_TCON0>;
assigned-clock-parents = <&ccu CLK_PLL_VIDEO0_2X>;
status = "okay";
};

View File

@@ -188,12 +188,30 @@
&i2c1 {
status = "okay";
/* Alternative magnetometer */
af8133j: magnetometer@1c {
compatible = "voltafield,af8133j";
reg = <0x1c>;
reset-gpios = <&pio 1 1 GPIO_ACTIVE_LOW>;
avdd-supply = <&reg_dldo1>;
dvdd-supply = <&reg_dldo1>;
mount-matrix = "0", "-1", "0",
"-1", "0", "0",
"0", "0", "-1";
/* status will be fixed up in firmware */
status = "disabled";
};
/* Magnetometer */
lis3mdl: magnetometer@1e {
compatible = "st,lis3mdl-magn";
reg = <0x1e>;
vdd-supply = <&reg_dldo1>;
vddio-supply = <&reg_dldo1>;
mount-matrix = "0", "1", "0",
"-1", "0", "0",
"0", "0", "1";
};
/* Light/proximity sensor */
@@ -212,6 +230,9 @@
interrupts = <7 5 IRQ_TYPE_EDGE_RISING>; /* PH5 */
vdd-supply = <&reg_dldo1>;
vddio-supply = <&reg_dldo1>;
mount-matrix = "0", "1", "0",
"-1", "0", "0",
"0", "0", "1";
};
};

View File

@@ -9,7 +9,7 @@
#include "sun50i-a64-pinetab.dts"
/ {
model = "PineTab, Early Adopter's version";
model = "Pine64 PineTab Early Adopter";
compatible = "pine64,pinetab-early-adopter", "allwinner,sun50i-a64";
};

View File

@@ -14,7 +14,7 @@
#include <dt-bindings/pwm/pwm.h>
/ {
model = "PineTab, Development Sample";
model = "Pine64 PineTab Developer Sample";
compatible = "pine64,pinetab", "allwinner,sun50i-a64";
chassis-type = "tablet";

View File

@@ -8,7 +8,7 @@
#include "sun50i-a64-sopine.dtsi"
/ {
model = "SoPine with baseboard";
model = "Pine64 SOPINE on Baseboard carrier board";
compatible = "pine64,sopine-baseboard", "pine64,sopine",
"allwinner,sun50i-a64";
@@ -103,6 +103,17 @@
};
};
/* On Wifi/BT connector */
&mmc1 {
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
vmmc-supply = <&reg_dldo4>;
vqmmc-supply = <&reg_eldo1>;
bus-width = <4>;
non-removable;
status = "disabled";
};
&mmc2 {
pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins>;
@@ -175,6 +186,14 @@
status = "okay";
};
/* On Wifi/BT connector, with RTS/CTS */
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
uart-has-rtscts;
status = "disabled";
};
/* On Pi-2 connector */
&uart2 {
pinctrl-names = "default";

View File

@@ -369,6 +369,8 @@
&tcon0 {
pinctrl-names = "default";
pinctrl-0 = <&lcd_rgb666_pins>;
assigned-clocks = <&ccu CLK_TCON0>;
assigned-clock-parents = <&ccu CLK_PLL_VIDEO0_2X>;
status = "okay";
};

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