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1558 Commits

Author SHA1 Message Date
Tom Rini
e50b1e8715 Prepare v2025.10
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-10-06 13:13:09 -06:00
Tom Rini
dc6c80056e global: Add expected space between '#include' and directive
These files had '#include<file.h>' rather than '#include <file.h>' which
while functional is not the correct style.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-10-04 13:31:01 -06:00
Yegor Yefremov
c23688d053 clk: ti: fix K3 clock driver help texts
Add "in SPL" to the SPL related driver help texts.

Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
2025-10-04 12:51:01 -06:00
Thomas Bonnefille
3bbaa9dca6 env: fix typo in multiple Kconfig descriptions
%s/environemt/environment

Signed-off-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
2025-10-04 12:15:57 -06:00
Sam Protsenko
072264c4b3 Revert "fdt: Make sure there is no stale initrd left"
This reverts commit 9fe2e4b464.

Commit 9fe2e4b464 ("fdt: Make sure there is no stale initrd left")
introduces a regression in case when U-Boot transfers control to an EFI
app which acts as a subsequent bootloading program. Such an app might
try to set "linux,initrd-start" and "linux,initrd-end" fdt properties,
but by that time those properties are already removed by the code added
in the mentioned commit.

Particularly, the issue was observed on the E850-96 board where GBL EFI
app [1] can't run Android successfully anymore. More specifically, the
kernel can't see the ramdisk and panics with next messages:

    /dev/root: Can't open blockdev
    VFS: Cannot open root device "" or unknown-block(0,0): error -6
    Please append a correct "root=" boot option; ...
    Kernel panic - not syncing: VFS: Unable to mount root fs on
    unknown-block(0,0)

fdt_initrd() function (where initrd dts properties are removed) is
called two times:

1. First it's called by EFI boot manager (e.g. as a part of U-Boot
Standard Boot mechanism) when it's installing FDT:

    fdt_initrd
    image_setup_libfdt
    efi_install_fdt
    efi_bootmgr_run
    efi_mgr_boot

It's already enough for EFI app to malfunction. But then it's also
called second time:

2. From the EFI app, via EFI DT fixup protocol:

    fdt_initrd
    image_setup_libfdt
    efi_dt_fixup
    struct efi_dt_fixup_protocol efi_dt_fixup_prot = {
        .fixup = efi_dt_fixup
    };

See [2] for specific GBL code which sets those fdt properties and then
runs DT fixup protocol callback.

This issue was discussed [3], but no action was taken since then. Revert
this patch for now, until a proper solution can be found.

[1] https://source.android.com/docs/core/architecture/bootloader/generic-bootloader/gbl-dev
[2] https://android.googlesource.com/platform/bootable/libbootloader/+/refs/heads/gbl-mainline/gbl/libgbl/src/android_boot/mod.rs#208
[3] https://lists.denx.de/pipermail/u-boot/2025-July/593879.html

Fixes: 9fe2e4b464 ("fdt: Make sure there is no stale initrd left")
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
2025-10-03 07:45:20 -06:00
Tom Rini
5a3c306aaf Merge tag 'doc-202510-rc6' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request doc-202510-rc6

CI: https://source.denx.de/u-boot/custodians/u-boot-efi/-/pipelines/27807

* Update coding style to recommend b4 for patch submission
* pytest: Fix inline code and other formatting
* develop: fix grammar and syntax
2025-10-03 07:43:36 -06:00
Martin Schwan
a8d451aa14 doc: pytest: Fix inline code and other formatting
Mainly fix inline code and some other formatting mistakes. Inline code
uses double backticks `` in reStructuredText instead of single backticks
as in Markdown.

Also fix some smaller formatting issues, such as excess colons before
literal blocks.

Signed-off-by: Martin Schwan <m.schwan@phytec.de>
2025-10-03 06:01:33 +02:00
Javier Tia
5a21f5b4c9 doc: Update coding style to recommend b4 for patch submission
Replace references to patman with b4 as the recommended tool for
preparing and sending patches. b4 is widely adopted in the Linux kernel
community and U-Boot ships with configuration to simplify its use with
the project mailing list.

The updated guidelines describe how to prepare series with b4, handle
cover letters and recipient lists, run style checks, and send patches
safely. Instructions also highlight how to collect and apply review tags
before resending.

This change documents the preferred workflow for contributors and
ensures consistency with common practices across related upstream
communities.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Signed-off-by: Javier Tia <javier.tia@linaro.org>
2025-10-03 05:59:34 +02:00
Yegor Yefremov
eb5014841c doc: develop: fix grammar and syntax
Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2025-10-03 05:58:45 +02:00
Andrew Goodbody
72f72fab00 b4-config: Improve b4 config for correct operation
The recent change to .b4-config resulted in some expected recipients not
being added to the address lists. Rework the commands so that all
expected recipients are added while maintaining the ordering from the
first change.

Fixes: 26efc940c8 ("b4-config: configure `b4` for U-Boot")

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-10-02 11:30:15 -06:00
Tom Rini
5b93c3ec7f Merge tag 'u-boot-stm32-20250930' of https://source.denx.de/u-boot/custodians/u-boot-stm
CI: https://source.denx.de/u-boot/custodians/u-boot-stm/-/pipelines/27776

- stm32mp1: Fix env_get_location()
- stm32mp2: Update register used by BL31 for boot parameter
2025-09-30 10:47:19 -06:00
Jamie Gibbons
8dee93cfc5 board: mpfs_icicle: fix pointer assignment in board_fdt_blob_setup()
Correct the assignment in board_fdt_blob_setup() to use *fdtp instead of
fdtp, ensuring the caller receives the correct FDT address. This
resolves an issue where the device tree pointer was not properly set due
to assigning to the local parameter rather than the dereferenced
pointer.

Fixes: 7c16ebba1e ("board: mpfs_icicle: implement board_fdt_blob_setup()/board_fit_config_name_match()")
Signed-off-by: Jamie Gibbons <jamie.gibbons@microchip.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
2025-09-30 10:10:08 -06:00
Patrick Delaunay
8a2e75e6a1 stm32mp2: update register used by BL31 for boot parameter
Use the ARM64 kernel booting register settings, defined in Linux
documentation Documentation/arch/arm64/booting.rst:

 x0 = physical address of device tree blob (dtb) in system RAM.

so kernel can replace U-Boot in FIP without modification of BL31.

Use x0 for future TF-A version and keep x2 as fallback to be compatible
with previous version of TF-A BL31.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2025-09-30 17:37:10 +02:00
Tom Rini
662672dede Merge tag 'net-20250930' of https://source.denx.de/u-boot/custodians/u-boot-net
Pull request net-20250930

net-common:
- DesignWare: avoid regulator enable failure
- Fix RMII help text

net-lwip:
- Ensure alignment of packet buffers
- Use NTP server(s) obtained from DHCP
2025-09-30 08:57:25 -06:00
Kory Maincent
d1afa66504 Revert "board: st: stm32mp1: Clean env_get_location()"
This reverts commit d37641c61b.

Restore support for environment storage in EXT4 filesystem on eMMC boot.
The previous cleanup incorrectly removed this fallback option which is
needed for boards that store their environment in an EXT4 partition.

This configuration is OS-specific rather than board-dependent and should
remain as it is configurable via menuconfig. Even if it is not described
in ST defconfigs people may have enabled it in their defconfig.

Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2025-09-30 16:44:26 +02:00
Tim Harvey
b2217c935e net: lwip: ensure alignment of packet buffers
Network packet buffers should be aligned to PKTALIGN. Add a compiler
attribute to ensure this.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
[jf: use __aligned(x) from <linux/compiler_attributes.h>]
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
2025-09-30 13:08:38 +02:00
Jerome Forissier
61a6f5ab99 net: lwip: dhcp: set ntpserverip environment variable
Once the DHCP exchange is complete, if we have an IP address for an NTP
server, set the ntpserverip environment variable accordingly. Although
not necessary to make the sntp command use that server (since it is
known internally to the lwIP stack), this makes the behavior in line
with the legacy NET stack. This is also consistent with exporting the
DNS servers etc.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Suggested-by: Michal Simek <michal.simek@amd.com>
2025-09-30 12:01:36 +02:00
Jerome Forissier
57a623230e net: lwip: dhcp: make NTP servers usable by the sntp command
When both CMD_DHCP and CMD_SNTP are enabled, one would expect the NTP
servers received by DHCP to be used by the sntp command by default. Fix
dhcp_loop() so that it is indeed the case.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reported-by: Michal Simek <michal.simek@amd.com>
2025-09-30 12:01:36 +02:00
Jerome Forissier
4462ab9a0b net: lwip: enable debug traces for SNTP when CONFIG_LWIP_DEBUG is set
Now that SNTP is supported, enable SNTP debug traces when LWIP_DEBUG is
enabled. In particular, this allows to see which NTP servers are
received during DHCP.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
2025-09-30 12:01:36 +02:00
Ben Wolsieffer
bf82aa8ae0 net: designware: avoid regulator enable failure
Use regulator_set_enable_if_allowed() to avoid failure if regulator is
shared between multiple devices.

Signed-off-by: Ben Wolsieffer <ben.wolsieffer@hefring.com>
2025-09-30 12:01:36 +02:00
Yegor Yefremov
adc6d192e9 net: fix RMII help text
Replace MII with RMII as it is a Reduced Media-Independent Interface.

Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
2025-09-30 12:01:36 +02:00
Daniel P. Berrangé
a239b0b0b6 Add symlink from gpl-2.0.txt to a COPYING file
While it is good that the "Licenses/" directory contains the text
for all licenses that are applicable to u-boot code, it is harder
to determine at a glance what the default and/or preferred license
is. While humans can look at the Licenses/README file, this is not
machine parseable, making it tricky for license detection tools to
automatically determine/report on the overall / aggregate u-boot
license.

The project previously had a top level COPYING file containing a
short blurb, followed by the GPL license text. This was removed
back in commit eca3aeb352 when
the "Licenses/" directory was introduced. For the benefit of
automated tools, it is helpful to retain a top level COPYING
file in the repository. Rather than duplicate the license text,
however, a symlink from the Licenses/gpl-2.0.txt file should
suffice.

Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Reported-by: Alex Bennée <alex.bennee@linaro.org>
Acked-by: Tom Rini <trini@konsulko.com>
2025-09-29 11:56:16 -06:00
Jiaxun Yang
26efc940c8 b4-config: configure b4 for U-Boot
`b4` is a commandline tool to make patch-based development easier.

Provide a .b4-config file to match U-Boot's development preference about
who is cc'd on patch submission.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
[trini: Reword slightly]
2025-09-29 10:05:19 -06:00
Maksim Kiselev
522a58af83 i2c: designware_i2c: Don't warn if reset DT property is not present
If reset property is missing in DT, then we get this warning:
	designware_i2c@0: Can't get reset: -2

Avoid this by checking if reset DT property is present, first.

Fixes: 622597dee4 ("i2c: designware: add reset ctrl to driver")
Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com>
Reviewed-by: Heiko Schocher <hs@nabladev.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2025-09-29 08:01:15 -06:00
Tom Rini
07b7259b8b Merge tag 'efi-2025-10-rc6' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request efi-2025-10-rc6

CI:

* https://source.denx.de/u-boot/custodians/u-boot-efi/-/pipelines/27745

Docs:

* Correct encodings for spl memory layout diagrams
* Suggest usage of KDOC_WERROR when building documentation
* Replace references to README.fdt-control
* Clarify precedence of environment locations
* Add documentation for the TI am335x_evm board
* Remove README.commands.itest
* Add a note about asking for feedback in the development process

UEFI:

* Cleanup UEFI Variables Kconfig menu
2025-09-27 08:05:53 -06:00
Michal Simek
a0fe8cedcb efi_loader: Cleanup UEFI Variables menu selection
There are 3 options listed between choice/endchoice FILE/TEE/NO_STORE.
There is no reason to add other config with dependencies between
choice/endchoice because they can never be selected because they depends on
only that 3 options which can be selected.
That's why move additional configuration with dependency below choice
section.

Signed-off-by: Michal Simek <michal.simek@amd.com>
2025-09-27 09:22:00 +02:00
E Shattow
c9aad6dbd9 doc: Update mentions of README.fdt-control
Update documents 'README.fdt-control' reference to replacement 'control.rst':
  doc/arch/nios2.rst
  dts/Makefile

Also convert some adjacent pathname mentions to rST links where applicable

Fixes: 3e9fddfc4f "doc: Move devicetree control doc to rST"
Signed-off-by: E Shattow <e@freeshell.de>
2025-09-27 09:20:22 +02:00
Tom Rini
7b5e66a2b3 doc: develop: process: Add note about asking for feedback
It can be unclear to contributors what to do if they haven't gotten any
feedback on patches they have submitted. Add a sentence saying that if
they feel it's been too long without any comment, it's OK to reply
again.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-09-27 09:19:20 +02:00
E Shattow
77493c488b doc: build: documentation: add description of KDOC_WERROR
Describe KDOC_WERROR and recommend when building documentation for a patch
submission.

Signed-off-by: E Shattow <e@freeshell.de>
2025-09-27 09:18:48 +02:00
Anshul Dalal
0e4fad5f41 doc: memory: fix encodings for spl layout diagrams
The commit 284ef1bbce ("doc: memory: Add documentation for system
RAM") added documentation for U-Boot's memory usage along with diagrams
showcasing the SPL's memory usage. Although the SVGs for the diagrams
were improperly encoded.

Therefore, this patch fixes the older SVGs with one's with better
encoding and reduced size created using inkscape[1].

[1]: https://inkscape.org/

Reported-by: Alexander Dahl <ada@thorsis.com>
Fixes: 284ef1bbce ("doc: memory: Add documentation for system RAM")
Signed-off-by: Anshul Dalal <anshuld@ti.com>
2025-09-27 09:11:54 +02:00
Ricardo Simoes
75ef35b578 doc: environment: clarify env precedence
Since commit 5cf6a06a it is possible to have both text-based and
old-style C environment files. But so far the environment documentation
has not reflected this change. This commit fixes that.

Signed-off-by: Ricardo Simoes <ricardo.simoes@pt.bosch.com>
Signed-off-by: Mark Jonas <mark.jonas@de.bosch.com>
2025-09-27 09:11:34 +02:00
Tom Rini
e59e10240c doc: Remove README.commands.itest
We currently document this command in doc/usage/cmd/itest.rst and this
documentation is more comprehensive than the older README file. Delete
the older file.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2025-09-27 09:08:08 +02:00
Neha Malcom Francis
9585c8f45f doc: memory: Restore missing diagram
When applying the patch that became commit a2d881f5bcd3 ("doc: memory:
Add documentation for system RAM") one of the diagrams was missed.
Re-add this missing file.

Reported-by: Adriano Carvalho <adrianocarvalho.pt@gmail.com>
Fixes: a2d881f5bcd3 doc: memory: Add documentation for system RAM
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
[trini: Take Neha's original svg and re-apply it]
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-09-27 09:00:27 +02:00
Sidharth Seela
fa1922846b doc: board: ti: am335x_evm: Add documentation
Link: https://lore.kernel.org/u-boot/20250829191830.GZ124814@bill-the-cat/

Add documentation for config changes required to enable Falcon SD-FAT boot.

Signed-off-by: Sidharth Seela <sidharthseela@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
2025-09-27 08:58:39 +02:00
Yegor Yefremov
9b45d574af spl: nand: initialize writesize for am335x
Initialize mtd->writesize in nand_init() as otherwise
nand_page_size() returns 0 and this affects NAND read
operations.

Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
2025-09-25 18:54:07 -06:00
Peng Fan
9a20a4fba5 MAINTAINERS: Update MMC/POWER/FREESCALE QORIQ
- Update MMC entry to match 'mmc' using 'N'
- Add myself as POWER maintainer for regulator and pmic patches. I have
  started to handle relevant patches.
- Update QORIQ maintainer. Priyanka has moved to work on other stuff, I
  have been handling this for quite some time.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-09-25 18:53:28 -06:00
Jerome Forissier
5074fd5f72 MAINTAINERS: update NETWORK and NETWORK (LWIP)
Add myself as a maintainer of the NETWORK subsystem since:
- I have effectively been handling net patches in my patchwork queue and
sending pull requests to Tom,
- I do have push access to the u-boot-net custodian tree.

Also, add u-boot-net as the SCM tree for NETWORK (LWIP) since it is where
lwIP-related patches end up too.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
CC: Ramon Fried <rfried.dev@gmail.com>
CC: Joe Hershberger <joe.hershberger@ni.com>
CC: Tom Rini <trini@konsulko.com>
2025-09-25 18:53:07 -06:00
Tom Rini
0d5d489ab1 Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sh
RZG2 boot failure fix for boot with TFA which does not pass DT, and
R-Car Gen4 PCIe controller driver alignment with Linux fixes.
2025-09-25 18:50:11 -06:00
Marek Vasut
19c292a8c5 pci: pcie-rcar-gen4: Add missing 1ms delay after PWR reset assertion
R-Car V4H Reference Manual R19UH0186EJ0130 Rev.1.30 Apr. 21, 2025 page 585
Figure 9.3.2 Software Reset flow (B) indicates that for peripherals in HSC
domain, after reset has been asserted by writing a matching reset bit into
register SRCR, it is mandatory to wait 1ms.

Because it is the controller driver which can determine whether or not the
controller is in HSC domain based on its compatible string, add the missing
delay into the controller driver.

This 1ms delay is documented on R-Car V4H and V4M, it is currently unclear
whether S4 is affected as well. This patch does apply the extra delay on
R-Car S4 as well.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-09-25 23:19:17 +02:00
Marek Vasut
38541b5db5 pci: pcie-rcar-gen4: Assure reset occurs before DBI access
Assure the reset is latched and the core is ready for DBI access.
On R-Car V4H, the PCIe reset is asynchronized and does not take
effect immediately, but needs a short time to complete. In case
DBI access happens in that short time, that access generates an
SError. Make sure that condition can never happen, read back the
state of the reset which should turn the asynchronized reset into
synchronized one, and wait a little over 1ms to add additional
safety margin.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-09-25 23:19:17 +02:00
Marek Vasut
eb69747cd2 pci: pcie-rcar-gen4: Fix inverted break condition in PHY initialization
R-Car V4H Reference Manual R19UH0186EJ0130 Rev.1.30 Apr. 21, 2025 page 4581
Figure 104.3b Initial Setting of PCIEC(example), third quarter of the figure
indicates that register 0xf8 should be polled until bit 18 becomes set to 1.

Register 0xf8 bit 18 is 0 immediately after write to PCIERSTCTRL1 and is set
to 1 in less than 1 ms afterward. The current readl_poll_timeout() break
condition is inverted and returns when register 0xf8 bit 18 is set to 0,
which in most cases means immediately. In case CONFIG_DEBUG_LOCK_ALLOC=y ,
the timing changes just enough for the first readl_poll_timeout() poll to
already read register 0xf8 bit 18 as 1 and afterward never read register
0xf8 bit 18 as 0, which leads to timeout and failure to start the PCIe
controller.

Fix this by inverting the poll condition to match the reference manual
initialization sequence.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-09-25 23:19:17 +02:00
Mathieu Othacehe
9c7e61fccc board: rzg2l: Check the DTB pointer passed by the TF-A.
On the RZG2L platform, the advised
TF-A (https://github.com/renesas-rz/rzg_trusted-firmware-a/tree/v2.5/rzg2l)
does not pass any DTB blob to U-Boot.

On the other hand, the RZG2L part of U-Boot expects a DTB to be passed.  It
means that if one flashes the latest TF-A as well as the mainline U-Boot,
it will crash trying to dereference the NULL DTB pointer before outputing
anything.

Check if the DTB pointer is NULL before trying to use it.

Signed-off-by: Mathieu Othacehe <othacehe@gnu.org>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-09-25 23:18:34 +02:00
Tom Rini
f53fe908ac Merge patch series "Fix boot w/ scriptaddr & minor newline issue"
Wadim Egorov <w.egorov@phytec.de> says:

First patch fixes boot issues with script boot method and the
second patch is a minor formatting fix in our board detection code.

@TI: I think the scriptaddr should be also updated for most TI/K3 and
beagle board boards.

Link: https://lore.kernel.org/r/20250919063948.3093358-1-w.egorov@phytec.de
2025-09-24 07:50:13 -06:00
Wadim Egorov
96971e5090 board: phytec: common: Fix missing newline in error message
The error message in phytec_get_product_name() was missing a newline,
causing log output to be concatenated with subsequent messages. Add
the newline to improve readability.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
2025-09-24 07:50:13 -06:00
Wadim Egorov
ac046ad187 board: phytec: phycore_am6xx: Update scriptaddr
After switching our boards to standard boot, we observed that the
kernel hangs when booting with the "script" boot method over the
network.

The original scriptaddr value was copied from ti_common.env and
remained unused for some time. On phycore-am62x and phycore-am62ax,
however, this address conflicts with the current location where
ATF is loaded (CONFIG_K3_ATF_LOAD_ADDR).

Move scriptaddr to 0x89100000, directly after fdtoverlay_addr_r.
The phycore-am64x is not affected by this issue, but we update it
as well to keep all phycore-am6xx boards consistent.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Reviewed-by: Anshul Dalal <anshuld@ti.com>
2025-09-24 07:50:13 -06:00
Raymond Mao
d3074f3d69 MAINTAINERS: Add myself into the list for MbedTLS
Add myself into the list for MbedTLS.

Signed-off-by: Raymond Mao <raymond.mao@linaro.org>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-09-23 12:37:48 -06:00
Tom Rini
a6caca94fc MAINTAINERS: Update Luka Perkov's roles
Per a private email, drop Luka Perkov from MAINTAINERS entries.

Reviewed-by: Tony Dinh <mibodhi@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-09-23 12:37:40 -06:00
Tom Rini
2f2ab7e13a Prepare v2025.10-rc5
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-09-23 07:33:47 -06:00
Tom Rini
df4c18067f Merge tag 'u-boot-imx-master-20250922' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/27685

- Fix Phycore i.MX93 voltage modes
- Call DM post init function for init_r phase on i.MX8ULP
- Fix ELE FW version print bug on i.MX8UL EVK.
- Fix LPCG number in ccm_reg structure on i.MX93
2025-09-22 08:22:22 -06:00
Primoz Fiser
1f95591cee board: phytec: phycore-imx93: Fix i.MX93 voltage modes
Fix support for i.MX93 voltage modes on phyCORE-i.MX93 SoM boards.

First of all, Kconfig option CONFIG_IMX9_LOW_DRIVE_MODE is gone since
commit c9efcad237 ("imx93_evk: Remove CONFIG_IMX9_LOW_DRIVE_MODE and
ld defconfig") and was replaced by runtime detection mechanism. Thus
lets use is_voltage_mode() instead of Kconfig to detect CPU type and
select proper voltage mode.

Secondly, 1400MHz ND mode (Nominal Drive) requiring 0.85V BUCK voltage
was not supported with current power_init_board() PMIC settings. Add
check also for this CPU type and set BUCK voltage accordingly.

Last but not least, add printf() printouts about PMIC voltage mode to
the console. This makes it more apparent and verbose about voltage mode
in use. Also our internal tests depend on this printout to catch issues
with i.MX93 CPU types and set PMIC voltage modes.

Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
2025-09-21 09:09:13 -03:00
Ye Li
2d7a6f19bb arm: imx9: Fix LPCG number in ccm_reg structure
The LPCG number on iMX93 and iMX91 is 127 not 122. The wrong
value is used in ccm_reg structure and Coverity reports several
issues as out-of-bounds write.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2025-09-21 09:08:50 -03:00
Ye Li
aee2357987 imx8ulp_evk: Fix ELE FW version print bug
According to latest ELE Get FW version API, the FW version word is defined
as below. The patch version only has 4 bits and minor version has 12 bits.
However, the codes use 8 bits for patch version and minor version. Add the
patch to fix the issue.

ELE firmware version
[31] - When set indicates a dirty build.
[30] - Reserved
[29:28] - Hotfix version.
[27] - When set, indicate that ELE FW is authenticated and operational.
[26:25] - Reserved
[24] - When set, indicate that an alternative FW is running.
[23:16] - Indicate the major version. This byte is checked against the
version set in the fuses to determine if the FW execution can be authorized
[15:4] - Indicate the minor version.
[3:0] - Indicate the patch version.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2025-09-21 09:08:26 -03:00
Ye Li
9390876cc8 imx: imx8ulp: Call DM post init function for init_r phase
The ELE MU driver needs to be probed at init_r phase as well because
some ELE APIs will be called.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2025-09-21 09:07:58 -03:00
Kunihiko Hayashi
d33b21b7e2 ARM: Remove mistyped GICV3 definition from ARCH_SYNQUACER
The config "GIC_V3" seems to be typo, and currently "GICV3" remains
disabled. This should be removed until needed.

Fixes: 5cd4a355e0 ("board: synquacer: Add DeveloperBox 96boards EE support")
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
2025-09-20 12:02:58 -06:00
Tom Rini
f28891d444 Merge patch series "board: dhelectronics: Check pointer before access in dh_get_value_from_eeprom_buffer()"
This series from Marek Vasut <marek.vasut@mailbox.org> cleans up some of
the common code between dhelectronics platforms.

Link: https://lore.kernel.org/r/20250907010103.667681-1-marek.vasut@mailbox.org
2025-09-17 09:06:53 -06:00
Marek Vasut
7cd9d2db26 board: dhelectronics: Use isascii() before isprint() in dh_read_eeprom_id_page()
The isprint() checks printability across all 256 characters, some of the
upper 128 characters are printable and produce artifacts on UART. Call
isascii() first to only consider the bottom 7bit ASCII characters as
printable, and then check their printability using isprint(). This fixes
a rare misprint in case the ID page content is uninitialized or corrupted.

Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
Reviewed-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
2025-09-17 09:06:37 -06:00
Marek Vasut
5634cf1afc board: dhelectronics: Check pointer before access in dh_get_value_from_eeprom_buffer()
The eip pointer in dh_get_value_from_eeprom_buffer() might be NULL.
The current NULL pointer check happens too late, after the eip was
accessed in variable assignment. Reorder the two, so the NULL pointer
check happens first, and any access second, otherwise the access may
trigger a hang or other undefined behavior.

Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
Reviewed-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
2025-09-17 09:06:37 -06:00
Tom Rini
eea731b50c Merge tag 'u-boot-imx-master-20250917' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/27660

- Restore the support for the i.MX95 A0 silicon.
2025-09-17 07:54:06 -06:00
Tom Rini
a3ec093512 Merge patch series "Hyperflash boot fixes for j721e/j7200"
Anurag Dutta <a-dutta@ti.com> says:

This series introdues a couple of small fixes that involves
enabling hyperflash at R5 SPL and u-boot proper stage and
Kconfig changes that are required for HBMC boot on j721e/j7200

Test logs:
https://gist.github.com/anuragdutta731/0f56e8d9bdf0cfe3d221c69d09a58704

Link: https://lore.kernel.org/r/20250917094659.3922343-1-a-dutta@ti.com
2025-09-17 07:52:31 -06:00
Anurag Dutta
6d4320d761 arm: dts: k3-j721e-r5-common-proc-board: Enable HBMC in R5 SPL stage
Enable HBMC in the R5 SPL stage

Fixes: c9df79ee64 ("arm: dts: k3-j721e-r5-common: Add HBMC overrides for R5 SPL")
Signed-off-by: Anurag Dutta <a-dutta@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
2025-09-17 07:51:32 -06:00
Anurag Dutta
517744041f configs: j7200_evm_*_defconfig: Enable HBMC and MUX_MMIO at SPL
Add the HBMC and MUX_MMIO configs in the SPL and u-boot proper
stage for successful HBMC boot.

Signed-off-by: Anurag Dutta <a-dutta@ti.com>
2025-09-17 07:51:32 -06:00
Anurag Dutta
96cbe36c0b configs: j721e_evm_r5: Enable HBMC and MUX_MMIO at SPL
Add the HBMC and MUX_MMIO configs in the R5 SPL stage for
successful HBMC boot.

Signed-off-by: Anurag Dutta <a-dutta@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
2025-09-17 07:51:32 -06:00
Anurag Dutta
dd4039e380 mtd: Kconfig: Add SPL_MUX_MMIO dependency to HBMC driver
MUX_MMIO is needed by HBMC in SPL stage. Enable it at SPL as well
as u-boot proper stage.

Signed-off-by: Anurag Dutta <a-dutta@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
2025-09-17 07:51:32 -06:00
Michal Simek
5b35aa9da1 xilinx: Disable SPL_OS_BOOT for Zynq and ZynqMP
The commit 210702ae6c ("spl: spi: fix falcon mode for spi boot") fixed
the logic of spl_start_uboot() where 0 means OS boot and 1 means u-boot.
Zynq/ZynqMP enable OS_BOOT by default but it was never really be used
that's why disable it to boot via U-Boot phase all the time.

Signed-off-by: Michal Simek <michal.simek@amd.com>
2025-09-17 07:50:05 -06:00
Tom Rini
097ef53d63 Merge tag 'u-boot-stm32-20250917' of https://source.denx.de/u-boot/custodians/u-boot-stm
CI: https://source.denx.de/u-boot/custodians/u-boot-stm/-/pipelines/27648

- Fix net suport for STM32MP2
- Fix to prevent hang in clk-stm32-core for STM32MP13
- Fix ethernet init for DH STM32MP1
2025-09-17 07:49:15 -06:00
Anurag Dutta
f6d5bda0e3 board: ti: am57xx: Remove "ti/omap/" from name_fit_config
Commit 649f4a7d3c ("board: ti: am57xx: Set fdtfile from C code
instead of findfdt script") prepends "ti/omap/" to the actual name
of the fdtfile whereas fit image boot needs exact dtb name. So, remove
"ti/omap" from name_fit_config by substituting it with an empty string.

Fixes: 649f4a7d3c ("board: ti: am57xx: Set fdtfile from C code instead of findfdt script")
Signed-off-by: Anurag Dutta <a-dutta@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
2025-09-17 07:48:52 -06:00
Alice Guo
b3bbbf5fee imx95_evk: Restore support for i.MX95 A0 silicon
This patch is used to restore support for i.MX95 A0 silicon. To avoid
duplicating defconfig, imx95.config is added and can be shared between
imx95_a0_19x19_evk_defconfig and imx95_19x19_evk_defconfig.

container.cfg and imximage.cfg are used to created .cfgout files that
are be passed to mkimage with -n to build flash.bin. Now they have been
deleted and replaced by adding their content to properties of node which
type is nxp-imx9image under binman node.

Fixes: 9936724aa9 ("imx95_evk: Add i.MX95 B0 support")

Signed-off-by: Alice Guo <alice.guo@nxp.com>
Tested-By: Tim Harvey <tharvey@gateworks.com> # imx95-19x19-evk (rA0)
2025-09-17 08:16:05 -03:00
Alice Guo
5c389e6190 binman: add a new entry type to support .bin file generation for the i.MX95 platform
To support passing specific commands defined in enum imx8image_cmd to
the imx8image_copy_image() function, this patch introduces a new entry
type nxp-imx9image. This entry generates a plain text data file
containing the relevant commands, enabling flexible configuration during
image creation.

Signed-off-by: Alice Guo <alice.guo@nxp.com>
2025-09-17 08:16:04 -03:00
E Shattow
b82fa9d752 board: starfive: visionfive2: deprecate mixed-case product ids VF7110a VF7110b
Per recent discussion [1] product IDs VF7110A or VF7110B from EEPROM are
sufficient to select for VisionFive 2 1.2a or VisionFive 2 1.3b boards.
There are no VisionFive 2 products with mixed-case product IDs in EERPOM
so factor out the unnecessary select case conditional.

1: https://lore.kernel.org/u-boot/ZQ2PR01MB1307D97D2C9566B8EE443812E6062@ZQ2PR01MB1307.CHNPR01.prod.partner.outlook.cn/

Signed-off-by: E Shattow <e@freeshell.de>
Reported-by: Hal Feng <hal.feng@starfivetech.com>
2025-09-16 10:16:54 -06:00
Marek Vasut
0f4bfee3cf ARM: stm32: Perform node compatible check for KS8851 early
Check the compatible string of ethernet1 node for KS8851 very early on,
before calling uclass_get_device_by_of_path() which might initialize
the device and possibly attempt to configure MAC address into device
which is not KS8851. Doing the compatibility check early prevent this.

Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2025-09-16 17:36:53 +02:00
Marek Vasut
483e19b0ad net: dwc_eth_qos: Fix support for stm32mp2 platform
The layout of SYSCFG_ETHnCR on STM32MP25xx is slightly different yet again.
Add missing swizzling to program the correct register with the correct content.

Fixes: 20afca89ed ("net: dwc_eth_qos: add support of stm32mp2 platform")
Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
Reviewed-by: Christophe ROULLIER<christophe.roullier@foss.st.com>
2025-09-16 15:24:30 +02:00
Marek Vasut
7b9b34aa6d clk: stm32: Pass udevice pointer to clk_register_composite()
The clk_register_composite() does clk_resolve_parent_clk() look up,
which requires valid udevice pointer. Do not pass NULL, pass a valid
device pointer to prevent hang on registering ck_usbo_48m clock on
STM32MP13xx.

Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2025-09-16 15:24:30 +02:00
Ye Li
2dbde3f9b0 arm: armv8: Fix spl recover data section broken
SPL recover data section is broken which causes reboot failure on
some i.MX platforms (iMX8QM/iMX95).
The global variable cold_reboot_flag is assigned to weak reset_flag
function which always return 1, so restore never been executed in
warm reboot.

Fixes: 1c37e59bfb ("arm: armv8: Improve SPL data save and restore implementation")
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2025-09-13 17:59:23 -06:00
Anshul Dalal
210702ae6c spl: spi: fix falcon mode for spi boot
spl_start_uboot is a board overridable function that switches to falcon
boot mode on return value of 0.

Though for SPI, the falcon boot mode was being enabled on return value
of 1 which is not the correct behaviour. Therefore this patch fixes it
to the expected boot flow.

Fixes: 14509a28aa ("spl: spi: Consolidate spi_load_image_os into spl_spi_load_image")
Signed-off-by: Anshul Dalal <anshuld@ti.com>
2025-09-12 08:24:21 -06:00
Tom Rini
c9800dc906 Merge patch series "Fix dma_addr_t for R5 SPL"
Anshul Dalal <anshuld@ti.com> says:

On various TI's K3 platforms boot failure was observed on SPI NOR since the
commit 5609f200d0 ("arm: Kconfig: enable LTO for ARCH_K3"). This issue was
root caused to stack corruption by the 'udma_transfer' function. Where the local
variable 'paddr' of type 'dma_addr_t' was being written to as a 64-bit value
which overwrote the stack frame of the caller (dma_memcpy) as only 32-bits had
been reserved for paddr on the stack, specifically the r4 register in the frame
of dma_memcpy was being overwritten with a 0.

drivers/dma/ti/k3-udma.c:2192:

	int udma_transfer(...)
	{
		...
		dma_addr_t paddr = 0;

		...
		/* paddr was written to as 64-bit value here */
		udma_poll_completion(uc, &paddr);
	}

drivers/dma/dma-uclass.c:234:

	int dma_memcpy(...)
	{
		dma_addr_t destination;
		dma_addr_t source;
		int ret;

		...

		/* This call resolves to udma_transfer */
		ret = ops->transfer(...);

		...

		dma_unmap_single(destination, ...);
		dma_unmap_single(...);
		return ret;
	}

Enabling LTO changed how gcc mapped local variables of dma_memcpy to CPU
registers, where earlier the bug was hidden since the overwritten register
'r4' was allotted to 'ret' but was allotted to 'destination' once LTO was
enabled. And since the overwritten value was 0, the bug remained undetected
as it just meant ret was 0, but having 'destination' set to 0 caused
dma_unmap_single to fail silently leading to boot failures.

The fix entails enabling DMA_ADDR_T_64BIT which changes dma_addr_t from u32 to
u64 for the R5 SPL thus reserving enough space for 'paddr' to prevent the
overflow.

Link: https://lore.kernel.org/r/20250903115207.572304-1-anshuld@ti.com
2025-09-11 10:03:12 -06:00
Anshul Dalal
7bcc604ef8 config: arch: k3: enable DMA_ADDR_T_64BIT
ARCH_K3 encompasses both 32 and 64-bit cores on the same SoC, though the
DMA addresses are always 64-bit in size.

With the current implementation, the R5 SPL uses a u32 for dma_addr_t
which leads to data overflow when functions such as k3_nav_*_pop_mem try
to write a 64-bit address to dma_addr_t variable.

In certain cases it leads to stack corruption which manifest as boot
failures on certain compilers, such as SPI boot on GCC 14.2 or 13.3.

Therefore this patch selects CONFIG_DMA_ADDR_T_64BIT for all ARCH_K3.

Fixes: ffcc66e8fe ("dma: ti: add driver to K3 UDMA")
Signed-off-by: Anshul Dalal <anshuld@ti.com>
Reviewed-by: Prasanth Babu Mantena <p-mantena@ti.com>
2025-09-11 10:03:02 -06:00
Anshul Dalal
e9e55fefb1 dma: ti: k3-udma: fix dma_addr_t typecasts
dma_addr_t is used to store any valid DMA address which might not
necessarily be the same size as host architecture's word size. Though
various typecasts in k3's dma and usb driver expect dma_addr_t to be the
same size as the word size.

This leads the compiler to throw a "cast from pointer to integer of
different size" warning when the condition is not met, for example when
enabling CONFIG_DMA_ADDR_T_64BIT for the R5 core.

Therefore this patch fixes the typecasts by using 'uintptr_t' as an
intermediary type which is guaranteed to be the same size as void* on
the host architecture. Thus, eliminating the compiler warning.

Signed-off-by: Anshul Dalal <anshuld@ti.com>
2025-09-11 10:03:02 -06:00
Heiko Thiery
fd7510e516 env: fix config dependency for ENV_OFFSET_REDUND_RELATIVE_END
Since commit 5fb88fa725 "env: Rename SYS_REDUNDAND_ENVIRONMENT to ENV_REDUNDANT"
the option SYS_REDUNDAND_ENVIRONMENT is no longer available and should be
renamed to ENV_REDUNDANT.

Fixes: 95f03ee65c ("env: mmc: fix offsets relative to the end of the partition")
Signed-off-by: Heiko Thiery <heiko.thiery@gmail.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2025-09-11 09:59:47 -06:00
Tom Rini
000fbc7ae5 configs: Resync with savedefconfig
Resync all defconfig files using qconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-09-10 15:25:09 -06:00
Heinrich Schuchardt
2083378ff0 spl: SPL_DM_SPI_FLASH depends on SPL_DM_SPI
The SPI flash driver does not build without SPI support enabled.

Fixes: 4151f4f822 ("spl: Rework and tighten some dependencies")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Anshul Dalal <anshuld@ti.com>
2025-09-10 13:44:44 -06:00
E Shattow
1a7882de8c configs: starfive: Add visionfive2 CONFIG_DNS enabled
Enable CONFIG_DNS for visionfive2 board target. With CONFIG_PROT_DNS_LWIP
enabled and CONFIG_CMD_DNS disabled this restores DNS functionality
displaced by LwIP DNS refactoring during the merge window.

Signed-off-by: E Shattow <e@freeshell.de>
2025-09-09 08:11:07 -06:00
Patrick Rudolph
77ef938212 configs: Fix crash on coreboot x86
Booting u-boot as payload with coreboot's main branch is currently broken
since commit [1] on x86 as U-boot assumes the active GDT matches what
U-Boot would have installed in start16.S.

Make no assumptions and always load the GDT when building as coreboot
payload to make sure the segment registers are actually matching the GDT.

Fixes #GP seen when booting U-Boot as coreboot payload.

1: https://review.coreboot.org/c/coreboot/+/87255

Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Link: https://review.coreboot.org/c/coreboot/+/87255
Reviewed-by: Tom Rini <trini@konsulko.com>
2025-09-08 14:28:09 -06:00
Tom Rini
7a4f3c5652 Prepare v2025.10-rc4
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-09-08 10:17:59 -06:00
Boon Khai Ng
bc52200ebf MAINTAINERS: Add entry for DesignWare XGMAC driver
Add a MAINTAINERS entry for the DesignWare XGMAC network driver to
ensure future patches are properly routed for review and support.

Signed-off-by: Boon Khai Ng <boon.khai.ng@altera.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2025-09-08 09:16:18 -06:00
Tom Rini
8c981709e0 configs: Resync with savedefconfig
Resync all defconfig files using qconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-09-08 08:51:08 -06:00
Tom Rini
a433ac255b Merge patch series "AM57 boot fixes"
Anurag Dutta <a-dutta@ti.com> says:

This patch series migrates from .h to .env format for am57xx/dra7xx.
Also, we do relevant changes so that the fdtfile can be set from C code.

logs : https://gist.github.com/anuragdutta731/82560cc9bc958ca70a25a95a7031eeea

Link: https://lore.kernel.org/r/20250901061659.986164-1-a-dutta@ti.com
2025-09-08 08:44:54 -06:00
Anurag Dutta
878888fd07 board: ti: dra7xx: Set fdtfile from C code instead of findfdt script
We now can provide a map and have the standard fdtfile variable set from
code itself. This allows for bootstd to "just work".

Signed-off-by: Anurag Dutta <a-dutta@ti.com>
2025-09-08 08:44:33 -06:00
Anurag Dutta
649f4a7d3c board: ti: am57xx: Set fdtfile from C code instead of findfdt script
We now can provide a map and have the standard fdtfile variable set from
code itself. This allows for bootstd to "just work".

Signed-off-by: Anurag Dutta <a-dutta@ti.com>
2025-09-08 08:44:33 -06:00
Anurag Dutta
bc020bf53a board: ti: am57xx: Change to using .env
Move to using .env file for setting up environment variables
for am57xx and dra7xx.

Signed-off-by: Anurag Dutta <a-dutta@ti.com>
2025-09-08 08:44:33 -06:00
Anurag Dutta
5138d3a561 include: env: ti: Use .env for environment variables
Add omap common environment variables to .env. We retain the old-style C
environment .h files to maintain compatibility with other omap devices that
have not moved to using .env yet.

Signed-off-by: Anurag Dutta <a-dutta@ti.com>
2025-09-08 08:44:33 -06:00
Tom Rini
7d5312e162 Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sh 2025-09-08 08:33:30 -06:00
Marek Vasut
b5294efd21 arm64: renesas: r8a779g3: Use $loadaddr in bootcmd on Retronix R-Car V4H Sparrow Hawk board
Avoid use of hard-coded address in boot command, instead use $loadaddr
which is the default load address. This improves consistency of the
environment on this board.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-09-07 20:29:50 +02:00
Marek Vasut
275978df0d ARM: renesas: Enable CONFIG_ENV_VARS_UBOOT_CONFIG on all boards
The CONFIG_ENV_VARS_UBOOT_CONFIG extends U-Boot environment with
variables arch/board/board_name/soc/vendor, which can be used to
discern different devices from each other based purely on U-Boot
environment variables.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-09-07 20:29:14 +02:00
Tom Rini
328747974a Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-samsung
- Fix issues reported by smatch
- exynos4210-origen cleanups
- e850-96 improvements
2025-09-05 08:15:16 -06:00
Tom Rini
76b8edbc73 Merge branch 'staging' of https://source.denx.de/u-boot/custodians/u-boot-tegra
Branch contains minor improvents for ASUS SL101 and Jetson Nano along
with support for Microsoft Surface 2 tablet.
2025-09-03 15:21:14 -06:00
Tom Rini
8d2bde7af1 Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sh
- Fix an issue reported by smatch in rzg2l pinctrl driver
2025-09-03 15:19:15 -06:00
Andrew Goodbody
93c3404de9 spi: exynos: Remove extra term from test
In spi_rx_tx there comes a test for execution of a code block that
allows execution if rxp is not NULL or stopping is true. However all the
code in this block relies on rxp being valid so allowing entry just if
stopping is true does not make sense. So remove this from the test
expression leaving just a NULL check for rxp.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2025-09-03 19:32:38 +09:00
Andrew Goodbody
8705ee4b6d pinctrl: rzg2l: Variable may not have been assigned to
In rzg2l_pinconf_set and rzg2l_get_pin_muxing if the call to
rzg2l_selector_decode fails then the variable pin may not have been
assigned to. Remove the use of pin from the error message. Also update
the error message to show the invalid selector used instead of port
which will be the error code returned.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Paul Barker <paul@pbarker.dev>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-09-03 02:45:08 +02:00
Tom Rini
d367be2b13 Merge tag 'u-boot-rockchip-20250831' of https://source.denx.de/u-boot/custodians/u-boot-rockchip
CI: https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/pipelines/27522

- New Board support:
  rk3588 Xunlong Orange Pi 5 Ultra;
  rk3588s GameForce Ace;
  rk3576 ArmSoM Sige5;

- rk3328 soc fixes;
- usb controller and phy fixes;
- new rk3328 ddr timing;
- other board level updates;
2025-09-01 09:50:01 -06:00
Tom Rini
5e711fe26b Merge tag 'efi-2025-10-rc4' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request efi-2025-10-rc4.

CI:

* https://source.denx.de/u-boot/custodians/u-boot-efi/-/pipelines/27527

Documentation:

* Rephrasing and text corrections for buildman

UEFI:

* Serial: Use correct EFI status type
* Let EFI_HTTP_BOOT select CMD_DHCP
* Let EFI_VARIABLES_PRESEED depend on !COMPILE_TEST
2025-09-01 07:51:04 -06:00
Henrik Grimler
949f71c13e ARM: exynos: pinmux: add newlines to debug messages
To make stdout messages easier to read and understand.

Signed-off-by: Henrik Grimler <henrik@grimler.se>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2025-09-01 18:27:17 +09:00
Henrik Grimler
354b3d7892 ARM: exynos: pinmux: fix parentheses alignments
For multi-line commands the lines should preferably be aligned with
the opening parenthesis.

Signed-off-by: Henrik Grimler <henrik@grimler.se>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2025-09-01 18:27:17 +09:00
Henrik Grimler
869a18c7e3 ARM: exynos: use correct exynos4210-origen SoC in Kconfig
There exists both a Origen board based on exynos4210, and a board
based on exynos4412. U-boot only supports the one based on exynos
4210, but Kconfig string was accidentally written as Exynos4412 Origen
in previous migration to Kconfig. Fix the string to clear up
confusion, and to not give the impression that both types of Origen
boards are supported.

Fixes: 72df68cc6b ("exynos: kconfig: move board select menu and common settings")

Signed-off-by: Henrik Grimler <henrik@grimler.se>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2025-09-01 18:27:17 +09:00
Svyatoslav Ryhel
392b5b426c board: transformer-t20: add separate env for SL101
SL101 unlike TF101/G has no Lid sensor, so lets add a separate env for
SL101 without Lid sensor used.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2025-09-01 11:35:54 +03:00
Svyatoslav Ryhel
bd903be324 ARM: tegra20: transformer: fix Hall sensor behavior
Hall sensor found in SL101 is not used for closed dock detection as on
TF101 or TF101G, it is used to detect if keyboard slider is out. To address
this, lets move Lid sensor switch into TF101/G trees and add Tablet mode
switch into SL101 tree.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2025-09-01 11:23:21 +03:00
Sam Protsenko
e1d02147b3 configs: e850-96: Enable Ethernet
LAN9514 is a chip on E850-96 board which acts as a USB host hub and
Ethernet controller. It's controlled via USB lines when DWC3 is
configured to be in USB host role (by setting the "dr_mode" property to
"host" value in e850-96 dts file).

Enable network support and LAN9514 chip support. This makes Ethernet
functional on E850-96 board.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2025-09-01 16:37:13 +09:00
Sam Protsenko
88a465b47c configs: e850-96: Enable USB host support
Exynos850 SoC has a dual-role USB controller which can be configured in
USB host role. As it's the only one USB controller on the board, it's
shared between "device" USB connector (micro-USB) and host USB
connectors. The hardware automatically powers on the host related parts
when the micro-USB cable (for device role) is being disconnected. Also,
as U-Boot lacks dynamic USB role switching capability, the only way to
switch the role at the moment is to modify "dr_mode" property in
U-Boot's device tree file here:

    dts/upstream/src/arm64/exynos/exynos850-e850-96.dts

This won't affect the dynamic role switching later in Linux kernel, as a
separate (different) device tree blob is provided to the kernel.

Enable the USB host support and corresponding commands to make it
functional in E850-96 board.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2025-09-01 16:37:13 +09:00
Sam Protsenko
e52e4320ba configs: e850-96: Disable CONFIG_DEFAULT_FDT_FILE
Linux kernel should use some separate device tree obtained from another
source anyway. For example the dtb file can be read from /boot directory
in eMMC rootfs partition, either by GRUB or U-Boot. Using U-Boot's
device tree blob to provide it to the kernel (when
CONFIG_DEFAULT_FDT_FILE is set and nobody else overrides this choice)
might lead to undesired effects when booting the OS. For example, if a
user sets "dr_mode" property to "host" value in U-Boot's dts to enable
USB host capabilities in U-Boot, it might confuse usb-conn-gpio driver
in Linux kernel later like this:

    platform connector: deferred probe pending: usb-conn-gpio:
    failed to get role switch

Disable CONFIG_DEFAULT_FDT_FILE option to avoid any possible confusion.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2025-09-01 16:37:13 +09:00
Sam Protsenko
75f75832d0 board: samsung: e850-96: Add bootdev var to choose boot device
Provide a way for the user to select which storage to load the LDFW
firmware from, by setting the corresponding environment variables:
  - bootdev: block device interface name
  - bootdevnum: block device number
  - bootdevpart: partition number

This might be useful when the OS is flashed and booted from a different
storage device than eMMC (e.g. USB flash drive). In this case it should
be sufficient to just set:

    => setenv bootdev usb
    => env save

assuming that the USB drive layout follows the same partitioning scheme
as defined in $partitions.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2025-09-01 16:37:13 +09:00
Sam Protsenko
c542140d7c board: samsung: e850-96: Extract device info from fw loading code
Make it possible to provide the information about storage device where
LDFW firmware resides to the firmware loading routine. The firmware
loader code shouldn't have that data hard-coded anyway, and it also
allows for implementing more dynamic behavior later, like choosing the
storage device containing LDFW via some environment variables.

No functional change.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2025-09-01 16:37:13 +09:00
Sam Protsenko
8fefc2eb96 board: samsung: e850-96: Configure PMIC regulators
Make use of PMIC configuration routines and enable all LDOs that might
be useful for bootloader and kernel. The most crucial regulator being
enabled at the moment is LDO24 which provides power to LAN9514 chip.
That makes Ethernet controller and USB hub functional.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2025-09-01 16:37:12 +09:00
Sam Protsenko
17b1d78484 board: samsung: e850-96: Add PMIC code
Add functions for configuring voltage regulators on S2MPU12 PMIC chip
for E850-96 board. The chip is accessed by commanding APM core (via
ACPM IPC protocol) to perform corresponding transfers over I3C bus.

The most important regulator being set up is LDO24 used for LAN9514 chip
power. As LAN9514 implements USB hub and Ethernet controller
functionality, it's crucial to enable and configure LDO24 to be able to
use it further. While at it, configure the rest of regulators that might
be needed later, both in the bootloader and in kernel.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2025-09-01 16:37:12 +09:00
Sam Protsenko
6ebd9aa6d3 board: samsung: e850-96: Add ACPM code
Add functions to access I3C bus via APM (Active Power Management) core
by using ACPM IPC protocol. It will be further used for configuring PMIC
chip voltage regulators.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2025-09-01 16:37:12 +09:00
Sam Protsenko
cb64735bdd board: samsung: e850-96: Set ethaddr
Set the environment variable for Ethernet MAC address (ethaddr). Use the
SoC ID to make sure it's unique. It'll be formatted in a way that
follows the consecutive style of the serial number ("serial#" variable),
i.e.:

    OTP_CHIPID0   = 0xf51c8113
    OTP_CHIPID1   = 0x236
    get_chip_id() = 0x236f51c8113
    serial#       = 00000236f51c8113
    ethaddr       = 02:36:f5:1c:81:13

where corresponding bytes of the MAC address are:

    mac_addr[0]   = 0x02   // OTP_CHIPID1[15:8]
    mac_addr[1]   = 0x36   // OTP_CHIPID1[7:0]
    mac_addr[2]   = 0xf5   // OTP_CHIPID0[31:24]
    mac_addr[3]   = 0x1c   // OTP_CHIPID0[23:16]
    mac_addr[4]   = 0x81   // OTP_CHIPID0[15:8]
    mac_addr[5]   = 0x13   // OTP_CHIPID0[7:0]

because OTP_CHIPID1 has only 16 significant bits (with actual ID
values), and all 32 bits of OTP_CHIPID0 are significant.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2025-09-01 16:37:12 +09:00
Sam Protsenko
3b36c242eb usb: host: dwc3-of-simple: Add exynos850 compatible
Enable support for Exynos850 SoC in DWC3 host glue layer driver.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Marek Vasut <marek.vasut@mailbox.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2025-09-01 16:37:12 +09:00
Andrew Goodbody
c901732558 clk: exynos: Fix always true test
In exynos7420_peric1_get_rate the variable ret is declared as an
'unsigned int' but is then used to receive the return value of
clk_get_by_index which returns an int. The value of ret is then tested
for being less than 0 which will always fail for an unsigned variable.
Fix this by declaring ret as an 'int' so that the test for the error
condition is valid.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2025-09-01 16:37:08 +09:00
Simon Glass
d20b8792c5 arm: Fix swtiching typo
This should say 'switching', so fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2025-08-30 20:45:33 +02:00
Adriano Carvalho
1041ce48a9 doc: Capitalize the word Buildman whenever it's used as a proper noun
This consistency reads a bit nicer.

Signed-off-by: Adriano Carvalho <adrianocarvalho.pt@gmail.com>
2025-08-30 20:45:33 +02:00
Adriano Carvalho
0492657c74 doc: Rephrase to be more precise and less confusing (build)
It was "... doing the same build ... will not trigger a rebuild".

Signed-off-by: Adriano Carvalho <adrianocarvalho.pt@gmail.com>
2025-08-30 20:45:33 +02:00
Adriano Carvalho
01bf38a05e doc: Rephrase to read a bit nicer
Reads better.

Signed-off-by: Adriano Carvalho <adrianocarvalho.pt@gmail.com>
2025-08-30 20:45:33 +02:00
Adriano Carvalho
ac0e3d2541 doc: Rephrase to be more clear
It might not be clear what is meant with "to make sure the shell leaves it alone".

Signed-off-by: Adriano Carvalho <adrianocarvalho.pt@gmail.com>
2025-08-30 20:45:33 +02:00
Adriano Carvalho
77c72bcb0d doc: Rephrase in a simpler way
It reads a bit nicer.

Signed-off-by: Adriano Carvalho <adrianocarvalho.pt@gmail.com>
2025-08-30 20:45:33 +02:00
Adriano Carvalho
b14d24af40 doc: Add riscv and unfold the list with the architecture/code name
riscv was missing from the list.
To some, the architecture's name may not be obvious from the code name.

Signed-off-by: Adriano Carvalho <adrianocarvalho.pt@gmail.com>
2025-08-30 20:45:33 +02:00
Adriano Carvalho
76733999b0 doc: Use "supports" instead of "has"
Strictly speaking, "has" doesn't make sense.
"supports" seems like a better word and it probably was what the original author meant.

Signed-off-by: Adriano Carvalho <adrianocarvalho.pt@gmail.com>
2025-08-30 20:45:33 +02:00
Adriano Carvalho
45d32d2911 doc: Quote all long form options using double backticks/grave accents
Otherwise, the two dashes are rendered as just one.

Signed-off-by: Adriano Carvalho <adrianocarvalho.pt@gmail.com>
2025-08-30 20:45:33 +02:00
Adriano Carvalho
6a006c56ee doc: Fix obvious typos and minor improvements
These are fixes to what looks like obvious typos.
Some minor improvments are also included, such as:
- Write "symbolic link" instead of symlink
- Correct capitalization for LLVM (all caps)
- Remove dead link and surrounding sentence

Signed-off-by: Adriano Carvalho <adrianocarvalho.pt@gmail.com>
2025-08-30 20:45:33 +02:00
Jan Kiszka
6deac6147b efi: Select also CMD_DHCP from EFI_HTTP_BOOT
This is needed because distro_efi_read_bootflow_net will then need
dhcp_run which is not already enabled by CMD_NET.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2025-08-30 20:45:33 +02:00
Tom Rini
4910a7cc69 efi_loader: Make EFI_VARIABLES_PRESEED depend on !COMPILE_TEST
When doing compile testing build we cannot rely on having a valid file
for EFI_VAR_SEED_FILE to exist, so disable this option when doing
compile tests.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Acked-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2025-08-30 20:45:33 +02:00
Andrew Goodbody
c04fb8b505 efi: serial: Use correct EFI status type
int is not sufficient to hold and test the return from an EFI function
call. Use efi_status_t instead so that the test can work as expected.

This issue was found by Smatch.

Fixes: 275854baee ("efi: Add a serial driver")
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2025-08-30 20:45:33 +02:00
Jonas Karlman
0e68a93d7c rockchip: rk3588-generic: Move usb nodes to board dts
After the commit 7a53abb183 ("rockchip: rk3588: Remove USB3 DRD nodes
in u-boot.dtsi") was merged for v2024.10 there is no reason to keep the
usb nodes for the Generic RK3588 board in the board u-boot.dtsi.

Move usb related nodes from board u-boot.dtsi to main board device tree.

While at it, also drop use of the usb3-phy as we only want to enable the
usb2-phy to be compatible with as many boards as possible.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-08-31 00:48:15 +08:00
Jonas Karlman
be585d4916 rockchip: rk3576: Disable USB3OTG0 U3 port early
The RK3576 SoC comes with USB OTG support using a DWC3 controller with
a USB2 PHY and a USB3 PHY (USBDP PHY).

Some board designs may not use the USBDP PHY for USB3 purpose. For these
board to use USB OTG the input clock source must change to use UTMI clk
instead of PIPE clk.

Change to always disable the USB3OTG0 U3 port early and leave it to the
USBDP PHY driver to re-enable the U3 port when a usb3-phy is described
in the board device tree.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-08-31 00:48:15 +08:00
Jonas Karlman
9d39a56922 rockchip: rk3588: Disable USB3OTG U3 ports early
The RK3588 SoC comes with USB OTG support using a DWC3 controller with
a USB2 PHY and a USB3 PHY (USBDP PHY).

Some board designs may not use the USBDP PHY for USB3 purpose. For these
board to use USB OTG the input clock source must change to use UTMI clk
instead of PIPE clk.

Change to always disable the USB3OTG U3 ports early and leave it to the
USBDP PHY driver to re-enable the U3 port when a usb3-phy is described
in the board device tree.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-08-31 00:48:15 +08:00
Jonas Karlman
fca01a8792 phy: rockchip: typec: Fix improper use of UCLASS_PHY
The Rockchip TypeC glue driver improperly present itself as a UCLASS_PHY
driver, without ever implementing the required phy_ops.

This is something that in special circumstances can lead to a NULL
pointer dereference followed by a SError crash.

Change the glue driver to use UCLASS_NOP to fix this.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-08-31 00:48:15 +08:00
Jonas Karlman
c8e6a7131d phy: rockchip: inno-usb2: Fix improper use of UCLASS_PHY
The Rockchip USB2PHY glue driver improperly present itself as a
UCLASS_PHY driver, without ever implementing the required phy_ops.

This is something that in special circumstances can lead to a NULL
pointer dereference followed by a SError crash.

Change the glue driver to use UCLASS_NOP to fix this.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-08-31 00:48:15 +08:00
Jonas Karlman
12dd645914 phy: rockchip: naneng-combphy: Use syscon_regmap_lookup_by_phandle
Change to use syscon_regmap_lookup_by_phandle() helper instead of
finding the syscon udevice and making a call to syscon_get_regmap().

No runtime change is expected with this simplication.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-08-31 00:48:15 +08:00
Jonas Karlman
8a3d377d4c phy: rockchip: naneng-combphy: Simplify init ops
The init ops for Rockchip COMBPHY driver is more complex than it needs
to be, e.g. declaring multiple init functions that only differ in the
error message.

Simplify the init ops based on code from the Linux mainline driver.

This change also ensure that errors returned from combphy_cfg() and
reset_deassert_bulk() is propertly propagated to the caller. No other
runtime change is expected with this simplication.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-08-31 00:48:15 +08:00
Jonas Karlman
dfd2774cfc phy: rockchip: naneng-combphy: Fix Generic PHY reference counting
Generic PHY reference counting helps ensure driver ops for init/exit and
power on/off are called at correct state. For this to work the PHY
driver must initialize PHY-id to a persistent value in of_xlate ops.

The Rockchip COMBPHY driver does not initialize the PHY-id field, this
typically lead to use of unshared reference counting among different
struct phy instances.

Initialize the PHY-id in of_xlate ops to ensure use of shared reference
counting among all struct phy instances.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-08-31 00:48:15 +08:00
Jonas Karlman
1e8370318f phy: rockchip: usbdp: Simplify init ops
With working shared reference counting for Generic PHY ops there is no
need for the Rockchip USBDP PHY driver to keep its own status (reference
counting) handling.

Simplify the init ops now that shared reference counting is working.
This also removes the unused mode_change handling as part of the
simplication.

No runtime change is expected with this simplication.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-08-31 00:48:15 +08:00
Jonas Karlman
0336e97b11 phy: rockchip: usbdp: Fix Generic PHY reference counting
Generic PHY reference counting helps ensure driver ops for init/exit and
power on/off are called at correct state. For this to work the PHY
driver must initialize PHY-id to a persistent value in of_xlate ops.

The Rockchip USBDP PHY driver does not initialize the PHY-id field, this
typically lead to use of unshared reference counting among different
struct phy instances.

Initialize the PHY-id in of_xlate ops to ensure use of shared reference
counting among all struct phy instances.

E.g. on a ROCK 5B following could be observed:

  => usb start
  starting USB...
  [...]
  Bus usb@fc400000: 2 USB Device(s) found
         scanning usb for storage devices... 1 Storage Device(s) found

  => usb reset
  resetting USB...
  [...]
  rockchip_udphy phy@fed90000: cmn ana lcpll lock timeout
  rockchip_udphy phy@fed90000: failed to init usbdp combophy
  rockchip_udphy phy@fed90000: PHY: Failed to init phy@fed90000: -110.
  Can't init PHY1
  Bus usb@fc400000: probe failed, error -110
         scanning usb for storage devices... 0 Storage Device(s) found

With shared reference counting this is fixed:

  => usb reset
  resetting USB...
  [...]
  Bus usb@fc400000: 2 USB Device(s) found
         scanning usb for storage devices... 1 Storage Device(s) found

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-08-31 00:48:15 +08:00
Niu Zhihong
ffa1485c81 board: rockchip: Add Xunlong Orange Pi 5 Ultra
The Orange Pi 5 Ultra is another board in the Orange Pi 5 family.

Orange Pi 5 Ultra uses Rockchip RK3588,
a new generation of octa-core 64-bit ARM processor,
which includes quad-core A76 and quad-core A55.

Features tested on a Orange Pi 5 Ultra 16GB:
- SD-card boot
- eMMC boot

ROCKCHIP_TPL:
https://github.com/rockchip-linux/rkbin/tree/master/bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v1.18.bin

BL31:
https://github.com/rockchip-linux/rkbin/tree/master/bin/rk35/rk3588_bl31_v1.48.elf

Signed-off-by: Niu Zhihong <zhihong@nzhnb.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-08-30 23:35:40 +08:00
Diederik de Haas
b2ebdd592e rockchip: rk3568-nanopi-r5s: Enable ROCKUSB on NanoPi R5S
Enable the needed modules so that ROCKUSB can be used to update the
NanoPi R5S.

Signed-off-by: Diederik de Haas <didi.debian@cknow.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-08-30 23:35:27 +08:00
Andrew Goodbody
97b0f9f8ce mmc: rockchip_sdhci: Do not test unsigned for being less than 0
In rockchip_sdhci_execute_tuning the variable tuning_loop_counter is
tested for being less than 0. Ensure that it is a signed type by
declaring it as s8 instead of char.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-08-30 23:33:32 +08:00
Quentin Schulz
1961bba4bc power: rk8xx: allow to customize RK806 reset mode
The RK806 PMIC has a bitfield for configuring the restart/reset behavior
(which I assume Rockchip calls "function") whenever the PMIC is reset
either programmatically (c.f. DEV_RST in the datasheet) or via PWRCTRL
or RESETB pins.

For RK806, the following values are possible for RST_FUN:

0b00 means "Restart PMU"
0b01 means "Reset all the power off reset registers, forcing
	the state to switch to ACTIVE mode"
0b10 means "Reset all the power off reset registers, forcing
	the state to switch to ACTIVE mode, and simultaneously
	pull down the RESETB PIN for 5mS before releasing"
0b11 means the same as for 0b10 just above.

This adds the appropriate logic in the driver to parse the new
rockchip,reset-mode DT property to pass this information. It just
happens that the values in the binding match the values to write in the
bitfield so no mapping is necessary.

For backward compatibility reasons, if the property is missing we set it
to 0b10 (i.e. BIT(7)) like before this commit was merged instead of
leaving it untouched like in the kernel driver.

Note that this does nothing useful for U-Boot at the moment as the ways
to reset the device (e.g. via `reset` command) doesn't interact with the
RK8xx PMIC and simply does a CPU reset.
Considering the upstream Linux kernel left this register untouched until
(assumed) v6.17[1], this is useful for cases in which the U-Boot
bootloader has this patch (and running with a DT with
rockchip,reset-mode property set) and running an upstream kernel before
(assumed) v6.17, or alternatively later without the property in the
kernel DT.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd.git/commit/?id=87b48d86b77686013f5c2a8866ed299312b671db

Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-08-30 23:28:20 +08:00
Quentin Schulz
82d8327162 arm64: dts: rockchip: force PMIC reset behavior to restart PMU on RK3588 Tiger
The bootloader for RK3588 Tiger currently forces the PMIC reset behavior
(stored in RST_FUN bitfield in register SYS_CFG3 of the PMIC) to 0b1X
which is incorrect for our devices.

It is required to restart the PMU as otherwise the companion
microcontroller cannot detect the PMIC (and by extension the full
product and main SoC) being rebooted which is an issue as that is used
to reset a few things like the PWM beeper and watchdogs.

Let's add the new rockchip,reset-mode property to make sure the PMIC
reset behavior is the expected one.

Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Link: https://lore.kernel.org/r/20250627-rk8xx-rst-fun-v4-5-ce05d041b45f@cherry.de
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

[ upstream commit: e82f642b9821384045915dc30e73df7de8424827 ]

(cherry picked from commit d9c568906be166834f4f977bc7f704176bac5b8a)
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-08-30 23:28:20 +08:00
Quentin Schulz
8df0eba814 arm64: dts: rockchip: force PMIC reset behavior to restart PMU on RK3588 Jaguar
The bootloader for RK3588 Jaguar currently forces the PMIC reset
behavior (stored in RST_FUN bitfield in register SYS_CFG3 of the PMIC)
to 0b1X which is incorrect for our devices.

It is required to restart the PMU as otherwise the companion
microcontroller cannot detect the PMIC (and by extension the full
product and main SoC) being rebooted which is an issue as that is used
to reset a few things like the PWM beeper and watchdogs.

Let's add the new rockchip,reset-mode property to make sure the PMIC
reset behavior is the expected one.

Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Link: https://lore.kernel.org/r/20250627-rk8xx-rst-fun-v4-4-ce05d041b45f@cherry.de
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

[ upstream commit: ee907113430aa02a8202c91bb574c385ecc28aa2 ]

(cherry picked from commit 8bd14566b75f9409de703a0d2f9a0704b71a7ebe)
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-08-30 23:28:20 +08:00
Quentin Schulz
2890838117 arm64: dts: rockchip: add header for RK8XX PMIC constants
To make it easier to read the device tree, let's add constants for the
rockchip,reset-mode property values that are currently only applicable
to RK806 PMIC.

Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
[dt-maintainers did not consider this part of the binding, so we're
 keeping the header in the devicetree directory]
Link: https://lore.kernel.org/r/20250627-rk8xx-rst-fun-v4-3-ce05d041b45f@cherry.de
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

[ upstream commit: 304be20e65ca08fc2e9cb58eb939a0054d8a8b81 ]

(cherry picked from commit 0e417bfcbc385c127c7f5ea01df6289aed8325c2)
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-08-30 23:28:20 +08:00
Quentin Schulz
4e3d2972d1 dt-bindings: mfd: rk806: Allow to customize PMIC reset mode
The RK806 PMIC allows to configure its reset/restart behavior whenever
the PMIC is reset either programmatically or via some external pins
(e.g. PWRCTRL or RESETB).

The following modes exist:
 - 0; restart PMU,
 - 1; reset all power off reset registers and force state to switch to
   ACTIVE mode,
 - 2; same as mode 1 and also pull RESETB pin down for 5ms,

For example, some hardware may require a full restart (mode 0) in order
to function properly as regulators are shortly interrupted in this mode.

This is the case for RK3588 Jaguar and RK3588 Tiger which have a
companion microcontroller running on an independent power supply and
monitoring the PMIC power rail to know the state of the main system.
When it detects a restart, it resets its own IPs exposed to the main
system as if to simulate its own reset. Failing to perform this fake
reset of the microcontroller may break things (e.g. watchdog not
automatically disabled, buzzer still running until manually disabled,
leftover configuration from previous main system state, etc...).

Some other systems may be depending on the power rails to not be
interrupted even for a small amount of time[1].

This allows to specify how the PMIC should perform on the hardware level
and may differ between hardware designs, so a DT property seems
warranted. I unfortunately do not see how this could be made generic
enough to make it a non-vendor property.

[1] https://lore.kernel.org/linux-rockchip/2577051.irdbgypaU6@workhorse/

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: "Rob Herring (Arm)" <robh@kernel.org>
Link: https://lore.kernel.org/r/20250627-rk8xx-rst-fun-v4-1-ce05d041b45f@cherry.de
Signed-off-by: Lee Jones <lee@kernel.org>

[ upstream commit: 404005d1083997daec7236620b9ba14bccdce449 ]

(cherry picked from commit 8ee72356e9844265334fd344bc05139d1f615c4d)
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-08-30 23:28:20 +08:00
Jonas Karlman
50c8b58eea rockchip: rk3528-radxa-e20c: Enable USB gadget Kconfig options
Radxa E20C has a USB OTG Type-C port for Debug and Data.

Add required Kconfig options to use USB gadget features once pending
USB nodes finally lands in dts/upstream by a future sync.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-08-30 23:26:08 +08:00
Jianwei Zheng
dfc6ec058e phy: rockchip: naneng-combphy: Add support for RK3528
Add support for the PCIe/USB3 combo PHY used in the RK3528 SoC.

Config values are taken from vendor U-Boot linux-6.1-stan-rkr5 tag.

Signed-off-by: Jianwei Zheng <jianwei.zheng@rock-chips.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-08-30 23:26:08 +08:00
Jonas Karlman
0f310a0895 usb: dwc3-generic: Use combined glue and ctrl node for RK3528
Like Rockchip RK3328, RK3568 and RK3588, the RK3528 also have a single
node to represent the glue and ctrl for USB 3.0.

Use rk_ops as driver data to select correct ctrl node for RK3528 DWC3.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-08-30 23:26:08 +08:00
Jonas Karlman
281c66f39b rockchip: clk: clk_rk3528: Add dummy CLK_REF_PCIE_INNER_PHY support
Add dummy support for the CLK_REF_PCIE_INNER_PHY clock to allow probe of
the phy-rockchip-naneng-combphy driver on RK3528.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-08-30 23:26:08 +08:00
Jonas Karlman
58d39bbd77 rockchip: rk3528: Disable USB3OTG U3 port early
The RK3528 SoC comes with USB OTG support using a DWC3 controller with
a USB2 PHY and a USB3 PHY (COMBPHY).

Some board designs may not use the COMBPHY for USB3 purpose. For these
board to use USB OTG the input clock source must change to use UTMI clk
instead of PIPE clk.

Change to always disable the USB3OTG U3 port early and leave it to the
COMBPHY driver to re-enable the U3 port when a usb3-phy is described in
the board device tree.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-08-30 23:26:08 +08:00
Jonas Karlman
95ae8b040b arm: dts: rockchip: Set init-microvolt for pwm-regulators on Radxa E20C
Radxa E20C has two main pwm-regulators, vdd_arm and vdd_logic.

Add init-microvolt props to ensure the regulators are initialized at
the recommended power-on sequence voltage instead of at max voltage.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-08-30 23:26:08 +08:00
Jonas Karlman
2e3b37d589 arm: dts: rockchip: Use sdmmc node from dts/upstream on RK3528
Drop the sdmmc node from soc u-boot.dtsi and instead use the sdmmc node
from rk3528.dtsi with v6.16-dts now merged to dts/upstream.

This cleanup has no intended functional change.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-08-30 23:26:08 +08:00
Jonas Karlman
9b3b5e03b8 rockchip: rk3528-generic: Fix boot after dts/upstream v6.16-dts merge
The rk3528-generic target can no longer boot after v6.16-dts was merged
into dts/upstream, and instead end up in a boot loop:

  No serial driver found
  resetting ...

After Linux commit 34d2730fbbdd ("arm64: dts: rockchip: move rk3528
i2c+uart aliases to board files") there is no longer an alias for
serial0 defined for the U-Boot only rk3528-generic device tree.

Add a board specific aliases node that include the missing serial0 alias
to resolve the boot issue and ensure that stdout-path = "serial0:..."
can be resolved by U-Boot.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-08-30 23:26:08 +08:00
Marius Dinu
6048bbbb92 rk3288: add fdtoverlay_addr_r to default env
rk3288 is missing fdtoverlay_addr_r.
The new addresses match those used by rk3308.
Tested on Asus TinkerBoard S.

Signed-off-by: Marius Dinu <m95d+git@psihoexpert.ro>
Cc: Simon Glass <sjg@chromium.org>
Cc: Philipp Tomsich <philipp.tomsich@vrull.eu>
Cc: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-08-30 23:04:23 +08:00
Jakob Unterwurzacher
de0c91e7a7 board: rockchip: unblock CAN bus in spl_board_init on Jaguar
GPIO0_B7 is routed to TXI of the on-board CAN transceiver. The
line has a pull-down per SoC default.

This means the CAN transceiver transmits a dominant zero
and blocks the CAN bus until Linux boots and reconfigures the pin.

Let's switch to pull-up as soon as we can (i.e. in SPL).
This cuts down the "bus is blocked" time from 10 seconds to < 1 second.

Of course, to this needs CONFIG_SPL_BOARD_INIT, so enable it
the Jaguar defconfig.

Signed-off-by: Jakob Unterwurzacher <jakob.unterwurzacher@cherry.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-08-30 23:03:54 +08:00
Quentin Schulz
a979380123 rockchip: puma-rk3399: enable "env erase" command
Erasing the environment to start from scratch is actually very useful
and "env erase" is the proper way to do it instead of using "env
default -a && env save", so let's enable support for it.

Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-08-30 23:03:18 +08:00
Quentin Schulz
755653c06c rockchip: ringneck-px30: enable "env erase" command
Erasing the environment to start from scratch is actually very useful
and "env erase" is the proper way to do it instead of using "env
default -a && env save", so let's enable support for it.

Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-08-30 23:03:18 +08:00
Quentin Schulz
3c8b94ac91 rockchip: jaguar-rk3588: enable "env erase" command
Erasing the environment to start from scratch is actually very useful
and "env erase" is the proper way to do it instead of using "env
default -a && env save", so let's enable support for it.

Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-08-30 23:03:18 +08:00
Quentin Schulz
009bc00bf9 rockchip: tiger-rk3588: enable "env erase" command
Erasing the environment to start from scratch is actually very useful
and "env erase" is the proper way to do it instead of using "env
default -a && env save", so let's enable support for it.

Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-08-30 23:03:18 +08:00
Jonas Karlman
ae2faeae67 board: rockchip: Add ArmSoM Sige5
ArmSoM-Sige5 adopts the second-generation 8nm high-performance AIOT
platform Rockchip RK3576, with a 6 TOPS computing power NPU and support
for up to 16GB of large memory. It supports 4K video encoding and
decoding, offers rich interfaces including dual gigabit Ethernet ports,
WiFi 6 & BT5, and various video outputs.

Features tested on a ArmSoM Sige5 v1.1:
- SD-card boot
- eMMC boot
- Ethernet
- PCIe NVMe

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-08-30 23:01:45 +08:00
Jon Lin
cca7e79c7a phy: rockchip: naneng-combphy: Add support for RK3576
Add support for the PCIe/USB3/SATA combo PHYs used in the RK3576 SoC.

Config values are taken from vendor U-Boot linux-6.1-stan-rkr5 tag.

Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-08-30 23:01:44 +08:00
Jonas Karlman
2a6039a209 rockchip: clk: clk_rk3576: Add dummy CLK_REF_PCIEx_PHY support
Add dummy support for the CLK_REF_PCIEx_PHY clocks to allow probe of the
phy-rockchip-naneng-combphy driver on RK3576.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-08-30 23:01:44 +08:00
Frank Wang
0d966d3932 phy: rockchip: usbdp: Add support for RK3576
Add support for the USB3.0+DP PHY used in the RK3576 SoC.

Config values are taken from vendor U-Boot linux-6.1-stan-rkr5 tag.

Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-08-30 23:01:29 +08:00
Frank Wang
b518886f6d phy: rockchip-inno-usb2: Add support for RK3576
Add support for the USB2.0 PHYs used in the RK3576 SoC.

Config values are taken from vendor U-Boot linux-6.1-stan-rkr5 tag.

Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-08-30 23:01:29 +08:00
Jonas Karlman
2d87afba58 usb: dwc3-generic: Use combined glue and ctrl node for RK3576
Like Rockchip RK3328, RK3568 and RK3588, the RK3576 also have a single
node to represent the glue and ctrl for USB 3.0.

Use rk_ops as driver data to select correct ctrl node for RK3576 DWC3.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-08-30 23:01:29 +08:00
Jonas Karlman
bdcda6be27 arm: dts: rockchip: Include OTP in U-Boot pre-reloc phase for RK3576
Update rk3576-u-boot.dtsi to include OTP in U-Boot pre-reloc phase for
checkboard() to be able to read information about the running SoC model
and variant from OTP and print it during boot:

  U-Boot 2025.04 (Apr 22 2025 - 20:43:17 +0000)

  Model: Generic RK3576
  SoC:   RK3576
  DRAM:  8 GiB

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-08-30 23:01:28 +08:00
Jonas Karlman
a72e8feaca rockchip: rk3576: Implement checkboard() to print SoC variant
Implement checkboard() to print current SoC model used by a board when
U-Boot proper is running.

  U-Boot 2025.04 (Apr 22 2025 - 20:43:17 +0000)

  Model: Generic RK3576
  SoC:   RK3576
  DRAM:  8 GiB

Information about the SoC model and variant is read from OTP.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-08-30 23:01:28 +08:00
Jonas Karlman
108d9f11ea board: rockchip: Add minimal generic RK3576 board
Add a minimal generic RK3576 board that only have eMMC, SDMMC and USB
OTG enabled. This defconfig can be used to boot from eMMC or SD-card on
most RK3576 boards that follow reference board design.

eMMC and SD-card boot tested on:
- ArmSoM CM5
- ArmSoM Sige5
- FriendlyElec NanoPi M5
- Luckfox Omni3576
- Toybrick TB-RK3576D

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-08-30 23:01:28 +08:00
Jonas Karlman
dd2c7df419 rockchip: Add default USB_GADGET_PRODUCT_NUM for RK3576
Use 0x350e as the default USB Product ID for Rockchip RK3576, same PID
being used by the BootROM when the device is in MASKROM mode.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-08-30 23:01:28 +08:00
Jonas Karlman
d079cdbc53 rng: rockchip_rng: Add compatible for RK3576
The RK3576 SoC contains a RKRNG block that can be used to generate
random numbers using the rockchip_rng driver.

Add compatible for RK3576 to support random numbers:

  => rng list
  RNG #0 - rng@2a410000

  => rng
  00000000: 36 dd ab 98 ec fb fe d1 cf 36 b3 e1 9b 3d 00 90  6........6...=..
  00000010: f5 84 de 75 6b 27 48 9e 13 62 12 6c 50 ca 47 1a  ...uk'H..b.lP.G.
  00000020: b3 4d fc 43 c5 b5 2d be 07 27 03 26 bb 69 61 2a  .M.C..-..'.&.ia*
  00000030: 6f 70 01 83 4e ce 91 7a 5a 6c 7c 00 43 87 3e c5  op..N..zZl|.C.>.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-08-30 23:01:28 +08:00
Tom Rini
9bd3fc8cd9 usb: gadget: rockchip: Fix spacing around the Kconfig option
This Kconfig option used spaces and not tabs for indentation. Switch to
tabs.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-08-30 22:41:16 +08:00
Tom Rini
571244f574 usb: gadget: rockchip: Add missing dependency
The rockchip usb gadget driver cannot build without platform specific
headers being available. Express that requirement in Kconfig as well.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-08-30 22:41:16 +08:00
Da Xue
578e168387 arm64: dts: rockchip: roc-3328-cc: use 1600 ddr4 timing
Swap the ROC-3328-CC from DDR4 666 to 1600 timing to boost performance.

Signed-off-by: Da Xue <da@libre.computer>
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-08-30 22:34:00 +08:00
Da Xue
d48f063a53 ram: rk3328: add ddr4-1600 sdram timing
Add DDR4 1600MHz SDRAM timing data from LibreComputer u-boot sources
for the ROC-3328-CC board.

Signed-off-by: Da Xue <da@libre.computer>
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-08-30 22:34:00 +08:00
Chris Morgan
9d98a6b980 rockchip: Add support for GameForce Ace
The GameForce Ace is an RK3588S based handheld gaming device.

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-08-30 22:33:51 +08:00
Quentin Schulz
2390eb8b61 rockchip: px30/rk3326: Implement checkboard() to print SoC variant
This implements checkboard() to print the current SoC model used by a
board, e.g. one of:

SoC:   PX30
SoC:   PX30S
SoC:   PX30K
SoC:   RK3326
SoC:   RK3326S

when U-Boot proper is running.

The information is read from the OTP and also the DDR_GRF. There's no
public information as far as I know about the layout and stored
information on OTP but this was provided by Rockchip themselves through
their support channel.

The OTP stores the information of whether the SoC is PX30K or something
else. To differentiate between PX30/RK3326 and PX30S/RK3326S, one needs
to read some undocumented bitfield in a DDR_GRF register as done in
vendor kernel,
c.f. https://github.com/armbian/linux-rockchip/blob/rk-6.1-rkr5.1/drivers/soc/rockchip/rockchip-cpuinfo.c#L118-L133.

I do not own a PX30S, nor RK3326/RK3326S so cannot test it works
properly.

Also add the OTP node to the pre-relocation phase of U-Boot proper so
that the SoC variant can be printed when DISPLAY_BOARDINFO is enabled.
This is not required if DISPLAY_BOARDINFO_LATE is enabled because this
happens after relocation. If both are enabled, then the SoC variant will
be printed twice in the boot log, e.g.:

U-Boot 2025.07-rc3-00014-g7cb731574ae6-dirty (May 28 2025 - 13:52:47 +0200)

Model: Theobroma Systems PX30-uQ7 SoM on Haikou devkit
SoC:   PX30  <---- due to DISPLAY_BOARDINFO
DRAM:  2 GiB
PMIC:  RK809 (on=0x40, off=0x00)
Core:  293 devices, 27 uclasses, devicetree: separate
MMC:   mmc@ff370000: 1, mmc@ff390000: 0
Loading Environment from MMC... Reading from MMC(1)... OK

In:    serial@ff030000
Out:   serial@ff030000
Err:   serial@ff030000
Model: Theobroma Systems PX30-uQ7 SoM on Haikou devkit
SoC:   PX30  <----- due to DISPLAY_BOARDINFO_LATE
Net:   eth0: ethernet@ff360000

Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-08-30 22:25:23 +08:00
Alex Shumsky
1848a50437 rockchip: rockchip-inno-usb2: Fix Synchronous Abort on usb start
Fix NULL pointer dereference that happen when rockchip-inno-usb2 clock
enabled before device probe. This early clock enable call happen in process
of parent clock activation added in ac30d90f33.

Fixes: 229218373c ("phy: rockchip-inno-usb2: Add support for clkout_ctl_phy").
Fixes: ac30d90f33 ("clk: Ensure the parent clocks are enabled while reparenting")
Co-authored-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Alex Shumsky <alexthreed@gmail.com>
Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-08-30 22:23:35 +08:00
Tom Rini
e4c8b32d03 Merge branch 'master' of git://source.denx.de/u-boot-usb
- Fix a use after free error in cdns3 gadget support in some cases.
2025-08-29 14:58:45 -06:00
Andrew Goodbody
ae2cd1b52d usb: cdns3: Do not access memory after free
The call to cdns3_gadget_ep_free_request will free priv_req so do the
call to list_del_init which accesses the memory pointed to by priv_req
before the free.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
2025-08-29 13:12:41 +02:00
Tom Rini
3dc5e9a010 Merge tag 'u-boot-stm32-20250825' of https://source.denx.de/u-boot/custodians/u-boot-stm
CI: https://source.denx.de/u-boot/custodians/u-boot-stm/-/pipelines/27466

- Enable OF_UPSTREAM_BUILD_VENDOR for stm32mp25_defconfig
- Fix to avoid inifite loop in stm32_sdmmc2 driver
- Populate oobavail field of nand_ecclayout in stm32_fmc2_nand driver
2025-08-26 08:33:10 -06:00
Tom Rini
349cf24859 Merge tag 'u-boot-at91-fixes-2025.10-a' of https://source.denx.de/u-boot/custodians/u-boot-at91
First set of u-boot-at91 fixes for the 2025.10 cycle:

This set includes smatch fixes for clocks and mmc and one QSPI fix.
2025-08-26 08:30:21 -06:00
Tom Rini
dca578a9c9 Prepare v2025.10-rc3
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-08-25 13:06:38 -06:00
Anshul Dalal
bd5036ddf2 remoteproc: k3: update compatible for am654 syscon
The existing compatible name for U-Boot's k3 system controller driver
i.e "ti,am625-system-controller" has been added to linux[1] device-tree.
This compatible in kernel is meant for configuring the Control Module
registers (CTRL_MMR0).

However in U-Boot, the matching driver was being used to load the system
firmware on the secure M-cores by the R5 SPL and therefore must be
updated to a different compatible to avoid conflicts.

Therefore, this patch renames all references of the compatible to
"ti,am654-tisci-rproc-r5". The "-r5" is appended so as to avoid any
future conflicts since r5 specific compatibles should only be useful for
U-Boot.

[1]: 5959618631fe ("dt-bindings: mfd: ti,j721e-system-controller: Add compatible string for AM654")
     https://lore.kernel.org/r/20250421214620.3770172-2-afd@ti.com

Signed-off-by: Anshul Dalal <anshuld@ti.com>
2025-08-25 12:46:33 -06:00
Wadim Egorov
03baafe062 board: phytec: phycore_am6xx: Add rauc to bootmeths
Add rauc to bootmeths variable if BOOTMETH_RAUC is enabled.
This is setting a proper default for RAUC enabled systems.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Reviewed-by: Martin Schwan <m.schwan@phytec.de>
2025-08-25 10:15:16 -06:00
Martin Schwan
997c0c45c1 bootstd: rauc: Do not select BOOTMETH_GLOBAL
Since the bootmeth "rauc" is not a global boot method, do not select the
corresponding BOOTMETH_GLOBAL option.

Signed-off-by: Martin Schwan <m.schwan@phytec.de>
2025-08-25 10:15:12 -06:00
Tom Rini
4a7ae028f8 Merge tag 'xilinx-for-v2025.10-rc3' of https://source.denx.de/u-boot/custodians/u-boot-microblaze
AMD/Xilinx/FPGA changes for v2025.10-rc3

Fix smatch issues in zynqmp ipi and pinctrl drivers

zynqmp:
- Add missing zu1cg device
- Add missing ethernet alias for kr260-revB
- Define empty BOOTENV_DEV_SHARED_XSPI macro

fpga:
- Address reported coverity issues

net:
- axi_emac: Fix timeout test

versal2:
- Define usb_pgood_delay for fix device detection
2025-08-25 10:06:03 -06:00
Patrice Chotard
198c48f265 configs: stm32mp25: Enable OF_UPSTREAM_BUILD_VENDOR
Initially, only one STM32MP25 based board was available, the
stm32mp257f-ev1 board which was set by default in stm32mp25_defconfig.

Since commit 79f3e77133 ("Subtree merge tag 'v6.16-dts' of dts repo [1] into dts/upstream")
we inherited of a second MP25 based board which is the stm32mp257f-dk board.

Enable OF_UPSTREAM_BUILD_VENDOR and set OF_UPSTREAM_VENDOR to allow all
STMicroelectronics DT compilation.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2025-08-25 16:54:53 +02:00
Christophe Kerello
1067d2060f mmc: stm32_sdmmc2: avoid infinite while loop
Avoid unlimited while loop by adding a timeout. The timeout is
calculated based on a minimal throughput of 256 KB/s.
The timeout is set at least to 2 seconds.

Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2025-08-25 16:47:39 +02:00
Christophe Kerello
4c28c4d9a3 mtd: rawnand: stm32_fmc2: set available OOB bytes per page
File system such as YAFFS2 need to know the number of available
OOB bytes per page to be able to choose if they should locate their
metadata in the data area or in the spare area.

Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2025-08-25 16:47:04 +02:00
Venkatesh Yadav Abbarapu
37aee09d83 configs: versal2: Add usb_pgood_delay for versal2 boards
Add usb_pgood_delay to ensure proper detection of USB devices.
Increase the USB power good delay for versal2 specific boards,
as certain USB sticks may not be detected without it.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20250818045304.4058177-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2025-08-25 16:20:48 +02:00
Andrew Goodbody
88e3524393 net: axi_emac: Fix timeout test
The timeout test in axi_dma_init is not correct due to the
post-decrement used on the timeout variable which will mean timeout is
not 0 if the timeout occurs. Make the timeout variable an int instead of
a u32 and then test for timeout being -1.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Link: https://lore.kernel.org/r/20250806-net_xilinx_axi-v2-1-6311cf59451d@linaro.org
Signed-off-by: Michal Simek <michal.simek@amd.com>
2025-08-25 16:20:48 +02:00
Michal Simek
0109a7de96 arm64: versal2: Define BOOTENV_DEV_SHARED_XSPI when distro is disabled
When DISTRO_DEFAULT is disabled there is missing empty
BOOTENV_DEV_SHARED_XSPI macro defined.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/4c195468c0341ddd2aca98f83cdcbd40117cc9ee.1753885919.git.michal.simek@amd.com
2025-08-25 16:20:48 +02:00
Michal Simek
cb57991250 arm64: zynqmp: Add missing ethernet alias for kr260-revB
Ethernet aliases are used in fdt_fixup_ethernet() to inject
local-mac-address in every boot for OS. Similar change has been done for
other carrier cards by commit c4a7112536 ("arm64: zynqmp: Describe
ethernet controllers via aliases on SOM").

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/87d88dba98f7ed96463964684ee45a506d557226.1753797318.git.michal.simek@amd.com
2025-08-25 16:20:48 +02:00
Michal Simek
34762f6c00 fpga: lattice: Remove unused support
There is no single platform which is using this driver that's why remove it
completely. Some issues regarding this code are also reported by Coverity
(CID 583143, 583144, 583145, 583146).

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/367cd55ab8d9fb262ac23fe748babc6b2b59bee0.1753686468.git.michal.simek@amd.com
2025-08-25 16:20:48 +02:00
Michal Simek
0870281a41 fpga: Remove ancient ACEX1K support
Coverity (CID 583149) reports issue on code which is not enabled by any
real platform that's why remove it completely.

Acked-by: Alexander Dahl <ada@thorsis.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20fe425910b6266a2bf0555bda67f60c1dd3aa61.1753686468.git.michal.simek@amd.com
2025-08-25 16:20:48 +02:00
Michal Simek
7fc04c9a82 fpga: xilinx: Check valid desc structure
FPGA validation can fail and return value needs to be checked.

Addresses-Coverity-ID: CID 583150: Null pointer dereferences  (NULL_RETURNS)
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/876b6f8dbc99ca305460183dbd18635a35ccc989.1753686468.git.michal.simek@amd.com
2025-08-25 16:20:48 +02:00
Alexander Dahl
818f6002e1 fpga: cyclon2: Remove message never printed
else branch is never reached.  Print "Done." anyways to keep behaviour.

Addresses-Coverity-ID: 583148
Link: https://lore.kernel.org/u-boot/20250725132645.GA1807455@bill-the-cat/
Fixes: f0ff4692ff ("Add FPGA Altera Cyclone 2 support Patch by Heiko Schocher, 15 Aug 2006")
Signed-off-by: Alexander Dahl <ada@thorsis.com>
Link: https://lore.kernel.org/r/20250804090816.42603-1-ada@thorsis.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2025-08-25 16:20:47 +02:00
Frank Böwingloh
3b765ae050 soc: xilinx: zynqmp: Fix zu1cg device detection
Currently u-boot displayed a zu1cg soc as "Chip:  zu1eg".
A value of 0468_8093h in the IDCODE (CSU) Register defines a ZU1 soc
not only for the EG family but also for the CG family as described
in the Xilinx Zynq UltraScale+ UG1085 documentation in Table 1-2.

Signed-off-by: Frank Böwingloh <f.boewingloh@beckhoff.com>
Cc: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20250808123134.636-1-f.boewingloh@beckhoff.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2025-08-25 16:20:47 +02:00
Andrew Goodbody
6ce599f513 pinctrl: zynqmp: Avoid using uninitialised variable
In zynqmp_pinconf_set if param is PIN_CFG_IOSTANDARD or
PIN_CONFIG_POWER_SOURCE and zynqmp_pm_pinctrl_get_config returns an
error then value will not be assigned to when its value is tested to be
not equal to arg. Add code to only test value not equal to arg if ret is
false.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Link: https://lore.kernel.org/r/20250807-pinctrl_misc-v1-4-eeb564a1b032@linaro.org
Signed-off-by: Michal Simek <michal.simek@amd.com>
2025-08-25 16:20:47 +02:00
Andrew Goodbody
7aac843944 pinctrl: zynqmp: Ensure ret is initialised
In zynqmp_pinctrl_prepare_func_groups if called with func->ngroups == 0
then ret will not be assigned to before its value is returned on exit.
Initialise ret to ensure it is always valid.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Link: https://lore.kernel.org/r/20250807-pinctrl_misc-v1-3-eeb564a1b032@linaro.org
Signed-off-by: Michal Simek <michal.simek@amd.com>
2025-08-25 16:20:47 +02:00
Andrew Goodbody
0d1c4fd514 mailbox: zynqmp: Fix off by 1 errors
Use resource_size to correctly calculate the size to pass to
devm_ioremap and avoid the off by 1 errors previously present.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Link: https://lore.kernel.org/r/20250728-zynqmp-ipi-v1-1-b2bd144a9521@linaro.org
Signed-off-by: Michal Simek <michal.simek@amd.com>
2025-08-25 16:20:47 +02:00
Tom Rini
7d879baa6f Merge branch 'u-boot-nand-23082025' of https://source.denx.de/u-boot/custodians/u-boot-nand-flash
CI: https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/pipelines/27449

This series address issues found by Andrew Goodbody and David Regan. Add
a new benchmark tool from Miguel and small feature
2025-08-24 08:01:29 -06:00
Tom Rini
cb0b67fa49 Merge branch 'master' of git://source.denx.de/u-boot-usb
- A DWC2 fix, i.MX95 USB3 PHY support and i.MX95 OTG support
2025-08-23 13:53:34 -06:00
Tom Rini
c635e3952c Merge tag 'u-boot-imx-master-20250823' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/27447

- Fix the environment location when booting from USB on i.MX93.
- Fix env location when booting from USB on phycore-imx93.
- Fix conflict early SPL malloc address on imx93 boards.
2025-08-23 13:52:54 -06:00
Patrick Delaunay
332714b905 usb: dwc2: fix reset logic in dwc2_core_reset
Use GUSBCFG_FORCEHOSTMODE to detected the HOST forced mode as it is done
in the Linux driver drivers/usb/dwc2/core.c:dwc2_core_reset().

The host polling must be executed only if the current mode is host,
either due to the force HOST mode (which persists after core reset)
or the connector id pin.

The GUSBCFG_FORCEDEVMODE bits is used to force the device mode (for
example used on STM32MP1x platform) and when it is activated the DWC2 reset
failed with the trace:
"dwc2_core_reset: Waiting for GINTSTS_CURMODE_HOST timeout"

Fixes: c5d685b899 ("usb: dwc2: Unify flush and reset logic with v4.20a support")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Junhui Liu <junhui.liu@pigmoral.tech>
Tested-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Marek Vasut <marek.vasut@mailbox.org>
2025-08-23 18:20:01 +02:00
Tim Harvey
445aad45f4 usb: ehci-mx6: Add i.MX95 OTG support
When the usb node is defined dr_mode="otg" ehci_usb_phy_mode() is called
to determine the mode from status registers.

The IMX95RM does not currently define the USBNC STATUS register but it is
assumed to be an omission as the first three registers are defined.
It has been expirimentally verified that the USBNC_PHY_STATUS register
at offset 0x23C bit4 (USBNC_PHYSTATUS_ID_DIG) reads 0 when USB_ID is GND
and 1 when floating.

Use is_imx9() as this driver works for i.MX91, i.MX93 and i.MX95 and all
of these determine the role based on the USBNC_PHY_STATUS register.

Fixes: 801b5fafd3 "(usb: ehci-mx6: Add i.MX95 support")
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Alice Guo <alice.guo@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2025-08-23 18:17:59 +02:00
Tim Harvey
edbcf8e359 phy: phy-imx8mq-usb: Add support for i.MX95 USB3 PHY
Add initial support for i.MX95 USB.30 PHY, which is similar to
the i.MX8MQ and i.MX8MP USB PHY.

The i.MX95 USB3 PHY has a Type-C Assist block (TCA) consisting of two
functional blocks (XBar assist and VBus assist) and is documented
in the i.MX95 RM Chapter 163.3.8 Type-C assist (TCA) block.

Instead of relying on an external MUX for Type-C plug orientation the
XBar can handle the flip internally.

Add initial support for i.MX95 by:
 - allowing the driver to be enabled i.MX95
 - resetting the XBar
 - configuring the TCA in System Configuration mode (which was determined
   to be necessary to enable the PHY in device-mode)

Follow-on support will need to be added to steer the XBar based on
either board design (if only one pair is brought out) or if used with a
Type-C controller.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Tested-by: Alice Guo <alice.guo@nxp.com>
2025-08-23 18:17:48 +02:00
Andrew Goodbody
6b156c62ce mtd: nand: Do not dereference before NULL check
In nanddev_init mtd and memorg are assigned values that dereference nand
but this happens before a NULL check for nand. Move the assignments
after the NULL check.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2025-08-23 16:37:26 +02:00
Miquel Raynal
d246e70cf8 cmd: mtd: Enable speed benchmarking
Linux features a flash_speed speed test from the mtd-utils suite, U-Boot
does not. Benchmarks are useful for speed improvement developments as
well as troubleshooting or regression testing sometimes.

Enable a benchmark option to enable this feature.

Example of output on a Nuvoton platform:

MA35D1> mtd read nor0 0x81000000 0 0x10000
Reading 65536 byte(s) at offset 0x00000000
MA35D1> mtd read.benchmark nor0 0x81000000 0 0x10000
Reading 65536 byte(s) at offset 0x00000000
Read speed: 3752kiB/s

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2025-08-23 16:37:22 +02:00
david regan
bb5d3a7a1c cmd: nand: nand dump with ecc option
option to show nand dump data ecc corrected as opposed to just raw

Signed-off-by: david regan <dregan@broadcom.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2025-08-23 16:37:20 +02:00
david regan
b5ce63e135 cmd: nand: nand dump display update
show characters with nand dump similar to md
along with offset into NAND

Signed-off-by: david regan <dregan@broadcom.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2025-08-23 16:37:17 +02:00
david regan
7ec4e91b2f cmd: nand: more descriptive help info
nand read/write raw change 'count' to 'pages' since count is ambiguous

Signed-off-by: david regan <dregan@broadcom.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2025-08-23 16:37:14 +02:00
david regan
590c28b378 cmd: nand: bug fix MTD_OOB_AUTO to MTD_OPS_AUTO_OOB
bug fix MTD_OOB_AUTO to MTD_OPS_AUTO_OOB since MTD_OOB_AUTO does not exist

Fixes: dfe64e2c89 ("mtd: resync with Linux-3.7.1")
Signed-off-by: david regan <dregan@broadcom.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2025-08-23 16:37:11 +02:00
Dinesh Maniyam
5d54230223 mtd: nand: cadence: Fix device assignment to avoid warm reset issue
The driver currently does:
    mtd->dev->parent = cadence->dev;

This works in Linux because `struct mtd_info` embeds a `struct device`,
so `mtd->dev` is always valid and its `.parent` can be set.

In U-Boot, however, `mtd->dev` is only a pointer to a `struct udevice`.
Dereferencing it before assignment is invalid, which breaks the device
hierarchy. As a result, consumers relying on `mtd->dev` (e.g. partition
parser, reset and re-init paths) operate on a dangling pointer. This
leads to failures during warm reset when the NAND device is accessed
again.

Fix by assigning the device pointer directly:
    mtd->dev = cadence->dev;

This matches U-Boot’s device model, preserves a valid hierarchy, and
resolves the warm reset issue on Cadence NAND.

Fixes: ebc41cad ("drivers: mtd: nand: Add driver for Cadence Nand")
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@altera.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2025-08-23 16:37:05 +02:00
Ye Li
cb5f3e4f52 imx: imx93_{evk, frdm, qsb}: Fix conflict SPL early malloc address
Because the early malloc pool size is set to 0x18000, so using this
start address may cause conflict with ATF, then corrupt the heap data.
So we delete the definition to use the default early malloc pool from
CONFIG_SPL_STACK to avoid any conflict

Signed-off-by: Ye Li <ye.li@nxp.com>

Cherry picked from nxp-imx/uboot-imx commit
1ba675df122627a19debe1d807877052705372c6

Jérémie Dautheribes: applied the same patch to the frdm and qsb
imx93-based boards
Signed-off-by: Jérémie Dautheribes <jeremie.dautheribes@bootlin.com>
2025-08-23 08:21:48 -03:00
Primoz Fiser
a7528da151 board: phytec: phycore-imx93: Fix EEPROM bus mismatch in SPL
Fix PHYTEC EEPROM bus mismatch between SPL and U-Boot proper by enabling
CONFIG_SPL_DM_SEQ_ALIAS=y on phyCORE-i.MX93 boards. This way, both the
SPL and U-Boot proper will respect the device-tree aliases for I2C devs
and use the same I2C bus number for phytec_eeprom_data_setup() function
calls. This makes code less confusing and more robust.

Fixes an issue apparent since commit 79f3e77133 ("Subtree merge tag
'v6.16-dts' of dts repo [1] into dts/upstream") where SPL would spew the
following error:

  phytec_eeprom_read: i2c EEPROM not found: -110.
  phytec_eeprom_data_setup: EEPROM data init failed

While later in U-Boot proper, EEPROM would be successfully read out.
This happens because Linux device-tree for phyBOARD-Segin-i.MX93 since
aforementioned commit enables I2C bus 2 (lpi2c2 is used for audio codec
and RTC) which breaks SPL I2C bus number ordering and I2C EEPROM bus is
shifted by +1. Now, lets prevent this from happening again by utilizing
device-tree aliases also in the SPL.

Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
2025-08-23 08:21:25 -03:00
João Paulo Gonçalves
a20dbbb071 arm: imx: imx9: soc: Fix env location when booting from USB
On i.MX9 platforms, when booting from USB, the U-Boot environment is
always assumed to be in RAM. However, this causes the boot to hang when
`CONFIG_ENV_IS_NOWHERE` is not enabled. The boot also hangs even if the
environment is present in another storage media (for example, eMMC). Fix
the issue by correctly handling the U-Boot environment's location when
booting from USB. Also for i.MX95, set the environment location based on
the ENV config and not solely based on the boot device type.

Suggested-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: João Paulo Gonçalves <joao.goncalves@toradex.com>
2025-08-23 08:20:52 -03:00
Tom Rini
94e690c44a Merge patch series "bootstd: rauc: Fix segfault when scanning device with unsupported layout"
Martin Schwan <m.schwan@phytec.de> says:

This series fixes a segfault, that would occur at the end of scanning a
device, which does not contain the required partition layout scheme for
a RAUC system.

With this series, a "bootflow scan" should now correctly scan the
specified devices with boot method "rauc" without crashing on invalid
partition schemes.

Link: https://lore.kernel.org/r/20250813-wip-bootmeth-rauc-priv-free-v1-0-1ef928169469@phytec.de
2025-08-21 15:05:15 -06:00
Martin Schwan
498e423457 bootstd: rauc: Free private data when booting
The private data struct can be freed when loading the boot script, as we
don't need the slot information anymore at this point.

Signed-off-by: Martin Schwan <m.schwan@phytec.de>
Tested-by: Wadim Egorov <w.egorov@phytec.de>
2025-08-21 15:05:04 -06:00
Martin Schwan
302830499d bootstd: rauc: Move freeing private struct to its own function
Move freeing a distro_rauc_priv struct to a new, separate function for
better reuse.

Signed-off-by: Martin Schwan <m.schwan@phytec.de>
Tested-by: Wadim Egorov <w.egorov@phytec.de>
2025-08-21 15:05:04 -06:00
Martin Schwan
b389967f9a bootstd: rauc: Don't null bootflow->bootmeth_priv
Don't null bootflow->bootmeth_priv, as the private struct is freed later
on by the bootflow.

Signed-off-by: Martin Schwan <m.schwan@phytec.de>
Tested-by: Wadim Egorov <w.egorov@phytec.de>
2025-08-21 15:05:04 -06:00
Martin Schwan
074066790c bootstd: rauc: Fix segfault when cleaning up slots
Fix a segfault when cleaning up the slots from the private struct. This
fault was generated by accessing a member of a null pointer.

Signed-off-by: Martin Schwan <m.schwan@phytec.de>
Tested-by: Wadim Egorov <w.egorov@phytec.de>
2025-08-21 15:05:04 -06:00
Tom Rini
0174b33803 Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sh
- DRAM controller driver off-by-one error fix.
2025-08-21 12:43:10 -06:00
Andrew Goodbody
b34b18a2c9 ram: renesas: dbsc5: Fix off by 1 errors
In dbsc5_read_vref_training the arrays dvw_min_byte0_table and
dvw_min_byte1_table have 128 elements per channel. The variable
vref_stop_index is limited to be a maximum of 128. This means that the
index used to access the arrays must use a test of '< vref_stop_index'
rather than '<= vref_stop_index' in order to prevent out of bounds
accesses to the arrays.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Tested-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-08-20 23:02:55 +02:00
Peter Robinson
a353211288 ARM: tegra210: p3450: fix Jetson Nano SPI flash
The Nano's SPI flash stopped working in U-Boot, as the prior stage loaded
U-Boot, the only thing it was used for was save/loading env vars so update
the DT so it can now initialise it. It also drops enabling the old
TEGRA114_SPI driver, as the flash hangs off the faster TEGRA210_QSPI
interface, nothing on the Nano uses the old interface by default so it's
surplus.

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2025-08-20 16:23:11 +03:00
Peter Robinson
9999821e75 configs: p3450: reduce size of Jetson Nano u-boot.bin
The Jetson Nano contains all it's firmware on a 4Mb SPI flash, the
allocated size in that flash for U-Boot is 753664 bytes so we need to
ensure the u-boot.bin doesn't exceed that else it will fail.

Add a BOARD_SIZE_LIMIT and drop a few large, and somewhat esoteric, options
to bring us back under that limit.

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2025-08-20 16:23:11 +03:00
Jonas Schwöbel
e69e2dc7f5 board: microsoft: add Microsoft Surface 2 support
Surface 2 is a Surface-series Windows RT hybrid tablet computer created by
Microsoft. Surface 2 uses a 1.7 GHz quad-core Nvidia Tegra 4 chipset with
2 GB of RAM, features 10.6 inch FullHD ClearType HD screen with 16:9 aspect
ratio and 32/64 GB of internal memory that can be supplemented with a
microSDXC card giving up to 64 GB of additional storage.

Signed-off-by: Jonas Schwöbel <jonasschwoebel@yahoo.de>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2025-08-20 16:22:49 +03:00
Tom Rini
54fbdd4088 Merge tag 'net-20250818' of https://source.denx.de/u-boot/custodians/u-boot-net
Pull request net-20250818.

This is mostly code cleanup and fixes, mainly for issues reported by the
Smatch tool, plus two small features for NET_LWIP as well as support for
the BCM54612E phy.

net-common:
- Fix a bunch of issues reported by Smatch
- Introduce CONFIG_DNS
- Add support for BCM54612E phy

net-legacy:
- Add missing SPDX-License-Identifier for files originating from LiMon

net-lwip:
- ping: initialize net_try_count to 1
- sntp: remove redundant sys_check_timeouts()
- tftp: resend initial request
- Add Kconfig option to show ICMP unreachable errors
2025-08-18 10:54:44 -06:00
Andrew Goodbody
c4526c390a phy: cadence: torrent: Set an error code for return
In cdns_torrent_phy_probe the test for too many lanes configured does
not set an error code before taking the error path. This could lead to a
silent failure if the calling code does not detect the error. Add the
code to return -EINVAL in this case.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-08-18 15:47:58 +02:00
Andrew Goodbody
783ea37c7b phy: cadence: sierra: Remove variable that is not assigned to
In cdns_sierra_pll_bind_of_clocks the variable 'i' is declared but never
assigned to before its value is used in a dev_err. Replace clk_names[i]
by the name passed to device_bind(), i.e., "pll_mux_clk". With that, the
clk_names[] array is unused and can therefore be removed.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
[jf: update description]
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
2025-08-18 15:47:58 +02:00
Andrew Goodbody
5deb50f749 net: ks8851_mll: Remove unreachable code
In ks8851_mll_detect_chip the if..else code detects the case of (val &
0xfff0) != CIDER_ID and returns if found. So testing for this again will
always fail and the code is unreachable. Just remove the test and code
block.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-08-18 15:47:58 +02:00
Jerome Forissier
90c05f68fc net: lwip: ping: set net_try_count to 1
The legacy network stack sets net_try_count to 1 at the beginning of the
net_loop() function. This is required for net_start_again() to work
properly. Therefore, set the variable accordingly in the do_ping()
function when NET_LWIP=y. This fixes an issue where a ping to an
unreachable destination would run twice on the same network device. For
example with qemu_arm64_lwip_defconfig:

 => dhcp
 DHCP client bound to address 10.0.2.15 (3 ms)
 => ping 10.0.0.1
 Using virtio-net#32 device
 ping failed; host 10.0.0.1 is not alive
 Using virtio-net#32 device
 ping failed; host 10.0.0.1 is not alive
 => QEMU: Terminated

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
2025-08-18 15:47:58 +02:00
Andrew Goodbody
2cb9fef65b net: cortina_ni: Fix typo accessing wrong phy
In ca_phy_probe when checking for an external phy it uses a field from
the internal phy due to what is assumed to be a copy/paste typo. Make
the obvious fix to use the field from the external phy.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-08-18 15:47:58 +02:00
Jerome Forissier
8f80e30579 lwip: sntp: remove redundant sys_check_timeouts()
Now that sys_check_timeouts() is called in net_lwip_rx(), there is no
need to call it from the SNTP receive loop. Remove the redundant call.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
2025-08-18 15:47:58 +02:00
Jerome Forissier
46fc565599 lwip: tftp: resend initial request
The TFTP implementation does not resend the initial request if there is
no response from the server. Since TFTP is based on UDP, there should be
a mechanism to deal with unreliable transmissions at this point, similar
to what we have for data packets. Therefore, introduce request
retransmission.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
CC: Venkatesh Abbarapu <venkatesh.abbarapu@amd.com>
CC: Michal Simek <michal.simek@amd.com>
CC: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-08-18 15:47:58 +02:00
Jerome Forissier
512be89796 net: introduce CONFIG_DNS
Introduce the DNS Kconfig symbol so that various network commands may
use host names without the dns command (CMD_DNS) being selected.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
CC: E Shattow <e@freeshell.de>
2025-08-18 15:47:58 +02:00
Andrew Goodbody
425f9839f3 net: octeontx2: NULL check before dereference
In rvu_af_init if the code fails to allocate memory for nix_af it will
take the error path with nix_af == NULL which will dereference nix_af.
Add the appropriate NULL check.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-08-18 15:47:57 +02:00
Andrew Goodbody
6bc6fec3b3 net: octeontx2: Restore default value for err
In nix_lf_setup there is a default value assigned to err in case an
error is detected. However this default value will be overwritten in the
for loop so that later code does not return an error code from the
function. Add a new assignment to restore err to the default error code.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-08-18 15:47:57 +02:00
Andrew Goodbody
c6561a467c net: mvpp2: Use field just assigned in error test
In mvpp2_probe the code attempts to get a value for "gop-port-id" and
assigns it to port->gop_id but it then tests port->id for being equal to
-1. That is an impossible test as port->id is a field of type u8 so
cannot be negative. Change the test to port->gop_id.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-08-18 15:47:57 +02:00
Andrew Goodbody
3aa3d37282 net: mvpp2: Cannot test unsigned variable to be negative
In phy_info_parse all uses of the variable phyaddr are as an int so
declaring as u32 is not useful and prevents the test for an error return
from fdtdec_get_int ever detecting an error. Change phyaddr to be an
int.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-08-18 15:47:57 +02:00
Andrew Goodbody
6781b90f89 net: mvpp2: Return -ENOMEM for failed alloc
Instead of returning -1 on a failed alloc, return -ENOMEM.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-08-18 15:47:57 +02:00
Andrew Goodbody
b24c89affd net: mvpp2: Fix impossible test
You cannot test an unsigned char to be >= 256. Instead make the
variables start and end to be ints.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-08-18 15:47:57 +02:00
Andrew Goodbody
34bc71f2db net: mv88e6xxx: Fix logical operator instead of bitwise
In mv88e6xxx_port_enable when attempting to mask out the previous
settings of two bits a logical operator was used instead of a bitwise
operator. Fix this.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-08-18 15:47:57 +02:00
Andrew Goodbody
ff36afe346 net: mediatek: Use correct variable for return
In mtk_eth_of_to_plat, the last error check has the value in
'priv->phy_addr' but returns ret. Correct to return 'priv->phy_addr'
instead.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-08-18 15:47:57 +02:00
Andrew Goodbody
ed3b08874f net: ldpaa_eth: Fix buffer overflow in memset
In ldpaa_eth_open a memset is used to initialise a struct to 0 but the
size passed is that of a different struct. Correct to pass the sizeof
the struct that is being initialised.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-08-18 15:47:57 +02:00
Max Merchel
4800a6a0b3 net: add missing SPDX-License-Identifier for files originating from LiMon
The header of LiMon imported files reference a License file which
does not exist in U-Boot. Some files were forgotten when adding the
SPDX-License-Identifier.
The LiMon files were originally licensed under GPLv2 as can be seen in
commit [2ea91039].

Based on this commit, add the correct SPDX license identifier.
While at it drop the reference to the non-existing License file from all
LiMon files and update the SPDX-License-Identifier to SPDX version 3.

Signed-off-by: Max Merchel <Max.Merchel@ew.tq-group.com>
2025-08-18 15:47:57 +02:00
Jerome Forissier
6b914d5596 net: lwip: add Kconfig option to show ICMP unreachable errors
Add Kconfig symbol LWIP_ICMP_SHOW_UNREACH which, when enabled, prints a
message to the console upon reception of ICMP unreachable messages. For
example:

 $ make qemu_arm64_lwip_defconfig
 $ qemu-system-aarch64 -M virt -cpu max -nographic -bios u-boot.bin
 [...]
 => dhcp
 DHCP client bound to address 10.0.2.15 (0 ms)
 => tftp 192.168.0.100:69:Image
 Using virtio-net#32 device
 TFTP from server 192.168.0.100; our IP address is 10.0.2.15
 Filename 'Image'.
 Load address: 0x40200000
 Loading: ICMP destination unreachable (host unreachable) from 192.168.0.16
 Timeout!
 => tftp 192.168.0.16:69:Image
 Using virtio-net#32 device
 TFTP from server 192.168.0.16; our IP address is 10.0.2.15
 Filename 'Image'.
 Load address: 0x40200000
 Loading: ICMP destination unreachable (port unreachable) from 192.168.0.16
 Timeout!
 =>

Submitted upstream as https://github.com/lwip-tcpip/lwip/pull/73.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
2025-08-18 14:08:57 +02:00
Jerome Forissier
fbd79b493d lwip: icmp: allow reporting ICMP destination unreachable
Allow reporting ICMP destination unreachable messages via a user-defined
callback.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
2025-08-18 14:08:57 +02:00
Jim Liu
0cabbe3235 net: phy: broadcom: add support for BCM54612E
It's Broadcom PHY simply described as single-port
RGMII 10/100/1000BASE-T PHY.

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2025-08-18 14:08:57 +02:00
Jim Liu
59ec495f6c net: designware: Fix get_timer value overflow
get_timer returns a ulong value representing system time in ms.
On a 64-bit system, this ulong value is 64 bits long. However,
the driver stores it in a 32-bit unsigned integer, which overflows
after 49 days up time, causing the driver to get an incorrect time.

Replace the unsigned int variable with a ulong type to properly store
the value returned by get_timer.

Signed-off-by: Stanley Chu <yschu@nuvoton.com>
Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2025-08-18 14:08:57 +02:00
Andrew Goodbody
2e9155cb9f phy: marvell: Cannot test unsigned field to be negative
In comphy_cp110_init_serdes_map in comphy_cp110.c there are two fields
in cfg, comphy_lanes_count and comphy_mux_bitcount, which are fetched
from the FDT blob with fdtdec_get_int which returns an int. These two
fields are then tested for being negative. However the fields are
declared as unsigned so those tests must always fail. Change the
declaration of those fields to be int instead of u32 and the code will
work as expected.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Stefan Roese <stefan.roese@mailbox.org>
2025-08-18 14:08:57 +02:00
Andrew Goodbody
a75c8a4b88 phy: marvell: Fix off by 1 limit checks
The limit checks in get_speed_string and get_type_string are off by 1 as
they do not account for the maximum index into an array that can be used
is 1 less than the number of elements in that array. Adjust the limit
checks to allow for this.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Stefan Roese <stefan.roese@mailbox.org>
2025-08-18 14:08:57 +02:00
Andrew Goodbody
4b2d64f388 net: phy: vitesse: Fix incorrect test for timeout
In vsc8514_config there is a while loop for detecting a config failure
using a timeout counter with a post-decrement. In the case of a timeout
this will result in the loop exiting with timeout == -1 so use that as
the test below the loop to detect that the timeout occurred.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
2025-08-18 14:08:57 +02:00
Andrew Goodbody
0ce7fef9e2 net: octeontx: Free allocated memory on error
In octeontx_smi_probe if an error is detected then memory that was
allocated is not freed. Small refactor of the code to use a common
return and free memory. Also return -ENOMEM for an allocation failure.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-08-18 14:08:57 +02:00
Andrew Goodbody
62b4a482b9 net: octeontx: Remove unneeded test
In nicvf_cq_handler there is a test for !cqe_count which will return if
true so it is guaranteed that cqe_count will true after that point. This
makes the later test for cqe_count redundant so it can be removed.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-08-18 14:08:57 +02:00
Andrew Goodbody
45eedb7b80 net: octeontx: Remove unneeded code
In nicvf_rcv_pkt_handler there is no need to initialise err as it is
assigned to immediately after. Also the test for !pkt will return if
true meaning that pkt is guaranteed to be true after that code block and
so no need to test for it and the redundant test can be removed.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-08-18 14:08:57 +02:00
Tom Rini
6dee9a5b74 Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sh
Fixes for newer revision of Retronix R-Car V4H Sparrow Hawk and fixes
for boards which enable POSITION_INDEPENDENT and also set non-zero
CONFIG_TEXT_BASE.
2025-08-17 17:48:14 -06:00
Lad Prabhakar
c797d8bac9 configs: Remove redundant CONFIG_TEXT_BASE assignments for Renesas defconfigs
The Renesas board defconfigs explicitly set CONFIG_TEXT_BASE=0x50000000,
however U-Boot's POSITION_INDEPENDENT=y build default already places text
at 0x0. These hardcoded overrides are therefore unnecessary and will be
pruned automatically in upcoming resyncs.

Remove the CONFIG_TEXT_BASE lines from the following defconfigs:
  - hihope_rzg2_defconfig
  - r8a77970_eagle_defconfig
  - r8a77970_v3msk_defconfig
  - r8a77990_ebisu_defconfig
  - r8a77995_draak_defconfig
  - r8a779a0_falcon_defconfig
  - renesas_rzg2l_smarc_defconfig
  - rz2_beacon_defconfig
  - silinux_ek874_defconfig

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-08-17 14:41:23 +02:00
Marek Vasut
797255d897 arm64: dts: renesas: r8a779g3: Describe generic SPI NOR support on Retronix R-Car V4H Sparrow Hawk board
Retronix R-Car V4H Sparrow Hawk EVTA1 is populated with Spansion S25FS512S,
EVTB1 is populated with Winbond W77Q51NW. Describe the SPI NOR using generic
"jedec,spi-nor" compatible, because both flashes can be auto-detected based
on their built-in IDs.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-08-17 14:41:23 +02:00
Marek Vasut
1df2880e95 arm64: dts: renesas: r8a779g3: Set VDDQ18_25_AVB voltage on Retronix R-Car V4H Sparrow Hawk EVTB1
The Retronix R-Car V4H Sparrow Hawk EVTB1 uses 1V8 IO voltage supply
for VDDQ18_25_AVB power rail. Update the AVB0 pinmux to reflect the
change in IO voltage. Since the VDDQ18_25_AVB power rail is shared,
all four AVB0, AVB1, AVB2, TSN0 PFC/GPIO POC[7..4] registers have to
be configured the same way.

Correct the voltage for EVTA1 boards accordingly by patching the U-Boot
control DT in SPL.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-08-17 14:41:23 +02:00
Marek Vasut
74bc80190c arm64: dts: renesas: r8a779g3: Invert microSD voltage selector on Retronix R-Car V4H Sparrow Hawk EVTB1
Invert the polarity of microSD voltage selector on Retronix R-Car V4H
Sparrow Hawk board. The voltage selector was not populated on prototype
EVTA1 boards, and is implemented slightly different on EVTB1 boards. As
the EVTA1 boards are from a limited run and generally not available,
update the DT to make it compatible with EVTB1 microSD voltage selector.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-08-17 14:41:23 +02:00
Marek Vasut
c818fd0594 arm64: renesas: r8a779g3: Enable xHCI USB on Retronix R-Car V4H Sparrow Hawk board
Enable support for PCIe based xHCI USB 3.0 driver and USB mass
storage support on Retronix R-Car V4H Sparrow Hawk board .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-08-17 14:41:23 +02:00
Marek Vasut
47148dfd8f arm64: renesas: r8a779g3: Disable dual-rank DRAM on Retronix R-Car V4H ES2 Sparrow Hawk
The R-Car V4H SoC before rev.3.0 can not support dual-rank LPDDR5 DRAM.
This affects 16 GiB dual-rank DRAM configuration of Retronix R-Car V4H
Sparrow Hawk board. Fall back to 8 GiB single-rank DRAM configuration
on such systems instead.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-08-17 14:41:23 +02:00
Marek Vasut
e394ef09bc arm64: renesas: r8a779g3: Disable MicroSD UHS modes on Retronix R-Car V4H Sparrow Hawk EVTA1
The Retronix R-Car V4H Sparrow Hawk old revision EVTA1 does not have MicroSD
voltage switch populated on the board, therefore the board supports only 3V3
and non-UHS MicroSD cards. While the EVTB1 board is populated with Winbond
W77Q51NW SPI NOR, the EVTA1 board is populated with Spansion S25FS512S SPI
NOR, those those SPI NOR IDs to discern the two board revisions and apply
the MicroSD related DT changes.

The MicroSD related DT changes modify the regulator node, which is now a
regulator-fixed and supplies only 3V3, and remove sd-uhs-sdr50 and
sd-uhs-sdr104 properties from the MicroSD slot controller node.

The MicroSD related DT changes cannot be applied as DTO, because the base
DT contains nodes which have to be removed in case of EVTA1, but have to
be present in case of EVTB1 and newer revisions of the board. Because the
EVTA1 is an old revision of the board that is not generally available, it
is better to special case it and keep the base DT compatible with EVTB1
and newer revisions of the board which are actually available.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-08-17 14:41:23 +02:00
Marek Vasut
93297f1f9b pci: pcie-rcar-gen4: Fix PHY initialization
R-Car V4H Reference Manual R19UH0186EJ0130 Rev.1.30 Apr. 21, 2025
page 4581 Figure 104.3b Initial Setting of PCIEC(example) middle
of the figure indicates that fourth write into register 0x148 [2:0]
is 0x3 or GENMASK(1, 0). The current code writes GENMASK(11, 0)
which is a typo. Fix the typo.

Fixes: be3dd0dc2f ("pci: pcie-rcar-gen4: Add Renesas R-Car Gen4 DW PCIe controller driver")
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-08-17 14:41:23 +02:00
Martin Schwan
0c558bbad9 bootstd: rauc: Change global method to check any partition
The bootmeth rauc should scan all partitions, in particular whole
devices, and not be a global method. There may exist multiple RAUC
systems on different devices and they should all be detected. This also
fixes a bug, where both a global bootflow and one using an actual,
complete device would be detected at the same time, when scanning for
valid bootflows.

Signed-off-by: Martin Schwan <m.schwan@phytec.de>
Tested-by: Wadim Egorov <w.egorov@phytec.de>
2025-08-14 09:18:43 -06:00
Tom Rini
6531aeed37 env: Correct Kconfig type for ENV_MMC_SW_PARTITION
As part of renaming environment related Kconfig options,
ENV_MMC_SW_PARTITION was inadvertently changed from a string to a bool.
Correct this.

Fixes: ffc4914703 ("env: Rename ENV_MMC_PARTITION to ENV_MMC_SW_PARTITION")
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-08-14 09:17:02 -06:00
Tom Rini
5e2ade730a Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-riscv
CI: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/27379

- Board: mbv: Prepare MBV for CI
- Board: MPFS Icicle Kit cleanup
- Board: Add Andes Voyager board support
- RISCV: Update SYS_BOOTM_LEN to commonly used value
- starfive: fix return code of `mac write_eeprom`
- arch/riscv/lib: update memmove and memcpy for big-endian
2025-08-14 08:51:42 -06:00
Ben Dooks
35d6caad6d arch/riscv/lib: update memmove and memcpy for big-endian
Change the shift patterns for the unaligned memory move and copy code
to deal with big-endian by definign macros to change the shfit left and
right to go the opposite way.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-08-14 15:33:00 +08:00
Heinrich Schuchardt
909ceacf4a starfive: fix return code of mac write_eeprom
When writing the EEPROM fails, the command usage help text is displayed
after the error message. We should only display the error message instead.

If writing the EEPROM fails, return CMD_RET_FAILURE (1) instead of
CMD_RET_USAGE (-1).

Fixes: aea1bd95b6 ("eeprom: starfive: Enable ID EEPROM configuration")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Acked-by: E Shattow <e@freeshell.de>
2025-08-14 15:33:00 +08:00
Leo Yu-Chi Liang
3856d93ea3 board: MAINTAINERS: Add Voyager board maintainer
Add Voyager board maintainer.

Signed-off-by: Randolph Sheng-Kai Lin <randolph@andestech.com>
Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-08-14 15:33:00 +08:00
Leo Yu-Chi Liang
2da685378f doc: board: voyager: Add documentation for Voyager
Add documentation for Voyager board.

Signed-off-by: Randolph Sheng-Kai Lin <randolph@andestech.com>
Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-08-14 15:33:00 +08:00
Leo Yu-Chi Liang
3239ef494c configs: andes: add Voyager board defconfig
Add default configuration file for Voyager board.

Signed-off-by: Randolph Sheng-Kai Lin <randolph@andestech.com>
Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-08-14 15:33:00 +08:00
Leo Yu-Chi Liang
35995f7ebf board: andestech: Add Voyager board support
Introduce Voyager board specific code, including
- dram info
- shared cache enabling

Signed-off-by: Randolph Sheng-Kai Lin <randolph@andestech.com>
Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-08-14 15:33:00 +08:00
Leo Yu-Chi Liang
a25e1aacdb riscv: dts: andes: Add Voyager device tree
Introduce the initial device tree support for Andes Voyager board.
We will convert to OF_UPSTREAM once the patch series for kernel is merged.

Signed-off-by: Randolph Sheng-Kai Lin <randolph@andestech.com>
Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-08-14 15:33:00 +08:00
Leo Yu-Chi Liang
87f98d9225 riscv: board: Add Andes Voyager board Kconfig support
The Voyager is Andes' first RISC-V development board.
It is built around Qilai SoC,
which includes Andes AX45MP quad-core cluster.

Introduce the Kconfig entry for the Voyager board.

Signed-off-by: Randolph Sheng-Kai Lin <randolph@andestech.com>
Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-08-14 15:33:00 +08:00
Leo Yu-Chi Liang
89e4154431 common: spl: fix compilation warning
Explicitly specify the type by replacing macro with variable
to fix the possible compilation warning.

Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-08-14 15:33:00 +08:00
Jamie Gibbons
f6da31b634 board: microchip: mpfs_icicle: update to use system controller
A new system controller driver has been created to make code modular and
improve and clean code. Update and remove functions to account for these
additional drivers.

Signed-off-by: Jamie Gibbons <jamie.gibbons@microchip.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-08-14 15:33:00 +08:00
Jamie Gibbons
c93a93e4f2 board: microchip: mpfs_icicle: enable new driver configs
Enable the MPFS mailbox and system controller drivers for use with the
Icicle kit. These functions are crucial for the board setup functions
that run in the Icicle board file - mpfs_icicle.c.

Signed-off-by: Jamie Gibbons <jamie.gibbons@microchip.com>
Acked-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-08-14 15:33:00 +08:00
Jamie Gibbons
b7a0ad16f9 misc: add PolarFire SoC system controller
This driver provides an interface to access the functions of the system
controller on the Microchip PolarFire SoC.
This driver includes functions to use the system controller to read
the device serial number.

Signed-off-by: Jamie Gibbons <jamie.gibbons@microchip.com>
Acked-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-08-14 15:33:00 +08:00
Jamie Gibbons
111e9bf6a5 mailbox: add PolarFire SoC mailbox driver
This driver adds support for the single mailbox channel of the MSS
system controller on the Microchip PolarFire SoC.

Signed-off-by: Jamie Gibbons <jamie.gibbons@microchip.com>
Acked-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-08-14 15:33:00 +08:00
Jamie Gibbons
69539ef2f1 board: microchip: mpfs_icicle: make use of ft_board_setup()
Move ethernet mac address setting to ft_board_setup() to remove the need
for fdt set in custom boot script.

Signed-off-by: Jamie Gibbons <jamie.gibbons@microchip.com>
Acked-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-08-14 15:33:00 +08:00
Jamie Gibbons
c22c40546b configs: microchip_mpfs_icicle: enable CONFIG_OF_BOARD_SETUP
Enable CONFIG_OF_BOARD_SETUP and other dependencies to allow the use of
the ft_board_setup() function to replace fdt set in boot scripts for
Microchip's MPFS Icicle kit.

Signed-off-by: Jamie Gibbons <jamie.gibbons@microchip.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-08-14 15:33:00 +08:00
Michal Simek
87bd5806e6 xilinx: mbv: Use separate DTB for binman nodes
The commit d92fdb6067 ("binman: Add option for pointing to separate
description") added support for separating binman description to own file
not the be the part of DT for OS.
The main reason is that binman is not passing dt schema validation that's
why want to keep it separated.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Acked-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-08-14 14:32:00 +08:00
Michal Simek
5fe8b53209 xilinx: mbv: Fix dt properties in interrupt controller node
Properties didn't match dt binding that's why should be fixed.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-08-14 14:32:00 +08:00
Michal Simek
441ac08142 xilinx: mbv: Add missing mmu-type cpu property
OpenSBI expects mmu-type to be present in DT that's why add it. Without it
OpenSBI disable CPU node which ends up in not working boot.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-08-14 14:32:00 +08:00
Michal Simek
5f5bba72c2 xilinx: mbv: Disable OF_HAS_PRIOR_STAGE
There is no reason to use OF_BOARD for MBV because reduced DT is used by
SPL and full DT is passed via u-boot.img or u-boot.itb. There is no reason
to pick up DTB from certain address.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-08-14 14:32:00 +08:00
Martin Herren
4bd206a423 riscv: Increase Microchip Icicle's SYS_BOOTM_LEN
Increase Icicle's SYS_BOOTM_LEN to 0x4000000 which is the new default
value.
Done on Conor Dooley's request.

Signed-off-by: Martin Herren <sputnik@on-the-web.ch>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-08-14 14:32:00 +08:00
Martin Herren
2fd48ef2d7 riscv: Remove default SYS_BOOTM_LEN from defconfig
Remove CONFIG_SYS_BOOTM_LEN from all riscv defconfigs where the new
default value is used.

Signed-off-by: Martin Herren <sputnik@on-the-web.ch>
Acked-by: Michal Simek <michal.simek@amd.com> # xilinx_mbv
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-08-14 14:32:00 +08:00
Martin Herren
b8e140c1f2 riscv: Set SYS_BOOTM_LEN default to 0x4000000
This changes the default value to the most commonly used one among
existing defconfigs.

Signed-off-by: Martin Herren <sputnik@on-the-web.ch>
Acked-by: Michal Simek <michal.simek@amd.com> # xilinx_mbv
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
2025-08-14 14:32:00 +08:00
Martin Herren
4da366de5d riscv: Set SYS_BOOTM_LEN explicitly to 0x800000
For all riscv defconfigs that use the current default value.

This is done in provision of changing the default value to the most
common used value of 0x4000000.

Signed-off-by: Martin Herren <sputnik@on-the-web.ch>
Acked-by: Michal Simek <michal.simek@amd.com> # xilinx_mbv
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-08-14 14:32:00 +08:00
Michal Simek
c64fc632a8 riscv: cpu: Use CONFIG_IS_ENABLED(CPU) instead of plain ifdef
ifdef CONFIG_CPU only works in U-Boot proper but macro is not working when
XPL phases are used. In this case CONFIG_SPL_CPU is also defined and can be
disabled which is causing compilation error.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-08-14 14:32:00 +08:00
Tom Rini
869217ee29 Merge tag 'qcom-fixes-13Aug2025' of https://source.denx.de/u-boot/custodians/u-boot-snapdragon
CI: https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/pipelines/27364

Quite a few Smatch issues reported by Andrew, and the LMB allocation
fix.
2025-08-13 08:57:49 -06:00
Andrew Goodbody
d9fbc1d70b pinctrl: qcom: sdm845: Limit check off by 1
The driver specifies 154 pins so should have a maximum selector of 153
to ensure that the index into the array special_pins_names does not
overflow.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Link: https://lore.kernel.org/r/20250807-pinctrl_qcom-v1-2-42fac6707fd5@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-08-13 15:18:49 +02:00
Andrew Goodbody
be12b6e158 pinctrl: qcom: sa8775: Limit check for array index not correct
In sa8775p_get_pin_name the limit check for the index into
msm_special_pins_data allows for more elements than exist. Add code to
ensure the array index remains in bounds.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Link: https://lore.kernel.org/r/20250807-pinctrl_qcom-v1-1-42fac6707fd5@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-08-13 15:18:49 +02:00
Andrew Goodbody
8a0bb0b176 button: qcom-pmic: Fix dereference of uninitialised pointer
The pointer 'label' is declared and later dereferenced without ever
having a value assigned to it. Add an assignment to this pointer so it
will be valid later when dereferenced.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://lore.kernel.org/r/20250723-button-qcom-pmic-v1-1-9c317ac71167@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-08-13 15:17:46 +02:00
Andrew Goodbody
10e65926a3 serial: msm-geni: No need to NULL check priv
The NULL check for priv in qcom_geni_serial_poll_bit serves no useful
prupose as too much other code surrounding it relies on priv being
valid. Remove the NULL check for priv and other related code.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Link: https://lore.kernel.org/r/20250811-serial_msm_geni-v1-2-4499179491bc@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-08-13 15:17:36 +02:00
Andrew Goodbody
f236451cb4 serial: msm-geni: Detect error from get_clk_div_rate
In msm_serial_setbrg if the call to get_clk_div_rate fails then there
will not have been an assignment to clk_div which will lead to the call
to geni_serial_baud using an uninitialised value.
Check for an error from get_clk_div_rate and return an error code if so.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://lore.kernel.org/r/20250811-serial_msm_geni-v1-1-4499179491bc@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-08-13 15:17:36 +02:00
Casey Connolly
23e1a11f4e mach-snapdragon: fix erroneous lmb allocations
In commit 6e4675b8e5 ("lmb: replace the lmb_alloc() and
lmb_alloc_base() API's") an additional allocation was mistakenly
introduced resulting in ${kernel_comp_size} containing the address of a
second 64mb region rather than the actual value of KERNEL_COMP_SIZE.

Additionally, in commit b40d7b8f72 ("Merge patch series "lmb: use
a single API for all allocations"") merge conflict resulted in an
additional 128mb allocation for ${loadaddr} when CONFIG_FASTBOOT
is enabled, where it should actually be set to the same value as
${fastboot_addr_r} to respect size constraints (and since it doesn't
seem to interfer with any bootflows).

Fixup both of these, freeing up 192mb of memory.

Fixes: 6e4675b8e5 ("lmb: replace the lmb_alloc() and lmb_alloc_base() API's")
Fixes: b40d7b8f72 ("Merge patch series "lmb: use a single API for all allocations"")
Link: https://lore.kernel.org/r/20250811104710.1896382-1-casey.connolly@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-08-13 15:14:04 +02:00
Andrew Goodbody
fda7bee646 phy: qcom: Fix ret is uninitialised
In qcom_snps_eusb2_phy_probe after the call to devm_clk_get if an error
is found then ret is printed but has not been assigned to by the code.
Decode the error from the pointer and assign it to ret.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250806-phy_qcom_snps-v1-1-5cda830026c7@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-08-13 15:13:16 +02:00
Andrew Goodbody
c1168f9938 mmc: gen_atmel_mci: NULL check variable before use
In mci_send_cmd the pointer 'data' is optional so guard its use with a
NULL check to prevent any attempt to dereference it when not provided.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2025-08-13 12:59:36 +03:00
Andrew Goodbody
4fb189a58e mmc: gen_atmel_mci: Remove duplicate checks
Remove duplicate checks on status from mci_data_read and mci_data_write
which are guaranteed to be true as exiting the above do..while loop
above requires that to be so.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2025-08-13 12:59:36 +03:00
Andrew Goodbody
b824136ab4 mfd: atmel-smc: Ensure match is initialised
If the test in the for loop is never matched then the variable 'match'
will never be assigned to. Provide an initial value so this cannot be a
problem.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-08-13 12:59:36 +03:00
Andrew Goodbody
da13ce8a6b clk: at91: Fix use of unsigned loop index
The use of the unsigned variable 'i' as a loop index leads to the test
for i being non-negative always being true. Instead declare 'i' as an
int so that the for loop will terminate as expected.
If the original for loop completes 'i' will be 1 past the end of the
array so decrement it in the subsequent error path to prevent an out of
bounds access occurring.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-08-13 12:59:36 +03:00
Andrew Goodbody
29ea990a1c clk: at91: Fix testing of unsigned variable to be negative
The variable 'index' is declared as unsigned but used to receive the
return value of a function returning 'int'. This value is then tested
for being less than zero to detect an error condition but as index is
unsigned this can never be true. Change the variable 'index' to be an
int so that the error condition can be detected.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-08-13 12:59:36 +03:00
Ramin Moussavi
709b5be0a4 spi: atmel_qspi: fix race condition in transfer completion check
In atmel_qspi_transfer(), the status register is polled with:

  imr = QSPI_SR_INSTRE | QSPI_SR_CSR;
  return readl_poll_timeout(aq->regs + QSPI_SR, sr,
                            (sr & imr) == imr,
                            ATMEL_QSPI_TIMEOUT);

However, this is racy: QSPI_SR_INSTRE can be set before QSPI_SR_CSR,
and will then be cleared by the read. If that happens, the condition
"(sr & imr) == imr" can never be true, and the function times out.

This race condition is avoided in at91bootstrap by accumulating the
status bits across reads until both bits have been observed:

  /* Poll INSTruction End and Chip Select Rise flags. */
  imr = (QSPI_SR_INSTRE | QSPI_SR_CSR);
  sr = 0;
  do {
    udelay(1);
    sr |= qspi_readl(qspi, QSPI_SR) & imr;
  } while ((--timeout) && (sr != imr));

Update U-Boot's atmel_qspi_transfer() to use the same pattern,
ensuring that both flags are observed even if they are not set
simultaneously.

Signed-off-by: Ramin Moussavi <lordrasmus@gmail.com>
[eugen.hristev@linaro.org: remove 'sr' and fix commit msg]
Signed-off-by: Eugen Hristev <eugen.hristev@linaro.org>
2025-08-13 12:59:02 +03:00
Tom Rini
8385793c4c Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi
These changes are  mostly smaller fixes, and some additions that were
dependent on recent DT updates: We switch the S3/V3/V3s over to
OF_UPSTREAM, the DTs were already identical anyway. While at it, Paul
sent more fixes for this SoC, I am pulling in two easy fixes that were
ready and low risk. Apart from other assorted fixes, this PR also
enables Ethernet on the new A527/T527 boards, made possible by the DT
update from the DT rebasing repository.

This passed the CI, and was boot tested on boards with Allwinner A10,
A20, A33, V40, A80, A83T, T113s3, F1C100s, H3, A64, H6, H616, A133 and
T527 SoCs.
2025-08-12 09:23:13 -06:00
Andre Przywara
c453a80cc3 sunxi: H616: dram: fix LPDDR3 mode register settings
The JEDEC LPDDR3 spec defines mode register 0 (MR0) as being read-only,
so there is no point in trying to set its value.
Also the H616 memory controller encodes the mode register index to be
written starting from bit 8 in MRCTRL1 (for LPDDR3 and LPDDR4 chips), so
we need to OR in that number to tell the controller which MR to program.

On top of that, the mode registers between DDR3 and LPDDR3 are
completely different, so writing values crafted for DDR3 into a LPDDR3
chip is just wrong. Due to the above mentioned bugs the writes for
MR0-MR2 did not have any effect (as they were all trying to set the
read-only MR0), so the mode registers just stayed unchanged.

Looking at the LPDDR3 spec and the BSP code, let's write the proper MR
values into LPDDR3 chips, using the proper addressing mode.
Use the opportunity to document the LPDDR3 mode register bits written.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2025-08-12 10:44:07 +01:00
Eric Anderson
7161a5f686 sunxi: Enable SPL/SPI boot for OLinuXino Lime2
58e9502e6 "arm: sunxi: Enable SPL/SPI boot for Olinuxino Lime2-eMMC
boards" enabled SPI boot for the eMMC variant. Olimex offers the
"s16MB" variant with SPI flash populated but without eMMC populated.
Tested on board rev L.

Signed-off-by: Eric Anderson <ejona86@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2025-08-12 10:44:07 +01:00
Andre Przywara
4b8405b547 sunxi: spl: initialise timer before clocks
Recent changes in the H6 clock code added delay() calls into the SPL clock
setup routine, which requires the timers to work. When compiling for
AArch64, we are always using the Arm Generic Timer (aka. arch timer),
which does not require further setup, hence having an empty timer_init()
routine.
However for 32-bit SoCs we use the Allwinner timers, which require some
setup routine, and hence we need timer_init() to be called before
clock_init().

Swap the order of the two calls, to be more robust when compiling the H6
clock code for AArch32 or when using the Allwinner timers for whatever
reason.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2025-08-12 10:44:01 +01:00
Paul Kocialkowski
b26eea99b1 sunxi: pinecube: Enable EMAC and network support
The pinecube has an ethernet connector which uses the EMAC and internal
PHY of the chip. Enable it in the config.

Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
2025-08-12 00:50:57 +01:00
Andre Przywara
cef5636d5a sunxi: a133: dram: fix data type for address variable
Variables holding addresses are typically using the "long" C type in
U-Boot, to be easily compatible with both 32-bit and 64-bit builds.

The A133 DRAM driver is typically compiled for AArch64, so u64 is the
same type as unsigned long, but that breaks when compiling the DRAM
driver in AArch32 (for some experiments).

Fix the type to make the code more portable.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2025-08-12 00:50:57 +01:00
Andre Przywara
50dfe957c6 sunxi: a527: radxa/avaota: enable Ethernet
The first of the two Ethernet controllers in the Allwinner A527/T527 is
compatible to the MAC from the previous SoCs. Consequently the recent DT
update brought use the MAC node, using the A64 compatible string as the
fallback, which works out of the box.

Enable the sun8i-emac Ethernet driver in the defconfig for the Radxa and
the Avaota boards, so that kernels and other data can be loaded via
TFTP. Please note that only one of the Ethernet sockets will work, the
second MAC is not compatible, and needs a new U-Boot driver. The
X96QPro+ TV box unfortunately uses only this second EMAC, so Ethernet
cannot be used there at the moment.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2025-08-12 00:50:57 +01:00
Andre Przywara
06b18e1ed5 pinctrl: sunxi: a523: change Ethernet pin function name
The name of the pin function was changed last minute in the DT, from
emac0 to gmac0.
Adjust the name we use in the pinctrl driver accordingly.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2025-08-12 00:50:57 +01:00
Paul Kocialkowski
e706ea63b9 sunxi: Kconfig: Fix default order for V3s DRAM clock
The V3s (using co-packaged DRAM) runs at 360 MHz, which is specified in
the common platform Kconfig file. However the value for MACH_SUN8I will
be picked up instead due to ordering.

Re-order the defaults to have MACH_SUN8I_V3S before MACH_SUN8I and let
it select the correct default. Also update the LicheePi Zero Dock
defconfig to remove the value, which is now correctly selected.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2025-08-12 00:50:57 +01:00
Paul Kocialkowski
23137e72f0 sunxi: Switch V3/V3s device-tree source to OF_UPSTREAM
There is nothing special for u-boot in the V3/V3s device-tree files,
they are just copies of the upstream ones.

Remove the copies and switch to OF_UPSTREAM for supported boards.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2025-08-12 00:50:48 +01:00
Tom Rini
acfacf4524 Prepare v2025.10-rc2
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-08-11 13:47:46 -06:00
Tom Rini
ea9b3dbfdd configs: Resync with savedefconfig
Resync all defconfig files using qconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-08-11 12:05:31 -06:00
Tom Rini
6d3382fad3 arm: socfpga: Correct how we set BOOTFILE
In order to set the BOOTFILE symbol we first need to have USE_BOOTFILE
be set, or some of the logic might not work as expected later on when
building. Second, defaults like this belong with the symbol itself.

Fixes: da595d236b ("include: configs: soc64: Use CONFIG_SPL_ATF to differentiate bootfile")
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-08-11 11:58:25 -06:00
Tom Rini
83ce0b483c Merge tag 'u-boot-socfpga-next-20250808' of https://source.denx.de/u-boot/custodians/u-boot-socfpga
This pull request introduces initial U-Boot support for Agilex7 M-series, along
with several enhancements and cleanups across existing Agilex platforms. Key
changes include new board support, DDR driver additions, updated device trees,
and broader SoCFPGA SPL improvements.

Highlights:

- Agilex7 M-series bring-up:
  - Basic DT support and board initialization for Agilex7 M-series SoC and
    SoCDK.
  - New sdram_agilex7m DDR driver with UIBSSM mailbox support and HBM support.
  - Clock driver support for Agilex7 M-series.
  - New defconfig: socfpga_agilex7m_defconfig.
- Agilex and Agilex5 enhancements:
  - Improved SPL support: ASYNC interrupt enabling, system manager init
    refactor, and cold scratch register usage.
  - Updated firewall probing and watchdog support in SPL.
  - Cleaned up DDR code, added secure region support for ATF, and improved warm
    reset handling.
- Device Tree and config updates:
  - Migration to upstream Linux DT layout for Agilex platforms.
  - Consolidated socfpga_agilex_defconfig and removed deprecated configs.
  - Platform-specific environment variables for Distro Boot added.
- Driver fixes and cleanups:
  - dwc_eth_xgmac and clk-agilex cleanup and improvements.
  - Several coverity and style fixes.

Contributions in this PR are from Alif Zakuan Yuslaimi, Tingting Meng, and
Andrew Goodbody.  This patch set has been tested on Agilex 5 devkit, Agilex
devkit and Agilex7m devkit.

Passing all pipeline tests at SoCFPGA U-boot custodian
https://source.denx.de/u-boot/custodians/u-boot-socfpga/-/pipelines/27318
2025-08-08 11:13:41 -06:00
Tom Rini
e51e139cdf Merge tag 'efi-2025-10-rc2' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request efi-2025-10-rc2

Documentation:

* Describe running U-Boot as a pflash image on RISC-V QEMU
* Correct the description of the bootph-verify device-tree property

UEFI:

* In mkeficapsule fix a resource leak in read_bin_file()
* Support loading a Linux initial RAM disk with the bootefi command.
2025-08-08 11:09:42 -06:00
Heiko Schocher
9fd31937dd MAINTAINERS: update email address of Heiko Schocher
use the new email address for community work.

While at it, cleanup git shortlog output, by adding
fixes in .mailmap

Signed-off-by: Heiko Schocher <hs@nabladev.com>
2025-08-08 08:33:59 -06:00
Tom Rini
7ef148daa4 Merge tag 'u-boot-imx-master-20250808' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/27314

- Several Smatch reported fixes.
- Enable the temperature command on imx8ulp-evk.
- Fix mx8mm_fracpll_tbl.
- Make optee packaging optional for imx8m.
- Reuse and export low_drive_freq_update() on imx9.
- Enable USB OTG ID pin pull up in SPL on dh-imx6.
2025-08-08 08:33:19 -06:00
Tingting Meng
8eecbaf957 configs: Add defconfig for Agilex7 M-series
Add defconfig for Agilex7 M-series.

Signed-off-by: Tingting Meng <tingting.meng@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-08-08 22:20:55 +08:00
Tingting Meng
2f429d2eb4 arch: arm: dts: Update Makefile for new platform Agilex7 M-series
Update Makefile to support Agilex7 M-series platform enablement.

Signed-off-by: Tingting Meng <tingting.meng@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-08-08 22:20:55 +08:00
Tingting Meng
605cf610c1 arch: arm: mach-socfpga: Update kconfig for new platform Agilex7 M-series
Update Kconfig for new platform Agilex7 M-series.

Signed-off-by: Tingting Meng <tingting.meng@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-08-08 22:20:54 +08:00
Tingting Meng
4face059c1 ddr: altera: soc64: Fix dram size calculation in clamshell mode
Fix wrong memory size calculation in clamshell mode

Signed-off-by: Tingting Meng <tingting.meng@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-08-08 22:20:54 +08:00
Tingting Meng
e5bc1aee5e ddr: altera: soc64: Clean up bit-shift by zero bit
Clean up bit-shift by zero bit

Signed-off-by: Tingting Meng <tingting.meng@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-08-08 22:20:54 +08:00
Tingting Meng
0b5376b34a ddr: altera: Add DDR driver for Agilex7 M-series
This is for new platform enablement for Agilex7 M-series.
Add DDR driver for Agilex7 M-series. This driver is designed to support
DDR and HBM memory. The official HBM handoff is not ready yet, therefore
hardcoded handoff is used for HBM driver validation on mUDV board.

Signed-off-by: Tingting Meng <tingting.meng@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-08-08 22:20:54 +08:00
Tingting Meng
a00a7a2570 ddr: altera: Add uibssm mailbox support for Agilex7 M-series with HBM
Add uibssm mailbox driver for Agilex7 M-series. HPS will interact with UIB
and HBM subsystem through software defined mailbox interface.
HPS can retrieve HBM memory interface calibration status, UIB
configuration, memory interfae configuration, trigger calibration and etc
with the list of supported mailbox command type and opcode.

Signed-off-by: Tingting Meng <tingting.meng@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-08-08 22:20:53 +08:00
Tingting Meng
7a7c10054d clk: altera: Add clock support for Agilex7 M-series
Agilex7 M-series reuse the clock driver from Agilex.

Signed-off-by: Tingting Meng <tingting.meng@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-08-08 22:20:53 +08:00
Tingting Meng
da595d236b include: configs: soc64: Use CONFIG_SPL_ATF to differentiate bootfile
ATF boot flow (SPL->ATF->U-Boot Proper->OS) boot to OS via kernel.itb file
using bootm command.

Change to use CONFIG_SPL_ATF to differentiate the bootfile of default
environment variable. We shouldn't use CONFIG_FIT because it is enabled
by default for U-Boot Proper.

Signed-off-by: Tingting Meng <tingting.meng@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-08-08 22:20:53 +08:00
Tingting Meng
f64130138a include: configs: Add config header file for Agilex7 M-series
Add config header file for new platform Agilex7 M-series.

Signed-off-by: Tingting Meng <tingting.meng@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-08-08 22:20:52 +08:00
Tingting Meng
7ef12cd7b2 arch: arm: mach-socfpga: Update handoff settings for Agilex7 M-series
Handoff settings updated for new platform Agilex7 M-series.

Signed-off-by: Tingting Meng <tingting.meng@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-08-08 22:20:52 +08:00
Tingting Meng
bd961f896f arch: arm: mach-socfpga: Improve help info.
To improve help info for bridge enable/disable command.

Signed-off-by: Tingting Meng <tingting.meng@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-08-08 22:20:52 +08:00
Tingting Meng
8f7d55037c arch: arm: mach-socfpga: Add Agilex7 M-series mach-socfgpa enablement
Add platform related files for new platform Agilex7 M-series.

Signed-off-by: Tingting Meng <tingting.meng@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-08-08 22:20:51 +08:00
Tingting Meng
4f14fa7cff arch: arm: dts: Basic device tree support added for Agilex7 M-series
Agilex7 M-series support has been added using upstream Linux DTS.

socfpga_agilex_socdk-u-boot.dtsi was updated to support both Agilex and
Agilex7 M-series platforms.

Signed-off-by: Tingting Meng <tingting.meng@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-08-08 22:20:51 +08:00
Tingting Meng
78c44977a2 arch: arm: dts: agilex: Switch to using upstream Linux DT config
Migrate the legacy Agilex platform to use the upstream Linux device tree
configuration. This helps reduce maintenance overhead and aligns U-Boot
with the Linux kernel's DTS hierarchy and naming conventions.

This change improves consistency between U-Boot and Linux by removing
custom/legacy DTS handling and instead relying on the standardized
definitions provided by the upstream Linux DTS.

Signed-off-by: Tingting Meng <tingting.meng@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-08-08 22:20:51 +08:00
Tingting Meng
c465ff14a3 arch: arm: agilex: Clean up DT settings in U-Boot dtsi files
Reorganize misplaced properties by moving board-common settings from
socfpga_agilex_socdk-u-boot.dtsi to socfpga_agilex-u-boot.dtsi to maintain
proper separation between common and board-level configurations.

Signed-off-by: Tingting Meng <tingting.meng@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-08-08 22:20:50 +08:00
Alif Zakuan Yuslaimi
71916a72f1 arm: socfpga: soc64: Perform warm reset after L2 reset in SPL
SPL checks for a magic word in the system manager's scratch
register to determine if an L2 reset has occurred. If detected,
SPL places all slave CPUs (CPU1–3) into WFI mode. The master
CPU (CPU0) then initiates a warm reset by writing to the RMR_EL3
system register and also enters WFI mode.

This warm reset flow is handled entirely within the HPS. The
function `socfpga_sysreset_request()` triggers the warm
reset, and upon SPL re-entry, the updated `lowlevel_init_soc64.S`
handles the necessary initialization.

Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-08-08 22:20:50 +08:00
Alif Zakuan Yuslaimi
c8f5166cff sysreset: socfpga: soc64: Enable L2 reset
Put all slave CPUs (CPU1-3) into WFI mode. Master CPU (CPU0) writes
the magic word into system manager's scratch register to indicate
the system has performed L2 reset and request reset manager to
perform hardware handshake and then trigger L2 reset. CPU0 put
itself into WFI mode. L2 reset will reboot all HPS CPU cores after
which all HPS cores are in WFI mode. L2 reset is followed by warm
reset request by SPL via RMR_EL3 system register.

Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-08-08 22:20:50 +08:00
Alif Zakuan Yuslaimi
3a1cd4ffd7 arm: socfpga: misc: Exclude Agilex from clock manager base address retrieval
Agilex retrieves its clock manager address via probing its own clock
driver model during the SPL initialization.

Therefore, excluding Agilex from calling its clock driver in misc
driver to retrieve the clock manager address.

Once all SoC64 devices has been successfully transition to clock
driver model method, this implementation will be cleaned up.

Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-08-08 22:20:49 +08:00
Alif Zakuan Yuslaimi
9a7881abeb include: configs: socfpga: Add environment variables for distro boot
Added environment variables needed to support NAND distro boot

Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-08-08 22:20:49 +08:00
Alif Zakuan Yuslaimi
1e354de7fc ddr: altera: agilex: Get ACF from boot scratch register
The DDR data rate must be set correctly in the DDRIOCTRL
register according to the Actual Clock Frequency (ACF) value.

By enabling the reading of ACF value from bit 18 of the boot
scratch register during initialization, the DDR data rate is
able to be configured accurately.

Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-08-08 22:20:49 +08:00
Alif Zakuan Yuslaimi
209d53eb1b arm: socfpga: Define the usage of boot scratch cold reg 8
The boot scratch cold reg 8 is shared between DBE, DDR init progress
update and Linux EDAC. This patch defines how the bits are used by
respective features above and their macro names used in U-Boot.

Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-08-08 22:20:48 +08:00
Alif Zakuan Yuslaimi
2c0faf0721 ddr: altera: agilex: Remove code redundancy
Remove redundant code for MPFE CSR firewall disabled as this was
already set in DTreg dts.

Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-08-08 22:20:48 +08:00
Alif Zakuan Yuslaimi
362c355dd7 ddr: altera: soc64: Add secure region support for ATF flow
Setting up firewall regions based on SDRAM memory banks configuration
(up to CONFIG_NR_DRAM_BANKS banks) instead of using whole address space.

First 1 MiB (0 to 0xfffff) of SDRAM is configured as secure region,
other address spaces are non-secure regions. The ARM Trusted Firmware (ATF)
image is located in this first 1 MiB memory region. So, this can prevent
software executing at non-secure state EL0-EL2 and non-secure masters
access to secure region.

Add common function for firewall setup and reuse for all SoC64 devices.

Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-08-08 22:20:48 +08:00
Alif Zakuan Yuslaimi
1dc683005d arm: socfpga: agilex: Enable system manager driver for Agilex
The base address of system manager can be retrieved
using DT framework through the system manager driver.

Enable system manager support for Agilex by probing the
system manager driver to initialize during SPL boot up.

Signed-off-by: Boon Khai Ng <boon.khai.ng@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-08-08 22:20:48 +08:00
Alif Zakuan Yuslaimi
5416a3a306 arm: socfpga: agilex5: Refactor system manager driver initialization
Refactor system manager initialization by searching for system manager
alias in Agilex5 device tree instead of manually passing node name to
the device model calling function

Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-08-08 22:20:47 +08:00
Alif Zakuan Yuslaimi
a44423e7e9 drivers: clk: agilex: Replace status polling with wait_for_bit_le32()
Replace cm_wait_for_fsm() function with wait_for_bit_le32() function
which supports accurate timeout.

Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-08-08 22:20:47 +08:00
Alif Zakuan Yuslaimi
6a4453ab06 drivers: watchdog: Enable watchdog support in SPL for Agilex
Enable watchdog as early as possible after clock initialization
which is set at 10 seconds.

Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-08-08 22:20:46 +08:00
Tien Fong Chee
3721998510 arm: socfpga: Enable ASYNC interrupts in Agilex SPL
Asynchronous aborts were previously masked at SPL
entry.

To ensure early detection of system errors
such as ECC faults or bus errors, asynchronous aborts
should be explicitly unmasked by clearing the A-bit in
the DAIF register during Agilex SPL initialization.

Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>

# Conflicts:
#	arch/arm/mach-socfpga/spl_agilex.c
2025-08-08 22:20:42 +08:00
Alif Zakuan Yuslaimi
677147c167 arm: socfpga: Update Agilex SPL data save and restore implementation
Enable backup for data section to support warm reset in Agilex SPL as
no SPL image would be reloaded in warm reset.

Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-08-08 22:19:23 +08:00
Primoz Fiser
b6e2cfca1a board: phytec: phycore-imx93: Add VOLT_LOW_DRIVE frequency fixup
For phyCORE-i.MX93 SoMs with i.MX93 parts running in VOLT_LOW_DRIVE mode
(SoCs with speed grade fuse set to 900 MHz) reduce usdhc clocks from 400
MHz to 266 MHz. Do this in board code since global imx9 board_fix_fdt()
is not used in case of phycore-imx93 board since commit d3b9b79968
("board: phytec: imx93: Add eeprom-based hardware introspection").

While at it, add a note to ft_board_setup() function to inform that
fixup for Linux device-tree is taken care by ft_system_setup() in imx9
global arch/arm/mach-imx/imx9/soc.c implementation.

Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
2025-08-08 08:28:06 -03:00
Primoz Fiser
442e752854 imx9: soc: Reuse and export low_drive_freq_update()
Reuse and export low_drive_freq_update() function. This way global imx9
board_fix_fdt() doesn't duplicate code. While low_drive_freq_update()
can be reused on boards such as phyCORE-i.MX93 (TARGET_PHYCORE_IMX93)
which is not using the global imx9 board_fix_fdt() implementation.

While at it, make printout logic less verbose by only outputting on the
error condition and not on each successful clock fixup. Also drop now
invalid comment (low_drive_freq_update() now does fixup for internal and
kernel device-tree).

Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
2025-08-08 08:28:06 -03:00
Alif Zakuan Yuslaimi
60a377db98 arm: socfpga: agilex: Probe DT for firewall setup
Update Agilex SPL code to implement device tree model
for firewall registers setup by using DTreg driver to
probe from device tree for the firewall settings instead
of calling firewall driver function.

Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-08-08 16:01:03 +08:00
Alif Zakuan Yuslaimi
e328332aaf arch: arm: dts: agilex: Update Agilex device tree
Update exisitng Agilex device tree to support multiple flashes boot
- MMC, QSPI and NAND.

Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-08-08 16:00:45 +08:00
Alif Zakuan Yuslaimi
d77b25ee37 configs: agilex: Combine defconfig for all boot flashes
Combine all MMC, NAND and QSPI configs into single defconfig which is named
as "socfpga_agilex_defconfig". This will be the default defconfig to use.
It supports booting from all three flashes using ARM Trusted Firmware (ATF)
as the secure runtime monitor.

Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-08-08 16:00:30 +08:00
Alif Zakuan Yuslaimi
532fd00bdb drivers: clk: agilex: Use real clock source frequency
Update the ARMv8 generic timer frequency register (cntfrq_el0)
with the actual hardware timer frequency (COUNTER_FREQUENCY_REAL).

The generic timer frequency was set to 0x200000000 during boot clk
which needs to be set to 0x400000000 when transition from boot clk
to PLL clk.

This will ensure that subsequent timer operations are based on the
correct frequency, ensuring accurate timekeeping.

Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-08-08 16:00:16 +08:00
Andrew Goodbody
28c06d67cf net: dwc_eth_xgmac_socfpga: Remove always true test
In dwxgmac_of_get_mac_mode there is a test for mac_mode which will
return if false. After this point mac_mode is guaranteed to be true so
there is no need to test for this. Remove that test.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-08-08 15:59:58 +08:00
Andrew Goodbody
7701cc3415 net: dwc_eth_xgmac: Use unwind goto on error
In xgmac_probe there is a direct return after the point where unwind
gotos start to be used to undo actions performed by earlier code. Use
the appropriate unwind goto instead.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-08-08 15:58:10 +08:00
Leo Yu-Chi Liang
598df59f75 doc: spl: fix typo 'TPL' to 'VPL'
Fix typo: change 'TPL' to 'VPL'.

Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2025-08-08 08:52:12 +02:00
Simon Glass
47e9b73954 efi_loader: Support loading a ramdisk with bootefi
It is sometimes useful to be able to boot via EFI using a Linux initrd.
Add support for this.

Fix a 'specifiy' typo while here.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-08-08 08:45:18 +02:00
Heinrich Schuchardt
8e5d34a3a2 doc: qemu-riscv: describe running as flash image
Describe how to build U-Boot to be run by QEMU as an emulated flash image.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2025-08-08 08:45:05 +02:00
Heinrich Schuchardt
e16646c0ad tools: mkeficapsule: resource leak in read_bin_file()
Free the allocated buffer in case of an error.

Fixes: 9e63786e2b ("tools: mkeficapsule: rework the code a little bit")
Addresses-Coverity-ID: 345917 Resource leak
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2025-08-08 08:44:52 +02:00
Tom Rini
123cd77122 pylibfdt: setup.py: Drop license_files
On more recent versions of setuptools the warning about not being able
to find the files specified in license_files has re-appeared. This is
because as best I can tell, it can't and won't look in $(srctree) but
rather only subdirectories of scripts/dtc/pylibfdt. Since we already
provide both SPDX tags and a license field with the SPDX contents, let
us just drop license_files as it's not mandatory.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-08-07 11:16:12 -06:00
Heinrich Schuchardt
4b97de0e28 virtio: fix freeing of virtio ring buffer
If the allocation if the bounce buffer fails, virtio_free_pages is called
with a random value from the stack.

Ensure that vring.size is initialized.

Fixes: 37e53db38b ("virtio: Allocate bounce buffers for devices with VIRTIO_F_IOMMU_PLATFORM")
Addresses-Coverity-ID: 453314 Uninitialized scalar variable
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2025-08-07 11:15:54 -06:00
Shiji Yang
c60898c9c6 meminfo: correct "free" memory region size
The size of free memory should be $lmb_base - $ram_base.

Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
2025-08-07 11:15:41 -06:00
Takahiro Kuwano
a0526d44da mtd: spi-nor: Fix return value of s25_s28_mdp_ready()
s25_s28_mdp_ready() returns 1 when spansion_sr_ready() returns negative
value (error code). Fix this problem by following Linux implementation.

Fixes: 1c3dd193b5 ("mtd: spi-nor-core: Add fixups for Cypress s25hl-t/s25hs-t")
Reported-by: Hiroyuki Saito <Hiroyuki.Saito2@infineon.com>
Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2025-08-07 11:14:35 -06:00
Balaji Selvanathan
b32dda3450 drivers: scsi: fix inaccurate block count reporting in scsi operations
The 'blks' variable in scsi_read/write/erase functions is updated
regardless of pass/fail of the scsi operation . If the scsi operation
fails, 'blkcnt' is updated using an incorrect value of 'blks'. This
wrong 'blkcnt' is returned to the caller and it assumes all blocks were
processed correctly.

Fix this by updating the 'blks' variable only if the scsi operation
succeeds.

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
2025-08-07 11:14:23 -06:00
Tom Rini
e652183ca0 Merge patch series "arm: dts: k3-am62a: remove GP security variant for AM62A"
Bryan Brattlof <bb@ti.com> says:

The AM62Ax was created right when TI was shifting to their high security
(HS-FS and HS-SE) processes. During this transition a small subset of
AM62A parts where configured to use the old "GP" security for internal
and for select groups of partners but never sold for the wider public.

To help simplify the build and to avoid any confusion of which security
configurations are supported going forward remove the GP builds for the
AM62A SoCs.

Link: https://lore.kernel.org/r/20250729-no-62a-gp-v1-0-1dbdb4469ad3@ti.com
2025-08-07 11:14:07 -06:00
Bryan Brattlof
14706485aa arm: dts: k3-am62a-phycore: remove GP tiboot3 builds
The AM62Ax SoC family was the last part from TI to support the GP
security variant, however this security variant was used mostly
internally and with select early partners and never sold publicly.

To simplify things and to avoid any confusion on which parts are
supported in the future, remove the GP tiboo3.bin builds from binman.

Signed-off-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Acked-by: Wadim Egorov <w.egorov@phytec.de>
2025-08-07 11:14:01 -06:00
Bryan Brattlof
724a71c13e arm: dts: k3-am62a-sk: remove GP tiboot3 builds
The AM62Ax SoC family was the last part from TI to support the GP
security variant, however this security variant was used mostly
internally and with select early partners and never sold publicly.

To simplify things and to avoid any confusion of which parts are
supported in the future, remove the GP tiboot3.bin builds from binman.

Signed-off-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
2025-08-07 11:14:01 -06:00
Yannic Moog
b57ed14793 dts: imx8m{m,n,p,q}: Make optee packaging optional
binman can omit packaging an optional blob when it is missing.
This allows us to not bother with config options.
The core challenge is the interaction between tf-a and OP-TEE where
U-Boot/binman does not know whether tf-a was built with SPD=opteed or
without. This is important because tf-a might jump into the void when no
optee_os is present, leading to boot failure. Thus by marking it
optional, user is prompted to recheck (due to the warning message)
whether they really have the right combination of tf-a and optee.

Due to a bug in binman, we had to guard binman tee.bin with OPTEE config
as builds would error when tee.bin was not present in path; Even though
optee_os was marked as optional in the binman tree. Since the bug has
been resolved in
commit d4f61eae2a ("Merge patch series "Fix handling of optional blobs in binman"")
we can mark it optional again without getting build errors.

Note that after this commit a warning will be printed when optee is not
present for a binman build.

Image 'image' is missing optional external blobs but is still functional: tee-os

/binman/section/fit/images/tee/tee-os (tee.bin):
   See the documentation for your board. You may need to build Open Portable
   Trusted Execution Environment (OP-TEE) and build with TEE=/path/to/tee.bin

Signed-off-by: Yannic Moog <y.moog@phytec.de>
2025-08-07 08:16:33 -03:00
Andrew Goodbody
53158c8cf2 net: fec_mxc: Set error code on error exit
In fecmxc_probe if a timeout is detected when resetting the chip no
error code is set before taking the error exit. This could lead to a
silent failure. Instead set an error code.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-08-07 08:16:18 -03:00
Marek Vasut
d011462eea ARM: imx6: dh-imx6: Enable USB OTG ID pin pull up in SPL
Enable SoC pull up for USB OTG ID pin in SPL. There is no dedicated pull up
resistor on the SoM itself, and the pull up is mandatory for correct USB OTG
ID pin detection. U-Boot proper already configures the USB OTG ID pin pull
up via DT pinctrl node entry.

Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
Tested-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
2025-08-07 08:16:03 -03:00
Andrew Goodbody
5275b5612b imx: scu_api: Remove unnecessary NULL check
In sc_seco_secvio_dgo_config there is a check for data being NULL but
this occurs after data has already been dereferenced. All callers of the
function provide a valid pointer for data so no need for the NULL check.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-08-07 08:15:45 -03:00
Peng Fan
b1a89c5232 imx8m: clock: Correct imx8mm_fracpll_tbl
The minimum frequency of Fref (Fin / p) is 6MHz for the PLL AC
Electrical Characteristics. Setting p with 9 or 8 voilates the Spec.

Update the settings to match Spec.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-08-07 08:15:24 -03:00
Andrew Goodbody
66324e0cec cpu: imx8_cpu: Provide default temperatures
Add setting default temperatures to the weak version of
get_cpu_temp_grade so these values will not be used uninitialised.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-08-07 08:15:00 -03:00
David Zang
fa2c414943 imx8ulp_evk: Enable temperature command
User can display temperature in the console runtime on i.MX8ULP board.

Signed-off-by: David Zang <davidzangcs@gmail.com>
2025-08-07 08:14:31 -03:00
Andrew Goodbody
b65ea8534f clk: imx: Free pll on error path
For an unknown pll type the error path neglects to free the memory just
allocated. Add the free.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-08-07 08:13:17 -03:00
Tom Rini
3526f990b7 Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sh
Various fixes for smatch warnings, the i2c one might be also coming in
via Heiko / I2C tree, let me know if there is conflict.

There is also W77Q51NW SPI NOR ID support, with the DT portion omitted
for now.
2025-08-06 16:07:17 -06:00
Marek Vasut
ef15585a74 arm64: renesas: r8a779g3: Enable Winbond SPI NOR support on Retronix R-Car V4H Sparrow Hawk board
Enable support for Winbond SPI NOR on Retronix R-Car V4H Sparrow Hawk board,
this is required to support W77Q51NW on new board revision EVTB1 operational.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-08-06 15:04:58 -06:00
Andrew Goodbody
6c49b082f0 net: rswitch: Fix error detection
In rswitch_probe the error detection after the call to devm_clk_get is
very wrong. It checks the value of ret which is uninitialised at that
point. Instead it should be using the macros for including errors into
pointers.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-08-06 16:52:27 +02:00
Marek Vasut
393ace55be mtd: spi-nor-ids: Add support for Winbond W77Q51NW
Add IDs for Winbond W77Q51NW, 512M-bit Secure Serial Flash Memory
with Post-Quantum Cryptography, Dual/Quad SPI, QPI and DTR . The
flash part is similar to W25Q512NWM .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2025-08-06 16:52:27 +02:00
Andrew Goodbody
78b2d408fb i2c: rcar_iic: Do not use unitialised variable
In rcar_iic_xfer if nmsgs == 0 the ret will not be assigned to. As ret
will always be 0 if the for loop is entered, may as well just return 0.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-08-06 16:52:27 +02:00
Andrew Goodbody
4ef864f1ae clk: renesas: Do not test unsigned variable to be less than 0
In rcar_clk_set_rate64_div_table the unsigned variable 'value' is used
to receive the return value from rcar_clk_get_table_val which returns an
int and then attempts to test for being less than 0, which can never be
true. Instead declare value as an int so the code can behave as
expected. Also remove initial values from 'value' and 'div' as they are
not needed.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-08-06 16:52:27 +02:00
Tom Rini
29d5636c6f Merge tag 'i2c-updates-for-2025-10-rc2' of https://source.denx.de/u-boot/custodians/u-boot-i2c
i2c updates for v2025.10-rc2

bugfixes:

- rcar_iic: do not use unitialised variable
  from Andrew

- fix coverity issue in cmd/i2c.c
  from Heiko

new driver:

late, but hopefully okay for rc2, as already picked up when
merge window was open, but there was a problem in common code,
which is now fixed

- new i3c driver support from Dinesh
2025-08-06 08:06:23 -06:00
Dinesh Maniyam
d35589f7d4 configs: agilex5_defconfig: Enable i3c configs for agilex5
Enable configs for i3c in agilex5.

Signed-off-by: Dinesh Maniyam <dinesh.maniyam@altera.com>
2025-08-06 08:42:22 +02:00
Dinesh Maniyam
fdb6ab9fd5 configs: sandbox_defconfig: Enable configs for sandbox i3c
Enable configs for sandbox i3c.

Signed-off-by: Dinesh Maniyam <dinesh.maniyam@altera.com>
2025-08-06 08:42:06 +02:00
Dinesh Maniyam
9e014408c1 test: cmd: Add simple test for i3c
Add simple test to check i3c controller defined in sandbox test DT.
Basically, this test case will check validity of the i3c controller
by probing it and perform basic commands of cmd/i3c.c

Signed-off-by: Dinesh Maniyam <dinesh.maniyam@altera.com>
2025-08-06 08:41:52 +02:00
Dinesh Maniyam
b875409da7 cmd: Add i3c command support.
Add i3c command file to support select, get i3c device
target list, read and write operation.

Signed-off-by: Dinesh Maniyam <dinesh.maniyam@altera.com>
2025-08-06 08:41:30 +02:00
Dinesh Maniyam
82cc368cd2 i3c: master: dw-i3c-master: Fix OD_TIMING for spike filter
Fix the I3C device with spike filter unable to detect issue by setting
tHIGH_INIT to 200ns for first broadcast address.
This is according to MIPI SPEC 1.1.1 for first broadcast address
which is already part of linux upstreamed patch.

Signed-off-by: Dinesh Maniyam <dinesh.maniyam@altera.com>
2025-08-06 08:41:14 +02:00
Dinesh Maniyam
b5cf7cd174 drivers: i3c: master: Enable probe i3c without slave device
Picked linux i3c driver upstraming patch to fix the issue to
probe for i3c controller without slave device attached.
With this fix, the ret check will be on command error and will success
without slave device attached.

Signed-off-by: Dinesh Maniyam <dinesh.maniyam@altera.com>
2025-08-06 08:41:01 +02:00
Dinesh Maniyam
ca4c92cbff drivers: i3c: Add i3c sandbox simple test.
Add s simple test for the I3C uclass in sandbox.

Signed-off-by: Dinesh Maniyam <dinesh.maniyam@altera.com>
2025-08-06 08:40:44 +02:00
Dinesh Maniyam
03caa3769a drivers: i3c: Enabled Kconfig and Makefile for DWI3C
Enable the Kconfig and Makefile for the MIPI DWI3C driver.

hs: fixed typo on drivers/i3c/master/Kconfig

Signed-off-by: Dinesh Maniyam <dinesh.maniyam@altera.com>
2025-08-06 08:39:39 +02:00
Dinesh Maniyam
a19a6e7124 drivers: Enabled Kconfig and Makefile for i3c support
Add new i3c driver to U-Boot drivers.

Signed-off-by: Dinesh Maniyam <dinesh.maniyam@altera.com>
2025-08-06 08:38:26 +02:00
Dinesh Maniyam
e49a513760 drivers: i3c: Add i3c uclass driver.
Enable i3c general uclass driver. This uclass driver will have
genaral read and write api to call the specific i3c driver.

Signed-off-by: Dinesh Maniyam <dinesh.maniyam@altera.com>
2025-08-06 08:37:34 +02:00
Dinesh Maniyam
1009c96f15 drivers: i3c: Add driver for MIPI DWI3C
Enable driver for Synopsis MIPI DWI3C for the family
device agilex5. This driver is migrated from linux version 6.6.37 LTS

Signed-off-by: Dinesh Maniyam <dinesh.maniyam@altera.com>
2025-08-06 08:37:13 +02:00
Dinesh Maniyam
633c0cf486 drivers: i3c: Add new i3c uclass id
Add i3c general uclass id.

Signed-off-by: Dinesh Maniyam <dinesh.maniyam@altera.com>
2025-08-06 08:36:59 +02:00
Heiko Schocher
b1463957d1 cmd: i2c: fix coverity issue
coverity scan reported issue:
** CID 583415:       Integer handling issues  (INTEGER_OVERFLOW)
/cmd/i2c.c: 369           in do_i2c_write()

change the length variable into type int.

Signed-off-by: Heiko Schocher <hs@denx.de>
2025-08-06 07:49:13 +02:00
Andrew Goodbody
b68875656c i2c: rcar_iic: Do not use unitialised variable
In rcar_iic_xfer if nmsgs == 0 the ret will not be assigned to. As ret
will always be 0 if the for loop is entered, may as well just return 0.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
2025-08-06 07:48:40 +02:00
Philip Molloy
007610da2c Makefile: Remove expansion of undefined variable
The U-Boot environment was previously stored in the boot loader stream
using ldr, but it has been replaced by the default environment built
into the U-Boot executable or an environment on external storage

Fixes: ea3310e8aa ("Blackfin: Remove")

Signed-off-by: Philip Molloy <philip.molloy@analog.com>
Reviewed-by: Greg Malysa <malysagreg@gmail.com>
2025-08-04 18:23:16 -06:00
Michal Simek
fcac9bfbbd cmd: bdinfo: Fix showing correct IP address based on current device
Use the same logic as is used for MAC address where bdi shows mac address
for current device where index (idx) is used to point to correct IP address
which is read and show.

Signed-off-by: Michal Simek <michal.simek@amd.com>
2025-08-04 18:23:16 -06:00
Heinrich Schuchardt
c03d7a4801 Kconfig: typo restict
%s/restict/restrict/

SPL and TPL have separate options (plural).

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
2025-08-04 18:23:16 -06:00
Tom Rini
12a94b894d test: py: test_fit_mkimage_validate: Only run either test on sandbox
Both of these tests are only valid for sandbox (and require dtc) so both
tests need the pytest annotations.

Fixes: 93d09d3bd8 ("test: fit: add test case for invalid default configuration reference")
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-08-04 18:23:13 -06:00
Tom Rini
851c3f28d0 Merge branch 'u-boot-nand-03082025' of https://source.denx.de/u-boot/custodians/u-boot-nand-flash
CI: https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/pipelines/27258

This series address issues found by Andrew Goodbody and mostly drop
driver that are not used by any board
2025-08-04 08:23:43 -06:00
Tom Rini
488ae65f39 Merge branch 'staging' of https://source.denx.de/u-boot/custodians/u-boot-tegra
-  Pegatron Chagall, Samsung Galaxy R (GT-I9103) and Captivate Glide
   (SGH-i927) support
2025-08-04 08:23:00 -06:00
Tom Rini
8877bbe67a mtd: nand: raw: Remove unused octeontx_nand driver
As no platforms use this driver anymore let's go ahead and remove it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-08-03 10:32:08 +02:00
Tom Rini
cb34f23bdb mtd: nand: raw: Remove unused mxic_nand driver
As no platforms use this driver anymore let's go ahead and remove it.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
2025-08-03 10:31:14 +02:00
Tom Rini
2412f00fc9 mtd: nand: raw: Remove unused lpc32xx_nand_slc driver
As no platforms use this driver anymore let's go ahead and remove it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-08-03 10:27:47 +02:00
Andrew Goodbody
2724246216 mtd: rawnand: mxs_nand: Ensure err is set for error path
In mxs_nand_init_ctrl there are a couple of error paths that do not set
err which could lead to the errors being silently ignored despite the
function not completing. Rather than just using if to detect these
errors use err to collect the error return value from the called
functions.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
2025-08-03 10:22:04 +02:00
Andrew Goodbody
2756de5213 mtd: rawnand: denali: Remove always true test
In denali_wait_for_irq the code will either return from inside the while
loop or exit with time_left being 0. The following test for time_left
being 0 is guranteed to be true so remove the test and the following
unreachable code.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
2025-08-03 10:22:04 +02:00
Andrew Goodbody
ebf8aaf7af mtd: rawnand: cortina_nand: Fix -ENOMEM detection
In init_nand_dma there was code to detect failure to allocate memory but
it had two problems. Firstly the 2nd clause when info->tx_desc was NULL
attempted to free info->tx_desc when it should be freeing info->rx_desc.
Secondly there was no detection of both allocations failing, arguably
the more likely scenario. Refactor the code to simplify it and just fail
as soon as either allocation fails.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
2025-08-03 10:22:04 +02:00
Andrew Goodbody
56372f834c mtd: nand: sunxi: Free allocated memory on errors
Add kfree calls on error paths for memory that was allocated. This will
prevent memory leaks.

This issue found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-By: Michael Trimarchi <michael@amarulasolutions.com>
2025-08-03 10:20:16 +02:00
Andrew Goodbody
4003ed1c1e mtd: rawnand: stm32_fmc2: Ensure to return error code
In stm32_fmc2_nfc_probe there are 3 error returns that do not set the
error code before returning which could lead to the error being silently
ignored. Just return -EINVAL in each case.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2025-08-03 10:20:16 +02:00
Andrew Goodbody
42ef9a0b7f mtd: nand: pxa3xx: Free memory on error
In pxa3xx_nand_probe_dt if the function detects an error after
allocating memory that memory is not freed before exit. Add the
appropriate free.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: MIchael Trimarchi <michael@amarulasolutions.com>
2025-08-03 10:20:16 +02:00
Tom Rini
ae5711f881 Merge patch series "env: mtd: add the missing put_mtd_device()"
This series from Shiji Yang <yangshiji66@outlook.com> fixes some issues
with the recently added "environment in mtd (generic)" functionality.

Link: https://lore.kernel.org/r/OSBPR01MB1670E56647F1F8B4BA66A931BC59A@OSBPR01MB1670.jpnprd01.prod.outlook.com
2025-08-01 17:59:07 -06:00
Shiji Yang
7e842bd331 env: mtd: initialize saved_buf pointer
When sect_size is greater than the CONFIG_ENV_SIZE, this wild
pointer will cause CPU halt or system crash.

Fixes: 03fb08d4ae ("env: Introduce support for MTD")
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
2025-08-01 17:58:59 -06:00
Shiji Yang
39ae954b04 env: mtd: add the missing put_mtd_device()
The mtd device is got in setup_mtd_device(), we must put the mtd
device before exiting the function to update the mtd use count.
This patch fixes the following env error:

> Removing MTD device #2 (u-boot-env) with use count 1
> Error when deleting partition "u-boot-env" (-16)

Fixes: 03fb08d4ae ("env: Introduce support for MTD")
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
2025-08-01 17:58:58 -06:00
Mikko Rapeli
d0075e2d73 Makefile: add dependency from lib to arch/$(ARCH)/lib
Top level Makefile starts separate "make" processes for each each
subdirectory. lib/efi_loader apps now depend on lib.a from
arch/$(ARCH)/lib if CONFIG_USE_PRIVATE_LIBGCC is enabled which creates
a race conditions since dependency from lib/efi_loader EFI apps to
arch/$(ARCH)/lib/lib.a is not explicit:

arm-poky-linux-gnueabi-ld.bfd: cannot find arch/arm/lib/lib.a: No such file or directory
make[3]: *** [scripts/Makefile.lib:512: lib/efi_loader/testapp_efi.so] Error 1

This error was seen on yocto/OE-core CI builds after u-boot 2025.07 update:

https://lists.openembedded.org/g/openembedded-core/message/220004

https://autobuilder.yoctoproject.org/valkyrie/api/v2/logs/2914600/raw_inline

    |    rm -f lib/efi_loader/built-in.o; arm-poky-linux-gnueabi-ar cDPrsT lib/efi_loader/built-in.o lib/efi_loader/efi_bootmgr.o lib/efi_loader/efi_bootbin.o lib/efi_loader
/efi_boottime.o lib/efi_loader/efi_helper.o lib/efi_loader/efi_console.o lib/efi_loader/efi_device_path.o lib/efi_loader/efi_device_path_to_text.o lib/efi_loader/efi_device_
path_utilities.o lib/efi_loader/efi_dt_fixup.o lib/efi_loader/efi_fdt.o lib/efi_loader/efi_file.o lib/efi_loader/efi_hii.o lib/efi_loader/efi_hii_config.o lib/efi_loader/efi
_image_loader.o lib/efi_loader/efi_load_options.o lib/efi_loader/efi_memory.o lib/efi_loader/efi_root_node.o lib/efi_loader/efi_runtime.o lib/efi_loader/efi_setup.o lib/efi_
loader/efi_string.o lib/efi_loader/efi_unicode_collation.o lib/efi_loader/efi_var_common.o lib/efi_loader/efi_var_mem.o lib/efi_loader/efi_variable.o lib/efi_loader/efi_var_
file.o lib/efi_loader/efi_watchdog.o lib/efi_loader/efi_disk.o lib/efi_loader/efi_net.o lib/efi_loader/efi_smbios.o lib/efi_loader/efi_load_initrd.o lib/efi_loader/efi_confo
rmance.o
    |   arm-poky-linux-gnueabi-ld.bfd -nostdlib -zexecstack -znocombreloc -znorelro --no-warn-rwx-segments -L /srv/pokybuild/yocto-worker/oe-selftest-armhost/build/build-st-
3119200/tmp/work/beaglebone_yocto-poky-linux-gnueabi/u-boot/2025.07/sources/u-boot-2025.07 -T arch/arm/lib/elf_arm_efi.lds -shared -Bsymbolic -s lib/efi_loader/helloworld.o
lib/efi_loader/efi_crt0.o lib/efi_loader/efi_reloc.o lib/efi_loader/efi_freestanding.o arch/arm/lib/lib.a -o lib/efi_loader/helloworld_efi.so
    | arm-poky-linux-gnueabi-ld.bfd: cannot find arch/arm/lib/lib.a: No such file or directory
    | make[3]: *** [scripts/Makefile.lib:512: lib/efi_loader/helloworld_efi.so] Error 1

The different "make" processes share common scripts/Makefile.build
and scripts/Makefile.libs but since they are separate processes
the Makefile rules can't add a dependency from lib/uefi_loader targets
to arch/$(ARCH)/lib/lib.a. Or the file level dependency can be added but
then "make" produces a too sparse error message which does not mention
that one of the dependencies like arch/$(ARCH)/lib/lib.a was not found:

make[3]: *** No rule to make target 'lib/efi_loader/helloworld.efi', needed by '__build'.  Stop.

Fix this dependency problem by building arch/$(ARCH)/lib before lib
if CONFIG_USE_PRIVATE_LIBGCC was enabled.

To reproduce the race condition more reliably, add a "sleep 10" delay
before linker command cmd_link_l_target with 2025.07
or to $(lib-target): target in scripts/Makefile.build with master branch
after Kbuild update.

Fixes: 43d43241d1 ("scripts/Makefile.lib: add PLATFORM_LIBGCC to efi linking")

Cc: Adriano Cordova <adrianox@gmail.com>
Cc: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Mikko Rapeli <mikko.rapeli@linaro.org>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2025-08-01 10:56:22 -06:00
Tom Rini
231b40724d Merge tag 'net-20250801' of https://source.denx.de/u-boot/custodians/u-boot-net
Pull request for net-20250801

net:
- Support overriding Auto Negotiation timeout with env variable
  'phy_aneg_timeout'
- Add missing virtqueue_kick() in free_pkt()
- Remove bcm281xx ethernet driver
- Tighten some network driver dependencies in Kconfig
- Add <cpu_func.h> to some platforms
- Fix a debug print in ftgmac100.cA
- Add parentheses around PSEUDO_HDR_SIZE

net-lwip:
- Fix build error with CONFIG_LWIP_DEBUG=y
- Remove eth_init() from net_init() as it is called later
- Simplify net_lwip_eth_start()

net-legacy:
- wget: Fix comparison of unsigned variable
- Incorrect macro used (TCP_0_NOP instead of TCP_1_NOP)
2025-08-01 08:47:50 -06:00
Siddharth Vadapalli
5a4bfe3877 net: phy: Support overriding Auto Negotiation timeout with env variable
The Auto Negotiation procedure between two Ethernet PHYs consists of
determining the best commonly supported parameters among Speed,
Duplex Mode and Flow Control.

The time taken for this procedure is not only dependent on the local
PHY used, but also on the link-partner PHY.

While a timeout can be specified in the form of a "CONFIG" on the basis
of the local PHY present on the device, since the timeout also depends
on the link-partner PHY, it might be necessary to modify the timeout.

To avoid rebuilding the bootloader for a given device, just because it
may be connected to various link-partner PHYs, each with a different
timeout, introduce an environment variable named "phy_aneg_timeout" and
override "CONFIG_PHY_ANEG_TIMEOUT" with "phy_aneg_timeout".

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
[jf: add missing #include <env.h>]
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
2025-08-01 10:42:22 +02:00
Jerome Forissier
71056afe20 lwip: provide a sntp_format_time() function
Provide a trivial implementation of sntp_format_time() to fix a build
error when CONFIG_LWIP_DEBUG=y:

lib/lwip/lwip/src/apps/sntp/sntp.c: In function ‘sntp_format_time’:
lib/lwip/lwip/src/apps/sntp/sntp.c:283:10: error: implicit declaration of function ‘ctime’ [-Werror=implicit-function-declaration]
  283 |   return ctime(&ut);
      |          ^~~~~

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
2025-08-01 09:30:47 +02:00
Christian Speich
d1b4bfc984 virtio: net: Add missing virtqueue_kick in free_pkt
Every virtqueue_add must eventually be followed by virtqueue_kick for to
properly notify the peer that new buffers have been put into the queue.

This is currently missing for virtio-net and may result in non-working
network when the host has depleted the rx buffers and waits for new
buffers. Depending on the host it may busy poll on the virtio queue or
wait for the kick. Qemu does the latter and may break.

Signed-off-by: Christian Speich <c.speich@avm.de>
2025-08-01 09:30:47 +02:00
Tom Rini
3c1ac44caa arm: bcm281xx: Remove ethernet driver
As no platforms enable the ethernet driver, remove it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-08-01 09:30:47 +02:00
Tom Rini
982aac5754 net: Tighten some network driver dependencies
A large number of network drivers cannot build without access to some
platform specific header files. Express those requirements in Kconfig as
well. This covers the QUICC engine drivers as that is networking
driver infrastructure.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-08-01 09:30:47 +02:00
Tom Rini
5564a4be25 net: Add <cpu_func.h> to some platforms
The common portable header for CPU related functions such as cache
flushing and invalidation is <cpu_func.h> so add that to these drivers.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-08-01 09:30:47 +02:00
Tom Rini
3a5da11ffe drivers/net/ftgmac100.c: Fix a debug print
In the debug print in ftgmac100_send we want to say where the packet is
in memory and what the length is, so use %p to print that.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-08-01 09:30:47 +02:00
Tim Harvey
51eb2bff87 net: lwip: remove eth_init from net_init as it is called later
The call to eth_init within net_init causes the network interface to
start, stop, start again which can cause issues with certain network
device drivers. Remove it to make it behave like the legacy network
path.

Fixes: 5666865dec ("net: lwip: fix initialization sequence before a command")
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
2025-08-01 09:30:47 +02:00
Tim Harvey
bd4de55951 net: lwip: simplify net_lwip_eth_start
For NET_LWIP eth_is_on_demand_init() is always 1 so remove the check and
simplify the code.

Suggested-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
2025-08-01 09:30:47 +02:00
Andrew Goodbody
9104267e67 net: wget: Fix comparison of unsigned variable
content_length is an unsigned long and so testing that it is >= 0 will
always be true. Instead test that it is != -1 as that is the condition
set on error.

This issue found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
2025-08-01 09:30:47 +02:00
Andrew Goodbody
c29c5ed296 net: Incorrect NOP macro used for test
In tcp_parse_options the uchar p[0] is attempted to test for a match
with the 32bit macro TCP_0_NOP which can never be true. Instead test
against the 8bit macro TCP_1_NOP.

This issue found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
2025-08-01 09:30:47 +02:00
Andrew Goodbody
31a8d2d340 net: Add parens to macro PSEUDO_HDR_SIZE
Smatch reports a warning about possibly needing parens around the macro
PSEUDO_HDR_SIZE. This will not affect the one place the macro is used
but add the parens anyway as it is good practice to have them and if the
macro is used again in the future it could possibly matter then.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
2025-08-01 09:30:47 +02:00
Ion Agorria
c55cbaf133 board: samsung: add Samsung Galaxy R (GT-I9103) and Captivate Glide (SGH-i927) support
The Galaxy R (GT-I9103) and Captivate Glide (SGH-i927) are both Tegra 2
based Samsung smartphones released in 2011. They both feature 1 GB of RAM
and 8 GB of expandable flash memory. The key difference is that the
Captivate Glide has an OLED panel (contrary to LCD in Galaxy R) and a
QWERTY keyboard in form factor of a slider.

Signed-off-by: Ion Agorria <ion@agorria.com>
Reviewed-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2025-08-01 08:46:53 +03:00
Ion Agorria
018d3c99b4 video: backlight: add Samsung CMC623 backlight PWM driver
Add support for PWM backlight found in Samsung CMC623 image converter.

Signed-off-by: Ion Agorria <ion@agorria.com>
Reviewed-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2025-08-01 08:46:36 +03:00
Ion Agorria
c2bcd685ec video: bridge: add Samsung CMC623 image converter driver
Add support for a Samsung CMC623 image converter chip found in several
Samsung devices such as Samsung Galaxy R (I9103) and Samsung Galaxy
Tab 10.1 (GT-P75xx).

Signed-off-by: Ion Agorria <ion@agorria.com>
Reviewed-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2025-08-01 08:46:20 +03:00
Ion Agorria
c6ec48a2ba video: panel: add Samsung S6E63M0 panel driver
Samsung S6E63M0 controller is found in some OLED panels like one used in
the Samsung Captivate Glide. Currently only DBI C panel is implemented.

Signed-off-by: Ion Agorria <ion@agorria.com>
Reviewed-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2025-08-01 08:46:02 +03:00
Ion Agorria
649d9c38a8 video: panel: add Sony L4F00430T01 panel driver
Sony L4F00430T01 LCD module is found in Samsung Galaxy R. The panel has a
WVGA resolution (480x800) and is setup over SPI, video data comes from RGB.

Signed-off-by: Ion Agorria <ion@agorria.com>
Reviewed-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2025-08-01 08:44:44 +03:00
Svyatoslav Ryhel
aa291c5f8b video: tegra: parametrize PCLK and DE polarity
Configure pixel clock and data enable polarity according to panel flags.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2025-08-01 08:44:28 +03:00
Svyatoslav Ryhel
d564f395bc board: chagall: add Pegatron Chagall support
The Pegatron Chagall (originally built by Pegatron, but later rebranded by
other vendors under names Fujitsu Stylistic M532, Olivetti Olipad 3,
Siragon 4N, Realpad Bunaken, DNS AirTab P110w / P110g etc) is a mostly
business-oriented tablet sold in 2012 in different variants, mostly in
Europe, with slight differences in storage size (16GB/32GB) and presence
of built-in cellular modem.

Tested-by: Raffaele Tranquillini <raffaele.tranquillini@gmail.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2025-08-01 08:43:41 +03:00
Ion Agorria
0106f051d7 ARM: tegra: Use AES engine for crypto functions
Previously software based AES encryption was used with previously known
device specific keys (SBK), now that we have AES driver we can simply
delegate this to the engine without prior knowledge of the key (assuming
it is still loaded).

Signed-off-by: Ion Agorria <ion@agorria.com>
2025-08-01 08:43:41 +03:00
Ion Agorria
f0fc95e1a5 ARM: tegra: Enable BSEV for devices that use CMD_EBTUPDATE
Enable BSEV for devices that support u-boot self-upgrading feature.

Signed-off-by: Ion Agorria <ion@agorria.com>
2025-08-01 08:43:41 +03:00
Ion Agorria
bbfdb1ea9a ARM: tegra: Add BSE bindings
Add device tree nodes for BSEA and BSEV devices on Tegra20 and Tegra30.

Signed-off-by: Ion Agorria <ion@agorria.com>
2025-08-01 08:43:41 +03:00
Ion Agorria
f230bc6cf7 ARM: tegra: Add LP0 support for ODM production
Now that we have working AES engine driver we can request the warmboot code
to be encrypted and signed  with SBK if the device requires so. This
unlocks LP0 support for most devices in the wild as they use ODM Production
Secure.

We are not aware of any "ODM Production Open" device nor have access to
thus this has not been tested on one, merely added for completeness.

Signed-off-by: Ion Agorria <ion@agorria.com>
2025-08-01 08:43:41 +03:00
Ion Agorria
b01f0a7c1d crypto: tegra: Add Tegra AES engine driver
This driver allows using Tegra AES engines within BSEV and BSEA blocks to
encrypt and decrypt data using different AES algorithms.

One use case is allowing u-boot to self update by using the already loaded
AES key in the engine's SBK slot by the bootrom.

Particular care must be taken as chainloaded u-boot's may not have the SBK
slot loaded as the vendor bootloader erases it before leaving it.

Signed-off-by: Ion Agorria <ion@agorria.com>
2025-08-01 08:43:41 +03:00
Ion Agorria
aaf4c26187 ARM: tegra: Relocate fuse code from warmboot file
Move a set of helpers used in warmboot code to more appropriate AP and FUSE
locations.

Signed-off-by: Ion Agorria <ion@agorria.com>
2025-08-01 08:43:41 +03:00
Tom Rini
f5e968a28e Merge tag 'u-boot-stm32-20250731' of https://source.denx.de/u-boot/custodians/u-boot-stm
CI: https://source.denx.de/u-boot/custodians/u-boot-stm/-/pipelines/27236

- Add support for STM32 TIMERS and STM32 PWM on STM32MP25
- Add STM32MP13xx SPL and OpTee-OS start support
- Fix header misuse in stm32 reset drivers
- Fix STMicroelectronics spelling
- Fix clk-stm32h7 wrong macros used in register read
- Fix PRE_CON_BUF_ADDR on STM32MP13
- Fix clock identifier passed to struct scmi_clk_parent_set_in
- Fix stm32 reset for STM32F4/F7 and H7
- Enable OF_UPSTREAM_BUILD_VENDOR for stm32mp13_defconfig
- Add STM32MP23 SoC and stm32mp235f-dk board support
2025-07-31 10:04:32 -06:00
Tom Rini
eef444c389 Merge tag 'u-boot-socfpga-next-20250731' of https://source.denx.de/u-boot/custodians/u-boot-socfpga
This pull request includes updates for the SoCFPGA platform intended for the 2025.10 release
cycle. The highlights focus on enabling the Power Manager for Agilex5, NAND boot support
enhancements, and various bug fixes and cleanups across SoCFPGA components.

CI:

  * https://source.denx.de/u-boot/custodians/u-boot-socfpga/-/pipelines/27221

Summary of changes:

Agilex5 Power Manager:

  *   Initial driver support and DT bindings are added for the Agilex5 Power Manager, enabling
better power domain control.

NAND Boot Support for Agilex5:

  *   SPL support for NAND boot is enabled.
  *   UBI/UBIFS support is configured in defconfigs.
  *   Memory layout updates (malloc and BSS relocation) ensure proper boot behavior.

Code Quality Improvements:

  *   Coverity and runtime bug fixes (e.g., jtag_usercode check, sub-device conditionals).
  *   Several cleanup patches addressing formatting, logic, and initialization issues.

General Maintenance:

  *   SPDX license tags and header include fixes.
  *   Device tree updates to limit SPI clock frequency and other minor adjustments.

These contributions come from Alif Zakuan Yuslaimi, Andrew Goodbody, Dinesh Maniyam, Naresh
Kumar Ravulapalli, and Tingting Meng.

This patch set has been tested on Agilex 5 devkit.
2025-07-31 08:42:06 -06:00
Tom Rini
79f3e77133 Subtree merge tag 'v6.16-dts' of dts repo [1] into dts/upstream
[1] https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git

Perform a few fixups in our dts* files to match upstream changes.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-30 09:53:54 -06:00
Tom Rini
ecec23fc9a Squashed 'dts/upstream/' changes from fe2d6c49bb4e..d08867ef8f12
d08867ef8f12 Merge tag 'v6.16-dts-raw'
0a3935a7ac7e Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
cdbf9e831b32 Merge tag 'soc-fixes-6.16-3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
bad311fb385a arm64: dts: rockchip: Drop netdev led-triggers on NanoPi R5S
2e218e73258a Merge tag 'sunxi-clk-fixes-for-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-fixes
0d793561b36b Merge tag 'v6.16-rc7-dts-raw'
4afd44a0f9e1 Merge tag 'char-misc-6.16-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc
d4258ca2506f Merge tag 'sunxi-fixes-for-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/fixes
6f58a4a3d85b Merge tag 'soc-fixes-6.16-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
7d36fa2aead7 Merge tag 'v6.16-rc6-dts-raw'
5b4fe5bc4d6c Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
658c2ac70a6b Merge tag 'qcom-arm64-fixes-for-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/fixes
30434c1bbe5b Merge tag 'v6.16-rockchip-dtsfixes1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/fixes
fe1c74e923db Merge tag 'imx-fixes-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixes
fc87372bbb95 Merge tag 'net-6.16-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
95306cebd27f arm64: dts: allwinner: a523: Rename emac0 to gmac0
87991de983b4 dt-bindings: net: sun8i-emac: Rename A523 EMAC0 to GMAC0
660bbdcb1908 arm64: dts: freescale: imx8mm-verdin: Keep LDO5 always on
2a8f1cf921d8 Merge tag 'v6.16-rc5-dts-raw'
7764f9945554 Merge tag 'i2c-for-6.16-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux
f308bc1b45ec Merge tag 'soc-fixes-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
3801555e90ae Merge tag 'input-for-v6.16-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
f6493b7ab2e6 Merge tag 'iio-fixes-for-6.16a' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/jic23/iio into char-misc-linus
06e8c2fc200d Merge tag 'net-6.16-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
c5acde066c90 clk: sunxi-ng: v3s: Fix CSI SCLK clock name
3bfb31865adf Merge tag 'apple-soc-fixes-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/sven/linux into arm/fixes
ee3a6c0c6e28 dt-bindings: net: sophgo,sg2044-dwmac: Drop status from the example
3de3f2c47ebc dt-bindings: i2c: realtek,rtl9301: Fix missing 'reg' constraint
21a8d452d496 arm64: dts: imx95: Correct the DMA interrupter number of pcie0_ep
9767855abcf1 arm64: dts: rockchip: Add missing fan-supply to rk3566-quartz64-a
92b2acaf0da3 arm64: dts: rockchip: use cs-gpios for spi1 on ringneck
647bec67d41e Merge tag 'v6.16-rc4-dts-raw'
3de530f62c29 arm64: dts: add big-endian property back into watchdog node
70aadb6d7760 arm64: dts: imx95-15x15-evk: fix the overshoot issue of NETC
d3b30b770c70 arm64: dts: imx95-19x19-evk: fix the overshoot issue of NETC
87ec6dc7cb55 Merge tag 'tty-6.16-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty
d1c317d2ce13 dt-bindings: iio: gyro: invensense,mpu3050: change irq maxItems
fe8a968606e7 dt-bindings: iio: adc: adi,ad7606: fix dt_schema validation warning
70aa5d0e1460 Merge tag 'devicetree-fixes-for-6.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
30f939ec9d1e dt-bindings: serial: 8250: Make clocks and clock-frequency exclusive
7c401dc8faf7 Merge tag 'v6.16-rc3-dts-raw'
84298fd5232d Merge tag 'i2c-for-6.16-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux
5e306c8e57da dt-bindings: clock: mediatek: Add #reset-cells property for MT8188
9f63f409ab73 arm64: dts: rockchip: list all CPU supplies on ArmSoM Sige5
4e22da9b6577 arm64: dts: imx8mp-venice-gw74xx: fix TPM SPI frequency
d3fb320a33e9 arm64: dts: imx8mp-venice-gw73xx: fix TPM SPI frequency
e31af1649925 arm64: dts: imx8mp-venice-gw72xx: fix TPM SPI frequency
c2aa28307e3a arm64: dts: imx8mp-venice-gw71xx: fix TPM SPI frequency
90a33540cd99 Merge tag 'libnvdimm-fixes-6.16-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/nvdimm/nvdimm
b8ab2abeeac6 dt-bindings: HID: i2c-hid: elan: Introduce Elan eKTH8D18
85773da82c5c Merge tag 'powerpc-6.16-3' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux
cb5c58a1e4b6 Merge tag 'v6.16-rc2-dts-raw'
ac5a2455698d arm64: dts: apple: Move touchbar mipi {address,size}-cells from dtsi to dts
bc677b407179 arm64: dts: apple: Drop {address,size}-cells from SPI NOR
76c8cfce5e1f arm64: dts: apple: t8103: Fix PCIe BCM4377 nodename
f0db656aa694 powerpc: dts: mpc8315erdb: Add GPIO controller node
96311d89661c powerpc/microwatt: Fix model property in device tree
2b4fde2f5082 dt-bindings: i2c: nvidia,tegra20-i2c: Specify the required properties
095eda05803e dt-bindings: serial: Convert altr,uart-1.0 to DT schema
db0e58d2587f dt-bindings: serial: Convert altr,juart-1.0 to DT schema
d2c031826ad8 dt-bindings: pmem: Convert binding to YAML
693df0922817 Merge tag 'v6.16-rc1-dts-raw'
42bf1c74586e arm64: dts: qcom: x1e80100: describe uefi rtc offset
07c8ad44a26d arm64: dts: qcom: sc8280xp-x13s: describe uefi rtc offset
ee54a18d8a5b dt-bindings: soc: fsl,ls1028a-reset: Drop extra "/" in $id
0c4780dea8a9 arm64: dts: rockchip: Add cd-gpios for sdcard detect on Cool Pi 4B
96e8f4d737e7 arm64: dts: rockchip: Add cd-gpios for sdcard detect on Cool Pi CM5
fa6ea8235d1b arm64: dts: rockchip: Adjust the HDMI DDC IO driver strength for rk3588
f1f137de95a6 arm64: dts: rockchip: fix rk3576 pcie1 linux,pci-domain
a4d276ce3997 pinctrl: MAINTAINERS: Drop bouncing Jianlong Huang
f2276a9a3306 Merge tag 'loongarch-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
9b7f7912690b Merge tag 'riscv-for-linus-6.16-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
34a79d8b450a Merge tag 'spi-v6.16-merge-window' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
60656d9d69c7 Merge tag 'pwm/for-6.16-rc1-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/ukleinek/linux
185483e5516d Merge tag 'usb-6.16-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb
82b0ede70e81 Merge tag 'tty-6.16-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty
cf5586288846 Merge tag 'char-misc-6.16-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc
70afb5f7dba1 Merge tag 'mips_6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux
fdbd471f36e9 LoongArch: dts: Add PWM support to Loongson-2K2000
3ced8eecbb60 LoongArch: dts: Add PWM support to Loongson-2K1000
fbe4122cb758 LoongArch: dts: Add PWM support to Loongson-2K0500
ea388cd12b48 dt-bindings: drm/bridge: ti-sn65dsi83: drop $ref to fix lvds-vod* warnings
7103b4c36a4a Merge tag 'riscv-mw2-6.16-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/alexghiti/linux into for-next
9a6b386a2d3e Merge tag 'riscv-mw1-6.16-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/alexghiti/linux into for-next
4e717f475d40 Merge tag 'rtc-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux
08614ae8e2cb Merge tag 'dmaengine-6.16-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine
b8aa7fef75df Merge tag 'phy-for-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy
1b1aad416ff8 Merge tag 'pci-v6.16-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci
aba43883f85b Merge branch 'pci/dt-bindings'
1d90b503befe Merge branch 'pci/controller/qcom'
0db0a94747d9 Merge tag 'leds-next-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/leds
9bf6649192bc Merge tag 'mfd-next-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd
0107bcabb83c Merge tag 'ata-6.16-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/libata/linux
af3695e9189a Merge tag 'hwmon-for-v6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging
2b4267b37eda Merge tag 'hyperv-next-signed-20250602' of git://git.kernel.org/pub/scm/linux/kernel/git/hyperv/linux
fed506f23c59 Merge tag 'input-for-v6.16-rc0' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
26c047f1d621 Merge tag 'mtd/for-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux
509d8a0be181 Merge tag 'rproc-v6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/remoteproc/linux
213c5dbadd23 Merge tag 'mailbox-v6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/jassibrar/mailbox
77b1744dd134 Merge tag 'nand/for-6.16' into mtd/next
69598f8cf6f4 dt-bindings: pwm: adi,axi-pwmgen: Fix clocks
418d565e162f dt-bindings: rtc: rzn1: add optional second clock
7e286e009f74 Merge tag 'linux-watchdog-6.16-rc1' of git://www.linux-watchdog.org/linux-watchdog
e54e07e995ad Merge tag 'i3c/for-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/i3c/linux
b77068b989d1 Merge tag 'for-linus' of https://github.com/openrisc/linux
538862aba33e dt-bindings: watchdog: renesas,wdt: Document RZ/V2N (R9A09G056) support
a8ad8f16aa05 dt-bindings: watchdog: samsung-wdt: Add exynos990-wdt compatible
51eb468dec31 Merge tag 'mm-nonmm-stable-2025-05-31-15-28' of git://git.kernel.org/pub/scm/linux/kernel/git/akpm/mm
07ddd9da3372 Merge tag 'soc-newsoc-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
d9e9df4c73ea Merge tag 'soc-dt-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
e32b012ba92c Merge tag 'soc-arm-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
8229dffd6155 Merge tag 'soc-drivers-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
92ddbc7b281f Merge tag 'iommu-updates-v6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/iommu/linux
60fccc768ca3 Merge tag 'i2c-for-6.16-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux
de3468345344 Merge tag 'pinctrl-v6.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
64d64658bb1d Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
2feab0192b3d Merge tag 'renesas-dts-for-v6.16-tag5' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
d2e6c3b1a961 Merge tag 'scsi-misc' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi
799cac52d435 Merge tag 'devicetree-for-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
7bb3a108ef22 dt-bindings: mailbox: qcom,apcs: Add separate node for clock-controller
939cb0c4baa1 Merge branches 'clk-amlogic', 'clk-allwinner', 'clk-rockchip' and 'clk-qcom' into clk-next
1142409d3ba1 Merge branches 'clk-socfpga', 'clk-sophgo', 'clk-thead' and 'clk-samsung' into clk-next
baaeae2a216c Merge branches 'clk-bindings', 'clk-renesas', 'clk-spacemit' and 'clk-cleanup' into clk-next
ce2790c97a29 Merge tag 'net-next-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next
b7b077d37b30 Merge tag 'drm-next-2025-05-28' of https://gitlab.freedesktop.org/drm/kernel
9671e900d11e Merge tag 'media/v6.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media
ceab2a443756 dt-bindings: timer: Add fsl,vf610-pit.yaml
797ede01deb9 dt-bindings: gpu: mali-bifrost: Add compatible for RZ/G3E SoC
9e6cc5046d38 ASoC: dt-bindings: qcom,sm8250: Add Fairphone 5 sound card
c0d1d4762e35 dt-bindings: net: dsa: mediatek,mt7530: Add airoha,an7583-switch
85d3dd3767d7 Merge tag 'thermal-6.16-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
608dc836c43c Merge tag 'mmc-v6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc
e709800437f0 Merge tag 'pmdomain-v6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/linux-pm
2fed8c22fca0 Merge tag 'for-v6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/sre/linux-power-supply
841871381e3f Merge tag 'spi-v6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
82e042806351 Merge tag 'regulator-v6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator
6cd98d149a4e Merge tag 'gpio-updates-for-v6.16-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux
c56d7645f65d Merge tag 'sound-6.16-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound
531f5a82239b Merge tag 'pwm/for-6.16-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/ukleinek/linux
c5c642e59f80 dt-bindings: arm/cpus: Allow 2 power-domains entries
1f34e1ba0664 dt-bindings: usb: dwc3-xilinx: allow dma-coherent
7fe9ca816df0 media: dt-bindings: sony,imx219: Allow props from video-interface-devices
23e1a9da2b61 dt-bindings: soundwire: qcom: Document v2.1.0 version of IP block
dc18bda804b0 dt-bindings: watchdog: fsl-imx-wdt: add compatible string fsl,ls1021a-wdt
39e0723837f5 dt-bindings: pinctrl: amlogic,pinctrl-a4: Add missing constraint on allowed 'group' node properties
52320e279b5f Merge tag 'timers-clocksource-2025-05-25' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
4ac72745a3ba Merge tag 'irq-msi-2025-05-25' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
eabba266a125 Merge tag 'irq-drivers-2025-05-25' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
cfeb2af0f1dc spi: dt-bindings: spi-sg2044-nor: Add SOPHGO SG2042
3fe54a460693 dt-bindings: mailbox: qcom: Add the SM7150 APCS compatible
d48dd7367ff4 dt-bindings: mailbox: add Sophgo CV18XX series SoC
7205fdc68aac Merge tag 'v6.16-p1' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6
78be8e64e1d5 Merge tag 'linux-can-next-for-6.16-20250522' of git://git.kernel.org/pub/scm/linux/kernel/git/mkl/linux-can-next
c268694ae6c1 dt-bindings: net: airoha: Add EN7581 memory-region property
4f5aa39b37b3 arm64: dts: renesas: rzg3e-smarc-som: Reduce I2C2 clock frequency
b33d0aa6f5f2 dt-bindings: rtc: add schema for NXP S32G2/S32G3 SoCs
a11101f2861b dt-bindings: at91rm9260-rtt: add microchip,sama7d65-rtt
0868d96a7d71 dt-bindings: rtc: at91rm9200: add microchip,sama7d65-rtc
32d48c35b490 dt-bindings: rtc: qcom-pm8xxx: add uefi-variable offset
538b161c06d8 dt-bindings: i3c: silvaco,i3c-master: add i.MX94 and i.MX95 I3C
8d0721592b6a dt-bindings: watchdog: Add rk3562 compatible
7e2f745f8729 dt-bindings: watchdog: fsl,scu-wdt: Document imx8qm
46093162d96a dt-bindings: watchdog: Add NXP Software Watchdog Timer
b2ba88747136 Merge tag 'asoc-v6.16-2' of https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into for-next
277fcfcc8dce dt-bindings: microsoft,vmbus: Add interrupt and DMA coherence properties
93eb157cdee2 ASoC: codecs: add support for ES8375
62137585c9f1 Merge tag 'i2c-host-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/andi.shyti/linux into i2c/for-mergewindow
07176cad5d48 Merge branches 'fixes', 'apple/dart', 'arm/smmu/updates', 'arm/smmu/bindings', 'fsl/pamu', 'mediatek', 'renesas/ipmmu', 's390', 'intel/vt-d', 'amd/amd-vi' and 'core' into next
e17bfdf2bd3d ASoC: dt-bindings: Add Everest ES8375 audio CODEC
b8f581eae5d9 dt-bindings: i2c: i2c-wmt: Convert to YAML
89a9fc8a198e dt-bindings: mfd: syscon: Add mediatek,mt8365-infracfg-nao
cf5bbfd397e6 dt-bindings: mfd: Correct indentation and style in DTS example
563f0fcfdb0f dt-bindings: mfd: Drop unrelated nodes from DTS example
1edb48c66ec4 dt-bindings: mfd: syscon: Add qcom,apq8064-sps-sic
9b2ea6c9e8cb dt-bindings: mfd: syscon: Add qcom,apq8064-mmss-sfpb
29ee27ad1c0a dt-bindings: mfd: syscon: Add mt7988-topmisc
c75d8d1f7422 dt-bindings: mfd: mediatek,mt8195-scpsys: Add support for MT6893
37027ad45e6d dt-bindings: mfd: samsung,s2mps11: add s2mpg10
0a34ed586984 dt-bindings: mfd: syscon: Add microchip,sama7d65-secumod
903f759ee35d dt-bindings: mfd: syscon: atmel,sama5d2-secumod: Convert to yaml
be643f887bf8 dt-bindings: mfd: atmel: Add microchip,sama7d65-gpbr
d35666a54bce dt-bindings: mmc: sdhci-of-dwcmhsc: Allow use of a power-domain
9c4b88c5a89e Merge tag 'wireless-next-2025-05-22' of https://git.kernel.org/pub/scm/linux/kernel/git/wireless/wireless-next
1b4f682e3ad4 Merge tag 'for-net-next-2025-05-22' of git://git.kernel.org/pub/scm/linux/kernel/git/bluetooth/bluetooth-next
b21424815167 Merge tag 'asoc-v6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into for-next
dd6fc25d89c7 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
88b634bfddd2 Merge tag 'icc-6.16-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/djakov/icc into char-misc-next
635c310eb96e Merge tag 'coresight-next-v6.16' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/coresight/linux into char-misc-next
c9cd65d9ea51 Merge branches 'ib-firmware-mfd-6.16', 'ib-mfd-clocksource-pwm-6.16', 'ib-mfd-gpio-nvmem-6.16', 'ib-mfd-regulator-6.16' and 'ib-mfd-regulator-6.16-1' into ibs-for-mfd-merged
2c559dd38fb0 Merge tag 'iio-for-6.16a-take2' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/jic23/iio into char-misc-next
89c022fde09d Add Tegra264 support in AHUB drivers
ad5d21e87116 dt-bindings: display: rockchip: Convert cdn-dp-rockchip.txt to yaml
e34c1605234f Merge tag 'davinci-updates-for-v6.16-rc1' of https://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux into soc/arm
ca95dc05b5bb Merge tag 'juno-updates-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into soc/dt
9bab5690961c dt-bindings: ASoC: Document Tegra264 APE support
3fac990c1607 dt-bindings: ASoC: admaif: Add missing properties
2ff27434f054 dt-bindings: mfd: brcm,bcm59056: Add compatible for BCM59054
d2bb71f7f921 dt-bindings: mfd: brcm,bcm59056: Convert to YAML
508b29e71313 ASoC: dt-bindings: audio-graph-card2: reference audio-graph routing property
026c9a82d4d6 dt-bindings: leds: Add Texas Instruments TPS6131x flash LED driver
5aab6ddffa44 dt-bindings: net: Document support for Aeonsemi PHYs
c66ed7b8b5f8 Merge tag 'qcom-arm64-for-6.16-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
2c15df445738 Merge tag 'qcom-arm32-for-6.16-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
7d52cefecf33 Merge tag 'mtk-dts64-for-v6.16-2' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/dt
c3be03f1576b Merge tag 'v6.16-rockchip-dts32-2' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
151e84ca25b1 Merge tag 'v6.16-rockchip-dts64-3' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
fd61f1d659e9 Merge tag 'v6.16-rockchip-dts64-2' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
69ecc61139f5 Merge tag 'mvebu-dt64-6.16-1' of https://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into soc/dt
755e06a92789 Merge tag 'renesas-dts-for-v6.16-tag4' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
03424c08167f Merge tag 'renesas-dts-for-v6.16-tag3' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
224238999a2c Merge tag 'riscv-dt-for-v6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt
ef9c1679cc0a Merge tag 'microchip-dt64-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into soc/dt
45f7c4fc1a32 Merge tag 'at91-dt-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into soc/dt
2f4d88f59336 Merge tag 'sunxi-dt-for-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into soc/dt
5ce4d3de1bab Merge tag 'stm32-dt-for-v6.16-1' of https://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into soc/dt
d89aa840ef5d Merge tag 'spacemit-dt-for-6.16-1' of https://github.com/spacemit-com/linux into soc/dt
43d0dd81da74 Merge tag 'qcom-arm32-for-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
325cd9e9946a Merge tag 'dt-vt8500-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt into soc/dt
09c407adcd2c Merge tag 'qcom-arm64-for-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
9fc38b83cdf5 Merge tag 'nuvoton-arm-6.16-devicetree' of https://git.kernel.org/pub/scm/linux/kernel/git/joel/bmc into soc/dt
c83799c8dd90 Merge tag 'qcom-drivers-for-6.16-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers
e0314147cea5 Merge tag 'riscv-cache-for-v6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/drivers
b1f49e53cf77 Merge tag 'samsung-drivers-6.16-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/drivers
3b55c18b3508 arm64: dts: nuvoton: Add pinctrl
deb09c527dc0 dt-bindings: spi: samsung: add exynosautov920-spi compatible
66dd7fd01067 mailmap: update and consolidate Casey Connolly's name and email
a0fb0d3f5f30 Merge tag 'riscv-sophgo-soc-for-v6.16' of https://github.com/sophgo/linux into soc/drivers
4160f8827e4d Merge tag 'qcom-drivers-for-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers
bb77a5a73912 Merge tag 'soc-drivers-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt into soc/drivers
8707811d045c Merge tag 'amlogic-driver-for-v6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux into soc/drivers
1e7fa6c4dbaa Merge tag 'dt64-cleanup-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt into soc/dt
e2e43e44fc51 Merge tag 'amlogic-arm64-dt-for-v6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux into soc/dt
73195a6e0c5c Merge tag 'amlogic-arm-dt-for-v6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux into soc/dt
38aa5a686d0e Merge tag 'samsung-dt64-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt
5d33e21e66f0 Merge tag 'reset-for-v6.16' of git://git.pengutronix.de/pza/linux into soc/drivers
3e9d465085a9 ARM: dts: samsung: sp5v210-aries: Align wifi node name with bindings
0b927692a7bd Merge tag 'ti-k3-dt-for-v6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into soc/dt
0d52eb1cf5e4 arm64: dts: blaize-blzp1600: Enable GPIO support
da83afa6eb07 Merge tag 'thead-dt-for-v6.16' of https://github.com/pdp7/linux into soc/dt
4acee1d7632f dt-bindings: clock: socfpga: convert to yaml
e950e3eb3a33 dt-bindings: gpio: vf610: add ngpios and gpio-reserved-ranges
6f5a37dc8f30 ASoC: dt-bindings: audio-graph-card2: add missing mic-det-gpios
c04f34769343 dt-bindings: net: bluetooth: nxp: Add support for host-wakeup
541687515c1a dt-bindings: iio: adc: Add ROHM BD79100G
bb454172d88f dt-bindings: iio: adc: add NCT7201 ADCs
2d2b2b5c0772 dt-bindings: trivial-devices: Document SEN0322
8bec7a21e263 dt-bindings: iio: adc: mcp3911: add reset-gpios
ca406ea016be dt-bindings: iio: dac: Add adi,ad3530r.yaml
5fe995b1dd53 dt-bindings: iio: adc: Add compatible for Dimensity 1200 MT6893
1edc97a95aa5 dt-bindings: iio: dac: ad7293: add vrefin support
082ad88205a7 dt-bindings: Add device tree support for Winsen MHZ19B CO2 sensor
85963b0bd856 dt-bindings: Add Winsen to the vendor prefixes
c046c1cfd311 dt-bindings: spmi: Add Apple SPMI controller
92648c8bb3a5 dt-bindings: can: renesas,rcar-canfd: Document RZ/G3E support
a315f55a2a76 dt-bindings: can: renesas,rcar-canfd: Simplify the conditional schema
cf60fa765e1b dt-bindings: spmi: Add Apple SPMI NVMEM
2e56f235875c Merge tag 'mux-drv-6.16' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/krzk/linux into char-misc-next
41d62a413c79 dt-bindings: serial: 8250_omap: Drop redundant properties
6266de5456c9 dt-bindings: serial: Convert socionext,milbeaut-usio-uart to DT schema
b1248495c539 dt-bindings: serial: Convert microchip,pic32mzda-uart to DT schema
7a584be8cc34 dt-bindings: serial: Convert arm,sbsa-uart to DT schema
7faba0d1c0e1 dt-bindings: serial: Convert snps,arc-uart to DT schema
5d9cace6931e dt-bindings: serial: Convert marvell,armada-3700-uart to DT schema
b11585afcde7 dt-bindings: serial: Convert lantiq,asc to DT schema
2ee62910d9da dt-bindings: serial: Convert cirrus,ep7209-uart to DT schema
076f1b9065fd dt-bindings: serial: Convert arm,mps2-uart to DT schema
0f5b4990e744 dt-bindings: serial: Convert nxp,lpc3220-hsuart to DT schema
4604628e13ff dt-bindings: serial: Convert cnxt,cx92755-usart to DT schema
1be5ca8fbeae dt-bindings: serial: atmel,at91-usart: add microchip,sama7d65-usart
75cc729209d8 dt-bindings: usb: ti,usb8041: Add binding for TI USB8044 hub controller
c8b951038c12 dt-bindings: usb: samsung,exynos-dwc3: add dt-schema ExynosAutov920
214f164d27c6 dt-bindings: usb: Add Parade PS8833 Type-C retimer variant
8ec32a7db2e9 scsi: ufs: qcom: dt-bindings: Document the SM8750 UFS Controller
69025409db1d dt-bindings: display: bridge: renesas,dsi: allow properties from dsi-controller
486cad5cf1af dt-bindings: trivial-devices: Add VZ89TE to trivial
b0b6d2e9f637 arm64: dts: rockchip: move rk3562 pinctrl node outside the soc node
d6d0b4dfd181 arm64: dts: rockchip: fix rk3562 pcie unit addresses
95d9d7ed4bf1 arm64: dts: rockchip: move rk3528 pinctrl node outside the soc node
1bb1fbbea578 arm64: dts: rockchip: remove a double-empty line from rk3576 core dtsi
f0317857788b arm64: dts: rockchip: move rk3576 pinctrl node outside the soc node
83e4382f7a80 arm64: dts: rockchip: fix rk3576 pcie unit addresses
c4d3574fd109 arm64: dts: rockchip: Drop assigned-clock* from cpu nodes on rk3588
57e8cb7db7e9 arm64: dts: rockchip: Add missing SFC power-domains to rk3576
b6cea1360aa8 spi: dt-bindings: Add rk3528-spi compatible
34e62490c1c3 Revert "arm64: dts: mediatek: mt8390-genio-common: Add firmware-name for scp0"
23224a425b5f arm64: dts: mediatek: mt8188: Address binding warnings for MDP3 nodes
161f225efa42 arm64: dts: mt6359: Rename RTC node to match binding expectations
887334da0795 arm64: dts: mt8365-evk: Add goodix touchscreen support
6acb2267910a arm64: dts: mediatek: mt8188: Add missing #reset-cells property
4792760f558d arm64: dts: airoha: en7581: Add PCIe nodes to EN7581 SoC evaluation board
b6d6f3110d36 arm64: dts: airoha: en7581: Add gpio-ranges property for gpio controller
572c9e06138f arm64: dts: mediatek: mt7988a-bpi-r4: configure spi-nodes
1b9defdec732 arm64: dts: mediatek: mt7988a-bpi-r4: Add fan and coolingmaps
5269d9f97b76 arm64: dts: mediatek: mt7988: add phy calibration efuse subnodes
de8fba00158e arm64: dts: mediatek: mt7988: move uart0 and spi1 pins to soc dtsi
2046f03225a8 arm64: dts: mediatek: mt7988: add spi controllers
190bdc8a1f3d arm64: dts: mediatek: mt7988a-bpi-r4: enable xsphy
7a7fefa74dda arm64: dts: mediatek: mt7988: Add xsphy for ssusb0/pcie2
748391bdc918 arm64: dts: mediatek: mt7988a-bpi-r4: allow hw variants of bpi-r4
9bd2134f30ff dt-bindings: arm: mediatek: add bpi-r4 2g5 phy variant
6fb595f7e057 Add sound card support for QCS9100 and QCS9075
0cac869da752 arm64: dts: renesas: white-hawk-ard-audio: Fix TPU0 groups
114fba940bdd mips: dts: Add EcoNet DTS with EN751221 and SmartFiber XP8421-B board
30d15ab14519 dt-bindings: vendor-prefixes: Add SmartFiber
824fd090ff69 dt-bindings: mips: Add EcoNet platform binding
d5b777cdf13c mips: dts: pic32: pic32mzda: Rename the sdhci nodename to match with common mmc-controller binding
38f9e24fec25 arm64: dts: qcom: sm4450: Add RPMh power domains support
9b5728807d08 arm64: dts: qcom: x1e80100-lenovo-yoga-slim7x: add retimers, dp altmode support
7e66fc1ced1e arm64: dts: qcom: ipq5424: Enable PCIe PHYs and controllers
6c037567bdce arm64: dts: qcom: ipq5424: Add PCIe PHYs and controller nodes
57668bababda arm64: dts: qcom: sc7280: Mark FastRPC context banks as dma-coherent
3e567e1e43b4 arm64: dts: qcom: sdx75-idp: Enable QPIC BAM & QPIC NAND support
aa2605ef1c0c arm64: dts: qcom: sdx75: Add QPIC NAND support
becd21cdde7d arm64: dts: qcom: sdx75: Add QPIC BAM support
339faffccdd0 arm64: dts: qcom: qcm2290: Add crypto engine
be5a2cb0e4d4 arm64: dts: qcom: x1e80100-vivobook-s15: Add bluetooth
1b9b8c4d0807 arm64: dts: qcom: x1e80100: Add PCIe lane equalization preset properties
d1065386a278 arm64: dts: qcom: qcs615: Fix up UFS clocks
24d341363edf arm64: dts: qcom: sa8775p: Clean up the PSCI PDs
25e8d99a99ac arm64: dts: qcom: msm8996-oneplus: Add SLPI VDD_PX
708f2ebe5562 arm64: dts: qcom: sm6350-pdx213: Wire up USB regulators
ae9cc53d8e50 arm64: dts: qcom: msm8998-yoshino: Add QUSB2PHY VDD supply
a14bc1f54f72 arm64: dts: qcom: msm8998-mtp: Add QUSB2PHY VDD supply
8a32261a7a9d arm64: dts: qcom: msm8998-fxtec: Add QUSB2PHY VDD supply
421e97a3fd6c arm64: dts: qcom: qcs615: Remove disallowed property from AOSS_QMP node
c891929b43f6 arm64: dts: qcom: msm8998: Remove mdss_hdmi_phy phandle argument
e1906f10fb90 arm64: dts: qcom: sdm845: Add specific APPS RSC compatible
57034f8ab737 arm64: dts: qcom: sc7180: Add specific APPS RSC compatible
2b09cf544e89 arm64: dts: qcom: ipq5332-rdp441: Enable PCIe phys and controllers
9e039129755d arm64: dts: qcom: ipq5332: Add PCIe related nodes
f4173e14cb38 arm64: dts: qcom: ipq9574: Add MHI to pcie nodes
f3bc67041b0a arm64: dts: qcom: sar2130p: add display nodes
5c82bf82ae12 arm64: dts: qcom: sdm845-starqltechn: add modem support
20f31a3e411b arm64: dts: qcom: sdm845-starqltechn: add graphics support
eafd56e51f9c arm64: dts: qcom: sdm845-starqltechn: add initial sound support
60ed1a6b1df9 arm64: dts: qcom: qrb2210-rb1: add Bluetooth support
e600d195af05 dt-bindings: i2c: i2c-rk3x: Add compatible string for RK3528
ba298e1880ec dt-bindings: i2c: renesas,riic: Document RZ/V2N (R9A09G056) support
8360480c58d7 dt-bindings: i2c: dw: Add Sophgo SG2044 SoC I2C controller
519a8fc26117 dt-bindings: i2c: dw: merge duplicate compatible entry.
a5b8efc7c924 dt-bindings: i2c: i2c-mt65xx: Add MediaTek Dimensity 1200 MT6893
c7e668fbc28e dt-bindings: net: wireless: ath12k: describe firmware-name property
c315c2d590f0 dt-bindings: timer: renesas,tpu: remove binding documentation
2e0c91fb13ae Merge branch 'icc-sa8775p' into icc-next
fb0b120a1a93 dt-bindings: mmc: spacemit,sdhci: add support for K1 SoC
46ff3a1b29bc ASoC: dt-bindings: qcom,sm8250: Add QCS9100 and QCS9075 sound card
d1d279316629 dt-binding: mmc: microchip,sdhci-pic32: convert text based binding to json schema
330730b5c105 dt-bindings: crypto: Convert Marvell CESA to DT schema
e2659dcdb3ea dt-bindings: crypto: Convert img,hash-accelerator to DT schema
4dc2e127ef91 dt-bindings: crypto: Convert hisilicon,hip0{6,7}-sec to DT schema
44772d6d4e9b dt-bindings: crypto: Convert brcm,spum-crypto to DT schema
fbb6c9a494af dt-bindings: crypto: Convert axis,artpec6-crypto to DT schema
c017f54c9fff dt-bindings: crypto: Convert amd,ccp-seattle-v1a to DT schema
a5f94755bfb6 dt-bindings: crypto: Drop obsolete mediatek,eip97-crypto
ff768caf62eb dt-bindings: crypto: fsl,sec-v4.0: Add fsl,sec-v6.0
6ecbc066dc7c Merge tag 'drm-msm-next-2025-05-16' of https://gitlab.freedesktop.org/drm/msm into drm-next
9dfb31b362db riscv: dts: sophgo: switch precise compatible for existed clock device for CV18XX
85e7467e1300 riscv: dts: sophgo: Add initial device tree of Sophgo SRD3-10
83177f084b2f dt-bindings: riscv: sophgo: Add SG2044 compatible string
3737ab2125be dt-bindings: interrupt-controller: Add Sophgo SG2044 PLIC
247d63c217bc dt-bindings: interrupt-controller: Add Sophgo SG2044 CLINT mswi
f0df16d747de riscv: dts: sopgho: use SOC_PERIPHERAL_IRQ to calculate interrupt number
809b2feac3f8 riscv: dts: sophgo: rename header file cv18xx.dtsi to cv180x.dtsi
3f8df5f3e748 riscv: dts: sophgo: Move riscv cpu definition to a separate file
2909054d6f9d riscv: dts: sophgo: Move all soc specific device into soc dtsi file
f4cdf8f5f17b riscv: sophgo: dts: Add spi controller for SG2042
c2b7b3a675c7 riscv: dts: sophgo: sg2042: add pinctrl support
d05f1cff48c5 ARM: dts: qcom: apq8064-ifc6410: drop HDMI HPD GPIO
7a6c138888cf arm64: dts: qcom: qcm2290: fix (some) of QUP interconnects
adc6b59b4259 arm64: dts: qcom: sc8280xp-crd: Enable SLPI
ec0bf0004515 arm64: dts: qcom: sc8280xp-lenovo-thinkpad-x13s: enable sensors DSP
0f644dd61ebb arm64: dts: qcom: sc8280xp: Add SLPI
92734dba91d4 arm64: dts: qcom: sc8280xp: Fix node order
2e29d8db414b arm64: dts: qcom: x1e80100: Enable cpufreq
59bd0aec0418 arm64: dts: qcom: x1e80100: Add cpucp mailbox and sram nodes
6528ca226950 arm64: dts: qcom: x1e80100-hp-x14: drop bogus USB retimer
b15ca38a9a5a arm64: dts: qcom: x1e78100-t14s: Enable audio headset support
a187fa6211ad arm64: dts: qcom: x1e78100-t14s: enable SDX62 modem
5eca7d1cfd49 dt-bindings: PCI: microchip,pcie-host: Fix DMA coherency property
50f1a27c303c dt-bindings: timer: renesas,ostm: Document RZ/V2N (R9A09G056) support
8d256f3ddec5 dt-bindings: thermal: qcom-tsens: Add ipq5018 compatible
7be116f73307 dt-bindings: thermal: Add support for Airoha EN7581 thermal sensor
cc1a22604a95 dt-bindings: timer: Convert marvell,armada-370-timer to DT schema
ea4284f3e172 dt-bindings: timer: Convert ti,keystone-timer to DT schema
4f1bf0aa2ecb dt-bindings: timer: Convert st,spear-timer to DT schema
494bc2733ec5 dt-bindings: timer: Convert socionext,milbeaut-timer to DT schema
a2e0a62b5750 dt-bindings: timer: Convert snps,arc-timer to DT schema
46d4eaf6b0dc dt-bindings: timer: Convert snps,archs-rtc to DT schema
935c813b69af dt-bindings: timer: Convert snps,archs-gfrc to DT schema
5f8cc6ccdcfa dt-bindings: timer: Convert lsi,zevio-timer to DT schema
ef36916d6a28 dt-bindings: timer: Convert jcore,pit to DT schema
878db709baf4 dt-bindings: timer: Convert img,pistachio-gptimer to DT schema
c032acacb214 dt-bindings: timer: Convert ezchip,nps400-timer to DT schema
1b65ea760f37 dt-bindings: timer: Convert cirrus,clps711x-timer to DT schema
f460f99b561c dt-bindings: timer: Convert altr,timer-1.0 to DT schema
e5d2349b1506 dt-bindings: timer: Add ESWIN EIC7700 CLINT
440820d62a31 dt-bindings: timer: Add EcoNet EN751221 "HPT" CPU Timer
bf84d1e94975 dt-bindings: timer: Convert arm,mps2-timer to DT schema
bcc8b8e14160 dt-bindings: timer: Add Sophgo SG2044 ACLINT timer
93db5ef1eaf2 dt-bindings: timer: Convert cnxt,cx92755-timer to DT schema
9460d854813b dt-bindings: timer: Convert csky,gx6605s-timer to DT schema
28a94c60f1d9 dt-bindings: timer: Convert csky,mptimer to DT schema
c9ae39b1b998 dt-bindings: timer: Convert marvell,orion-timer to DT schema
c0c401e88d14 dt-bindings: timer: Convert fsl,gtm to YAML
96d7ce4f7338 dt-bindings: timer: Add NXP System Timer Module
67b135f96793 Merge branch 'for-linus' into for-next
737898027ddf ARM: dts: microchip: sama7g54_curiosity: Add fixed-partitions for spi-nor flash
c86ffc0d331c ARM: dts: microchip: sama7d65: Add RTT timer to curiosity board
cb9109d2f17f ARM: dts: microchip: sama7d65: Add RTT and GPBR Support for sama7d65 SoC
cb1ae1d11442 ARM: dts: microchip: sama7d65: Add SRAM and DRAM components support
a5bda086b593 ARM: dts: microchip: sama7d65_curiosity: add EEPROM
621ce651bf39 ARM: dts: microchip: sama7d65: Add MCP16502 to sama7d65 curiosity
30bf5da5dd65 ARM: dts: microchip: sama7d65: Enable GMAC interface
00eda56f3bad ARM: dts: microchip: sama7d65: Add FLEXCOMs to sama7d65 SoC
cd6e1758eecc ARM: dts: microchip: sama7d65: Add gmac interfaces for sama7d65 SoC
5e46b349a198 Merge tag 'v6.15-rc6' into next
12821e764fcc Merge tag 'mediatek-drm-next-20250515' of https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux into drm-next
f21637ac3d69 riscv: dts: starfive: jh7110-common: bootph-pre-ram hinting needed by boot loader
382ce3ced12b riscv: dts: starfive: jh7110-common: add eeprom node to i2c5
e5e233a1b36f riscv: dts: starfive: jh7110-common: qspi flash setting read-delay 2 cycles max 100MHz
796fcc4bd000 riscv: dts: starfive: jh7110-common: add CPU BUS PERH QSPI clocks to syscrg
3a25610392e1 riscv: dts: starfive: jh7110-common: use macros for MMC0 pins
8d3efdc1a649 riscv: dts: starfive: fml13v01: enable USB 3.0 port
23fae8676f65 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
0cf0323d1114 arm64: dts: rockchip: Improve LED config for NanoPi R5S
e3bece005d7b arm64: dts: rockchip: add px30-pp1516 base dtsi and board variants
6a9591a44535 dt-bindings: arm: rockchip: add PX30-PP1516 boards from Theobroma Systems
3e6efd7e76f8 arm64: dts: rockchip: add px30-cobra base dtsi and board variants
b42058e5589c dt-bindings: arm: rockchip: add PX30-Cobra boards from Theobroma Systems
76d0d8e00c9a arm64: dts: rockchip: move reset to dedicated eth-phy node on ringneck
cb54a264ecdb arm64: dts: rockchip: add basic mdio node to px30
0a0ebebfdd45 arm64: dts: rockchip: disable unrouted USB controllers and PHY on RK3399 Puma with Haikou
97640da1f41d arm64: dts: rockchip: disable unrouted USB controllers and PHY on RK3399 Puma
0fe42d171081 arm64: dts: rockchip: fix internal USB hub instability on RK3399 Puma
53aacaed0ad1 dt-bindings: usb: cypress,hx3: Add support for all variants
17b25bb5d028 dt-bindings: ata: Convert arasan,cf-spear1340 to DT schema
a942b710d148 dt-bindings: ata: Convert marvell,orion-sata to DT schema
2b89ce177fad dt-bindings: ata: Convert cavium,ebt3000-compact-flash to DT schema
7452325fd0c4 dt-bindings: ata: Convert apm,xgene-ahci to DT schema
5c3af2fd178e dt-bindings: ata: Convert st,ahci to DT schema
0ed8fb4eda2a ARM: dts: rockchip: add rk3036 usb2phy nodes and enable them on kylin
76b476eca710 arm64: dts: rockchip: move rk3528 i2c+uart aliases to board files
19b80e137230 dt-bindings: Document Tegra264 HDA Support
ea2c684c09e7 dt-bindings: Update Tegra194 and Tegra234 HDA bindings
c1909afcb360 ASoC: codecs: add support for ES8389
8426194407bf spi: dt-bindings: tegra: Document IOMMU property for Tegra234 QSPI
62ad37f8f2ed dt-bindings: net: snps,dwmac: Align mdio node in example with bindings
ef92e3eda5a9 media: dt-bindings: renesas,vsp1: add top-level constraints
95ec73c1eddb media: dt-bindings: renesas,fcp: add top-level constraints
b0b60170175f arm64: dts: qcom: x1e80100-hp-elitebook-ultra-g1q: DT for HP EliteBook Ultra G1q
c7583d9b7c0c dt-bindings: arm: qcom: Document HP EliteBook Ultra G1q
76902454839f arm64: dts: qcom: x1e80100-hp-omnibook-x14: add sound label
a955543d1653 arm64: dts: qcom: sm8650: add the missing l2 cache node
cc5e19202270 ARM: dts: qcom: apq8064: link LVDS clocks
da97b5b4917b arm64: dts: qcom: x1e001de-devkit: Enable support for both Type-A USB ports
d45699c17e6e arm64: dts: qcom: Add industrial mezzanine support for qcs6490-rb3gen2
9b7d10ecf824 arm64: dts: qcom: x1e80100-hp-omnibook-x14: Enable SMB2360 0 and 1
0f8fa5904528 ARM: dts: qcom-msm8960: add missing clocks to the timer node
5f6bbd1d3884 arm64: dts: qcom: ipq5018: enable the download mode support
0bf354f3bdd0 dt-bindings: mfd: qcom,tcsr: Add compatible for ipq5018
6f60724b4f2e arm64: dts: qcom: msm8998-lenovo-miix-630: add Venus node
78729fd6dfe3 arm64: dts: qcom: ipq5018: Enable PCIe
d2aedac00e9c arm64: dts: qcom: ipq5018: Add PCIe related nodes
559cb4221c84 arm64: dts: qcom: sm8350: Fix typo in pil_camera_mem node
94419a80d052 arm64: dts: qcom: x1e80100-romulus: Enable DP over Type-C
f44415787e7f dt-bindings: cache: add QiLai compatible to ax45mp
08e9a9a39b30 ARM: dts: davinci: da850-evm: Increase fifo threshold
ad280853f61b dt-bindings: gpio: tegra186: Add gpio-ranges
7b998eb79596 dt-bindings: mmc: vt8500-sdmmc: Convert to YAML
d5a8ccb27d8c dt-bindings: mmc: sdhci-msm: Add the SM7150 compatible
fd1a8c37a25c dt-bindings: mmc: fsl,esdhc: add compatible string fsl,ls1021a-esdhc
77ecc38be615 dt-bindings: mmc: mtk-sd: Add support for Dimensity 1200 MT6893
2c24ea1a68a1 dt-bindings: mmc: sdhci-of-dwcmhsc: Add Sophgo SG2044 support
2b3a0861f554 dt-bindings: mmc: arasan,sdhci: Add Renesas RZ/N1D
03a4c81a9ab7 dt-bindings: mmc: renesas,sdhi: Document RZ/V2N support
52e04e847a22 dt-bindings: mmc: marvell,xenon-sdhci: Drop requiring 2 clocks
163995fb1db9 dt-bindings: mmc: marvell,xenon-sdhci: Add reference to sdhci-common.yaml
50c1b5b51bd9 dt-bindings: mmc: marvell,xenon-sdhci: Allow "dma-coherent" and "iommus"
6b9ef3e93796 dt-bindings: mmc: Remove redundant sdhci.txt
ea090fe3f0ba arm64: dts: renesas: r9a09g057: Add DMAC nodes
2dc3ede3ee99 dt-bindings: dma: rz-dmac: Document RZ/V2H(P) family of SoCs
f17786beeb4b dt-bindings: dma: rz-dmac: Restrict properties for RZ/A1H
4062957c0797 arm64: dts: allwinner: a100: add Liontron H-A133L board support
6cd646345b08 dt-bindings: Document Tegra264 ADMA support
c751179c1fed ASoC: dt-bindings: mediatek: Simplify mediatek,clk-provider
d133a86545cd regulator: dt-bindings: mt6357: Drop fixed compatible requirement
465ea6ad77e4 riscv: dts: renesas: Add specific RZ/Five cache compatible
40fb609df22a dt-bindings: phy: rockchip,inno-usb2phy: add rk3562
3a0a0b51136f dt-bindings: phy: rockchip,inno-usb2phy: add rk3036 compatible
8ee5033b766d dt-bindings: phy: renesas,usb2-phy: Document RZ/V2H(P) SoC
9b528f755a22 dt-bindings: phy: renesas,usb2-phy: Add clock constraint for RZ/G2L family
d24fabd489af dt-bindings: phy: samsung,usb3-drd-phy: add exynos2200 support
9fdcbbd17f0c dt-bindings: phy: add exynos2200 eusb2 phy support
3529480b0e97 dt-bindings: phy: rockchip: Convert RK3399 PCIe PHY to schema
40cec851b166 dt-bindings: phy: imx8mq-usb: add imx95 tuning support
7fff9434c126 dt-bindings: phy: imx8mq-usb: fix fsl,phy-tx-vboost-level-microvolt property
ee3f5c78f48f ASoC: dt-bindings: Add Everest ES8389 audio CODEC
00b2fda0a367 dt-bindings: phy: mediatek,tphy: Add support for MT6893
65a55e49f6ac dt-bindings: phy: mediatek,dsi-phy: Add support for MT6893
276d6f9a15b2 ARM: dts: stm32: add initial support for stm32mp157-ultra-fly-sbc board
57ea261308f9 dt-bindings: arm: stm32: Document Ultratronik's Fly board DT binding
44704b414013 dt-bindings: vendor-prefixes: Add Ultratronik
1595ef915c5e arm64: dts: st: use lptimer3 as tick broadcast source on stm32mp257f-ev1
f0c546bfa99d arm64: dts: st: add low-power timer nodes on stm32mp251
1ffad119ccb4 arm64: dts: st: Add SPI NOR flash support on stm32mp257f-ev1 board
12747b4ee44b arm64: dts: st: Add ospi port1 pinctrl entries in stm32mp25-pinctrl.dtsi
02caa1aece88 arm64: dts: st: Add OMM node on stm32mp251
19c508dc3d58 ARM: dts: stm32: support STM32h747i-disco board
9d5ec2c9c5d5 ARM: dts: stm32: add an extra pin map for USART1 on stm32h743
59621a6472cd ARM: dts: stm32: add pin map for UART8 controller on stm32h743
8fe35c381c7c ARM: dts: stm32: add uart8 node for stm32h743 MCU
aae9a0192918 dt-bindings: clock: stm32h7: rename USART{7,8}_CK to UART{7,8}_CK
06f64674b332 dt-bindings: arm: stm32: add compatible for stm32h747i-disco board
9a72c83f2e67 ARM: dts: stm32h7-pinctrl: add _a suffix to u[s]art_pins phandles
f907d6456095 ARM: dts: st: stm32: Align wifi node name with bindings
11b819c7a67a ARM: dts: stm32: add low power timer on STM32F746
9c62520ce1f6 ARM: dts: stm32: add vrefint support to adc on stm32mp13
1f4bfaf76020 ARM: dts: stm32: add vrefint calibration on stm32mp13
24225621dc54 dt-bindings: phy: rockchip: Convert RK3399 Type-C PHY to schema
a74d58d14616 dt-bindings: phy: cadence-torrent: enable PHY_TYPE_USXGMII
0cdc2d006c41 dt-bindings: phy: mtk-xs-phy: support type switch by pericfg
54599aec7dc4 dt-bindings: phy: mtk-xs-phy: Add mt7988 compatible
bc3951af24ec dt-bindings: ata: Convert ti,dm816-ahci to DT schema
c52df73fb82d riscv: dts: spacemit: add gpio LED for system heartbeat
9ea19a5fd9a0 riscv: dts: spacemit: add gpio support for K1 SoC
99f3d360eac3 riscv: dts: spacemit: Acquire clocks for UART
4a6e0a0058b8 riscv: dts: spacemit: Acquire clocks for pinctrl
76ca3d9c3343 riscv: dts: spacemit: Add clock tree for SpacemiT K1
c439ada53241 dt-bindings: trivial-devices: Add Maxim max30208
094f9976968a dt-bindings: soc: fsl,qman-fqd: Fix reserved-memory.yaml reference
7346cb46c9cc dt-bindings: interrupt-controller: Convert ti,omap-intc-irq to DT schema
1a3c8332700b dt-bindings: interrupt-controller: Convert ti,omap4-wugen-mpu to DT schema
16a954b6f7cd dt-bindings: interrupt-controller: Convert ti,keystone-irq to DT schema
f140b56fbd3c dt-bindings: interrupt-controller: Convert technologic,ts4800-irqc to DT schema
a36fcbda86fe dt-bindings: interrupt-controller: Convert st,spear3xx-shirq to DT schema
fca0cfe246ea dt-bindings: interrupt-controller: Convert snps,dw-apb-ictl to DT schema
a129aba3d807 dt-bindings: interrupt-controller: Convert snps,archs-intc to DT schema
3c46f013a4cb dt-bindings: interrupt-controller: Convert snps,archs-idu-intc to DT schema
6d2c252561ae dt-bindings: interrupt-controller: Convert snps,arc700-intc to DT schema
4bd22a347e0c dt-bindings: interrupt-controller: Convert qca,ar7100-misc-intc to DT schema
758a06785fa1 dt-bindings: interrupt-controller: Convert qca,ar7100-cpu-intc to DT schema
e8586aed8d6c dt-bindings: interrupt-controller: Convert marvell,odmi-controller to DT schema
cd31b6552214 dt-bindings: interrupt-controller: Convert marvell,cp110-icu to DT schema
486280047d47 dt-bindings: interrupt-controller: Convert marvell,ap806-sei to DT schema
257773207f9b dt-bindings: interrupt-controller: Convert marvell,ap806-gicp to DT schema
ccf7d0237412 dt-bindings: interrupt-controller: Convert marvell,armada-8k-pic to DT schema
9c0f9b138b59 dt-bindings: interrupt-controller: Convert lsi,zevio-intc to DT schema
6e6f1ad3f4ef dt-bindings: interrupt-controller: Convert jcore,aic to DT schema
68c1ed5d2aae dt-bindings: interrupt-controller: Convert img,pdc-intc to DT schema
ed32c7530696 dt-bindings: interrupt-controller: Convert google,goldfish-pic to DT schema
72cb10cd21c0 dt-bindings: interrupt-controller: Convert ezchip,nps400-ic to DT schema
52170bfc0584 dt-bindings: interrupt-controller: Convert csky,mpintc to DT schema
66d63b28d3a5 dt-bindings: interrupt-controller: Convert csky,apb-intc to DT schema
566f66349efe dt-bindings: interrupt-controller: Convert cirrus,ep7209-intc to DT schema
e1db76de5df2 dt-bindings: interrupt-controller: Convert brcm,bcm6345-l1-intc to DT schema
9f589c30f9b4 dt-bindings: interrupt-controller: Convert arm,nvic to DT schema
73718cb7e2b8 dt-bindings: interrupt-controller: Convert amazon,al-fic to DT schema
b023286f3b16 dt-bindings: interrupt-controller: Convert al,alpine-msix to DT schema
0379a7325124 dt-bindings: interrupt-controller: Convert abilis,tb10x-ictl to DT schema
9dfa70d6da10 dt-bindings: interrupt-controller: Convert microchip,pic32mzda-evic to DT schema
e2c7df57fcc2 dt-bindings: interrupt-controller: Convert chrp,open-pic to DT schema
a5aa7aa29361 dt-bindings: interrupt-controller: Convert cdns,xtensa-{mx,pic} to DT schema
8c61a1524b88 dt-bindings: interrupt-controller: Convert ti,cp-intc to DT schema
fd1686389af0 dt-bindings: interrupt-controller: Convert aspeed,ast2xxx-scu-ic to DT schema
5b9b0407663f dt-bindings: interrupt-controller: Convert aspeed,ast2400-i2c-ic to DT schema
f9bbcc9b6c01 dt-bindings: interrupt-controller: Convert faraday,ftintc010 to DT schema
7294b1050582 dt-bindings: interrupt-controller: Convert arm,versatile-fpga-irq to DT schema
649b5c8621b8 dt-bindings: interrupt-controller: Convert marvell,orion-bridge-intc to DT schema
734c54291c99 dt-bindings: interrupt-controller: Convert brcm,bcm2835-armctrl-ic to DT schema
664ccaddb8c7 dt-bindings: interrupt-controller: Convert cnxt,cx92755-ic to DT schema
0ea75feee1fc dt-bindings: Move altr,msi-controller to interrupt-controller directory
6495e4ed6240 dt-bindings: display: msm: correct example in SM8350 MDSS schema
5b9ad5a2dfdd ARM: dts: rockchip: Sonoff-iHost: correct IO domain voltages
9769e597df87 ARM: dts: rockchip: Sonoff-iHost: adjust SDIO for stability
cfc9b15d5a11 arm64: dts: qcom: qcs615: add QCrypto nodes
9c0b672d1a26 ARM: dts: qcom: apq8064: move replicator out of soc node
b8fdb42c3ef8 ARM: dts: qcom: apq8064: use new compatible for SPS SIC device
ff32b336f170 ARM: dts: qcom: apq8064: use new compatible for SFPB device
6bc1bbe5e284 ARM: dts: qcom: apq8064 merge hw splinlock into corresponding syscon device
97c58abad644 ARM: dts: qcom: apq8064: add missing clocks to the timer node
588277158131 ARM: dts: qcom: apq8064-lg-nexus4-mako: Enable WiFi
c38f33d12773 dt-bindings: remoteproc: qcom,sm8150-pas: Add missing SC8180X compatible
0e18b8f3302e dt-bindings: remoteproc: qcom,sm8350-pas: Add SC8280XP
8b2b4a3d2f48 arm64: dts: qcom: qcm6490-fairphone-fp5: Add DisplayPort sound support
d4442f6cb5b5 arm64: dts: qcom: sa8775p: Add default pin configurations for QUP SEs
d80b5d5eb446 arm64: dts: qcom: sm8550: add iris DT node
440474042b22 arm64: dts: qcom: sm8750: Add LLCC node
52b421406179 dt-bindings: cache: Convert marvell,tauros2-cache to DT schema
c9a46662587b dt-bindings: cache: Convert marvell,{feroceon,kirkwood}-cache to DT schema
c5ded6da00b3 Merge tag 'ib-mfd-gpio-nvmem-v6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd into gpio/for-next
4c5098982fc0 dt-bindings: pinctrl: qcom: correct gpio-ranges in examples for qcs8300
e5f1fdf5993a dt-bindings: pinctrl: qcom: correct gpio-ranges in examples for qcs615
d4bb52b1a986 dt-bindings: mfd: stm32-lptimer: Add support for stm32mp25
625ca4337c13 dt-bindings: arm: sunxi: Add Liontron H-A133L board name
f04a227e17cd dt-bindings: vendor-prefixes: Add Liontron name
bfe02c5509da ARM: dts: bananapi: add support for PHY LEDs
c38080e2bde0 arm64: dts: exynos: gs101: add pmu-intr-gen syscon node
aaaa3d2d975d dt-bindings: soc: samsung: exynos-pmu: gs101: add google,pmu-intr-gen phandle
60e3d8f854d2 dt-bindings: soc: google: Add gs101-pmu-intr-gen binding documentation
de42c4f36861 Merge 6.15-rc6 into usb-next
07f7e9376270 dt-bindings: vertexcom-mse102x: Fix IRQ type in example
58b1a45e9a93 dt-bindings: net: renesas-gbeth: Add support for RZ/V2N (R9A09G056) SoC
52ca9c9ddc70 dt-bindings: cache: qcom,llcc: Document SM8750 LLCC block
025a2913e06b arm64: dts: fvp: Add ETE and TRBE nodes for Rev C model
5ad508ce1d56 arm64: dts: arm: Drop the clock-frequency property from timer nodes
25d74c506801 arm64: dts: fvp: Reserve 64MB for the FF-A firmware in memory map
9e9e8b5cf5a6 arm64: dts: fvp: Add CPU idle states for Rev C model
f473d29f366e arm64: dts: fvp: Add system timer for broadcast during CPU idle
007cc6992f97 dt-bindings: hwmon: Add bindings for mpq8785 driver
76523dbde424 dt-bindings: Add SQ52206 to ina2xx devicetree bindings
6c8240f637d2 dt-bindings: display/msm: hdmi: Fix constraints on additional 'port' properties
85f8e9ee5faf dt-bindings: display/msm/hdmi: drop obsolete GPIOs from schema
fdfcf09cd00d dt-bindings: allwinner: add H616 DE33 clock binding
b972073fb318 dt-bindings: cache: add specific RZ/Five compatible to ax45mp
0298beca0879 Merge tag 'imx-dt64-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt
f2bb39101a3b Merge tag 'imx-dt-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt
6c162beac92a Merge tag 'imx-bindings-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt
3ee6d99dd050 Merge tag 'omap-for-v6.16/dt-signed' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap into soc/dt
3f5fa91e9e2d ARM: dts: vt8500: list all four timer interrupts
1f83cca57612 ARM: dts: vt8500: add DT nodes for the system config ID register
6c470fc07949 ARM: dts: vt8500: Add VIA APC Rock/Paper board
febd1ce7bd7c dt-bindings: arm: vt8500: Add VIA APC Rock/Paper boards
95f9c7c6dc87 Merge branch 'arm32-for-6.15' into arm32-for-6.16
c8676402f0c1 arm64: dts: qcom: sdm845-xiaomi-beryllium-ebbg: introduce touchscreen support
ab71f552530b arm64: dts: qcom: sdm845-xiaomi-beryllium-tianma: introduce touchscreen support
d3b7b1cd4294 arm64: dts: qcom: sdm845-xiaomi-beryllium-common: add touchscreen related nodes
be86327be1f6 arm64: dts: qcom: qcs8300: add the pcie smmu node
d1df8506d7f8 dt-bindings: arm: qcom,ids: add SoC ID for SM8750
aa1565085185 arm64: dts: qcom: x1e80100-*: Drop useless DP3 compatible override
13c97c62e922 ARM: dts: qcom: msm8226-motorola-falcon: specify vddio_disp output voltage
133d8def9bb5 ARM: dts: qcom: msm8226-motorola-falcon: limit TPS65132 to 5.4V
891fc76ba245 ARM: dts: qcom: msm8226-motorola-falcon: add I2C clock frequencies
e69bb23d6f80 ARM: dts: qcom: msm8226-motorola-falcon: add clocks, power-domain to simpleFB
9fe2e9dfcb24 arm64: dts: rockchip: drop wrong spdif clock from edp1 on rk3588
5141e453466a arm64: dts: rockchip: Add RK3562 evb2 devicetree
20bdf0cc35a8 arm64: dts: rockchip: add core dtsi for RK3562 SoC
e228bf1a80cf dt-bindings: input: convert dlg,da7280.txt to dt-schema
3958d8fa0b1f arm64: dts: qcom: msm8953: Add interconnects
fe42f0e4c34a arm64: dts: qcom: msm8953: Add uart_5
574d98f8dc8f arm64: dts: qcom: sm8350: Use q6asm defines for reg
1ece6dc8a89e arm64: dts: qcom: sm7325-nothing-spacewar: Use q6asm defines for reg
0c54cbe1b4a1 arm64: dts: qcom: sdm850*: Use q6asm defines for reg
90aef0299579 arm64: dts: qcom: sdm845*: Use q6asm defines for reg
b7b96192306a arm64: dts: qcom: sc7280: Use q6asm defines for reg
f61e104f90f9 arm64: dts: qcom: sc7180-acer-aspire1: Use q6asm defines for reg
7630b69ba5ed arm64: dts: qcom: qrb5165-rb5: Use q6asm defines for reg
e10687993363 arm64: dts: qcom: msm8996*: Use q6asm defines for reg
34723a48b744 arm64: dts: qcom: msm8953: Use q6asm defines for reg
f836b37531ba arm64: dts: qcom: msm8916-modem-qdsp6: Use q6asm defines for reg
d20576ba16ab arm64: dts: qcom: apq8096-db820c: Use q6asm defines for reg
4fe4605f0189 arm64: dts: qcom: qcm6490-fairphone-fp5: Hook up DisplayPort over USB-C
19532936991f arm64: dts: qcom: qcm6490-fairphone-fp5: Add OCP96011 audio switch
4816893c07b5 arm64: dts: qcom: qcm6490-fairphone-fp5: Add PTN36502 redriver
e21032020eb3 dt-bindings: clock: add SM6350 QCOM video clock bindings
963a57d1a640 arm64: dts: qcom: sm6350: Align reg properties with latest style
a6498df45f67 arm64: dts: qcom: sc7280: Stop setting dmic01 pinctrl for va-macro
f575876f8adf arm64: dts: qcom: x1e80100: Add OPPs up to Turbo L3 for GPU
28999942677d arm64: dts: qcom: x1e80100: Add ACD levels for GPU
134ab78d697d spi: dt-bindings: nuvoton,wpcm450-fiu: Drop unrelated nodes from DTS example
6c96065aa8cb spi: dt-bindings: fsl,dspi: Fix example indentation
b2c36c9410e6 dt-bindings: arm: rockchip: Add rk3562 evb2 board
1a6745865a66 dt-bindings: soc: rockchip: Add rk3562 syscon compatibles
11bb268f9698 dt-bindings: rockchip: pmu: Add rk3562 compatible
c6c0fbd0b465 arm64: dts: rockchip: Enable Ethernet controller on Radxa E20C
882f3957a39f arm64: dts: rockchip: Add GMAC nodes for RK3528
878d50ae8ece Merge tag 'tegra-for-6.16-arm-dt' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt
9935f8964201 Merge tag 'tegra-for-6.16-arm64-dt' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt
27648c567dd3 dt-bindings: PCI: Convert v3,v360epc-pci to DT schema
720f8541f5da dt-bindings: clock: sun50i-h616-ccu: Add LVDS reset
6f75843afb57 dt-bindings: gpu: mali-bifrost: Add compatible for RZ/V2N SoC
eb155080b68f dt-bindings: soc: qcom: qcom,rpm: add missing clock/-names properties
b9554cc578d9 dt-bindings: soc: qcom,rpm: add missing clock-controller node
599b2c9eda58 Merge tag 'tegra-for-6.16-dt-bindings' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt
ae1e35821ad4 Merge tag 'memory-controller-drv-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into soc/drivers
9cb0a9935a2e Merge tag 'memory-controller-drv-renesas-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into soc/drivers
e3b2e5a3cafd Merge tag 'scmi-updates-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into soc/drivers
593a164161fe Merge tag 'mtk-soc-for-v6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/drivers
6ac9a220784a Merge tag 'samsung-drivers-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/drivers
1e29760150ff Merge tag 'v6.16-rockchip-dts32-1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
3af4a1919ecf Merge tag 'v6.16-rockchip-dts64-1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
7da1d84ce8a9 Merge tag 'asahi-soc-dt-6.16' of https://github.com/AsahiLinux/linux into soc/dt
859f06fdd36e Merge tag 'arm-soc/for-6.16/devicetree-arm64' of https://github.com/Broadcom/stblinux into soc/dt
9b1d4cdc396e Merge tag 'arm-soc/for-6.16/devicetree' of https://github.com/Broadcom/stblinux into soc/dt
ea0f80a223b4 Merge tag 'renesas-dts-for-v6.16-tag2' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
2754fead3c67 Merge tag 'renesas-dts-for-v6.16-tag1' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
ee1cbe4b8690 Merge tag 'renesas-dt-bindings-for-v6.16-tag1' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
9172333f1c36 Merge tag 'socfpga_dts_updates_for_v6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into soc/dt
65945ed4ecf7 ARM: dts: vt8500: use correct ohci/ehci node names
db3d273ea6dd ARM: dts: ti: omap: use correct ohci/ehci node names
29098c0b2750 ARM: dts: st: use correct ohci/ehci node names
f2573fbf2983 ARM: dts: nxp: lpc: use correct ohci/ehci node names
6818afe8c49c ARM: dts: marvell: use correct ohci/ehci node names
73262063f45d arm64: dts: rockchip: add Rock 5B+
7909790b5192 dt-bindings: arm: rockchip: Add Radxa ROCK 5B+
4238190b0f49 arm64: dts: rockchip: move rock 5b to include file
ef9fc0fca3cc arm64: dts: rockchip: Add rk3399-evb-ind board
24335e68a617 dt-bindings: arm: rockchip: Add rk3399 industry evaluation board
a5d824bc4857 arm64: dts: rockchip: Enable HDMI audio on Sige5
5915b8ba5ff7 arm64: dts: rockchip: Add analog audio on RK3576 Sige5
cfa4fa721fc4 arm64: dts: rockchip: Add RK3576 HDMI audio
cd275a639ae9 arm64: dts: rockchip: Add RK3576 SAI nodes
66849b21618c arm64: dts: rockchip: Enable SD-card interface on Radxa E20C
4674d377180c arm64: dts: rockchip: Add SDMMC/SDIO controllers for RK3528
24c4ac403174 Merge branch 'v6.16-shared/clkids' into v6.16-armsoc/dts64
1f0210a2d1c9 ARM: dts: amlogic: meson8-fernsehfee3: Describe regulators
f2d00ba732ef ARM: dts: amlogic: Add TCU Fernsehfee 3.0
503326d77770 dt-bindings: arm: amlogic: Add TCU Fernsehfee 3.0 board
049bdf8c194c dt-bindings: vendor-prefixes: Add TC Unterhaltungselektronik AG
b987dfc06d4e dt-bindings: reset: Add compatible for Amlogic A4/A5 Reset Controller
ad8117c16a75 ARM: dts: mxs: use padconfig macros
3c692a3cd472 arm64: dts: freescale: Add PHYTEC phyBOARD-Nash-i.MX93 support
44179fccbf35 bindings: arm: fsl: Add PHYTEC phyBOARD-Nash-i.MX93 board
58b8e29378d4 arm64: dts: freescale: imx8mp-toradex-smarc: use generic gpio node name
955a4e348a47 arm64: dts: freescale: imx8mp-toradex-smarc: add gpio expander
1a275a3d9d35 arm64: dts: freescale: imx8mp-toradex-smarc: add embedded controller
1783722ca70f arm64: dts: freescale: imx8mp-toradex-smarc: add fan PWM configuration
f2e560c30759 arm64: dts: imx93-tqma9352-mba91xxca: disable Open Drain for MDIO
49e05d4dcb41 dt: bindings: arm: add bindings for TQMa95xxSA
c4ede310e854 arm64: dt: imx95: Add TQMa95xxSA
3f51af4e9314 ARM: dts: imx7d: update opp-table voltages
faa7b0f09960 dt-bindings: mfd: Add max77759 binding
adb36b1583dc dt-bindings: nvmem: Add max77759 binding
626e4d4c2dd1 dt-bindings: gpio: Add max77759 binding
59579e8080e7 ARM: dts: nxp: Align wifi node name with bindings
a57498324c33 arm64: dts: imx: Align wifi node name with bindings
dda8571e68ba arm64: dts: freescale: add initial device tree for TQMa8XxS
420ccf352c88 dt-bindings: arm: add TQMa8XxS boards
2c22f0454dbc arm64: dts: imx8mp-tqma8mpql-mba8mp-ras314: Add Raspberry Pi Camera V2 overlay
8e30973098b1 arm64: dts: freescale: Add minimal dts support for imx943 evk
b7f8b9829627 arm64: dts: freescale: Add basic dtsi for imx943
b171f67469ba dt-bindings: arm: fsl: add i.MX943 EVK board
51a46f724ce6 arm64: dts: ti: k3-j722s-evm: Add overlay for TEVI OV5640
0b98d867cbe7 arm64: dts: ti: k3-j722s-evm: Add overlay for quad IMX219
f02ee6932e03 arm64: dts: ti: j722s-evm: Add MUX to control CSI2RX
5015bfcb82cc arm64: dts: ti: j722s-evm: Add DT nodes for power regulators
ec097bc51325 arm64: dts: ti: k3-am62a-phycore-som: Reserve main_timer2 for C7x DSP
b8c5a617d6bc arm64: dts: ti: k3-am62a-phycore-som: Reserve main_rti4 for C7x DSP
3031c3fe18db arm64: dts: ti: k3-am62a-phycore-som: Enable Co-processors
739cbc1d54d9 arm64: dts: ti: k3-am62-phycore-som: Enable Co-processors
c02b9c9cefdf arm64: dts: ti: k3-am62x-phyboard-lyra-gpio-fan: Update cooling maps
a615712406dd arm64: dts: ti: k3-am62a: Enable CPU freq throttling on thermal alert
e39e8901b8f9 arm64: dts: ti: k3-j721e-common-proc-board: Enable OSPI1 on J721E
74294f5566ae arm64: dts: imx8-colibri: Add PCIe support
62b02d402a77 arm64: dts: freescale: imx93-phyboard-segin: Order node alphabetically
a6acee4ac52a arm64: dts: freescale: imx93-phyboard-segin: Add EQOS Ethernet
1d0d44116304 arm64: dts: freescale: imx93-phyboard-segin: Add I2S audio
f0fea5510d92 arm64: dts: freescale: imx93-phyboard-segin: Add USB support
a2cf356b1399 arm64: dts: freescale: imx93-phyboard-segin: Add CAN support
7a1af769f159 arm64: dts: freescale: imx93-phyboard-segin: Add RTC support
f7809266a2ee arm64: dts: freescale: imx93-phyboard-segin: Set CMD/DATA SION bit to fix ERR052021
7206d2882315 arm64: dts: freescale: imx93-phyboard-segin: Fix SD-card pinctrl
b2469f6146c6 arm64: dts: freescale: imx93-phyboard-segin: Disable SD-card write-protect
5b40838286a0 arm64: dts: freescale: imx93-phyboard-segin: Drop eMMC no-1-8-v flag
073a3258de8c arm64: dts: freescale: imx93-phycore-som: Add eMMC no-1-8-v by default
745f39b81f20 arm64: dts: freescale: imx93-phycore-som: Enhance eMMC pinctrl
6b1bf8706c84 arm64: dts: freescale: imx93-phycore-som: Disable LED pull-up
767f031ca462 arm64: dts: freescale: imx93-phycore-som: Add EEPROM support
d562521d7664 arm64: dts: freescale: imx93-phycore-som: Add PMIC support
744b873154a9 media: dt-bindings: Add amlogic,c3-isp.yaml
1f1824e8d41c media: dt-bindings: Add amlogic,c3-mipi-adapter.yaml
2a83b3a89adf media: dt-bindings: Add amlogic,c3-mipi-csi2.yaml
bfb60c429ab7 Add RZ/G3E xSPI support
6bc5ca9e9e31 arm64: dts: add imx8mp-libra-rdk-fpsc LVDS panel overlay
bb5fe43bf772 arm64: dts: add imx8mp-libra-rdk-fpsc board
6d47c5101c87 dt-bindings: arm: add imx8mp-libra-rdk-fpsc
34d5fc0c469e arm64: tegra: Wire up CEC to devkits
b4122e423095 arm64: tegra: Add CEC controller on Tegra210
81403688d54d arm64: tegra: Add fallback CEC compatibles
860a0306e7cb media: dt-bindings: Document Tegra186 and Tegra194 cec
814cf0ca9673 ARM: tegra: apalis-eval: Remove pcie-switch node
7336f5eff07b arm64: tegra: Add uartd serial alias for Jetson TX1 module
773a698cffd0 arm64: tegra: Bump #address-cells and #size-cells on Tegra186
6eb9ab33c1ca arm64: tegra: p2180: Explicitly enable GPU
97a72f63b02b arm64: tegra: p3310: Explicitly enable GPU
dc394ae50b15 arm64: tegra: Add DMA properties for Tegra186 and Tegra194 UARTs
0c8116fdf82b arm64: tegra: Drop remaining serial clock-names and reset-names
cf8710c05237 arm64: tegra: Enable PWM fan on the Jetson TX2 Devkit
10909b6e7512 arm64: tegra: Enable PWM fan on the Jetson TX1 Devkit
6c62747d11ae ARM: tegra: Add device-tree for ASUS Transformer Pad LTE TF300TL
45ff634f62bd dt-bindings: arm: tegra: Add Asus Transformer Pad TF300TL
17f175deb9ee dt-bindings: arm: tegra: Group Tegra30 based ASUS Transformers
45c2549c2180 dt-bindings: interrupt-controller: Convert nvidia,tegra20-ictlr to DT schema
f732c059581d arm64: tegra: Add I2C aliases for Tegra234
2275ec7fcdcb arm64: tegra: Configure QSPI clocks and add DMA
5bbc2a8c5070 dt-bindings: dma: nvidia,tegra20-apbdma: convert text based binding to json schema
2af32339da6c ARM: tegra: Rename the apbdma nodename to match with common dma-controller binding
5604f94f1d7b dt-bindings: clock: rk3036: add SCLK_USB480M clock-id
f929318ed0ef ARM: dts: renesas: r9a06g032-rzn1d400-eb: Enable USB host port
358563053427 ARM: dts: renesas: r9a06g032-rzn1d400-db: Add pinmux for the CPLD
075b685b47f4 arm64: dts: renesas: white-hawk-single: Improve Ethernet TSN description
9e2e4c5571be ARM: dts: renesas: r9a06g032-rzn1d400-db: Enable USB device port
b0a3caca0471 ARM: dts: renesas: r9a06g032-rzn1d400-eb: Describe 9-pin D-sub serial port
e4e1d7312e3a arm64: dts: renesas: beacon-renesom: Align wifi node name with bindings
f0ce8327c980 arm64: dts: renesas: rzg2l-smarc: Enable GPT on carrier board
e2a02100e30b arm64: dts: renesas: r9a07g054: Add GPT support
b745dbf0e8d0 arm64: dts: renesas: r9a07g044: Add GPT support
02e6b1b121fc arm64: dts: renesas: sparrow-hawk: Add MSIOF Sound support
9d4b51f0467a ARM: dts: renesas: r9a06g032-rzn1d400-eb: Add GMAC1 port
0522e8351f89 Merge tag 'renesas-r9a09g047-dt-binding-defs-tag3' into renesas-clk-for-v6.16
01db475996bf dt-bindings: clock: renesas,r9a09g047-cpg: Add XSPI and GBETH PTP core clocks
9aab5b0dd0ce dt-bindings: riscv: Add xsfvfwmaccqqq ISA extension description
871364b29b15 dt-bindings: riscv: Add xsfvfnrclipxfqf ISA extension description
f6dd93536c85 dt-bindings: riscv: Add xsfvqmaccdod and xsfvqmaccqoq ISA extension description
01794edd9948 dt-bindings: clock: Add GRF clock definition for RK3528
dd0175a5cb33 arm64: dts: rockchip: Move rk3568 PCIe3 MSI to use GIC ITS
49deec21e26c arm64: dts: rockchip: Update eMMC for NanoPi R5 series
e9d28cbe7969 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
a33a192ad701 dt-bindings: display: panel: Add Novatek NT37801
76b3a3804dd7 dt-bindings: display: panel: convert truly,nt35597.txt to dt-schema
14bbe9563987 ARM: dts: am335x: Set wakeup-source for UART0
46060816b6be dt-bindings: mux: add optional regulator binding to gpio mux
0a5ec97f672c riscv: dts: thead: Add device tree VO clock controller
5a3d46ddd366 dt-bindings: clock: thead: Add TH1520 VO clock controller
0bac955e720a dt-bindings: arm: qcom: Add SM7150 Google Pixel 4a
e5487155fa85 ARM: dts: qcom: ipq4019: Drop redundant CPU "clock-latency"
3b45cd0540a8 dt-bindings: PCI: pci-ep: Add support for iommu-map and msi-map
85e37e6a8a00 arm64: dts: allwinner: a100: set maximum MMC frequency
71610c8f6573 dt-bindings: memory-controllers: Add STM32 Octo Memory Manager controller
4a6f85f46c97 arm64: dts: rockchip: Add vcc-supply to SPI flash on rk3566-rock3c
27cb7181fa25 arm64: dts: qcom: msm8939: Drop generic UART pinctrl templates
0299a80853e3 arm64: dts: qcom: msm8916: Drop generic UART pinctrl templates
f7626223fbef arm64: dts: qcom: msm8916-motorola: Use UART1 console pinctrl
bc047fb23c7e arm64: dts: qcom: msm8919/39: Use UART2 console pinctrl where appropriate
82a1d0626f30 arm64: dts: qcom: msm8916/39: Introduce new UART console pinctrl
9671fb87cd7a arm64: dts: qcom: msm8916/39: Move UART pinctrl to board files
7ae4d81f0acd arm64: dts: qcom: x1e80100: Fix PCIe 3rd controller DBI size
21a18efb9369 arm64: dts: qcom: x1e/x1p: Add EL2 overlay for WoA devices
b08db9175aea arm64: dts: qcom: x1e80100: Add PCIe IOMMU
aa60c3acb06a arm64: dts: qcom: sc8280xp: Add EL2 overlay for WoA devices
83b237618bf2 arm64: dts: qcom: sc8280xp: Add PCIe IOMMU
665f9564abc0 arm64: dts: qcom: sc7180: Add EL2 overlay for WoA devices
87b448b47006 dt-bindings: interrupt-controller: Convert openrisc,ompic to DT schema
a2901e9860d9 Merge tag 'wireless-next-2025-05-06' of https://git.kernel.org/pub/scm/linux/kernel/git/wireless/wireless-next
90076255cd0e This patch set did some clean up and add runtime pm
2a73fae0eef7 dt-bindings: soc: sophgo: add RTC support for Sophgo CV1800 series
db6d6e0cc454 dt-bindings: clock: sophgo: add clock controller for SG2044
4f7b03443bcf dt-bindings: soc: sophgo: Add SG2044 top syscon device
411ad66f6c87 dt-bindings: clock: sophgo: Use precise compatible for CV1800 series SoC
e6cfd7fc83e3 dt-bindings: clock: Drop st,stm32h7-rcc.txt
c05f831cb19b dt-bindings: clock: convert bcm2835-aux-clock to yaml
3eb3880ced4d dt-bindings: clock: Drop maxim,max77686.txt
d11740d0cb1c arm64: dts: qcom: x1e001de-devkit: Fix pin config for USB0 retimer vregs
a3c4d35cf2d0 arm64: dts: qcom: x1e001de-devkit: Describe USB retimers resets pin configs
e8a588366b40 arm64: dts: qcom: x1e80100-qcp: Fix vreg_l2j_1p2 voltage
b2fd69366c77 arm64: dts: qcom: x1e80100-lenovo-yoga-slim7x: Fix vreg_l2j_1p2 voltage
73d93d5bd92c arm64: dts: qcom: x1e80100-hp-omnibook-x14: Fix vreg_l2j_1p2 voltage
b1458d47b907 arm64: dts: qcom: x1e80100-asus-vivobook-s15: Fix vreg_l2j_1p2 voltage
3d4bc8f706a7 arm64: dts: qcom: x1e001de-devkit: Fix vreg_l2j_1p2 voltage
02a3d15ce9d1 arm64: dts: qcom: x1-crd: Fix vreg_l2j_1p2 voltage
f50e1070cfe1 arm64: dts: qcom: sc7280: add UFS operating points
36a66deea079 dt-bindings: arm: qcom: Add Asus Zenbook A14
388cf04293fc arm64: dts: qcom: qcs8300: Add cpufreq scaling node
2770dfb61311 arm64: dts: qcom: sda660-ifc6560: Fix dt-validate warning
ff4c18346f89 arm64: dts: qcom: sdm660-lavender: Add missing USB phy supply
41ddc955d99c arm64: dts: qcom: sdm630: Add modem metadata mem
5e1d302c47f2 arm64: dts: ipq6018: drop standalone 'smem' node
935bb6b903f7 dt-bindings: input: touchscreen: edt-ft5x06: use unevaluatedProperties
19170f83f4d6 dt-bindings: interrupt-controller: Convert opencores,or1k-pic to DT schema
a813b7184209 dt-bindings: media: convert imx.txt to yaml format
f036436d4e3a arm64: dts: ti: k3-j721s2: Add GPU node
05217f9f363a arm64: dts: ti: k3-am62: New GPU binding details
e3b4871cc54c arm64: dts: ti: k3-am62-main: Add PRUSS-M node
f21fd9e2b809 arm64: dts: ti: k3-am64: Reserve timers used by MCU FW
7554d6edc067 arm64: dts: ti: k3-am62a7-sk: Reserve main_rti4 for C7x DSP
9c7c2c426a28 arm64: dts: ti: k3-am62a7-sk: Reserve main_timer2 for C7x DSP
4dc654f3ea4f arm64: dts: ti: k3-am62x-sk-common: Enable IPC with remote processors
ccd74102c419 arm64: dts: ti: k3-am62p5-sk: Enable IPC with remote processors
2cf6f198463c arm64: dts: ti: k3-am62a7-sk: Enable IPC with remote processors
d115e1eada3e arm64: dts: ti: k3-am62a-main: Add C7xv device node
87d1a5e90b69 arm64: dts: ti: k3-am62a-wakeup: Add R5F device node
349f1d769bb6 arm64: dts: ti: k3-am62a-mcu: Add R5F remote proc node
e74c39a60ea5 arm64: dts: ti: k3-am62-wakeup: Add wakeup R5F node
6c2036041051 arm64: dts: ti: k3-am62: Add ATCM and BTCM cbass ranges
776ccc66e63e arm64: dts: ti: k3-am625-beagleplay: Add required voltage supplies for TEVI-OV5640
ad3ac0dd79a7 arm64: dts: ti: k3-am625-beagleplay: Add required voltage supplies for OV5640
165924ec0e5a arm64: dts: ti: k3-am62x: Add required voltage supplies for TEVI-OV5640
57f7626a30df arm64: dts: ti: k3-am62x: Add required voltage supplies for OV5640
ea8502a760f3 arm64: dts: ti: k3-am62x: Add required voltage supplies for IMX219
5a11adf3759f arm64: dts: ti: k3-am62p5-sk: Add regulator nodes for AM62P
557dca1160b4 media: dt-bindings: sony,imx290: Update usage example
2f12e85b926d media: dt-bindings: sony,imx415: update maintainer e-mail address
465494fa972e arm64: dts: mt6359: Add missing 'compatible' property to regulators node
dadfed8c1931 arm/arm64: dts: mediatek: Add missing "#sound-dai-cells" to linux,bt-sco
5ae022ae9660 arm64: dts: mediatek: mt8390-genio-common: Set ssusb2 default dual role mode to host
6eba789bfdbd arm64: dts: mediatek: mt8395-genio-1200-evk: Disable unused backlight
4feac5571d3c arm64: dts: mediatek: mt6357: Drop regulator-fixed compatibles
856c2b05f9e9 arm64: dts: rockchip: Enable regulators for Radxa E20C
b7970c3a509b arm64: dts: rockchip: Add pwm nodes for RK3528
9537ebf0af18 media: dt-bindings: Add ST VD55G1 camera sensor
2270d79148b6 media: dt-bindings: Add ST VD56G3 camera sensor
1acf6a10e0c2 media: dt-bindings: Add OmniVision OV02C10
711f90dc2821 Merge drm/drm-next into drm-misc-next
1ea0f9e44221 BackMerge tag 'v6.15-rc5' into drm-next
0c67bd9ea5e2 AsoC: Phase out hybrid PCI devres
4249e9eeb523 arm64: dts: rockchip: Add onboard EEPROM for Radxa E20C
f1835c1d3102 arm64: dts: rockchip: Add I2C controllers for RK3528
9124dcd6b6ca dt-bindings: clock: rk3576: add IOC gated clocks
195ab4f8a4fd arm64: tegra: tegra210-p2894: Align GPIO hog node name with preferred style
9b87fa574f97 arm64: dts: bcm: Add reference to RPi 2 (2nd rev)
7fc72ab2aa49 ARM: dts: bcm: Add support for Raspberry Pi 2 (2nd rev)
8d7e910606f3 dt-bindings: arm: bcm2835: Add Raspberry Pi 2 (2nd rev)
79860f59b8ce dt-bindings: reset: sophgo: Add SG2044 bindings.
0f5d34937143 dt-bindings: reset: Document RZ/V2H(P) USB2PHY reset
25cfcb091747 arm64: dts: rockchip: add RK3576 RNG node
7500df32a633 arm64: dts: amlogic: Add A5 Reset Controller
06a6f9e68bb5 arm64: dts: amlogic: Add A4 Reset Controller
5526b16a2902 arm64: dts: amlogic: add support for xiaomi-aquaman/Mi TV Stick
41bcfded41fb dt-bindings: arm: amlogic: add S805Y and Mi TV Stick
89e5c3f0d82f arm64: dts: amlogic: gxl: set i2c bias to pull-up
42dec1aa5d48 dt-bindings: rng: rockchip,rk3588-rng: add rk3576-rng compatible
b47e9a75a1f5 arm64: dts: renesas: r9a09g047e57-smarc: Enable CAN Transceiver
4f4bdff8036a arm64: dts: renesas: r9a09g047e57-smarc: Enable CANFD
4948f0e037d7 arm64: dts: renesas: r9a09g047: Add CANFD node
ca3cc0b21e41 arm64: dts: rockchip: Switch to undeprecated qcom,calibration-variant on RK3399
b6eaa60c5b68 arm64: dts: rockchip: Add vcc-supply to SPI flash on rk3566-quartz64-b
a811ecd47f98 arm64: dts: rockchip: Add phy-supply to gmac0 on NanoPi R5S
92db0f57859b ARM: dts: rockchip: enable Mali gpu on rk3066 marsboard
af638cbdc9f4 ARM: dts: rockchip: enable hdmi on rk3066 marsboard
e5ed6360a0bb Revert "ARM: dts: rockchip: drop grf reference from rk3036 hdmi"
e8e08fa436aa ARM: dts: rockchip: Add ref clk for hdmi
8f6e1742dc0d dt-bindings: display: panel: Add BOE TD4320
fe3f772e4234 Merge git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux v6.15-rc5
295a83cac5a6 dt-bindings: hwinfo: Add VIA/WonderMedia SoC identification
dfebd1da805d dt-bindings: opp: Add v2-qcom-adreno vendor bindings
008f0861616f dt-bindings: display: rockchip,inno-hdmi: Document GRF for RK3036 HDMI
b6f43ec6014d dt-bindings: display: rockchip,inno-hdmi: Fix Document of RK3036 compatible
e066fecec49c dt-bindings: display: ltk500hd1829: add port property
aac56bec913a dt-bindings: display: ltk050h3146w: add port property
2679eb9c1099 arm64: dts: allwinner: t527: add EMAC0 to Avaota-A1 board
a84e9b1ef511 arm64: dts: allwinner: a527: add EMAC0 to Radxa A5E board
d67d653027ac arm64: dts: allwinner: a523: Add EMAC0 ethernet MAC
2c2285f92bd4 dt-bindings: sram: sunxi-sram: Add A523 compatible
906efd1c226c dt-bindings: pwm: add support for MC33XS2410
c45f7825b9a3 arm64: dts: ti: k3-am65-main: Add missing taps to sdhci0
abfe507190c9 arm64: dts: ti: k3-am62p-j722s-common-main: Set eMMC clock parent to default
05be23aa2598 arm64: dts: ti: k3-am62a-main: Set eMMC clock parent to default
d7281ad6c7f0 arm64: dts: ti: k3-am62-main: Set eMMC clock parent to default
5d554875ee67 arm64: dts: ti: am62p-verdin: Add ivy
5910df5fae25 arm64: dts: ti: am62p-verdin: Add yavia
c56788f3dc13 arm64: dts: ti: am62p-verdin: Add mallow
26225792edf9 arm64: dts: ti: am62p-verdin: Add dahlia
d2963aa25b8d arm64: dts: ti: Add Toradex Verdin AM62P
9f3a0c2c8544 dt-bindings: arm: ti: Add Toradex Verdin AM62P
0e1a2f9ae270 arm64: dts: ti: k3-j784s4-j742s2-evm-common: Enable ACSPCIE0 output for PCIe1
38b84d8c08ed arm64: dts: ti: k3-j784s4-j742s2-main-common: Add ACSPCIE0 node
db5f03dc9cc5 arm64: dts: ti: k3-j784s4-j742s2-main-common: Switch to 64-bit address space for PCIe0 and PCIe1
15243bd3bb0f arm64: dts: ti: k3-j722s-main: Switch to 64-bit address space for PCIe0
1ccd5d5c0b25 arm64: dts: ti: k3-j721s2-main: Switch to 64-bit address space for PCIe1
b45b19421146 arm64: dts: ti: k3-j721e-main: Switch to 64-bit address space for PCIe0 and PCIe1
c58f019a0643 arm64: dts: ti: k3-j721e: Add ranges for PCIe0 DAT1 and PCIe1 DAT1
ac9f688b927f arm64: dts: ti: k3-j7200-main: Switch to 64-bit address space for PCIe1
8c1c5e3952fe arm64: dts: ti: k3-am64-main: Switch to 64-bit address space for PCIe0
9bd6216a75f9 arm64: dts: ti: k3-am6*: Remove disable-wp for eMMC
9391e35a9961 arm64: dts: ti: k3-am62*: Add non-removable flag for eMMC
efc9013586bd arm64: dts: ti: k3-am6*: Add boot phase flag to support MMC boot
20228e421df8 dt-bindings: media: renesas,isp: Add ISP core function block
0d57e67f6fd1 dt-bindings: media: qcom,sm8550-iris: document QCS8300 IRIS accelerator
929624534b09 dt-bindings: media: qcom,sm8550-iris: document SM8650 IRIS accelerator
dfd2223ffa4c dt-bindings: arm: psci: change labels to lower-case in example
733d55025477 dt-bindings: net: via-rhine: Convert to YAML
2e15a84f751b dt-bindings: display: msm: document DSI controller and phy on SA8775P
f7cce69098b3 dt-bindings: msm: dsi-controller-main: document the SA8775P DSI CTRL
0dfaeb000391 dt-bindings: display: msm-dsi-phy-7nm: document the SA8775P DSI PHY
afd72e545768 dt-bindings: display: msm: sm8350-mdss: Describe the CPU-CFG icc path
4a36951513b4 dt-bindings: display/msm: Add Qualcomm SAR2130P
4efeb8748c14 dt-bindings: net: sun8i-emac: Add A523 EMAC0 compatible
e5b81042e489 dt-bindings: display/msm: qcom,sc7280-dpu: describe SAR2130P
92699890681b dt-bindings: display/msm: dsi-phy-7nm: describe SAR2130P
01da1f48bd4a dt-bindings: display/msm: dsi-controller-main: describe SAR2130P
e50e3900c247 dt-bindings: display/msm: dp-controller: describe SAR2130P
50b4d3ab2f90 dt-bindings: display: msm: mdp4: add LCDC clock and PLL source
dc3117f0d58a dt-bindings: msm: qcom,mdss: Document interconnect paths
675f0bfb1706 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
84a58e460c62 dt-bindings: power: supply: Document Maxim MAX8971 charger
6bbc7ffdc64a spi: dt-bindings: spi-qpic-snand: Add IPQ5018 compatible
626cc8b07ead ARM: dts: omap4: panda: cleanup bluetooth
bcf5e5f95ba9 ARM: dts: omap4: panda: fix resources needed for Wifi
52e01741cd60 dt-bindings: usb: realtek,rts5411: Adapt usb-hub.yaml
dc73d9f2d3be dt-bindings: usb: Add binding for PS5511 hub controller
9dac5fe200f7 dt-bindings: usb: Introduce usb-hub.yaml
9f2adf2c7968 arm64: dts: rockchip: fix usb-c port functionality on rk3588-nanopc-t6
6c497c6eba1d arm64: dts: exynos: add initial support for Samsung Galaxy J6
e046936b0e72 arm64: dts: exynos: add initial support for Samsung Galaxy A2 Core
6948e73799e5 arm64: dts: exynos: add initial support for Samsung Galaxy J7 Prime
9c3c04c2d87b arm64: dts: exynos: add initial devicetree support for exynos7870
551070b23bf8 dt-bindings: arm: samsung: add compatibles for exynos7870 devices
e12137fe5717 arm64: dts: rockchip: Enable bluetooth of AP6611s on OrangePI5 Max/Ultra
feb54a4cfc60 dt-bindings: memory: Document RZ/G3E support
151b9911dfff arm64: dts: apple: Add PMIC NVMEM
1034cfa91f13 ASoC: codec: twl4030: Convert to GPIO descriptors
a781ea3fe6f5 dt-bindings: crypto: fsl,sec-v4.0-mon: Add "power-off-time-sec"
7d7e67ac6cb8 dt-bindings: reset: syscon-reboot: add google,gs101-reboot
8feed3b94fdd spi: axi-spi-engine: offload instruction optimization
2c42fa887eba arm64: dts: exynosautov920: add cpucl1/2 clock DT nodes
99c94468b170 dt-bindings: clock: exynosautov920: add cpucl1/2 clock definitions
e0d9b0f244f9 dt-bindings: hwmon: Add Sophgo SG2044 external hardware monitor support
1991cce4d18b dt-bindings: power: supply: Document Pegatron Chagall fuel gauge
a3572ed09649 dt-bindings: vendor-prefixes: add prefix for Pegatron Corporation
0bf560ff10e1 arm64: dts: rockchip: add SATA nodes to RK3576
6e434b1b73aa dt-bindings: clock: convert vf610-clock.txt to yaml format
1f0623137e5a dt-bindings: arm: arm,coresight-static-replicator: add optional clocks
107b934a7fb5 dt-bindings: mtd: qcom,nandc: Document the SDX75 NAND controller
bf701761289b dt-bindings: power: reset: add toradex,smarc-ec
3f3c4e59f9ba dt-bindings: interconnect: sm8650: document the MASTER_APSS_NOC
d9188b52a9dc dt-bindings: interconnect: Correct indentation and style in DTS example
b31830e88153 arm64: dts: rockchip: Add vcc-supply to SPI flash on rk3588-rock-5b
7a4bb5be4074 arm64: dts: rockchip: Add vcc-supply to SPI flash on rk3566-pinetab2
104277ae91b0 arm64: dts: rockchip: Add vcc-supply to SPI flash on rk3399-rockpro64
4078c21208d8 arm64: dts: rockchip: Add vcc-supply to SPI flash on rk3328-rock64
852abcba0fe4 arm64: dts: rockchip: Add vcc supply to spi flash on rk3399-roc-pc
c88c9d3b42f7 arm64: dts: rockchip: enable pcie on Sige5
bbbd016dd1ad arm64: dts: rockchip: Add HDMI support for roc-rk3576-pc
f5b1563af154 arm64: dts: rockchip: Enable HDMI0 audio output for Indiedroid Nova
4a9ca88961e2 arm64: dts: rockchip: Add rk3588 evb2 board
0ee39726af75 dt-bindings: arm: rockchip: Add rk3588 evb2 board
677235aee353 arm64: dts: rockchip: Add pcie1 slot for rk3576 evb1 board
921916e138df arm64: dts: rockchip: Enable eDP display for Cool Pi GenBook
719b9d6deca7 arm64: dts: rockchip: Add eDP1 dt node for rk3588
5999cea2c433 arm64: dts: rockchip: enable HDMI out audio on Khadas Edge2
7079948ecc6f arm64: dts: rockchip: Add HDMI & VOP2 to Khadas Edge2
763e2383f0a8 arm64: dts: rockchip: Add bluetooth support to Khadas Edge2
46e308df7a7f arm64: dts: rockchip: add overlay for tiger-haikou video-demo adapter
86fd593d347f dt-bindings: mtd: convert vf610-nfc to yaml format
42bcbd1ec509 dt-bindings: ata: rockchip-dwc-ahci: add RK3576 compatible
9d3907b0dc81 Merge 6.15-rc4 into usb-next
69c335bc812d Merge 6.15-rc4 into tty-next
96bd6de45bb5 dt-bindings: mtd: Add Loongson-1 NAND Controller
7466915999d4 arm64: dts: allwinner: a64: Add WiFi/BT header on SOPINE Baseboard
1dc8db0178a9 arm64: dts: allwinner: a64: Add WiFi/BT header on PINE A64
1cd3a1d2b00d arm64: dts: allwinner: correct the model name for Radxa Cubie A5E
600ef18c9822 ARM: dts: allwinner: Align wifi node name with bindings
1914fe32e80a arm64: dts: allwinner: Align wifi node name with bindings
c022a034b1d6 arm64: dts: allwinner: h616: enable Mali GPU for all boards
e9933d2fb4d7 arm64: dts: allwinner: h616: Add Mali GPU node
803a02505b52 arm64: dts: allwinner: h700: Add hp-det-gpios for Anbernic RG35XX
bf34e9d35324 arm64: dts: allwinner: h5/h6: Drop spurious 'clock-latency-ns' properties
3f45bf7f52f0 arm/arm64: dts: allwinner: Use preferred node names for cooling maps
3a879d878553 arm64: dts: allwinner: h616: add YuzukiHD Chameleon support
0b9e163070f5 dt-bindings: arm: sunxi: Add YuzukiHD Chameleon board name
91ad117321c0 arm64: dts: allwinner: a523: add Radxa A5E support
69f8fbcdd27d dt-bindings: power: supply: bq24190: Add BQ24193 compatible
c7f9db5b72c6 dt-bindings: reset: atmel,at91sam9260-reset: add microchip,sama7d65-rstc
4107b274a54e dt-bindings: power: supply: Correct indentation and style in DTS example
0def74e690b2 arm64: dts: exynosautov920: add cpucl0 clock DT nodes
21de0b373e61 dt-bindings: clock: exynosautov920: add cpucl0 clock definitions
bb8a9492ece1 MIPS: Loongson64: Add missing '#interrupt-cells' for loongson64c_ls7a
4da20eae1087 mips: dts: realtek: Add MDIO controller
693da0a03149 arm64: dts: allwinner: a523: add X96Q-Pro+ support
ebcb8469ef43 arm64: dts: allwinner: a523: add Avaota-A1 router support
ddd2264cb891 ARM: dts: rockchip: Drop redundant CPU "clock-latency"
98a69848d374 arm64: dts: rockchip: add dsi controller nodes on rk3588
3e476fb13a10 arm64: dts: rockchip: add mipi dcphy nodes to rk3588
32be2a8c8e02 dt-bindings: PCI: qcom: Add MHI registers for IPQ9574
9cafacd8c4c9 ASoC: add Renesas MSIOF sound driver
5acc974247a4 dt-bindings: renesas,sh-msiof: Add MSIOF I2S Sound support
81e1bd55f661 arm64: dts: ti: k3-am625-sk: Enable PWM
16c71470bff1 arm64: dts: ti: k3-am62a7-sk: Enable PWM
716448152383 arm64: dts: ti: k3-am62p5-sk: Enable PWM
c94675306a28 arm64: dts: ti: Add basic support for phyBOARD-Izar-AM68x
c388cf2e36b8 dt-bindings: arm: ti: Add bindings for PHYTEC AM68x based hardware
43874d152bfe arm64: dts: ti: k3-j784s4-j742s2-main-common: Fix length of serdes_ln_ctrl
241109b8c8f6 arm64: dts: ti: am65x: Add missing power-supply for Rocktech-rk101 panel
22b82bf80770 arm64: dts: ti: k3-am65-main: Add system controller compatible
9680a390671a dt-bindings: mfd: ti,j721e-system-controller: Add compatible string for AM654
8e985cb49182 arm64: dts: ti: k3-j721e-common-proc-board-infotainment: Update to comply with device tree schema
25240cd26ef5 riscv: dts: thead: Introduce reset controller node
40f6c8eba924 media: dt-bindings: Document Tegra186 and Tegra194 cec
8d47ce901c2c dt-bindings: serial: amlogic,meson-uart: Add compatible string for S6/S7/S7D
16cb9f9e498a dt-bindings: serial: mediatek,uart: Add compatible for MT6893
6e6039994c8b dt-bindings: usb: usb-switch: Allow data-lanes property in port
a8fc1dcece74 dt-bindings: usb: generic-ehci: Add VIA/WonderMedia compatible
932da7a8df7b dt-bindings: usb: usb-device: relax compatible pattern to a contains
772b2e8cb9dd dt-bindings: usb: renesas,usbhs: Add RZ/V2H(P) SoC support
b0282744d363 Merge tag 'ath-next-20250418' of git://git.kernel.org/pub/scm/linux/kernel/git/ath/ath into wireless-next
f1ded0dfbccb media: dt-bindings: Convert Analog Devices ad5820 to DT schema
ae47e78ed52c media: dt-bindings: Add OmniVision OV02E10
79596bb37f98 media: dt-bindings: ti,ds90ub960: Allow setting serializer address
e48c94010dd5 media: dt-bindings: media: i2c: align filenames format with standard
d4b3524bf7a6 arm64: dts: imx8mq-evk: add pcie[0,1]-ep nodes
af70c3ed355a arm64: dts: imx8mq: add pcie0-ep node
b3f9adea45f5 arm64: dts: imx8mm-evk: add pcie0-ep node and apply pcie0-ep overlay file
67af22b950f2 arm64: dts: imx95: add pcie1 ep overlay file and create pcie-ep dtb files
be98b5a4b268 arm64: dts: imx8: use common imx-pcie0-ep.dtso to enable PCI ep function
72cb1708ae6b arm64: dts: imx8dxl-evk: Add pcie0-ep node and use unified pcie0 label
d1bf4f7b077e arm64: dts: imx8dxl-ss-hsio: correct irq number for imx8dxl
58861f28ee1d arm64: dts: imx8: create unified pcie0 and pcie0_ep label for all chips
e90c11e7667e arm64: dts: imx8-apalis: Add PCIe and SATA support
c0b02f0c33c7 Revert "arm64: dts: imx93-tqma9352-mba93xxla: enable Open Drain for MDIO"
5906f9c2d71a Revert "arm64: dts: imx93-tqma9352-mba93xxca: enable Open Drain for MDIO"
42b2289cec15 arm64: dts: imx8mp-beacon: Enable RTC interrupt and wakeup-source
d5bc51143411 arm64: dts: imx8mn-beacon: Enable RTC interrupt and wakeup-source
d9b339df2d8d arm64: dts: imx8mm-beacon: Enable RTC interrupt and wakeup-source
4e9004d5ecaa arm64: dts: imx8mn-beacon: Configure Ethernet PHY reset and GPIO IRQ
88dcf5d7f9c7 arm64: dts: imx8mm-beacon: Configure Ethernet PHY reset and GPIO IRQ
4258324f7cad arm64: dts: imx8mn-beacon: Set SAI5 MCLK direction to output for HDMI audio
957674dfa0b4 arm64: dts: imx8mm-beacon: Set SAI5 MCLK direction to output for HDMI audio
3825ee8ab2fe arm64: dts: imx8mp-beacon: Fix RTC capacitive load
6c24afc09355 arm64: dts: imx8mn-beacon: Fix RTC capacitive load
002e93c2520b arm64: dts: imx8mm-beacon: Fix RTC capacitive load
fdcb73bb223c arm64: add initial device tree for TQMa93xx/MBa91xxCA
e6d059456914 dt-bindings: arm: add MBa91xxCA Mainboard for TQMa93xxCA/LA SOM
6e3150878b7f arm64: dts: freescale: add Toradex SMARC iMX8MP
6a14e799ccce dt-bindings: arm: fsl: add Toradex SMARC iMX8MP SoM and carrier
0b198af79fa2 arm64: dts: s32gxxxa-rdb: Add PCA85073A RTC module over I2C0
e01c88e81a57 arm64: dts: imx95-15x15-evk: enable USB2.0 node
2956a2fad59b arm64: dts: imx95-19x19-evk: enable USB2.0 node
b57e40b4b93e arm64: dts: imx95: add USB2.0 nodes
8912cf0407cd ARM: dts: imx6q-apalis: remove pcie-switch node
42c8e16469f9 arm64: dts: imx8mp: Add device tree for Nitrogen8M Plus ENC Carrier Board
36e551b010e9 dt-bindings: arm: fsl: Add Boundary Device Nitrogen8M Plus ENC Carrier Board
6472a607374f dt-bindings: net: brcm,unimac-mdio: Add asp-v3.0
ec5333381e64 dt-bindings: net: brcm,asp-v2.0: Add asp-v3.0
e7636d5ce4c2 dt-bindings: net: brcm,unimac-mdio: Remove asp-v2.0
ac81b792e66f dt-bindings: net: brcm,asp-v2.0: Remove asp-v2.0
b523691f91fc dt-bindings: power: qcom,rpmpd: Add SM4450 compatible
e77a87a724fa dt-bindings: pwm: vt8500-pwm: Convert to YAML
0fb0156996ae dt-bindings: pwm: mediatek,pwm-disp: Add compatible for MT6893
0badf787ac7e dt-bindings: mfd: bd96802: Add ROHM BD96806
cb95b5d3c057 dt-bindings: mfd: bd96801: Add ROHM BD96805
1fbf3128a581 dt-bindings: mfd: Add ROHM BD96802 PMIC
5966dca99c06 dt-bindings: regulator: Add ROHM BD96802 PMIC
ae31878acd85 dt-bindings: power: Add Allwinner H6/H616 PRCM PPU
f4a58e101181 dt-bindings: gpu: Add 'resets' property for GPU initialization
3dce8ed7efbf arm64: dts: renesas: r8a779h0: Add ISP core function block
7ab5541f5631 arm64: dts: renesas: r8a779g0: Add ISP core function block
7c5f77250e86 arm64: dts: renesas: r8a779a0: Add ISP core function block
72a455b37dc7 arm64: dts: renesas: r8a779g3: Add Retronix R-Car V4H Sparrow Hawk board support
8cfc94f50e33 dt-bindings: soc: renesas: Document Retronix R-Car V4H Sparrow Hawk board support
e92bf5beb087 dt-bindings: vendor-prefixes: Add Retronix Technology Inc.
575112a9940a arm64: dts: mediatek: Add MT8186 Ponyta Chromebooks
9be55ad24aee dt-bindings: arm: mediatek: Add MT8186 Ponyta Chromebook
47f7ec1e89b3 arm64: dts: mediatek: mt8186-corsola: make SDIO card removable
d5854c28c729 dt-bindings: interrupt-controller: via,vt8500-intc: Convert to YAML
240e1020a18e dt-bindings: arm/cpus: allow up to 3 interconnects entries
c230496b1449 dt-bindings: display: Add Sitronix ST7571 LCD Controller
0b90b9d75595 dt-bindings: hwmon: ti,tmp102: document optional V+ supply property
26de36c3334a dt-bindings: hwmon: pmbus: add lt3074
d2fcc47c99f6 dt-bindings: hwmon: amc6821: add fan and PWM output
83785e4a4d68 dt-bindings: wireless: qcom,wcnss: Use wireless-controller.yaml
a62d4dcab2d7 dt-bindings: wireless: silabs,wfx: Use wireless-controller.yaml
5afb07ef0f59 dt-bindings: wireless: bcm4329-fmac: Use wireless-controller.yaml schema
9477f2559b7e dt-bindings: net: Add generic wireless controller
66bcd13cf8a7 dt-bindings: net: Add network-class schema for mac-address properties
8afa56eb8b9b dt-bindings: dma: fsl-edma: increase maxItems of interrupts and interrupt-names
cfbc26c13ea3 dt-bindings: dma: qcom,bam: Document dma-coherent property
7474a36b64bb dt-bindings: soc: qcom,rpmh-rsc: Limit power-domains requirement
207d29dd5aa7 dt-bindings: power: rockchip: Add support for RK3562 SoC
1f4f5e6d471c Add RK3576 SAI Audio Controller Support
f3bb7170abd4 arm64: dts: mediatek: mt8395-nio-12l: Enable Audio DSP and sound card
11ee3efc86c9 arm64: dts: mediatek: mt8390-genio-common: Add Display on DSI0
69d9b1270387 arm64: dts: mediatek: mt8395-genio-1200-evk: Add display on DSI0
13816981f2f2 arm64: dts: freescale: imx8mm-verdin: Add EEPROM compatible fallback
7ca80da3dbc5 arm64: dts: freescale: imx8mp-verdin: Add EEPROM compatible fallback
8927d1c11a35 arm64: dts: mt8183: Add port node to mt8183.dtsi
8d696ebbe281 ARM: dts: ls1021a-tqmals1021a: change sound card model name
fc79cde19de2 ARM: dts: ls1021a-tqmals1021a: Add overlay for CDTech DC44 RGB display
1a279450be52 ARM: dts: ls1021a-tqmals1021a: Add overlay for CDTech FC21 RGB display
891d4f7327ed ARM: dts: ls1021a-tqmals1021a: Add LVDS overlay for Tianma TM070JVGH33
d313da9895c1 ARM: dts: ls1021a-tqmals1021a: Add HDMI overlay
d2014560f7a9 ARM: dts: ls1021a-tqmals1021a: Add vcc-supply for spi-nor
d0573667ab9f ARM: dts: ls1021a-tqmals1021a: Fix license
15f3dec744dc ARM: dts: imx: Drop redundant CPU "clock-latency"
37bf4d2bccdf arm64: dts: imx: Drop redundant CPU "clock-latency"
7eaf105a0367 dt-bindings: pinctrl: convert fsl,imx7ulp-pinctrl.txt to yaml format
accab92f7c4f media: dt-bindings: renesas,rzg2l-cru: Document Renesas RZ/G3E SoC
948ceb8e33d1 media: dt-bindings: renesas,rzg2l-csi2: Document Renesas RZ/G3E CSI-2 block
6914e693d51d media: dt-bindings: renesas,rzg2l-csi2: Document Renesas RZ/V2H(P) SoC
eb4dda012b0d media: dt-bindings: media: renesas,fcp: Document RZ/V2H(P) SoC
a7f4d9c91d74 media: dt-bindings: media: renesas,vsp1: Document RZ/V2H(P)
01687fc2770e arm64: dts: imx8qm-mek: consolidate reserved-memory
1a3288716f35 dt-bindings: pinctrl: spacemit: add clock and reset property
9ebe2fd36cd6 dt-bindings: power: mediatek: Support Dimensity 1200 MT6893 MTCMOS
eede67deb547 dt-bindings: PCI: qcom: Add IPQ5018 SoC
1bd879b82bec dt-bindings: PCI: Remove obsolete .txt docs
a59cf6bd0a89 dt-bindings: PCI: Convert marvell,armada8k-pcie to schema
62bb3eef59ee dt-bindings: PCI: Convert Marvell EBU to schema
be24a3971fd2 dt-bindings: PCI: sifive,fu740-pcie: Fix include placement in DTS example
a3908fe56239 dt-bindings: PCI: Correct indentation and style in DTS example
159e9454d956 dt-bindings: PCI: dwc: rockchip: Add rk3562 support
ef0f37ca5ff5 dt-bindings: PCI: dw: rockchip: Add rk3576 support
ebc2179ccf8f dt-bindings: net: Document support for Renesas RZ/V2H(P) GBETH
472799cc1133 dt-bindings: net: dwmac: Increase 'maxItems' for 'interrupts' and 'interrupt-names'
1997420be337 dt-bindings: net: dp83822: add constraints for mac-termination-ohms
e706611ad55b dt-bindings: net: ethernet-phy: add property mac-termination-ohms
10faeaae6517 dt-bindings: iio: imu: icm42600: add interrupt naming support
d2b5833dde70 dt-bindings: ROHM BD79104 ADC
050b648678c0 dt-bindings: iio: adc: adi,ad7606: add SPI offload properties
61c34bb63511 dt-bindings: iio: adc: ad7380: add AD7389-4
520f1aa3afd9 dt-bindings: Add ROHM BD7970x variants
9db7709f449c dt-bindings: ROHM BD79124 ADC/GPO
484465e0026d dt-bindings: iio: filter: Add lpf/hpf freq margins
c0d5d6f0abd0 dt-bindings: iio: adc: amlogic,meson-saradc: Add GXLX SoC compatible
10988aac05c5 dt-bindings: iio: light: bh1750: Add reset-gpios property
c9f357746caa dt-bindings: iio: Use unevaluatedProperties for SPI devices
aad2a4aba149 dt-bindings: iio: Correct indentation and style in DTS example
7c7b549aa38c dt-bindings: display: imx: convert fsl,tcon.txt to yaml format
22d2cf8b3f78 dt-bindings: fsl: convert m4if.txt and tigerp.txt to yaml format
e07e2c2f96fe dt-bindings: display: imx: convert ldb.txt to yaml format
a9b92e46c884 dt-bindings: powerpc: Convert fsl/pmc.txt to YAML
ca4517cfee45 dt-bindings: virtio: pci-iommu: Add ref to pci-device.yaml
86b145f94994 dt-bindings: backlight: add TI LP8864/LP8866 LED-backlight drivers
c2ba19c59cef dt-bindings: display: imx: convert fsl-imx-drm.txt to yaml format
fb650bd91b53 dt-bindings: interrupt-controller: Add missed fsl tzic controller
1f5c4df2e936 dt-bindings: remove RZ/N1S bindings
335c675342f4 dt-bindings: Remove obsolete numa.txt
855e8fcacd8e dt-bindings: Remove obsolete cpu-topology.txt
195c40fcc4b6 dt-bindings: counter: Convert ftm-quaddec.txt to yaml format
417caeebdd6c dt-bindings: cpufreq: Drop redundant Mediatek binding
f6548c04b52e dt-bindings: arm/cpus: Add power-domains constraints
2ddae0f8d5fe dt-bindings: arm/cpus: Add missing properties
28a210612928 dt-bindings: Reference opp-v1 schema in CPU schemas
fe6dc7443d31 dt-bindings: arm/cpus: Re-wrap 'description' entries
c64045034fdf dt-bindings: arm/cpus: Add schemas for "enable-method" dependencies
df668f6655f1 ASoC: dt-bindings: add schema for rockchip SAI controllers
1d48e25ced56 arm64: dts: add support for S7D based Amlogic BM202
0c1264e70500 arm64: dts: add support for S7 based Amlogic BP201
593f1d88b3b7 arm64: dts: add support for S6 based Amlogic BL209
410b38d60404 dt-bindings: arm: amlogic: add S7D support
2ca205bee2ea dt-bindings: arm: amlogic: add S7 support
20f8de3f09b1 dt-bindings: arm: amlogic: add S6 support
3c7e8180dc78 ASoC: dt-bindings: fsl,mqs: Document audio graph port
a80240369b3a arm64: dts: mediatek: mt8390-genio-common: Add firmware-name for scp0
1755d247e0e6 arm64: dts: mediatek: mt8188: Describe SCP as a cluster with two cores
17a60804ef13 dt-bindings: soc: amlogic: S4 supports clk-measure
8c786a9d5d99 dt-bindings: soc: amlogic: C3 supports clk-measure
11eee42e07c5 arm64: dts: amlogic: S4: Add clk-measure controller node
532a71d8ed7f arm64: dts: amlogic: C3: Add clk-measure controller node
44fcfeee7cf3 arm64: dts: rockchip: Add rk3576 pcie nodes
671d11c0c112 arm64: dts: rockchip: Enable HDMI audio outputs for Cool Pi CM5 EVB
5d9a0d8efcc1 arm64: dts: rockchip: Enable HDMI1 on Cool Pi CM5 EVB
edcac1a68928 arm64: dts: rockchip: Rename hdmi-con to hdmi0-con for Cool Pi CM5 EVB
6164d1b5f147 arm64: dts: rockchip: Enable eDP0 display on RK3588S EVB1 board
7a5418e7cb3b arm64: dts: rockchip: Add eDP0 node for RK3588
49ec37e83ae2 Merge tag 'renesas-r9a09g057-dt-binding-defs-tag3' into renesas-clk-for-v6.16
45233ddb59b5 dt-bindings: clock: renesas,r9a09g057-cpg: Add USB2 PHY and GBETH PTP core clocks
bad521c00e8d arm64: dts: renesas: rzg3e-smarc-som: Enable Mali-G52
ec4f1ea3a42a arm64: dts: renesas: r9a09g047: Add Mali-G52 GPU node
28fa85b6d9f9 arm64: dts: renesas: rzg3e-smarc-som: Add RAA215300 pmic support
f8d7d5853e29 arm64: dts: renesas: rzg3e-smarc-som: Add I2C2 device pincontrol
a03e6f70cfb9 dt-bindings: soc: renesas: Add Renesas RZ/T2H (R9A09G077) SoC
ed79e930a772 arm64: dts: exynos: Add DT node for all UART ports
e27cacd3b8c5 arm64: dts: amlogic: Drop redundant CPU "clock-latency"
3b88cda61806 arm64: dts: amlogic: gxlx-s905l-p271: add saradc compatible
4fe442ce931a arm64: dts: amlogic: a1: enable UART RX and TX pull up by default
96a635366da2 arm64: dts: amlogic: axg: enable UART RX and TX pull up by default
2c676fabc600 arm64: dts: amlogic: g12: enable UART RX and TX pull up by default
b9f6d24ba1a8 arm64: dts: amlogic: gxl: enable UART RX and TX pull up by default
744536cebfea arm64: dts: amlogic: gxbb: enable UART RX and TX pull up by default
62731c5b2949 arm64: dts: amlogic: a4: add pinctrl node
08023b0f21ab ARM: dts: amlogic: meson8b: enable UART RX and TX pull up by default
84e4059661d3 ARM: dts: amlogic: meson8: enable UART RX and TX pull up by default
7fffb9023d36 arm64: dts: imx8mp-evk: Enable DSP node for remoteproc usage
02671eee212b arm64: dts: imx8mp: Add DSP clocks
d87bc6cce59c arm64: dts: imx8mp: Configure dsp node for rproc usage
7aaa6e97a546 arm64: dts: imx8mp: Add mu2 root clock
9a7ac78ffb7a arm64: dts: imx8mp: Use resets property
36a025b9b2cb ARM: dts: imx51-digi-connectcore-som: Fix MMA7455 compatible
9dc44c77abcf ARM: dts: nxp: Align NAND controller node name with bindings
30c126d6dbab ARM: dts: imx: Fix the iim compatible string
4a9140955168 ARM: dts: imx31/imx6: Use flash as the NOR node name
86a6c4e28468 arm64: dts: imx: add imx95 dts for sof
60488f92956c arm64: dts: imx8mq: Add linux,pci-domain into pcie-ep node
6c877f641153 arm64: dts: imx8mm-phyboard-polis-peb-av-10: Set lvds-vod-swing
51f47e7c0b4c arm64: dts: qcom: qdu1000: Add snps,dis_u3_susphy_quirk
ef6bc0bf348e arm64: dts: qcom: qcs615: Add snps,dis_u3_susphy_quirk
cf3e5871d878 arm64: dts: qcom: sm8450: Add snps,dis_u3_susphy_quirk
074247f3be2b arm64: dts: qcom: sm8350: Add snps,dis_u3_susphy_quirk
7406a3e0937d arm64: dts: qcom: sm8150: Add snps,dis_u3_susphy_quirk
614a08df6a4a arm64: dts: ti: k3-j784s4-j742s2-evm: Add overlay to enable USB0 Type-A
094cbe1a912d arm64: dts: ti: k3-am67a-beagley-ai: Add bootph for main_gpio1
a63b4daf4b79 dt-bindings: display: rockchip: analogix-dp: Add support for RK3588
e4c693434b30 dt-bindings: display: rockchip: analogix-dp: Add support to get panel from the DP AUX bus
d1e65709163b arm64: dts: qcom: x1e80100-hp-omnibook-x14: Remove invalid bt-en-sleep node
2cb79ee30004 Merge branch 'arm32-for-6.15' into arm64-for-6.16
43b365ed3fc7 dt-bindings: pci: apple,pcie: Add t6020 compatible string
7a1b30bb0eea dt-bindings: PCI: qcom,pcie-sc8180x: Add 'global' interrupt
ade654bc2d03 dt-bindings: PCI: qcom: Allow IPQ6018 to use 8 MSI and one 'global' interrupt
5d87250e09fd dt-bindings: PCI: qcom: Allow IPQ8074 to use 8 MSI and one 'global' interrupt
4fa9a33a89aa dt-bindings: PCI: qcom: Allow MSM8998 to use 8 MSI and one 'global' interrupt
87908d20f9b5 dt-bindings: PCI: qcom: Add 'global' interrupt for SDM845 SoC
77377b0980f6 dt-bindings: PCI: qcom,pcie-sc7280: Add 'global' interrupt
95050a994ec3 dt-bindings: PCI: qcom,pcie-sa8775p: Add 'global' interrupt
4d5a69cb16bf dt-bindings: PCI: qcom,pcie-sm8350: Add 'global' interrupt
46e0cc9c1aa9 dt-bindings: PCI: qcom,pcie-sm8250: Add 'global' interrupt
ba7c1c776905 dt-bindings: PCI: qcom,pcie-sm8150: Add 'global' interrupt
70aa3043231a dt-bindings: misc: Describe TI FPC202 dual port controller
da01ee99aa22 arm64: dts: ti: Add k3-am62-pocketbeagle2
de444d92c16f dt-bindings: arm: ti: Add PocketBeagle2
4a5c06ef7268 arm64: dts: ti: k3-am625-verdin: Add EEPROM compatible fallback
85889ab7cccb arm64: dts: ti: k3-am62p-j722s: Add rng node
99c4e495818d arm64: dts: ti: k3-am64: Add PCIe ctrl node to main_conf region
05c44f561285 arm64: dts: ti: k3-j721s2: Add PCIe ctrl node to scm_conf region
9d8a3b7ffe5b arm64: dts: ti: k3-j7200: Add PCIe ctrl node to scm_conf region
d93d024659d6 arm64: dts: ti: k3-j721e: Add PCIe ctrl node to scm_conf region
a98c73a3f45f dt-bindings: soc: ti: ti,j721e-system-controller: Add PCIe ctrl property
5c346d01e6e2 arm64: dts: ti: k3-am62x: Rename I2C switch to I2C mux in OV5640 overlay
8ea0ac26429e arm64: dts: ti: k3-am62x: Rename I2C switch to I2C mux in IMX219 overlay
cb6797019f26 arm64: dts: ti: k3-am62x: Remove clock-names property from IMX219 overlay
15eccb1baa91 arm64: dts: ti: k3-j721e-sk: Add requiried voltage supplies for IMX219
3aa414595924 arm64: dts: ti: k3-j721e-sk: Remove clock-names property from IMX219 overlay
889f193469ef arm64: dts: ti: k3-am68-sk: Fix regulator hierarchy
9a5103dd484c arm64: dts: ti: k3-j721e-sk: Add DT nodes for power regulators
541f9536e43a arm64: dts: ti: k3-j722s-evm: Drop redundant status within serdes0/serdes1
a82340293539 arm64: dts: ti: k3-j722s-main: Don't disable serdes0 and serdes1
69db838227f8 arm64: dts: ti: k3-j722s-main: Disable "serdes_wiz0" and "serdes_wiz1"
50ace9c7fca6 arm64: dts: ti: k3-j722s-evm: Enable "serdes_wiz0" and "serdes_wiz1"
c68fb8dfcecc arm64: dts: ti: k3-j784s4-evm-usxgmii-exp1-exp2: drop pinctrl-names
f7e7b4782d11 spi: dt-bindings: Fix description mentioning a removed property
40b5957489e6 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
a76293f399ef dt-bindings: display: panel: Add Visionox G2647FB105
31bf80b7e095 dt-bindings: display: panel: Add Himax HX8279/HX8279-D DDIC panels
3d0544beaaa9 dt-bindings: vendor-prefixes: Add Shenzhen Aoly Technology Co., Ltd.
aadceed2b38f dt-bindings: display: simple: Add Tianma P0700WXF1MBAA panel
a7ec818fd1b6 dt-bindings: dma: Add Arm DMA-350
b3e59c644dfa ASoC: mt8195: Add support for MT8395 Radxa NIO 12L
1e0a96627fed dt-bindings: iommu: mediatek: Add binding for MT6893 MM IOMMU
58366e7824fc dt-bindings: gpio: spacemit: add support for K1 SoC
af0ce3f46116 ASoC: dt-bindings: mt8195: add missing audio routing and link-name
3f5cd90ccdf5 ASoC: dt-bindings: mt8195: add compatible mt8195_mt6359
ea716e20528e dt-bindings: pwm: Add RZ/G2L GPT binding
103d3ddc2b21 dt-bindings: pinctrl: convert fsl,vf610-pinctrl.txt to yaml format
cd7fc0138a87 dt-bindings: pinctrl: mediatek: Add support for mt8196
e036f09b4726 dt-bindings: pinctrl: mediatek: Add support for MT6893
9ad102711159 dt-bindings: pinctrl: mediatek: Correct indentation and style in DTS example
a3f46993c1d8 dt-bindings: pinctrl: mediatek: Drop unrelated nodes from DTS example
5aaff15d6d3c dt-bindings: display: mediatek: Add binding for MT8195 HDMI-TX v2
09efe288b44d dt-bindings: display: mediatek: Add binding for HDMIv2 DDC
ef5598e4b3d3 dt-bindings: clock: spacemit: Add spacemit,k1-pll
65c5c58321a4 dt-bindings: soc: spacemit: Add spacemit,k1-syscon
5d45a2a0a682 arm64: dts: qcom: sdm670: add camss and cci
98e1d9e9dd0e arm64: dts: mediatek: mt8196: Add pinmux macro header file
0124ced0cefe arm64: dts: mediatek: Add MT6893 pinmux macro header file
b4f4a5903e9f arm64: dts: mediatek: mt7622: Align GPIO hog name with bindings
27ba1cca68e2 arm64: dts: exynos: update all samsung,mode constants
c212190a0719 arm64: dts: qcom: sm8750-qrd: Enable modem
0c0d0f9db397 arm64: dts: qcom: sm8750-mtp: Enable modem
2dbfda4a1fca arm64: dts: qcom: sm8750: Add Modem / MPSS
dbdccf6854da arm64: dts: qcom: qcs6490-rb3gen2: Update the LPASS audio node
3ea9ff6b6b1f arm64: dts: qcom: qcm6490-idp: Update the LPASS audio node
515c678e4680 arm64: dts: qcom: sa8775p: Remove cdsp compute-cb@10
a797c39416e5 arm64: dts: qcom: sa8775p: Remove extra entries from the iommus property
c7412fe27214 arm64: dts: qcom: sm8650: use correct size for VBIF regions
a9ead2dddaf4 arm64: dts: qcom: sm8550: use correct size for VBIF regions
2684f559cb43 arm64: dts: qcom: sm8450: use correct size for VBIF regions
4d3789d6ba95 arm64: dts: qcom: sm8350: use correct size for VBIF regions
848bec2a462d arm64: dts: qcom: sm8250: use correct size for VBIF regions
8e40db4bb6bb arm64: dts: qcom: sm8150: use correct size for VBIF regions
5a868a02e7cf arm64: dts: qcom: sm6350: use correct size for VBIF regions
dffd3d4bcc12 arm64: dts: qcom: sm6125: use correct size for VBIF regions
cb1203e882d8 arm64: dts: qcom: sm6115: use correct size for VBIF regions
ba2eaf6365b2 arm64: dts: qcom: sdm845: use correct size for VBIF regions
30d1db2367db arm64: dts: qcom: sdm670: use correct size for VBIF regions
b9b2eed490b9 arm64: dts: qcom: sc8280xp: use correct size for VBIF regions
deb12da90a9f arm64: dts: qcom: sc8180x: use correct size for VBIF regions
eedd6875af28 arm64: dts: qcom: sc7280: use correct size for VBIF regions
dc88454477ff arm64: dts: qcom: sc7180: use correct size for VBIF regions
9835c454bf62 arm64: dts: qcom: sa8775p: use correct size for VBIF regions
b4368defbe1e arm64: dts: qcom: qcm2290: use correct size for VBIF regions
ebb5589fdeaa arm64: dts: qcom: msm8998: use correct size for VBIF regions
3ce4be3b9d8e arm64: dts: qcom: sa8775p: mark MDP interconnects as ALWAYS on
43adeccee9db arm64: dts: qcom: sc7280: Use the header with DSI phy clock IDs
c2b74a5ab3ec arm64: dts: qcom: sdm660-xiaomi-lavender: Add missing SD card detect GPIO
81d7bb6bfb24 ASoC: Add codec driver for Cirrus Logic CS48L32 DSP
4da4895ae7c6 arm64: dts: apple: Add SPMI controller nodes
7dd41ba7ca89 ASoC: dt-bindings: Add Cirrus Logic CS48L32 audio DSP
ba0f5e8a4bbb dt-bindings: usb: Introduce qcom,snps-dwc3
f7e8d13af32d dt-bindings: usb: samsung,exynos-dwc3: add exynos2200 compatible
376d95f4fcfd dt-bindings: net: wireless: Add Realtek RTL8188ETV USB WiFi
1393ec501aad dt-bindings: gpu: img: Add BXS-4-64 devicetree bindings
04e4825e5e66 dt-bindings: gpu: img: Future-proofing enhancements
f61cd93fb04d dt-bindings: interconnect: Add EPSS L3 compatible for SA8775P
48d0f5c99b80 arm64: dts: mediatek: mt8195: Add power domain for dp_intf0
fd5871672cfb dt-bindings: pinctl: amlogic,pinctrl-a4: Add compatible string for A5
80d9fbe4ae24 arm64: dts: mediatek: mt8188: Add all Multimedia Data Path 3 nodes
519c51530765 dt-bindings: media: mediatek: mdp3: Add compatibles for MT8188 MDP3
86930b41fb55 dt-bindings: display: mediatek: Add compatibles for MT8188 MDP3
23020928772e dt-bindings: memory: mtk-smi: Add support for MT6893
32ce7f7677ee ARM: dts: qcom: sdx55/sdx65: Fix CPU power-domain-names
489603d7ae76 arm64: dts: qcom: msm8992-lg-h815: Fix CPU node "enable-method" property dependencies
1acb8a3afec9 arm64: dts: qcom: msm8939: Fix CPU node "enable-method" property dependencies
58430ce78a75 arm64: dts: qcom: qdu1000: Fix qcom,freq-domain
51c305a0eec9 arm64: dts: qcom: Remove unnecessary MM_[UD]L audio routes
0ddb3701d5a2 arm64: dts: qcom: x1e80100-lenovo-yoga-slim7x: enable MICs LDO
d2d340219d57 arm64: dts: qcom: remove max-speed = 1G for RGMII for ethernet
2e97866fef19 riscv: dts: thead: Introduce power domain nodes with aon firmware
3203bed54904 dt-bindings: net: ti: k3-am654-cpsw-nuss: evaluate fixed-link property
57d708a99684 dt-bindings: net: ethernet-controller: add 5000M speed to fixed-link
4c7f11603555 dt-bindings: interrupt-controller: Add Sophgo SG2044 MSI controller
be5c965c1e13 arm64: dts: marvell: Drop unused "pinctrl-names"
970715b11ece Add support for Loongson-1 AC97
9c7b95fb32ec dt-bindings: soc: mediatek: dvfsrc: Add support for MT6893
09a106a121fc arm64: dts: mediatek: mt8186: starmie: Fix external display
b4b6de803068 arm64: dts: mediatek: mt8195: Reparent vdec1/2 and venc1 power domains
d029a36da846 arm64: dts: mediatek: mt8390-genio-common: Fix pcie pinctrl dtbs_check error
72a769730bb5 arm64: dts: mediatek: mt8395-genio-1200-evk: Add scp firmware-name
ea454778c25d arm64: dts: mediatek: mt8395-nio-12l: Add scp firmware-name
3be6964ca5d7 arm64: dts: mediatek: mt8188: Fix IOMMU device for rdma0
b75a3a2e52bc dt-bindings: firmware: Add i.MX95 SCMI LMM and CPU protocol
4755ea6ea789 ARM: dts: renesas: r9a06g032-rzn1d400-eb: describe SD card port
e18bd34b9406 ARM: dts: renesas: r9a06g032: Describe SDHCI controllers
d8697a0b8be3 arm64: dts: renesas: Add initial device tree for RZ/V2N EVK
e31a92d550aa arm64: dts: renesas: Add initial SoC DTSI for RZ/V2N
6c01ced6fc08 Merge tag 'renesas-r9a09g056-dt-binding-defs-tag1' into renesas-dts-for-v6.16
be5c7945dfbc dt-bindings: pinctrl: renesas: Document RZ/V2N SoC
757f7c111e60 dt-bindings: clock: renesas: Document RZ/V2N SoC CPG
14a6a632f90b dt-bindings: soc: renesas: Document SYS for RZ/V2N SoC
7f01c2ee0bf2 dt-bindings: soc: renesas: Document Renesas RZ/V2N SoC variants and EVK
a5a215f049ad ARM: dts: renesas: r9a06g032-rzn1d400-db: Describe keys
1252dbd741d4 ARM: dts: renesas: r9a06g032-rzn1d400-eb: Describe I2C bus
eef897044665 ARM: dts: renesas: r9a06g032-rzn1d400-db: Describe I2C bus
5f148a8d8dfc ARM: dts: renesas: r9a06g032: Describe I2C controllers
f8ef11f15d0d ARM: dts: renesas: Add r9a06g032-rzn1d400-eb board device-tree
15c36ca1f1aa dt-bindings: pwm: Add Loongson PWM controller
f13ab79ad775 ASoC: dt-bindings: Add bindings for Richtek rt9123p
551439fc8917 ASoC: dt-bindings: Add bindings for Richtek rt9123
67b9a4a613e5 ASoC: dt-bindings: Add Realtek ALC203 Codec
cd0cbd25ba04 ASoC: dt-bindings: Add Loongson-1 AC97 Controller
d19f03845632 arm64: dts: apple: t8015: Add CPU caches
96e590bf75e3 arm64: dts: apple: t8012: Add CPU caches
f403b51db93d arm64: dts: apple: t8011: Add CPU caches
1ffd100554f7 arm64: dts: apple: t8010: Add CPU caches
ab70b5862bf9 arm64: dts: apple: s8001: Add CPU caches
1e80d37ce322 arm64: dts: apple: s800-0-3: Add CPU caches
7fc695068e5e arm64: dts: apple: t7001: Add CPU caches
d91d60a37dac arm64: dts: apple: t7000: Add CPU caches
446475ce91b6 arm64: dts: apple: s5l8960x: Add CPU caches
51ac91f86b5a arm64: dts: broadcom: bcm2712: Use "l2-cache" for L2 cache node names
3b1c9669fcb3 dt-bindings: serial: Add compatible for Renesas RZ/T2H SoC in sci
27b96d2832df dt-bindings: serial: 8250: support an optional second clock
9487008acf8e dt-bindings: serial: snps-dw-apb-uart: Simplify DMA-less RZ/N1 rule
c58e818dffba dt-bindings: usb: usbmisc-imx: add support for i.MX95 platform
925760feb157 dt-bindings: usb: chipidea: Add i.MX95 compatible string 'fsl,imx95-usb'
3f95cd9eb7ee dt-bindings: usb: smsc,usb3503: Correct indentation and style in DTS example
0c1b24f9cf87 dt-bindings: usb: dwc3: Allow connector in USB controller node
c4d9df4388d4 dt-bindings: usb: qcom,dwc3: Add SM8750 compatible
ab3e4701d6ae dt-bindings: phy: qcom: uniphy-pcie: Add ipq5018 compatible
962144dc8146 dt-bindings: media: add support for video hardware on QCS615 platform
2dfdfac83463 dt-bindings: media: qcom,sm8550-iris: document SA8775p IRIS accelerator
e4ad9ca4085b dt-bindings: media: Add qcom,x1e80100-camss
80ddf0af6187 dt-bindings: media: camss: Restrict bus-type property
c34ae9de8ac5 ASoC: dt-bindings: Update example for enabling USB offload on SM8250
1d86a3fe426b ASoC: dt-bindings: qcom,q6dsp-lpass-ports: Add USB_RX port
2a377d8f94b5 ALSA: Add USB audio device jack type
cf0cbf431777 ARM: dts: at91: at91sam9263: fix NAND chip selects
fbe5a79f2873 ARM: dts: at91: usb_a9g20: move wrong RTC node
066ddcdd974a ARM: dts: at91: calao_usb: simplify chosen node
81de6966411b ARM: dts: at91: usb_a9260: use 'stdout-path'
8161869d1b43 ARM: dts: at91: calao_usb: simplify memory node
3dd34def8029 ARM: dts: at91: usb_a9263: fix GPIO for Dataflash chip select
a3f21e5b3a39 ARM: dts: at91: usb_a9g20: add SPI EEPROM
35085606ce0f dt-bindings: phy: brcmstb-usb-phy: Add support for bcm74110
be4f0bbd2ad9 ARM: dts: nokia n900: remove useless io-channel-cells property
0b7ceacf9b52 dt-bindings: display: simple: Add NLT NL13676BC25-03F panel
a5339a602279 dt-bindings: vendor-prefixes: Add EcoNet
b382b0963bb2 dt-bindings: phy: samsung,usb3-drd-phy: add exynos7870-usbdrd-phy compatible
db1d9d73cbf8 dt-bindings: phy: rockchip: Add missing "phy-supply" property
ea31b71e8dc7 arm64: dts: rockchip: Move SHMEM memory to reserved memory on rk3588
752a63fbba9f arm64: dts: rockchip: Add UART DMA support for RK3528
2342a94e45da arm64: dts: rockchip: Add DMA controller for RK3528
955f7dfa8330 arm64: dts: rockchip: Add missing uart3 interrupt for RK3528
ae0c23f1d3bf arm64: dts: rockchip: Rename vcc3v3_pcie0 to vcc3v3_pcie1 for rk3576-evb1-v10
ff36044b88d2 dt-bindings: display: rockchip,vop: Drop assigned-clocks
177de0ee8887 dt-bindings: firmware: google,gs101-acpm-ipc: add PMIC child node
627460f28703 regulator: dt-bindings: adi,adp5055-regulator: Add adp5055 support
6fba86b23019 arm64: dts: qcom: sm8650: Use the header with DSI phy clock IDs
7cf8e450c836 arm64: dts: qcom: sm8550: Use the header with DSI phy clock IDs
611ef92fbe1e arm64: dts: qcom: sm8450: Use the header with DSI phy clock IDs
dbf9c8e23c16 arm64: dts: qcom: sm8350: Use the header with DSI phy clock IDs
60d462b300bd arm64: dts: qcom: sm8250: Use the header with DSI phy clock IDs
0161b8b428a5 arm64: dts: qcom: sm8150: Use the header with DSI phy clock IDs
00fcce9a5938 arm64: dts: qcom: sm6350: Use the header with DSI phy clock IDs
d00674635be1 arm64: dts: qcom: sm6125: Use the header with DSI phy clock IDs
734afb56dbec arm64: dts: qcom: sm6115: Use the header with DSI phy clock IDs
4c902aa0c3c8 arm64: dts: qcom: sdm845: Use the header with DSI phy clock IDs
2b72c350b768 arm64: dts: qcom: sdm670: Use the header with DSI phy clock IDs
0178dfa7f6b7 arm64: dts: qcom: sdm630: Use the header with DSI phy clock IDs
c7974eda5aee arm64: dts: qcom: sc8180x: Use the header with DSI phy clock IDs
bbd34acbea44 arm64: dts: qcom: sc7180: Use the header with DSI phy clock IDs
72fe36f8dbd7 arm64: dts: qcom: qcm2290: Use the header with DSI phy clock IDs
39411c953302 arm64: dts: qcom: msm8998: Use the header with DSI phy clock IDs
350d85710230 arm64: dts: qcom: msm8996: Use the header with DSI phy clock IDs
bcabc03510bb arm64: dts: qcom: msm8976: Use the header with DSI phy clock IDs
ebfed549cc2d arm64: dts: qcom: msm8953: Use the header with DSI phy clock IDs
f204d52efc5f arm64: dts: qcom: msm8939: Use the header with DSI phy clock IDs
33ad178a48de arm64: dts: qcom: msm8917: Use the header with DSI phy clock IDs
5bfc873d7def arm64: dts: qcom: msm8916: Use the header with DSI phy clock IDs
f8fe1b41ce57 ARM: dts: qcom: msm8974: Use the header with DSI phy clock IDs
f96c56c7a652 ARM: dts: qcom: msm8226: Use the header with DSI phy clock IDs
f4143e343821 arm64: dts: fsd: Add Ethernet support for PERIC Block of FSD SoC
91c650cbe054 arm64: dts: fsd: Add Ethernet support for FSYS0 Block of FSD SoC
c3b35fa8b9a4 ASoC: wcd938x: enable t14s audio headset
37fdec27303b ARM: dts: nuvoton: Add MMC Nodes
b28b0dcdee93 ARM: dts: nuvoton: Add OHCI node
129b618c0219 ARM: dts: nuvoton: Add UDC nodes
151b1957ef4f ARM: dts: nuvoton: Add EDAC node
5c9e6533646b ARM: dts: nuvoton: Align GPIO hog name with bindings
67dfb235fd15 Merge branch 'arm64-for-6.15' into arm64-for-6.16
7ec23a778f3d ARM: dts: Drop DTS for BCM59056 PMU
b443a6223701 ARM: dts: bcm2166x: Add bcm2166x-pinctrl DTSI
9b7546c46ae5 ARM: dts: bcm2166x-common: Add pinctrl node
d70d01b71b71 arm64: dts: broadcom: bcm2712-rpi-5-b: Enable PCIe DT nodes
66cd796ed18b arm64: dts: broadcom: bcm2712: Add PCIe DT nodes
eb4502801000 dt-bindings: cache: sifive,ccache0: Add ESWIN EIC7700 SoC compatibility
4a1378329189 dt-bindings: remoteproc: stm32-rproc: Add firmware-name property
2b4be4ef6b2e dt-bindings: arm: sunxi: Add new board names for A523 generation
b4a4490611e1 dt-bindings: vendor-prefixes: Add YuzukiHD name
247a3572abcf arm64: dts: allwinner: Add Allwinner A523 .dtsi file
82ae2cf2441d arm64: dts: microchip: sparx5: Fix CPU node "enable-method" property dependencies
640d7abca1ba dt-bindings: writing-schema: Explain sub-nodes with additionalProperties:true
d0e1f7ab79fe Merge drm/drm-next into drm-misc-next
9463aad4a8cb dt-bindings: Document Blaize BLZP1600 GPIO driver
1cd181f49a96 arm64: dts: renesas: Remove undocumented compatible micron,mt25qu512a
ad32dcce24ed arm64: dts: renesas: r8a779f4: Add UFS tuning parameters in E-FUSE
374d98a0c04e arm64: dts: renesas: r9a09g047: Add ICU node
f84a5fd28547 arm64: dts: renesas: r9a09g047e57-smarc: Enable SDHI1
6a8407e40474 arm64: dts: renesas: rzg3e-smarc-som: Add support to enable SD on SDHI0
0622623eda68 arm64: dts: renesas: rzg3e-smarc-som: Enable SDHI{0,2}
1963097f0f58 arm64: dts: renesas: r9a09g057: Add support for enabling SDHI internal regulator
260b2d4cff22 arm64: dts: renesas: r9a09g047: Add SDHI0-SDHI2 nodes
e9ca7811de33 dt-bindings: reset: Add T-HEAD TH1520 SoC Reset Controller
03493b4dcc7c dt-bindings: gpio: pca95xx: add Toradex ecgpiol16
f061f5b90a52 dt-bindings: gpio: Correct indentation and style in DTS example
56d2ab45bc92 dt-bindings: interrupt-controller: Add EcoNet EN751221 INTC
3a22dd525deb ARM: dts: rockchip: Add aliases for rk3036-kylin MMC devices
ce9f22f3ac6b arm64: dts: rockchip: Enable HDMI audio output for RK3588 Tiger Haikou
4d53761f203d arm64: dts: rockchip: Enable HDMI audio output for RK3588 Jaguar
05839dce445f arm64: dts: rockchip: Enable HDMI ports on ArmSoM W3
1a906b44673a arm64: dts: rockchip: aliase sdhci as mmc0 for rk3566 box demo
4cc0db11d181 arm64: dts: rockchip: Add gmac phy reset GPIO to QNAP TS433
df34889c120b arm64: dts: rockchip: Correct gmac phy address on QNAP TS433
c2599bd7ba60 arm64: dts: rockchip: enable HDMI sound on FriendlyElec NanoPC-T6
e0105bf99fc5 arm64: dts: rockchip: enable HDMI1 on FriendlyElec NanoPC-T6
993f067b157f arm64: dts: rockchip: Enable ufshc on rk3576 evb1 board
9503e1049d7d arm64: dts: rockchip: change rng reset id back to its constant value
6769059a9a92 dt-bindings: crypto: qcom-qce: document QCS615 crypto engine
8b630d3d0343 spi: dt-bindings: st,stm32mp25-ospi: Make "resets" a required property
41f5c2138eda ASoC: dt-bindings: fsl,mqs: Reference common DAI properties
aca7d7c8231d ASoC: dt-bindings: maxim,max98925: Fix include placement in DTS example
85cb1980874d ASoC: dt-bindings: wcd93xx: add bindings for audio mux controlling hp
bda617efa5fc dt-bindings: display: panel: samsung,atna40yk20: document ATNA40YK20
6567ff08e8a6 arm64: dts: socfpga: agilex: Add dma channel id for spi
74c2199c410b arm64: dts: socfpga: agilex5: add led and memory nodes
6314a862e1f0 arm64: dts: intel: socfpga_agilex: add frequencies to internal oscillators
b6d3a349163f ARM: dts: socfpga: Add basic support for Terrasic's de10-nano
edfe33549623 dt-bindings: altera: Add compatible for Terasic's DE10-nano
1848a10387d0 arm64: dts: socfpga: agilex5: add qspi flash node
ead0491aa20a dt-bindings: firmware: stratix10: Convert to json-schema
d2eb681bb33e dt-bindings: fpga: stratix10: Convert to json-schema
77eaed14fef5 arm64: dts: socfpga: agilex5: fix gpio0 address
d8b351236603 arm64: dts: socfpga: agilex5: add NAND daughter board
638d117a6307 dt-bindings: intel: document Agilex5 NAND daughter board
0b86dfc98961 dt-bindings: net: wireless: describe the ath12k AHB module for IPQ5332
31fe92148c84 dt-bindings: gpu: v3d: Add V3D driver maintainer as DT maintainer
3b8d3bd14126 dt-bindings: gpu: v3d: Add SMS register to BCM2712 compatible
e45f0f5ee9c5 dt-bindings: gpu: v3d: Add per-compatible register restrictions
146ae6a0cc6a arm64: dts: qcom: x1e001de-devkit: fix USB retimer reset polarity
3f64d8354c4d arm64: dts: qcom: qcs8300: Add RPMh sleep stats
110c25056755 arm64: dts: qcom: ipq9574: Add nsscc node
76e32ecd464a Merge branch '20250313110359.242491-1-quic_mmanikan@quicinc.com' into arm64-for-6.15
fe21f24088be arm64: dts: qcom: x1e80100: enable rtc
1f7bad44a3d1 arm64: dts: qcom: sc8280xp-x13s: switch to uefi rtc offset
1932030c0c07 arm64: dts: qcom: sm8650: Fix domain-idle-state for CPU2
061462bb07da ARM: dts: qcom: Initial dts for LG Nexus 4
3705995fb324 arm64: dts: qcom: sa8775p: Add LMH interrupts for cpufreq_hw node
ac0b8ef17d01 arm64: dts: qcom: qcs615: remove disallowed property in spmi bus node
31de34fe7762 arm64: dts: qcom: x1e80100-vivobook-s15: Enable micro-sd card reader
c8133dbde91d arm64: dts: qcom: x1e80100-vivobook-s15: Enable USB-A ports
7333726fee23 arm64: dts: qcom: ipq5424: enable GPIO based LEDs and Buttons
99e6dcb2c981 arm64: dts: qcom: sm7325-nothing-spacewar: Enable panel and GPU
d1449baefa9d ARM: dts: qcom: msm8226-samsung-matisse-common: Enable modem
218a51a4c950 ARM: dts: qcom: msm8926-htc-memul: Enable modem
ec85529af07e ARM: dts: qcom: Introduce dtsi for LTE-capable MSM8926
8927425afd18 ARM: dts: qcom: msm8226: Add BAM DMUX Ethernet/IP device
2a8d7e638921 ARM: dts: qcom: msm8226: Add modem remoteproc node
5303a947ab02 ARM: dts: qcom: msm8226: Add smsm node
2f298f8b4106 ARM: dts: qcom: msm8226: Add node for TCSR halt regs
ce1a1df49c35 arm64: dts: qcom: qcs6490-rb3gen2-vision-mezzanine: Add vision mezzanine
ef593efe4221 arm64: dts: qcom: sc7280: Add support for camss
81f54e00f40f arm64: dts: qcom: ipq9574: Fix USB vdd info
a2f9aa17c719 arm64: dts: qcom: qcm6490-idp: Update protected clocks list
f1964aec801b arm64: dts: qcom: x1e78100-t14s: fix missing HID supplies
efe9b44f4f23 arm64: dts: qcom: x1e80100-qcp: mark l12b and l15b always-on
65f57c317bff arm64: dts: qcom: x1e80100-yoga-slim7x: mark l12b and l15b always-on
4df0b435b8ce arm64: dts: qcom: x1e80100-hp-x14: mark l12b and l15b always-on
40cf0d330276 arm64: dts: qcom: x1e80100-dell-xps13-9345: mark l12b and l15b always-on
62a8ce218aa0 arm64: dts: qcom: x1e001de-devkit: mark l12b and l15b always-on
53e58f66f64f arm64: dts: qcom: x1e78100-t14s: mark l12b and l15b always-on
52f17b4830b6 arm64: dts: qcom: x1e80100-crd: mark l12b and l15b always-on
2e0f9145b47e arm64: dts: qcom: sc8280xp-crd: add support for volume-up key
8555fbf8367f arm64: dts: qcom: x1e80100-crd: Drop duplicate DMIC supplies
715f877e8303 arm64: dts: qcom: sc8280xp-x13s: Drop duplicate DMIC supplies
1991771e2f0d arm64: dts: qcom: x1e78100-t14s: Add OLED variant
2d3002b4a49d arm64: dts: qcom: x1e78100-t14s: Add LCD variant with backlight support
fb84b985b331 dt-bindings: arm: qcom: Document Lenovo ThinkPad T14s Gen 6 LCD and OLED
34f18fc9f9a9 arm64: dts: qcom: qcm6490-fairphone-fp5: Add touchscreen node
0fc33da859aa arm64: dts: qcom: sm8750: Correct clocks property for uart14 node
e392ce11427f arm64: dts: qcom: qcs6490-rb3gen2: Add orientation gpio
265874138759 arm64: dts: qcom: ipq5424: add reserved memory region for bootloader
3bb2a608664d arm64: dts: qcom: qcs8300: Add device node for gfx_smmu
4ea98a741024 arm64: dts: qcom: qcs8300-ride: Enable second USB controller on QCS8300 Ride
dc6e06f3ca59 arm64: dts: qcom: sm8250: Fix CPU7 opp table
2ea8db25021b arm64: dts: qcom: x1e80100-crd: add gpio-keys label for lid switch
05a7db3bd663 arm64: dts: qcom: x1e80100-crd: add support for volume-up key
804469542c98 arm64: dts: qcom: x1e001de-devkit: Drop clock-names from PS8830
cf004f327add arm64: dts: qcom: x1e80100-romulus: Drop clock-names from PS8830
ae4ea2fc84d5 arm64: dts: qcom: x1e80100-dell-xps13-9345: Drop clock-names from PS8830
8f90f22d05b4 arm64: dts: qcom: sc8180x: Rename AOSS_QMP to power-management
76cf4114ff7b arm64: dts: qcom: qcs615: Rename AOSS_QMP to power-management
b5c3438db8ee arm64: dts: qcom: sdx75: Rename AOSS_QMP to power-management
c7537e0429c8 arm64: dts: qcom: sdx75: Fix up the USB interrupt description
b0786b5d200c arm64: dts: qcom: ipq9574: Remove eMMC node
c1d9b6d09198 arm64: dts: qcom: ipq9574: Enable SPI NAND for ipq9574
494f401c3e8c arm64: dts: qcom: ipq9574: Add SPI nand support
0800cd2ac181 arm64: dts: qcom: sm6125: Initial support for xiaomi-ginkgo
44f77eafc733 dt-bindings: arm: qcom: Add Xiaomi Redmi Note 8
7076352823cc arm64: dts: qcom: sc7280: drop video decoder and encoder nodes
52bfe54b74fa arm64: dts: qcom: sa8775p: Add CTCU and ETR nodes
498de1e01884 arm64: dts: qcom: qrb5165-rb5: add compressed playback support
773069e8ecaf arm64: dts: qcom: sm8650: add PPI interrupt partitions for the ARM PMUs
07ddcafd37f3 arm64: dts: qcom: sm8650: switch to interrupt-cells 4 to add PPI partitions
652b5ebbff21 ARM: dts: qcom: msm8960: Add thermal sensor (tsens)
3278100c97aa arm64: dts: qcom: qcs615: add TRNG node
bb2b0cc8d9a8 arm64: dts: qcom: sm8750: Fix cluster hierarchy for idle states
c1a73ba7c1cf arm64: dts: qcom: sm8450: add PCIe EP device nodes
718439f6e82d arm64: dts: qcom: sar2130p: add PCIe EP device nodes
9cf55d5faba5 arm64: dts: qcom: Drop `tx-sched-sp` property
568f3c8b2b5d ARM: dts: qcom: msm8960: Add BAM
ab027c48e4ad arm64: dts: qcom: msm8917-xiaomi-riva: Add display backlight
2138fc94be48 arm64: dts: qcom: pm8937: Add LPG PWM driver
e91a4033e4ce arm64: dts: qcom: ipq9574: fix the msi interrupt numbers of pcie3
38691f9d0837 arm64: dts: qcom: ipq9574: Add missing properties for cryptobam
be1438b63f67 arm64: dts: qcom: sa8775p: Add missing properties for cryptobam
66b846921c08 arm64: dts: qcom: sm8650: Add missing properties for cryptobam
2dac12521235 arm64: dts: qcom: sm8550: Add missing properties for cryptobam
fdc35bd52bc8 arm64: dts: qcom: sm8450: Add missing properties for cryptobam
4a32c2aa8f4e arm64: dts: qcom: sm8350: Reenable crypto & cryptobam
52d68253ad12 arm64: dts: qcom: sm8750-qrd: Enable CDSP
c82aa2b08a97 arm64: dts: qcom: sm8750-mtp: Enable CDSP
5f73938ce2e7 arm64: dts: qcom: sm8750: Add CDSP
9cd9e329ed44 arm64: dts: qcom: sm8750-qrd: Enable ADSP
9f7809fb268c arm64: dts: qcom: sm8750-mtp: Enable ADSP
daf1a64625c6 arm64: dts: qcom: sm8750: Add LPASS macro codecs and pinctrl
ffabaffd686a arm64: dts: qcom: sm8750: Add IPCC, SMP2P, AOSS and ADSP
e4c81cca30eb arm64: dts: qcom: ipq5424: Enable MMC
add2c5457210 arm64: dts: qcom: sm8750: Add ICE nodes
732dd897ea8f arm64: dts: qcom: sm8750: Add TRNG nodes
918bf155967b arm64: dts: qcom: sm8750: Add QCrypto nodes
1b23fab56ee1 arm64: dts: qcom: Use recommended MBN firmware path
c08efec1e5aa dt-bindings: display: simple: Add POWERTIP PH128800T004-ZZA01 panel
0b314a523a02 arm64: dts: qcom: sdm845-starqltechn: add touchscreen support
53102db27a11 arm64: dts: qcom: sdm845-starqltechn: add display PMIC
ff7fcf3adb6f arm64: dts: qcom: sdm845-starqltechn: add max77705 PMIC
3548ab694bac arm64: dts: qcom: sdm845-starqltechn: add gpio keys
e999ae3e334e arm64: dts: qcom: sdm845-starqltechn: remove excess reserved gpios
eccbdc90a7a6 arm64: dts: qcom: sdm845-starqltechn: refactor node order
c40aa640a72e arm64: dts: qcom: sdm845-starqltechn: fix usb regulator mistake
53c6b51bd2f3 arm64: dts: qcom: sdm845-starqltechn: remove wifi
8016d08c4ee4 arm64: dts: qcom: sdm845: enable gmu
7558c172ac2c arm64: dts: qcom: x1e80100-t14s: Enable external DisplayPort support
c8b1cf4d58de arm64: dts: qcom: x1e80100-t14s: Describe the Parade PS8830 retimers
e8f48aa148c3 arm64: dts: qcom: x1e80100-crd: Enable external DisplayPort support
12953b040829 arm64: dts: qcom: x1e80100-crd: Describe the Parade PS8830 retimers
1c12f1a1c5e0 arm64: dts: qcom: x1e80100-romulus: Keep L12B and L15B always on
cd6009eec380 arm64: dts: qcom: sm8650: add all 8 coresight ETE nodes
08f0a5fbfb5c arm64: dts: qcom: x1e80100-qcp: Add WiFi/BT pwrseq
c86a96b79dc4 arm64: dts: qcom: sm8750: Add RPMh sleep stats
b6ad871ee6ae arm64: dts: qcom: Correct white-space style
80b421a10451 arm64: dts: qcom: sm8750: Change labels to lower-case
deee6d373e3f arm64: dts: qcom: sdm632-fairphone-fp3: Enable modem
e919ef3dc364 arm64: dts: qcom: sdm632-fairphone-fp3: Add firmware-name for adsp & wcnss
56e365fe287f arm64: dts: qcom: sdm632-fairphone-fp3: Add newlines between regulator nodes
50e52f7993e6 arm64: dts: qcom: sdm632-fairphone-fp3: Move status properties last
0f637990483d arm64: dts: qcom: qcs615: Add Command DB support
c2141cabcc17 arm64: dts: qcom: sm8250-elish: Switch to undeprecated qcom,calibration-variant
ec526e787936 arm64: dts: qcom: sc8280xp: Switch to undeprecated qcom,calibration-variant
5360722ae36a arm64: dts: qcom: sa8775p-ride: Switch to undeprecated qcom,calibration-variant
7f183e0e4b2a arm64: dts: qcom: qcm6490: Switch to undeprecated qcom,calibration-variant
20ccf83f7dc8 arm64: dts: qcom: sm8150-hdk: Switch to undeprecated qcom,calibration-variant
a2aae9258894 arm64: dts: qcom: sm6115: Switch to undeprecated qcom,calibration-variant
bc753687cc11 arm64: dts: qcom: sda660-ifc6560: Switch to undeprecated qcom,calibration-variant
766ecec7fc27 arm64: dts: qcom: sdm845: Switch to undeprecated qcom,calibration-variant
b81275ed77c7 arm64: dts: qcom: sc7180: Switch to undeprecated qcom,calibration-variant
003514422bb8 arm64: dts: qcom: qrb4210-rb2: Switch to undeprecated qcom,calibration-variant
372494e32ec5 arm64: dts: qcom: qrb2210-rb1: Switch to undeprecated qcom,calibration-variant
3d7f887f925f arm64: dts: qcom: msm8998: Switch to undeprecated qcom,calibration-variant
2a6360a0bcaa ARM: dts: qcom: ipq4018: Switch to undeprecated qcom,calibration-variant
711fd3c53856 arm64: dts: qcom: x1e80100-qcp: Enable HBR3 on external DPs
458ec1a15657 arm64: dts: qcom: x1e80100-hp-x14: Enable HBR3 on external DPs
d6a6bfedf9ae arm64: dts: qcom: x1e001de-devkit: Enable HBR3 on external DPs
f8e50df5d86b arm64: dts: qcom: x1e80100-dell-xps13-9345: Enable external DP support
ae23d69c45b0 arm64: dts: qcom: sdm845-db845c-navigation-mezzanine: Drop CMA heap
8e96ef991250 arm64: dts: qcom: qrb5165-rb5-vision-mezzanine: Drop CMA heap
4b367fd64b02 arm64: dts: qcom: x1e80100: Drop unused passive thermal trip points for CPU
ebf1f1e6c385 arm64: dts: qcom: x1e80100: Add GPU cooling
1cd853d3e939 arm64: dts: qcom: x1e80100: Apply consistent critical thermal shutdown
989e32428df3 arm64: dts: qcom: x1e80100: Fix video thermal zone
9eb704b5190c arm64: dts: qcom: sm8650: add missing cpu-cfg interconnect path in the mdss node
b254425701f6 arm64: dts: qcom: sm8550: add missing cpu-cfg interconnect path in the mdss node
a7f79cd2cb8c arm64: dts: qcom: x1e80100-slim7x: Drop incorrect qcom,ath12k-calibration-variant
a9f8c3d91d5b arm64: dts: qcom: qcs8300: Partially revert "arm64: dts: qcom: qcs8300: add QCrypto nodes"
86e24dafc90b arm64: dts: qcom: sa8775p: Partially revert "arm64: dts: qcom: sa8775p: add QCrypto nodes"
06c923231f08 arm64: dts: qcom: sdm630: Add missing resets to mmc blocks
25333fee1f77 Merge branch '20250203063427.358327-2-alexeymin@postmarketos.org' into arm64-for-6.15
7b608006630d arm64: dts: qcom: sm8650: add UFS OPP table instead of freq-table-hz property
0e0842f4df4b arm64: dts: qcom: sm8650: add QUP serial engines OPP tables
93cb0237bce4 arm64: dts: qcom: sm8650: add OPP table support to PCIe
ca623f9ea777 arm64: dts: qcom: sm8650: add USB interconnect paths
f839c213fc9c arm64: dts: qcom: sm8650: set CPU interconnect paths as ACTIVE_ONLY
e53196775ca4 arm64: dts: qcom: sm8650: use ICC tag for IPA interconnect phandles
706f8f120ead arm64: dts: qcom: sm8550: add QUP serial engines OPP tables
967498cd6d5c arm64: dts: qcom: sm8550: add OPP table support to PCIe
9642703be003 arm64: dts: qcom: sm8550: set CPU interconnect paths as ACTIVE_ONLY
ee0cb175c65e arm64: dts: qcom: sm8550: use ICC tag for all interconnect phandles
ca70a7700ecf arm64: dts: qcom: qcm6490-fairphone-fp5: Enable the GPU
eb752ff527d3 arm64: dts: qcom: qcm6490-fairphone-fp5: Enable display
1d95c3da8c55 arm64: dts: qcom: sm7325-nothing-spacewar: Enable camera EEPROMs
dc2ab4600182 arm64: dts: qcom: sm7325-nothing-spacewar: Add CAM fixed-regulators
4ba736c0dcd3 arm64: dts: qcom: sm8650: drop remaining polling-delay-passive properties
4ec33ea53ea8 arm64: dts: qcom: sm8650: harmonize all unregulated thermal trip points
ef1efd695a2e arm64: dts: qcom: sm8650: setup gpu thermal with higher temperatures
8f99a70eeaf5 arm64: dts: qcom: sm8650: drop cpu thermal passive trip points
b2141c8af961 arm64: dts: qcom: Add X1P42100 SoC and CRD
536623483d06 arm64: dts: qcom: Commonize X1 CRD DTSI
f41f13783cb5 arm64: dts: qcom: x1e80100: Wire up PCIe PHY NOCSR resets
e57b76ee802c arm64: dts: qcom: qcs8300: Add QUPv3 configuration
736071f5b962 arm64: dts: qcom: ipq5424: Add thermal zone nodes
eb736b571ca1 arm64: dts: qcom: ipq5424: Add tsens node
8198b0084ab9 arm64: dts: qcom: ipq5332: Add thermal zone nodes
3009d9c8d08e arm64: dts: qcom: ipq5332: Add tsens node
1c84ea51ce71 arm64: dts: qcom: ipq6018: add LDOA2 regulator
747916e6b00a arm64: dts: qcom: ipq6018: rename labels of mp5496 regulator
863c608cd0b9 arm64: dts: qcom: ipq6018: move mp5496 regulator out of soc dtsi
da4ec8d0edbc arm64: dts: qcom: ipq6018: add 1.5GHz CPU Frequency
80e82218d6e1 arm64: dts: qcom: ipq6018: add 1.2GHz CPU Frequency
19ceff512d98 arm64: dts: qcom: sa8775p-ride: Add firmware-name in BT node
57a9930fcd81 arm64: dts: qcom: x1e80100: Mark usb_2 as dma-coherent
1237cb4eccbd arm64: dts: qcom: qrb5165-rb5: enable sensors DSP
1f5e82091632 arm64: dts: qcom: sdm845-db845c: enable sensors DSP
faf34ece59aa arm64: dts: qcom: sc8280xp: Fix clock for spi0 to spi7
94a09b9504e4 arm64: dts: qcom: qcs8300-ride: Enable PMIC peripherals
94da6d6bf1fe arm64: dts: qcom: qcs8300: Adds SPMI support
79bffbd44317 ARM: dts: qcom: Fix indentation errors
233806c3ca1d arm64: dts: qcom: qcm2290: Add uart3 node
e10add854aaa arm64: dts: qcom: qcs6490-rb3gen2: add and enable BT node
eabcc9205de0 arm64: dts: qcom: sm8650: add cpu OPP table with DDR, LLCC & L3 bandwidths
2f231a9d2e0f arm64: dts: qcom: sm8650: add cpu interconnect nodes
6eedd85983ed arm64: dts: qcom: sm8650: add OSM L3 node
6e335b12f60e arm64: dts: qcom: x1e80100: Add the watchdog device
b926cb91094d arm64: dts: qcom: qcs6490-rb3gen2: Add vadc and adc-tm channels
cb00ad63e5ce arm64: dts: qcom: sc8280xp-pmics: Add more temp-alarm devices
bb44fe9e84d2 arm64: dts: qcom: sc8280xp-pmics: Fix slave ID in interrupts configuration
668f6b1e8012 arm64: dts: qcom: x1e80100: Set CPU interconnect paths as ACTIVE_ONLY

git-subtree-dir: dts/upstream
git-subtree-split: d08867ef8f12adb80b84725a5e82538a5ca46a12
2025-07-30 08:23:25 -06:00
Tom Rini
9773b27e12 Merge patch series "rockchip: puma-rk3399: anticipate breakage with v6.16 DT"
Quentin Schulz <foss+uboot@0leil.net> says:

Due to updates to the Device Tree (migrating to onboard USB hub nodes
instead of (badly) hacking things with a gpio regulator that doesn't
actually work properly), we now need to enable the onboard USB hub
driver in U-Boot.

This anticipates upcoming breakage when 6.16 DT will be merged into
U-Boot's dts/upstream.

The series can be applied as is before v6.16 DT is merged or only the
defconfig changes after 6.16 DT has been merged.

The last two patches are simply to avoid probing devices that aren't
actually routed on RK3399 Puma, which is nice to have but doesn't fix
anything.

Note that this depends on the following series:
https://lore.kernel.org/u-boot/20250722-usb_onboard_hub_cypress_hx3-v4-0-91c3ee958c0e@thaumatec.com/

Link: https://lore.kernel.org/r/20250730-puma-usb-cypress-v1-0-b1c203c733f9@cherry.de
2025-07-30 08:23:01 -06:00
Quentin Schulz
e12e9320a3 arm64: dts: rockchip: disable unrouted USB controllers and PHY on RK3399 Puma with Haikou
The u2phy0_host port is the part of the USB PHY0 (namely the
HOST0_DP/DM lanes) which routes directly to the USB2.0 HOST
controller[1]. The other lanes of the PHY are routed to the USB3.0 OTG
controller (dwc3), which we do use.

The HOST0_DP/DM lanes aren't routed on RK3399 Puma so let's simply
disable the USB2.0 controllers.

USB3 OTG has been known to be unstable on RK3399 Puma Haikou for a
while, one of the recurring issues being that only USB2 is detected and
not USB3 in host mode. Reading the justification above and seeing that
we are keeping u2phy0_host in the Haikou carrierboard DTS probably may
have bothered you since it should be changed to u2phy0_otg. The issue is
that if it's switched to that, USB OTG on Haikou is entirely broken. I
have checked the routing in the Gerber file, the lanes are going to the
expected ball pins (that is, NOT HOST0_DP/DM).
u2phy0_host is for sure the wrong part of the PHY to use, but it's the
only one that works at the moment for that board so keep it until we
figure out what exactly is broken.

No intended functional change.

[1] https://rockchip.fr/Rockchip%20RK3399%20TRM%20V1.3%20Part2.pdf
    Chapter 2 USB2.0 PHY

Fixes: 2c66fc34e945 ("arm64: dts: rockchip: add RK3399-Q7 (Puma) SoM")
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Signed-off-by: Lukasz Czechowski <lukasz.czechowski@thaumatec.com>
Link: https://lore.kernel.org/r/20250425-onboard_usb_dev-v2-5-4a76a474a010@thaumatec.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

[ upstream commit: febd8c6ab52c683b447fe22fc740918c86feae43 ]

(cherry picked from commit 0a0ebebfdd4558512675e1aff34bddb770086cb0)
2025-07-30 08:23:00 -06:00
Quentin Schulz
d0681cf0c8 arm64: dts: rockchip: disable unrouted USB controllers and PHY on RK3399 Puma
The u2phy1_host port is the part of the USB PHY1 (namely the
HOST1_DP/DM lanes) which routes directly to the USB2.0 HOST
controller[1]. The other lanes of the PHY are routed to the USB3.0 OTG
controller (dwc3), which we do use.

The HOST1_DP/DM lanes aren't routed on RK3399 Puma so let's simply
disable the USB2.0 controllers and associated part in USB2.0 PHY.

No intended functional change.

[1] https://rockchip.fr/Rockchip%20RK3399%20TRM%20V1.3%20Part2.pdf
    Chapter 2 USB2.0 PHY

Fixes: 2c66fc34e945 ("arm64: dts: rockchip: add RK3399-Q7 (Puma) SoM")
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Signed-off-by: Lukasz Czechowski <lukasz.czechowski@thaumatec.com>
Link: https://lore.kernel.org/r/20250425-onboard_usb_dev-v2-4-4a76a474a010@thaumatec.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

[ upstream commit: 3373af1d76bacd054b37f3e10266dd335ce425f8 ]

(cherry picked from commit 97640da1f41d022484c1a4725bed943a5ae56073)
2025-07-30 08:23:00 -06:00
Lukasz Czechowski
6dd61725a2 arm64: dts: rockchip: fix internal USB hub instability on RK3399 Puma
Currently, the onboard Cypress CYUSB3304 USB hub is not defined in
the device tree, and hub reset pin is provided as vcc5v0_host
regulator to usb phy. This causes instability issues, as a result
of improper reset duration.

The fixed regulator device requests the GPIO during probe in its
inactive state (except if regulator-boot-on property is set, in
which case it is requested in the active state). Considering gpio
is GPIO_ACTIVE_LOW for Puma, it means it’s driving it high. Then
the regulator gets enabled (because regulator-always-on property),
which drives it to its active state, meaning driving it low.

The Cypress CYUSB3304 USB hub actually requires the reset to be
asserted for at least 5 ms, which we cannot guarantee right now
since there's no delay in the current config, meaning the hub may
sometimes work or not. We could add delay as offered by
fixed-regulator but let's rather fix this by using the proper way
to model onboard USB hubs.

Define hub_2_0 and hub_3_0 nodes, as the onboard Cypress hub
consist of two 'logical' hubs, for USB2.0 and USB3.0.
Use the 'reset-gpios' property of hub to assign reset pin instead
of using regulator. Rename the vcc5v0_host regulator to
cy3304_reset to be more meaningful. Pin is configured to
output-high by default, which sets the hub in reset state
during pin controller initialization. This allows to avoid double
enumeration of devices in case the bootloader has setup the USB
hub before the kernel.
The vdd-supply and vdd2-supply properties in hub nodes are
added to provide correct dt-bindings, although power supplies are
always enabled based on HW design.

Fixes: 2c66fc34e945 ("arm64: dts: rockchip: add RK3399-Q7 (Puma) SoM")
Cc: stable@vger.kernel.org # 6.6
Cc: stable@vger.kernel.org # Backport of the patch in this series fixing product ID in onboard_dev_id_table in drivers/usb/misc/onboard_usb_dev.c driver
Signed-off-by: Lukasz Czechowski <lukasz.czechowski@thaumatec.com>
Link: https://lore.kernel.org/r/20250425-onboard_usb_dev-v2-3-4a76a474a010@thaumatec.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

[ upstream commit: d7cc532df95f7f159e40595440e4e4b99481457b ]

(cherry picked from commit 0fe42d171081426ab119ca5c0eb130e5f3a9a805)
2025-07-30 08:23:00 -06:00
Lukasz Czechowski
c419fd8134 dt-bindings: usb: cypress,hx3: Add support for all variants
The Cypress HX3 hubs use different default PID value depending
on the variant. Update compatibles list.
Becasuse all hub variants use the same driver data, allow the
dt node to have two compatibles: leftmost which matches the HW
exactly, and the second one as fallback.

Fixes: 1eca51f58a10 ("dt-bindings: usb: Add binding for Cypress HX3 USB 3.0 family")
Cc: stable@vger.kernel.org # 6.6
Cc: stable@vger.kernel.org # Backport of the patch ("dt-bindings: usb: usb-device: relax compatible pattern to a contains") from list: https://lore.kernel.org/linux-usb/20250418-dt-binding-usb-device-compatibles-v2-1-b3029f14e800@cherry.de/
Cc: stable@vger.kernel.org # Backport of the patch in this series fixing product ID in onboard_dev_id_table in drivers/usb/misc/onboard_usb_dev.c driver
Signed-off-by: Lukasz Czechowski <lukasz.czechowski@thaumatec.com>
Reviewed-by: "Rob Herring (Arm)" <robh@kernel.org>
Link: https://lore.kernel.org/r/20250425-onboard_usb_dev-v2-2-4a76a474a010@thaumatec.com
[taken with Greg's blessing]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

[ upstream commit: 1ad4b5a7de16806afc1aeaf012337e62af04e001 ]

(cherry picked from commit 53aacaed0ad140b017c803d9777473c6c62f5352)
2025-07-30 08:23:00 -06:00
Quentin Schulz
7c0491ccc6 dt-bindings: usb: usb-device: relax compatible pattern to a contains
The dt-core typically allows multiple compatibles[1] but usb-device
currently forces a single compatible.

This is an issue when multiple devices with slightly different productID
all behave the same. This would require the driver to keep updating its
compatible matching table to include this new productID instead of doing
what is usually done: have two compatibles, the leftmost which matches
exactly the HW device definition, and the rightmost one as a fallback
which is assumed to be 100% compatible with the device at hand. If this
assumption turns out to be wrong, it is easy to work around this without
having to modify the device tree by handling the leftmost compatible in the driver.

[1] https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/dt-core.yaml#L21-L25

Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250418-dt-binding-usb-device-compatibles-v2-1-b3029f14e800@cherry.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

[ upstream commit: 495df45f38c8ba3d74c3180a0a13a0ecbfa717d1 ]

(cherry picked from commit 932da7a8df7b6b43453d640b383d0076d5a7d9a5)
2025-07-30 08:23:00 -06:00
Quentin Schulz
7810d079ad configs: puma-rk3399: enable onboard USB hub support
Since commit
https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git/commit/?id=0fe42d171081426ab119ca5c0eb130e5f3a9a805
RK3399 Puma now models the onboard USB hub properly via onboard USB hub
device nodes with appropriate reset and power supplies instead of
hacking things around (a hack that didn't even work reliably).

This means this driver needs to be enabled in U-Boot as well otherwise
USB will stop working at all.

Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
2025-07-30 08:23:00 -06:00
Tom Rini
300b49a07d Merge patch series "rockchip: ringneck-px30: anticipate breakage with v6.16-rc1 DT"
Quentin Schulz <foss+uboot@0leil.net> says:

v6.16-rc1 will bring an incompatible change to the Device Tree of PX30
Ringneck which will break Ethernet support.

Unfortunately, the designware net driver's logic doesn't seem to allow
having the old Device Tree (without MDIO bus and Ethernet PHY nodes)
with DM_MDIO and DM_ETH_PHY enabled so there cannot be a smooth
transition.

Since this is going to bite me in a few months time, let's just break
and fix it now in a couple of commits so I don't have to think about it
later :)

This can be cleanly applied on master or next, I have absolutely zero
preference on the branch this should be merged in (my opinion is that
it's too late in the 2024.07 cycle to bring this in :) ).

Link: https://lore.kernel.org/r/20250611-ringneck-mdio-v1-0-529a40a0f966@cherry.de
2025-07-30 08:21:00 -06:00
Quentin Schulz
21c3a37f07 configs: ringneck-px30: fix Ethernet
Due to updates to the Device Tree (migrating from snps,reset-*
properties to a PHY node on the MDIO bus) in previous commits and the
inability of the designware net driver to support the old Device Tree
(without the MDIO bus and PHY nodes) with DM_MDIO and DM_ETH_PHY
enabled, support for Ethernet on Ringneck PX30 is currently broken.

Now that the transition was made, we can simply enable DM_MDIO and
DM_ETH_PHY to fix Ethernet support on that board. Ideally, we could
squash this commit with the one migrating the Device Tree, but we want
to keep having upstream changes to the Device Trees made by
tools/update-subtree.sh tool without manual intervention.

Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
2025-07-30 08:20:51 -06:00
Heiko Stuebner
8279df493c arm64: dts: rockchip: move reset to dedicated eth-phy node on ringneck
Using snps,reset-* properties to handle the ethernet-phy resets is
deprecated and instead a real phy node should be used.

Move the Ringneck phy-reset properties to such a node

Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Tested-by: Quentin Schulz <quentin.schulz@cherry.de>
Link: https://lore.kernel.org/r/20250514150745.2437804-3-heiko@sntech.de
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

[ upstream commit: e463625af7f92c4a9f097f7fb87f6baaad6e762a ]

(cherry picked from commit 76d0d8e00c9ac845ca8d6cbe191cf015ca3a8c16)

Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
2025-07-30 08:20:51 -06:00
Heiko Stuebner
b279bd7282 arm64: dts: rockchip: add basic mdio node to px30
Using snps,reset-* properties for handling the phy-reset is deprecated
and instead a real phy node should be defined that then contains the
reset-gpios handling.

To facilitate this, add the core mdio node under the px30's gmac, similar
to how the other Rockchip socs already do this.

Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Link: https://lore.kernel.org/r/20250514150745.2437804-2-heiko@sntech.de
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

[ upstream commit: ede4837a504ca7e5811217060aa8300b8d0cf7f2 ]

(cherry picked from commit cb54a264ecdb9e95b1529e4542e157cb9acded30)

Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
2025-07-30 08:20:51 -06:00
Tom Rini
6549dbfd26 Merge patch series "Extend usb_onboard_hub driver to support Cypress HX3 hub family"
Lukasz Czechowski <lukasz.czechowski@thaumatec.com> says:

This patch series extends the usb_onboard_hub driver to allow for
support of more types of onboard hub devices, and adds the Cypress HX3
hub family.

First patch in the series updates the bind function, so that it no
longer uses hardcoded compatible strings.
Next patch simplifies the code, by removing unnecessary dm_gpio function
call.
Third patch updates the remove function, which allows the prevent issues
with usb devices reenumeration, in case of calling "usb reset". Although
the issue could still occur in case of invalid initial state of reset
gpio, it is minimized with no impact on main usb_hub driver.
Fourth patch extends the driver with support for multiple power
supplies, the same way it is done in kernel driver.  Finally, last patch
provides hub data and of_match table entries for Cypress HX3

Link: https://lore.kernel.org/r/20250722-usb_onboard_hub_cypress_hx3-v4-0-91c3ee958c0e@thaumatec.com
2025-07-30 08:20:35 -06:00
Lukasz Czechowski
a1f8103bbe usb: onboard-hub: Add support for Cypress HX3 family
The HX3 is a family of USB3.0 hub controllers that comes in
different variants: CYUSB330x/CYUSB331x/CYUSB332x/CYUSB230x.
To support this hub, controlling of reset pin and two
power supplies is required.
The reset time is set to 10ms, based on the datasheet [1].
Power-on delay time is not required, so it is set to 0.
The compatible strings added to of_match table are
compliant with usb/cypress,hx3.yaml bindings.

[1] https://www.infineon.com/dgdl/Infineon-HX3_USB_3_0_Hub_Consumer_Industrial-DataSheet-v22_00-EN.pdf?fileId=8ac78c8c7d0d8da4017d0ecb53f644b8

Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Signed-off-by: Lukasz Czechowski <lukasz.czechowski@thaumatec.com>
2025-07-30 07:57:17 -06:00
Lukasz Czechowski
3eb6b0f504 usb: onboard-hub: Add support for multiple power supplies
Some of the onboard hubs require multiple power supplies, so extend
the driver to support them.
The implementation is inspired by the kernel driver, as introduced
by commit [1] in the v6.10 kernel.

[1] ec1848cd5d

Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Signed-off-by: Lukasz Czechowski <lukasz.czechowski@thaumatec.com>
2025-07-30 07:57:17 -06:00
Lukasz Czechowski
42a025412d usb: onboard-hub: Set the reset gpio pin before freeing
In the usb_onboard_hub_remove, the reset gpio, if available, is
freed. The pin state however, remains unchanged, as set in the
usb_onboard_hub_reset. The hub is then left enabled.

During second onboard hub probing, the hub is initially enabled
(reset pin in state "0"), and then it is being reset by the reset
function (transition to "1" and then to "0"). Because of this,
the hub first disconnects from root hub, and then it connects again.

When the devices are being discovered in the usb_scan_port in the
usb_hub driver, initially there is the USB_PORT_STAT_CONNECTION bit
not set in portstatus, but USB_PORT_STAT_C_CONNECTION set in
portchange data (which is because disconnect event occurred first).
In this condition, the driver does not wait for devices to appear.
This can cause the hub (and all child devices) to be not enumerated
when rescanning on "usb reset" command.

To fix this, set the reset gpio to active in usb_onboard_hub_remove,
to put the hub into reset state.
However, in case the hub reset pin is by default held in high
state by HW before U-Boot takes over, in which case the USB hub is
active, then during the first probe it gets reset and we might get
into the same issue of the hub being not enumerated.

Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Signed-off-by: Lukasz Czechowski <lukasz.czechowski@thaumatec.com>
2025-07-30 07:57:17 -06:00
Lukasz Czechowski
480753ca92 usb: onboard-hub: Use devm API do automatically free the reset GPIO
The reset GPIO is obtained during driver probing by the function
devm_gpiod_get_optional, which means the GPIO will be automatically
freed when the device is removed. Because of this, explicit call
to free the reset GPIO in hub remove function is not needed.
To support the Managed device resources, the DEVRES config must
be enabled, otherwise the devres functions fall back to non-managed
variants. Set the necessary dependency to DEVRES in Kconfig.

Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Signed-off-by: Lukasz Czechowski <lukasz.czechowski@thaumatec.com>
2025-07-30 07:57:17 -06:00
Lukasz Czechowski
a4446e13db usb: onboard-hub: Use the ofnode to check if the peer-hub was probed
Currently the check in usb_onboard_hub_bind is relying on specific
compatible string for the Michrochip USB5744. Replace this with
more generic approach that will allow to add new types of devices
to the of_match table. Because the driver only needs to bind one
"half" of the hub, the peer-hub node is used to find out if it
was already done. In case peer-hub was bound, -ENODEV is returned.

Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Signed-off-by: Lukasz Czechowski <lukasz.czechowski@thaumatec.com>
2025-07-30 07:57:17 -06:00
Tom Rini
bb708e8249 Merge tag 'u-boot-watchdog-20250730' of https://source.denx.de/u-boot/custodians/u-boot-watchdog
CI: https://dev.azure.com/sr0718/u-boot/_build/results?buildId=395&view=results

- watchdog for STM32MP family updates (Antonio, Clément and Patrice)
2025-07-30 07:53:46 -06:00
Patrice Chotard
e064db5fe7 reset: stm32: Fix set_clr field
STM32F4/F7 and H7 series doesn't have a clear reset register, so
set_clr field must be set to false.

Fixes: 0994a627c2 ("reset: stm32mp25: add stm32mp25 reset driver")

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2025-07-30 14:55:17 +02:00
Dinesh Maniyam
4064e7c9fc socfpga_agilex5: config: Relocate malloc and bss address
With Inline ECC enabled, the bottom 1/8 of DDR is reserved
for ECC parity bits and must not be used for general data address
allocation. Previously, the SPL bss and malloc addresses were allocated
inside this ECC parity region if the DDR size is 1GB.

This caused ECC hardware to detect stale or invalid parity bits,
leading to data correction attempts and DMA polling hangs or failures.

Fix this by relocating the malloc and bss to the usable 7/8 region of DDR
and is fully ECC-safe.

This change ensures reliable ddr address operation and
prevents unintended memory corruption.

Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-07-30 17:45:31 +08:00
Dinesh Maniyam
169039f4f1 configs: socfpga: soc64: agilex5: Enable NAND boot with UBI / UBIFS
Add the required configuration in the U-Boot env to enable Linux NAND
boot with UBI / UBIFS.

Signed-off-by: Dinesh Maniyam <dinesh.maniyam@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-07-30 17:45:31 +08:00
Alif Zakuan Yuslaimi
9f68908686 arch: arm: agilex5: Enable power manager for Agilex5
Agilex5 FSBL is required to disable the power of unused peripheral SRAM
blocks to reduce power consumption.

Introducing a new power manager driver for Agilex5 which will be called
as part of Agilex5 SPL initialization process.

This driver will read the peripheral handoff data obtained from the
bitstream and will power off the specified peripheral's SRAM from the
handoff data values.

Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-07-30 17:45:31 +08:00
Tingting Meng
5119cffaf4 arm: socfpga: agilex5: Sub-device check enabled for runtime workaround
Sub-device information is retrieved from the JTAG ID in Boot Scratch
Cold 4 Register. This interface is introduced to allow device-specific
errata workarounds to be applied in the future, based on the detected
sub-device type.

Signed-off-by: Tingting Meng <tingting.meng@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2025-07-30 17:45:30 +08:00
Tingting Meng
8eb3812c58 arm: socfpga: agilex5: Coverity issue cleanup in jtag_usercode check
A redundant comparison (jtag_usercode >= 0) was removed from the
condition checking jtag_usercode. Since jtag_usercode is an unsigned
integer, the check for non-negativity was always true. The code was
simplified to resolve the Coverity warning.

Signed-off-by: Tingting Meng <tingting.meng@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2025-07-30 17:45:30 +08:00
Andrew Goodbody
6e1cc5d861 socfpga_dtreg: Ensure reg is initialised before use
In socfpga_dtreg_probe it is possible that if mask is 0 then reg will
not be assigned to before first use. Refactor the code slightly to
ensure that reg is always assigned to and remove a piece of duplicated
code.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-07-30 17:45:30 +08:00
Dinesh Maniyam
344d785aba dts: agilex5: Enabled nand boot in SPL
Enable nand as one of the bootable media in SPL.

Signed-off-by: Dinesh Maniyam <dinesh.maniyam@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-07-30 17:45:30 +08:00
Andrew Goodbody
5a13fa7c66 ddr: altera: n5x: size_t cannot be less than 0
The function socfpga_get_handoff_size returns an int so make the struct
fields used to accept the return value also an int so that testing for
less than 0 is then valid.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-07-30 17:45:29 +08:00
Andrew Goodbody
dff25bb4ab clk: n5x: Fix misplaced paren
Smatch reported an issue about the precedence of shift being higher than
mask in clk_get_emac_clk_hz. This turned out to be a misplaced paren in
one of the calculations. Fix this by placing the paren in the same place
as in the other similar calculations in the same function.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-07-30 17:45:29 +08:00
Naresh Kumar Ravulapalli
b9767ad357 arm: socfpga: n5x: Remove invalid configuration for N5X
This configuration is not valid for N5X; removing it.

Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>
Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-07-30 17:45:28 +08:00
Andrew Goodbody
f4aa24af69 arm: socfpga: Remove unnecessary for loop
The for loop in fpgamgr_program_poll_cd will always terminate after a
single pass and so is not necessary. Remove it and all related code and
leave only the code that is effective.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-07-30 17:45:28 +08:00
Naresh Kumar Ravulapalli
46d5cf3847 arch: arm: socfpga: Include BSD-3-Clause as license identifier
All the source code of secure_vab.c and secure_vab.h are from Intel
and Altera. Updating the license to use either GPL-2.0 or
BSD-3-Clause because this copy of code may be used for open source
and internal project.

Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-07-30 17:45:28 +08:00
Naresh Kumar Ravulapalli
05e97d0ef8 arch: arm: socfpga: Fix header file includes
Appropriate header files are included according to U-Boot
coding style.

Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-07-30 17:45:28 +08:00
Dinesh Maniyam
e88024b34b arch: arm: dts: agilex5: Set spi-max-freq to 50Mhz
This patch is to set spi-max-freq to 50Mhz. This will add support to the
driver to set the operation speed according to the slave device up to
50Mhz. Without this node, the driver just can adjust the operation speed
to the default speed which is far below the best
operation speed of the SPI slave device.

Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-07-30 17:45:28 +08:00
Patrice Chotard
7e1e22c70d watchdog: don't autostart watchdog on STM32MP architecture
On STM32MP reference boards, the watchdog is started by a previous
boot stage (e.g. bootrom or secure OS), so the config flag
WATCHDOG_AUTOSTART is not required.
It's preferable to rely on the DT properties "u-boot,autostart" or
"u-boot,noautostart", if needed.

For backward compatibility on defconfigs that are based on SPL,
thus cannot rely on a previous boot stage for starting the
watchdog, enable WATCHDOG_AUTOSTART in their respective defconfig.
The change in stm32mp15_dhsom.config is propagated to:
- configs/stm32mp15_dhcom_basic.config
- configs/stm32mp15_dhcor_basic.config
and then to:
- stm32mp15_dhcom_basic_defconfig
- stm32mp15_dhcom_drc02_basic_defconfig
- stm32mp15_dhcom_pdk2_basic_defconfig
- stm32mp15_dhcom_picoitx_basic_defconfig
- stm32mp15_dhcor_avenger96_basic_defconfig
- stm32mp15_dhcor_basic_defconfig
- stm32mp15_dhcor_drc_compact_basic_defconfig
- stm32mp15_dhcor_testbench_basic_defconfig

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2025-07-30 08:01:11 +02:00
Clément Le Goffic
4bef031d69 watchdog: stm32mp: check the watchdog status
Add a mean to check the IWDG status based on the peripheral version.
This is done by either checking the status bit ONF either by updating
the reload register with the same value and check if the reload succeed.

Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2025-07-30 08:01:11 +02:00
Antonio Borneo
6319fabe32 watchdog: arm_smc_wdt: get wdt status through SMCWD_GET_TIMELEFT
The optional SMCWD_GET_TIMELEFT command can be used to detect if
the watchdog has already been started.
See the implementation in OP-TEE secure OS [1].

At probe time, check if the watchdog is already started and then
call wdt_set_force_autostart(). This will keep U-Boot pinging the
watchdog even when the property 'u-boot,noautostart' is present.

Link: https://github.com/OP-TEE/optee_os/commit/a7f2d4bd8632 [1]

Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2025-07-30 08:01:11 +02:00
Antonio Borneo
091303c788 watchdog: wdt-uclass.c: add wdt_set_force_autostart() helper
The watchdog could have been already started by a previous boot
stage (e.g. bootrom or secure OS). U-Boot has to start and kick
the watchdog even when CONFIG_WATCHDOG_AUTOSTART is not enabled
or when the DT property u-boot,noautostart is present.

Add the helper wdt_set_force_autostart() that can be called by the
driver's probe() when it detects that the watchdog has already
been started and is running.

Co-developed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2025-07-30 08:01:11 +02:00
Tom Rini
09974c7a64 Merge patch series "bintool fixes"
Jerome Forissier <jerome.forissier@linaro.org> says:

Two small fixes for binman (bintool). The first patch avoids a warning,
the second one makes sure the APT package list is up-to-date when
running apt_install(). That one fixes a CI issue I encountered.

Link: https://lore.kernel.org/r/20250724091342.59902-1-jerome.forissier@linaro.org
2025-07-29 17:00:14 -06:00
Jerome Forissier
252a2b2750 binman: bintool: run 'apt-get update -y' on first invocation of apt_install()
'apt-get update -y' may be required to make sure that the list of
packages is up-to-date and that the subsequent 'apt-get install'
operations can find the requested packages.

Fixes the following CI error:

 Fetch: zstd
 - trying method: binary download
 - sudo apt-get install -y zstd
 Exception: Error 100 running 'sudo apt-get install -y zstd': E: Unable to locate package zstd

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Bryan Brattlof <bb@ti.com>
2025-07-29 17:00:07 -06:00
Jerome Forissier
2babd34eac binman: bintool: use apt-get instead of apt
The 'apt' command is not meant to be used in scripts or tools. Please
see the man page [1] for details. Therefore, use 'apt-get' instead.
This avoids the following warning:

WARNING: apt does not have a stable CLI interface. Use with caution in scripts.

[1] https://manpages.debian.org/bookworm/apt/apt.8.en.html#SCRIPT_USAGE_AND_DIFFERENCES_FROM_OTHER_APT_TOOLS

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Bryan Brattlof <bb@ti.com>
2025-07-29 17:00:07 -06:00
Justin Swartz
bb04b7bcf6 tools: mips-relocs: replace format string introducers
The statement that prints the ELF object type value assumes that "%lx"
(long unsigned int, hexadecimal) is suitable for printing a uint64_t
typed value. While this may seem to work for some machines, ie. amd64,
it isn't ideal on a 32-bit system, such as x86 where uint64_t is likely
to be equivalent to a long long unsigned int, as indicated by:

  ../tools/mips-relocs.c:275:34:
  warning: format '%lx' expects argument of type 'long unsigned int',
           but argument 2 has type 'uint64_t'
           {aka 'long long unsigned int'} [-Wformat=]
  275 |                 printf("type 0x%lx\n", ehdr_field(e_type));
      |                                ~~^
      |                                  |
      |                                  long unsigned int
      |                                %llx

As the ehdr_field function-like macro expands to a uint64_t value,
it is better to use the PRIx64 macro in place of "%lx" to ensure that
the correct format string introducer is specified for the actual type
hiding behind uint64_t.

A similar issue is also present in the report of .rel section overflow,
where "%lx" is used to print a few size_t typed values, and would be
better served by "%zx" instead.

Signed-off-by: Justin Swartz <justin.swartz@risingedge.co.za>
Fixes: 9630146411 ("MIPS: make size of relocation table fixed but configurable")
Fixes: 703ec9ddf9 ("MIPS: Stop building position independent code")
Cc: Paul Burton <paulburton@kernel.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Masahiro Yamada <masahiroy@kernel.org>
2025-07-29 16:48:10 -06:00
Tom Rini
a8f20bb665 Merge patch series "bios_emulator: Fix two issues found by Smatch"
Andrew Goodbody <andrew.goodbody@linaro.org> says:

Smatch found two issues in bios_emulator, a buffer overflow and missing
parens for a macro. Fix them both.

Link: https://lore.kernel.org/r/20250723-bios_emulator-v1-0-78b9ef7b9b4a@linaro.org
2025-07-29 13:14:52 -06:00
Andrew Goodbody
0fdcca86d8 bios_emulator: Add parens to xorl macro
The xorl macro lacked surrounding parens which meant that it could have
unexpected results when used in expressions. Fix this by adding the
surrounding parens to make its use predictable.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-07-29 13:14:47 -06:00
Andrew Goodbody
4b8aba93bd bios_emulator: Fix buffer overflow
Using strcpy to copy a 4 character string into a 4 byte field in a
structure will overflow that field as it writes the terminating \0 into
the following field. Correct this by using memcpy instead.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-07-29 13:14:46 -06:00
Andrew Goodbody
ae409a84e7 spl: NULL check variable before dereference
In boot_from_devices the variable loader is not NULL checked after
assignment and before first use but later code does check it for NULL.
Add a NULL check before first use.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-07-29 13:12:12 -06:00
Tom Rini
808d4bc2bd Merge tag 'u-boot-marvell-20250729' of https://source.denx.de/u-boot/custodians/u-boot-marvell
CI: https://dev.azure.com/sr0718/u-boot/_build/results?buildId=394&view=results

- cmd: tlv_eeprom: Minor improvements (Hugo)
- kirkwood: Enable bootstd and other modernization for ib62x0 board
  (Tony)
- spi: mvebu: Correct dependencies on MVEBU_A3700_SPI (Tom)
- ddr: marvell: a38x: Fix unsigned issues detected by smatch (Andrew)
2025-07-29 09:36:59 -06:00
Patrice Chotard
1cec03bb1f treewide: Fix STMicroelectronics spelling
Fix STMicroelectronics spelling in comments.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2025-07-29 17:02:32 +02:00
Patrick Delaunay
ab0127e2ce ARM: stm32: fix PRE_CON_BUF_ADDR on STM32MP13
Since SYS_MALLOC_F_LEN increasing to 0x2100000 on STM32MP13, the
pre-console buffer is overlapped by stack (0xC0400000 + 0x2100000),
so the this buffer must be moved just before the bootstage to avoid issue.

After this patch the pre-relocation memory mapping for STM32MP13x is:

C3000000	= Bootstage	CONFIG_BOOTSTAGE_STASH_ADDR
C2FFF000	= PreConsole	CONFIG_PRE_CON_BUF_ADDR
           with size CONFIG_PRE_CON_BUF_SZ = 4096
C0400000	= start for stack	with CONFIG_CUSTOM_SYS_INIT_SP_ADDR
           including CONFIG_SYS_MALLOC_F_LEN
C0000000	= Load Address of U-Boot	with CONFIG_TEXT_BASE

Fixes: 93c962c7af7e ("configs: stm32mp13: increase SYS_MALLOC_F_LEN to 0x210000")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2025-07-29 17:02:32 +02:00
Patrice Chotard
34841992e0 configs: stm32mp13: Enable OF_UPSTREAM_BUILD_VENDOR
Enable OF_UPSTREAM_BUILD_VENDOR and set OF_UPSTREAM_VENDOR.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2025-07-29 17:02:32 +02:00
Patrice Chotard
694ed99185 arm: stm32mp: replace space by tab in sys_proto.h
Cosmetic update to replace space by tab in sys_proto.h

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2025-07-29 17:02:32 +02:00
Patrice Chotard
a2b5286ae4 ARM: dts: stm32: Add stm32mp235f-dk-u-boot
Add U-Boot specific file for stm32mp235f-dk board

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2025-07-29 17:02:31 +02:00
Patrice Chotard
fdd30ee308 ARM: stm32mp: Add STM32MP23 support
Add STM32MP23 support which is a cost optimized of STM32MP25.
More details available at:
https://www.st.com/en/microcontrollers-microprocessors/stm32mp2-series.html

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2025-07-29 17:02:31 +02:00
Marek Vasut
998da69da6 ARM: dts: stm32: Switch defconfig to SPL for DH STM32MP13xx DHCOR DHSBC
Update defconfig to make use of U-Boot SPL to initialize DH STM32MP13xx
DHCOM DHSBC SoM and board. This is largely a move of SPL enablement from
DH STM32MP15xx DHSOM defconfigs into generic DH STM32MP1xx defconfig .
Support for SPI NOR chips which are not used on STM32MP13xx DHCOR are
moved into STM32MP15xx DHSOM defconfigs. Changes to STM32MP13xx DHCOR
defconfig then enable SPL support, CCF in SPL to configure clock, pin
configuration support in SPL, and OpTee OS start support in U-Boot.

Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
2025-07-29 17:02:31 +02:00
Marek Vasut
1143fd4c35 ARM: dts: stm32: Add SPL specifics for DH STM32MP13xx DHCOR DHSBC
Add SPL specific DT additions to DH STM32MP13xx DHCOR DHSBC . These
include I2C3 configuration which is required to access the PMIC,
PMIC regulator and QSPI NOR bootph-all properties to allow SPL to
configure PMIC buck regulators and load from QSPI NOR respectively,
etzpc bus switch to simple-bus to prevent interference from TFABOOT
specific configuration, and RCC configuration to define clock tree
configuration used by this platform.

Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
2025-07-29 17:02:31 +02:00
Marek Vasut
bf53344bff ARM: dts: stm32: Add STM32MP13x SPL specific DT additions
Add DT additions required by U-Boot SPL to bring up the hardware.
This includes binman node to generate STM32 Image v2.0 which can be
booted by the BootROM, clock entries used by the SPL clock driver
during clock tree initialization, and syscon-reboot node so U-Boot
can reset the system without having to rely on PSCI call.

Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
2025-07-29 17:02:31 +02:00
Marek Vasut
fa21426cc8 ARM: dts: stm32: Add 512 MiB DRAM settings for DH STM32MP13xx DHCOR DHSBC
Add DRAM settings for 512 MiB of DRAM variant of DH STM32MP13xx DHCOR DHSBC.

Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
2025-07-29 17:02:31 +02:00
Marek Vasut
da43c242fb ARM: dts: stm32: Add stm32mp13-ddr.dtsi template
Factor out common parts of STM32MP15xx DRAM controller configuration DT
description into stm32mp1-ddr.dtsi and introduce stm32mp13-ddr.dtsi which
describes STM32MP13xx DRAM controller configuration in DT.

Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
2025-07-29 17:02:31 +02:00
Marek Vasut
bd50cb5cde ARM: stm32: Add STM32MP13xx debug UART initialization
Add default STM32MP13xx debug UART initialization. This is similar
to STM32MP15xx debug UART initialization, except the RCC registers
are at different offsets and the UART pinmux pins are different.

Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
2025-07-29 17:02:31 +02:00
Marek Vasut
61d353dc92 ARM: stm32: Add STM32MP13xx PMIC initialization for DDR3 DRAM type
The STM32MP13xx PMIC initialization for DDR3 DRAM type is similar
to the STM32MP15xx PMIC initialization, except the VTT rail is not
enabled. Fill in the STM32MP13xx support.

Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
2025-07-29 17:02:31 +02:00
Marek Vasut
a36e87127a ARM: stm32: Limit early cache enablement in SPL to STM32MP15xx
The STM32MP13xx SRAM size is half that the SRAM size on STM32MP15xx,
disable early dcache start on STM32MP13xx as the TLB itself takes
about a quarter of the SPL size. The dcache will be enabled later,
once DRAM is available and TLB can be placed in DRAM.

Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
2025-07-29 17:02:31 +02:00
Marek Vasut
b87ebbe87c ARM: stm32: Add STM32MP13xx SPL hardware initialization
Add hardware initialization for the STM32MP13xx in SPL. This is
similar to STM32MP15xx except the code has to enable MCE to bring
DRAM controller up later.

Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
2025-07-29 17:02:31 +02:00
Marek Vasut
5705938597 ARM: stm32: Add STM32MP13xx SPL Kconfig options
Introduce Kconfig options used by SPL on STM32MP13xx and isolate
the Kconfig options only used in case TFA BL2 is used as a SPL
behind CONFIG_TFABOOT dependency.

Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
2025-07-29 17:02:31 +02:00
Andrew Goodbody
8693fe92ac clk: stm32: Wrong macros used in register read
Smatch reported a warning about a shift macro being used as a mask. Make
the obvious changes to make this register read calculation work the same
as the previous ones.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2025-07-29 17:02:31 +02:00
Alice Guo
52b7ad7bec clk: scmi: Fix clock identifier passed to struct scmi_clk_parent_set_in
Commit aa7bdc1af5 ("clk: scmi: manage properly the clk identifier with
CFF") enables CONFIG_CLK_AUTO_ID, so need to use clk_get_id() to get the
real SCMI CLK ID, otherwise wrong ID is used when set clk parent.

Fixes: aa7bdc1af5 ("clk: scmi: manage properly the clk identifier with
CCF")

Signed-off-by: Alice Guo <alice.guo@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2025-07-29 17:02:31 +02:00
Marek Vasut
f91bb6d1df reset: stm32: Fix header misuse
The stm32-reset-core.h is located in drivers/reset/stm32/ , it has to
be included using "stm32-reset-core.h" and not <stm32-reset-core.h> ,
otherwise the build fails. Fix it.

Fixes: 0994a627c2 ("reset: stm32mp25: add stm32mp25 reset driver")
Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2025-07-29 17:02:31 +02:00
Cheick Traore
f6764328c6 configs: stm32mp25: Enable MFD timer and PWM for stm32mp25_defconfig
Enable the following configs:

- CONFIG_MFD_STM32_TIMERS: enables support for the STM32 multifunction
                           timer
- CONFIG_DM_PWM: enables support for pulse-width modulation devices
- CONFIG_CMD_PWM: enables 'pwm' command to control PWM channels
- CONFIG_PWM_STM32: enables support for the STM32 PWM devices

Signed-off-by: Cheick Traore <cheick.traore@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2025-07-29 17:02:31 +02:00
Cheick Traore
3f14dc91ab pwm: stm32: add support for stm32mp25
Add support for STM32MP25 SoC.
IPIDR register is used to check the hardware configuration register
when available to gather the number of complementary outputs.

Signed-off-by: Cheick Traore <cheick.traore@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2025-07-29 16:44:58 +02:00
Cheick Traore
8e1fafb807 arm: stm32mp2: add multifunction timer support for stm32mp25
Add support for STM32MP25 SoC.
Identification and hardware configuration registers allow to read the
timer version and capabilities (counter width, ...).
So, rework the probe to avoid touching ARR register by simply read the
counter width when available. This may avoid messing with a possibly
running timer.
Also add useful bit fields to stm32-timers header file.

Signed-off-by: Cheick Traore <cheick.traore@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2025-07-29 16:44:58 +02:00
Tom Rini
0662dae4df Merge tag 'u-boot-at91-2025.10-b' of https://source.denx.de/u-boot/custodians/u-boot-at91
Second set of u-boot-at91 features for the 2025.10 cycle:

This feature set includes the addition of new sama7d65 SoC and a new
board named sama7d65-curiosity.
2025-07-29 07:55:49 -06:00
Andrew Goodbody
b35ddfc57a ddr: marvell: a38x: Fix unsigned issues
Cannot test an unsigned variable to be less than 0, it will always fail.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Stefan Roese <stefan.roese@mailbox.org>
2025-07-29 08:44:18 +02:00
Tom Rini
c8114a01ad spi: mvebu: Correct dependencies on MVEBU_A3700_SPI
A dependency exposed by "make allyesconfig" is that the logic around
this symbol was not quite correct. It needs to depend on ARCH_MVEBU and
ARM64 and then select CLK_MVEBU.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2025-07-29 08:44:18 +02:00
Tony Dinh
53f328663d arm: kirkwood: Enable bootstd and other modernization for ib62x0 board
Enable bootstd.
Update defconfigs to the latest u-boot requirements.
Enable SYS_THUMB_BUILD and LTO and to reduce binary size.
Enable NET_RANDOM_ETHADDR.
Disable JFFS2 support.

Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2025-07-29 08:44:18 +02:00
Hugo Villeneuve
ee6d8ba15e cmd: tlv_eeprom: improve mac_read_from_eeprom() log messages
mac_read_from_eeprom() always display debug infos, and this messes up the
display of the "Net:" section details:

Before:
    Net:   EEPROM: TlvInfo v1 len=172
    eth0: ethernet@11c20000

After:
    Net:   eth0: ethernet@11c20000

Fix by moving unconditional "EEPROM: " header into each message and
changing debug message to use log_debug().

Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
2025-07-29 08:44:18 +02:00
Hugo Villeneuve
dedef8f6f9 cmd: tlv_eeprom: fix typo errors in comments and error msg
Fix typo errors in comments and error message by replacing EERPOM->EEPROM.

Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
2025-07-29 08:44:18 +02:00
Tom Rini
182cb30084 Prepare v2025.10-rc1
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-28 18:23:01 -06:00
Andrew Davis
0faf23611e arm: mach-k3: Fix typo for TIFSSTUB_GP in IMAGE_ID enum
Signed-off-by: Andrew Davis <afd@ti.com>
2025-07-28 18:22:22 -06:00
Rasmus Villemoes
51013e7bfb .gitignore: don't ignore .gitattributes files
In a private fork, it's not unreasonable to commit various binary
files associated to one's project, and thus put a suitable
.gitattributes file next to it to force git to treat that file as
binary. In my case, I have a .xslx spreadsheet used for computing
suitable RAM timing tables, which I wanted to put in
board/<vendor>/<project>. Git duly warned me that it would do LF/CRLF
mangling, so I also added a .gitattributes file next to it with

  *.xlsx binary

but upon adding that file, git told me that I'd have to use -f because
it's a dot-file that is by default ignored.

Add .gitattributes to the list of dot-files that should not be
ignored.

While in here, sort the list and update the comment, as there are also
files which git itself does not make use of in the list, cf. linux
commit f46e65da48b2 (".gitignore: exclude .get_maintainer.ignore and
.gitattributes").

Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
Reviewed-by: Tom Rini <trini@konsulko.com>
2025-07-28 13:04:42 -06:00
Andrew Goodbody
b83f865e75 cmd: elf: Prevent possible buffer overflow
In do_bootvx the environment variable 'bootdev' is fetched and copied
into a buffer without confirming that it will not overflow that buffer.
Use strlcpy to ensure that the buffer will not be overflowed.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-07-28 13:04:42 -06:00
Tom Rini
9b2e794190 configs: Resync with savedefconfig
Resync all defconfig files using qconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-28 09:50:16 -06:00
Casey Connolly
174128ad6e treewide: fix Casey's name
I updated the mailmap a while back but it's nice to have authorship
comments adjusted too.

Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-07-28 08:53:20 -06:00
Tom Rini
14dd807a48 Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi
These patches add support for the new Allwinner A523/A527/T527 SoC (all
same die), alongside with defconfigs for three boards using one of those
SoCs.
The patches are the usual combination of refactoring (of the SPL clock
code this time), tweaks to existing drivers to support peripherals in
their A523 versions, and new drivers for pincontrol and clocks. A big
chunk is of course the DRAM controller init routines, many thanks to
Jernej and Mikhail for providing this code, after a big reverse
engineering effort.
Since the DTs for the three supported boards have been merged into the
kernel repo recently, this is concluded by cherry-picks of those
patches, and the defconfig files to finally enable booting those boards.

The patches have been sitting around for a while, and folks are already
using them, so it's now time to get them into the tree.

Gitlab CI passed, and I booted that briefly on those three boards, plus
on some other SoCs to spot potential regressions.
2025-07-28 08:08:16 -06:00
Andre Przywara
0199794b30 sunxi: A523: add defconfigs for three boards
So far developers seem to use three popular boards:
- Avaota A1: dev board with USB 3.0, dual Ethernet, small display
- X96QPro+: TV box with Gigabit Ethernet, USB 3.0, eMMC
- Radxa A5E: small dev board with USB3/M.2 2230 (muxed), dual Ethernet

Add the defconfig files for those boards, containing the DRAM parameters
and the usual Kconfig options.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2025-07-27 23:12:20 +01:00
Andre Przywara
4112b26537 arm64: dts: allwinner: a523: add Avaota-A1 router support
The Avaota A1 router board is an Open Source hardware board, designed
by YuzukiHD. Pine64 produces some boards and sells them. It uses the
Allwinner A527 or T527 SoC, and comes with the following features:
  - Eight ARM Cortex-A55 cores, Mali-G57 MC1 GPU
  - 1GiB/2GiB/4GiB LPDDR4 DRAM
  - AXP717 + AXP323 PMIC
  - Raspberry-Pi-2 compatible GPIO header
  - 1 USB 2.0 type A host port, 1 USB 3.0 type A host post
  - 1 USB 2.0 type C port (OTG + serial debug)
  - MicroSD slot
  - eMMC between 16 and 128 GiB
  - on-board 16MiB bootable SPI NOR flash
  - two 1Gbps Ethernet ports (via RTL8211F PHYs)
  - HDMI port
  - DP port
  - camera and LCD connectors
  - 3.5mm headphone jack
  - (yet) unsupported WiFi/BT chip
  - 1.3" LC display, connected via SPI
  - 12 V barrel plug for power supply

Add the devicetree file describing the currently supported features.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://patch.msgid.link/20250307005712.16828-12-andre.przywara@arm.com
[wens@csie.org: Squash in SD card detect pull resistor fix]
Link: https://patch.msgid.link/20250425003422.3465-1-andre.przywara@arm.com
Signed-off-by: Chen-Yu Tsai <wens@csie.org>

[ upstream commit: dbe54efa32afe5b82763c015cbe9e64c4d4e117a ]

(cherry picked from commit ebcb8469ef4336c05c6b9f409714a23cfc891fff)
2025-07-27 23:12:20 +01:00
Andre Przywara
499d931751 arm64: dts: allwinner: a523: add Radxa A5E support
The Radxa A5E is a development board using the Allwinner A527 SoC, which
is using the same die as the A523 SoC, just exposing the pins of more
peripherals (like HDMI or the 2nd MAC). The board features:

  - Allwinner A527/T527 SoC: 8 ARM Cortex-A55 cores, Mali-G57 MC1 GPU
  - 1GiB/2GiB/4GiB LPDDR4 DRAM
  - AXP717 + AXP323 PMICs
  - Raspberry-Pi-2 compatible 40pin GPIO header
  - 1 USB 2.0 type C port (OTG), also power supply
  - 1 USB 3.0 type A host port (multiplexed with M.2 slot)
  - 1 M.2 M-key 2230 slot, with 1 PCIe2.1 lane connected (multiplexed
    with USB 3.0 port)
  - MicroSD slot
  - optional eMMC, 8, 16 or 32GB available
  - optional on-board 16MiB bootable SPI NOR flash
  - two 1Gbps Ethernet ports (via MAXIO MAE0621A PHYs)
  - PoE header for optional supply circuit on one Ethernet port
  - WiFi 802.11 a/b/g/n/ac/ax (LB-Link BL-M8800DS2 module using AIC8800)
  - HDMI port
  - camera and LCD connectors
  - power supply via USB-C connector (but no PD) or GPIO header pins

This .dts describes the devices as far as we support them at the moment.
The PMIC rails have been assigned as per the schematics.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://patch.msgid.link/20250307005712.16828-14-andre.przywara@arm.com
[wens@csie.org: Squash in SD card detect pull resistor fix]
Link: https://patch.msgid.link/20250425003422.3465-1-andre.przywara@arm.com
[wens@csie.org: Rename dts file to sun55i-a527-cubie-a5e.dts]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>

[ upstream commit: c2520cd032ae8ca3fdaf77b3f3aa687c8cb7843f ]

(cherry picked from commit 91ad117321c0901094c1d6467df90f5f6757569a)
2025-07-27 23:12:20 +01:00
Andre Przywara
184b599533 arm64: dts: allwinner: a523: add X96Q-Pro+ support
The X96QPro+ is a TV box using the Allwinner H728 SoC. That SoC seems to
be a package variant of the A523 family, at least it uses the same SoC
ID and is compatible as far as we can assess.

It comes with the following specs:
  - Allwinner H728 SoC: 8 Arm Cortex-A55 cores, Mali-G57 MC1 GPU
  - 2 or 4GiB DDR3L DRAM
  - 32, 64, or 128 GiB eMMC flash
  - AXP717 + AXP323 PMICs
  - Gigabit Ethernet (using MAXIO PHY)
  - HDMI port
  - 2 * USB 2.0 ports
  - 1 * USB 3.0 port
  - microSD card slot
  - TOSLINK digital audio output
  - 3.5mm A/V port
  - infrared sensor
  - 7-segment display
  - 5V barrel plug power supply
  - power button

The PCB provides holes for soldering a UART header or cable, this is
connected to the debug UART0. There is another set of UART pins
available. The board also features a FEL button (accessible through the
3.5mm socket) and a reset button (only accessible when case is open).

This .dts just describes the basic peripherals as far as we support them
at the moment. The PMIC rail assignments are reverse engineered as far
as possible, by dumping them from a running Android system, and correlating
them to other boards using the same SoC.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://patch.msgid.link/20250307005712.16828-13-andre.przywara@arm.com
[wens@csie.org: Squash in SD card detect pull resistor fix]
Link: https://patch.msgid.link/20250425003422.3465-1-andre.przywara@arm.com
Signed-off-by: Chen-Yu Tsai <wens@csie.org>

[ upstream commit: 4ee87d875071390b4e24ce46dbdd792216d61651 ]

(cherry picked from commit 693da0a03149b77a3e2bc11cfd314df8cc2fab40)
2025-07-27 23:12:20 +01:00
Andre Przywara
f378267812 arm64: dts: allwinner: Add Allwinner A523 .dtsi file
The Allwinner A523, and its siblings A527 and T527, which share the same
die, are a new family of SoCs introduced in 2023. They features eight
Arm Cortex-A55 cores, and, among the other usual peripherals, a PCIe and
USB 3.0 controller.

Add the basic SoC devicetree .dtsi for the chip, describing the
fundamental peripherals: the cores, GIC, timer, RTC, CCU and pinctrl.
Also some other peripherals are fully compatible with previous IP, so
add the USB and MMC nodes as well.
The other peripherals will be added in the future, once we understand
their compatibility and DT requirements.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://patch.msgid.link/20250307005712.16828-9-andre.przywara@arm.com
Signed-off-by: Chen-Yu Tsai <wens@csie.org>

[ upstream commit: 35ac96f796649346c9b0440413dc6c5138249b3e ]

(cherry picked from commit 247a3572abcfd7a0d48e12f8f810f1cbae5ce4f4)
2025-07-27 23:12:20 +01:00
Andre Przywara
08f3f477c6 sunxi: add basic A523 support
Add the basic Kconfig options, addresses and other values for the
existing Kconfig settings for the new Allwinner A523/T527/H728 SoC.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2025-07-27 23:11:31 +01:00
Mikhail Kalashnikov
45310eb74b sunxi: A523: add DDR3 DRAM support
Add reverse engineered code to add support for DDR3 DRAM chips on the
Allwinner A523 DRAM controller.
The timings are copying what boot0 set up on the X96QPro+ TV box, though
they seem quite suboptimal, with longer latencies that would be required
for DDR3-1600. The chips are also actually capable of DDR3-1833, so
there is room for future improvement.

Signed-off-by: Mikhail Kalashnikov <iuncuim@gmail.com>
[Andre: rework to copy from H616 DDR3 driver, calculate timings]
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2025-07-27 23:11:08 +01:00
Jernej Skrabec
39a6a2a8a2 sunxi: A523: add DRAM initialisation routine
DRAM init code, as per reverse engineering and matching against
previous SoCs. As usual no real documentation, and the DRAM controller
is the usual mixture of close-to-previous IP and new inventions.

This version supports LPDDR4 for now only, as seen on the early boards.

This needs improvements, but it can be done later.

Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2025-07-27 23:02:09 +01:00
Jernej Skrabec
d157dec118 sunxi: sun50i_h6: add A523 SPL clock setup code
This adds the early A523 clock setup code, for the basic peripheral PLL
and the basic bus clocks (APB/AHB). This is quite close to the existing
H6 and H616 clock code, so this shares the same file. A few bits and bobs
are different, though, so filter for the A523 in a few occasions.

Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2025-07-27 22:58:05 +01:00
Andre Przywara
7a5170a6fc sunxi: update cpu_sunxi_ncat2.h
The cpu_sunxi_ncat2.h header file contains addresses of some peripherals
that are needed for the SPL, for chips that belong to the "NCAT2"
generation.
The Allwinner A523 is a member of this group, but a few addresses
differ, and we need a few more addresses, for playing with the core
reset, for instance.

Add the new addresses needed for the A523 and guard existing definitions
that conflict with that new chip.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2025-07-27 22:57:35 +01:00
Andre Przywara
1063678a70 power: regulator: add AXP323 support
The X-Powers AXP323 is very close sibling to the AXP313A, only that it
adds support for dual-phasing the first two DC/DC converters.

We do not really care about this particular feature, so just add the new
compatible string and tie it to the existing AXP313A support code.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2025-07-27 22:57:35 +01:00
Andre Przywara
869d396191 sunxi: mmc: add support for Allwinner A523 MMC mod clock
The Allwinner A523 SoC has a slightly changed mod clock, where the P
factor, formerly a shift value, is now a second divider value.
Also the input clock is not PLL_PERIPH0 (600MHz) anymore, but
PLL_PERIPH0_400M (for MMC0/1), so adjust the input rate calculation
accordingly. MMC2 has a different set of parents, so the input clock
is 800 MHz there.
Adjust for all of this.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2025-07-27 22:57:35 +01:00
Andre Przywara
14c66b9e35 pinctrl: sunxi: add Allwinner A523 pinctrl description
The new DT pinctrl binding would allow us to read the pinmux values from
the DT, but it is actually easier to just continue with hardcoding the
mux values in the driver, and matching them against the "function" name.

Add the values for the primary and secondary pin controller on the A523.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2025-07-27 22:57:35 +01:00
Andre Przywara
d508d995d1 clk: sunxi: Add support for the A523 -R CCU
Add a clock driver for the PRCM clock controller on the Allwinner A523
family of SoCs, often also used with an "r" prefix or suffix.
This just describes the clock gates and reset lines for the few devices
that we would need, most prominently the R_I2C device for the PMIC.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2025-07-27 22:57:35 +01:00
Andre Przywara
1d0b1d46cc clk: sunxi: Add support for the A523 CCU
Add a clock driver for the main clock controller on the Allwinner A523
family of SoCs.
As usual, this just describes the clock gates and reset lines for the
few device that U-Boot cares about: USB, Ethernet, MMC, I2C, SPI.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2025-07-27 22:57:35 +01:00
Andre Przywara
1482481817 sunxi: spl: add support for Allwinner A523 watchdog
The watchdog in the Allwinner A523 SoC differs a bit from the one in the
previous SoCs: it lives in a separate register frame, so no longer
inside some timer device, and it manages to shuffle around some
registers a bit. But it also conveniently adds a direct reset
functionality, so we don't need to use a dummy timeout period.

Avoid introducing a new MMIO register frame C struct, but just define
the one needed register offset as a macro. Then just trigger this new
direct reset functionality in the A523 specific reset_cpu()
implementation.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2025-07-27 22:57:35 +01:00
Andre Przywara
17b47bbc34 sunxi: clock: H6: add A523 CPU PLL support
The Allwinner A523 features 8 CPU cores, organised in two clusters, both
driven by separate PLLs. Also there is the DSU PLL, which clocks the
hardware that connects the cores to the rest of the system.
And while the PLL registers itself are very similar, they are located in
a separate register frame, outside the main CCU, and also the register
controlling the CPU clock source (mux) is different.

Provide a separate function that reparents the two clusters and the DSU,
while their PLLs are programmed. For the actual PLL programming, we rely
on the existing shared routine.

The selection between the new A523 routine and the existing code is made
with C if statements, but since the choice is effectively made at compile
time already, the compiler optimises away the other code paths, leaving
just the one required function in.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2025-07-27 22:57:35 +01:00
Andre Przywara
915ac864f4 sunxi: clock: H6: factor out H6/H616 CPU clock setup
When we program the CPU PLL, we need to switch the CPU clock source away
from the PLL temporarily, then switch it back, once the PLL has
stabilised.

The CPU CLK register will be different on the A523, so move the current
code into a separate function, to allow using a different version of
that later for the A523.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2025-07-27 22:57:35 +01:00
Andre Przywara
ff4dda1db2 sunxi: clock: H6: factor out clock_set_pll()
The SPL initial clock setup code for the Allwinner H6 and H616 SoCs uses
a simple CPU PLL setup routine, which programs all register bits at once,
then waits for the LOCK bit to clear.
The manual suggests to follow a certain procedure for bringing up any
PLLs, which involves several register writes, one at a time, and some
delays. Also the H616 and the new A523 require some tiny changes in this
sequence, and the different SoCs also feature some extra bits here and
there, which we should not just clear.

So factor out the PLL setup routine, and make it follow the manual's
suggestion. This will read the PLL register at the beginning, then tweak
the bits we need to manipulate, and writes the register several times on
the way. This allows to cover the specific bits for different SoCs.

Besides improving the reliability of the PLL setup, this helps with the
A523, which requires *three* CPU PLLs to be programmed.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2025-07-27 22:57:35 +01:00
Andre Przywara
f02e64d011 sunxi: clock: H6: unify PLL control bit definitions
The Allwinner PLLs share most of their control bits, they differ mostly
in the factors and dividers.

Drop the PLL specific definition of those common bits, and use one
shared macro, for all PLLs.

This requires changing the users in the SPL clock and DRAM code.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2025-07-27 22:57:35 +01:00
Tom Rini
4c3b5fcd81 Merge tag 'efi-2025-10-rc1' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request efi-2025-10-rc1

CI: https://source.denx.de/u-boot/custodians/u-boot-efi/-/pipelines/27176

Documentation:

* update FIT signature testing instructions
* describe defconfigs for AM69-SK

UEFI:

* provide unit test for system table pointer
* efi_realloc() must check efi_alloc() return value
* correct EFI_DEBUG_TABLE_ENTRY_SIZE
* avoid NULL dereference in ESRT creation tests
* add missing check in FMP.GetImageInfo()
* rename lib/efi to lib/efi_client
* rename CONFIG_EFI to CONFIG_EFI_CLIENT
* create a new CONFIG_EFI
* update maintainers for EFI_CLIENT
2025-07-26 09:21:09 -06:00
Enric Balletbo i Serra
afd5426043 docs: Update FIT signature testing instructions
Update the FIT signature testing instructions to use the pytest suite instead of
the old vboot_test.sh script.

Signed-off-by: Enric Balletbo i Serra <eballetbo@kernel.org>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
2025-07-26 07:37:03 +02:00
Heinrich Schuchardt
5bab07296c efi_loader: add missing check in FMP.GetImageInfo()
The UEFI 2.11 specification, chapter 23.1.3 requires
EFI_FIRMWARE_MANAGEMENT_PROTOCOL.GetImageInfo() to return
EFI_INVALID_PARAMETER if *ImageInfoSize is not too small
and ImageInfo is NULL.

Fixes: f27c201485 ("efi_loader: add firmware management protocol for FIT image")
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2025-07-26 07:37:03 +02:00
Heinrich Schuchardt
ca01c847f6 efi_selftest: fix ESRT creation tests
The code foresees that parameters descriptor_size and descriptor_count
might be NULL and then dereferences them without further check.

The size check must take into account the descriptor count.

ImageInfo might be NULL. In this case we must not dereference it.

Fixes: 4ac6041c3c ("efi: ESRT creation tests")
Addresses-Coverity-ID: CID 569497: Null pointer dereferences (FORWARD_NULL)
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2025-07-26 07:37:03 +02:00
Heinrich Schuchardt
7e2506e3a2 efi_loader: correct EFI_DEBUG_TABLE_ENTRY_SIZE
With the current code we allocate to little memory when adding entries to
the EFI_DEBUG_INFO_TABLE and we fail to correctly move entries when an
entry is removed.

EFI_DEBUG_TABLE_ENTRY_SIZE must be the size of an entry in the
EFI_DEBUG_INFO_TABLE, not the size of a pointer.

Fixes: 146546138a ("efi: add EFI_DEBUG_IMAGE_INFO for debug")
Addresses-Coverity-ID: CID 569498: Code maintainability issues (SIZEOF_MISMATCH)
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2025-07-26 07:37:03 +02:00
Heinrich Schuchardt
aa703a816a efi_loader: efi_realloc() must check efi_alloc() return value
Avoid copying to NULL if out of memory.

Fixes: 3c08df58cc ("lib: efi_loader: efi_memory.c: add efi_realloc() for realloc memory")
Addresses-Coverity-ID: 569499: Null pointer dereferences (NULL_RETURNS)
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2025-07-26 07:37:03 +02:00
Heinrich Schuchardt
b9bb2627bb efi_selftest: check system table pointer
Enhance the debug support unit test.

Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2025-07-26 07:37:03 +02:00
Mattijs Korpershoek
62b3dbfc5e doc: board: ti: Add defconfigs for AM69-SK
The J784S4 and AM69 Platforms page only details the defconfigs for
J784S4.

Mention the ones needed for AM69-SK as well, to guide users on how to
build for that board.

Signed-off-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
2025-07-26 07:37:03 +02:00
Simon Glass
ca0b03ba60 efi: Update maintainers for EFI_CLIENT
The 'EFI PAYLOAD' entry really refers to the EFI loader and EFI APP
refers to the app and the payload.

Rename 'EFI PAYLOAD' to 'EFI LOADER' and 'EFI APP' to 'EFI CLIENT'

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-07-26 07:34:34 +02:00
Simon Glass
81ce639e61 efi: Create a new CONFIG_EFI
Create a Kconfig which indicates that EFI functionality is in use,
either as a client (EFI app / stub) or provider (EFI loader). This will
make it easier to share code between these two parts of U-Boot

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-07-26 07:34:31 +02:00
Simon Glass
0029f2447b efi: Rename CONFIG_EFI to CONFIG_EFI_CLIENT
The generic name 'EFI' would be more useful for common EFI features. At
present it just refers to the EFI app and stub, which is confusing.

Rename it to EFI_CLIENT

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-07-26 07:34:28 +02:00
Simon Glass
2ea9579523 efi: Rename the lib/efi directory
This directory was created when U-Boot gained the ability to run as an
EFI app in 2015. Since then the EFI-loader feature has been added.

The code in lib/efi is not actually used by the loader, so the name is
confusing.

Rename the directory to efi_client to indicate that it includes files
just for U-Boot being a client of EFI, i.e. the EFI app and stub.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-07-26 07:29:31 +02:00
Tom Rini
1d782a3f22 Docker, CI: Update to latest Ubuntu and Dockerfile
- Update to Ubuntu "Jammy" 20250714 tag
- Update to current Dockerfile which brings us QEMU 10.0.2 and newer
  coreboot and pulls in lz4 via the non-legacy package name.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-25 13:03:01 -06:00
Tom Rini
2a19fc236f Merge patch series "CI: Disable sifive_unleashed_sdcard QEMU testing"
This series from myself brings CI up to using QEMU 10.0.2 for platforms.
We need to disable one test for now while a report to upstream QEMU is
resolved and also need to now update coreboot in order to be able to
build a version of it non-interactively (source locations have changed).

Link: https://lore.kernel.org/r/20250716001539.2483390-1-trini@konsulko.com
2025-07-25 10:55:45 -06:00
Tom Rini
0fabedfcde CI: Update to coreboot 25.03
At this point there's problems rebuilding coreboot-24.08 without manual
intervention. Let us upgrade to a newer version.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-25 10:55:40 -06:00
Tom Rini
910aa6c1ef Dockerfile: Update to QEMU 10.0.2
As QEMU 10.0.2 is the current release, update to that so that we can
update other features within CI.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-25 10:55:40 -06:00
Tom Rini
4f8755fe08 CI: Disable sifive_unleashed_sdcard QEMU testing
Changes in upstream QEMU have lead to this specific configuration of the
sifive_unleashed platform not working in QEMU. Until this can be
root caused and resolved, disable this test for now.

Link: https://gitlab.com/qemu-project/qemu/-/issues/2945
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-25 10:55:40 -06:00
Tom Rini
088d24eb96 Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-samsung
- Enhanced e850-96 support
2025-07-25 07:50:44 -06:00
Ryan Wanner
ecbe341012 configs: sama7d65_curiosity: Add defconfig for sama7d65_curiosity
Add initial mmc defconfig to boot from SDMMC1.

Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
Signed-off-by: Romain Sioen <Romain.Sioen@microchip.com>
2025-07-25 11:54:43 +03:00
Ryan Wanner
9e40ad0f81 board: sama7d65_curiosity: Add support for sama7d65_curiosity
Add board specific functions for sama7d65_curiosity.

Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
2025-07-25 11:54:43 +03:00
Ryan Wanner
0c29ddfe0c ARM: dts: at91: sama7d65-curiosity: Add DT tweaks for sama7d65-curiosity board
Add u-boot device tree and tweaks for sama7d65-curiosity board on top of
the upstream DTS files in dts/upstream.

Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
[varshini.rajendran@microchip.com: align with Linux DT and add tweaks]
Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
2025-07-25 11:54:43 +03:00
Ryan Wanner
1fd6fcf95a ARM: mach-at91: add support for new SoC sama7d65
Add support for new SoC sama7d65.

Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
2025-07-25 11:54:43 +03:00
Ryan Wanner
8dff5dd290 clk: at91: sama7d65: add clock support
Add clock support for SAMA7D65

Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
[romain.sioen@microchip.com: add Fractional PLL core
output range]
Signed-off-by: Romain Sioen <romain.sioen@microchip.com>
[varshini.rajendran@microchip.com: adapt driver to upstream]
Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
2025-07-25 11:54:43 +03:00
Ryan Wanner
eff0e49d1c clk: at91: Update MAX PLL and master clk ID
Update the MAX PLL and master CLK ID to support sama7d65
SoC family.

Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
2025-07-25 11:54:43 +03:00
Sam Protsenko
f83f2397a1 doc: samsung: Describe flashing process for E850-96
Now that USB is enabled on the E850-96 board, DFU and fastboot tools are
functional and can be used to flash images to eMMC. Update the E850-96
documentation accordingly and describe flashing to User Data Area and
Boot HW Partition of eMMC using fastboot and DFU tools.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2025-07-25 10:17:21 +09:00
Sam Protsenko
fd76fdc34e board: samsung: e850-96: Enable EFI Capsule Update mechanism
Make it possible to update E850-96 firmware binaries using EFI Capsule
Update mechanism. For example, to update the U-Boot binary, the capsule
file can be generated like this:

    $ ./tools/mkeficapsule --index 4 \
      --guid 629578c3-ffb3-4a89-ac0c-611840727779 \
      u-boot.bin capsule4.bin

The resulting 'capsule4.bin' should be copied to ESP partition (in
/boot/efi/EFI/UpdateCapsule/ directory). Then after reboot U-Boot will
update the 'bootloader' area in eMMC Boot Partition A (boot0) and remove
the capsule file, by EFI boot manager executed as a part of Standard
Boot:

    Applying capsule capsule4.bin succeeded.
    Reboot after firmware update.

The kernel will also expose the ESRT table information via SysFS in
/sys/firmware/efi/esrt/entries.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2025-07-25 10:17:21 +09:00
Sam Protsenko
9472bc2b50 configs: e850-96: Enable USB gadget and fastboot
Now that USB phy and dwc3 glue layer was added for Exynos850, USB gadget
is functional on E850-96 board. Enable next features to make it useful:

  - Exynos850 USB PHY driver (needed for all USB functions)
  - dwc3 generic driver
  - USB gadget
  - CONFIG_DM_USB_GADGET: needed for DWC3 glue layer to instantiate the
    peripheral driver, i.e. dwc3_generic_peripheral_probe()
  - USB VID and PID
  - DFU
  - Fastboot (including flashing to eMMC boot partitions)

As all Exynos firmware binaries (including U-Boot) are contained in eMMC
boot partition A (mmc0boot0), because that's where Boot ROM code jumps,
it might be useful to be able to flash that area with fastboot. Other
more fine grained choices for updating the firmware would be DFU and EFI
Capsule Update mechanism.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2025-07-25 10:17:21 +09:00
Sam Protsenko
fcb53c5a69 configs: e850-96: Increase malloc() pool size
"fastboot flash" tries to malloc 8 MiB buffer after receiving data over
USB and trying to write it to eMMC. Right now only 8.12 MiB malloc is
available for E850-96 overall, which leads to this issue:

    Malloc failed for: CHUNK_TYPE_RAW

Fix it by increasing malloc pool size from 8.12 MiB up to 32 MiB, like
it's done in many other boards using fastboot.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2025-07-25 10:17:21 +09:00
Sam Protsenko
d15a7b0459 board: samsung: e850-96: Add Android partitions
Matches downstream Android-Q partition table created by flashing the
modified gpt.img [1], with added ESP partition (EFI System Partition).
It's an A/B slotted Android partition table, so it's possible to boot
Android from this table using Android GBL EFI app. Tested using
AOSP/main images for E850-96 with booting via GBL app.

[1] https://gitlab.com/Linaro/96boards/e850-96/tools/gpt/-/blob/master/gpt_layout_uboot_q_ab

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2025-07-25 10:17:21 +09:00
Sam Protsenko
c0a8b48b71 board: samsung: e850-96: Add dfu_alt_info
Add 'dfu_alt_info' environment variable which contains:
  - Linux eMMC partitions ('esp' and 'rootfs')
  - eMMC Boot Partition A layout, where all the firmware reside

It makes it possible to update the bootloader (U-Boot). All sizes in
'dfu_alt_info' are given in 512B blocks (LBA). eMMC size is 58.2 GiB.
The eMMC Boot Partition A (mmc0boot0) layout looks like this:

                 boot0 partition (4 MiB)
       0x0 +----------------------------------+
           |         fwbl1 (12 KiB)           |
      0x18 +----------------------------------+
           |         epbl (76 KiB)            |
      0xb0 +----------------------------------+
           |         bl2 (256 KiB)            |
     0x2b0 +----------------------------------+
           |         dram_train (16 KiB)      |
     0x2d0 +----------------------------------+
           |         ect_test (50 KiB)        |
     0x334 +----------------------------------+
           |         acpm_test (130 KiB)      |
     0x438 +----------------------------------+
           |         bootloader (2 MiB)       |
    0x1438 +----------------------------------+
           |         el3_mon (256 KiB)        |
    0x1638 +----------------------------------+

where U-Boot should be flashed into 'bootloader' partition. So U-Boot
binary size should be 2 MiB or less. The whole boot0 partition is 4 MiB,
but only 2.8 MiB is currently used.

With this change, the U-Boot binary can be updated on eMMC like this:

    => dfu 0 mmc 0
    $ dfu-util -D u-boot.bin -a bootloader

Looking at E850-96 booting diagram at [1,2], it's easy to see how these
binaries are being executed in the same order they are placed in
mmc0boot0 area. E.g. fwbl1 is definitely BL1 (software part of Boot
ROM). So it's obvious the ROM code just reads the binary from eMMC at
0x0 offset into RAM (SRAM?) and executes it.

All mentioned images can be found at [3], as stated in E850-96 U-Boot
documentation. 'dram_train', 'ect_test' and 'acpm_test' areas should be
ignored -- they are not flashed with real images.

[1] doc/board/samsung/e850-96.rst
[2] https://docs.u-boot.org/en/latest/board/samsung/e850-96.html
[3] https://gitlab.com/Linaro/96boards/e850-96/images/-/tree/master/images

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2025-07-25 10:17:21 +09:00
Sam Protsenko
34a6f585f0 board: samsung: e850-96: Setup serial# env var
Setup "serial#" environment variable from the chip ID. The chip ID is
read from Exynos850 SoC OTP (One Time Programmable) memory, which acts
like an EEPROM and contains unique SoC ID. This "serial#" variable is
further used for "fastboot devices" serial number, etc.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2025-07-25 10:17:21 +09:00
Sam Protsenko
ba713dd7d4 usb: dwc3-generic: Add Exynos850 support
The only thing needed from DWC3 glue layer for Exynos850 is to enable
USB clocks. The generic glue layer driver already does that. Add
Exynos850 dwc3 compatible string to enable support for this chip.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2025-07-25 10:17:21 +09:00
Sam Protsenko
80c1606d13 phy: samsung: Add Exynos USB DRD PHY driver
Add DM driver for Exynos USB PHY controllers. For now it only supports
Exynos850 SoC. Only UTMI+ (USB 2.0) PHY interface is implemented, as
Exynos850 doesn't support USB 3.0. Only two clocks are used for this
controller:
  - phy: bus clock, used for PHY registers access
  - ref: PHY reference clock (OSCCLK)

Ported from Linux kernel: drivers/phy/samsung/phy-exynos5-usbdrd.c

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2025-07-25 10:17:21 +09:00
Tom Rini
021783860f Merge tag 'u-boot-imx-master-20250724' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/27149

- Add support for the NXP imx93 frdm board.
- imx93_evk and phycore-imx93 cleanups.
- Convert imx6dl-sielaff to OF_UPSTREAM and fix serial download mode boot.
- Fix crash in imx power-domain.
- Migrate Phytec imx8mm boards to standard boot.
- Fix smatch warnings.
2025-07-24 15:31:17 -06:00
Tom Rini
896f570d56 Merge patch series "Add support for K3 BIST"
Neha Malcom Francis <n-francis@ti.com> says:

This series implements a driver for the BIST (Built-In Self Test) module
for K3 devices. The BIST driver must ideally support triggering of BIST
tests, both PBIST (Memory BIST) and LBIST (Logic BIST) on a core. Both
tests are destructive in nature. Please see links [1] and [2] for
further information regarding the two.

At boot up, BIST is executed by hardware for the MCU domain
automatically as part of HW POST. So BIST has been checked only for the
MCU domain when U-Boot comes up in the usual U-Boot to Linux boot flow.
To facilitate the use-case where some safe firmware is intended to be
run on a safe core, it is best to have triggered the BIST tests on that
core. As an example, we take triggering the BIST tests on the MAIN R52_x
cores. The triggering patch is kept as DONOTMERGE.

The general procedure for triggering BIST on a core is:
	1. Power on the core under test following a sequence
	2. Trigger the BIST test
	3. Reset the core under test following a sequence

BIST tests are triggered from A72 SPL where the DM (Device Manager
firmware that handles power management) is already up and can perform
these power sequences for us.

Boot logs (with LOG_DEBUG and CONFIG_K3_BIST enabled) and DT node kept (already
merged to ti-k3-dts-next [3]):
https://gist.github.com/nehamalcom/3fed504d038b54e3e05ba3874d73d603

[1] https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/latest/exports/docs/sdl/sdl_docs/userguide/j721e/modules/pbist.html#introduction
[2] https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/latest/exports/docs/sdl/sdl_docs/userguide/j721e/modules/lbist.html#introduction
[3] https://lore.kernel.org/all/175205725858.918402.3771835070085533874.b4-ty@ti.com/

Link: https://lore.kernel.org/r/20250716062156.2564297-1-n-francis@ti.com
2025-07-24 13:30:20 -06:00
Bryan Brattlof
6d68ac9730 arm: dts: k3: use SPL_TEXT_BASE for R5 SPL load address
The load address for the R5's SPL is defined in Kconfig by
SPL_TEXT_BASE. Rather than hard coding the load address which could
lead to hard to debug issues if this value is changed, just use the
SPL_TEXT_BASE value.

Reviewed-by: Andrew Davis <afd@ti.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
2025-07-24 13:30:20 -06:00
Rebecca Cran
a70bbc4436 arm: dts: ast2600.dtsi: Fix typo of uart11 reg address
The uart11 reg address was a copy of the value for uart10.
Update it to the correct value.

Signed-off-by: Rebecca Cran <rebecca@os.amperecomputing.com>
2025-07-24 13:30:20 -06:00
Andrew Goodbody
8f3820dc3a fs: exfat: Remove unused label code
Smatch reported a possible buffer overflow in exfat_set_label but it
turns out that this code is unused so just guard the function with
'#ifndef __UBOOT__' as well as exfat_get_label that is also unused and
the helper static find_label.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-07-24 13:30:20 -06:00
Andrew Goodbody
5c0827eede sandbox: eth-raw: Prevent possible buffer overflow
Instead of strcpy which is unbounded use strlcpy to ensure that the
receiving buffer cannot be overflowed.

This issue found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-07-24 13:30:20 -06:00
Sam Protsenko
70a4d1fa1d treewide: Remove empty board_init() function from all boards
Commit 86acdce2ba ("common: add config for board_init() call")
introduced CONFIG_BOARD_INIT option. This option can be disabled for the
boards where board_init() function is not needed. Remove empty
board_init() calls for all boards where it's possible, and disable
CONFIG_BOARD_INIT in all related defconfigs.

This cleanup was made semi-automatically using these scripts: [1].

No functional change, but the binary size for the modified boards is
reduced a bit.

[1] https://github.com/joe-skb7/uboot-convert-scripts/tree/master/remove-board-init

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Tested-by: Adam Ford <aford173@gmail.com> #imx8mm_beacon
Tested-by: Bryan Brattlof <bb@ti.com>
Acked-by: Peng Fan <peng.fan@nxp.com>  #NXP boards
2025-07-24 13:30:19 -06:00
Neha Malcom Francis
a7ddab97aa arm: mach-k3: j784s4_init: Trigger LBIST and PBIST on MAIN R5 2_0
Trigger all tests of PBIST and LBIST using appropriate calls to set the
core under test (MAIN R5 2_0) to it's required state.

Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
2025-07-24 11:50:21 -06:00
Neha Malcom Francis
b56066e03c drivers: misc: k3_bist: Add K3 BIST driver
Add a driver for the BIST module that support triggering of both PBIST
(Memory BIST) and LBIST (Logic BIST) tests. Also expose the relevant
operations and functions that would be required for an end user to
trigger the tests.

Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
2025-07-24 11:50:21 -06:00
Andrew Goodbody
70bf6e33e1 uclass: Cleanup uclass_find_next_device
uclass_find_next_device always returns 0, so instead make it a void and
update calling sites.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-07-24 11:49:18 -06:00
Tom Rini
7bf2a52b49 Merge tag 'xilinx-for-v2025.10-rc1-v2' of https://source.denx.de/u-boot/custodians/u-boot-microblaze
AMD/Xilinx/FPGA changes for v2025.10-rc1 v2

zynqmp:
- Generate fit-dtb.blob all the time
- Simplify power-domain driver bind

zynqmp_mini:
- Remove PSCI_RESET

fpga:
- Improve user feedback in case of FPGA bitstream load failure

misc:
- Fix kernel-doc in gpio zynq and axi_mrmac

spi:
- Revert fix in STIG mode

[trini: Remove CONFIG_FPGA_VERSALPL=y from sandbox due to
        sandbox+clang+asan test problem]
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-24 08:56:38 -06:00
Tom Rini
47b4a9b1a6 Merge tag 'mmc-master-2025-07-24' of https://source.denx.de/u-boot/custodians/u-boot-mmc
CI: https://source.denx.de/u-boot/custodians/u-boot-mmc/-/pipelines/27140

- Fix emmc error state after mmc write timeout
- Minor cleanup s5p_sdhci
- Support DT upstream for exynos5420 and exynos4210 mmc
2025-07-24 07:54:20 -06:00
Fabio Estevam
b40c9b0c22 imx93_frdm: Add initial board support
Add the initial board support for the NXP i.MX93 FRDM board:

https://www.nxp.com/design/design-center/development-boards-and-designs/frdm-i-mx-93-development-board:FRDM-IMX93

Based on the NXP U-Boot code.

There were attempts to upstream the board devicetree, but it has not been
accepted upstream yet:

https://lore.kernel.org/linux-arm-kernel/20250526-fpg-nxp-imx93-frdm-v2-2-e5ad0efaec33@pengutronix.de/

Once it reaches upstream, we can switch to OF_UPSTREAM.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2025-07-24 08:01:03 -03:00
Ye Li
10b6d472d2 spl: spl_imx_container: Delete uninitialized variable
The 'overhead' variable is uninitialized and actually shall not be used.
Delete it to fix coverity CID 37041718 - Uninitialized scalar variable.

Fixes: 73c40fcb73 ("spl: Refactor spl_load_info->read to use units of bytes")
Reported-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-07-24 08:00:47 -03:00
Fabio Estevam
e01fa565df imx93_evk: Remove PMIC and USB header files
There is no PMIC and USB related C code in this file.

Remove these unneeded header files.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2025-07-24 08:00:28 -03:00
Fabio Estevam
98eae17dd3 imx93_evk: Remove unneeded header files
There is nothing in this file that makes use of the definitions from
sizes.h and stringify.h.

Remove them.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2025-07-24 08:00:28 -03:00
Fabio Estevam
eb6d649065 imx93_evk: Fix the board name in MAINTAINERS title
The board name is "i.MX93 EVK", not "MEK".

Fix it accordingly.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
2025-07-24 08:00:28 -03:00
Andrew Goodbody
110a23e479 imx93: adc: local variable ret should not be unsigned
Local variable ret is declared as unsigned but is used to receive the
return value of functions that return int. ret is then tested for being
negative which must always fail. Change ret to be an int.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-07-24 08:00:08 -03:00
Yannic Moog
e6e8c601ed board: phytec: migrate imx8mm boards to standard boot
remove boot logic from shared env file for phyboard-polis and
phygate-tauri.
Adjust configs for both boards as well.
Space at the beginning of addressable RAM is reserved for space used via
standard boot env variables. CONFIG_SYS_LOAD_ADDR is set to the lowest
address behind the standard boot variables reserved space.

Signed-off-by: Yannic Moog <y.moog@phytec.de>
2025-07-24 07:59:49 -03:00
Frieder Schrempf
4a9d6b2e1d imx: power-domain: Fix crash due to uninitialized 'id' field
In case of the i.MX8M power-domains (i.MX8MQ, MM, MN) there is only
one power-domain for each device. Therefore the 'id' field in struct
power_domain should always be zero.

Currently if a power-domain is accessed after the initial bind, the
'id' field is left uninitialized. This didn't cause any problems
until the following commits were introduced:

9086b64ca0 ("power-domain: Add support for refcounting (again)")
a785ef2448 ("imx: power-domain: Enable refcounting on imx8mp")

Now the 'id' field gets accessed in the power_domain_off() sequence
and the invalid value causes "Synchronous Abort" failures.

This was observed on a i.MX8MM board when running "usb start" and
then "usb stop".

Fix this issue by setting power_domain->id to '0' in
imx8m_power_domain_of_xlate().

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Fixes: d08a194871 ("imx: add support for i.MX8MQ power domain controller")
Fixes: 9086b64ca0 ("power-domain: Add support for refcounting (again)")
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
2025-07-24 07:59:22 -03:00
Frieder Schrempf
25140f8908 configs: imx6dl_sielaff: Set CONFIG_SDP_LOADADDR to fix SDP boot
We need to set CONFIG_SDP_LOADADDR to a reasonable value in order
to successfully load the U-Boot proper image in SPL via SDP.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Acked-by: Peng Fan <peng.fan@nxp.com>
2025-07-24 07:58:59 -03:00
Frieder Schrempf
7056aad696 imx6dl-sielaff: Convert to OF_UPSTREAM
Switch to OF_UPSTREAM to make use of the upstream devicetree.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2025-07-24 07:58:59 -03:00
Vitor Soares
cada57d5b9 toradex: tdx-cfg-block: add verdin i.mx8m mini 0216 pid4
Add PID4 0216 Verdin iMX8M Mini Quad 2GB WB IT to config block handling.

Signed-off-by: Vitor Soares <vitor.soares@toradex.com>
Acked-by: Francesco Dolcini <francesco.dolcini@toradex.com>
2025-07-24 07:56:31 -03:00
Primoz Fiser
51b140f9f3 board: phytec: phycore-imx93: Drop unused include files
Drop unused include files from the PHYTEC phyCORE-i.MX93 board code.

Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
2025-07-24 07:56:14 -03:00
Primoz Fiser
10322524bb board: phytec: phycore-imx93: Drop unused PMIC define
Drop unused define for PCA9450 PMIC register which is already part of
the header file <power/pca9450.h> since commit 1d0d257043 ("imx93_evk:
spl: update pmic settings").

Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
2025-07-24 07:56:14 -03:00
Michal Simek
27fa1e2c17 firmware: zynqmp: Simplify power-domain driver bind
CONFIG_IS_ENABLED macro is covering CONFIG_POWER_DOMAIN or
CONFIG_SPL_POWER_DOMAIN Kconfig symbols based on build target which
simplify logic around binding power domain driver.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/c75627e92eeaffedf0f7e682edd4f6f39f0b5706.1752826352.git.michal.simek@amd.com
2025-07-24 09:06:52 +02:00
Michal Simek
7ad14936e3 arm64: zynqmp: Let fit-dtb.blob generated all the time
There is a value to generate fit-dtb.blob even for cases without SPL
because flows with FSBL also require it.

Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/c2952da3c064d67821cd166d2392db39c1d23b2c.1752822270.git.michal.simek@amd.com
2025-07-24 09:05:40 +02:00
Prasanth Babu Mantena
e6345dfc2a Revert "spi: cadence_qspi: Fix odd byte write issue in STIG mode"
The buffer that is being used to write into the flash needs
to be handled properly with padding of 0xFF. The place that
this is done can be at a more generic place like spi-nor core.

This reverts commit cd91235070.

Signed-off-by: Prasanth Babu Mantena <p-mantena@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20250716070407.2082524-1-p-mantena@ti.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2025-07-24 09:04:04 +02:00
Venkatesh Yadav Abbarapu
ee56866f11 net: xilinx: Fix kernel-doc for axi_mrmac function parameters
The kernel-doc comment for the axi_mrmac_recv function was missing
the colon (':') after the '@packetp' parameter tag.

The kernel-doc comment for the axi_mrmac_free_pkt function was missing
the colon (':') after the 'length' parameter tag.

This caused a Sparse warnings regarding the 'packetp' and 'length'
parameters not being described. Fix the formatting to align
with kernel-doc standards and resolve the warning.

drivers/net/xilinx_axi_mrmac.c:357:
warning: Function parameter or member 'packetp' not described
in 'axi_mrmac_recv'
drivers/net/xilinx_axi_mrmac.c:411:
warning: Function parameter or member 'length' not described
in 'axi_mrmac_free_pkt'

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20250717044855.1359443-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2025-07-24 08:54:16 +02:00
Venkatesh Yadav Abbarapu
62c2c5d247 gpio: zynq: Fix the documentation warning in zynq_gpio_get_bank_pin
The 'dev' parameter in the zynq_gpio_get_bank_pin function was not
described in its kernel-doc comment block, leading to a Sparse warning.

drivers/gpio/zynq_gpio.c:194: warning: Function parameter or member 'dev'
not described in 'zynq_gpio_get_bank_pin'

Add a description for the 'dev' parameter to satisfy the documentation
requirements and improve code clarity for this function.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20250717044632.1353588-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2025-07-24 08:54:16 +02:00
Pieter Van Trappen
d9f1754543 configs: enable FPGA commands and drivers at sandbox_defconfig
Enable to facilitate compiler checks on most FPGA-related sources.

Signed-off-by: Pieter Van Trappen <pieter.van.trappen@cern.ch>
Link: https://lore.kernel.org/r/20250708152455.1214487-7-vtpieter@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2025-07-24 08:54:15 +02:00
Pieter Van Trappen
ac48a75ac1 drivers: fpga: fix function declaration without a prototype
As reported by clang 20.1, fix multiple of the following:
 drivers/fpga/ivm_core.c:593:23: error: a function declaration without
 a prototype is deprecated in all versions of C
 [-Werror,-Wstrict-prototypes]
  593 | long int ispVMDataSize()
      |                       ^
      |                        void

Also fix the following warning from checkpatch.pl:
 WARNING: Prefer 'long' over 'long int' as the int is unnecessary

Signed-off-by: Pieter Van Trappen <pieter.van.trappen@cern.ch>
Link: https://lore.kernel.org/r/20250708152455.1214487-6-vtpieter@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2025-07-24 08:54:15 +02:00
Pieter Van Trappen
354b2a29ec drivers: fpga: cleanup printf usage
Remove `fpga_no_sup` to get rid of Werror=unused-function when all
FPGA configurations are enabled.

Swap all printf calls to log_* as this is now preferred and includes
the calling __func__.

Signed-off-by: Pieter Van Trappen <pieter.van.trappen@cern.ch>
Link: https://lore.kernel.org/r/20250708152455.1214487-5-vtpieter@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2025-07-24 08:54:15 +02:00
Pieter Van Trappen
53a10c8ce9 drivers: fpga: correct compiler errors and warnings
Errors reported by GCC 14.2 when enabling FPGA commands and
drivers. Also many style fixes as reported by checkpatch.pl on the
diffs. Most changes in stratixII.c which has been reorganized as well
to avoid the top function prototypes.

No functional changes.

Signed-off-by: Pieter Van Trappen <pieter.van.trappen@cern.ch>
Link: https://lore.kernel.org/r/20250708152455.1214487-4-vtpieter@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2025-07-24 08:54:15 +02:00
Pieter Van Trappen
5d74cf2204 drivers: fpga: add Kconfig dependency
FPGA_SOCFPGA requires ARCH_SOCFPGA cause socfpga.c contains
arch/arm/mach-socfpga/* include macros.

Signed-off-by: Pieter Van Trappen <pieter.van.trappen@cern.ch>
Link: https://lore.kernel.org/r/20250708152455.1214487-3-vtpieter@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2025-07-24 08:54:15 +02:00
Pieter Van Trappen
f08dcc5524 cmd: fpga: improve user feedback in case of bitstream load failure
In cmd/fpga.c, change some `debug` calls to `log_err` for important
user feedback and use CMD_RET_FAILURE in favor of CMD_RET_USAGE due to
its long output which hides the actual, useful return message. Change
the remaining `debug` calls to `log_debug`. Remove all 'fpga:' and
__func__ strings as log_* has this covered.

For `do_fpga_loads`, move up the `do_fpga_check_params` call for more
consistent command output; use a constant instead of multiple '5' use.

In drivers/fpga/zynq*.c, change 'up to' to 'above' which corrects this
confusing/wrong statement.

Signed-off-by: Pieter Van Trappen <pieter.van.trappen@cern.ch>
Link: https://lore.kernel.org/r/20250708152455.1214487-2-vtpieter@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2025-07-24 08:54:15 +02:00
Michal Simek
86786bdba3 xilinx: zynqmp: Remove PSCI_RESET from mini configurations
There is no reason to call reset in these size constrained configurations
that's why remove it to get some space.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/cb5189d676852cad7ab3c0691490b2d0dac618b4.1751014928.git.michal.simek@amd.com
2025-07-24 08:54:15 +02:00
Iulian Banaga
1080815650 Fix emmc error state after mmc write timeout
This is a fix for the sporadic mmc write failure:
  mmc write failed
  0 blocks written: ERROR

After this happens the emmc will remain in an error state
where subsequent read/writes fail with a timeout.

The mmc driver sends CMD25 - WRITE_MULTIPLE_BLOCK which
can sporadically timeout. When this happens, the mmc driver
aborts the transfer and returns the above error messages.

But the emmc still remains in data transfer mode, since
the timeout was decided by uboot, not by the emmc.

Fix this by sending the STOP_TRANSMISSION command (CMD12)
and waiting for the emmc to be in ready state again (CMD13).

Transferring data blocks after a CMD25 can take anywhere
between 5 and +15s on Samsung EMMCs and the current timeout
is not enough. Increase the timeout by 2x to accommodate the
long transfer times observed.

Signed-off-by: Iulian Banaga <iulianeugen.banaga@mobileye.com>
Acked-by: Jimmy Durand Wesolowski <jimmy.wesolowski@mobileye.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-07-24 12:43:31 +08:00
Jaehoon Chung
bda1e3f0e7 mmc: exynos_dw_mmc: add exynos5420 compatibles
The exynos5420 DTSes in linux kernel uses the compatibles
samsung,exynos5420-dw-mshc{,-smu} instead of just
samsung,exynos-dwmmc. Match the additional compatibles in the driver
to make it possible to use it with DTSes from Linux kernel.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
[ grimler: rebase after clksel reg abstraction and re-write commit message ]
Signed-off-by: Henrik Grimler <henrik@grimler.se>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-07-24 12:35:38 +08:00
Henrik Grimler
95f8a22e2a mmc: s5p_sdhci: add samsung,exynos4210-sdhci compatible
the Exynos4210 devices in u-boot uses samsung,exynos4412-sdhci as
sdhci compatible in their DTSes, while the upstream DTSes uses
samsung,exynos4210-sdhci.

Add samsung,exynos4210-sdhci compatible string for s5p_sdhci driver as
well so that it can be used with upstream DTSes.

Signed-off-by: Henrik Grimler <henrik@grimler.se>
Reviewed-by: Anand Moon <linux.amoon@gmail.com>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-07-24 12:35:35 +08:00
Henrik Grimler
4381d7bb33 mmc: s5p_sdhci: remove duplicated card detect code
The common sdhci infrastructure is already parsing the cd-gpios
property, since commit 451931ea70 ("mmc: sdhci: Read cd-gpio from
devicetree"). The s5p code is therefore duplicated, and also broken
since it assumes that the GPIO value is inverted, while the sdhci code
correctly follows the ACTIVE_LOW/ACTIVE_HIGH flag specified in the
device tree.

This fix was originally authored by Simon Shields:
https://github.com/fourkbomb/u-boot/commit/2eac9dea7903

The change has been tested on exynos4210-i9100, a device similar to
exynos4210-trats.

Signed-off-by: Henrik Grimler <henrik@grimler.se>
Reviewed-by: Anand Moon <linux.amoon@gmail.com>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-07-24 12:35:34 +08:00
Greg Malysa
3532f1f5ed block: Remove blk_find_first/next
In [0], Andrew noted a code quality issue in the implementation of
blk_find_first and blk_find_next. This led to the observation that the
logic of these functions was also likely incorrect, and based on a quick
check it seemed the functions were unused outside of test code, which
did not exercise the potential failure case, so we felt they should be
removed. In [1], a test patch which illustrates the failure in sandbox
is provided for reference.

Because a more thorough check agrees that these functions are unused,
they are currently incorrect, and fixed/removable flags on block devices
prior to probe are unreliable, just remove these functions instead of
fixing them. All potential users should have used blk_first_device_err
instead anyway.

CI results at [2].

[0] https://patchwork.ozlabs.org/project/uboot/patch/20250714-blk-uclass-v1-1-d21428c5f762@linaro.org/
[1] https://gist.github.com/gmalysa/b05e73a5c14bc18c5741a0e0e06a2992
[2] https://gitlab.com/gmalysa/lnxdsp-u-boot/-/pipelines/1931210857

Signed-off-by: Greg Malysa <malysagreg@gmail.com>
Reviewed-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-07-23 17:37:14 -06:00
Michal Simek
cf13f33d3a sysreset: psci: Fix SPL dependency
SYSRESET_PSCI should select SPL_ARM_PSCI_FW only when SPL_SYSRESET is
enabled/required. This change saves 1.6kB on Xilinx ZynqMP Kria platform.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2025-07-23 17:37:11 -06:00
Andrew Goodbody
25d3e0509c cmd: gpt: Fix off by 1 errors
The buffer for a name to be copied into must also contain the
terminating 0 byte but strlen returns the length of the string without
counting that 0 byte. Adjust the length checks to take this into
account.

This issue found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-07-23 17:37:08 -06:00
Andrew Goodbody
d29c1092eb abuf: Remove code that prevented test code running
When abuf was introduced some test code was prevented from running using
a 'return 0' early in the functions. A comment said it crashed on
sandbox due to a 'bug' in realloc. Some time later a bug in abuf_realloc
was fixed but this test code was never enabled.

Remove the early 'return 0' instances so that the test code can run.
Also remove some checks that relied on the implementation details of the
U-Boot memory code as these can fail on sandbox which uses system memory
code. Besides that this code should be testing abuf implementation not
the underlying memory code which has its own tests.
Finally use a new #define for the allocs that are meant to fail to
ensure they do fail on all CI platforms.

This issue found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-07-23 17:37:05 -06:00
Tom Rini
71c96a8b2a Azure: Temporarily switch to GitHub mirror of u-boot-test-hooks
In order to unblock this CI workflow for the moment, switch to using a
mirror of u-boot-test-hooks on GitHub rather than source.denx.de.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-23 13:36:37 -06:00
Tom Rini
67c791dcdf patman: Update test for Anatolij's new email address
This test was failing due to matching on Anatolij's old email address.
Switch to the new one.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-23 13:36:37 -06:00
Tom Rini
d0b9b9a80f Merge patch series "mkimage: validate default configuration reference"
Aristo Chen <jj251510319013@gmail.com> says:

This patch series introduces a validation step in `mkimage` to ensure that
the `default` property under the `/configurations` node in a FIT image
references a valid subnode. If the referenced node does not exist, mkimage
now prints an error and fails early. This helps prevent runtime failures
when U-Boot attempts to boot using an undefined configuration.

The first patch implements the validation logic in `fit_image.c`. The second
patch fixes an invalid default configuration reference exposed by this new
check in the `k3-am65-iot2050-boot-image.dtsi`. The final patch adds a test
case to verify that mkimage correctly fails when an invalid default
configuration is present in the ITS file.

This series improves the robustness of FIT image generation and helps
catch malformed image trees during build time.

Link: https://lore.kernel.org/r/20250715130317.3886-1-aristo.chen@canonical.com
2025-07-23 13:12:22 -06:00
Aristo Chen
93d09d3bd8 test: fit: add test case for invalid default configuration reference
Recent changes to mkimage introduced a validation step to ensure that
the 'default' property under the /configurations node in a FIT image
references a valid configuration subnode. If the referenced node is
missing, mkimage will now return an error.

This patch adds a Python test case to verify that mkimage correctly
fails when the 'default' configuration does not exist. The test creates
a minimal ITS with an invalid default reference and checks that mkimage
produces the expected error message.

Signed-off-by: Aristo Chen <aristo.chen@canonical.com>
2025-07-23 13:12:16 -06:00
Aristo Chen
edb4bf3868 tools: fit_image: validate existence of default configuration node
When a FIT image declares a default configuration via the
'configurations/default' property, it must reference a valid subnode
under the /configurations node. If the named default does not exist,
U-Boot will fail to boot the image when no explicit configuration is
provided.

This patch adds a validation step in mkimage to check that the
referenced default configuration node is present. If not, mkimage will
print an error and abort.

This helps catch malformed or outdated ITS files early at build time
instead of deferring failure to runtime.

Signed-off-by: Aristo Chen <aristo.chen@canonical.com>
2025-07-23 13:12:16 -06:00
Aristo Chen
f7b03695d4 arm: k3-am65-iot2050: Fix invalid default configuration reference
mkimage introduced a validation step to ensure that the 'default'
property under the /configurations node in a FIT image refers to a
valid subnode. This exposed an issue in the
k3-am65-iot2050-boot-image.dtsi, where the 'default' property was set to
"ti/k3-am6528-iot2050-basic" and "ti/k3-am6528-iot2050-basic-pg2", which
do not correspond to actual configuration node names.

This patch updates both /configurations nodes to reference the correct
subnode.

Without this fix, mkimage will fail with an error:
"ERROR: Default configuration 'ti/k3-am6528-iot2050-basic' not found
under /configurations"

An upcoming commit will validate the if the default configuration exists

Signed-off-by: Aristo Chen <aristo.chen@canonical.com>
2025-07-23 13:12:16 -06:00
Tom Rini
a9aed78a6d Merge patch series "bootstd: rauc: Small fixes"
Martin Schwan <m.schwan@phytec.de> says:

Fix some small bugs that I noticed during testing.

Link: https://lore.kernel.org/r/20250714-wip-bootmeth-rauc-fixes-v1-0-69d2b80e7606@phytec.de
2025-07-22 13:53:23 -06:00
Martin Schwan
f271b06270 bootstd: rauc: Only scan all partitions instead of boot files
Only scan for the existence of all required partitions of a RAUC system,
instead of searching for boot script files in all of them.

Previously, it might have occurred, that a slot did not contain required
files and RAUC already marked the corresponding slot as bad (not
suitable for booting). In that case, scanning for a non-existence boot
script would result in an error (and thus not booting anything), which
was different behavior compared to the legacy RAUC boot.

Signed-off-by: Martin Schwan <m.schwan@phytec.de>
2025-07-22 13:53:17 -06:00
Martin Schwan
84cef694e7 bootstd: rauc: Fix segfault occurring during private struct access
Fix a potential segmentation fault, by not accessing the member of a
null pointer to a private slot's name field.

Signed-off-by: Martin Schwan <m.schwan@phytec.de>
2025-07-22 13:53:17 -06:00
Martin Schwan
a7d1214d2c bootstd: rauc: Fix potential memory leak
Fix a potential memory leak, by checking the return value of realloc
first, before assigning it to the private list of slots.

Signed-off-by: Martin Schwan <m.schwan@phytec.de>
2025-07-22 13:53:17 -06:00
Holger Brunck
ef7bb0ee1f km: pg-wcom-ls1021xa: update MAINTAINERS
The mainainers for these boards have changed.

Signed-off-by: Holger Brunck <holger.brunck@hitachienergy.com>
Signed-off-by: Tomas Alvarez Vanoli <tomas.alvarez-vanoli@hitachienergy.com>
2025-07-22 13:53:03 -06:00
Tomas Alvarez Vanoli
f1b5cb6f50 km: pg-wcom-ls102xa: call qrio deblock cfg earlier
Move the call to configure the qrio i2c deblock pins earlier.
Before this, the call was happening after the first attempt to deblock
the SDP EEPROM, which resulted in a not correct sequence.

Signed-off-by: Tomas Alvarez Vanoli <tomas.alvarez-vanoli@hitachienergy.com>
Signed-off-by: Holger Brunck <holger.brunck@hitachienergy.com>
2025-07-22 13:53:03 -06:00
Holger Brunck
cec0a39b58 km: pg-wcom-ls102xa: add netdev in board env file
Upcoming boards will have different ethernet interfaces. So we move this
variable out of the common code.

Signed-off-by: Holger Brunck <holger.brunck@hitachienergy.com>
2025-07-22 13:53:03 -06:00
Holger Brunck
6175371f66 arm: ls1021a-pg-wcom: add i2c mux node and eeprom
We are now using the DM code for the i2c mux and to read out the
inventory eeprom. Therefore we need to add the nodes to the specific DTS
files.

Signed-off-by: Holger Brunck <holger.brunck@hitachienergy.com>
2025-07-22 13:53:03 -06:00
Holger Brunck
97e71c09bd km: drop KM_RESERVED_PRAM
This variable is unused since we dropped the support for the Kirkwood
boards.

Signed-off-by: Holger Brunck <holger.brunck@hitachienergy.com>
2025-07-22 13:53:03 -06:00
Tomas Alvarez Vanoli
b408cca7b7 km: qrio: fix set_gpio read/modify/write
Setting GPIO by reading the value of the GPRT register, toggling the
correct bit and then writing it causes input values to transfer to the
output. Here's how (example):

1) set gpio 17 and 18 as input.
2) set gpio 17 output value to 0 (read gprt, change 17 to 0, write).
3) set gpio 18 output value to 0 (read gprt, change 18 to 0, write).

The problem here is that because we set 17 as input, and it's a pull-up,
when we read gprt in step 3, the bit 17 will be 1 and not 0.
Instead of doing read/write/modify, the solution is to keep track
internally of the user set GPIOs, and replace the read step with this
static variable.

Signed-off-by: Tomas Alvarez Vanoli <tomas.alvarez-vanoli@hitachienergy.com>
Signed-off-by: Holger Brunck <holger.brunck@hitachienergy.com>
2025-07-22 13:52:01 -06:00
Andrew Goodbody
23d2c182d4 fastboot: Fix off by 1 error
strlen only reports length of string not including terminating 0 byte
but this has to be included in length of receiving buffer on copy so
adjust length check to be correct.

This issue found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
2025-07-22 11:30:14 -06:00
Ariel D'Alessandro
afca60620a drivers: fastboot: Add support for SPI flash memory
Fastboot currently supports MMC and NAND flash devices. Similarly,
extend the support to SPI flash memories.

Note that in this initial implementation, partitions on the device are
not supported yet, but raw partitions can be set in U-Boot environment.

To define a raw partition descriptor, add an environment variable
similar to the MMC case:

```
fastboot_raw_partition_<raw partition name>=<offset> <size>
```

for example:

```
fastboot_raw_partition_boot=0x0 0x1000000
```

Signed-off-by: Ariel D'Alessandro <ariel.dalessandro@collabora.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
2025-07-22 11:30:14 -06:00
Bryan Brattlof
babae80169 include: env: ti_common: remove bootm_size
As the size of 64b ARM kernels, DTs, vendor firmware, and initial ram
disks continues to grow, the 256MB size limit set aside for image
processing by the bootm command has become too small for some K3
reference boards.

For ARMv7 removing this limit could introduce issues so move the
bootm_size variable to ti_armv7_keystone2.env and remove the limit for
any board using a TI K3 SoC.

Signed-off-by: Bryan Brattlof <bb@ti.com>
2025-07-22 11:30:14 -06:00
Yannic Moog
187ac12927 binman: Fix typing for python >= 3.7
To get the [] annotation working with python 3.7 and 3.8, import
annotations.

Reported-by: Tim Harvey <tharvey@gateworks.com>
Fixes: 21bc3433a4 ("binman: rework dropping absent entries from packaged image")
Reviewed-by: Bryan Brattlof <bb@ti.com>
Signed-off-by: Yannic Moog <y.moog@phytec.de>
Tested-by: Tim Harvey <tharvey@gateworks.com>
2025-07-22 11:30:03 -06:00
Andrew Goodbody
b9db211e39 lmb: Remove unreachable code
Code after a break is unreachable so remove it.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-07-22 11:29:33 -06:00
Holger Brunck
01548afc43 arm: fix lmb region reservation when PRAM is defined
PRAM usage is not taken into account when reserving lmb for ARM
architecture, this means that predefined PRAM region is marked as
reserved by the architecture and cannot be used by other users.

Signed-off-by: Holger Brunck <holger.brunck@hitachienergy.com>
2025-07-22 11:29:31 -06:00
Francesco Dolcini
50ef42c948 board: toradex: Fix variant (wifi/non-wifi) selection
Do not dereference NULL, when "variant" env variable is not present.

Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
2025-07-22 11:28:04 -06:00
Gokul Praveen
7d41363977 configs: KASLR OPTEE RNG support for K3 devices
KASLR, or Kernel Address Space Layout Randomization, is a security
feature in the Linux kernel that randomizes the memory location
where the kernel is loaded during boot.

OP-TEE RNG is a Random Number Generator (RNG) component within the
Open Portable Trusted Execution Environment (OP-TEE) which provides
a random number to U-BOOT and U-BOOT provides this random number
as seed value to the LINUX kernel for KASLR.

Add KASLR OPTEE RNG support across K3 devices by enabling the required
configs.

Signed-off-by: Gokul Praveen <g-praveen@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com>
2025-07-22 10:16:06 -06:00
Anatolij Gustschin
f2f451d9d6 MAINTAINERS: Update email of Anatolij Gustschin
Use new email for community work. Also remove my
capricorn SoM maintainer entry since I do not
have access to this hardware anymore.

Signed-off-by: Anatolij Gustschin <ag.dev.uboot@gmail.com>
2025-07-21 09:22:21 -06:00
Tom Rini
c99f6d9167 Merge tag 'doc-202510-rc1' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request doc-202510-rc1

Documentation:

* describe Dragonwing IQ8 board building/flashing
* move PXE README into HTML documentation
* PXE: mention extlinux.conf and sysboot
* correct references in x86-fit-boot.rst
2025-07-19 08:38:31 -06:00
Tom Rini
7c85ee1f49 Merge tag 'i2c-for-2025.10-take2' of https://source.denx.de/u-boot/custodians/u-boot-i2c
i2c updates for v2025.10

- i2c Kconfig updates from Tom
  - add some driver dependencies
  - added missing include delay.h in iproc_i2c.c

- i2c: muxes: Add PCA9541 i2c arbitrator driver
  from Padmarao Begari

- pca954x: add pca9545 support
  from Frank Wunderlich

- cmd: i2c: fix build when CFG_SYS_I2C_NOPROBES defined with DM_I2C
  From Holger Brunck
2025-07-19 08:38:11 -06:00
Fiona Klute
4caf13f9a6 doc: PXE: mention extlinux.conf and sysboot
These use the same format as PXE boot.

Signed-off-by: Fiona Klute <fiona.klute@gmx.de>
Cc: Tom Rini <trini@konsulko.com>
2025-07-19 12:37:40 +02:00
Fiona Klute
773830f4d9 doc: PXE usage: move environment variables to a separate section
This works better with RST formatting, and avoids duplication.

Signed-off-by: Fiona Klute <fiona.klute@gmx.de>
Cc: Tom Rini <trini@konsulko.com>
2025-07-19 12:37:36 +02:00
Fiona Klute
80bf3ad511 doc: move PXE README into usage documentation
This is only a reformatting, with a few grammar fixes (capitalization,
and a missing "is" and "be" added each).

Signed-off-by: Fiona Klute <fiona.klute@gmx.de>
Cc: Tom Rini <trini@konsulko.com>
2025-07-19 12:37:27 +02:00
Heinrich Schuchardt
579f253384 doc: correct references in x86-fit-boot.rst
Correct the references for

* the x86 boot protocol description
* the FIT file format

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2025-07-19 12:36:53 +02:00
Balaji Selvanathan
9fe50b5a0a doc: board: qualcomm: document Dragonwing IQ8 board building/flashing
Introducing documentation support for Qualcomm Dragonwing IQ8 QCS8300
board. Documents the build and flashing steps.

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
2025-07-19 12:35:20 +02:00
Mark Kettenis
bd0ade7d09 kbuild: Don't mandate gcc as the host compiler
Systems that use clang may not have gcc installed.  Set
HOSTCC to cc and HOSTCXX to c++ like we did before to make those
systems work again.

Fixes: 5f520875bd ("kbuild: Bump the build system to 5.1")
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
2025-07-18 12:22:24 -06:00
Tom Rini
15d99b3bf5 python: requirements.txt: Update a few modules for security issues
The GitHub dependabot tool has reported a number of issues recently with
some modules that we use. While unlikely to be exploitable in the way we
use them, update various libraries to the latest.

Reported-by: GitHub dependabot
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-18 12:22:20 -06:00
Tom Rini
bf9a78f109 misc: Remove DS4510 driver
As no platforms use this driver anymore and it's not been converted from
to DM_I2C for use, remove it.

Fixes: ed7fe2bee1 ("ppc: Remove xpedite boards")
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-18 12:22:17 -06:00
Tom Rini
bdf443ffd5 drivers: misc: Remove pca9551_led driver
This driver has not been converted to DM_I2C and the last platform that
used it was removed as well. Remove the driver.

Fixes: 4bbcec08eb ("arm: Remove mx6dlarm2 board")
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-18 12:22:13 -06:00
Tom Rini
786e1f6dea sandbox: Add dummy sync()
In order to compile more drivers, add an empty sync() function.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-18 12:22:11 -06:00
Tom Rini
a05c01c8e6 input: Tighten dependency requirements for TEGRA_KEYBOARD
This driver requires headers which only exist on Tegra. Express that
requirement in Kconfig as well.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-18 12:22:09 -06:00
Tom Rini
14d20133a8 misc: Tighten requirements on IHS_FPGA driver
This driver requires that the gdsys legacy driver option also be enabled
in order to build. Express that requirement in Kconfig as well.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-18 12:22:05 -06:00
Tom Rini
0f83825802 Merge tag 'u-boot-imx-master-20250717' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/27088

- Add support for the i.MX95 B0 version.
- Enable standard boot for phycore-imx8mp.
- Kconfig fixes for i.MX MMC and FSL_SEC_MON.
- Support 4Gb single die variant of the i.MX8MM Venice board.
2025-07-17 11:42:46 -06:00
Tom Rini
31b5df2e8b Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-riscv
CI: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/27087

- Board: mpfs_icicle: Fix board_fit_config_name_match and disable
  DEBUG_UART
- Board: Add SD card support to the Beagle-V-Fire
- Board: Add support for TH1520-integrated GMACs
2025-07-17 11:39:50 -06:00
Tom Rini
d63b99748f Merge tag 'mmc-2025-07-16' of https://source.denx.de/u-boot/custodians/u-boot-mmc
Drop unused kona_sdhci driver
Tighten config dependencies and a minor cleanup
2025-07-17 11:39:07 -06:00
Tom Rini
fee5f4b619 mmc: Remove unused kona_sdhci driver
As no platforms use this driver anymore, remove it.

Signed-off-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-07-17 11:39:07 -06:00
Tom Rini
f57b4a94c5 mmc: Tighten some mmc driver dependencies
A large number of mmc drivers cannot build without access to some
platform specific header files. Express those requirements in Kconfig as
well.

Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-07-17 11:39:07 -06:00
Andrew Goodbody
1d2723731b mmc: Take cleanup path to free memory on error exit
Instead of returning -EINVAL directly which will not call the cleanup
path to free memory, fix the code to set the error and then goto the
cleanup code.

This issue found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-07-17 11:39:06 -06:00
Tim Harvey
6dc91a8408 venice: display DRAM MR registers and decoding if debug enabled
While this is interesting and useful for debugging there isn't extremely
useful information so we will only show it if debug is enabled.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2025-07-17 09:58:42 -03:00
Tim Harvey
2c692bff83 venice: lpddr4_timing_imx8mm: update ddr phy config for mscale_v3.10
Update the ddr phy config values to those created by the mscale_v3.10
tool. The original values were obtained using mscale_v3.10. The v3.10
tool removed ddr phy register values of 0x0.

This has no functional change but makes comparing and patching ddr
configuration easier in addition to slightly shrinking the DRAM config
size.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2025-07-17 09:58:42 -03:00
Tim Harvey
c2bfdb24c8 venice: lpddr4_timing_imx8mm: add 4gb single die support
Add dram support for the MT53E1G32D2FW-046 RevC part which is a single die
32Gbit density part vs RevA/B which were dual-die parts:
 - use a previously unused EEPROM byte to denote a variant of the
   base config to be patched
 - add a dram description string
 - return the board struct from eeprom_init and pass it to the
   spl_dram_init function so that it has access to the EEPROM
 - move ddr_init into the spl_dram_init so that it can be patched
   in the per-soc init function

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2025-07-17 09:58:42 -03:00
Tim Harvey
393c3de771 venice: lpddr4_timing_imx8mm: add DDRC_ADDRMAP7 config
Add the configuration register for DDRC_ADDRMAP7 which was added in the
RAP spreadsheet v19. This has no functional change but allows DRAM
configuration to be patched in a later commit.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2025-07-17 09:58:42 -03:00
Holger Brunck
94354e3a92 armv8: ls1043a: make some erratas dependent from USB
These erratas are only useful if USB is enabled. If it is disabled
these erratas might cause issues.

Signed-off-by: Holger Brunck <holger.brunck@hitachienergy.com>
2025-07-17 09:58:22 -03:00
David Zang
c71ea4b9a4 soc: imx8ulp: Add celsius unit for temperature
Make temperature unit (celsius) more clear to reduce confusion.

Signed-off-by: David Zang <davidzangcs@gmail.com>
2025-07-17 09:57:55 -03:00
Tom Rini
d4a9ce26cb nxp: Move FSL_SEC_MON related options to arch/Kconfig.nxp
The options related to FSL_SEC_MON are part of the chain of trust
related options and should be under that menu, so move it there.
Furthermore we don't need to prompt for the driver itself but do need to
allow for configuration of the monitor endianess.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-17 09:57:39 -03:00
Tom Rini
7e42f3671d arm: imx: Remove unused mxcmmc driver
As no platforms use this driver anymore, remove it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-17 09:57:23 -03:00
Tom Rini
795f6bd294 brppt2: Use the correct MMC driver
As part of splitting the i.MX parts of FSL_ESDHC out from the more
legacy parts, the FSL_ESDHC_IMX symbol was added. This platform is the
only one which was not converted correctly.

Fixes: e37ac717d7 ("Convert to use fsl_esdhc_imx for i.MX platforms")
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-17 09:57:09 -03:00
Leonard Anderweit
2a32b4f340 phycore-imx8mp: Enable standard boot
Enable standard boot for the phycore-imx8mp and use it as default. Add
all variables required for standard boot to the environment.

Signed-off-by: Leonard Anderweit <l.anderweit@phytec.de>
Tested-by: Martin Schwan <m.schwan@phytec.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2025-07-17 09:56:52 -03:00
Alice Guo
9936724aa9 imx95_evk: Add i.MX95 B0 support
i.MX95 B0 uses image container format v2 and needs DUMMY_DDR so that
update imximage.cfg and container.cfg for it.

Signed-off-by: Alice Guo <alice.guo@nxp.com>
2025-07-17 09:56:33 -03:00
Ye Li
42337445b5 spl: imx: Add support for new PQC container
To support PQC container format which is used for post quantum
authentication on new i.MX parts like i.MX94

The major changes compared to legacy container format is in
signature block, new container tag and version, and new alignment
of container header.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
2025-07-17 09:56:33 -03:00
Alice Guo
cb06e1082a tools: imx8image: Add 2 new commands CMD_CNTR_VERSION and CMD_DUMMY_DDR
i.MX95 B0 uses image container format v2, and `one container header
occupies 0x4000, so that CMD_CNTR_VERSION needs to be added.

The purpose of CMD_DUMMY_DDR is to create a dummy image entry in boot
container prior the DDR OEI image entry. ROM reads the address of DUMMY
DDR image entry and passes it to DDR OEI in OEI entry function as
parameter value, in order to indicate the offset of training data with
the boot container.

Signed-off-by: Alice Guo <alice.guo@nxp.com>
2025-07-17 09:56:33 -03:00
Ye Li
cadc0abe65 arm: imx: Update ELE get_info structure for i.MX94
Since i.MX94, the ELE get_info structure is updated to add
OEM PQC SRK hash, so update it.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
2025-07-17 09:56:33 -03:00
Yao Zi
18c6e8cd69 configs: th1520_lpi4a: Enable network support
Enable the network stack, the designware ethernet driver and
corresponding glue driver. The Lichee Pi 4A board ships two RTL8211F
phys, both attached to GMAC 0, thus support for Realtek phys and DM
support for MDIO devices are enabled as well.

Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-07-17 14:37:40 +08:00
Yao Zi
e875813600 riscv: dts: th1520: Describe GMACs and enable them on Lichee Pi 4A
TH1520 SoC ships two MAC controllers based on Designware Ethernet IP
that are capable of Gigabit operation. Describe them in SoC devicetree
and enable them for Lichee Pi 4A.

Signed-off-by: Yao Zi <ziyao@disroot.org>
Acked-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-07-17 14:37:40 +08:00
Yao Zi
8a3c3a8a11 drivers: net: Add T-Head DWMAC glue layer
The Designware IP integrated in TH1520 SoC requires extra clock
configuration to operate correctly. The Linux kernel's T-Head DWMAC glue
driver is ported and adapted to U-Boot's API.

Signed-off-by: Yao Zi <ziyao@disroot.org>
Acked-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-07-17 14:37:40 +08:00
Yao Zi
12b90ea3c2 riscv: cpu: th1520: Limit upper RAM boundary to 4 GiB
TH1520 SoC ships DMA peripherals that could only reach the first 32-bit
range of memory, for example, the GMAC controllers. Let's limit the
usable top of RAM below 4GiB to ensure DMA allocations are accessible to
all peripherals.

Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-07-17 14:37:40 +08:00
Yao Zi
00a3b0eb8e clk: thead: th1520-ap: Correctly handle flags for dividers
Unlike the gate clocks which make no use of flags, most dividers in
TH1520 SoC are one-based, thus are applied with CLK_DIVIDER_ONE_BASED
flag. We couldn't simply ignore the flag, which causes wrong results
when calculating the clock rates.

Add a member to ccu_div_internal for defining the flags, and pass it to
divider_recalc_rate(). With this fix, frequency of all the clocks match
the Linux kernel's calculation.

Fixes: e6bfa6fc94 ("clk: thead: Port clock controller driver of TH1520 SoC")
Signed-off-by: Yao Zi <ziyao@disroot.org>
Acked-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-07-17 14:37:40 +08:00
Eoin Dickson
cde3d1ff30 spi: coreqspi: add xfer function for PolarFire SoC
Add xfer function to PolarFire SoC coreqspi driver. The read and write
operations are limited to one byte at a time instead of four as CMD18
(multiple block read) reads garbage when four byte ops are enabled.

Signed-off-by: Eoin Dickson <eoin.dickson@microchip.com>
Acked-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-07-17 14:37:36 +08:00
Eoin Dickson
63e8a80cb3 gpio: add PolarFire SoC GPIO and Core GPIO driver
This driver adds GPIO support for PolarFire SoC family, this is required
to add sd card support on the Beagle-V-Fire as it uses GPIO chip selects

Signed-off-by: Eoin Dickson <eoin.dickson@microchip.com>
Acked-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-07-17 14:37:36 +08:00
Conor Dooley
4675216c7a configs: microchip_mpfs_icicle: disable DEBUG_UART
By default DEBUG_UART uses the SBI DBCN extension on S-Mode RISC-V
platforms, but the Icicle Kit's firmware doesn't support it. Since
DEBUG_UART is getting turned on automagically and this is somewhat
misleading, disable it in the Icicle kit's defconfig.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-07-17 14:37:29 +08:00
Conor Dooley
b052fba599 board: mpfs_icicle: fix board_fit_config_name_match()
The loop in the icicle implementation of board_fit_config_name_match()
runs strtok() to split off the vendor portion of the compatible string
using , as the delimiter. strtok() modifies a string in place, so where
the first config and compatible do not match, the compatible has been
modified by the time the loop hits the second iteration.
Since stringlists in dt land are null separated strings, the nulls
strtok() inserts to replace the delimiter increase the number of strings
in the compatible list. When the second iteration of the loop calls
fdt_stringlist_get(), it gets the vendorless portion of the first
compatible string, rather than the second compatible string. Copy each
compatible before calling strtok() to avoid this problem.

The temporary string the compatible is copied to is statically
allocated, as attempts to dynamically allocate it at this stage of boot
were met with "alloc space exhausted" errors.

Fixes: 7c16ebba1e ("board: mpfs_icicle: implement board_fdt_blob_setup()/board_fit_config_name_match()")
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-07-17 14:37:26 +08:00
Mark Kettenis
3b4604a40b board: vexpress_ca9x4: Enable D-cache and MMU
Enable the D-cache, which will also enable the MMU.  The latter
make sure we don't do unaligned access on Strongly-ordered memory,
which has UNPREDICTABLE behaviour according the architecture
definition.  This fixes using U-Boot with recent versions of
QEMU's vexpress-ca9 emulation.

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
2025-07-16 10:56:28 -06:00
Andrew Goodbody
f1c03778a4 boot: Ensure method_flags is initialised before use
The local variable method_flags is only assigned to in some of the
code paths leaving it possibly uninitialised at first use.
Initialise method_flags at declaration to ensure that it cannot be
used uninitialised. Also remove now redundant assignments.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-07-16 10:56:28 -06:00
Rasmus Villemoes
343a30aba3 arm: dts: am335x-evm: remove duplicate chosen node
The stdout-path property is already set to this value in the other
chosen node ~15 lines above.

Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
2025-07-16 10:56:28 -06:00
Tom Rini
a76a843792 Merge tag 'u-boot-dfu-20250716' of https://source.denx.de/u-boot/custodians/u-boot-dfu
u-boot-dfu-20250716

Android:
- Fix printing lbaint_t format in AVB and android_ab messages

DFU:
- Fix dfu_config_interfaces() for single interface DFU syntax
2025-07-16 10:56:28 -06:00
Sam Protsenko
89911825a2 dfu: Fix dfu_config_interfaces() for single interface DFU syntax
As stated in DFU documentation [1], the device interface part might be
missing in dfu_alt_info:

    dfu_alt_info
        The DFU setting for the USB download gadget with a semicolon
        separated string of information on each alternate:
            dfu_alt_info="<alt1>;<alt2>;....;<altN>"
        When several devices are used, the format is:
            - <interface> <dev>'='alternate list (';' separated)

So in first case dfu_alt_info might look like something like this:

    dfu_alt_info="mmc 0=rawemmc raw 0 0x747c000 mmcpart 1;"

And in second case (when the interface is missing):

    dfu_alt_info="rawemmc raw 0 0x747c000 mmcpart 1;"

When the interface is not specified the 'dfu' command crashes when
called using 'dfu 0' or 'dfu list' syntax:

    => dfu list
    "Synchronous Abort" handler, esr 0x96000006, far 0x0

That's happening due to incorrect string handling in
dfu_config_interfaces(). In case when the interface is not specified in
dfu_alt_info it triggers this corner case:

    d = strsep(&s, "=");  // now d contains s, and s is NULL
    if (!d)
        break;
    a = strsep(&s, "&");  // s is already NULL, so a is NULL too
    if (!a)               // corner case
        a = s;            // a is NULL now

which causes NULL pointer dereference later in this call, due to 'a'
being NULL:

    part = skip_spaces(part);

That's because as per strsep() behavior, when delimiter ("&") is not
found, the token (a) becomes the entire string (s), and string (s)
becomes NULL. To fix that issue assign "a = d" instead of "a = s",
because at that point variable d actually contains previous s, which
should be used in this case.

[1] doc/usage/dfu.rst

Fixes: commit febabe3ed4 ("dfu: allow to manage DFU on several devices")
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Link: https://lore.kernel.org/r/20250709042342.13544-1-semen.protsenko@linaro.org
Signed-off-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
2025-07-16 10:56:28 -06:00
Tom Rini
d9a9b4e352 common/avb_verify.c: Make use of LBAF for printing lbaint_t
When printing the contents of an lbaint_t variable we need to use LBAF
to print it in order to get the correct format type depending on 32 or
64bit-ness.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Link: https://lore.kernel.org/r/20250702010603.19354-2-trini@konsulko.com
Signed-off-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
2025-07-16 10:56:28 -06:00
Tom Rini
116d15939b boot/android_ab.c: Make use of LBAF for printing lbaint_t
When printing the contents of an lbaint_t variable we need to use LBAF
to print it in order to get the correct format type depending on 32 or
64bit-ness. Furthermore, printed message should not be split as that
makes finding them harder, so bring this back to a single line.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Link: https://lore.kernel.org/r/20250702010603.19354-1-trini@konsulko.com
Signed-off-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
2025-07-16 10:56:28 -06:00
Holger Brunck
070c48fdb6 cmd: i2c: fix build when CFG_SYS_I2C_NOPROBES defined with DM_I2C
When DM_I2C is enabled and CFG_SYS_I2C_NOPROBES is defined, the
building is broken due to already existing 'bus' local variable.
Rename udevice 'bus' to 'cur_bus' to fix this.

Signed-off-by: Holger Brunck <holger.brunck@hitachienergy.com>
2025-07-16 09:21:03 +02:00
Tom Rini
fb98816439 i2c: Kconfig: Tighten some i2c driver dependencies
A few i2c drivers cannot build without access to some platform specific
header files. Express those requirements in Kconfig as well.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-16 09:20:13 +02:00
Tom Rini
7def358efc i2c: Add missing <linux/delay.h> to iproc_i2c.c
This driver makes delay function calls while relying on an indirection
inclusion of <linux/delay.h>. Add the missing include directly.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-16 09:20:13 +02:00
Stefan Roese
bcc7bc69b9 MAINTAINERS: Update email of Stefan Roese
Use the @mailbox.org mail address also for community work.

Signed-off-by: Stefan Roese <stefan.roese@mailbox.org>
2025-07-15 11:20:10 -06:00
Tom Rini
2af7f4a456 Merge patch series "drivers/net/airoha_eth: fixes"
Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> says:

Several fixes for the airoha ethernet driver.

Link: https://lore.kernel.org/r/20250709092810.4032971-1-mikhail.kshevetskiy@iopsys.eu
2025-07-15 09:56:08 -06:00
Mikhail Kshevetskiy
0e59a2ca9d drivers/net/airoha_eth: enable hw padding of short tx packets
Transmission of short packets does not work good for XFI (GDM2) and
HSGMII (GDM3) interfaces. The issue can be solved with:

 - padding of short packets to 60 bytes
 - setting of PAD_EN bit in the corresponding REG_GDM_FWD_CFG(n)
   register.

The issue should present for the lan switch (GDM1) as well, but it does
does not appear due to unknown reason.

This patch set PAD_EN bit for the used GDM.

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
2025-07-15 09:56:01 -06:00
Mikhail Kshevetskiy
997786bbf4 drivers/net/airoha_eth: fix stalling in package receiving
ARCH_DMA_MINALIGN is 64 for ARMv7a/ARMv8a architectures, but RX/TX
descriptors are 32 bytes long. So they may not be aligned on an
ARCH_DMA_MINALIGN boundary. In case of RX path, this may cause the
following problem

1) Assume that a packet has arrived and the EVEN rx descriptor has been
   updated with the incoming data. The driver will invalidate and check
   the corresponding rx descriptor.

2) Now suppose the next descriptor (ODD) has not yet completed.

   Please note that all even descriptors starts on 64-byte boundary,
   and the odd ones are NOT aligned on 64-byte boundary.

   Inspecting even descriptor, we will read the entire CPU cache line
   (64 bytes). So we read and sore in CPU cache also the next (odd)
   descriptor.

3) Now suppose the next packet (for the odd rx descriptor) arrived
   while the first packet was being processed. So we have new data
   in memory but old data in cache.

4) After packet processing (in arht_eth_free_pkt() function) we will
   cleanup the descriptor and put it back to rx queue.

   This will call flush_dcache_range() function for the even descriptor,
   so the odd one will be flushed as well (it is in the same cache line).
   So the old data will be written to the next rx descriptor.

5) We get a freeze. The next descriptor is empty (so the driver is
   waiting for packets), but the hardware will continue to receive
   packets on other available descriptors. This will continue until
   the last available rx descriptor is full. Then the hardware will
   also freeze.

The problem will be solved if the previous descriptor will be put back
to the queue instead of the current one.

If the current descriptor is even (starts on a 64-byte boundary),
then putting the previous descriptor to the rx queue will affect
the previous cache line. To be 100% ok, we must make sure that the
previous and the one before the previous descriptor cannot be used
for receiving at this moment.

If the current descriptor is odd, then the previous descriptor is on
the same cache line. Both (current and previous) descriptors are not
currently in use, so issue will not arrise.

WARNING: The following restrictions on PKTBUFSRX must be held:
  * PKTBUFSRX is even,
  * PKTBUFSRX >= 4.

The bug appears on 32-bit airoha platform, but should be present on
64-bit as well.

The code was tested both on 32-bit and 64-bit airoha boards.

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
2025-07-15 09:56:01 -06:00
Mikhail Kshevetskiy
5d49fa9e56 drivers/net/airoha_eth: fix packet transmission errors
The dma_map_single() function calls one of the functions
  * invalidate_dcache_range(),
  * flush_dcache_range().
Both of them expect that 'vaddr' is aligned to the ARCH_DMA_MINALIGN
boundary. Unfortunately, RX/TX descriptors are 32-byte long. Thus they
might not be aligned to the ARCH_DMA_MINALIGN boundary. Data flushing
(or invalidating) might do nothing in this case.

The same applies to dma_unmap_single() function.

In the TX path case the issue might prevent package transmission (filled
TX descriptor was not flushed).

To fix an issue a special wrappers for
  * dma_map_single(),
  * dma_unmap_single()
functions were created. The patch fix flushing/invalidatiog for the
RX path as well.

The bug appears on 32-bit airoha platform, but should be present on
64-bit as well.

The code was tested both on 32-bit and 64-bit airoha boards.

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
2025-07-15 09:56:01 -06:00
Mikhail Kshevetskiy
189d0b4477 drivers/net/airoha_eth: add missing terminator for compatible devices list
Compatible device list must have a terminator. If terminator is missed
the u-boot driver subsystem will access random data placed after the
list in the memory.

The issue can be observed with the "dm compat" command.

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
2025-07-15 09:56:01 -06:00
Tom Rini
8d51fb54aa Merge patch series "fs: exfat: Fix some Smatch issues"
Andrew Goodbody <andrew.goodbody@linaro.org> says:

Smatch reported issues with variables being dereferenced before NULL
checks and also testing an unsigned variable for being negative.

Link: https://lore.kernel.org/r/20250707-exfat_fix-v1-0-e5783978cd11@linaro.org
2025-07-15 09:55:54 -06:00
Andrew Goodbody
dd4693136b fs: exfat: Remove pointless variable uoffset
In exfat_generic_pread and exfat_generic_pwrite offset is passed in as a
off_t type which is defined as 'unsigned long long' so there is no need
to create the variable uoffset as a uint64_t as this is just a direct
copy of offset. Also remove the impossible test of 'offset < 0' as this
is always false due to offset being unsigned.

This issue found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-07-15 09:55:48 -06:00
Andrew Goodbody
505e273475 fs: exfat: Perform NULL check before dereference
In the functions exfat_pread and exfat_pwrite there is a NULL check for
ctxt.cur_dev but this has already been derefenced twice before this
happens.
Refactor the code a bit to put the NULL check first.

This issue found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-07-15 09:55:48 -06:00
Rasmus Villemoes
f08e29351d tools: mkimage: make size_inc a signed type
In the Fixes commit, I initialized size_inc from the return value of
the new fit_estimate_hash_sig_size() helper. That helper may fail and
report that by returning a negative value, but I overlooked that
size_inc had type size_t, and hence the error check doesn't work.

Change size_inc to have type int so the error check works.  Inside the
loop, it is passed to another function as a size_t parameter, but
that's fine, because we know it is non-negative, and its value may be
incremented in steps of 1024 and is capped at ~64K, so it will
certainly never overflow an int.

Fixes: 7d4eacb0e6 ("mkimage: do a rough estimate for the size needed for hashes/signatures")
Addresses-Coverity-ID: 569495: Integer handling issues  (NEGATIVE_RETURNS)
Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
2025-07-15 09:55:41 -06:00
Andrew Goodbody
9204cae093 fs: btrfs: Do not free multi when guaranteed to be NULL
multi is guaranteed to be NULL in the first two error exit paths so the
attempt to free it is not needed. Remove those calls.

This issue found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-07-15 09:55:37 -06:00
Weijie Gao
70db2be9fb net: mediatek: correct the AN8855 TPID value in port isolation settings
The TPID value should be 0x9100 instead of 0x8100 according to the
datasheet.

Fixes: cedafee9ff (net: mediatek: add support for Airoha AN8855 ethernet switch)
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2025-07-15 09:55:34 -06:00
Andrew Goodbody
cd79a2839b ofnode: NULL check bootscr_flash_size before dereference
Move the NULL check of bootscr_flash_size to before the first time it is
dereferenced to avoid any possible segment violations.

This issue found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2025-07-14 15:16:56 -06:00
David Zang
5f70be08b0 Fix autoboot countdown printing wrong
Originally when bootdelay >99, the countdown breaks. Setting bootdelay
at 101 or bigger will trigger this error.

Signed-off-by: David Zang <davidzangcs@gmail.com>
2025-07-14 15:16:53 -06:00
Anshul Dalal
b7d70fe68b configs: am62x: fix CONFIG_NR_DRAM_BANKS to 1
CONFIG_NR_DRAM_BANKS defines the number of DRAM banks on the
device. The default value of NR_DRAM_BANKS for ARCH_K3 is set to 2
(arch/arm/mach-k3/Kconfig:199) but should be 1 for am62x platforms.

This patch updates NR_DRAM_BANKS value for all am62x platforms to 1.

Fixes: 2969ed31b8 ("configs: Add am62x_beagleplay_*_defconfig")
Fixes: 2d257d9279 ("configs: Add configs for AM62x SK")
Fixes: 085cd6459d ("board: phytec: am62x: Add PHYTEC phyCORE-AM62x SoM")
Fixes: 7d1a10659f ("board: toradex: add verdin am62 support")

Signed-off-by: Anshul Dalal <anshuld@ti.com>
2025-07-14 15:16:51 -06:00
Andrew Goodbody
22039ef94a pci: Assign a default value on reads on error
Many callers of PCI read functions do not check the return value for
error before using the variable that should contain the value read were
there not to be an error. However in the error case this variable is
never assigned to and so will contain uninitialised data.
To provide some certainty as to behaviour in the error case assign a
default value of all bits set.

This issue found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-07-14 15:16:48 -06:00
Lucas Dietrich
6a269b7fde ecdsa: fix segfault in mkimage when "-r" option is not set
Fix a segmentation fault in the ECDSA signing logic of `mkimage`
that occurs when the "-r" option is not specified.

This reproduces the logic in `lib/rsa/rsa-sign.c` by checking if
`info->require_keys` is non-null before passing it to
`fdt_setprop_string()`.

Signed-off-by: Lucas Dietrich <lucas.dietrich.git@proton.me>
2025-07-14 15:16:45 -06:00
Andrew Goodbody
41713b9967 scsi: Make static functions consistent using lbaint_t
The static helper functions are inconsistent in their use of their third
parameter which is used to pass a block count. Keep consistency by
always using lbaint_t here. This will fix an issue where two left shifts
were overflowing the variable type in use.

This issue found by Smatch

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2025-07-14 15:16:43 -06:00
Ilias Apalodimas
c28ff2112a tools: gen_ethaddr_crc: Make functions static
These functions are only used locally. Enabling -Wmissing-prototypes
triggers a warning. Mark them as static.

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-07-14 15:16:40 -06:00
Ilias Apalodimas
d2a5bb2104 tools: ublimage: Make ublimage_check_params() static
This functions is only used locally and triggers a warning when
compiling with -Wmissing-prototypes. Mark it as static.

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-07-14 15:16:38 -06:00
Ilias Apalodimas
2115ec51d4 tools: mkenvimage: Make xstrtol() static
This function is only used locally. Enabling -Wmissing-prototypes triggers
a warning. Mark it as static.

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-07-14 15:16:35 -06:00
Ilias Apalodimas
bcc8d24d62 tools: bmp_logo: Mark local functions with static
These functions are only used locally. Enabling -Wmissing-prototypes triggers
a warning. Mark them as static.

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-07-14 15:16:33 -06:00
Andrew Goodbody
bae3a34cb9 cros_ec: sandbox: Use correct value for number of slots
In the definition of struct ec_state the number of slots that are
created is VSTORE_SLOT_COUNT (==4) but the value of req->slot is
checked against EC_VSTORE_SLOT_MAX (==32) so this can lead to memory
access beyond that allocated.
Instead change the size check to use VSTORE_SLOT_COUNT to ensure it
matches what has actually been allocated.

This issue found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
2025-07-14 15:16:30 -06:00
Philip Molloy
ebfbc77109 README: remove obsolete note
Renaming SPL to XPL fixes the issue referenced in this note so the note
is no longer necessary

Fixes: 1d6132e2a2 ("global: Use CONFIG_XPL_BUILD instead of CONFIG_SPL_BUILD")

Signed-off-by: Philip Molloy <philip.molloy@analog.com>
2025-07-14 12:44:04 -06:00
Philip Molloy
b4c65b337a gpio: add SPL to Kconfig option description
DM_GPIO_LOOKUP_LABEL and SPL_DM_GPIO_LOOKUP_LABEL had the same
description and therefore appeared to be duplicates in Kconfig frontends

Signed-off-by: Philip Molloy <philip.molloy@analog.com>
2025-07-14 12:44:04 -06:00
Philip Molloy
b476530a84 pinctrl-uclass: update comment to reflect code
The logic was updated without modifying the comment above it

Fixes: 72b8c6d1eb ("pinctrl: don't fall back to pinctrl_select_state_simple()")

Signed-off-by: Philip Molloy <philip.molloy@analog.com>
2025-07-14 12:44:04 -06:00
Tom Rini
f1e5599241 Merge patch series "integer limit macro consolidation"
Rasmus Villemoes <ravi@prevas.dk> says:

I was bitten by our limit macros not being usable in #if conditionals
when building a standalone app. It turns out that the work to fix that
had already been started by the inclusion of the mbedtls library, so
it's something that people do hit.

Let's finish the job by providing suitable limit macros for all three families:

- Standard C types, char, short, ...
- Kernel-style fixed-width types s8, u64, ...
- POSIX/C99 fixed-width types int16_t, uint32_t, ...

Please note that a naive approach like spelling out the full decimal
value for the constants doesn't really work, as there is no such thing
as a "negative integer constant". That is, doing

#define LLONG_MIN -9223372036854775808LL

would lead to the compiler complaining

  warning: integer constant is so large that it is unsigned

and the type of that LLONG_MIN would actually be "unsigned long long", so e.g.

#if LLONG_MIN >= 0
#warning "LLONG_MIN is not negative?"
#endif

would fire.

Link: https://lore.kernel.org/r/20250707203655.613340-1-ravi@prevas.dk
2025-07-14 12:43:33 -06:00
Rasmus Villemoes
dd260d95fd limits.h: provide all limit macros for standard [u]intNN_t types
Currently, we only have UINT32_MAX and UINT64_MAX in limits.h, and
then stdint.h and kernel.h somewhat randomly define UINT8_MAX and
INT32_MAX, respectively.

Provide a full set of definitions in terms of the min/max macros for
the types that [u]intNN_t are defined in terms of, namely the {s,u}NN
ones.

Try to avoid breaking whatever depended on getting UINT8_MAX from our
compat stdint.h by replacing it with an include of limits.h.

Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
2025-07-14 12:43:28 -06:00
Rasmus Villemoes
0604595c16 move limits for sNN/uNN types from kernel.h to limits.h
Since we define the {s,u}{8,16,32,64} types the same way on all
architectures, i.e. everybody uses asm-generic/int-ll64.h, we can just
define the associated limit macros in terms of those for the
corresponding types. This eliminates another set of limit macros that
are not usable in #if conditionals.

These type names and macros are not C or POSIX, so there's no language
violation, but certainly a violation of developers' reasonable
expectations.

Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
2025-07-14 12:43:28 -06:00
Rasmus Villemoes
dc323f3bee move more limits from kernel.h to limits.h and standardize their definitions
In a customer project that was building a stand-alone application, I
hit a problem related to the fact that our LONG_MAX and friends are
not standards-compliant, in that they are not "suitable for use in #if
preprocessing directives"

... /toolchain_none/arm-cortexa8-eabi/sys-include/machine/_default_types.h:25:31: error: missing binary operator before token "long"
   25 |   || ( defined(LLONG_MAX) && (LLONG_MAX > 0x7fffffff) )
      |                               ^~~~~~~~~

So following up on commit 13de848338 ("mbedtls: add mbedtls into the
build system"), move the rest of the macros associated to the standard
C types {signed,unsigned} {char, short, int, long, long long} (and of
course bare 'char') to limits.h.

Make use of the fact that both gcc and clang provide suitable
predefined __FOO_MAX__ macros for the signed types, and use a standard
scheme for defining the FOO_MIN and UFOO_MAX macros in terms of
FOO_MAX.

Note that suffixes like L and ULL are allowed for preprocessor
integers; it is (casts) which are not. And using appropriate suffixes,
we can arrange for the type of e.g. UINT_MAX to be "unsigned int" due
to integer promotion rules.

Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
2025-07-14 12:43:28 -06:00
Tom Rini
235e14b0f1 Merge tag 'qcom-main-20250714' of https://source.denx.de/u-boot/custodians/u-boot-snapdragon
CI: https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/pipelines/27056

- Fix unused access in ufetch
- Add missing clock for SM8650
- Port the Linux SPMI GPIO driver and port over SM8550 (other platforms
  should follow)
2025-07-14 08:54:19 -06:00
Rui Miguel Silva
07ddbb89c9 clk: qcom: sm8650: add usb3 noc clk
Commit [0] introduced, correctly, the bubble of qcom clock errors to
make it easy to spot missing clocks in the platforms, and this is a case
of that, add the GCC_CFG_NOC_USB3_PRIM_AXI_CLK clock to sm8650 clock
pool.

0: 7c5460afec ("clk/qcom: bubble up qcom_gate_clk_en() errors")

Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250618093253.225929-1-rui.silva@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-07-14 15:35:24 +02:00
Balaji Selvanathan
9cd3118e4a watchdog: qcom-wdt: Drop read check on write-only WDT_EN register
On some Qualcomm platforms, such as Dragonwing boards, the WDT_EN
register is write-only. Reading it back after enabling the watchdog
can return invalid data or cause unexpected behavior.

In particular, the check:
  if (readl(wdt_addr(wdt, WDT_EN)) != 1)
may fail even though the watchdog is correctly enabled and running.
This leads to misleading error messages and unnecessary failures.

Removing the read check ensures compatibility and avoids false
negatives on platforms where WDT_EN is not readable.

This work builds upon this previous submission:
https://lore.kernel.org/u-boot/20250625094607.1348494-1-gopinath.sekar@oss.qualcomm.com/

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Link: https://lore.kernel.org/r/20250701065738.1644669-1-balaji.selvanathan@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-07-14 15:35:24 +02:00
Casey Connolly
ea166b1db1 qcom_defconfig: enable USB mass storage gadget
Enable the USB mass storage gadget to make it easy to access the
internal storage on the board.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250626132550.353332-1-casey.connolly@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-07-14 15:35:24 +02:00
Andrew Goodbody
8830e72092 cmd: ufetch: Initialise size before first use
The local variable size is not assigned to before it is used
for the first time. Correct this.

This issue was found by Smatch.

Fixes: 86d462c05d (cmd: add a fetch utility)
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Link: https://lore.kernel.org/r/20250626-ufetch_fix-v1-1-025afdb85dc2@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-07-14 15:35:24 +02:00
Neil Armstrong
d8da51a87c gpio: qcom: move pm8550 gpio to new driver
Move support of the pm8550 gpios to the newly introduced
driver and drop the compatible entry and the read-only quirk
at the same time from the old driver.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Rui Miguel Silva <rui.silva@linaro.org>
Acked-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250630-topic-sm8x50-pmic-gpio-pinctrl-new-v2-2-cc1512931197@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-07-14 15:35:24 +02:00
Neil Armstrong
d0ceeb944a gpio: qcom: add new driver for SPMI gpios
The current qcom_pmic_gpio driver is too limited and doesn't
support state tracking for all pins like the Linux driver.

Adding full pinconf support would require adding the state
and it's much simpler to restart from scratch with a new
driver based on the Linux one adapted to the U-Boot GPIO
and Pinctrl APIs.

For now only the PMICs I've been able to validate are
added in the compatible list but we should be able to
add the entire list from the Linux driver.

There's a few difference from the Linux driver:
- no IRQ support
- uses the U-Boot GPIO flags that maps very well
- uses the gpio-ranges to get the pins count
- no debugfs but prints the pin state via pinmux callback

It uses the same CONFIG entry as the old one, since
the ultimate goal is to migrate entirely on this new
driver once we verify it doesn't break the older
platforms.

Tested-by: Alexey Minnekhanov <alexeymin@postmarketos.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Rui Miguel Silva <rui.silva@linaro.org>
Acked-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250630-topic-sm8x50-pmic-gpio-pinctrl-new-v2-1-cc1512931197@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-07-14 15:35:24 +02:00
Yao Zi
e80998a77b kbuild: Avoid including architecture-specific Makefile twice
Stranges errors are observed when building U-Boot master for almost any
RISC-V board, the messages are in two types, one is about duplicated
symbols,

	u-boot/arch/riscv/cpu//mtrap.S:32: multiple definition of `trap_entry';
	arch/riscv/cpu/mtrap.o: u-boot/arch/riscv/cpu//mtrap.S:32: first defined here

and the other is fixdep's complaint about missing dependency files,

	fixdep: error opening file: arch/riscv/cpu/.mtrap.o.d: No such file or directory
	fixdep: error opening file: arch/riscv/cpu//.start.o.d: No such file or directory

where the latter could only be reproduced when building parallelly.

Both the two types of errors are about files in arch/riscv/cpu, and
there's a suspicious slash character in the reported path. Looking
through RISC-V-specific Makefiles, there's only one place that may
expand to such a path,

	libs-y += arch/riscv/cpu/$(CPU)/

The right hand expands to "arch/riscv/cpu//" if $(CPU) isn't defined at
the time of including. With some debug statement added to
arch/riscv/Makefile, the output proves that arch/riscv/Makefile is
included twice, once with $(CPU) undefined and once defined correctly
according to CONFIG_SYS_CPU.

Futher bisecting shows an extra include statement against
arch/$(SRCARCH)/Makefile is added in earlier bump of Kbuild system. But
the statement is evaluated before config.mk is included and definition
of $(CPU), causing objects in arch/riscv/cpu/ are built and linked twice
(once as "arch/riscv/cpu/*", and once as "arch/riscv/cpu//*"), resulting
in the error.

Let's simply remove the extra include to fix these nasty errors. For
config targets, bumping Kbuild also introduced a new include to
arch/$(SRCARCH)/Makefile, which is removed as well for consistency.

Fixes: 5f520875bd ("kbuild: Bump the build system to 5.1")
Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Tested-by: Fabio Estevam <festevam@gmail.com>
Tested-by: Bryan Brattlof <bb@ti.com>
2025-07-12 09:49:26 -06:00
Padmarao Begari
55d6d715a4 i2c: muxes: Add PCA9541 i2c arbitrator driver
Add a driver for the PCA9541 i2c bus arbitrator based
on the Linux driver for the same device.

Co-developed-by: Jonathan Stroud <jonathan.stroud@amd.com>
Signed-off-by: Jonathan Stroud <jonathan.stroud@amd.com>
Signed-off-by: Padmarao Begari <padmarao.begari@amd.com>
2025-07-12 07:36:51 +02:00
Frank Wunderlich
4d104f0f5e i2c: muxes: pca954x: add pca9545 support
Add support for 4 channel pca9545 found on Bananapi R4.

Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Acked-by: Michal Simek <michal.simek@amd.com>
2025-07-12 07:36:30 +02:00
Tom Rini
53bd87651e block: sandbox: Add support for SYS_64BIT_LBA
In order to use SYS_64BIT_LBA with this driver we need for "start" to
also be of type lbaint_t and to then use the correct printf format
characters.

Reviewed-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-11 11:33:25 -06:00
Tom Rini
7adb9b03a6 Kconfig: Test for !COMPILE_TEST in some locations
We have a few options that we cannot enable in a "allyesconfig" type
build because we cannot use zero as a default value.

- The logic around HAS_BOARD_SIZE_LIMIT assumes that if we have set this
  then we compare with it. Similarly, we need to set SPL_NO_BSS_LIMIT as
  the default there.
- Both SYS_CUSTOM_LDSCRIPT and ENV_USE_DEFAULT_ENV_TEXT_FILE then prompt
  for a file name to use.
- The SYS_I2C_SOFT driver is a legacy driver which requires a lot of
  configuration within the board config. file instead, so disable it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-11 11:33:25 -06:00
Tom Rini
011079c375 Kconfig: Add COMPILE_TEST option
Take the COMPILE_TEST option from the Linux Kernel v6.15 and since the
wording there is OK for us too, use it verbatim. Also update the default
for WERROR to be COMPILE_TEST which again matches the Linux Kernel.

This is the first big step needed to allow for "allyesconfig" to be
possible as it then lets us then disable things that aren't valid for a
compile only test.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-11 11:33:25 -06:00
Tom Rini
d0ed963690 global: Make ARCH_MISC_INIT a selected symbol
This symbol is not something that the user should be enabling or
disabling but rather the developer for a particular board should select
it when required.

This is mostly size neutral, however a few places do have changes. In
the case of i.MX6ULL systems, it is always the case that
arch_misc_init() could call setup_serial_number() and do useful work,
but was not enabled widely, but now is. In the case of i.MX23/28
systems, we should be able to call mx28_fixup_vt() again here, so do so.
Finally, some platforms were calling arch_misc_init() and then not doing
anything and this results in removing the option.

Acked-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-11 11:33:25 -06:00
Tom Rini
0d50d5fc52 toradex: Switch from ARCH_MISC_INIT to MISC_INIT_R in some cases
The hook arch_misc_init was not intended to be used for per-board hooks.
This can be done with misc_init_r instead, which is what follows
immediately after arch_misc_init. Switch a few platforms.

Acked-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-11 11:33:25 -06:00
Andrew Goodbody
ff8a41ce49 fs: erofs: Do NULL check before dereferencing pointer
The assignments to sect and off use the pointer from ctxt.cur_dev but
that has not been NULL checked before this is done. So instead move the
assignments after the NULL check.

This issue found by Smatch

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Gao Xiang <xiang@kernel.org>
2025-07-11 11:33:25 -06:00
Neha Malcom Francis
a21ec39944 board: ti: Clean up formatting in rm-cfg.yaml
Move to using the latest generated RM YAML configuration files generated
by the K3 Resource Partitioning Tool which updates them to have standard
formatting with respect to indentation.

These files were generated from the untagged commit 41718bd5f915 ("docs: Update
docs and move them to docs folder") of the K3 Resource Partitioning tool. This
tool is packaged as a part of the public SDK and is not otherwise
publicly available.

Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
2025-07-11 11:33:25 -06:00
Tom Rini
c29dfc2bb2 Merge patch series "fs: ext4fs: Fix some issues found by Smatch"
Andrew Goodbody <andrew.goodbody@linaro.org> says:

Smatch reported some issues in the ext4fs code. This includes a
suggestion to use an unwind goto, to not negate a return value and to
ensure that a NULL check happens before the pointer is dereferenced.

Link: https://lore.kernel.org/r/20250704-ext4fs_fix-v1-0-5c6acf4bf839@linaro.org
2025-07-11 11:33:25 -06:00
Tom Rini
b4528976e7 Merge patch series "Create uclass for HW AES cryptographic devices"
Svyatoslav Ryhel <clamor95@gmail.com> says:

Add uclass for HW AES cryptographic devices found on some devices, like
Tegra20/Tegra30 SoC AES engine.

Link: https://lore.kernel.org/r/20250629105711.24687-1-clamor95@gmail.com
2025-07-11 11:33:25 -06:00
Tom Rini
3403e4469b Merge patch series "Enable RNG support for KASLR on Toradex arm64 TI SoMs"
Emanuele Ghidoli <emanuele.ghidoli@toradex.com> says:

This patch series enables RNG support to automatically populate
/chosen/kaslr-seed on the following Toradex arm64 TI System on Modules:
- Verdin AM62
- Verdin AM62P

This improves kernel security by supporting Kernel Address Space Layout
Randomization (KASLR) using a runtime-provided seed.

Link: https://lore.kernel.org/r/20250702134942.1483436-1-ghidoliemanuele@gmail.com
2025-07-11 11:33:24 -06:00
Emanuele Ghidoli
ba57c79c6f configs: verdin-am62p: enable RNG support for KASLR
Enable DM_RNG in U-Boot to populate /chosen/kaslr-seed automatically.
Enable OP-TEE, which supports RNG, to provide entropy.

Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
2025-07-11 11:33:23 -06:00
Emanuele Ghidoli
2d72a0bc43 configs: verdin-am62: enable RNG support for KASLR
Enable DM_RNG in U-Boot to populate /chosen/kaslr-seed automatically.
Enable OP-TEE, which supports RNG, to provide entropy.

Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
2025-07-11 11:33:23 -06:00
Andrew Goodbody
2d6221262e fs: ext4fs: Perform NULL check before dereference
In the function put_ext4 there is a NULL check for fs->dev_desc but this
has already been derefenced twice before this happens. Refactor the code
a bit to put the NULL check first.

This issue found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-07-11 10:44:29 -06:00
Andrew Goodbody
36f05e6224 fs: ext4fs: Use unwind goto to free memory on error
Ensure that allocated memory is freed on error exit replace the direct
return calls with 'goto fail'.

This issue found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-07-11 10:44:29 -06:00
Andrew Goodbody
a7e44898b4 fs: ext4fs: Do not negate error before returning it
In ext4fs_readdir it calls ext4fs_read_file and checks the return value
for non-zero to detect an error. This return value should be returned as
is rather than being negated.

This issue found by Smatch

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-07-11 10:44:29 -06:00
Svyatoslav Ryhel
e82ba0be9b test: dm: add AES engine test
Create a basic test suit for AES DM uclass that covers all available
operations.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2025-07-11 10:43:29 -06:00
Ion Agorria
b01444aa14 cmd: aes: Add support for DM AES drivers
This adds new aes subcommands to use interface provided by AES UCLASS which
can be used to expose HW AES engines.

Signed-off-by: Ion Agorria <ion@agorria.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2025-07-11 10:43:29 -06:00
Ion Agorria
a2e86dafd7 crypto: aes: Add software AES DM driver
This adds AES crypto engine using the AES Uclass implemented in software,
serves as example implementation and for uclass tests.

Those implementing HW AES crypto engine drivers can use this as basis and
replace software parts with the HW specifics of their device.

Signed-off-by: Ion Agorria <ion@agorria.com>
2025-07-11 10:43:29 -06:00
Ion Agorria
0d84494064 dm: crypto: Create AES uclass
Create a basic framework for a group of devices that perform AES
cryptographic operations.

Signed-off-by: Ion Agorria <ion@agorria.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2025-07-11 10:43:29 -06:00
Tom Rini
561134e04d Merge tag 'u-boot-imx-master-20250710' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/27010

- Fix the i.MX8M Nano GPU path.
- Enable RNG support for KASLR on Toradex i.MX8 boards.
- Enable watchdog and clock driver for imx6ulz_smm_m2b.
- Tighten dependencies on CMD_BLOB.
- Remove the rest of i.MX31 support.
2025-07-11 08:38:53 -06:00
Tom Rini
6bb0679377 Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sh
- SH Ether clean ups, RZ/A1 clean ups, RZ/A1 Genmai support
- Gen3 EEPROM DT node clean up
- V4H SA0 BootROM compatible binman etype, SCIF compatible SREC
  generation for Gen4
2025-07-10 16:44:08 -06:00
Magnus Damm
25adecf094 ARM: renesas: Add support for the r7s72100 Genmai board
Add r7s72100 Genmai board support. Serial console, NOR Flash and
Ethernet are known to work however on-board SDRAM is not yet enabled.

Signed-off-by: Magnus Damm <damm@opensource.se>
2025-07-10 19:26:56 +02:00
Magnus Damm
6e20aa243d ARM: renesas: Put common r7s72100 code in board/renesas/common
Break out SoC specific code from the GR-Peach board and put it into the
board/renesas/common directory so it can be easily shared between the
GR-Peach and Genmai boards.

Signed-off-by: Magnus Damm <damm@opensource.se>
2025-07-10 19:26:56 +02:00
Marek Vasut
74fc581374 ARM: renesas: Split common RZ/A1 and GR-PEACH defconfigs
Split the RZ/A1 GR-PEACH defconfig into board-specific defconfig
and common RZ/A1 SoC defconfig. This is a preparatory patch for
new RZ/A1 boards, no functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-07-10 19:26:56 +02:00
Marek Vasut
64a2c3731f arm64: renesas: Switch R-Car V4H to renesas_rcar4_sa0 binman etype
Replace current ad-hoc generation of SA0 header with renesas_rcar4_sa0 binman
etype on Renesas R-Car V4H. The new binman etype generates header which is
almost identical to the current ad-hoc SA0 header, with one difference, the
load length matches the actual payload size, which slightly improves boot time.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-07-10 19:26:56 +02:00
Marek Vasut
583b49a0ce binman: Add renesas_rcar4_sa0 etype
Add new etype which generates the Renesas R-Car Gen4 SA0 header.
This header is placed at the beginning of SPI NOR and describes
where should data from SPI NOR offset 0x40000 be loaded to, and
how much data should be loaded there. In case of U-Boot, this is
used to load SPL and possibly other payload(s) into RT-VRAM.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-07-10 19:26:56 +02:00
Marek Vasut
48ec1fd4f4 arm64: dts: renesas: Clean up sysinfo EEPROM DT description on R-Car Gen3
Most of the sysinfo EEPROM node eeprom@50 is now part of the core DTs,
remove duplicate DT properties from *-u-boot.dtsi . Adjust the phandle
reference to i2c-eeprom in sysinfo node using <&{i2c_*/eeprom@50}> to
avoid need for DT label. No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-07-10 19:26:56 +02:00
Marek Vasut
1fc646fda1 arm: renesas: configs: Drop deprecated comments
Remove various deprecated code comments, no functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-07-10 19:26:56 +02:00
Marek Vasut
f8e0b53264 net: sh_eth: arm: renesas: README: Drop CFG_SH_ETHER_PHY_MODE
Drop CFG_SH_ETHER_PHY_MODE from configuration files, this value
is never used. No functional change intended.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-07-10 19:26:56 +02:00
Marek Vasut
e583ea549e net: sh_eth: arm: renesas: README: Drop CFG_SH_ETHER_PHY_ADDR
Drop CFG_SH_ETHER_PHY_ADDR from README and configuration files, this
value is never used, PHY address is extracted from control DT instead.
No functional change intended.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-07-10 19:26:56 +02:00
Marek Vasut
397b5e9ce4 net: sh_eth: Drop phy_addr assignment
Drop unused struct sh_eth_info *port_info .phy_addr member assignment.
PHY address is extracted from control DT. No functional change intended.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-07-10 19:26:55 +02:00
Marek Vasut
787dafb15a net: sh_eth: arm: renesas: README: Drop CFG_SH_ETHER_CACHE_*
Drop CFG_SH_ETHER_CACHE_WRITEBACK and CFG_SH_ETHER_CACHE_INVALIDATE,
which are now always enabled in the sh_eth driver, because those cache
operations are always available. On architectures which do not implement
cache operations yet, cache operations have to be implemented first.

CFG_SH_ETHER_ALIGNE_SIZE now set as SH_ETHER_ALIGN_SIZE in sh_eth.h
based on architecture and no longer configured on board level.

Remove CFG_SH_ETHER_CACHE_WRITEBACK configuration option from README.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-07-10 19:26:55 +02:00
Marek Vasut
16a9002109 net: sh_eth: Convert cache operations to static functions
Turn the current cache operation macros into static functions to improve
compiler coverage checking. This does change the driver behavior slightly,
the driver now expects those cache operation functions to be available on
all architectures on which it is used. This should pose no problem, as the
driver is only used on 32bit and 64bit ARM, which both have those operations.
The CFG_SH_ETHER_ALIGNE_SIZE is converted to SH_ETHER_ALIGN_SIZE and defined
as either 64 on ARM or 16 on SH.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-07-10 19:26:55 +02:00
Marek Vasut
fc85e55205 net: sh_eth: arm: renesas: README: Drop CFG_SH_ETHER_USE_PORT
The CFG_SH_ETHER_USE_PORT configuration option is a remnant from
before U-Boot DM existed and SH Ethernet made full use of it, and
is no longer used, remove it.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-07-10 19:26:55 +02:00
Marek Vasut
45e0a55ff6 net: sh_eth: Pass struct port_info around
The struct sh_eth_dev .port member is always set to 0, therefore only
single-ported SH Ethernet is ever used. Support for multiple SH Ethernet
ports implemented on driver level is a remnant from before U-Boot DM
existed.

Pass struct sh_eth_info port_info around directly and remove the
struct sh_eth_dev entirely. Handling of multiple ports should be done
by U-Boot DM and multiple per-driver-instance private data.

No functional change intended.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-07-10 19:26:55 +02:00
Marek Vasut
26758c24b9 arm64: renesas: Add Renesas R-Car Gen4 SCIF/HSCIF loader SREC generation
Add Renesas R-Car Gen4 SCIF/HSCIF loader compatible SREC generation.
This is a regular U-Boot SPL SREC augmented with a short header which
describes where to store the received data and how much data to store.
This header is interpreted by the R-Car Gen4 BootROM SCIF/HSCIF loader.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-07-10 19:26:55 +02:00
Marek Vasut
f85d97b26c arm64: renesas: Convert SCIF SREC from u-boot-spl.bin
Convert u-boot-spl.bin instead of u-boot-spl ELF into SCIF loader
compatible SREC. The u-boot-spl.bin includes SPL DT, while the ELF
does not, which leads to failure to start SPL via SCIF loader due
to missing SPL DT. Fix this by using u-boot-spl.bin which includes
the DT.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-07-10 19:26:55 +02:00
Andrew Goodbody
f074616014 nvme: Fix memory leak on error path of nvme_init
The use of log_msg_ret to log a message and return an error meant that
memory allocated earlier in the function was not freed on this error
path. Instead log the message in the same way that log_msg_ret would do
and then goto the cleanup code to free the memory.

This issue found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-07-10 08:41:23 -06:00
Magnus Damm
39b836d898 makefile: Adjust distclean to remove .binman_stamp file
Remove the .binman_stamp file during distclean

Signed-off-by: Magnus Damm <damm@opensource.se>
2025-07-10 08:41:20 -06:00
MD Danish Anwar
c589dc0c24 net: ti: icssg: Read firmware name from device-tree
Update the ICSSG PRU Ethernet driver to read PRU/RTU/TXPRU firmware names
from the Device Tree using the "firmware-name" property, instead of relying
on the hard-coded firmware names. The firmware names are parsed during
prueth_probe() and stored in the prueth->firmwares for each slice. The
driver now uses these dynamically loaded names when starting the PRU cores.

This change improves flexibility and allows firmware selection to be
controlled via the device tree, making the driver more adaptable to
different platforms and firmware configurations.

Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
2025-07-10 08:41:18 -06:00
Tom Rini
9cede1930b disk/part_dos.c: Make use of LBAF for printing lbaint_t
When printing the contents of an lbaint_t variable we need to use LBAF
to print it in order to get the correct format type depending on 32 or
64bit-ness.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-10 08:41:14 -06:00
Tom Rini
3393f3ddac common/log_syslog.c: Add missing include of <env.h>
This file was making environment calls without including <env.h> and so
relying on an indirect inclusion from elsewhere. Add the missing include
directly.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-10 08:41:12 -06:00
Tom Rini
1e8665e513 post: Add dependency on ARM || PPC
The post framework requires architecture specific implementation
details. At the moment this is only done for ARM and PowerPC so express
that requirement in Kconfig as well.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-10 08:41:10 -06:00
Tom Rini
1645f9f979 cmd/Kconfig: Tighten dependencies on CMD_SEAMA
In order to build this command we need to have configured some other
board specific features. Express that requirement in Kconfig as well.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-10 08:41:07 -06:00
Tom Rini
e7342decd5 adc: Tighten some adc driver dependencies
A few adc drivers cannot build without access to some platform specific
header files. Express those requirements in Kconfig as well.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-10 08:41:05 -06:00
Tom Rini
a713fa1b5d ata: Correct two dependency issues
First, the SATA_MV driver can only build on kirkwood or mvebu platforms
due to header requirements, so add that as a dependency here. Second,
SYS_SATA_MAX_DEVICE is also used by the API code so allow it to be
configured in that case.

Reviewed-by: Tony Dinh <mibodhi@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-10 08:41:03 -06:00
Tom Rini
dbe1fa4d26 crypto: aspeed: Tighten some dependencies for the aspeed platforms
Some of the aspeed platform drivers cannot build without platform
specific headers being available. Express those requirements in Kconfig as
well.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-10 08:41:00 -06:00
Tom Rini
60b2eb40d1 crypto: fsl: Only allow these to be chosen on ARM/PowerPC
These drivers require various headers which only exist on the ARM /
PowerPC platforms which implement the hardware. Express that requirement
in Kconfig as well.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-10 08:40:58 -06:00
Tom Rini
42dee43d62 crypto: nuvoton: Tighten some dependencies for the nuvoton platforms
The nuvoton AES driver cannot build without platform specific headers
being available. Express that requirement in Kconfig as well.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-10 08:40:55 -06:00
Tom Rini
0b41329003 dma: ti: Tighten some dependencies for some ti platforms
The TI EDMA3 driver cannot build without platform specific headers being
available. Express that requirement in Kconfig as well.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-10 08:40:52 -06:00
Tom Rini
8a31f18269 gpio: Tighten some gpio driver dependencies
A large number of gpio drivers cannot build without access to some platform
specific header files. Express those requirements in Kconfig as well.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-10 08:40:50 -06:00
Tom Rini
7faaa16a47 sandbox: Add some missing {clr,set,clrset}bits variants
Add the 16, 32 and 64bit versions of the non-endian {clr,set,clrset}bits
macros.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-10 08:40:47 -06:00
Naresh Kumar Ravulapalli
acf964c475 drivers: net: phy: micrel: Try to get phy node from phy-handle
If phy node isn't found in ethernet-phy subnode, try to get it from
phy-handle. And when this fails, only then use Ethernet node. This
fix results in getting correct phy handle properties for the
phy node if defined.

Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>
2025-07-10 08:40:45 -06:00
Alexander Stein
76f11d6de3 arm: imx: imx8m: soc: Fix i.MX8M Nano GPU paths
The SoC node is called 'soc@0', even on NXP branch 6.6-fslc. This fixes
the boot on i.MX8M Nano DualLite, as there is no GPU.

Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
2025-07-10 08:02:11 -03:00
Michael Trimarchi
a4b03f8005 configs: imx6ulz_smm_m2b: Add board watchdog reset configuration
Add the configuration that allow to reset the board from reset
cmd

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2025-07-10 08:02:11 -03:00
Michael Trimarchi
a61e5c6427 configs/imx6ulz_smm_m2b_defconfig: Enable clock framework
Enable the clock framework on the m2b platform as was done
in m2 variant. This helps to increase the NAND controller performance.

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2025-07-10 08:02:11 -03:00
Tom Rini
b284c34725 arm: imx: Remove the rest of i.MX31 support
With the removal of the last i.MX31 platform we can remove the rest of
the underlying architecture code as well.

Fixes: f247354708 ("arm: Remove mx31pdk board")
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
2025-07-10 08:02:11 -03:00
Tom Rini
097e01d56f cmd/Kconfig: Tighten dependencies on CMD_BLOB
In order for this command to build we need to compile
drivers/crypto/fsl/fsl_blob.c and this in turn includes
drivers/crypto/fsl/jr.h which references "ccsr_sec_t" which is only a
defined type for SYS_FSL_SEC_COMPAT >= 4. Express that requirement in
Kconfig as well.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2025-07-10 08:02:11 -03:00
Emanuele Ghidoli
2a7acc865b configs: colibri-imx8x: enable RNG support for KASLR
Enable DM_RNG in U-Boot to automatically populate /chosen/kaslr-seed
and enable CAAM to provide entropy.
Enable ARCH_MISC_INIT to initialize the CAAM job ring.

Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
Acked-by: Francesco Dolcini <francesco.dolcini@toradex.com>
2025-07-10 08:02:11 -03:00
Emanuele Ghidoli
a8b7be5e00 configs: apalis-imx8: enable RNG support for KASLR
Enable DM_RNG in U-Boot to automatically populate /chosen/kaslr-seed
and enable CAAM to provide entropy.
Enable ARCH_MISC_INIT to initialize the CAAM job ring.

Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
Acked-by: Francesco Dolcini <francesco.dolcini@toradex.com>
2025-07-10 08:02:11 -03:00
Emanuele Ghidoli
3d278f0df2 configs: toradex-smarc-imx8mp: enable RNG support for KASLR
Enable DM_RNG in U-Boot to automatically populate /chosen/kaslr-seed.

Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
Acked-by: Francesco Dolcini <francesco.dolcini@toradex.com>
2025-07-10 08:02:11 -03:00
Emanuele Ghidoli
3da2323e7b configs: verdin-imx8mp: enable RNG support for KASLR
Enable DM_RNG in U-Boot to automatically populate /chosen/kaslr-seed.

Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
Acked-by: Francesco Dolcini <francesco.dolcini@toradex.com>
2025-07-10 08:02:11 -03:00
Emanuele Ghidoli
d192a0876a configs: verdin-imx8mm: enable RNG support for KASLR
Enable DM_RNG in U-Boot to automatically populate /chosen/kaslr-seed
and enable CAAM to provide entropy.

Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
Acked-by: Francesco Dolcini <francesco.dolcini@toradex.com>
2025-07-10 08:02:11 -03:00
Heinrich Schuchardt
344e179805 lmb: add missing fallthrough in lmb_alloc_mem()
Add fallthrough to clarify the intent.

Addresses-Coverity-ID: CID 569481: Control flow issues (MISSING_BREAK)
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Acked-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-07-09 10:39:37 -06:00
Tom Rini
a517081af9 cmd: Remove "universe" command.
We have had no platforms that make use of this since 2015, so drop it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-09 10:39:33 -06:00
Tom Rini
b7c87e2828 cmd: Remove "tsi148" command
We have had no platforms that make use of this since 2021, so drop it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-09 10:39:31 -06:00
Tom Rini
da31f4a07c dma: Remove lpc32x_dma driver
This driver has no users after we removed the last supported platform in
2024.

Fixes: 26ed58b40f ("arm: Remove devkit3250 board")
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-09 10:39:28 -06:00
Tom Rini
e6d7477103 gpio: Remove tca642x support
This driver has no users after we removed the last supported platform in
2023.

Fixes: 7a3ee61f55 ("arm: Remove omap5_uevm board")
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-09 10:39:25 -06:00
Yannic Moog
538719cb6a binman: migrate from pkg_resources to importlib
pkg_resources is deprecated, use migration guide in [1] to migrate to
importlib.resources.
Keep the Python 3.6 backwards compatibility.
This also fixes the binman version test which failed for setuptools
versions that print the deprecation warning.
Change from __name__ to __package__ as with the transition from
pkg_resources to importlib_resources using __name__ results in
TypeErrors [2].

[1] https://importlib-resources.readthedocs.io/en/latest/migration.html
[2] https://github.com/python/importlib_resources/issues/60

Reviewed-by: Bryan Brattlof <bb@ti.com>
Signed-off-by: Yannic Moog <y.moog@phytec.de>
2025-07-09 10:39:22 -06:00
Tom Rini
bbca681cde Merge patch series "board: ti: am33xx: Add Ethernet support for Beaglebone Green Eco"
Romain Gantois <romain.gantois@bootlin.com> says:

This is version one of my series which enables Ethernet support on the BBGE
board. This requires three main changes:

 - Describing the MAC<->PHY link and DP83867 PHY accurately in the device
   tree
 - Enabling the RGMII1 pinmux configuration
 - Enabling the DP83867 driver

These changes are all applied in patch 2.

Patch 1 enables excluding the DP83867 driver from SPL. This is done to
avoid size issues when adding the DP83867 driver to the am335x-evm
defconfig.

Link: https://lore.kernel.org/r/20250626-bbge-ethernet-v1-0-5b544fb1898f@bootlin.com
2025-07-09 08:45:33 -06:00
Romain Gantois
48b1f8a396 board: ti: am33xx: Add Ethernet support for Beaglebone Green Eco
Currently, the Ethernet interface of the BBGE board isn't properly
supported.

To support this interface, describe the MAC<->PHY RGMII link and the
DP83867 PHY in the BBGE device tree. Enable the DP83867 PHY driver in
U-Boot Proper and mux the relevant RGMII lines.

Signed-off-by: Romain Gantois <romain.gantois@bootlin.com>
Tested-by: Judith Mendez <jm@ti.com>
2025-07-09 08:45:27 -06:00
Romain Gantois
7eaa8aaa9a net: phy: dp83867: Allow excluding driver from SPL
The DP83867 PHY driver is used by the BeagleBoneGreen Eco board, but adding
it to the am335x-evm defconfig causes SPL to overflow its size limits.

Add a separate option to enable this driver in SPL, so that it can be
enabled in U-Boot without adding unnecessary volume to SPL.

Signed-off-by: Romain Gantois <romain.gantois@bootlin.com>
Tested-by: Judith Mendez <jm@ti.com>
2025-07-09 08:45:27 -06:00
Tom Rini
971bd7614c Merge patch series "Improve Verdin AM62P thermal setup by generalizing ft_board_setup_ex()"
João Paulo Gonçalves <jpaulo.silvagoncalves@gmail.com> says:

In some use cases, board-specific device tree changes must not be overwritten
by system fixups. Although U-Boot provides ft_board_setup_ex() for this
purpose, it is currently only used on TI Keystone. This series makes
ft_board_setup_ex() a generic option, allowing its use by other architectures
and boards.

Additionally, considering that Toradex Verdin-AM62P hardware lifetime
guarantees are based on a 105°C junction temperature (while TI AM62Px supports
up to 125°C), this series implements necessary changes within TI K3 AM62P and
Toradex board code. These changes include exporting common fixup device Tree
functions used in TI K3 for board-code access and also fixup for AM62P thermal
zones to correctly reflect the number of CPU nodes according to the SoC part
number.

Link: https://lore.kernel.org/r/20250623-am62p-fdt-fixup-trip-points-v1-0-12355eb6a72f@toradex.com
2025-07-09 08:40:36 -06:00
João Paulo Gonçalves
a03f4a632b board: toradex: verdin-am62p: Add fixup for critical trip points
While TI AM62P supports up to 125°C junction temperature, Tj, for
industrial and automotive parts, Toradex Verdin-AM62P hardware lifetime
guarantees consider a 105°C Tj. Fixup the device tree temperature
critical trip points to match the hardware specifications. The
implementation ensures the architecture code will not overwrite the
board specific changes by enabling CONFIG_OF_BOARD_SETUP_EXTENDED for
the Verdin-AM62P.

Signed-off-by: João Paulo Gonçalves <joao.goncalves@toradex.com>
Acked-by: Francesco Dolcini <francesco.dolcini@toradex.com>
2025-07-09 08:40:03 -06:00
João Paulo Gonçalves
7f4baa866d arm: mach-k3: am62p: fixup thermal cooling device by cpu number
TI AM62Px devices support CPU throttling based on thermal alerts.
However, the device tree assumes a 4-core configuration. Since the AM62P
also supports 2-core configurations, add a fixup to dynamically adjust
the cooling-device nodes within thermal zones based on the actual number
of CPU cores available.

Signed-off-by: João Paulo Gonçalves <joao.goncalves@toradex.com>
2025-07-09 08:40:03 -06:00
João Paulo Gonçalves
9e672e4260 arm: mach-k3: Export common fdt fixups for use in board code
Avoid code duplication by making the common TI K3 device tree fixup
functions to be reusable by board-specific code.

Signed-off-by: João Paulo Gonçalves <joao.goncalves@toradex.com>
2025-07-09 08:40:03 -06:00
João Paulo Gonçalves
2b7c6b6f3c boot: Make ft_board_setup_ex() generic
In some use cases, board-specific device tree changes must not be
overwritten by system fixups. Although U-Boot provides
ft_board_setup_ex() for this purpose, it is currently only used on TI
Keystone. Make ft_board_setup_ex() to be a generic option, allowing its
use by other architectures/boards. To maintain backward compatibility,
enable it by default on TI Keystone.

Signed-off-by: João Paulo Gonçalves <joao.goncalves@toradex.com>
2025-07-09 08:40:03 -06:00
Andrew Goodbody
074e059527 boot: menu: Do not dereference pointer if pointer is NULL
scene_obj_find can return NULL but this is not checked for before
the return is dereferenced. Add a NULL check.

This issue was found by Smatch.

Also add a NULL check for str.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2025-07-08 18:15:20 -06:00
Andrew Goodbody
c3b43eeaea boot: pxe: Prevent evaluation of uninitialised variable
In the case where parse_sliteral returns an error then label_name
will not have been assigned to. In order to prevent evaluating
label_name in this case add a check for the return value of parse_sliteral.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-07-08 18:15:20 -06:00
Christian Marangi
0ffd456516 env: Fix possible out-of-bound access in env_do_env_set
It was discovered that env_do_env_set() currently suffer from a long
time of a possible out-of-bound access for the argv array handling.

The BUG is present in the function env_do_env_set() line:

name = argv[1];

where the function at this point assume the argv at index 1 is always
present and can't be NULL. Aside from the fact that it's always
better to validate argv entry with the argc variable, situation where
the argv[1] is NULL is actually possible and not an error condition.

A example of where an out-of-bound access is triggered is with the
command "askenv - Press ENTER to ...".
This is a common pattern for bootmenu entry to ask the user input after
a bootmenu command succeeded.

In the context of such command, the while loop before "name = argv[1];"
parse the "-" char as an option arg and increment the argv pointer by
one (to make the rest of the logic code ignore the option argv) and
decrement argc value.

The while loop logic is correct but at the "name = argv[1];" line, the
argv have only one element left (the "-" char) and accessing argv[1]
(aka the secong element from argv pointer) cause an out-of-bound access
(making the bootloader eventually crash with strchr searching in invalid
data)

To better handle this and prevent the out-of-bound access, actually
check the argv entry left (with the use of the argc variable) and exit
early before doing any kind of array access.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2025-07-08 18:15:20 -06:00
Tom Rini
1930a7df10 fit-dtb.blob.gz: Pass "-n" to gzip
Sometimes when building a platform such as imx28_btt3 we can get an
error such as:

gzip: fit-dtb.blob: warning: file timestamp out of range for gzip format
make[1]: *** [Makefile:1219: fit-dtb.blob.gz] Error 2
make[1]: *** Deleting file 'fit-dtb.blob.gz'
make: *** [Makefile:186: sub-make] Error 2

This is typically resolved by telling gzip to ignore the timestamp.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-08 18:15:20 -06:00
Javier Martinez Canillas
6df1b1cd4e tools: termios_linux.h: Fix build error on ppc64
Commit 93b55636b0 ("tools: kwboot: Allow any baudrate on Linux") added a
tcgetattr() function to be used, instead of the libc's termios functions.

This was done to allow using the raw TCGETS2/TCSETS2 ioctls that allow to
support arbitrary baud rates.

This breaks the build for PowerPC, because that architecture does not have
a struct termios2 defined because the termios and ktermios are the same.

On PowerPC, the termios ioctl() emulates the TCGETS2/TCSETS*2 ioctls with
tcgetattr/tcsetattr using just the struct termios (that's as mentioned the
same than what is defined as struct termios2 in other architectures).

So there is no need to use the TCGETS2/TCSETS2 ioctls on that architecture
and just TCGETS/TCSETS ioctls with termios as defined by PowerPC is enough.

Fixes: 93b55636b0 ("tools: kwboot: Allow any baudrate on Linux")
Signed-off-by: Javier Martinez Canillas <javierm@redhat.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2025-07-08 18:15:20 -06:00
Hrushikesh Salunke
61a3e1b043 pci_endpoint: pci_cdns_ti_ep: Fix the include path for header file
The commit under fixes tag includes "pcie-cadence.h" using angle
brackets. Since the header file is not in standard include path change
it to double quotes to ensure proper inclusion and avoid build issues,
especially on older compilers.

Fixes: a4a0edc604 ("pci_endpoint: Add TI K3 Cadence PCIe Endpoint Controller driver")
Signed-off-by: Hrushikesh Salunke <h-salunke@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
2025-07-08 16:19:31 -06:00
Wadim Egorov
537dc703d7 board: phytec: rm-cfg: Update rm-cfg to reflect new resource reservation
With the latest TIFS firmware, an additional virtual interrupt and
event is reserved for TIFS usage on am62x and am62ax devices.

Update the rm-cfg to reflect this new reservation.

Based on commit 87720385ab ("board: ti: rm-cfg: Update rm-cfg to
reflect new resource reservation").

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
2025-07-08 16:19:31 -06:00
Manorit Chawdhry
29be3d7d05 Makefile: Fix of_list_dirs with EXT_DTB
EXT_DTB overrides the of_list_dirs that is passed to binman during
builds. This causes binman to not find the normal DTB paths and instead
it just is able to use the path for EXT_DTB only.

Add the default of_list_dirs that is used for normal binman builds to
EXT_DTB usecase as well.

Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Reviewed-by: Aniket Limaye <a-limaye@ti.com>
2025-07-08 16:19:31 -06:00
Tobias Olausson
0707f73a8b lib/rsa: allow matching pkcs11 path by object id
The object= part matches against the label that the pkcs11 token uses
for that object, but in some cases, specifically with a Yubikey using
ykcs11, where the keys have been imported, the labels differ between the
private and public keys [1], making the object= matching useless. These
keys will have the same id however, so matching against that works for
both the private and public part.

[1]: https://github.com/Yubico/yubico-piv-tool/blob/master/doc/YKCS11/Functions_and_values.adoc#key-alias-per-slot-and-object-type

Signed-off-by: Tobias Olausson <tobias@eub.se>
2025-07-08 16:19:31 -06:00
Andrew Goodbody
ebb2c9e550 common: readline: Fix always true test
The variable base is unsigned so >= 0 is always true. Fix this test
so that it is actually useful. The fix prevents the code from causing
a segfault in the case where Ctrl-w is pressed on a line consisting
only of spaces.

Fixes: dcc18ce0db ("cli: Implement delete-word in cread_line()")
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-07-08 15:35:49 -06:00
Tom Rini
3833600dba Merge patch series "include/ndisc.h: Audit include list"
This series from myself largely completes an audit of extraneous include
directives in 'include/*.h' and does not go in to other directories.

Link: https://lore.kernel.org/r/20250628224352.85694-1-trini@konsulko.com
2025-07-08 13:11:19 -06:00
Tom Rini
e3574b2714 include/vsc9953.h: Audit include list
This file does not need <config.h> nor <miiphy.h> so remove them.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-08 13:11:12 -06:00
Tom Rini
a591af1123 include/spl_gpio.h: Audit include list
This file does not need <asm/gpio.h> so remove it. This file does
however need <linux/types.h> so add that in. This also shows that
arch/arm/mach-rockchip/rk3399/rk3399.c and board/lg/star/star.c were
indirectly getting <asm/gpio.h> from here, so add <asm/gpio.h> to them.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-08 13:11:12 -06:00
Tom Rini
7788df3e92 include/sata.h: Audit include list
This file does not need <part.h> so remove it. This file does however
need <stdbool.h> so add that in.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-08 13:11:12 -06:00
Tom Rini
643607b3f8 include/part.h: Audit include list
This file does not need <linker_lists.h> so remove it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-08 13:11:12 -06:00
Tom Rini
01feea9ab0 include/ndisc.h: Audit include list
This file should not include itself, drop that.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-08 13:11:12 -06:00
Tom Rini
9be6c5f967 Merge patch series "kbuild: Update Makefile.extrawarn to 5.1"
This series from Ilias Apalodimas <ilias.apalodimas@linaro.org> largely
finishes the re-sync with the Linux Kernel v5.1 kbuild system.

Link: https://lore.kernel.org/r/20250627185723.342553-1-ilias.apalodimas@linaro.org
2025-07-08 13:10:12 -06:00
Ilias Apalodimas
5f520875bd kbuild: Bump the build system to 5.1
Our last sync with the kernel was 5.1. Even that was a partial one
as some patches from 4.x kernels were already missing making the
transition to a modern kbuild infeasible.

We are so out of sync now, that tracking the patches and backporting
them one by one makes little sense and it's going to take ages.

This is an attempt to sync up Makefile[.lib/.kbuild].
Unfortunately due to sheer amount of patches this is not easy to review,
but that's what we decided during a community call.

One of the biggest changes is get rid of partial linking entirely and
build .a archives isntead of .o.
We diaviate from the kernel on that. Instead of calling a custom script
to create the archive symbol table, we call ar with rcTP (isntead of
rcSTP) since we want a resulting archive that's sauble with the linker.

The only affected platforms are PPC ones. Unfortunately I don't have any
of them around to test, but the objdump of the resulting files --
arch/powerpc/lib/built-in.[oa] looks identical.

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-07-08 13:10:03 -06:00
Ilias Apalodimas
22595e7430 kbuild: Update Makefile.extrawarn to 5.1
Since we are updating our kbuild system to 5.1, add the relevant
clang changes from upstream

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-07-08 13:10:02 -06:00
Tom Rini
72582405a6 Merge tag 'xilinx-for-v2025.10-rc1' of https://source.denx.de/u-boot/custodians/u-boot-microblaze
AMD/Xilinx changes for v2025.10-rc1

cmd:
- Introduce CMD_HELP Kconfig option

fpga:
- Fix in intel_smd_mb

mini:
- Remove simple-bus driver and description
- Disable CMD_HELP

firmware:
- Fix dependencies
- Switch to new SMC firmware format

cadence qspi:
- Fix read/write STIG mode
- Set tshsl_ns to at least one sclk_ns

sdhci:
- Call sdhci reset if wired

zynqmp-clk:
- Add support for DPLL clock source

zynqmp:
- Sync clock ID bindings with Linux
- defconfig updates
- Enable rng-seed generation

versal:
- Fix clock dependency

versal2:
- defconfig updates
- Enable sysreset

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# gpg:                using EDDSA key 97022C40ACF6D6A516A7596FAB07FEF04EF511F5
# gpg: Can't check signature: No public key
2025-07-08 09:40:39 -06:00
Tom Rini
f75eaf7356 Merge tag 'net-next-20250708' of https://source.denx.de/u-boot/custodians/u-boot-net
Pull request net-next-20250708

lwip:
- Call sys_check_timeouts() and schedule() on RX to fix an issue on
  boards with a watchdog and simplify the code
- Enable IP_FRAG and IP_REASSEMBLY
- Add support for setting the TFTP blocksize at runtime
- Fix DNS initialization in wget
- Add the sntp command
- Move code from net/lwip/${cmd}.c to cmd/lwip/${cmd}.c
2025-07-08 09:34:47 -06:00
Venkatesh Yadav Abbarapu
a00f312e74 arm64: versal2: Remove the ZynqMP Firmware from mini ospi
Remove the config ZYNQMP_FIRMWARE and also update the initial
stack address.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20250707092102.831697-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2025-07-08 15:01:25 +02:00
Venkatesh Yadav Abbarapu
6b772a0bcc cadence_qspi: fix odd byte read issue in STIG mode
In DDR mode, even bytes are read using DMA, while the remaining odd
bytes are read using STIG mode. However, the data is not correctly
transferred into the flash read data lower register because the
supplementary byte of the STIG opcode is not being written to the
opcode extension register, resulting in incorrect data being read.

To resolve this issue, when using STIG transactions, the corresponding
supplementary byte of any STIG opcode must be defined in the Opcode
Extension Register (Lower). Issue has been observed on the Macronix
MX66UM2G45G flashes.

Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20250702053953.640046-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2025-07-08 15:01:25 +02:00
Venkatesh Yadav Abbarapu
bfa3f147e1 spi: cadence_qspi: Set tshsl_ns to at least one sclk_ns
tshsl_ns is the clock delay for chip select deassert. This is the delay in
master reference clocks for the length that the master mode chip select
outputs are de-asserted between transactions.

The minimum delay is always SCLK period to ensure the chip select is never
re-asserted within one SCLK period.

That is why tshsl_ns delay should be at least one sclk_ns value. If it is
less than sclk_ns, set it equal to sclk_ns.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20250702065717.3871435-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2025-07-08 15:01:25 +02:00
Michal Simek
92fcd3c168 xilinx: Disable help command for all mini configurations
There is no reason to have help command available because none is calling
it and only make binary bigger that's why disable it.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/885a74b7f5b28ea7850a6ebaaf879dd8b13e18c8.1751286059.git.michal.simek@amd.com
2025-07-08 15:01:25 +02:00
Michal Simek
43341fc021 cmd: Introduce CMD_HELP
Add option to disable help command in size constrained systems to save some
space. There is also no need to have ifdefs around CMDLINE because all
commands depends on it.
And also mark cmd_help dependency in test_help.py.

Reviewed-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/c17f825fb8a74e1d1912a3fd09a9a880c84a8bfd.1751286059.git.michal.simek@amd.com
2025-07-08 15:00:17 +02:00
Michal Simek
229ec06353 arm64: zynqmp: Enable rng-seed generation
SOM has TPM with RNG in it that's why enable rng-seed generation.

Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/0e55eb3eade94e9cd0ffe04da0618aa6b1589f01.1751442246.git.michal.simek@amd.com
2025-07-08 14:58:44 +02:00
Venkatesh Yadav Abbarapu
cd91235070 spi: cadence_qspi: Fix odd byte write issue in STIG mode
Starting from 'commit <8077d296adff> ("spi: cadence-quadspi: Use STIG
mode for all ops with small payload") the utilization of STIG mode
has been implemented for read and write operations involving less
than 8 bytes of data.

However, following this commit, encountering timeout issues occurs when
writing odd bytes of data in DDR mode, as indicated below:
"jedec_spi_nor flash@0: flash operation timed out
SF: 3 bytes @ 0x0 Written: ERROR -110"

To resolve this issue, the number of bytes to write has been updated
specifically for DDR mode.

Signed-off-by: Tejas Bhumkar <tejas.arvind.bhumkar@amd.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20250704040444.671604-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2025-07-08 14:58:44 +02:00
Venkatesh Yadav Abbarapu
28fe6ea6e5 config: versal2: Update timer clock to 100Mhz
U-Boot timer clock is not updated when it is migrated from
emulator to silicon. Update CONFIG_COUNTER_FREQUENCY to 100Mhz.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20250704090920.678557-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2025-07-08 14:58:44 +02:00
Venkatesh Yadav Abbarapu
22add070a4 arm64: versal2: Enable reset and poweroff via sysreset framework
reset and poweroff are called via hooks in psci driver which is going
around sysreset framework that's why enable sysreset drivers and do
reset and poweroff via this framework.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20250707040607.758919-2-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2025-07-08 14:58:44 +02:00
Venkatesh Yadav Abbarapu
fbd586d358 arm64: versal2: Do not define do_reset() if sysreset is enabled
If sysreset is enabled reset_cpu is defined in sysreset uclass
that's why it can't be in platform/board code.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20250707040607.758919-3-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2025-07-08 14:58:44 +02:00
Venkatesh Yadav Abbarapu
7d8eafcf98 xilinx: zynqmp: disable CONFIG_SPI_FLASH_BAR
Legacy SPI flash devices used a 24-bit (3-byte) addressing scheme,
limiting the addressable memory to 16 MB. To support larger densities
(256 Mbit and higher), extended addressing schemes, such as 32-bit
(4-byte) addressing, were introduced. If the flash density exceeds
16 MB and CONFIG_SPI_FLASH_BAR is disabled, the device will use a
4-byte addressing mode.

Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20250707043738.795179-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2025-07-08 14:58:44 +02:00
Venkatesh Yadav Abbarapu
f289c36f07 config: amd: Enable the SPI_STACKED_PARALLEL config option
Enable the SPI_STACKED_PARALLEL config option for
AMD versal2 platform, as this is required for parallel and
stacked memories.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20250707043037.792987-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2025-07-08 14:58:43 +02:00
Naresh Kumar Ravulapalli
a988d4ea00 drivers: fpga: intel_sdm_mb: Check SIP SMC status in send_bitstream()
While sending bitstream via SIP SMC, busy status received does not
correspond to error, instead it means transfer is accepted but SDM
doesn't have any more free buffer space. Hence, data transmission
is continued when busy status is received.

Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>
Link: https://lore.kernel.org/r/20250701044311.3670-1-nareshkumar.ravulapalli@altera.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2025-07-08 14:58:43 +02:00
Michal Simek
14f627bf43 xilinx: Remove simple-bus description from mini configurations
simple bus node and drivers not bringing up any value for mini
configuration that's why remove it and disable drivers for it to save some
space.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/a51b11fa21c504a19701ebdccc1e61e899e1aed5.1751016029.git.michal.simek@amd.com
2025-07-08 14:58:43 +02:00
Venkatesh Yadav Abbarapu
b714685577 mmc: zynq_sdhci: Reset the host controller
Reset the host controller at the early stage of probe so that the
configuration will be done properly for reboot cases.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20250626062440.295301-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2025-07-08 14:58:43 +02:00
Michal Simek
1b267fe182 firmware: xilinx: Prepare code for new SMC firmware format
Separate code to own function to be able to add new enhancement format.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/cf99fe1af82bc004de3e313d4018464f4504f380.1750858165.git.michal.simek@amd.com
2025-07-08 14:58:43 +02:00
Tom Rini
237574c181 firmware: xilinx: Tighten dependencies for ZYNQMP_FIRMWARE
The ZYNQMP_FIRMWARE code  cannot build without platform specific headers
being available. Express that requirement in Kconfig as well.

Signed-off-by: Tom Rini <trini@konsulko.com>
Link: https://lore.kernel.org/r/20250702010410.18828-1-trini@konsulko.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2025-07-08 14:58:43 +02:00
Padmarao Begari
d8510df627 xilinx: zynqmp: Enable xilinx ethernet phy
Enable xilinx ethernet phy on ZynqMP by default.

Signed-off-by: Padmarao Begari <padmarao.begari@amd.com>
Link: https://lore.kernel.org/r/20250624084645.1185428-1-padmarao.begari@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2025-07-08 14:58:43 +02:00
Padmarao Begari
a5f2aa4b38 clk: zynqmp: Add support for dpll clock source
The clock driver fails to correctly calculate the PLL clock
rate for peripherals when using the DPLL as the clock source.
The DPLL operates within the full power domain, while peripheral
clocks reside in the low power domain. To ensure accurate PLL
clock rate computation when the peripheral clock source is set
to DPLL, the DPLL-to-LPD cross divisor is used.

Signed-off-by: Padmarao Begari <padmarao.begari@amd.com>
Link: https://lore.kernel.org/r/20250618094329.296731-1-padmarao.begari@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2025-07-08 14:58:43 +02:00
Tom Rini
4216a86343 arm: zynqmp: Remove local copy of 'dt-bindings/clock/xlnx-zynqmp-clk.h'
As part of the recent cleanup of dt-bindigns header files we did not
remove our copy of dt-bindings/clock/xlnx-zynqmp-clk.h at the time. This
is because the difference between ours and current upstream is that
current upstream has a #warning to not use it and to instead use
xlnx-zynqmp-clk.h. So we change zynqmp-clk-ccf.dtsi to use the other
and upstream-only file and then delete our dt-bindings file.

Signed-off-by: Tom Rini <trini@konsulko.com>
Tested-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20250612181128.340232-1-trini@konsulko.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2025-07-08 14:58:43 +02:00
Michal Simek
ed1c1385ce clk: versal: Fix clock driver dependency
Driver fully depends on firmware driver to be present that's why change
imply to depends on to cover it.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/bd18a4ce3e65411bb956636d4a2ef4b5fbe8b9e1.1749104235.git.michal.simek@amd.com
2025-07-08 14:58:43 +02:00
Jerome Forissier
203be3197d configs: qemu_arm64_lwip_defconfig: enable CMD_SNTP
Enable the sntp command by default in the arm64 QEMU defconfig for lwIP
since this config is meant to have all the features supported by lwIP.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
2025-07-08 11:07:37 +02:00
Jerome Forissier
a9675211dd doc: add doc/cmd/sntp.rst and remove doc/README.SNTP
Add a proper documentation file for the sntp command in RST format and
drop doc/README.SNTP. The documentation now includes the NET_LWIP
specificities.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
2025-07-08 11:07:37 +02:00
Jerome Forissier
a2a0c7527e lwip: add sntp command
Implement the sntp command when NET_LWIP=y.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
2025-07-08 11:07:37 +02:00
Jerome Forissier
77f0bed326 net: extract function net_sntp_set_rtc() from sntp_handler()
Extract the code that sets the RTC clock from sntp_handler() in
net/sntp.c and make it a new function net_sntp_set_rtc() in
net/net-common.c. This will allow re-use with NET_LWIP.

According to [1] it is safe to assume that all devices have been
converted to DM_RTC so drop the useless code.

[1] https://lists.denx.de/pipermail/u-boot/2025-June/591376.html

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
2025-07-08 11:07:37 +02:00
Jerome Forissier
ab1fdb5436 lwip: ping: accept host name when CONFIG_CMD_DNS=y
Update the ping command so that a host name is accepted in addition to
an IP address, provided DNS support is enabled.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
2025-07-08 11:07:37 +02:00
Jerome Forissier
9501274f94 lwip: add net_lwip_dns_resolve()
Add a helper fonction to convert an IP address (supplied as a text
string) or a host name to an ip_addr_t.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
2025-07-08 11:07:37 +02:00
Jerome Forissier
1361d9f4f0 lwip: dns: do not print IP address when a variable is specified
When calling "dns <hostname> <varname>", do not print out the IP address
of <hostname> onto the console. Print it only when no variable is
passed. The reason is to be able to call do_dns() from another command
in need of the DNS services without polluting the output.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
2025-07-08 11:07:37 +02:00
Jerome Forissier
d3136d22a6 lwip: dns: do not return CMD_RET_FAILURE on successful resolution
The DNS loop checks for a non-zero IP address after DNS resolution, but
the address is in fact never copied into the context. Fix that.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
2025-07-08 11:07:37 +02:00
Jerome Forissier
d3761a31ef lwip: split net/lwip/wget.c
Split net/lwip/wget.c in two: one part which implements CONFIG_WGET
stays in net/ while the part that implements CONFIG_CMD_WGET is moved
into cmd/.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
2025-07-08 11:07:37 +02:00
Jerome Forissier
ba814b8b5a lwip: split cmd/net-lwip.c into one file per command
Move each command in cmd/net-lwip.c into its own file
(cmd/lwip/${cmd}.c).

Suggested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
2025-07-08 11:07:37 +02:00
Jerome Forissier
d63c4434bf lwip: move net/lwip/ping.c to cmd/lwip
Prepare to split the ping command from cmd/net-lwip.c by moving the
implementation from net/lwip/dns.c to cmd/lwip.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
2025-07-08 11:07:37 +02:00
Jerome Forissier
1c55e0370b lwip: move net/lwip/dns.c to cmd/lwip
Prepare to split the dns command from cmd/net-lwip.c by moving the
implementation from net/lwip/dns.c to cmd/lwip.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
2025-07-08 11:07:37 +02:00
Jerome Forissier
0a9374deb8 lwip: remove net/lwip/eth_internal.h
net/lwip/eth_internal.h is not used. Remove it.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
2025-07-08 11:07:37 +02:00
Tim Harvey
d373436f50 net: lwip: wget: initialize dns if a hostname is used in a URL
Initialize dns servers if a hostname (vs ipaddr) is used in a URL.
Otherwise the wget will fail without displaying an error due to
dns_gethostbyname failing silently when no DNS servers are set unless
you have previously performed a 'dns <arg>' command.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
2025-07-08 11:07:37 +02:00
Tim Harvey
a383869d6b net: lwip: move dns init to common function
move the dns init including setting the dns servers from env vars to a
common function as other commands that support hostname lookups will
need this.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
[jf: add CMD_DNS conditional to support NET_LWIP && !CMD_DNS]
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
2025-07-08 11:05:29 +02:00
Tim Harvey
e4e97f7052 net: lwip: tftp: add support for setting blocksize at runtime
Add support for setting the blocksize at runtime via the tftpblocksize env
variable as such is done with the legacy stack (CONFIG_NET).

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
2025-07-08 09:53:59 +02:00
Tim Harvey
50a86eb97f net: lwip: enable IP_FRAG and IP_REASSEMBLY
Enable IP_FRAG and IP_REASSEMBLY to allow packets larger than MTU.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2025-07-08 09:53:59 +02:00
Tim Harvey
08a8d1455a net: lwip: call sys_check_timeouts and schedule on rx
Call schedule() in net_lwip_rx() to service U-Boot tasks and
actions during packet rx.

As a cleanup also move sys_check_timeouts() here and remove it from the
functions that call net_lwip_rx().

This resolves the issue of an active watchdog resetting the board on
long network activities.

Suggested-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
2025-07-08 09:53:59 +02:00
Tom Rini
b379335f14 configs: Resync with savedefconfig
Resync all defconfig files using qconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-07 14:15:18 -06:00
Tom Rini
6d0b8874fd Merge branch 'next' 2025-07-07 14:10:59 -06:00
Tom Rini
7598b469c1 Merge tag 'u-boot-dfu-next-20250703' of https://source.denx.de/u-boot/custodians/u-boot-dfu into next
u-boot-dfu-next-20250703

CI job:
- https://source.denx.de/u-boot/custodians/u-boot-dfu/-/pipelines/26938

Android:
- Fix uninitialized vhdr pointer in image-android.c
- Fix uninitialized vhdr pointer in abootimg cmd

DFU:
- Update maintainers file to include spl/spl_dfu
2025-07-03 08:27:29 -06:00
Tom Rini
1323b480a6 Merge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-riscv into next
CI: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/26936

- RISC-V: Add big-endian build support
- Board: aclint_ipi: Support T-Head C900 CLINT
- Board: mpfs_icicle: Implement
  board_fdt_blob_setup()/board_fit_config_name_match()
- Driver: pinctrl: Port pin controller driver for T-Head TH1520 SoC
- Driver: cache: Update dependency for ANDES_L2_CACHE
2025-07-03 08:26:50 -06:00
Tom Rini
218db7bdbd Merge tag 'efi-next-03072025' of https://source.denx.de/u-boot/custodians/u-boot-tpm into next
Sughosh added EFI HTTP(s) support into our eficonfig application. Up to
now we could only enable that via our efidebug command. Users now get that
option on the eficonfig menu.

Javier implemented support for the EFI_PARTITION_INFO_PROTOCOL,
to provide cached partition information for GPT partition types.
The protocol describes legacy MBR partition types, but that's for backward
compatibility and not implemented by this series.
The protocol is needed by [0], an implementation of a UEFI based A/B boot
protocol for the root filesystem.

Paul added support for EFI_DEBUG_IMAGE_INFO_TABLE. This is part of the EFI
spec and is defining a debug protocol that Google currently uses to debug
their Generic Bootloader project [1][2], using EFI to load Android.
Heinrich contributed a test EFI application for it as well.
The efi_realloc() function he added will realloc any type of memory to
BootServicesData, but keeping in mind the new protocol is the only consumer
he will fix that on a followup patch.

Finally another round of smatch fixes from Andrew cleans up coding errors.

The CI https://source.denx.de/u-boot/custodians/u-boot-tpm/-/pipelines/26935
seems happy

[0] https://gitlab.com/CentOS/automotive/src/ukiboot
[1] https://lpc.events/event/18/contributions/1704/attachments/1550/3231/Android%20Generic%20Boot%20Loader.pdf
[2] https://source.android.com/docs/core/architecture/bootloader/generic-bootloader
2025-07-03 08:25:38 -06:00
Tom Rini
f62062a64d cache: Update dependency for ANDES_L2_CACHE
The cache driver here can only build on RISCV due to header
dependencies. Express that requirement in Kconfig as well.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-07-03 18:11:06 +08:00
Conor Dooley
7c16ebba1e board: mpfs_icicle: implement board_fdt_blob_setup()/board_fit_config_name_match()
The firmware on the Icicle is capable of providing a devicetree in a1 to
U-Boot, but until now the devicetree has been packaged in a "payload" [1]
alongside U-Boot (or other bootloaders/RTOSes) and appended to the image.
The address of this appended devicetree is placed in a1 by the firmware.
This meant that the mechanism used by OF_SEPARATE to locate the
devicetree at the end of the image would pick up the one provided by the
firmware when u-boot-nodtb.bin was in the payload and U-Boot's devicetree
when u-boot.bin was.

The firmware is now going to be capable of providing a minimal devicetree
(quite cut down due to severe space constraints), but this devicetree is
linked into the firmware that runs out of the L2 rather than at the end
of the U-Boot image.

Implement board_fdt_blob_setup() so that this devicetree can be
optionally used, and the devicetree provided in the "payload" can be
used without relying on "happening" to implement the same strategy as
OF_SEPARATE expects in combination with u-boot-nodtb.bin.
Unlike other RISC-V boards, the firmware provided devicetree is only
used when OF_BOARD is set, so that the almost certainly more complete
devicetree in U-Boot will be used unless explicitly requested otherwise.

Implement board_fit_config_name_match(), so that, using the firmware
provided cut-down/minimal dtb, U-Boot can select one of several
devicetrees when MULTI_DTB_FIT is enabled.

Enabling both MULTI_DTB_FIT and OF_BOARD will lead to a conflict
between the two options, with the latter taking priority due to
board_fdt_blob_setup() being executed before board_fit_config_name_match(),
which causes gd->fdt_blob to be overwritten with a pointer to the
minimal devicetree rather than the location of the fit image containing
the multiple dtbs. Let MULTI_DTB_FIT take priority in this case, by
explicitly blocking the override when MULTI_DTB_FIT is enabled.

Link: https://github.com/polarfire-soc/hart-software-services/blob/master/tools/hss-payload-generator/README.md [1]
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-07-03 18:11:02 +08:00
Yao Zi
c7e27f9a4a riscv: cpu: th1520: Enable pinctrl by default
Select PINCTRL_TH1520 in CPU Kconfig entry and update defconfig for
existing TH1520-based boards to ensure PINCTRL is enabled.

Signed-off-by: Yao Zi <ziyao@disroot.org>
Acked-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-07-03 18:10:58 +08:00
Yao Zi
a4f9013e31 riscv: dts: th1520: Add pin controllers
Describe the three pin controllers integrated in TH1520 SoC. Since we
don't have support for clocks in the AON region, a dummy fixed-clock
node is added to supply the pin controller locating in it.

Signed-off-by: Yao Zi <ziyao@disroot.org>
Acked-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-07-03 18:10:58 +08:00
Yao Zi
4981db8130 pinctrl: Port pin controller driver for T-Head TH1520 SoC
The SoC pads of TH1520 are separated into three groups (AP 1, AP 2 and
AON) controlled by independent pin controllers. This patch ports their
driver from Linux kernel with most code for setting pinconf and pinmux
kept as is.

The dt-binding of TH1520 pin controller uses a schema where pins to
configure are specfied as strings and looked up at runtime, which the
generic pinctrl helpers of U-Boot cannot parse, thus a customized
set_state() callback is implemented to parse pinconfig nodes and setup
the configuration.

Signed-off-by: Yao Zi <ziyao@disroot.org>
Acked-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-07-03 18:10:58 +08:00
Ben Dooks
364627596c riscv: byteorder: add test for big-endian
Test for big-endian either via __RISCVEB__ which migth be
rather old, or check the BYTE_ORDER if the compiler defines
it (which should be any modern gcc like v12)

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Acked-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-07-03 18:10:50 +08:00
Ben Dooks
7bd65e89ad riscv: add build support for big-endian
Add support to build code big-endian if the board supports
it. Updates the makefile to pass the correct compiler and
elf flags.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Reviewed-by: Tom Rini <trini@konsulko.com>
2025-07-03 18:10:50 +08:00
Heinrich Schuchardt
95732f2bf8 efi_loader: add dbginfodump.efi
Provide a test application to dump the EFI_DEBUG_IMAGE_INFO_TABLE
as implemented in EDK II.

EFI_DEBUG_IMAGE_INFO is not packed in contrast to many other EFI
structures.

As of today EDK II when removing an entry in the EfiDebugImageInfoTable
just sets NormalImage = NULL but does not compact the array. So
TableSize reflects the number of non-NULL entries and not the array
size as reported independently in
https://github.com/tianocore/edk2/pull/11013 and
https://github.com/tianocore/edk2/pull/11019.

The current implementation tolerates this deviation from the UEFI
specification.

This is what the output may look like:

    Debug Info Table Dump
    =====================

    => dump
    Modified
    Number of entries: 0x0000004a
    Info type 0x00000001
      Address: [0x000000008315a000, 0x00000000831bafff]
      File: FvFile(D6A2CB7F-6A18-4E2F-B43B-9920A733700A)
      Handle: 0x000000017fe3cb18
    ...
    Info type 0x00000001
      Address: [0x000000017e8db000, 0x000000017ea00f3f]
      File: FvFile(7C04A583-9E3E-4F1C-AD65-E05268D0B4D1)
      Handle: 0x000000017f358e98
    Info type 0x00000001
      Address: [0x000000017eae5000, 0x000000017eae81ff]
      File: \dbginfodump.efi
      Handle: 0x000000017eaf0298
    =>

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-07-03 12:26:45 +03:00
Ying-Chun Liu (PaulLiu)
2e5ca84aad efi: selftest: add selftest for EFI_DEBUG_SUPPORT
Add selftest to check the installed configuration table that has
the correct GUID.

Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Cc: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-07-03 12:25:56 +03:00
Ying-Chun Liu (PaulLiu)
146546138a efi: add EFI_DEBUG_IMAGE_INFO for debug
This commit adds the functionality of generate EFI_DEBUG_IMAGE_INFO
while loading the image.

This feature is described in UEFI Spec 2.10. Section 18.4.3.
The implementation ensures support for hardware-assisted debugging and
provides a standardized mechanism for debuggers to discover the load
address of an EFI application.

Cc: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Cc: Peter Robinson <pbrobinson@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-07-03 12:25:56 +03:00
Ying-Chun Liu (PaulLiu)
3c08df58cc lib: efi_loader: efi_memory.c: add efi_realloc() for realloc memory
Add efi_realloc() for realloc memory that previously alloc by efi_alloc().
Note that if realloced memory is explicitly allocated as BootServicesData.

Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Cc: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Cc: Peter Robinson <pbrobinson@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-07-03 12:25:56 +03:00
Ying-Chun Liu (PaulLiu)
e7a85ec651 efi: add EFI_DEBUG_IMAGE_INFO_TABLE for debug
EFI_DEBUG_IMAGE_INFO_TABLE is used to store EFI_LOADED_IMAGE for
debug purpose. This commit adds the table to the EFI_CONFIGURATION_TABLE.

This feature is described in UEFI Spec version 2.10. Section 18.4.
The implementation ensures support for hardware-assisted debugging and
provides a standardized mechanism for debuggers to discover and interact
with system-level debug resources.

Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Cc: Peter Robinson <pbrobinson@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-07-03 12:25:56 +03:00
Ying-Chun Liu (PaulLiu)
aaf7be96c2 efi: add EFI_SYSTEM_TABLE_POINTER for debug
Add EFI_SYSTEM_TABLE_POINTER structure for remote debugger to locate
the address of EFI_SYSTEM_TABLE.

This feature is described in UEFI SPEC version 2.10. Section 18.4.2.
The implementation ensures support for hardware-assisted debugging and
provides a standardized mechanism for debuggers to discover the EFI
system table.

Cc: Peter Robinson <pbrobinson@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de> # change memset(systab_pointer, 0 ...) -> systab_pointer->crc32 = 0;
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-07-03 12:25:47 +03:00
Sughosh Ganu
46a564d689 test: wget: add a test case for validating URI
The wget module has a function wget_validate_uri() which is used for
validating the URI to be used by wget. Add a basic test case for this
function.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-07-03 11:34:20 +03:00
Sughosh Ganu
ed004a260a cmd: eficonfig: add support for URI device path based boot options
The eficonfig command provides a menu based interface for maintenance
of the EFI boot options. Add support for adding a URI based boot
option. This boot option can then be used for HTTP boot.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Tested-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-07-03 11:34:10 +03:00
Andrew Goodbody
9a64eecad6 efi_loader: Prevent free of uninitialised pointer
Taking a goto to out_of_resources before receive_lengths is assigned
will result in an attempt to free an unitialised pointer. Instead
initialise receive_lengths to NULL on declaration to prevent this from
occurring.

This issue was found by Smatch.

Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-07-03 11:32:49 +03:00
Andrew Goodbody
5753dc3f65 efi_loader: Prevent dereference of uninitialised variable
If phandler is returned as NULL from efi_search_protocol then
protocol_interface is never assigned to. Instead return
EFI_UNSUPPORTED as per the spec.

This issue found by Smatch.

Also eliminate the use of the variable protocol_interface as it is not
needed.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-07-03 11:32:49 +03:00
Andrew Goodbody
9d95a35715 efi_loader: Prevent dereferencing NULL pointer
Taking the first goto error: in file_open could either result in an
attempt to dereference fh when NULL or else free fh->path which has
not been assigned to and so will be unknown. Avoid both of these
problems by passing path to free instead of fh->path.

This issue found by Smatch.

Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-07-03 11:32:49 +03:00
Javier Martinez Canillas
4e103418be efi_selftest: Add basic partition info check to block io test
Test the EFI_PARTITION_INFO_PROTOCOL in the existing EFI_BLOCK_IO_PROTOCOL
unit test. It is fairly basic, since it only checks that the values of the
struct efi_partition_info .revision, .type and .system fields are correct.

It doesn't check the MBR partition record information, because that's not
supported by the EFI_PARTITION_INFO_PROTOCOL implementation yet. The test
can be extended once the support is implemented, or if the in-memory disk
image used for the test is modified to have a GPT partition type instead.

Suggested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Javier Martinez Canillas <javierm@redhat.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-07-03 11:32:49 +03:00
Javier Martinez Canillas
2fdfb802e3 efi_loader: disk: add EFI_PARTITION_INFO_PROTOCOL support
The UEFI 2.10 specification mentions that this protocol shall be installed
along with EFI_BLOCK_IO_PROTOCOL. It provides cached partition information
for MBR and GPT partition types.

This patch just implements support for GPT partition types. The legacy MBR
partition types is only needed for backward compatibility and can be added
as a follow-up if needed, to make it fully compliant with the EFI spec.

Signed-off-by: Javier Martinez Canillas <javierm@redhat.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-07-03 11:32:49 +03:00
Javier Martinez Canillas
f517d93842 disk: efi: expose the part_get_gpt_pte() helper function
This function will be used by the EFI application disk support code
to provide data required by the EFI_PARTITION_INFORMATION_PROTOCOL.

Signed-off-by: Javier Martinez Canillas <javierm@redhat.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-07-03 11:32:49 +03:00
Javier Martinez Canillas
4b0414d146 disk: efi: Move logic to get a GPT entry into a helper function
Factor out the logic to get the Partition Table Entry (PTE) of a given
partition into a helper function, since it could be used by other code.

Signed-off-by: Javier Martinez Canillas <javierm@redhat.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-07-03 11:32:49 +03:00
Yao Zi
a23c1b3fc0 board: thead: licheepi4a: Bring up secondary cores in SPL
Setup core information and bring secondary HARTs up for a functional
multi-core system.

Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-07-03 16:14:13 +08:00
Yao Zi
ddb52eac41 riscv: dts: th1520: Preserve CLINT node for SPL
Preserve CLINT node for SPL, whose IPI functionality is essential for
operation of a multi-core system.

Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-07-03 16:14:13 +08:00
Yao Zi
f28911368e riscv: cpu: th1520: Add a routine to bring up secondary cores
On coldboot, only HART 0 among the four HARTs of TH1520 is brought up by
hardware, and the remaining HARTs are in reset states, requiring manual
setup of reset address and deassertion to function normal. Introduce a
routine to do the work.

Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-07-03 16:14:13 +08:00
Yao Zi
5afad3d4a3 riscv: cpu: th1520: Setup CPU feature CSRs in harts_early_init
C910 cores integrated in TH1520 SoC provide various customized CSRs for
configuring core behavior, including cache coherency and timing, branch
predication, and clock gating for internal components.

This patch sets them up for efficient operation and satisfying
requirements of an SMP system.

Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-07-03 16:14:13 +08:00
Yao Zi
4153ceb0fe riscv: aclint_ipi: Support T-Head C900 CLINT
Although timer component of the CLINT isn't fully compatible with the
generic RISC-V ACLINT, the IPI component behaves the same.

As the CLINT doesn't have corresponding riscv_aclint_timer driver
available, let's try looking for a compatible SYSCON device directly
when no riscv_aclint_timer device could be found on IPI initialization.

Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-07-03 16:14:13 +08:00
Tom Rini
c405bab766 Merge tag 'mmc-next-2025-07-02' of https://source.denx.de/u-boot/custodians/u-boot-mmc into next
CI: https://source.denx.de/u-boot/custodians/u-boot-mmc/-/pipelines/26911

- Get clock manager address via DT for socfpga_dw_mmc
- Revert "drivers: mmc: rpmb: Use R1 response"
- Fix offsets relative to the end of the partition for mmc env
2025-07-02 07:51:57 -06:00
Andrew Goodbody
4b489f5173 boot: android: Prevent use of unintialised variable
Initialise vhdr to prevent its use when uninitialised.

This issue was found with Smatch.

Fixes: e058176be3 (android: boot: add vendor boot image to prepare for v3, v4 support)
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Link: https://lore.kernel.org/r/20250625-abootimg_fix-v4-2-df7af00e87b0@linaro.org
Signed-off-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
2025-07-02 12:10:25 +02:00
Andrew Goodbody
4b9717c686 cmd: abootimg: Prevent use of unintialised variable
Initialise vhdr to prevent its use when uninitialised.

This issue was found with Smatch.

Fixes: 636da2039a (android: boot: support boot image header version 3 and 4)
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Link: https://lore.kernel.org/r/20250625-abootimg_fix-v4-1-df7af00e87b0@linaro.org
[mkorpershoek: fixed trivial typo in commit msg]
Signed-off-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
2025-07-02 12:10:04 +02:00
Mattijs Korpershoek
a673292082 MAINTAINERS: Add common/spl/spl_dfu to DFU entry
This was not listed as part of the DFU entry.

Add it to make sure that the DFU maintainers get CC'ed on
patches for spl_dfu.

Link: https://lore.kernel.org/r/20250618-maintainers-dfu-spl-v1-1-03f4bc745e36@kernel.org
Signed-off-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
2025-07-02 12:08:50 +02:00
Alif Zakuan Yuslaimi
be7fc8f331 mmc: socfpga_dw_mmc: Retrieve clock manager address via DT
Update the MMC driver to retrieve the clock manager base address via
probing the clock manager node in the device tree.

Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-07-02 12:47:18 +08:00
Jan Kiszka
49666c41e9 Revert "drivers: mmc: rpmb: Use R1 response"
This reverts commit ae93d8106b.
It is no longer needed since 24b1e0c7e2.

Since the obsolete include pulled in byteorder.h which is needed by now,
include this one directly.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-07-02 12:44:44 +08:00
Michael Walle
95f03ee65c env: mmc: fix offsets relative to the end of the partition
According to the help text, you can set negative offsets to indicated
that the offset is relative to the end of the parition. But kconfig
doesn't let you specify negative hex values. I think this fell through
the cracks when converting the symbol from a '#define' to a kconfig
option.

Introduce a new boolean kconfig option to switch on the "relative to the
end" behavior.

Signed-off-by: Michael Walle <mwalle@kernel.org>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-07-02 12:39:21 +08:00
Tom Rini
cbb5672790 Merge patch series "binman: properly error out if path provided to key-name-hint in signature nodes"
Quentin Schulz <foss+uboot@0leil.net> says:

I misunderstood the documentation and put the signing key in a keys/
directory while setting key-name-hint property in the signature node and
u-boot-spl-pubkey-dtb to a path.

mkimage doesn't fail if it cannot find the public key when signing a
FIT but returns something on stderr to notify the user it couldn't find
the key. The issue is that bintool currently discards stderr if the
command successfully returns, so the FIT is not signed AND the user
isn't made aware of it unless the image is manually inspected.

mkimage does fail when trying to insert a public key in a DTB if it
isn't found but we can have a better error message.

Link: https://lore.kernel.org/r/20250418-binman-pubkey-dir-v2-0-b6b90a765ffe@cherry.de
2025-07-01 10:52:04 -06:00
Quentin Schulz
4e7e0ebcf5 binman: etype: u_boot_spl_pubkey_dtb: provide more explicit error for key-name-hint with path
key-name-hint property in u-boot-spl-pubkey-dtb binman entry may contain
a path instead of a filename due to user mistake.

Because we currently assume it is a filename instead of a path, binman
will find the full path to the key based on that path, and return the
dirname of the full path but keeps the path in key-name-hint instead of
stripping the directories from it.

This means mkimage will fail with the following error message if we have
key-name-hint set to keys/dev:

binman: Error 1 running 'fdt_add_pubkey -a sha256,rsa2048 -k /home/qschulz/work/upstream/u-boot/keys -n keys/dev -r conf /home/qschulz/work/upstream/u-boot/build/ringneck/u-boot-spl-dtbdhsfx3mf': Couldn't open RSA certificate: '/home/qschulz/work/upstream/u-boot/keys/keys/dev.crt': No such file or directory

Let's make it a bit more obvious what the error is by erroring out in
binman if a path is provided in key-name-hint (it is named key-name-hint
and not key-path-hint after all).

Fixes: 5609843b57 ("binman: etype: Add u-boot-spl-pubkey-dtb etype")
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2025-07-01 10:52:01 -06:00
Quentin Schulz
2ddc47f9aa binman: etype: fit: raise ValueError if key-name-hint is a path
mkimage doesn't fail if it cannot find the public key but it prints to
stderr. Considering that btool.run() discards stderr, it means binman
happily returns an unsigned FIT and doesn't tell you something went
wrong.

Binman will actually find the file if there's a path in the
key-name-hint property but the current logic expects key-name-hint to be
a filename and thus returns the dirname of the found path for the key,
but with the original key-name-hint appended. This means we can have the
following:

- key-name-hint = "keys/dev"
- name = "/home/qschulz/work/upstream/u-boot/keys/"

so we pass /home/qschulz/work/upstream/u-boot/keys/ to the -k option of
mkimage but the FIT still contains "keys/dev" in key-name-hint which
means mkimage will try to find the key at
/home/qschulz/work/upstream/u-boot/keys/keys/, which doesn't exist.

Let's assume paths are simply not supported (it is named key-name-hint
and not key-path-hint after all) and raise an error if the property
contains a path so that the build fails and not quietly.

Fixes: 133c000ca3 ("binman: implement signing FIT images during image build")
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2025-07-01 10:52:01 -06:00
Simon Glass
919ba46d72 buildman: Support an in-tree build in the current dir
Allow -w to be used with -i to do a build without a separate output
directory.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-07-01 10:49:32 -06:00
Simon Glass
9002ab0986 buildman: Correct behaviour of --in-tree
This option doesn't work as expected since it sets the cwd to the work
directory, which does not necessarily hold the source code.

It should be left unset, so that the current directory is the source
directory.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-07-01 10:49:32 -06:00
Chuanhong Guo
506ceddffd mtd/spinand: gigadevice: sync supported chips with linux 6.9
Adding support for:
GD5F1GQ4RExxG
GD5F2GQ4UExxG
GD5F2GQ4RExxG
GD5F1GQ5RExxG
GD5F2GQ5UExxG
GD5F2GQ5RExxG
GD5F4GQ6UExxG
GD5F4GQ6RExxG
GD5F1GM7UExxG
GD5F1GM7RExxG
GD5F2GM7UExxG
GD5F2GM7RExxG
GD5F4GM8UExxG
GD5F4GM8RExxG
GD5F2GQ5xExxH
GD5F1GQ5RExxH
GD5F1GQ4RExxH

Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
2025-07-01 10:43:03 -06:00
Tom Rini
cff294c74c Merge tag 'tpm-next-01072025' of https://source.denx.de/u-boot/custodians/u-boot-tpm into next
CI: https://source.denx.de/u-boot/custodians/u-boot-tpm/-/pipelines/26897

Updates from Andrew fixing issues reported by smatch.  It picked up
cases of enum functions returning integers instead of enum values.
2025-07-01 07:41:40 -06:00
Tom Rini
6c654d4b89 Merge tag 'u-boot-imx-next-20250630' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx into next
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/26882

- Add capsule update support for i.MX8M EVKs.
- Fixes for Vybrid BK4 board.
- Use common gpio.h in i.MXRT.
2025-07-01 07:38:19 -06:00
Andrew Goodbody
8280d2a77f tpm: Make use of TPM2_ALG_INVAL from enum
Now that the enum includes TPM2_ALG_INVAL, use that name in the
code.

Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-07-01 08:46:38 +03:00
Andrew Goodbody
1fde88de16 cmd: tpm: Fix attempt to return value not in enum
The function tpm2_name_to_algorithm is defined as returning an
enum for the algorithm specified but it also attempts to return
an error on failure, but that error is not included in the enum.
Add the error to the enum so that it can be returned.

This issue was reported by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-07-01 08:46:38 +03:00
Giulio Benetti
a14da5ed61 arch/arm/include/asm/arch-imxrt/gpio.h: imxrt gpio use common gpio.h
The current file defines a struct gpio_regs identical to the one in
<asm/mach-imx/gpio.h>. To eliminate code duplication and align with
the approach used for i.MX8M, include the common header instead of
redefining the struct.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2025-06-29 10:08:10 -03:00
Lukasz Majewski
612421af51 arm: pinctrl: Define .mux_mask field for NXP's SoC
The commit e8a9521e64
("vf500/vf610: synchronise device trees with linux")
has synchronized U-Boot's DTS with v5.19 Linux kernel.
It turned out that in Linux's upstream iomuxc node description the
'fsl,mux_mask' was missing, so the U-Boot's pinctrl driver for NXP's
Vybrid SoC was not working properly.

As by default the mux mask was set to 0, for example the vf610 based
boards (like BK4) were bricked, due to misconfiguration of gpio at
early boot stage.

The fix for all NXP eligible boards is to define .mux_mask field for
soc specific *pinctrl_soc_info structure and use it directly in pinctrl
MMIO driver, without the need to read the "fsl,mux_mask" property from
device tree.

This change brings the NXP's pinctrl driver in U-Boot closer to Linux
upstream one.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com> #for i.MX8ULP
2025-06-29 10:07:55 -03:00
Lukasz Majewski
2a775b0259 config: nxp: vf610: Remove CONFIG_SYS_MALLOC_F_LEN
The commit c69103218e ("i2c: mxc_i2c: add DM_FLAG_PRE_RELOC flag")
has enabled by default the i2c initialization in the pre-relocation
phase.
It turned out that vf610 based boards had too small SYS_MALLOC_F_LEN
pool size.

As a solution the explicit value of CONFIG_SYS_MALLOC_F_LEN for all
vf610 based boards has been removed from their configs.

Instead, the default value of 0x2000 is now used, which causes boards
to work correctly again. This approach has been tested on BK4 device.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2025-06-29 10:07:41 -03:00
Lukasz Majewski
ecf8169ef8 dts: pcm052: bk4: Use proper compatible for QSPI SPI-NOR memory
In the contemporary U-Boot the "spi-flash" compatible is used only when
CONFIG_$(PHASE_)SPI_FLASH_TINY is defined so spi-nor-tiny.c is compiled.

As vf610 devices are not using SPL at all, the SPI_FLASH_TINY is not
defined and no QSPI flash child nodes are considered as valid ones.

The result is that the 'sf probe' command fails and SPI NOR memory is not
accessible on e.g. BK4 device.

The fix is to use proper compatible - in this case "jedec,spi-nor".

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2025-06-29 10:07:23 -03:00
Peng Fan
6b5ba62650 imx8mq: evk: Add support for capsule update
Capsule update is EFI based firmware update which is widely
used in various OS distributions. This feature is required
by ARM System-Ready compliance test. So
 - Define image array and GUID
 - Select configs for EFI Capsule update

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-06-29 10:07:06 -03:00
Peng Fan
484a195ed9 imx93: evk: Add support for capsule update
Capsule update is EFI based firmware update which is widely
used in various OS distributions. This feature is required
by ARM System-Ready compliance test. So
 - Define image array and GUID
 - Select configs for EFI Capsule update

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-06-29 10:07:06 -03:00
Peng Fan
22c8f81713 imx8mn: evk: Add support for capsule update
Capsule update is EFI based firmware update which is widely
used in various OS distributions. This feature is required
by ARM System-Ready compliance test. So
 - Define image array and GUID
 - Select configs for EFI Capsule update

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-06-29 10:07:06 -03:00
Peng Fan
ba605b4803 imx8mm: evk: Add support for capsule update
Capsule update is EFI based firmware update which is widely
used in various OS distributions. This feature is required
by ARM System-Ready compliance test. So
 - Define image array and GUID
 - Select configs for EFI Capsule update

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-06-29 10:07:05 -03:00
Peng Fan
441ca189e0 imx8mp: evk: Add support for capsule update
Capsule update is EFI based firmware update which is widely
used in various OS distributions. This feature is required
by ARM System-Ready compliance test. So
 - Define image array and GUID
 - Select configs for EFI Capsule update

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-06-29 10:07:05 -03:00
Tom Rini
490ae8ceae Revert the last two mach-k3 changes
This reverts both commit 4628730ee6 ("mach-k3: add runtime memory
carveouts for MMU table") as well as commit b77066d732 ("mach-k3: add
dynamic mmu fixups for SPL stage") as some feedback from previous
iterations was missed.

This reverts commit b77066d732 and commit
4628730ee6.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-06-27 13:07:43 -06:00
Tom Rini
02bb597ed6 Merge patch series "Fix io accessors for KVM"
Ilias Apalodimas <ilias.apalodimas@linaro.org> says:

Instructions that lead ito an exception in the hypervisor can't modify two
CPU registers at once for the ARM ISA.

These instructions cannot be emulated by KVM as they do not produce
syndrome information data that KVM can use to infer the destination
register, the faulting address, whether it was a load or store, or
if it's a 32 or 64 bit general-purpose register.
As a result an external abort is injected from QEMU, via ext_dabt_pending.

Link: https://lore.kernel.org/r/20250618065828.1312146-1-ilias.apalodimas@linaro.org
2025-06-27 11:50:30 -06:00
Ilias Apalodimas
fcc60481ae qemu: arm: Enable virtualizable IO accessors
We recently added IO accessors that will work with KVM for any MMIO
access that casues an exception to the hypervisor. Enable them by
default for QEMU.

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Tested-by: Mikko Rapeli <mikko.rapeli@linaro.org>
2025-06-27 11:48:20 -06:00
Ilias Apalodimas
dc512700ad arm: io.h: Fix io accessors for KVM
commit 2e2c2a5e72 ("arm: qemu: override flash accessors to use virtualizable instructions")
explains why we can't have instructions with multiple output registers
when running under QEMU + KVM and the instruction leads to an exception
to the hypervisor.

USB XHCI is such a case (MMIO) where a ldr w1, [x0], #4 is emitted for
xhci_start() which works fine with QEMU but crashes for QEMU + KVM.

These instructions cannot be emulated by KVM as they do not produce
syndrome information data that KVM can use to infer the destination
register, the faulting address, whether it was a load or store, or
if it's a 32 or 64 bit general-purpose register.
As a result an external abort is injected from QEMU, via ext_dabt_pending
to KVM and we end up throwing an exception that looks like

 U-Boot 2025.07-rc4 (Jun 10 2025 - 12:00:15 +0000)
 [...]
 Register 8001040 NbrPorts 8
 Starting the controller
 "Synchronous Abort" handler, esr 0x96000010, far 0x10100040
 elr: 000000000005b1c8 lr : 000000000005b1ac (reloc)
 elr: 00000000476fc1c8 lr : 00000000476fc1ac
 x0 : 0000000010100040 x1 : 0000000000000001
 x2 : 0000000000000000 x3 : 0000000000003e80
 x4 : 0000000000000000 x5 : 00000000477a5694
 x6 : 0000000000000038 x7 : 000000004666f360
 x8 : 0000000000000000 x9 : 00000000ffffffd8
 x10: 000000000000000d x11: 0000000000000006
 x12: 0000000046560a78 x13: 0000000046560dd0
 x14: 00000000ffffffff x15: 000000004666eed2
 x16: 00000000476ee2f0 x17: 0000000000000000
 x18: 0000000046660dd0 x19: 000000004666f480
 x20: 0000000000000000 x21: 0000000010100040
 x22: 0000000010100000 x23: 0000000000000000
 x24: 0000000000000000 x25: 0000000000000000
 x26: 0000000000000000 x27: 0000000000000000
 x28: 0000000000000000 x29: 000000004666f360

 Code: d5033fbf aa1503e0 5287d003 52800002 (b8004401)
 Resetting CPU ...

There are two problems making this the default.
- It will emit ldr + add or str + add instead of ldr/str(post increment)
  in somne cases
- Some platforms that depend on TPL/SPL grow in size enough so that the
  binary doesn't fit anymore.

So let's add proper I/O accessors add a Kconfig option
to turn it off by default apart from our QEMU builds.

Reported-by: Mikko Rapeli <mikko.rapeli@linaro.org>
Tested-by: Mikko Rapeli <mikko.rapeli@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-06-27 11:48:20 -06:00
Ilias Apalodimas
b56c0632ad nxp: Prepare macros for KVM changes
A following patch is replacing our IO accessors with
do { ... } while(0) ones in order to make them usable with KVM.

That leads to an error eventually looking like this:
arch/arm/include/asm/io.h:62:9: error: expected expression before 'do'
   62 |         do {                                            \
      |         ^~
arch/arm/include/asm/io.h:211:41: note: in expansion of macro '__raw_writel'
  211 | #define out_arch(type,endian,a,v)       __raw_write##type(cpu_to_##endian(v),a)
      |                                         ^~~~~~~~~~~
arch/arm/include/asm/io.h:223:25: note: in expansion of macro 'out_arch'
  223 | #define out_be32(a,v)   out_arch(l,be32,a,v)
      |                         ^~~~~~~~
drivers/spi/fsl_dspi.c:127:17: note: in expansion of macro 'out_be32'
  127 |                 out_be32(addr, val) : out_le32(addr, val);
      |                 ^~~~~~~~

So adjust the current macros and code to be compatible with the upcoming
change.

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2025-06-27 11:48:20 -06:00
Tom Rini
e5d4733c2e m68k: Remove astro_mcf5373l board
This board is currently unmaintained. Remove it.

Acked-by: Angelo Dureghello <angelo@kernel-space.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-06-27 10:02:19 -06:00
Tom Rini
adb6e0bad6 tools: rmboard.py: Fix conversion from run_pipe to new helper
When this utility was converted from run_pipe and to the new output
helper, two problems were introduced. First, the conversion for calling
"git rm -f" wasn't correct. Change this to match the other conversions.
Second, the final call we do we need to construct the list because we
print that command for the user to use to inspect remaining references.

Fixes: 3d094ce28a ("u_boot_pylib: Add a function to run a single command")
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-06-27 10:02:19 -06:00
Vignesh Raghavendra
95d303f7e5 mach-k3: am62ax: am62a7_init: Drop write to non existent register
Per section 14.2.1.3 Kick Protection Registers of AM62A TRM[1],
there is no partition 5. Delete it.

[1] https://www.ti.com/lit/pdf/spruj16

Fixes: b511b371ad ("arm: mach-k3: introduce basic files to support the am62a")
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
2025-06-27 10:02:19 -06:00
Bryan Brattlof
b14b3de652 test/py/test_mmc: wrap multi-argument printf-style strings
Newer versions of python will emit a TypeError about not enough
arguments for a format string:

    FAILED ub/test/py/tests/test_mmc.py::test_mmc_dev - TypeError: not enough arguments for format string
    FAILED ub/test/py/tests/test_mmc.py::test_mmcinfo - TypeError: not enough arguments for format string
    FAILED ub/test/py/tests/test_mmc.py::test_mmc_info - TypeError: not enough arguments for format string
    FAILED ub/test/py/tests/test_mmc.py::test_mmc_rescan - TypeError: not enough arguments for format string
    FAILED ub/test/py/tests/test_mmc.py::test_mmc_part - TypeError: not enough arguments for format string

Add parentheses around all multi argument format strings so all
arguments will be passed to the format string

Signed-off-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2025-06-27 10:02:19 -06:00
Anshul Dalal
b77066d732 mach-k3: add dynamic mmu fixups for SPL stage
On platforms with spl splash support i.e CONFIG_VIDEO=y, the top of DDR
is reserved for the framebuffer.

The size for the framebuffer is computed at runtime by video_reserve.
During the MMU configuration an entry corresponding to the framebuffer
should be dynamically created to properly map the required space for the
framebuffer.

Therefore this patch adds k3_spl_mem_map_init which adds the required
MMU entry by querying the gd after the framebuffer size has been
computed in spl_reserve_video_from_ram_top.

For non VIDEO=y platforms, the added k3_spl_mem_map_init function gets
optimized out of the final binary so overall, the spl size is not
impacted[1].

[1]: Tested on clang 19.1.7 and gcc 15.1.1

Signed-off-by: Anshul Dalal <anshuld@ti.com>
2025-06-27 10:02:19 -06:00
Anshul Dalal
4628730ee6 mach-k3: add runtime memory carveouts for MMU table
In u-boot we only provide a single MMU table for all k3 platforms,
this does not scale for devices with reserved memory outside the range
0x9e780000 - 0xa0000000 or for devices with < 2GiB of memory (eg
am62-SIP with 512MiB of RAM).

To properly configure the MMU on various k3 platforms, the
reserved-memory regions need to be queried at runtime from the
device-tree and the MMU table should be updated accordingly.

This patch adds the required fixups to the MMU table (during proper
U-boot stage) by marking the reserved regions as non cacheable and
keeping the remaining area as cacheable.

For the A-core SPL, the 128MiB region starting from SPL_TEXT_BASE
is marked as cacheable i.e 0x80080000 to 0x88080000.

The 128MiB size is chosen to allow for future use cases such as falcon
boot from the A-Core SPL which would require loading kernel image from
the SPL stage. This change also ensures the reserved memory regions that
all exist past 0x88080000 are non cacheable preventing speculative
accesses to those addresses.

Signed-off-by: Anshul Dalal <anshuld@ti.com>
2025-06-27 10:02:18 -06:00
Tom Rini
661bb0c7e0 Merge patch series "drivers: pci: pcie_dw_common: Add dw_pcie_link_set_max_link_width()"
This patch set from Marek Vasut <marek.vasut+renesas@mailbox.org>
introduces dw_pcie_link_set_max_link_width() similar to the Linux Kernel
and then migrates the current platform drivers to use it. Next it adds
support for Renesas R-Car Gen4 platforms and enables it on one.

Link: https://lore.kernel.org/r/20250617081641.8385-1-marek.vasut+renesas@mailbox.org
2025-06-27 08:32:29 -06:00
Marek Vasut
d7c1148790 arm64: dts: renesas: r8a779g3: Enable PCIe/NVMe on Retronix R-Car V4H Sparrow Hawk board
Enable support for R-Car Gen4 PCIe controller and NVMe storage
on Retronix R-Car V4H Sparrow Hawk board .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-06-27 08:25:56 -06:00
Marek Vasut
be3dd0dc2f pci: pcie-rcar-gen4: Add Renesas R-Car Gen4 DW PCIe controller driver
Add R-Car Gen4 PCIe controller support for host mode.

This controller is based on Synopsys DesignWare PCIe. However, this
particular controller has a number of vendor-specific registers, and as
such, requires initialization code, including PHY firmware loading.

The PHY firmware loading is implemented in an entirely generic manner,
by calling a firmware loading script, which the user can configure in
a way they require. This provides the user with flexibility of loading
the PCIe firmware from whichever storage device they need to load it
from.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-06-27 08:25:56 -06:00
Marek Vasut
17b5e8acfc pci: pcie_dw_rockchip: Use dw_pcie_link_set_max_link_width()
Use dw_pcie_link_set_max_link_width() instead of local implementation
of the same functionality. This does change the behavior slightly, as
the dw_pcie_link_set_max_link_width() implementation also programs the
LNKCAP register MLW, this should however be correct and is now aligned
with Linux kernel behavior.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-06-27 08:25:56 -06:00
Marek Vasut
579ac25b17 pci: pcie_dw_qcom: Use dw_pcie_link_set_max_link_width()
Use dw_pcie_link_set_max_link_width() instead of local implementation
of the same functionality.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
2025-06-27 08:25:56 -06:00
Marek Vasut
a83def8615 pci: pcie_dw_meson: Use dw_pcie_link_set_max_link_width()
Use dw_pcie_link_set_max_link_width() instead of local implementation
of the same functionality. This does change the behavior slightly, as
the dw_pcie_link_set_max_link_width() implementation also programs the
LNKCAP register MLW, this should however be correct and is now aligned
with Linux kernel behavior.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
2025-06-27 08:25:56 -06:00
Marek Vasut
4600b59568 drivers: pci: pcie_dw_common: Add dw_pcie_link_set_max_link_width()
Add dw_pcie_link_set_max_link_width() implementation ported from Linux kernel
as of commit 89db0793c9f2 ("PCI: dwc: Add missing PCI_EXP_LNKCAP_MLW handling").
This is common code which is already duplicated in multiple drivers.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-06-27 08:25:56 -06:00
Tom Rini
f2220962f9 Merge patch series "sandbox: enable CONFIG_CMD_BOOTEFI_SELFTEST by default"
Heinrich Schuchardt <heinrich.schuchardt@canonical.com> says:

The sandbox is used for a lot of generic development, we should run the
UEFI tests there, too.

The TPM emulation on the sandbox is incomplete. Disable the TCG test on
sandbox.

Link: https://lore.kernel.org/r/20250617061945.9266-1-heinrich.schuchardt@canonical.com
2025-06-26 17:18:33 -06:00
Heinrich Schuchardt
d7aee0c5ce sandbox: enable CONFIG_CMD_BOOTEFI_SELFTEST by default
The sandbox is used for a lot of generic development, we should run the
UEFI tests there, too.

Reported-by: Javier Martinez Canillas <javierm@redhat.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Javier Martinez Canillas <javierm@redhat.com>
2025-06-26 17:18:29 -06:00
Heinrich Schuchardt
615620479e test: disable TCG test on sandbox
The TPM emulation on the sandbox is incomplete.
Even basic tcg2 functionality like get_capability() fails:

    lib/efi_selftest/efi_selftest_tcg2.c(886):
    ERROR: get_manufacturer_id buffer too small failed

Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Javier Martinez Canillas <javierm@redhat.com>
2025-06-26 17:18:29 -06:00
Tom Rini
231b56fd9b Merge patch series "Add TI K3 PCIe Endpoint Controller support for AM64X"
Hrushikesh Salunke <h-salunke@ti.com> says:

This series adds support for the Endpoint mode on Cadence PCIe controller
on TI's K3 family of SoCs. The driver is an adaptation of the Linux
driver (drivers/pci/controller/cadence/pci-j721e.c) and has been
implemented specifically for Endpoint mode of operation on AM64X. A minor
set of changes will be sufficient to support other K3 SoCs as well.

This patch is tested on AM64X EVM. Following are the log corresponding
to this feature.

https://gist.github.com/hrushikesh221/e8557cbe7667877c50f7d7e9bb96d060

Link: https://lore.kernel.org/r/20250616164929.631791-1-h-salunke@ti.com
2025-06-26 17:16:49 -06:00
Hrushikesh Salunke
7d70986071 configs: am64x_evm_a53_defconfig: Enable configs for PCI Endpoint mode
TI's AM64x SoC has a single instance of PCIe Controller namely PCIe0
which is a Cadence PCIe Controller. To support PCI Endpoint
functionality with the PCIe0 instance of PCIe, enable the corresponding
configs.

Signed-off-by: Hrushikesh Salunke <h-salunke@ti.com>
2025-06-26 17:16:40 -06:00
Hrushikesh Salunke
a4a0edc604 pci_endpoint: Add TI K3 Cadence PCIe Endpoint Controller driver
Add support for Endpoint mode of operation in the Cadence PCIe
Controller present on TI's K3 SoCs. This driver is an adaptation of the
Linux kernel v6.15 driver (drivers/pci/controller/cadence/pci-j721e.c).

Signed-off-by: Hrushikesh Salunke <h-salunke@ti.com>
2025-06-26 17:16:40 -06:00
Tom Rini
45d951d466 Merge patch series "malloc size cleanup for K3 devices"
Udit Kumar <u-kumar1@ti.com> says:

Many boards based upon K3 ARCH overrides default malloc size to 32MB,
as part of cleanup, add default size of 32MB for K3 ARCH.

Link: https://lore.kernel.org/r/20250614093717.2479920-1-u-kumar1@ti.com
2025-06-26 15:54:36 -06:00
Heiko Thiery
cf2abe7b1e mach-k3: j722s: enable caches for the SPL stage
This is same as done in commit 27cd65ca1b ("mach-k3: am62ax: enable
caches for the SPL stage").

This is resulting in ~2x speedup in the A53 SPL stage.

Signed-off-by: Heiko Thiery <heiko.thiery@gmail.com>
2025-06-26 15:54:18 -06:00
Udit Kumar
27c0b05855 configs: j7*/*am62*: Remove malloc size overwrite at config level.
Use default value of malloc size coming from Kconfig, instead of
board specific override.

Signed-off-by: Udit Kumar <u-kumar1@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2025-06-26 13:53:55 -06:00
Udit Kumar
e53d46393e Kconfig: Add default malloc size of K3 ARCH
Many boards of K3 overwrites default malloc size, instead
of doing at almost each board level,
Add default size at Kconfig.

Signed-off-by: Udit Kumar <u-kumar1@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2025-06-26 13:53:55 -06:00
Anshul Dalal
5609f200d0 arm: Kconfig: enable LTO for ARCH_K3
CONFIG_LTO enables Link Time Optimizations that helps in reducing binary
size. The config has been validated on all K3 platforms so can be safely
enabled.

Signed-off-by: Anshul Dalal <anshuld@ti.com>
2025-06-26 13:48:43 -06:00
Hrushikesh Salunke
f05ba765a1 phy: cadence: torrent: add support for three or more links using 2 protocols
This is a port of the corresponding commit in the Linux kernel which
adds the same support for the Cadence Torrent driver[0]. The commit
message below is taken as-is from the Linux kernel commit being ported.

The Torrent SERDES can support at most two different protocols (PHY types).
This only mandates that the device-tree sub-nodes used to represent the
configuration should describe links with at-most two different protocols.

The existing implementation however imposes an artificial constraint that
allows only two links (device-tree sub-nodes). As long as at-most two
protocols are chosen, using more than two links to describe them in an
alternating configuration is still a valid configuration of the Torrent
SERDES.

A 3-Link 2-Protocol configuration of the 4-Lane SERDES can be:
Lane 0 => Protocol 1 => Link 1
Lane 1 => Protocol 1 => Link 1
Lane 2 => Protocol 2 => Link 2
Lane 3 => Protocol 1 => Link 3

A 4-Link 2-Protocol configuration of the 4-Lane SERDES can be:
Lane 0 => Protocol 1 => Link 1
Lane 1 => Protocol 2 => Link 2
Lane 2 => Protocol 1 => Link 3
Lane 3 => Protocol 2 => Link 4

[0] 5b7b83a983

Signed-off-by: Hrushikesh Salunke <h-salunke@ti.com>
2025-06-26 13:48:36 -06:00
牛 志宏
7fd2795a4b bootm: Pass SMP core ID and DTB address for ELF-formatted kernels
When booting RISC-V ELF-formatted kernel images (IH_TYPE_KERNEL + IH_OS_ELF),
explicitly pass SMP hart ID (via a0/argc) and DTB address (via a1/argv)
to comply with modern SMP-enabled kernels' boot protocol requirements.
See https://www.kernel.org/doc/html/latest/arch/riscv/boot.html#register-state

Signed-off-by: Zone.N <zone.niuzh@hotmail.com>
2025-06-26 13:48:04 -06:00
Tom Rini
778c552f86 Merge patch series "sandbox: align LMB memory"
Heinrich Schuchardt <heinrich.schuchardt@canonical.com> says:

To implement the EFI_SYSTEM_TABLE_POINTER we need 4 MiB aligned
memory.

On the sandbox LMB uses addresses relative to the start of a page aligned
RAM buffer allocated with mmap(). This leads to a mismatch of alignment
between EFI which uses pointers and LMB which uses phys_addr_t.

Ensure that the RAM buffer used for LMB is 4 MiB aligned.

Provide a unit test for efi_alloc_aligned_pages() verifying this alignment.

Do not overwrite RAM size in dram_init().

Link: https://lore.kernel.org/r/20250608075428.32631-1-heinrich.schuchardt@canonical.com
2025-06-26 13:45:43 -06:00
Heinrich Schuchardt
788df05362 test: unit test for efi_alloc_aligned_pages()
Provide unit tests for efi_alloc_aligned_pages() and
efi_allocate_pages().

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-06-26 13:45:33 -06:00
Heinrich Schuchardt
5c8de1bcfb sandbox: align LMB memory
To implement the EFI_SYSTEM_TABLE_POINTER we need 4 MiB aligned
memory.

On the sandbox LMB uses addresses relative to the start of a page aligned
RAM buffer allocated with mmap(). This leads to a mismatch of alignment
between EFI which uses pointers and LMB which uses phys_addr_t.

Ensure that the RAM buffer used for LMB is 4 MiB aligned.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-06-26 13:45:33 -06:00
Heinrich Schuchardt
d50fd7f911 sandbox: fix dram_init()
dram_init() must not overwrite the value of gd->ram_buf set by
setup_ram_buf() for main U-Boot or board_init_f() for SPL.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-06-26 13:45:33 -06:00
Rasmus Villemoes
7d4eacb0e6 mkimage: do a rough estimate for the size needed for hashes/signatures
Background:

I have several customers that will be using a certain remote signing
service for signing their images, in order that the private keys are
never exposed outside that company's secure servers. This is done via
a pkcs#11 interface that talks to the remote signing server, and all
of that works quite well.

However, the way this particular signing service works is that one
must upfront create a "signing session", where one indicates which
keys one will use and, importantly, how many times each key will (may)
be used. Then, depending on the keys requested and the customer's
configuration, one or more humans must authorize that signing session
So for example, if official release keys are to be used, maybe two
different people from upper management must authorize, while if
development keys are requested, the developer himself can authorize
the session.

Once authorized, the requester receives a token that must then be used
for signing via one of the keys associated to that session.

I have that integrated in Yocto in a way that when a CI starts a BSP
build, it automatically works out which keys will be needed (e.g. one
for signing U-Boot, another for signing a kernel FIT image) based on
bitbake metadata, requests an appropriate signing session, and the
appropriate people are then notified and can then look at the details
of that CI pipeline and confirm that it is legitimate.

The problem:

The way mkimage does FIT image signing means that the remote server
can be asked to perform a signature an unbounded number of times, or
at least a number of times that cannot be determined upfront. This
means that currently, I need to artificially say that a kernel key
will be used, say, 10 times, even when only a single FIT image with
just one configuration node is created.

Part of the security model is that once the number of signings using a
given key has been depleted, the authorization token becomes useless
even if somehow leaked from the CI - and _if_ it is leaked/compromised
and abused before the CI has gotten around to do its signings, the
build will then fail with a clear indication of the
compromise. Clearly, having to specify a "high enough" expected use
count is counter to that part of the security model, because it will
inevitably leave some allowed uses behind.

While not perfect, we can give a reasonable estimate of an upper bound
on the necessary extra size by simply counting the number of hash and
signature nodes in the FIT image.

As indicated in the comments, one could probably make it even more
precise, and if there would ever be signatures larger than 512 bytes,
probably one would have to do that. But this works well enough in
practice for now, and is in fact an improvement in the normal case:
Currently, starting with size_inc of 0 is guaranteed to fail, so we
always enter the loop at least twice, even when not doing any signing
but merely filling hash values.

Just in case I've missed anything, keep the loop incrementing 1024
bytes at a time, and also, in case the estimate turns out to be over
64K, ensure that we do at least one attempt by changing to a do-while
loop.

With a little debug printf, creating a FIT image with three
configuration nodes previously resulted in

  Trying size_inc=0
  Trying size_inc=1024
  Trying size_inc=2048
  Trying size_inc=3072
  Succeeded at size_inc=3072

and dumping info from the signing session (where I've artifically
asked for 10 uses of the kernel key) shows

      "keyid": "kernel-dev-20250218",
      "usagecount": 9,
      "maxusagecount": 10

corresponding to 1+2+3+3 signatures requested (so while the loop count
is roughly linear in the number of config nodes, the number of
signings is quadratic).

With this, I instead get

  Trying size_inc=3456
  Succeeded at size_inc=3456

and the expected

      "keyid": "kernel-dev-20250218",
      "usagecount": 3,
      "maxusagecount": 10

thus allowing me to set maxusagecount correctly.

Update a binman test case accordingly: With the previous behaviour,
mkimage would try size_inc=0 and then size_inc=1024 and then
succeed. With this patch, we first try, and succeed, with 4*128=512
due to the four hash nodes (and no signature nodes) in 161_fit.dts, so
the image ends up 512 bytes smaller.

Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
2025-06-26 11:48:39 -06:00
Tom Rini
ba60a726d9 Merge patch series "Propagate bootph-all and bootph-some-ram property to all supernodes"
Moteen Shah <m-shah@ti.com> says:

In the U-Boot pre-relocation stage, if the parent node lacks
bootph-all/bootph-some-ram property and the driver lacks a pre-reloc
flag, all of its subsequent subnodes gets skipped over from driver
binding—even if they have a bootph* property.

This series addresses the issue by scanning through all the nodes during
build time and propagating the applicable  property to all of its supernode.

Link: https://lore.kernel.org/r/20250516114148.3862114-1-m-shah@ti.com
2025-06-26 11:48:39 -06:00
Moteen Shah
1b5e41964c tools: binman: ftest.py: Add testcase for bootph-* propagation
Add a testcase to ensure that scan_and_prop_bootph() actually
propagates bootph-* properties to supernodes.

Signed-off-by: Moteen Shah <m-shah@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2025-06-26 11:48:37 -06:00
Moteen Shah
d85d15fdfe tools: binman: control.py: Propagate bootph-all/bootph-some-ram properties to supernodes
As per bootph schema, bootph-* property in child node should be
implied in their parent, but this feature is not implemented in
the U-Boot proper stage (before relocation) resulting in devices
not being bound because of the missing bootph-all or bootph-some-ram
property in the parent node.

To mitigate this issue, add a function to scan through all the nodes
in the device-tree for bootph-all and bootph-some-ram properties. If
found, propagate it to all of its parent nodes up the hierarchy.

Signed-off-by: Moteen Shah <m-shah@ti.com>
Signed-off-by: Simon Glass <sjg@chromium.org>

Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
2025-06-26 09:58:41 -06:00
Tom Rini
d4f61eae2a Merge patch series "Fix handling of optional blobs in binman"
Yannic Moog <y.moog@phytec.de> says:

This series solves a contradiction regarding ext blobs packaged in
binman. When they are marked as optional, by default they are faked, two
messages are emitted. One says the image is not functional the other
says the image is still functional. Both concern the same binman
entry/blob.

Binman is set up to have fake external blobs in case they are missing.
This is regardless on whether they are optional or not.
The implementation does not allow different types of entries to override
the faking decision; at least there wouldn't be much sense in doing so.

Here is an example build output of a phycore-imx8mp:

  BINMAN  .binman_stamp
Image 'image' is missing optional external blobs but is still functional: tee-os

/binman/section/fit/images/tee/tee-os (tee.bin):
   See the documentation for your board. You may need to build Open Portable
   Trusted Execution Environment (OP-TEE) and build with TEE=/path/to/tee.bin

Image 'image' has faked optional external blobs and is still functional: tee.bin

  OFCHK   .config

The output stays to inform/warn the user, but in this case the tee-os
entry will not be present in the final image.

Link: https://lore.kernel.org/r/20250613-binman_faked_optional-v3-0-1e23dd7c41a2@phytec.de
2025-06-26 09:54:24 -06:00
Yannic Moog
0dbb0a8d1f binman: test: assert optional blobs don't cause non-functionality
When external blobs are marked optional, they should not cause a
build to fail. Extend the test cases for FitTeeOsOptional and
ExtblobOptional.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Yannic Moog <y.moog@phytec.de>
Reviewed-by: Bryan Brattlof <bb@ti.com>
2025-06-26 09:54:05 -06:00
Yannic Moog
e749d64b46 binman: ftest: pass allow_fake_blob to _DoReadFileDtb
Some test cases don't use _DoTestFile directly which accepts
allow_fake_blobs. However, they specifically test functionality that
requires external blobs not to be faked. Extend the _DoReadFileDtb
signature to allow passing that option to _DoTestFile.

Also fix tests that require non-faked ext blobs.
By default, external blobs are faked. Some tests care only about more
basic functionality. In those cases no external blobs should be faked.
That would trigger a different (binman) case which is not in scope for
those particular tests.
Thus, disable faked blobs for those test cases.

Signed-off-by: Yannic Moog <y.moog@phytec.de>
Reviewed-by: Bryan Brattlof <bb@ti.com>
2025-06-26 09:54:05 -06:00
Yannic Moog
f5817e05ef binman: add faked optional entry case in CheckForProblems
When having an entry that is marked as optional and is missing in the
final image, the following output is observed:

  CFGS    spl/u-boot-spl.cfgout
  BINMAN  .binman_stamp
Image 'image' has faked external blobs and is non-functional: tee.bin

Image 'image' is missing optional external blobs but is still functional: tee-os

/binman/section/fit/images/tee/tee-os (tee.bin):
   See the documentation for your board. You may need to build Open Portable
   Trusted Execution Environment (OP-TEE) and build with TEE=/path/to/tee.bin

Some images are invalid
make: *** [Makefile:1135: .binman_stamp] Error 103

To solve this contradictory messaging, when checking the faked blob
list, remove entries that are allowed to be missing. Instead add an
info message for faked optional blobs. Also reduce verbosity of the
optional image warning to an info message.

Signed-off-by: Yannic Moog <y.moog@phytec.de>
Reviewed-by: Bryan Brattlof <bb@ti.com>
2025-06-26 09:54:05 -06:00
Yannic Moog
21bc3433a4 binman: rework dropping absent entries from packaged image
When blobs are absent and are marked as optional, they can be safely
dropped from the binman tree. Use the drop_absent function for that.
Rename drop_absent to drop_absent_optional as we do not want to drop any
entries that are absent; they should be reported by binman as errors
when they are missing.
We also reorder the processing of the image the following:
- We call the CheckForProblems function before the image is built.
- We drop entries after we checked for problems with the image.
This is okay because CheckForProblems does not look at the file we have
written but rather queries the data structure (image) built with binman.
This also allows us to get all error and warning messages that we want
to report while avoiding putting missing optional entries in the final
image.
As only the blobs are dropped, the sections still remain in the
assembled image. Thus add them to the expected test case checks where
necessary.

In addition, a rework of testPackTeeOsOptional test case is necessary.

The test did not really do what it was supposed to. The description said
that optional binary is tested, but the binary is not marked as
optional. Further, the tee.elf file, when included in the image
properly, also shows up in the image data. This must be added as well.

As there is no global variable for the elf data, set the pathname to the
elf file that was created when setting up the test suite.
For the test case get the filename and read the contents, comparing them
to the contents of the created binman image.

Signed-off-by: Yannic Moog <y.moog@phytec.de>
Reviewed-by: Bryan Brattlof <bb@ti.com>
2025-06-26 09:54:05 -06:00
Yannic Moog
3ae668b9d2 binman: mark optional missing blobs as absent
Optional blobs should mark themselves as absent to avoid being packed
into an image.
Extend the documentation of this behaviour. Although the documentation
implied this before, the "optional" property had not been explained
properly before.
The behaviour will change as now absent entries are no longer
packed into an image. The image map will also reflect this.
As a result, the CheckForProblems() function will no longer alert on
optional (blob) entries. This is because the missing optional images
were removed before CheckForProblems is called.
Adjust the testExtblobOptional test case to highlight that we are
testing not only an optional image but the image is missing as well. The
behaviour for these is different where the latter will not be packaged
into the image.

Reported-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Yannic Moog <y.moog@phytec.de>
Reviewed-by: Bryan Brattlof <bb@ti.com>
2025-06-26 09:54:05 -06:00
Yannic Moog
a657d87f08 binman: drop "faked" return value from check_fake_fname
check_fake_fname sets the faked member of the entry. Use that member
to get the faked status instead of a returned value indicating the same.
Add type annotations to the modified functions while at it.

Signed-off-by: Yannic Moog <y.moog@phytec.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bryan Brattlof <bb@ti.com>
2025-06-26 09:54:05 -06:00
Tom Rini
2cfbf412a0 Merge patch series "add a few entries into missing-blob-help"
Bryan Brattlof <bb@ti.com> says:

Now that TIFS and DM firmwares are marked as mandatory items for a
successful build[0] we should provide some more descriptive help text on
where to get the firmware in the event they are not found and add links
to more information about them.

We do need to expand the regex to allow the '.' dot in 'ti-fs-enc.bin'
so we can add it to the list which was the lesser number of lines
changed than renaming all these entries to 'tifs' or 'ti-fs' which the
current regex will match.

Link: https://lore.kernel.org/r/20250612-missing-blob-help-entries-v2-0-36f1c8078155@ti.com
2025-06-26 08:33:42 -06:00
Tom Rini
ed2007d27b Merge patch series "net: consolidate PXE processor architecture type Kconfig"
Heinrich Schuchardt <heinrich.schuchardt@canonical.com> says:

DHCP and DHCPv6 use the same value defined in
https://www.iana.org/assignments/dhcpv6-parameters#processor-architecture
to encode the processor architecture type. We should only use a single
Kconfig symbol for both protocols.

Furthermore we should make the value customizable. This allows for instance
to choose between "x86 BIOS" or "x64 UEFI".

As "x86 BIOS" is encoded as 0, we should not use this value to switch
off transmission of the DHCP option. Use 0xFF instead.

Link: https://lore.kernel.org/r/20250608074228.12407-1-heinrich.schuchardt@canonical.com
2025-06-26 08:33:42 -06:00
Tom Rini
579d1a1bb7 Merge patch series "mkimage: validate image references in FIT configurations"
Aristo Chen <jj251510319013@gmail.com> says:

This series introduces a validation step in mkimage to ensure that all image
names referenced under the /configurations node of a FIT source (ITS) are
actually defined under the /images node.

### Motivation

When using mkimage to build FIT images, it's easy to mistakenly reference
nonexistent image nodes in configurations (e.g., referencing a missing `fdt` or
`firmware` node). Such issues are often not caught until runtime in U-Boot.

This series aims to catch these errors early during FIT image creation by
validating the configuration references in mkimage itself.

Link: https://lore.kernel.org/r/20250610074121.8308-1-aristo.chen@canonical.com
2025-06-26 08:33:42 -06:00
Bryan Brattlof
c1c8d2db43 binmain: include ti-fs-enc.bin into missing-blob-help
Now that the TIFS firmware is marked as a mandatory component to a
successful build, provide some helpful descriptions to what it is and
links to more information about how to get this needed firmware.

Signed-off-by: Bryan Brattlof <bb@ti.com>
2025-06-26 08:18:48 -06:00
Bryan Brattlof
85c4c34dc9 binman: allow '.' to be included in the missing blob tags
Extend the regex to add periods '.' in the tag so entries like
ti-fs-enc.bin can be represented in the missing-blob-help file.

Signed-off-by: Bryan Brattlof <bb@ti.com>
2025-06-26 08:18:48 -06:00
Bryan Brattlof
cf744bda69 binman: add sysfw-inner-cert to missing-blob-help
Now that the inner certificate for TI's Foundation Security TIFS
firmware is mandatory to a successful build, provide some guidance on
what it is and links to the documentation on how to obtain the firmware
blobs.

Reviewed-by: Anshul Dalal <anshuld@ti.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
2025-06-26 08:18:48 -06:00
Bryan Brattlof
f16f17fb05 binman: add ti-dm entry to missing-blob-help
Now that ti-dm is marked as a mandatory component for a successful
build, adding some helping text about how to resolve a failed build will
be needed. Add some text around what ti-dm is and links to more
documentation on how to obtain the firmware binaries

Reviewed-by: Anshul Dalal <anshuld@ti.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
2025-06-26 08:18:48 -06:00
Bryan Brattlof
562dcc6240 binman: alphabetize missing-blob entries
As the list of entries grows let's alphabetize the list to make
searching a little easier. No functional changes intended

Reviewed-by: Anshul Dalal <anshuld@ti.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
2025-06-26 08:18:48 -06:00
Heinrich Schuchardt
092f0c45f4 net: consolidate PXE processor architecture type Kconfig
DHCP and DHCPv6 use the same value defined in
https://www.iana.org/assignments/dhcpv6-parameters#processor-architecture
to encode the processor architecture type. We should only use a single
Kconfig symbol for both protocols.

Furthermore we should make the value customizable. This allows for instance
to choose between "x86 BIOS" or "x64 UEFI".

As "x86 BIOS" is encoded as 0, we should not use this value to switch
off transmission of the DHCP option. Use 0xFF instead.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2025-06-26 08:17:17 -06:00
Heinrich Schuchardt
14480c84dc cmd: remove duplicate DHCPv6 Kconfig definitions
Remove duplicate definition of

* DHCP6_PXE_CLIENTARCH
* DHCP6_PXE_DHCP_OPTION
* DHCP6_ENTERPRISE_ID

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Fixes: da24eb5532 ("Merge patch series "BOOTP/DHCPv4 enhancements"")
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Fixes: 5eb1b78438 ("Merge patch series "test/py: enable HTTP testing"")
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
2025-06-26 08:17:17 -06:00
Aristo Chen
647931cfed arm: dts: phycore-am62x: Add missing tifsstub image nodes for FIT loadables
The phycore-am62x build was broken due to mkimage reporting an undefined
'image "tifsstub-hs"' in the 'loadables' property of the FIT configuration.
This occurred because the `loadables` field referenced `tifsstub-hs`,
`tifsstub-fs`, and `tifsstub-gp`, but no corresponding nodes were defined
under /images.

This patch was inspired by commit 622f826bf0
("arm: dts: phycore-am62x: Package TIFS Stub"). It resolves the issue by
adding proper Binman nodes for each TIFS variant (`tifsstub-hs`,
`tifsstub-fs`, and `tifsstub-gp`).

Signed-off-by: Aristo Chen <aristo.chen@canonical.com>
2025-06-26 08:12:54 -06:00
Aristo Chen
21f75eb7af test: py: add mkimage test for undefined image references in FIT configs
Add a test case to verify that mkimage correctly rejects a FIT source
that references a non-existent image from a configuration node.

This test introduces a minimal ITS that defines a valid kernel image
but references a missing "fdt" image under the /configurations section.
The test asserts that mkimage fails with a clear error message, as
introduced in the new validation logic.

This helps ensure the validation logic behaves correctly and prevents
regressions in future FIT enhancements.

Signed-off-by: Aristo Chen <aristo.chen@canonical.com>
2025-06-26 08:12:54 -06:00
Aristo Chen
3071e264c9 binman: test: Ensure all config references exist in /images node
Several binman FIT test device trees reference image nodes such as atf
and uboot in their /configurations sections, but those image nodes
were not actually defined in the /images node. This mismatch can lead
to validation errors when stricter consistency checks are introduced.

This patch adds minimal definitions for atf and uboot under the
/images node in all relevant test DTS files.

Signed-off-by: Aristo Chen <aristo.chen@canonical.com>
2025-06-26 08:12:54 -06:00
Aristo Chen
7a8b25a771 tools: mkimage: validate image references in FIT configurations
When parsing a FIT image source (ITS), mkimage does not currently check
whether the image names referenced in the /configurations section (e.g.
"kernel", "fdt", "ramdisk", "loadables") actually exist in the /images
node.

This patch introduces a validation step during FIT import that iterates
over each configuration and verifies that all referenced image names are
defined under /images. If a missing image is detected, an appropriate
error is reported and mkimage exits with FDT_ERR_NOTFOUND.

This ensures that configuration integrity is validated at build time.

Signed-off-by: Aristo Chen <aristo.chen@canonical.com>
2025-06-26 08:12:54 -06:00
Aristo Chen
21705d3914 tools: mkimage: propagate error codes from fit_handle_file()
The fit_handle_file() function previously returned a hardcoded -1 on
error. This change updates the logic to return the actual error code
stored in `ret`, allowing for error propagation.

This improves debuggability and enables downstream callers to
distinguish different failure causes, such as FDT_ERR_NOTFOUND or
other errors.

Signed-off-by: Aristo Chen <aristo.chen@canonical.com>
2025-06-26 08:12:54 -06:00
Tom Rini
40e083353a Gitlab: Allow running sandbox test.py jobs on more hosts
With a test investigation of how long each of our current build machines
can take to run the sandbox test.py job, we can see that the longest
running hosts are any of the arm64 machines. In some cases this may be a
matter of overall system load, but in others it's hard to say. The
challenge with these tests is that the run itself is single threaded and
covers a large number of tests. There may be gains made in looking in to
optimizing some individual tests. For now however we will likely gain
the most by removing potential bottle necks here and allow any amd64 or
arm64 host to run the test instead of trying to ensure they only run on
one of the few "fast" machines.

Link: https://source.denx.de/u-boot/u-boot/-/pipelines/26533/test_report
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-06-25 16:25:05 -06:00
Jamin Lin
ed51f3e446 lib: ecdsa: Add support for loading ECDSA public key from FDT
This patch adds support for parsing ECDSA public keys from the device tree
blob (FDT) under the `/signature` node. The public key is expected to be
defined using:

  - ecdsa,curve (e.g., "prime256v1", "secp384r1")
  - ecdsa,x-point
  - ecdsa,y-point

The implementation introduces:
- struct ecdsa_public_key to hold parsed key fields
- fdt_get_key() to parse the curve and coordinates from the FDT
- read_key_from_fdt() to convert the parsed values into an OpenSSL EC_KEY
- load_key_from_fdt() to support loading keys using required_keynode,
  keyname hint, or fallback to scanning all subnodes under "/signature".

If "info->fdt_blob" is provided, the key is loaded from the FDT. Otherwise,
the code falls back to loading a PEM-formatted key from file as before.

This allows for ECDSA signature verification where the public key is
embedded in the FIT image device tree, useful for systems that require
signature validation without external files.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
2025-06-25 13:45:38 -06:00
Bryan Brattlof
e18472f1de binman: openssl: disable JTAG access by default
Typically boards operating in production environments will not be
monitored and so will not need JTAG access unlocked. Disable the debug
extension by default (set debugType = 0) unless we add the 'debug'
property in the binman configs.

Acked-by: Andrew Davis <afd@ti.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
2025-06-25 13:43:34 -06:00
Mark Kettenis
f35f053755 cmd: smbios: Fix header for type 3 entries
Change from "Baseboard Information" to "Chassis information".

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2025-06-25 13:42:26 -06:00
Tim Harvey
e63e088b60 rtc: add ds1672 driver
Add support for Dallas/Maxim ds1672 32bit counter RTC.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2025-06-25 13:42:04 -06:00
Tony Dinh
29cb98d515 fs: ext4fs: Fix: Data abort in ext4fs_log_gdt()
Return ENOMEM in ext4fs_log_gdt when number of blocks per gdt is more than
number of allocated journal entries.

Signed-off-by: Tony Dinh <mibodhi@gmail.com>
2025-06-25 13:41:35 -06:00
Tom Rini
b40d7b8f72 Merge patch series "lmb: use a single API for all allocations"
Sughosh Ganu <sughosh.ganu@linaro.org> says:

The LMB module has a bunch for API's which are used for allocating
memory. There are a couple of API's for requesting memory, and two
more for reserving regions of memory. Replace these different API's
with a single one, lmb_alloc_mem(). The type of allocation to be made
is specified through one of the parameters to the function.

Additionally, the two API's for reserving regions of memory,
lmb_reserve() and lmb_alloc_addr() are the same with one
difference. One can reserve any memory region with lmb_reserve(),
while lmb_alloc_addr() actually checks that the memory region being
requested is part of the LMB memory map. Reserving memory that is not
part of the LMB memory map is pretty futile -- the allocation
functions do not allocate memory which has not been added to the LMB
memory map.

This series also removes the functionality allowing for reserving
memory regions outside the LMB memory map. Any request for reserving a
region of memory outside the LMB memory map now returns an -EINVAL
error.

Certain places in the common code using the LMB API's were not
checking the return value of the functions. Checks have been added for
them. There are some calls being made from the architecture/platform
specific code which too do not check the return value. Those have been
kept the same, as I do not have the platform with me to check if it
causes any issues on those platforms.

In addition, there is a patch which refactors code in
lmb_overlaps_region() and lmb_can_reserve_region() so that both
functionalities can be put in a single function, lmb_overlap_checks().

Finally, a new patch has been added which checks the return value of
the lmb allocation function before copying the device-tree to the
allocated address.

Link: https://lore.kernel.org/r/20250617104346.1379981-1-sughosh.ganu@linaro.org
[trini: Rework arch/arm/mach-snapdragon/board.c merge]
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-06-25 09:57:01 -06:00
Sughosh Ganu
9b0ed9e69b doc: add lmb documentation
The LMB module has undergone significant changes in the recent
past. Add a document which briefly describes what the LMB module does,
and the changes that have been made to it's design since the 2025.01
release.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-06-25 09:50:37 -06:00
Sughosh Ganu
4641419f41 mach-snapdragon: add a check before copying FDT to fdt_addr_r
The board_late_init() function allocates memory for a bunch of
environment variables, including fdt_addr_r. The device-tree then gets
copied to the memory pointed to by fdt_addr_r. However, the memory
allocation request can fail, in which case the address that is being
written to would not be allocated. Add a check that the memory
allocation has succeeded before copying the device-tree.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
2025-06-25 09:50:37 -06:00
Sughosh Ganu
7aa19c3667 lmb: use a single function to check for allocation and reservation requests
The functions that handle allocation requests check if a region of
memory overlaps with a used region. This is done through
lmb_overlaps_region(). Similar checks are done for reservation
requests made to the LMB module, where the caller asks specifically
for a particular region of memory. These checks are being done through
lmb_can_reserve_region().

There are subtle differences in the checking needed for allocation
requests, as against reservation requests. In the former, it is only
needed to be checked if a region is overlapping with an existing
used region, and return as soon as an overlap is found. For
reservation request checks, because U-Boot allows for re-use of in-use
regions with a particular memory attribute, this check has to iterate
through all the regions that might overlap with the requested region,
and then check that the necessary conditions are met to allow for the
overlap.

Combine these two checks in a single function, lmb_overlap_checks() as
both lmb_overlaps_region() and lmb_can_reserve_region() are pretty
similar otherwise.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-06-25 09:50:37 -06:00
Sughosh Ganu
745f981f70 lmb: use a single function to free up memory
There is no need to have two separate API's for freeing up memory. Use
a single API lmb_free() to achieve this.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-06-25 09:50:37 -06:00
Sughosh Ganu
3faffba6f1 lmb: staticise lmb_add_memory()
lmb_add_memory() is only called from the lmb module. Mark the function
as static.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-06-25 09:50:37 -06:00
Sughosh Ganu
6e4675b8e5 lmb: replace the lmb_alloc() and lmb_alloc_base() API's
There currently are two API's for requesting memory from the LMB
module, lmb_alloc() and lmb_alloc_base(). The function which does the
actual allocation is the same. Use the earlier introduced API
lmb_alloc_mem() for both types of allocation requests.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-06-25 09:50:37 -06:00
Sughosh Ganu
9d37a3d6e8 lmb: replace lmb_reserve() and lmb_alloc_addr() API's
There currently are multiple allocation API's in the LMB module. There
are a couple of API's for allocating memory(lmb_alloc() and
lmb_alloc_base()), and then there are two for requesting a reservation
for a particular memory region (lmb_reserve() and
lmb_alloc_addr()). Introduce a single API lmb_alloc_mem() which will
cater to all types of allocation requests and replace lmb_reserve()
and lmb_alloc_addr() with the new API.

Moreover, the lmb_reserve() API is pretty similar to the
lmb_alloc_addr() API, with the one difference being that the
lmb_reserve() API allows for reserving any address passed to it --
the address need not be part of the LMB memory map. The
lmb_alloc_addr() does check that the address being requested is
actually part of the LMB memory map.

There is no need to support reserving memory regions which are outside
the LMB memory map. Remove the lmb_reserve() API functionality and use
the functionality provided by lmb_alloc_addr() instead. The
lmb_alloc_addr() will check if the requested address is part of the
LMB memory map and return an error if not.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-06-25 09:50:37 -06:00
Tom Rini
0862a8c48f Merge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-sunxi into next
This concludes support for the Allwinner A133 SoC, the biggest chunk of
which is the DRAM init code. Also includes support for a devboard using
this SoC, the DT of which  got added to the kernel only recently. The
same is true for another H618 devboard, so add the respective devconfig
as well.

Gitlab CI passed, and I booted that briefly on those two boards.
2025-06-25 08:07:16 -06:00
Tom Rini
59e6462d7c Merge tag 'qcom-next-23Jun-1' of https://source.denx.de/u-boot/custodians/u-boot-snapdragon into next
This PR introduces 3 new platforms, two from the new Dragonwing IQx
series (QCS615 and QCS8300) as well as the IPQ5424.

Additionally:

* Support for booting downstream Android boot images on some phones is
  added
* Capsule update support is expanded to be more generic, determining
  which partition U-Boot was flashed to automatically and supporting
  many more boards.
* Minor capsule update bugs are fixed
* A watchdog driver is added and gets timeout support
* Autoboot now requires pressing "space" specifically to stop booting as
  a workaround for some boards getting rogue key presses which would
  cause autoboot to fail
* Documentation is added for the Dragonwing boards
* The RB1/2 now use USB gadget mode rather than host
* A bug is fixed where GPIO reads could return incorrect values
2025-06-24 07:54:51 -06:00
Casey Connolly
7f4af4c550 doc: board/qualcomm: remove signing references from dragonwing.rst
The mkmbn tool isn't available yet, so it's still necessary to use
qtestsign for signing.

Update the docs to describe it, this can be reverted once mkmbn and the
associated tooling is merged.

Link: https://lore.kernel.org/u-boot/20250616162626.247802-1-casey.connolly@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-06-24 07:54:51 -06:00
Luca Weiss
35a03711ce clk/qcom: sm8250: Fix variable name of msm_clk_data
Update the variable name to sm8250_gcc_data as it's in the sm8250
driver.

Fixes: dcd688229c ("clk/qcom: add driver for sm8250 GCC")
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250611-qcom-clk-variable-names-v1-2-37615b74daad@fairphone.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-06-24 07:54:51 -06:00
Luca Weiss
8c6481b738 clk/qcom: sc7280: Fix variable name of msm_clk_data
Update the variable name to sc7280_gcc_data as it's in the sc7280
driver.

Fixes: f50e7be6bb ("clk/qcom: add initial clock driver for sc7280")
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250611-qcom-clk-variable-names-v1-1-37615b74daad@fairphone.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-06-24 07:54:51 -06:00
Luca Weiss
41e2de28c0 doc: board/qualcomm: Add example for boot image version 2
As required e.g. on Fairphone 5, add an example how to use boot image
with header version 2.

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://lore.kernel.org/r/20250611-qualcomm-doc-update-v1-3-5cf8cd94974d@fairphone.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-06-24 07:54:51 -06:00
Luca Weiss
13043a2339 doc: board/qualcomm: Replace buildman build instructions
This command does not work as described in this doc, so replace it with
a regular make with qcom_defconfig, as already used for other
defconfigs.

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://lore.kernel.org/r/20250611-qualcomm-doc-update-v1-2-5cf8cd94974d@fairphone.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-06-24 07:54:51 -06:00
Luca Weiss
6746e81ba6 doc: board/qualcomm: Fix commands for compilation missing CROSS_COMPILE
One needs to set CROSS_COMPILE also for the actual compilation, not just
for the kconfig step, otherwise the host arch compiler would be used.

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://lore.kernel.org/r/20250611-qualcomm-doc-update-v1-1-5cf8cd94974d@fairphone.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-06-24 07:54:51 -06:00
Caleb Connolly
5df87251c2 qcom_defconfig: enable capsule update support
We can now correctly identify which partition U-Boot is flashed to
between uefi, xbl, and boot (including A/B support) so enable capsule
update support for all boards.

Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Link: https://lore.kernel.org/r/20250411-b4-qcom-capsule-update-improvements-v2-4-27f6b2fcc4a9@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-06-24 07:54:51 -06:00
Caleb Connolly
b946a9ff1b dfu: scsi: don't call scsi_scan()
Calling scsi_scan() results in all the block devices (and EFI block
devices) being destroyed and re-created. This breaks the EFI filesystem
drivers during capsule update.

Remove the call, since boards really should be calling scsi_scan()
themselves during board_init().

Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Link: https://lore.kernel.org/r/20250411-b4-qcom-capsule-update-improvements-v2-3-27f6b2fcc4a9@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-06-24 07:54:51 -06:00
Caleb Connolly
fe80a5f800 mach-snapdragon: CapsuleUpdate: support all boot methods
Expand capsule update support to correctly identify which partition
U-Boot is flashed to (between xbl, uefi, and boot including A/B
variants).

Use qcom_boot_source to determine if we were chainloaded from ABL,
meaning U-Boot is on the boot partition, otherwise we assume uefi if
it's available, finally leaving the xbl partition.

Set a different fw_name based on the target partition to prevent GUID
collisions, since a board may support U-Boot flashed to boot or XBL we
need to differentiate them since the U-Boot binary must be built
differently.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Link: https://lore.kernel.org/r/20250411-b4-qcom-capsule-update-improvements-v2-2-27f6b2fcc4a9@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-06-24 07:54:51 -06:00
Caleb Connolly
35cdb4676e mach-snapdragon: track boot source
Keep track of whether we were loaded via ABL or if U-Boot is running as
a first-stage bootloader.

For now we set this based on if we have a valid external FDT or not,
since it isn't possible to chainload U-Boot from ABL without there being
an external FDT.

This will be used to inform the capsule update logic which partition
U-Boot is flashed to.

Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Link: https://lore.kernel.org/r/20250411-b4-qcom-capsule-update-improvements-v2-1-27f6b2fcc4a9@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-06-24 07:54:51 -06:00
Aswin Murugan
32f0291900 board: qualcomm: Add MAINTAINERS entries for Dragonwing platforms
Added MAINTAINERS entries for the Qualcomm Dragonwing platforms, following
the discussion in the referenced thread.
https://lore.kernel.org/u-boot/20250603192206.GK1382132@bill-the-cat/

Signed-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Acked-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Acked-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250610093732.2060702-1-aswin.murugan@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-06-24 07:54:51 -06:00
George Chan
a43ba5497f mach-snapdragon: Enhance android image handling memory footprint
In order to unzipped kernel from androidboot img, extra memory for
loadaddr is needed. So once fastboot is enabled fastboot memory also
share with loadaddr.

That can balance with memory constrain soc and android usecase.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: George Chan <gchan9527@gmail.com>
Link: https://lore.kernel.org/r/20250518-android-boot-v3-3-02c8768e131f@gmail.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-06-24 07:54:51 -06:00
George Chan
ca2a038346 mach-snapdragon: Enable workaround of ignoring androidboot addr
Enable the workaround for whole snapdragon family.

Suggested-by: Casey Connolly <casey.connolly@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: George Chan <gchan9527@gmail.com>
Link: https://lore.kernel.org/r/20250518-android-boot-v3-2-02c8768e131f@gmail.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-06-24 07:54:51 -06:00
George Chan
e122850933 boot/image-android: Workaround kernel/ramdisk invalid addr
Some androidboot image have invalid kernel/ramdisk load addr,
force to ignore those value and use loadaddr instead.

There is a concern on exposing the whole memory to image loading is
dangerous. Also, since it's not always possible to change the load
addr by repacking the boot.img (mainly due to AVB signature mismatch),
we need a way to use kernel_addr_r and ramdisk_addr_r.

Suggested-by: Casey Connolly <casey.connolly@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Tested-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Signed-off-by: George Chan <gchan9527@gmail.com>
Link: https://lore.kernel.org/r/20250518-android-boot-v3-1-02c8768e131f@gmail.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-06-24 07:54:51 -06:00
Casey Connolly
482fc6a82a board: qualcomm: add a MAINTAINERS file
Add a MAINTAINERS file for assigning maintainership of a particular
Qualcomm platform or board (if board specific files exist). It is
intended to supplement the treewide ARM SNAPDRAGON maintainers with
folks who have a more specific interest.

Add an initial entry for the QCS6490 platform which powers the RB3 Gen 2 board.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250604113452.1075503-2-casey.connolly@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-06-24 07:54:51 -06:00
Aswin Murugan
caac92ad28 configs: add qcom_qcs615_defconfig
Introduce a defconfig for QCS615 based boards.

Signed-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250521035324.1182833-6-aswin.murugan@oss.qualcomm.com
[casey: fix subject msg]
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-06-24 07:54:51 -06:00
Aswin Murugan
ddb3c75774 qcom_defconfig: Enable QCS615 clock driver
Enable the QCS615 clock driver in Qualcomm defconfig.

Signed-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250521035324.1182833-5-aswin.murugan@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-06-24 07:54:51 -06:00
Aswin Murugan
4add840e7e clk/qcom: qcs615: Add GCC clock driver for QCS615
Port Linux's gcc-qcs615.c driver to U-Boot for basic bring-up.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250521035324.1182833-4-aswin.murugan@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-06-24 07:54:51 -06:00
Aswin Murugan
d9dd486c5b phy: qcom: Enable QMP UFS PHY driver for QCS615
Enable QMP phy for QCS615, referenced from Linux.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250521035324.1182833-3-aswin.murugan@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-06-24 07:54:49 -06:00
Aswin Murugan
abe2faf426 dts: qcs615-ride-u-boot.dtsi: Add memory entry to bootup
Added the memory entry to bootup.

Signed-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250521035324.1182833-2-aswin.murugan@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-06-24 07:54:49 -06:00
Balaji Selvanathan
5afb01b2ab configs: add qcom_qcs8300_defconfig
Introduce a defconfig for QCS8300 based boards.

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250529154931.1879976-7-quic_bselvana@quicinc.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-06-24 07:54:49 -06:00
Balaji Selvanathan
1c6f9b4558 qcom_defconfig: Enable QCS8300 clock driver
Enable the QCS8300 clock driver in Qualcomm defconfig.

Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250529154931.1879976-6-quic_bselvana@quicinc.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-06-24 07:54:49 -06:00
Balaji Selvanathan
b661d7c96b phy: qcom: Enable QMP UFS PHY driver for QCS8300
Enable QMP phy for QCS8300, referenced from Linux.

Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250529154931.1879976-5-quic_bselvana@quicinc.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-06-24 07:54:23 -06:00
Balaji Selvanathan
57f232607b clk/qcom: qcs8300: Add GCC clock driver for QCS8300
* Port Linux's gcc-qcs8300.c driver to U-Boot for basic bring-up.

* Enable QCS8300 clocks in qcom_defconfig.

Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250529154931.1879976-4-quic_bselvana@quicinc.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-06-24 07:54:03 -06:00
Balaji Selvanathan
8e29f5adcc dts: qcs8300-ride-u-boot.dtsi: Add memory entry to bootup
Added the memory entry to bootup.

Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250529154931.1879976-3-quic_bselvana@quicinc.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-06-24 07:54:03 -06:00
Balaji Selvanathan
e71cfbbae6 doc: board: qualcomm: document Dragonwing board building/flashing
Introducing documentation support for Qualcomm Dragonwing series
boards. Documents the build and flashing steps.

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250529154931.1879976-2-quic_bselvana@quicinc.com
[Casey: add dragonwing to board/qualcomm/index.rst]
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-06-24 07:54:03 -06:00
Sumit Garg
787ef52288 mach-snapdragon: of_fixup: Drop USB dr_mode override for RB1/2
The default DIP switch configuration on RB1/2 is to enable flashing
support via USB type-c port either using QDL or fastboot. It's just
cumbersome to get the host mode working in U-Boot via DIP switch toggle
when you need the flashing capability using the type-c port.

So instead lets enable fastboot in U-Boot for RB1/2 boards which is
more useful in the default board DIP switch configuration. This let's
us to drop dr_mode DT fixup.

Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250516130854.606067-1-sumit.garg@kernel.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-06-24 07:54:03 -06:00
Aswin Murugan
ddc527ac43 gpio: msm_gpio: return correct value for gpio read
In the current implementation, the GPIO read operation considers
both the input and outbut bits (bits 0 and 1). It should only consider
the state of input bit, i.e bit 0. To address this, mask input bit
alone and read it.

Signed-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250508113646.1462518-1-aswin.murugan@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-06-24 07:53:33 -06:00
Andre Przywara
babf74be60 sunxi: H616: add support for YuzukiHD Chameleon board
The Chameleon board is an OpenHardware devboard made by YuzukiTsuru,
featuring an Allwinner H616 SoC. The form factor resembles the Raspberry
Pi Model A boards, though it differs significantly in its features.
Apart from the usual peripherals of those kind of boards (SD card, eMMC,
WiFi, HDMI), it features four USB-C 2.0 ports.

Add a defconfig for the board, the DRAM parameters have been extracted
from the firmware shipped with the board.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2025-06-24 13:44:52 +01:00
Andre Przywara
63c9c69780 arm64: dts: allwinner: h616: add YuzukiHD Chameleon support
The Chameleon board is an OpenHardware devboard made by YuzukiTsuru.
The form factor resembles the Raspberry Pi Model A boards, though it
differs significantly in its features:

  - Allwinner H618 SoC (4 * Arm Cortex-A53 cores, 1MB L2 cache, 1.4 GHz)
  - between 512MiB and 2GiB DDR3 DRAM
  - up to 128 GiB eMMC flash
  - AXP313a PMIC
  - 100 Mbit/s Ethernet pins on a header
  - XR829 WIFI+Bluetooth chip
  - 4 * USB 2.0 USB-C ports
  - microSD card slot
  - 3.5mm A/V port

Add the devicetree describing the board's peripherals and their
connections.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://patch.msgid.link/20250307005712.16828-16-andre.przywara@arm.com
Signed-off-by: Chen-Yu Tsai <wens@csie.org>

[ upstream commit: f4a6b0f7200f8629f4138f1094ce654ab75df41e ]

(cherry picked from commit 3a879d878553d57057ce0a7096bfbf1eb077f6dc)
2025-06-24 13:44:52 +01:00
Andre Przywara
be5038f168 sunxi: add support for Liontron H-A133L board
The Liontron H-A133L is an industrial development board based on the
Allwinner A133 SoC. It uses LPDDR4 DRAM, eMMC, and an AXP707 PMIC.

Add a defconfig with the required DRAM settings.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2025-06-24 13:44:48 +01:00
Andre Przywara
1cc93d42b2 arm64: dts: allwinner: a100: add Liontron H-A133L board support
The H-A133L board is an industrial development board made by Liontron.
It contains a number of dedicated JST connectors, to connect external
peripherals. It features:

- Allwinner A133 SoC (4 * Arm Cortex-A53 cores at up to 1.6 GHz)
- 1 GiB, 2 GiB or 4 GiB of LPDDR4 DRAM
- between 16 and 128 GiB eMMC flash
- AXP707 PMIC (compatible to AXP803)
- 100 Mbit/s RJ45 Ethernet socket, using an JLSemi JL1101 PHY
- XR829 WIFI+Bluetooth chip
- 2 * USB 2.0 USB-A ports, plus three sets of USB pins on connectors
  (connected via a USB hub connected to USB1 on the SoC)
- microSD card slot
- 3.5mm A/V port
- 12V power supply
- connectors for an LVDS or MIPI-DSI panel

Add the devicetree describing the board's peripherals and their
connections.

Despite being a devboard, the manufacturer does not publish a schematic
(I asked), so the PMIC rail assignments were bases on BSP dumps,
educated guesses and some experimentation. Dropping the always-on
property from any of the rails carrying it will make the board hang as
soon as the kernel turns off unused regulators.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Link: https://patch.msgid.link/20250505164729.18175-4-andre.przywara@arm.com
[wens@csie.org: fix property in &usbphy; fix comment typo in &usb_otg]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>

[ upstream commit: a3cd12acb7b74d9b243cd893209972fc657d0bd3 ]

(cherry picked from commit 4062957c0797752dcf8b71f99c7aa47301c70aac)
2025-06-24 01:59:10 +01:00
Andre Przywara
2b2783a1c0 arm64: dts: allwinner: a100: set maximum MMC frequency
The manual for the Allwinner A133 SoC mentions that the maximum
supported MMC frequency is 150 MHz, for all of the MMC devices.

Describe that in the DT entry, to help drivers setting the right
interface frequency.

Fixes: fcfbb8d9ec58 ("arm64: allwinner: a100: Add MMC related nodes")
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Link: https://patch.msgid.link/20250505202416.23753-1-andre.przywara@arm.com
Signed-off-by: Chen-Yu Tsai <wens@csie.org>

[ upstream commit: d8f10550448b03d3c5c6d9392119205c65ebfc89 ]

(cherry picked from commit 85e37e6a8a002eb231df8209478d7ff2b134a451)
2025-06-24 01:59:09 +01:00
Andre Przywara
fb4c3b2a04 sunxi: add support for the Allwinner A100/A133 SoC
The Allwinner A100 SoC has been around for a while, mostly on cheap
tablets, but didn't generate much interest in the community so far.
There were some efforts by two Allwinner employees in 2020, which led
to basic upstream Linux support for that SoC, although this momentum
dried up pretty quickly, leaving a lot of peripherals unsupported.

The A100 was silently replaced with the seemingly identical Allwinner
A133, which is reportedly a better bin of the A100. So far we assume
that both are compatible from a software perspective. There are some
more devices with the A133 out there now, so people are working on
filling the gaps, and adding U-Boot (and TF-A) support.

Based on the just added pinctrl, clock and DRAM support, this adds the
missing bits, mostly addresses and values for the SPL.

The A133 seems to be an predecessor to the H6, so we can share a lot of
code with that (and the H616 code), and just need to adjust some details.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2025-06-24 01:59:09 +01:00
Cody Eksal
7a337270c0 sunxi: A133: add DRAM init code
This adds preliminary support for the DRAM controller in the Allwinner
A100/A133 SoCs.
This is work in progress, and has rough edges, but works on at least
three different boards. It contains support for DDR4 and LPDDR4.

Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
[Andre: formatting fixes, adapt to mainline, drop unused parameters,
	remove struct struct sunxi_mctl_com_reg, hardcode MR registers,
	switch to mctl_check_pattern(), remove simple DRAM check]
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2025-06-24 01:59:09 +01:00
Tom Rini
184e7d0bb2 Merge tag 'v2025.07-rc5' into next
Prepare v2025.07-rc5

With this merge, tighten up the LTO_FLAGS removal we added to not
trigger on ARMv7 (which is Thumb-2 and should be fine).
2025-06-23 16:15:23 -06:00
Balaji Selvanathan
35811a7b0d drivers: watchdog: qcom: Add timeout configuration support in watchdog
This patch enhances the Qualcomm watchdog driver by introducing
support for dynamic timeout configuration. Specifically:

- Calculates and sets the bark and bite timeout values based on
  the clock rate and the requested timeout in milliseconds.
- Adds retrieval of the watchdog clock rate during probe using
  the common clock framework.
- Adds a default timeout value for ARCH_SNAPDRAGON
  in WATCHDOG_TIMEOUT_MSECS.

These changes improve the configurability and accuracy of the
watchdog timer on Qualcomm platforms.

This work builds upon the previous submission:
https://lore.kernel.org/all/20250422-b4-qcom-wdt-v3-1-730d4d5a858d@paulsajna.com/

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250527124926.128413-1-balaji.selvanathan@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-06-23 18:50:39 +02:00
Casey Connolly
530764de9f watchdog: qcom: introduce qcom-wdt driver
Some Qualcomm device vendors decide to turn the watchdog on in the
bootloader, resulting in the device being reset if it isn't petted every
~30 seconds. Introduce a driver to keep the watchdog happy and prevent this
annoying behaviour.

Signed-off-by: Paul Sajna <hello@paulsajna.com>
Co-authored-by: Paul Sajna <hello@paulsajna.com>
Tested-by: Paul Sajna <hello@paulsajna.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250422-b4-qcom-wdt-v3-1-730d4d5a858d@paulsajna.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-06-23 18:50:38 +02:00
Varadarajan Narayanan
cb99e1257b configs: add qcom_ipq5424_mmc_defconfig
Introduce a defconfig for the Qualcomm IPQ5424 SoC based RDPs.
Presently supports eMMC.

Per the flash memory layout, U-Boot size cannot exceed 756KB. With this
defconfig, u-boot.mbn size is ~480KB.

Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://lore.kernel.org/r/20250304110105.2762124-7-quic_varada@quicinc.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-06-23 18:50:21 +02:00
Varadarajan Narayanan
c4aa86c04f pinctrl: qcom: Add ipq5424 pinctrl driver
Add pinctrl driver for the TLMM block found in the ipq5424 SoC.

Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://lore.kernel.org/r/20250304110105.2762124-6-quic_varada@quicinc.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-06-23 18:50:21 +02:00
Varadarajan Narayanan
d7fb15c17d clk/qcom: add initial clock driver for ipq5424
Add initial set of clocks and resets for enabling U-Boot on ipq5424
based RDP platforms.

Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://lore.kernel.org/r/20250304110105.2762124-5-quic_varada@quicinc.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-06-23 18:50:21 +02:00
Varadarajan Narayanan
c1363633c6 doc: board/qualcomm: Update RDP signing instructions
IPQ5424 expects U-Boot to have MBN version 7 header. The qtestsign tool
presently documented doesn't support v7. Hence update the instructions
to use a different tool that can support both v6 and v7.

Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://lore.kernel.org/r/20250304110105.2762124-4-quic_varada@quicinc.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-06-23 18:50:21 +02:00
Varadarajan Narayanan
9997cc261a dts: ipq5424-rdp466-u-boot: add override dtsi
Add initial support for the IPQ5424 MMC based RDP platforms.
Define memory layout statically.

Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://lore.kernel.org/r/20250304110105.2762124-3-quic_varada@quicinc.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-06-23 18:50:21 +02:00
Tom Rini
dbf7fd557a Merge patch series "Consistent Kconfig environment options CONFIG_ENV_ prefix"
Marek Vasut <marek.vasut+renesas@mailbox.org> says:

Rename the environment related variables and add ENV_ prefix, so that
all configuration options which are related to environment would have
an CONFIG_ENV_ prefix. No functional change.

Link: https://lore.kernel.org/r/20250609192701.20260-1-marek.vasut+renesas@mailbox.org
2025-06-20 12:57:47 -06:00
Marek Vasut
224224c9fa env: Drop DELAY_ENVIRONMENT
There are no users of DELAY_ENVIRONMENT and the same effect can
be achieved either using DT /config/load-environment property,
or by using ENV_IS_NOWHERE . Remove this configuration option
and matching functionality.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-06-20 12:15:08 -06:00
Marek Vasut
fb5235239a env: Rename DEFAULT_ENV_FILE to ENV_DEFAULT_ENV_TEXT_FILE
Rename the variable and add ENV_ prefix, so that all configuration
options which are related to environment would have an CONFIG_ENV_
prefix. No functional change.

Also rename USE_DEFAULT_ENV_FILE to USE_ENV_DEFAULT_ENV_TEXT_FILE .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-06-20 12:15:08 -06:00
Marek Vasut
ffc4914703 env: Rename ENV_MMC_PARTITION to ENV_MMC_SW_PARTITION
Rename the variable and add ENV_ prefix, so that all configuration
options which are related to environment would have an CONFIG_ENV_
prefix. No functional change.

Use ENV_MMC_SW_PARTITION to clarify this is the SD/MMC software
partition table entry selector. Update the help text accordingly.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-06-20 12:15:08 -06:00
Marek Vasut
31617b880a env: Rename SYS_MMC_ENV_PART to ENV_MMC_EMMC_HW_PARTITION
Rename the variable and add ENV_ prefix, so that all configuration
options which are related to environment would have an CONFIG_ENV_
prefix. No functional change.

Use ENV_MMC_EMMC_HW_PARTITION to clarify this is the eMMC hardware
partition selector, not a software partition table entry selector.
Retain the ENV_MMC_ prefix to make it easier to search for all the
SD/MMC related ENV options. Update the help text accordingly.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-06-20 12:15:08 -06:00
Marek Vasut
0f44d5549e env: Rename SYS_MMC_ENV_DEV to ENV_MMC_DEVICE_INDEX
Rename the variable and add ENV_ prefix, so that all configuration
options which are related to environment would have an CONFIG_ENV_
prefix. No functional change.

Use ENV_MMC_DEVICE_INDEX to clarify this is the SD/MMC device
index, a number, as enumerated by U-Boot. Update the help text
accordingly.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-06-20 12:15:08 -06:00
Marek Vasut
123682c765 env: Rename SYS_RELOC_GD_ENV_ADDR to ENV_RELOC_GD_ENV_ADDR
Rename the variable and add ENV_ prefix, so that all configuration
options which are related to environment would have an CONFIG_ENV_
prefix. No functional change.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-06-20 12:15:08 -06:00
Marek Vasut
5fb88fa725 env: Rename SYS_REDUNDAND_ENVIRONMENT to ENV_REDUNDANT
Rename the variable and add ENV_ prefix, so that all configuration
options which are related to environment would have an CONFIG_ENV_
prefix. No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-06-20 12:15:08 -06:00
Marek Vasut
0fd9a3480a env: Rename OVERWRITE_ETHADDR_ONCE to ENV_OVERWRITE_ETHADDR_ONCE
Rename the variable and add ENV_ prefix, so that all configuration
options which are related to environment would have an CONFIG_ENV_
prefix. No functional change.

Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-06-20 12:15:08 -06:00
Tom Rini
73fd245623 Merge patch series "bootstd: Fix efi_mgr usage in bootmeths env var"
Sam Protsenko <semen.protsenko@linaro.org> says:

Defining the 'bootmeths' environment variable with efi_mgr causes NULL
pointer dereference when running 'bootflow scan' on the E850-96 board.
This patch series fixes that, and cleans up the surrounding code a
little while at it.

Link: https://lore.kernel.org/r/20250112034213.13153-1-semen.protsenko@linaro.org
2025-06-20 08:01:16 -06:00
Sam Protsenko
8c61fc082e bootstd: Fix incorrect struct name in bootmeth_setup_iter_order()
There is no such thing as struct bootmeth, it's probably a typo. This
issue doesn't affect the execution as it's a pointer, and pointer sizes
are the same for all data types. But it can be confusing, so make it
struct udevice, as it should be.

Fixes: a950d31abe ("bootstd: Add the bootmeth uclass and helpers")
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
2025-06-20 08:01:09 -06:00
Sam Protsenko
8da358c0a1 bootstd: Probe bootmeth devices for bootmeths env var
Specifying efi_mgr in 'bootmeths' environment variable leads to NULL
pointer dereference when 'bootflow scan' is executed, with call trace
like this:

    priv->fake_dev // NULL pointer dereference
    .read_bootflow = efi_mgr_read_bootflow()
    bootmeth_get_bootflow()
    bootflow_check()
    bootflow_scan_first()
    do_bootflow_scan()
    'bootflow scan -l'

That happens because in case when 'bootmeths' env var is defined the
bootmeth_efi_mgr driver is not probed, and the memory for its private
data isn't allocated by .priv_auto. In case when 'bootmeths' env var is
not defined, the std->bootmeth_count is 0, and the execution flow in
bootmeth_setup_iter_order() takes "no ordering" path, which in turn runs
uclass_get_device_by_seq() -> ... -> device_probe(), so issue isn't
present there. But when 'bootmeths' is defined and contains efi_mgr, the
std->bootmeth_count > 0, so bootmeth_setup_iter_order() follows the "we
have an ordering" path, where devices are not probed. In other words:

    'bootmeths' defined           'bootmeths' not defined
    --------------------------------------------------------
    priv == NULL                    priv != NULL
         ^                                ^
         |                        device_alloc_priv()
     no probe                     device_of_to_plat()
         ^                        device_probe()
         |                        uclass_get_device_tail()
    dev = order[i]                uclass_get_device_by_seq()
         ^                                ^
         | have an ordering               | no ordering
         +----------------+---------------+
                          |
             bootmeth_setup_iter_order()
             bootflow_scan_first()
             do_bootflow_scan()

Add an explicit device_probe() call in "we have an ordering" case to fix
the issue.

Fixes: c627cfc14c ("bootstd: Allow scanning for global bootmeths separately")
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2025-06-20 08:01:09 -06:00
Sam Protsenko
11319e0e2b bootstd: Fix memleak on errors in bootmeth_setup_iter_order()
Free memory allocated for 'order' (array of bootmeths) on error paths in
bootmeth_setup_iter_order() function.

Fixes: c627cfc14c ("bootstd: Allow scanning for global bootmeths separately")
Fixes: 10d16faa43 ("bootstd: Detect empty bootmeth")
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2025-06-20 08:01:09 -06:00
Tom Rini
4bbfd1c042 Merge tag 'u-boot-at91-2025.10-a' of https://source.denx.de/u-boot/custodians/u-boot-at91 into next
First set of u-boot-at91 features for the 2025.10 cycle:

This feature set includes the addition of new sam9x7 SoC and a new board
named sam9x7-curiosity. There is also new support for sam9x60 compatible
at91 watchdog.
2025-06-20 07:59:34 -06:00
Eric Schikschneit
5ba5cbf5a2 dtc: Add Kconfig option to pad device tree blob
This will allow arch(s) that use device tree blobs to pad the end of the
device tree so they can be modified by board files at run time. This will
help prevent errors such as FDT_ERR_NOSPACE from occurring.

Signed-off-by: Eric Schikschneit <eric.schikschneit@novatechautomation.com>
[trini: Change default order so that X86 && EFI_APP works correctly]
2025-06-19 19:00:09 -06:00
Tom Rini
0c6c8065a2 Merge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-sh into next
- Assorted cleanups and R-Car Gen4 watchdog driver
2025-06-19 08:11:25 -06:00
Manikandan Muralidharan
9b9a2c9994 configs: sam9x75_curiosity: Add initial mmc default config
Add default configuration for sd-card to boot the linux kernel.

Signed-off-by: Manikandan Muralidharan <manikandan.m@microchip.com>
Reviewed-by: Eugen Hristev <eugen.hristev@linaro.org>
2025-06-19 13:56:43 +03:00
Manikandan Muralidharan
ee6d7a5bf8 board: sam9x75_curiosity: Add support for sam9x75 curiosity
Add board specific functions for sam9x75 curiosity

Signed-off-by: Manikandan Muralidharan <manikandan.m@microchip.com>
Reviewed-by: Eugen Hristev <eugen.hristev@linaro.org>
2025-06-19 13:56:43 +03:00
Manikandan Muralidharan
c65f413ea0 ARM: dts: at91: sam9x75_curiosity: add tweaks for sam9x75 curiosity board
Since the SoC and board DT are already available in dts/upstream,
add the difference from upstream DTS to at91-sam9x75_curiosity-u-boot.dtsi

Signed-off-by: Manikandan Muralidharan <manikandan.m@microchip.com>
Reviewed-by: Eugen Hristev <eugen.hristev@linaro.org>
2025-06-19 13:56:43 +03:00
Varshini Rajendran
f66e0825c6 ARM: at91: Add sam9x7 soc
Add new Microchip sam9x7 SoC based on an ARM926.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
Signed-off-by: Balamanikandan Gunasundar <balamanikandan.gunasundar@microchip.com>
Signed-off-by: Manikandan Muralidharan <manikandan.m@microchip.com>
2025-06-19 13:56:43 +03:00
Varshini Rajendran
c9d609be60 clk: at91: sam9x7: add pmc driver for sam9x7 SoC family
Add PMC driver support for sam9x7 SoC family

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
[balamanikandan.gunasundar@microchip.com: Add peripheral clock id for pmecc]
Signed-off-by: Balamanikandan Gunasundar <balamanikandan.gunasundar@microchip.com>
2025-06-19 13:56:43 +03:00
Manikandan Muralidharan
ed5ffbee48 clk: at91: clk-main: drop parent_name check when registering main_rc oscillator
The clk_register function logs an error if parent_name is missing from the
Device Tree.On the SAM9X7, the main_rc node is omitted to stay aligned with
the Linux Device Tree.Remove the parent_name check in at91_clk_main_rc()
to allow it to pass NULL when the parent is not specified.

Signed-off-by: Manikandan Muralidharan <manikandan.m@microchip.com>
2025-06-19 13:56:43 +03:00
Varshini Rajendran
107cf34bd7 clk: at91: sam9x60-pll: add support for HW PLL freq dividers
Add support for hardware dividers for PLL IDs.In sam9x7 SoC,
PLL_ID_PLLA and PLL_ID_PLLA_DIV2 has /2 hardware dividers
each.

fcorepllack -----> HW Div = 2 -+--> fpllack
                               |
                               +--> HW Div = 2 ---> fplladiv2ck

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
2025-06-19 13:56:43 +03:00
Varshini Rajendran
02217d07a3 clk: at91: sam9x60-pll: add support for core clock frequency inputs
Add support for different core clock frequency input ranges
for different PLL IDs in the PLL driver and align sam9x60, sama7g5 SOC
platforms.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
2025-06-19 13:56:43 +03:00
Manikandan Muralidharan
ef0ae31dcc dt-bindings: drop at91.h from clock includes
Remove clock/at91.h file as it is subset of
dts/upstream/include/dt-bindings/clock/at91.h.
The constants defined in this header are being used only in dts

Signed-off-by: Manikandan Muralidharan <manikandan.m@microchip.com>
2025-06-19 13:56:43 +03:00
Fabio Estevam
f414dbcc13 board: sama5d27_wlsom1_ek: Get RAM size and base from devicetree
Instead of using defines for the RAM size and base address, retrieve these
information from the devicetree.

This aligns with the sama5d27_som1_ek board in commit 73c1589f02
("board: sama5d27_som1_ek: Get dram size and base from device tree").

While at it, remove a spurious '/* SPL */' comment.

Signed-off-by: Fabio Estevam <festevam@denx.de>
2025-06-19 13:56:43 +03:00
Zixun LI
57fb27c027 ARM: dts: at91: sam9x60-curiosity: Enable watchdog node
Enable watchdog node on SAM9X60-Curiosity board.

A default timeout of 16s is added which is the maximum supported value,
also matching Linux driver's behavior.

Signed-off-by: Zixun LI <admin@hifiphile.com>
Reviewed-by: Eugen Hristev <eugen.hristev@linaro.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2025-06-19 13:56:43 +03:00
Zixun LI
d18f1f4730 ARM: dts: sam9x60: Add watchdog DT node
Add the watchdog timer node for the sam9x60 SoC's.

Signed-off-by: Zixun LI <admin@hifiphile.com>
Reviewed-by: Eugen Hristev <eugen.hristev@linaro.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2025-06-19 13:56:42 +03:00
Zixun LI
ac46b48d30 watchdog: at91sam9_wdt: Add SAM9X60 support
SAM9X60 has a slightly different watchdog implementation:
- Timer value moved into a new register WLR
- Some MR register fields have their position changed

This patch add SAM9X60 support, also adds a compatible
for SAMA5D4 which is the same as existing SAM9260.

Signed-off-by: Zixun LI <admin@hifiphile.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2025-06-19 13:56:41 +03:00
Zixun LI
c8bf2d686d watchdog: at91sam9_wdt: Rename priv to wdt
"wdt" is a better name for watchdog rather than generic "priv".

Signed-off-by: Zixun LI <admin@hifiphile.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2025-06-19 13:56:13 +03:00
Zixun LI
98a83fc23b arm: at91: wdt: Rename regval in priv data to mr
Use the name "mr" since we are referring to timer mode register.

Signed-off-by: Zixun LI <admin@hifiphile.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2025-06-19 13:56:13 +03:00
Zixun LI
c7e4262580 arm: at91: wdt: Remove at91_wdt struct
at91_wdt struct is only used by spl, remove this reference and the struct
itself.

Signed-off-by: Zixun LI <admin@hifiphile.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2025-06-19 13:56:13 +03:00
Tom Rini
ff43c2272a Merge patch series "Print version of the DM firmware"
Moteen Shah <m-shah@ti.com> says:

This patch series adds the functionality to print the DM firmware
version being used. Before requesting TISCI for the DM version we
first check if the DM split mode capability exists, if yes, we proceed
onto making the call to TISCI for retrieving the version information.

DM split mode capability indicates that the DM is a separate binary
altogether and has its own versioning information similar to TIFS.

Boot Logs: https://gist.github.com/Jamm02/37864f605445944a0c0caf426e0aba50

Link: https://software-dl.ti.com/tisci/esd/latest/2_tisci_msgs/general/core.html#tisci-msg-query-fw-caps
Link: https://lore.kernel.org/r/20250609081434.1000377-1-m-shah@ti.com
2025-06-18 15:54:48 -06:00
Tom Rini
6226bfa41a Merge patch series "Add IPC support on MCU R5F cluster in Split Mode"
Beleswar Padhi <b-padhi@ti.com> says:

This series adds remoteproc support on MCU R5F in Split mode.

During boot, ROM can bring up the boot R5F cores in either lockstep or
split mode based on X509 certificate flags. If booted in lockstep mode,
the MCU R5F cores will run first the R5 SPL, and then once A72 comes up,
will run the Device Manager (DM) firmware. But if booted in split mode, core
0 will run DM firmware and second core sits in WFI. Shut it down so that
other firmwares can later be loaded on them.

The shutdown of MCU R5 Core 1 is invoked at A72 SPL init, as by that
time Device Manager (DM) is up and running on R5 Core 0. The shutdown
of MCU R5 Core 1 is handled by Device Manager itself.

Test logs:
https://gist.github.com/3V3RYONE/ee8e3cb9aa5f4c5c00b059b9c14bfa98

Link: https://lore.kernel.org/r/20250609081429.1724643-1-b-padhi@ti.com
2025-06-18 15:54:48 -06:00
Tom Rini
009d7722ff Merge patch series "bootstd: New bootmeth for RAUC A/B systems"
Martin Schwan <m.schwan@phytec.de> says:

This series implements a new bootmeth for RAUC A/B systems. RAUC (Robust
Auto Update Controller) is a lightweight update client, providing "Safe
and Secure OTA Updates for Embedded Linux". See the following links for
more information about RAUC:

  https://rauc.io/
  https://rauc.readthedocs.io/en/latest/

PHYTEC uses RAUC in its Yocto based distribution "Ampliphy" as the
default way of updating embedded devices based on PHYTEC hardware. So
far, the logic selecting the correct partitions and files to boot was
being implemented in the U-Boot environment. While this is a
straightforward way to do it, adding and supporting new platforms became
somewhat tedious and is platform-specific. The introduction of U-Boot's
"Standard Boot" provided a convincing alternative, promising a simpler
and more portable way of booting, even for RAUC systems. This led me to
implement a new bootmeth supporting RAUC A/B systems. Note, that this
new bootmeth is not proprietary to PHYTEC products and is designed to
work on other hardware with a RAUC A/B system, too.

The bootmeth currently only supports symmetric A/B partitioning layouts.
E.g. A/rescue is not (yet) supported. The partition indexes and default
slot tries can be specified via configuration options.

For now, the bootmeth_rauc uses a similar approach for loading the
Kernel and device tree as the bootmeth_script, in that it requires a FIT
containing a U-Boot script loading the desired distro. It could be
possible to support booting without a script and load the Kernel and DT
directly with this bootmeth, but I found the script method to be very
flexible for now, in letting the distro decide what to load.

The bootmeth_rauc was tested on a phyBOARD-Pollux i.MX8M Plus [1] with
BSP-Yocto-Ampliphy-i.MX8MP-PD24.1.2 [2].

Supported boot devices are currently only MMC devices, but it should be
possible to add SPI flashes in the future.

To test this patch stack with PHYTEC's phyBOARD-Pollux i.MX8M Plus
board, you need to adjust the boot files to include the boot.scr.uimg
containing the distro's boot script and set "optargs" to "${raucargs}"
in it. Also disable any legacyboot in the U-Boot environment and simply
boot with Standard Boot:

  bootmeth order rauc
  bootflow scan -lb

[1]: https://www.phytec.eu/en/produkte/single-board-computer/phyboard-pollux/
[2]: https://download.phytec.de/Software/Linux/BSP-Yocto-i.MX8MP/BSP-Yocto-Ampliphy-i.MX8MP-PD24.1.2/

Link: https://lore.kernel.org/r/20250604-wip-bootmeth-rauc-v3-0-f9fad913c57e@phytec.de
[trini: Don't enable by default]
2025-06-18 15:54:33 -06:00
Moteen Shah
003e7d70cd arm: mach-k3: Print version of DM firmware during boot process
Print DM firmware's version in the boot up process of K3 devices,
having DM capability(DM as a separate binary).

Signed-off-by: Moteen Shah <m-shah@ti.com>
2025-06-18 12:20:25 -06:00
Moteen Shah
7bdbda262c arm: mach-k3: Add a function for printing DM version
Add a function to print version of the DM firmware in use.
The function queries the firmware capabilities first and if
DM split mode bit is set, sends a request to TISCI for
retrieving the version information.

The DM split mode bit indicates that DM is a separate binary
altogether and hence it will have its own versioning.

Signed-off-by: Moteen Shah <m-shah@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
2025-06-18 12:20:25 -06:00
Moteen Shah
60ee945855 firmware: ti_sci.c: Add a function to request DM metadata using ti_sci* calls
Add a function to retrieve information of the DM firmware's ABI versions,
RM/PM HAL, firmware version, etc using TI_SCI protocol.

Signed-off-by: Moteen Shah <m-shah@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
2025-06-18 12:20:25 -06:00
Moteen Shah
e1252194b6 firmware: ti_sci.c: Add a function to query DM firmware's capability
Add a new function to query the capabilities of the DM firmware, using
TI SCI protocol to retrieve a 64-bit firmware capability, where each bit
represents a specific capability supported by the firmware.

Signed-off-by: Moteen Shah <m-shah@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
2025-06-18 12:20:25 -06:00
Moteen Shah
33fc7751b9 ti_sci_* : Add capability to access DM firmware's metadata
Introduce response and request structs to receive and request
information regarding DM version, etc from TI SCI.

Signed-off-by: Moteen Shah <m-shah@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
2025-06-18 12:20:25 -06:00
Moteen Shah
3bc174031d ti_sci_*: Add utility to access tisci firmware and SOC capability
Introduce response and request structs for receiving information
regarding FW/SOC capability from DM. The received capability can
further be used to call certain API's based on the feature supoorted
by the DM firmware.

Signed-off-by: Moteen Shah <m-shah@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
2025-06-18 12:20:25 -06:00
Beleswar Padhi
574321414f board: ti: j7*: Add firmware for MCU R5 core1
Link the default firmware in the environment variable for MCU R5 core1
for all J7 platforms.

Signed-off-by: Beleswar Padhi <b-padhi@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
2025-06-18 12:16:39 -06:00
Beleswar Padhi
92e77d3768 remoteproc: k3-r5: Acquire processor control before reset ops
Acquire processor control before doing core reset operations in probe
routine. Release the control afterwards, so that it can be acquired
during core loading operations.

Signed-off-by: Beleswar Padhi <b-padhi@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
2025-06-18 12:16:39 -06:00
Beleswar Padhi
87a9c1f5a0 arch: mach-k3: common: Add support to shutdown MCU R5 Core 1
During boot, ROM can bring up the MCU R5F cores in either lockstep or
split mode based on X509 certificate flags. If booted in split mode,
core 0 will run DM firmware and second core sits in WFI. Add support to
shut down core 1 so that other firmwares can later be loaded on them.

The shutdown of MCU R5 Core 1 is invoked at A72 SPL init, as by that
time Device Manager (DM) is up and running on R5 Core 0. The shutdown
request of Core 1 is handled by Device Manager itself.

Signed-off-by: Beleswar Padhi <b-padhi@ti.com>
2025-06-18 12:16:39 -06:00
Beleswar Padhi
873e9dedd0 arm: mach-k3: {am6/j7}*_hardware.h: Expose MCU R5 proc and device ids
Currently the MCU R5 processor ids and device ids are only defined for
R5 SPL Stage. Expose these ids always so that A72 SPL can utilize this
information to shutdown MCU R5 Core 1 when booted in Split mode.

Signed-off-by: Beleswar Padhi <b-padhi@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
2025-06-18 12:16:39 -06:00
Martin Schwan
309f77c33a doc: Add description for bootmeth rauc
Add documentation for the bootmeth "rauc", which boots an A/B system
with RAUC from MMC.

Signed-off-by: Martin Schwan <m.schwan@phytec.de>
2025-06-18 12:15:35 -06:00
Martin Schwan
7e5c2c782f bootstd: Add implementation for bootmeth rauc
Add a bootmeth driver which supports booting A/B system with RAUC as
their update client.

Signed-off-by: Martin Schwan <m.schwan@phytec.de>
Tested-by: Wadim Egorov <w.egorov@phytec.de>
2025-06-18 12:15:35 -06:00
Shmuel Leib Melamud
b1d017afda renesas: Renesas R-Car Gen4 watchdog driver
Add support of Renesas R-Car Gen4 watchdog timer. Timeouts up to
8184.0s are supported (CKS1 register is not involved). The watchdog
uses the clock of type CLK_TYPE_GEN4_MDSEL.

The timeout is set in
dts/upstream/src/arm64/renesas/r8a779f0-spider-cpu.dtsi section &rwdt.

This driver is based on upstream linux commit:
e70140ba0d2b("Get rid of 'remove_new' relic from platform driver struct")

Signed-off-by: Shmuel Leib Melamud <smelamud@redhat.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-06-18 17:18:47 +02:00
Tom Rini
ce2a7fcbd5 Merge patch series "list.h/treewide: get rid of no-op prefetch()"
Rasmus Villemoes <ravi@prevas.dk> says:

While looking through list.h, I saw that the regular list_* helpers
(and one of the hlist_* ones) still contain the prefetch() that was
removed in linux 14 years ago. It doesn't do anything, but makes the
macros harder to read, so get rid of it, and the fallback, no-op
definition that they relied on. That requires removing a few uses
outside list.h as well.

checkpatch warns about some whitespace issues in list.h, but as I've
copied whole kerneldoc+#define blocks directly from the linux kernel,
I think it's better to just accept that so that we don't introduce
needless diffs. The "macro argument reuse" arguments should also be
ignored, as e.g. the "member" arguments are obviously always just bare
identifiers, and the "pos" arguments must be assigned to multiple
times.

Link: https://lore.kernel.org/r/20250507121246.518691-1-ravi@prevas.dk
2025-06-18 08:05:29 -06:00
Rasmus Villemoes
1d19bbcb68 linux/list.h: drop fallback definition of prefetch()
None of the list helpers use prefetch() anymore, and no C code relies
on getting this definition from list.h. In any case, such an arch/cpu
specific thing does not belong in a header that just consists of cpp
helper macros.

Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
2025-06-18 08:05:04 -06:00
Rasmus Villemoes
f0ba1435a8 mips: drop unused prefetch code and logic
AFAICT, CONFIG_CPU_HAS_PREFETCH has never existed as a proper Kconfig
symbol in U-Boot, nor has any board include file ever defined it.

Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
2025-06-18 08:05:04 -06:00
Rasmus Villemoes
f5fa73a625 treewide: drop no-op prefetch() calls
These all end up using the no-op prefetch() defined in linux/list.h,
because the only possible real implementation is in
arch/mips/include/asm/processor.h, which is behing
CONFIG_CPU_HAS_PREFETCH which is nowhere defined.

In order to be able to drop that fallback definition from list.h,
first remove all uses.

Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
2025-06-18 08:05:04 -06:00
Rasmus Villemoes
c1c2b5c6a4 linux/list.h: drop use of prefetch()
The use of prefetch() in these list helpers was dropped back in 2011
in linux (e66eed651fd1 ("list: remove prefetching from regular list
iterators")). No arch in U-Boot defines any actual prefetch(), and as
the referenced commit says, it's usually not a win anyway.

Whole-sale sync of list.h is not really feasible, but we can
synchronize the macros containing a prefetch() with their linux
implementations as of v6.15-rc5, also importing the various helpers
needed, e.g. list_is_head() and list_next_entry().

Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
2025-06-18 08:05:04 -06:00
Shmuel Leib Melamud
77700bcc1d clk: renesas: Handle CLK_TYPE_GEN4_MDSEL in gen3_clk_get_rate64()
Add support of CLK_TYPE_GEN4_MDSEL clock type to gen3_clk_get_rate64()
function. In particular, this type of clock is used by Renesas R-Car
Gen4 watchdog. It operates similarly to CLK_TYPE_GEN3_MDSEL clock.

Signed-off-by: Shmuel Leib Melamud <smelamud@redhat.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2025-06-18 15:08:52 +02:00
Marek Vasut
dd8f57ed2f ARM: dts: renesas: Drop most of bootph-* tags
The bootph-* tags are now part of mainline Linux DTs as commits:
f1a1268572cc ("ARM: dts: renesas: rcar-gen2: Add boot phase tags")
399f14ff6625 ("arm64: dts: renesas: rcar: Add boot phase tags")
624b2a23d46a ("arm64: dts: renesas: rzg2: Add boot phase tags")
Drop local duplicates of the same tags, as well as duplicate
property assignments which are part of the core DTs themselves.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
2025-06-18 15:08:52 +02:00
Tom Rini
5d7e003248 Merge tag 'u-boot-imx-next-20250617' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx into next
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/26728

- Add support for imx28 BTT boards.
2025-06-17 08:12:39 -06:00
Lukasz Majewski
9d7f90782d ARM: imx: mxs: Add support for imx287 based BTT devices
The btt[c3] devices are based on imx287 SoC.

U-Boot SPL 2025.04-01081-g07e086681d26 (Apr 16 2025 - 12:24:36 +0200)
Trying to boot from MMC1

U-Boot 2025.04-01081-g07e086681d26 (Apr 16 2025 - 12:24:36 +0200)

CPU:   Freescale i.MX28 rev1.2 at 454 MHz
BOOT:  SSP SPI #3, master, 3V3 NOR
Model: BTT3
Board: LWE BTT SoM HW rev 0
DRAM:  256 MiB
Core:  86 devices, 15 uclasses, devicetree: separate
MMC:   MXS MMC: 0
Loading Environment from SPIFlash... SF: Detected is25lp128 with page
                    size 256 Bytes, erase size 64 KiB, total 16 MiB
OK
In:    serial@80074000
Out:   serial@80074000
Err:   serial@80074000
Net:   eth0: ethernet@800f0000
Hit any key to stop autoboot:  0

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2025-06-16 14:40:27 -03:00
Tom Rini
62d24441e0 Merge tag 'u-boot-dfu-next-20250616' of https://source.denx.de/u-boot/custodians/u-boot-dfu into next
u-boot-dfu-next-20250616

CI: https://source.denx.de/u-boot/custodians/u-boot-dfu/-/pipelines/26704

Usb gadget:
- Atmel: Improve gadget disconnect stability by power cycling
2025-06-16 11:06:51 -06:00
Tom Rini
4d23c8aeaa Merge tag 'u-boot-dfu-next-20250616' of https://source.denx.de/u-boot/custodians/u-boot-dfu into next
u-boot-dfu-next-20250616

CI: https://source.denx.de/u-boot/custodians/u-boot-dfu/-/pipelines/26704

Usb gadget:
- Fix ti_musb driver in gadget mode (with DM_USB_GADGET)

DFU:
- mmc/scsi backends when using 10 or more partitions
2025-06-16 09:39:31 -06:00
Zixun LI
ca036308a5 usb: gadget: atmel: reliably generate disconnect by disabling controller
Contrary to the datasheet, setting both DETACH and PULLD_DIS bits to 1
does not always drive the DP and DM lines to high-impedance. This
prevents the host from reliably detecting a USB disconnect and subsequent
reconnect.

The symptom is that the first gadget command (e.g., dhcp) succeeds, while
subsequent commands (e.g., nfs) fail.

Disabling and re-enabling the controller entirely, instead of toggling the
PULLD_DIS bit, reliably generates a disconnect event.

The Linux driver works correctly because gadget_disconnect/gadget_connect
are always followed by gadget_udc_start/gadget_udc_stop. In U-Boot
pullup() is used solely.

This behavior has been observed on the SAM9X60-Curiosity and
AT91SAM9G25-EK boards and has been reported to Microchip.

Signed-off-by: Zixun LI <admin@hifiphile.com>
Link: https://lore.kernel.org/r/20250602-pullup-v1-1-edcde5a050dd@hifiphile.com
[mkorpershoek: reworded commit title + comment to usba_udc_pullup()]
Signed-off-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
2025-06-16 11:56:19 +02:00
Tom Rini
9de873b4c3 Merge patch series "linux/bitfield.h: sync <linux/bitfield.h> from Linux 6.15 + winbond"
Christian Marangi <ansuelsmth@gmail.com> says:

This small series sync linux/bitfield.h from Linux 6.15 and fix all
the compilation error due to a change in the header include.

The sync is needed to make it easier to support the winbond changes.

The changes are CI test with [1]

[1] https://github.com/u-boot/u-boot/pull/777

Link: https://lore.kernel.org/r/20250607211133.2005-1-ansuelsmth@gmail.com
2025-06-14 09:13:39 -06:00
Christian Marangi
fe37fb8214 mtd: spinand: winbond: add Winbond W25N04KV flash support
Add Winbond W25N04KV flash support that use a different value to detect
ECC bitflip.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2025-06-14 09:11:10 -06:00
Christian Marangi
01cc7046ad linux/bitfield.h: sync <linux/bitfield.h> from Linux 6.15
Sync bitfield.h header with Linux 6.15 version. Mainly is to permit the
introduction of FIELD_PREP_CONST. The bug.h header changed to
build_bug.h doesn't cause any regression as we also ship split header
similar to how it's done with in Linux.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2025-06-14 09:11:10 -06:00
Christian Marangi
5c734237ac arm: apple: rtkit: add missing header linux/bug.h and linux/bitops.h
The GENMASK/GENMASK_ULL macro requires inclusion of linux/bitops.h
header. It does currently work as bitfield.h includes it indirectly
but this will change when bitfield.h will be synced with new Linux
version.

Also raw printf require linux/bug.h header (also currently included
indirectly by bitfield.h)

Explicitly include the headers to fix future compilation error.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2025-06-14 09:11:10 -06:00
Christian Marangi
1f1aafe0b5 iommu: qcom-smmu: add missing linux/bug.h header for WARN_ON
The WARN macro requires inclusion of linux/bug.h header. It does
currently work as bitfield.h includes it indirectly but this will
change when bitfield.h will be synced with new Linux version.

Explicitly include the header to fix future compilation error.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2025-06-14 09:11:10 -06:00
Christian Marangi
7d0f273379 clk: imx: add missing linux/bug.h header for WARN
The WARN macro requires inclusion of linux/bug.h header. It does
currently work as bitfield.h includes it indirectly but this will
change when bitfield.h will be synced with new Linux version.

Explicitly include the header to fix future compilation error.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2025-06-14 09:11:10 -06:00
Tom Rini
03817a2a80 Merge patch series "Hex value prefix case cleanup"
E Shattow <e@freeshell.de> says:

Make consistent use of lowercase hexadecimal prefix '0x' throughout U-Boot.

There are a few remaining uses of uppercase 'X' to denote hexadecimal prefix
or placeholder in documentation and error messages.

External devicetree-rebasing dts/upstream and the generated code of
xilinx/zynq are ignored for the series.

Link: https://lore.kernel.org/r/20250606224558.1117422-1-e@freeshell.de
2025-06-14 09:10:48 -06:00
E Shattow
0230ad1c30 include: use lowercase hex prefix style
Use consistent lowercase hex prefix style in include/*

Signed-off-by: E Shattow <e@freeshell.de>
2025-06-14 09:09:40 -06:00
E Shattow
58bcf9ab19 arch: use lowercase hex prefix style
Use consistent lowercase hex prefix style in arch/*

Signed-off-by: E Shattow <e@freeshell.de>
2025-06-14 09:09:40 -06:00
E Shattow
d1aacc9c78 lib: use lowercase hex prefix style
Use consistent lowercase hex prefix style in lib/*

Signed-off-by: E Shattow <e@freeshell.de>
2025-06-14 09:09:40 -06:00
E Shattow
c5824a1b3d tools: use lowercase hex prefix style
Use consistent lowercase hex prefix style in tools/*

Signed-off-by: E Shattow <e@freeshell.de>
2025-06-14 09:09:40 -06:00
E Shattow
449a556652 drivers: use lowercase hex prefix style
Use consistent lowercase hex prefix style in drivers/*

Does not change hex prefix case in allcaps uppercase style error messages

Signed-off-by: E Shattow <e@freeshell.de>
2025-06-14 09:09:39 -06:00
E Shattow
ba7634c6b6 board: use lowercase hex prefix style
Use consistent lowercase hex prefix style in board/*

Does not change auto-generated files in xilinx/zynq/*/ps7_init_gpl.c

Signed-off-by: E Shattow <e@freeshell.de>
2025-06-14 09:09:39 -06:00
E Shattow
9f208a3e70 configs: use lowercase hex prefix style
Use consistent lowercase hex prefix style in configs/*

Signed-off-by: E Shattow <e@freeshell.de>
2025-06-14 09:09:39 -06:00
Tom Rini
2556caa89c Merge patch series "drop volatile from global data"
Rasmus Villemoes <ravi@prevas.dk> says:

There's really no reason for the gd pointer to have the volatile
qualifier.

In fact, I claim that it's completely unnecessary and just pessimizes
code generation and forces ugly casts in lots of places. For example,
see the casts in drivers/core/tag.c where elements are added to
gd->dm_taglist, or a helper such as cyclic_get_list() that should not
be needed.

Also, it is what ends up standing in the way of an otherwise
innocent code cleanup of list.h:
https://lore.kernel.org/u-boot/20250522165656.GB2179216@bill-the-cat/

Note that riscv, x86 as well as arm64 with LTO enabled has not had
this volatile qualifier, so it's unlikely there's any generic code
that depends on it.

Link: https://lore.kernel.org/r/20250604195612.2312979-1-ravi@prevas.dk
2025-06-13 16:57:34 -06:00
Rasmus Villemoes
ae86cd8c59 riscv: remove volatile from set_gd prototype
It's slightly ironic that riscv at very first had the gd pointer
volatile qualified [6020faf62c ("riscv: nx25: include: Add header
files to support RISC-V")], removed that back in 2018
[40717eb849 ("riscv: checkpatch: Fix use of volatile")], and then in
2020 this helper was added [6b9966e1aa ("riscv: define function
set_gd()")] which needlessly had volatile in the prototype.

Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
2025-06-13 16:57:15 -06:00
Rasmus Villemoes
ce55643546 arm: remove volatile from set_gd prototype
The global gd pointer is no longer volatile-qualified. Callers of this
helper function have been updated to no longer use volatile-qualifed
temporary variables, so update the prototype accordingly.

Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
2025-06-13 16:57:15 -06:00
Rasmus Villemoes
abe705be47 lib/trace: drop volatile qualifier from "save gd" variables
The global gd pointer is no longer volatile-qualified, so drop that
qualifier from these bookkeeping variables.

Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
2025-06-13 16:57:15 -06:00
Rasmus Villemoes
83b040983c efi: drop volatile qualifier from "save gd" variables
The global gd pointer is no longer volatile-qualified, so drop that
qualifier from these bookkeeping variables.

Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2025-06-13 16:57:15 -06:00
Rasmus Villemoes
01869368c0 arm: imx: remove unnecessary volatile qualifiers from "save gd" variables
Now that the global gd pointer is no longer volatile-qualified,
there's no reason for the temporary variables used for
saving/restoring it to have that qualifier.

Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
Tested-by: Anshul Dalal <anshuld@ti.com>
2025-06-13 16:57:15 -06:00
Rasmus Villemoes
30b97f58f2 arc: drop volatile qualifier from gd pointer
Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
2025-06-13 16:57:15 -06:00
Rasmus Villemoes
a6f3d70a6b m68k: drop pointless #if 0 block
The way DECLARE_GLOBAL_DATA_PTR is used, the stuff under #if 0 can
never compile as you cannot have a non-constant initializer at global
scope (and one would get linker errors as well because the 'gd' symbol
would be defined in multiple TUs).

Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
Acked-by: Angelo Dureghello <angelo@kernel-space.org>
2025-06-13 16:57:15 -06:00
Rasmus Villemoes
e66d7fc089 m68k: drop volatile qualifier from gd pointer
Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
2025-06-13 16:57:15 -06:00
Rasmus Villemoes
fe0fa2bb66 microblaze: drop volatile qualifier from gd pointer
Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
2025-06-13 16:57:14 -06:00
Rasmus Villemoes
344c7e091c mips: drop volatile qualifier from gd pointer
Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
2025-06-13 16:57:14 -06:00
Rasmus Villemoes
aa53d9bb7d powerpc: drop volatile qualifier from gd pointer
Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
2025-06-13 16:57:14 -06:00
Rasmus Villemoes
45fa0014ba arm: drop volatile qualifier from gd pointer
There's a bunch of other places where this qualifier should be
dropped, e.g. in the set_gd() prototype and for various variables used
for stashing the value in the mach-imx/ directory and elsewhere. But
that will be done in follow-up patches.

Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
Tested-by: Anshul Dalal <anshuld@ti.com>
2025-06-13 16:57:14 -06:00
Simon Glass
f73450918d spl: Rename jump_to_image_no_args()
This function is currently a misnomer at times as we have cases where it
passes arguments to the image. In preparation for making that be a more
common case rename this function to jump_to_image(...). In order to do
this, rename jump_to_image in board_init_r(...) to jumper so that we do
not have a conflict.

Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Reword the commit message, adding missing cases of
        jump_to_image_no_args()]
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-06-13 13:22:53 -06:00
Simon Glass
a6e4fdfd77 x86: Move Intel GNVS file into the common include directory
Move this so we can include it from sandbox, needed since it is in a
bloblist and must have a check.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-06-13 13:10:33 -06:00
Tom Rini
7660feeedc Merge patch series "ti: Add support for eCAP PWM and LCD pin mux"
Sukrut Bellary <sbellary@baylibre.com> says:

This patch series adds the support for

1. In am33xx SoC[1], enhanced capture (eCAP) supports auxiliary PWM (APWM).
This series adds the PWM driver support for the APWM feature for eCAP on
AM33xx. AM335X_ECAP0_IN_PWM0_OUT is used to enable the backlight.

2. Fix build warning in ti-ehrpwm driver in dev_deb().

3. Enable eCAP0 PWM and LCD pin muxing to support splash screen on
AM335x EVM[2].

[1] AM335x TRM - https://www.ti.com/lit/ug/spruh73q/spruh73q.pdf
[2] AM335x EVM - https://www.ti.com/tool/TMDXEVM3358

per discussion on the earlier patch series,
https://lore.kernel.org/all/20250319202516.3300444-1-sbellary@baylibre.com/
dropping the device tree changes in this series due to OF_UPSTREAM
conflict.
As we are dropping the DT patch, started with the new series instead of
V2.

This series doesn't contain defconfig changes since we don't want to
enable LCD, splash screen and PWM support by default.
Enabling splash screen and PWM support in defconfig causes u-boot crash
on AM335x based beaglebone black. This will be handled in a separate
patch.

Link: https://lore.kernel.org/r/20250530212232.1686613-1-sbellary@baylibre.com
2025-06-12 16:27:02 -06:00
Sukrut Bellary
04df37a095 board: ti: am335x: Enable eCAP0 PWM and LCD pin muxing
On AM335x EVM[1],
1. pin AM335X_ECAP0_IN_PWM0_OUT is used to enable the
backlight. ECAP0 can be configured in single channel PWM mode.
If CONFIG_PWM_TI_ECAP is enabled, perform eCAP0 pin muxing.

2. Pins LCD_DATA0 - LCD_DATA15, gpmc_ad8 - gpmc_ad15 and
lcd_vsync, lcd_sync, lcd_ac_bias_en, lcd_pclk are used for driving LCD.
If CONFIG_AM335X_LCD is enabled, perform the LCD pin muxing.

This is required to enable splash screen support on AM335x EVM.
[1] AM335x EVM - https://www.ti.com/tool/TMDXEVM3358

Signed-off-by: Sukrut Bellary <sbellary@baylibre.com>
2025-06-12 16:26:56 -06:00
Sukrut Bellary
d0bcbf782f pwm: ti: am33xx: Fix build warnings in dev_dbg()
If CONFIG_PWM_TI_EHRPWM is enabled, it throws the build warning in
dev_dbg() due to incorrect format specifier as,

"warning: format ‘%lx’ expects argument of type ‘long unsigned int’, but
argument 4 has type ‘fdt_addr_t’ {aka ‘unsigned int’}".

Fix this with the correct format specifier.

Signed-off-by: Sukrut Bellary <sbellary@baylibre.com>
2025-06-12 16:26:56 -06:00
Sukrut Bellary
1bf82082b9 pwm: ti: am33xx: Enable Auxiliary PWM using eCAP
In am33xx SoC[1], enhanced capture (eCAP) supports auxiliary PWM (APWM).
This series adds the PWM driver support for the APWM feature for eCAP on
AM33xx.

eCAP HW also supports the capture mode. Currently, this driver only
supports APWM.

This is based on the Linux kernel driver -> drivers/pwm/pwm-tiecap.c
Version: v6.12

Tested on AM335x EVM[2].

[1] AM335x TRM - https://www.ti.com/lit/ug/spruh73q/spruh73q.pdf
[2] AM335x EVM - https://www.ti.com/tool/TMDXEVM3358

Signed-off-by: Sukrut Bellary <sbellary@baylibre.com>
2025-06-12 16:26:56 -06:00
Yao Zi
548d997229 ram: Move Kconfig options into their own menu entry
RAM drivers using Device Model currently lack of their own Kconfig menu
entry, which makes Kconfig put all options of the class in the top-level
menu of device drivers. These options are also incorrectly grouped with
pinctrl options in the generated .config, which is hard to read. Let's
create a menu entry for these drivers.

Fixes: 6c51df6859 ("dm: Add support for RAM drivers")
Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
2025-06-12 16:14:33 -06:00
Aristo Chen
0805e46486 bootstage: Fix typo
Fix typo from heder to header

Signed-off-by: Aristo Chen <aristo.chen@canonical.com>
2025-06-12 16:14:33 -06:00
Richard Weinberger
9fe2e4b464 fdt: Make sure there is no stale initrd left
Although if we don't setup an initrd, there could be a stale initrd
setting from the previous boot firmware in the live device tree. So,
make sure there is no setting left if we don't want an initrd.

This can happen when booting on a Raspberry Pi. The boot firmware can
happily load an initrd before us and configuring the addresses in the
live device tree we get handed over.

Especially the setting `auto_initramfs` in config.txt is dangerous.
When enabled (default), the firmware tries to be smart and looks for
initramfs files.

Signed-off-by: Richard Weinberger <richard@nod.at>
2025-06-12 16:13:51 -06:00
Tony Dinh
53cc4332b3 ext4fs: Fix: Read outside partition error (take 2)
Use lbaint_t for blknr to avoid overflow in ext4fs_read_file().

Background:

blknr (block number) used in ext4fs_read_file() could be increased to a
very large value and causes a wrap around at 32 bit signed integer max,
thus becomes negative. This results in an out-of-normal range for sector
number (during the assignment delayed_start = blknr) where delayed_start
sector is typed uint64 lbaint_t. This causes the "Read outside partition"
error.

Looks like we also have this overflown problem in ext4_write.c that needs
to be addressed.

This patch was tested on the Synology DS116 (Armada 385) board, and a
4TB Seagate HDD.

Signed-off-by: Tony Dinh <mibodhi@gmail.com>
2025-06-12 13:22:26 -06:00
Bryan Brattlof
52c0290526 binman: add atf-bl1 to etypes
Some SoCs require a Trusted Firmware-A (TF-A) AP Trusted ROM (BL1) to
initialize the SoC before U-Boot can run properly. Add an atf-bl1 etype
so we can properly package BL1 into a final binary

Signed-off-by: Bryan Brattlof <bb@ti.com>
Acked-by: Simon Glass <sjg@chromium.org>
2025-06-12 13:22:23 -06:00
Emanuele Ghidoli
79ae5510a2 arm: mach-k3: j784s4: Call do_board_detect() before DDR probing
Call do_board_detect() hook before the K3 DDRSS driver gets probed.
It will allow boards to adjust DDR timings in do_board_detect().

Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
2025-06-12 13:19:59 -06:00
Tom Rini
d142036b4c Merge patch series "Update the kbuild system to 5.1"
Ilias Apalodimas <ilias.apalodimas@linaro.org> says:

Another series backporting and merging patches from Linux 5.1 kbuild.
There is still a gap that I plan to update after this series gets
merged [0]

[0] 5da099cef0

Link: https://lore.kernel.org/r/20250611202449.2317279-1-ilias.apalodimas@linaro.org
2025-06-11 16:22:53 -06:00
Ilias Apalodimas
070b81458a kbuild: fix single target build for external module
Backported from kernel
commit e07db28eea38 ("kbuild: fix single target build for external module")

It's worth noting that crmodverdir is empty for U-Boot.
Just backport it to make diffing easier

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-06-11 16:21:36 -06:00
Ilias Apalodimas
45acf56e59 kbuild: make 'archprepare' depend on 'scripts'
Backported from kernel
commit 059bc9fc375e ("kbuild: make 'archprepare' depend on 'scripts'")

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-06-11 16:21:36 -06:00
Ilias Apalodimas
4a247d1376 kbuild: mark prepare0 as PHONY to fix external module build
Backported from kernel
commit e00d88804814 ("kbuild: mark prepare0 as PHONY to fix external module build")

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-06-11 16:21:36 -06:00
Ilias Apalodimas
27529f1cb0 kbuild: skip parsing pre sub-make code for recursion
Backported from kernel
commit 221cc2d27ddc ("kbuild: skip parsing pre sub-make code for recursion")

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-06-11 16:21:36 -06:00
Ilias Apalodimas
d1b6489ef1 kbuild: do not overwrite .gitignore in output directory
Backported from kernel
commit 156e7cbb3ef5 ("kbuild: do not overwrite .gitignore in output directory")

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-06-11 16:21:36 -06:00
Ilias Apalodimas
057a53b570 gcc-9: silence 'address-of-packed-member' warning
Backported from kernel
commit 6f303d60534c ("gcc-9: silence 'address-of-packed-member' warning")

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-06-11 16:21:36 -06:00
Ilias Apalodimas
931f04a85a kbuild: remove meaningless prepare2 target
Backported from kernel
commit 4f1c1008e786 ("kbuild: remove meaningless prepare2 target")

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-06-11 16:21:36 -06:00
Ilias Apalodimas
156fdc57f7 kbuild: gitignore output directory
Backported from kernel
commit 3a51ff344204 ("kbuild: gitignore output directory"

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-06-11 16:21:36 -06:00
Ilias Apalodimas
c4a52fbb67 kbuild: use -Werror=implicit-... instead of -Werror-implicit-...
Backported from kernel
commit b89f25ea7892 ("kbuild: use -Werror=implicit-... instead of -Werror-implicit-..."

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-06-11 16:21:36 -06:00
Ilias Apalodimas
3991f85e4c kbuild: clang: choose GCC_TOOLCHAIN_DIR not on LD
Backported from kernel
commit ad15006cc784 ("kbuild: clang: choose GCC_TOOLCHAIN_DIR not on LD")

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-06-11 16:21:36 -06:00
Ilias Apalodimas
a76fb6981f kbuild: use assignment instead of define ... endef for filechk_* rules
Backported from kernel
commit ba97df45581f ("kbuild: use assignment instead of define ... endef for filechk_* rules")

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-06-11 16:21:36 -06:00
Ilias Apalodimas
0ebda5f1f0 kbuild: add -Werror=implicit-int flag unconditionally
Backported from kernel
commit 61a0902a06d6a ("kbuild: add -Werror=implicit-int flag unconditionally")

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-06-11 16:21:36 -06:00
Ilias Apalodimas
7e81e690d7 kbuild: add -fno-PIE flag unconditionally
Backport from kernel
commit 42a92bccd213 ("kbuild: add -fno-PIE flag unconditionally")

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-06-11 16:21:36 -06:00
Tom Rini
ae297ca722 Merge patch series "dm: core: use {s,u}32 instead of int for dev_read_{s,u}32_default"
Quentin Schulz <foss+uboot@0leil.net> says:

Out of all the dev_read_*_default functions, only two do not properly
use the type as argument and return type: dev_read_u32_default and
dev_read_s32_default. They both use int instead of u32/s32.

Considering that it's generally not guaranteed that an int is 4 bytes
but also for consistency sake, let's have them use the expected type.

Note that I have not tested this, just stumbled upon that inconsistency
by chance.

Link: https://lore.kernel.org/r/20250528-dev_read_x32_default-v1-0-6ab1734dd7a2@cherry.de
2025-06-11 13:31:45 -06:00
Quentin Schulz
ad03050e26 dm: core: use s32 instead of int for dev_read_s32_default
dev_read_s32_default is for getting an s32 from a Device Tree property
and allows to take a default value if that property is missing.

Considering it calls ofnode_read_u32_default which takes a u32 and
returns a u32, it should do the same instead of using an int, especially
considering that int size is typically architecture-specific, as opposed
to s32/u32.

s32 and u32 being the same size, dev_read_s32* functions calling
ofnode_read_u32_default shouldn't be an issue (at the type level at
least) as the information will be stored appropriately in 4B regardless
of the sign.

This incidentally matches all other dev_read_*_default functions.

Fixes: a1b17e4f4c ("dm: core: Add a function to read into a unsigned int")
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2025-06-11 13:31:35 -06:00
Quentin Schulz
b4b66e2f29 dm: core: use u32 instead of int for dev_read_u32_default
dev_read_u32_default is for getting a u32 from a Device Tree property
and allows to take a default value if that property is missing.

Considering it calls ofnode_read_u32_default which takes a u32 and
returns a u32, it should do the same instead of using an int, especially
considering that int size is typically architecture-specific, as opposed
to u32.

This incidentally matches all other dev_read_*_default functions (except
dev_read_s32_default which will be tackled in the next commit).

Fixes: 47a0fd3bad ("dm: core: Implement live tree 'read' functions")
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2025-06-11 13:31:35 -06:00
Tom Rini
4b5cb57611 Merge tag 'u-boot-stm32-20250611' of https://source.denx.de/u-boot/custodians/u-boot-stm into next
CI: https://source.denx.de/u-boot/custodians/u-boot-stm/-/pipelines/26607

- Add clock and reset drivers support for STM32MP25
- Add STM32H747-Discovery board support
- Add tamp_nvram driver
- Add SPL support and clock tree init to STM32MP13 RCC driver
- Add STM32MP13xx ram support
- Add support for STM32 Image V2.0 for STM32MP13xx
- Fix SYSRAM size on STM32MP13xx
- Fix DBGMCU macro on STM32MP13xx
- Auto-detect ROM API table on STM32MP15xx
2025-06-11 12:00:36 -06:00
Dario Binacchi
7ab0ee3a59 board: stm32: add stm32h747-discovery board support
The board includes an STM32H747XI SoC with the following resources:
 - 2 Mbytes Flash
 - 1 Mbyte SRAM
 - LCD-TFT controller
 - MIPI-DSI interface
 - FD-CAN
 - USB 2.0 high-speed/full-speed
 - Ethernet MAC
 - camera interface

Detailed information can be found at:
https://www.st.com/en/evaluation-tools/stm32h747i-disco.html

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2025-06-11 12:00:36 -06:00
Dario Binacchi
366f0bfe4f ARM: dts: stm32: add stm32h747i-disco-u-boot DTS file
Add stm32h747i-disco-u-boot DTS file with FMC SDRAM node and its
pinmux settings.

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2025-06-11 12:00:36 -06:00
Dario Binacchi
cb348ba58f ARM: dts: stm32: support STM32h747i-disco board
The board includes an STM32H747XI SoC with the following resources:
 - 2 Mbytes Flash
 - 1 Mbyte SRAM
 - LCD-TFT controller
 - MIPI-DSI interface
 - FD-CAN
 - USB 2.0 high-speed/full-speed
 - Ethernet MAC
 - camera interface

Detailed information can be found at:
https://www.st.com/en/evaluation-tools/stm32h747i-disco.html

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Link: https://lore.kernel.org/r/20250427074404.3278732-9-dario.binacchi@amarulasolutions.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>

[ upstream commit: 49ba8fc6eab63165639ffbb9f976222d39739cab ]

(cherry picked from commit 19c508dc3d584dc81c0cc6a05576f436022db5b6)
2025-06-11 12:00:32 -06:00
Dario Binacchi
3a310f59c3 ARM: dts: stm32: add an extra pin map for USART1 on stm32h743
Add an additional pin map configuration for using the USART1 controller
on the stm32h743 MCU.

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Link: https://lore.kernel.org/r/20250427074404.3278732-8-dario.binacchi@amarulasolutions.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>

[ upstream commit: 8e71dfe46a4a1e9505b1a327470f879b63388968 ]

(cherry picked from commit 9d5ec2c9c5d5131e701447c5c32aaf6c688c6e01)
2025-06-11 12:00:19 -06:00
Dario Binacchi
1addd0e429 ARM: dts: stm32: add pin map for UART8 controller on stm32h743
Add a pin map configuration for using the UART8 controller on the
stm32h743 MCU.

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Link: https://lore.kernel.org/r/20250427074404.3278732-7-dario.binacchi@amarulasolutions.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>

[ upstream commit: 47d16ab94b8e5e85aedba3cd22cfdf3877bf1dfb ]

(cherry picked from commit 59621a6472cd6eeb748ed6d6202a21d0f3cc5a83)
2025-06-11 12:00:15 -06:00
Dario Binacchi
d4fe7cd8ca ARM: dts: stm32: add uart8 node for stm32h743 MCU
Add support for UART8 by applying the settings specified in the
reference manual RM0433.

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Link: https://lore.kernel.org/r/20250427074404.3278732-6-dario.binacchi@amarulasolutions.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>

[ upstream commit: 07aa43adae2363c3734055aeba0789536fa0f8f2 ]

(cherry picked from commit 8fe35c381c7c6db1b95c80be551afada1e9f28e0)
2025-06-11 12:00:10 -06:00
Dario Binacchi
e543e8b409 dt-bindings: clock: stm32h7: rename USART{7,8}_CK to UART{7,8}_CK
As stated in the reference manual RM0433, the STM32H743 MCU has
USART1/2/3/6, UART4/5/7/8, and LPUART1. The patches make all the clock
macros for the serial ports consistent with the documentation.

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250427074404.3278732-5-dario.binacchi@amarulasolutions.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>

[ upstream commit: ecab3c40fa49a2073c4c916ebff9496a6b5db7bd ]

(cherry picked from commit aae9a01929183784bf3e2a8001aba408bd0dadf3)
2025-06-11 12:00:05 -06:00
Dario Binacchi
484f098b2f dt-bindings: arm: stm32: add compatible for stm32h747i-disco board
The board includes an STM32H747XI SoC with the following resources:
 - 2 Mbytes Flash
 - 1 MByte SRAM
 - LCD-TFT controller
 - MIPI-DSI interface
 - FD-CAN
 - USB 2.0 high-speed/full-speed
 - Ethernet MAC
 - camera interface

Detailed information can be found at:
https://www.st.com/en/evaluation-tools/stm32h747i-disco.html

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250427074404.3278732-3-dario.binacchi@amarulasolutions.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>

[ upstream commit: 815d49f61ea049075482161f897aa13e1ae30cbb ]

(cherry picked from commit 06f64674b332c7db4ac56a4dccb0e960d25bea24)
2025-06-11 12:00:01 -06:00
Dario Binacchi
5d15b43052 ARM: dts: stm32h7-pinctrl: add _a suffix to u[s]art_pins phandles
Allow expanding possible configurations for the same peripheral,
consistent with the scheme adopted in Linux.

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Link: https://lore.kernel.org/r/20250427074404.3278732-2-dario.binacchi@amarulasolutions.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>

[ upstream commit: 6a36dca4375fce51b627f5a985a79fc8b8bd7f55 ]

(cherry picked from commit 9a72c83f2e670087ae2d6dc54d2926f16c6762d0)
2025-06-11 11:59:57 -06:00
Simeon Marijon
6b9ecdfe9a stm32mp: Add tamp_nvram driver
TAMP backup registers will be exposed as nvmem cells.

Each registers ([0..127] for STM32MP2, [0..31] for STM32MP1) could be
exposed as nvmem cells under the nvram node in device tree

Signed-off-by: Simeon Marijon <simeon.marijon@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2025-06-11 09:42:56 +02:00
Marek Vasut
3f2eb09c22 tools: stm32image: Add support for STM32 Image V2.0
Add support for generating STM32 Image V2.0, which is used by STM32MP13xx.
The image header layout is similar to STM32MP15xx STM32 Image V1.0, but is
different enough to justify duplicate functions to generate the v2 image.
This code at least attempts to align the V1 and V2 image handling where
possible.

Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
2025-06-11 09:42:56 +02:00
Marek Vasut
447d1bd05a ram: stm32mp1: Add STM32MP13xx support
Add support for configuring DRAM controller on STM32MP13xx SoC.
The DRAM controller is basically identical to the DWC controller
on STM32MP15xx SoC, except the bus width is reduced from 32bit to
16bit and a few registers and bits are therefore not present.

Handle the difference by factoring these parts out. Use IS_ENABLE()
as much as possible to assure code which is not enabled on builds
for a single SoC gets compiled out. Handle the different offset of
RCC_DDRITFCR register and missing DDRC2 clock the same way.

Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
2025-06-11 09:42:56 +02:00
Marek Vasut
0298696b1e clk: stm32mp13: Add SPL support and clock tree init to STM32MP13 RCC driver
Add SPL support and clock tree init to STM32MP13 RCC driver. This
consists of two parts, make SCMI into an optional dependency and
add clock tree initialization. The SCMI dependency is made optional
first by registering the few core clock provided by SCMI clock as
fixed clock, and second by letting the clock core parse out the
clock configuration from SoC registers. The clock initialization
code is derived from STM32MP15xx clock tree initialization code,
which is almost identical, except for the use of new PLL2000 for
PLL1 on STM32MP13xx .

Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
2025-06-11 09:42:56 +02:00
Marek Vasut
b2c50bd30b clk: stm32mp13: Fix typo in STM32MP13 RCC driver
Fix basic typo, missing t in security . No functional change .

Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2025-06-11 09:42:55 +02:00
Marek Vasut
ecd6fd02e1 ARM: stm32: Auto-detect ROM API table on STM32MP15xx
The ROM API table location is passed to the SPL by BootROM in register r0,
make use of this, store the content of r0 and later use it to access the
ROM API table to determine current boot device.

Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2025-06-11 09:42:55 +02:00
Marek Vasut
d4972d5b59 ARM: stm32: Fix DBGMCU macro on STM32MP13xx
The DBGMCU block is available at address 0x50081000 both on STM32MP13xx
and on STM32MP15xx . There is no reason to limit the DBGMCU macro being
set only on STM32MP15xx , remove the ifdeffery.

Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2025-06-11 09:42:55 +02:00
Marek Vasut
380d6f8c19 ARM: stm32: Fix SYSRAM size on STM32MP13xx
The STM32MP13xx has only 128 kiB of SYSRAM starting at address 0x2ffe0000 .
The STM32MP15xx has 256 kiB of SYSRAM starting at address 0x2ffc0000 . Make
sure both SoCs configure ARMV7_SECURE_BASE correctly . Define the SYSRAM
base in stm32.h to be consistent with the STM32MP15xx macro.

Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2025-06-11 09:42:55 +02:00
Marek Vasut
7df29a172a ARM: stm32: Drop unnecessary space
Drop a space after tab, no functional change.

Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2025-06-11 09:42:55 +02:00
Patrice Chotard
38aa59bb36 configs: stm32mp25: increase SYS_MALLOC_F_LEN to 0x60000
Due activation of SCMI, we need to increase SYS_MALLOC_F_LEN value
to avoid following message:

U-Boot 2025.04-01224-g75b77a2a6d31-dirty (Apr 25 2025 - 11:23:30 +0200)

alloc space exhausted ptr 400040 limit 400000
alloc space exhausted ptr 400020 limit 400000
alloc space exhausted ptr 400060 limit 400000
alloc space exhausted ptr 400060 limit 400000

Set SYS_MALLOC_F_LEN to 0x60000 to fix this issue.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2025-06-11 09:42:55 +02:00
Patrice Chotard
1cdb64ad3a configs: stm32mp13: increase SYS_MALLOC_F_LEN to 0x210000
Due SCMI update to protocol v2.0, we need to increase
SYS_MALLOC_F_LEN value to avoid following message:
alloc space exhausted ptr 200040 limit 200000

Set SYS_MALLOC_F_LEN to 0x210000 to fix this issue.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2025-06-11 09:42:55 +02:00
Patrice Chotard
fddf9886d2 ARM: dts: stm32: switch from fixed to scmi clocks for stm32mp257f-ev1
SCMI clocks are now available, switch from fixed to SCMI clocks.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2025-06-11 09:42:55 +02:00
Gabriel Fernandez
0994a627c2 reset: stm32mp25: add stm32mp25 reset driver
Implement STM32MP25 reset drivers using stm32-core-reset API.
This reset stm32-reset-core API and will be able to use DT binding
index started from 0.

This patch also moves legacy reset into stm32 directory reset.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2025-06-11 09:42:55 +02:00
Gabriel Fernandez
901e0d95df clk: stm32: fix clock counter
In RCC the ops of the CCF registered CLK device can be called directly,
this patch avoid recursive call of clk_ function done by CCF clock
framework which update the clock information, for example
clk_enable is called 2 times, clkp->enable_count is increased 2 times.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Lukasz Majewski <lukma@denx.de>
Cc: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2025-06-11 09:42:55 +02:00
Patrick Delaunay
51954665a7 phy: stm32-usbphyc: manage properly the clk identifier with CCF
Add private uclass data for "stm32-usbphyc-clk" as it is not done
by the driver model.

This clk struct is needed by CCF to save the unique id used to identify
each clock.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Lukasz Majewski <lukma@denx.de>
Cc: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2025-06-11 09:42:55 +02:00
Patrick Delaunay
aa7bdc1af5 clk: scmi: manage properly the clk identifier with CCF
Each clock identifier needs to be unique when CCF is activated,
and it is not respected today by SCMI clock driver.

This patch supports a unique clk id by using the uclass API
clk_get_id() / dev_clk_dm() and by activating by default
CONFIG_CLK_AUTO_ID with CCF which adds an offset to the SCMI
clock identifiers.

After this patch, the SCMI clock driver can coexist with other
clock provider without conflict, they can share internal identifier
[0..N] defined in their binding and the clock ID = 0
(reserved for dummy clock) is no more used.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Lukasz Majewski <lukma@denx.de>
Cc: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2025-06-11 09:42:55 +02:00
Patrick Delaunay
64b07829f7 clk: fixed_rate: configure clock ID with CONFIG_CLK_AUTO_ID
Update CLK ID to avoid 0 id, used for dummy clock with CCF
and to allow selection by clk_get_by_id, used to
get private data associated to the UCLASS_CLK device

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Lukasz Majewski <lukma@denx.de>
Cc: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2025-06-11 09:42:55 +02:00
Patrick Delaunay
56789994c4 sandbox: test: update for CONFIG_CLK_AUTO_ID support
Update the existing test dm_test_clk_ccf() with new CLK_ID macro.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Lukasz Majewski <lukma@denx.de>
Cc: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2025-06-11 09:42:55 +02:00
Patrick Delaunay
94e284a41d clk: sandbox: update driver for CONFIG_CLK_AUTO_ID support
Update the sandbox driver to allow support of the
CONFIG_CLK_AUTO_ID by using the new API clk_get_id()
to get the internal SANDBOX identifier.

With CONFIG_CLK_AUTO_ID, clk->id have the also seq identifier.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Lukasz Majewski <lukma@denx.de>
Cc: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2025-06-11 09:42:55 +02:00
Patrick Delaunay
0846bad0d0 clk: add CONFIG_CLK_AUTO_ID
Add a new config CONFIG_CLK_AUTO_ID to support a unique clk id
for all the clock providers, managed by clk uclass, when the clock
reference arg[0] is the same.

When the CONFIG is activated, the clock id is limited to the lower
CLK_ID_SZ = 24 bits in default clock xlate function
and the sequence number + 1 of the clk provider device is
added for the 8 higher bits.

We use sequence number + 1 to avoid the "dummy" clock id = 0,
used for invalid clock when CCF is activated.

When this config is activated, the new function clk_get_id()
should be used to get back the internal reference to clock
for the each clock provider.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Lukasz Majewski <lukma@denx.de>
Cc: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2025-06-11 09:42:55 +02:00
Gabriel Fernandez
49bc67b3fa clk: stm32mp25: implement clock check security function
Check clock security to avoid access at boot time.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Lukasz Majewski <lukma@denx.de>
Cc: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2025-06-11 09:42:55 +02:00
Gabriel Fernandez
fc6c5e703f clk: stm32mp25: Add clock driver support
Add clock driver support for STM32MP25 SoCs.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Signed-off-by: Valentin Caron <valentin.caron@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Lukasz Majewski <lukma@denx.de>
Cc: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2025-06-11 09:42:55 +02:00
Valentin Caron
ae7e0330ce clk: scmi: add compatibility with clock protocol 2.0
Since clock protocol 2.0, SCMI specification add an option field
"clock_enable_delay" to CLOCK_ATTRIBUTES command.

scmi_read_resp_from_smt() will return an error ("Buffer too small") as
the message length coming from the SCMI server is not the same as expected.

So implement a condition to SCMI clock protocol version to change the
length of the expected message.

Signed-off-by: Valentin Caron <valentin.caron@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Lukasz Majewski <lukma@denx.de>
Cc: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2025-06-11 09:42:55 +02:00
Tom Rini
9e50cf80d0 Merge tag 'tpm-next-10062025' of https://source.denx.de/u-boot/custodians/u-boot-tpm into next
CI: https://source.denx.de/u-boot/custodians/u-boot-tpm/-/pipelines/26601

Updates from Simon cleaning up some tests, with the intention of being used
in sandbox and actual hardware.
2025-06-10 16:31:30 -06:00
Simon Glass
693b7a738d test: tpm: Skip failing tests on coral
These tests have been failing for some months. Disable them so that a CI
run can pass on coral. Further work will be needed to see how to make
them pass.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-06-10 19:35:58 +03:00
Simon Glass
343f74b4e6 tpm: Drop unwanted special cases for sandbox
These don't seem to be needed.

Add a few notes about what to do next. Also mention parallel tests in
at the top of thefile.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-06-10 19:35:58 +03:00
Simon Glass
edc4bfd2e3 tpm: Convert sandbox-focussed tests to C
Some of the Python tests are a pain because they don't reset the TPM
state before each test. Driver model tests do this, so convert the
tests to C.

This means that these tests won't run on real hardware, but we have
tests which do TPM init, so there is still enough coverage.

Rename and update the Python tpm_init test to use 'tpm autostart',
since this fully initializes the TPM and performs the self tests.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-06-10 19:35:26 +03:00
Simon Glass
1f144b6174 tpm: sandbox: Support self-test continue in emulator
Add support for the self-test continue command in the TPM v1.2 emulator,
to match the functionality in the TPM v2 emulator.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-06-10 19:30:00 +03:00
Tom Rini
59d00e20fc Merge tag 'v2025.07-rc4' into next
Prepare v2025.07-rc4
2025-06-09 16:28:28 -06:00
Tom Rini
865130b730 Merge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-riscv into next
CI: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/26569

- SoC: add SPL support for licheepi4a
- RISC-V: raise SPL_SYS_MALLOC_SIZE to 8 MiB
2025-06-09 08:54:57 -06:00
Yao Zi
c89f2b1078 MAINTAINERS: riscv: cpu: th1520: Assign myself as maintainer
Assign myself to develop U-Boot port of T-Head TH1520 SoC, and help
maintain related code and review patches.

Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-06-09 10:44:14 +08:00
Yao Zi
cea164cdd0 doc: thead: lpi4a: Update for S-Mode proper U-Boot support
Proper U-Boot for Lichee Pi 4A now runs in S mode instead of M mode,
which means the extra firmware, OpenSBI, must be built and integrated
in the image, and the vendor U-Boot cannot chainload the result image
anymore as it runs in M mode.

Remove redundant information about chainloading and update build steps
to mention OpenSBI firmware.

Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-06-09 10:44:06 +08:00
Yao Zi
8ea114209a board: thead: licheepi4a: Run proper U-Boot in S-Mode
RISC-V software usually expects S mode when leaving the firmware, e.g.
UEFI applications could only run in S mode. Let's convert proper U-Boot
of Lichee Pi 4A port to run in S mode.

Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-06-09 10:44:06 +08:00
Yao Zi
6033a66f89 riscv: dts: th1520: Prepare binman configuration for loading OpenSBI
Add an OpenSBI entry to the FIT image. As it expects an FDT to be
passed, corresponding FDT entry is generated with of-list as well.

As SPL now passes a full FDT for following stages, proper U-Boot image
is packed into u-boot-with-spl.bin without a devicetree copy included.

Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-06-09 10:44:06 +08:00
Yao Zi
85cfabe895 riscv: cpu: th1520: Support cache enabling/disabling in M mode only
These operations rely on a customized M-mode CSR, MHCR, which isn't
available when running in S mode.

Let's fallback to the generic weak stub when running in S mode to avoid
illegal accesses.

Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-06-09 10:44:06 +08:00
Yao Zi
0463545678 riscv: cpu: th1520: Build spl.c for SPL only
Symbols in spl.c only function correctly in SPL stage. Build the file
for SPL only to avoid weak symbols in proper U-Boot being unexpectedly
reloaded.

Fixes: 5fe9ced355 ("riscv: cpu: Add TH1520 CPU support")
Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-06-09 10:44:06 +08:00
Heinrich Schuchardt
8b410cab51 configs: raise SPL_SYS_MALLOC_SIZE to 8 MiB on RISC-V
On several RISC-V boards we have seen that 1 MiB is a insufficient value
for CONFIG_SPL_SYS_MALLOC_SIZE.

For instance qemu-riscv32_spl_defconfig fails booting because u-boot.itb
exceeds 1 MiB.

8 MiB is a reasonable value that allows adding FPGA blobs or splash images
to main U-boot.

Reported-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-06-09 10:43:57 +08:00
Tom Rini
e96b6c0c18 Merge patch series "Remove as much arch/arm/dts/*.h as possible"
Tom Rini <trini@konsulko.com> says:

Taking inspiration from Heiko's patch[1] this series goes and cleans up
all of the arch/arm/dts/*.h files that can be easily removed. The big
challenge I ran in to here was that for some platforms that aren't using
OF_UPSTREAM were didn't have a sufficiently deep search path to find
files there rather than arch/arm/dts. This also showed that only ARM had
local header files to deal with.

[1]: https://lore.kernel.org/u-boot/20250528090536.765499-1-heiko.thiery@gmail.com/

Link: https://lore.kernel.org/r/20250528233050.3820722-1-trini@konsulko.com
2025-06-06 13:54:42 -06:00
Tom Rini
e87b5ed9d9 nxp: Remove local arch/arm/dts/imx8mm-pinfunc.h
We have this file in both arch/arm/dts and
dts/upstream/src/arm64/freescale. This file is identical save for
changes which have been made upstream.  Remove our local copy to get in
sync with upstream now.

Acked-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Peter Robinson <pbrobinson@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-06-06 13:54:42 -06:00
Tom Rini
872f69257a atmel: Remove local arch/arm/dts/{sama5d2, sama7g5}-pinfunc.h
We have these files in both arch/arm/dts and
dts/upstream/src/arm/microchip. These files are identical save for
changes which have been made upstream.  Remove our local copy to get in
sync with upstream now.

Reviewed-by: Peter Robinson <pbrobinson@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-06-06 13:54:42 -06:00
Tom Rini
fefc9329ea arch/arm/dts: Remove strict subset header
As part of moving to using OF_UPSTREAM and so the upstream DT related
header files we have a header that is under the arch/arm/dts directory
and differ in being a strict subset of what is found upstream. We can
remove this now to prevent future conflicts.

Reviewed-by: Peter Robinson <pbrobinson@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-06-06 13:54:42 -06:00
Tom Rini
96d95e6a53 arch/arm/dts: Remove functionally identical headers
As part of moving to using OF_UPSTREAM and so the upstream DT related
header files we have a number of these headers that are under the
arch/arm/dts directory and differ only in combinations of spacing
changes and/or switching to SPDX license tags. We can remove these now
to prevent future conflicts.

Reviewed-by: Peter Robinson <pbrobinson@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-06-06 13:54:42 -06:00
Tom Rini
7e97877440 arch/arm/dts: Remove identical headers
As part of moving to using OF_UPSTREAM and so the upstream DT related
header files we have a number of these headers that are under the
arch/arm/dts directory and are currently identical to the versions in
dts/upstream.  We can remove these now to prevent future conflicts.

Reviewed-by: Peter Robinson <pbrobinson@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-06-06 13:54:41 -06:00
Tom Rini
96e8ce71e9 arch/arm/dts: Remove unused header
As part of moving to using OF_UPSTREAM and so the upstream DT related
header files we have a header that is under the arch/arm/dts directory
and now unused. We can remove this now to prevent any future conflicts.

Reviewed-by: Peter Robinson <pbrobinson@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-06-06 13:54:41 -06:00
Tom Rini
c9b452acd9 scripts/Makefile.lib: Rework upstream_dtsi_include to get subdirectories
A problem with the logic in upstream_dtsi_include currently is that it
does not list directories such as dts/upstream/src/arm/nxp/imx and so
will not findi "imx6ul-pinfunc.h" for example as it is normally and
correctly included without vendor sub-paths. Expand the current wildcard
glob to catch these directories too.

Reviewed-by: Peter Robinson <pbrobinson@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-06-06 13:54:10 -06:00
Tom Rini
de39765316 include/dt-bindings: Remove headers we can safely upgrade
As part of moving to using OF_UPSTREAM and so the upstream dt-bindings
headers we have a number of these headers that are in our include
directory and while they are not a strict subset of the upstream version
of the headers, all platforms build with the new headers as well. We can
remove the copies under include/dt-bindings now to prevent future
conflicts.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-06-06 13:54:00 -06:00
Tom Rini
c8612ed98e include/dt-bindings/reset: Remove local version of bcm6318-reset.h
Aside from SPDX tags, the only difference between our version of this
header and upstream is that BCM6318_RST_HOSTMIPS was defined to 11 (the
same as BCM6318_RST_PHYMIPS) and is now defined to 12.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-06-06 10:50:17 -06:00
Tom Rini
d8ff4a0652 include/dt-bindings: Remove strict subset headers
As part of moving to using OF_UPSTREAM and so the upstream dt-bindings
headers we have a number of these headers that are in our include
directory and differ in being a strict subset of what is found upstream.
We can safely remove the copies under include/dt-bindings now to prevent
future conflicts.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-06-06 10:50:05 -06:00
Tom Rini
9006969b6d include/dt-bindings: Remove functionally identical headers
As part of moving to using OF_UPSTREAM and so the upstream dt-bindings
headers we have a number of these headers that are in our include
directory and differ only in combinations of spacing changes and/or
switching to SPDX license tags. We can safely remove the copies under
include/dt-bindings now to prevent future conflicts.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-06-06 10:50:05 -06:00
Tom Rini
f335f5265b include/dt-bindings: Remove identical headers
As part of moving to using OF_UPSTREAM and so the upstream dt-bindings
headers we have a number of these headers that are in our include
directory and are currently identical to the versions in dts/upstream.
We can remove these now to prevent future conflicts.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-06-06 10:49:56 -06:00
Tom Rini
ceeda322e7 include/dt-bindings: Remove unused headers
As part of moving to using OF_UPSTREAM and so the upstream dt-bindings
headers we have a number of these headers that are in our include
directory and not referenced by any code outside of dts/upstream. We can
remove these now to prevent future conflicts.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-06-06 10:49:56 -06:00
Heiko Thiery
a822b95da4 arm: dts: remove k3-serdes.h
This file is a duplicate and also comes with the sync of the linux
mainline dts files. By removing this the one from the dts folder should
be taken that is more up-to-date.

Signed-off-by: Heiko Thiery <heiko.thiery@gmail.com>
2025-06-05 16:57:35 -06:00
Raymond Mao
85683bd195 armv8: fix Clang warning on writing 32-bit variable to a 64-bit register
Clang is stricter than GCC when it comes to inline assembly and expects the
register to be written with explicitly same type of variable.

Fixes: c0e1775a86 ("armv8: Add arch-specific sysinfo platform driver")
Signed-off-by: Raymond Mao <raymond.mao@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-06-05 16:57:35 -06:00
Tom Rini
ef0eec3fa9 scripts/setlocalversion: sync with linux v6.15
The changes upstream since the last sync at commit 5c02350fa0
("scripts/setlocalversion: sync with linux v6.9") are

e2ff1219a554 setlocalversion: add -e option
523f3dbc187a setlocalversion: work around "git describe" performance

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-06-05 16:57:35 -06:00
Christian Marangi
8c986521c3 cmd: bootmenu: permit to select bootmenu entry with a shortcut
Permit to select a bootmenu entry with a key shortcut. This is
especially useful in production or testing scenario to automate flashing
procedure or testing procedure.

The boot entry are changed to append the shortcut key to it.

Example:
      1. Run default boot command.
      2. Boot system via TFTP.
      3. Boot production system from NAND.
      4. Boot recovery system from NAND.
      5. Load production system via TFTP then write to NAND.
      6. Load recovery system via TFTP then write to NAND.
      7. Load BL31+U-Boot FIP via TFTP then write to NAND.
      8. Load BL2 preloader via TFTP then write to NAND.
      9. Reboot.
      a. Reset all settings to factory defaults.
      0. Exit

0 is always reserved for Exit to console.
On pressing the keyboard key 2, the bootmenu entry 2 is selected and
executed.

Up to 34 key shortcut (0 excluded as reserved) are supported from 1-9
and a-z.
If a shortcut key not present in the bootmenu list is pressed, it is
simply ignored and eventually the autoboot is interrupted.

Capital A-Z are converted to lower a-z and the related option is
selected.

Suggested-by: Weijie Gao <weijie.gao@mediatek.com>
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Tested-by: Petr Štetiar <ynezz@true.cz>
2025-06-05 16:57:35 -06:00
Tom Rini
615997ec21 Merge patch series "Add baudrate accuracy compensation for MediaTek UART driver"
Weijie Gao <weijie.gao@mediatek.com> says:

This patch series adds baudrate accuracy compensation for MediaTek UART
driver in high-speed mode 3.

Link: https://lore.kernel.org/r/cover.1747991898.git.weijie.gao@mediatek.com
2025-06-05 16:57:35 -06:00
Weijie Gao
6952209ef2 serial: mediatek: enable baudrate accuracy compensation
The high-speed UART from MediaTek supports baudrate accuracy
compensation when using high-speed mode 3.

This is done by calculating the first digit of the fraction part of
sample count value. The fraction value will be then used as the
reference to insert 0 to 10 sample cycle(s) to one frame (assume
that frame format is 8n1, i.e. 10 bits per frame).

The fracdiv_[l/m] registers are used to determine whether a bit in one frame
should be inserted with one sample cycle.

With typical 40MHz source clock, the actual baudrates with/without
accuracy compensation are:

Ideal    w/o compensation w/ compensation
======== ================ ===============
9600     9603             9600
115200   114942           115207
921600   930232           921659
3000000  3076923          3007519

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2025-06-05 14:30:35 -06:00
Weijie Gao
6e15d3f91a serial: mediatek: fix register names and offsets
Fix UART register names and offsets according to the programming
guide to allow implementing some enhanced features.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2025-06-05 14:30:35 -06:00
Tom Rini
bed3b33e73 toradex: verdin-am62p: Add missing <linux/sizes.h>
This file uses SZ_1G but does not directly include <linux/sizes.h>, add
it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-06-04 07:34:21 -06:00
Parth Pancholi
b8c43968b8 board: toradex: add verdin am62p support
This adds initial support for the Toradex Verdin AM62P module.

The module consists of an TI AM62P family SoC, a TPS65219 PMIC, a
Gigabit Ethernet PHY, up to 8GB of LPDDR4 RAM, an eMMC, a TLA2024 ADC,
an I2C EEPROM, an RX8130 RTC, plus an optional Bluetooth/Wi-Fi module.

These specific changes adds support for Toradex Verdin AM62P Quad 2GB WB
IT module.

Link: https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62p
Link: https://www.toradex.com/products/carrier-board/verdin-development-board-kit
Signed-off-by: Parth Pancholi <parth.pancholi@toradex.com>
Signed-off-by: Vitor Soares <vitor.soares@toradex.com>
2025-06-03 17:18:03 -06:00
Emanuele Ghidoli
422222f517 linux/sizes.h: sync from kernel
The kernel added new size definitions and substituted the
boilerplate/reference to the license with a SPDX identifier.

Drop a local SZ_8G definition in MediaTek MT7988 SoC board file.

Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
2025-06-03 17:18:03 -06:00
Vitor Soares
4c93407165 toradex: tdx-cfg-block: add new pid4 support
Add the new PID4 to the ConfigBlock handling:
 - 0098 Aquila iMX95 Hexa 16GB WB IT
 - 0099 Verdin AM62P Quad 2GB WB IT
 - 0201 SMARC iMX95 Hexa 8GB IT
 - 0202 SMARC iMX95 Hexa 4GB WB IT
 - 0203 SMARC iMX95 Hexa 4GB ET
 - 0204 SMARC iMX95 Hexa 2GB WB IT
 - 0205 SMARC iMX95 Hexa 2GB ET
 - 0206 SMARC iMX8M Plus Quad 4GB IT
 - 0207 SMARC iMX8M Plus Quad 2GB WB IT
 - 0208 SMARC iMX8M Plus Quad 2GB IT
 - 0209 SMARC iMX8M Plus Quadlite 1GB WB ET
 - 0210 SMARC iMX8M Plus Quadlite 1GB ET
 - 0211 Aquila AM69 Octa 32GB IT
 - 0212 Aquila AM69 Octa 16GB WB IT
 - 0213 Aquila AM69 Octa 16GB IT
 - 0214 Aquila AM69 Octa 8GB WB IT
 - 0215 Aquila AM69 Octa 8GB IT

Signed-off-by: Vitor Soares <vitor.soares@toradex.com>
2025-06-03 17:18:03 -06:00
Anis Chali
5451504256 pinctrl: gpio: sx150x: add Semtech SX150x I2C GPIO expander and pinctrl driver
implement a driver to use semtech pinctrl and
 gpio expander, this driver is adapted from a
 existent linux driver that is written by
 Gregory Bean <gbean@codeaurora.org>.

Signed-off-by: Anis Chali <chalianis1@gmail.com>
2025-06-03 17:18:03 -06:00
Anton Moryakov
a4fb99ce4e tools: fix handle leak in ifdtool.c
Prevent file descriptor leaks by properly closing 'fd' and 'new_fd'
when fstat() or write() operations fail.

- Added close(fd) before return in open_for_read() if fstat() fails.
- Added close(new_fd) before return in write_image() if write() fails.
- No close needed if open() fails (fd == -1 is invalid).

Signed-off-by: Anton Moryakov <ant.v.moryakov@gmail.com>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
2025-06-03 17:18:02 -06:00
Tom Rini
d786c6b69f Merge patch series "Audit include list for include/[a-m]*.h"
Tom Rini <trini@konsulko.com> says:

Hey all,

Related to my other series I've posted recently on cleaning up some
headers, this series here is the result of at least lightly auditing the
#includes used in include/[a-m]*.h. This ignores subdirectories, as at
least in part I think the top-level includes we've constructed are the
most likely places to have some extra transitive include paths. I'm sure
there's exceptions and I'll likely audit deeper once this first pass is
done. This only gets as far as "include/m*.h" because I didn't want this
to get too big. This also sets aside <miiphy.h> and <phy.h>. While
miiphy.h does not directly need <phy.h> there are *so* many users and I
think I had half of the tree just about not building when I first tried.
It might be worth further investigation, but it might just be OK as-is.

Link: https://lore.kernel.org/r/20250521230119.2084088-1-trini@konsulko.com
2025-06-02 17:43:56 -06:00
Tom Rini
824f8f52a1 global: Cleanup usage of "ETH_ALEN"
The value of "ETH_ALEN" is defined to 6 in <linux/if_ether.h>. This file
is included in <net.h>. In the places where we had ETH_ALEN but no
direct include of <net.h>, add <linux/if_ether.h>. In the places where
we had a custom name used, make use of ETH_ALEN instead.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-06-02 17:26:16 -06:00
Tom Rini
2266595bf8 include/mtd.h: Cleanup usage
There are only a few things found in <mtd.h> today. Go through and audit
the C files which include <mtd.h> and remove it when not required. Then,
add it to the files which had either missed it or had an indirect
inclusion of it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-06-02 17:26:16 -06:00
Tom Rini
2cf46de9b6 include/mmc.h: Audit include list
This file does not need <linux/sizes.h> nor <linux/compiler.h> so remove
them. This exposes however that a number of other files had been relying
on this implicit include for <linux/sizes.h> so add that where needed.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-06-02 17:26:16 -06:00
Tom Rini
d81b57a3cc include/ide.h: Cleanup usage
At this point in time, <ide.h> provides the IDE_BUS macro and the
function prototype for ide_set_reset, which is used with IDE_RESET. The
only files which should include this header are the ones that either use
that macro or that function. Remove <blk.h> from <ide.h> and remove
<ide.h> from places which do not need it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-06-02 17:26:16 -06:00
Tom Rini
43d76dc7df include/fat.h: Audit include list
This file does not need <asm/cache.h> so remove it. However the file
common/spl/spl_fat.c does need it, so add it there.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-06-02 17:26:15 -06:00
Tom Rini
40d5f55331 include/efi_loader.h, include/efi_tcg2.h: Audit include list
In include/efi_loader.h we do not directly need <log.h>, <part_efi.h>,
<pe.h> nor <linux/oid_registry.h> so remove them. In include/efi_tcg2.h
we make use of <part_efi.h> but did not include it, so add it directly.

Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Tested-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-06-02 17:26:15 -06:00
Tom Rini
8f3c64a535 include/dwmmc.h: Audit include list
This file does not need <asm/cache.h> so remove it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-06-02 17:26:15 -06:00
Tom Rini
ddf050a5d6 include/dw_hdmi.h: Audit include list
This file does not need <edid.h> so remove it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-06-02 17:26:15 -06:00
Tom Rini
1585d92a05 include/dfu.h: Audit include list
This file does not need a forward declaration of 'struct list_head' as
it includes <linux/list.h> so remove it.

Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-06-02 17:26:15 -06:00
Tom Rini
cad8e20333 include/compiler.h: Audit include list
This file does not need <time.h> so remove it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-06-02 17:26:15 -06:00
Tom Rini
ef560b42ec include/cbfs.h: Audit include list
This file does not need <compiler.h> but does directly need
<linux/types.h>.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-06-02 17:26:15 -06:00
Tom Rini
5d14fca77a include/cadence-nand.h: Audit include list
This file does not need <linux/mtd/mtd.h> but does directly need
<linux/types.h>.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-06-02 17:26:15 -06:00
Tom Rini
5bbc8b5c55 include/bootstd.h: Audit include list
This file does not need <linux/list.h> so remove it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-06-02 17:26:15 -06:00
Tom Rini
48703b2d6b include/bootflow.h: Audit include list
This file does not need <linux/list.h> but does directly need
<linux/types.h>.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-06-02 17:26:15 -06:00
Tom Rini
377c75f8c5 include/bios_emul.h: Audit include list
This file does not need <pc.h> but does directly need
<linux/types.h>. Furthermore, arch/x86/lib/bios.c was getting <pci.h>
via <bios_emul.h> so add it there.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-06-02 17:26:15 -06:00
Tom Rini
6a891bb78c include/arm_ffa.h: Audit include list
This file does not need <linux/printk.h> but does directly need
<linux/types.h>.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-06-02 17:26:15 -06:00
Tom Rini
a510bc2c9a include/ahci.h: Audit include list
This file does not need <pci.h> but does directly need <linux/types.h>.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-06-02 17:26:15 -06:00
Marek Vasut
52caad0d14 ARM: Align image end to 8 bytes to fit DT alignment
Align U-Boot image end to 8 bytes to make sure DT alignment requirement
is fulfilled. This fixes a possible failure in fdt_find_separate() in
case the U-Boot image is aligned to 4 Bytes and DT is appended at the
end at already 8 Byte aligned offset.

Link: https://source.denx.de/u-boot/u-boot/-/issues/30
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
2025-06-02 17:25:35 -06:00
Tom Rini
d45b1d4ac9 Merge tag 'u-boot-dfu-next-20250602' of https://source.denx.de/u-boot/custodians/u-boot-dfu into next
u-boot-dfu-20250602

CI: https://source.denx.de/u-boot/custodians/u-boot-dfu/-/pipelines/26466

Usb gadget:
dwc2: Fix incorrect ULPI_UTMI_SEL bit setting
dwc2: Fix HBstLen setting for external DMA mode
dwc2: Various refactors to get the code closer to Linux
dwc2: Support reset logic for v4.20a
2025-06-02 08:43:10 -06:00
Junhui Liu
42911f61b7 usb: dwc2: Refactor register operations with clrsetbits macros
Refactor DWC2 USB gadget driver to replace manual read-modify-write
operations with `clrsetbits_le32`, `setbits_le32`, and `clrbits_le32`
macros, which simplify the code and improve readability.

Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Link: https://lore.kernel.org/r/20250126-dwc2-clrsetbits-refactor-v1-1-68c27e1b6f84@pigmoral.tech
Signed-off-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
2025-06-02 10:02:46 +02:00
Kongyang Liu
bd88148a1b usb: dwc2: Replace uint<x>_t types with u<x>
Updates all instances of uint8_t, uint16_t, and uint32_t to u8, u16, and
u32 respectively, ensuring consistent use of kernel-preferred types and
resolving checkpatch.pl warnings.

Signed-off-by: Kongyang Liu <seashell11234455@gmail.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Link: https://lore.kernel.org/r/20250110-dwc2-dev-v4-8-987f4fd6f8b2@pigmoral.tech
Signed-off-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
2025-06-02 09:57:43 +02:00
Kongyang Liu
c5d685b899 usb: dwc2: Unify flush and reset logic with v4.20a support
This patch merges flush and reset logic for both host and gadget code
into a common set of functions, reducing duplication. It also adds support
for the updated reset logic to compatible with core version since v4.20a.

This patch mainly refers to the patch in the kernel.
link: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=65dc2e725286106f99c6f6b78e3d9c52c15f3a9c

Signed-off-by: Kongyang Liu <seashell11234455@gmail.com>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Link: https://lore.kernel.org/r/20250110-dwc2-dev-v4-7-987f4fd6f8b2@pigmoral.tech
Signed-off-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
2025-06-02 09:57:43 +02:00
Kongyang Liu
24b0e2604e usb: dwc2: Extract macro definitions to common header
Some macros are shared between host and gadget code, causing duplicated
definitions. Move DWC2 macro definitions from host and gadget code into a
common header to reduce duplication.

Signed-off-by: Kongyang Liu <seashell11234455@gmail.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Link: https://lore.kernel.org/r/20250110-dwc2-dev-v4-6-987f4fd6f8b2@pigmoral.tech
Signed-off-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
2025-06-02 09:57:25 +02:00
Kongyang Liu
6def014bba usb: dwc2: Align macros with Linux kernel definitions
Update the DWC2 macros to match those used in the Linux kernel, making
it easier to synchronize updates with kernel. Also removed some unused
macros to cleanup the code.

Signed-off-by: Kongyang Liu <seashell11234455@gmail.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
Link: https://lore.kernel.org/r/20250110-dwc2-dev-v4-5-987f4fd6f8b2@pigmoral.tech
Signed-off-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
2025-06-02 09:57:25 +02:00
Kongyang Liu
a5699130f4 usb: dwc2: Clean up with bitfield macros
Use FIELD_PREP, FIELD_GET, BIT, and GENMASK macros to standardize bit
manipulation across the DWC2 code, improving readability and
maintainability without altering functionality.

Signed-off-by: Kongyang Liu <seashell11234455@gmail.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
Link: https://lore.kernel.org/r/20250110-dwc2-dev-v4-4-987f4fd6f8b2@pigmoral.tech
Signed-off-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
2025-06-02 09:57:25 +02:00
Kongyang Liu
bd6ef5097d usb: dwc2: Fix HBstLen setting for external DMA mode
The loop used to calculate HBstLen for extern DMA mode does not produce
the correct result according to the datasheet [1]. Replacing that loop
with a direct calculation using LOG2 to correctly assign the burst length
in the GAHBCFG register for external DMA mode.

[1] https://rockchip.fr/RK312X%20TRM/chapter-26-usb-otg-2-0.pdf#page=24

Signed-off-by: Kongyang Liu <seashell11234455@gmail.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
Link: https://lore.kernel.org/r/20250110-dwc2-dev-v4-3-987f4fd6f8b2@pigmoral.tech
Signed-off-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
2025-06-02 09:57:25 +02:00
Junhui Liu
94a1f8fe47 usb: dwc2: Fix incorrect ULPI_UTMI_SEL bit setting
The ULPI_UTMI_SEL bit in the DWC2 driver was set incorrectly. According
to the datasheet [1], this bit should be set to 0 for UTMI interface and 1
for ULPI interface. The existing code had this logic reversed,
causing the interface selection to be incorrect.

This commit corrects the ULPI_UTMI_SEL bit setting to match the
datasheet's description. Referencing the kernel's code [2] also confirms
this fix.

[1] https://rockchip.fr/RK312X%20TRM/chapter-26-usb-otg-2-0.pdf#page=30
[2] https://github.com/torvalds/linux/blob/v6.13-rc3/drivers/usb/dwc2/core.c#L1106

Reviewed-by: Marek Vasut <marex@denx.de>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
Link: https://lore.kernel.org/r/20250110-dwc2-dev-v4-2-987f4fd6f8b2@pigmoral.tech
Signed-off-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
2025-06-02 09:57:25 +02:00
Kongyang Liu
14f9041309 usb: dwc2: Extract register definitions to common header file
The same registers are accessed in both the otg and gatet drivers of
dwc2, and these registers are repeatedly defined in these two parts.
Extract register definitions into a common header file to reduce
redundancy and make the code more maintainable.

Signed-off-by: Kongyang Liu <seashell11234455@gmail.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
Link: https://lore.kernel.org/r/20250110-dwc2-dev-v4-1-987f4fd6f8b2@pigmoral.tech
Signed-off-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
2025-06-02 09:57:25 +02:00
Tom Rini
3d9f63519d Merge tag 'u-boot-imx-next-20250601' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx into next
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/26436

- Add i.MX6UL clk driver.
- Improve the .MX6UL NAND controller performance.
- Add imx6ulz BSH SMM M2B board.
- Several improvements for imx8m venice boards.
2025-06-01 09:36:18 -06:00
Michael Trimarchi
c7b82b4aab bsh: imx6ulz_smm_m2: Add imx6ulz BSH SMM M2B board
Introduce the BSH SystemMaster (SMM) M2B board. Notably, the M2B is
designed to leverage the existing device tree of its predecessor, the M2.
The primary distinction arises from memory incompatibilities with the M2.
To address this, we've implemented a configuration system that allows for
selective inclusion of the desired memory components.

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2025-05-31 16:59:28 -03:00
Michael Trimarchi
8642939ee0 configs/imx6ulz_smm_m2_defconfig: Enable clock framework
Enable the clock framework on the m2 platform.
This helps to increase the NAND controller performance.

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2025-05-31 16:59:12 -03:00
Michael Trimarchi
404a4c84d8 mtd: nand: Add support for EDO mode 1-5 to IMX6ULL platform
The clock driver allows to boost the NAND performance
controller. Make changes to let it use the new clock driver

=> time nand read ${loadaddr} kernel

NAND read: device 0 offset 0x500000, size 0x800000
 8388608 bytes read: OK

time: 0.488 seconds

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2025-05-31 16:59:12 -03:00
Michael Trimarchi
1c513b9edf mtd: mxs_nand_dt: Move from clk_get/clk_enable to clk_bulk api
Make simple the clock registration and enable and allow later
to add support for other platforms

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2025-05-31 16:59:11 -03:00
Michael Trimarchi
0f53197c3d clk: imx: add i.MX6UL clk driver
Add i.MX6UL clk driver for i.MX6UL CLK driver model usage

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
Tested-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2025-05-31 16:59:11 -03:00
Tim Harvey
37195f8413 imx8mp-venice-gw74xx: add w_disable2 gpio configuration
The GW74xx D revision has added a M2SKT_WDIS2# GPIO which routes to the
W_DISABLE2# pin of the M.2 socket.

Add the iomux and a line name for this and rename the existing
m2_wdis# signal to m2_wdis1#.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2025-05-30 19:10:56 -03:00
Tim Harvey
314469b6ba board: venice: append configuration string to model
Append the optional board configuration string to the model info.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2025-05-30 19:10:56 -03:00
Tim Harvey
41bc2d5334 board: venice: update model representation for venice-flex
Update the model string representation for the Venice-Flex product
family (GW8xxx).

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2025-05-30 19:10:56 -03:00
Tim Harvey
da9e2218af board: venice: add FSA support
The Gateworks Flexible Socket Adapters adapt common
busses such as SDIO/UART/USB/PCI to various connectors
such as M.2 B-Key, M.2 E-Key, M.2 M-Key, and MiniPCIe.

Each FSA has an EEPROM onboard describing its details as well as an
optional port-expander for configurable GPIO's.

Add support for identifying the FSA's and configuring their
details such as user description and GPIO's:
 - enable pca953x, pca954x and eeprom support for communicating
   with the I2C eeprom and gpio port expander on the FSA
 - add FSA detection support
 - add FSA gpio configuration support

Each FSA is identified in the device-tree by an alias to it's I2C
bus where an eeprom@54 node must exist as well as an gpio@20 node
for an io-expander. These nodes must be enabled so that
they can be probed to determine if they are actually present in
the system. If not present or not enabled the gpio expander can
not be used. This also requires livetree as the gpio expander
node if not present must be disabled.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2025-05-30 19:10:56 -03:00
Tim Harvey
9eebca1025 board: venice: add imx8mp-gw82xx support
The Gateworks GW82XX-2X is an ARM based single board computer (SBC)
comprised of the i.MX8M Plus based gw702x SoM and the gw82xx
baseboard featuring:
 - i.MX8M Plus SoC
 - LPDDR4 DRAM
 - eMMC FLASH
 - Gateworks System Controller (GSC)
 - microSD (1.8V/3.3V Capable)
 - panel status bi-color LED
 - pushbutton switch
 - fan controller with tachometer
 - USB Type-C connector
 - PCIe switch
 - 2x GbE RJ45 connectors
 - multi-protocol RS232/RS485/RS422 Serial ports
 - 2x Flexible Socket Adapters with SDIO/UART/USB/PCIe
   (for M.2 and miniPCIe expansion)
 - 2x isolated CAN
 - GPS
 - accelerometer
 - magnetometer
 - off-board connectors for: SPI, GPIO, I2C, ADC
 - Wide range DC power input
 - support for 802.3at PoE (via adapter)

Add support for it by providing its device-tree.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2025-05-30 19:10:56 -03:00
Tim Harvey
5e72676890 board: venice: flip logic for GSC supervisor enable
Flip the logic used to determine if a board has the proper hardware to
support enabling the GSC voltage supervisor so that we do not need to
keep adding new models to the list.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2025-05-30 19:10:56 -03:00
Tim Harvey
b1ead5a224 board: venice: use SOM model for PMIC adjustment on SOM
Use the SOM model to adjust PMIC settings on SOM's.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2025-05-30 19:10:56 -03:00
Tim Harvey
ea04f7261e board: venice: use baseboard model for family
The venice family of baseboards which is normally GW7xxx
is being expanded to GW8xxx so we need to use the baseboard
number instead of the som.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2025-05-30 19:10:56 -03:00
Tim Harvey
c83ab82640 board: venice: fix dram size for GW7901-SP486
The GW7901-SP486 with the exception of the -C revision has 2GB DRAM
loaded but incorrectly specifies 1GB in the EEPROM. Adjust the DRAM size
to account for this.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2025-05-30 19:10:55 -03:00
Tim Harvey
1bf9f1e550 board: venice: fix dram bus config for GW7902/GW7903/GW7904
The GW7902/GW7903/GW7904 have an alternate databus layout affecting a few
of the DDRC and DDR PHY registers.

The 512MB configuration used this alternate bus layout. Change
the 512MB config to the standard bus configuration and add a generic
function to patch the DDRC/PHY configs for the alternate bus layout.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2025-05-30 19:10:55 -03:00
Tim Harvey
66e8b17eee board: venice: move soc-specific dram config into soc-specific files
Move the determination of the dram timings into the soc-specific files.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2025-05-30 19:10:55 -03:00
Tim Harvey
2f1c3e1f9e configs: imx8m*_venice: enable GPT support
Enable support for working with General Partition Tables via the 'gpt'
command. Also enable support for generating random UUID's for GPT.

See: doc/README.gpt for examples

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2025-05-30 19:10:55 -03:00
Tim Harvey
ea26f2ac4c configs: imx8m*_venice: enable several commands useful for scripting
enable cat, xxd, and the ability for setexpr to return values in
variables which are all useful for scripting.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2025-05-30 19:10:55 -03:00
Tom Rini
6e03ca2409 Merge tag 'dm-pull-30may25' of git://git.denx.de/u-boot-dm into next
Bring in recent expo enhancements:
- multi-line text
- highlighting of menu items
- rationalisation of menu and expo code
- support for object alignment
- editable strings
- various bug fixes and tweaks

This also includes some required abuf improvements.
2025-05-30 13:53:50 -06:00
Tom Rini
5eb1b78438 Merge patch series "test/py: enable HTTP testing"
Adriano Cordova <adrianox@gmail.com> says:

Enable HTTP server in CI to support HTTP tests in pytest

QEMU does not emulate an HTTP server, unlike other services like DHCP or TFTP.
To enable HTTP  tests during CI runs, start a simple Python HTTP server
on port 80. This allows tests that require HTTP access to run.

The HTTP server is launched on the host. For QEMU environments launched
with '-netdev,user' this means that the HTTP server runs together with DHCP
at 10.0.2.2.  HTTP testing needs to be explicitly enabled with
env__efi_helloworld_net_http_test_skip = False.

We also default `WGET=y` in `ARCH_QEMU` configurations so that these HTTP
tests are included automatically when using QEMU in CI.

Link: https://lore.kernel.org/r/20250516085256.30386-1-adriano.cordova@canonical.com
2025-05-30 11:19:45 -06:00
Adriano Cordova
ec1d9f3fe8 cmd/Kconfig: select CMD_WGET if ARCH_QEMU
select CMD_WGET for ARCH_QEMU. This way HTTP can be tested
on the qemu platforms in CI.

Signed-off-by: Adriano Cordova <adriano.cordova@canonical.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-05-30 11:19:44 -06:00
Adriano Cordova
3e58991339 CI testing: add http server to CI tests
Add an http server to CI tests so that HTTP booting and
loading can be tested.

Signed-off-by: Adriano Cordova <adriano.cordova@canonical.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-05-30 11:19:43 -06:00
Marek Vasut
e15282f943 image: Fix FIT image loadable section custom processing
The original commit always generated linker list entries with the same
entry variable name, because _function passed to ll_entry_declare() is
not a variable and therefore was interpreted as fixed string. Change it
to _type which is a variable and which does allow generation of multiple
unique linker list entries, one for each U_BOOT_FIT_LOADABLE_HANDLER().

Fixes: d7be50921e ("image: Add FIT image loadable section custom processing")
Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
2025-05-30 10:19:24 -06:00
Tom Rini
c7f360f20d Gitlab: Rework sjg-lab calling test.py to be closer to test.py stage
There are a few differences between how the test.py stage invokes
test.py and how the sjg-lab stage invokes test.py. As a start of making
both the code and the output and artifacts similar, this updates the
sjg-lab stage with the following:
- Pass "-ra" so that we get the summary information in the job
- Make use of TEST_PY_EXTRA for passing "--capture=tee-sys"
- Re-order some of the arguments to be the same order when possible.

And most importantly:
- Create and save as an artifact the junitxml output.

The last part here is the kind of test result information that in the
future we should determine how to archive for future reference.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-05-30 10:19:02 -06:00
Tom Rini
2ab0f0d058 Merge patch series "Almost complete DM_SERIAL migration"
Tom Rini <trini@konsulko.com> says:

In a private thread, Simon asked about what's needed to get PowerPC
migrated to DM_SERIAL. I went and took a look, and to complete the
entire DM_SERIAL migration (excluding SPL/TPL) we're actually nearly
there. This series first migrates PowerPC (and some NXP Layerscape
boards that share history more clearly with PowerPC parts), with the
biggest change being to make sure we still use the correct legacy
drivers in SPL/TPL (where SPL is extremely constrained). With that out
of the way, I looked at what was left. With two exceptions, it's
platforms which can be trivially enabled for conversion, and so we do
that.

Link: https://lore.kernel.org/r/20250502201226.1369013-1-trini@konsulko.com
2025-05-30 10:17:40 -06:00
Tom Rini
b5321da5cc global: Convert almost all remaining non-DM_SERIAL users
This converts almost all of the remaining non-DM_SERIAL users to enable
DM_SERIAL. These are platforms where there have long been other SoC
boards that have switched and so it's been a matter of inertia keeping
these from being converted. Do so now.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-05-30 10:16:51 -06:00
Tom Rini
191b10ac70 PowerPC / Layerscape: Finish migration to DM_SERIAL
Migrate the few ARM Layerscape platforms that had not been switched
along with all remaining PowerPC platforms to DM_SERIAL. For PowerPC,
this means that platforms which use SPL/TPL, keeping the non-DM serial
driver enabled there as they do not use DM. We also rework the guards
on how to define CFG_SYS_NS16550_CLK so that this is mostly in one place
now.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-05-30 10:16:51 -06:00
Simon Glass
44fc287387 expo: Drop the special theme code for bootflow_menu
The expo now has all that is needed to apply a suitable theme, so drop
this unnecessary code. Any further tweaks can be added to the generic
expo code.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-30 09:49:33 +01:00
Simon Glass
8a9d40b047 expo: Set up menu fully in bootflow_menu_start()
Apply the theme, calculate dimensions, highlight the menu and arrange
the scene correctly, so that everything is ready to go when the expo
is rendered.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-30 09:49:33 +01:00
Simon Glass
f769735f88 expo: Split setting up the menu from adding items
Some callers may wish to add items later as they are discovered. Split
the setup code into its own function, to permit this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-30 09:49:33 +01:00
Simon Glass
06a9d88e4d expo: Update bootflow_menu_poll() to return a sequence ID
Rather than returning a bootflow, return the index of the bootflow. This
will allow callers to do their own translation to bootflows or some
other data structure.

Also return a special code when the user tries to move the pointer, so
that the caller can cancel the boot-menu timeout, if this is in use.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-30 09:49:33 +01:00
Simon Glass
f8f8f822c3 expo: Improve the visual appearance of the menu
The menu is currently quite basic. Make use of some recently added
features in expo, to:

- Show proper prompts
- Highlight the current item
- Centre text
- Use multi-line text instead of two independent lines
- Put a box around the items

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-30 09:49:32 +01:00
Simon Glass
ddd1c97653 expo: Provide a way to position things relative to display
It is often necessary to centre objects within the display area. Add a
special position value to indicate this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-30 09:49:32 +01:00
Simon Glass
8d7ae52d77 expo: Drop the render from expo_poll()
Within tests it is useful to be able to control rendering of the expo.
Drop the automatic call to expo_render() within expo_poll() and adjust
its callers to handle this instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-30 09:49:32 +01:00
Simon Glass
5bca479897 expo: Adjust expo_poll() to avoid looping forever
If the user does not quickly provide some input, exit so that other
things can be done, such as searching for the next OS.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-30 09:49:32 +01:00
Simon Glass
0dc8c7740c expo: Support highlighting menu items
Expo normally uses a pointer to show the current item. Add support for
highlighting as well, since this makes it easier for the user to see the
current item.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-30 09:49:32 +01:00
Simon Glass
86acc21d85 expo: Add forward declarations to scene_internal.h
Provide some forward declarations for types used in this file, to keep
the LSP happy and avoid errors if the caller happens not to include the
required header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-30 09:49:32 +01:00
Simon Glass
bebc3547b2 expo: Drop the gap between groups of menu items
The gap is intended to separate options which are on different bootdevs,
but most of the time there is only one. So drop this gap.

Keep the code around in case it becomes useful to have it in the style,
or based on some other mechanism.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-30 09:49:32 +01:00
Simon Glass
3c35fb03d5 expo: Use a simpler name for USB media
For USB devices we use the string 'usb_mass_storage' which is a bit
verbose. Use 'USB' instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-30 09:49:32 +01:00
Simon Glass
e005f18b93 expo: Begin implementation of a text editor
It is useful to be able to edit text, e.g. to allow the user to edit the
environment or the command-line arguments for the OS.

Add the beginnings of an implementation. Future work is needed to finish
this: keypress handling and scrolling. For now it just displays the
text.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-30 09:49:32 +01:00
Simon Glass
09f6f915fe expo: Support object alignment
Add support for left, right and centred alignment for text, in the
horizontal dimension.

Also support top, bottom and centred in the vertical dimension, for the
text object as a whole.

Alignment is not yet implemented for images. It has no meaning for
menus. A textline object uses a text object internally, so alignment
is supported there.

Provide some documentation to explain how objects are positioned.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-30 09:49:32 +01:00
Simon Glass
0635004e22 expo: Implement a box
It is useful to be able to draw a box around elements in the menu. Add
support for an unfilled box with a selectable thickness.

Note that there is no support for selecting the colour for any expo
objects yet.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-30 09:49:32 +01:00
Simon Glass
d25c62fd58 expo: Support white-on-black in the theme
Allow this setting to be controlled from the theme.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-30 09:49:32 +01:00
Simon Glass
03f9ce815c expo: Support rendering multiple lines of text
Use the measurement info to write each line of text separately, thus
respecting word-wrapping and newlines.

Fix up the comment for scene_obj_render() while we are here.

Since a lineedit does not support alignment, add a special case to just
display the text if there is no measurement. This happens assuming the
lineedit is initially empty.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-30 09:49:32 +01:00
Simon Glass
b62a8cfbb6 expo: Check the screen contents after rendering
Make sure that the screen contents are as expected when a scene has been
rendered.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-30 09:49:32 +01:00
Simon Glass
87750b0276 expo: Allow strings to be editable
In some cases dynamic text is needed, e.g. for a menu countdown. Add a
function which handles this, allowing the caller to take control of the
text that is shown on each render.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-30 09:49:32 +01:00
Simon Glass
589e4ccacf expo: Tidy up scene_txt_render()
Add an early return if there is no string. Move all declarations to the
top of the function.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-30 09:49:32 +01:00
Simon Glass
ead673dd24 expo: Move text-rendering into its own function
The code to render text is quite long, so put it in its own function.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-30 09:49:32 +01:00
Simon Glass
5a80996cb6 expo: Create a struct for generic text attributes
In preparation for adding more text types, refactor the common fields
into a new structure. This will allow common code to be used.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-30 09:49:32 +01:00
Simon Glass
5ea2b533ed expo: Line up all menu objects
At present labels are lined up vertically. Do the same with keys and
descriptions, since it looks nicer.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-30 09:49:32 +01:00
Simon Glass
e3c3f83cb6 expo: Support setting the size and bounds of an object
Add a function to allow the size of an object to be set independently
of its position.

Also add a function to permit the object's bounding box to be set
independently of its dimensions.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-30 09:49:32 +01:00
Simon Glass
baaf090734 expo: Make bounding-box calculation more flexible
In some cases it is useful to obtain more than just two bounding boxes
from a menu, e.g. to line up all descriptions vertically.

Use an array to obtain bounding-box information and calculate it
separately for each item.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-30 09:49:32 +01:00
Simon Glass
f04026a59f expo: Separate dimensions from the bounding box
At present each object has a width and height and the bounding box is
implicit in that.

This is not flexible enough to handle objects which are larger than
their contents might need. For example, when centring a text object we
might want to have it stretch across the whole width of the display even
if the text itself does not need that much space.

Create a new 'dimensions' field and convert the existing width/height
into x1/y1 coordinates.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-30 09:49:32 +01:00
Simon Glass
8636da86a2 expo: Use an abuf to hold strings
It is more convenient to put strings in an abuf so they can easily be
resized. Adjust the struct accordingly.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-30 09:49:32 +01:00
Simon Glass
8aa384d01a expo: Rename x and y in struct scene_obj_bbox
These coordinates are the top left values, so rename them to x0 and y0
in preparation for changing the width and height to x1 and y1

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-30 09:49:32 +01:00
Simon Glass
85a2954c29 expo: Rename scene_dim to scene_obj_bbox
At present we assume that each object is a simple box and that it fills
the whole box.

This is quite limiting for text objects, which we may want to centre
within the box. We need a position within the box where drawing starts.

Rename the scene_dim struct to indicate that it is a bounding box.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-30 09:49:32 +01:00
Simon Glass
a4ede5e0ac expo: Allow adding a single bootflow to a menu
Refactor bootflow_menu_add_all() to call a new bootflow_menu_add() to
add each of its bootflows.

Move the last_bootdev value into struct menu_priv to make this work.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-30 09:49:32 +01:00
Simon Glass
da754e20c9 expo: Split bootflow_menu_new() into two pieces
Split the iteration piece of this function into bootflow_menu_add_all()
so that it is possible for the caller to be in control of adding items
to the menu.

Move the expo_destroy() call into the caller.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-30 09:49:32 +01:00
Simon Glass
b991a0c8bf expo: Split bootflow_menu_run() into two pieces
Split the starting piece of this function into bootflow_menu_start()
and the polling part into bootflow_menu_poll() so that it is possible
for the caller to be in control of the event loop.

Move the expo_destroy() call into the caller.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-30 09:49:32 +01:00
Simon Glass
5098521114 expo: Test editing a lineedit
Open the lineedit and add a few characters, to check that things look
right.

At present when the user moves to a new menu item, the menu code
handles this immediately. This means it is not possible to use an expo
action to effect the same change.

Update this so that EXPOACT_POINT_ITEM is handled in cedit_do_action().

Expand the test to cover this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-30 09:49:32 +01:00
Simon Glass
d01b8e2266 expo: Adjust how menu items are highlighted
At present when the user moves to a new menu item, the menu code
handles this immediately. This means it is not possible to use an expo
action to effect the same change.

Update this so that EXPOACT_POINT_ITEM is handled in cedit_do_action().

Expand the test to cover this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-30 09:49:32 +01:00
Simon Glass
9f44b544e1 expo: Provide access to the current menu item
Add functions to allow a caller to find out the current menu item and to
select a different one.

Update the event handling so that an attempt to change the current item
(e.g. by pressing the up-arrow key) is reported to the caller, since
this may be used to cancel an autoboot timeout.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-30 09:49:32 +01:00
Simon Glass
c43791c487 expo: Test rendering a lineedit
Check the rendering output when adding characters to a line-edit object.

Add a separate test to check behaviour when starting with existing text
in the lineedit. The cursor should start at the end.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-30 09:49:32 +01:00
Simon Glass
23d2ddf1b4 expo: Pass in the video device for cedit_prepare()
At present this function locates it own video device. Pass it in to
provide more flexibility.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-30 09:49:32 +01:00
Simon Glass
5f99334296 expo: Test some cedit actions
Refactor the action-processing code into a new cedit_do_action()
function so we can call it from a test. Check moving to a new field and
opening the menu, to ensure that rendering is correct.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-30 09:49:32 +01:00
Simon Glass
932ea4a104 expo: Move cedit-state fields into expo
Move the boolean flags into struct expo so that the state can be
maintained over function calls.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-30 09:49:32 +01:00
Simon Glass
cd5b7d3132 expo: Create a rendering test for cedit
Add a test to check that the cedit renders as expected.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-30 09:49:32 +01:00
Simon Glass
34cb881cc0 expo: Destroy the cedit expo when done
Once 'cedit run' is completed, destroy the expo so that a fresh one is
used for any future editing.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-30 09:49:31 +01:00
Simon Glass
bf98604595 expo: Add a function to poll for input
Both bootflow_menu and cedit use similar logic to poll an expo. Move
this into the expo library so the code can be shared.

Update bootflow_menu_run() to return -EPIPE when the user quits without
choosing anything, since -EAGAIN is ambiguous and elsewhere means that
there is no input yet.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-30 09:49:31 +01:00
Simon Glass
5c365ecabc expo: Add CLI context to the expo
An expo generally needs to keep track of the keyboard state while it is
running, so move the context into struct expo

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-30 09:49:31 +01:00
Simon Glass
4f4b9477f4 abuf: Add a way to printf() into a buffer
It is useful to format a string into a buffer, with the sizing handled
automatically. Add a function for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-30 09:49:31 +01:00
Simon Glass
d58cebbbc7 abuf: Add a function to copy a buffer
It is useful to be able to copy an abuf, to allow changes while
preserving the original. Add a function for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-30 09:49:31 +01:00
Simon Glass
97b586695c abuf: Add a helper for initing and allocating a buffer
This construct appears in various places. Reduce code size by adding a
function for it.

It inits the abuf, then allocates it to the requested size.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-30 09:49:31 +01:00
Tom Rini
6b749d09c0 Merge patch series "Update kbuild"
Ilias Apalodimas <ilias.apalodimas@linaro.org> says:

Last time the kbuild scripts were synced with the Linux kernel was on the
4.20 release. Updating directly to 6.x makes the diff difficult to read, so
let's do the changes incrementally and bump to 5.1 first.

Since the number of commits is big, I am splitting this in multiple series.
This one includes most of the commits for Makefile.build,
Makefile.lib and some from Makefile.

commit eeb5687a7139649e ("kbuild: add -Werror=strict-prototypes flag unconditionally")
commit 3812b8c5c5d5 ("kbuild: make -r/-R effective in top Makefile for old Make versions")
commit b421b8a6cb87 ("kbuild: remove unused archmrproper")
commit 1a49b2fd8f58 ("kbuild: strip whitespace in cmd_record_mcount findstring")
commit 88110713ca9dfb ("kbuild: hardcode genksyms path and remove GENKSYMS variable")
commit 1d8001ef358 ("kbuild: generate modules.order only when CONFIG_MODULES=y")
commit 45c4372d00 ("kbuild: refactor quiet_modtag")
commit b39a691617e4 commit ("kbuild: remove redundant quiet_modtag for $(obj-m)")
commit 5439f09f488f ("kbuild: remove redundant 'set -e' from cmd_* defines")
commit e5d289100d3a ("kbuild: remove trailing semicolon from cmd_* passed to if_changed_rule")
commit 3a2429e1faf4 ("kbuild: change if_changed_rule for multi-line recipe")
commit ee3e46b7efd2 ("kbuild: refactor modversions build rules")
commit 4317ee3b6a5e ("kbuild: remove redundant 'set -e' from sub_cmd_record_mcount")
commit 392885ee82d3 ("kbuild: let fixdep directly write to .*.cmd files")
commit 898f5a009f22 ("kbuild: move archive command to scripts/Makefile.lib")
commit b79c6aa6a1f1 ("kbuild: remove unnecessary in-subshell execution")
commit afa974b77128 ("kbuild: add real-prereqs shorthand for $(filter-out FORCE,$^)")
commit ecbd10d90e94 ("kbuild: simplify rules of data compression with size appending")
commit 58156ba4468f ("kbuild: skip 'addtree' and 'flags' magic for external module build")
commit 172caf1993b7 ("kbuild: remove redundant target cleaning on failure")
commit f3fd4a3f3a38 ("kbuild: remove redundant 'set -e' from filechk_offsets")
commit a2237fec1e06 ("kbuild: Enable dtc graph_port warning by default")
commit 70523a3ce5ff ("kbuild: disable dtc simple_bus_reg warnings by default")
commit e4aca4595005 ("kbuild: de-duplicate fixdep usage")

Link: https://lore.kernel.org/r/20250520052153.307194-1-ilias.apalodimas@linaro.org
2025-05-29 18:43:15 -06:00
Ilias Apalodimas
0128b2cf4d kbuild: add -Werror=strict-prototypes flag unconditionally
Backported from kernel
commit eeb5687a7139649e ("kbuild: add -Werror=strict-prototypes flag unconditionally")

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-05-29 18:42:38 -06:00
Ilias Apalodimas
af1a993570 kbuild: make -r/-R effective in top Makefile for old Make versions
Backported from kernel
commit 3812b8c5c5d5 ("kbuild: make -r/-R effective in top Makefile for old Make versions")

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-05-29 18:42:38 -06:00
Ilias Apalodimas
0719c79e09 kbuild: remove unused archmrproper
Backported from kernel
commit b421b8a6cb87 ("kbuild: remove unused archmrproper")

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-05-29 18:42:38 -06:00
Ilias Apalodimas
25ab30f1c4 kbuild: strip whitespace in cmd_record_mcount findstring
Backport from kernel
commit 1a49b2fd8f58 ("kbuild: strip whitespace in cmd_record_mcount findstring")

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-05-29 18:42:38 -06:00
Ilias Apalodimas
bb08767f12 kbuild: hardcode genksyms path and remove GENKSYMS variable
Back port from kernel although it's not used since it makes diffing
easier.
commit 88110713ca9dfb ("kbuild: hardcode genksyms path and remove GENKSYMS variable")

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-05-29 18:42:38 -06:00
Ilias Apalodimas
1a59e6d3ba kbuild: generate modules.order only when CONFIG_MODULES=y
Backport from kernel although it is unused since it makes diffing easier.
commit 1d8001ef358 ("kbuild: generate modules.order only when CONFIG_MODULES=y")

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-05-29 18:42:38 -06:00
Ilias Apalodimas
88067ffc0c kbuild: refactor quiet_modtag
Backport from kernel
commit 45c4372d00 ("kbuild: refactor quiet_modtag")

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-05-29 18:42:37 -06:00
Ilias Apalodimas
47b6ab9737 kbuild: remove redundant quiet_modtag for $(obj-m)
Backported from kernel
commit b39a691617e4 commit ("kbuild: remove redundant quiet_modtag for $(obj-m)")

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-05-29 18:42:37 -06:00
Ilias Apalodimas
919bd66ca8 kbuild: remove redundant 'set -e' from cmd_* defines
Backported from kernel
commit 5439f09f488f ("kbuild: remove redundant 'set -e' from cmd_* defines")

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-05-29 18:42:37 -06:00
Ilias Apalodimas
82f75d890d kbuild: remove trailing semicolon from cmd_* passed to if_changed_rule
Backport from kernel
commit e5d289100d3a ("kbuild: remove trailing semicolon from cmd_* passed to if_changed_rule")

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-05-29 18:42:37 -06:00
Ilias Apalodimas
daf8f5af4c kbuild: change if_changed_rule for multi-line recipe
Backport from kernel
commit 3a2429e1faf4 ("kbuild: change if_changed_rule for multi-line recipe")

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-05-29 18:42:37 -06:00
Ilias Apalodimas
3679f24373 kbuild: refactor modversions build rules
Backport from kernel
commit ee3e46b7efd2 ("kbuild: refactor modversions build rules")

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-05-29 18:42:37 -06:00
Ilias Apalodimas
2c180949ec kbuild: remove redundant 'set -e' from sub_cmd_record_mcount
Back from kernel
commit 4317ee3b6a5e ("kbuild: remove redundant 'set -e' from sub_cmd_record_mcount")

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-05-29 18:42:37 -06:00
Ilias Apalodimas
cc571e29a8 kbuild: let fixdep directly write to .*.cmd files
Backport from kernel
commit 392885ee82d3 ("kbuild: let fixdep directly write to .*.cmd files")

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-05-29 18:42:37 -06:00
Ilias Apalodimas
47a4770c7a kbuild: move archive command to scripts/Makefile.lib
Backport from kernel
commit 898f5a009f22 ("kbuild: move archive command to scripts/Makefile.lib")

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-05-29 18:42:37 -06:00
Ilias Apalodimas
603a4ade16 kbuild: remove unnecessary in-subshell execution
Backport kernel changes

commit b79c6aa6a1f1 ("kbuild: remove unnecessary in-subshell execution")

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-05-29 18:42:37 -06:00
Ilias Apalodimas
a73c41c398 kbuild: add real-prereqs shorthand for $(filter-out FORCE, $^)
Backport from kernel
commit afa974b77128 ("kbuild: add real-prereqs shorthand for $(filter-out FORCE,$^)")

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-05-29 18:42:37 -06:00
Ilias Apalodimas
39160c5fbf kbuild: simplify rules of data compression with size appending
Backport kernel changes
commit ecbd10d90e94 ("kbuild: simplify rules of data compression with size appending")

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-05-29 18:42:37 -06:00
Ilias Apalodimas
3d21332c2f kbuild: skip 'addtree' and 'flags' magic for external module build
Backport from kernel
commit 58156ba4468f ("kbuild: skip 'addtree' and 'flags' magic for external module build")

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-05-29 18:42:37 -06:00
Ilias Apalodimas
cfccf25100 kbuild: remove redundant target cleaning on failure
Bacport from the kernel

commit 172caf1993b7 ("kbuild: remove redundant target cleaning on failure")

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-05-29 18:42:37 -06:00
Ilias Apalodimas
14795eba8b kbuild: remove redundant 'set -e' from filechk_offsets
Backport changes from the kernel

commit f3fd4a3f3a38 ("kbuild: remove redundant 'set -e' from filechk_offsets")

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-05-29 18:42:37 -06:00
Ilias Apalodimas
1ecfa813bb kbuild: Enable dtc graph_port warning by default
Backport changes from the kernel
commit a2237fec1e06 ("kbuild: Enable dtc graph_port warning by default")

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-05-29 18:42:37 -06:00
Ilias Apalodimas
31811fbb6b kbuild: disable dtc simple_bus_reg warnings by default
Backport changes from the kernel
commit 70523a3ce5ff ("kbuild: disable dtc simple_bus_reg warnings by default")

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-05-29 18:42:37 -06:00
Ilias Apalodimas
afba83ad89 kbuild: de-duplicate fixdep usage
Backported from the linux kernel
commit e4aca4595005 ("kbuild: de-duplicate fixdep usage")

A lot of the kernels kbuild depend on that patch. Backport it and pull in
the 'rule_as_o_S'a rule as well. This might end up being unused but it
doesn't break anything and makes diffing the files easier.

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-05-29 18:42:37 -06:00
Tom Rini
a619c44109 Merge patch series "Enable env in SCSI"
Varadarajan Narayanan <quic_varada@quicinc.com> says:

The qcs9100 based Ride platforms have UFS as their primary storage.
Hence add support to U-Boot env framework to be able to save and
retrieve the environment from UFS. The environment will be
saved/retrieved from the partition specified in the config option
CONFIG_SCSI_ENV_PART.

Also add an API to convert partition UUID string to block device
descriptor for UFS. This API will be used to get the block device
descriptor for the partition specified in CONFIG_SCSI_ENV_PART.

Link: https://lore.kernel.org/r/20250513091710.3719292-1-quic_varada@quicinc.com
2025-05-29 18:36:51 -06:00
Varadarajan Narayanan
142aab7f3e configs: qcs9100: Enable env in SCSI
Enable CONFIG_ENV_IS_IN_SCSI to store environment variables in SCSI.
Set env variables partition UUID as seen in qcs9100 based boards.

Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
2025-05-29 18:35:51 -06:00
Varadarajan Narayanan
8bf3e967f6 env: Add support for storing env variables in SCSI devices
Allow SCSI to be able to store environment variables.

Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Acked-by: Casey Connolly <casey.connolly@linaro.org>
2025-05-29 18:35:50 -06:00
Varadarajan Narayanan
9a2010941f scsi: Implement get_blk() function
Add a function to obtain the block device for SCSI.

Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Acked-by: Casey Connolly <casey.connolly@linaro.org>
2025-05-29 18:35:49 -06:00
Varadarajan Narayanan
43fd4bcefd disk: part: implement generic function part_get_info_by_uuid()
Add function to search for a partition by UUID as partition
names may not be unique.

Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Acked-by: Casey Connolly <casey.connolly@linaro.org>
2025-05-29 18:35:43 -06:00
Tom Rini
1481ae5d5a Merge patch series "Remove clocks from R5 dtsi for missed boards."
Manorit Chawdhry <m-chawdhry@ti.com> says:

Fix some of the boards that could be affected by the change done in [0].

[0]: https://lore.kernel.org/u-boot/20241121-b4-upstream-pll-fix-v1-0-904f618897a7@ti.com/T/#mecb70b415a364fdf322a94241438db7b5607e92b
Link: https://lore.kernel.org/r/20250515-b4-upstream-k3-pll-miss-v1-0-e38b89f027b8@ti.com
2025-05-29 08:33:17 -06:00
Manorit Chawdhry
8668c6a3bd arm: dts: k3-am62a7-phycore-r5*: Remove clocks from main_timer0
The commit 79d91e77f4 ("clk: ti: clk-k3-pll: Add additional robustness
steps to the PLL sequence") introduced a change which requires the
main_timer0 to not rely on it's own clocks which anyways was wrong.

Fix it by removing the clock dependency for it, also while at it, move
it from u-boot.dtsi to R5 as that is the only entity that should require
it as DM isn't up.

Fixes: 5d1aac358f ("arm: dts: k3-*-r5: Remove clocks from mcu_timer0")
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Acked-by: Wadim Egorov <w.egorov@phytec.de>
2025-05-29 08:33:11 -06:00
Manorit Chawdhry
2696d3baea arm: dts: k3-am625-verdin-r5*: Remove clocks from main_timer0
The commit 79d91e77f4 ("clk: ti: clk-k3-pll: Add additional robustness
steps to the PLL sequence") introduced a change which requires the
main_timer0 to not rely on it's own clocks which anyways was wrong.

Fix it by removing the clock dependency for it, also while at it, move
it from u-boot.dtsi to R5 as that is the only entity that should require
it as DM isn't up.

Fixes: 5d1aac358f ("arm: dts: k3-*-r5: Remove clocks from mcu_timer0")
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Acked-by: Francesco Dolcini <francesco.dolcini@toradex.com>
2025-05-29 08:33:11 -06:00
Manorit Chawdhry
92f1347d7c arm: dts: k3-am625-phycore-r5*: Remove clocks from main_timer0
The commit 79d91e77f4 ("clk: ti: clk-k3-pll: Add additional robustness
steps to the PLL sequence") introduced a change which requires the
main_timer0 to not rely on it's own clocks which anyways was wrong.

Fix it by removing the clock dependency for it, also while at it, move
it from u-boot.dtsi to R5 as that is the only entity that should require
it as DM isn't up.

Fixes: 5d1aac358f ("arm: dts: k3-*-r5: Remove clocks from mcu_timer0")
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Tested-by: Wadim Egorov <w.egorov@phytec.de>
2025-05-29 08:33:11 -06:00
Manorit Chawdhry
53f42c5643 arm: dts: k3-am625-beagleplay-r5*: Remove clocks from main_timer0
The commit 79d91e77f4 ("clk: ti: clk-k3-pll: Add additional robustness
steps to the PLL sequence") introduced a change which requires the
main_timer0 to not rely on it's own clocks which anyways was wrong.

Fix it by removing the clock dependency for it, also while at it, move
it from u-boot.dtsi to R5 as that is the only entity that should require
it as DM isn't up.

Fixes: 5d1aac358f ("arm: dts: k3-*-r5: Remove clocks from mcu_timer0")
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2025-05-29 08:33:11 -06:00
Tom Rini
4c0e1d8fad Merge patch series "Print Reset Reason for K3 based devices"
Wadim Egorov <w.egorov@phytec.de> says:

Although AM62x, AM62Ax, AM64x, and AM62Px share the same register for
reset reason, not all TRMs document this consistently. To avoid relying
on undocumented behavior, introduce SoC-specific implementations for
now. If TI confirms all SoCs share the same register, this can be moved to
common.c for reuse.

It will be mostly copy&paste for the mentioned devices.

Also, I am not sure how this Register operates exactly. I noticed that
two bits can be set at once, so I started to check for set bits instead
of having a switch/case logic.

Link: https://lore.kernel.org/r/20250515111554.2916254-1-w.egorov@phytec.de
2025-05-29 08:32:52 -06:00
Wadim Egorov
be93c0892d arm: mach-k3: am62x: Implement get_reset_reason()
Implement get_reset_reason() for AM62x to enable reporting of
the reset cause in the cpuinfo output.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
2025-05-29 08:32:28 -06:00
Wadim Egorov
a282950deb arm: mach-k3: Detect and print reset reason
Call get_reset_reason() during CPU info output and display the result
if the SoC provides the implementation. This helps in debugging by
providing context on the last system reset reason.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
2025-05-29 08:32:28 -06:00
Tom Rini
62905f4a92 Merge patch series "Remove <env.h> from <net.h>"
Tom Rini <trini@konsulko.com> says:

Hey all,

This is a v3 of Simon's series[1] and depends on the series[2] I posted
the other day that removes <env.h> from <command.h>. With this series
done, I believe we've tackled all of the current cases of headers which
include <env.h> without directly needing it. Much of this series is in
fact Simon's v2 with the main differneces being:
- Removing <env.h> from <net.h> at the end
- Removing env_to_ip() given how little it's used rather than shuffling
  around where it's declared and un-inline'ing it. For a rarely used
  helper, this ends up being cleaner I think. Especially looking at some
  of the users (which called env_get repeatedly). If there's strong
  opinion here about using the other method[3] we can do that instead.
- Setting aside for now how to handle CMD_ELF=y and NO_NET=y because
  today it's actually fine as we unconditionally build lib/net_utils.c
  where string_to_ip() is defined. I'm unsure if a further series is
  warranted here or not. We rely on link-time optimization to keep code
  readable too.

[1]: https://lore.kernel.org/all/20250501010456.3930701-1-sjg@chromium.org
[2]: https://lore.kernel.org/all/20250514225002.15361-1-trini@konsulko.com
[3]: https://lore.kernel.org/all/20250501010456.3930701-23-sjg@chromium.org
Link: https://lore.kernel.org/r/20250515234154.1859366-1-trini@konsulko.com
2025-05-29 08:31:07 -06:00
Tom Rini
fe33175c07 include/net.h: Drop <env.h>
Now that all of the cases of code that relied on <net.h> to provide
<env.h> (or one of the headers that it includes, and so forth) have been
fixed, we can drop the include from here.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-05-29 08:30:25 -06:00
Tom Rini
ae9ff5ae6f global: Avoid indirect inclusion of <env.h> from <net.h>
Now that env_get_ip() has been removed, the include file <net.h> does
not need anything from <env.h>. Furthermore, include/env.h itself
includes other headers which can lead to longer indirect inclusion
paths. To prepare to remove <env.h> from <net.h> fix all of the
remaining places which had relied on this indirect inclusion to instead
include <env.h> directly.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> # net/lwip
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Martyn Welch <martyn.welch@collabora.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-05-29 08:30:25 -06:00
Simon Glass
183d88cdfc net: dc2114x: Include env.h to permit reading the environment
This file uses the environment but does not include the header file.
Update it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-29 08:30:25 -06:00
Simon Glass
85b013e3f4 net: Include env.h in pcap.c
This file uses the environment but does not include the header file.
Update it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-29 08:30:25 -06:00
Simon Glass
22d4e22a3d net: Include byteorder in net6.h
This file uses byteorder but does not include the header file. Update
it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-29 08:30:25 -06:00
Simon Glass
7b612cfa75 technexion: Include env.h to permit reading the environment
This file reads from the environment but does not include the correct
header. Update it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-29 08:30:25 -06:00
Simon Glass
ea9afef22d liebherr: Include env.h to permit reading the environment
This file reads from the environment but does not include the correct
header. Update it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2025-05-29 08:30:25 -06:00
Simon Glass
98faae1617 google: Include env.h to permit reading the environment
This file reads from the environment but does not include the correct
header. Update it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-29 08:30:25 -06:00
Simon Glass
2876ff79b2 freescale: Include env.h to permit reading the environment
This file reads from the environment but does not include the correct
header. Update it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-29 08:30:25 -06:00
Simon Glass
6d9d6ba71a amlogic: Include env.h to permit reading the environment
This file reads from the environment but does not include the correct
header. Update it.

Reviewed-by: Viacheslav Bocharov <adeep@lexina.in>
Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-29 08:30:25 -06:00
Simon Glass
f24a197973 synology: Include env.h to permit reading the environment
This file reads from the environment but does not include the correct
header. Update it.

Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Tony Dinh <mibodhi@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-29 08:30:25 -06:00
Simon Glass
433e86abea tegra: Include env.h to permit reading the environment
This file reads from the environment but does not include the correct
header. Update it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-29 08:30:25 -06:00
Simon Glass
0f8a4a9c44 advantech: Include env.h in imx8qm_dmsse20_a1
This file uses the environment but does not include the header file.
Update it.

Acked-by: Oliver Graute <oliver.graute@kococonnector.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-29 08:30:25 -06:00
Simon Glass
bcf10f16ea toradex: Include env.h to permit reading the environment
Two files read from the environment but don't not include the correct
header. Update them.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-29 08:30:25 -06:00
Simon Glass
6e898e332b ronetix: Include env.h to permit reading the environment
This file reads from the environment but does not include the correct
header. Update it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-29 08:30:25 -06:00
Simon Glass
b413511611 phytec: Include env.h to permit reading the environment
This file reads from the environment but does not include the correct
header. Update it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-29 08:30:25 -06:00
Simon Glass
600145a8e1 venice: Include env.h to permit reading the environment
This file reads from the environment but does not include the correct
header. Update it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-29 08:30:25 -06:00
Simon Glass
0b9450989c net: Include string.h in net-legacy.h
This file uses memcpy() but does not include the header file. Update it.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-29 08:30:25 -06:00
Simon Glass
84a1c99055 imx8ulp_evk: Include env.h to permit reading the environment
This file reads from the environment but does not include the correct
header. Update it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-29 08:30:24 -06:00
Simon Glass
09c9957e88 dhelectronics: Include env.h to permit reading the environment
This file reads from the environment but does not include the correct
header. Update it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-29 08:30:24 -06:00
Simon Glass
67a7633e04 congatec: Include env.h to permit reading the environment
This file reads from the environment but does not include the correct
header. Update it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-05-29 08:30:24 -06:00
Tom Rini
05f6f6e8c7 net: Remove env_get_ip helper() function
Currently, we have the function env_get_ip which takes an IP address
in string form and returns a struct in_addr representation of that
address. It is however little used and means that a number of places
indirectly (and unclearly) get <env.h> via <net.h>. To clean this up
start by replacing env_get_ip() calls with string_to_ip() calls. This is
generally a no-op as env_get_ip(str) is an inline of
string_to_ip(env_get(str)) but in a few cases we can or already have
stored the result of env_get(str) and can save the additional call.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-05-29 08:30:24 -06:00
Tom Rini
e50dbb3a0a Merge patch series "Start removing <env.h> from headers when not required"
Tom Rini <trini@konsulko.com> says:

Given Simon's series at [1] I started looking in to what brings in
<env.h> when not strictly required and in turn has some unintended
implicit includes. This series takes care of the places where, commonly,
<linux/string.h> or <env.h> itself were required along with a few other
less common cases. This sets aside for the moment what to do about
net-common.h and env_get_ip() as I'm not entirely sure what's best
there.

[1]: https://patchwork.ozlabs.org/project/uboot/list/?series=454939&state=*
Link: https://lore.kernel.org/r/20250514225002.15361-1-trini@konsulko.com
2025-05-29 08:29:24 -06:00
Tom Rini
1e50f7457f include/command.h: Drop <env.h>
Now that all of the cases of code that relied on <command.h> to provide
<env.h> (or one of the headers that it includes, and so forth) have been
fixed, we can drop the include from here.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-05-29 08:29:16 -06:00
Tom Rini
dcb7d927d1 global: Avoid indirect inclusion of <env.h> from <command.h>
The include file <command.h> does not need anything from <env.h>.
Furthermore, include/env.h itself includes other headers which can lead
to longer indirect inclusion paths. To prepare to remove <env.h> from
<command.h> fix all of the places which had relied on this indirect
inclusion to instead include <env.h> directly.

Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org> # android, bcb
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> # spawn
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-05-29 08:29:16 -06:00
Tom Rini
d0e1ee6590 gpio: pca953x: Add missing <asm/byteorder.h>
This driver takes a long implicit include path to get this header which
it directly uses. Add it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-05-29 08:29:16 -06:00
Tom Rini
55717ca66f cmd/mem.c, test/cmd/mem_copy.c: Add <compiler.h>
These files require <compiler.h> in order to have MEM_SUPPORT_64BIT_DATA
be defined but currently rely on a long indirect include path to get it.
Add this directly.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-05-29 08:29:16 -06:00
Tom Rini
6430711849 global: Add <linux/string.h> instead of long indirect include path
In a number of cases we have C files which rely on a chain of indirect
include paths to get <linux/string.h> to be included via <command.h>. To
facilitate cleaning up <command.h> make this code directly include
<linux/string.h>.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-05-29 08:29:16 -06:00
Tom Rini
23be77e18d Merge patch series "regex patches"
Rasmus Villemoes <ravi@prevas.dk> says:

This started as a rather simple patch, 1/12, adding the ability to
more conveniently do regex matching in shell.

But with that, it became very easy to see what the slre library can
and especially what it cannot do, and that way I found both outright
bugs and a "wow, doesn't it support that syntax" gotcha. I couldn't
find any tests ('git grep slre -- test/' was empty), so I added a
small test suite and tweaked slre.c.

Link: https://lore.kernel.org/r/20250513084034.654865-1-ravi@prevas.dk
2025-05-29 08:27:13 -06:00
Rasmus Villemoes
ced883d92c test: slre: add tests for regex library
Inspecting the slre.c code reveals a few bugs; those are easy to
demonstrate with the new '=~' test operator. Before fixing them, let's
add a place to add test cases.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
2025-05-29 08:25:18 -06:00
Rasmus Villemoes
6990cc5257 doc: document test command
Add documentation for the test command, including the newly added =~
operator and some gotchas wrt. the numeric comparisons.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
2025-05-29 08:25:18 -06:00
Rasmus Villemoes
de6e54d74d test: slre: add tests for character ranges
The first of these, { "U-Boot", "^[B-Uo-t]*$", 0 }, would match
previously when the - and the letters were all interpreted literally.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
2025-05-29 08:25:18 -06:00
Rasmus Villemoes
fe4f211850 slre: implement support for ranges in character classes
When trying to use U-Boot's regex facility, it is a rather large
gotcha that [a-z] range syntax is not supported. It doesn't require a
lot of extra code to implement that; we just let the regular parsing
emit the start and end literal symbols as usual, and add a new
"escape" code RANGE.

At match time, this means the code will first just see an 'a' and try
to match that, and only then recognize that it's actually part of a
range and then do the 'a' <= ch <= 'z' test.

Of course, this means that a - in the middle of a [] pair no longer
matches a literal dash, but I highly doubt anybody relies on
that. Putting it first or last, or escaping it with \, as in most
other RE engines, continues to work.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
2025-05-29 08:25:18 -06:00
Rasmus Villemoes
4d08883556 test: slre: add test cases for escape char in character class
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
2025-05-29 08:25:18 -06:00
Rasmus Villemoes
5d3f91d6a8 slre: fix matching of escape sequence used inside character class
At the compile stage, the anyof() function clearly intends to handle escape
sequences like \d (for digits) inside square brackets, since the logic
emits a 0 byte followed by the code representing the character
class (NONSPACE, SPACE or DIGIT).

However, this is not handled in the corresponding match helper
is_any_of(); it just naively loops over all the bytes in the ->data
array emitted by anyof() and compares those directly to the current
character. For example, this means that the string "\x11" (containing
the single character with value 17) is matched by the regex "[#%\d]",
because DIGIT happens to be 17.

Fix that by recognizing a zero byte as indicating something special
and act accordingly. In order not to repeat the "increment *ofs and
return 1" in all places, put those two lines after a new match: label.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
2025-05-29 08:25:18 -06:00
Rasmus Villemoes
457f19815c slre: refactor is_any_but()
As preparation for fixing the handling of backslash-escapes used
inside a character class, refactor is_any_but() to be defined in terms
of is_any_of() so we don't have to repeat the same logic in two places.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
2025-05-29 08:25:18 -06:00
Rasmus Villemoes
ebdd78c487 test: slre: add some (negative) character class tests
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
2025-05-29 08:25:18 -06:00
Rasmus Villemoes
09b48305d3 test: slre: add more test cases
Add some tests for the "drop wrong anchored optimization". Without
the previous commit, the first, fifth and seventh of these would fail,
i.e. those:

	{ "xby", "^a|b", 1},
	{ "", "x*$", 1},
	{ "yy", "x*$", 1},

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
2025-05-29 08:25:18 -06:00
Rasmus Villemoes
19b3e24083 slre: drop wrong "anchored" optimization
The regex '^a|b' means "does the string start with a, or does it have
a b anywhere", not "does the string start with a or b" (the latter
should be spelled '^[ab]' or '^(a|b)'). It should match exactly the
same strings as 'b|^a'. But the current implementation hard-codes an
assumption that when the regex starts with a ^, the whole regex must
match from the beginning, i.e. it only attempts at offset 0.

It really should be completely symmetrical to 'b|c$' ("does it have a
b anywhere or end with c?"), which is treated correctly.

Another quirk is that currently the regex 'x*$', which should match
all strings (because it just means "does the string end
with 0 or more x'es"), does not, because in the unanchored case we
never attempt to match at ofs==len. In the anchored case, '^x*$', this
works correctly and matches exactly strings (including the empty
string) consisting entirely of x'es.

Fix both of these issues by dropping all use of the slre->anchored
member and always test at all possible offsets. If the regex does have
a ^ somewhere (including after a | branch character), that is
correctly handled by the match engine by only matching when *ofs is 0.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
2025-05-29 08:25:18 -06:00
Rasmus Villemoes
a5af8f9ad2 slre: add myself as maintainer
I guess that touching these files means "tag, you're it". That's fine
with me.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
2025-05-29 08:25:17 -06:00
Rasmus Villemoes
04044a567b cmd: test: add support for =~ operator
Currently, the only way to make use of regex matching in the shell is
by using "setexpr [g]sub" command. That's rather awkward for asking
whether a string matches a regex. At the very least, it requires
providing setexpr with a dummy target variable, but also, the return
value of setexpr doesn't say whether any substitutions were done, so
one would have to do some roundabout thing like

  env set dummy "${string_to_test}"
  setexpr sub dummy '<some regex>' ''
  if test "${dummy}" != "${string_to_test}" ; then ...

When CONFIG_REGEX is set, teach the test command a new operator, =~,
which will allow one to more naturally write

  if test "${string_to_test}" =~ '<some regex>' ; then ...

The =~ operator with similar functionality is also supported in bash
when using its "extended" test operator [[ ]].

Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
2025-05-29 08:25:17 -06:00
Tom Rini
2f3766949b Subtree merge tag 'v6.15-dts' of dts repo [1] into dts/upstream
[1] https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-05-27 11:07:10 -06:00
Tom Rini
a6b479b7ad Squashed 'dts/upstream/' changes from 955176a4ff59..fe2d6c49bb4e
fe2d6c49bb4e Merge tag 'v6.15-dts-raw'
3109849be809 Merge tag 'soc-fixes-6.15-3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
75e59270f7c5 Merge tag 'mvebu-fixes-6.15-1' of https://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into arm/fixes
69a2cec41405 Merge tag 'sunxi-fixes-for-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/fixes
64a925d7605a dt-bindings: can: microchip,mcp2510: Fix $id path
50d5bacc52a4 Merge tag 'v6.15-rc7-dts-raw'
b8973c10564b Merge tag 'soc-fixes-6.15-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
c88fc0f02e78 arm64: dts: marvell: uDPU: define pinctrl state for alarm LEDs
63756d9a84f8 Merge tag 'v6.15-rc6-dts-raw'
8de495f56dbd Merge tag 'input-for-v6.15-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
7346db7cb1f5 Merge tag 'imx-fixes-6.15-2' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixes
a12444223f6a arm64: dts: amazon: Fix simple-bus node name schema warnings
e605d5d7fe3d Merge tag 'asahi-soc-fixes-6.15' of https://github.com/AsahiLinux/linux into arm/fixes
fff11fe6a218 Merge tag 'riscv-sophgo-dt-fixes-for-v6.15-rc1' of https://github.com/sophgo/linux into arm/fixes
cbdc7e808a47 Merge tag 'amlogic-fixes-for-v6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux into arm/fixes
6569e1afaabb Merge tag 'v6.15-rockchip-dtsfixes1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/fixes
bad970d505c7 arm64: dts: imx8mp-var-som: Fix LDO5 shutdown causing SD card timeout
2498aef1d581 arm64: dts: imx8mp: use 800MHz NoC OPP for nominal drive mode
930a058ee559 Merge tag 'net-6.15-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
75e6b42a413a dt-bindings: net: ethernet-controller: Add informative text about RGMII delays
2fb1a42d2ab9 Merge tag 'soc-fixes-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
95bd2a8dfcd9 arm64: dts: amlogic: dreambox: fix missing clkc_audio node
84ef7812cc93 Merge tag 'v6.15-rc5-dts-raw'
724862669eee Merge tag 'spi-fix-v6.15-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
e56b01802fc8 riscv: dts: sophgo: fix DMA data-width configuration for CV18xx
f6364dd1ac42 arm64: dts: rockchip: fix Sige5 RTC interrupt pin
b6c1f156299d arm64: dts: st: Use 128kB size for aliased GIC400 register access on stm32mp23 SoCs
40c14b9e5f5e arm64: dts: st: Adjust interrupt-controller for stm32mp23 SoCs
62bf1a9664d4 arm64: dts: st: Use 128kB size for aliased GIC400 register access on stm32mp21 SoCs
fccc8448c30a arm64: dts: st: Adjust interrupt-controller for stm32mp21 SoCs
ad0c99d174ea arm64: dts: st: Use 128kB size for aliased GIC400 register access on stm32mp25 SoCs
282b9c077aae arm64: dts: st: Adjust interrupt-controller for stm32mp25 SoCs
3755c90eab9c Merge tag 'imx-fixes-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixes
b4c1abf11ff1 Merge tag 'juno-fix-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into arm/fixes
c7c3c68f3ce7 dt-bindings: mediatek,mt6779-keypad: Update Mattijs' email address
e4820115982e Merge tag 'v6.15-rc4-dts-raw'
5a4f16f09fb5 arm64: dts: imx8mm-verdin: Link reg_usdhc2_vqmmc to usdhc2
98e5be0c34f6 Revert "arm64: dts: allwinner: h6: Use RSB for AXP805 PMIC connection"
d6354f04cfe0 arm64: dts: rockchip: Assign RT5616 MCLK rate on rk3588-friendlyelec-cm3588
22b5bf714835 arm64: dts: rockchip: Align wifi node name with bindings in CB2
f7cb03107c26 Merge tag 'char-misc-6.15-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc
4acdc261f422 spi: dt-bindings: snps,dw-apb-ssi: Add compatible for SOPHGO SG2042 SoC
2ebbc79f9b14 spi: dt-bindings: snps,dw-apb-ssi: Merge duplicate compatible entry
08939b65ca58 arm64: dts: amlogic: g12: fix reference to unknown/untested PWM clock
73915dad61e7 arm64: dts: amlogic: gx: fix reference to unknown/untested PWM clock
fb321fd7cecd ARM: dts: amlogic: meson8b: fix reference to unknown/untested PWM clock
1499bef2c3a6 ARM: dts: amlogic: meson8: fix reference to unknown/untested PWM clock
a831b6c1c6b9 ARM: dts: opos6ul: add ksz8081 phy properties
3ae5c171fc05 arm64: dts: imx95: Correct the range of PCIe app-reg region
f118c5265c25 arm64: dts: imx8mp: configure GPU and NPU clocks in nominal DTSI
e281122066ea Merge tag 'v6.15-rc3-dts-raw'
1d7ab1ed4277 arm64: dts: apple: touchbar: Mark ps_dispdfr_be as always-on
b0dbfc0c19d7 dt-bindings: soc: fsl: fsl,ls1028a-reset: Fix maintainer entry
775d526af58f dt-bindings: timer: renesas,tpu: remove obsolete binding
739bb43d33b7 dt-bindings: nvmem: Add compatible for MSM8960
52f7f735cf15 dt-bindings: nvmem: Add compatible for IPQ5018
aeb6cb0b5324 dt-bindings: nvmem: fixed-cell: increase bits start value to 31
3a7b208d9e79 dt-bindings: nvmem: Add compatible for MS8937
1c27fc6ffa8e dt-bindings: nvmem: qfprom: Add X1E80100 compatible
d35d917d5816 dt-bindings: nvmem: rockchip,otp: Add compatible for RK3576
759e7828fe78 dt-bindings: nvmem: rockchip,otp: add missing limits for clock-names
e73a3d952883 arm64: dts: morello: Fix-up cache nodes
8386b46f9eda arm64: dts: rockchip: Fix mmc-pwrseq clock name on rock-pi-4
6b71f5ae1a2a arm64: dts: rockchip: Use "regulator-fixed" for btreg on px30-engicam for vcc3v3-btreg
2ed5901a514b dt-bindings: timer: nxp,sysctr-timer: Add i.MX94 support
e58a2db4c38c dt-bindings: interrupt-controller: fsl,irqsteer: Add i.MX94 support
622ce6b1ba08 dt-bindings: display: nwl-dsi: Allow 'data-lanes' property for port@1
e0ef023c67c0 dt-bindings: xilinx: Remove myself from maintainership
0449e8973a84 Merge tag 'v6.15-rc1-dts-raw'
b2db21710501 arm64: dts: rockchip: Add pinmuxing for eMMC on QNAP TS433
28265b46ce50 arm64: dts: rockchip: Remove overdrive-mode OPPs from RK3588J SoC dtsi
314cea8948b0 arm64: dts: rockchip: Allow Turing RK1 cooling fan to spin down
4314a01898d6 Merge tag 'input-for-v6.15-rc0' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
fcf2048dc9de Merge branch 'next' into for-linus
ba6c6579c9bd Merge tag 'riscv-for-linus-6.15-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
58f1d4c158c0 Merge tag 'rtc-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux
29912193033d Merge tag 'usb-6.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb
937ed4db2ab8 Merge tag 'tty-6.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty
ac589474b57a Merge tag 'thermal-6.15-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
6879712ce88d Merge tag 'i3c/for-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/i3c/linux
af2574352383 Merge tag 'linux-watchdog-6.15-rc1' of git://www.linux-watchdog.org/linux-watchdog
e81f3d825b82 Merge tag 'i2c-for-6.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux
bd876bc870df Merge tag 'dmaengine-6.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine
42065dec6c72 Merge tag 'phy-for-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy
301007542d03 Merge tag 'char-misc-6.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc
33b10181f970 Merge tag 'mm-nonmm-stable-2025-03-30-18-23' of git://git.kernel.org/pub/scm/linux/kernel/git/akpm/mm
d4643a038924 Merge patch series "Add some validation for vector, vector crypto and fp stuff"
cac1aa08f484 dt-bindings: rtc: max31335: Add max31331 support
26e04cf9cc79 Merge tag 'mailbox-v6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/jassibrar/mailbox
576a6900f13c Merge tag 'for-v6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/sre/linux-power-supply
78a2eae6cb86 Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
4194f888d6d6 Merge tag 'rproc-v6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/remoteproc/linux
c96994fe39c1 Merge tag 'pinctrl-v6.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
a42296696853 Merge tag 'backlight-next-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/backlight
6d0f08e93b76 Merge tag 'leds-next-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/leds
3bb45cc2ceab Merge tag 'mfd-next-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd
72713c04060a Merge tag 'mips_6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux
17102f25116b Merge tag 'devicetree-for-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
e44d9139748a Merge tag 'v6.15-p1' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6
b727a6e37d16 Merge tag 'pci-v6.15-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci
b1ec05cb6a63 Merge tag 'drm-next-2025-03-28' of https://gitlab.freedesktop.org/drm/kernel
34c876511338 Merge tag 'for-6.15/io_uring-reg-vec-20250327' of git://git.kernel.dk/linux
ddb37d4776e9 Merge tag 'for-6.15/io_uring-rx-zc-20250325' of git://git.kernel.dk/linux
c0a3226a4218 dt-bindings: i2c: snps,designware-i2c: describe Renesas RZ/N1D variant
f8da42670dd8 Merge tag 'powerpc-6.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux
38106689da03 dt-bindings: edac: altera: socfpga: Convert to YAML
7fa97aa2cc14 dt-bindings: pps: gpio: Correct indentation and style in DTS example
bc13b6ac45ca Merge branch 'pci/controller/xilinx-cpm'
51fe3683d562 Merge branch 'pci/controller/qcom'
14635816113e Merge branch 'pci/controller/mediatek'
c27d458c9018 Merge branch 'pci/controller/brcmstb'
910bd393ba5a Merge branch 'pci/controller/amd-mdb'
99abd782f5d4 Merge branch 'pci/controller/altera'
2b19e48fbedc Merge branch 'pci/dt-bindings'
ce77e68fec79 Merge tag 'soc-arm-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
c849f132da6e Merge tag 'soc-drivers-6.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
253861a5926a Merge tag 'soc-dt-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
b171384a2380 Merge tag 'net-next-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next
725971c9baeb Merge tag 'iommu-updates-v6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/iommu/linux
f39cd579edb7 Merge tag 'scsi-misc' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi
7f1c5dc0d96a Merge tag 'ata-6.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/libata/linux
1262e5915578 dt-bindings: mailbox: qcom: add compatible for MSM8226 SoC
e81c74aaf2e0 dt-bindings: mailbox: fsl,mu: Add i.MX94 compatible
f4f5865e81fd dt-bindings: mailbox: mediatek: Add support for MT8196 GCE mailbox
e054cac9ae6e Merge tag 'timers-clocksource-2025-03-26' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
b03526c21450 Merge branches 'clk-allwinner', 'clk-amlogic' and 'clk-qcom' into clk-next
a50392a2baf3 Merge branches 'clk-rockchip', 'clk-samsung' and 'clk-imx' into clk-next
e595cb4e5772 Merge branches 'clk-parent', 'clk-renesas', 'clk-mediatek' and 'clk-cleanup' into clk-next
dbd546c62c5c Merge tag 'mtd/for-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux
2eecb8cbb591 Merge tag 'platform-drivers-x86-v6.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pdx86/platform-drivers-x86
9d2cd6a3b1d5 Merge tag 'nand/for-6.15' into mtd/next
bd76b77d4e2c Merge tag 'sound-6.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound
2f3a8d13a1be Merge tag 'media/v6.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media
01edfbe94231 Merge tag 'pmdomain-v6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/linux-pm
33e6daed2dcb Merge tag 'mmc-v6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc
f661bbffece6 Merge tag 'gpio-updates-for-v6.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux
d98043246fc3 Merge tag 'hwmon-for-v6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging
f88a116702ac Merge tag 'pwm/for-6.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/ukleinek/linux
c1e80718e7c0 Merge tag 'spi-v6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
903bc8c7edc1 Merge tag 'regulator-v6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator
34d2a8ce3d44 Merge tag 'pm-6.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
be3477545a1b Merge tag 'for-net-next-2025-03-25' of git://git.kernel.org/pub/scm/linux/kernel/git/bluetooth/bluetooth-next
f46587488060 dt-bindings: thermal: Correct indentation and style in DTS example
ed91ea537f6b dt-bindings: thermal: Update for BCM74110
b56a3bd46a79 dt-bindings: thermal: tsens: Add ipq5332, ipq5424 compatible
408f714c8807 Merge tag 'irq-drivers-2025-03-23' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
2c7bdd5acc6a dt-bindings: net: bluetooth: nxp: Add support to set BD address
c878bbbc7198 dt-bindings: net: bluetooth: qualcomm: document WCN3950
3ddbb8fb8fe6 dt-bindings: net: bluetooth: nxp: Add wakeup pin properties
a4c451f881ed dt-bindings: net: qcom,ipa: Correct indentation and style in DTS example
86a6733d63fe Merge tag 'wireless-next-2025-03-20' of https://git.kernel.org/pub/scm/linux/kernel/git/wireless/wireless-next
8604a4e6caa1 dt-bindings: net: rockchip-dwmac: Add compatible string for RK3528
cacfdfd63704 dt-bindings: riscv: document vector crypto requirements
c9835a4f0732 dt-bindings: riscv: add vector sub-extension dependencies
b21477b0a350 dt-bindings: riscv: d requires f
a77e47812f3f dt-bindings: watchdog: sunxi: add Allwinner A523 compatible string
bf3232c697af Merge tag 'i2c-host-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/andi.shyti/linux into i2c/for-mergewindow
8f6d11a83a0a Merge tag 'docs-6.15' of git://git.lwn.net/linux
35477e322ba4 dt-bindings: PCI: Add common schema for devices accessible through PCI BARs
a345b6688502 Merge tag 'asoc-v6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into for-next
2baf484b277c Merge branch 'pm-cpufreq'
67a34184ddf2 dt-bindings: timer: Add SiFive CLINT2
2ddeb4d36e67 Merge tag 'cpufreq-arm-updates-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/vireshk/pm
f8ec1f1d1cc5 dt-bindings: remoteproc: Consolidate SC8180X and SM8150 PAS files
98322a22c22a dt-bindings: hwmon: Add Microchip emc2305 support
e80e09439582 media: dt-bindings: mediatek,vcodec-encoder: Drop assigned-clock properties
d8cea587c006 docs: dt-bindings: Specify ordering for properties within groups
83d44c13a32f dt-bindings: hwmon: Drop stray blank line in the header
28e3e5da1d38 dt-bindings: mfd: syscon: Add microchip,sama7d65-sfrbu
cdb8f10e1aaa dt-bindings: mfd: syscon: Add microchip,sama7d65-ddr3phy
723b3cd19dd1 dt-bindings: i2c: spacemit: add support for K1 SoC
c8e7edc109e3 dt-bindings: i2c: omap: Add mux-states property
6cd4c93c1892 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
0e19f27df8f7 Merge tag 'amlogic-arm-dt-for-v6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux into soc/dt
c65eff2dbcf7 Merge tag 'amlogic-arm64-dt-for-v6.15-v2' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux into soc/dt
bebc6d8370bf ASoC: wm8904: Add DMIC and DRC support
23803d09fa1b dt-bindings: serial: snps-dw-apb-uart: document RZ/N1 binding without DMA
eb71e94b0058 dt-bindings: serial: snps-dw-apb-uart: Add support for rk3562
819c0d972e58 dt-bindings: serial: fsl-lpuart: support i.MX94
da1dc4f87d0d dt-bindings: serial: samsung: add exynos7870-uart compatible
0791859ab251 Merge tag 'coresight-next-v6.15' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/coresight/linux into char-misc-next
1c289ddb61bc ASoC: dt-bindings: wm8904: Add DMIC, GPIO, MIC and EQ support
64345bc61380 spi: dt-bindings: cdns,qspi-nor: Require some peripheral properties
00c70a06c714 spi: dt-bindings: cdns,qspi-nor: Deprecate the Cadence compatible alone
c7b9fed01f76 spi: dt-bindings: cdns,qspi-nor: Be more descriptive regarding what this controller is
2951fd5da291 arm64: dts: Add gpio_intc node for Amlogic A5 SoCs
b7ea7dda1e2e arm64: dts: Add gpio_intc node for Amlogic A4 SoCs
06138f903a3c Merge branches 'apple/dart', 'arm/smmu/updates', 'arm/smmu/bindings', 'rockchip', 's390', 'core', 'intel/vt-d' and 'amd/amd-vi' into next
8495ad389173 Merge tag 'dt-cleanup-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt into soc/dt
a301f99cf614 Merge tag 'tegra-for-6.15-arm-dt' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt
cd03551a294d dt-bindings: gpu: arm,mali-midgard: add exynos7870-mali compatible
5b84d726ddaf Merge tag 'qcom-drivers-for-6.15-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers
f10573df66cb Merge tag 'qcom-drivers-for-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers
fa143ab38af1 Merge tag 'amlogic-drivers-for-v6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux into soc/drivers
bab3f090d9d3 Merge tag 'reset-for-v6.15' of git://git.pengutronix.de/pza/linux into soc/drivers
e13001093d96 Merge tag 'samsung-drivers-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/drivers
56c3ca45c2c7 Merge tag 'at91-soc-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into soc/arm
3b1e6f959fee Merge tag 'hisi-arm64-dt-for-6.15' of https://github.com/hisilicon/linux-hisi into soc/dt
75357dfed634 Merge tag 'riscv-dt-for-v6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt
9737b7a849d5 Merge tag 'omap-for-v6.15/dt-signed' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap into soc/dt
6432c5392792 Merge tag 'riscv-sophgo-dt-for-v6.15' of https://github.com/sophgo/linux into soc/dt
481e67465dc8 Merge tag 'mvebu-dt64-6.15-1' of https://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into soc/dt
96e8744cc103 Merge tag 'v6.15-rockchip-dts64-2' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
81ed54132fc0 Merge tag 'zynq-dt-for-6.15' of https://github.com/Xilinx/linux-xlnx into soc/dt
0a2824017157 Merge tag 'zynqmp-dt-for-6.14' of https://github.com/Xilinx/linux-xlnx into soc/dt
4e48222bf65f Merge tag 'sunxi-dt-for-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into soc/dt
b831e4e9bb20 Merge tag 'at91-dt-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into soc/dt
6faf8a6c4970 Merge tag 'stm32-dt-for-v6.15-1' of https://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into soc/dt
29c62c6339a6 dt-bindings: deprecate "snps,en-tx-lpi-clockgating" property
ac676ad15ceb ARM: dts: stm32: remove "snps,en-tx-lpi-clockgating" property
a3aeb65b5e21 riscv: dts: starfive: remove "snps,en-tx-lpi-clockgating" property
86032de3cc2d Merge tag 'ieee802154-for-net-next-2025-03-10' of git://git.kernel.org/pub/scm/linux/kernel/git/wpan/wpan-next
e3ae9db04517 dt-bindings: riscv: add Zaamo and Zalrsc ISA extension description
0cb4c6d785dc dt-bindings: i2c: i2c-rk3x: Add rk3562 support
3b5a8c070c44 dt-bindings: i2c: imx-lpi2c: add i.MX94 LPI2C
ce1e60e777db dt-bindings: i2c: qup: Document interconnects
ac988bf5af32 dt-bindings: i2c: qcom,i2c-qup: Document power-domains
9bcf0325b6ae dt-bindings: i2c: exynos5: add exynos7870-hsi2c compatible
497c36ba820d dt-bindings: i2c: samsung,s3c2410: add exynos7870-i2c compatible
2ba4ea354217 dt-bindings: mtd: atmel,dataflash: convert txt to yaml
3813b6843768 dt-bindings: mtd: gpmi-nand: Add compatible string for i.MX8 chips
4ba959479642 ASoC: codecs: Add aw88166 amplifier driver
559db5bb3df6 add sof support on imx95
f42c1e48e1ea dt-bindings: hwmon: Add description for sensor HTU31
3e54d6806c68 spi: Merge up fixes
c4c47e5bb42f regulator: dt-bindings: rtq2208: Cleanup whitespace
1aae375c7c42 regulator: dt-bindings: rtq2208: Mark fixed LDO VOUT property as deprecated
6cf18ee31953 Merge patch series "riscv: Add bfloat16 instruction support"
f306f44643f3 dt-bindings: riscv: add bfloat16 ISA extension description
d1349a8d0aa7 arm64: dts: hi3660: Add property for fixing CPUIdle
8283ad10d5c2 Merge tag 'samsung-pinctrl-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung into devel
bba239dcd4d7 Merge net-next/main to resolve conflicts
ee0acddba296 dt-bindings: rtc: pcf2127: Reference spi-peripheral-props.yaml
eb3c4568ad0b dt-bindings: hwmon: ti,ina2xx: Add INA233 device
26e91a5c1c4d ASoC: dt-bindings: audio-graph-card2: add widgets and hp-det-gpios support
20f74f1fc993 ASoC: dt-bindings: support imx95's CM7 core
79ab7f994af8 Merge branch '20250313110359.242491-1-quic_mmanikan@quicinc.com' into clk-for-6.15
1a7ee5fd2be3 dt-bindings: clock: Add ipq9574 NSSCC clock and reset definitions
7665c77f7cdb dt-bindings: clock: gcc-ipq9574: Add definition for GPLL0_OUT_AUX
832929f7a52a dt-bindings: hwmon: ltc2978: add support for LT717x
7758dfded334 dt-bindings: pinctrl: qcom: Add egpio function for sa8775p
f2341866dbb8 dt-bindings: pinctrl: airoha: Add missing gpio-ranges property
9abb426254c5 dt-bindings: pinctrl: at91-pio4: add microchip,sama7d65-pinctrl
d3812cbd3cf5 dt-bindings: rtc: qcom-pm8xxx: document qcom,no-alarm flag
d2d31cf30f25 dt-bindings: interrupt-controller: Add support for Amlogic A4 and A5 SoCs
91922237393f Merge tag 'v6.14-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux into gpio/for-next
49186c87530a dt-bindings: thermal: give OS some leeway in absence of critical-action
b7e2002c7f37 dt-bindings: cpufreq: cpufreq-qcom-hw: Narrow properties on SDX75, SA8775p and SM8650
d3db8a0a1e18 dt-bindings: cpufreq: cpufreq-qcom-hw: Drop redundant minItems:1
9b493bef6c64 dt-bindings: cpufreq: cpufreq-qcom-hw: Add missing constraint for interrupt-names
a0842ec452cb dt-bindings: cpufreq: cpufreq-qcom-hw: Add QCS8300 compatible
08344f6cf323 dt-bindings: clock: qcom,x1e80100-camcc: Fix the list of required-opps
b58d82c6f35a ASoC: dt-bindings: fsl,sai: Add i.MX94 support
52fcce301d62 regulator: dt-bindings: pca9450: Add nxp,pf9453 compatible string
5a327e9ff15c ASoC: dt-bindings: mediatek,mt8188-mt6359: Add mediatek,accdet
9d8dfb82b770 ASoC: dt-bindings: Add schema for "awinic,aw88166"
b21759520198 dt-bindings: phy: rockchip: Add rk3562 naneng-combophy compatible
3f127f8b13cf dt-bindings: phy: Add Rockchip MIPI C-/D-PHY schema
7fdfaa5e1649 arm64: dts: rockchip: remove ethm0_clk0_25m_out from Sige5 gmac0
e532d69208c3 arm64: dts: marvell: Use preferred node names for "simple-bus"
36438541d5f0 arm64: dts: marvell: Drop unused CP11X_TYPE define
a6ee6a6bd390 arm64: dts: marvell: Move arch timer and pmu nodes to top-level
dc3b5c12e6a4 dt-bindings: rng: rockchip,rk3588-rng: Drop unnecessary status from example
2df156046328 Merge tag 'ti-k3-dt-for-v6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into soc/dt
f57059f434cd Merge tag 'imx-dt64-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt
4378c7352b85 Merge tag 'imx-dt-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt
81231b09fca0 Merge tag 'imx-bindings-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt
f185c678c9a4 Merge tag 'spacemit-dt-for-6.15-1' of https://github.com/spacemit-com/linux into soc/dt
c18007158dda Merge tag 'davinci-updates-for-v6.15-rc1' of https://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux into soc/dt
d24528c09c20 arm64: dts: rockchip: Fix PWM pinctrl names
2e5608c86650 arm64: dts: rockchip: fix RK3576 SCMI clock IDs
52dc545f0788 dt-bindings: clock: rk3576: add SCMI clocks
24b2d3f6703c arm64: dts: rockchip: Fix pcie reset gpio on Orange Pi 5 Max
8f7a008a36a0 Merge tag 'samsung-dt64-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt
02def44715b4 Merge tag 'asahi-soc-dt-6.15-v3' of https://github.com/AsahiLinux/linux into soc/dt
50a5056a0fbc Merge tag 'v6.15-rockchip-dts64-1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
abd4cba3fc31 Merge tag 'tegra-for-6.15-arm64-dt-v2' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt
a8cb4de20f8e Merge tag 'tegra-for-6.15-dt-bindings' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt
920fc9d1facb arm64: dts: amd/seattle: Drop undocumented "spi-controller" properties
7303c3977e4a arm64: dts: amd/seattle: Fix bus, mmc, and ethernet node names
bdc46b592528 arm64: dts: amd/seattle: Move and simplify fixed clocks
5767b5ef37dc arm64: dts: amd/seattle: Base Overdrive B1 on top of B0 version
f66a26fc5063 Merge tag 'renesas-dts-for-v6.15-tag2' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
f94bc208615f dt-bindings: mfd: syscon: Add the pbus-csr node for Airoha EN7581 SoC
a6586b520e84 bindings: pinctrl: ingenic: add x1600
c5f11db1dc9c dt-bindings: mfd: syscon: Add rk3528 QoS register compatible
99b871852f02 dt-bindings: mfd: atmel,sama5d2-flexcom: Add microchip,sama7d65-flexcom
cee62549c1cf dt-bindings: mfd: qcom,tcsr: Add compatible for MSM8937
4b2dbbdb1106 dt-bindings: mfd: samsung,s2mps11: Add compatible for s2mpu05-pmic
e53b55f7425b dt-bindings: regulator: Add TI TPS65214 PMIC bindings
b70d9d3353c8 dt-bindings: regulator: Add TI TPS65215 PMIC bindings
f8f2120feff1 dt-bindings: mfd: Convert fsl,mcu-mpc8349emitx binding to YAML
fabf15359158 dt-bindings: mfd: stm32-timers: Add support for stm32mp25
27070527c9da Merge branches 'ib-mfd-input-leds-power-6.15', 'ib-mfd-power-6.15' and 'ib-mfd-regulator-6.15' into ibs-for-mfd-merged
3cfc089d7aee dt-bindings: can: fsl,flexcan: add i.MX94 support
e0c8c7d1cba3 dt-bindings: can: fsl,flexcan: add transceiver capabilities
867ef82b4496 dt-bindings: usb: qcom,dwc3: Synchronize minItems for interrupts and -names
4cfef97e6f55 Merge tag 'iio-for-6.15a' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/jic23/iio into char-misc-next
2bbf5d333bbb Merge tag 'mediatek-drm-next-6.15-v2' of https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux into drm-next
1e57f81382d5 arm64: dts: freescale: Add support for the GOcontroll Moduline Display
5eb64fd18835 ASoC: sun4i-codec: add headphone dectection for
7818917a7583 dt-bindings: clocks: atmel,at91rm9200-pmc: add missing compatibles
6144fc934c1d dt-bindings: reset: fix double id on rk3562-cru reset ids
cb698afb24b8 dt-bindings: spi: add compatibles for mt7988
c6d6437dbad2 dt-bindings: remoteproc: Add SM8750 MPSS
16f807a2f799 dt-bindings: power: qcom,kpss-acc-v2: add qcom,msm8916-acc compatible
9f908c3d4e3d ASoC: dt-bindings: sun4i-a10-codec: add hp-det-gpios
1cf4588d69c5 dt-bindings: connector: Add the GOcontroll Moduline module slot bindings
dcf3f572da06 dt-bindings: vendor-prefixes: add GOcontroll
fac0b8b2d03e ASoC: dt-bindings: tas2770: add compatible for TAS5770L
8af38e87bf30 ASoC: dt-bindings: tas27xx: add compatible for SN012776
7aa416c35ed5 arm64: dts: rockchip: Enable HDMI audio output for ArmSoM Sige7
bd4c8a1c08f9 arm64: dts: rockchip: Enable onboard eMMC on Radxa E20C
db7a99c423de arm64: dts: rockchip: Add SDHCI controller for RK3528
29d894b16a31 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
5857b1d7ade2 arm64: dts: rockchip: Remove bluetooth node from rock-3a
8464126790be arm64: dts: rockchip: Move rk356x scmi SHMEM to reserved memory
208e3a0a442e dt-bindings: clock: qcom: Add compatible for QCM6490 boards
b92c36eff4bf dt-bindings: clock: ti: Convert ti-clkctrl.txt to json-schema
0e87b6717e3c dt-bindings: dsp: fsl,dsp: Add resets property
6cc91fdea94d dt-bindings: reset: audiomix: Add reset ids for EARC and DSP
28a2aabbb6c4 dt-bindings: pinctrl: add compatible for Allwinner A523/T527
6b4d5de72979 dt-bindings: power: Add TH1520 SoC power domains
a441545e25fc dt-bindings: firmware: thead,th1520: Add support for firmware node
ecbefc112b34 regulator: dt-bindings: add documentation for s2mpu05-pmic regulators
678f2f84e7f4 dt-bindings: net: Define interrupt constraints for DWMAC vendor bindings
228d9ce5d3bb dt-bindings: net: rockchip-dwmac: Require rockchip,grf and rockchip,php-grf
20bbb3d2c8e7 dt-bindings: firmware: imx: add property reset-controller
5ba7b84e7bf0 dt-bindings: reset: atmel,at91sam9260-reset: add sam9x7
568847bfd352 dt-bindings: display: mediatek: dpi: add power-domains example
32e09f864be1 arm64: dts: st: add stm32mp215f-dk board support
559d24b54b4e dt-bindings: stm32: document stm32mp215f-dk board
da2175c8eedc arm64: dts: st: introduce stm32mp21 SoCs family
050105727605 arm64: dts: st: add stm32mp235f-dk board support
8a79caa82a70 dt-bindings: stm32: document stm32mp235f-dk board
6abc5bf17ba1 arm64: dts: st: introduce stm32mp23 SoCs family
e95c2526d6e9 dt-bindings: stm32: add STM32MP21 and STM32MP23 compatibles for syscon
c8aa9617a955 arm64: dts: st: add stm32mp257f-dk board support
5a615c7759c9 dt-bindings: stm32: document stm32mp257f-dk board
fa94a630d90d dt-bindings: watchdog: renesas,wdt: Document RZ/G3E support
c0aabcef7b8d dt-bindings: mmc: sunxi: add compatible strings for Allwinner A523
2486f6c1b421 dt-bindings: mmc: sunxi: Simplify compatible string listing
8ca3040b05de dt-bindings: mmc: sdhci-of-dwcmhsc: Add compatible string for RK3528
5b36bb4f4707 dt-bindings: mmc: rockchip-dw-mshc: Add compatible string for RK3528
8462dd3e6881 dt-bindings: mmc: renesas,sdhi: Document RZ/G3E support
d274a3df0a12 dt-bindings: mmc: rockchip-dw-mshc: Add support for rk3562
56b744861176 dt-bindings: mmc: Add support for rk3562 eMMC
eb9b6eec2dda arm64: dts: rockchip: Add AP6275P wireless support to ArmSoM Sige7
906b8cbb8d43 arm64: dts: rockchip: Enable HDMI audio outputs for Orange Pi 5 Plus
19e0533172f2 arm64: dts: rockchip: Enable HDMI1 on Orange Pi 5 Plus
0bbaa0ff4c09 arm64: dts: rockchip: Enable HDMI audio outputs for Orange Pi 5 Max
173563eb6666 arm64: dts: rockchip: Enable HDMI0 audio output for Orange Pi 5/5B
9895a2f169dd dt-bindings: clk: sunxi-ng: document two Allwinner A523 CCUs
b8f6cd67f8b3 dt-bindings: trivial-devices: Add Maxim max15301, max15303, and max20751
fc5147dfc750 dt-bindings: fsi: ibm,p9-scom: Add "ibm,fsi2pib" compatible
5f06f892eb53 Backmerge tag 'v6.14-rc6' into drm-next
fb0e8021a68f dt-bindings: iio: adc: Add i.MX94 and i.MX95 support
e15adeb19f02 dt-bindings: iio: adc: add AD7191
33496024fc8e dt-bindings: mmc: atmel,hsmci: Convert to json schema
7ab9faf87206 dt-bindings: mmc: mmc-slot: Make compatible property optional
ff4a69b28cf8 dt-bindings: mmc: fsl-imx-esdhc: Add i.MX94 support
b6c174fc7de2 dt-bindings: mmc: Change to additionalProperties to fix fail detect Unevaluated property
502377fe32de dt-bindings: mmc: samsung,exynos-dw-mshc: add exynos7870 support
d6ee3c852b25 dt-bindings: PCI: xilinx-cpm: Add compatible string for CPM5NC Versal Net host
a19185cc15d1 Merge tag 'at24-updates-for-v6.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux into i2c/for-mergewindow
0677248b0e32 dt-bindings: arm-smmu: Document QCS8300 GPU SMMU
efd6b0348bfa dt-bindings: spi: add SG2044 SPI NOR controller driver
d0f43207a01a dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the QCS8300 QMP PCIe PHY Gen4 x2
8d4b83e94b40 dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: document the SM8750 QMP UFS PHY
eeae88998b40 dt-bindings: phy: qcom,uniphy-pcie: Document PCIe uniphy
26a91c680522 ARM: dts: stm32: Add Plymovent AQM devicetree
4c21b9c842e3 ARM: dts: stm32: Add pinmux groups for Plymovent AQM board
904f0d522b88 dt-bindings: arm: stm32: Add Plymovent AQM board
a3a3221056c9 dt-bindings: sound: convert ICS-43432 binding to YAML
2f91de2a490b ARM: dts: apalis/colibri-imx6: Add support for v1.2
9eb0618252aa ARM: dts: apalis/colibri-imx6: Enable STMPE811 TS
f758e0d13235 dt-bindings: arm: fsl: Add VAR-SOM-MX6UL SoM and Concerto board
f76216ee5bc2 ARM: dts: imx6ul: Add Variscite Concerto board support
dd6e0d48db76 ARM: dts: imx6ul: Add Variscite VAR-SOM-MX6UL SoM support
b3d9184831ad arm64: dts: imx8qm-apalis: Remove compatible from SoM dtsi
517caee96f7e ARM: dts: vf610-colibri: Remove compatible from SoM dtsi
5656930f43b4 ARM: dts: imx6qdl-apalis/colibri: Remove compatible from SoM dtsi
fad232a946b4 dt-bindings: arm: fsl: drop usage of Toradex SOMs compatible alone
ea11d8d98354 arm64: dts: imx8mp: change AUDIO_AXI_CLK_ROOT freq. to 800MHz
0b17f7c82b59 arm64: dts: imx8mp: add AUDIO_AXI_CLK_ROOT to AUDIOMIX block
2bc9da478485 arm64: dts: imx93: add ddr edac support
ab9bf8d19072 arm64: dts: imx95: add ref clock for pcie nodes
1ad5ffe68e35 arm64: dts: mba8xx: Remove invalid property disable-gpio
ef030623665a ARM: dts: imx6ul-tqma6ul1: Change include order to disable fec2 node
1c284ff7a69f arm64: dts: imx8qm-ss-hsio: Wire up DMA IRQ for PCIe
4456f7d29f3a arm64: dts: im8mq-librem5: move dwc3 usb port under ports
9a66f214f03d arm64: dts: mba8mx: change sound card model name
4749d122ddde arm64: dts: imx8mp-tqma8mpql-mba8mpxl: change sound card model name
5269104e27e3 arm64: dts: s32g: add FlexCAN[0..3] support for s32g2 and s32g3
71b653961ab8 dt-bindings: arm: fsl: add i.MX95 15x15 EVK board
1ebef3515785 arm64: dts: imx95: Add imx95-15x15-evk support
9726256fedee arm64: dts: imx95: Add i3c1 and i3c2
94ef2b4371a4 arm64: dts: imx95: Add #io-channel-cells = <1> for adc node
d73e4f93cd40 ARM: dts: imx53-mba53: Fix the PCA9554 compatible
acd5a974e760 ARM: dts: imx31: Use nand-controller as node name
81ad2fe2f7b5 ARM: dts: vfxxx: Fix the order of the DMA entries
5447ae84fa8f ARM: dts: tqma7: Add partitions subnode to spi-nor
1ccfa18431b4 ARM: dts: imx7-tqma7: Add vcc-supply for spi-nor
1743d93ea655 ARM: dts: tqma6ul: Add partitions subnode to spi-nor
acde6cbf9cdf ARM: dts: imx6ul-tqma6ul: Add vcc-supply for spi-nor
c3ce52f0a98e ARM: dts: imx6ul-tqma6ul: Order DT properties
83b725debc91 ARM: dts: imx6qdl-tqma6: Add partitions subnode to spi-nor
4169f66d2bb7 ARM: dts: imx6qdl-tqma6: use sw4_reg as 3.3V supply
851b1c7d93cb ARM: dts: imx6qdl-tqma6: limit PMIC SW4 to 3.3V
2cb7d799b230 ARM: dts: imx6qdl-tqma6: Order DT properties
d4c064aa4ec4 arm64: dts: imx8mp-skov: support new 7" panel board
c8cb767887b4 arm64: dts: imx8mp-skov: add revC BD500 board
ea4b50b721d7 arm64: dts: imx8mp-skov: describe I2C bus recovery for all controllers
93fe81be94fe arm64: dts: imx8mp-skov: move I2C2 pin control group into DTSI
4e3e1bd5602f arm64: dts: imx8mp-skov: add basic board as fallback
26e62120b67b dt-bindings: arm: fsl: add more compatibles for Skov i.MX8MP variants
d9eebb23bec4 arm64: dts: freescale: imx8mp-skov: operate SoC in nominal mode
1dd517527ec2 arm64: dts: freescale: imx8mp-skov: configure LDB clock automatically
9fe870aa5fbb arm64: dts: imx8mp: add fsl,nominal-mode property into nominal.dtsi
36d591413641 arm64: dts: imx8mp: Add optional nominal drive mode DTSI
04b0ce30ed9a Merge patch series "scsi: ufs: renesas: Add support for R-Car S4-8 ES1.2"
c0c684cc130f scsi: ufs: dt-bindings: renesas,ufs: Add calibration data
fc09bffd40a1 arm64: dts: imx8mp: configure GPU and NPU clocks to overdrive rate
bd3329807adb arm64: dts: freescale: ten64: add usb hub definition
4057bd794cb2 Merge tag 'drm-msm-next-2025-03-09' of https://gitlab.freedesktop.org/drm/msm into drm-next
31ae3a9262da dt-bindings: dma: snps,dw-axi-dmac: Allow devices to be marked as noncoherent
1b13b0914156 dt-bindings: dma: Convert fsl,elo*-dma to YAML
c3ed4efc2e50 dt-bindings: dma: fsl-mxs-dma: Add compatible string for i.MX8 chips
aa353c2ac5c5 dt-bindings: input: goodix,gt9916: Document gt9897 compatible
6eb8cce7644b dt-bindings: pwm: imx: Add i.MX93, i.MX94 and i.MX95 support
cbd6df2de511 ARM: dts: stm32: Add support for STM32MP13xx DHCOR SoM and DHSBC rev.200 board
3167db834dfa ARM: dts: stm32: use IRQ_TYPE_EDGE_FALLING on stm32mp157c-dk2
b83d9874fa79 dt-bindings: gpio: vf610: Add i.MX94 support
58ce3a6f5491 Merge v6.14-rc6 into usb-next
ee4310889b80 dt-bindings: phy: document Allwinner A523 USB-2.0 PHY
e2e13ecd8aa4 dt-bindings: soc: samsung: exynos-usi: Drop unnecessary status from example
13c7fa153448 dt-bindings: watchdog: fsl-imx7ulp-wdt: Add i.MX94 support
6fc9ef1dce8b ASoC: dmic: add regulator support
f33253da3ed0 dt-bindings: pwm: rockchip: Add rockchip,rk3528-pwm
df96b42ccaa5 arm64: dts: rockchip: Add SPI NOR device on the ROCK 4D
8af8429d4741 arm64: dts: rockchip: Add SFC nodes for rk3576
460ef5b623e5 arm64: dts: rockchip: Add maskrom button to Radxa E20C
8ba64ba5cb30 arm64: dts: rockchip: Add SARADC node for RK3528
6793b56b79df arm64: dts: rockchip: Add user button to Radxa E20C
a3556ede6b48 arm64: dts: rockchip: Add leds node to Radxa E20C
4dc91efae86b arm64: dts: rockchip: Add HDMI support for rock-4d
6e03c7e28e2d arm64: dts: rockchip: enable SCMI clk for RK3528 SoC
2bdc1b582fc5 arm64: dts: rockchip: Enable HDMI receiver on rock-5b
be8c63cd54f8 arm64: dts: rockchip: Add device tree support for HDMI RX Controller
9ee90dfd6957 arm64: dts: rockchip: Add rk3528 QoS register node
cc3c4cf475e2 dt-bindings: mfd: syscon: Add rk3528 QoS register compatible
de0d9c50f68f ASoC: dt-bindings: fsl,imx-asrc: Document audio graph port
2e3ffd78169f ASoC: dt-bindings: add regulator support to dmic codec
0946c7535fed dt-bindings: PCI: fsl,layerscape-pcie-ep: Drop unnecessary status from example
0d08b7785cbf dt-bindings: PCI: fsl,layerscape-pcie-ep: Drop deprecated windows
499ff8f6f00e dt-bindings: crypto: qcom,prng: document QCS615
137ebe3e9e23 dt-bindings: crypto: inside-secure,safexcel: Allow dma-coherent
19a0ed3478a5 dt-bindings: net: Add support for Sophgo SG2044 dwmac
01ec431b0809 dt-bindings: display/msm: dsi-controller-main: Add missing minItems
899bbe0128ad dt-bindings: display/msm: dsi-controller-main: Combine if:then: entries
b6b83575709d dt-bindings: memory-controllers: qcom,ebi2: Enforce child props
7a5a115214b1 dt-bindings: memory-controllers: samsung,exynos4210-srom: Enforce child props
5cbcded3d915 arm64: tegra: p2180: Add TMP451 temperature sensor node
bb4e0081de49 arm64: tegra: p2597: Enable TCA9539 as IRQ controllers
64bca56d40df arm64: tegra: Define pinmuxing for gpio pads on Tegra210
a2afd5dbc694 arm64: tegra: p2597: Fix gpio for vdd-1v8-dis regulator
3074f948c0f0 arm64: tegra: Resize aperture for the IGX PCIe C5 slot
0556e73ad468 arm64: tegra: Remove the Orin NX/Nano suspend key
5075ae527c32 dt-bindings: timer: exynos4210-mct: add samsung,exynos2200-mct-peris compatible
b2d611510011 dt-bindings: timer: exynos4210-mct: Add samsung,exynos990-mct compatible
e25abb336b06 dt-bindings: timer: Correct indentation and style in DTS example
27659631b1ab ARM: dts: marvell: armada: Align GPIO hog name with bindings
45d76d30bd18 ARM: dts: marvell: kirkwood-openrd: Align GPIO hog name with bindings
ed88cf59518a arm64: dts: marvell: armada-8040: Align GPIO hog name with bindings
fd8985afa234 dt-bindings: Document Tegra114 HDA support
514aa1e9d711 dt-bindings: display: tegra: Document Tegra124 MIPI
6f895e2fc34b Merge branch 'for-6.15/io_uring-rx-zc' into for-6.15/io_uring-reg-vec
783a9ff2b877 arm64: dts: tesla: Change labels to lower-case
fb95fa637210 arm64: dts: exynos: gs101: Change labels to lower-case
8bb1ecf374d2 arm64: dts: ti: k3-am62a-phycore-som: Reorder properties per DTS coding style
b7183e25919b arm64: dts: ti: k3-am642-phyboard-electra: Reorder properties per DTS coding style
d3e54c73fad8 arm64: dts: ti: k3-am642-phyboard-electra: Add boot phase tags
c198a9892aee arm64: dts: ti: k3-am62a-phycore-som: Add boot phase tags
7adcaf738ea2 arm64: dts: ti: k3-am62x-phyboard-lyra: Add boot phase tags
08a8be409da1 Merge tag 'ath-next-20250305' of git://git.kernel.org/pub/scm/linux/kernel/git/ath/ath
b6eb736bdac9 dt-bindings: irq: sun7i-nmi: Document the Allwinner A523 NMI controller
29c23eb9e1e4 dt-bindings: net: Add FSD EQoS device tree bindings
7fcf7786e3c1 dt-bindings: ieee802154: ca8210: Update polarity of the reset pin
63f785ba85d6 dt-bindings: i3c: silvaco: Add npcm845 compatible string
4e7d4a0a5a98 dt-bindings: i3c: dw: Add power-domains
60779b9e5efd arm64: dts: apple: t8015: Add backlight nodes
d1c2cf3d6db3 arm64: dts: apple: t8010: Add backlight nodes
c493ad2b695a arm64: dts: apple: s800-0-3: Add backlight nodes
2a527cb076cb arm64: dts: apple: t7000: Add backlight nodes
8c09890d8a3a arm64: dts: apple: s5l8960x: Add backlight nodes
644d720366d7 spi: dt-bindings: fsl-lpspi: Add i.MX94 support
43baf3d00dd4 ARM: tegra: tf101: Add al3000a illuminance sensor node
01ff58401e94 dt-bindings: display: mitsubishi,aa104xd12: Adjust allowed and required properties
76f79fd8d2e1 dt-bindings: display: mitsubishi,aa104xd12: Allow jeida-18 for data-mapping
753638f98d53 ARM: tegra: Add DSI-A and DSI-B nodes on Tegra124
0dc63e559158 ARM: tegra: Add HDA node on Tegra114
c21c9d411a7b ARM: tegra: Add ARM PMU node on Tegra114
c169b6a13648 ARM: tegra: Switch DSI-B clock parent to PLLD on Tegra114
ce08790716a2 dt-bindings: media: mediatek,vcodec: Revise description
1d7d1f1bb863 dt-bindings: media: mediatek,jpeg: Relax IOMMU max item count
84ee1a870bac Merge tag 'mtk-dts64-for-v6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/dt
aded2fb69436 arm64: dts: nvidia: Remove unused and undocumented "regulator-ramp-delay-scale" property
ee85d6d69363 Merge tag 'juno-updates-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into soc/dt
9591e80db9de Merge tag 'asahi-soc-dt-6.15-v2' of https://github.com/AsahiLinux/linux into soc/dt
c078f53218f7 Merge tag 'renesas-dts-for-v6.15-tag1' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
ba3eae2fe133 Merge tag 'renesas-dt-bindings-for-v6.15-tag1' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
3077a635de45 Merge tag 'ixp4xx-dts-soc-for-v6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator into soc/dt
5dc02a7bec60 Merge tag 'asahi-soc-dt-6.15' of https://github.com/AsahiLinux/linux into soc/dt
131231dc887a arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable Mali-G31
f6f80ad2a1f4 arm64: dts: renesas: r9a09g057: Add Mali-G31 GPU node
bbda080c8952 arm64: dts: rockchip: add MNT Reform 2 laptop
eb0d04e0938d dt-bindings: arm: rockchip: Add MNT Reform 2 (RCORE)
ef01ba18d719 dt-bindings: soc: rockchip: Add RK3528 VPU GRF syscon
9d39d8aa54eb dt-bindings: soc: rockchip: Add RK3528 VO GRF syscon
2f989dc849ab dt-bindings: PCI: fsl,imx6q-pcie: Add optional DMA interrupt
f139ea2f5a06 dt-bindings: PCI: Convert fsl,mpc83xx-pcie to YAML
1dfe7500437d dt-bindings: PCI: qcom: Document the IPQ5332 PCIe controller
f83683dd6f9e arm64: dts: mediatek: mt8395-radxa-nio-12l: Add Radxa 8 HD panel
9595aadd9a31 arm64: dts: mediatek: mt8395-nio-12l: Prepare MIPI DSI port
9f598f6af2a3 arm64: dts: mediatek: mt8390-genio-common: Add delay codec for DMIC
b152da61f6cd arm64: dts: mediatek: mt8390-genio-common: Add routes for DMIC
7f5ef01f6c71 arm64: dts: mediatek: mt8395-nio-12l: Preconfigure DSI0 pipeline
7cefb6741548 arm64: mediatek: mt8195-cherry: Add graph for eDP and DP displays
bd0418035afa arm64: dts: mediatek: mt8195: Add base display controller graph
67a479e22dd9 arm64: dts: airoha: en7581: Fix clock-controller address
9f3a44607c09 arm64: dts: airoha: en7581: Add more nodes to EN7581 SoC evaluation board
6d3ac809c14a arm64: dts: mediatek: mt8390-genio-common: Configure touch vreg pins
f607df354b84 arm64: dts: mediatek: mt8188-geralt: Add graph for DSI and DP displays
b62844c6033e arm64: dts: rockchip: Enable hdmi out display for rk3576-evb-v10
70636ab4c427 dt-bindings: PCI: altera: Add binding for Agilex
5f2ac732a000 dt-bindings: qcom: geni-se: Add 'firmware-name' property for firmware loading
eb0afea35cd3 ASoC: Merge up fixes
a7fdc3022cc4 dt-bindings: soc: samsung: exynos-pmu: add exynos7870-pmu compatible
09611d37a4a2 dt-bindings: media: Document bindings for HDMI RX Controller
5733784ecab2 dt-bindings: gpio: loongson: Add new loongson gpio chip compatible
bde0820c0330 dt-bindings: pinctrl: Add bindings for BCM21664 pin controller
99ef71a02c72 dt-bindings: input: matrix_keypad - add wakeup-source property
6cc85963b28f arm64: dts: ti: k3-j722s-evm: Add camera peripherals
f57767d39255 arm64: dts: ti: k3-j722s-main: Add CSI2RX nodes
5f079de69dbc arm64: dts: ti: k3-j722s-main: Add BCDMA CSI overrides
fc74dd76227a arm64: dts: ti: k3-j722s: fix pinctrl settings
5916cffba231 arm64: dts: ti: k3-am62p: fix pinctrl settings
d442b5177760 arm64: dts: ti: am64-phyboard-electra: Add DT overlay for X27 connector
598a53f305e4 dt-bindings: remoteproc: qcom,wcnss-pil: Add support for single power-domain platforms
cda103526016 dt-bindings: remoteproc: qcom,msm8916-mss-pil: Add MSM8926
893c449685ce dt-bindings: remoteproc: qcom,msm8916-mss-pil: Add MSM8226
e9fa3e49686b dt-bindings: remoteproc: qcom,msm8916-mss-pil: Support platforms with one power domain
c9ba86664ced dt-bindings: remoteproc: Add SM8750 CDSP
0727f5f07392 dt-bindings: display/msm: qcom, sa8775p-mdss: Add missing eDP phy
0e759e398167 dt-bindings: remoteproc: qcom,sm6115-pas: Use recommended MBN firmware format in DTS example
ad59df2a8e47 dt-bindings: net: Convert fsl,gianfar to YAML
ecac8517df71 dt-bindings: net: fsl,gianfar-mdio: Update information about TBI
9f27542c356c dt-bindings: net: Convert fsl,gianfar-{mdio,tbi} to YAML
f3d1127d6da2 arm64: dts: rockchip: Enable hdmi display on sige5
4353815d5413 arm64: dts: rockchip: Add hdmi for rk3576
e898135e14ac arm64: dts: rockchip: Add vop for rk3576
c4a8c85028f9 ARM: dts: microchip: sama7g5: add ADC hw trigger edge type
e415d0ace351 ASoC: fsl_audmix: support audio graph card for audmix
81dd10b4d87c dt-bindings: arm: Add Coresight TMC Control Unit hardware
5ffae977c446 Merge tag 'wireless-next-2025-03-04-v2' of https://git.kernel.org/pub/scm/linux/kernel/git/wireless/wireless-next
8cdbfaccfe40 dt-bindings: iio: adc: ad7380: add adaq4381-4 compatible parts
c35357650277 dt-bindings: iio: adc: Add rockchip,rk3562-saradc string
ffdcbd963d7a dt-bindings: iio: adc: Add rockchip,rk3528-saradc variant
9ca8f9827434 arm64: dts: rockchip: Add ES8388 audio codec fallback on RK3588 boards
f8fb45ddefb3 arm64: dts: rockchip: Add ES8388 audio codec fallback on RK3399 ROC PC PLUS
45ccbb3708d1 dt-bindings: iio: light: al3010: add al3000a support
2dcb97b015ba Add STM32MP25 SPI NOR support
663e168d3026 ASoC: dt-bindings: everest,es8328: Require reg property
5973f33d36e4 ASoC: dt-bindings: everest,es8328: Mark ES8388 compatible with ES8328
d5fdb2909430 dt-bindings: net: airoha: Add airoha,npu phandle property
4b02ac198dfd dt-bindings: net: airoha: Add the NPU node for EN7581 SoC
9bcf6ccdd87c arm64: dts: rockchip: Add uart0 pinctrl to Radxa E20C
89a24fa2e923 arm64: dts: rockchip: Add pinctrl and gpio nodes for RK3528
340a7d991681 dt-bindings: soc: rockchip: Add RK3528 ioc grf syscon
2484bd1527c8 dt-bindings: mtd: physmap: Ensure all properties are defined
9a114f2cbbc5 dt-bindings: mtd: mxc-nand: Document fsl,imx31-nand
33bcbf56e498 dt-bindings: gpio: mvebu: Add missing 'gpio-ranges' property and hog nodes
9a17c1dc8a52 dt-bindings: pinctrl: Add pinctrl support for RK3528
a8fac5afd00e dt-bindings: clock: qcom: sm8450-camcc: Remove qcom,x1e80100-camcc leftover
3d038aa84fac dt-bindings: display: vop2: Add rk3576 support
539c3db87e49 dt-bindings: display: vop2: Add missing rockchip,grf property for rk3566/8
fc2f169c14d8 dt-bindings: display: vop2: describe constraint SoC by SoC
a9175c1faaf6 arm64: dts: apple: Add touchbar screen nodes
0a30c2fb605b dt-bindings: PCI: mediatek-gen3: Add mediatek,pbus-csr phandle array property
6c0991dfe309 ARM: dts: microchip: sama7d65: Add watchdog for sama7d65
3a5c0b5439e4 arm64: dts: corstone1000: Add definitions for secondary CPU cores
760344eaf4df dt-bindings: clock: imx8m: document nominal/overdrive properties
3ebf9fab8556 dt-bindings: display: Add Apple pre-DCP display controller
45f020c2ff12 dt-bindings: clock: imx8mp: add axi clock
25a9aae37c46 ASoC: dt-bindings: fsl,audmix: make 'dais' property to be optional
39ab44f1f451 ASoC: dt-bindings: fsl,audmix: Document audio graph port
751e72c4a42f ASoC: dt-bindings: fsl,sai: Document audio graph port
375185829d56 spi: dt-bindings: Introduce qcom,spi-qpic-snand
ca5abc134e5c dt-bindings: spi: Add STM32 OSPI controller
18e6b1036205 dt-bindings: PCI: amd-mdb: Add AMD Versal2 MDB PCIe Root Port Bridge
f8432e8085b8 dt-bindings: PCI: dwc: Add AMD Versal2 MDB SLCR support
f3240bd9ff15 dt-bindings: usb: samsung,exynos-dwc3: add exynos7870 support
578e6366fe17 dt-bindings: usb: dwc3: Add support for rk3562
9c7380c08c12 dt-bindings: usb: generic-xhci: Allow dma-coherent
f5355ed2d30b dt-bindings: usb: richtek,rt1711h: Add missing vbus power supply
2fecbb897235 dt-bindings: pinctrl: samsung: add exynos7870-wakeup-eint compatible
6acd675fdb2b dt-bindings: pinctrl: samsung: add exynos7870-pinctrl compatible
64247b825e83 arm64: dts: qcom: gaokun3: Add Embedded Controller node
0de83bdbd702 dt-bindings: platform: Add Huawei Matebook E Go EC
8c7e026bceb2 arm64: dts: ti: k3-j784s4-j742s2-main-common: Fix serdes_ln_ctrl reg-masks
b0f3437e4eed arm64: dts: ti: k3-am62p: Enable AUDIO_REFCLKx
7abf45296c55 dt-bindings: hwmon: gpio-fan: Add optional regulator support
ad715d63d5b9 dt-bindings: hwmon: Add UCD90320 gpio description
94282ccb3f77 dt-bindings: hwmon: ntc-thermistor: fix typo regarding the deprecation of the ntc, compatibles
37c47e53b269 dt-bindings: display: mediatek: dsc: Add MT8188 compatible
a880ab46aaf3 ARM: dts: microchip: sama7d65: Enable shutdown controller
5bf0dfe3a93e ARM: dts: microchip: sama7d65: Add SFRBU support to sama7d65
ceb3ca267777 ARM: dts: microchip: sama7d65: Add RTC support for sama7d65
33d484179e01 ARM: dts: microchip: sama7d65: Add Shutdown controller support
3a833187b48a ARM: dts: microchip: sama7d65: Add Reset Controller to sama7d65 SoC
cb7d22318d14 arm64: dts: ti: k3-am62-phycore-som: Reserve RTOS IPC memory
de40a5c334d5 arm64: dts: ti: k3-am64-phycore-som: Reserve RTOS IPC memory
c1de68dfb465 arm64: dts: ti: k3-am62p5-sk: Add serial alias
fc3a3408782e arm64: dts: ti: k3-am62a7-sk: Add serial alias
89fb433abb4a arm64: dts: ti: k3-am62x-sk-common: Add serial aliases
b40599be6e89 arm64: dts: ti: k3-am62p5-sk: Support SoC wakeup using USB1 wakeup
4e21f0928a3c arm64: dts: ti: k3-am625-beagleplay: Reserve 128MiB of global CMA
0e6efc73fbc4 arm64: dts: ti: k3-j721e-sk: Add boot phase tag to SERDES3
e62cc3a65c52 arm64: dts: ti: k3-j721e-common-proc-board: Add boot phase tag to SERDES3
df13b922a34e arm64: dts: ti: k3-am62p-j722s-common-wakeup: Configure ti-sysc for wkup_uart0
d5e905102b12 arm64: dts: ti: k3-am62a7-sk: Add alias for RTC
f0a08fa6651e arm64: dts: ti: k3-j721s2-som-p0: Add flash partition details
49435c1a2a18 arm64: dts: ti: k3-am62-verdin-dahlia: add Microphone Jack to sound card
dbb5bd13ad09 arm64: dts: ti: k3-j784s4-j742s2-main-common: Correct the GICD size
e42f6f652b25 arm64: dts: ti: k3-am62p5-sk: Add boot phase tag for USB0
d6d559bbf2a6 arm64: dts: ti: k3-am62a7-sk: Add boot phase tag for USB0
26e1b575e84d dt-bindings: display: mediatek: dpi: Add MT8195 and MT8188 compat
c32424d952a8 dt-bindings: crypto: Convert fsl,sec-2.0 to YAML
83100c586db1 dt-bindings: clock: add clock definitions and documentation for exynos7870 CMU
839f40a5722d dt-bindings: clock: add Exynos2200 SoC
22fe2b154172 dt-bindings: iommu: qcom,iommu: Add MSM8937 IOMMU to SMMUv1 compatibles
34189497288b dt-bindings: pwm: rockchip: Add rockchip,rk3562-pwm
9afffc8f0f22 dt-bindings: interrupt-controller: Convert nxp,lpc3220-mic.txt to yaml format
7fa643245f20 dt-bindings: gpu: Add rockchip,rk3562-mali compatible
3abda087dbf6 Merge branch 'v6.15-shared/clkids' into v6.15-clk/next
8cd451e705ff dt-bindings: clock: Add RK3562 cru
1f94b7afa565 arm64: dts: rockchip: add usb typec host support to rk3588-jaguar
05453dc67f58 dt-bindings: wireless: ath12k: Strip ath12k prefix from calibration property
da3621d60f14 dt-bindings: wireless: ath11k: Strip ath11k prefix from calibration property
6fdc1d052416 dt-bindings: wireless: ath10k: Strip ath10k prefix from calibration properties
9861592542dd dt-bindings: display/msm/gmu: Add Adreno 623 GMU
8e07cd8d79b5 arm64: dts: rockchip: Add GPU power domain regulator dependency for RK3588
4c6cdea070ff mdomain: Merge branch dt into next
af3fb092d876 dt-bindings: power: rockchip: add regulator support
1de33272f6b5 pmdomain: Merge tag 'v6.14-rc4' from Linus into next
922c569881d6 ARM: dts: microchip: fix faulty ohci/ehci node names
2a4f0bc75929 ARM: dts: microchip: usb_a9263: fix wrong vendor
22c00bf9a9ec dt-bindings: ARM: at91: add Calao USB boards
00a259802c74 dt-bindings: ARM: at91: make separate entry for Olimex board
f7ecad4dfdba arm64: dts: amlogic: g12: switch to the new PWM controller binding
e594907dbba0 arm64: dts: amlogic: axg: switch to the new PWM controller binding
0db68c194ba8 arm64: dts: amlogic: gx: switch to the new PWM controller binding
07569029f06a ARM: dts: amlogic: meson8b: switch to the new PWM controller binding
45a895b33ca6 ARM: dts: amlogic: meson8: switch to the new PWM controller binding
ecad1190684f dt-bindings: input: matrix_keypad - add missing property
7a5e2e594dcc Merge branch 'ib-amlogic-a4' into devel
84ad7c66e08d dt-bindings: pinctrl: Add support for Amlogic A4 SoC
81d115cd787a Merge branch 'ib-sophgo' into devel
2fb57a80ac82 dt-bindings: pinctrl: Add pinctrl for Sophgo SG2042 series SoC
d25e98a2e1d9 dt-bindings: clock: mediatek: Add SMI LARBs reset for MT8188
9d4fce6bf871 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
b0f9f15fa3eb arm64: dts: rockchip: Enable HDMI1 audio output for Orange Pi 5 Ultra
cb7a017df5cc arm64: dts: rockchip: Enable HDMI1 on Orange Pi 5 Ultra
7a10dcdcf5dd arm64: dts: rockchip: Add Orange Pi 5 Ultra board
bb2d35f7447a dt-bindings: arm: rockchip: Add Xunlong Orange Pi 5 Ultra
c61a839ade98 arm64: dts: rockchip: Adapt to differences between Orange Pi 5 Max and Ultra
f46eeb290a49 arm64: dts: rockchip: add hdmi1 support to ROCK 5 ITX
8abf4e075936 arm64: dts: rockchip: Enable HDMI audio outputs for Rock 5B
a779ebd82fb1 arm64: dts: rockchip: Add HDMI audio outputs for rk3588
b0c3cbe5b68d arm64: dts: rockchip: Enable HDMI1 on rk3588-evb1
40f977e4d24d arm64: dts: rockchip: Add HDMI1 PHY PLL clock source to VOP2 on RK3588
2f30db59cf45 arm64: dts: rockchip: Enable HDMI1 PHY clk provider on RK3588
027b0ef80afb spi: dt-bindings: Add rk3562 support
2533797ddce2 arm64: dts: morello: Add support for fvp dts
9f5663971e1f arm64: dts: morello: Add support for soc dts
3ff25bf13939 arm64: dts: morello: Add support for common functionalities
64de0a722178 dt-bindings: arm-pmu: Add support for ARM Rainier PMU
503c66e651f9 dt-bindings: arm: Add Rainier compatibility
f67be59b2a9a dt-bindings: arm: Add Morello fvp compatibility
9cb3ba5bb59e dt-bindings: arm: Add Morello compatibility
910e9d8438ef mips: dts: ralink: mt7628a: update system controller node and its consumers
0e7913ce1f04 dt-bindings: display: panel: Add Visionox RM692E5
33660ef35f42 dt-bindings: display: panel: Add Raydium RM67200
b9abbea75728 ARM: dts: stm32: add usr3 LED node to stm32f769-disco
972663879bc7 ARM: dts: stm32: rename LEDs nodes for stm32f769-disco
f5f056e5d15d ARM: dts: stm32: add push button to stm32f746 Discovery board
9209e9fa6ca9 ARM: dts: stm32: add led to stm32f746 Discovery board
c572b069bf16 dt-bindings: dma: fsl,edma: Add i.MX94 support
421f8d787226 dt-bindings: dma: atmel: add microchip,sama7d65-dma
3630c655aafd dt-bindings: clock: mediatek,mt8188: Add VDO1_DPI1_HDMI clock
8f22583cbe0b arm64: dts: rockchip: Enable USB3 OTG on rk3588s Cool Pi 4B
175b6ab4addb docs: dt: submitting-patches: Document sending DTS patches
12f69f638472 arm64: dts: rockchip: Add UART clocks for RK3528 SoC
60741472b42e arm64: dts: rockchip: Add clock generators for RK3528 SoC
9d809a089686 Merge branch 'v6.15-shared/clkids' into v6.15-armsoc/dts64
4b92d7bf7d17 Merge branch 'v6.15-shared/clkids' into v6.15-clk/next
8768d063e732 dt-bindings: clock: Document clock and reset unit of RK3528
eb4fa305444d powerpc/microwatt: Add SMP support
eb2feccfe7cb powerpc/microwatt: Device-tree updates
b01ec0c00687 arm64: dts: apple: Add touchbar digitizer nodes
99a9210485d1 ARM: dts: stm32: Add Priva E-Measuringbox devicetree
db39291d4cd4 ARM: dts: stm32: Add thermal support for STM32MP131
736b25b842a6 dt-bindings: arm: stm32: Add Priva E-Measuringbox board
ac84513b3de1 dt-bindings: vendor-prefixes: Add prefix for Priva
153d1dded8e2 ASoC: dt-bindings: xlnx,spdif: Convert to json-schema
1dfc9272871a ASoC: dt-bindings: xlnx,audio-formatter: Convert to json-schema
c05b804fd27e ASoC: dt-bindings: xlnx,i2s: Convert to json-schema
e6b5549e2ea1 dt-bindings: coresight: qcom,coresight-tpdm: Fix too many 'reg'
81c7d959642a dt-bindings: coresight: qcom,coresight-tpda: Fix too many 'reg'
d788495c297e dt-bindings: interrupt-controller: renesas,rzv2h-icu: Document RZ/G3E SoC
ef078fa51469 dt-bindings: gpio: nxp,pcf8575: add reset GPIO
e60b526a254b dt-bindings: display: qcom,sm8650-mdss: explicitly document mdp0-mem and cpu-cfg interconnect paths
5f6c7f3a882b dt-bindings: display: qcom,sm8550-mdss: explicitly document mdp0-mem and cpu-cfg interconnect paths
564ffb04cbff dt-bindings: display/msm/dsi-phy: Add header with exposed clock IDs
dfe70ec7cf52 riscv: sophgo: dts: Add msi controller for SG2042
05d993f3a6ec dt-bindings: interrupt-controller: Add Sophgo SG2042 MSI
a3b737ca15b2 Merge tag 'v6.14-rc4' into next
f3b5bc2ab93f dt-bindings: display/lvds-codec: add ti,sn65lvds822
b20b0aace0f0 dt-bindings: input: matrix_keypad: add settle time after enabling all columns
c6644ddbabe0 dt-bindings: input: matrix_keypad: convert to YAML
0204ceb1dac8 Enable DMIC for Genio 700/510 EVK
aaa0adb4e4ba dt-bindings: input: Correct indentation and style in DTS example
1bd35f025a98 ASoC: dt-bindings: fsl: Reference common DAI
9d01b52dd742 ASoC: dt-bindings: mediatek,mt8188-mt6359: Add DMIC backend to dai-link
4b7def7c217f Fix RK3588 power domain problems
02d8831bddbd ASoC: dt-bindings: fsl,imx-asrc: Reference common DAI properties
2756dbc5dccb ASoC: dt-bindings: fsl,easrc: Reference common DAI properties
be1e7ad12db3 Merge drm/drm-next into drm-misc-next
9876c6970616 dt-bindings: display: simple: Add BOE AV123Z7M-N17 panel
740d6f024cb4 dt-bindings: display: simple: add BOE AV101HDT-A10 panel
695f9094dd3e arm64: dts: mediatek: mt8188: Add base display controller graph
d953922a6352 arm64: dts: mediatek: mt8390-genio-700: Add USB, TypeC Controller, MUX
4a972b5813a9 arm64: dts: mediatek: mt8188: Add MTU3 nodes and correctly describe USB
c926d7135987 dt-bindings: usb: mediatek,mtk-xhci: Add port for SuperSpeed EP
3479b8607126 arm64: dts: mediatek: mt8395-genio-1200-evk: add support for TCPC port
1ea007fec939 dt-bindings: usb: mtu3: Add ports property
81bb891f02a1 arm64: dts: mediatek: mt8390-genio-common: Fix duplicated regulator name
c2ee67f8f91c arm64: dts: mediatek: mt8183: Switch to Elan touchscreen driver
1480b2b9c163 Merge tag 'v6.14-rc4' into drm-next
19566af01522 arm64: dts: imx8mm-phycore-som: Add overlay to disable SPI NOR flash
4d957d8455fd arm64: dts: imx8mm-phycore-som: Add no-eth phy overlay
e38b34b397ca arm64: dts: imx8mm-phycore-som: Add overlay for rproc
1d49d21dd81e arm64: dts: imx8mm-phyboard-polis: Add overlay for PEB-EVAL-01
3e8bdd2e0853 arm64: dts: imx8mm-phyboard-polis: Add support for PEB-AV-10
ea91b13eb856 arm64: dts: imx8mm-phyboard-polis: Assign missing regulator for bluetooth
884d4632d049 arm64: dts: imx8mm: move bulk of rtc properties to carrierboards
3bfc2236c593 arm64: dts: imx8mm-phygate-tauri-l: Set RTC as wakeup-source
1ca2b9c5de6b arm64: dts: imx8mm-phyboard-polis: Set RTC as wakeup-source
2a508a6ff135 arm64: dts: imx8mm-phyboard-polis: add RTC description
b9ef6209b80f arm64: dts: imx8mm-phycore-som: add descriptions to nodes
fa73714ac0c3 arm64: dts: imx8mm-phycore-som: Assign regulator for dsi to lvds bridge
b37946788b2f arm64: dts: imx8mm-phycore-som: Remove magic-packet property
8016d32846f7 arm64: dts: imx8mm-phycore-som: Fix bluetooth wakeup source
9d8e0c3c4f7c arm64: dts: imx8mm-phycore-som: Keep LDO3 on in suspend
b69b4e83993e arm64: dts: freescale: imx8mm-verdin: Remove LVDS panel and backlight
47beab578f6c arm64: dts: colibri-imx8x: Add missing gpio-line-names
20c64688c512 arm64: dts: s32g: add the eDMA nodes
a17008eb460a arm64: dts: imx95: add PCIe's msi-map and iommu-map property
13bbffb4e884 arm64: dts: imx8q: add PCIe EP overlay file for i.MX8QXP mek board
55a2bc97a378 arm64: dts: imx8q: add PCIe EP for i.MX8QM and i.MX8QXP
5e82dd84d613 arm64: dts: imx8-ss-hsio: fix indentation in pcie node
6114dc137559 arm64: dts: freescale: tqma8mqnl: Add vcc-supply for spi-nor
aa74db634145 arm64: dts: freescale: tqma8mqml: Add vcc-supply for spi-nor
8ac725ad672e arm64: dts: freescale: tqma8mq: Add vcc-supply for spi-nor
0b92969081bc arm64: dts: freescale: tqma8mpql: Add vcc-supply for spi-nor
e82710a7796c arm64: dts: imx8-apalis: add clock configuration for 44.1 kHz hdmi audio
05db5bdaa953 arm64: dts: s32g399a-rdb3: Add INA231 sensor entry over I2C4
50df896ee8a8 arm64: dts: s32g: add common 'S32G-EVB' and 'S32G-RDB' board support
e01e9b9dd62f arm64: dts: s32g: add I2C[0..2] support for s32g2 and s32g3
8be8d6f5fd39 arm64: dts: imx8qxp-mek: Complete WM8960 power supplies
1f7da937625a arm64: dts: imx8qm-mek: Complete WM8960 power supplies
6cb4cf4a8959 arm64: dts: imx8dxl-evk: Complete WM8960 power supplies
a823b8504cfc arm64: dts: imx8mp-evk: Complete WM8960 power supplies
f0fb71d2bfd2 arm64: dts: tqma9352-mba93xx[cl]a: swap ethernet aliases
e6c58c4e34f5 arm64: dts: mba93xxca: Do not assert power-down pins
34a0e3de0c9d arm64: dts: freescale: imx93-tqma9352-mba93xxca: sort pinctrl nodes
b41df0cb89cc arm64: dts: mba8xx: Add PCIe support
d0a618f195f1 arm64: dts: tqma8xx: Remove GPU TODO
43419b7de367 arm64: dts: tqma8xx: enable jpeg encode and decode
8eaabcf5b237 arm64: dts: tqma8xx: Add vcc-supply for spi-nor
a1706580b459 arm64: dts: imx8-ss-hsio: Wire up DMA IRQ for PCIe
abcd89649f74 arm64: dts: imx8mn-bsh-smm-s2pro: Remove invalid audio codec clock
73b9c2a4d2cf arm64: dts: imx8mp-skov: increase I2C clock frequency for RTC
15dad674cdf5 arm64: dts: imx8mp-skov: fix phy-mode
35f9d08e683e arm64: dts: imx8mp-skov: describe mains fail detection
918eb1e7f304 arm64: dts: imx8mp-skov: configure uart1 for RS485
b1c4121e92da arm64: dts: imx8mp-skov: describe LVDS display pipeline
4f3d28e9954c arm64: dts: imx8mp-skov: describe HDMI display pipeline
74ff20266638 arm64: dts: imx8mp-skov: use I2C5 for DDC
5ee605182ffa arm64: dts: imx8mp-skov: operate CPU at 850 mV by default
b9feeafd2708 arm64: dts: imx8mp-skov: correct PMIC board limits
6a3290b43d38 arm64: dts: imx8mp-kontron: Add support for reading SD_VSEL signal
afb10648ca50 arm64: dts: imx93-kontron: Fix SD card IO voltage control
7822c3bd0f88 arm64: dts: imx8mm-kontron: Add support for reading SD_VSEL signal
b90dec14cbfd ARM: dts: imx7d-sdb: Complete WM8960 power supplies
96289b986803 ARM: dts: imx6ul-14x14-evk: Complete WM8960 power supplies
baa99fba4fbd scsi: arm64: dts: rockchip: Add UFS support for RK3576 SoC
e1e953869373 scsi: ufs: dt-bindings: Document Rockchip UFS host controller
af1e5d055507 dt-bindings: PCI: brcmstb: Update bindings for PCIe on BCM2712
88b7337af159 dt-bindings: interrupt-controller: Add BCM2712 MSI-X bindings
e08f82eefaa7 dt-bindings: PCI: qcom-ep: Add SAR2130P compatible
4fd2560c686b dt-bindings: PCI: qcom-ep: Consolidate DMA vs non-DMA cases
652e3a3e15ee dt-bindings: PCI: qcom-ep: Enable DMA for SM8450
ffe279433d99 dt-bindings: PCI: qcom-ep: Describe optional IOMMU
cb5305df80d2 dt-bindings: PCI: qcom-ep: Describe optional dma-coherent property
9585b1fcf51a ASoC: dt-bindings: imx-card: Add playback-only and capture-only property
ed671a626791 dt-bindings: atmel-sysreg: Add SAMA7D65 Chip ID
6096197138a9 ARM: dts: microchip: sama7d65: Enable DMAs
e76971437b8a arm64: dts: ti: k3-j722s-evm: Fix USB2.0_MUX_SEL to select Type-C
ad4c5c253cfc ARM: dts: microchip: sama7d65: Add DMAs to sama7d65 SoC
21d60212633f ARM: dts: microchip: sama7d65: Add chipID for sama7d65
0ce77a32a2e4 arm64: dts: ti: k3-j784s4-evm-quad-port-eth-exp1: Remove duplicate hogs
b2c185c86ce6 arm64: dts: ti: k3-am62a-mcu: enable mcu domain pinmux
34a41a24c946 Merge tag 'v6.14-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux into HEAD
1a8fe57c561b arm64: dts: exynosautov920: add ufs phy for ExynosAutov920 SoC
53d1e146b05c ARM: dts: imx28-sps1: Fix GPIO LEDs description
10884a5224f4 ARM: dts: vf610-bk4: Use the more specific "lwn,bk4-spi"
edd698009292 arm64: dts: rockchip: disable I2C2 bus by default on RK3588 Tiger
9be02103e21d arm64: dts: rockchip: enable I2C3 in Haikou carrierboard, not Ringneck DTSI
5743a9dda2c4 arm64: dts: rockchip: enable Ethernet in Haikou carrierboard, not Puma DTSI
2420a6d5e78c arm64: dts: rockchip: add EEPROM found on RK3399 Puma Haikou
529f82cf3ce9 arm64: dts: rockchip: enable I2S0 in Haikou carrierboard, not Puma DTSI
28cf8608f8d9 arm64: dts: rockchip: disable I2C6 on Puma DTSI
a7b506f792bf arm64: dts: rockchip: move I2C6 from Haikou carrierboard to Puma DTSI
55a866e88323 arm64: dts: rockchip: move DDC bus from Haikou carrierboard to RK3399 Puma DTSI
27fd1de71a59 arm64: dts: rockchip: enable UART5 on RK3588 Tiger Haikou
6c3bb559bac0 arm64: dts: rockchip: Add Radxa ROCK 4D device tree
3544351bd438 dt-bindings: arm: rockchip: Add Radxa ROCK 4D board
d67cf6de8aac arm64: dts: rockchip: add rk3576 otp node
231a534cd743 arm64: dts: rockchip: add overlay for RK3399 Puma Haikou Video Demo adapter
abbc13f77a26 arm64: dts: rockchip: add overlay for PX30 Ringneck Haikou Video Demo adapter
046e0c70c93b arm64: dts: rockchip: add support for HAIKOU-LVDS-9904379 adapter for PX30 Ringneck
88fdb1f81232 dt-bindings: clock: sun50i-h616-ccu: Add LCD TCON clk and reset
4bb141531379 arm64: dts: allwinner: a100: Add CPU Operating Performance Points table
9fa5a7a0ef3c arm64: dts: allwinner: rg35xx: Add no-thermistor property for battery
31b4873bc1a6 arm64: dts: allwinner: h700: Add USB Host for RG35XX-H
a8a5f54af77e arm64: dts: allwinner: h700: Add LED1 for Anbernic RG35XX
d2ec9636e0dc arm64: dts: allwinner: h700: Set cpusldo to always-on for RG35XX
0e8ebe2be1eb dt-bindings: iio: Add adis16550 bindings
6ad196cd05d5 ARM: dts: mba6ul: change sound card model name
8ae441d65592 ARM: dts: imx7-mba7: change sound card model name
69323e39dc4e ARM: dts: imx6qdl-mba6: change sound card model name
6653d0117e05 dt-bindings: crypto: qcom-qce: Document the X1E80100 crypto engine
2c0efa8b0af1 dt-bindings: rng: add binding for Rockchip RK3588 RNG
23feff06013d dt-bindings: reset: Add SCMI reset IDs for RK3588
5b54b653b964 dt-bindings: gpu: mali-bifrost: Add Allwinner H616 compatible
cd5fe0987644 dt-bindings: trivial-devices: Add ti,tps53681
2be45ede3cbe dt-bindings: net: Add Realtek MDIO controller
afae7a251c1c dt-bindings: net: Add switch ports and interrupts to RTL9300
91d08b436193 dt-bindings: net: Move realtek,rtl9301-switch to net
aaf093926eff dt-bindings: gpu: mali-bifrost: Add compatible for RZ/V2H(P) SoC
2819855d187d mips: dts: ralink: mt7620a: update system controller node and its consumers
a2166e814c84 mips: dts: ralink: rt3883: update system controller node and its consumers
339e08846279 mips: dts: ralink: rt3050: update system controller node and its consumers
d3abcf7cf3ae mips: dts: ralink: rt2880: update system controller node and its consumers
84e9b0c2fff8 dt-bindings: clock: add clock definitions for Ralink SoCs
c28b259be385 dt-bindings: arm: coresight-tmc: Add "memory-region" property
f1546685ce0f ARM: dts: renesas: r9a06g032: Fix UART dma channel order
6a6883b926ad arm64: dts: renesas: rzg2: Add boot phase tags
9abb2281477d arm64: dts: renesas: rcar: Add boot phase tags
7795d76bbbc2 ARM: dts: renesas: rcar-gen2: Add boot phase tags
9e0d9f1c47ea arm64: dts: renesas: white-hawk-csi-dsi: Use names for CSI-2 data line orders
dc4f388ab13e arm64: dts: renesas: ulcb/kf: Use TDM Split Mode for capture
7dbc206c43da arm64: dts: renesas: Add initial support for MYIR Remi Pi
ee00ebca3993 arm64: dts: renesas: r9a08g045: Add OPP table
61c8b03d8ef2 arm64: dts: renesas: r9a09g057: Enable SYS node
0815ca2096bf arm64: dts: renesas: r9a09g047: Add SYS node
c36b3a2f01df arm64: dts: renesas: r9a08g045: Enable SYS node
e6d40d0d2cfb arm64: dts: renesas: r8a779f0: Disable rswitch ports by default
44cb5b4c5426 arm64: dts: renesas: r9a08g045s33-smarc-pmod: Add overlay for SCIF1
703f038f08d8 arm64: dts: renesas: rzg3s-smarc: Enable SCIF3
6706d23f287c arm64: dts: renesas: rzg3s-smarc-switches: Add a header to describe different switches
90d900e27288 arm64: dts: renesas: r8a779g0: Restore sort order
78dba0214fc6 arm64: dts: renesas: s4sk: Fix ethernet0 alias for rswitch
65e95070b6ba arm64: dts: renesas: spider-ethernet: Add ethernetN aliases for rswitch
caed2eab1bd4 arm64: dts: renesas: s4sk: Access rswitch ports via phandles
1cacb8200b69 arm64: dts: renesas: spider-ethernet: Access rswitch ports via phandles
a7c45e21fd00 arm64: dts: renesas: r8a779f0: Add labels for rswitch ports
d4ed59cf46f5 arm64: dts: renesas: Add initial device tree for Yuridenki-Shokai Kakip board
e359d28948ce arm64: dts: renesas: eagle-function-expansion: Align GPIO hog name with bindings
3d56ae096af8 arm64: dts: renesas: r8a779h0: Add VSPX instance
ae94b3852fbe arm64: dts: renesas: r8a779h0: Add FCPVX instance
ba28a5391cc6 arm64: dts: renesas: rzg3e-smarc-som: Enable watchdog
bb86f1ab211a arm64: dts: renesas: r9a09g047: Add WDT1-WDT3 nodes
bdfecb224c52 arm64: dts: renesas: gray-hawk-single: Restore sort order
149c2679df26 arm64: dts: renesas: r8a779a0: Add VSPX instances
afdd241afcbc arm64: dts: renesas: r8a779a0: Add FCPVX instances
6c91cfa7eda2 arm64: dts: renesas: gray-hawk-single: Describe AVB1 and AVB2
a6305fea1136 arm64: dts: renesas: r8a779h0: Remove #address- and #size-cells from AVB[0-2]
e384ea6d2c06 arm64: dts: renesas: r8a77990: Re-add voltages to OPP table
b94a86f224ed arm64: dts: renesas: r8a774c0: Re-add voltages to OPP table
73035ca45197 mips: dts: realtek: Add restart to Cisco SG220-26P
da5e72c52240 mips: dts: realtek: Add RTL838x SoC peripherals
e1258dbdceed mips: dts: realtek: Replace uart clock property
05fddbb7ebd9 mips: dts: realtek: Correct uart interrupt-parent
a457e7128f11 mips: dts: realtek: Add SoC IRQ node for RTL838x
57bde8194b75 mips: dts: realtek: Fold rtl83xx into rtl838x
64c98fba1502 mips: dts: realtek: Add address to SoC node name
9f6b4016f45a mips: dts: realtek: Clean up CPU clocks
a015cd4a0443 mips: dts: realtek: Decouple RTL930x base DTSI
e452c3447525 MIPS: mobileye: dts: eyeq6h: Enable cluster support
4913d71e6942 dt-bindings: mips: mips-cm: Add a new compatible string for EyeQ6
0b2d5fd80af4 dt-bindings: mips: Document mti,mips-cm
a429699ec2e2 dt-bindings: ata: Convert fsl,pq-sata to YAML
ac47e5894fc3 dt-bindings: hwinfo: samsung,exynos-chipid: add exynos7870-chipid compatible
93b63c5675fe media: dt-bindings: adv7180: Document the 'interrupts' property
a1c70718bc0f media: dt-bindings: aspeed,video-engine: Convert to json schema
4da9a2e40dd4 dt-bindings: media: st,stmipid02: correct lane-polarities maxItems
ae847cba005e mips: dts: ingenic: Switch to simple-audio-card,hp-det-gpios
f72623fbd64c arm64: dts: rockchip: rk356x: Move PCIe MSI to use GIC ITS instead of MBI
573d01eb7714 arm64: dts: rockchip: rk356x: Add MSI controller node
a62671cb3851 dt-bindings: xilinx: Deprecate header with firmware constants
d48d272341e2 arm64: zynqmp: Use DT header for firmware constants
c2265415c9c1 dt-bindings: power: supply: axp20x-battery: Add x-powers,no-thermistor
1c2d49b11f41 dt-bindings: vendor-prefixes: Document the 'pciclass' prefix
8fe54d8c1e6a dt-bindings: trivial-devices: Add ti,tps546b24
0c947a496323 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
ea5adb18bcaf dt-bindings: mfd: Add maxim,max77705
f5071bfa82eb dt-bindings: power: supply: add maxim,max77705 charger
26b6ca520742 dt-bindings: leds: qcom-lpg: Document PM8937 PWM compatible
115f06126ec6 dt-bindings: leds: backlight: apple,dwi-bl: Add Apple DWI backlight
ec6ae18eb982 spi: dt-bindings: Convert Freescale SPI bindings to YAML
b24a6dbfc7c3 Merge tag 'linux-can-next-for-6.15-20250219' of git://git.kernel.org/pub/scm/linux/kernel/git/mkl/linux-can-next
a17a9095c7fa ARM: dts: nxp: vf: Align GPIO hog name with bindings
90cfeb11e6bd dt-bindings: net: dsa: b53: add BCM53101 support
6df8500248bb dt-bindings: power: reset: xilinx: Make "interrupts" property optional
84dd8dd4c6b0 dt-bindings: power: reset: atmel,sama5d2-shdwc: Add microchip,sama7d65-shdwc
24ab1372bbf2 dt-bindings: input: touchscreen: Add Z2 controller
2dbbd7ff619b ASoC: dt-bindings: atmel-at91sam9g20ek: convert to json-schema
2e73e48c20e4 dt-bindings: usb: samsung,exynos-dwc3 Add exynos990 compatible
c554695fa890 USB: docs: Fix typo in aspeed-lpc.yaml
6f18dd0694b2 dt-bindings: usb: usb-device: Replace free-form 'reg' with constraints
f57d58abdd1f dt-bindings: usb: microchip,usb2514: add support for USB2512/USB2513
22c582f7410c dt-bindings: usb: microchip,usb2514: add support for vdda
bbd705c2b5f9 dt-binding: can: mcp251xfd: remove duplicate word
5ccbb5ed0811 dt-bindings: can: fsl,flexcan: add S32G2/S32G3 SoC support
b3155d3e94f8 dt-bindings: pinctrl: samsung: add exynos2200 compatible
b6ea4790ddc5 dt-bindings: pinctrl: samsung: add exynos2200-wakeup-eint compatible
c7b5bd42aef7 dt-bindings: hwinfo: samsung,exynos-chipid: add exynos2200 compatible
85d161c64b09 dt-bindings: soc: samsung: exynos-pmu: add exynos2200 compatible
467349660659 dt-bindings: soc: samsung: exynos-sysreg: add sysreg compatibles for exynos2200
f3a49191d711 arm64: dts: apple: Add SPI NOR nvram partition to all devices
32fb252ce1f3 arm64: dts: apple: t600x: Add spi controller nodes
7b672e8683fb arm64: dts: apple: t8112: Add spi controller nodes
11383e8e5d7f arm64: dts: apple: t8103: Add spi controller nodes
df2301056fc8 arm64: dts: apple: t8103: Fix spi4 power domain sort order
588bf84fbfc5 riscv: dts: starfive: jh7110-pine64-star64: enable USB 3.0 port
2260adebc79d riscv: dts: starfive: jh7110: pciephy0 USB 3.0 configuration registers
d46cea021cfc riscv: dts: starfive: fml13v01: enable pcie1
aca9a5c6177d riscv: dts: starfive: remove non-existent dac from jh7110
714ea90c3680 arm64: dts: apple: t7000: Add missing CPU p-state 7 for J96 and J97
b27dd2587832 ARM: dts: imx5: Fix the CCM interrupts description
028660f03192 ARM: dts: vfxxx: Fix the CAAM job ring node names
18d135dfe74a arm64: dts: mediatek: mt6359: fix dtbs_check error for audio-codec
1341f30d43e8 Merge drm/drm-next into drm-misc-next
4e43cbdb48d1 ARM: dts: imx53-ppd: Fix touchscreen reset-gpios
4ba7c5cec4fc ARM: dts: imx7s: Move csi-mux to below root
1d0f023c6ebe riscv: sophgo: dts: add cooling maps for Milk-V Pioneer
67fd41fa38f7 riscv: sophgo: dts: add pwm-fan for Milk-V Pioneer
af97acf23d50 dt-bindings: net: ethernet-phy: add property tx-amplitude-100base-tx-percent
3c2fcb7fd8f4 arm64: versal-net: Add description for b2197-00 revA board
51a5e958e52c dt-bindings: soc: Add new VN-X board description based on Versal NET
b3d3914cdb96 ASoC: tas2764: Random patches from the Asahi Linux
17494bd5ec3e riscv: dts: spacemit: Add Milk-V Jupiter board device tree
7154a6c8889d dt-bindings: riscv: spacemit: Add Milk-V Jupiter board compatible
b42bf3977a7b Merge commit '71f0dd5a3293d75d26d405ffbaedfdda4836af32' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next into for-6.15/io_uring-rx-zc
7faa56193b95 ASoC: dt-bindings: wlf,wm8960: add 'port' property
eaa850920663 arm64: dts: imx95-19x19-evk: add typec nodes and enable usb3 node
d145eb78bb29 arm64: dts: imx95: add usb3 related nodes
9e8c9998017c ARM: dts: mxs: Add descriptions for imx287 based btt3-[012] devices
327f79156245 dt-bindings: arm: Document the btt3 i.MX28 based board
77f03f406681 arm64: dts: imx8qm-mek: add audio-codec cs42888 and related nodes
f55a6cd37037 arm64: dts: imx8mq-librem5: remove undocument property 'extcon' for usb-pd@3f
cfac8cba2afb ARM: dts: microchip: sama7d65_curiosity: Add power monitor support
713b56b62a21 arm64: dts: exynosautov920: add CPU cache information
95afa38c66b5 ARM: dts: microchip: sama7d65: Add flexcom 10 node
11815f2bda26 ARM: dts: at91: usb_a9g20_lpw: use proper mmc node name
f2f5d8164a85 ARM: dts: at91: calao_usb: fix button nodes
4320615849bc ARM: dts: at91: use correct vendor name for Calao boards
fc606a98fb4c ARM: dts: at91: calao_usb: remove heartbeat for User LEDs
adf5d3205c13 ARM: dts: at91: calao_usb: fix wrong polarity for LED
02b371776f9f Merge 6.14-rc3 into usb-next
c79ef81e8b3f Merge 6.14-rc3 into tty-next
5d5087e055bc dt-bindings: iio: adc: Introduce ADS7138
81b74faf1bbd dt-bindings: iio: adc: add ADI ad4030, ad4630 and ad4632
4800c4aaad00 arm64: dts: rockchip: Add rng node to RK3588
fb5624b3aff6 dt-bindings: iio: adc: add ad4851
29c6d2f72796 dt-bindings: iio: adc: add ad485x axi variant
2aa06934b04b arm64: dts: exynos: gs101: add ACPM protocol node
9a410d40fffc arm64: dts: exynos: gs101: add AP to APM mailbox node
f67a8cbbc893 arm64: dts: exynos: gs101: add SRAM node
fd1eea66f8ff dt-bindings: firmware: add google,gs101-acpm-ipc
0c84b9a92cd8 dt-bindings: media: clarify stm32 csi & simplify example
cb82b9a812fb arm64: dts: exynos: gs101: add reboot-mode support (SYSIP_DAT0)
cafb5b1128f9 arm64: dts: exynos: gs101: align poweroff writes with downstream
b7103d0c00e2 arm64: dts: exynos: gs101: drop explicit regmap from reboot nodes
388e7272d092 arm64: dts: rockchip: Add devicetree for the ROC-RK3576-PC
89026942ddd0 dt-bindings: arm: rockchip: Add Firefly ROC-RK3576-PC binding
11054a56eb5e arm64: dts: rockchip: minimal support for Pre-ICT tester adapter for RK3588 Jaguar
fa30dcce2020 dt-bindings: soc: qcom: qcom,pmic-glink: Document SM8750 compatible
df945fcbeec5 Merge branch '20250109-qcs8300-mm-patches-new-v4-0-63e8ac268b02@quicinc.com' into clk-for-6.15
7c12a4b2f62e dt-bindings: clock: qcom: Add QCS8300 video clock controller
1f3bb677cac5 dt-bindings: clock: qcom: Add CAMCC clocks for QCS8300
d11f22ad6f0e dt-bindings: clock: qcom: Add GPU clocks for QCS8300
fd809190482c Merge branch '20250203063427.358327-2-alexeymin@postmarketos.org' into clk-for-6.15
5980968a3736 dt-bindings: clock: gcc-sdm660: Add missing SDCC resets
024211d099c3 dt-bindings: clock: gcc-sdm660: Add missing SDCC resets
b8807b3e1cb2 dt-bindings: clock: qcom,rpmcc: Add SDM429
5bce17b9c9ff pmdomain: Merge branch dt into next
82ed9883247a dt-bindings: power: add V853 ppu bindings
68169a0560d8 dt-bindings: serial: Add bindings for nvidia,tegra264-utc
668773b787ac dt-bindings: serial: Allow fsl,ns16550 with broken FIFOs
9648d88104e5 dt-bindings: usb: Add Parade PS8830 Type-C retimer bindings
0c7c8b465ec2 dt-bindings: usb: dwc3: Add a property to reserve endpoints
e939f6d880e2 Merge tag 'drm-misc-next-2025-02-12' of https://gitlab.freedesktop.org/drm/misc/kernel into drm-next
03f675fb2209 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
a1e21c6557d7 dt-bindings: imx: fsl,aips-bus: Ensure all properties are defined
9367c9acdab1 dt-bindings: phy: Add ExynosAutov920 UFS PHY bindings
4e5d9b054e9d dt-bindings: phy: samsung,usb3-drd-phy: gs101: require Type-C properties
7aa26eec3f52 dt-bindings: phy: samsung,usb3-drd-phy: add blank lines between DT properties
8fc192d8c786 dt-bindings: display: bridge: sn65dsi83: Add interrupt
27bd4bb30fdc dt-bindings: power: rpmpd: Fix comment for SM6375
2a0abedef196 arm64: dts: mediatek: mt8188: Add tertiary eMMC/SD/SDIO controller
58186cbc681f arm64: dts: mediatek: mt8188: Add VDO0's DSC and MERGE block nodes
9385b92b564a arm64: dts: mediatek: mt8188: Assign apll1 clock as parent to avoid hang
04c7795892af ARM: dts: ixp4xx: Add Netgear WG302 v1 GPIOs
e672efae7f1f ARM: dts: ixp4xx: Fix up PCI on WG302
dfe984c10836 ARM: dts: Properly assign NPE to ethA
47c38f7af771 loongarch: dts: remove non-existent DAC from 2k1000-ref
aecbe697ed9a ARM: dts: cirrus: ep7211: Align GPIO hog name with bindings
a950ae069eeb arm64: dts: exynos8895: Rename PMU nodes to fixup sorting
6aebfac1f2e6 arm64: dts: mediatek: add device-tree for Genio 510 EVK board
0a53b5690395 arm64: dts: mediatek: mt8390-genio-700-evk: Move common parts to dtsi
cd85db03d191 arm64: dts: marvell: Add missing board compatible for IEI-Puzzle-M801
37f65442ac9b arm64: dts: marvell: Fix missing/incorrect "marvell,armada3710" compatible
3f3f0055504c arm64: dts: marvell: Drop incomplete root compatible/model properties
900bc3ca59b4 dt-bindings: marvell: armada-7k-8k: Add missing 7040 and 8040 board compatibles
fdd9abb2b187 dt-bindings: marvell: armada-7k-8k: Move Armada 8KPlus to schema
42c1447c23e2 dt-bindings: marvell: armada-37xx: Add glinet,gl-mv1000 compatible
94879a4116ea arm64: dts: rockchip: Enable HDMI1 on Orange Pi 5 Max
2a8407332ac4 dt-bindings: pwm: Add support for PWM nexus node
481e9de30692 riscv: dts: starfive: Unify regulator naming scheme
a93373b7988b dt-bindings: media: camss: Add qcom,sdm670-camss
909002479174 arm64: dts: rockchip: linewrap gmac assigned-clocks on Quartz64 Model A/B files a bit
8457c997e974 arm64: dts: rockchip: remove rk3588 optee node
47e426fb98b2 dt-bindings: iio: dac: adi-axi-adc: add ad7606 variant
5116c83b9333 dt-bindings: iio: adc: adi,ad4695: add SPI offload properties
3ca14f0620da dt-bindings: leds: Convert leds-tlc591xx.txt to yaml format
e96e93245d76 dt-bindings: net: rfkill-gpio: enable booting in blocked state
1bf0b9eea5fd arm64: dts: rockchip: Enable HDMI1 out for Edgeble-6TOPS Modules
b0d56064489f arm64: dts: rockchip: Enable HDMI1 on rock-5b
873d0d388c38 arm64: dts: rockchip: Add HDMI1 node on RK3588
8716e9c85925 arm64: dts: rockchip: Add PHY node for HDMI1 TX port on RK3588
ad3eee0eda32 arm64: dts: rockchip: Enable SPDIF output on H96 Max V58
e51f476b2549 arm64: dts: rockchip: Add SPDIF nodes to RK3588(s) device trees
71a14fc267ad dt-bindings: net: smsc,lan9115: Ensure all properties are defined
5de2b7dc7768 dt-bindings: memory-controllers: samsung,exynos4210-srom: Split out child node properties
cd66a94e6d99 dt-bindings: memory-controllers: qcom,ebi2: Split out child node properties
0c6820b22794 dt-bindings: memory-controllers: Move qcom,ebi2 from bindings/bus/
94d614fdbd9a Merge tag 'spi-offload' into togreg
92fae782ee1d Documentation: Remove repeated word in docs
cf9f02118fe1 dt-bindings: phy: qcom,qmp-pcie: Drop reset number constraints
37229c163579 dt-bindings: phy: qcom,qmp-pcie: Add X1P42100 PCIe Gen4x4 PHY
913df9ddc676 dt-bindings: phy: Add rk3576 hdptx phy
33ebb61a9413 dt-bindings: display: panel: Add KD110N11-51IE and 2082109QFH040022-50E
d7efe5059077 dt-bindings: ASoC: rockchip: Add compatible for RK3588 SPDIF
9dd06b8dd8ac dt-bindings: dma: convert atmel-dma.txt to YAML
b25933f5b573 dt-bindings: vendor-prefixes: Update rockchip company name
a8e1f2c3f715 arm64: dts: rockchip: add dts for Ariaboard Photonicat RK3568
0b22b27cde74 dt-bindings: arm: rockchip: Add Ariaboard Photonicat RK3568
7ce8f717740a dt-bindings: vendor-prefixes: Add prefix for Ariaboard
17038a66bb8b arm64: dts: rockchip: switch Rock 5C to PMIC-based TSHUT reset
a7fde791ce29 arm64: dts: rockchip: add 'chassis-type' property on PineNote
acd8eab1d823 dt-bindings: clock: rk3188-common: add PCLK_CIF0/PCLK_CIF1
7d004cf97e38 dt-bindings: soc: renesas: Document MYIR Remi Pi board
d798bb42d18b arm64: dts: apple: t8015: Add cpufreq nodes
142ff02c87ca arm64: dts: apple: t8012: Add cpufreq nodes
423ad63e9ff5 arm64: dts: apple: t8011: Add cpufreq nodes
6fd3a983e7aa arm64: dts: apple: t8010: Add cpufreq nodes
2327e547433d arm64: dts: apple: s8001: Add cpufreq nodes
a5f95a9c11ca arm64: dts: apple: Add cpufreq nodes for S8000/S8003
d48321d9c0a2 arm64: dts: apple: t7001: Add cpufreq nodes
5af5ae6d020a arm64: dts: apple: t7000: Add cpufreq nodes
62a511b2e51a arm64: dts: apple: s5l8960x: Add cpufreq nodes
66b42d66b597 arm64: dts: apple: t8015: Add PMGR nodes
0f7c9deb5489 arm64: dts: apple: t8012: Add PMGR nodes
0f9f2a165a57 arm64: dts: apple: t8011: Add PMGR nodes
cc770ee797ee arm64: dts: apple: t8010: Add PMGR nodes
ab8f4186a843 arm64: dts: apple: s8001: Add PMGR nodes
b5e2aa91fa41 arm64: dts: apple: s800-0-3: Add PMGR nodes
262b4c2c6b63 arm64: dts: apple: t7001: Add PMGR node
4eccd0ed15e8 arm64: dts: apple: t7000: Add PMGR node
5cad2b1f1511 arm64: dts: apple: s5l8960x: Add PMGR node
3ae627f53660 dt-bindings: arm: apple: apple,pmgr-pwrstate: Add A7-A11, T2 compatibles
cf1acfdcd1ab dt-bindings: arm: apple: apple,pmgr: Add A7-A11, T2 compatibles
e6b8b4eb2893 arm64: dts: apple: Add T2 devices
3635f84149d5 dt-bindings: arm: apple: Add T2 devices
ecb90807423a arm64: dts: apple: Split s8000/s8003 SoC DTS files
0332b153fa3e dt-bindings: crypto: Add Inside Secure SafeXcel EIP-93 crypto engine
ad30fd49aa1e ARM: dts: sunxi: add support for NetCube Systems Kumquat
0463c05da755 ARM: dts: sunxi: add uart1_pe pinctrl for sun8i-v3s
64ab025e91c5 dt-bindings: arm: sunxi: Add NetCube Systems Kumquat board
135ecb1c0900 dt-bindings: vendor-prefixes: Add NetCube Systems Austria name
ba07d9983cd2 dt-bindings: iio: adf4371: add refin mode
95eb7af6dfd3 dt-bindings: iio: light: Add APDS9160 binding
32ed0be023c0 dt-bindings: iio: magnetometer: add binding for Si7210
3d902b3b97b5 riscv: sophgo: dts: add pwm controller for SG2042 SoC
c6a0c59c390f spi: dt-bindings: axi-spi-engine: add SPI offload properties
26ad965c5d62 dt-bindings: trigger-source: add generic PWM trigger source
69e102cfc84d dt-bindings: display: panel: Add compatible for CSOT PNA957QT1-1
a854ffec9ddf dt-bindings: vendor-prefixes: add csot
66fd41e84bce dt-bindings: mtd: arasan,nand-controller: Ensure all properties are defined
e0661cab113c dt-bindings: media: Add video support for QCOM SM8550 SoC
1e83da324d74 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
d30a4e7e782c Add static channel mapping between soundwire master
f9d3323c1b73 ASoC: cpcap: Implement jack headset detection
926489106ec0 This is continued work on Samsung S9(SM-9600)
0332d1781ba7 dt-bindings: media: camss: Add qcom,sm8550-camss binding
c6a4614b770b media: dt-bindings: update clocks for sc7280-camss
4c1200c39b8f Merge drm/drm-next into drm-misc-next
70de7a1b60f4 ASoC: dt-bindings: wcd937x-sdw: Add static channel mapping support
33c6fb10fda1 arm64: dts: mediatek: add support for MT8370 SoC
3d0e1130cf33 dt-bindings: arm: mediatek: add mt8370-evk board
d2d62c5d0e90 arm64: dts: rockchip: Fix label name of hdptxphy for RK3588
6605f13b8e1b arm64: dts: rockchip: Add HDMI0 PHY PLL clock source to VOP2 on RK3588
f962971332b4 arm64: dts: rockchip: Enable HDMI0 PHY clk provider on RK3588
1d392f374a7e dt-bindings: display: vop2: Add optional PLL clock properties
5ab646d63942 dt-bindings: display: rockchip: Fix label name of hdptxphy for RK3588 HDMI TX Controller
c2cc31a23d6c Revert "dt-bindings: serial: 8250: Add Airoha compatibles"
41f6c94c3fb4 ARM: dts: omap4-panda-a4: Add missing model and compatible properties
464c5f08f7cf dt-bindings: omap: Add TI Pandaboard A4 variant
66677d9f9b16 ARM: dts: ti/omap: omap4-serial: fix interrupts syntax
a6f47d7ebfcc ARM: dts: ti: omap: Align GPIO hog name with bindings
ffdbb206b0a5 arm64: dts: exynos8895-dreamlte: enable support for the touchscreen
21356aba4c79 arm64: dts: exynos8895-dreamlte: enable support for microSD storage
4b146b3f86ce arm64: dts: exynos8895: add a node for mmc
6a0044cd3e17 arm64: dts: exynos8895: define all usi nodes
2d75cfaed428 arm64: dts: exynos8895: add syscon nodes for peric0/1 and fsys0/1
9649031bcf98 Merge branch 'for-v6.15/samsung-soc-dt-bindings' into next/dt64
5a27c5397796 arm64: dts: exynos990: Rename and sort PMU nodes
fad948b46dc1 arm64: dts: exynos990: Add CMU_PERIS and MCT nodes
f51ef9e1e5ee Merge branch 'for-v6.15/samsung-clk-dt-bindings' into next/dt64
a517cff67d7a dt-bindings: soc: samsung: usi: add USIv1 and samsung,exynos8895-usi
0f0ca5993559 arm64: dts: mediatek: add display support for mt8365-evk
08a19a12abe1 arm64: dts: mediatek: add display blocks support for the MT8365 SoC
cbbc4673a9d2 arm64: dts: mediatek: mt8173: Fix some node names
5b7068d50a96 arm64: dts: mediatek: mt8173: Fix disp-pwm compatible string
3bc44bb385f8 arm64: dts: mediatek: mt8173-elm: Drop pmic's #address-cells and #size-cells
e8d00ab25c72 arm64: dts: airoha: en7581: Add default partition table for EVB board
d8075291fd7f arm64: dts: airoha: en7581: Add SNAND node
63cd70f67e52 arm64: dts: airoha: en7581: Add Clock Controller node
1e23fdb8aebc ASoC: dt-bindings: atmel,at91-ssc: Convert to YAML format
f092663478cd dt-bindings: pwm: sophgo: add PWM controller for SG2042
1f3f3de0aec6 dt-bindings: eeprom: at24: Add compatible for Giantec GT24P128E
4fba896db2e6 dt-bindings: eeprom: at24: Add compatible for Puya P24C64F
6392d4e28d8d dt-bindings: gpio: ast2400-gpio: Add hogs parsing
138b4d48b94a dt-bindings: net: faraday,ftgmac100: Add phys mode
b570187febfc riscv: dts: microchip: update pcie reg properties to new format
42dcb803b930 ASoC: dt-bindings: Add bindings for WCD934x DAIs
09c3b9df3660 dt-bindings: serial: pl011: Add optional power-domains property
4f0c7d1b5ac2 dt-bindings: serial: 8250: Add Airoha compatibles
ee81474fbc7b dt-bindings: serial: Add a new compatible string for UMS9632
9b704b0c3665 dt-bindings: clock: exynos990: Add CMU_PERIS block
a9c4ff6507a2 arm64: dts: exynos: gs101-raven: add new board file
a7bb8998ddf1 arm64: dts: exynos: gs101-oriole: move common Pixel6 & 6Pro parts into a .dtsi
da0ca70f88e6 arm64: dts: exynos: gs101-oriole: configure simple-framebuffer
dac1e08cdece dt-bindings: arm: google: add gs101-raven
080186bec3c2 arm64: dts: exynos: gs101: disable pinctrl_gsacore node
7c74bfc98c0c ARM: zynq: Do not define address/size-cells for nand-controller
ff5e3b12865d dt-bindings: iio: accel: mc3230: document mc3510c
4fc3fd99ee16 dt-bindings: iio: Correct indentation and style in DTS example
3af3fc397fdf dt-bindings: xilinx: Remove desciption for 16550 uart
a4e34a5b5e49 dt-bindings: xilinx: Remove description for SystemACE
7f8cc3643d7a dt-bindings: xilinx: Remove uartlite from xilinx.txt
666456d4cf96 arm64: zynqmp: add clock-output-names property in clock nodes
8a33cbb41574 ARM: zynq: Remove ethernet0 alias from Microzed
8dfe6851b546 ARM: zynq: Add sdhci to alias node
9ddc09b7b0df ARM: zynq: Enable QSPIs on platforms
6d73675978fe ARM: zynq: Fix fpga region DT nodes name
6c76353caff0 ARM: zynq: Rename i2c?-gpio to i2c?-gpio-grp
15fafeb17cb9 ARM: zynq: Define rtc alias on zc702/zc706
831329e67d45 ARM: zynq: Point via nvmem0 alias to eeprom on zc702/zc706
a4f4075bb7d0 ARM: zynq: Define u-boot bootscrip addr via DT
7f8aedee7529 ARM: zynq: Wire smcc with nand/nor memories on zc770 platform
8bcb31d8083c ARM: zynq: Mark boot-phase-specific device nodes
ef23211239f5 ARM: zynq: DT: List OCM memory for all platforms
85f3e03e1434 ARM: zynq: Remove deprecated device_type property
7e6f927d6b95 ARM: zynq: Replace 'io-standard' with 'power-source' property
83abe9885c89 dt-bindings: interrupt-controller: Add risc-v,aplic hart indexes
c05988583566 ARM: dts: stm32: lxa-fairytux2: add Linux Automation GmbH FairyTux 2
f2edad670168 dt-bindings: arm: stm32: add compatible strings for Linux Automation GmbH LXA FairyTux 2
3b3bc35e81ac dt-bindings: soc: renesas: Add RZ/G3E variant SYS binding
cb2e0436ada7 dt-bindings: soc: renesas: Document Yuridenki-Shokai Kakip board
6057199eb478 dt-bindings: vendor-prefixes: Add Yuridenki-Shokai Co. Ltd.
3c4392efd5f9 dt-bindings: soc: renesas: Document more Renesas RZ/V2H SoC variants
c09fc0ef8abe arm64: dts: rockchip: Use "dma-noncoherent" in base RK3588 SoC dtsi
ec750fb661af arm64: dts: rockchip: Describe why is HWRNG disabled in RK356x base dtsi
3aee8aaf8a6c arm64: dts: rockchip: Enable HDMI on armsom-sige7
1660f72aa147 arm64: dts: rockchip: Enable automatic fan control on Radxa Rock 5C
55073acc624c arm64: dts: rockchip: Add finer-grained PWM states for the fan on Rock 5C
b112f324c2a9 arm64: dts: rockchip: Enable USB OTG for Radxa ROCK Pi E
41123c761619 arm64: dts: rockchip: add support for sound output over HDMI on RK3399 Puma Haikou
edc802632427 ARM: dts: ti: davinci: Align GPIO hog name with bindings
8bdeb1cbd5b4 dt-bindings: hwmon: lm90: Add support for NCT7716, NCT7717 and NCT7718
5502124072e1 dt-bindings: hwmon: ltc2978: add support for ltm4673
eb140dbbba76 arm64: dts: imx8mp-skov-reva: Use hardware signal for SD card VSELECT
63a6c68df7cb dt-bindings: regulator: pca9450: Add properties for handling LDO5
cb0906024c41 dt-bindings: mfd: motorola-cpcap: Document audio-codec interrupts
c0cfd3272eb3 dt-bindings: display: renesas,du: add top-level constraints
dba95e8dd801 dt-bindings: display: renesas,du: narrow interrupts and resets per variants
b1ac75c9a524 dt-bindings: display: rockchip: Add rk3576 hdmi controller

git-subtree-dir: dts/upstream
git-subtree-split: fe2d6c49bb4e11ab4de4d2f9bd9234d1407c4f65
2025-05-27 09:02:20 -06:00
Tom Rini
6015a24a5a Merge tag 'dm-next-27may25' of git://git.denx.de/u-boot-dm into next
Sync up Python tools from my tree

- minor binman tweaks
- terminal improvements in u_boot_pylib
- patman move to asyncio
- patman support for new 'series' subcommand
2025-05-27 07:43:04 -06:00
Simon Glass
ec2482a24a patman: Add basic documentation for new features
Describe the new subcommands and how they should be used in a normal
workflow.

Note that the naming of branches is very rigid, or 'opinionated' in
marketing terms. Patman can track a single branch for each version of a
series and they must all be named the same, except for the
version-number suffix. Version 1 series have no suffix.

This description is fairly bare-bones but should be enough for some
initial testing and comments.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:43 +01:00
Simon Glass
a593f84d51 patman: Add tests for Cseries
Add various tests for the Cseries functionality, including both direct
and via-cmdline variants.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:43 +01:00
Simon Glass
cc6ce7157a patman: Implement the upstream subcommand
Add a command to allow managing the upstream tree. This is very basic
so far, only allowing setting the name and URL. Further work may allow
checking whether series apply cleaning on the upstream tree, etc.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:43 +01:00
Simon Glass
d1b6d855ac patman: Implement the series subcommand
Add a command to support management of series. These are local branches
which may have been sent to the mailing list, so may appear on the
patchwork server.

The new functionality uses a database, stored in a local file.

Various operations are supported:
   - add a new series
   - send a series and automatically link it with patchwork
   - 'increment' the version, to prepare to send an updated series
   - gather review/test tags from patchwork
   - check on progress, i.e. patches which are received new tags or
     comments
   - show comments on patches and cover letters

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:43 +01:00
Simon Glass
32d29f7fe4 patman: Update send function to return whether it sent
Indicate whether 'git send-email' was actually called, so that we don't
bother waiting for patchwork to receive our series if it wasn't.

The 'git send-email' seems to always return a code of 0 even if nothing
was sent, so we cannot use clues there. Ideally we would watch the
output to determine which patches were sent and which not, but that is
left for another day.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:43 +01:00
Simon Glass
d6c3f45878 patman: Support aliases for commands and subcommands
It is laborious to type long commands, so add some aliases to speed up
use of patman. For now, allow 'pw' for patchwork and 'st' for status.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:43 +01:00
Simon Glass
3f2b3f96e8 patman: Implement the patchwork subcommand
Add a command to allow setting and getting the patchwork project. This
is needed so that patman can use the correct ID when talking to the
patchwork server.

To support testing, allow passing in the test database, patchwork
object and Cseries object. Fake versions can then easily be provided for
certain test cases.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:43 +01:00
Simon Glass
e8b64cfdbb patman: Improve Series support for patchwork links
Update Series with a way to better manage the Series-links lines in
patches. Use this in the 'status' subcommand instead of the existing
primitive method of expecting a link without a version prefix.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:42 +01:00
Simon Glass
dcf630b3be patman: Introduce basic database support in Series
This class manages a series, i.e. a group of patches with a possible
cover letter. Add some properties for recording basic patchwork info,
including the database ID.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:42 +01:00
Simon Glass
dff62ec8b4 patman: Support returning the parsers to use
The parsing tests need to be able to try invalid arguments to make sure
that these are handled correctly. Provide a way to return the parsers
being used, as well as to pass in the parsers to use. This feature is
needed in test_series_no_subcmd(), for example.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:42 +01:00
Simon Glass
56d33104e1 patman: Use -c to show patch comments
We chose -C as the flag to enable showing comments because -c was used
in 'patman send' to specify the patch count. Now that the 'send' parser
is separated we don't need to do this and it is OK to use the same flag
in a different subcommand.

We want to have a flag for cover-letter comments, so it makes most sense
to have -C for that and -c for patch comments. Update the latter.

Put this in a function since the new 'series' command will add this flag
too.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:42 +01:00
Simon Glass
0ab5e441e7 patman: Enhance implementation of file-based defaults
Patman allows defaults for its command-line flags to be read from a
file. The implementation of this does not fully work with subcommands,
since we don't want a default for those.

Also, it relies on being able to parse any sort of cmdline in order to
figure out the options that are available. But in some cases, the
cmdline may not parse, e.g. if there are required options, or
conflicting options.

Add a class which can be safely used to parse any cmdline, since it
allows execution to continue even when errors are obtained. Use this to
determine the defaults, being careful to skip sub/commands.

Another way to handle all of this would be to maintain the defaults
separately and insert them into the parser manually. For now, I'm not
sure which is best.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:42 +01:00
Simon Glass
42588591e2 patman: Enhance patchwork interface to support Cseries
Add various new requests to the Patchwork class, so we can obtain the
required information. This includes cover letters and comments.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:42 +01:00
Simon Glass
2610699420 patman: Update status command support cover-letter info
Add support to the status module for reading and supporting cover
letters, including comments. Plumb this through to the patchwork module.
The actual support in the latter is not yet integrated.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:42 +01:00
Simon Glass
ce785fd9b7 patman: Add a Cseries class
This is the main class for dealing with series, across branches and the
database.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:42 +01:00
Simon Glass
24e7625085 patman: Add a helper for managing cseries
Add a module which includes helper functions for dealing with Cseries
objects.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:42 +01:00
Simon Glass
ba0c4008f2 patman: Add a simple database implementation
For recording series information, patman needs a database. Add a module
which uses sqlite3 for this. It has a basic schema, enough to support a
series subcommand.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:42 +01:00
Simon Glass
c9efedfc2f patman: Avoid touching the system or local config
Set the git variables to ensure that any local gitconfig is not used or
affected by the tests.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:42 +01:00
Simon Glass
dd16f0e262 patman: Add a fourth series for testing
Create one more series to use for testing. This one has four separate
patches.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:42 +01:00
Simon Glass
1be26d78cf patman: Move common test code into a new module
The func_test file is quite large. In order to allow new tests to be
added to a separate file, move the common test code into a separate
class, to be inherited by other classes.

Drop unnecessary imports in func_test

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:42 +01:00
Simon Glass
d5675b84c4 patman: Add a test for collecting a PATCH prefix
Add one more test for completeness, since this occurs commonly.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:42 +01:00
Simon Glass
77177ba82f patman: Use python3 with /usr/bin/env
If python2 is available then we must specify python3 here. Update the
test to handle this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:42 +01:00
Simon Glass
31a1c4c9d8 u_boot_pylib: Add more functions to gitutil
Add functions for checking a branch, showing a commit, etc. to support
the new functionality.

Git version 2.34.1 ignores --stat if --quiet is given, so adjust the
args so that this performs as expected.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:42 +01:00
Simon Glass
212ed6bdb7 patman: Deal with git safe-directory warning
When running tests where the .git directory is not owned by the current
user, various warnings are produced and the tests fail. This happens in
CI.

For patman itself, modify the gitutil.get_top_level() function to return
None in this case. Ensure that the warning is not shown, since it creates
about 1000 lines of output.

For checkpatch, the same warning is produced even though --no-tree is
given. Suppress that as well.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:42 +01:00
Simon Glass
45f239afa1 u_boot_pylib: Correct pylint warnings in gitutil
Correct various pylint warnings in this file.

The remaining ones are three functions with too many arguments (R0913
and R0918) and use of global (W0603).

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:42 +01:00
Simon Glass
2e680f6765 patman: Support collecting all lines in the commit message
In some cases we want to collect all lines in the commit message so that
the commit can be recreated with the same message as before, or perhaps
with light filtering.

Add support for this.

Series-to: u-boot
Cover-letter:
patman: Minor improvements to prepare for series handling
This series includes a number of internal improvements to patman:
- Tidy-up of parsing
- Adjust how tests create the git tree
- Support for creating patches in a different git directory
- Faster determination of the upstream branch
- Ability to collect the body of a commit message as a series of lines
END

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:42 +01:00
Simon Glass
07dcd1f9b7 patman: Tidy up function comments in the series module
This module is missing some comments, so add them.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:42 +01:00
Simon Glass
2bdb98a282 patman: Move -H out of the send command
This is the help for the whole of patman, so move it to the start of the
control function, rather than being inside 'patman send'.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:42 +01:00
Simon Glass
9126e16e63 patman: Move arguments for sent into the correct parser
Most of the arguments for the main parser are actually arguments for the
'send' parser. Move them there, in a separate function.

Fix a pylint warning for -D and the imports while here.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:42 +01:00
Simon Glass
828e84ac37 patman: Split subparsers into their own functions
Simplify the main parser by moving subparser code into separate
functions. Fix a few pylint warnings while here.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:42 +01:00
Simon Glass
b77a42bc75 patman: Add tests for help
Add a few tests to make sure that help is provided when requested.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:42 +01:00
Simon Glass
79addcc904 patman: Split parser creation from parsing
Tests may want to parse their own arguments. Refactor the parser code to
support this and allow settings to receive arguments as well.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:42 +01:00
Simon Glass
a52e80aee7 patman: Correct some pylint and asyncio issues
Correct some pylint warnings in this file. Make use of the existing
asyncio event loop, instead of creating a new one, since this also
destroys it afterwards, making it unavailable for tests which want to
share an event loop. Use tools.write_file() to avoid a warning about
encoding.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:42 +01:00
Simon Glass
8465b44cb5 patman: Use git to set up the test config
At present the branch information is dropped when writing the
configuration. It is easier to get git to set up the config anyway, so
update the test to do this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:42 +01:00
Simon Glass
3724cbade4 patman: Clean up creation of the git tree
The test starts with the HEAD pointing to the wrong place, so that the
created files appear to be deleted. Fix this by resetting the tree
before tests start. Add a check that the tree is clean.

Update pygit2 so that the enums are available.
2025-05-27 10:07:42 +01:00
Simon Glass
9302d672a5 patman: Use variables for series ID and title
Rather than hard-coding these values in the sample patches, use
variables so that we can refer to these in tests.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:42 +01:00
Simon Glass
6961eb7e5b patman: Use .git as the git directory
In tests, the 'git' directory is a subdirectory of the temporary
directory. Rename it to '.git' so that git will automatically find it
when git operations are done in the temporary directory. Set up the
config before the first git operation, so that this works correctly.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:42 +01:00
Simon Glass
8e737d41c0 patman: Use itr instead of lines for iterator
The variables 'lines' is used to hold a list of output lines within a
test, but also to hold an iterator through those lines. Use 'itr' for
the latter, to avoid confusion.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:42 +01:00
Simon Glass
8896247b58 patman: Correct use of str in code
Since str() is a reserved function we should not use it as a variable.
Fix this in the send module.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:42 +01:00
Simon Glass
a5afb75c6d patman: Allow setting a git directory when sending
Support specifying the git-directory when creating and sending patches.
This will allow better testing of this functionality, since we can use a
test directory.

For count_commits_to_branch() support an end commit while we are here.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:42 +01:00
Simon Glass
60b8709b98 patman: Allow setting the current directory when sending
Plumb a current-working-directory (cwd) through from send all the way to
the command gitutil libraries. This will allow better testing of this
functionality, since we can use a test directory.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:42 +01:00
Simon Glass
4f7bd6cae8 patman: Add all files to __init__.py
Some files are missing from the __all__ list, so add then. Reformat the
list to use more of the width of each line.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:42 +01:00
Simon Glass
afea95f653 u_boot_pylib: Speed up determining the upstream branch
Use --decorate to quickly detect the upstream branch, since this is much
faster than using 'git name-rev' on every possible commit.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:42 +01:00
Simon Glass
c885917c71 u_boot_pylib: Provide directories to gitutil functions
For testing it is useful to be able to set the current directory used
for git operations, as well as the git-repo directory. Update some of
the functions to support this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:42 +01:00
Simon Glass
0664a956e6 u_boot_pylib: Tidy up quoting of cc and to
The current approach to calling 'git send-email' puts double quotes
around each email address to ensure that it will pass the shell
correctly. This is a bit cumbersome and requires using a shell to sort
it all out.

Drop the quotes and use command.run() instead, to simplify things. This
will also make it possible to (later) set the current directory.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:42 +01:00
Simon Glass
db5d98de55 u_boot_pylib: Support a fatal level in tout
It is convenient to be able to print a message and exit. Add a new
'fatal' level to support this.

Update some assumptions about the level, so that the tools continue to
work as now.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:42 +01:00
Simon Glass
75ae217194 patman: Update Series.ShowActions() to pass alias
Instead of using settings.alias pass this value in. This allows tests to
work without using settings.alias

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:42 +01:00
Simon Glass
abfd67cccf patman: Pass aliases to Series.MakeCcFile()
Rather than accessing settings directly, pass the aliases in, so that
we can do the same from tests. With further work this will allow the
tests to work without using settings.alias

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:41 +01:00
Simon Glass
e10201aa8c patman: Pass the alias dict into gitutil.email_patches()
Rather than accessing the settings module in this function, require the
alias dict to be passed in.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:41 +01:00
Simon Glass
7dc55435b2 patman: Pass the alias dict into gitutil.build_email_list()
Rather than accessing the settings module in this function, require the
alias dict to be passed in.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:41 +01:00
Simon Glass
e70fdbd7e4 patman: Untangle settings from gitutil
The gitutil module is supposed to be independent from patman but one
piece was missed in the series which separated them.

Move the settings setup out of gitutil

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:41 +01:00
Simon Glass
f9b84f9141 patman: Drop the old status code
Now that we have the new asyncio implementation, drop the unused
ThreadPoolExecutor code.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:41 +01:00
Simon Glass
605717405f patman: Use a pager when outputting status
The pager makes it easier to review large number of comments. Add it
around the output.

Patman normally sends multiple concurrent requests to the patchwork
server, as this is faster. Provide an option to disable this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:41 +01:00
Simon Glass
52aef33f95 patman: Provide an option to run in single-threaded mode
Patman normally sends multiple concurrent requests to the patchwork
server, as this is faster. Provide an option to disable this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:41 +01:00
Simon Glass
45f4f62191 patman: Switch over to asyncio
Now that all the pieces are in place, switch over from using an executor
to using asyncio.

While we are here, import defaultdict to avoid needing to specify its
module.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:41 +01:00
Simon Glass
39f258494f patman: Use defaultdict directly
Import defaultdict to avoid needing to specify its module in multiple
places. Fix an extra blank line while here.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:41 +01:00
Simon Glass
0fb0b46200 patman: Add more information to Patch
The cover letter has some information on each patch, so allow this to be
stored in the Patch object.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:41 +01:00
Simon Glass
7052173fae patman: Show patches in yellow
When comments are shown below patches it can be hard to see the patch
subject. Use yellow instead of blue, since it stands out better.

Pass the colour object into show_responses() rather than creating a new
one, since that is tidier.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:41 +01:00
Simon Glass
289f4242c5 patman: Simplify test_find_new_responses()
This test uses the find_new_responses() function which combines
accessing patchwork and processing the results.

Since the test is aimed at testing processing, adjust it to call
process_reviews() instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:41 +01:00
Simon Glass
3fd99e2177 patman: Adjust how the fake request() function is provided
Instead of passing the URL and function to each call, put the fake
into the Patchwork object instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:41 +01:00
Simon Glass
3c5f27ce12 patman: Split out the processing of find_new_responses()
This function does patchwork calls and then processes the results. Move
the processing out so we can (later) test it separately.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:41 +01:00
Simon Glass
d63b075062 patman: Split up check_and_show_status()
This function has three phases:

- collecting things from patchwork
- doing some processing
- showing the results to the user / creating a branch

Refactor into two functions so we can eventually have the patchwork part
fully separated out.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:41 +01:00
Simon Glass
e2a991398d patman: Rename check_patchwork_status()
This function actually shows the status and does some other things.

Rename it to better reflect its purpose.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:41 +01:00
Simon Glass
d65490650f patman: Add reading of series and patch status
Expand the patchwork module so that it can match the current
requirements of the 'patman status' command, i.e. reading the state of a
series and the patches associated with it.

Since the format of each patchwork response is a little tricky to
understand, add examples in comments at the top of each function.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:41 +01:00
Simon Glass
24776ab276 patman: Move Patch and Review to patchwork module
These relate to information obtained from the patchwork server, so move
their definition into the new patchwork module.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:41 +01:00
Simon Glass
aef44950db patman: Create a module for handling patchwork
At present the patchwork implementation is very simple, just consisting
of a function which calls the REST API.

We want to create a fake patchwork for use in tests. So start a new
module to encapsulate communication with the patchwork server.

Use asyncio since it is easier to handle lots of concurrent requests
from different parts of the code.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:41 +01:00
Simon Glass
31d458b35d CI: Add a dependency file for patman
Now that patman has an unusual dependency, add a requirements.txt file
and use it in CI

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:41 +01:00
Simon Glass
770602195c patman: Move code for sending into its own module
The control module includes much of the implementation of patman's
'send' feature. As a first step to separating this out, move the sending
code into its own file.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:41 +01:00
Simon Glass
eca4653835 patman: Support extra test features
Provide support for the -X flag, which preserves the working directory
used by tests. Also support -N which shows captured output for tests.

Finally, allow selection of a particular test to run.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:41 +01:00
Simon Glass
6e64ae22c2 patman: Tidy up the start-up code
Much of this was written before the other Python tools and they have
evolved. Make a few updates:

- Rather than calling sys.exit(), return the exit code from the control
  module and use it in __main__
- Set up tout as it is used in some places
- We now have quite a few tests, so update the comment about that

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:41 +01:00
Simon Glass
f5ec4f05f9 patman: Rename test_basic() in test_checkpatch
This currently has the same name as a test in func_test.py so it isn't
possible to select one or the other with 'patman test test_basic': both
are executed.

Rename this one to avoid confusion.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:41 +01:00
Simon Glass
5053549532 patman: Correct a stray quote
A quote character was added a few years ago, but was not intended. Drop
it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:41 +01:00
Simon Glass
a61635d2af tools: Plumb in capture control
Add control of capturing output into u_boot_pylib and the tools which
use it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:41 +01:00
Simon Glass
9dee86cf53 u_boot_pylib: Allow disabling colour output
When running tests there is no situation in which we want ANSI output as
it makes it much harder to see what is going on in logs, tests, etc.

Provide a way to disable this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:41 +01:00
Simon Glass
55342144af u_boot_pylib: Avoid concurrent execution of only one test
There is no point in spinning up multiple processes if there is only one
test to execute. Add a check for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:41 +01:00
Simon Glass
1f18e8798f u_boot_pylib: Add a pager
It is useful to have a pager when outputting a lot of text. Add support
for this in the terminal library, making use of a context manager.

Also add a function to indicate whether the output device is a terminal
or not, while we are here, to avoid duplicating this code.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:41 +01:00
Simon Glass
f74c6f9a81 u_boot_pylib: Improve ANSI-colour output with backgrounds
The current implementation does not handle background colours very well:

- It outputs an incorrect code in some cases, leading to wrong colours
- Some functions lack a control for the background

Tidy this up so that background colours can be used in more places.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:41 +01:00
Simon Glass
b697480f19 u_boot_pylib: Allow control of capturing
Tests often capture output so they can check it. This means that if the
test fails it is not easy to see what the output actually was.

Add a -N flag which writes out the output after it has been captured.
This is not a perfect solution but it is simple and seems to work well
in practice.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:41 +01:00
Simon Glass
84f3deaa99 binman: Correct a typo in the toolpath comment
Fix the 'ist' typo in the comment for TestFunctional

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:41 +01:00
Simon Glass
ae3695f691 patman: Move capture_sys_output() into terminal and rename
This function is sometimes useful outside tests. Also it can affect how
terminal output is done, e.g. whether ANSI characters should be emitted
or not.

Move it out of the test_util package and into terminal.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:41 +01:00
Simon Glass
6330f94a35 patman: Move all non-test logic into control module
It is easier for tests if the top-level control logic is all in one
module. Create a new do_patman() function to handle this. Move the
existing code into it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:41 +01:00
Simon Glass
92d5d1e1cd binman: x86: Write skip-at-start when end-at-4gb is used
The end-at-4gb property implies a value for skip-at-start so add it into
the output FDT so that U-Boot can read it.

Now that skip-at-start is implemented, we can drop the workarounds used
in the x86 code to obtain the correct image-pos value.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:39 +01:00
Simon Glass
96b0a77da0 binman: Read the skip-at-start value on startup
This value provides an offset for all image-pos values in the image.
Read it on startup so that we can take account of it when calculating
positions.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 10:07:36 +01:00
Simon Glass
c3d3534806 buildman: Add a way to build a particular target
At present buildman only supports building the default target. Generally
this is what is wanted, but in some cases boards erroneously have a
different target for product extra files.

Add a --target option to help. Also add a comment indicating which
letters are free for new options.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-27 09:57:06 +01:00
Tom Rini
39b815d02d Merge tag 'v2025.07-rc3' into next
Prepare v2025.07-rc3
2025-05-26 16:07:19 -06:00
SkyLake.Huang
bab54f5942 net: phy: Do not do CL22 phy reset before ethernet phy driver probe
Remove unnecessary CL22 phy reset before ethernet phy driver
probe. Lots of ethernet phys requires driver to load firmware.
Before that, CL22 phy reset may lead to malfunction.

Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
2025-05-23 11:33:37 -06:00
Alexander Sverdlin
4434045647 net: tftp: don't call stop callback from UDP handler
Contrary to doc/develop/driver-model/ethernet.rst contract, eth_ops
.free_pkt can be called after .stop, there are several error paths in TFTP,
for instance:

eth_halt() <= tftp_handler() <= net_process_received_packet() <= eth_rx()
...
am65_cpsw_free_pkt() <= eth_rx()

Which results in (deliberately "tftpboot"ing non-existing file):

TFTP error: 'File not found' (1)
Not retrying...
am65_cpsw_nuss_port ethernet@8000000port@1: RX dma free_pkt failed -22

Avoid the DMA error message (and follow the documentation) by deferring
eth_halt() until net_loop() calls net_start_again() and only do
eth_halt_state_only() instead.

Fixes: aafda38fb2 ("Add error codes/handling for TFTP-server")
Signed-off-by: Alexander Sverdlin <alexander.sverdlin@siemens.com>
2025-05-23 11:33:18 -06:00
Tom Rini
da24eb5532 Merge patch series "BOOTP/DHCPv4 enhancements"
Sean Edmond <seanedmond@microsoft.com> says:

In our datacenter application, a single DHCP server is servicing 36000+ clients.
Improvements are required to the DHCPv4 retransmission behavior to align with
RFC and ensure less pressure is exerted on the server:
- retransmission backoff interval maximum is configurable
  (environment variable bootpretransmitperiodmax)
- initial retransmission backoff interval is configurable
  (environment variable bootpretransmitperiodinit)
- transaction ID is kept the same for each BOOTP/DHCPv4 request
  (not recreated on each retry)

For our application we'll use:
- bootpretransmitperiodmax=16000
- bootpretransmitperiodinit=2000

A new configuration BOOTP_RANDOM_XID has been added to enable a randomized
BOOTP/DHCPv4 transaction ID.

Enhance DHCPv4 sending/parsing option 209 (PXE config file).  A previous
patch was accepted.  A new patch fixes a possible double free() and
addresses latest review comments.

Link: https://lore.kernel.org/r/20240509023918.2504185-1-seanedmond@microsoft.com
2025-05-23 11:31:03 -06:00
Sean Edmond
2111bd7e93 net: bootp: add config option BOOTP_RANDOM_XID
The new config option BOOTP_RANDOM_XID will randomize the transaction ID
for each new BOOT/DHCPv4 exchange.

Signed-off-by: Sean Edmond <seanedmond@microsoft.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2025-05-23 11:28:51 -06:00
Sean Edmond
e6bca3305b net: bootp: BOOTP/DHCPv4 retransmission improvements
This patch introduces 3 improvements to align with RFC 951:
- retransmission backoff interval maximum is configurable
- initial retranmission backoff interval is configurable
- transaction ID is kept the same for each BOOTP/DHCPv4 request

In applications where thousands of nodes are serviced by a single DHCP
server, maximizing the retransmission backoff interval at 2 seconds (the
current u-boot default) exerts high pressure on the DHCP server and
network layer.

RFC 951 “7.2. Client Retransmission Strategy” states that the
retransmission backoff interval should be limited to 60 seconds.  This
patch allows the interval to be configurable using the environment
variable "bootpretransmitperiodmax"

The initial retranmission backoff period defaults to 250ms, which is
also too small for these scenarios with many clients.  This patch makes
the initial retransmission interval to be configurable using the
environment variable "bootpretransmitperiodinit".

Also, on a retransmission it is not expected for the transaction ID to
change (only the 'secs' field should be updated). Let's save the
transaction ID and use the same transaction ID for each BOOTP/DHCPv4
exchange.

Signed-off-by: Sean Edmond <seanedmond@microsoft.com>
2025-05-23 11:28:51 -06:00
Sean Edmond
c867045eef net: Enhancements for dhcp option 209
- Enable option 209 by default
- Set pxelinux_configfile to NULL to avoid potential double free
- change hardcoded 209 to a define

Signed-off-by: Sean Edmond <seanedmond@microsoft.com>
2025-05-23 11:28:51 -06:00
Aristo Chen
ef305ceff9 cmd: ximg: handle Z_BUF_ERROR explicitly in GZIP decompression
When decompressing GZIP-compressed image parts via the `imxtract` command,
explicitly handle the `Z_BUF_ERROR` return value from `gunzip()` to provide
a clearer diagnostic. This error typically indicates that the destination
buffer is too small to hold the uncompressed data.

Signed-off-by: Aristo Chen <aristo.chen@canonical.com>
[trini: Rework to indent the whole case with { } due to not using the
C23 extension]
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-05-22 14:26:38 -06:00
Ben Dooks
86acdce2ba common: add config for board_init() call
Add CONFIG_BOARD_INIT to specifu if the board_init() needs calling
during initcall phase, and default it to 'y' for the relevant
architectures which probably need it.

This allows anyone with a board that doesn't need it to just remove
it from the initcall list w/o an empty code block in the board init
file.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Reviewed-by: Tom Rini <trini@konsulko.com>
2025-05-22 13:55:17 -06:00
Weijie Gao
1bf2121297 clk: mediatek: add dummy clk enable/disable ops for apmixedsys clocks
Starting from commit ac30d90f33 (clk: Ensure the parent clocks are enabled
while reparenting), MediaTek filogic platforms will crash on booting when
initializing mmc devices.

The root cause is that to simplify the code, we reused the topckgen ops for
apmixedsys clocks as they share the get_rate with topckgen clocks while the
clk enable/disable ops are not available for apmixedsys clocks.

Now that a clock will be enabled first before reparenting, we have to add
dummy enable/disable ops for apmixedsys to avoid unexpected behavior when
apmixedsys clocks are the parent clock of the to-be-reparenting clocks.

Fixes: 40746bf429 (clk: mediatek: add clock driver support for MediaTek MT7981 SoC)
Fixes: 37d5a9a29d (clk: mediatek: add clock driver support for MediaTek MT7986 SoC)
Fixes: ece4e5804f (clk: mediatek: add clock driver support for MediaTek MT7987 SoC)
Fixes: 421436981a (clk: mediatek: add clock driver support for MediaTek MT7988 SoC)
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2025-05-22 13:55:05 -06:00
Bryan Brattlof
d47af3aff5 arm: dts: k3: require mandatory firmware in binman
TI's Foundational Security (TIFS), Device Management (DM) and Device
Management and Security Control (DMSC) firmware are required for a
successful boot. Remove the 'optional' flag so binman will emit an error
if these firmware components are not found

Signed-off-by: Bryan Brattlof <bb@ti.com>
Acked-by: Wadim Egorov <w.egorov@phytec.de>
2025-05-22 13:54:22 -06:00
Emanuele Ghidoli
df8dbc87a2 configs: verdin-am62: Drop unused or redundant config options
Several Kconfig options are enabled but unused or unnecessary for our
use case. These include features such as SPL FAT support, YMODEM, and
USB keyboard. Some R5-specific configurations are not used at all,
as U-Boot proper is not executed on that core.

Cleaning them up helps reduce build size and simplifies maintenance.

Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com>
2025-05-22 13:54:11 -06:00
Wadim Egorov
1385e4be42 configs: phycore_am6xx_a53_defconfig: Enable BOOTDEV_SPI_FLASH
Enable standard boot with SPI Flash & sync after savedefconfig.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
2025-05-22 13:53:51 -06:00
Wadim Egorov
cd48860fec board: phytec: common: k3: Factor out mac address setup
Factor out the mac address setup into setup_mac_from_eeprom().

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
2025-05-22 13:51:56 -06:00
Wadim Egorov
5900a2db4b board: phytec: common: k3: Update boot_targets at runtime
Factor out boot device detection from board_late_init() into a new
boot_targets_setup() helper.

Adjust the boot_targets environment variable to favor the device we
just booted from. If boot_targets is still at its default value,
prepend the current boot device to the list; otherwise leave any
user-customized order untouched.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
2025-05-22 13:51:56 -06:00
Wadim Egorov
7fbadff8a7 configs: phycore_am6xx: Default BOOTCOMMAND to standard boot
Make the "bootflow scan -lb" command execute first and
fallback to the legacy BSP boot scripts.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
2025-05-22 13:51:55 -06:00
Wadim Egorov
e423e35d0d board: phytec: phycore_am6xx: Set bootmeths & boot_targets environment
As part of our migration to the standard boot process, configure the
default values for the bootmeths and boot_targets environment variables.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
2025-05-22 13:51:55 -06:00
Nathan Morrisson
04c1a5b0d6 board: phytec: phycore_am64x: Update environment for fitboot
Add fit_addr_r to the environment to allow us to boot from a FIT image.

Signed-off-by: Nathan Morrisson <nmorrisson@phytec.com>
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
2025-05-22 13:51:55 -06:00
Nathan Morrisson
fdd2af2c13 board: phytec: phycore_am62x: Update environment for fitboot
Add fit_addr_r to the environment to allow us to boot from a FIT image.

Signed-off-by: Nathan Morrisson <nmorrisson@phytec.com>
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
2025-05-22 13:51:55 -06:00
Christoph Niedermaier
1e24e84db4 tiny-printf: Handle formatting of %p with an extra Kconfig
The formatting with %pa / %pap behaves like %x, which results in an
incorrect value being output. To improve this, a new fine-tuning
Kconfig SPL_USE_TINY_PRINTF_POINTER_SUPPORT for pointer formatting
has been added. If it is enabled, the output of %pa / %pap should
be correct, and if it is disabled, the pointer formatting is
completely unsupported. In addition to indicate unsupported formatting,
'?' will be output. This allows enabling pointer formatting only
when needed. For SPL_NET it is selected by default. Then it also
supports the formatting with %pm, %pM and %pI4.

In summery this level of %p support for tiny printf is possible now:

1) The standard tiny printf won't have support for pointer formatting.
   So it doesn't print misleading values for %pa, instead '?' will be
   output:
   %p   => ?
   %pa  => ?a
   %pap => ?ap

2) If SPL_USE_TINY_PRINTF_POINTER_SUPPORT is enabled or DEBUG is defined
   tiny printf supports formatting %p and %pa / %pap.

3) If SPL_NET is enabled the support of pointers is extended
   for %pm, %pM and %pI4.

Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
2025-05-22 10:57:12 -06:00
Johannes Krottmayer
0a00637157 arm: cpu: armv7m: add ENTRY/ENDPROC macros
Since GNU binutils version 2.44, assembly functions must include
the assembler directive .type name, %function. If not a call to
these functions fails with the error message 'Unknown destination
type (ARM/Thumb)' and the error message 'dangerous relocation:
unsupported relocation' at linking.

The macros ENTRY/ENDPROC includes this directive and should be
used for all assembly functions.

Signed-off-by: Johannes Krottmayer <johannes@krotti42.com>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2025-05-22 10:57:12 -06:00
Tom Rini
0bc9b288fa Merge tag 'dm-pull-16may25' of git://git.denx.de/u-boot-dm into next
Bring in the strim() changes and associated test
2025-05-16 08:33:18 -06:00
Simon Glass
13223f8ea1 test: Add a test for strim()
This function trims whitespace from the start and end of a string. Add a
test for it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-16 06:21:37 +02:00
Simon Glass
aea684a0c3 strim: Sync up with Linux version
Linux changed the behaviour of strim() so that a string with only spaces
reduces places the terminator at the start of the string, rather than
returning a pointer to the end of the string.

Bring in this version, from Linux v6.14

Add a comment about the new behaviour.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-05-16 06:21:36 +02:00
Tom Rini
5b82721337 include/command.h: Drop <env.h>
Now that all of the cases of code that relied on <command.h> to provide
<env.h> (or one of the headers that it includes, and so forth) have been
fixed, we can drop the include from here.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-05-14 13:38:54 -06:00
Tom Rini
7894816a98 global: Avoid indirect inclusion of <env.h> from <command.h>
The include file <command.h> does not need anything from <env.h>.
Furthermore, include/env.h itself includes other headers which can lead
to longer indirect inclusion paths. To prepare to remove <env.h> from
<command.h> fix all of the places which had relied on this indirect
inclusion to instead include <env.h> directly.

Signed-off-by: Tom Rini <trini@konsulko.com>
---
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Cc: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Jerome Forissier <jerome.forissier@linaro.org>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Lukasz Majewski <lukma@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Mark Kettenis <kettenis@openbsd.org>
Cc: Masahisa Kojima <kojima.masahisa@socionext.com>
Cc: Mattijs Korpershoek <mkorpershoek@kernel.org>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Cc: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Stefan Bosch <stefan_b@posteo.net>
Cc: Tien Fong Chee <tien.fong.chee@altera.com>
Cc: Tingting Meng <tingting.meng@altera.com>
Cc: Tobias Waldekranz <tobias@waldekranz.com>
2025-05-14 13:34:36 -06:00
Tom Rini
f97cfef5d9 gpio: pca953x: Add missing <asm/byteorder.h>
This driver takes a long implicit include path to get this header which
it directly uses. Add it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-05-14 12:39:35 -06:00
Tom Rini
2f0bf852ab cmd/mem.c, test/cmd/mem_copy.c: Add <compiler.h>
These files require <compiler.h> in order to have MEM_SUPPORT_64BIT_DATA
be defined but currently rely on a long indirect include path to get it.
Add this directly.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-05-14 12:21:31 -06:00
Tom Rini
60e313d5c6 global: Add <linux/string.h> instead of long indirect include path
In a number of cases we have C files which rely on a chain of indirect
include paths to get <linux/string.h> to be included via <command.h>. To
facilitate cleaning up <command.h> make this code directly include
<linux/string.h>.

Signed-off-by: Tom Rini <trini@konsulko.com>
---
Cc: Andrew Davis <afd@ti.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Dai Okamura <okamura.dai@socionext.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Francesco Dolcini <francesco.dolcini@toradex.com>
Cc: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Cc: Jens Wiklander <jens.wiklander@linaro.org>
Cc: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Cc: Mingkai Hu <mingkai.hu@nxp.com>
Cc: Priyanka Jain <priyanka.jain@nxp.com>
Cc: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefano Babic <sbabic@nabladev.com>
Cc: Svyatoslav Ryhel <clamor95@gmail.com>
Cc: Thierry Reding <treding@nvidia.com>
Cc: William Zhang <william.zhang@broadcom.com>
2025-05-14 12:15:31 -06:00
Tom Rini
4c26de2eea fs.h: Switch to using rtc_def.h
This file only needs the definition of 'struct rtc_time' and that is
found in <rtc_def.h>. Use that instead of pulling in rtc.h to pull in
rtc_def.h as rtc.h includes many other include files.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-05-13 11:30:09 -06:00
Tom Rini
a367817c9a fat.c: Add missing include
This file references rtc functions and implicitly includes <rtc.h>
today. Add this explicitly.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-05-13 11:30:09 -06:00
Tom Rini
720e0c0f1a ext4fs.c: Add missing include
This file references rtc functions and implicitly includes <rtc.h>
today. Add this explicitly.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-05-13 11:30:08 -06:00
Tom Rini
cfa00751b0 cmd/cat.c: Add missing include
This file references errno values and so needs to include
<linux/errno.h>.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-05-13 11:30:08 -06:00
5589 changed files with 238335 additions and 94555 deletions

View File

@@ -2,7 +2,7 @@ variables:
windows_vm: windows-2022
ubuntu_vm: ubuntu-24.04
macos_vm: macOS-14
ci_runner_image: trini/u-boot-gitlab-ci-runner:jammy-20250404-29Apr2025
ci_runner_image: trini/u-boot-gitlab-ci-runner:jammy-20250714-25Jul2025
# Add '-u 0' options for Azure pipelines, otherwise we get "permission
# denied" error when it tries to "useradd -m -u 1001 vsts_azpcontainer",
# since our $(ci_runner_image) user is not root.
@@ -251,7 +251,7 @@ stages:
# the below corresponds to .gitlab-ci.yml "before_script"
cd \${WORK_DIR}
git config --global --add safe.directory \${WORK_DIR}
git clone --depth=1 https://source.denx.de/u-boot/u-boot-test-hooks /tmp/uboot-test-hooks
git clone --depth=1 https://github.com/u-boot/u-boot-test-hooks /tmp/uboot-test-hooks
# qemu_arm64_lwip_defconfig is the same as qemu_arm64 but with NET_LWIP enabled.
# The test config and the boardenv file from qemu_arm64 can be re-used so create symlinks
ln -s conf.qemu_arm64_na /tmp/uboot-test-hooks/bin/travis-ci/conf.qemu_arm64_lwip_na
@@ -316,9 +316,20 @@ stages:
fi
export PATH=/opt/qemu/bin:/tmp/uboot-test-hooks/bin:\${PATH}
export PYTHONPATH=/tmp/uboot-test-hooks/py/travis-ci
python3 -m http.server 80 --directory "\${UBOOT_TRAVIS_BUILD_DIR}" > /dev/null 2>&1 &
HTTP_PID=\$!
sleep 1 # Give the server a moment to start
if ps -p \${HTTP_PID} > /dev/null; then
export HTTP_PID
else
unset HTTP_PID
fi
# "\${var:+"-k \$var"}" expands to "" if \$var is empty, "-k \$var" if not
./test/py/test.py -ra -o cache_dir="\$UBOOT_TRAVIS_BUILD_DIR"/.pytest_cache --bd \${TEST_PY_BD} \${TEST_PY_ID} \${TEST_PY_EXTRA} \${TEST_PY_TEST_SPEC:+"-k \${TEST_PY_TEST_SPEC}"} --build-dir "\$UBOOT_TRAVIS_BUILD_DIR" --report-dir "\$UBOOT_TRAVIS_BUILD_DIR" --junitxml=\$(System.DefaultWorkingDirectory)/results.xml
# the below corresponds to .gitlab-ci.yml "after_script"
if [[ -n "\${HTTP_PID}" ]]; then
kill \${HTTP_PID};
fi
rm -rf /tmp/uboot-test-hooks /tmp/venv
EOF
- task: CopyFiles@2
@@ -520,10 +531,11 @@ stages:
TEST_PY_BD: "r2dplus"
TEST_PY_ID: "--id tulip_qemu"
TEST_PY_TEST_SPEC: "not sleep"
sifive_unleashed_sdcard:
TEST_PY_BD: "sifive_unleashed"
TEST_PY_ID: "--id sdcard_qemu"
TEST_PY_TEST_SPEC: "not sleep"
# This is broken upsteam: https://gitlab.com/qemu-project/qemu/-/issues/2945
# sifive_unleashed_sdcard:
# TEST_PY_BD: "sifive_unleashed"
# TEST_PY_ID: "--id sdcard_qemu"
# TEST_PY_TEST_SPEC: "not sleep"
sifive_unleashed_spi-nor:
TEST_PY_BD: "sifive_unleashed"
TEST_PY_ID: "--id spi-nor_qemu"

6
.b4-config Normal file
View File

@@ -0,0 +1,6 @@
# Configuration for the `b4` tool
# See https://b4.docs.kernel.org/en/latest/config.html
[b4]
send-auto-to-cmd = scripts/get_maintainer.pl --nogit --nogit-fallback --nogit-chief-penguins --norolestats --nom
send-auto-cc-cmd = scripts/get_maintainer.pl --nogit-fallback --nogit-chief-penguins --norolestats --nol

1
.gitattributes vendored
View File

@@ -6,4 +6,3 @@
*.ttf binary
*.gz binary
*.png binary
*.svg binary

6
.gitignore vendored
View File

@@ -56,11 +56,12 @@ fit-dtb.blob*
/*.log
#
# git files that we don't want to ignore even it they are dot-files
# We don't want to ignore the following even if they are dot-files
#
!.get_maintainer.*
!.gitattributes
!.gitignore
!.mailmap
!.get_maintainer.*
#
# Generated files
@@ -75,6 +76,7 @@ fit-dtb.blob*
/keep-syms-lto.*
/*imx8mimage*
/*imx8mcst*
/*rcar4-sa0*
/drivers/video/u_boot_logo.S
/test/overlay/test-fdt-overlay.dtbo.S
/test/overlay/test-fdt-overlay-stacked.dtbo.S

View File

@@ -20,7 +20,7 @@ workflow:
# Grab our configured image. The source for this is found
# in the u-boot tree at tools/docker/Dockerfile
image: ${MIRROR_DOCKER}/trini/u-boot-gitlab-ci-runner:jammy-20250404-29Apr2025
image: ${MIRROR_DOCKER}/trini/u-boot-gitlab-ci-runner:jammy-20250714-25Jul2025
# We run some tests in different order, to catch some failures quicker.
stages:
@@ -106,10 +106,21 @@ stages:
# "${var:+"-k $var"}" expands to "" if $var is empty, "-k $var" if not
- export PATH=/opt/qemu/bin:/tmp/uboot-test-hooks/bin:${PATH};
export PYTHONPATH=/tmp/uboot-test-hooks/py/travis-ci;
python3 -m http.server 80 --directory "${UBOOT_TRAVIS_BUILD_DIR}" > /dev/null 2>&1 &
HTTP_PID=$!;
sleep 1;
if ps -p ${HTTP_PID} > /dev/null; then
export HTTP_PID;
else
unset HTTP_PID;
fi;
./test/py/test.py -ra --bd ${TEST_PY_BD} ${TEST_PY_ID} ${TEST_PY_EXTRA}
${TEST_PY_TEST_SPEC:+"-k ${TEST_PY_TEST_SPEC}"}
--build-dir "$UBOOT_TRAVIS_BUILD_DIR"
--junitxml=/tmp/${TEST_PY_BD}/results.xml
--junitxml=/tmp/${TEST_PY_BD}/results.xml;
if [[ -n "${HTTP_PID}" ]]; then
kill ${HTTP_PID};
fi
artifacts:
when: always
paths:
@@ -253,8 +264,8 @@ Check packing of Python tools:
sandbox test.py:
parallel:
matrix:
- HOST: "fast arm64"
- HOST: "fast amd64"
- HOST: "arm64"
- HOST: "amd64"
tags:
- ${HOST}
variables:
@@ -265,8 +276,8 @@ sandbox test.py:
sandbox with clang test.py:
parallel:
matrix:
- HOST: "fast arm64"
- HOST: "fast amd64"
- HOST: "arm64"
- HOST: "amd64"
tags:
- ${HOST}
variables:
@@ -277,8 +288,8 @@ sandbox with clang test.py:
sandbox64 test.py:
parallel:
matrix:
- HOST: "fast arm64"
- HOST: "fast amd64"
- HOST: "arm64"
- HOST: "amd64"
tags:
- ${HOST}
variables:
@@ -288,8 +299,8 @@ sandbox64 test.py:
sandbox64 with clang test.py:
parallel:
matrix:
- HOST: "fast arm64"
- HOST: "fast amd64"
- HOST: "arm64"
- HOST: "amd64"
tags:
- ${HOST}
variables:
@@ -300,8 +311,8 @@ sandbox64 with clang test.py:
sandbox64_lwip test.py:
parallel:
matrix:
- HOST: "fast arm64"
- HOST: "fast amd64"
- HOST: "arm64"
- HOST: "amd64"
tags:
- ${HOST}
variables:
@@ -508,12 +519,13 @@ r2dplus_tulip test.py:
TEST_PY_ID: "--id tulip_qemu"
<<: *buildman_and_testpy_dfn
sifive_unleashed_sdcard test.py:
variables:
TEST_PY_BD: "sifive_unleashed"
TEST_PY_TEST_SPEC: "not sleep"
TEST_PY_ID: "--id sdcard_qemu"
<<: *buildman_and_testpy_dfn
# This is broken upsteam: https://gitlab.com/qemu-project/qemu/-/issues/2945
#sifive_unleashed_sdcard test.py:
# variables:
# TEST_PY_BD: "sifive_unleashed"
# TEST_PY_TEST_SPEC: "not sleep"
# TEST_PY_ID: "--id sdcard_qemu"
# <<: *buildman_and_testpy_dfn
sifive_unleashed_spi-nor test.py:
variables:
@@ -594,8 +606,10 @@ coreboot test.py:
- export strategy="-s uboot -e off"
- export USE_LABGRID_SJG=1
# export verbose="-v"
- ${SRC}/test/py/test.py --role ${ROLE} --build-dir "${OUT}"
--capture=tee-sys -k "not bootstd ${TEST_PY_TEST_SPEC}" || ret=$?
- ${SRC}/test/py/test.py -ra --role ${ROLE} ${TEST_PY_EXTRA:-"--capture=tee-sys"}
--build-dir "${OUT}"
${TEST_PY_TEST_SPEC:+"-k ${TEST_PY_TEST_SPEC}"}
--junitxml=${OUT}/results.xml || ret=$?
- U_BOOT_BOARD_IDENTITY="${ROLE}" u-boot-test-release || true
- if [[ $ret -ne 0 ]]; then
exit $ret;
@@ -605,6 +619,9 @@ coreboot test.py:
paths:
- "build/${BOARD}/test-log.html"
- "build/${BOARD}/multiplexed_log.css"
- "build/${BOARD}/results.xml"
reports:
junit: "build/${BOARD}/results.xml"
expire_in: 1 week
rpi3:

View File

@@ -48,6 +48,11 @@ Greg Malysa <malysagreg@gmail.com> <greg.malysa@timesys.com>
Harini Katakam <harini.katakam@amd.com> <harini.katakam@xilinx.com>
Harsha <harsha.harsha@amd.com> <harsha.harsha@xilinx.com>
Heiko Stuebner <heiko.stuebner@cherry.de> <heiko.stuebner@theobroma-systems.com>
Heiko Schocher <hs@nabladev.com> <hs@denx.de>
Heiko Schocher <hs@nabladev.com> <hs@pollux.denx.de>
Heiko Schocher <hs@nabladev.com> <heiko.schocher@invitel.hu>
Heiko Schocher <hs@nabladev.com> <[hs@denx.de]>
Heiko Schocher <hs@nabladev.com> <hs@pollux.(none)>
Heinrich Schuchardt <xypron.glpk@gmx.de> <heinrich.schuchardt@canonical.com>
Heinrich Schuchardt <xypron.glpk@gmx.de> xypron.glpk@gmx.de <xypron.glpk@gmx.de>
Ibai Erkiaga <ibai.erkiaga-elorza@amd.com> <ibai.erkiaga-elorza@xilinx.com>
@@ -125,7 +130,7 @@ Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com> <siva.durga.pala
Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com> <sivadur@xilinx.com>
Srinivas Goud <srinivas.goud@amd.com> <srinivas.goud@xilinx.com>
Srinivas Neeli <srinivas.neeli@amd.com> <srinivas.neeli@xilinx.com>
Stefan Roese <sr@denx.de> <stroese>
Stefan Roese <stefan.roese@mailbox.org> <stroese>
Stefano Babic <sbabic@nabladev.com>
Stefano Stabellini <stefano.stabellini@amd.com> <stefano.stabellini@xilinx.com>
No generic patch CC mail please <noreply@example.com> <swarren@wwwdotorg.org>

1
COPYING Symbolic link
View File

@@ -0,0 +1 @@
Licenses/gpl-2.0.txt

20
Kconfig
View File

@@ -27,8 +27,22 @@ config DEPRECATED
code that relies on deprecated features that will be removed and
the conversion deadline has passed.
config COMPILE_TEST
bool "Compile also drivers which will not load"
help
Some drivers can be compiled on a different platform than they are
intended to be run on. Despite they cannot be loaded there (or even
when they load they cannot be used due to missing HW support),
developers still, opposing to distributors, might want to build such
drivers to compile-test them.
If you are a developer and want to build everything available, say Y
here. If you are a user/distributor, say N here to exclude useless
drivers to be distributed.
config WERROR
bool "Compile U-Boot with warnings as errors"
default COMPILE_TEST
help
A U-Boot build should not cause any compiler warnings, and this
enables the '-Werror' flag to enforce that rule.
@@ -309,7 +323,7 @@ config SYS_MALLOC_F_LEN
config SYS_MALLOC_LEN
hex "Define memory for Dynamic allocation"
default 0x4000000 if SANDBOX
default 0x2000000 if ARCH_ROCKCHIP || ARCH_OMAP2PLUS || ARCH_MESON
default 0x2000000 if ARCH_ROCKCHIP || ARCH_OMAP2PLUS || ARCH_MESON || ARCH_K3
default 0x200000 if ARCH_BMIPS || X86
default 0x4020000 if SUNXI_MINIMUM_DRAM_MB >= 256
default 0x220000 if SUNXI_MINIMUM_DRAM_MB >= 64
@@ -523,6 +537,7 @@ config BUILD_TARGET
config HAS_BOARD_SIZE_LIMIT
bool "Define a maximum size for the U-Boot image"
depends on !COMPILE_TEST
default y if RCAR_32 || RCAR_64
help
In some cases, we need to enforce a hard limit on how big the U-Boot
@@ -537,10 +552,11 @@ config BOARD_SIZE_LIMIT
Maximum size of the U-Boot image. When defined, the build system
checks that the actual size does not exceed it. This does not
include SPL nor TPL, on platforms that use that functionality, they
have a separate option to restict size.
have separate options to restrict size.
config SYS_CUSTOM_LDSCRIPT
bool "Use a custom location for the U-Boot linker script"
depends on !COMPILE_TEST
help
Normally when linking U-Boot we will look in the board directory,
the CPU directory and finally the "cpu" directory of the architecture

View File

@@ -152,12 +152,14 @@ ARM ALTERA SOCFPGA
M: Marek Vasut <marex@denx.de>
M: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
M: Tien Fong Chee <tien.fong.chee@altera.com>
M: Tingting Meng <tingting.meng@altera.com>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-socfpga.git
F: drivers/ddr/altera/
F: arch/arm/dts/socfpga_*
F: arch/arm/mach-socfpga/
F: configs/socfpga_agilex5_vab_defconfig
F: board/intel/agilex-socdk/
F: configs/socfpga_*
F: drivers/ddr/altera/
F: drivers/power/domain/altr-pmgr-agilex5.c
F: drivers/sysreset/sysreset_socfpga*
ARM AMLOGIC SOC SUPPORT
@@ -344,7 +346,6 @@ F: drivers/spi/gxp_spi.c
ARM IPQ40XX
M: Robert Marko <robert.marko@sartura.hr>
M: Luka Perkov <luka.perkov@sartura.hr>
S: Maintained
F: arch/arm/mach-ipq40xx/
F: include/dt-bindings/clock/qcom,gcc-ipq4019.h
@@ -361,7 +362,7 @@ S: Maintained
F: drivers/misc/ls2_sfp.c
ARM MARVELL KIRKWOOD ARMADA-XP ARMADA-38X ARMADA-37XX ARMADA-7K/8K
M: Stefan Roese <sr@denx.de>
M: Stefan Roese <stefan.roese@mailbox.org>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-marvell.git
F: arch/arm/mach-kirkwood/
@@ -384,7 +385,7 @@ F: drivers/watchdog/orion_wdt.c
F: include/configs/mv-common.h
ARM MARVELL PCIE CONTROLLER DRIVERS
M: Stefan Roese <sr@denx.de>
M: Stefan Roese <stefan.roese@mailbox.org>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-marvell.git
F: drivers/pci/pci-aardvark.c
@@ -400,7 +401,7 @@ F: include/configs/pxa1908.h
ARM MARVELL SERIAL DRIVERS
M: Pali Rohár <pali@kernel.org>
M: Stefan Roese <sr@denx.de>
M: Stefan Roese <stefan.roese@mailbox.org>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-marvell.git
F: drivers/serial/serial_mvebu_a3700.c
@@ -468,7 +469,6 @@ F: drivers/memory/atmel-ebi.c
F: drivers/misc/microchip_flexcom.c
F: drivers/timer/atmel_tcb_timer.c
F: include/dt-bindings/clk/at91.h
F: include/dt-bindings/clock/at91.h
F: include/dt-bindings/dma/at91.h
F: include/dt-bindings/mfd/at91-usart.h
F: include/dt-bindings/mfd/atmel-flexcom.h
@@ -603,6 +603,7 @@ ARM SAMSUNG EXYNOS850 SOC
M: Sam Protsenko <semen.protsenko@linaro.org>
S: Maintained
F: drivers/clk/exynos/clk-exynos850.c
F: drivers/phy/phy-exynos-usbdrd.c
F: drivers/pinctrl/exynos/pinctrl-exynos850.c
ARM SAMSUNG SOC DRIVERS
@@ -654,7 +655,7 @@ F: include/dt-bindings/pinctrl/adi-adsp.h
F: include/env/adi/
ARM SNAPDRAGON
M: Caleb Connolly <caleb.connolly@linaro.org>
M: Casey Connolly <casey.connolly@linaro.org>
M: Neil Armstrong <neil.armstrong@linaro.org>
R: Sumit Garg <sumit.garg@kernel.org>
L: u-boot-qcom@groups.io
@@ -718,7 +719,7 @@ F: drivers/power/regulator/stm32-vrefbuf.c
F: drivers/power/regulator/stpmic1.c
F: drivers/ram/stm32mp1/
F: drivers/remoteproc/stm32_copro.c
F: drivers/reset/stm32-reset.c
F: drivers/reset/stm32/
F: drivers/rng/optee_rng.c
F: drivers/rng/stm32_rng.c
F: drivers/rtc/stm32_rtc.c
@@ -1022,7 +1023,7 @@ S: Maintained
F: cmd/cat.c
CFI FLASH
M: Stefan Roese <sr@denx.de>
M: Stefan Roese <stefan.roese@mailbox.org>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-cfi-flash.git
F: drivers/mtd/cfi_flash.c
@@ -1053,7 +1054,7 @@ F: cmd/cpu.c
F: doc/usage/cpu.rst
CYCLIC
M: Stefan Roese <sr@denx.de>
M: Stefan Roese <stefan.roese@mailbox.org>
S: Maintained
F: cmd/cyclic.c
F: common/cyclic.c
@@ -1073,6 +1074,7 @@ T: git https://source.denx.de/u-boot/custodians/u-boot-dfu.git
F: cmd/dfu.c
F: cmd/usb_*.c
F: common/dfu.c
F: common/spl/spl_dfu.c
F: common/update.c
F: doc/api/dfu.rst
F: doc/usage/dfu.rst
@@ -1092,7 +1094,7 @@ F: drivers/core/
F: include/dm/
F: test/dm/
EFI APP
EFI CLIENT
M: Simon Glass <sjg@chromium.org>
M: Heinrich Schuchardt <xypron.glpk@gmx.de>
S: Maintained
@@ -1102,11 +1104,11 @@ F: configs/efi-x86_app*
F: doc/develop/uefi/u-boot_on_efi.rst
F: drivers/block/efi-media-uclass.c
F: drivers/block/sb_efi_media.c
F: lib/efi/efi_app.c
F: lib/efi_client/
F: scripts/build-efi.sh
F: test/dm/efi_media.c
EFI PAYLOAD
EFI LOADER
M: Heinrich Schuchardt <xypron.glpk@gmx.de>
M: Ilias Apalodimas <ilias.apalodimas@linaro.org>
S: Maintained
@@ -1221,7 +1223,7 @@ S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-freebsd.git
FREESCALE QORIQ
M: Priyanka Jain <priyanka.jain@nxp.com>
M: Peng Fan <peng.fan@nxp.com>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq.git
F: drivers/watchdog/sp805_wdt.c
@@ -1242,15 +1244,22 @@ F: drivers/misc/gsc.c
F: include/gsc.h
I2C
M: Heiko Schocher <hs@denx.de>
M: Heiko Schocher <hs@nabladev.com>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-i2c.git
F: drivers/i2c/
I3C
M: Dinesh <dinesh.maniyam@altera.com>
S: Maintained
T: git https://source.denx.de/u-boot/u-boot.git
F: cmd/i3c.c
F: drivers/i3c/
KWBIMAGE / KWBOOT TOOLS
M: Pali Rohár <pali@kernel.org>
M: Marek Behún <kabel@kernel.org>
M: Stefan Roese <sr@denx.de>
M: Stefan Roese <stefan.roese@mailbox.org>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-marvell.git
F: doc/README.kwbimage
@@ -1282,6 +1291,11 @@ T: git git://github.com/ARM-software/u-boot.git
F: drivers/video/mali_dp.c
F: drivers/i2c/i2c-versatile.c
MBEDTLS
M: Raymond Mao <raymond.mao@linaro.org>
S: Maintained
F: lib/mbedtls/
MEMBUF
M: Simon Glass <sjg@chromium.org>
S: Maintained
@@ -1396,10 +1410,12 @@ M: Jaehoon Chung <jh80.chung@samsung.com>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-mmc.git
F: drivers/mmc/
N: mmc
NETWORK
M: Joe Hershberger <joe.hershberger@ni.com>
M: Ramon Fried <rfried.dev@gmail.com>
M: Jerome Forissier <jerome.forissier@linaro.org>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-net.git
F: drivers/net/
@@ -1409,6 +1425,8 @@ F: net/
NETWORK (LWIP)
M: Jerome Forissier <jerome.forissier@linaro.org>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-net.git
F: cmd/lwip/
F: cmd/net-lwip.c
F: configs/qemu_arm64_lwip_defconfig
F: drivers/net/sandbox-lwip.c
@@ -1488,7 +1506,7 @@ F: drivers/pci_endpoint/
F: include/pci_ep.h
PCI MPC85xx
M: Heiko Schocher <hs@denx.de>
M: Heiko Schocher <hs@nabladev.com>
S: Maintained
F: drivers/pci/pci_mpc85xx.c
@@ -1500,6 +1518,7 @@ F: test/cmd/pci_mps.c
POWER
M: Jaehoon Chung <jh80.chung@samsung.com>
M: Peng Fan <peng.fan@nxp.com>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-pmic.git
F: drivers/power/
@@ -1569,6 +1588,15 @@ F: drivers/clk/clk_k210.c
F: drivers/pinctrl/pinctrl-k210.c
F: include/k210/
RISC-V T-HEAD TH1520
M: Yao Zi <ziyao@disroot.org>
S: Maintained
F: arch/riscv/cpu/th1520/
F: drivers/clk/thead/clk-th1520-ap.c
F: drivers/net/dwmac_thead.c
F: drivers/pinctrl/pinctrl-th1520.c
F: drivers/ram/thead/th1520_ddr.c
RNG
M: Sughosh Ganu <sughosh.ganu@linaro.org>
R: Heinrich Schuchardt <xypron.glpk@gmx.de>
@@ -1628,6 +1656,13 @@ F: drivers/gpio/sl28cpld-gpio.c
F: drivers/misc/sl28cpld.c
F: drivers/watchdog/sl28cpld-wdt.c
SLRE
M: Rasmus Villemoes <ravi@prevas.dk>
S: Maintained
F: include/slre.h
F: lib/slre.c
F: test/lib/slre.c
SMCCC TRNG
M: Etienne Carriere <etienne.carriere@linaro.org>
S: Maintained
@@ -1769,13 +1804,13 @@ F: lib/optee
UBI
M: Kyungmin Park <kmpark@infradead.org>
M: Heiko Schocher <hs@denx.de>
M: Heiko Schocher <hs@nabladev.com>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-ubi.git
F: drivers/mtd/ubi/
UFETCH
M: Caleb Connolly <caleb.connolly@linaro.org>
M: Casey Connolly <casey.connolly@linaro.org>
S: Maintained
F: cmd/ufetch.c
@@ -1847,7 +1882,7 @@ F: common/spl_reloc.c
F: include/vbe.h
VIDEO
M: Anatolij Gustschin <agust@denx.de>
M: Anatolij Gustschin <ag.dev.uboot@gmail.com>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-video.git
F: drivers/video/
@@ -1866,7 +1901,7 @@ F: test/dm/virtio.c
F: doc/develop/driver-model/virtio.rst
WATCHDOG
M: Stefan Roese <sr@denx.de>
M: Stefan Roese <stefan.roese@mailbox.org>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-watchdog.git
F: cmd/wdt.c

958
Makefile

File diff suppressed because it is too large Load Diff

22
README
View File

@@ -379,15 +379,6 @@ The following options need to be configured:
CONFIG_SH_ETHER
Support for Renesas on-chip Ethernet controller
CFG_SH_ETHER_USE_PORT
Define the number of ports to be used
CFG_SH_ETHER_PHY_ADDR
Define the ETH PHY's address
CFG_SH_ETHER_CACHE_WRITEBACK
If this option is set, the driver enables cache flush.
- TPM Support:
CONFIG_TPM
Support TPM devices.
@@ -950,15 +941,6 @@ The following options need to be configured:
the environment like the "source" command or the
boot command first.
CONFIG_DELAY_ENVIRONMENT
Normally the environment is loaded when the board is
initialised so that it is available to U-Boot. This inhibits
that so that the environment is not available until
explicitly loaded later by U-Boot code. With CONFIG_OF_CONTROL
this is instead controlled by the value of
/config/load-environment.
- Automatic software updates via TFTP server
CONFIG_UPDATE_TFTP
CONFIG_UPDATE_TFTP_CNT_MAX
@@ -1412,10 +1394,6 @@ Low Level (hardware related) configuration options:
VPL. Code that needs phase-specific behaviour can check this,
or (where possible) use xpl_phase() instead.
Note that CONFIG_XPL_BUILD *is* always defined when either
of CONFIG_TPL_BUILD / CONFIG_VPL_BUILD is defined. This can be
counter-intuitive and should perhaps be changed.
- CONFIG_TPL_BUILD
Set when the currently running compilation is for an artifact
that will end up in the TPL build (as opposed to SPL, VPL or

View File

@@ -63,6 +63,13 @@ config SYS_CACHELINE_SIZE
default 64 if RISCV
default 32 if MIPS
config SYS_DTC_PAD_BYTES
int "Size in bytes to pad device tree blob"
default 32768 if X86 && EFI_APP
default 4096 if ARC || ARM64 || M68K || MICROBLAZE || NIOS2 \
|| RISCV || SANDBOX || X86
default 0
config LINKER_LIST_ALIGN
int
default 32 if SANDBOX
@@ -213,6 +220,7 @@ config SANDBOX
imply BITREVERSE
select BLOBLIST
imply LTO
imply CMD_BOOTEFI_SELFTEST
imply CMD_DM
imply CMD_EXCEPTION
imply CMD_GETTIME

View File

@@ -84,6 +84,28 @@ config SYS_FSL_SFP_VER_3_4
endchoice
config FSL_SEC_MON
bool
help
Freescale Security Monitor block is responsible for monitoring
system states.
Security Monitor can be transitioned on any security failures,
like software violations or hardware security violations.
choice
prompt "Security monitor interaction endianess"
depends on FSL_SEC_MON
default SYS_FSL_SEC_MON_BE if PPC
default SYS_FSL_SEC_MON_LE
config SYS_FSL_SEC_MON_LE
bool "Security monitor interactions are little endian"
config SYS_FSL_SEC_MON_BE
bool "Security monitor interactions are big endian"
endchoice
config SPL_UBOOT_KEY_HASH
string "Non-SRK key hash for U-Boot public/private key pair"
depends on SPL

View File

@@ -11,4 +11,4 @@ dtb-$(CONFIG_TARGET_IOT_DEVKIT) += iot_devkit.dtb
include $(srctree)/scripts/Makefile.dts
# Add any required device tree compiler flags here
DTC_FLAGS += -R 4 -p 0x1000
DTC_FLAGS += -R 4

View File

@@ -20,6 +20,6 @@ struct arch_global_data {
#include <asm-generic/global_data.h>
#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r25")
#define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm ("r25")
#endif /* __ASM_ARC_GLOBAL_DATA_H */

View File

@@ -30,7 +30,7 @@ config COUNTER_FREQUENCY
ROCKCHIP_RK3288 || ROCKCHIP_RK322X || ROCKCHIP_RK3036
default 25000000 if ARCH_LX2160A || ARCH_LX2162A || ARCH_LS1088A
default 100000000 if ARCH_ZYNQMP
default 200000000 if ARCH_SOCFPGA && ARM64 && TARGET_SOCFPGA_AGILEX5
default 200000000 if TARGET_SOCFPGA_AGILEX5 || TARGET_SOCFPGA_AGILEX7M
default 0
help
For platforms with ARMv8-A and ARMv7-A which features a system
@@ -108,6 +108,18 @@ config LNX_KRNL_IMG_TEXT_OFFSET_BASE
The value subtracted from CONFIG_TEXT_BASE to calculate the
TEXT_OFFSET value written to the Linux kernel image header.
config KVM_VIRT_INS
bool "Emit virtualizable instructions"
help
Instructions in the ARM ISA that have multiple output registers,
can't be used if the instruction leads to an exception to the hypervisor.
These instructions cannot be emulated by KVM because they do not produce
syndrome information data that KVM can use to infer the destination
register, the faulting address, whether it was a load or store,
if it's a 32 or 64 bit general-purpose register amongst other things.
Use this to produce virtualizable instructions if you plan to run U-Boot
with KVM.
config NVIC
bool
@@ -810,6 +822,7 @@ config ARCH_KEYSTONE
imply CMD_SAVES
imply DM_I2C
imply FIT
imply OF_BOARD_SETUP_EXTENDED
imply SOC_TI
imply TI_KEYSTONE_SERDES
@@ -820,7 +833,12 @@ config ARCH_K3
select FIT
select REGEX
select FIT_SIGNATURE if ARM64
select DMA_ADDR_T_64BIT
select LTO
imply TI_SECURE_DEVICE
imply DM_RNG if ARM64
imply TEE if ARM64
imply OPTEE if ARM64
config ARCH_OMAP2PLUS
bool "TI OMAP2+"
@@ -892,6 +910,7 @@ config ARCH_IMX8
config ARCH_IMX8M
bool "NXP i.MX8M platform"
select ARCH_MISC_INIT if FSL_CAAM
select ARM64
select GPIO_EXTRA_HEADER
select MACH_IMX
@@ -941,6 +960,7 @@ config ARCH_IMXRT
config ARCH_MX23
bool "NXP i.MX23 family"
select ARCH_MISC_INIT
select CPU_ARM926EJS
select GPIO_EXTRA_HEADER
select MACH_IMX
@@ -948,17 +968,12 @@ config ARCH_MX23
config ARCH_MX28
bool "NXP i.MX28 family"
select ARCH_MISC_INIT
select CPU_ARM926EJS
select GPIO_EXTRA_HEADER
select MACH_IMX
select SUPPORT_SPL
config ARCH_MX31
bool "NXP i.MX31 family"
select CPU_ARM1136
select GPIO_EXTRA_HEADER
select MACH_IMX
config ARCH_MX7ULP
bool "NXP MX7ULP"
select BOARD_POSTCLK_INIT
@@ -1067,7 +1082,7 @@ config ARCH_OWL
select CLK
select CLK_OWL
select OF_CONTROL
select SYS_RELOC_GD_ENV_ADDR
select ENV_RELOC_GD_ENV_ADDR
imply CMD_DM
config ARCH_QEMU
@@ -1095,6 +1110,7 @@ config ARCH_QEMU
config ARCH_RENESAS
bool "Renesas ARM SoCs"
select ARCH_MISC_INIT if DISPLAY_CPUINFO && !(RZA1 || RZN1)
select DM
select DM_SERIAL
select GPIO_EXTRA_HEADER
@@ -1104,7 +1120,6 @@ config ARCH_RENESAS
imply FAT_WRITE
imply OF_UPSTREAM
imply SYS_THUMB_BUILD
imply ARCH_MISC_INIT if DISPLAY_CPUINFO
config ARCH_SNAPDRAGON
bool "Qualcomm Snapdragon SoCs"
@@ -1125,6 +1140,7 @@ config ARCH_SNAPDRAGON
select LINUX_KERNEL_IMAGE_HEADER if !ENABLE_ARM_SOC_BOOT0_HOOK
select SYSRESET
select SYSRESET_PSCI
select ANDROID_BOOT_IMAGE_IGNORE_BLOB_ADDR
imply OF_UPSTREAM
imply CMD_DM
imply DM_USB_GADGET
@@ -1158,8 +1174,9 @@ config ARCH_SOCFPGA
select SYSRESET
select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
select SYSRESET_SOCFPGA_SOC64 if !TARGET_SOCFPGA_AGILEX5 && \
TARGET_SOCFPGA_SOC64
TARGET_SOCFPGA_SOC64
select SYSRESET_PSCI if TARGET_SOCFPGA_AGILEX5
select USE_BOOTFILE if SPL_ATF && TARGET_SOCFPGA_SOC64
imply CMD_DM
imply CMD_MTDPARTS
imply CRC32_VERIFY
@@ -1207,7 +1224,7 @@ config ARCH_SUNXI
select USB_STORAGE if DISTRO_DEFAULTS && USB_HOST
select SPL_USE_TINY_PRINTF if SPL
select USE_PREBOOT
select SYS_RELOC_GD_ENV_ADDR
select ENV_RELOC_GD_ENV_ADDR
imply BOARD_LATE_INIT
imply CMD_DM
imply CMD_GPT
@@ -1532,7 +1549,6 @@ config TARGET_LX2160AQDS
config TARGET_LX2162AQDS
bool "Support lx2162aqds"
select ARCH_LX2162A
select ARCH_MISC_INIT
select ARM64
select ARMV8_MULTIENTRY
select ARCH_SUPPORT_TFABOOT
@@ -1945,7 +1961,6 @@ config TARGET_SL28
config TARGET_TEN64
bool "Support ten64"
select ARCH_LS1088A
select ARCH_MISC_INIT
select ARM64
select ARMV8_MULTIENTRY
select ARCH_SUPPORT_TFABOOT
@@ -1989,7 +2004,6 @@ config ARCH_SYNQUACER
bool "Socionext SynQuacer SoCs"
select ARM64
select DM
select GIC_V3
select PSCI_RESET
select SYSRESET
select SYSRESET_PSCI
@@ -2303,8 +2317,6 @@ source "arch/arm/mach-octeontx2/Kconfig"
source "arch/arm/cpu/armv7/ls102xa/Kconfig"
source "arch/arm/mach-imx/mx3/Kconfig"
source "arch/arm/mach-imx/mx5/Kconfig"
source "arch/arm/mach-imx/mx6/Kconfig"

View File

@@ -36,7 +36,8 @@ config ARMV7_SECURE_BASE
hex "Base address for secure mode memory"
depends on HAS_ARMV7_SECURE_BASE
default 0xfff00000 if TEGRA124
default 0x2ffc0000 if ARCH_STM32MP
default 0x2ffe0000 if STM32MP13X
default 0x2ffc0000 if STM32MP15X
default 0x2f000000 if ARCH_MX7ULP
default 0x10010000 if ARCH_LS1021A
default 0x00900000 if ARCH_MX7

View File

@@ -7,5 +7,4 @@ obj-y += clk-core.o
obj-y += clk-bcm281xx.o
obj-y += clk-sdio.o
obj-y += clk-bsc.o
obj-$(CONFIG_BCM_SF2_ETH) += clk-eth.o
obj-y += clk-usb-otg.o

View File

@@ -307,27 +307,6 @@ static struct ccu_clock kps_ccu_clk = {
.freq_tbl = slave_axi_freq_tbl,
};
#ifdef CONFIG_BCM_SF2_ETH
static struct ccu_clock esub_ccu_clk = {
.clk = {
.name = "esub_ccu_clk",
.ops = &ccu_clk_ops,
.ccu_clk_mgr_base = ESUB_CLK_BASE_ADDR,
},
.num_policy_masks = 1,
.policy_freq_offset = 0x00000008,
.freq_bit_shift = 8,
.policy_ctl_offset = 0x0000000c,
.policy0_mask_offset = 0x00000010,
.policy1_mask_offset = 0x00000014,
.policy2_mask_offset = 0x00000018,
.policy3_mask_offset = 0x0000001c,
.lvm_en_offset = 0x00000034,
.freq_id = 2,
.freq_tbl = esub_freq_tbl,
};
#endif
/*
* Bus clocks
*/
@@ -562,9 +541,6 @@ struct clk_lookup arch_clk_tbl[] = {
CLK_LK(bsc1_apb),
CLK_LK(bsc2_apb),
CLK_LK(bsc3_apb),
#ifdef CONFIG_BCM_SF2_ETH
CLK_LK(esub_ccu),
#endif
};
/* public array size */

View File

@@ -1,142 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Broadcom Corporation.
*/
#include <asm/io.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <asm/arch/sysmap.h>
#include <asm/kona-common/clk.h>
#include "clk-core.h"
#define WR_ACCESS_ADDR ESUB_CLK_BASE_ADDR
#define WR_ACCESS_PASSWORD 0xA5A500
#define PLLE_POST_RESETB_ADDR (ESUB_CLK_BASE_ADDR + 0x00000C00)
#define PLLE_RESETB_ADDR (ESUB_CLK_BASE_ADDR + 0x00000C58)
#define PLLE_RESETB_I_PLL_RESETB_PLLE_MASK 0x00010000
#define PLLE_POST_RESETB_I_POST_RESETB_PLLE_MASK 0x00000001
#define PLL_LOCK_ADDR (ESUB_CLK_BASE_ADDR + 0x00000C38)
#define PLL_LOCK_PLL_LOCK_PLLE_MASK 0x00000001
#define ESW_SYS_DIV_ADDR (ESUB_CLK_BASE_ADDR + 0x00000A04)
#define ESW_SYS_DIV_PLL_SELECT_MASK 0x00000300
#define ESW_SYS_DIV_DIV_MASK 0x0000001C
#define ESW_SYS_DIV_PLL_VAR_208M_CLK_SELECT 0x00000100
#define ESW_SYS_DIV_DIV_SELECT 0x4
#define ESW_SYS_DIV_TRIGGER_MASK 0x00000001
#define ESUB_AXI_DIV_DEBUG_ADDR (ESUB_CLK_BASE_ADDR + 0x00000E04)
#define ESUB_AXI_DIV_DEBUG_PLL_SELECT_MASK 0x0000001C
#define ESUB_AXI_DIV_DEBUG_PLL_SELECT_OVERRIDE_MASK 0x00000040
#define ESUB_AXI_DIV_DEBUG_PLL_VAR_208M_CLK_SELECT 0x0
#define ESUB_AXI_DIV_DEBUG_TRIGGER_MASK 0x00000001
#define PLL_MAX_RETRY 100
/* Enable appropriate clocks for Ethernet */
int clk_eth_enable(void)
{
int rc = -1;
int retry_count = 0;
rc = clk_get_and_enable("esub_ccu_clk");
/* Enable Access to CCU registers */
writel((1 | WR_ACCESS_PASSWORD), WR_ACCESS_ADDR);
writel(readl(PLLE_POST_RESETB_ADDR) &
~PLLE_POST_RESETB_I_POST_RESETB_PLLE_MASK,
PLLE_POST_RESETB_ADDR);
/* Take PLL out of reset and put into normal mode */
writel(readl(PLLE_RESETB_ADDR) | PLLE_RESETB_I_PLL_RESETB_PLLE_MASK,
PLLE_RESETB_ADDR);
/* Wait for PLL lock */
rc = -1;
while (retry_count < PLL_MAX_RETRY) {
udelay(100);
if (readl(PLL_LOCK_ADDR) & PLL_LOCK_PLL_LOCK_PLLE_MASK) {
rc = 0;
break;
}
retry_count++;
}
if (rc == -1) {
printf("%s: ETH-PLL lock timeout, Ethernet is not enabled!\n",
__func__);
return -1;
}
writel(readl(PLLE_POST_RESETB_ADDR) |
PLLE_POST_RESETB_I_POST_RESETB_PLLE_MASK,
PLLE_POST_RESETB_ADDR);
/* Switch esw_sys_clk to use 104MHz(208MHz/2) clock */
writel((readl(ESW_SYS_DIV_ADDR) &
~(ESW_SYS_DIV_PLL_SELECT_MASK | ESW_SYS_DIV_DIV_MASK)) |
ESW_SYS_DIV_PLL_VAR_208M_CLK_SELECT | ESW_SYS_DIV_DIV_SELECT,
ESW_SYS_DIV_ADDR);
writel(readl(ESW_SYS_DIV_ADDR) | ESW_SYS_DIV_TRIGGER_MASK,
ESW_SYS_DIV_ADDR);
/* Wait for trigger complete */
rc = -1;
retry_count = 0;
while (retry_count < PLL_MAX_RETRY) {
udelay(100);
if (!(readl(ESW_SYS_DIV_ADDR) & ESW_SYS_DIV_TRIGGER_MASK)) {
rc = 0;
break;
}
retry_count++;
}
if (rc == -1) {
printf("%s: SYS CLK Trigger timeout, Ethernet is not enabled!\n",
__func__);
return -1;
}
/* switch Esub AXI clock to 208MHz */
writel((readl(ESUB_AXI_DIV_DEBUG_ADDR) &
~(ESUB_AXI_DIV_DEBUG_PLL_SELECT_MASK |
ESUB_AXI_DIV_DEBUG_PLL_SELECT_OVERRIDE_MASK |
ESUB_AXI_DIV_DEBUG_TRIGGER_MASK)) |
ESUB_AXI_DIV_DEBUG_PLL_VAR_208M_CLK_SELECT |
ESUB_AXI_DIV_DEBUG_PLL_SELECT_OVERRIDE_MASK,
ESUB_AXI_DIV_DEBUG_ADDR);
writel(readl(ESUB_AXI_DIV_DEBUG_ADDR) |
ESUB_AXI_DIV_DEBUG_TRIGGER_MASK,
ESUB_AXI_DIV_DEBUG_ADDR);
/* Wait for trigger complete */
rc = -1;
retry_count = 0;
while (retry_count < PLL_MAX_RETRY) {
udelay(100);
if (!(readl(ESUB_AXI_DIV_DEBUG_ADDR) &
ESUB_AXI_DIV_DEBUG_TRIGGER_MASK)) {
rc = 0;
break;
}
retry_count++;
}
if (rc == -1) {
printf("%s: AXI CLK Trigger timeout, Ethernet is not enabled!\n",
__func__);
return -1;
}
/* Disable Access to CCU registers */
writel(WR_ACCESS_PASSWORD, WR_ACCESS_ADDR);
return rc;
}

View File

@@ -1,5 +1,6 @@
config ARCH_LS1021A
bool
select ARCH_MISC_INIT if FSL_CAAM
select FSL_DEVICE_DISABLE
select FSL_IFC if !QSPI_BOOT && !SD_BOOT_QSPI
select LS102XA_STREAM_ID

View File

@@ -4,13 +4,19 @@
* Kamil Lulko, <kamil.lulko@gmail.com>
*/
#include <linux/linkage.h>
#include <asm/assembler.h>
.globl reset
.type reset, %function
reset:
W(b) _main
/*
* Startup code (reset vector)
*/
ENTRY(reset)
W(b) _main @ Jump to _main (C runtime crt0.S)
ENDPROC(reset)
.globl c_runtime_cpu_setup
c_runtime_cpu_setup:
mov pc, lr
/*
* Setup CPU for C runtime
*/
ENTRY(c_runtime_cpu_setup)
mov pc, lr @ Jump back to caller
ENDPROC(c_runtime_cpu_setup)

View File

@@ -41,10 +41,11 @@ ENTRY(return_to_fel)
str w2, [x1]
ldr w0, =0xfa50392f // CPU hotplug magic
#ifdef CONFIG_MACH_SUN50I_H616
#if defined(CONFIG_MACH_SUN50I_H616) || defined(CONFIG_MACH_SUN50I_A133) || \
defined(CONFIG_MACH_SUN55I_A523)
ldr w2, =(SUNXI_R_CPUCFG_BASE + 0x1c0)
str w0, [x2], #0x4
#elif CONFIG_MACH_SUN50I_H6
#elif defined(CONFIG_MACH_SUN50I_H6)
ldr w2, =(SUNXI_RTC_BASE + 0x1b8) // BOOT_CPU_HP_FLAG_REG
str w0, [x2], #0x4
#else

View File

@@ -77,11 +77,11 @@ config ARCH_LS1043A
select SYS_FSL_DDR_BE
select SYS_FSL_DDR_VER_50
select SYS_FSL_ERRATUM_A008850 if !TFABOOT
select SYS_FSL_ERRATUM_A008997
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A008997 if USB
select SYS_FSL_ERRATUM_A009008 if USB
select SYS_FSL_ERRATUM_A009660 if !TFABOOT
select SYS_FSL_ERRATUM_A009663 if !TFABOOT
select SYS_FSL_ERRATUM_A009798
select SYS_FSL_ERRATUM_A009798 if USB
select SYS_FSL_ERRATUM_A009942 if !TFABOOT
select SYS_FSL_ERRATUM_A010315 if PCIE_LAYERSCAPE
select SYS_FSL_ERRATUM_A010539
@@ -328,6 +328,7 @@ config ARCH_LX2160A
config FSL_LSCH2
bool
select ARCH_MISC_INIT if FSL_CAAM
select SKIP_LOWLEVEL_INIT
select SYS_FSL_CCSR_GUR_BE
select SYS_FSL_CCSR_SCFG_BE

View File

@@ -802,7 +802,7 @@ enum boot_src get_boot_src(void)
int mmc_get_env_dev(void)
{
enum boot_src src = get_boot_src();
int dev = CONFIG_SYS_MMC_ENV_DEV;
int dev = CONFIG_ENV_MMC_DEVICE_INDEX;
switch (src) {
case BOOT_SOURCE_SD_MMC:

View File

@@ -7,6 +7,7 @@
#include <config.h>
#include <clock_legacy.h>
#include <efi_loader.h>
#include <env.h>
#include <log.h>
#include <asm/cache.h>
#include <linux/libfdt.h>

View File

@@ -11,15 +11,15 @@ char __data_save_end[0] __section(".__data_save_end");
u32 cold_reboot_flag = 1;
u32 __weak reset_flag(void)
u32 __weak reset_flag(u32 flag)
{
return 1;
return flag;
}
void spl_save_restore_data(void)
{
u32 data_size = __data_save_end - __data_save_start;
cold_reboot_flag = reset_flag();
cold_reboot_flag = reset_flag(cold_reboot_flag);
if (cold_reboot_flag == 1) {
/* Save data section to data_save section */

View File

@@ -134,7 +134,7 @@ int sysinfo_get_cache_info(u8 level, struct cache_info *cinfo)
/* Select cache level */
csselr_el1 = (level << 1);
asm volatile("msr csselr_el1, %0" : : "r" (csselr_el1));
asm volatile("msr csselr_el1, %0" : : "r" ((u64)csselr_el1));
/* Read CCSIDR_EL1 */
asm volatile("mrs %0, ccsidr_el1" : "=r" (creg.data));

View File

@@ -53,13 +53,14 @@ SECTIONS
__rel_dyn_end = .;
}
. = ALIGN(8);
_image_binary_end = .;
_end = .;
.bss __rel_dyn_start (OVERLAY) : {
__bss_start = .;
*(.bss*)
. = ALIGN(4);
. = ALIGN(8);
__bss_end = .;
}
__bss_size = __bss_end - __bss_start;

View File

@@ -153,14 +153,14 @@ SECTIONS
__efi_runtime_rel_stop = .;
}
. = ALIGN(4);
. = ALIGN(8);
__image_copy_end = .;
/*
* if CONFIG_USE_ARCH_MEMSET is not selected __bss_end - __bss_start
* needs to be a multiple of 4 and we overlay .bss with .rel.dyn
* needs to be a multiple of 8 and we overlay .bss with .rel.dyn
*/
.rel.dyn ALIGN(4) : {
.rel.dyn ALIGN(8) : {
__rel_dyn_start = .;
*(.rel*)
__rel_dyn_end = .;

View File

@@ -92,6 +92,8 @@ dtb-$(CONFIG_ARCH_TEGRA) += \
tegra20-motorola-olympus.dtb \
tegra20-paz00.dtb \
tegra20-plutux.dtb \
tegra20-samsung-bose.dtb \
tegra20-samsung-n1.dtb \
tegra20-seaboard.dtb \
tegra20-tec.dtb \
tegra20-trimslice.dtb \
@@ -117,10 +119,13 @@ dtb-$(CONFIG_ARCH_TEGRA) += \
tegra30-lg-p895.dtb \
tegra30-microsoft-surface-rt.dtb \
tegra30-ouya.dtb \
tegra30-pegatron-chagall.dtb \
tegra30-tec-ng.dtb \
tegra30-wexler-qc750.dtb \
tegra114-asus-tf701t.dtb \
tegra114-dalmore.dtb \
tegra114-microsoft-surface-2-0b.dtb \
tegra114-microsoft-surface-2-13.dtb \
tegra114-nvidia-tegratab.dtb \
tegra124-apalis.dtb \
tegra124-jetson-tk1.dtb \
@@ -445,7 +450,6 @@ dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb \
dtb-$(CONFIG_TARGET_THUNDERX_88XX) += thunderx-88xx.dtb
dtb-$(CONFIG_ARCH_SOCFPGA) += \
socfpga_agilex_socdk.dtb \
socfpga_agilex5_socdk.dtb \
socfpga_arria5_secu1.dtb \
socfpga_arria5_socdk.dtb \
@@ -646,11 +650,6 @@ dtb-$(CONFIG_MACH_SUN8I_R40) += \
sun8i-r40-oka40i-c.dtb \
sun8i-t3-cqa3t-bv3.dtb \
sun8i-v40-bananapi-m2-berry.dtb
dtb-$(CONFIG_MACH_SUN8I_V3S) += \
sun8i-s3-elimo-initium.dtb \
sun8i-s3-pinecube.dtb \
sun8i-v3-sl631-imx179.dtb \
sun8i-v3s-licheepi-zero.dtb
dtb-$(CONFIG_MACH_SUN8I_R528) += \
sun8i-t113s-mangopi-mq-r-t113.dtb
dtb-$(CONFIG_MACH_SUN50I_H5) += \
@@ -760,7 +759,6 @@ dtb-y += \
imx6dl-riotboard.dtb \
imx6dl-sabreauto.dtb \
imx6dl-sabresd.dtb \
imx6dl-sielaff.dtb \
imx6dl-wandboard-revd1.dtb
endif
@@ -918,12 +916,14 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mq-librem5-r4.dtb
dtb-$(CONFIG_ARCH_IMX9) += \
imx93-11x11-frdm.dtb \
imx93-var-som-symphony.dtb
dtb-$(CONFIG_ARCH_IMXRT) += imxrt1020-evk.dtb \
imxrt1170-evk.dtb \
dtb-$(CONFIG_RZA1) += \
r7s72100-genmai.dtb \
r7s72100-gr-peach.dtb
dtb-$(CONFIG_TARGET_AT91SAM9261EK) += at91sam9261ek.dtb
@@ -1111,7 +1111,9 @@ dtb-$(CONFIG_SOC_K3_AM62A7) += \
k3-am62a7-r5-sk.dtb \
k3-am62a7-r5-phycore-som-2gb.dtb
dtb-$(CONFIG_SOC_K3_AM62P5) += k3-am62p5-r5-sk.dtb
dtb-$(CONFIG_SOC_K3_AM62P5) += k3-am62p5-r5-sk.dtb \
k3-am62p5-verdin-r5.dtb \
k3-am62p5-verdin-wifi-dev.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt7622-rfb.dtb \

View File

@@ -7,6 +7,7 @@
#include "am33xx.dtsi"
#include "am335x-bone-common.dtsi"
#include "am335x-bonegreen-common.dtsi"
#include <dt-bindings/net/ti-dp83867.h>
/ {
model = "TI AM335x BeagleBone Green Eco";
@@ -25,6 +26,24 @@
interrupt-names = "mc";
};
&cpsw_emac0 {
phy-mode = "rgmii-id";
phy-handle = <&dp83867_0>;
};
&davinci_mdio {
/delete-node/ ethernet-phy@0;
dp83867_0: ethernet-phy@0 {
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
ti,min-output-impedance;
ti,dp83867-rxctrl-strap-quirk;
};
};
&baseboard_eeprom {
/delete-property/ vcc-supply;
};

View File

@@ -27,10 +27,6 @@
reg = <0x80000000 0x10000000>; /* 256 MB */
};
chosen {
stdout-path = &uart0;
};
vbat: fixedregulator0 {
compatible = "regulator-fixed";
regulator-name = "vbat";

View File

@@ -15,6 +15,6 @@
* because SBL de-initialises them. Indicate that the UART pins should be configured
* during all boot stages.
*/
&blsp_uart2_default {
&blsp_uart2_console_default {
bootph-all;
};

View File

@@ -463,7 +463,7 @@
drive-strength = <16>;
};
&blsp_uart1_default {
&blsp_uart1_console_default {
bootph-all;
};

View File

@@ -794,7 +794,7 @@
uart11: serial@1e790500 {
compatible = "ns16550a";
reg = <0x1e790400 0x20>;
reg = <0x1e790500 0x20>;
reg-shift = <2>;
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scu ASPEED_CLK_GATE_UART11CLK>;

View File

@@ -95,3 +95,7 @@
&slow_xtal {
bootph-all;
};
&watchdog {
timeout-sec = <16>;
};

View File

@@ -336,3 +336,7 @@
&usb2 {
status = "okay";
};
&watchdog {
status = "okay";
};

View File

@@ -0,0 +1,95 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* at91-sam9x75_curiosity-u-boot.dtsi - Device Tree file for SAM9X75
* CURIOSITY board.
*
* Copyright (C) 2025 Microchip Technology Inc. and its subsidiaries
*
* Author: Manikandan Muralidharan <manikandan.m@microchip.com>
*/
/ {
cpus {
cpu@0 {
clocks = <&pmc PMC_TYPE_CORE 25>, <&pmc PMC_TYPE_CORE 17>, <&main_xtal>;
clock-names = "cpu", "master", "xtal";
};
};
clocks {
slow_rc_osc: slow_rc_osc {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <18500>;
};
};
ahb {
bootph-all;
apb {
bootph-all;
pinctrl {
bootph-all;
};
};
};
chosen {
bootph-all;
};
};
&clk32k {
bootph-all;
clocks = <&slow_rc_osc>, <&slow_xtal>;
};
&dbgu {
bootph-all;
};
&gmac {
compatible = "microchip,sam9x7-gem", "cdns,sama7g5-gem";
};
&main_xtal {
bootph-all;
};
&pinctrl_dbgu_default {
bootph-all;
};
&pinctrl_sdmmc0_default {
bootph-all;
};
&pioA {
bootph-all;
};
&pioB {
bootph-all;
};
&pit64b0 {
bootph-all;
};
&pmc {
bootph-all;
};
&sdmmc0 {
bootph-all;
};
&slow_xtal {
bootph-all;
};
&slow_rc_osc {
bootph-all;
};

View File

@@ -0,0 +1,80 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* at91-sama7d65_curiosity-u-boot.dtsi - Device Tree Include file for
* SAMA7D65 CURIOSITY.
*
* Copyright (c) 2023 Microchip Technology Inc. and its subsidiaries
*
* Author: Ryan Wanner <ryan.wanner@microchip.com>
*/
/{
aliases {
serial0 = &uart6;
};
chosen {
bootph-all;
};
clocks {
slow_rc_osc: slow_rc_osc {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32000>;
};
};
cpus {
cpu@0 {
clocks = <&pmc PMC_TYPE_CORE 8>, <&pmc PMC_TYPE_CORE 26>, <&main_xtal>;
clock-names = "cpu", "master", "xtal";
};
};
soc {
bootph-all;
};
};
&clk32k {
clocks = <&slow_rc_osc>, <&slow_xtal>;
};
&main_xtal {
bootph-all;
};
&pioa {
bootph-all;
};
&pinctrl_uart6_default {
bootph-all;
};
&pit64b0 {
bootph-all;
};
&pmc {
bootph-all;
};
&sdmmc1 {
assigned-clock-parents = <&pmc PMC_TYPE_CORE 27>; /* MCK1 div */
microchip,sdcal-inverted;
no-1-8-v;
};
&slow_rc_osc {
bootph-all;
};
&slow_xtal {
bootph-all;
};
&uart6 {
bootph-all;
};

View File

@@ -1,79 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Samsung Exynos DTS pinctrl constants
*
* Copyright (c) 2016 Samsung Electronics Co., Ltd.
* http://www.samsung.com
* Copyright (c) 2022 Linaro Ltd
* Author: Krzysztof Kozlowski <krzk@kernel.org>
*/
#ifndef __DTS_ARM64_SAMSUNG_EXYNOS_PINCTRL_H__
#define __DTS_ARM64_SAMSUNG_EXYNOS_PINCTRL_H__
#define EXYNOS_PIN_PULL_NONE 0
#define EXYNOS_PIN_PULL_DOWN 1
#define EXYNOS_PIN_PULL_UP 3
/* Pin function in power down mode */
#define EXYNOS_PIN_PDN_OUT0 0
#define EXYNOS_PIN_PDN_OUT1 1
#define EXYNOS_PIN_PDN_INPUT 2
#define EXYNOS_PIN_PDN_PREV 3
/*
* Drive strengths for Exynos5410, Exynos542x, Exynos5800, Exynos7885, Exynos850
* (except GPIO_HSI block), ExynosAutov9 (FSI0, PERIC1)
*/
#define EXYNOS5420_PIN_DRV_LV1 0
#define EXYNOS5420_PIN_DRV_LV2 1
#define EXYNOS5420_PIN_DRV_LV3 2
#define EXYNOS5420_PIN_DRV_LV4 3
/* Drive strengths for Exynos5433 */
#define EXYNOS5433_PIN_DRV_FAST_SR1 0
#define EXYNOS5433_PIN_DRV_FAST_SR2 1
#define EXYNOS5433_PIN_DRV_FAST_SR3 2
#define EXYNOS5433_PIN_DRV_FAST_SR4 3
#define EXYNOS5433_PIN_DRV_FAST_SR5 4
#define EXYNOS5433_PIN_DRV_FAST_SR6 5
#define EXYNOS5433_PIN_DRV_SLOW_SR1 8
#define EXYNOS5433_PIN_DRV_SLOW_SR2 9
#define EXYNOS5433_PIN_DRV_SLOW_SR3 0xa
#define EXYNOS5433_PIN_DRV_SLOW_SR4 0xb
#define EXYNOS5433_PIN_DRV_SLOW_SR5 0xc
#define EXYNOS5433_PIN_DRV_SLOW_SR6 0xf
/* Drive strengths for Exynos7 (except FSYS1) */
#define EXYNOS7_PIN_DRV_LV1 0
#define EXYNOS7_PIN_DRV_LV2 2
#define EXYNOS7_PIN_DRV_LV3 1
#define EXYNOS7_PIN_DRV_LV4 3
/* Drive strengths for Exynos7 FSYS1 block */
#define EXYNOS7_FSYS1_PIN_DRV_LV1 0
#define EXYNOS7_FSYS1_PIN_DRV_LV2 4
#define EXYNOS7_FSYS1_PIN_DRV_LV3 2
#define EXYNOS7_FSYS1_PIN_DRV_LV4 6
#define EXYNOS7_FSYS1_PIN_DRV_LV5 1
#define EXYNOS7_FSYS1_PIN_DRV_LV6 5
/* Drive strengths for Exynos850 GPIO_HSI block */
#define EXYNOS850_HSI_PIN_DRV_LV1 0 /* 1x */
#define EXYNOS850_HSI_PIN_DRV_LV1_5 1 /* 1.5x */
#define EXYNOS850_HSI_PIN_DRV_LV2 2 /* 2x */
#define EXYNOS850_HSI_PIN_DRV_LV2_5 3 /* 2.5x */
#define EXYNOS850_HSI_PIN_DRV_LV3 4 /* 3x */
#define EXYNOS850_HSI_PIN_DRV_LV4 5 /* 4x */
#define EXYNOS_PIN_FUNC_INPUT 0
#define EXYNOS_PIN_FUNC_OUTPUT 1
#define EXYNOS_PIN_FUNC_2 2
#define EXYNOS_PIN_FUNC_3 3
#define EXYNOS_PIN_FUNC_4 4
#define EXYNOS_PIN_FUNC_5 5
#define EXYNOS_PIN_FUNC_6 6
#define EXYNOS_PIN_FUNC_EINT 0xf
#define EXYNOS_PIN_FUNC_F EXYNOS_PIN_FUNC_EINT
#endif /* __DTS_ARM64_SAMSUNG_EXYNOS_PINCTRL_H__ */

View File

@@ -130,29 +130,29 @@
pinctrl_lpuart0: lpuart0grp {
fsl,pins = <
SC_P_UART0_RX_ADMA_UART0_RX 0X06000020
SC_P_UART0_TX_ADMA_UART0_TX 0X06000020
SC_P_UART0_RX_ADMA_UART0_RX 0x06000020
SC_P_UART0_TX_ADMA_UART0_TX 0x06000020
>;
};
pinctrl_lpuart1: lpuart1grp {
fsl,pins = <
SC_P_UART1_RX_ADMA_UART1_RX 0X06000020
SC_P_UART1_TX_ADMA_UART1_TX 0X06000020
SC_P_UART1_RX_ADMA_UART1_RX 0x06000020
SC_P_UART1_TX_ADMA_UART1_TX 0x06000020
>;
};
pinctrl_lpuart2: lpuart2grp {
fsl,pins = <
SC_P_UART2_RX_ADMA_UART2_RX 0X06000020
SC_P_UART2_TX_ADMA_UART2_TX 0X06000020
SC_P_UART2_RX_ADMA_UART2_RX 0x06000020
SC_P_UART2_TX_ADMA_UART2_TX 0x06000020
>;
};
pinctrl_lpuart3: lpuart3grp {
fsl,pins = <
SC_P_FLEXCAN2_RX_ADMA_UART3_RX 0X06000020
SC_P_FLEXCAN2_TX_ADMA_UART3_TX 0X06000020
SC_P_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020
SC_P_FLEXCAN2_TX_ADMA_UART3_TX 0x06000020
>;
};

View File

@@ -580,7 +580,7 @@
rtc0: rtc@fff04000 {
compatible = "arm,pl031", "arm,primecell";
reg = <0x0 0Xfff04000 0x0 0x1000>;
reg = <0x0 0xfff04000 0x0 0x1000>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg_ctrl HI3660_PCLK>;
clock-names = "apb_pclk";

View File

@@ -1,327 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Header providing constants for i.MX23 pinctrl bindings.
*
* Copyright (C) 2013 Lothar Waßmann <LW@KARO-electronics.de>
*/
#ifndef __DT_BINDINGS_MX23_PINCTRL_H__
#define __DT_BINDINGS_MX23_PINCTRL_H__
#include "mxs-pinfunc.h"
#define MX23_PAD_GPMI_D00__GPMI_D00 0x0000
#define MX23_PAD_GPMI_D01__GPMI_D01 0x0010
#define MX23_PAD_GPMI_D02__GPMI_D02 0x0020
#define MX23_PAD_GPMI_D03__GPMI_D03 0x0030
#define MX23_PAD_GPMI_D04__GPMI_D04 0x0040
#define MX23_PAD_GPMI_D05__GPMI_D05 0x0050
#define MX23_PAD_GPMI_D06__GPMI_D06 0x0060
#define MX23_PAD_GPMI_D07__GPMI_D07 0x0070
#define MX23_PAD_GPMI_D08__GPMI_D08 0x0080
#define MX23_PAD_GPMI_D09__GPMI_D09 0x0090
#define MX23_PAD_GPMI_D10__GPMI_D10 0x00a0
#define MX23_PAD_GPMI_D11__GPMI_D11 0x00b0
#define MX23_PAD_GPMI_D12__GPMI_D12 0x00c0
#define MX23_PAD_GPMI_D13__GPMI_D13 0x00d0
#define MX23_PAD_GPMI_D14__GPMI_D14 0x00e0
#define MX23_PAD_GPMI_D15__GPMI_D15 0x00f0
#define MX23_PAD_GPMI_CLE__GPMI_CLE 0x0100
#define MX23_PAD_GPMI_ALE__GPMI_ALE 0x0110
#define MX23_PAD_GPMI_CE2N__GPMI_CE2N 0x0120
#define MX23_PAD_GPMI_RDY0__GPMI_RDY0 0x0130
#define MX23_PAD_GPMI_RDY1__GPMI_RDY1 0x0140
#define MX23_PAD_GPMI_RDY2__GPMI_RDY2 0x0150
#define MX23_PAD_GPMI_RDY3__GPMI_RDY3 0x0160
#define MX23_PAD_GPMI_WPN__GPMI_WPN 0x0170
#define MX23_PAD_GPMI_WRN__GPMI_WRN 0x0180
#define MX23_PAD_GPMI_RDN__GPMI_RDN 0x0190
#define MX23_PAD_AUART1_CTS__AUART1_CTS 0x01a0
#define MX23_PAD_AUART1_RTS__AUART1_RTS 0x01b0
#define MX23_PAD_AUART1_RX__AUART1_RX 0x01c0
#define MX23_PAD_AUART1_TX__AUART1_TX 0x01d0
#define MX23_PAD_I2C_SCL__I2C_SCL 0x01e0
#define MX23_PAD_I2C_SDA__I2C_SDA 0x01f0
#define MX23_PAD_LCD_D00__LCD_D00 0x1000
#define MX23_PAD_LCD_D01__LCD_D01 0x1010
#define MX23_PAD_LCD_D02__LCD_D02 0x1020
#define MX23_PAD_LCD_D03__LCD_D03 0x1030
#define MX23_PAD_LCD_D04__LCD_D04 0x1040
#define MX23_PAD_LCD_D05__LCD_D05 0x1050
#define MX23_PAD_LCD_D06__LCD_D06 0x1060
#define MX23_PAD_LCD_D07__LCD_D07 0x1070
#define MX23_PAD_LCD_D08__LCD_D08 0x1080
#define MX23_PAD_LCD_D09__LCD_D09 0x1090
#define MX23_PAD_LCD_D10__LCD_D10 0x10a0
#define MX23_PAD_LCD_D11__LCD_D11 0x10b0
#define MX23_PAD_LCD_D12__LCD_D12 0x10c0
#define MX23_PAD_LCD_D13__LCD_D13 0x10d0
#define MX23_PAD_LCD_D14__LCD_D14 0x10e0
#define MX23_PAD_LCD_D15__LCD_D15 0x10f0
#define MX23_PAD_LCD_D16__LCD_D16 0x1100
#define MX23_PAD_LCD_D17__LCD_D17 0x1110
#define MX23_PAD_LCD_RESET__LCD_RESET 0x1120
#define MX23_PAD_LCD_RS__LCD_RS 0x1130
#define MX23_PAD_LCD_WR__LCD_WR 0x1140
#define MX23_PAD_LCD_CS__LCD_CS 0x1150
#define MX23_PAD_LCD_DOTCK__LCD_DOTCK 0x1160
#define MX23_PAD_LCD_ENABLE__LCD_ENABLE 0x1170
#define MX23_PAD_LCD_HSYNC__LCD_HSYNC 0x1180
#define MX23_PAD_LCD_VSYNC__LCD_VSYNC 0x1190
#define MX23_PAD_PWM0__PWM0 0x11a0
#define MX23_PAD_PWM1__PWM1 0x11b0
#define MX23_PAD_PWM2__PWM2 0x11c0
#define MX23_PAD_PWM3__PWM3 0x11d0
#define MX23_PAD_PWM4__PWM4 0x11e0
#define MX23_PAD_SSP1_CMD__SSP1_CMD 0x2000
#define MX23_PAD_SSP1_DETECT__SSP1_DETECT 0x2010
#define MX23_PAD_SSP1_DATA0__SSP1_DATA0 0x2020
#define MX23_PAD_SSP1_DATA1__SSP1_DATA1 0x2030
#define MX23_PAD_SSP1_DATA2__SSP1_DATA2 0x2040
#define MX23_PAD_SSP1_DATA3__SSP1_DATA3 0x2050
#define MX23_PAD_SSP1_SCK__SSP1_SCK 0x2060
#define MX23_PAD_ROTARYA__ROTARYA 0x2070
#define MX23_PAD_ROTARYB__ROTARYB 0x2080
#define MX23_PAD_EMI_A00__EMI_A00 0x2090
#define MX23_PAD_EMI_A01__EMI_A01 0x20a0
#define MX23_PAD_EMI_A02__EMI_A02 0x20b0
#define MX23_PAD_EMI_A03__EMI_A03 0x20c0
#define MX23_PAD_EMI_A04__EMI_A04 0x20d0
#define MX23_PAD_EMI_A05__EMI_A05 0x20e0
#define MX23_PAD_EMI_A06__EMI_A06 0x20f0
#define MX23_PAD_EMI_A07__EMI_A07 0x2100
#define MX23_PAD_EMI_A08__EMI_A08 0x2110
#define MX23_PAD_EMI_A09__EMI_A09 0x2120
#define MX23_PAD_EMI_A10__EMI_A10 0x2130
#define MX23_PAD_EMI_A11__EMI_A11 0x2140
#define MX23_PAD_EMI_A12__EMI_A12 0x2150
#define MX23_PAD_EMI_BA0__EMI_BA0 0x2160
#define MX23_PAD_EMI_BA1__EMI_BA1 0x2170
#define MX23_PAD_EMI_CASN__EMI_CASN 0x2180
#define MX23_PAD_EMI_CE0N__EMI_CE0N 0x2190
#define MX23_PAD_EMI_CE1N__EMI_CE1N 0x21a0
#define MX23_PAD_GPMI_CE1N__GPMI_CE1N 0x21b0
#define MX23_PAD_GPMI_CE0N__GPMI_CE0N 0x21c0
#define MX23_PAD_EMI_CKE__EMI_CKE 0x21d0
#define MX23_PAD_EMI_RASN__EMI_RASN 0x21e0
#define MX23_PAD_EMI_WEN__EMI_WEN 0x21f0
#define MX23_PAD_EMI_D00__EMI_D00 0x3000
#define MX23_PAD_EMI_D01__EMI_D01 0x3010
#define MX23_PAD_EMI_D02__EMI_D02 0x3020
#define MX23_PAD_EMI_D03__EMI_D03 0x3030
#define MX23_PAD_EMI_D04__EMI_D04 0x3040
#define MX23_PAD_EMI_D05__EMI_D05 0x3050
#define MX23_PAD_EMI_D06__EMI_D06 0x3060
#define MX23_PAD_EMI_D07__EMI_D07 0x3070
#define MX23_PAD_EMI_D08__EMI_D08 0x3080
#define MX23_PAD_EMI_D09__EMI_D09 0x3090
#define MX23_PAD_EMI_D10__EMI_D10 0x30a0
#define MX23_PAD_EMI_D11__EMI_D11 0x30b0
#define MX23_PAD_EMI_D12__EMI_D12 0x30c0
#define MX23_PAD_EMI_D13__EMI_D13 0x30d0
#define MX23_PAD_EMI_D14__EMI_D14 0x30e0
#define MX23_PAD_EMI_D15__EMI_D15 0x30f0
#define MX23_PAD_EMI_DQM0__EMI_DQM0 0x3100
#define MX23_PAD_EMI_DQM1__EMI_DQM1 0x3110
#define MX23_PAD_EMI_DQS0__EMI_DQS0 0x3120
#define MX23_PAD_EMI_DQS1__EMI_DQS1 0x3130
#define MX23_PAD_EMI_CLK__EMI_CLK 0x3140
#define MX23_PAD_EMI_CLKN__EMI_CLKN 0x3150
#define MX23_PAD_GPMI_D00__LCD_D8 0x0001
#define MX23_PAD_GPMI_D01__LCD_D9 0x0011
#define MX23_PAD_GPMI_D02__LCD_D10 0x0021
#define MX23_PAD_GPMI_D03__LCD_D11 0x0031
#define MX23_PAD_GPMI_D04__LCD_D12 0x0041
#define MX23_PAD_GPMI_D05__LCD_D13 0x0051
#define MX23_PAD_GPMI_D06__LCD_D14 0x0061
#define MX23_PAD_GPMI_D07__LCD_D15 0x0071
#define MX23_PAD_GPMI_D08__LCD_D18 0x0081
#define MX23_PAD_GPMI_D09__LCD_D19 0x0091
#define MX23_PAD_GPMI_D10__LCD_D20 0x00a1
#define MX23_PAD_GPMI_D11__LCD_D21 0x00b1
#define MX23_PAD_GPMI_D12__LCD_D22 0x00c1
#define MX23_PAD_GPMI_D13__LCD_D23 0x00d1
#define MX23_PAD_GPMI_D14__AUART2_RX 0x00e1
#define MX23_PAD_GPMI_D15__AUART2_TX 0x00f1
#define MX23_PAD_GPMI_CLE__LCD_D16 0x0101
#define MX23_PAD_GPMI_ALE__LCD_D17 0x0111
#define MX23_PAD_GPMI_CE2N__ATA_A2 0x0121
#define MX23_PAD_AUART1_RTS__IR_CLK 0x01b1
#define MX23_PAD_AUART1_RX__IR_RX 0x01c1
#define MX23_PAD_AUART1_TX__IR_TX 0x01d1
#define MX23_PAD_I2C_SCL__GPMI_RDY2 0x01e1
#define MX23_PAD_I2C_SDA__GPMI_CE2N 0x01f1
#define MX23_PAD_LCD_D00__ETM_DA8 0x1001
#define MX23_PAD_LCD_D01__ETM_DA9 0x1011
#define MX23_PAD_LCD_D02__ETM_DA10 0x1021
#define MX23_PAD_LCD_D03__ETM_DA11 0x1031
#define MX23_PAD_LCD_D04__ETM_DA12 0x1041
#define MX23_PAD_LCD_D05__ETM_DA13 0x1051
#define MX23_PAD_LCD_D06__ETM_DA14 0x1061
#define MX23_PAD_LCD_D07__ETM_DA15 0x1071
#define MX23_PAD_LCD_D08__ETM_DA0 0x1081
#define MX23_PAD_LCD_D09__ETM_DA1 0x1091
#define MX23_PAD_LCD_D10__ETM_DA2 0x10a1
#define MX23_PAD_LCD_D11__ETM_DA3 0x10b1
#define MX23_PAD_LCD_D12__ETM_DA4 0x10c1
#define MX23_PAD_LCD_D13__ETM_DA5 0x10d1
#define MX23_PAD_LCD_D14__ETM_DA6 0x10e1
#define MX23_PAD_LCD_D15__ETM_DA7 0x10f1
#define MX23_PAD_LCD_RESET__ETM_TCTL 0x1121
#define MX23_PAD_LCD_RS__ETM_TCLK 0x1131
#define MX23_PAD_LCD_DOTCK__GPMI_RDY3 0x1161
#define MX23_PAD_LCD_ENABLE__I2C_SCL 0x1171
#define MX23_PAD_LCD_HSYNC__I2C_SDA 0x1181
#define MX23_PAD_LCD_VSYNC__LCD_BUSY 0x1191
#define MX23_PAD_PWM0__ROTARYA 0x11a1
#define MX23_PAD_PWM1__ROTARYB 0x11b1
#define MX23_PAD_PWM2__GPMI_RDY3 0x11c1
#define MX23_PAD_PWM3__ETM_TCTL 0x11d1
#define MX23_PAD_PWM4__ETM_TCLK 0x11e1
#define MX23_PAD_SSP1_DETECT__GPMI_CE3N 0x2011
#define MX23_PAD_SSP1_DATA1__I2C_SCL 0x2031
#define MX23_PAD_SSP1_DATA2__I2C_SDA 0x2041
#define MX23_PAD_ROTARYA__AUART2_RTS 0x2071
#define MX23_PAD_ROTARYB__AUART2_CTS 0x2081
#define MX23_PAD_GPMI_D00__SSP2_DATA0 0x0002
#define MX23_PAD_GPMI_D01__SSP2_DATA1 0x0012
#define MX23_PAD_GPMI_D02__SSP2_DATA2 0x0022
#define MX23_PAD_GPMI_D03__SSP2_DATA3 0x0032
#define MX23_PAD_GPMI_D04__SSP2_DATA4 0x0042
#define MX23_PAD_GPMI_D05__SSP2_DATA5 0x0052
#define MX23_PAD_GPMI_D06__SSP2_DATA6 0x0062
#define MX23_PAD_GPMI_D07__SSP2_DATA7 0x0072
#define MX23_PAD_GPMI_D08__SSP1_DATA4 0x0082
#define MX23_PAD_GPMI_D09__SSP1_DATA5 0x0092
#define MX23_PAD_GPMI_D10__SSP1_DATA6 0x00a2
#define MX23_PAD_GPMI_D11__SSP1_DATA7 0x00b2
#define MX23_PAD_GPMI_D15__GPMI_CE3N 0x00f2
#define MX23_PAD_GPMI_RDY0__SSP2_DETECT 0x0132
#define MX23_PAD_GPMI_RDY1__SSP2_CMD 0x0142
#define MX23_PAD_GPMI_WRN__SSP2_SCK 0x0182
#define MX23_PAD_AUART1_CTS__SSP1_DATA4 0x01a2
#define MX23_PAD_AUART1_RTS__SSP1_DATA5 0x01b2
#define MX23_PAD_AUART1_RX__SSP1_DATA6 0x01c2
#define MX23_PAD_AUART1_TX__SSP1_DATA7 0x01d2
#define MX23_PAD_I2C_SCL__AUART1_TX 0x01e2
#define MX23_PAD_I2C_SDA__AUART1_RX 0x01f2
#define MX23_PAD_LCD_D08__SAIF2_SDATA0 0x1082
#define MX23_PAD_LCD_D09__SAIF1_SDATA0 0x1092
#define MX23_PAD_LCD_D10__SAIF_MCLK_BITCLK 0x10a2
#define MX23_PAD_LCD_D11__SAIF_LRCLK 0x10b2
#define MX23_PAD_LCD_D12__SAIF2_SDATA1 0x10c2
#define MX23_PAD_LCD_D13__SAIF2_SDATA2 0x10d2
#define MX23_PAD_LCD_D14__SAIF1_SDATA2 0x10e2
#define MX23_PAD_LCD_D15__SAIF1_SDATA1 0x10f2
#define MX23_PAD_LCD_D16__SAIF_ALT_BITCLK 0x1102
#define MX23_PAD_LCD_RESET__GPMI_CE3N 0x1122
#define MX23_PAD_PWM0__DUART_RX 0x11a2
#define MX23_PAD_PWM1__DUART_TX 0x11b2
#define MX23_PAD_PWM3__AUART1_CTS 0x11d2
#define MX23_PAD_PWM4__AUART1_RTS 0x11e2
#define MX23_PAD_SSP1_CMD__JTAG_TDO 0x2002
#define MX23_PAD_SSP1_DETECT__USB_OTG_ID 0x2012
#define MX23_PAD_SSP1_DATA0__JTAG_TDI 0x2022
#define MX23_PAD_SSP1_DATA1__JTAG_TCLK 0x2032
#define MX23_PAD_SSP1_DATA2__JTAG_RTCK 0x2042
#define MX23_PAD_SSP1_DATA3__JTAG_TMS 0x2052
#define MX23_PAD_SSP1_SCK__JTAG_TRST 0x2062
#define MX23_PAD_ROTARYA__SPDIF 0x2072
#define MX23_PAD_ROTARYB__GPMI_CE3N 0x2082
#define MX23_PAD_GPMI_D00__GPIO_0_0 0x0003
#define MX23_PAD_GPMI_D01__GPIO_0_1 0x0013
#define MX23_PAD_GPMI_D02__GPIO_0_2 0x0023
#define MX23_PAD_GPMI_D03__GPIO_0_3 0x0033
#define MX23_PAD_GPMI_D04__GPIO_0_4 0x0043
#define MX23_PAD_GPMI_D05__GPIO_0_5 0x0053
#define MX23_PAD_GPMI_D06__GPIO_0_6 0x0063
#define MX23_PAD_GPMI_D07__GPIO_0_7 0x0073
#define MX23_PAD_GPMI_D08__GPIO_0_8 0x0083
#define MX23_PAD_GPMI_D09__GPIO_0_9 0x0093
#define MX23_PAD_GPMI_D10__GPIO_0_10 0x00a3
#define MX23_PAD_GPMI_D11__GPIO_0_11 0x00b3
#define MX23_PAD_GPMI_D12__GPIO_0_12 0x00c3
#define MX23_PAD_GPMI_D13__GPIO_0_13 0x00d3
#define MX23_PAD_GPMI_D14__GPIO_0_14 0x00e3
#define MX23_PAD_GPMI_D15__GPIO_0_15 0x00f3
#define MX23_PAD_GPMI_CLE__GPIO_0_16 0x0103
#define MX23_PAD_GPMI_ALE__GPIO_0_17 0x0113
#define MX23_PAD_GPMI_CE2N__GPIO_0_18 0x0123
#define MX23_PAD_GPMI_RDY0__GPIO_0_19 0x0133
#define MX23_PAD_GPMI_RDY1__GPIO_0_20 0x0143
#define MX23_PAD_GPMI_RDY2__GPIO_0_21 0x0153
#define MX23_PAD_GPMI_RDY3__GPIO_0_22 0x0163
#define MX23_PAD_GPMI_WPN__GPIO_0_23 0x0173
#define MX23_PAD_GPMI_WRN__GPIO_0_24 0x0183
#define MX23_PAD_GPMI_RDN__GPIO_0_25 0x0193
#define MX23_PAD_AUART1_CTS__GPIO_0_26 0x01a3
#define MX23_PAD_AUART1_RTS__GPIO_0_27 0x01b3
#define MX23_PAD_AUART1_RX__GPIO_0_28 0x01c3
#define MX23_PAD_AUART1_TX__GPIO_0_29 0x01d3
#define MX23_PAD_I2C_SCL__GPIO_0_30 0x01e3
#define MX23_PAD_I2C_SDA__GPIO_0_31 0x01f3
#define MX23_PAD_LCD_D00__GPIO_1_0 0x1003
#define MX23_PAD_LCD_D01__GPIO_1_1 0x1013
#define MX23_PAD_LCD_D02__GPIO_1_2 0x1023
#define MX23_PAD_LCD_D03__GPIO_1_3 0x1033
#define MX23_PAD_LCD_D04__GPIO_1_4 0x1043
#define MX23_PAD_LCD_D05__GPIO_1_5 0x1053
#define MX23_PAD_LCD_D06__GPIO_1_6 0x1063
#define MX23_PAD_LCD_D07__GPIO_1_7 0x1073
#define MX23_PAD_LCD_D08__GPIO_1_8 0x1083
#define MX23_PAD_LCD_D09__GPIO_1_9 0x1093
#define MX23_PAD_LCD_D10__GPIO_1_10 0x10a3
#define MX23_PAD_LCD_D11__GPIO_1_11 0x10b3
#define MX23_PAD_LCD_D12__GPIO_1_12 0x10c3
#define MX23_PAD_LCD_D13__GPIO_1_13 0x10d3
#define MX23_PAD_LCD_D14__GPIO_1_14 0x10e3
#define MX23_PAD_LCD_D15__GPIO_1_15 0x10f3
#define MX23_PAD_LCD_D16__GPIO_1_16 0x1103
#define MX23_PAD_LCD_D17__GPIO_1_17 0x1113
#define MX23_PAD_LCD_RESET__GPIO_1_18 0x1123
#define MX23_PAD_LCD_RS__GPIO_1_19 0x1133
#define MX23_PAD_LCD_WR__GPIO_1_20 0x1143
#define MX23_PAD_LCD_CS__GPIO_1_21 0x1153
#define MX23_PAD_LCD_DOTCK__GPIO_1_22 0x1163
#define MX23_PAD_LCD_ENABLE__GPIO_1_23 0x1173
#define MX23_PAD_LCD_HSYNC__GPIO_1_24 0x1183
#define MX23_PAD_LCD_VSYNC__GPIO_1_25 0x1193
#define MX23_PAD_PWM0__GPIO_1_26 0x11a3
#define MX23_PAD_PWM1__GPIO_1_27 0x11b3
#define MX23_PAD_PWM2__GPIO_1_28 0x11c3
#define MX23_PAD_PWM3__GPIO_1_29 0x11d3
#define MX23_PAD_PWM4__GPIO_1_30 0x11e3
#define MX23_PAD_SSP1_CMD__GPIO_2_0 0x2003
#define MX23_PAD_SSP1_DETECT__GPIO_2_1 0x2013
#define MX23_PAD_SSP1_DATA0__GPIO_2_2 0x2023
#define MX23_PAD_SSP1_DATA1__GPIO_2_3 0x2033
#define MX23_PAD_SSP1_DATA2__GPIO_2_4 0x2043
#define MX23_PAD_SSP1_DATA3__GPIO_2_5 0x2053
#define MX23_PAD_SSP1_SCK__GPIO_2_6 0x2063
#define MX23_PAD_ROTARYA__GPIO_2_7 0x2073
#define MX23_PAD_ROTARYB__GPIO_2_8 0x2083
#define MX23_PAD_EMI_A00__GPIO_2_9 0x2093
#define MX23_PAD_EMI_A01__GPIO_2_10 0x20a3
#define MX23_PAD_EMI_A02__GPIO_2_11 0x20b3
#define MX23_PAD_EMI_A03__GPIO_2_12 0x20c3
#define MX23_PAD_EMI_A04__GPIO_2_13 0x20d3
#define MX23_PAD_EMI_A05__GPIO_2_14 0x20e3
#define MX23_PAD_EMI_A06__GPIO_2_15 0x20f3
#define MX23_PAD_EMI_A07__GPIO_2_16 0x2103
#define MX23_PAD_EMI_A08__GPIO_2_17 0x2113
#define MX23_PAD_EMI_A09__GPIO_2_18 0x2123
#define MX23_PAD_EMI_A10__GPIO_2_19 0x2133
#define MX23_PAD_EMI_A11__GPIO_2_20 0x2143
#define MX23_PAD_EMI_A12__GPIO_2_21 0x2153
#define MX23_PAD_EMI_BA0__GPIO_2_22 0x2163
#define MX23_PAD_EMI_BA1__GPIO_2_23 0x2173
#define MX23_PAD_EMI_CASN__GPIO_2_24 0x2183
#define MX23_PAD_EMI_CE0N__GPIO_2_25 0x2193
#define MX23_PAD_EMI_CE1N__GPIO_2_26 0x21a3
#define MX23_PAD_GPMI_CE1N__GPIO_2_27 0x21b3
#define MX23_PAD_GPMI_CE0N__GPIO_2_28 0x21c3
#define MX23_PAD_EMI_CKE__GPIO_2_29 0x21d3
#define MX23_PAD_EMI_RASN__GPIO_2_30 0x21e3
#define MX23_PAD_EMI_WEN__GPIO_2_31 0x21f3
#endif /* __DT_BINDINGS_MX23_PINCTRL_H__ */

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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2025
* Lukasz Majewski, DENX Software Engineering, lukma@denx.de
*/
#include "imx28-btt3-u-boot.dtsi"

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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2025
* Lukasz Majewski, DENX Software Engineering, lukma@denx.de
*/
#include "imx28-btt3-u-boot.dtsi"

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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2025
* Lukasz Majewski, DENX Software Engineering, lukma@denx.de
*/
#include "imx28-btt3-u-boot.dtsi"

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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2025
* Lukasz Majewski, DENX Software Engineering, lukma@denx.de
*/
/*
* The minimal augmentation DTS U-Boot file to allow eMMC driver
* configuration in SPL for falcon boot.
*/
#include "imx28-u-boot.dtsi"
/ {
aliases {
/delete-property/ saif0;
/delete-property/ saif1;
/delete-property/ spi0;
/delete-property/ spi1;
/delete-property/ usbphy0;
/delete-property/ usbphy1;
};
apb@80000000 {
bootph-pre-ram;
apbh@80000000 {
bootph-pre-ram;
};
apbx@80040000 {
bootph-pre-ram;
};
};
/delete-node/ keypad;
/delete-node/ panel;
/delete-node/ sdio-pwrseq;
/delete-node/ sound;
};
&clks {
bootph-pre-ram;
status = "disable";
};
&duart {
/delete-property/ clocks;
bootph-pre-ram;
type = <1>; /* TYPE_PL011 */
};
&gpio0 {
bootph-pre-ram;
};
&gpio3 {
bootph-pre-ram;
};
&gpio4 {
bootph-pre-ram;
};
&pinctrl {
/delete-property/ pinctrl-names;
/delete-property/ pinctrl-0;
bootph-pre-ram;
};
&ssp0 {
bootph-pre-ram;
};
&ssp3 {
num-cs = <2>;
spi-max-frequency = <40000000>;
bootph-pre-ram;
};
/delete-node/ &hog_pins_a;
/delete-node/ &keypad_pins_bttc;
/delete-node/ &lcdif;
/delete-node/ &lcdif_sync_pins_bttc;
/delete-node/ &pwm;
/delete-node/ &saif0;
/delete-node/ &saif1;
/delete-node/ &ssp1;
/delete-node/ &ssp2;
/delete-node/ &usb0;
/delete-node/ &usb1;
/delete-node/ &usbphy0;
/delete-node/ &usbphy1;

View File

@@ -1,500 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Header providing constants for i.MX28 pinctrl bindings.
*
* Copyright (C) 2013 Lothar Waßmann <LW@KARO-electronics.de>
*/
#ifndef __DT_BINDINGS_MX28_PINCTRL_H__
#define __DT_BINDINGS_MX28_PINCTRL_H__
#include "mxs-pinfunc.h"
#define MX28_PAD_GPMI_D00__GPMI_D0 0x0000
#define MX28_PAD_GPMI_D01__GPMI_D1 0x0010
#define MX28_PAD_GPMI_D02__GPMI_D2 0x0020
#define MX28_PAD_GPMI_D03__GPMI_D3 0x0030
#define MX28_PAD_GPMI_D04__GPMI_D4 0x0040
#define MX28_PAD_GPMI_D05__GPMI_D5 0x0050
#define MX28_PAD_GPMI_D06__GPMI_D6 0x0060
#define MX28_PAD_GPMI_D07__GPMI_D7 0x0070
#define MX28_PAD_GPMI_CE0N__GPMI_CE0N 0x0100
#define MX28_PAD_GPMI_CE1N__GPMI_CE1N 0x0110
#define MX28_PAD_GPMI_CE2N__GPMI_CE2N 0x0120
#define MX28_PAD_GPMI_CE3N__GPMI_CE3N 0x0130
#define MX28_PAD_GPMI_RDY0__GPMI_READY0 0x0140
#define MX28_PAD_GPMI_RDY1__GPMI_READY1 0x0150
#define MX28_PAD_GPMI_RDY2__GPMI_READY2 0x0160
#define MX28_PAD_GPMI_RDY3__GPMI_READY3 0x0170
#define MX28_PAD_GPMI_RDN__GPMI_RDN 0x0180
#define MX28_PAD_GPMI_WRN__GPMI_WRN 0x0190
#define MX28_PAD_GPMI_ALE__GPMI_ALE 0x01a0
#define MX28_PAD_GPMI_CLE__GPMI_CLE 0x01b0
#define MX28_PAD_GPMI_RESETN__GPMI_RESETN 0x01c0
#define MX28_PAD_LCD_D00__LCD_D0 0x1000
#define MX28_PAD_LCD_D01__LCD_D1 0x1010
#define MX28_PAD_LCD_D02__LCD_D2 0x1020
#define MX28_PAD_LCD_D03__LCD_D3 0x1030
#define MX28_PAD_LCD_D04__LCD_D4 0x1040
#define MX28_PAD_LCD_D05__LCD_D5 0x1050
#define MX28_PAD_LCD_D06__LCD_D6 0x1060
#define MX28_PAD_LCD_D07__LCD_D7 0x1070
#define MX28_PAD_LCD_D08__LCD_D8 0x1080
#define MX28_PAD_LCD_D09__LCD_D9 0x1090
#define MX28_PAD_LCD_D10__LCD_D10 0x10a0
#define MX28_PAD_LCD_D11__LCD_D11 0x10b0
#define MX28_PAD_LCD_D12__LCD_D12 0x10c0
#define MX28_PAD_LCD_D13__LCD_D13 0x10d0
#define MX28_PAD_LCD_D14__LCD_D14 0x10e0
#define MX28_PAD_LCD_D15__LCD_D15 0x10f0
#define MX28_PAD_LCD_D16__LCD_D16 0x1100
#define MX28_PAD_LCD_D17__LCD_D17 0x1110
#define MX28_PAD_LCD_D18__LCD_D18 0x1120
#define MX28_PAD_LCD_D19__LCD_D19 0x1130
#define MX28_PAD_LCD_D20__LCD_D20 0x1140
#define MX28_PAD_LCD_D21__LCD_D21 0x1150
#define MX28_PAD_LCD_D22__LCD_D22 0x1160
#define MX28_PAD_LCD_D23__LCD_D23 0x1170
#define MX28_PAD_LCD_RD_E__LCD_RD_E 0x1180
#define MX28_PAD_LCD_WR_RWN__LCD_WR_RWN 0x1190
#define MX28_PAD_LCD_RS__LCD_RS 0x11a0
#define MX28_PAD_LCD_CS__LCD_CS 0x11b0
#define MX28_PAD_LCD_VSYNC__LCD_VSYNC 0x11c0
#define MX28_PAD_LCD_HSYNC__LCD_HSYNC 0x11d0
#define MX28_PAD_LCD_DOTCLK__LCD_DOTCLK 0x11e0
#define MX28_PAD_LCD_ENABLE__LCD_ENABLE 0x11f0
#define MX28_PAD_SSP0_DATA0__SSP0_D0 0x2000
#define MX28_PAD_SSP0_DATA1__SSP0_D1 0x2010
#define MX28_PAD_SSP0_DATA2__SSP0_D2 0x2020
#define MX28_PAD_SSP0_DATA3__SSP0_D3 0x2030
#define MX28_PAD_SSP0_DATA4__SSP0_D4 0x2040
#define MX28_PAD_SSP0_DATA5__SSP0_D5 0x2050
#define MX28_PAD_SSP0_DATA6__SSP0_D6 0x2060
#define MX28_PAD_SSP0_DATA7__SSP0_D7 0x2070
#define MX28_PAD_SSP0_CMD__SSP0_CMD 0x2080
#define MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT 0x2090
#define MX28_PAD_SSP0_SCK__SSP0_SCK 0x20a0
#define MX28_PAD_SSP1_SCK__SSP1_SCK 0x20c0
#define MX28_PAD_SSP1_CMD__SSP1_CMD 0x20d0
#define MX28_PAD_SSP1_DATA0__SSP1_D0 0x20e0
#define MX28_PAD_SSP1_DATA3__SSP1_D3 0x20f0
#define MX28_PAD_SSP2_SCK__SSP2_SCK 0x2100
#define MX28_PAD_SSP2_MOSI__SSP2_CMD 0x2110
#define MX28_PAD_SSP2_MISO__SSP2_D0 0x2120
#define MX28_PAD_SSP2_SS0__SSP2_D3 0x2130
#define MX28_PAD_SSP2_SS1__SSP2_D4 0x2140
#define MX28_PAD_SSP2_SS2__SSP2_D5 0x2150
#define MX28_PAD_SSP3_SCK__SSP3_SCK 0x2180
#define MX28_PAD_SSP3_MOSI__SSP3_CMD 0x2190
#define MX28_PAD_SSP3_MISO__SSP3_D0 0x21a0
#define MX28_PAD_SSP3_SS0__SSP3_D3 0x21b0
#define MX28_PAD_AUART0_RX__AUART0_RX 0x3000
#define MX28_PAD_AUART0_TX__AUART0_TX 0x3010
#define MX28_PAD_AUART0_CTS__AUART0_CTS 0x3020
#define MX28_PAD_AUART0_RTS__AUART0_RTS 0x3030
#define MX28_PAD_AUART1_RX__AUART1_RX 0x3040
#define MX28_PAD_AUART1_TX__AUART1_TX 0x3050
#define MX28_PAD_AUART1_CTS__AUART1_CTS 0x3060
#define MX28_PAD_AUART1_RTS__AUART1_RTS 0x3070
#define MX28_PAD_AUART2_RX__AUART2_RX 0x3080
#define MX28_PAD_AUART2_TX__AUART2_TX 0x3090
#define MX28_PAD_AUART2_CTS__AUART2_CTS 0x30a0
#define MX28_PAD_AUART2_RTS__AUART2_RTS 0x30b0
#define MX28_PAD_AUART3_RX__AUART3_RX 0x30c0
#define MX28_PAD_AUART3_TX__AUART3_TX 0x30d0
#define MX28_PAD_AUART3_CTS__AUART3_CTS 0x30e0
#define MX28_PAD_AUART3_RTS__AUART3_RTS 0x30f0
#define MX28_PAD_PWM0__PWM_0 0x3100
#define MX28_PAD_PWM1__PWM_1 0x3110
#define MX28_PAD_PWM2__PWM_2 0x3120
#define MX28_PAD_SAIF0_MCLK__SAIF0_MCLK 0x3140
#define MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK 0x3150
#define MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK 0x3160
#define MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 0x3170
#define MX28_PAD_I2C0_SCL__I2C0_SCL 0x3180
#define MX28_PAD_I2C0_SDA__I2C0_SDA 0x3190
#define MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 0x31a0
#define MX28_PAD_SPDIF__SPDIF_TX 0x31b0
#define MX28_PAD_PWM3__PWM_3 0x31c0
#define MX28_PAD_PWM4__PWM_4 0x31d0
#define MX28_PAD_LCD_RESET__LCD_RESET 0x31e0
#define MX28_PAD_ENET0_MDC__ENET0_MDC 0x4000
#define MX28_PAD_ENET0_MDIO__ENET0_MDIO 0x4010
#define MX28_PAD_ENET0_RX_EN__ENET0_RX_EN 0x4020
#define MX28_PAD_ENET0_RXD0__ENET0_RXD0 0x4030
#define MX28_PAD_ENET0_RXD1__ENET0_RXD1 0x4040
#define MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK 0x4050
#define MX28_PAD_ENET0_TX_EN__ENET0_TX_EN 0x4060
#define MX28_PAD_ENET0_TXD0__ENET0_TXD0 0x4070
#define MX28_PAD_ENET0_TXD1__ENET0_TXD1 0x4080
#define MX28_PAD_ENET0_RXD2__ENET0_RXD2 0x4090
#define MX28_PAD_ENET0_RXD3__ENET0_RXD3 0x40a0
#define MX28_PAD_ENET0_TXD2__ENET0_TXD2 0x40b0
#define MX28_PAD_ENET0_TXD3__ENET0_TXD3 0x40c0
#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK 0x40d0
#define MX28_PAD_ENET0_COL__ENET0_COL 0x40e0
#define MX28_PAD_ENET0_CRS__ENET0_CRS 0x40f0
#define MX28_PAD_ENET_CLK__CLKCTRL_ENET 0x4100
#define MX28_PAD_JTAG_RTCK__JTAG_RTCK 0x4140
#define MX28_PAD_EMI_D00__EMI_DATA0 0x5000
#define MX28_PAD_EMI_D01__EMI_DATA1 0x5010
#define MX28_PAD_EMI_D02__EMI_DATA2 0x5020
#define MX28_PAD_EMI_D03__EMI_DATA3 0x5030
#define MX28_PAD_EMI_D04__EMI_DATA4 0x5040
#define MX28_PAD_EMI_D05__EMI_DATA5 0x5050
#define MX28_PAD_EMI_D06__EMI_DATA6 0x5060
#define MX28_PAD_EMI_D07__EMI_DATA7 0x5070
#define MX28_PAD_EMI_D08__EMI_DATA8 0x5080
#define MX28_PAD_EMI_D09__EMI_DATA9 0x5090
#define MX28_PAD_EMI_D10__EMI_DATA10 0x50a0
#define MX28_PAD_EMI_D11__EMI_DATA11 0x50b0
#define MX28_PAD_EMI_D12__EMI_DATA12 0x50c0
#define MX28_PAD_EMI_D13__EMI_DATA13 0x50d0
#define MX28_PAD_EMI_D14__EMI_DATA14 0x50e0
#define MX28_PAD_EMI_D15__EMI_DATA15 0x50f0
#define MX28_PAD_EMI_ODT0__EMI_ODT0 0x5100
#define MX28_PAD_EMI_DQM0__EMI_DQM0 0x5110
#define MX28_PAD_EMI_ODT1__EMI_ODT1 0x5120
#define MX28_PAD_EMI_DQM1__EMI_DQM1 0x5130
#define MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK 0x5140
#define MX28_PAD_EMI_CLK__EMI_CLK 0x5150
#define MX28_PAD_EMI_DQS0__EMI_DQS0 0x5160
#define MX28_PAD_EMI_DQS1__EMI_DQS1 0x5170
#define MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN 0x51a0
#define MX28_PAD_EMI_A00__EMI_ADDR0 0x6000
#define MX28_PAD_EMI_A01__EMI_ADDR1 0x6010
#define MX28_PAD_EMI_A02__EMI_ADDR2 0x6020
#define MX28_PAD_EMI_A03__EMI_ADDR3 0x6030
#define MX28_PAD_EMI_A04__EMI_ADDR4 0x6040
#define MX28_PAD_EMI_A05__EMI_ADDR5 0x6050
#define MX28_PAD_EMI_A06__EMI_ADDR6 0x6060
#define MX28_PAD_EMI_A07__EMI_ADDR7 0x6070
#define MX28_PAD_EMI_A08__EMI_ADDR8 0x6080
#define MX28_PAD_EMI_A09__EMI_ADDR9 0x6090
#define MX28_PAD_EMI_A10__EMI_ADDR10 0x60a0
#define MX28_PAD_EMI_A11__EMI_ADDR11 0x60b0
#define MX28_PAD_EMI_A12__EMI_ADDR12 0x60c0
#define MX28_PAD_EMI_A13__EMI_ADDR13 0x60d0
#define MX28_PAD_EMI_A14__EMI_ADDR14 0x60e0
#define MX28_PAD_EMI_BA0__EMI_BA0 0x6100
#define MX28_PAD_EMI_BA1__EMI_BA1 0x6110
#define MX28_PAD_EMI_BA2__EMI_BA2 0x6120
#define MX28_PAD_EMI_CASN__EMI_CASN 0x6130
#define MX28_PAD_EMI_RASN__EMI_RASN 0x6140
#define MX28_PAD_EMI_WEN__EMI_WEN 0x6150
#define MX28_PAD_EMI_CE0N__EMI_CE0N 0x6160
#define MX28_PAD_EMI_CE1N__EMI_CE1N 0x6170
#define MX28_PAD_EMI_CKE__EMI_CKE 0x6180
#define MX28_PAD_GPMI_D00__SSP1_D0 0x0001
#define MX28_PAD_GPMI_D01__SSP1_D1 0x0011
#define MX28_PAD_GPMI_D02__SSP1_D2 0x0021
#define MX28_PAD_GPMI_D03__SSP1_D3 0x0031
#define MX28_PAD_GPMI_D04__SSP1_D4 0x0041
#define MX28_PAD_GPMI_D05__SSP1_D5 0x0051
#define MX28_PAD_GPMI_D06__SSP1_D6 0x0061
#define MX28_PAD_GPMI_D07__SSP1_D7 0x0071
#define MX28_PAD_GPMI_CE0N__SSP3_D0 0x0101
#define MX28_PAD_GPMI_CE1N__SSP3_D3 0x0111
#define MX28_PAD_GPMI_CE2N__CAN1_TX 0x0121
#define MX28_PAD_GPMI_CE3N__CAN1_RX 0x0131
#define MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT 0x0141
#define MX28_PAD_GPMI_RDY1__SSP1_CMD 0x0151
#define MX28_PAD_GPMI_RDY2__CAN0_TX 0x0161
#define MX28_PAD_GPMI_RDY3__CAN0_RX 0x0171
#define MX28_PAD_GPMI_RDN__SSP3_SCK 0x0181
#define MX28_PAD_GPMI_WRN__SSP1_SCK 0x0191
#define MX28_PAD_GPMI_ALE__SSP3_D1 0x01a1
#define MX28_PAD_GPMI_CLE__SSP3_D2 0x01b1
#define MX28_PAD_GPMI_RESETN__SSP3_CMD 0x01c1
#define MX28_PAD_LCD_D03__ETM_DA8 0x1031
#define MX28_PAD_LCD_D04__ETM_DA9 0x1041
#define MX28_PAD_LCD_D08__ETM_DA3 0x1081
#define MX28_PAD_LCD_D09__ETM_DA4 0x1091
#define MX28_PAD_LCD_D20__ENET1_1588_EVENT2_OUT 0x1141
#define MX28_PAD_LCD_D21__ENET1_1588_EVENT2_IN 0x1151
#define MX28_PAD_LCD_D22__ENET1_1588_EVENT3_OUT 0x1161
#define MX28_PAD_LCD_D23__ENET1_1588_EVENT3_IN 0x1171
#define MX28_PAD_LCD_RD_E__LCD_VSYNC 0x1181
#define MX28_PAD_LCD_WR_RWN__LCD_HSYNC 0x1191
#define MX28_PAD_LCD_RS__LCD_DOTCLK 0x11a1
#define MX28_PAD_LCD_CS__LCD_ENABLE 0x11b1
#define MX28_PAD_LCD_VSYNC__SAIF1_SDATA0 0x11c1
#define MX28_PAD_LCD_HSYNC__SAIF1_SDATA1 0x11d1
#define MX28_PAD_LCD_DOTCLK__SAIF1_MCLK 0x11e1
#define MX28_PAD_SSP0_DATA4__SSP2_D0 0x2041
#define MX28_PAD_SSP0_DATA5__SSP2_D3 0x2051
#define MX28_PAD_SSP0_DATA6__SSP2_CMD 0x2061
#define MX28_PAD_SSP0_DATA7__SSP2_SCK 0x2071
#define MX28_PAD_SSP1_SCK__SSP2_D1 0x20c1
#define MX28_PAD_SSP1_CMD__SSP2_D2 0x20d1
#define MX28_PAD_SSP1_DATA0__SSP2_D6 0x20e1
#define MX28_PAD_SSP1_DATA3__SSP2_D7 0x20f1
#define MX28_PAD_SSP2_SCK__AUART2_RX 0x2101
#define MX28_PAD_SSP2_MOSI__AUART2_TX 0x2111
#define MX28_PAD_SSP2_MISO__AUART3_RX 0x2121
#define MX28_PAD_SSP2_SS0__AUART3_TX 0x2131
#define MX28_PAD_SSP2_SS1__SSP2_D1 0x2141
#define MX28_PAD_SSP2_SS2__SSP2_D2 0x2151
#define MX28_PAD_SSP3_SCK__AUART4_TX 0x2181
#define MX28_PAD_SSP3_MOSI__AUART4_RX 0x2191
#define MX28_PAD_SSP3_MISO__AUART4_RTS 0x21a1
#define MX28_PAD_SSP3_SS0__AUART4_CTS 0x21b1
#define MX28_PAD_AUART0_RX__I2C0_SCL 0x3001
#define MX28_PAD_AUART0_TX__I2C0_SDA 0x3011
#define MX28_PAD_AUART0_CTS__AUART4_RX 0x3021
#define MX28_PAD_AUART0_RTS__AUART4_TX 0x3031
#define MX28_PAD_AUART1_RX__SSP2_CARD_DETECT 0x3041
#define MX28_PAD_AUART1_TX__SSP3_CARD_DETECT 0x3051
#define MX28_PAD_AUART1_CTS__USB0_OVERCURRENT 0x3061
#define MX28_PAD_AUART1_RTS__USB0_ID 0x3071
#define MX28_PAD_AUART2_RX__SSP3_D1 0x3081
#define MX28_PAD_AUART2_TX__SSP3_D2 0x3091
#define MX28_PAD_AUART2_CTS__I2C1_SCL 0x30a1
#define MX28_PAD_AUART2_RTS__I2C1_SDA 0x30b1
#define MX28_PAD_AUART3_RX__CAN0_TX 0x30c1
#define MX28_PAD_AUART3_TX__CAN0_RX 0x30d1
#define MX28_PAD_AUART3_CTS__CAN1_TX 0x30e1
#define MX28_PAD_AUART3_RTS__CAN1_RX 0x30f1
#define MX28_PAD_PWM0__I2C1_SCL 0x3101
#define MX28_PAD_PWM1__I2C1_SDA 0x3111
#define MX28_PAD_PWM2__USB0_ID 0x3121
#define MX28_PAD_SAIF0_MCLK__PWM_3 0x3141
#define MX28_PAD_SAIF0_LRCLK__PWM_4 0x3151
#define MX28_PAD_SAIF0_BITCLK__PWM_5 0x3161
#define MX28_PAD_SAIF0_SDATA0__PWM_6 0x3171
#define MX28_PAD_I2C0_SCL__TIMROT_ROTARYA 0x3181
#define MX28_PAD_I2C0_SDA__TIMROT_ROTARYB 0x3191
#define MX28_PAD_SAIF1_SDATA0__PWM_7 0x31a1
#define MX28_PAD_LCD_RESET__LCD_VSYNC 0x31e1
#define MX28_PAD_ENET0_MDC__GPMI_CE4N 0x4001
#define MX28_PAD_ENET0_MDIO__GPMI_CE5N 0x4011
#define MX28_PAD_ENET0_RX_EN__GPMI_CE6N 0x4021
#define MX28_PAD_ENET0_RXD0__GPMI_CE7N 0x4031
#define MX28_PAD_ENET0_RXD1__GPMI_READY4 0x4041
#define MX28_PAD_ENET0_TX_CLK__HSADC_TRIGGER 0x4051
#define MX28_PAD_ENET0_TX_EN__GPMI_READY5 0x4061
#define MX28_PAD_ENET0_TXD0__GPMI_READY6 0x4071
#define MX28_PAD_ENET0_TXD1__GPMI_READY7 0x4081
#define MX28_PAD_ENET0_RXD2__ENET1_RXD0 0x4091
#define MX28_PAD_ENET0_RXD3__ENET1_RXD1 0x40a1
#define MX28_PAD_ENET0_TXD2__ENET1_TXD0 0x40b1
#define MX28_PAD_ENET0_TXD3__ENET1_TXD1 0x40c1
#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_ER 0x40d1
#define MX28_PAD_ENET0_COL__ENET1_TX_EN 0x40e1
#define MX28_PAD_ENET0_CRS__ENET1_RX_EN 0x40f1
#define MX28_PAD_GPMI_CE2N__ENET0_RX_ER 0x0122
#define MX28_PAD_GPMI_CE3N__SAIF1_MCLK 0x0132
#define MX28_PAD_GPMI_RDY0__USB0_ID 0x0142
#define MX28_PAD_GPMI_RDY2__ENET0_TX_ER 0x0162
#define MX28_PAD_GPMI_RDY3__HSADC_TRIGGER 0x0172
#define MX28_PAD_GPMI_ALE__SSP3_D4 0x01a2
#define MX28_PAD_GPMI_CLE__SSP3_D5 0x01b2
#define MX28_PAD_LCD_D00__ETM_DA0 0x1002
#define MX28_PAD_LCD_D01__ETM_DA1 0x1012
#define MX28_PAD_LCD_D02__ETM_DA2 0x1022
#define MX28_PAD_LCD_D03__ETM_DA3 0x1032
#define MX28_PAD_LCD_D04__ETM_DA4 0x1042
#define MX28_PAD_LCD_D05__ETM_DA5 0x1052
#define MX28_PAD_LCD_D06__ETM_DA6 0x1062
#define MX28_PAD_LCD_D07__ETM_DA7 0x1072
#define MX28_PAD_LCD_D08__ETM_DA8 0x1082
#define MX28_PAD_LCD_D09__ETM_DA9 0x1092
#define MX28_PAD_LCD_D10__ETM_DA10 0x10a2
#define MX28_PAD_LCD_D11__ETM_DA11 0x10b2
#define MX28_PAD_LCD_D12__ETM_DA12 0x10c2
#define MX28_PAD_LCD_D13__ETM_DA13 0x10d2
#define MX28_PAD_LCD_D14__ETM_DA14 0x10e2
#define MX28_PAD_LCD_D15__ETM_DA15 0x10f2
#define MX28_PAD_LCD_D16__ETM_DA7 0x1102
#define MX28_PAD_LCD_D17__ETM_DA6 0x1112
#define MX28_PAD_LCD_D18__ETM_DA5 0x1122
#define MX28_PAD_LCD_D19__ETM_DA4 0x1132
#define MX28_PAD_LCD_D20__ETM_DA3 0x1142
#define MX28_PAD_LCD_D21__ETM_DA2 0x1152
#define MX28_PAD_LCD_D22__ETM_DA1 0x1162
#define MX28_PAD_LCD_D23__ETM_DA0 0x1172
#define MX28_PAD_LCD_RD_E__ETM_TCTL 0x1182
#define MX28_PAD_LCD_WR_RWN__ETM_TCLK 0x1192
#define MX28_PAD_LCD_HSYNC__ETM_TCTL 0x11d2
#define MX28_PAD_LCD_DOTCLK__ETM_TCLK 0x11e2
#define MX28_PAD_SSP1_SCK__ENET0_1588_EVENT2_OUT 0x20c2
#define MX28_PAD_SSP1_CMD__ENET0_1588_EVENT2_IN 0x20d2
#define MX28_PAD_SSP1_DATA0__ENET0_1588_EVENT3_OUT 0x20e2
#define MX28_PAD_SSP1_DATA3__ENET0_1588_EVENT3_IN 0x20f2
#define MX28_PAD_SSP2_SCK__SAIF0_SDATA1 0x2102
#define MX28_PAD_SSP2_MOSI__SAIF0_SDATA2 0x2112
#define MX28_PAD_SSP2_MISO__SAIF1_SDATA1 0x2122
#define MX28_PAD_SSP2_SS0__SAIF1_SDATA2 0x2132
#define MX28_PAD_SSP2_SS1__USB1_OVERCURRENT 0x2142
#define MX28_PAD_SSP2_SS2__USB0_OVERCURRENT 0x2152
#define MX28_PAD_SSP3_SCK__ENET1_1588_EVENT0_OUT 0x2182
#define MX28_PAD_SSP3_MOSI__ENET1_1588_EVENT0_IN 0x2192
#define MX28_PAD_SSP3_MISO__ENET1_1588_EVENT1_OUT 0x21a2
#define MX28_PAD_SSP3_SS0__ENET1_1588_EVENT1_IN 0x21b2
#define MX28_PAD_AUART0_RX__DUART_CTS 0x3002
#define MX28_PAD_AUART0_TX__DUART_RTS 0x3012
#define MX28_PAD_AUART0_CTS__DUART_RX 0x3022
#define MX28_PAD_AUART0_RTS__DUART_TX 0x3032
#define MX28_PAD_AUART1_RX__PWM_0 0x3042
#define MX28_PAD_AUART1_TX__PWM_1 0x3052
#define MX28_PAD_AUART1_CTS__TIMROT_ROTARYA 0x3062
#define MX28_PAD_AUART1_RTS__TIMROT_ROTARYB 0x3072
#define MX28_PAD_AUART2_RX__SSP3_D4 0x3082
#define MX28_PAD_AUART2_TX__SSP3_D5 0x3092
#define MX28_PAD_AUART2_CTS__SAIF1_BITCLK 0x30a2
#define MX28_PAD_AUART2_RTS__SAIF1_LRCLK 0x30b2
#define MX28_PAD_AUART3_RX__ENET0_1588_EVENT0_OUT 0x30c2
#define MX28_PAD_AUART3_TX__ENET0_1588_EVENT0_IN 0x30d2
#define MX28_PAD_AUART3_CTS__ENET0_1588_EVENT1_OUT 0x30e2
#define MX28_PAD_AUART3_RTS__ENET0_1588_EVENT1_IN 0x30f2
#define MX28_PAD_PWM0__DUART_RX 0x3102
#define MX28_PAD_PWM1__DUART_TX 0x3112
#define MX28_PAD_PWM2__USB1_OVERCURRENT 0x3122
#define MX28_PAD_SAIF0_MCLK__AUART4_CTS 0x3142
#define MX28_PAD_SAIF0_LRCLK__AUART4_RTS 0x3152
#define MX28_PAD_SAIF0_BITCLK__AUART4_RX 0x3162
#define MX28_PAD_SAIF0_SDATA0__AUART4_TX 0x3172
#define MX28_PAD_I2C0_SCL__DUART_RX 0x3182
#define MX28_PAD_I2C0_SDA__DUART_TX 0x3192
#define MX28_PAD_SAIF1_SDATA0__SAIF0_SDATA1 0x31a2
#define MX28_PAD_SPDIF__ENET1_RX_ER 0x31b2
#define MX28_PAD_ENET0_MDC__SAIF0_SDATA1 0x4002
#define MX28_PAD_ENET0_MDIO__SAIF0_SDATA2 0x4012
#define MX28_PAD_ENET0_RX_EN__SAIF1_SDATA1 0x4022
#define MX28_PAD_ENET0_RXD0__SAIF1_SDATA2 0x4032
#define MX28_PAD_ENET0_TX_CLK__ENET0_1588_EVENT2_OUT 0x4052
#define MX28_PAD_ENET0_RXD2__ENET0_1588_EVENT0_OUT 0x4092
#define MX28_PAD_ENET0_RXD3__ENET0_1588_EVENT0_IN 0x40a2
#define MX28_PAD_ENET0_TXD2__ENET0_1588_EVENT1_OUT 0x40b2
#define MX28_PAD_ENET0_TXD3__ENET0_1588_EVENT1_IN 0x40c2
#define MX28_PAD_ENET0_RX_CLK__ENET0_1588_EVENT2_IN 0x40d2
#define MX28_PAD_ENET0_COL__ENET0_1588_EVENT3_OUT 0x40e2
#define MX28_PAD_ENET0_CRS__ENET0_1588_EVENT3_IN 0x40f2
#define MX28_PAD_GPMI_D00__GPIO_0_0 0x0003
#define MX28_PAD_GPMI_D01__GPIO_0_1 0x0013
#define MX28_PAD_GPMI_D02__GPIO_0_2 0x0023
#define MX28_PAD_GPMI_D03__GPIO_0_3 0x0033
#define MX28_PAD_GPMI_D04__GPIO_0_4 0x0043
#define MX28_PAD_GPMI_D05__GPIO_0_5 0x0053
#define MX28_PAD_GPMI_D06__GPIO_0_6 0x0063
#define MX28_PAD_GPMI_D07__GPIO_0_7 0x0073
#define MX28_PAD_GPMI_CE0N__GPIO_0_16 0x0103
#define MX28_PAD_GPMI_CE1N__GPIO_0_17 0x0113
#define MX28_PAD_GPMI_CE2N__GPIO_0_18 0x0123
#define MX28_PAD_GPMI_CE3N__GPIO_0_19 0x0133
#define MX28_PAD_GPMI_RDY0__GPIO_0_20 0x0143
#define MX28_PAD_GPMI_RDY1__GPIO_0_21 0x0153
#define MX28_PAD_GPMI_RDY2__GPIO_0_22 0x0163
#define MX28_PAD_GPMI_RDY3__GPIO_0_23 0x0173
#define MX28_PAD_GPMI_RDN__GPIO_0_24 0x0183
#define MX28_PAD_GPMI_WRN__GPIO_0_25 0x0193
#define MX28_PAD_GPMI_ALE__GPIO_0_26 0x01a3
#define MX28_PAD_GPMI_CLE__GPIO_0_27 0x01b3
#define MX28_PAD_GPMI_RESETN__GPIO_0_28 0x01c3
#define MX28_PAD_LCD_D00__GPIO_1_0 0x1003
#define MX28_PAD_LCD_D01__GPIO_1_1 0x1013
#define MX28_PAD_LCD_D02__GPIO_1_2 0x1023
#define MX28_PAD_LCD_D03__GPIO_1_3 0x1033
#define MX28_PAD_LCD_D04__GPIO_1_4 0x1043
#define MX28_PAD_LCD_D05__GPIO_1_5 0x1053
#define MX28_PAD_LCD_D06__GPIO_1_6 0x1063
#define MX28_PAD_LCD_D07__GPIO_1_7 0x1073
#define MX28_PAD_LCD_D08__GPIO_1_8 0x1083
#define MX28_PAD_LCD_D09__GPIO_1_9 0x1093
#define MX28_PAD_LCD_D10__GPIO_1_10 0x10a3
#define MX28_PAD_LCD_D11__GPIO_1_11 0x10b3
#define MX28_PAD_LCD_D12__GPIO_1_12 0x10c3
#define MX28_PAD_LCD_D13__GPIO_1_13 0x10d3
#define MX28_PAD_LCD_D14__GPIO_1_14 0x10e3
#define MX28_PAD_LCD_D15__GPIO_1_15 0x10f3
#define MX28_PAD_LCD_D16__GPIO_1_16 0x1103
#define MX28_PAD_LCD_D17__GPIO_1_17 0x1113
#define MX28_PAD_LCD_D18__GPIO_1_18 0x1123
#define MX28_PAD_LCD_D19__GPIO_1_19 0x1133
#define MX28_PAD_LCD_D20__GPIO_1_20 0x1143
#define MX28_PAD_LCD_D21__GPIO_1_21 0x1153
#define MX28_PAD_LCD_D22__GPIO_1_22 0x1163
#define MX28_PAD_LCD_D23__GPIO_1_23 0x1173
#define MX28_PAD_LCD_RD_E__GPIO_1_24 0x1183
#define MX28_PAD_LCD_WR_RWN__GPIO_1_25 0x1193
#define MX28_PAD_LCD_RS__GPIO_1_26 0x11a3
#define MX28_PAD_LCD_CS__GPIO_1_27 0x11b3
#define MX28_PAD_LCD_VSYNC__GPIO_1_28 0x11c3
#define MX28_PAD_LCD_HSYNC__GPIO_1_29 0x11d3
#define MX28_PAD_LCD_DOTCLK__GPIO_1_30 0x11e3
#define MX28_PAD_LCD_ENABLE__GPIO_1_31 0x11f3
#define MX28_PAD_SSP0_DATA0__GPIO_2_0 0x2003
#define MX28_PAD_SSP0_DATA1__GPIO_2_1 0x2013
#define MX28_PAD_SSP0_DATA2__GPIO_2_2 0x2023
#define MX28_PAD_SSP0_DATA3__GPIO_2_3 0x2033
#define MX28_PAD_SSP0_DATA4__GPIO_2_4 0x2043
#define MX28_PAD_SSP0_DATA5__GPIO_2_5 0x2053
#define MX28_PAD_SSP0_DATA6__GPIO_2_6 0x2063
#define MX28_PAD_SSP0_DATA7__GPIO_2_7 0x2073
#define MX28_PAD_SSP0_CMD__GPIO_2_8 0x2083
#define MX28_PAD_SSP0_DETECT__GPIO_2_9 0x2093
#define MX28_PAD_SSP0_SCK__GPIO_2_10 0x20a3
#define MX28_PAD_SSP1_SCK__GPIO_2_12 0x20c3
#define MX28_PAD_SSP1_CMD__GPIO_2_13 0x20d3
#define MX28_PAD_SSP1_DATA0__GPIO_2_14 0x20e3
#define MX28_PAD_SSP1_DATA3__GPIO_2_15 0x20f3
#define MX28_PAD_SSP2_SCK__GPIO_2_16 0x2103
#define MX28_PAD_SSP2_MOSI__GPIO_2_17 0x2113
#define MX28_PAD_SSP2_MISO__GPIO_2_18 0x2123
#define MX28_PAD_SSP2_SS0__GPIO_2_19 0x2133
#define MX28_PAD_SSP2_SS1__GPIO_2_20 0x2143
#define MX28_PAD_SSP2_SS2__GPIO_2_21 0x2153
#define MX28_PAD_SSP3_SCK__GPIO_2_24 0x2183
#define MX28_PAD_SSP3_MOSI__GPIO_2_25 0x2193
#define MX28_PAD_SSP3_MISO__GPIO_2_26 0x21a3
#define MX28_PAD_SSP3_SS0__GPIO_2_27 0x21b3
#define MX28_PAD_AUART0_RX__GPIO_3_0 0x3003
#define MX28_PAD_AUART0_TX__GPIO_3_1 0x3013
#define MX28_PAD_AUART0_CTS__GPIO_3_2 0x3023
#define MX28_PAD_AUART0_RTS__GPIO_3_3 0x3033
#define MX28_PAD_AUART1_RX__GPIO_3_4 0x3043
#define MX28_PAD_AUART1_TX__GPIO_3_5 0x3053
#define MX28_PAD_AUART1_CTS__GPIO_3_6 0x3063
#define MX28_PAD_AUART1_RTS__GPIO_3_7 0x3073
#define MX28_PAD_AUART2_RX__GPIO_3_8 0x3083
#define MX28_PAD_AUART2_TX__GPIO_3_9 0x3093
#define MX28_PAD_AUART2_CTS__GPIO_3_10 0x30a3
#define MX28_PAD_AUART2_RTS__GPIO_3_11 0x30b3
#define MX28_PAD_AUART3_RX__GPIO_3_12 0x30c3
#define MX28_PAD_AUART3_TX__GPIO_3_13 0x30d3
#define MX28_PAD_AUART3_CTS__GPIO_3_14 0x30e3
#define MX28_PAD_AUART3_RTS__GPIO_3_15 0x30f3
#define MX28_PAD_PWM0__GPIO_3_16 0x3103
#define MX28_PAD_PWM1__GPIO_3_17 0x3113
#define MX28_PAD_PWM2__GPIO_3_18 0x3123
#define MX28_PAD_SAIF0_MCLK__GPIO_3_20 0x3143
#define MX28_PAD_SAIF0_LRCLK__GPIO_3_21 0x3153
#define MX28_PAD_SAIF0_BITCLK__GPIO_3_22 0x3163
#define MX28_PAD_SAIF0_SDATA0__GPIO_3_23 0x3173
#define MX28_PAD_I2C0_SCL__GPIO_3_24 0x3183
#define MX28_PAD_I2C0_SDA__GPIO_3_25 0x3193
#define MX28_PAD_SAIF1_SDATA0__GPIO_3_26 0x31a3
#define MX28_PAD_SPDIF__GPIO_3_27 0x31b3
#define MX28_PAD_PWM3__GPIO_3_28 0x31c3
#define MX28_PAD_PWM4__GPIO_3_29 0x31d3
#define MX28_PAD_LCD_RESET__GPIO_3_30 0x31e3
#define MX28_PAD_ENET0_MDC__GPIO_4_0 0x4003
#define MX28_PAD_ENET0_MDIO__GPIO_4_1 0x4013
#define MX28_PAD_ENET0_RX_EN__GPIO_4_2 0x4023
#define MX28_PAD_ENET0_RXD0__GPIO_4_3 0x4033
#define MX28_PAD_ENET0_RXD1__GPIO_4_4 0x4043
#define MX28_PAD_ENET0_TX_CLK__GPIO_4_5 0x4053
#define MX28_PAD_ENET0_TX_EN__GPIO_4_6 0x4063
#define MX28_PAD_ENET0_TXD0__GPIO_4_7 0x4073
#define MX28_PAD_ENET0_TXD1__GPIO_4_8 0x4083
#define MX28_PAD_ENET0_RXD2__GPIO_4_9 0x4093
#define MX28_PAD_ENET0_RXD3__GPIO_4_10 0x40a3
#define MX28_PAD_ENET0_TXD2__GPIO_4_11 0x40b3
#define MX28_PAD_ENET0_TXD3__GPIO_4_12 0x40c3
#define MX28_PAD_ENET0_RX_CLK__GPIO_4_13 0x40d3
#define MX28_PAD_ENET0_COL__GPIO_4_14 0x40e3
#define MX28_PAD_ENET0_CRS__GPIO_4_15 0x40f3
#define MX28_PAD_ENET_CLK__GPIO_4_16 0x4103
#define MX28_PAD_JTAG_RTCK__GPIO_4_20 0x4143
#endif /* __DT_BINDINGS_MX28_PINCTRL_H__ */

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@@ -1,768 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*/
#ifndef __DTS_IMX51_PINFUNC_H
#define __DTS_IMX51_PINFUNC_H
/*
* The pin function ID is a tuple of
* <mux_reg conf_reg input_reg mux_mode input_val>
*/
#define MX51_PAD_EIM_D16__AUD4_RXFS 0x05c 0x3f0 0x000 0x5 0x0
#define MX51_PAD_EIM_D16__AUD5_TXD 0x05c 0x3f0 0x8d8 0x7 0x0
#define MX51_PAD_EIM_D16__EIM_D16 0x05c 0x3f0 0x000 0x0 0x0
#define MX51_PAD_EIM_D16__GPIO2_0 0x05c 0x3f0 0x000 0x1 0x0
#define MX51_PAD_EIM_D16__I2C1_SDA 0x05c 0x3f0 0x9b4 0x4 0x0
#define MX51_PAD_EIM_D16__UART2_CTS 0x05c 0x3f0 0x000 0x3 0x0
#define MX51_PAD_EIM_D16__USBH2_DATA0 0x05c 0x3f0 0x000 0x2 0x0
#define MX51_PAD_EIM_D17__AUD5_RXD 0x060 0x3f4 0x8d4 0x7 0x0
#define MX51_PAD_EIM_D17__EIM_D17 0x060 0x3f4 0x000 0x0 0x0
#define MX51_PAD_EIM_D17__GPIO2_1 0x060 0x3f4 0x000 0x1 0x0
#define MX51_PAD_EIM_D17__UART2_RXD 0x060 0x3f4 0x9ec 0x3 0x0
#define MX51_PAD_EIM_D17__UART3_CTS 0x060 0x3f4 0x000 0x4 0x0
#define MX51_PAD_EIM_D17__USBH2_DATA1 0x060 0x3f4 0x000 0x2 0x0
#define MX51_PAD_EIM_D18__AUD5_TXC 0x064 0x3f8 0x8e4 0x7 0x0
#define MX51_PAD_EIM_D18__EIM_D18 0x064 0x3f8 0x000 0x0 0x0
#define MX51_PAD_EIM_D18__GPIO2_2 0x064 0x3f8 0x000 0x1 0x0
#define MX51_PAD_EIM_D18__UART2_TXD 0x064 0x3f8 0x000 0x3 0x0
#define MX51_PAD_EIM_D18__UART3_RTS 0x064 0x3f8 0x9f0 0x4 0x1
#define MX51_PAD_EIM_D18__USBH2_DATA2 0x064 0x3f8 0x000 0x2 0x0
#define MX51_PAD_EIM_D19__AUD4_RXC 0x068 0x3fc 0x000 0x5 0x0
#define MX51_PAD_EIM_D19__AUD5_TXFS 0x068 0x3fc 0x8e8 0x7 0x0
#define MX51_PAD_EIM_D19__EIM_D19 0x068 0x3fc 0x000 0x0 0x0
#define MX51_PAD_EIM_D19__GPIO2_3 0x068 0x3fc 0x000 0x1 0x0
#define MX51_PAD_EIM_D19__I2C1_SCL 0x068 0x3fc 0x9b0 0x4 0x0
#define MX51_PAD_EIM_D19__UART2_RTS 0x068 0x3fc 0x9e8 0x3 0x1
#define MX51_PAD_EIM_D19__USBH2_DATA3 0x068 0x3fc 0x000 0x2 0x0
#define MX51_PAD_EIM_D20__AUD4_TXD 0x06c 0x400 0x8c8 0x5 0x0
#define MX51_PAD_EIM_D20__EIM_D20 0x06c 0x400 0x000 0x0 0x0
#define MX51_PAD_EIM_D20__GPIO2_4 0x06c 0x400 0x000 0x1 0x0
#define MX51_PAD_EIM_D20__SRTC_ALARM_DEB 0x06c 0x400 0x000 0x4 0x0
#define MX51_PAD_EIM_D20__USBH2_DATA4 0x06c 0x400 0x000 0x2 0x0
#define MX51_PAD_EIM_D21__AUD4_RXD 0x070 0x404 0x8c4 0x5 0x0
#define MX51_PAD_EIM_D21__EIM_D21 0x070 0x404 0x000 0x0 0x0
#define MX51_PAD_EIM_D21__GPIO2_5 0x070 0x404 0x000 0x1 0x0
#define MX51_PAD_EIM_D21__SRTC_ALARM_DEB 0x070 0x404 0x000 0x3 0x0
#define MX51_PAD_EIM_D21__USBH2_DATA5 0x070 0x404 0x000 0x2 0x0
#define MX51_PAD_EIM_D22__AUD4_TXC 0x074 0x408 0x8cc 0x5 0x0
#define MX51_PAD_EIM_D22__EIM_D22 0x074 0x408 0x000 0x0 0x0
#define MX51_PAD_EIM_D22__GPIO2_6 0x074 0x408 0x000 0x1 0x0
#define MX51_PAD_EIM_D22__USBH2_DATA6 0x074 0x408 0x000 0x2 0x0
#define MX51_PAD_EIM_D23__AUD4_TXFS 0x078 0x40c 0x8d0 0x5 0x0
#define MX51_PAD_EIM_D23__EIM_D23 0x078 0x40c 0x000 0x0 0x0
#define MX51_PAD_EIM_D23__GPIO2_7 0x078 0x40c 0x000 0x1 0x0
#define MX51_PAD_EIM_D23__SPDIF_OUT1 0x078 0x40c 0x000 0x4 0x0
#define MX51_PAD_EIM_D23__USBH2_DATA7 0x078 0x40c 0x000 0x2 0x0
#define MX51_PAD_EIM_D24__AUD6_RXFS 0x07c 0x410 0x8f8 0x5 0x0
#define MX51_PAD_EIM_D24__EIM_D24 0x07c 0x410 0x000 0x0 0x0
#define MX51_PAD_EIM_D24__GPIO2_8 0x07c 0x410 0x000 0x1 0x0
#define MX51_PAD_EIM_D24__I2C2_SDA 0x07c 0x410 0x9bc 0x4 0x0
#define MX51_PAD_EIM_D24__UART3_CTS 0x07c 0x410 0x000 0x3 0x0
#define MX51_PAD_EIM_D24__USBOTG_DATA0 0x07c 0x410 0x000 0x2 0x0
#define MX51_PAD_EIM_D25__EIM_D25 0x080 0x414 0x000 0x0 0x0
#define MX51_PAD_EIM_D25__KEY_COL6 0x080 0x414 0x9c8 0x1 0x0
#define MX51_PAD_EIM_D25__UART2_CTS 0x080 0x414 0x000 0x4 0x0
#define MX51_PAD_EIM_D25__UART3_RXD 0x080 0x414 0x9f4 0x3 0x0
#define MX51_PAD_EIM_D25__USBOTG_DATA1 0x080 0x414 0x000 0x2 0x0
#define MX51_PAD_EIM_D26__EIM_D26 0x084 0x418 0x000 0x0 0x0
#define MX51_PAD_EIM_D26__KEY_COL7 0x084 0x418 0x9cc 0x1 0x0
#define MX51_PAD_EIM_D26__UART2_RTS 0x084 0x418 0x9e8 0x4 0x3
#define MX51_PAD_EIM_D26__UART3_TXD 0x084 0x418 0x000 0x3 0x0
#define MX51_PAD_EIM_D26__USBOTG_DATA2 0x084 0x418 0x000 0x2 0x0
#define MX51_PAD_EIM_D27__AUD6_RXC 0x088 0x41c 0x8f4 0x5 0x0
#define MX51_PAD_EIM_D27__EIM_D27 0x088 0x41c 0x000 0x0 0x0
#define MX51_PAD_EIM_D27__GPIO2_9 0x088 0x41c 0x000 0x1 0x0
#define MX51_PAD_EIM_D27__I2C2_SCL 0x088 0x41c 0x9b8 0x4 0x0
#define MX51_PAD_EIM_D27__UART3_RTS 0x088 0x41c 0x9f0 0x3 0x3
#define MX51_PAD_EIM_D27__USBOTG_DATA3 0x088 0x41c 0x000 0x2 0x0
#define MX51_PAD_EIM_D28__AUD6_TXD 0x08c 0x420 0x8f0 0x5 0x0
#define MX51_PAD_EIM_D28__EIM_D28 0x08c 0x420 0x000 0x0 0x0
#define MX51_PAD_EIM_D28__KEY_ROW4 0x08c 0x420 0x9d0 0x1 0x0
#define MX51_PAD_EIM_D28__USBOTG_DATA4 0x08c 0x420 0x000 0x2 0x0
#define MX51_PAD_EIM_D29__AUD6_RXD 0x090 0x424 0x8ec 0x5 0x0
#define MX51_PAD_EIM_D29__EIM_D29 0x090 0x424 0x000 0x0 0x0
#define MX51_PAD_EIM_D29__KEY_ROW5 0x090 0x424 0x9d4 0x1 0x0
#define MX51_PAD_EIM_D29__USBOTG_DATA5 0x090 0x424 0x000 0x2 0x0
#define MX51_PAD_EIM_D30__AUD6_TXC 0x094 0x428 0x8fc 0x5 0x0
#define MX51_PAD_EIM_D30__EIM_D30 0x094 0x428 0x000 0x0 0x0
#define MX51_PAD_EIM_D30__KEY_ROW6 0x094 0x428 0x9d8 0x1 0x0
#define MX51_PAD_EIM_D30__USBOTG_DATA6 0x094 0x428 0x000 0x2 0x0
#define MX51_PAD_EIM_D31__AUD6_TXFS 0x098 0x42c 0x900 0x5 0x0
#define MX51_PAD_EIM_D31__EIM_D31 0x098 0x42c 0x000 0x0 0x0
#define MX51_PAD_EIM_D31__KEY_ROW7 0x098 0x42c 0x9dc 0x1 0x0
#define MX51_PAD_EIM_D31__USBOTG_DATA7 0x098 0x42c 0x000 0x2 0x0
#define MX51_PAD_EIM_A16__EIM_A16 0x09c 0x430 0x000 0x0 0x0
#define MX51_PAD_EIM_A16__GPIO2_10 0x09c 0x430 0x000 0x1 0x0
#define MX51_PAD_EIM_A16__OSC_FREQ_SEL0 0x09c 0x430 0x000 0x7 0x0
#define MX51_PAD_EIM_A17__EIM_A17 0x0a0 0x434 0x000 0x0 0x0
#define MX51_PAD_EIM_A17__GPIO2_11 0x0a0 0x434 0x000 0x1 0x0
#define MX51_PAD_EIM_A17__OSC_FREQ_SEL1 0x0a0 0x434 0x000 0x7 0x0
#define MX51_PAD_EIM_A18__BOOT_LPB0 0x0a4 0x438 0x000 0x7 0x0
#define MX51_PAD_EIM_A18__EIM_A18 0x0a4 0x438 0x000 0x0 0x0
#define MX51_PAD_EIM_A18__GPIO2_12 0x0a4 0x438 0x000 0x1 0x0
#define MX51_PAD_EIM_A19__BOOT_LPB1 0x0a8 0x43c 0x000 0x7 0x0
#define MX51_PAD_EIM_A19__EIM_A19 0x0a8 0x43c 0x000 0x0 0x0
#define MX51_PAD_EIM_A19__GPIO2_13 0x0a8 0x43c 0x000 0x1 0x0
#define MX51_PAD_EIM_A20__BOOT_UART_SRC0 0x0ac 0x440 0x000 0x7 0x0
#define MX51_PAD_EIM_A20__EIM_A20 0x0ac 0x440 0x000 0x0 0x0
#define MX51_PAD_EIM_A20__GPIO2_14 0x0ac 0x440 0x000 0x1 0x0
#define MX51_PAD_EIM_A21__BOOT_UART_SRC1 0x0b0 0x444 0x000 0x7 0x0
#define MX51_PAD_EIM_A21__EIM_A21 0x0b0 0x444 0x000 0x0 0x0
#define MX51_PAD_EIM_A21__GPIO2_15 0x0b0 0x444 0x000 0x1 0x0
#define MX51_PAD_EIM_A22__EIM_A22 0x0b4 0x448 0x000 0x0 0x0
#define MX51_PAD_EIM_A22__GPIO2_16 0x0b4 0x448 0x000 0x1 0x0
#define MX51_PAD_EIM_A23__BOOT_HPN_EN 0x0b8 0x44c 0x000 0x7 0x0
#define MX51_PAD_EIM_A23__EIM_A23 0x0b8 0x44c 0x000 0x0 0x0
#define MX51_PAD_EIM_A23__GPIO2_17 0x0b8 0x44c 0x000 0x1 0x0
#define MX51_PAD_EIM_A24__EIM_A24 0x0bc 0x450 0x000 0x0 0x0
#define MX51_PAD_EIM_A24__GPIO2_18 0x0bc 0x450 0x000 0x1 0x0
#define MX51_PAD_EIM_A24__USBH2_CLK 0x0bc 0x450 0x000 0x2 0x0
#define MX51_PAD_EIM_A25__DISP1_PIN4 0x0c0 0x454 0x000 0x6 0x0
#define MX51_PAD_EIM_A25__EIM_A25 0x0c0 0x454 0x000 0x0 0x0
#define MX51_PAD_EIM_A25__GPIO2_19 0x0c0 0x454 0x000 0x1 0x0
#define MX51_PAD_EIM_A25__USBH2_DIR 0x0c0 0x454 0x000 0x2 0x0
#define MX51_PAD_EIM_A26__CSI1_DATA_EN 0x0c4 0x458 0x9a0 0x5 0x0
#define MX51_PAD_EIM_A26__DISP2_EXT_CLK 0x0c4 0x458 0x908 0x6 0x0
#define MX51_PAD_EIM_A26__EIM_A26 0x0c4 0x458 0x000 0x0 0x0
#define MX51_PAD_EIM_A26__GPIO2_20 0x0c4 0x458 0x000 0x1 0x0
#define MX51_PAD_EIM_A26__USBH2_STP 0x0c4 0x458 0x000 0x2 0x0
#define MX51_PAD_EIM_A27__CSI2_DATA_EN 0x0c8 0x45c 0x99c 0x5 0x0
#define MX51_PAD_EIM_A27__DISP1_PIN1 0x0c8 0x45c 0x9a4 0x6 0x0
#define MX51_PAD_EIM_A27__EIM_A27 0x0c8 0x45c 0x000 0x0 0x0
#define MX51_PAD_EIM_A27__GPIO2_21 0x0c8 0x45c 0x000 0x1 0x0
#define MX51_PAD_EIM_A27__USBH2_NXT 0x0c8 0x45c 0x000 0x2 0x0
#define MX51_PAD_EIM_EB0__EIM_EB0 0x0cc 0x460 0x000 0x0 0x0
#define MX51_PAD_EIM_EB1__EIM_EB1 0x0d0 0x464 0x000 0x0 0x0
#define MX51_PAD_EIM_EB2__AUD5_RXFS 0x0d4 0x468 0x8e0 0x6 0x0
#define MX51_PAD_EIM_EB2__CSI1_D2 0x0d4 0x468 0x000 0x5 0x0
#define MX51_PAD_EIM_EB2__EIM_EB2 0x0d4 0x468 0x000 0x0 0x0
#define MX51_PAD_EIM_EB2__FEC_MDIO 0x0d4 0x468 0x954 0x3 0x0
#define MX51_PAD_EIM_EB2__GPIO2_22 0x0d4 0x468 0x000 0x1 0x0
#define MX51_PAD_EIM_EB2__GPT_CMPOUT1 0x0d4 0x468 0x000 0x7 0x0
#define MX51_PAD_EIM_EB3__AUD5_RXC 0x0d8 0x46c 0x8dc 0x6 0x0
#define MX51_PAD_EIM_EB3__CSI1_D3 0x0d8 0x46c 0x000 0x5 0x0
#define MX51_PAD_EIM_EB3__EIM_EB3 0x0d8 0x46c 0x000 0x0 0x0
#define MX51_PAD_EIM_EB3__FEC_RDATA1 0x0d8 0x46c 0x95c 0x3 0x0
#define MX51_PAD_EIM_EB3__GPIO2_23 0x0d8 0x46c 0x000 0x1 0x0
#define MX51_PAD_EIM_EB3__GPT_CMPOUT2 0x0d8 0x46c 0x000 0x7 0x0
#define MX51_PAD_EIM_OE__EIM_OE 0x0dc 0x470 0x000 0x0 0x0
#define MX51_PAD_EIM_OE__GPIO2_24 0x0dc 0x470 0x000 0x1 0x0
#define MX51_PAD_EIM_CS0__EIM_CS0 0x0e0 0x474 0x000 0x0 0x0
#define MX51_PAD_EIM_CS0__GPIO2_25 0x0e0 0x474 0x000 0x1 0x0
#define MX51_PAD_EIM_CS1__EIM_CS1 0x0e4 0x478 0x000 0x0 0x0
#define MX51_PAD_EIM_CS1__GPIO2_26 0x0e4 0x478 0x000 0x1 0x0
#define MX51_PAD_EIM_CS2__AUD5_TXD 0x0e8 0x47c 0x8d8 0x6 0x1
#define MX51_PAD_EIM_CS2__CSI1_D4 0x0e8 0x47c 0x000 0x5 0x0
#define MX51_PAD_EIM_CS2__EIM_CS2 0x0e8 0x47c 0x000 0x0 0x0
#define MX51_PAD_EIM_CS2__FEC_RDATA2 0x0e8 0x47c 0x960 0x3 0x0
#define MX51_PAD_EIM_CS2__GPIO2_27 0x0e8 0x47c 0x000 0x1 0x0
#define MX51_PAD_EIM_CS2__USBOTG_STP 0x0e8 0x47c 0x000 0x2 0x0
#define MX51_PAD_EIM_CS3__AUD5_RXD 0x0ec 0x480 0x8d4 0x6 0x1
#define MX51_PAD_EIM_CS3__CSI1_D5 0x0ec 0x480 0x000 0x5 0x0
#define MX51_PAD_EIM_CS3__EIM_CS3 0x0ec 0x480 0x000 0x0 0x0
#define MX51_PAD_EIM_CS3__FEC_RDATA3 0x0ec 0x480 0x964 0x3 0x0
#define MX51_PAD_EIM_CS3__GPIO2_28 0x0ec 0x480 0x000 0x1 0x0
#define MX51_PAD_EIM_CS3__USBOTG_NXT 0x0ec 0x480 0x000 0x2 0x0
#define MX51_PAD_EIM_CS4__AUD5_TXC 0x0f0 0x484 0x8e4 0x6 0x1
#define MX51_PAD_EIM_CS4__CSI1_D6 0x0f0 0x484 0x000 0x5 0x0
#define MX51_PAD_EIM_CS4__EIM_CS4 0x0f0 0x484 0x000 0x0 0x0
#define MX51_PAD_EIM_CS4__FEC_RX_ER 0x0f0 0x484 0x970 0x3 0x0
#define MX51_PAD_EIM_CS4__GPIO2_29 0x0f0 0x484 0x000 0x1 0x0
#define MX51_PAD_EIM_CS4__USBOTG_CLK 0x0f0 0x484 0x000 0x2 0x0
#define MX51_PAD_EIM_CS5__AUD5_TXFS 0x0f4 0x488 0x8e8 0x6 0x1
#define MX51_PAD_EIM_CS5__CSI1_D7 0x0f4 0x488 0x000 0x5 0x0
#define MX51_PAD_EIM_CS5__DISP1_EXT_CLK 0x0f4 0x488 0x904 0x4 0x0
#define MX51_PAD_EIM_CS5__EIM_CS5 0x0f4 0x488 0x000 0x0 0x0
#define MX51_PAD_EIM_CS5__FEC_CRS 0x0f4 0x488 0x950 0x3 0x0
#define MX51_PAD_EIM_CS5__GPIO2_30 0x0f4 0x488 0x000 0x1 0x0
#define MX51_PAD_EIM_CS5__USBOTG_DIR 0x0f4 0x488 0x000 0x2 0x0
#define MX51_PAD_EIM_DTACK__EIM_DTACK 0x0f8 0x48c 0x000 0x0 0x0
#define MX51_PAD_EIM_DTACK__GPIO2_31 0x0f8 0x48c 0x000 0x1 0x0
#define MX51_PAD_EIM_LBA__EIM_LBA 0x0fc 0x494 0x000 0x0 0x0
#define MX51_PAD_EIM_LBA__GPIO3_1 0x0fc 0x494 0x978 0x1 0x0
#define MX51_PAD_EIM_CRE__EIM_CRE 0x100 0x4a0 0x000 0x0 0x0
#define MX51_PAD_EIM_CRE__GPIO3_2 0x100 0x4a0 0x97c 0x1 0x0
#define MX51_PAD_DRAM_CS1__DRAM_CS1 0x104 0x4d0 0x000 0x0 0x0
#define MX51_PAD_NANDF_WE_B__GPIO3_3 0x108 0x4e4 0x980 0x3 0x0
#define MX51_PAD_NANDF_WE_B__NANDF_WE_B 0x108 0x4e4 0x000 0x0 0x0
#define MX51_PAD_NANDF_WE_B__PATA_DIOW 0x108 0x4e4 0x000 0x1 0x0
#define MX51_PAD_NANDF_WE_B__SD3_DATA0 0x108 0x4e4 0x93c 0x2 0x0
#define MX51_PAD_NANDF_RE_B__GPIO3_4 0x10c 0x4e8 0x984 0x3 0x0
#define MX51_PAD_NANDF_RE_B__NANDF_RE_B 0x10c 0x4e8 0x000 0x0 0x0
#define MX51_PAD_NANDF_RE_B__PATA_DIOR 0x10c 0x4e8 0x000 0x1 0x0
#define MX51_PAD_NANDF_RE_B__SD3_DATA1 0x10c 0x4e8 0x940 0x2 0x0
#define MX51_PAD_NANDF_ALE__GPIO3_5 0x110 0x4ec 0x988 0x3 0x0
#define MX51_PAD_NANDF_ALE__NANDF_ALE 0x110 0x4ec 0x000 0x0 0x0
#define MX51_PAD_NANDF_ALE__PATA_BUFFER_EN 0x110 0x4ec 0x000 0x1 0x0
#define MX51_PAD_NANDF_CLE__GPIO3_6 0x114 0x4f0 0x98c 0x3 0x0
#define MX51_PAD_NANDF_CLE__NANDF_CLE 0x114 0x4f0 0x000 0x0 0x0
#define MX51_PAD_NANDF_CLE__PATA_RESET_B 0x114 0x4f0 0x000 0x1 0x0
#define MX51_PAD_NANDF_WP_B__GPIO3_7 0x118 0x4f4 0x990 0x3 0x0
#define MX51_PAD_NANDF_WP_B__NANDF_WP_B 0x118 0x4f4 0x000 0x0 0x0
#define MX51_PAD_NANDF_WP_B__PATA_DMACK 0x118 0x4f4 0x000 0x1 0x0
#define MX51_PAD_NANDF_WP_B__SD3_DATA2 0x118 0x4f4 0x944 0x2 0x0
#define MX51_PAD_NANDF_RB0__ECSPI2_SS1 0x11c 0x4f8 0x930 0x5 0x0
#define MX51_PAD_NANDF_RB0__GPIO3_8 0x11c 0x4f8 0x994 0x3 0x0
#define MX51_PAD_NANDF_RB0__NANDF_RB0 0x11c 0x4f8 0x000 0x0 0x0
#define MX51_PAD_NANDF_RB0__PATA_DMARQ 0x11c 0x4f8 0x000 0x1 0x0
#define MX51_PAD_NANDF_RB0__SD3_DATA3 0x11c 0x4f8 0x948 0x2 0x0
#define MX51_PAD_NANDF_RB1__CSPI_MOSI 0x120 0x4fc 0x91c 0x6 0x0
#define MX51_PAD_NANDF_RB1__ECSPI2_RDY 0x120 0x4fc 0x000 0x2 0x0
#define MX51_PAD_NANDF_RB1__GPIO3_9 0x120 0x4fc 0x000 0x3 0x0
#define MX51_PAD_NANDF_RB1__NANDF_RB1 0x120 0x4fc 0x000 0x0 0x0
#define MX51_PAD_NANDF_RB1__PATA_IORDY 0x120 0x4fc 0x000 0x1 0x0
#define MX51_PAD_NANDF_RB1__SD4_CMD 0x120 0x4fc 0x000 0x5 0x0
#define MX51_PAD_NANDF_RB2__DISP2_WAIT 0x124 0x500 0x9a8 0x5 0x0
#define MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x124 0x500 0x000 0x2 0x0
#define MX51_PAD_NANDF_RB2__FEC_COL 0x124 0x500 0x94c 0x1 0x0
#define MX51_PAD_NANDF_RB2__GPIO3_10 0x124 0x500 0x000 0x3 0x0
#define MX51_PAD_NANDF_RB2__NANDF_RB2 0x124 0x500 0x000 0x0 0x0
#define MX51_PAD_NANDF_RB2__USBH3_H3_DP 0x124 0x500 0x000 0x7 0x0
#define MX51_PAD_NANDF_RB2__USBH3_NXT 0x124 0x500 0xa20 0x6 0x0
#define MX51_PAD_NANDF_RB3__DISP1_WAIT 0x128 0x504 0x000 0x5 0x0
#define MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x128 0x504 0x000 0x2 0x0
#define MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x128 0x504 0x968 0x1 0x0
#define MX51_PAD_NANDF_RB3__GPIO3_11 0x128 0x504 0x000 0x3 0x0
#define MX51_PAD_NANDF_RB3__NANDF_RB3 0x128 0x504 0x000 0x0 0x0
#define MX51_PAD_NANDF_RB3__USBH3_CLK 0x128 0x504 0x9f8 0x6 0x0
#define MX51_PAD_NANDF_RB3__USBH3_H3_DM 0x128 0x504 0x000 0x7 0x0
#define MX51_PAD_GPIO_NAND__GPIO_NAND 0x12c 0x514 0x998 0x0 0x0
#define MX51_PAD_GPIO_NAND__PATA_INTRQ 0x12c 0x514 0x000 0x1 0x0
#define MX51_PAD_NANDF_CS0__GPIO3_16 0x130 0x518 0x000 0x3 0x0
#define MX51_PAD_NANDF_CS0__NANDF_CS0 0x130 0x518 0x000 0x0 0x0
#define MX51_PAD_NANDF_CS1__GPIO3_17 0x134 0x51c 0x000 0x3 0x0
#define MX51_PAD_NANDF_CS1__NANDF_CS1 0x134 0x51c 0x000 0x0 0x0
#define MX51_PAD_NANDF_CS2__CSPI_SCLK 0x138 0x520 0x914 0x6 0x0
#define MX51_PAD_NANDF_CS2__FEC_TX_ER 0x138 0x520 0x000 0x2 0x0
#define MX51_PAD_NANDF_CS2__GPIO3_18 0x138 0x520 0x000 0x3 0x0
#define MX51_PAD_NANDF_CS2__NANDF_CS2 0x138 0x520 0x000 0x0 0x0
#define MX51_PAD_NANDF_CS2__PATA_CS_0 0x138 0x520 0x000 0x1 0x0
#define MX51_PAD_NANDF_CS2__SD4_CLK 0x138 0x520 0x000 0x5 0x0
#define MX51_PAD_NANDF_CS2__USBH3_H1_DP 0x138 0x520 0x000 0x7 0x0
#define MX51_PAD_NANDF_CS3__FEC_MDC 0x13c 0x524 0x000 0x2 0x0
#define MX51_PAD_NANDF_CS3__GPIO3_19 0x13c 0x524 0x000 0x3 0x0
#define MX51_PAD_NANDF_CS3__NANDF_CS3 0x13c 0x524 0x000 0x0 0x0
#define MX51_PAD_NANDF_CS3__PATA_CS_1 0x13c 0x524 0x000 0x1 0x0
#define MX51_PAD_NANDF_CS3__SD4_DAT0 0x13c 0x524 0x000 0x5 0x0
#define MX51_PAD_NANDF_CS3__USBH3_H1_DM 0x13c 0x524 0x000 0x7 0x0
#define MX51_PAD_NANDF_CS4__FEC_TDATA1 0x140 0x528 0x000 0x2 0x0
#define MX51_PAD_NANDF_CS4__GPIO3_20 0x140 0x528 0x000 0x3 0x0
#define MX51_PAD_NANDF_CS4__NANDF_CS4 0x140 0x528 0x000 0x0 0x0
#define MX51_PAD_NANDF_CS4__PATA_DA_0 0x140 0x528 0x000 0x1 0x0
#define MX51_PAD_NANDF_CS4__SD4_DAT1 0x140 0x528 0x000 0x5 0x0
#define MX51_PAD_NANDF_CS4__USBH3_STP 0x140 0x528 0xa24 0x7 0x0
#define MX51_PAD_NANDF_CS5__FEC_TDATA2 0x144 0x52c 0x000 0x2 0x0
#define MX51_PAD_NANDF_CS5__GPIO3_21 0x144 0x52c 0x000 0x3 0x0
#define MX51_PAD_NANDF_CS5__NANDF_CS5 0x144 0x52c 0x000 0x0 0x0
#define MX51_PAD_NANDF_CS5__PATA_DA_1 0x144 0x52c 0x000 0x1 0x0
#define MX51_PAD_NANDF_CS5__SD4_DAT2 0x144 0x52c 0x000 0x5 0x0
#define MX51_PAD_NANDF_CS5__USBH3_DIR 0x144 0x52c 0xa1c 0x7 0x0
#define MX51_PAD_NANDF_CS6__CSPI_SS3 0x148 0x530 0x928 0x7 0x0
#define MX51_PAD_NANDF_CS6__FEC_TDATA3 0x148 0x530 0x000 0x2 0x0
#define MX51_PAD_NANDF_CS6__GPIO3_22 0x148 0x530 0x000 0x3 0x0
#define MX51_PAD_NANDF_CS6__NANDF_CS6 0x148 0x530 0x000 0x0 0x0
#define MX51_PAD_NANDF_CS6__PATA_DA_2 0x148 0x530 0x000 0x1 0x0
#define MX51_PAD_NANDF_CS6__SD4_DAT3 0x148 0x530 0x000 0x5 0x0
#define MX51_PAD_NANDF_CS7__FEC_TX_EN 0x14c 0x534 0x000 0x1 0x0
#define MX51_PAD_NANDF_CS7__GPIO3_23 0x14c 0x534 0x000 0x3 0x0
#define MX51_PAD_NANDF_CS7__NANDF_CS7 0x14c 0x534 0x000 0x0 0x0
#define MX51_PAD_NANDF_CS7__SD3_CLK 0x14c 0x534 0x000 0x5 0x0
#define MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 0x150 0x538 0x000 0x2 0x0
#define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x150 0x538 0x974 0x1 0x0
#define MX51_PAD_NANDF_RDY_INT__GPIO3_24 0x150 0x538 0x000 0x3 0x0
#define MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT 0x150 0x538 0x938 0x0 0x0
#define MX51_PAD_NANDF_RDY_INT__SD3_CMD 0x150 0x538 0x000 0x5 0x0
#define MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x154 0x53c 0x000 0x2 0x0
#define MX51_PAD_NANDF_D15__GPIO3_25 0x154 0x53c 0x000 0x3 0x0
#define MX51_PAD_NANDF_D15__NANDF_D15 0x154 0x53c 0x000 0x0 0x0
#define MX51_PAD_NANDF_D15__PATA_DATA15 0x154 0x53c 0x000 0x1 0x0
#define MX51_PAD_NANDF_D15__SD3_DAT7 0x154 0x53c 0x000 0x5 0x0
#define MX51_PAD_NANDF_D14__ECSPI2_SS3 0x158 0x540 0x934 0x2 0x0
#define MX51_PAD_NANDF_D14__GPIO3_26 0x158 0x540 0x000 0x3 0x0
#define MX51_PAD_NANDF_D14__NANDF_D14 0x158 0x540 0x000 0x0 0x0
#define MX51_PAD_NANDF_D14__PATA_DATA14 0x158 0x540 0x000 0x1 0x0
#define MX51_PAD_NANDF_D14__SD3_DAT6 0x158 0x540 0x000 0x5 0x0
#define MX51_PAD_NANDF_D13__ECSPI2_SS2 0x15c 0x544 0x000 0x2 0x0
#define MX51_PAD_NANDF_D13__GPIO3_27 0x15c 0x544 0x000 0x3 0x0
#define MX51_PAD_NANDF_D13__NANDF_D13 0x15c 0x544 0x000 0x0 0x0
#define MX51_PAD_NANDF_D13__PATA_DATA13 0x15c 0x544 0x000 0x1 0x0
#define MX51_PAD_NANDF_D13__SD3_DAT5 0x15c 0x544 0x000 0x5 0x0
#define MX51_PAD_NANDF_D12__ECSPI2_SS1 0x160 0x548 0x930 0x2 0x1
#define MX51_PAD_NANDF_D12__GPIO3_28 0x160 0x548 0x000 0x3 0x0
#define MX51_PAD_NANDF_D12__NANDF_D12 0x160 0x548 0x000 0x0 0x0
#define MX51_PAD_NANDF_D12__PATA_DATA12 0x160 0x548 0x000 0x1 0x0
#define MX51_PAD_NANDF_D12__SD3_DAT4 0x160 0x548 0x000 0x5 0x0
#define MX51_PAD_NANDF_D11__FEC_RX_DV 0x164 0x54c 0x96c 0x2 0x0
#define MX51_PAD_NANDF_D11__GPIO3_29 0x164 0x54c 0x000 0x3 0x0
#define MX51_PAD_NANDF_D11__NANDF_D11 0x164 0x54c 0x000 0x0 0x0
#define MX51_PAD_NANDF_D11__PATA_DATA11 0x164 0x54c 0x000 0x1 0x0
#define MX51_PAD_NANDF_D11__SD3_DATA3 0x164 0x54c 0x948 0x5 0x1
#define MX51_PAD_NANDF_D10__GPIO3_30 0x168 0x550 0x000 0x3 0x0
#define MX51_PAD_NANDF_D10__NANDF_D10 0x168 0x550 0x000 0x0 0x0
#define MX51_PAD_NANDF_D10__PATA_DATA10 0x168 0x550 0x000 0x1 0x0
#define MX51_PAD_NANDF_D10__SD3_DATA2 0x168 0x550 0x944 0x5 0x1
#define MX51_PAD_NANDF_D9__FEC_RDATA0 0x16c 0x554 0x958 0x2 0x0
#define MX51_PAD_NANDF_D9__GPIO3_31 0x16c 0x554 0x000 0x3 0x0
#define MX51_PAD_NANDF_D9__NANDF_D9 0x16c 0x554 0x000 0x0 0x0
#define MX51_PAD_NANDF_D9__PATA_DATA9 0x16c 0x554 0x000 0x1 0x0
#define MX51_PAD_NANDF_D9__SD3_DATA1 0x16c 0x554 0x940 0x5 0x1
#define MX51_PAD_NANDF_D8__FEC_TDATA0 0x170 0x558 0x000 0x2 0x0
#define MX51_PAD_NANDF_D8__GPIO4_0 0x170 0x558 0x000 0x3 0x0
#define MX51_PAD_NANDF_D8__NANDF_D8 0x170 0x558 0x000 0x0 0x0
#define MX51_PAD_NANDF_D8__PATA_DATA8 0x170 0x558 0x000 0x1 0x0
#define MX51_PAD_NANDF_D8__SD3_DATA0 0x170 0x558 0x93c 0x5 0x1
#define MX51_PAD_NANDF_D7__GPIO4_1 0x174 0x55c 0x000 0x3 0x0
#define MX51_PAD_NANDF_D7__NANDF_D7 0x174 0x55c 0x000 0x0 0x0
#define MX51_PAD_NANDF_D7__PATA_DATA7 0x174 0x55c 0x000 0x1 0x0
#define MX51_PAD_NANDF_D7__USBH3_DATA0 0x174 0x55c 0x9fc 0x5 0x0
#define MX51_PAD_NANDF_D6__GPIO4_2 0x178 0x560 0x000 0x3 0x0
#define MX51_PAD_NANDF_D6__NANDF_D6 0x178 0x560 0x000 0x0 0x0
#define MX51_PAD_NANDF_D6__PATA_DATA6 0x178 0x560 0x000 0x1 0x0
#define MX51_PAD_NANDF_D6__SD4_LCTL 0x178 0x560 0x000 0x2 0x0
#define MX51_PAD_NANDF_D6__USBH3_DATA1 0x178 0x560 0xa00 0x5 0x0
#define MX51_PAD_NANDF_D5__GPIO4_3 0x17c 0x564 0x000 0x3 0x0
#define MX51_PAD_NANDF_D5__NANDF_D5 0x17c 0x564 0x000 0x0 0x0
#define MX51_PAD_NANDF_D5__PATA_DATA5 0x17c 0x564 0x000 0x1 0x0
#define MX51_PAD_NANDF_D5__SD4_WP 0x17c 0x564 0x000 0x2 0x0
#define MX51_PAD_NANDF_D5__USBH3_DATA2 0x17c 0x564 0xa04 0x5 0x0
#define MX51_PAD_NANDF_D4__GPIO4_4 0x180 0x568 0x000 0x3 0x0
#define MX51_PAD_NANDF_D4__NANDF_D4 0x180 0x568 0x000 0x0 0x0
#define MX51_PAD_NANDF_D4__PATA_DATA4 0x180 0x568 0x000 0x1 0x0
#define MX51_PAD_NANDF_D4__SD4_CD 0x180 0x568 0x000 0x2 0x0
#define MX51_PAD_NANDF_D4__USBH3_DATA3 0x180 0x568 0xa08 0x5 0x0
#define MX51_PAD_NANDF_D3__GPIO4_5 0x184 0x56c 0x000 0x3 0x0
#define MX51_PAD_NANDF_D3__NANDF_D3 0x184 0x56c 0x000 0x0 0x0
#define MX51_PAD_NANDF_D3__PATA_DATA3 0x184 0x56c 0x000 0x1 0x0
#define MX51_PAD_NANDF_D3__SD4_DAT4 0x184 0x56c 0x000 0x2 0x0
#define MX51_PAD_NANDF_D3__USBH3_DATA4 0x184 0x56c 0xa0c 0x5 0x0
#define MX51_PAD_NANDF_D2__GPIO4_6 0x188 0x570 0x000 0x3 0x0
#define MX51_PAD_NANDF_D2__NANDF_D2 0x188 0x570 0x000 0x0 0x0
#define MX51_PAD_NANDF_D2__PATA_DATA2 0x188 0x570 0x000 0x1 0x0
#define MX51_PAD_NANDF_D2__SD4_DAT5 0x188 0x570 0x000 0x2 0x0
#define MX51_PAD_NANDF_D2__USBH3_DATA5 0x188 0x570 0xa10 0x5 0x0
#define MX51_PAD_NANDF_D1__GPIO4_7 0x18c 0x574 0x000 0x3 0x0
#define MX51_PAD_NANDF_D1__NANDF_D1 0x18c 0x574 0x000 0x0 0x0
#define MX51_PAD_NANDF_D1__PATA_DATA1 0x18c 0x574 0x000 0x1 0x0
#define MX51_PAD_NANDF_D1__SD4_DAT6 0x18c 0x574 0x000 0x2 0x0
#define MX51_PAD_NANDF_D1__USBH3_DATA6 0x18c 0x574 0xa14 0x5 0x0
#define MX51_PAD_NANDF_D0__GPIO4_8 0x190 0x578 0x000 0x3 0x0
#define MX51_PAD_NANDF_D0__NANDF_D0 0x190 0x578 0x000 0x0 0x0
#define MX51_PAD_NANDF_D0__PATA_DATA0 0x190 0x578 0x000 0x1 0x0
#define MX51_PAD_NANDF_D0__SD4_DAT7 0x190 0x578 0x000 0x2 0x0
#define MX51_PAD_NANDF_D0__USBH3_DATA7 0x190 0x578 0xa18 0x5 0x0
#define MX51_PAD_CSI1_D8__CSI1_D8 0x194 0x57c 0x000 0x0 0x0
#define MX51_PAD_CSI1_D8__GPIO3_12 0x194 0x57c 0x998 0x3 0x1
#define MX51_PAD_CSI1_D9__CSI1_D9 0x198 0x580 0x000 0x0 0x0
#define MX51_PAD_CSI1_D9__GPIO3_13 0x198 0x580 0x000 0x3 0x0
#define MX51_PAD_CSI1_D10__CSI1_D10 0x19c 0x584 0x000 0x0 0x0
#define MX51_PAD_CSI1_D11__CSI1_D11 0x1a0 0x588 0x000 0x0 0x0
#define MX51_PAD_CSI1_D12__CSI1_D12 0x1a4 0x58c 0x000 0x0 0x0
#define MX51_PAD_CSI1_D13__CSI1_D13 0x1a8 0x590 0x000 0x0 0x0
#define MX51_PAD_CSI1_D14__CSI1_D14 0x1ac 0x594 0x000 0x0 0x0
#define MX51_PAD_CSI1_D15__CSI1_D15 0x1b0 0x598 0x000 0x0 0x0
#define MX51_PAD_CSI1_D16__CSI1_D16 0x1b4 0x59c 0x000 0x0 0x0
#define MX51_PAD_CSI1_D17__CSI1_D17 0x1b8 0x5a0 0x000 0x0 0x0
#define MX51_PAD_CSI1_D18__CSI1_D18 0x1bc 0x5a4 0x000 0x0 0x0
#define MX51_PAD_CSI1_D19__CSI1_D19 0x1c0 0x5a8 0x000 0x0 0x0
#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC 0x1c4 0x5ac 0x000 0x0 0x0
#define MX51_PAD_CSI1_VSYNC__GPIO3_14 0x1c4 0x5ac 0x000 0x3 0x0
#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC 0x1c8 0x5b0 0x000 0x0 0x0
#define MX51_PAD_CSI1_HSYNC__GPIO3_15 0x1c8 0x5b0 0x000 0x3 0x0
#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK 0x000 0x5b4 0x000 0x0 0x0
#define MX51_PAD_CSI1_MCLK__CSI1_MCLK 0x000 0x5b8 0x000 0x0 0x0
#define MX51_PAD_CSI2_D12__CSI2_D12 0x1cc 0x5bc 0x000 0x0 0x0
#define MX51_PAD_CSI2_D12__GPIO4_9 0x1cc 0x5bc 0x000 0x3 0x0
#define MX51_PAD_CSI2_D13__CSI2_D13 0x1d0 0x5c0 0x000 0x0 0x0
#define MX51_PAD_CSI2_D13__GPIO4_10 0x1d0 0x5c0 0x000 0x3 0x0
#define MX51_PAD_CSI2_D14__CSI2_D14 0x1d4 0x5c4 0x000 0x0 0x0
#define MX51_PAD_CSI2_D15__CSI2_D15 0x1d8 0x5c8 0x000 0x0 0x0
#define MX51_PAD_CSI2_D16__CSI2_D16 0x1dc 0x5cc 0x000 0x0 0x0
#define MX51_PAD_CSI2_D17__CSI2_D17 0x1e0 0x5d0 0x000 0x0 0x0
#define MX51_PAD_CSI2_D18__CSI2_D18 0x1e4 0x5d4 0x000 0x0 0x0
#define MX51_PAD_CSI2_D18__GPIO4_11 0x1e4 0x5d4 0x000 0x3 0x0
#define MX51_PAD_CSI2_D19__CSI2_D19 0x1e8 0x5d8 0x000 0x0 0x0
#define MX51_PAD_CSI2_D19__GPIO4_12 0x1e8 0x5d8 0x000 0x3 0x0
#define MX51_PAD_CSI2_VSYNC__CSI2_VSYNC 0x1ec 0x5dc 0x000 0x0 0x0
#define MX51_PAD_CSI2_VSYNC__GPIO4_13 0x1ec 0x5dc 0x000 0x3 0x0
#define MX51_PAD_CSI2_HSYNC__CSI2_HSYNC 0x1f0 0x5e0 0x000 0x0 0x0
#define MX51_PAD_CSI2_HSYNC__GPIO4_14 0x1f0 0x5e0 0x000 0x3 0x0
#define MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK 0x1f4 0x5e4 0x000 0x0 0x0
#define MX51_PAD_CSI2_PIXCLK__GPIO4_15 0x1f4 0x5e4 0x000 0x3 0x0
#define MX51_PAD_I2C1_CLK__GPIO4_16 0x1f8 0x5e8 0x000 0x3 0x0
#define MX51_PAD_I2C1_CLK__I2C1_CLK 0x1f8 0x5e8 0x000 0x0 0x0
#define MX51_PAD_I2C1_DAT__GPIO4_17 0x1fc 0x5ec 0x000 0x3 0x0
#define MX51_PAD_I2C1_DAT__I2C1_DAT 0x1fc 0x5ec 0x000 0x0 0x0
#define MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x200 0x5f0 0x000 0x0 0x0
#define MX51_PAD_AUD3_BB_TXD__GPIO4_18 0x200 0x5f0 0x000 0x3 0x0
#define MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x204 0x5f4 0x000 0x0 0x0
#define MX51_PAD_AUD3_BB_RXD__GPIO4_19 0x204 0x5f4 0x000 0x3 0x0
#define MX51_PAD_AUD3_BB_RXD__UART3_RXD 0x204 0x5f4 0x9f4 0x1 0x2
#define MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x208 0x5f8 0x000 0x0 0x0
#define MX51_PAD_AUD3_BB_CK__GPIO4_20 0x208 0x5f8 0x000 0x3 0x0
#define MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x20c 0x5fc 0x000 0x0 0x0
#define MX51_PAD_AUD3_BB_FS__GPIO4_21 0x20c 0x5fc 0x000 0x3 0x0
#define MX51_PAD_AUD3_BB_FS__UART3_TXD 0x20c 0x5fc 0x000 0x1 0x0
#define MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x210 0x600 0x000 0x0 0x0
#define MX51_PAD_CSPI1_MOSI__GPIO4_22 0x210 0x600 0x000 0x3 0x0
#define MX51_PAD_CSPI1_MOSI__I2C1_SDA 0x210 0x600 0x9b4 0x1 0x1
#define MX51_PAD_CSPI1_MISO__AUD4_RXD 0x214 0x604 0x8c4 0x1 0x1
#define MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x214 0x604 0x000 0x0 0x0
#define MX51_PAD_CSPI1_MISO__GPIO4_23 0x214 0x604 0x000 0x3 0x0
#define MX51_PAD_CSPI1_SS0__AUD4_TXC 0x218 0x608 0x8cc 0x1 0x1
#define MX51_PAD_CSPI1_SS0__ECSPI1_SS0 0x218 0x608 0x000 0x0 0x0
#define MX51_PAD_CSPI1_SS0__GPIO4_24 0x218 0x608 0x000 0x3 0x0
#define MX51_PAD_CSPI1_SS1__AUD4_TXD 0x21c 0x60c 0x8c8 0x1 0x1
#define MX51_PAD_CSPI1_SS1__ECSPI1_SS1 0x21c 0x60c 0x000 0x0 0x0
#define MX51_PAD_CSPI1_SS1__GPIO4_25 0x21c 0x60c 0x000 0x3 0x0
#define MX51_PAD_CSPI1_RDY__AUD4_TXFS 0x220 0x610 0x8d0 0x1 0x1
#define MX51_PAD_CSPI1_RDY__ECSPI1_RDY 0x220 0x610 0x000 0x0 0x0
#define MX51_PAD_CSPI1_RDY__GPIO4_26 0x220 0x610 0x000 0x3 0x0
#define MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x224 0x614 0x000 0x0 0x0
#define MX51_PAD_CSPI1_SCLK__GPIO4_27 0x224 0x614 0x000 0x3 0x0
#define MX51_PAD_CSPI1_SCLK__I2C1_SCL 0x224 0x614 0x9b0 0x1 0x1
#define MX51_PAD_UART1_RXD__GPIO4_28 0x228 0x618 0x000 0x3 0x0
#define MX51_PAD_UART1_RXD__UART1_RXD 0x228 0x618 0x9e4 0x0 0x0
#define MX51_PAD_UART1_TXD__GPIO4_29 0x22c 0x61c 0x000 0x3 0x0
#define MX51_PAD_UART1_TXD__PWM2_PWMO 0x22c 0x61c 0x000 0x1 0x0
#define MX51_PAD_UART1_TXD__UART1_TXD 0x22c 0x61c 0x000 0x0 0x0
#define MX51_PAD_UART1_RTS__GPIO4_30 0x230 0x620 0x000 0x3 0x0
#define MX51_PAD_UART1_RTS__UART1_RTS 0x230 0x620 0x9e0 0x0 0x0
#define MX51_PAD_UART1_CTS__GPIO4_31 0x234 0x624 0x000 0x3 0x0
#define MX51_PAD_UART1_CTS__UART1_CTS 0x234 0x624 0x000 0x0 0x0
#define MX51_PAD_UART2_RXD__FIRI_TXD 0x238 0x628 0x000 0x1 0x0
#define MX51_PAD_UART2_RXD__GPIO1_20 0x238 0x628 0x000 0x3 0x0
#define MX51_PAD_UART2_RXD__UART2_RXD 0x238 0x628 0x9ec 0x0 0x2
#define MX51_PAD_UART2_TXD__FIRI_RXD 0x23c 0x62c 0x000 0x1 0x0
#define MX51_PAD_UART2_TXD__GPIO1_21 0x23c 0x62c 0x000 0x3 0x0
#define MX51_PAD_UART2_TXD__UART2_TXD 0x23c 0x62c 0x000 0x0 0x0
#define MX51_PAD_UART3_RXD__CSI1_D0 0x240 0x630 0x000 0x2 0x0
#define MX51_PAD_UART3_RXD__GPIO1_22 0x240 0x630 0x000 0x3 0x0
#define MX51_PAD_UART3_RXD__UART1_DTR 0x240 0x630 0x000 0x0 0x0
#define MX51_PAD_UART3_RXD__UART3_RXD 0x240 0x630 0x9f4 0x1 0x4
#define MX51_PAD_UART3_TXD__CSI1_D1 0x244 0x634 0x000 0x2 0x0
#define MX51_PAD_UART3_TXD__GPIO1_23 0x244 0x634 0x000 0x3 0x0
#define MX51_PAD_UART3_TXD__UART1_DSR 0x244 0x634 0x000 0x0 0x0
#define MX51_PAD_UART3_TXD__UART3_TXD 0x244 0x634 0x000 0x1 0x0
#define MX51_PAD_OWIRE_LINE__GPIO1_24 0x248 0x638 0x000 0x3 0x0
#define MX51_PAD_OWIRE_LINE__OWIRE_LINE 0x248 0x638 0x000 0x0 0x0
#define MX51_PAD_OWIRE_LINE__SPDIF_OUT 0x248 0x638 0x000 0x6 0x0
#define MX51_PAD_KEY_ROW0__KEY_ROW0 0x24c 0x63c 0x000 0x0 0x0
#define MX51_PAD_KEY_ROW1__KEY_ROW1 0x250 0x640 0x000 0x0 0x0
#define MX51_PAD_KEY_ROW2__KEY_ROW2 0x254 0x644 0x000 0x0 0x0
#define MX51_PAD_KEY_ROW3__KEY_ROW3 0x258 0x648 0x000 0x0 0x0
#define MX51_PAD_KEY_COL0__KEY_COL0 0x25c 0x64c 0x000 0x0 0x0
#define MX51_PAD_KEY_COL0__PLL1_BYP 0x25c 0x64c 0x90c 0x7 0x0
#define MX51_PAD_KEY_COL1__KEY_COL1 0x260 0x650 0x000 0x0 0x0
#define MX51_PAD_KEY_COL1__PLL2_BYP 0x260 0x650 0x910 0x7 0x0
#define MX51_PAD_KEY_COL2__KEY_COL2 0x264 0x654 0x000 0x0 0x0
#define MX51_PAD_KEY_COL2__PLL3_BYP 0x264 0x654 0x000 0x7 0x0
#define MX51_PAD_KEY_COL3__KEY_COL3 0x268 0x658 0x000 0x0 0x0
#define MX51_PAD_KEY_COL4__I2C2_SCL 0x26c 0x65c 0x9b8 0x3 0x1
#define MX51_PAD_KEY_COL4__KEY_COL4 0x26c 0x65c 0x000 0x0 0x0
#define MX51_PAD_KEY_COL4__SPDIF_OUT1 0x26c 0x65c 0x000 0x6 0x0
#define MX51_PAD_KEY_COL4__UART1_RI 0x26c 0x65c 0x000 0x1 0x0
#define MX51_PAD_KEY_COL4__UART3_RTS 0x26c 0x65c 0x9f0 0x2 0x4
#define MX51_PAD_KEY_COL5__I2C2_SDA 0x270 0x660 0x9bc 0x3 0x1
#define MX51_PAD_KEY_COL5__KEY_COL5 0x270 0x660 0x000 0x0 0x0
#define MX51_PAD_KEY_COL5__UART1_DCD 0x270 0x660 0x000 0x1 0x0
#define MX51_PAD_KEY_COL5__UART3_CTS 0x270 0x660 0x000 0x2 0x0
#define MX51_PAD_USBH1_CLK__CSPI_SCLK 0x278 0x678 0x914 0x1 0x1
#define MX51_PAD_USBH1_CLK__GPIO1_25 0x278 0x678 0x000 0x2 0x0
#define MX51_PAD_USBH1_CLK__I2C2_SCL 0x278 0x678 0x9b8 0x5 0x2
#define MX51_PAD_USBH1_CLK__USBH1_CLK 0x278 0x678 0x000 0x0 0x0
#define MX51_PAD_USBH1_DIR__CSPI_MOSI 0x27c 0x67c 0x91c 0x1 0x1
#define MX51_PAD_USBH1_DIR__GPIO1_26 0x27c 0x67c 0x000 0x2 0x0
#define MX51_PAD_USBH1_DIR__I2C2_SDA 0x27c 0x67c 0x9bc 0x5 0x2
#define MX51_PAD_USBH1_DIR__USBH1_DIR 0x27c 0x67c 0x000 0x0 0x0
#define MX51_PAD_USBH1_STP__CSPI_RDY 0x280 0x680 0x000 0x1 0x0
#define MX51_PAD_USBH1_STP__GPIO1_27 0x280 0x680 0x000 0x2 0x0
#define MX51_PAD_USBH1_STP__UART3_RXD 0x280 0x680 0x9f4 0x5 0x6
#define MX51_PAD_USBH1_STP__USBH1_STP 0x280 0x680 0x000 0x0 0x0
#define MX51_PAD_USBH1_NXT__CSPI_MISO 0x284 0x684 0x918 0x1 0x0
#define MX51_PAD_USBH1_NXT__GPIO1_28 0x284 0x684 0x000 0x2 0x0
#define MX51_PAD_USBH1_NXT__UART3_TXD 0x284 0x684 0x000 0x5 0x0
#define MX51_PAD_USBH1_NXT__USBH1_NXT 0x284 0x684 0x000 0x0 0x0
#define MX51_PAD_USBH1_DATA0__GPIO1_11 0x288 0x688 0x000 0x2 0x0
#define MX51_PAD_USBH1_DATA0__UART2_CTS 0x288 0x688 0x000 0x1 0x0
#define MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x288 0x688 0x000 0x0 0x0
#define MX51_PAD_USBH1_DATA1__GPIO1_12 0x28c 0x68c 0x000 0x2 0x0
#define MX51_PAD_USBH1_DATA1__UART2_RXD 0x28c 0x68c 0x9ec 0x1 0x4
#define MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x28c 0x68c 0x000 0x0 0x0
#define MX51_PAD_USBH1_DATA2__GPIO1_13 0x290 0x690 0x000 0x2 0x0
#define MX51_PAD_USBH1_DATA2__UART2_TXD 0x290 0x690 0x000 0x1 0x0
#define MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x290 0x690 0x000 0x0 0x0
#define MX51_PAD_USBH1_DATA3__GPIO1_14 0x294 0x694 0x000 0x2 0x0
#define MX51_PAD_USBH1_DATA3__UART2_RTS 0x294 0x694 0x9e8 0x1 0x5
#define MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x294 0x694 0x000 0x0 0x0
#define MX51_PAD_USBH1_DATA4__CSPI_SS0 0x298 0x698 0x000 0x1 0x0
#define MX51_PAD_USBH1_DATA4__GPIO1_15 0x298 0x698 0x000 0x2 0x0
#define MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x298 0x698 0x000 0x0 0x0
#define MX51_PAD_USBH1_DATA5__CSPI_SS1 0x29c 0x69c 0x920 0x1 0x0
#define MX51_PAD_USBH1_DATA5__GPIO1_16 0x29c 0x69c 0x000 0x2 0x0
#define MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x29c 0x69c 0x000 0x0 0x0
#define MX51_PAD_USBH1_DATA6__CSPI_SS3 0x2a0 0x6a0 0x928 0x1 0x1
#define MX51_PAD_USBH1_DATA6__GPIO1_17 0x2a0 0x6a0 0x000 0x2 0x0
#define MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x2a0 0x6a0 0x000 0x0 0x0
#define MX51_PAD_USBH1_DATA7__ECSPI1_SS3 0x2a4 0x6a4 0x000 0x1 0x0
#define MX51_PAD_USBH1_DATA7__ECSPI2_SS3 0x2a4 0x6a4 0x934 0x5 0x1
#define MX51_PAD_USBH1_DATA7__GPIO1_18 0x2a4 0x6a4 0x000 0x2 0x0
#define MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x2a4 0x6a4 0x000 0x0 0x0
#define MX51_PAD_DI1_PIN11__DI1_PIN11 0x2a8 0x6a8 0x000 0x0 0x0
#define MX51_PAD_DI1_PIN11__ECSPI1_SS2 0x2a8 0x6a8 0x000 0x7 0x0
#define MX51_PAD_DI1_PIN11__GPIO3_0 0x2a8 0x6a8 0x000 0x4 0x0
#define MX51_PAD_DI1_PIN12__DI1_PIN12 0x2ac 0x6ac 0x000 0x0 0x0
#define MX51_PAD_DI1_PIN12__GPIO3_1 0x2ac 0x6ac 0x978 0x4 0x1
#define MX51_PAD_DI1_PIN13__DI1_PIN13 0x2b0 0x6b0 0x000 0x0 0x0
#define MX51_PAD_DI1_PIN13__GPIO3_2 0x2b0 0x6b0 0x97c 0x4 0x1
#define MX51_PAD_DI1_D0_CS__DI1_D0_CS 0x2b4 0x6b4 0x000 0x0 0x0
#define MX51_PAD_DI1_D0_CS__GPIO3_3 0x2b4 0x6b4 0x980 0x4 0x1
#define MX51_PAD_DI1_D1_CS__DI1_D1_CS 0x2b8 0x6b8 0x000 0x0 0x0
#define MX51_PAD_DI1_D1_CS__DISP1_PIN14 0x2b8 0x6b8 0x000 0x2 0x0
#define MX51_PAD_DI1_D1_CS__DISP1_PIN5 0x2b8 0x6b8 0x000 0x3 0x0
#define MX51_PAD_DI1_D1_CS__GPIO3_4 0x2b8 0x6b8 0x984 0x4 0x1
#define MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1 0x2bc 0x6bc 0x9a4 0x2 0x1
#define MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN 0x2bc 0x6bc 0x9c4 0x0 0x0
#define MX51_PAD_DISPB2_SER_DIN__GPIO3_5 0x2bc 0x6bc 0x988 0x4 0x1
#define MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6 0x2c0 0x6c0 0x000 0x3 0x0
#define MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO 0x2c0 0x6c0 0x9c4 0x0 0x1
#define MX51_PAD_DISPB2_SER_DIO__GPIO3_6 0x2c0 0x6c0 0x98c 0x4 0x1
#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17 0x2c4 0x6c4 0x000 0x2 0x0
#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7 0x2c4 0x6c4 0x000 0x3 0x0
#define MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK 0x2c4 0x6c4 0x000 0x0 0x0
#define MX51_PAD_DISPB2_SER_CLK__GPIO3_7 0x2c4 0x6c4 0x990 0x4 0x1
#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN16 0x2c8 0x6c8 0x000 0x2 0x0
#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN8 0x2c8 0x6c8 0x000 0x3 0x0
#define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS 0x2c8 0x6c8 0x000 0x0 0x0
#define MX51_PAD_DISPB2_SER_RS__GPIO3_8 0x2c8 0x6c8 0x994 0x4 0x1
#define MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x2cc 0x6cc 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x2d0 0x6d0 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x2d4 0x6d4 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x2d8 0x6d8 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x2dc 0x6dc 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x2e0 0x6e0 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT6__BOOT_USB_SRC 0x2e4 0x6e4 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x2e4 0x6e4 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG 0x2e8 0x6e8 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x2e8 0x6e8 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT8__BOOT_SRC0 0x2ec 0x6ec 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x2ec 0x6ec 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT9__BOOT_SRC1 0x2f0 0x6f0 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x2f0 0x6f0 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE 0x2f4 0x6f4 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x2f4 0x6f4 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2 0x2f8 0x6f8 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x2f8 0x6f8 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL 0x2fc 0x6fc 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x2fc 0x6fc 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0 0x300 0x700 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x300 0x700 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1 0x304 0x704 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x304 0x704 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH 0x308 0x708 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x308 0x708 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0 0x30c 0x70c 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x30c 0x70c 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1 0x310 0x710 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x310 0x710 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0 0x314 0x714 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x314 0x714 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT18__DISP2_PIN11 0x314 0x714 0x000 0x5 0x0
#define MX51_PAD_DISP1_DAT18__DISP2_PIN5 0x314 0x714 0x000 0x4 0x0
#define MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1 0x318 0x718 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x318 0x718 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT19__DISP2_PIN12 0x318 0x718 0x000 0x5 0x0
#define MX51_PAD_DISP1_DAT19__DISP2_PIN6 0x318 0x718 0x000 0x4 0x0
#define MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0 0x31c 0x71c 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x31c 0x71c 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT20__DISP2_PIN13 0x31c 0x71c 0x000 0x5 0x0
#define MX51_PAD_DISP1_DAT20__DISP2_PIN7 0x31c 0x71c 0x000 0x4 0x0
#define MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1 0x320 0x720 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x320 0x720 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT21__DISP2_PIN14 0x320 0x720 0x000 0x5 0x0
#define MX51_PAD_DISP1_DAT21__DISP2_PIN8 0x320 0x720 0x000 0x4 0x0
#define MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0 0x324 0x724 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x324 0x724 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT22__DISP2_D0_CS 0x324 0x724 0x000 0x6 0x0
#define MX51_PAD_DISP1_DAT22__DISP2_DAT16 0x324 0x724 0x000 0x5 0x0
#define MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1 0x328 0x728 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x328 0x728 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT23__DISP2_D1_CS 0x328 0x728 0x000 0x6 0x0
#define MX51_PAD_DISP1_DAT23__DISP2_DAT17 0x328 0x728 0x000 0x5 0x0
#define MX51_PAD_DISP1_DAT23__DISP2_SER_CS 0x328 0x728 0x000 0x4 0x0
#define MX51_PAD_DI1_PIN3__DI1_PIN3 0x32c 0x72c 0x000 0x0 0x0
#define MX51_PAD_DI1_PIN2__DI1_PIN2 0x330 0x734 0x000 0x0 0x0
#define MX51_PAD_DI_GP2__DISP1_SER_CLK 0x338 0x740 0x000 0x0 0x0
#define MX51_PAD_DI_GP2__DISP2_WAIT 0x338 0x740 0x9a8 0x2 0x1
#define MX51_PAD_DI_GP3__CSI1_DATA_EN 0x33c 0x744 0x9a0 0x3 0x1
#define MX51_PAD_DI_GP3__DISP1_SER_DIO 0x33c 0x744 0x9c0 0x0 0x0
#define MX51_PAD_DI_GP3__FEC_TX_ER 0x33c 0x744 0x000 0x2 0x0
#define MX51_PAD_DI2_PIN4__CSI2_DATA_EN 0x340 0x748 0x99c 0x3 0x1
#define MX51_PAD_DI2_PIN4__DI2_PIN4 0x340 0x748 0x000 0x0 0x0
#define MX51_PAD_DI2_PIN4__FEC_CRS 0x340 0x748 0x950 0x2 0x1
#define MX51_PAD_DI2_PIN2__DI2_PIN2 0x344 0x74c 0x000 0x0 0x0
#define MX51_PAD_DI2_PIN2__FEC_MDC 0x344 0x74c 0x000 0x2 0x0
#define MX51_PAD_DI2_PIN3__DI2_PIN3 0x348 0x750 0x000 0x0 0x0
#define MX51_PAD_DI2_PIN3__FEC_MDIO 0x348 0x750 0x954 0x2 0x1
#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x34c 0x754 0x000 0x0 0x0
#define MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x34c 0x754 0x95c 0x2 0x1
#define MX51_PAD_DI_GP4__DI2_PIN15 0x350 0x758 0x000 0x4 0x0
#define MX51_PAD_DI_GP4__DISP1_SER_DIN 0x350 0x758 0x9c0 0x0 0x1
#define MX51_PAD_DI_GP4__DISP2_PIN1 0x350 0x758 0x000 0x3 0x0
#define MX51_PAD_DI_GP4__FEC_RDATA2 0x350 0x758 0x960 0x2 0x1
#define MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x354 0x75c 0x000 0x0 0x0
#define MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x354 0x75c 0x964 0x2 0x1
#define MX51_PAD_DISP2_DAT0__KEY_COL6 0x354 0x75c 0x9c8 0x4 0x1
#define MX51_PAD_DISP2_DAT0__UART3_RXD 0x354 0x75c 0x9f4 0x5 0x8
#define MX51_PAD_DISP2_DAT0__USBH3_CLK 0x354 0x75c 0x9f8 0x3 0x1
#define MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x358 0x760 0x000 0x0 0x0
#define MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x358 0x760 0x970 0x2 0x1
#define MX51_PAD_DISP2_DAT1__KEY_COL7 0x358 0x760 0x9cc 0x4 0x1
#define MX51_PAD_DISP2_DAT1__UART3_TXD 0x358 0x760 0x000 0x5 0x0
#define MX51_PAD_DISP2_DAT1__USBH3_DIR 0x358 0x760 0xa1c 0x3 0x1
#define MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x35c 0x764 0x000 0x0 0x0
#define MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x360 0x768 0x000 0x0 0x0
#define MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x364 0x76c 0x000 0x0 0x0
#define MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x368 0x770 0x000 0x0 0x0
#define MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x36c 0x774 0x000 0x0 0x0
#define MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x36c 0x774 0x000 0x2 0x0
#define MX51_PAD_DISP2_DAT6__GPIO1_19 0x36c 0x774 0x000 0x5 0x0
#define MX51_PAD_DISP2_DAT6__KEY_ROW4 0x36c 0x774 0x9d0 0x4 0x1
#define MX51_PAD_DISP2_DAT6__USBH3_STP 0x36c 0x774 0xa24 0x3 0x1
#define MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x370 0x778 0x000 0x0 0x0
#define MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x370 0x778 0x000 0x2 0x0
#define MX51_PAD_DISP2_DAT7__GPIO1_29 0x370 0x778 0x000 0x5 0x0
#define MX51_PAD_DISP2_DAT7__KEY_ROW5 0x370 0x778 0x9d4 0x4 0x1
#define MX51_PAD_DISP2_DAT7__USBH3_NXT 0x370 0x778 0xa20 0x3 0x1
#define MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x374 0x77c 0x000 0x0 0x0
#define MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x374 0x77c 0x000 0x2 0x0
#define MX51_PAD_DISP2_DAT8__GPIO1_30 0x374 0x77c 0x000 0x5 0x0
#define MX51_PAD_DISP2_DAT8__KEY_ROW6 0x374 0x77c 0x9d8 0x4 0x1
#define MX51_PAD_DISP2_DAT8__USBH3_DATA0 0x374 0x77c 0x9fc 0x3 0x1
#define MX51_PAD_DISP2_DAT9__AUD6_RXC 0x378 0x780 0x8f4 0x4 0x1
#define MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x378 0x780 0x000 0x0 0x0
#define MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x378 0x780 0x000 0x2 0x0
#define MX51_PAD_DISP2_DAT9__GPIO1_31 0x378 0x780 0x000 0x5 0x0
#define MX51_PAD_DISP2_DAT9__USBH3_DATA1 0x378 0x780 0xa00 0x3 0x1
#define MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x37c 0x784 0x000 0x0 0x0
#define MX51_PAD_DISP2_DAT10__DISP2_SER_CS 0x37c 0x784 0x000 0x5 0x0
#define MX51_PAD_DISP2_DAT10__FEC_COL 0x37c 0x784 0x94c 0x2 0x1
#define MX51_PAD_DISP2_DAT10__KEY_ROW7 0x37c 0x784 0x9dc 0x4 0x1
#define MX51_PAD_DISP2_DAT10__USBH3_DATA2 0x37c 0x784 0xa04 0x3 0x1
#define MX51_PAD_DISP2_DAT11__AUD6_TXD 0x380 0x788 0x8f0 0x4 0x1
#define MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x380 0x788 0x000 0x0 0x0
#define MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x380 0x788 0x968 0x2 0x1
#define MX51_PAD_DISP2_DAT11__GPIO1_10 0x380 0x788 0x000 0x7 0x0
#define MX51_PAD_DISP2_DAT11__USBH3_DATA3 0x380 0x788 0xa08 0x3 0x1
#define MX51_PAD_DISP2_DAT12__AUD6_RXD 0x384 0x78c 0x8ec 0x4 0x1
#define MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x384 0x78c 0x000 0x0 0x0
#define MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x384 0x78c 0x96c 0x2 0x1
#define MX51_PAD_DISP2_DAT12__USBH3_DATA4 0x384 0x78c 0xa0c 0x3 0x1
#define MX51_PAD_DISP2_DAT13__AUD6_TXC 0x388 0x790 0x8fc 0x4 0x1
#define MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x388 0x790 0x000 0x0 0x0
#define MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x388 0x790 0x974 0x2 0x1
#define MX51_PAD_DISP2_DAT13__USBH3_DATA5 0x388 0x790 0xa10 0x3 0x1
#define MX51_PAD_DISP2_DAT14__AUD6_TXFS 0x38c 0x794 0x900 0x4 0x1
#define MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x38c 0x794 0x000 0x0 0x0
#define MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x38c 0x794 0x958 0x2 0x1
#define MX51_PAD_DISP2_DAT14__USBH3_DATA6 0x38c 0x794 0xa14 0x3 0x1
#define MX51_PAD_DISP2_DAT15__AUD6_RXFS 0x390 0x798 0x8f8 0x4 0x1
#define MX51_PAD_DISP2_DAT15__DISP1_SER_CS 0x390 0x798 0x000 0x5 0x0
#define MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x390 0x798 0x000 0x0 0x0
#define MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x390 0x798 0x000 0x2 0x0
#define MX51_PAD_DISP2_DAT15__USBH3_DATA7 0x390 0x798 0xa18 0x3 0x1
#define MX51_PAD_SD1_CMD__AUD5_RXFS 0x394 0x79c 0x8e0 0x1 0x1
#define MX51_PAD_SD1_CMD__CSPI_MOSI 0x394 0x79c 0x91c 0x2 0x2
#define MX51_PAD_SD1_CMD__SD1_CMD 0x394 0x79c 0x000 0x0 0x0
#define MX51_PAD_SD1_CLK__AUD5_RXC 0x398 0x7a0 0x8dc 0x1 0x1
#define MX51_PAD_SD1_CLK__CSPI_SCLK 0x398 0x7a0 0x914 0x2 0x2
#define MX51_PAD_SD1_CLK__SD1_CLK 0x398 0x7a0 0x000 0x0 0x0
#define MX51_PAD_SD1_DATA0__AUD5_TXD 0x39c 0x7a4 0x8d8 0x1 0x2
#define MX51_PAD_SD1_DATA0__CSPI_MISO 0x39c 0x7a4 0x918 0x2 0x1
#define MX51_PAD_SD1_DATA0__SD1_DATA0 0x39c 0x7a4 0x000 0x0 0x0
#define MX51_PAD_EIM_DA0__EIM_DA0 0x01c 0x000 0x000 0x0 0x0
#define MX51_PAD_EIM_DA1__EIM_DA1 0x020 0x000 0x000 0x0 0x0
#define MX51_PAD_EIM_DA2__EIM_DA2 0x024 0x000 0x000 0x0 0x0
#define MX51_PAD_EIM_DA3__EIM_DA3 0x028 0x000 0x000 0x0 0x0
#define MX51_PAD_SD1_DATA1__AUD5_RXD 0x3a0 0x7a8 0x8d4 0x1 0x2
#define MX51_PAD_SD1_DATA1__SD1_DATA1 0x3a0 0x7a8 0x000 0x0 0x0
#define MX51_PAD_EIM_DA4__EIM_DA4 0x02c 0x000 0x000 0x0 0x0
#define MX51_PAD_EIM_DA5__EIM_DA5 0x030 0x000 0x000 0x0 0x0
#define MX51_PAD_EIM_DA6__EIM_DA6 0x034 0x000 0x000 0x0 0x0
#define MX51_PAD_EIM_DA7__EIM_DA7 0x038 0x000 0x000 0x0 0x0
#define MX51_PAD_SD1_DATA2__AUD5_TXC 0x3a4 0x7ac 0x8e4 0x1 0x2
#define MX51_PAD_SD1_DATA2__SD1_DATA2 0x3a4 0x7ac 0x000 0x0 0x0
#define MX51_PAD_EIM_DA10__EIM_DA10 0x044 0x000 0x000 0x0 0x0
#define MX51_PAD_EIM_DA11__EIM_DA11 0x048 0x000 0x000 0x0 0x0
#define MX51_PAD_EIM_DA8__EIM_DA8 0x03c 0x000 0x000 0x0 0x0
#define MX51_PAD_EIM_DA9__EIM_DA9 0x040 0x000 0x000 0x0 0x0
#define MX51_PAD_SD1_DATA3__AUD5_TXFS 0x3a8 0x7b0 0x8e8 0x1 0x2
#define MX51_PAD_SD1_DATA3__CSPI_SS1 0x3a8 0x7b0 0x920 0x2 0x1
#define MX51_PAD_SD1_DATA3__SD1_DATA3 0x3a8 0x7b0 0x000 0x0 0x0
#define MX51_PAD_GPIO1_0__CSPI_SS2 0x3ac 0x7b4 0x924 0x2 0x0
#define MX51_PAD_GPIO1_0__GPIO1_0 0x3ac 0x7b4 0x000 0x1 0x0
#define MX51_PAD_GPIO1_0__SD1_CD 0x3ac 0x7b4 0x000 0x0 0x0
#define MX51_PAD_GPIO1_1__CSPI_MISO 0x3b0 0x7b8 0x918 0x2 0x2
#define MX51_PAD_GPIO1_1__GPIO1_1 0x3b0 0x7b8 0x000 0x1 0x0
#define MX51_PAD_GPIO1_1__SD1_WP 0x3b0 0x7b8 0x000 0x0 0x0
#define MX51_PAD_EIM_DA12__EIM_DA12 0x04c 0x000 0x000 0x0 0x0
#define MX51_PAD_EIM_DA13__EIM_DA13 0x050 0x000 0x000 0x0 0x0
#define MX51_PAD_EIM_DA14__EIM_DA14 0x054 0x000 0x000 0x0 0x0
#define MX51_PAD_EIM_DA15__EIM_DA15 0x058 0x000 0x000 0x0 0x0
#define MX51_PAD_SD2_CMD__CSPI_MOSI 0x3b4 0x7bc 0x91c 0x2 0x3
#define MX51_PAD_SD2_CMD__I2C1_SCL 0x3b4 0x7bc 0x9b0 0x1 0x2
#define MX51_PAD_SD2_CMD__SD2_CMD 0x3b4 0x7bc 0x000 0x0 0x0
#define MX51_PAD_SD2_CLK__CSPI_SCLK 0x3b8 0x7c0 0x914 0x2 0x3
#define MX51_PAD_SD2_CLK__I2C1_SDA 0x3b8 0x7c0 0x9b4 0x1 0x2
#define MX51_PAD_SD2_CLK__SD2_CLK 0x3b8 0x7c0 0x000 0x0 0x0
#define MX51_PAD_SD2_DATA0__CSPI_MISO 0x3bc 0x7c4 0x918 0x2 0x3
#define MX51_PAD_SD2_DATA0__SD1_DAT4 0x3bc 0x7c4 0x000 0x1 0x0
#define MX51_PAD_SD2_DATA0__SD2_DATA0 0x3bc 0x7c4 0x000 0x0 0x0
#define MX51_PAD_SD2_DATA1__SD1_DAT5 0x3c0 0x7c8 0x000 0x1 0x0
#define MX51_PAD_SD2_DATA1__SD2_DATA1 0x3c0 0x7c8 0x000 0x0 0x0
#define MX51_PAD_SD2_DATA1__USBH3_H2_DP 0x3c0 0x7c8 0x000 0x2 0x0
#define MX51_PAD_SD2_DATA2__SD1_DAT6 0x3c4 0x7cc 0x000 0x1 0x0
#define MX51_PAD_SD2_DATA2__SD2_DATA2 0x3c4 0x7cc 0x000 0x0 0x0
#define MX51_PAD_SD2_DATA2__USBH3_H2_DM 0x3c4 0x7cc 0x000 0x2 0x0
#define MX51_PAD_SD2_DATA3__CSPI_SS2 0x3c8 0x7d0 0x924 0x2 0x1
#define MX51_PAD_SD2_DATA3__SD1_DAT7 0x3c8 0x7d0 0x000 0x1 0x0
#define MX51_PAD_SD2_DATA3__SD2_DATA3 0x3c8 0x7d0 0x000 0x0 0x0
#define MX51_PAD_GPIO1_2__CCM_OUT_2 0x3cc 0x7d4 0x000 0x5 0x0
#define MX51_PAD_GPIO1_2__GPIO1_2 0x3cc 0x7d4 0x000 0x0 0x0
#define MX51_PAD_GPIO1_2__I2C2_SCL 0x3cc 0x7d4 0x9b8 0x2 0x3
#define MX51_PAD_GPIO1_2__PLL1_BYP 0x3cc 0x7d4 0x90c 0x7 0x1
#define MX51_PAD_GPIO1_2__PWM1_PWMO 0x3cc 0x7d4 0x000 0x1 0x0
#define MX51_PAD_GPIO1_3__GPIO1_3 0x3d0 0x7d8 0x000 0x0 0x0
#define MX51_PAD_GPIO1_3__I2C2_SDA 0x3d0 0x7d8 0x9bc 0x2 0x3
#define MX51_PAD_GPIO1_3__PLL2_BYP 0x3d0 0x7d8 0x910 0x7 0x1
#define MX51_PAD_GPIO1_3__PWM2_PWMO 0x3d0 0x7d8 0x000 0x1 0x0
#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ 0x3d4 0x7fc 0x000 0x0 0x0
#define MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B 0x3d4 0x7fc 0x000 0x1 0x0
#define MX51_PAD_GPIO1_4__DISP2_EXT_CLK 0x3d8 0x804 0x908 0x4 0x1
#define MX51_PAD_GPIO1_4__EIM_RDY 0x3d8 0x804 0x938 0x3 0x1
#define MX51_PAD_GPIO1_4__GPIO1_4 0x3d8 0x804 0x000 0x0 0x0
#define MX51_PAD_GPIO1_4__WDOG1_WDOG_B 0x3d8 0x804 0x000 0x2 0x0
#define MX51_PAD_GPIO1_5__CSI2_MCLK 0x3dc 0x808 0x000 0x6 0x0
#define MX51_PAD_GPIO1_5__DISP2_PIN16 0x3dc 0x808 0x000 0x3 0x0
#define MX51_PAD_GPIO1_5__GPIO1_5 0x3dc 0x808 0x000 0x0 0x0
#define MX51_PAD_GPIO1_5__WDOG2_WDOG_B 0x3dc 0x808 0x000 0x2 0x0
#define MX51_PAD_GPIO1_6__DISP2_PIN17 0x3e0 0x80c 0x000 0x4 0x0
#define MX51_PAD_GPIO1_6__GPIO1_6 0x3e0 0x80c 0x000 0x0 0x0
#define MX51_PAD_GPIO1_6__REF_EN_B 0x3e0 0x80c 0x000 0x3 0x0
#define MX51_PAD_GPIO1_7__CCM_OUT_0 0x3e4 0x810 0x000 0x3 0x0
#define MX51_PAD_GPIO1_7__GPIO1_7 0x3e4 0x810 0x000 0x0 0x0
#define MX51_PAD_GPIO1_7__SD2_WP 0x3e4 0x810 0x000 0x6 0x0
#define MX51_PAD_GPIO1_7__SPDIF_OUT1 0x3e4 0x810 0x000 0x2 0x0
#define MX51_PAD_GPIO1_8__CSI2_DATA_EN 0x3e8 0x814 0x99c 0x2 0x2
#define MX51_PAD_GPIO1_8__GPIO1_8 0x3e8 0x814 0x000 0x0 0x0
#define MX51_PAD_GPIO1_8__SD2_CD 0x3e8 0x814 0x000 0x6 0x0
#define MX51_PAD_GPIO1_8__USBH3_PWR 0x3e8 0x814 0x000 0x1 0x0
#define MX51_PAD_GPIO1_9__CCM_OUT_1 0x3ec 0x818 0x000 0x3 0x0
#define MX51_PAD_GPIO1_9__DISP2_D1_CS 0x3ec 0x818 0x000 0x2 0x0
#define MX51_PAD_GPIO1_9__DISP2_SER_CS 0x3ec 0x818 0x000 0x7 0x0
#define MX51_PAD_GPIO1_9__GPIO1_9 0x3ec 0x818 0x000 0x0 0x0
#define MX51_PAD_GPIO1_9__SD2_LCTL 0x3ec 0x818 0x000 0x6 0x0
#define MX51_PAD_GPIO1_9__USBH3_OC 0x3ec 0x818 0x000 0x1 0x0
#endif /* __DTS_IMX51_PINFUNC_H */

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// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright (C) 2022 Kontron Electronics GmbH
*/
/dts-v1/;
#include "imx6dl.dtsi"
#include <dt-bindings/clock/imx6qdl-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
model = "Sielaff i.MX6 Solo";
compatible = "sielaff,imx6dl-board", "fsl,imx6dl";
chosen {
stdout-path = &uart2;
};
backlight: pwm-backlight {
compatible = "pwm-backlight";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_backlight>;
pwms = <&pwm3 0 50000 0>;
brightness-levels = <0 0 64 88 112 136 184 232 255>;
default-brightness-level = <4>;
enable-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>;
power-supply = <&reg_backlight>;
};
cec {
compatible = "cec-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hdmi_cec>;
cec-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
hdmi-phandle = <&hdmi>;
};
enet_ref: clock-enet-ref {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
clock-output-names = "enet-ref";
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_keys>;
key-0 {
gpios = <&gpio2 16 0>;
debounce-interval = <10>;
linux,code = <1>;
};
key-1 {
gpios = <&gpio3 27 0>;
debounce-interval = <10>;
linux,code = <2>;
};
key-2 {
gpios = <&gpio5 4 0>;
debounce-interval = <10>;
linux,code = <3>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
led-debug {
label = "debug-led";
gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>;
default-state = "off";
linux,default-trigger = "heartbeat";
};
};
memory@80000000 {
reg = <0x80000000 0x20000000>;
device_type = "memory";
};
osc_eth_phy: clock-osc-eth-phy {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
clock-output-names = "osc-eth-phy";
};
panel {
compatible = "lg,lb070wv8";
backlight = <&backlight>;
power-supply = <&reg_3v3>;
port {
panel_in_lvds: endpoint {
remote-endpoint = <&lvds_out>;
};
};
};
reg_3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
reg_backlight: regulator-backlight {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_backlight>;
enable-active-high;
gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>;
regulator-name = "backlight";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
};
reg_usb_otg_vbus: regulator-usb-otg-vbus {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usbotg_vbus>;
enable-active-high;
gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>;
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
};
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
cs-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>;
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <20000000>;
};
};
&fec {
/*
* Set PTP clock to external instead of internal reference, as the
* REF_CLK from the PHY is fed back into the i.MX6 and the GPR
* register needs to be set accordingly (see mach-imx6q.c).
*/
clocks = <&clks IMX6QDL_CLK_ENET>,
<&clks IMX6QDL_CLK_ENET>,
<&enet_ref>,
<&clks IMX6QDL_CLK_ENET_REF>;
clock-names = "ipg", "ahb", "ptp", "enet_out";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-connection-type = "rmii";
phy-handle = <&ethphy>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy: ethernet-phy@1 {
reg = <1>;
clocks = <&osc_eth_phy>;
clock-names = "rmii-ref";
micrel,led-mode = <1>;
reset-assert-us = <500>;
reset-deassert-us = <100>;
reset-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
};
};
};
&gpio1 {
gpio-line-names =
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "key-out", "key-in",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
};
&gpio2 {
gpio-line-names =
"", "", "", "", "", "", "", "",
"lan9500a-rst", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
};
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
status = "okay";
};
&hdmi {
ddc-i2c-bus = <&i2c4>;
status = "okay";
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
clock-frequency = <100000>;
status = "okay";
rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
};
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
clock-frequency = <100000>;
status = "okay";
touchscreen@55 {
compatible = "sitronix,st1633";
reg = <0x55>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_touch>;
interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
interrupt-parent = <&gpio5>;
gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
status = "disabled";
};
touchscreen@5d {
compatible = "goodix,gt928";
reg = <0x5d>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_touch>;
interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&gpio5>;
irq-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
status = "disabled";
};
};
&i2c4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
clock-frequency = <100000>;
status = "okay";
};
&ldb {
status = "okay";
lvds: lvds-channel@0 {
fsl,data-mapping = "spwg";
fsl,data-width = <24>;
status = "okay";
port@4 {
reg = <4>;
lvds_out: endpoint {
remote-endpoint = <&panel_in_lvds>;
};
};
};
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
&usbh1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbh1>;
disable-over-current;
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
usb1@1 {
compatible = "usb4b4,6570";
reg = <1>;
clocks = <&clks IMX6QDL_CLK_CKO>;
assigned-clocks = <&clks IMX6QDL_CLK_CKO>,
<&clks IMX6QDL_CLK_CKO2_SEL>;
assigned-clock-parents = <&clks IMX6QDL_CLK_CKO2>,
<&clks IMX6QDL_CLK_OSC>;
assigned-clock-rates = <12000000 0>;
};
};
&usbotg {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
dr_mode = "host";
over-current-active-low;
vbus-supply = <&reg_usb_otg_vbus>;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3>;
cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_3v3>;
voltage-ranges = <3300 3300>;
no-1-8-v;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl_hog: hoggrp {
fsl,pins = <
MX6QDL_PAD_RGMII_RD0__GPIO6_IO25 0x1b0b0 /* PMIC_IRQ */
MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x1b0b0
MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x1b0b0
MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0
MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0
MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0
>;
};
pinctrl_backlight: backlightgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x100b1
>;
};
pinctrl_ecspi2: ecspi2grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1
MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1
MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1
MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x100b1
>;
};
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1
>;
};
pinctrl_gpio_keys: gpiokeysgrp {
fsl,pins = <
MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x1b080
MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x1b080
MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b080
>;
};
pinctrl_gpio_leds: gpioledsgrp {
fsl,pins = <
MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1b0b0
>;
};
pinctrl_gpmi_nand: gpminandgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
>;
};
pinctrl_hdmi_cec: hdmicecgrp {
fsl,pins = <
MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x1b8b1
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001f8b1
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001f8b1
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX6QDL_PAD_GPIO_7__I2C4_SCL 0x4001b8b1
MX6QDL_PAD_GPIO_8__I2C4_SDA 0x4001b8b1
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
>;
};
pinctrl_reg_backlight: regbacklightgrp {
fsl,pins = <
MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b1
>;
};
pinctrl_reg_usbotg_vbus: regusbotgvbusgrp {
fsl,pins = <
MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b1
>;
};
pinctrl_touch: touchgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b0
MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b0
>;
};
pinctrl_usbh1: usbh1grp {
fsl,pins = <
MX6QDL_PAD_GPIO_3__USB_H1_OC 0x1b0b1
MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x1b0b0
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b1
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x100b1
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_9__WDOG1_B 0x1b0b0
>;
};
};

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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright 2016 Freescale Semiconductor, Inc.
* Copyright 2017-2018 NXP.
*
*/
#ifndef __DTS_IMX6SLL_PINFUNC_H
#define __DTS_IMX6SLL_PINFUNC_H
/*
* The pin function ID is a tuple of
* <mux_reg conf_reg input_reg mux_mode input_val>
*/
#define MX6SLL_PAD_WDOG_B__WDOG1_B 0x0014 0x02DC 0x0000 0x0 0x0
#define MX6SLL_PAD_WDOG_B__WDOG1_RESET_B_DEB 0x0014 0x02DC 0x0000 0x1 0x0
#define MX6SLL_PAD_WDOG_B__UART5_RI_B 0x0014 0x02DC 0x0000 0x2 0x0
#define MX6SLL_PAD_WDOG_B__GPIO3_IO18 0x0014 0x02DC 0x0000 0x5 0x0
#define MX6SLL_PAD_REF_CLK_24M__XTALOSC_REF_CLK_24M 0x0018 0x02E0 0x0000 0x0 0x0
#define MX6SLL_PAD_REF_CLK_24M__I2C3_SCL 0x0018 0x02E0 0x068C 0x1 0x0
#define MX6SLL_PAD_REF_CLK_24M__PWM3_OUT 0x0018 0x02E0 0x0000 0x2 0x0
#define MX6SLL_PAD_REF_CLK_24M__USB_OTG2_ID 0x0018 0x02E0 0x0560 0x3 0x0
#define MX6SLL_PAD_REF_CLK_24M__CCM_PMIC_READY 0x0018 0x02E0 0x05AC 0x4 0x0
#define MX6SLL_PAD_REF_CLK_24M__GPIO3_IO21 0x0018 0x02E0 0x0000 0x5 0x0
#define MX6SLL_PAD_REF_CLK_24M__SD3_WP 0x0018 0x02E0 0x0794 0x6 0x0
#define MX6SLL_PAD_REF_CLK_32K__XTALOSC_REF_CLK_32K 0x001C 0x02E4 0x0000 0x0 0x0
#define MX6SLL_PAD_REF_CLK_32K__I2C3_SDA 0x001C 0x02E4 0x0690 0x1 0x0
#define MX6SLL_PAD_REF_CLK_32K__PWM4_OUT 0x001C 0x02E4 0x0000 0x2 0x0
#define MX6SLL_PAD_REF_CLK_32K__USB_OTG1_ID 0x001C 0x02E4 0x055C 0x3 0x0
#define MX6SLL_PAD_REF_CLK_32K__SD1_LCTL 0x001C 0x02E4 0x0000 0x4 0x0
#define MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22 0x001C 0x02E4 0x0000 0x5 0x0
#define MX6SLL_PAD_REF_CLK_32K__SD3_CD_B 0x001C 0x02E4 0x0780 0x6 0x0
#define MX6SLL_PAD_PWM1__PWM1_OUT 0x0020 0x02E8 0x0000 0x0 0x0
#define MX6SLL_PAD_PWM1__CCM_CLKO 0x0020 0x02E8 0x0000 0x1 0x0
#define MX6SLL_PAD_PWM1__AUDIO_CLK_OUT 0x0020 0x02E8 0x0000 0x2 0x0
#define MX6SLL_PAD_PWM1__CSI_MCLK 0x0020 0x02E8 0x0000 0x4 0x0
#define MX6SLL_PAD_PWM1__GPIO3_IO23 0x0020 0x02E8 0x0000 0x5 0x0
#define MX6SLL_PAD_PWM1__EPIT1_OUT 0x0020 0x02E8 0x0000 0x6 0x0
#define MX6SLL_PAD_KEY_COL0__KEY_COL0 0x0024 0x02EC 0x06A0 0x0 0x0
#define MX6SLL_PAD_KEY_COL0__I2C2_SCL 0x0024 0x02EC 0x0684 0x1 0x0
#define MX6SLL_PAD_KEY_COL0__LCD_DATA00 0x0024 0x02EC 0x06D8 0x2 0x0
#define MX6SLL_PAD_KEY_COL0__SD1_CD_B 0x0024 0x02EC 0x0770 0x4 0x1
#define MX6SLL_PAD_KEY_COL0__GPIO3_IO24 0x0024 0x02EC 0x0000 0x5 0x0
#define MX6SLL_PAD_KEY_ROW0__KEY_ROW0 0x0028 0x02F0 0x06C0 0x0 0x0
#define MX6SLL_PAD_KEY_ROW0__I2C2_SDA 0x0028 0x02F0 0x0688 0x1 0x0
#define MX6SLL_PAD_KEY_ROW0__LCD_DATA01 0x0028 0x02F0 0x06DC 0x2 0x0
#define MX6SLL_PAD_KEY_ROW0__SD1_WP 0x0028 0x02F0 0x0774 0x4 0x1
#define MX6SLL_PAD_KEY_ROW0__GPIO3_IO25 0x0028 0x02F0 0x0000 0x5 0x0
#define MX6SLL_PAD_KEY_COL1__KEY_COL1 0x002C 0x02F4 0x06A4 0x0 0x0
#define MX6SLL_PAD_KEY_COL1__ECSPI4_MOSI 0x002C 0x02F4 0x0658 0x1 0x1
#define MX6SLL_PAD_KEY_COL1__LCD_DATA02 0x002C 0x02F4 0x06E0 0x2 0x0
#define MX6SLL_PAD_KEY_COL1__SD3_DATA4 0x002C 0x02F4 0x0784 0x4 0x0
#define MX6SLL_PAD_KEY_COL1__GPIO3_IO26 0x002C 0x02F4 0x0000 0x5 0x0
#define MX6SLL_PAD_KEY_ROW1__KEY_ROW1 0x0030 0x02F8 0x06C4 0x0 0x0
#define MX6SLL_PAD_KEY_ROW1__ECSPI4_MISO 0x0030 0x02F8 0x0654 0x1 0x1
#define MX6SLL_PAD_KEY_ROW1__LCD_DATA03 0x0030 0x02F8 0x06E4 0x2 0x0
#define MX6SLL_PAD_KEY_ROW1__CSI_FIELD 0x0030 0x02F8 0x0000 0x3 0x0
#define MX6SLL_PAD_KEY_ROW1__SD3_DATA5 0x0030 0x02F8 0x0788 0x4 0x0
#define MX6SLL_PAD_KEY_ROW1__GPIO3_IO27 0x0030 0x02F8 0x0000 0x5 0x0
#define MX6SLL_PAD_KEY_COL2__KEY_COL2 0x0034 0x02FC 0x06A8 0x0 0x0
#define MX6SLL_PAD_KEY_COL2__ECSPI4_SS0 0x0034 0x02FC 0x065C 0x1 0x1
#define MX6SLL_PAD_KEY_COL2__LCD_DATA04 0x0034 0x02FC 0x06E8 0x2 0x0
#define MX6SLL_PAD_KEY_COL2__CSI_DATA12 0x0034 0x02FC 0x05B8 0x3 0x1
#define MX6SLL_PAD_KEY_COL2__SD3_DATA6 0x0034 0x02FC 0x078C 0x4 0x0
#define MX6SLL_PAD_KEY_COL2__GPIO3_IO28 0x0034 0x02FC 0x0000 0x5 0x0
#define MX6SLL_PAD_KEY_ROW2__KEY_ROW2 0x0038 0x0300 0x06C8 0x0 0x0
#define MX6SLL_PAD_KEY_ROW2__ECSPI4_SCLK 0x0038 0x0300 0x0650 0x1 0x1
#define MX6SLL_PAD_KEY_ROW2__LCD_DATA05 0x0038 0x0300 0x06EC 0x2 0x0
#define MX6SLL_PAD_KEY_ROW2__CSI_DATA13 0x0038 0x0300 0x05BC 0x3 0x1
#define MX6SLL_PAD_KEY_ROW2__SD3_DATA7 0x0038 0x0300 0x0790 0x4 0x0
#define MX6SLL_PAD_KEY_ROW2__GPIO3_IO29 0x0038 0x0300 0x0000 0x5 0x0
#define MX6SLL_PAD_KEY_COL3__KEY_COL3 0x003C 0x0304 0x06AC 0x0 0x0
#define MX6SLL_PAD_KEY_COL3__AUD6_RXFS 0x003C 0x0304 0x05A0 0x1 0x1
#define MX6SLL_PAD_KEY_COL3__LCD_DATA06 0x003C 0x0304 0x06F0 0x2 0x0
#define MX6SLL_PAD_KEY_COL3__CSI_DATA14 0x003C 0x0304 0x05C0 0x3 0x1
#define MX6SLL_PAD_KEY_COL3__GPIO3_IO30 0x003C 0x0304 0x0000 0x5 0x0
#define MX6SLL_PAD_KEY_COL3__SD1_RESET 0x003C 0x0304 0x0000 0x6 0x0
#define MX6SLL_PAD_KEY_ROW3__KEY_ROW3 0x0040 0x0308 0x06CC 0x0 0x1
#define MX6SLL_PAD_KEY_ROW3__AUD6_RXC 0x0040 0x0308 0x059C 0x1 0x1
#define MX6SLL_PAD_KEY_ROW3__LCD_DATA07 0x0040 0x0308 0x06F4 0x2 0x1
#define MX6SLL_PAD_KEY_ROW3__CSI_DATA15 0x0040 0x0308 0x05C4 0x3 0x2
#define MX6SLL_PAD_KEY_ROW3__GPIO3_IO31 0x0040 0x0308 0x0000 0x5 0x0
#define MX6SLL_PAD_KEY_ROW3__SD1_VSELECT 0x0040 0x0308 0x0000 0x6 0x0
#define MX6SLL_PAD_KEY_COL4__KEY_COL4 0x0044 0x030C 0x06B0 0x0 0x1
#define MX6SLL_PAD_KEY_COL4__AUD6_RXD 0x0044 0x030C 0x0594 0x1 0x1
#define MX6SLL_PAD_KEY_COL4__LCD_DATA08 0x0044 0x030C 0x06F8 0x2 0x1
#define MX6SLL_PAD_KEY_COL4__CSI_DATA16 0x0044 0x030C 0x0000 0x3 0x0
#define MX6SLL_PAD_KEY_COL4__GPIO4_IO00 0x0044 0x030C 0x0000 0x5 0x0
#define MX6SLL_PAD_KEY_COL4__USB_OTG1_PWR 0x0044 0x030C 0x0000 0x6 0x0
#define MX6SLL_PAD_KEY_ROW4__KEY_ROW4 0x0048 0x0310 0x06D0 0x0 0x1
#define MX6SLL_PAD_KEY_ROW4__AUD6_TXC 0x0048 0x0310 0x05A4 0x1 0x1
#define MX6SLL_PAD_KEY_ROW4__LCD_DATA09 0x0048 0x0310 0x06FC 0x2 0x1
#define MX6SLL_PAD_KEY_ROW4__CSI_DATA17 0x0048 0x0310 0x0000 0x3 0x0
#define MX6SLL_PAD_KEY_ROW4__GPIO4_IO01 0x0048 0x0310 0x0000 0x5 0x0
#define MX6SLL_PAD_KEY_ROW4__USB_OTG1_OC 0x0048 0x0310 0x076C 0x6 0x2
#define MX6SLL_PAD_KEY_COL5__KEY_COL5 0x004C 0x0314 0x0694 0x0 0x1
#define MX6SLL_PAD_KEY_COL5__AUD6_TXFS 0x004C 0x0314 0x05A8 0x1 0x1
#define MX6SLL_PAD_KEY_COL5__LCD_DATA10 0x004C 0x0314 0x0700 0x2 0x0
#define MX6SLL_PAD_KEY_COL5__CSI_DATA18 0x004C 0x0314 0x0000 0x3 0x0
#define MX6SLL_PAD_KEY_COL5__GPIO4_IO02 0x004C 0x0314 0x0000 0x5 0x0
#define MX6SLL_PAD_KEY_COL5__USB_OTG2_PWR 0x004C 0x0314 0x0000 0x6 0x0
#define MX6SLL_PAD_KEY_ROW5__KEY_ROW5 0x0050 0x0318 0x06B4 0x0 0x2
#define MX6SLL_PAD_KEY_ROW5__AUD6_TXD 0x0050 0x0318 0x0598 0x1 0x1
#define MX6SLL_PAD_KEY_ROW5__LCD_DATA11 0x0050 0x0318 0x0704 0x2 0x1
#define MX6SLL_PAD_KEY_ROW5__CSI_DATA19 0x0050 0x0318 0x0000 0x3 0x0
#define MX6SLL_PAD_KEY_ROW5__GPIO4_IO03 0x0050 0x0318 0x0000 0x5 0x0
#define MX6SLL_PAD_KEY_ROW5__USB_OTG2_OC 0x0050 0x0318 0x0768 0x6 0x3
#define MX6SLL_PAD_KEY_COL6__KEY_COL6 0x0054 0x031C 0x0698 0x0 0x2
#define MX6SLL_PAD_KEY_COL6__UART4_DCE_RX 0x0054 0x031C 0x075C 0x1 0x2
#define MX6SLL_PAD_KEY_COL6__UART4_DTE_TX 0x0054 0x031C 0x0000 0x1 0x0
#define MX6SLL_PAD_KEY_COL6__LCD_DATA12 0x0054 0x031C 0x0708 0x2 0x1
#define MX6SLL_PAD_KEY_COL6__CSI_DATA20 0x0054 0x031C 0x0000 0x3 0x0
#define MX6SLL_PAD_KEY_COL6__GPIO4_IO04 0x0054 0x031C 0x0000 0x5 0x0
#define MX6SLL_PAD_KEY_COL6__SD3_RESET 0x0054 0x031C 0x0000 0x6 0x0
#define MX6SLL_PAD_KEY_ROW6__KEY_ROW6 0x0058 0x0320 0x06B8 0x0 0x2
#define MX6SLL_PAD_KEY_ROW6__UART4_DCE_TX 0x0058 0x0320 0x0000 0x1 0x0
#define MX6SLL_PAD_KEY_ROW6__UART4_DTE_RX 0x0058 0x0320 0x075C 0x1 0x3
#define MX6SLL_PAD_KEY_ROW6__LCD_DATA13 0x0058 0x0320 0x070C 0x2 0x1
#define MX6SLL_PAD_KEY_ROW6__CSI_DATA21 0x0058 0x0320 0x0000 0x3 0x0
#define MX6SLL_PAD_KEY_ROW6__GPIO4_IO05 0x0058 0x0320 0x0000 0x5 0x0
#define MX6SLL_PAD_KEY_ROW6__SD3_VSELECT 0x0058 0x0320 0x0000 0x6 0x0
#define MX6SLL_PAD_KEY_COL7__KEY_COL7 0x005C 0x0324 0x069C 0x0 0x2
#define MX6SLL_PAD_KEY_COL7__UART4_DCE_RTS 0x005C 0x0324 0x0758 0x1 0x2
#define MX6SLL_PAD_KEY_COL7__UART4_DTE_CTS 0x005C 0x0324 0x0000 0x1 0x0
#define MX6SLL_PAD_KEY_COL7__LCD_DATA14 0x005C 0x0324 0x0710 0x2 0x1
#define MX6SLL_PAD_KEY_COL7__CSI_DATA22 0x005C 0x0324 0x0000 0x3 0x0
#define MX6SLL_PAD_KEY_COL7__GPIO4_IO06 0x005C 0x0324 0x0000 0x5 0x0
#define MX6SLL_PAD_KEY_COL7__SD1_WP 0x005C 0x0324 0x0774 0x6 0x3
#define MX6SLL_PAD_KEY_ROW7__KEY_ROW7 0x0060 0x0328 0x06BC 0x0 0x2
#define MX6SLL_PAD_KEY_ROW7__UART4_DCE_CTS 0x0060 0x0328 0x0000 0x1 0x0
#define MX6SLL_PAD_KEY_ROW7__UART4_DTE_RTS 0x0060 0x0328 0x0758 0x1 0x3
#define MX6SLL_PAD_KEY_ROW7__LCD_DATA15 0x0060 0x0328 0x0714 0x2 0x1
#define MX6SLL_PAD_KEY_ROW7__CSI_DATA23 0x0060 0x0328 0x0000 0x3 0x0
#define MX6SLL_PAD_KEY_ROW7__GPIO4_IO07 0x0060 0x0328 0x0000 0x5 0x0
#define MX6SLL_PAD_KEY_ROW7__SD1_CD_B 0x0060 0x0328 0x0770 0x6 0x3
#define MX6SLL_PAD_EPDC_DATA00__EPDC_DATA00 0x0064 0x032C 0x0000 0x0 0x0
#define MX6SLL_PAD_EPDC_DATA00__ECSPI4_MOSI 0x0064 0x032C 0x0658 0x1 0x2
#define MX6SLL_PAD_EPDC_DATA00__LCD_DATA24 0x0064 0x032C 0x0000 0x2 0x0
#define MX6SLL_PAD_EPDC_DATA00__CSI_DATA00 0x0064 0x032C 0x05C8 0x3 0x2
#define MX6SLL_PAD_EPDC_DATA00__GPIO1_IO07 0x0064 0x032C 0x0000 0x5 0x0
#define MX6SLL_PAD_EPDC_DATA01__EPDC_DATA01 0x0068 0x0330 0x0000 0x0 0x0
#define MX6SLL_PAD_EPDC_DATA01__ECSPI4_MISO 0x0068 0x0330 0x0654 0x1 0x2
#define MX6SLL_PAD_EPDC_DATA01__LCD_DATA25 0x0068 0x0330 0x0000 0x2 0x0
#define MX6SLL_PAD_EPDC_DATA01__CSI_DATA01 0x0068 0x0330 0x05CC 0x3 0x2
#define MX6SLL_PAD_EPDC_DATA01__GPIO1_IO08 0x0068 0x0330 0x0000 0x5 0x0
#define MX6SLL_PAD_EPDC_DATA02__EPDC_DATA02 0x006C 0x0334 0x0000 0x0 0x0
#define MX6SLL_PAD_EPDC_DATA02__ECSPI4_SS0 0x006C 0x0334 0x065C 0x1 0x2
#define MX6SLL_PAD_EPDC_DATA02__LCD_DATA26 0x006C 0x0334 0x0000 0x2 0x0
#define MX6SLL_PAD_EPDC_DATA02__CSI_DATA02 0x006C 0x0334 0x05D0 0x3 0x2
#define MX6SLL_PAD_EPDC_DATA02__GPIO1_IO09 0x006C 0x0334 0x0000 0x5 0x0
#define MX6SLL_PAD_EPDC_DATA03__EPDC_DATA03 0x0070 0x0338 0x0000 0x0 0x0
#define MX6SLL_PAD_EPDC_DATA03__ECSPI4_SCLK 0x0070 0x0338 0x0650 0x1 0x2
#define MX6SLL_PAD_EPDC_DATA03__LCD_DATA27 0x0070 0x0338 0x0000 0x2 0x0
#define MX6SLL_PAD_EPDC_DATA03__CSI_DATA03 0x0070 0x0338 0x05D4 0x3 0x2
#define MX6SLL_PAD_EPDC_DATA03__GPIO1_IO10 0x0070 0x0338 0x0000 0x5 0x0
#define MX6SLL_PAD_EPDC_DATA04__EPDC_DATA04 0x0074 0x033C 0x0000 0x0 0x0
#define MX6SLL_PAD_EPDC_DATA04__ECSPI4_SS1 0x0074 0x033C 0x0660 0x1 0x1
#define MX6SLL_PAD_EPDC_DATA04__LCD_DATA28 0x0074 0x033C 0x0000 0x2 0x0
#define MX6SLL_PAD_EPDC_DATA04__CSI_DATA04 0x0074 0x033C 0x05D8 0x3 0x2
#define MX6SLL_PAD_EPDC_DATA04__GPIO1_IO11 0x0074 0x033C 0x0000 0x5 0x0
#define MX6SLL_PAD_EPDC_DATA05__EPDC_DATA05 0x0078 0x0340 0x0000 0x0 0x0
#define MX6SLL_PAD_EPDC_DATA05__ECSPI4_SS2 0x0078 0x0340 0x0664 0x1 0x1
#define MX6SLL_PAD_EPDC_DATA05__LCD_DATA29 0x0078 0x0340 0x0000 0x2 0x0
#define MX6SLL_PAD_EPDC_DATA05__CSI_DATA05 0x0078 0x0340 0x05DC 0x3 0x2
#define MX6SLL_PAD_EPDC_DATA05__GPIO1_IO12 0x0078 0x0340 0x0000 0x5 0x0
#define MX6SLL_PAD_EPDC_DATA06__EPDC_DATA06 0x007C 0x0344 0x0000 0x0 0x0
#define MX6SLL_PAD_EPDC_DATA06__ECSPI4_SS3 0x007C 0x0344 0x0000 0x1 0x0
#define MX6SLL_PAD_EPDC_DATA06__LCD_DATA30 0x007C 0x0344 0x0000 0x2 0x0
#define MX6SLL_PAD_EPDC_DATA06__CSI_DATA06 0x007C 0x0344 0x05E0 0x3 0x2
#define MX6SLL_PAD_EPDC_DATA06__GPIO1_IO13 0x007C 0x0344 0x0000 0x5 0x0
#define MX6SLL_PAD_EPDC_DATA07__EPDC_DATA07 0x0080 0x0348 0x0000 0x0 0x0
#define MX6SLL_PAD_EPDC_DATA07__ECSPI4_RDY 0x0080 0x0348 0x0000 0x1 0x0
#define MX6SLL_PAD_EPDC_DATA07__LCD_DATA31 0x0080 0x0348 0x0000 0x2 0x0
#define MX6SLL_PAD_EPDC_DATA07__CSI_DATA07 0x0080 0x0348 0x05E4 0x3 0x2
#define MX6SLL_PAD_EPDC_DATA07__GPIO1_IO14 0x0080 0x0348 0x0000 0x5 0x0
#define MX6SLL_PAD_EPDC_DATA08__EPDC_DATA08 0x0084 0x034C 0x0000 0x0 0x0
#define MX6SLL_PAD_EPDC_DATA08__ECSPI3_MOSI 0x0084 0x034C 0x063C 0x1 0x2
#define MX6SLL_PAD_EPDC_DATA08__EPDC_PWR_CTRL0 0x0084 0x034C 0x0000 0x2 0x0
#define MX6SLL_PAD_EPDC_DATA08__GPIO1_IO15 0x0084 0x034C 0x0000 0x5 0x0
#define MX6SLL_PAD_EPDC_DATA09__EPDC_DATA09 0x0088 0x0350 0x0000 0x0 0x0
#define MX6SLL_PAD_EPDC_DATA09__ECSPI3_MISO 0x0088 0x0350 0x0638 0x1 0x2
#define MX6SLL_PAD_EPDC_DATA09__EPDC_PWR_CTRL1 0x0088 0x0350 0x0000 0x2 0x0
#define MX6SLL_PAD_EPDC_DATA09__GPIO1_IO16 0x0088 0x0350 0x0000 0x5 0x0
#define MX6SLL_PAD_EPDC_DATA10__EPDC_DATA10 0x008C 0x0354 0x0000 0x0 0x0
#define MX6SLL_PAD_EPDC_DATA10__ECSPI3_SS0 0x008C 0x0354 0x0648 0x1 0x2
#define MX6SLL_PAD_EPDC_DATA10__EPDC_PWR_CTRL2 0x008C 0x0354 0x0000 0x2 0x0
#define MX6SLL_PAD_EPDC_DATA10__GPIO1_IO17 0x008C 0x0354 0x0000 0x5 0x0
#define MX6SLL_PAD_EPDC_DATA11__EPDC_DATA11 0x0090 0x0358 0x0000 0x0 0x0
#define MX6SLL_PAD_EPDC_DATA11__ECSPI3_SCLK 0x0090 0x0358 0x0630 0x1 0x2
#define MX6SLL_PAD_EPDC_DATA11__EPDC_PWR_CTRL3 0x0090 0x0358 0x0000 0x2 0x0
#define MX6SLL_PAD_EPDC_DATA11__GPIO1_IO18 0x0090 0x0358 0x0000 0x5 0x0
#define MX6SLL_PAD_EPDC_DATA12__EPDC_DATA12 0x0094 0x035C 0x0000 0x0 0x0
#define MX6SLL_PAD_EPDC_DATA12__UART2_DCE_RX 0x0094 0x035C 0x074C 0x1 0x4
#define MX6SLL_PAD_EPDC_DATA12__UART2_DTE_TX 0x0094 0x035C 0x0000 0x1 0x0
#define MX6SLL_PAD_EPDC_DATA12__EPDC_PWR_COM 0x0094 0x035C 0x0000 0x2 0x0
#define MX6SLL_PAD_EPDC_DATA12__GPIO1_IO19 0x0094 0x035C 0x0000 0x5 0x0
#define MX6SLL_PAD_EPDC_DATA12__ECSPI3_SS1 0x0094 0x035C 0x064C 0x6 0x1
#define MX6SLL_PAD_EPDC_DATA13__EPDC_DATA13 0x0098 0x0360 0x0000 0x0 0x0
#define MX6SLL_PAD_EPDC_DATA13__UART2_DCE_TX 0x0098 0x0360 0x0000 0x1 0x0
#define MX6SLL_PAD_EPDC_DATA13__UART2_DTE_RX 0x0098 0x0360 0x074C 0x1 0x5
#define MX6SLL_PAD_EPDC_DATA13__EPDC_PWR_IRQ 0x0098 0x0360 0x0668 0x2 0x0
#define MX6SLL_PAD_EPDC_DATA13__GPIO1_IO20 0x0098 0x0360 0x0000 0x5 0x0
#define MX6SLL_PAD_EPDC_DATA13__ECSPI3_SS2 0x0098 0x0360 0x0640 0x6 0x1
#define MX6SLL_PAD_EPDC_DATA14__EPDC_DATA14 0x009C 0x0364 0x0000 0x0 0x0
#define MX6SLL_PAD_EPDC_DATA14__UART2_DCE_RTS 0x009C 0x0364 0x0748 0x1 0x4
#define MX6SLL_PAD_EPDC_DATA14__UART2_DTE_CTS 0x009C 0x0364 0x0000 0x1 0x0
#define MX6SLL_PAD_EPDC_DATA14__EPDC_PWR_STAT 0x009C 0x0364 0x066C 0x2 0x0
#define MX6SLL_PAD_EPDC_DATA14__GPIO1_IO21 0x009C 0x0364 0x0000 0x5 0x0
#define MX6SLL_PAD_EPDC_DATA14__ECSPI3_SS3 0x009C 0x0364 0x0644 0x6 0x1
#define MX6SLL_PAD_EPDC_DATA15__EPDC_DATA15 0x00A0 0x0368 0x0000 0x0 0x0
#define MX6SLL_PAD_EPDC_DATA15__UART2_DCE_CTS 0x00A0 0x0368 0x0000 0x1 0x0
#define MX6SLL_PAD_EPDC_DATA15__UART2_DTE_RTS 0x00A0 0x0368 0x0748 0x1 0x5
#define MX6SLL_PAD_EPDC_DATA15__EPDC_PWR_WAKE 0x00A0 0x0368 0x0000 0x2 0x0
#define MX6SLL_PAD_EPDC_DATA15__GPIO1_IO22 0x00A0 0x0368 0x0000 0x5 0x0
#define MX6SLL_PAD_EPDC_DATA15__ECSPI3_RDY 0x00A0 0x0368 0x0634 0x6 0x1
#define MX6SLL_PAD_EPDC_SDCLK__EPDC_SDCLK_P 0x00A4 0x036C 0x0000 0x0 0x0
#define MX6SLL_PAD_EPDC_SDCLK__ECSPI2_MOSI 0x00A4 0x036C 0x0624 0x1 0x2
#define MX6SLL_PAD_EPDC_SDCLK__I2C2_SCL 0x00A4 0x036C 0x0684 0x2 0x2
#define MX6SLL_PAD_EPDC_SDCLK__CSI_DATA08 0x00A4 0x036C 0x05E8 0x3 0x2
#define MX6SLL_PAD_EPDC_SDCLK__GPIO1_IO23 0x00A4 0x036C 0x0000 0x5 0x0
#define MX6SLL_PAD_EPDC_SDLE__EPDC_SDLE 0x00A8 0x0370 0x0000 0x0 0x0
#define MX6SLL_PAD_EPDC_SDLE__ECSPI2_MISO 0x00A8 0x0370 0x0620 0x1 0x2
#define MX6SLL_PAD_EPDC_SDLE__I2C2_SDA 0x00A8 0x0370 0x0688 0x2 0x2
#define MX6SLL_PAD_EPDC_SDLE__CSI_DATA09 0x00A8 0x0370 0x05EC 0x3 0x2
#define MX6SLL_PAD_EPDC_SDLE__GPIO1_IO24 0x00A8 0x0370 0x0000 0x5 0x0
#define MX6SLL_PAD_EPDC_SDOE__EPDC_SDOE 0x00AC 0x0374 0x0000 0x0 0x0
#define MX6SLL_PAD_EPDC_SDOE__ECSPI2_SS0 0x00AC 0x0374 0x0628 0x1 0x1
#define MX6SLL_PAD_EPDC_SDOE__CSI_DATA10 0x00AC 0x0374 0x05B0 0x3 0x2
#define MX6SLL_PAD_EPDC_SDOE__GPIO1_IO25 0x00AC 0x0374 0x0000 0x5 0x0
#define MX6SLL_PAD_EPDC_SDSHR__EPDC_SDSHR 0x00B0 0x0378 0x0000 0x0 0x0
#define MX6SLL_PAD_EPDC_SDSHR__ECSPI2_SCLK 0x00B0 0x0378 0x061C 0x1 0x2
#define MX6SLL_PAD_EPDC_SDSHR__EPDC_SDCE4 0x00B0 0x0378 0x0000 0x2 0x0
#define MX6SLL_PAD_EPDC_SDSHR__CSI_DATA11 0x00B0 0x0378 0x05B4 0x3 0x2
#define MX6SLL_PAD_EPDC_SDSHR__GPIO1_IO26 0x00B0 0x0378 0x0000 0x5 0x0
#define MX6SLL_PAD_EPDC_SDCE0__EPDC_SDCE0 0x00B4 0x037C 0x0000 0x0 0x0
#define MX6SLL_PAD_EPDC_SDCE0__ECSPI2_SS1 0x00B4 0x037C 0x062C 0x1 0x1
#define MX6SLL_PAD_EPDC_SDCE0__PWM3_OUT 0x00B4 0x037C 0x0000 0x2 0x0
#define MX6SLL_PAD_EPDC_SDCE0__GPIO1_IO27 0x00B4 0x037C 0x0000 0x5 0x0
#define MX6SLL_PAD_EPDC_SDCE1__EPDC_SDCE1 0x00B8 0x0380 0x0000 0x0 0x0
#define MX6SLL_PAD_EPDC_SDCE1__WDOG2_B 0x00B8 0x0380 0x0000 0x1 0x0
#define MX6SLL_PAD_EPDC_SDCE1__PWM4_OUT 0x00B8 0x0380 0x0000 0x2 0x0
#define MX6SLL_PAD_EPDC_SDCE1__GPIO1_IO28 0x00B8 0x0380 0x0000 0x5 0x0
#define MX6SLL_PAD_EPDC_SDCE2__EPDC_SDCE2 0x00BC 0x0384 0x0000 0x0 0x0
#define MX6SLL_PAD_EPDC_SDCE2__I2C3_SCL 0x00BC 0x0384 0x068C 0x1 0x2
#define MX6SLL_PAD_EPDC_SDCE2__PWM1_OUT 0x00BC 0x0384 0x0000 0x2 0x0
#define MX6SLL_PAD_EPDC_SDCE2__GPIO1_IO29 0x00BC 0x0384 0x0000 0x5 0x0
#define MX6SLL_PAD_EPDC_SDCE3__EPDC_SDCE3 0x00C0 0x0388 0x0000 0x0 0x0
#define MX6SLL_PAD_EPDC_SDCE3__I2C3_SDA 0x00C0 0x0388 0x0690 0x1 0x2
#define MX6SLL_PAD_EPDC_SDCE3__PWM2_OUT 0x00C0 0x0388 0x0000 0x2 0x0
#define MX6SLL_PAD_EPDC_SDCE3__GPIO1_IO30 0x00C0 0x0388 0x0000 0x5 0x0
#define MX6SLL_PAD_EPDC_GDCLK__EPDC_GDCLK 0x00C4 0x038C 0x0000 0x0 0x0
#define MX6SLL_PAD_EPDC_GDCLK__ECSPI2_SS2 0x00C4 0x038C 0x0000 0x1 0x0
#define MX6SLL_PAD_EPDC_GDCLK__CSI_PIXCLK 0x00C4 0x038C 0x05F4 0x3 0x2
#define MX6SLL_PAD_EPDC_GDCLK__GPIO1_IO31 0x00C4 0x038C 0x0000 0x5 0x0
#define MX6SLL_PAD_EPDC_GDCLK__SD2_RESET 0x00C4 0x038C 0x0000 0x6 0x0
#define MX6SLL_PAD_EPDC_GDOE__EPDC_GDOE 0x00C8 0x0390 0x0000 0x0 0x0
#define MX6SLL_PAD_EPDC_GDOE__ECSPI2_SS3 0x00C8 0x0390 0x0000 0x1 0x0
#define MX6SLL_PAD_EPDC_GDOE__CSI_HSYNC 0x00C8 0x0390 0x05F0 0x3 0x2
#define MX6SLL_PAD_EPDC_GDOE__GPIO2_IO00 0x00C8 0x0390 0x0000 0x5 0x0
#define MX6SLL_PAD_EPDC_GDOE__SD2_VSELECT 0x00C8 0x0390 0x0000 0x6 0x0
#define MX6SLL_PAD_EPDC_GDRL__EPDC_GDRL 0x00CC 0x0394 0x0000 0x0 0x0
#define MX6SLL_PAD_EPDC_GDRL__ECSPI2_RDY 0x00CC 0x0394 0x0000 0x1 0x0
#define MX6SLL_PAD_EPDC_GDRL__CSI_MCLK 0x00CC 0x0394 0x0000 0x3 0x0
#define MX6SLL_PAD_EPDC_GDRL__GPIO2_IO01 0x00CC 0x0394 0x0000 0x5 0x0
#define MX6SLL_PAD_EPDC_GDRL__SD2_WP 0x00CC 0x0394 0x077C 0x6 0x2
#define MX6SLL_PAD_EPDC_GDSP__EPDC_GDSP 0x00D0 0x0398 0x0000 0x0 0x0
#define MX6SLL_PAD_EPDC_GDSP__PWM4_OUT 0x00D0 0x0398 0x0000 0x1 0x0
#define MX6SLL_PAD_EPDC_GDSP__CSI_VSYNC 0x00D0 0x0398 0x05F8 0x3 0x2
#define MX6SLL_PAD_EPDC_GDSP__GPIO2_IO02 0x00D0 0x0398 0x0000 0x5 0x0
#define MX6SLL_PAD_EPDC_GDSP__SD2_CD_B 0x00D0 0x0398 0x0778 0x6 0x2
#define MX6SLL_PAD_EPDC_VCOM0__EPDC_VCOM0 0x00D4 0x039C 0x0000 0x0 0x0
#define MX6SLL_PAD_EPDC_VCOM0__AUD5_RXFS 0x00D4 0x039C 0x0588 0x1 0x1
#define MX6SLL_PAD_EPDC_VCOM0__UART3_DCE_RX 0x00D4 0x039C 0x0754 0x2 0x4
#define MX6SLL_PAD_EPDC_VCOM0__UART3_DTE_TX 0x00D4 0x039C 0x0000 0x2 0x0
#define MX6SLL_PAD_EPDC_VCOM0__GPIO2_IO03 0x00D4 0x039C 0x0000 0x5 0x0
#define MX6SLL_PAD_EPDC_VCOM0__EPDC_SDCE5 0x00D4 0x039C 0x0000 0x6 0x0
#define MX6SLL_PAD_EPDC_VCOM1__EPDC_VCOM1 0x00D8 0x03A0 0x0000 0x0 0x0
#define MX6SLL_PAD_EPDC_VCOM1__AUD5_RXD 0x00D8 0x03A0 0x057C 0x1 0x1
#define MX6SLL_PAD_EPDC_VCOM1__UART3_DCE_TX 0x00D8 0x03A0 0x0000 0x2 0x0
#define MX6SLL_PAD_EPDC_VCOM1__UART3_DTE_RX 0x00D8 0x03A0 0x0754 0x2 0x5
#define MX6SLL_PAD_EPDC_VCOM1__GPIO2_IO04 0x00D8 0x03A0 0x0000 0x5 0x0
#define MX6SLL_PAD_EPDC_VCOM1__EPDC_SDCE6 0x00D8 0x03A0 0x0000 0x6 0x0
#define MX6SLL_PAD_EPDC_BDR0__EPDC_BDR0 0x00DC 0x03A4 0x0000 0x0 0x0
#define MX6SLL_PAD_EPDC_BDR0__UART3_DCE_RTS 0x00DC 0x03A4 0x0750 0x2 0x2
#define MX6SLL_PAD_EPDC_BDR0__UART3_DTE_CTS 0x00DC 0x03A4 0x0000 0x2 0x0
#define MX6SLL_PAD_EPDC_BDR0__GPIO2_IO05 0x00DC 0x03A4 0x0000 0x5 0x0
#define MX6SLL_PAD_EPDC_BDR0__EPDC_SDCE7 0x00DC 0x03A4 0x0000 0x6 0x0
#define MX6SLL_PAD_EPDC_BDR1__EPDC_BDR1 0x00E0 0x03A8 0x0000 0x0 0x0
#define MX6SLL_PAD_EPDC_BDR1__UART3_DCE_CTS 0x00E0 0x03A8 0x0000 0x2 0x0
#define MX6SLL_PAD_EPDC_BDR1__UART3_DTE_RTS 0x00E0 0x03A8 0x0750 0x2 0x3
#define MX6SLL_PAD_EPDC_BDR1__GPIO2_IO06 0x00E0 0x03A8 0x0000 0x5 0x0
#define MX6SLL_PAD_EPDC_BDR1__EPDC_SDCE8 0x00E0 0x03A8 0x0000 0x6 0x0
#define MX6SLL_PAD_EPDC_PWR_CTRL0__EPDC_PWR_CTRL0 0x00E4 0x03AC 0x0000 0x0 0x0
#define MX6SLL_PAD_EPDC_PWR_CTRL0__AUD5_RXC 0x00E4 0x03AC 0x0584 0x1 0x1
#define MX6SLL_PAD_EPDC_PWR_CTRL0__LCD_DATA16 0x00E4 0x03AC 0x0718 0x2 0x1
#define MX6SLL_PAD_EPDC_PWR_CTRL0__GPIO2_IO07 0x00E4 0x03AC 0x0000 0x5 0x0
#define MX6SLL_PAD_EPDC_PWR_CTRL1__EPDC_PWR_CTRL1 0x00E8 0x03B0 0x0000 0x0 0x0
#define MX6SLL_PAD_EPDC_PWR_CTRL1__AUD5_TXFS 0x00E8 0x03B0 0x0590 0x1 0x1
#define MX6SLL_PAD_EPDC_PWR_CTRL1__LCD_DATA17 0x00E8 0x03B0 0x071C 0x2 0x1
#define MX6SLL_PAD_EPDC_PWR_CTRL1__GPIO2_IO08 0x00E8 0x03B0 0x0000 0x5 0x0
#define MX6SLL_PAD_EPDC_PWR_CTRL2__EPDC_PWR_CTRL2 0x00EC 0x03B4 0x0000 0x0 0x0
#define MX6SLL_PAD_EPDC_PWR_CTRL2__AUD5_TXD 0x00EC 0x03B4 0x0580 0x1 0x1
#define MX6SLL_PAD_EPDC_PWR_CTRL2__LCD_DATA18 0x00EC 0x03B4 0x0720 0x2 0x1
#define MX6SLL_PAD_EPDC_PWR_CTRL2__GPIO2_IO09 0x00EC 0x03B4 0x0000 0x5 0x0
#define MX6SLL_PAD_EPDC_PWR_CTRL3__EPDC_PWR_CTRL3 0x00F0 0x03B8 0x0000 0x0 0x0
#define MX6SLL_PAD_EPDC_PWR_CTRL3__AUD5_TXC 0x00F0 0x03B8 0x058C 0x1 0x1
#define MX6SLL_PAD_EPDC_PWR_CTRL3__LCD_DATA19 0x00F0 0x03B8 0x0724 0x2 0x1
#define MX6SLL_PAD_EPDC_PWR_CTRL3__GPIO2_IO10 0x00F0 0x03B8 0x0000 0x5 0x0
#define MX6SLL_PAD_EPDC_PWR_COM__EPDC_PWR_COM 0x00F4 0x03BC 0x0000 0x0 0x0
#define MX6SLL_PAD_EPDC_PWR_COM__LCD_DATA20 0x00F4 0x03BC 0x0728 0x2 0x1
#define MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 0x00F4 0x03BC 0x055C 0x4 0x4
#define MX6SLL_PAD_EPDC_PWR_COM__GPIO2_IO11 0x00F4 0x03BC 0x0000 0x5 0x0
#define MX6SLL_PAD_EPDC_PWR_COM__SD3_RESET 0x00F4 0x03BC 0x0000 0x6 0x0
#define MX6SLL_PAD_EPDC_PWR_IRQ__EPDC_PWR_IRQ 0x00F8 0x03C0 0x0668 0x0 0x1
#define MX6SLL_PAD_EPDC_PWR_IRQ__LCD_DATA21 0x00F8 0x03C0 0x072C 0x2 0x1
#define MX6SLL_PAD_EPDC_PWR_IRQ__USB_OTG2_ID 0x00F8 0x03C0 0x0560 0x4 0x3
#define MX6SLL_PAD_EPDC_PWR_IRQ__GPIO2_IO12 0x00F8 0x03C0 0x0000 0x5 0x0
#define MX6SLL_PAD_EPDC_PWR_IRQ__SD3_VSELECT 0x00F8 0x03C0 0x0000 0x6 0x0
#define MX6SLL_PAD_EPDC_PWR_STAT__EPDC_PWR_STAT 0x00FC 0x03C4 0x066C 0x0 0x1
#define MX6SLL_PAD_EPDC_PWR_STAT__LCD_DATA22 0x00FC 0x03C4 0x0730 0x2 0x1
#define MX6SLL_PAD_EPDC_PWR_STAT__ARM_EVENTI 0x00FC 0x03C4 0x0000 0x4 0x0
#define MX6SLL_PAD_EPDC_PWR_STAT__GPIO2_IO13 0x00FC 0x03C4 0x0000 0x5 0x0
#define MX6SLL_PAD_EPDC_PWR_STAT__SD3_WP 0x00FC 0x03C4 0x0794 0x6 0x2
#define MX6SLL_PAD_EPDC_PWR_WAKE__EPDC_PWR_WAKE 0x0100 0x03C8 0x0000 0x0 0x0
#define MX6SLL_PAD_EPDC_PWR_WAKE__LCD_DATA23 0x0100 0x03C8 0x0734 0x2 0x1
#define MX6SLL_PAD_EPDC_PWR_WAKE__ARM_EVENTO 0x0100 0x03C8 0x0000 0x4 0x0
#define MX6SLL_PAD_EPDC_PWR_WAKE__GPIO2_IO14 0x0100 0x03C8 0x0000 0x5 0x0
#define MX6SLL_PAD_EPDC_PWR_WAKE__SD3_CD_B 0x0100 0x03C8 0x0780 0x6 0x2
#define MX6SLL_PAD_LCD_CLK__LCD_CLK 0x0104 0x03CC 0x0000 0x0 0x0
#define MX6SLL_PAD_LCD_CLK__LCD_WR_RWN 0x0104 0x03CC 0x0000 0x2 0x0
#define MX6SLL_PAD_LCD_CLK__PWM4_OUT 0x0104 0x03CC 0x0000 0x4 0x0
#define MX6SLL_PAD_LCD_CLK__GPIO2_IO15 0x0104 0x03CC 0x0000 0x5 0x0
#define MX6SLL_PAD_LCD_ENABLE__LCD_ENABLE 0x0108 0x03D0 0x0000 0x0 0x0
#define MX6SLL_PAD_LCD_ENABLE__LCD_RD_E 0x0108 0x03D0 0x0000 0x2 0x0
#define MX6SLL_PAD_LCD_ENABLE__UART2_DCE_RX 0x0108 0x03D0 0x0000 0x4 0x0
#define MX6SLL_PAD_LCD_ENABLE__UART2_DTE_TX 0x0108 0x03D0 0x0000 0x4 0x0
#define MX6SLL_PAD_LCD_ENABLE__GPIO2_IO16 0x0108 0x03D0 0x0000 0x5 0x0
#define MX6SLL_PAD_LCD_HSYNC__LCD_HSYNC 0x010C 0x03D4 0x06D4 0x0 0x0
#define MX6SLL_PAD_LCD_HSYNC__LCD_CS 0x010C 0x03D4 0x0000 0x2 0x0
#define MX6SLL_PAD_LCD_HSYNC__UART2_DCE_TX 0x010C 0x03D4 0x0000 0x4 0x0
#define MX6SLL_PAD_LCD_HSYNC__UART2_DTE_RX 0x010C 0x03D4 0x074C 0x4 0x1
#define MX6SLL_PAD_LCD_HSYNC__GPIO2_IO17 0x010C 0x03D4 0x0000 0x5 0x0
#define MX6SLL_PAD_LCD_HSYNC__ARM_TRACE_CLK 0x010C 0x03D4 0x0000 0x6 0x0
#define MX6SLL_PAD_LCD_VSYNC__LCD_VSYNC 0x0110 0x03D8 0x0000 0x0 0x0
#define MX6SLL_PAD_LCD_VSYNC__LCD_RS 0x0110 0x03D8 0x0000 0x2 0x0
#define MX6SLL_PAD_LCD_VSYNC__UART2_DCE_RTS 0x0110 0x03D8 0x0748 0x4 0x0
#define MX6SLL_PAD_LCD_VSYNC__UART2_DTE_CTS 0x0110 0x03D8 0x0000 0x4 0x0
#define MX6SLL_PAD_LCD_VSYNC__GPIO2_IO18 0x0110 0x03D8 0x0000 0x5 0x0
#define MX6SLL_PAD_LCD_VSYNC__ARM_TRACE_CTL 0x0110 0x03D8 0x0000 0x6 0x0
#define MX6SLL_PAD_LCD_RESET__LCD_RESET 0x0114 0x03DC 0x0000 0x0 0x0
#define MX6SLL_PAD_LCD_RESET__LCD_BUSY 0x0114 0x03DC 0x06D4 0x2 0x1
#define MX6SLL_PAD_LCD_RESET__UART2_DCE_CTS 0x0114 0x03DC 0x0000 0x4 0x0
#define MX6SLL_PAD_LCD_RESET__UART2_DTE_RTS 0x0114 0x03DC 0x0748 0x4 0x1
#define MX6SLL_PAD_LCD_RESET__GPIO2_IO19 0x0114 0x03DC 0x0000 0x5 0x0
#define MX6SLL_PAD_LCD_RESET__CCM_PMIC_READY 0x0114 0x03DC 0x05AC 0x6 0x2
#define MX6SLL_PAD_LCD_DATA00__LCD_DATA00 0x0118 0x03E0 0x06D8 0x0 0x1
#define MX6SLL_PAD_LCD_DATA00__ECSPI1_MOSI 0x0118 0x03E0 0x0608 0x1 0x0
#define MX6SLL_PAD_LCD_DATA00__USB_OTG2_ID 0x0118 0x03E0 0x0560 0x2 0x2
#define MX6SLL_PAD_LCD_DATA00__PWM1_OUT 0x0118 0x03E0 0x0000 0x3 0x0
#define MX6SLL_PAD_LCD_DATA00__UART5_DTR_B 0x0118 0x03E0 0x0000 0x4 0x0
#define MX6SLL_PAD_LCD_DATA00__GPIO2_IO20 0x0118 0x03E0 0x0000 0x5 0x0
#define MX6SLL_PAD_LCD_DATA00__ARM_TRACE00 0x0118 0x03E0 0x0000 0x6 0x0
#define MX6SLL_PAD_LCD_DATA00__SRC_BOOT_CFG00 0x0118 0x03E0 0x0000 0x7 0x0
#define MX6SLL_PAD_LCD_DATA01__LCD_DATA01 0x011C 0x03E4 0x06DC 0x0 0x1
#define MX6SLL_PAD_LCD_DATA01__ECSPI1_MISO 0x011C 0x03E4 0x0604 0x1 0x0
#define MX6SLL_PAD_LCD_DATA01__USB_OTG1_ID 0x011C 0x03E4 0x055C 0x2 0x3
#define MX6SLL_PAD_LCD_DATA01__PWM2_OUT 0x011C 0x03E4 0x0000 0x3 0x0
#define MX6SLL_PAD_LCD_DATA01__AUD4_RXFS 0x011C 0x03E4 0x0570 0x4 0x0
#define MX6SLL_PAD_LCD_DATA01__GPIO2_IO21 0x011C 0x03E4 0x0000 0x5 0x0
#define MX6SLL_PAD_LCD_DATA01__ARM_TRACE01 0x011C 0x03E4 0x0000 0x6 0x0
#define MX6SLL_PAD_LCD_DATA01__SRC_BOOT_CFG01 0x011C 0x03E4 0x0000 0x7 0x0
#define MX6SLL_PAD_LCD_DATA02__LCD_DATA02 0x0120 0x03E8 0x06E0 0x0 0x1
#define MX6SLL_PAD_LCD_DATA02__ECSPI1_SS0 0x0120 0x03E8 0x0614 0x1 0x0
#define MX6SLL_PAD_LCD_DATA02__EPIT2_OUT 0x0120 0x03E8 0x0000 0x2 0x0
#define MX6SLL_PAD_LCD_DATA02__PWM3_OUT 0x0120 0x03E8 0x0000 0x3 0x0
#define MX6SLL_PAD_LCD_DATA02__AUD4_RXC 0x0120 0x03E8 0x056C 0x4 0x0
#define MX6SLL_PAD_LCD_DATA02__GPIO2_IO22 0x0120 0x03E8 0x0000 0x5 0x0
#define MX6SLL_PAD_LCD_DATA02__ARM_TRACE02 0x0120 0x03E8 0x0000 0x6 0x0
#define MX6SLL_PAD_LCD_DATA02__SRC_BOOT_CFG02 0x0120 0x03E8 0x0000 0x7 0x0
#define MX6SLL_PAD_LCD_DATA03__LCD_DATA03 0x0124 0x03EC 0x06E4 0x0 0x1
#define MX6SLL_PAD_LCD_DATA03__ECSPI1_SCLK 0x0124 0x03EC 0x05FC 0x1 0x0
#define MX6SLL_PAD_LCD_DATA03__UART5_DSR_B 0x0124 0x03EC 0x0000 0x2 0x0
#define MX6SLL_PAD_LCD_DATA03__PWM4_OUT 0x0124 0x03EC 0x0000 0x3 0x0
#define MX6SLL_PAD_LCD_DATA03__AUD4_RXD 0x0124 0x03EC 0x0564 0x4 0x0
#define MX6SLL_PAD_LCD_DATA03__GPIO2_IO23 0x0124 0x03EC 0x0000 0x5 0x0
#define MX6SLL_PAD_LCD_DATA03__ARM_TRACE03 0x0124 0x03EC 0x0000 0x6 0x0
#define MX6SLL_PAD_LCD_DATA03__SRC_BOOT_CFG03 0x0124 0x03EC 0x0000 0x7 0x0
#define MX6SLL_PAD_LCD_DATA04__LCD_DATA04 0x0128 0x03F0 0x06E8 0x0 0x1
#define MX6SLL_PAD_LCD_DATA04__ECSPI1_SS1 0x0128 0x03F0 0x060C 0x1 0x1
#define MX6SLL_PAD_LCD_DATA04__CSI_VSYNC 0x0128 0x03F0 0x05F8 0x2 0x0
#define MX6SLL_PAD_LCD_DATA04__WDOG2_RESET_B_DEB 0x0128 0x03F0 0x0000 0x3 0x0
#define MX6SLL_PAD_LCD_DATA04__AUD4_TXC 0x0128 0x03F0 0x0574 0x4 0x0
#define MX6SLL_PAD_LCD_DATA04__GPIO2_IO24 0x0128 0x03F0 0x0000 0x5 0x0
#define MX6SLL_PAD_LCD_DATA04__ARM_TRACE04 0x0128 0x03F0 0x0000 0x6 0x0
#define MX6SLL_PAD_LCD_DATA04__SRC_BOOT_CFG04 0x0128 0x03F0 0x0000 0x7 0x0
#define MX6SLL_PAD_LCD_DATA05__LCD_DATA05 0x012C 0x03F4 0x06EC 0x0 0x1
#define MX6SLL_PAD_LCD_DATA05__ECSPI1_SS2 0x012C 0x03F4 0x0610 0x1 0x1
#define MX6SLL_PAD_LCD_DATA05__CSI_HSYNC 0x012C 0x03F4 0x05F0 0x2 0x0
#define MX6SLL_PAD_LCD_DATA05__AUD4_TXFS 0x012C 0x03F4 0x0578 0x4 0x0
#define MX6SLL_PAD_LCD_DATA05__GPIO2_IO25 0x012C 0x03F4 0x0000 0x5 0x0
#define MX6SLL_PAD_LCD_DATA05__ARM_TRACE05 0x012C 0x03F4 0x0000 0x6 0x0
#define MX6SLL_PAD_LCD_DATA05__SRC_BOOT_CFG05 0x012C 0x03F4 0x0000 0x7 0x0
#define MX6SLL_PAD_LCD_DATA06__LCD_DATA06 0x0130 0x03F8 0x06F0 0x0 0x1
#define MX6SLL_PAD_LCD_DATA06__ECSPI1_SS3 0x0130 0x03F8 0x0618 0x1 0x0
#define MX6SLL_PAD_LCD_DATA06__CSI_PIXCLK 0x0130 0x03F8 0x05F4 0x2 0x0
#define MX6SLL_PAD_LCD_DATA06__AUD4_TXD 0x0130 0x03F8 0x0568 0x4 0x0
#define MX6SLL_PAD_LCD_DATA06__GPIO2_IO26 0x0130 0x03F8 0x0000 0x5 0x0
#define MX6SLL_PAD_LCD_DATA06__ARM_TRACE06 0x0130 0x03F8 0x0000 0x6 0x0
#define MX6SLL_PAD_LCD_DATA06__SRC_BOOT_CFG06 0x0130 0x03F8 0x0000 0x7 0x0
#define MX6SLL_PAD_LCD_DATA07__LCD_DATA07 0x0134 0x03FC 0x06F4 0x0 0x0
#define MX6SLL_PAD_LCD_DATA07__ECSPI1_RDY 0x0134 0x03FC 0x0600 0x1 0x0
#define MX6SLL_PAD_LCD_DATA07__CSI_MCLK 0x0134 0x03FC 0x0000 0x2 0x0
#define MX6SLL_PAD_LCD_DATA07__AUDIO_CLK_OUT 0x0134 0x03FC 0x0000 0x4 0x0
#define MX6SLL_PAD_LCD_DATA07__GPIO2_IO27 0x0134 0x03FC 0x0000 0x5 0x0
#define MX6SLL_PAD_LCD_DATA07__ARM_TRACE07 0x0134 0x03FC 0x0000 0x6 0x0
#define MX6SLL_PAD_LCD_DATA07__SRC_BOOT_CFG07 0x0134 0x03FC 0x0000 0x7 0x0
#define MX6SLL_PAD_LCD_DATA08__LCD_DATA08 0x0138 0x0400 0x06F8 0x0 0x0
#define MX6SLL_PAD_LCD_DATA08__KEY_COL0 0x0138 0x0400 0x06A0 0x1 0x1
#define MX6SLL_PAD_LCD_DATA08__CSI_DATA09 0x0138 0x0400 0x05EC 0x2 0x0
#define MX6SLL_PAD_LCD_DATA08__ECSPI2_SCLK 0x0138 0x0400 0x061C 0x4 0x0
#define MX6SLL_PAD_LCD_DATA08__GPIO2_IO28 0x0138 0x0400 0x0000 0x5 0x0
#define MX6SLL_PAD_LCD_DATA08__ARM_TRACE08 0x0138 0x0400 0x0000 0x6 0x0
#define MX6SLL_PAD_LCD_DATA08__SRC_BOOT_CFG08 0x0138 0x0400 0x0000 0x7 0x0
#define MX6SLL_PAD_LCD_DATA09__LCD_DATA09 0x013C 0x0404 0x06FC 0x0 0x0
#define MX6SLL_PAD_LCD_DATA09__KEY_ROW0 0x013C 0x0404 0x06C0 0x1 0x1
#define MX6SLL_PAD_LCD_DATA09__CSI_DATA08 0x013C 0x0404 0x05E8 0x2 0x0
#define MX6SLL_PAD_LCD_DATA09__ECSPI2_MOSI 0x013C 0x0404 0x0624 0x4 0x0
#define MX6SLL_PAD_LCD_DATA09__GPIO2_IO29 0x013C 0x0404 0x0000 0x5 0x0
#define MX6SLL_PAD_LCD_DATA09__ARM_TRACE09 0x013C 0x0404 0x0000 0x6 0x0
#define MX6SLL_PAD_LCD_DATA09__SRC_BOOT_CFG09 0x013C 0x0404 0x0000 0x7 0x0
#define MX6SLL_PAD_LCD_DATA10__LCD_DATA10 0x0140 0x0408 0x0700 0x0 0x1
#define MX6SLL_PAD_LCD_DATA10__KEY_COL1 0x0140 0x0408 0x06A4 0x1 0x1
#define MX6SLL_PAD_LCD_DATA10__CSI_DATA07 0x0140 0x0408 0x05E4 0x2 0x0
#define MX6SLL_PAD_LCD_DATA10__ECSPI2_MISO 0x0140 0x0408 0x0620 0x4 0x0
#define MX6SLL_PAD_LCD_DATA10__GPIO2_IO30 0x0140 0x0408 0x0000 0x5 0x0
#define MX6SLL_PAD_LCD_DATA10__ARM_TRACE10 0x0140 0x0408 0x0000 0x6 0x0
#define MX6SLL_PAD_LCD_DATA10__SRC_BOOT_CFG10 0x0140 0x0408 0x0000 0x7 0x0
#define MX6SLL_PAD_LCD_DATA11__LCD_DATA11 0x0144 0x040C 0x0704 0x0 0x0
#define MX6SLL_PAD_LCD_DATA11__KEY_ROW1 0x0144 0x040C 0x06C4 0x1 0x1
#define MX6SLL_PAD_LCD_DATA11__CSI_DATA06 0x0144 0x040C 0x05E0 0x2 0x0
#define MX6SLL_PAD_LCD_DATA11__ECSPI2_SS1 0x0144 0x040C 0x062C 0x4 0x0
#define MX6SLL_PAD_LCD_DATA11__GPIO2_IO31 0x0144 0x040C 0x0000 0x5 0x0
#define MX6SLL_PAD_LCD_DATA11__ARM_TRACE11 0x0144 0x040C 0x0000 0x6 0x0
#define MX6SLL_PAD_LCD_DATA11__SRC_BOOT_CFG11 0x0144 0x040C 0x0000 0x7 0x0
#define MX6SLL_PAD_LCD_DATA12__LCD_DATA12 0x0148 0x0410 0x0708 0x0 0x0
#define MX6SLL_PAD_LCD_DATA12__KEY_COL2 0x0148 0x0410 0x06A8 0x1 0x1
#define MX6SLL_PAD_LCD_DATA12__CSI_DATA05 0x0148 0x0410 0x05DC 0x2 0x0
#define MX6SLL_PAD_LCD_DATA12__UART5_DCE_RTS 0x0148 0x0410 0x0760 0x4 0x0
#define MX6SLL_PAD_LCD_DATA12__UART5_DTE_CTS 0x0148 0x0410 0x0000 0x4 0x0
#define MX6SLL_PAD_LCD_DATA12__GPIO3_IO00 0x0148 0x0410 0x0000 0x5 0x0
#define MX6SLL_PAD_LCD_DATA12__ARM_TRACE12 0x0148 0x0410 0x0000 0x6 0x0
#define MX6SLL_PAD_LCD_DATA12__SRC_BOOT_CFG12 0x0148 0x0410 0x0000 0x7 0x0
#define MX6SLL_PAD_LCD_DATA13__LCD_DATA13 0x014C 0x0414 0x070C 0x0 0x0
#define MX6SLL_PAD_LCD_DATA13__KEY_ROW2 0x014C 0x0414 0x06C8 0x1 0x1
#define MX6SLL_PAD_LCD_DATA13__CSI_DATA04 0x014C 0x0414 0x05D8 0x2 0x0
#define MX6SLL_PAD_LCD_DATA13__UART5_DCE_CTS 0x014C 0x0414 0x0000 0x4 0x0
#define MX6SLL_PAD_LCD_DATA13__UART5_DTE_RTS 0x014C 0x0414 0x0760 0x4 0x1
#define MX6SLL_PAD_LCD_DATA13__GPIO3_IO01 0x014C 0x0414 0x0000 0x5 0x0
#define MX6SLL_PAD_LCD_DATA13__ARM_TRACE13 0x014C 0x0414 0x0000 0x6 0x0
#define MX6SLL_PAD_LCD_DATA13__SRC_BOOT_CFG13 0x014C 0x0414 0x0000 0x7 0x0
#define MX6SLL_PAD_LCD_DATA14__LCD_DATA14 0x0150 0x0418 0x0710 0x0 0x0
#define MX6SLL_PAD_LCD_DATA14__KEY_COL3 0x0150 0x0418 0x06AC 0x1 0x1
#define MX6SLL_PAD_LCD_DATA14__CSI_DATA03 0x0150 0x0418 0x05D4 0x2 0x0
#define MX6SLL_PAD_LCD_DATA14__UART5_DCE_RX 0x0150 0x0418 0x0764 0x4 0x0
#define MX6SLL_PAD_LCD_DATA14__UART5_DTE_TX 0x0150 0x0418 0x0000 0x4 0x0
#define MX6SLL_PAD_LCD_DATA14__GPIO3_IO02 0x0150 0x0418 0x0000 0x5 0x0
#define MX6SLL_PAD_LCD_DATA14__ARM_TRACE14 0x0150 0x0418 0x0000 0x6 0x0
#define MX6SLL_PAD_LCD_DATA14__SRC_BOOT_CFG14 0x0150 0x0418 0x0000 0x7 0x0
#define MX6SLL_PAD_LCD_DATA15__LCD_DATA15 0x0154 0x041C 0x0714 0x0 0x0
#define MX6SLL_PAD_LCD_DATA15__KEY_ROW3 0x0154 0x041C 0x06CC 0x1 0x0
#define MX6SLL_PAD_LCD_DATA15__CSI_DATA02 0x0154 0x041C 0x05D0 0x2 0x0
#define MX6SLL_PAD_LCD_DATA15__UART5_DCE_TX 0x0154 0x041C 0x0000 0x4 0x0
#define MX6SLL_PAD_LCD_DATA15__UART5_DTE_RX 0x0154 0x041C 0x0764 0x4 0x1
#define MX6SLL_PAD_LCD_DATA15__GPIO3_IO03 0x0154 0x041C 0x0000 0x5 0x0
#define MX6SLL_PAD_LCD_DATA15__ARM_TRACE15 0x0154 0x041C 0x0000 0x6 0x0
#define MX6SLL_PAD_LCD_DATA15__SRC_BOOT_CFG15 0x0154 0x041C 0x0000 0x7 0x0
#define MX6SLL_PAD_LCD_DATA16__LCD_DATA16 0x0158 0x0420 0x0718 0x0 0x0
#define MX6SLL_PAD_LCD_DATA16__KEY_COL4 0x0158 0x0420 0x06B0 0x1 0x0
#define MX6SLL_PAD_LCD_DATA16__CSI_DATA01 0x0158 0x0420 0x05CC 0x2 0x0
#define MX6SLL_PAD_LCD_DATA16__I2C2_SCL 0x0158 0x0420 0x0684 0x4 0x1
#define MX6SLL_PAD_LCD_DATA16__GPIO3_IO04 0x0158 0x0420 0x0000 0x5 0x0
#define MX6SLL_PAD_LCD_DATA16__SRC_BOOT_CFG24 0x0158 0x0420 0x0000 0x7 0x0
#define MX6SLL_PAD_LCD_DATA17__LCD_DATA17 0x015C 0x0424 0x071C 0x0 0x0
#define MX6SLL_PAD_LCD_DATA17__KEY_ROW4 0x015C 0x0424 0x06D0 0x1 0x0
#define MX6SLL_PAD_LCD_DATA17__CSI_DATA00 0x015C 0x0424 0x05C8 0x2 0x0
#define MX6SLL_PAD_LCD_DATA17__I2C2_SDA 0x015C 0x0424 0x0688 0x4 0x1
#define MX6SLL_PAD_LCD_DATA17__GPIO3_IO05 0x015C 0x0424 0x0000 0x5 0x0
#define MX6SLL_PAD_LCD_DATA17__SRC_BOOT_CFG25 0x015C 0x0424 0x0000 0x7 0x0
#define MX6SLL_PAD_LCD_DATA18__LCD_DATA18 0x0160 0x0428 0x0720 0x0 0x0
#define MX6SLL_PAD_LCD_DATA18__KEY_COL5 0x0160 0x0428 0x0694 0x1 0x2
#define MX6SLL_PAD_LCD_DATA18__CSI_DATA15 0x0160 0x0428 0x05C4 0x2 0x1
#define MX6SLL_PAD_LCD_DATA18__GPT_CAPTURE1 0x0160 0x0428 0x0670 0x4 0x1
#define MX6SLL_PAD_LCD_DATA18__GPIO3_IO06 0x0160 0x0428 0x0000 0x5 0x0
#define MX6SLL_PAD_LCD_DATA18__SRC_BOOT_CFG26 0x0160 0x0428 0x0000 0x7 0x0
#define MX6SLL_PAD_LCD_DATA19__LCD_DATA19 0x0164 0x042C 0x0724 0x0 0x0
#define MX6SLL_PAD_LCD_DATA19__KEY_ROW5 0x0164 0x042C 0x06B4 0x1 0x1
#define MX6SLL_PAD_LCD_DATA19__CSI_DATA14 0x0164 0x042C 0x05C0 0x2 0x2
#define MX6SLL_PAD_LCD_DATA19__GPT_CAPTURE2 0x0164 0x042C 0x0674 0x4 0x1
#define MX6SLL_PAD_LCD_DATA19__GPIO3_IO07 0x0164 0x042C 0x0000 0x5 0x0
#define MX6SLL_PAD_LCD_DATA19__SRC_BOOT_CFG27 0x0164 0x042C 0x0000 0x7 0x0
#define MX6SLL_PAD_LCD_DATA20__LCD_DATA20 0x0168 0x0430 0x0728 0x0 0x0
#define MX6SLL_PAD_LCD_DATA20__KEY_COL6 0x0168 0x0430 0x0698 0x1 0x1
#define MX6SLL_PAD_LCD_DATA20__CSI_DATA13 0x0168 0x0430 0x05BC 0x2 0x2
#define MX6SLL_PAD_LCD_DATA20__GPT_COMPARE1 0x0168 0x0430 0x0000 0x4 0x0
#define MX6SLL_PAD_LCD_DATA20__GPIO3_IO08 0x0168 0x0430 0x0000 0x5 0x0
#define MX6SLL_PAD_LCD_DATA20__SRC_BOOT_CFG28 0x0168 0x0430 0x0000 0x7 0x0
#define MX6SLL_PAD_LCD_DATA21__LCD_DATA21 0x016C 0x0434 0x072C 0x0 0x0
#define MX6SLL_PAD_LCD_DATA21__KEY_ROW6 0x016C 0x0434 0x06B8 0x1 0x1
#define MX6SLL_PAD_LCD_DATA21__CSI_DATA12 0x016C 0x0434 0x05B8 0x2 0x2
#define MX6SLL_PAD_LCD_DATA21__GPT_COMPARE2 0x016C 0x0434 0x0000 0x4 0x0
#define MX6SLL_PAD_LCD_DATA21__GPIO3_IO09 0x016C 0x0434 0x0000 0x5 0x0
#define MX6SLL_PAD_LCD_DATA21__SRC_BOOT_CFG29 0x016C 0x0434 0x0000 0x7 0x0
#define MX6SLL_PAD_LCD_DATA22__LCD_DATA22 0x0170 0x0438 0x0730 0x0 0x0
#define MX6SLL_PAD_LCD_DATA22__KEY_COL7 0x0170 0x0438 0x069C 0x1 0x1
#define MX6SLL_PAD_LCD_DATA22__CSI_DATA11 0x0170 0x0438 0x05B4 0x2 0x1
#define MX6SLL_PAD_LCD_DATA22__GPT_COMPARE3 0x0170 0x0438 0x0000 0x4 0x0
#define MX6SLL_PAD_LCD_DATA22__GPIO3_IO10 0x0170 0x0438 0x0000 0x5 0x0
#define MX6SLL_PAD_LCD_DATA22__SRC_BOOT_CFG30 0x0170 0x0438 0x0000 0x7 0x0
#define MX6SLL_PAD_LCD_DATA23__LCD_DATA23 0x0174 0x043C 0x0734 0x0 0x0
#define MX6SLL_PAD_LCD_DATA23__KEY_ROW7 0x0174 0x043C 0x06BC 0x1 0x1
#define MX6SLL_PAD_LCD_DATA23__CSI_DATA10 0x0174 0x043C 0x05B0 0x2 0x1
#define MX6SLL_PAD_LCD_DATA23__GPT_CLKIN 0x0174 0x043C 0x0678 0x4 0x1
#define MX6SLL_PAD_LCD_DATA23__GPIO3_IO11 0x0174 0x043C 0x0000 0x5 0x0
#define MX6SLL_PAD_LCD_DATA23__SRC_BOOT_CFG31 0x0174 0x043C 0x0000 0x7 0x0
#define MX6SLL_PAD_AUD_RXFS__AUD3_RXFS 0x0178 0x0440 0x0000 0x0 0x0
#define MX6SLL_PAD_AUD_RXFS__I2C1_SCL 0x0178 0x0440 0x067C 0x1 0x1
#define MX6SLL_PAD_AUD_RXFS__UART3_DCE_RX 0x0178 0x0440 0x0754 0x2 0x0
#define MX6SLL_PAD_AUD_RXFS__UART3_DTE_TX 0x0178 0x0440 0x0000 0x2 0x0
#define MX6SLL_PAD_AUD_RXFS__I2C3_SCL 0x0178 0x0440 0x068C 0x4 0x1
#define MX6SLL_PAD_AUD_RXFS__GPIO1_IO00 0x0178 0x0440 0x0000 0x5 0x0
#define MX6SLL_PAD_AUD_RXFS__ECSPI3_SS0 0x0178 0x0440 0x0648 0x6 0x0
#define MX6SLL_PAD_AUD_RXFS__MBIST_BEND 0x0178 0x0440 0x0000 0x7 0x0
#define MX6SLL_PAD_AUD_RXC__AUD3_RXC 0x017C 0x0444 0x0000 0x0 0x0
#define MX6SLL_PAD_AUD_RXC__I2C1_SDA 0x017C 0x0444 0x0680 0x1 0x1
#define MX6SLL_PAD_AUD_RXC__UART3_DCE_TX 0x017C 0x0444 0x0000 0x2 0x0
#define MX6SLL_PAD_AUD_RXC__UART3_DTE_RX 0x017C 0x0444 0x0754 0x2 0x1
#define MX6SLL_PAD_AUD_RXC__I2C3_SDA 0x017C 0x0444 0x0690 0x4 0x1
#define MX6SLL_PAD_AUD_RXC__GPIO1_IO01 0x017C 0x0444 0x0000 0x5 0x0
#define MX6SLL_PAD_AUD_RXC__ECSPI3_SS1 0x017C 0x0444 0x064C 0x6 0x0
#define MX6SLL_PAD_AUD_RXD__AUD3_RXD 0x0180 0x0448 0x0000 0x0 0x0
#define MX6SLL_PAD_AUD_RXD__ECSPI3_MOSI 0x0180 0x0448 0x063C 0x1 0x0
#define MX6SLL_PAD_AUD_RXD__UART4_DCE_RX 0x0180 0x0448 0x075C 0x2 0x0
#define MX6SLL_PAD_AUD_RXD__UART4_DTE_TX 0x0180 0x0448 0x0000 0x2 0x0
#define MX6SLL_PAD_AUD_RXD__SD1_LCTL 0x0180 0x0448 0x0000 0x4 0x0
#define MX6SLL_PAD_AUD_RXD__GPIO1_IO02 0x0180 0x0448 0x0000 0x5 0x0
#define MX6SLL_PAD_AUD_TXC__AUD3_TXC 0x0184 0x044C 0x0000 0x0 0x0
#define MX6SLL_PAD_AUD_TXC__ECSPI3_MISO 0x0184 0x044C 0x0638 0x1 0x0
#define MX6SLL_PAD_AUD_TXC__UART4_DCE_TX 0x0184 0x044C 0x0000 0x2 0x0
#define MX6SLL_PAD_AUD_TXC__UART4_DTE_RX 0x0184 0x044C 0x075C 0x2 0x1
#define MX6SLL_PAD_AUD_TXC__SD2_LCTL 0x0184 0x044C 0x0000 0x4 0x0
#define MX6SLL_PAD_AUD_TXC__GPIO1_IO03 0x0184 0x044C 0x0000 0x5 0x0
#define MX6SLL_PAD_AUD_TXFS__AUD3_TXFS 0x0188 0x0450 0x0000 0x0 0x0
#define MX6SLL_PAD_AUD_TXFS__PWM3_OUT 0x0188 0x0450 0x0000 0x1 0x0
#define MX6SLL_PAD_AUD_TXFS__UART4_DCE_RTS 0x0188 0x0450 0x0758 0x2 0x0
#define MX6SLL_PAD_AUD_TXFS__UART4_DTE_CTS 0x0188 0x0450 0x0000 0x2 0x0
#define MX6SLL_PAD_AUD_TXFS__SD3_LCTL 0x0188 0x0450 0x0000 0x4 0x0
#define MX6SLL_PAD_AUD_TXFS__GPIO1_IO04 0x0188 0x0450 0x0000 0x5 0x0
#define MX6SLL_PAD_AUD_TXD__AUD3_TXD 0x018C 0x0454 0x0000 0x0 0x0
#define MX6SLL_PAD_AUD_TXD__ECSPI3_SCLK 0x018C 0x0454 0x0630 0x1 0x0
#define MX6SLL_PAD_AUD_TXD__UART4_DCE_CTS 0x018C 0x0454 0x0000 0x2 0x0
#define MX6SLL_PAD_AUD_TXD__UART4_DTE_RTS 0x018C 0x0454 0x0758 0x2 0x1
#define MX6SLL_PAD_AUD_TXD__GPIO1_IO05 0x018C 0x0454 0x0000 0x5 0x0
#define MX6SLL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x0190 0x0458 0x0000 0x0 0x0
#define MX6SLL_PAD_AUD_MCLK__PWM4_OUT 0x0190 0x0458 0x0000 0x1 0x0
#define MX6SLL_PAD_AUD_MCLK__ECSPI3_RDY 0x0190 0x0458 0x0634 0x2 0x0
#define MX6SLL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x0190 0x0458 0x0000 0x4 0x0
#define MX6SLL_PAD_AUD_MCLK__GPIO1_IO06 0x0190 0x0458 0x0000 0x5 0x0
#define MX6SLL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x0190 0x0458 0x073C 0x6 0x1
#define MX6SLL_PAD_UART1_RXD__UART1_DCE_RX 0x0194 0x045C 0x0744 0x0 0x0
#define MX6SLL_PAD_UART1_RXD__UART1_DTE_TX 0x0194 0x045C 0x0000 0x0 0x0
#define MX6SLL_PAD_UART1_RXD__PWM1_OUT 0x0194 0x045C 0x0000 0x1 0x0
#define MX6SLL_PAD_UART1_RXD__UART4_DCE_RX 0x0194 0x045C 0x075C 0x2 0x4
#define MX6SLL_PAD_UART1_RXD__UART4_DTE_TX 0x0194 0x045C 0x0000 0x2 0x0
#define MX6SLL_PAD_UART1_RXD__UART5_DCE_RX 0x0194 0x045C 0x0764 0x4 0x6
#define MX6SLL_PAD_UART1_RXD__UART5_DTE_TX 0x0194 0x045C 0x0000 0x4 0x0
#define MX6SLL_PAD_UART1_RXD__GPIO3_IO16 0x0194 0x045C 0x0000 0x5 0x0
#define MX6SLL_PAD_UART1_TXD__UART1_DCE_TX 0x0198 0x0460 0x0000 0x0 0x0
#define MX6SLL_PAD_UART1_TXD__UART1_DTE_RX 0x0198 0x0460 0x0744 0x0 0x1
#define MX6SLL_PAD_UART1_TXD__PWM2_OUT 0x0198 0x0460 0x0000 0x1 0x0
#define MX6SLL_PAD_UART1_TXD__UART4_DCE_TX 0x0198 0x0460 0x0000 0x2 0x0
#define MX6SLL_PAD_UART1_TXD__UART4_DTE_RX 0x0198 0x0460 0x075C 0x2 0x5
#define MX6SLL_PAD_UART1_TXD__UART5_DCE_TX 0x0198 0x0460 0x0000 0x4 0x0
#define MX6SLL_PAD_UART1_TXD__UART5_DTE_RX 0x0198 0x0460 0x0764 0x4 0x7
#define MX6SLL_PAD_UART1_TXD__GPIO3_IO17 0x0198 0x0460 0x0000 0x5 0x0
#define MX6SLL_PAD_UART1_TXD__UART5_DCD_B 0x0198 0x0460 0x0000 0x7 0x0
#define MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x019C 0x0464 0x067C 0x0 0x0
#define MX6SLL_PAD_I2C1_SCL__UART1_DCE_RTS 0x019C 0x0464 0x0740 0x1 0x0
#define MX6SLL_PAD_I2C1_SCL__UART1_DTE_CTS 0x019C 0x0464 0x0000 0x1 0x0
#define MX6SLL_PAD_I2C1_SCL__ECSPI3_SS2 0x019C 0x0464 0x0640 0x2 0x0
#define MX6SLL_PAD_I2C1_SCL__SD3_RESET 0x019C 0x0464 0x0000 0x4 0x0
#define MX6SLL_PAD_I2C1_SCL__GPIO3_IO12 0x019C 0x0464 0x0000 0x5 0x0
#define MX6SLL_PAD_I2C1_SCL__ECSPI1_SS1 0x019C 0x0464 0x060C 0x6 0x0
#define MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x01A0 0x0468 0x0680 0x0 0x0
#define MX6SLL_PAD_I2C1_SDA__UART1_DCE_CTS 0x01A0 0x0468 0x0000 0x1 0x0
#define MX6SLL_PAD_I2C1_SDA__UART1_DTE_RTS 0x01A0 0x0468 0x0740 0x1 0x1
#define MX6SLL_PAD_I2C1_SDA__ECSPI3_SS3 0x01A0 0x0468 0x0644 0x2 0x0
#define MX6SLL_PAD_I2C1_SDA__SD3_VSELECT 0x01A0 0x0468 0x0000 0x4 0x0
#define MX6SLL_PAD_I2C1_SDA__GPIO3_IO13 0x01A0 0x0468 0x0000 0x5 0x0
#define MX6SLL_PAD_I2C1_SDA__ECSPI1_SS2 0x01A0 0x0468 0x0610 0x6 0x0
#define MX6SLL_PAD_I2C2_SCL__I2C2_SCL 0x01A4 0x046C 0x0684 0x0 0x3
#define MX6SLL_PAD_I2C2_SCL__AUD4_RXFS 0x01A4 0x046C 0x0570 0x1 0x2
#define MX6SLL_PAD_I2C2_SCL__SPDIF_IN 0x01A4 0x046C 0x0738 0x2 0x2
#define MX6SLL_PAD_I2C2_SCL__SD3_WP 0x01A4 0x046C 0x0794 0x4 0x3
#define MX6SLL_PAD_I2C2_SCL__GPIO3_IO14 0x01A4 0x046C 0x0000 0x5 0x0
#define MX6SLL_PAD_I2C2_SCL__ECSPI1_RDY 0x01A4 0x046C 0x0600 0x6 0x1
#define MX6SLL_PAD_I2C2_SDA__I2C2_SDA 0x01A8 0x0470 0x0688 0x0 0x3
#define MX6SLL_PAD_I2C2_SDA__AUD4_RXC 0x01A8 0x0470 0x056C 0x1 0x2
#define MX6SLL_PAD_I2C2_SDA__SPDIF_OUT 0x01A8 0x0470 0x0000 0x2 0x0
#define MX6SLL_PAD_I2C2_SDA__SD3_CD_B 0x01A8 0x0470 0x0780 0x4 0x3
#define MX6SLL_PAD_I2C2_SDA__GPIO3_IO15 0x01A8 0x0470 0x0000 0x5 0x0
#define MX6SLL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x01AC 0x0474 0x05FC 0x0 0x1
#define MX6SLL_PAD_ECSPI1_SCLK__AUD4_TXD 0x01AC 0x0474 0x0568 0x1 0x1
#define MX6SLL_PAD_ECSPI1_SCLK__UART5_DCE_RX 0x01AC 0x0474 0x0764 0x2 0x2
#define MX6SLL_PAD_ECSPI1_SCLK__UART5_DTE_TX 0x01AC 0x0474 0x0000 0x2 0x0
#define MX6SLL_PAD_ECSPI1_SCLK__EPDC_VCOM0 0x01AC 0x0474 0x0000 0x3 0x0
#define MX6SLL_PAD_ECSPI1_SCLK__SD2_RESET 0x01AC 0x0474 0x0000 0x4 0x0
#define MX6SLL_PAD_ECSPI1_SCLK__GPIO4_IO08 0x01AC 0x0474 0x0000 0x5 0x0
#define MX6SLL_PAD_ECSPI1_SCLK__USB_OTG2_OC 0x01AC 0x0474 0x0768 0x6 0x1
#define MX6SLL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x01B0 0x0478 0x0608 0x0 0x1
#define MX6SLL_PAD_ECSPI1_MOSI__AUD4_TXC 0x01B0 0x0478 0x0574 0x1 0x1
#define MX6SLL_PAD_ECSPI1_MOSI__UART5_DCE_TX 0x01B0 0x0478 0x0000 0x2 0x0
#define MX6SLL_PAD_ECSPI1_MOSI__UART5_DTE_RX 0x01B0 0x0478 0x0764 0x2 0x3
#define MX6SLL_PAD_ECSPI1_MOSI__EPDC_VCOM1 0x01B0 0x0478 0x0000 0x3 0x0
#define MX6SLL_PAD_ECSPI1_MOSI__SD2_VSELECT 0x01B0 0x0478 0x0000 0x4 0x0
#define MX6SLL_PAD_ECSPI1_MOSI__GPIO4_IO09 0x01B0 0x0478 0x0000 0x5 0x0
#define MX6SLL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x01B4 0x047C 0x0604 0x0 0x1
#define MX6SLL_PAD_ECSPI1_MISO__AUD4_TXFS 0x01B4 0x047C 0x0578 0x1 0x1
#define MX6SLL_PAD_ECSPI1_MISO__UART5_DCE_RTS 0x01B4 0x047C 0x0760 0x2 0x2
#define MX6SLL_PAD_ECSPI1_MISO__UART5_DTE_CTS 0x01B4 0x047C 0x0000 0x2 0x0
#define MX6SLL_PAD_ECSPI1_MISO__EPDC_BDR0 0x01B4 0x047C 0x0000 0x3 0x0
#define MX6SLL_PAD_ECSPI1_MISO__SD2_WP 0x01B4 0x047C 0x077C 0x4 0x0
#define MX6SLL_PAD_ECSPI1_MISO__GPIO4_IO10 0x01B4 0x047C 0x0000 0x5 0x0
#define MX6SLL_PAD_ECSPI1_SS0__ECSPI1_SS0 0x01B8 0x0480 0x0614 0x0 0x1
#define MX6SLL_PAD_ECSPI1_SS0__AUD4_RXD 0x01B8 0x0480 0x0564 0x1 0x1
#define MX6SLL_PAD_ECSPI1_SS0__UART5_DCE_CTS 0x01B8 0x0480 0x0000 0x2 0x0
#define MX6SLL_PAD_ECSPI1_SS0__UART5_DTE_RTS 0x01B8 0x0480 0x0760 0x2 0x3
#define MX6SLL_PAD_ECSPI1_SS0__EPDC_BDR1 0x01B8 0x0480 0x0000 0x3 0x0
#define MX6SLL_PAD_ECSPI1_SS0__SD2_CD_B 0x01B8 0x0480 0x0778 0x4 0x0
#define MX6SLL_PAD_ECSPI1_SS0__GPIO4_IO11 0x01B8 0x0480 0x0000 0x5 0x0
#define MX6SLL_PAD_ECSPI1_SS0__USB_OTG2_PWR 0x01B8 0x0480 0x0000 0x6 0x0
#define MX6SLL_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x01BC 0x0484 0x061C 0x0 0x1
#define MX6SLL_PAD_ECSPI2_SCLK__SPDIF_EXT_CLK 0x01BC 0x0484 0x073C 0x1 0x2
#define MX6SLL_PAD_ECSPI2_SCLK__UART3_DCE_RX 0x01BC 0x0484 0x0754 0x2 0x2
#define MX6SLL_PAD_ECSPI2_SCLK__UART3_DTE_TX 0x01BC 0x0484 0x0000 0x2 0x0
#define MX6SLL_PAD_ECSPI2_SCLK__CSI_PIXCLK 0x01BC 0x0484 0x05F4 0x3 0x1
#define MX6SLL_PAD_ECSPI2_SCLK__SD1_RESET 0x01BC 0x0484 0x0000 0x4 0x0
#define MX6SLL_PAD_ECSPI2_SCLK__GPIO4_IO12 0x01BC 0x0484 0x0000 0x5 0x0
#define MX6SLL_PAD_ECSPI2_SCLK__USB_OTG2_OC 0x01BC 0x0484 0x0768 0x6 0x2
#define MX6SLL_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x01C0 0x0488 0x0624 0x0 0x1
#define MX6SLL_PAD_ECSPI2_MOSI__SDMA_EXT_EVENT1 0x01C0 0x0488 0x0000 0x1 0x0
#define MX6SLL_PAD_ECSPI2_MOSI__UART3_DCE_TX 0x01C0 0x0488 0x0000 0x2 0x0
#define MX6SLL_PAD_ECSPI2_MOSI__UART3_DTE_RX 0x01C0 0x0488 0x0754 0x2 0x3
#define MX6SLL_PAD_ECSPI2_MOSI__CSI_HSYNC 0x01C0 0x0488 0x05F0 0x3 0x1
#define MX6SLL_PAD_ECSPI2_MOSI__SD1_VSELECT 0x01C0 0x0488 0x0000 0x4 0x0
#define MX6SLL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x01C0 0x0488 0x0000 0x5 0x0
#define MX6SLL_PAD_ECSPI2_MISO__ECSPI2_MISO 0x01C4 0x048C 0x0620 0x0 0x1
#define MX6SLL_PAD_ECSPI2_MISO__SDMA_EXT_EVENT0 0x01C4 0x048C 0x0000 0x1 0x0
#define MX6SLL_PAD_ECSPI2_MISO__UART3_DCE_RTS 0x01C4 0x048C 0x0750 0x2 0x0
#define MX6SLL_PAD_ECSPI2_MISO__UART3_DTE_CTS 0x01C4 0x048C 0x0000 0x2 0x0
#define MX6SLL_PAD_ECSPI2_MISO__CSI_MCLK 0x01C4 0x048C 0x0000 0x3 0x0
#define MX6SLL_PAD_ECSPI2_MISO__SD1_WP 0x01C4 0x048C 0x0774 0x4 0x2
#define MX6SLL_PAD_ECSPI2_MISO__GPIO4_IO14 0x01C4 0x048C 0x0000 0x5 0x0
#define MX6SLL_PAD_ECSPI2_MISO__USB_OTG1_OC 0x01C4 0x048C 0x076C 0x6 0x1
#define MX6SLL_PAD_ECSPI2_SS0__ECSPI2_SS0 0x01C8 0x0490 0x0628 0x0 0x0
#define MX6SLL_PAD_ECSPI2_SS0__ECSPI1_SS3 0x01C8 0x0490 0x0618 0x1 0x1
#define MX6SLL_PAD_ECSPI2_SS0__UART3_DCE_CTS 0x01C8 0x0490 0x0000 0x2 0x0
#define MX6SLL_PAD_ECSPI2_SS0__UART3_DTE_RTS 0x01C8 0x0490 0x0750 0x2 0x1
#define MX6SLL_PAD_ECSPI2_SS0__CSI_VSYNC 0x01C8 0x0490 0x05F8 0x3 0x1
#define MX6SLL_PAD_ECSPI2_SS0__SD1_CD_B 0x01C8 0x0490 0x0770 0x4 0x2
#define MX6SLL_PAD_ECSPI2_SS0__GPIO4_IO15 0x01C8 0x0490 0x0000 0x5 0x0
#define MX6SLL_PAD_ECSPI2_SS0__USB_OTG1_PWR 0x01C8 0x0490 0x0000 0x6 0x0
#define MX6SLL_PAD_SD1_CLK__SD1_CLK 0x01CC 0x0494 0x0000 0x0 0x0
#define MX6SLL_PAD_SD1_CLK__KEY_COL0 0x01CC 0x0494 0x06A0 0x2 0x2
#define MX6SLL_PAD_SD1_CLK__EPDC_SDCE4 0x01CC 0x0494 0x0000 0x3 0x0
#define MX6SLL_PAD_SD1_CLK__GPIO5_IO15 0x01CC 0x0494 0x0000 0x5 0x0
#define MX6SLL_PAD_SD1_CMD__SD1_CMD 0x01D0 0x0498 0x0000 0x0 0x0
#define MX6SLL_PAD_SD1_CMD__KEY_ROW0 0x01D0 0x0498 0x06C0 0x2 0x2
#define MX6SLL_PAD_SD1_CMD__EPDC_SDCE5 0x01D0 0x0498 0x0000 0x3 0x0
#define MX6SLL_PAD_SD1_CMD__GPIO5_IO14 0x01D0 0x0498 0x0000 0x5 0x0
#define MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x01D4 0x049C 0x0000 0x0 0x0
#define MX6SLL_PAD_SD1_DATA0__KEY_COL1 0x01D4 0x049C 0x06A4 0x2 0x2
#define MX6SLL_PAD_SD1_DATA0__EPDC_SDCE6 0x01D4 0x049C 0x0000 0x3 0x0
#define MX6SLL_PAD_SD1_DATA0__GPIO5_IO11 0x01D4 0x049C 0x0000 0x5 0x0
#define MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x01D8 0x04A0 0x0000 0x0 0x0
#define MX6SLL_PAD_SD1_DATA1__KEY_ROW1 0x01D8 0x04A0 0x06C4 0x2 0x2
#define MX6SLL_PAD_SD1_DATA1__EPDC_SDCE7 0x01D8 0x04A0 0x0000 0x3 0x0
#define MX6SLL_PAD_SD1_DATA1__GPIO5_IO08 0x01D8 0x04A0 0x0000 0x5 0x0
#define MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x01DC 0x04A4 0x0000 0x0 0x0
#define MX6SLL_PAD_SD1_DATA2__KEY_COL2 0x01DC 0x04A4 0x06A8 0x2 0x2
#define MX6SLL_PAD_SD1_DATA2__EPDC_SDCE8 0x01DC 0x04A4 0x0000 0x3 0x0
#define MX6SLL_PAD_SD1_DATA2__GPIO5_IO13 0x01DC 0x04A4 0x0000 0x5 0x0
#define MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x01E0 0x04A8 0x0000 0x0 0x0
#define MX6SLL_PAD_SD1_DATA3__KEY_ROW2 0x01E0 0x04A8 0x06C8 0x2 0x2
#define MX6SLL_PAD_SD1_DATA3__EPDC_SDCE9 0x01E0 0x04A8 0x0000 0x3 0x0
#define MX6SLL_PAD_SD1_DATA3__GPIO5_IO06 0x01E0 0x04A8 0x0000 0x5 0x0
#define MX6SLL_PAD_SD1_DATA4__SD1_DATA4 0x01E4 0x04AC 0x0000 0x0 0x0
#define MX6SLL_PAD_SD1_DATA4__KEY_COL3 0x01E4 0x04AC 0x06AC 0x2 0x2
#define MX6SLL_PAD_SD1_DATA4__EPDC_SDCLK_N 0x01E4 0x04AC 0x0000 0x3 0x0
#define MX6SLL_PAD_SD1_DATA4__UART4_DCE_RX 0x01E4 0x04AC 0x075C 0x4 0x6
#define MX6SLL_PAD_SD1_DATA4__UART4_DTE_TX 0x01E4 0x04AC 0x0000 0x4 0x0
#define MX6SLL_PAD_SD1_DATA4__GPIO5_IO12 0x01E4 0x04AC 0x0000 0x5 0x0
#define MX6SLL_PAD_SD1_DATA5__SD1_DATA5 0x01E8 0x04B0 0x0000 0x0 0x0
#define MX6SLL_PAD_SD1_DATA5__KEY_ROW3 0x01E8 0x04B0 0x06CC 0x2 0x2
#define MX6SLL_PAD_SD1_DATA5__EPDC_SDOED 0x01E8 0x04B0 0x0000 0x3 0x0
#define MX6SLL_PAD_SD1_DATA5__UART4_DCE_TX 0x01E8 0x04B0 0x0000 0x4 0x0
#define MX6SLL_PAD_SD1_DATA5__UART4_DTE_RX 0x01E8 0x04B0 0x075C 0x4 0x7
#define MX6SLL_PAD_SD1_DATA5__GPIO5_IO09 0x01E8 0x04B0 0x0000 0x5 0x0
#define MX6SLL_PAD_SD1_DATA6__SD1_DATA6 0x01EC 0x04B4 0x0000 0x0 0x0
#define MX6SLL_PAD_SD1_DATA6__KEY_COL4 0x01EC 0x04B4 0x06B0 0x2 0x2
#define MX6SLL_PAD_SD1_DATA6__EPDC_SDOEZ 0x01EC 0x04B4 0x0000 0x3 0x0
#define MX6SLL_PAD_SD1_DATA6__UART4_DCE_RTS 0x01EC 0x04B4 0x0758 0x4 0x4
#define MX6SLL_PAD_SD1_DATA6__UART4_DTE_CTS 0x01EC 0x04B4 0x0000 0x4 0x0
#define MX6SLL_PAD_SD1_DATA6__GPIO5_IO07 0x01EC 0x04B4 0x0000 0x5 0x0
#define MX6SLL_PAD_SD1_DATA7__SD1_DATA7 0x01F0 0x04B8 0x0000 0x0 0x0
#define MX6SLL_PAD_SD1_DATA7__KEY_ROW4 0x01F0 0x04B8 0x06D0 0x2 0x2
#define MX6SLL_PAD_SD1_DATA7__CCM_PMIC_READY 0x01F0 0x04B8 0x05AC 0x3 0x3
#define MX6SLL_PAD_SD1_DATA7__UART4_DCE_CTS 0x01F0 0x04B8 0x0000 0x4 0x0
#define MX6SLL_PAD_SD1_DATA7__UART4_DTE_RTS 0x01F0 0x04B8 0x0758 0x4 0x5
#define MX6SLL_PAD_SD1_DATA7__GPIO5_IO10 0x01F0 0x04B8 0x0000 0x5 0x0
#define MX6SLL_PAD_SD2_RESET__SD2_RESET 0x01F4 0x04BC 0x0000 0x0 0x0
#define MX6SLL_PAD_SD2_RESET__WDOG2_B 0x01F4 0x04BC 0x0000 0x2 0x0
#define MX6SLL_PAD_SD2_RESET__SPDIF_OUT 0x01F4 0x04BC 0x0000 0x3 0x0
#define MX6SLL_PAD_SD2_RESET__CSI_MCLK 0x01F4 0x04BC 0x0000 0x4 0x0
#define MX6SLL_PAD_SD2_RESET__GPIO4_IO27 0x01F4 0x04BC 0x0000 0x5 0x0
#define MX6SLL_PAD_SD2_CLK__SD2_CLK 0x01F8 0x04C0 0x0000 0x0 0x0
#define MX6SLL_PAD_SD2_CLK__AUD4_RXFS 0x01F8 0x04C0 0x0570 0x1 0x1
#define MX6SLL_PAD_SD2_CLK__ECSPI3_SCLK 0x01F8 0x04C0 0x0630 0x2 0x1
#define MX6SLL_PAD_SD2_CLK__CSI_DATA00 0x01F8 0x04C0 0x05C8 0x3 0x1
#define MX6SLL_PAD_SD2_CLK__GPIO5_IO05 0x01F8 0x04C0 0x0000 0x5 0x0
#define MX6SLL_PAD_SD2_CMD__SD2_CMD 0x01FC 0x04C4 0x0000 0x0 0x0
#define MX6SLL_PAD_SD2_CMD__AUD4_RXC 0x01FC 0x04C4 0x056C 0x1 0x1
#define MX6SLL_PAD_SD2_CMD__ECSPI3_SS0 0x01FC 0x04C4 0x0648 0x2 0x1
#define MX6SLL_PAD_SD2_CMD__CSI_DATA01 0x01FC 0x04C4 0x05CC 0x3 0x1
#define MX6SLL_PAD_SD2_CMD__EPIT1_OUT 0x01FC 0x04C4 0x0000 0x4 0x0
#define MX6SLL_PAD_SD2_CMD__GPIO5_IO04 0x01FC 0x04C4 0x0000 0x5 0x0
#define MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x0200 0x04C8 0x0000 0x0 0x0
#define MX6SLL_PAD_SD2_DATA0__AUD4_RXD 0x0200 0x04C8 0x0564 0x1 0x2
#define MX6SLL_PAD_SD2_DATA0__ECSPI3_MOSI 0x0200 0x04C8 0x063C 0x2 0x1
#define MX6SLL_PAD_SD2_DATA0__CSI_DATA02 0x0200 0x04C8 0x05D0 0x3 0x1
#define MX6SLL_PAD_SD2_DATA0__UART5_DCE_RTS 0x0200 0x04C8 0x0760 0x4 0x4
#define MX6SLL_PAD_SD2_DATA0__UART5_DTE_CTS 0x0200 0x04C8 0x0000 0x4 0x0
#define MX6SLL_PAD_SD2_DATA0__GPIO5_IO01 0x0200 0x04C8 0x0000 0x5 0x0
#define MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x0204 0x04CC 0x0000 0x0 0x0
#define MX6SLL_PAD_SD2_DATA1__AUD4_TXC 0x0204 0x04CC 0x0574 0x1 0x2
#define MX6SLL_PAD_SD2_DATA1__ECSPI3_MISO 0x0204 0x04CC 0x0638 0x2 0x1
#define MX6SLL_PAD_SD2_DATA1__CSI_DATA03 0x0204 0x04CC 0x05D4 0x3 0x1
#define MX6SLL_PAD_SD2_DATA1__UART5_DCE_CTS 0x0204 0x04CC 0x0000 0x4 0x0
#define MX6SLL_PAD_SD2_DATA1__UART5_DTE_RTS 0x0204 0x04CC 0x0760 0x4 0x5
#define MX6SLL_PAD_SD2_DATA1__GPIO4_IO30 0x0204 0x04CC 0x0000 0x5 0x0
#define MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x0208 0x04D0 0x0000 0x0 0x0
#define MX6SLL_PAD_SD2_DATA2__AUD4_TXFS 0x0208 0x04D0 0x0578 0x1 0x2
#define MX6SLL_PAD_SD2_DATA2__CSI_DATA04 0x0208 0x04D0 0x05D8 0x3 0x1
#define MX6SLL_PAD_SD2_DATA2__UART5_DCE_RX 0x0208 0x04D0 0x0764 0x4 0x4
#define MX6SLL_PAD_SD2_DATA2__UART5_DTE_TX 0x0208 0x04D0 0x0000 0x4 0x0
#define MX6SLL_PAD_SD2_DATA2__GPIO5_IO03 0x0208 0x04D0 0x0000 0x5 0x0
#define MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x020C 0x04D4 0x0000 0x0 0x0
#define MX6SLL_PAD_SD2_DATA3__AUD4_TXD 0x020C 0x04D4 0x0568 0x1 0x2
#define MX6SLL_PAD_SD2_DATA3__CSI_DATA05 0x020C 0x04D4 0x05DC 0x3 0x1
#define MX6SLL_PAD_SD2_DATA3__UART5_DCE_TX 0x020C 0x04D4 0x0000 0x4 0x0
#define MX6SLL_PAD_SD2_DATA3__UART5_DTE_RX 0x020C 0x04D4 0x0764 0x4 0x5
#define MX6SLL_PAD_SD2_DATA3__GPIO4_IO28 0x020C 0x04D4 0x0000 0x5 0x0
#define MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x0210 0x04D8 0x0000 0x0 0x0
#define MX6SLL_PAD_SD2_DATA4__SD3_DATA4 0x0210 0x04D8 0x0784 0x1 0x1
#define MX6SLL_PAD_SD2_DATA4__UART2_DCE_RX 0x0210 0x04D8 0x074C 0x2 0x2
#define MX6SLL_PAD_SD2_DATA4__UART2_DTE_TX 0x0210 0x04D8 0x0000 0x2 0x0
#define MX6SLL_PAD_SD2_DATA4__CSI_DATA06 0x0210 0x04D8 0x05E0 0x3 0x1
#define MX6SLL_PAD_SD2_DATA4__SPDIF_OUT 0x0210 0x04D8 0x0000 0x4 0x0
#define MX6SLL_PAD_SD2_DATA4__GPIO5_IO02 0x0210 0x04D8 0x0000 0x5 0x0
#define MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x0214 0x04DC 0x0000 0x0 0x0
#define MX6SLL_PAD_SD2_DATA5__SD3_DATA5 0x0214 0x04DC 0x0788 0x1 0x1
#define MX6SLL_PAD_SD2_DATA5__UART2_DCE_TX 0x0214 0x04DC 0x0000 0x2 0x0
#define MX6SLL_PAD_SD2_DATA5__UART2_DTE_RX 0x0214 0x04DC 0x074C 0x2 0x3
#define MX6SLL_PAD_SD2_DATA5__CSI_DATA07 0x0214 0x04DC 0x05E4 0x3 0x1
#define MX6SLL_PAD_SD2_DATA5__SPDIF_IN 0x0214 0x04DC 0x0738 0x4 0x1
#define MX6SLL_PAD_SD2_DATA5__GPIO4_IO31 0x0214 0x04DC 0x0000 0x5 0x0
#define MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x0218 0x04E0 0x0000 0x0 0x0
#define MX6SLL_PAD_SD2_DATA6__SD3_DATA6 0x0218 0x04E0 0x078C 0x1 0x1
#define MX6SLL_PAD_SD2_DATA6__UART2_DCE_RTS 0x0218 0x04E0 0x0748 0x2 0x2
#define MX6SLL_PAD_SD2_DATA6__UART2_DTE_CTS 0x0218 0x04E0 0x0000 0x2 0x0
#define MX6SLL_PAD_SD2_DATA6__CSI_DATA08 0x0218 0x04E0 0x05E8 0x3 0x1
#define MX6SLL_PAD_SD2_DATA6__SD2_WP 0x0218 0x04E0 0x077C 0x4 0x1
#define MX6SLL_PAD_SD2_DATA6__GPIO4_IO29 0x0218 0x04E0 0x0000 0x5 0x0
#define MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x021C 0x04E4 0x0000 0x0 0x0
#define MX6SLL_PAD_SD2_DATA7__SD3_DATA7 0x021C 0x04E4 0x0790 0x1 0x1
#define MX6SLL_PAD_SD2_DATA7__UART2_DCE_CTS 0x021C 0x04E4 0x0000 0x2 0x0
#define MX6SLL_PAD_SD2_DATA7__UART2_DTE_RTS 0x021C 0x04E4 0x0748 0x2 0x3
#define MX6SLL_PAD_SD2_DATA7__CSI_DATA09 0x021C 0x04E4 0x05EC 0x3 0x1
#define MX6SLL_PAD_SD2_DATA7__SD2_CD_B 0x021C 0x04E4 0x0778 0x4 0x1
#define MX6SLL_PAD_SD2_DATA7__GPIO5_IO00 0x021C 0x04E4 0x0000 0x5 0x0
#define MX6SLL_PAD_SD3_CLK__SD3_CLK 0x0220 0x04E8 0x0000 0x0 0x0
#define MX6SLL_PAD_SD3_CLK__AUD5_RXFS 0x0220 0x04E8 0x0588 0x1 0x0
#define MX6SLL_PAD_SD3_CLK__KEY_COL5 0x0220 0x04E8 0x0694 0x2 0x0
#define MX6SLL_PAD_SD3_CLK__CSI_DATA10 0x0220 0x04E8 0x05B0 0x3 0x0
#define MX6SLL_PAD_SD3_CLK__WDOG1_RESET_B_DEB 0x0220 0x04E8 0x0000 0x4 0x0
#define MX6SLL_PAD_SD3_CLK__GPIO5_IO18 0x0220 0x04E8 0x0000 0x5 0x0
#define MX6SLL_PAD_SD3_CLK__USB_OTG1_PWR 0x0220 0x04E8 0x0000 0x6 0x0
#define MX6SLL_PAD_SD3_CMD__SD3_CMD 0x0224 0x04EC 0x0000 0x0 0x0
#define MX6SLL_PAD_SD3_CMD__AUD5_RXC 0x0224 0x04EC 0x0584 0x1 0x0
#define MX6SLL_PAD_SD3_CMD__KEY_ROW5 0x0224 0x04EC 0x06B4 0x2 0x0
#define MX6SLL_PAD_SD3_CMD__CSI_DATA11 0x0224 0x04EC 0x05B4 0x3 0x0
#define MX6SLL_PAD_SD3_CMD__USB_OTG2_ID 0x0224 0x04EC 0x0560 0x4 0x1
#define MX6SLL_PAD_SD3_CMD__GPIO5_IO21 0x0224 0x04EC 0x0000 0x5 0x0
#define MX6SLL_PAD_SD3_CMD__USB_OTG2_PWR 0x0224 0x04EC 0x0000 0x6 0x0
#define MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x0228 0x04F0 0x0000 0x0 0x0
#define MX6SLL_PAD_SD3_DATA0__AUD5_RXD 0x0228 0x04F0 0x057C 0x1 0x0
#define MX6SLL_PAD_SD3_DATA0__KEY_COL6 0x0228 0x04F0 0x0698 0x2 0x0
#define MX6SLL_PAD_SD3_DATA0__CSI_DATA12 0x0228 0x04F0 0x05B8 0x3 0x0
#define MX6SLL_PAD_SD3_DATA0__USB_OTG1_ID 0x0228 0x04F0 0x055C 0x4 0x1
#define MX6SLL_PAD_SD3_DATA0__GPIO5_IO19 0x0228 0x04F0 0x0000 0x5 0x0
#define MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x022C 0x04F4 0x0000 0x0 0x0
#define MX6SLL_PAD_SD3_DATA1__AUD5_TXC 0x022C 0x04F4 0x058C 0x1 0x0
#define MX6SLL_PAD_SD3_DATA1__KEY_ROW6 0x022C 0x04F4 0x06B8 0x2 0x0
#define MX6SLL_PAD_SD3_DATA1__CSI_DATA13 0x022C 0x04F4 0x05BC 0x3 0x0
#define MX6SLL_PAD_SD3_DATA1__SD1_VSELECT 0x022C 0x04F4 0x0000 0x4 0x0
#define MX6SLL_PAD_SD3_DATA1__GPIO5_IO20 0x022C 0x04F4 0x0000 0x5 0x0
#define MX6SLL_PAD_SD3_DATA1__JTAG_DE_B 0x022C 0x04F4 0x0000 0x6 0x0
#define MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x0230 0x04F8 0x0000 0x0 0x0
#define MX6SLL_PAD_SD3_DATA2__AUD5_TXFS 0x0230 0x04F8 0x0590 0x1 0x0
#define MX6SLL_PAD_SD3_DATA2__KEY_COL7 0x0230 0x04F8 0x069C 0x2 0x0
#define MX6SLL_PAD_SD3_DATA2__CSI_DATA14 0x0230 0x04F8 0x05C0 0x3 0x0
#define MX6SLL_PAD_SD3_DATA2__EPIT1_OUT 0x0230 0x04F8 0x0000 0x4 0x0
#define MX6SLL_PAD_SD3_DATA2__GPIO5_IO16 0x0230 0x04F8 0x0000 0x5 0x0
#define MX6SLL_PAD_SD3_DATA2__USB_OTG2_OC 0x0230 0x04F8 0x0768 0x6 0x0
#define MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x0234 0x04FC 0x0000 0x0 0x0
#define MX6SLL_PAD_SD3_DATA3__AUD5_TXD 0x0234 0x04FC 0x0580 0x1 0x0
#define MX6SLL_PAD_SD3_DATA3__KEY_ROW7 0x0234 0x04FC 0x06BC 0x2 0x0
#define MX6SLL_PAD_SD3_DATA3__CSI_DATA15 0x0234 0x04FC 0x05C4 0x3 0x0
#define MX6SLL_PAD_SD3_DATA3__EPIT2_OUT 0x0234 0x04FC 0x0000 0x4 0x0
#define MX6SLL_PAD_SD3_DATA3__GPIO5_IO17 0x0234 0x04FC 0x0000 0x5 0x0
#define MX6SLL_PAD_SD3_DATA3__USB_OTG1_OC 0x0234 0x04FC 0x076C 0x6 0x0
#define MX6SLL_PAD_GPIO4_IO20__SD1_STROBE 0x0238 0x0500 0x0000 0x0 0x0
#define MX6SLL_PAD_GPIO4_IO20__AUD6_RXFS 0x0238 0x0500 0x05A0 0x2 0x0
#define MX6SLL_PAD_GPIO4_IO20__ECSPI4_SS0 0x0238 0x0500 0x065C 0x3 0x0
#define MX6SLL_PAD_GPIO4_IO20__GPT_CAPTURE1 0x0238 0x0500 0x0670 0x4 0x0
#define MX6SLL_PAD_GPIO4_IO20__GPIO4_IO20 0x0238 0x0500 0x0000 0x5 0x0
#define MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x023C 0x0504 0x0000 0x0 0x0
#define MX6SLL_PAD_GPIO4_IO21__AUD6_RXC 0x023C 0x0504 0x059C 0x2 0x0
#define MX6SLL_PAD_GPIO4_IO21__ECSPI4_SCLK 0x023C 0x0504 0x0650 0x3 0x0
#define MX6SLL_PAD_GPIO4_IO21__GPT_CAPTURE2 0x023C 0x0504 0x0674 0x4 0x0
#define MX6SLL_PAD_GPIO4_IO21__GPIO4_IO21 0x023C 0x0504 0x0000 0x5 0x0
#define MX6SLL_PAD_GPIO4_IO19__SD3_STROBE 0x0240 0x0508 0x0000 0x0 0x0
#define MX6SLL_PAD_GPIO4_IO19__AUD6_RXD 0x0240 0x0508 0x0594 0x2 0x0
#define MX6SLL_PAD_GPIO4_IO19__ECSPI4_MOSI 0x0240 0x0508 0x0658 0x3 0x0
#define MX6SLL_PAD_GPIO4_IO19__GPT_COMPARE1 0x0240 0x0508 0x0000 0x4 0x0
#define MX6SLL_PAD_GPIO4_IO19__GPIO4_IO19 0x0240 0x0508 0x0000 0x5 0x0
#define MX6SLL_PAD_GPIO4_IO25__AUD6_TXC 0x0244 0x050C 0x05A4 0x2 0x0
#define MX6SLL_PAD_GPIO4_IO25__ECSPI4_MISO 0x0244 0x050C 0x0654 0x3 0x0
#define MX6SLL_PAD_GPIO4_IO25__GPT_COMPARE2 0x0244 0x050C 0x0000 0x4 0x0
#define MX6SLL_PAD_GPIO4_IO25__GPIO4_IO25 0x0244 0x050C 0x0000 0x5 0x0
#define MX6SLL_PAD_GPIO4_IO18__AUD6_TXFS 0x0248 0x0510 0x05A8 0x2 0x0
#define MX6SLL_PAD_GPIO4_IO18__ECSPI4_SS1 0x0248 0x0510 0x0660 0x3 0x0
#define MX6SLL_PAD_GPIO4_IO18__GPT_COMPARE3 0x0248 0x0510 0x0000 0x4 0x0
#define MX6SLL_PAD_GPIO4_IO18__GPIO4_IO18 0x0248 0x0510 0x0000 0x5 0x0
#define MX6SLL_PAD_GPIO4_IO24__AUD6_TXD 0x024C 0x0514 0x0598 0x2 0x0
#define MX6SLL_PAD_GPIO4_IO24__ECSPI4_SS2 0x024C 0x0514 0x0664 0x3 0x0
#define MX6SLL_PAD_GPIO4_IO24__GPT_CLKIN 0x024C 0x0514 0x0678 0x4 0x0
#define MX6SLL_PAD_GPIO4_IO24__GPIO4_IO24 0x024C 0x0514 0x0000 0x5 0x0
#define MX6SLL_PAD_GPIO4_IO23__AUDIO_CLK_OUT 0x0250 0x0518 0x0000 0x2 0x0
#define MX6SLL_PAD_GPIO4_IO23__SD1_RESET 0x0250 0x0518 0x0000 0x3 0x0
#define MX6SLL_PAD_GPIO4_IO23__SD3_RESET 0x0250 0x0518 0x0000 0x4 0x0
#define MX6SLL_PAD_GPIO4_IO23__GPIO4_IO23 0x0250 0x0518 0x0000 0x5 0x0
#define MX6SLL_PAD_GPIO4_IO17__USB_OTG1_ID 0x0254 0x051C 0x055C 0x2 0x2
#define MX6SLL_PAD_GPIO4_IO17__SD1_VSELECT 0x0254 0x051C 0x0000 0x3 0x0
#define MX6SLL_PAD_GPIO4_IO17__SD3_VSELECT 0x0254 0x051C 0x0000 0x4 0x0
#define MX6SLL_PAD_GPIO4_IO17__GPIO4_IO17 0x0254 0x051C 0x0000 0x5 0x0
#define MX6SLL_PAD_GPIO4_IO22__SPDIF_IN 0x0258 0x0520 0x0738 0x2 0x0
#define MX6SLL_PAD_GPIO4_IO22__SD1_WP 0x0258 0x0520 0x0774 0x3 0x0
#define MX6SLL_PAD_GPIO4_IO22__SD3_WP 0x0258 0x0520 0x0794 0x4 0x1
#define MX6SLL_PAD_GPIO4_IO22__GPIO4_IO22 0x0258 0x0520 0x0000 0x5 0x0
#define MX6SLL_PAD_GPIO4_IO16__SPDIF_OUT 0x025C 0x0524 0x0000 0x2 0x0
#define MX6SLL_PAD_GPIO4_IO16__SD1_CD_B 0x025C 0x0524 0x0770 0x3 0x0
#define MX6SLL_PAD_GPIO4_IO16__SD3_CD_B 0x025C 0x0524 0x0780 0x4 0x1
#define MX6SLL_PAD_GPIO4_IO16__GPIO4_IO16 0x025C 0x0524 0x0000 0x5 0x0
#define MX6SLL_PAD_GPIO4_IO26__WDOG1_B 0x0260 0x0528 0x0000 0x2 0x0
#define MX6SLL_PAD_GPIO4_IO26__PWM4_OUT 0x0260 0x0528 0x0000 0x3 0x0
#define MX6SLL_PAD_GPIO4_IO26__CCM_PMIC_READY 0x0260 0x0528 0x05AC 0x4 0x1
#define MX6SLL_PAD_GPIO4_IO26__GPIO4_IO26 0x0260 0x0528 0x0000 0x5 0x0
#define MX6SLL_PAD_GPIO4_IO26__SPDIF_EXT_CLK 0x0260 0x0528 0x073C 0x6 0x0
#endif /* __DTS_IMX6SLL_PINFUNC_H */

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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright 2014 - 2015 Freescale Semiconductor, Inc.
*/
#ifndef __DTS_IMX6UL_PINFUNC_H
#define __DTS_IMX6UL_PINFUNC_H
/*
* The pin function ID is a tuple of
* <mux_reg conf_reg input_reg mux_mode input_val>
*/
#define MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x0014 0x02a0 0x0000 5 0
#define MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x0018 0x02a4 0x0000 5 0
#define MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x001c 0x02a8 0x0000 5 0
#define MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0020 0x02ac 0x0000 5 0
#define MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0024 0x02b0 0x0000 5 0
#define MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0028 0x02b4 0x0000 5 0
#define MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x002c 0x02b8 0x0000 5 0
#define MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0030 0x02bc 0x0000 5 0
#define MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0034 0x02c0 0x0000 5 0
#define MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0038 0x02c4 0x0000 5 0
#define MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x003c 0x02c8 0x0000 5 0
#define MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x0040 0x02cc 0x0000 5 0
#define MX6UL_PAD_JTAG_MOD__SJC_MOD 0x0044 0x02d0 0x0000 0 0
#define MX6UL_PAD_JTAG_MOD__GPT2_CLK 0x0044 0x02d0 0x05a0 1 0
#define MX6UL_PAD_JTAG_MOD__SPDIF_OUT 0x0044 0x02d0 0x0000 2 0
#define MX6UL_PAD_JTAG_MOD__ENET1_REF_CLK_25M 0x0044 0x02d0 0x0000 3 0
#define MX6UL_PAD_JTAG_MOD__CCM_PMIC_RDY 0x0044 0x02d0 0x04c0 4 0
#define MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x0044 0x02d0 0x0000 5 0
#define MX6UL_PAD_JTAG_MOD__SDMA_EXT_EVENT00 0x0044 0x02d0 0x0610 6 0
#define MX6UL_PAD_JTAG_TMS__SJC_TMS 0x0048 0x02d4 0x0000 0 0
#define MX6UL_PAD_JTAG_TMS__GPT2_CAPTURE1 0x0048 0x02d4 0x0598 1 0
#define MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x0048 0x02d4 0x05f0 2 0
#define MX6UL_PAD_JTAG_TMS__CCM_CLKO1 0x0048 0x02d4 0x0000 3 0
#define MX6UL_PAD_JTAG_TMS__CCM_WAIT 0x0048 0x02d4 0x0000 4 0
#define MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x0048 0x02d4 0x0000 5 0
#define MX6UL_PAD_JTAG_TMS__SDMA_EXT_EVENT01 0x0048 0x02d4 0x0614 6 0
#define MX6UL_PAD_JTAG_TMS__EPIT1_OUT 0x0048 0x02d4 0x0000 8 0
#define MX6UL_PAD_JTAG_TDO__SJC_TDO 0x004c 0x02d8 0x0000 0 0
#define MX6UL_PAD_JTAG_TDO__GPT2_CAPTURE2 0x004c 0x02d8 0x059c 1 0
#define MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x004c 0x02d8 0x05fc 2 0
#define MX6UL_PAD_JTAG_TDO__CCM_CLKO2 0x004c 0x02d8 0x0000 3 0
#define MX6UL_PAD_JTAG_TDO__CCM_STOP 0x004c 0x02d8 0x0000 4 0
#define MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x004c 0x02d8 0x0000 5 0
#define MX6UL_PAD_JTAG_TDO__MQS_RIGHT 0x004c 0x02d8 0x0000 6 0
#define MX6UL_PAD_JTAG_TDO__EPIT2_OUT 0x004c 0x02d8 0x0000 8 0
#define MX6UL_PAD_JTAG_TDI__SJC_TDI 0x0050 0x02dc 0x0000 0 0
#define MX6UL_PAD_JTAG_TDI__GPT2_COMPARE1 0x0050 0x02dc 0x0000 1 0
#define MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x0050 0x02dc 0x05f8 2 0
#define MX6UL_PAD_JTAG_TDI__PWM6_OUT 0x0050 0x02dc 0x0000 4 0
#define MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x0050 0x02dc 0x0000 5 0
#define MX6UL_PAD_JTAG_TDI__MQS_LEFT 0x0050 0x02dc 0x0000 6 0
#define MX6UL_PAD_JTAG_TDI__SIM1_POWER_FAIL 0x0050 0x02dc 0x0000 8 0
#define MX6UL_PAD_JTAG_TCK__SJC_TCK 0x0054 0x02e0 0x0000 0 0
#define MX6UL_PAD_JTAG_TCK__GPT2_COMPARE2 0x0054 0x02e0 0x0000 1 0
#define MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x0054 0x02e0 0x05f4 2 0
#define MX6UL_PAD_JTAG_TCK__PWM7_OUT 0x0054 0x02e0 0x0000 4 0
#define MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x0054 0x02e0 0x0000 5 0
#define MX6UL_PAD_JTAG_TCK__OSC32K_32K_OUT 0x0054 0x02e0 0x0000 6 0
#define MX6UL_PAD_JTAG_TCK__SIM2_POWER_FAIL 0x0054 0x02e0 0x0000 8 0
#define MX6UL_PAD_JTAG_TRST_B__SJC_TRSTB 0x0058 0x02e4 0x0000 0 0
#define MX6UL_PAD_JTAG_TRST_B__GPT2_COMPARE3 0x0058 0x02e4 0x0000 1 0
#define MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x0058 0x02e4 0x0000 2 0
#define MX6UL_PAD_JTAG_TRST_B__PWM8_OUT 0x0058 0x02e4 0x0000 4 0
#define MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x0058 0x02e4 0x0000 5 0
#define MX6UL_PAD_JTAG_TRST_B__REF_CLK_24M 0x0058 0x02e4 0x0000 6 0
#define MX6UL_PAD_JTAG_TRST_B__CAAM_RNG_OSC_OBS 0x0058 0x02e4 0x0000 8 0
#define MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x005c 0x02e8 0x05ac 0 1
#define MX6UL_PAD_GPIO1_IO00__GPT1_CAPTURE1 0x005c 0x02e8 0x058c 1 0
#define MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x005c 0x02e8 0x04b8 2 0
#define MX6UL_PAD_GPIO1_IO00__ENET1_REF_CLK1 0x005c 0x02e8 0x0574 3 0
#define MX6UL_PAD_GPIO1_IO00__MQS_RIGHT 0x005c 0x02e8 0x0000 4 0
#define MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x005c 0x02e8 0x0000 5 0
#define MX6UL_PAD_GPIO1_IO00__ENET1_1588_EVENT0_IN 0x005c 0x02e8 0x0000 6 0
#define MX6UL_PAD_GPIO1_IO00__SRC_SYSTEM_RESET 0x005c 0x02e8 0x0000 7 0
#define MX6UL_PAD_GPIO1_IO00__WDOG3_WDOG_B 0x005c 0x02e8 0x0000 8 0
#define MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0x0060 0x02ec 0x05b0 0 1
#define MX6UL_PAD_GPIO1_IO01__GPT1_COMPARE1 0x0060 0x02ec 0x0000 1 0
#define MX6UL_PAD_GPIO1_IO01__USB_OTG1_OC 0x0060 0x02ec 0x0664 2 0
#define MX6UL_PAD_GPIO1_IO01__ENET2_REF_CLK2 0x0060 0x02ec 0x057c 3 0
#define MX6UL_PAD_GPIO1_IO01__MQS_LEFT 0x0060 0x02ec 0x0000 4 0
#define MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x0060 0x02ec 0x0000 5 0
#define MX6UL_PAD_GPIO1_IO01__ENET1_1588_EVENT0_OUT 0x0060 0x02ec 0x0000 6 0
#define MX6UL_PAD_GPIO1_IO01__SRC_EARLY_RESET 0x0060 0x02ec 0x0000 7 0
#define MX6UL_PAD_GPIO1_IO01__WDOG1_WDOG_B 0x0060 0x02ec 0x0000 8 0
#define MX6UL_PAD_GPIO1_IO02__I2C1_SCL 0x0064 0x02f0 0x05a4 0 0
#define MX6UL_PAD_GPIO1_IO02__GPT1_COMPARE2 0x0064 0x02f0 0x0000 1 0
#define MX6UL_PAD_GPIO1_IO02__USB_OTG2_PWR 0x0064 0x02f0 0x0000 2 0
#define MX6UL_PAD_GPIO1_IO02__ENET1_REF_CLK_25M 0x0064 0x02f0 0x0000 3 0
#define MX6UL_PAD_GPIO1_IO02__USDHC1_WP 0x0064 0x02f0 0x066c 4 0
#define MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x0064 0x02f0 0x0000 5 0
#define MX6UL_PAD_GPIO1_IO02__SDMA_EXT_EVENT00 0x0064 0x02f0 0x0610 6 1
#define MX6UL_PAD_GPIO1_IO02__SRC_ANY_PU_RESET 0x0064 0x02f0 0x0000 7 0
#define MX6UL_PAD_GPIO1_IO02__UART1_DCE_TX 0x0064 0x02f0 0x0000 8 0
#define MX6UL_PAD_GPIO1_IO02__UART1_DTE_RX 0x0064 0x02f0 0x0624 8 0
#define MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x0068 0x02f4 0x05a8 0 1
#define MX6UL_PAD_GPIO1_IO03__GPT1_COMPARE3 0x0068 0x02f4 0x0000 1 0
#define MX6UL_PAD_GPIO1_IO03__USB_OTG2_OC 0x0068 0x02f4 0x0660 2 0
#define MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x0068 0x02f4 0x0000 3 0
#define MX6UL_PAD_GPIO1_IO03__USDHC1_CD_B 0x0068 0x02f4 0x0668 4 0
#define MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x0068 0x02f4 0x0000 5 0
#define MX6UL_PAD_GPIO1_IO03__CCM_DI0_EXT_CLK 0x0068 0x02f4 0x0000 6 0
#define MX6UL_PAD_GPIO1_IO03__SRC_TESTER_ACK 0x0068 0x02f4 0x0000 7 0
#define MX6UL_PAD_GPIO1_IO03__UART1_DCE_RX 0x0068 0x02f4 0x0624 8 1
#define MX6UL_PAD_GPIO1_IO03__UART1_DTE_TX 0x0068 0x02f4 0x0000 8 0
#define MX6UL_PAD_GPIO1_IO04__ENET1_REF_CLK1 0x006c 0x02f8 0x0574 0 1
#define MX6UL_PAD_GPIO1_IO04__PWM3_OUT 0x006c 0x02f8 0x0000 1 0
#define MX6UL_PAD_GPIO1_IO04__USB_OTG1_PWR 0x006c 0x02f8 0x0000 2 0
#define MX6UL_PAD_GPIO1_IO04__REF_CLK_24M 0x006c 0x02f8 0x0000 3 0
#define MX6UL_PAD_GPIO1_IO04__USDHC1_RESET_B 0x006c 0x02f8 0x0000 4 0
#define MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x006c 0x02f8 0x0000 5 0
#define MX6UL_PAD_GPIO1_IO04__ENET2_1588_EVENT0_IN 0x006c 0x02f8 0x0000 6 0
#define MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX 0x006c 0x02f8 0x0000 8 0
#define MX6UL_PAD_GPIO1_IO04__UART5_DTE_RX 0x006c 0x02f8 0x0644 8 2
#define MX6UL_PAD_GPIO1_IO05__ENET2_REF_CLK2 0x0070 0x02fc 0x057c 0 1
#define MX6UL_PAD_GPIO1_IO05__PWM4_OUT 0x0070 0x02fc 0x0000 1 0
#define MX6UL_PAD_GPIO1_IO05__ANATOP_OTG2_ID 0x0070 0x02fc 0x04bc 2 0
#define MX6UL_PAD_GPIO1_IO05__CSI_FIELD 0x0070 0x02fc 0x0530 3 0
#define MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x0070 0x02fc 0x0000 4 0
#define MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x0070 0x02fc 0x0000 5 0
#define MX6UL_PAD_GPIO1_IO05__ENET2_1588_EVENT0_OUT 0x0070 0x02fc 0x0000 6 0
#define MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX 0x0070 0x02fc 0x0644 8 3
#define MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX 0x0070 0x02fc 0x0000 8 0
#define MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x0074 0x0300 0x0578 0 0
#define MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x0074 0x0300 0x0580 1 0
#define MX6UL_PAD_GPIO1_IO06__USB_OTG_PWR_WAKE 0x0074 0x0300 0x0000 2 0
#define MX6UL_PAD_GPIO1_IO06__CSI_MCLK 0x0074 0x0300 0x0000 3 0
#define MX6UL_PAD_GPIO1_IO06__USDHC2_WP 0x0074 0x0300 0x069c 4 0
#define MX6UL_PAD_GPIO1_IO06__GPIO1_IO06 0x0074 0x0300 0x0000 5 0
#define MX6UL_PAD_GPIO1_IO06__CCM_WAIT 0x0074 0x0300 0x0000 6 0
#define MX6UL_PAD_GPIO1_IO06__CCM_REF_EN_B 0x0074 0x0300 0x0000 7 0
#define MX6UL_PAD_GPIO1_IO06__UART1_DCE_CTS 0x0074 0x0300 0x0000 8 0
#define MX6UL_PAD_GPIO1_IO06__UART1_DTE_RTS 0x0074 0x0300 0x0620 8 0
#define MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x0078 0x0304 0x0000 0 0
#define MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x0078 0x0304 0x0000 1 0
#define MX6UL_PAD_GPIO1_IO07__USB_OTG_HOST_MODE 0x0078 0x0304 0x0000 2 0
#define MX6UL_PAD_GPIO1_IO07__CSI_PIXCLK 0x0078 0x0304 0x0528 3 0
#define MX6UL_PAD_GPIO1_IO07__USDHC2_CD_B 0x0078 0x0304 0x0674 4 1
#define MX6UL_PAD_GPIO1_IO07__GPIO1_IO07 0x0078 0x0304 0x0000 5 0
#define MX6UL_PAD_GPIO1_IO07__CCM_STOP 0x0078 0x0304 0x0000 6 0
#define MX6UL_PAD_GPIO1_IO07__UART1_DCE_RTS 0x0078 0x0304 0x0620 8 1
#define MX6UL_PAD_GPIO1_IO07__UART1_DTE_CTS 0x0078 0x0304 0x0000 8 0
#define MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x007c 0x0308 0x0000 0 0
#define MX6UL_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x007c 0x0308 0x0000 1 0
#define MX6UL_PAD_GPIO1_IO08__SPDIF_OUT 0x007c 0x0308 0x0000 2 0
#define MX6UL_PAD_GPIO1_IO08__CSI_VSYNC 0x007c 0x0308 0x052c 3 1
#define MX6UL_PAD_GPIO1_IO08__USDHC2_VSELECT 0x007c 0x0308 0x0000 4 0
#define MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x007c 0x0308 0x0000 5 0
#define MX6UL_PAD_GPIO1_IO08__CCM_PMIC_RDY 0x007c 0x0308 0x04c0 6 1
#define MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x007c 0x0308 0x0640 8 1
#define MX6UL_PAD_GPIO1_IO08__UART5_DTE_CTS 0x007c 0x0308 0x0000 8 0
#define MX6UL_PAD_GPIO1_IO09__PWM2_OUT 0x0080 0x030c 0x0000 0 0
#define MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY 0x0080 0x030c 0x0000 1 0
#define MX6UL_PAD_GPIO1_IO09__SPDIF_IN 0x0080 0x030c 0x0618 2 0
#define MX6UL_PAD_GPIO1_IO09__CSI_HSYNC 0x0080 0x030c 0x0524 3 1
#define MX6UL_PAD_GPIO1_IO09__USDHC2_RESET_B 0x0080 0x030c 0x0000 4 0
#define MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x0080 0x030c 0x0000 5 0
#define MX6UL_PAD_GPIO1_IO09__USDHC1_RESET_B 0x0080 0x030c 0x0000 6 0
#define MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x0080 0x030c 0x0000 8 0
#define MX6UL_PAD_GPIO1_IO09__UART5_DTE_RTS 0x0080 0x030c 0x0640 8 2
#define MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x0084 0x0310 0x0000 0 0
#define MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX 0x0084 0x0310 0x0624 0 2
#define MX6UL_PAD_UART1_TX_DATA__ENET1_RDATA02 0x0084 0x0310 0x0000 1 0
#define MX6UL_PAD_UART1_TX_DATA__I2C3_SCL 0x0084 0x0310 0x05b4 2 0
#define MX6UL_PAD_UART1_TX_DATA__CSI_DATA02 0x0084 0x0310 0x04c4 3 1
#define MX6UL_PAD_UART1_TX_DATA__GPT1_COMPARE1 0x0084 0x0310 0x0000 4 0
#define MX6UL_PAD_UART1_TX_DATA__GPIO1_IO16 0x0084 0x0310 0x0000 5 0
#define MX6UL_PAD_UART1_TX_DATA__SPDIF_OUT 0x0084 0x0310 0x0000 8 0
#define MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x0088 0x0314 0x0624 0 3
#define MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX 0x0088 0x0314 0x0000 0 0
#define MX6UL_PAD_UART1_RX_DATA__ENET1_RDATA03 0x0088 0x0314 0x0000 1 0
#define MX6UL_PAD_UART1_RX_DATA__I2C3_SDA 0x0088 0x0314 0x05b8 2 0
#define MX6UL_PAD_UART1_RX_DATA__CSI_DATA03 0x0088 0x0314 0x04c8 3 1
#define MX6UL_PAD_UART1_RX_DATA__GPT1_CLK 0x0088 0x0314 0x0594 4 0
#define MX6UL_PAD_UART1_RX_DATA__GPIO1_IO17 0x0088 0x0314 0x0000 5 0
#define MX6UL_PAD_UART1_RX_DATA__SPDIF_IN 0x0088 0x0314 0x0618 8 1
#define MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS 0x008c 0x0318 0x0000 0 0
#define MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS 0x008c 0x0318 0x0620 0 2
#define MX6UL_PAD_UART1_CTS_B__ENET1_RX_CLK 0x008c 0x0318 0x0000 1 0
#define MX6UL_PAD_UART1_CTS_B__USDHC1_WP 0x008c 0x0318 0x066c 2 1
#define MX6UL_PAD_UART1_CTS_B__CSI_DATA04 0x008c 0x0318 0x04d8 3 0
#define MX6UL_PAD_UART1_CTS_B__ENET2_1588_EVENT1_IN 0x008c 0x0318 0x0000 4 0
#define MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x008c 0x0318 0x0000 5 0
#define MX6UL_PAD_UART1_CTS_B__USDHC2_WP 0x008c 0x0318 0x069c 8 1
#define MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS 0x0090 0x031c 0x0620 0 3
#define MX6UL_PAD_UART1_RTS_B__UART1_DTE_CTS 0x0090 0x031c 0x0000 0 0
#define MX6UL_PAD_UART1_RTS_B__ENET1_TX_ER 0x0090 0x031c 0x0000 1 0
#define MX6UL_PAD_UART1_RTS_B__USDHC1_CD_B 0x0090 0x031c 0x0668 2 1
#define MX6UL_PAD_UART1_RTS_B__CSI_DATA05 0x0090 0x031c 0x04cc 3 1
#define MX6UL_PAD_UART1_RTS_B__ENET2_1588_EVENT1_OUT 0x0090 0x031c 0x0000 4 0
#define MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0090 0x031c 0x0000 5 0
#define MX6UL_PAD_UART1_RTS_B__USDHC2_CD_B 0x0090 0x031c 0x0674 8 2
#define MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x0094 0x0320 0x0000 0 0
#define MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x0094 0x0320 0x062c 0 0
#define MX6UL_PAD_UART2_TX_DATA__ENET1_TDATA02 0x0094 0x0320 0x0000 1 0
#define MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x0094 0x0320 0x05bc 2 0
#define MX6UL_PAD_UART2_TX_DATA__CSI_DATA06 0x0094 0x0320 0x04dc 3 0
#define MX6UL_PAD_UART2_TX_DATA__GPT1_CAPTURE1 0x0094 0x0320 0x058c 4 1
#define MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x0094 0x0320 0x0000 5 0
#define MX6UL_PAD_UART2_TX_DATA__ECSPI3_SS0 0x0094 0x0320 0x0560 8 0
#define MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x0098 0x0324 0x062c 0 1
#define MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x0098 0x0324 0x0000 0 0
#define MX6UL_PAD_UART2_RX_DATA__ENET1_TDATA03 0x0098 0x0324 0x0000 1 0
#define MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x0098 0x0324 0x05c0 2 0
#define MX6UL_PAD_UART2_RX_DATA__CSI_DATA07 0x0098 0x0324 0x04e0 3 0
#define MX6UL_PAD_UART2_RX_DATA__GPT1_CAPTURE2 0x0098 0x0324 0x0590 4 0
#define MX6UL_PAD_UART2_RX_DATA__GPIO1_IO21 0x0098 0x0324 0x0000 5 0
#define MX6UL_PAD_UART2_RX_DATA__SJC_DONE 0x0098 0x0324 0x0000 7 0
#define MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x0098 0x0324 0x0554 8 0
#define MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x009c 0x0328 0x0000 0 0
#define MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS 0x009c 0x0328 0x0628 0 0
#define MX6UL_PAD_UART2_CTS_B__ENET1_CRS 0x009c 0x0328 0x0000 1 0
#define MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x009c 0x0328 0x0000 2 0
#define MX6UL_PAD_UART2_CTS_B__CSI_DATA08 0x009c 0x0328 0x04e4 3 0
#define MX6UL_PAD_UART2_CTS_B__GPT1_COMPARE2 0x009c 0x0328 0x0000 4 0
#define MX6UL_PAD_UART2_CTS_B__GPIO1_IO22 0x009c 0x0328 0x0000 5 0
#define MX6UL_PAD_UART2_CTS_B__SJC_DE_B 0x009c 0x0328 0x0000 7 0
#define MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x009c 0x0328 0x055c 8 0
#define MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x00a0 0x032c 0x0628 0 1
#define MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x00a0 0x032c 0x0000 0 0
#define MX6UL_PAD_UART2_RTS_B__ENET1_COL 0x00a0 0x032c 0x0000 1 0
#define MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x00a0 0x032c 0x0588 2 0
#define MX6UL_PAD_UART2_RTS_B__CSI_DATA09 0x00a0 0x032c 0x04e8 3 0
#define MX6UL_PAD_UART2_RTS_B__GPT1_COMPARE3 0x00a0 0x032c 0x0000 4 0
#define MX6UL_PAD_UART2_RTS_B__GPIO1_IO23 0x00a0 0x032c 0x0000 5 0
#define MX6UL_PAD_UART2_RTS_B__SJC_FAIL 0x00a0 0x032c 0x0000 7 0
#define MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x00a0 0x032c 0x0558 8 0
#define MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x00a4 0x0330 0x0000 0 0
#define MX6UL_PAD_UART3_TX_DATA__UART3_DTE_RX 0x00a4 0x0330 0x0634 0 0
#define MX6UL_PAD_UART3_TX_DATA__ENET2_RDATA02 0x00a4 0x0330 0x0000 1 0
#define MX6UL_PAD_UART3_TX_DATA__SIM1_PORT0_PD 0x00a4 0x0330 0x0000 2 0
#define MX6UL_PAD_UART3_TX_DATA__CSI_DATA01 0x00a4 0x0330 0x04d4 3 0
#define MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x00a4 0x0330 0x0000 4 0
#define MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS 0x00a4 0x0330 0x0628 4 2
#define MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x00a4 0x0330 0x0000 5 0
#define MX6UL_PAD_UART3_TX_DATA__SJC_JTAG_ACT 0x00a4 0x0330 0x0000 7 0
#define MX6UL_PAD_UART3_TX_DATA__ANATOP_OTG1_ID 0x00a4 0x0330 0x04b8 8 1
#define MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x00a8 0x0334 0x0634 0 1
#define MX6UL_PAD_UART3_RX_DATA__UART3_DTE_TX 0x00a8 0x0334 0x0000 0 0
#define MX6UL_PAD_UART3_RX_DATA__ENET2_RDATA03 0x00a8 0x0334 0x0000 1 0
#define MX6UL_PAD_UART3_RX_DATA__SIM2_PORT0_PD 0x00a8 0x0334 0x0000 2 0
#define MX6UL_PAD_UART3_RX_DATA__CSI_DATA00 0x00a8 0x0334 0x04d0 3 0
#define MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x00a8 0x0334 0x0628 4 3
#define MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS 0x00a8 0x0334 0x0000 4 0
#define MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x00a8 0x0334 0x0000 5 0
#define MX6UL_PAD_UART3_RX_DATA__EPIT1_OUT 0x00a8 0x0334 0x0000 8 0
#define MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x00ac 0x0338 0x0000 0 0
#define MX6UL_PAD_UART3_CTS_B__UART3_DTE_RTS 0x00ac 0x0338 0x0630 0 0
#define MX6UL_PAD_UART3_CTS_B__ENET2_RX_CLK 0x00ac 0x0338 0x0000 1 0
#define MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x00ac 0x0338 0x0000 2 0
#define MX6UL_PAD_UART3_CTS_B__CSI_DATA10 0x00ac 0x0338 0x04ec 3 0
#define MX6UL_PAD_UART3_CTS_B__ENET1_1588_EVENT1_IN 0x00ac 0x0338 0x0000 4 0
#define MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x00ac 0x0338 0x0000 5 0
#define MX6UL_PAD_UART3_CTS_B__EPIT2_OUT 0x00ac 0x0338 0x0000 8 0
#define MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x00b0 0x033c 0x0630 0 1
#define MX6UL_PAD_UART3_RTS_B__UART3_DTE_CTS 0x00b0 0x033c 0x0000 0 0
#define MX6UL_PAD_UART3_RTS_B__ENET2_TX_ER 0x00b0 0x033c 0x0000 1 0
#define MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x00b0 0x033c 0x0584 2 0
#define MX6UL_PAD_UART3_RTS_B__CSI_DATA11 0x00b0 0x033c 0x04f0 3 0
#define MX6UL_PAD_UART3_RTS_B__ENET1_1588_EVENT1_OUT 0x00b0 0x033c 0x0000 4 0
#define MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x00b0 0x033c 0x0000 5 0
#define MX6UL_PAD_UART3_RTS_B__WDOG1_WDOG_B 0x00b0 0x033c 0x0000 8 0
#define MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x00b4 0x0340 0x0000 0 0
#define MX6UL_PAD_UART4_TX_DATA__UART4_DTE_RX 0x00b4 0x0340 0x063c 0 0
#define MX6UL_PAD_UART4_TX_DATA__ENET2_TDATA02 0x00b4 0x0340 0x0000 1 0
#define MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x00b4 0x0340 0x05a4 2 1
#define MX6UL_PAD_UART4_TX_DATA__CSI_DATA12 0x00b4 0x0340 0x04f4 3 0
#define MX6UL_PAD_UART4_TX_DATA__CSU_CSU_ALARM_AUT02 0x00b4 0x0340 0x0000 4 0
#define MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x00b4 0x0340 0x0000 5 0
#define MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK 0x00b4 0x0340 0x0544 8 1
#define MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x00b8 0x0344 0x063c 0 1
#define MX6UL_PAD_UART4_RX_DATA__UART4_DTE_TX 0x00b8 0x0344 0x0000 0 0
#define MX6UL_PAD_UART4_RX_DATA__ENET2_TDATA03 0x00b8 0x0344 0x0000 1 0
#define MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x00b8 0x0344 0x05a8 2 2
#define MX6UL_PAD_UART4_RX_DATA__CSI_DATA13 0x00b8 0x0344 0x04f8 3 0
#define MX6UL_PAD_UART4_RX_DATA__CSU_CSU_ALARM_AUT01 0x00b8 0x0344 0x0000 4 0
#define MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x00b8 0x0344 0x0000 5 0
#define MX6UL_PAD_UART4_RX_DATA__ECSPI2_SS0 0x00b8 0x0344 0x0550 8 1
#define MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x00bc 0x0348 0x0000 5 0
#define MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI 0x00bc 0x0348 0x054c 8 0
#define MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x00bc 0x0348 0x0000 0 0
#define MX6UL_PAD_UART5_TX_DATA__UART5_DTE_RX 0x00bc 0x0348 0x0644 0 4
#define MX6UL_PAD_UART5_TX_DATA__ENET2_CRS 0x00bc 0x0348 0x0000 1 0
#define MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x00bc 0x0348 0x05ac 2 2
#define MX6UL_PAD_UART5_TX_DATA__CSI_DATA14 0x00bc 0x0348 0x04fc 3 0
#define MX6UL_PAD_UART5_TX_DATA__CSU_CSU_ALARM_AUT00 0x00bc 0x0348 0x0000 4 0
#define MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x00c0 0x034c 0x0644 0 5
#define MX6UL_PAD_UART5_RX_DATA__UART5_DTE_TX 0x00c0 0x034c 0x0000 0 0
#define MX6UL_PAD_UART5_RX_DATA__ENET2_COL 0x00c0 0x034c 0x0000 1 0
#define MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x00c0 0x034c 0x05b0 2 2
#define MX6UL_PAD_UART5_RX_DATA__CSI_DATA15 0x00c0 0x034c 0x0500 3 0
#define MX6UL_PAD_UART5_RX_DATA__CSU_CSU_INT_DEB 0x00c0 0x034c 0x0000 4 0
#define MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x00c0 0x034c 0x0000 5 0
#define MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO 0x00c0 0x034c 0x0548 8 1
#define MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x00c4 0x0350 0x0000 0 0
#define MX6UL_PAD_ENET1_RX_DATA0__UART4_DCE_RTS 0x00c4 0x0350 0x0638 1 0
#define MX6UL_PAD_ENET1_RX_DATA0__UART4_DTE_CTS 0x00c4 0x0350 0x0000 1 0
#define MX6UL_PAD_ENET1_RX_DATA0__PWM1_OUT 0x00c4 0x0350 0x0000 2 0
#define MX6UL_PAD_ENET1_RX_DATA0__CSI_DATA16 0x00c4 0x0350 0x0504 3 0
#define MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x00c4 0x0350 0x0000 4 0
#define MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0x00c4 0x0350 0x0000 5 0
#define MX6UL_PAD_ENET1_RX_DATA0__KPP_ROW00 0x00c4 0x0350 0x05d0 6 0
#define MX6UL_PAD_ENET1_RX_DATA0__USDHC1_LCTL 0x00c4 0x0350 0x0000 8 0
#define MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x00c8 0x0354 0x0000 0 0
#define MX6UL_PAD_ENET1_RX_DATA1__UART4_DCE_CTS 0x00c8 0x0354 0x0000 1 0
#define MX6UL_PAD_ENET1_RX_DATA1__UART4_DTE_RTS 0x00c8 0x0354 0x0638 1 1
#define MX6UL_PAD_ENET1_RX_DATA1__PWM2_OUT 0x00c8 0x0354 0x0000 2 0
#define MX6UL_PAD_ENET1_RX_DATA1__CSI_DATA17 0x00c8 0x0354 0x0508 3 0
#define MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x00c8 0x0354 0x0584 4 1
#define MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0x00c8 0x0354 0x0000 5 0
#define MX6UL_PAD_ENET1_RX_DATA1__KPP_COL00 0x00c8 0x0354 0x05c4 6 0
#define MX6UL_PAD_ENET1_RX_DATA1__USDHC2_LCTL 0x00c8 0x0354 0x0000 8 0
#define MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x00cc 0x0358 0x0000 0 0
#define MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS 0x00cc 0x0358 0x0640 1 3
#define MX6UL_PAD_ENET1_RX_EN__UART5_DTE_CTS 0x00cc 0x0358 0x0000 1 0
#define MX6UL_PAD_ENET1_RX_EN__OSC32K_32K_OUT 0x00cc 0x0358 0x0000 2 0
#define MX6UL_PAD_ENET1_RX_EN__CSI_DATA18 0x00cc 0x0358 0x050c 3 0
#define MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x00cc 0x0358 0x0000 4 0
#define MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02 0x00cc 0x0358 0x0000 5 0
#define MX6UL_PAD_ENET1_RX_EN__KPP_ROW01 0x00cc 0x0358 0x05d4 6 0
#define MX6UL_PAD_ENET1_RX_EN__USDHC1_VSELECT 0x00cc 0x0358 0x0000 8 0
#define MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x00d0 0x035c 0x0000 0 0
#define MX6UL_PAD_ENET1_TX_DATA0__UART5_DCE_CTS 0x00d0 0x035c 0x0000 1 0
#define MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS 0x00d0 0x035c 0x0640 1 4
#define MX6UL_PAD_ENET1_TX_DATA0__REF_CLK_24M 0x00d0 0x035c 0x0000 2 0
#define MX6UL_PAD_ENET1_TX_DATA0__CSI_DATA19 0x00d0 0x035c 0x0510 3 0
#define MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x00d0 0x035c 0x0588 4 1
#define MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03 0x00d0 0x035c 0x0000 5 0
#define MX6UL_PAD_ENET1_TX_DATA0__KPP_COL01 0x00d0 0x035c 0x05c8 6 0
#define MX6UL_PAD_ENET1_TX_DATA0__USDHC2_VSELECT 0x00d0 0x035c 0x0000 8 0
#define MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x00d4 0x0360 0x0000 0 0
#define MX6UL_PAD_ENET1_TX_DATA1__UART6_DCE_CTS 0x00d4 0x0360 0x0000 1 0
#define MX6UL_PAD_ENET1_TX_DATA1__UART6_DTE_RTS 0x00d4 0x0360 0x0648 1 2
#define MX6UL_PAD_ENET1_TX_DATA1__PWM5_OUT 0x00d4 0x0360 0x0000 2 0
#define MX6UL_PAD_ENET1_TX_DATA1__CSI_DATA20 0x00d4 0x0360 0x0514 3 0
#define MX6UL_PAD_ENET1_TX_DATA1__ENET2_MDIO 0x00d4 0x0360 0x0580 4 1
#define MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0x00d4 0x0360 0x0000 5 0
#define MX6UL_PAD_ENET1_TX_DATA1__KPP_ROW02 0x00d4 0x0360 0x05d8 6 0
#define MX6UL_PAD_ENET1_TX_DATA1__WDOG1_WDOG_RST_B_DEB 0x00d4 0x0360 0x0000 8 0
#define MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x00d8 0x0364 0x0000 0 0
#define MX6UL_PAD_ENET1_TX_EN__UART6_DCE_RTS 0x00d8 0x0364 0x0648 1 3
#define MX6UL_PAD_ENET1_TX_EN__UART6_DTE_CTS 0x00d8 0x0364 0x0000 1 0
#define MX6UL_PAD_ENET1_TX_EN__PWM6_OUT 0x00d8 0x0364 0x0000 2 0
#define MX6UL_PAD_ENET1_TX_EN__CSI_DATA21 0x00d8 0x0364 0x0518 3 0
#define MX6UL_PAD_ENET1_TX_EN__ENET2_MDC 0x00d8 0x0364 0x0000 4 0
#define MX6UL_PAD_ENET1_TX_EN__GPIO2_IO05 0x00d8 0x0364 0x0000 5 0
#define MX6UL_PAD_ENET1_TX_EN__KPP_COL02 0x00d8 0x0364 0x05cc 6 0
#define MX6UL_PAD_ENET1_TX_EN__WDOG2_WDOG_RST_B_DEB 0x00d8 0x0364 0x0000 8 0
#define MX6UL_PAD_ENET1_TX_CLK__ENET1_TX_CLK 0x00dc 0x0368 0x0000 0 0
#define MX6UL_PAD_ENET1_TX_CLK__UART7_DCE_CTS 0x00dc 0x0368 0x0000 1 0
#define MX6UL_PAD_ENET1_TX_CLK__UART7_DTE_RTS 0x00dc 0x0368 0x0650 1 0
#define MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x00dc 0x0368 0x0000 2 0
#define MX6UL_PAD_ENET1_TX_CLK__CSI_DATA22 0x00dc 0x0368 0x051c 3 0
#define MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x00dc 0x0368 0x0574 4 2
#define MX6UL_PAD_ENET1_TX_CLK__GPIO2_IO06 0x00dc 0x0368 0x0000 5 0
#define MX6UL_PAD_ENET1_TX_CLK__KPP_ROW03 0x00dc 0x0368 0x0000 6 0
#define MX6UL_PAD_ENET1_TX_CLK__GPT1_CLK 0x00dc 0x0368 0x0594 8 1
#define MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x00e0 0x036c 0x0000 0 0
#define MX6UL_PAD_ENET1_RX_ER__UART7_DCE_RTS 0x00e0 0x036c 0x0650 1 1
#define MX6UL_PAD_ENET1_RX_ER__UART7_DTE_CTS 0x00e0 0x036c 0x0000 1 0
#define MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x00e0 0x036c 0x0000 2 0
#define MX6UL_PAD_ENET1_RX_ER__CSI_DATA23 0x00e0 0x036c 0x0520 3 0
#define MX6UL_PAD_ENET1_RX_ER__EIM_CRE 0x00e0 0x036c 0x0000 4 0
#define MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07 0x00e0 0x036c 0x0000 5 0
#define MX6UL_PAD_ENET1_RX_ER__KPP_COL03 0x00e0 0x036c 0x0000 6 0
#define MX6UL_PAD_ENET1_RX_ER__GPT1_CAPTURE2 0x00e0 0x036c 0x0590 8 1
#define MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x00e4 0x0370 0x0000 0 0
#define MX6UL_PAD_ENET2_RX_DATA0__UART6_DCE_TX 0x00e4 0x0370 0x0000 1 0
#define MX6UL_PAD_ENET2_RX_DATA0__UART6_DTE_RX 0x00e4 0x0370 0x064c 1 1
#define MX6UL_PAD_ENET2_RX_DATA0__SIM1_PORT0_TRXD 0x00e4 0x0370 0x0000 2 0
#define MX6UL_PAD_ENET2_RX_DATA0__I2C3_SCL 0x00e4 0x0370 0x05b4 3 1
#define MX6UL_PAD_ENET2_RX_DATA0__ENET1_MDIO 0x00e4 0x0370 0x0578 4 1
#define MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x00e4 0x0370 0x0000 5 0
#define MX6UL_PAD_ENET2_RX_DATA0__KPP_ROW04 0x00e4 0x0370 0x0000 6 0
#define MX6UL_PAD_ENET2_RX_DATA0__USB_OTG1_PWR 0x00e4 0x0370 0x0000 8 0
#define MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x00e8 0x0374 0x0000 0 0
#define MX6UL_PAD_ENET2_RX_DATA1__UART6_DCE_RX 0x00e8 0x0374 0x064c 1 2
#define MX6UL_PAD_ENET2_RX_DATA1__UART6_DTE_TX 0x00e8 0x0374 0x0000 1 0
#define MX6UL_PAD_ENET2_RX_DATA1__SIM1_PORT0_CLK 0x00e8 0x0374 0x0000 2 0
#define MX6UL_PAD_ENET2_RX_DATA1__I2C3_SDA 0x00e8 0x0374 0x05b8 3 1
#define MX6UL_PAD_ENET2_RX_DATA1__ENET1_MDC 0x00e8 0x0374 0x0000 4 0
#define MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x00e8 0x0374 0x0000 5 0
#define MX6UL_PAD_ENET2_RX_DATA1__KPP_COL04 0x00e8 0x0374 0x0000 6 0
#define MX6UL_PAD_ENET2_RX_DATA1__USB_OTG1_OC 0x00e8 0x0374 0x0664 8 1
#define MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x00ec 0x0378 0x0000 0 0
#define MX6UL_PAD_ENET2_RX_EN__UART7_DCE_TX 0x00ec 0x0378 0x0000 1 0
#define MX6UL_PAD_ENET2_RX_EN__UART7_DTE_RX 0x00ec 0x0378 0x0654 1 0
#define MX6UL_PAD_ENET2_RX_EN__SIM1_PORT0_RST_B 0x00ec 0x0378 0x0000 2 0
#define MX6UL_PAD_ENET2_RX_EN__I2C4_SCL 0x00ec 0x0378 0x05bc 3 1
#define MX6UL_PAD_ENET2_RX_EN__EIM_ADDR26 0x00ec 0x0378 0x0000 4 0
#define MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x00ec 0x0378 0x0000 5 0
#define MX6UL_PAD_ENET2_RX_EN__KPP_ROW05 0x00ec 0x0378 0x0000 6 0
#define MX6UL_PAD_ENET2_RX_EN__ENET1_REF_CLK_25M 0x00ec 0x0378 0x0000 8 0
#define MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x00f0 0x037c 0x0000 0 0
#define MX6UL_PAD_ENET2_TX_DATA0__UART7_DCE_RX 0x00f0 0x037c 0x0654 1 1
#define MX6UL_PAD_ENET2_TX_DATA0__UART7_DTE_TX 0x00f0 0x037c 0x0000 1 0
#define MX6UL_PAD_ENET2_TX_DATA0__SIM1_PORT0_SVEN 0x00f0 0x037c 0x0000 2 0
#define MX6UL_PAD_ENET2_TX_DATA0__I2C4_SDA 0x00f0 0x037c 0x05c0 3 1
#define MX6UL_PAD_ENET2_TX_DATA0__EIM_EB_B02 0x00f0 0x037c 0x0000 4 0
#define MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x00f0 0x037c 0x0000 5 0
#define MX6UL_PAD_ENET2_TX_DATA0__KPP_COL05 0x00f0 0x037c 0x0000 6 0
#define MX6UL_PAD_ENET2_TX_DATA0__REF_CLK_24M 0x00f0 0x037c 0x0000 8 0
#define MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x00f4 0x0380 0x0000 0 0
#define MX6UL_PAD_ENET2_TX_DATA1__UART8_DCE_TX 0x00f4 0x0380 0x0000 1 0
#define MX6UL_PAD_ENET2_TX_DATA1__UART8_DTE_RX 0x00f4 0x0380 0x065c 1 0
#define MX6UL_PAD_ENET2_TX_DATA1__SIM2_PORT0_TRXD 0x00f4 0x0380 0x0000 2 0
#define MX6UL_PAD_ENET2_TX_DATA1__ECSPI4_SCLK 0x00f4 0x0380 0x0564 3 0
#define MX6UL_PAD_ENET2_TX_DATA1__EIM_EB_B03 0x00f4 0x0380 0x0000 4 0
#define MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 0x00f4 0x0380 0x0000 5 0
#define MX6UL_PAD_ENET2_TX_DATA1__KPP_ROW06 0x00f4 0x0380 0x0000 6 0
#define MX6UL_PAD_ENET2_TX_DATA1__USB_OTG2_PWR 0x00f4 0x0380 0x0000 8 0
#define MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x00f8 0x0384 0x0000 0 0
#define MX6UL_PAD_ENET2_TX_EN__UART8_DCE_RX 0x00f8 0x0384 0x065c 1 1
#define MX6UL_PAD_ENET2_TX_EN__UART8_DTE_TX 0x00f8 0x0384 0x0000 1 0
#define MX6UL_PAD_ENET2_TX_EN__SIM2_PORT0_CLK 0x00f8 0x0384 0x0000 2 0
#define MX6UL_PAD_ENET2_TX_EN__ECSPI4_MOSI 0x00f8 0x0384 0x056c 3 0
#define MX6UL_PAD_ENET2_TX_EN__EIM_ACLK_FREERUN 0x00f8 0x0384 0x0000 4 0
#define MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x00f8 0x0384 0x0000 5 0
#define MX6UL_PAD_ENET2_TX_EN__KPP_COL06 0x00f8 0x0384 0x0000 6 0
#define MX6UL_PAD_ENET2_TX_EN__USB_OTG2_OC 0x00f8 0x0384 0x0660 8 1
#define MX6UL_PAD_ENET2_TX_CLK__ENET2_TX_CLK 0x00fc 0x0388 0x0000 0 0
#define MX6UL_PAD_ENET2_TX_CLK__UART8_DCE_CTS 0x00fc 0x0388 0x0000 1 0
#define MX6UL_PAD_ENET2_TX_CLK__UART8_DTE_RTS 0x00fc 0x0388 0x0658 1 0
#define MX6UL_PAD_ENET2_TX_CLK__SIM2_PORT0_RST_B 0x00fc 0x0388 0x0000 2 0
#define MX6UL_PAD_ENET2_TX_CLK__ECSPI4_MISO 0x00fc 0x0388 0x0568 3 0
#define MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x00fc 0x0388 0x057c 4 2
#define MX6UL_PAD_ENET2_TX_CLK__GPIO2_IO14 0x00fc 0x0388 0x0000 5 0
#define MX6UL_PAD_ENET2_TX_CLK__KPP_ROW07 0x00fc 0x0388 0x0000 6 0
#define MX6UL_PAD_ENET2_TX_CLK__ANATOP_OTG2_ID 0x00fc 0x0388 0x04bc 8 1
#define MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x0100 0x038c 0x0000 0 0
#define MX6UL_PAD_ENET2_RX_ER__UART8_DCE_RTS 0x0100 0x038c 0x0658 1 1
#define MX6UL_PAD_ENET2_RX_ER__UART8_DTE_CTS 0x0100 0x038c 0x0000 1 0
#define MX6UL_PAD_ENET2_RX_ER__SIM2_PORT0_SVEN 0x0100 0x038c 0x0000 2 0
#define MX6UL_PAD_ENET2_RX_ER__ECSPI4_SS0 0x0100 0x038c 0x0570 3 0
#define MX6UL_PAD_ENET2_RX_ER__EIM_ADDR25 0x0100 0x038c 0x0000 4 0
#define MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x0100 0x038c 0x0000 5 0
#define MX6UL_PAD_ENET2_RX_ER__KPP_COL07 0x0100 0x038c 0x0000 6 0
#define MX6UL_PAD_ENET2_RX_ER__WDOG1_WDOG_ANY 0x0100 0x038c 0x0000 8 0
#define MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x0104 0x0390 0x0000 0 0
#define MX6UL_PAD_LCD_CLK__LCDIF_WR_RWN 0x0104 0x0390 0x0000 1 0
#define MX6UL_PAD_LCD_CLK__UART4_DCE_TX 0x0104 0x0390 0x0000 2 0
#define MX6UL_PAD_LCD_CLK__UART4_DTE_RX 0x0104 0x0390 0x063c 2 2
#define MX6UL_PAD_LCD_CLK__SAI3_MCLK 0x0104 0x0390 0x0600 3 0
#define MX6UL_PAD_LCD_CLK__EIM_CS2_B 0x0104 0x0390 0x0000 4 0
#define MX6UL_PAD_LCD_CLK__GPIO3_IO00 0x0104 0x0390 0x0000 5 0
#define MX6UL_PAD_LCD_CLK__WDOG1_WDOG_RST_B_DEB 0x0104 0x0390 0x0000 8 0
#define MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x0108 0x0394 0x0000 0 0
#define MX6UL_PAD_LCD_ENABLE__LCDIF_RD_E 0x0108 0x0394 0x0000 1 0
#define MX6UL_PAD_LCD_ENABLE__UART4_DCE_RX 0x0108 0x0394 0x063c 2 3
#define MX6UL_PAD_LCD_ENABLE__UART4_DTE_TX 0x0108 0x0394 0x0000 2 0
#define MX6UL_PAD_LCD_ENABLE__SAI3_TX_SYNC 0x0108 0x0394 0x060c 3 0
#define MX6UL_PAD_LCD_ENABLE__EIM_CS3_B 0x0108 0x0394 0x0000 4 0
#define MX6UL_PAD_LCD_ENABLE__GPIO3_IO01 0x0108 0x0394 0x0000 5 0
#define MX6UL_PAD_LCD_ENABLE__ECSPI2_RDY 0x0108 0x0394 0x0000 8 0
#define MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x010c 0x0398 0x05dc 0 0
#define MX6UL_PAD_LCD_HSYNC__LCDIF_RS 0x010c 0x0398 0x0000 1 0
#define MX6UL_PAD_LCD_HSYNC__UART4_DCE_CTS 0x010c 0x0398 0x0000 2 0
#define MX6UL_PAD_LCD_HSYNC__UART4_DTE_RTS 0x010c 0x0398 0x0638 2 2
#define MX6UL_PAD_LCD_HSYNC__SAI3_TX_BCLK 0x010c 0x0398 0x0608 3 0
#define MX6UL_PAD_LCD_HSYNC__WDOG3_WDOG_RST_B_DEB 0x010c 0x0398 0x0000 4 0
#define MX6UL_PAD_LCD_HSYNC__GPIO3_IO02 0x010c 0x0398 0x0000 5 0
#define MX6UL_PAD_LCD_HSYNC__ECSPI2_SS1 0x010c 0x0398 0x0000 8 0
#define MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x0110 0x039c 0x0000 0 0
#define MX6UL_PAD_LCD_VSYNC__LCDIF_BUSY 0x0110 0x039c 0x05dc 1 1
#define MX6UL_PAD_LCD_VSYNC__UART4_DCE_RTS 0x0110 0x039c 0x0638 2 3
#define MX6UL_PAD_LCD_VSYNC__UART4_DTE_CTS 0x0110 0x039c 0x0000 2 0
#define MX6UL_PAD_LCD_VSYNC__SAI3_RX_DATA 0x0110 0x039c 0x0604 3 0
#define MX6UL_PAD_LCD_VSYNC__WDOG2_WDOG_B 0x0110 0x039c 0x0000 4 0
#define MX6UL_PAD_LCD_VSYNC__GPIO3_IO03 0x0110 0x039c 0x0000 5 0
#define MX6UL_PAD_LCD_VSYNC__ECSPI2_SS2 0x0110 0x039c 0x0000 8 0
#define MX6UL_PAD_LCD_RESET__LCDIF_RESET 0x0114 0x03a0 0x0000 0 0
#define MX6UL_PAD_LCD_RESET__LCDIF_CS 0x0114 0x03a0 0x0000 1 0
#define MX6UL_PAD_LCD_RESET__CA7_MX6UL_EVENTI 0x0114 0x03a0 0x0000 2 0
#define MX6UL_PAD_LCD_RESET__SAI3_TX_DATA 0x0114 0x03a0 0x0000 3 0
#define MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x0114 0x03a0 0x0000 4 0
#define MX6UL_PAD_LCD_RESET__GPIO3_IO04 0x0114 0x03a0 0x0000 5 0
#define MX6UL_PAD_LCD_RESET__ECSPI2_SS3 0x0114 0x03a0 0x0000 8 0
#define MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x0118 0x03a4 0x0000 0 0
#define MX6UL_PAD_LCD_DATA00__PWM1_OUT 0x0118 0x03a4 0x0000 1 0
#define MX6UL_PAD_LCD_DATA00__CA7_MX6UL_TRACE0 0x0118 0x03a4 0x0000 2 0
#define MX6UL_PAD_LCD_DATA00__ENET1_1588_EVENT2_IN 0x0118 0x03a4 0x0000 3 0
#define MX6UL_PAD_LCD_DATA00__I2C3_SDA 0x0118 0x03a4 0x05b8 4 2
#define MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0x0118 0x03a4 0x0000 5 0
#define MX6UL_PAD_LCD_DATA00__SRC_BT_CFG00 0x0118 0x03a4 0x0000 6 0
#define MX6UL_PAD_LCD_DATA00__SAI1_MCLK 0x0118 0x03a4 0x05e0 8 1
#define MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x011c 0x03a8 0x0000 0 0
#define MX6UL_PAD_LCD_DATA01__PWM2_OUT 0x011c 0x03a8 0x0000 1 0
#define MX6UL_PAD_LCD_DATA01__CA7_MX6UL_TRACE1 0x011c 0x03a8 0x0000 2 0
#define MX6UL_PAD_LCD_DATA01__ENET1_1588_EVENT2_OUT 0x011c 0x03a8 0x0000 3 0
#define MX6UL_PAD_LCD_DATA01__I2C3_SCL 0x011c 0x03a8 0x05b4 4 2
#define MX6UL_PAD_LCD_DATA01__GPIO3_IO06 0x011c 0x03a8 0x0000 5 0
#define MX6UL_PAD_LCD_DATA01__SRC_BT_CFG01 0x011c 0x03a8 0x0000 6 0
#define MX6UL_PAD_LCD_DATA01__SAI1_TX_SYNC 0x011c 0x03a8 0x05ec 8 0
#define MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x0120 0x03ac 0x0000 0 0
#define MX6UL_PAD_LCD_DATA02__PWM3_OUT 0x0120 0x03ac 0x0000 1 0
#define MX6UL_PAD_LCD_DATA02__CA7_MX6UL_TRACE2 0x0120 0x03ac 0x0000 2 0
#define MX6UL_PAD_LCD_DATA02__ENET1_1588_EVENT3_IN 0x0120 0x03ac 0x0000 3 0
#define MX6UL_PAD_LCD_DATA02__I2C4_SDA 0x0120 0x03ac 0x05c0 4 2
#define MX6UL_PAD_LCD_DATA02__GPIO3_IO07 0x0120 0x03ac 0x0000 5 0
#define MX6UL_PAD_LCD_DATA02__SRC_BT_CFG02 0x0120 0x03ac 0x0000 6 0
#define MX6UL_PAD_LCD_DATA02__SAI1_TX_BCLK 0x0120 0x03ac 0x05e8 8 0
#define MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x0124 0x03b0 0x0000 0 0
#define MX6UL_PAD_LCD_DATA03__PWM4_OUT 0x0124 0x03b0 0x0000 1 0
#define MX6UL_PAD_LCD_DATA03__CA7_MX6UL_TRACE3 0x0124 0x03b0 0x0000 2 0
#define MX6UL_PAD_LCD_DATA03__ENET1_1588_EVENT3_OUT 0x0124 0x03b0 0x0000 3 0
#define MX6UL_PAD_LCD_DATA03__I2C4_SCL 0x0124 0x03b0 0x05bc 4 2
#define MX6UL_PAD_LCD_DATA03__GPIO3_IO08 0x0124 0x03b0 0x0000 5 0
#define MX6UL_PAD_LCD_DATA03__SRC_BT_CFG03 0x0124 0x03b0 0x0000 6 0
#define MX6UL_PAD_LCD_DATA03__SAI1_RX_DATA 0x0124 0x03b0 0x05e4 8 0
#define MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x0128 0x03b4 0x0000 0 0
#define MX6UL_PAD_LCD_DATA04__UART8_DCE_CTS 0x0128 0x03b4 0x0000 1 0
#define MX6UL_PAD_LCD_DATA04__UART8_DTE_RTS 0x0128 0x03b4 0x0658 1 2
#define MX6UL_PAD_LCD_DATA04__CA7_MX6UL_TRACE4 0x0128 0x03b4 0x0000 2 0
#define MX6UL_PAD_LCD_DATA04__ENET2_1588_EVENT2_IN 0x0128 0x03b4 0x0000 3 0
#define MX6UL_PAD_LCD_DATA04__SPDIF_SR_CLK 0x0128 0x03b4 0x0000 4 0
#define MX6UL_PAD_LCD_DATA04__GPIO3_IO09 0x0128 0x03b4 0x0000 5 0
#define MX6UL_PAD_LCD_DATA04__SRC_BT_CFG04 0x0128 0x03b4 0x0000 6 0
#define MX6UL_PAD_LCD_DATA04__SAI1_TX_DATA 0x0128 0x03b4 0x0000 8 0
#define MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x012c 0x03b8 0x0000 0 0
#define MX6UL_PAD_LCD_DATA05__UART8_DCE_RTS 0x012c 0x03b8 0x0658 1 3
#define MX6UL_PAD_LCD_DATA05__UART8_DTE_CTS 0x012c 0x03b8 0x0000 1 0
#define MX6UL_PAD_LCD_DATA05__CA7_MX6UL_TRACE5 0x012c 0x03b8 0x0000 2 0
#define MX6UL_PAD_LCD_DATA05__ENET2_1588_EVENT2_OUT 0x012c 0x03b8 0x0000 3 0
#define MX6UL_PAD_LCD_DATA05__SPDIF_OUT 0x012c 0x03b8 0x0000 4 0
#define MX6UL_PAD_LCD_DATA05__GPIO3_IO10 0x012c 0x03b8 0x0000 5 0
#define MX6UL_PAD_LCD_DATA05__SRC_BT_CFG05 0x012c 0x03b8 0x0000 6 0
#define MX6UL_PAD_LCD_DATA05__ECSPI1_SS1 0x012c 0x03b8 0x0000 8 0
#define MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x0130 0x03bc 0x0000 0 0
#define MX6UL_PAD_LCD_DATA06__UART7_DCE_CTS 0x0130 0x03bc 0x0000 1 0
#define MX6UL_PAD_LCD_DATA06__UART7_DTE_RTS 0x0130 0x03bc 0x0650 1 2
#define MX6UL_PAD_LCD_DATA06__CA7_MX6UL_TRACE6 0x0130 0x03bc 0x0000 2 0
#define MX6UL_PAD_LCD_DATA06__ENET2_1588_EVENT3_IN 0x0130 0x03bc 0x0000 3 0
#define MX6UL_PAD_LCD_DATA06__SPDIF_LOCK 0x0130 0x03bc 0x0000 4 0
#define MX6UL_PAD_LCD_DATA06__GPIO3_IO11 0x0130 0x03bc 0x0000 5 0
#define MX6UL_PAD_LCD_DATA06__SRC_BT_CFG06 0x0130 0x03bc 0x0000 6 0
#define MX6UL_PAD_LCD_DATA06__ECSPI1_SS2 0x0130 0x03bc 0x0000 8 0
#define MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x0134 0x03c0 0x0000 0 0
#define MX6UL_PAD_LCD_DATA07__UART7_DCE_RTS 0x0134 0x03c0 0x0650 1 3
#define MX6UL_PAD_LCD_DATA07__UART7_DTE_CTS 0x0134 0x03c0 0x0000 1 0
#define MX6UL_PAD_LCD_DATA07__CA7_MX6UL_TRACE7 0x0134 0x03c0 0x0000 2 0
#define MX6UL_PAD_LCD_DATA07__ENET2_1588_EVENT3_OUT 0x0134 0x03c0 0x0000 3 0
#define MX6UL_PAD_LCD_DATA07__SPDIF_EXT_CLK 0x0134 0x03c0 0x061c 4 0
#define MX6UL_PAD_LCD_DATA07__GPIO3_IO12 0x0134 0x03c0 0x0000 5 0
#define MX6UL_PAD_LCD_DATA07__SRC_BT_CFG07 0x0134 0x03c0 0x0000 6 0
#define MX6UL_PAD_LCD_DATA07__ECSPI1_SS3 0x0134 0x03c0 0x0000 8 0
#define MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x0138 0x03c4 0x0000 0 0
#define MX6UL_PAD_LCD_DATA08__SPDIF_IN 0x0138 0x03c4 0x0618 1 2
#define MX6UL_PAD_LCD_DATA08__CA7_MX6UL_TRACE8 0x0138 0x03c4 0x0000 2 0
#define MX6UL_PAD_LCD_DATA08__CSI_DATA16 0x0138 0x03c4 0x0504 3 1
#define MX6UL_PAD_LCD_DATA08__EIM_DATA00 0x0138 0x03c4 0x0000 4 0
#define MX6UL_PAD_LCD_DATA08__GPIO3_IO13 0x0138 0x03c4 0x0000 5 0
#define MX6UL_PAD_LCD_DATA08__SRC_BT_CFG08 0x0138 0x03c4 0x0000 6 0
#define MX6UL_PAD_LCD_DATA08__FLEXCAN1_TX 0x0138 0x03c4 0x0000 8 0
#define MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x013c 0x03c8 0x0000 0 0
#define MX6UL_PAD_LCD_DATA09__SAI3_MCLK 0x013c 0x03c8 0x0600 1 1
#define MX6UL_PAD_LCD_DATA09__CA7_MX6UL_TRACE9 0x013c 0x03c8 0x0000 2 0
#define MX6UL_PAD_LCD_DATA09__CSI_DATA17 0x013c 0x03c8 0x0508 3 1
#define MX6UL_PAD_LCD_DATA09__EIM_DATA01 0x013c 0x03c8 0x0000 4 0
#define MX6UL_PAD_LCD_DATA09__GPIO3_IO14 0x013c 0x03c8 0x0000 5 0
#define MX6UL_PAD_LCD_DATA09__SRC_BT_CFG09 0x013c 0x03c8 0x0000 6 0
#define MX6UL_PAD_LCD_DATA09__FLEXCAN1_RX 0x013c 0x03c8 0x0584 8 2
#define MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x0140 0x03cc 0x0000 0 0
#define MX6UL_PAD_LCD_DATA10__SAI3_RX_SYNC 0x0140 0x03cc 0x0000 1 0
#define MX6UL_PAD_LCD_DATA10__CA7_MX6UL_TRACE10 0x0140 0x03cc 0x0000 2 0
#define MX6UL_PAD_LCD_DATA10__CSI_DATA18 0x0140 0x03cc 0x050c 3 1
#define MX6UL_PAD_LCD_DATA10__EIM_DATA02 0x0140 0x03cc 0x0000 4 0
#define MX6UL_PAD_LCD_DATA10__GPIO3_IO15 0x0140 0x03cc 0x0000 5 0
#define MX6UL_PAD_LCD_DATA10__SRC_BT_CFG10 0x0140 0x03cc 0x0000 6 0
#define MX6UL_PAD_LCD_DATA10__FLEXCAN2_TX 0x0140 0x03cc 0x0000 8 0
#define MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x0144 0x03d0 0x0000 0 0
#define MX6UL_PAD_LCD_DATA11__SAI3_RX_BCLK 0x0144 0x03d0 0x0000 1 0
#define MX6UL_PAD_LCD_DATA11__CA7_MX6UL_TRACE11 0x0144 0x03d0 0x0000 2 0
#define MX6UL_PAD_LCD_DATA11__CSI_DATA19 0x0144 0x03d0 0x0510 3 1
#define MX6UL_PAD_LCD_DATA11__EIM_DATA03 0x0144 0x03d0 0x0000 4 0
#define MX6UL_PAD_LCD_DATA11__GPIO3_IO16 0x0144 0x03d0 0x0000 5 0
#define MX6UL_PAD_LCD_DATA11__SRC_BT_CFG11 0x0144 0x03d0 0x0000 6 0
#define MX6UL_PAD_LCD_DATA11__FLEXCAN2_RX 0x0144 0x03d0 0x0588 8 2
#define MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x0148 0x03d4 0x0000 0 0
#define MX6UL_PAD_LCD_DATA12__SAI3_TX_SYNC 0x0148 0x03d4 0x060c 1 1
#define MX6UL_PAD_LCD_DATA12__CA7_MX6UL_TRACE12 0x0148 0x03d4 0x0000 2 0
#define MX6UL_PAD_LCD_DATA12__CSI_DATA20 0x0148 0x03d4 0x0514 3 1
#define MX6UL_PAD_LCD_DATA12__EIM_DATA04 0x0148 0x03d4 0x0000 4 0
#define MX6UL_PAD_LCD_DATA12__GPIO3_IO17 0x0148 0x03d4 0x0000 5 0
#define MX6UL_PAD_LCD_DATA12__SRC_BT_CFG12 0x0148 0x03d4 0x0000 6 0
#define MX6UL_PAD_LCD_DATA12__ECSPI1_RDY 0x0148 0x03d4 0x0000 8 0
#define MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x014c 0x03d8 0x0000 0 0
#define MX6UL_PAD_LCD_DATA13__SAI3_TX_BCLK 0x014c 0x03d8 0x0608 1 1
#define MX6UL_PAD_LCD_DATA13__CA7_MX6UL_TRACE13 0x014c 0x03d8 0x0000 2 0
#define MX6UL_PAD_LCD_DATA13__CSI_DATA21 0x014c 0x03d8 0x0518 3 1
#define MX6UL_PAD_LCD_DATA13__EIM_DATA05 0x014c 0x03d8 0x0000 4 0
#define MX6UL_PAD_LCD_DATA13__GPIO3_IO18 0x014c 0x03d8 0x0000 5 0
#define MX6UL_PAD_LCD_DATA13__SRC_BT_CFG13 0x014c 0x03d8 0x0000 6 0
#define MX6UL_PAD_LCD_DATA13__USDHC2_RESET_B 0x014c 0x03d8 0x0000 8 0
#define MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x0150 0x03dc 0x0000 0 0
#define MX6UL_PAD_LCD_DATA14__SAI3_RX_DATA 0x0150 0x03dc 0x0604 1 1
#define MX6UL_PAD_LCD_DATA14__CA7_MX6UL_TRACE14 0x0150 0x03dc 0x0000 2 0
#define MX6UL_PAD_LCD_DATA14__CSI_DATA22 0x0150 0x03dc 0x051c 3 1
#define MX6UL_PAD_LCD_DATA14__EIM_DATA06 0x0150 0x03dc 0x0000 4 0
#define MX6UL_PAD_LCD_DATA14__GPIO3_IO19 0x0150 0x03dc 0x0000 5 0
#define MX6UL_PAD_LCD_DATA14__SRC_BT_CFG14 0x0150 0x03dc 0x0000 6 0
#define MX6UL_PAD_LCD_DATA14__USDHC2_DATA4 0x0150 0x03dc 0x068c 8 0
#define MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x0154 0x03e0 0x0000 0 0
#define MX6UL_PAD_LCD_DATA15__SAI3_TX_DATA 0x0154 0x03e0 0x0000 1 0
#define MX6UL_PAD_LCD_DATA15__CA7_MX6UL_TRACE15 0x0154 0x03e0 0x0000 2 0
#define MX6UL_PAD_LCD_DATA15__CSI_DATA23 0x0154 0x03e0 0x0520 3 1
#define MX6UL_PAD_LCD_DATA15__EIM_DATA07 0x0154 0x03e0 0x0000 4 0
#define MX6UL_PAD_LCD_DATA15__GPIO3_IO20 0x0154 0x03e0 0x0000 5 0
#define MX6UL_PAD_LCD_DATA15__SRC_BT_CFG15 0x0154 0x03e0 0x0000 6 0
#define MX6UL_PAD_LCD_DATA15__USDHC2_DATA5 0x0154 0x03e0 0x0690 8 0
#define MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x0158 0x03e4 0x0000 0 0
#define MX6UL_PAD_LCD_DATA16__UART7_DCE_TX 0x0158 0x03e4 0x0000 1 0
#define MX6UL_PAD_LCD_DATA16__UART7_DTE_RX 0x0158 0x03e4 0x0654 1 2
#define MX6UL_PAD_LCD_DATA16__CA7_MX6UL_TRACE_CLK 0x0158 0x03e4 0x0000 2 0
#define MX6UL_PAD_LCD_DATA16__CSI_DATA01 0x0158 0x03e4 0x04d4 3 1
#define MX6UL_PAD_LCD_DATA16__EIM_DATA08 0x0158 0x03e4 0x0000 4 0
#define MX6UL_PAD_LCD_DATA16__GPIO3_IO21 0x0158 0x03e4 0x0000 5 0
#define MX6UL_PAD_LCD_DATA16__SRC_BT_CFG24 0x0158 0x03e4 0x0000 6 0
#define MX6UL_PAD_LCD_DATA16__USDHC2_DATA6 0x0158 0x03e4 0x0694 8 0
#define MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x015c 0x03e8 0x0000 0 0
#define MX6UL_PAD_LCD_DATA17__UART7_DCE_RX 0x015c 0x03e8 0x0654 1 3
#define MX6UL_PAD_LCD_DATA17__UART7_DTE_TX 0x015c 0x03e8 0x0000 1 0
#define MX6UL_PAD_LCD_DATA17__CA7_MX6UL_TRACE_CTL 0x015c 0x03e8 0x0000 2 0
#define MX6UL_PAD_LCD_DATA17__CSI_DATA00 0x015c 0x03e8 0x04d0 3 1
#define MX6UL_PAD_LCD_DATA17__EIM_DATA09 0x015c 0x03e8 0x0000 4 0
#define MX6UL_PAD_LCD_DATA17__GPIO3_IO22 0x015c 0x03e8 0x0000 5 0
#define MX6UL_PAD_LCD_DATA17__SRC_BT_CFG25 0x015c 0x03e8 0x0000 6 0
#define MX6UL_PAD_LCD_DATA17__USDHC2_DATA7 0x015c 0x03e8 0x0698 8 0
#define MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x0160 0x03ec 0x0000 0 0
#define MX6UL_PAD_LCD_DATA18__PWM5_OUT 0x0160 0x03ec 0x0000 1 0
#define MX6UL_PAD_LCD_DATA18__CA7_MX6UL_EVENTO 0x0160 0x03ec 0x0000 2 0
#define MX6UL_PAD_LCD_DATA18__CSI_DATA10 0x0160 0x03ec 0x04ec 3 1
#define MX6UL_PAD_LCD_DATA18__EIM_DATA10 0x0160 0x03ec 0x0000 4 0
#define MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x0160 0x03ec 0x0000 5 0
#define MX6UL_PAD_LCD_DATA18__SRC_BT_CFG26 0x0160 0x03ec 0x0000 6 0
#define MX6UL_PAD_LCD_DATA18__USDHC2_CMD 0x0160 0x03ec 0x0678 8 1
#define MX6UL_PAD_LCD_DATA19__EIM_DATA11 0x0164 0x03f0 0x0000 4 0
#define MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x0164 0x03f0 0x0000 5 0
#define MX6UL_PAD_LCD_DATA19__SRC_BT_CFG27 0x0164 0x03f0 0x0000 6 0
#define MX6UL_PAD_LCD_DATA19__USDHC2_CLK 0x0164 0x03f0 0x0670 8 1
#define MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x0164 0x03f0 0x0000 0 0
#define MX6UL_PAD_LCD_DATA19__PWM6_OUT 0x0164 0x03f0 0x0000 1 0
#define MX6UL_PAD_LCD_DATA19__WDOG1_WDOG_ANY 0x0164 0x03f0 0x0000 2 0
#define MX6UL_PAD_LCD_DATA19__CSI_DATA11 0x0164 0x03f0 0x04f0 3 1
#define MX6UL_PAD_LCD_DATA20__EIM_DATA12 0x0168 0x03f4 0x0000 4 0
#define MX6UL_PAD_LCD_DATA20__GPIO3_IO25 0x0168 0x03f4 0x0000 5 0
#define MX6UL_PAD_LCD_DATA20__SRC_BT_CFG28 0x0168 0x03f4 0x0000 6 0
#define MX6UL_PAD_LCD_DATA20__USDHC2_DATA0 0x0168 0x03f4 0x067c 8 1
#define MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x0168 0x03f4 0x0000 0 0
#define MX6UL_PAD_LCD_DATA20__UART8_DCE_TX 0x0168 0x03f4 0x0000 1 0
#define MX6UL_PAD_LCD_DATA20__UART8_DTE_RX 0x0168 0x03f4 0x065c 1 2
#define MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x0168 0x03f4 0x0534 2 0
#define MX6UL_PAD_LCD_DATA20__CSI_DATA12 0x0168 0x03f4 0x04f4 3 1
#define MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x016c 0x03f8 0x0000 0 0
#define MX6UL_PAD_LCD_DATA21__UART8_DCE_RX 0x016c 0x03f8 0x065c 1 3
#define MX6UL_PAD_LCD_DATA21__UART8_DTE_TX 0x016c 0x03f8 0x0000 1 0
#define MX6UL_PAD_LCD_DATA21__ECSPI1_SS0 0x016c 0x03f8 0x0540 2 0
#define MX6UL_PAD_LCD_DATA21__CSI_DATA13 0x016c 0x03f8 0x04f8 3 1
#define MX6UL_PAD_LCD_DATA21__EIM_DATA13 0x016c 0x03f8 0x0000 4 0
#define MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x016c 0x03f8 0x0000 5 0
#define MX6UL_PAD_LCD_DATA21__SRC_BT_CFG29 0x016c 0x03f8 0x0000 6 0
#define MX6UL_PAD_LCD_DATA21__USDHC2_DATA1 0x016c 0x03f8 0x0680 8 1
#define MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x0170 0x03fc 0x0000 0 0
#define MX6UL_PAD_LCD_DATA22__MQS_RIGHT 0x0170 0x03fc 0x0000 1 0
#define MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x0170 0x03fc 0x053c 2 0
#define MX6UL_PAD_LCD_DATA22__CSI_DATA14 0x0170 0x03fc 0x04fc 3 1
#define MX6UL_PAD_LCD_DATA22__EIM_DATA14 0x0170 0x03fc 0x0000 4 0
#define MX6UL_PAD_LCD_DATA22__GPIO3_IO27 0x0170 0x03fc 0x0000 5 0
#define MX6UL_PAD_LCD_DATA22__SRC_BT_CFG30 0x0170 0x03fc 0x0000 6 0
#define MX6UL_PAD_LCD_DATA22__USDHC2_DATA2 0x0170 0x03fc 0x0684 8 0
#define MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x0174 0x0400 0x0000 0 0
#define MX6UL_PAD_LCD_DATA23__MQS_LEFT 0x0174 0x0400 0x0000 1 0
#define MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x0174 0x0400 0x0538 2 0
#define MX6UL_PAD_LCD_DATA23__CSI_DATA15 0x0174 0x0400 0x0500 3 1
#define MX6UL_PAD_LCD_DATA23__EIM_DATA15 0x0174 0x0400 0x0000 4 0
#define MX6UL_PAD_LCD_DATA23__GPIO3_IO28 0x0174 0x0400 0x0000 5 0
#define MX6UL_PAD_LCD_DATA23__SRC_BT_CFG31 0x0174 0x0400 0x0000 6 0
#define MX6UL_PAD_LCD_DATA23__USDHC2_DATA3 0x0174 0x0400 0x0688 8 1
#define MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0178 0x0404 0x0000 0 0
#define MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x0178 0x0404 0x0670 1 2
#define MX6UL_PAD_NAND_RE_B__QSPI_B_SCLK 0x0178 0x0404 0x0000 2 0
#define MX6UL_PAD_NAND_RE_B__KPP_ROW00 0x0178 0x0404 0x05d0 3 1
#define MX6UL_PAD_NAND_RE_B__EIM_EB_B00 0x0178 0x0404 0x0000 4 0
#define MX6UL_PAD_NAND_RE_B__GPIO4_IO00 0x0178 0x0404 0x0000 5 0
#define MX6UL_PAD_NAND_RE_B__ECSPI3_SS2 0x0178 0x0404 0x0000 8 0
#define MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x017c 0x0408 0x0000 0 0
#define MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x017c 0x0408 0x0678 1 2
#define MX6UL_PAD_NAND_WE_B__QSPI_B_SS0_B 0x017c 0x0408 0x0000 2 0
#define MX6UL_PAD_NAND_WE_B__KPP_COL00 0x017c 0x0408 0x05c4 3 1
#define MX6UL_PAD_NAND_WE_B__EIM_EB_B01 0x017c 0x0408 0x0000 4 0
#define MX6UL_PAD_NAND_WE_B__GPIO4_IO01 0x017c 0x0408 0x0000 5 0
#define MX6UL_PAD_NAND_WE_B__ECSPI3_SS3 0x017c 0x0408 0x0000 8 0
#define MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0180 0x040c 0x0000 0 0
#define MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x0180 0x040c 0x067c 1 2
#define MX6UL_PAD_NAND_DATA00__QSPI_B_SS1_B 0x0180 0x040c 0x0000 2 0
#define MX6UL_PAD_NAND_DATA00__KPP_ROW01 0x0180 0x040c 0x05d4 3 1
#define MX6UL_PAD_NAND_DATA00__EIM_AD08 0x0180 0x040c 0x0000 4 0
#define MX6UL_PAD_NAND_DATA00__GPIO4_IO02 0x0180 0x040c 0x0000 5 0
#define MX6UL_PAD_NAND_DATA00__ECSPI4_RDY 0x0180 0x040c 0x0000 8 0
#define MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0184 0x0410 0x0000 0 0
#define MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x0184 0x0410 0x0680 1 2
#define MX6UL_PAD_NAND_DATA01__QSPI_B_DQS 0x0184 0x0410 0x0000 2 0
#define MX6UL_PAD_NAND_DATA01__KPP_COL01 0x0184 0x0410 0x05c8 3 1
#define MX6UL_PAD_NAND_DATA01__EIM_AD09 0x0184 0x0410 0x0000 4 0
#define MX6UL_PAD_NAND_DATA01__GPIO4_IO03 0x0184 0x0410 0x0000 5 0
#define MX6UL_PAD_NAND_DATA01__ECSPI4_SS1 0x0184 0x0410 0x0000 8 0
#define MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0188 0x0414 0x0000 0 0
#define MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x0188 0x0414 0x0684 1 1
#define MX6UL_PAD_NAND_DATA02__QSPI_B_DATA00 0x0188 0x0414 0x0000 2 0
#define MX6UL_PAD_NAND_DATA02__KPP_ROW02 0x0188 0x0414 0x05d8 3 1
#define MX6UL_PAD_NAND_DATA02__EIM_AD10 0x0188 0x0414 0x0000 4 0
#define MX6UL_PAD_NAND_DATA02__GPIO4_IO04 0x0188 0x0414 0x0000 5 0
#define MX6UL_PAD_NAND_DATA02__ECSPI4_SS2 0x0188 0x0414 0x0000 8 0
#define MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x018c 0x0418 0x0000 0 0
#define MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x018c 0x0418 0x0688 1 2
#define MX6UL_PAD_NAND_DATA03__QSPI_B_DATA01 0x018c 0x0418 0x0000 2 0
#define MX6UL_PAD_NAND_DATA03__KPP_COL02 0x018c 0x0418 0x05cc 3 1
#define MX6UL_PAD_NAND_DATA03__EIM_AD11 0x018c 0x0418 0x0000 4 0
#define MX6UL_PAD_NAND_DATA03__GPIO4_IO05 0x018c 0x0418 0x0000 5 0
#define MX6UL_PAD_NAND_DATA03__ECSPI4_SS3 0x018c 0x0418 0x0000 8 0
#define MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0190 0x041c 0x0000 0 0
#define MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x0190 0x041c 0x068c 1 1
#define MX6UL_PAD_NAND_DATA04__QSPI_B_DATA02 0x0190 0x041c 0x0000 2 0
#define MX6UL_PAD_NAND_DATA04__ECSPI4_SCLK 0x0190 0x041c 0x0564 3 1
#define MX6UL_PAD_NAND_DATA04__EIM_AD12 0x0190 0x041c 0x0000 4 0
#define MX6UL_PAD_NAND_DATA04__GPIO4_IO06 0x0190 0x041c 0x0000 5 0
#define MX6UL_PAD_NAND_DATA04__UART2_DCE_TX 0x0190 0x041c 0x0000 8 0
#define MX6UL_PAD_NAND_DATA04__UART2_DTE_RX 0x0190 0x041c 0x062c 8 2
#define MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0194 0x0420 0x0000 0 0
#define MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x0194 0x0420 0x0690 1 1
#define MX6UL_PAD_NAND_DATA05__QSPI_B_DATA03 0x0194 0x0420 0x0000 2 0
#define MX6UL_PAD_NAND_DATA05__ECSPI4_MOSI 0x0194 0x0420 0x056c 3 1
#define MX6UL_PAD_NAND_DATA05__EIM_AD13 0x0194 0x0420 0x0000 4 0
#define MX6UL_PAD_NAND_DATA05__GPIO4_IO07 0x0194 0x0420 0x0000 5 0
#define MX6UL_PAD_NAND_DATA05__UART2_DCE_RX 0x0194 0x0420 0x062c 8 3
#define MX6UL_PAD_NAND_DATA05__UART2_DTE_TX 0x0194 0x0420 0x0000 8 0
#define MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0198 0x0424 0x0000 0 0
#define MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x0198 0x0424 0x0694 1 1
#define MX6UL_PAD_NAND_DATA06__SAI2_RX_BCLK 0x0198 0x0424 0x0000 2 0
#define MX6UL_PAD_NAND_DATA06__ECSPI4_MISO 0x0198 0x0424 0x0568 3 1
#define MX6UL_PAD_NAND_DATA06__EIM_AD14 0x0198 0x0424 0x0000 4 0
#define MX6UL_PAD_NAND_DATA06__GPIO4_IO08 0x0198 0x0424 0x0000 5 0
#define MX6UL_PAD_NAND_DATA06__UART2_DCE_CTS 0x0198 0x0424 0x0000 8 0
#define MX6UL_PAD_NAND_DATA06__UART2_DTE_RTS 0x0198 0x0424 0x0628 8 4
#define MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x019c 0x0428 0x0000 0 0
#define MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x019c 0x0428 0x0698 1 1
#define MX6UL_PAD_NAND_DATA07__QSPI_A_SS1_B 0x019c 0x0428 0x0000 2 0
#define MX6UL_PAD_NAND_DATA07__ECSPI4_SS0 0x019c 0x0428 0x0570 3 1
#define MX6UL_PAD_NAND_DATA07__EIM_AD15 0x019c 0x0428 0x0000 4 0
#define MX6UL_PAD_NAND_DATA07__GPIO4_IO09 0x019c 0x0428 0x0000 5 0
#define MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS 0x019c 0x0428 0x0628 8 5
#define MX6UL_PAD_NAND_DATA07__UART2_DTE_CTS 0x019c 0x0428 0x0000 8 0
#define MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x01a0 0x042c 0x0000 0 0
#define MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x01a0 0x042c 0x0000 1 0
#define MX6UL_PAD_NAND_ALE__QSPI_A_DQS 0x01a0 0x042c 0x0000 2 0
#define MX6UL_PAD_NAND_ALE__PWM3_OUT 0x01a0 0x042c 0x0000 3 0
#define MX6UL_PAD_NAND_ALE__EIM_ADDR17 0x01a0 0x042c 0x0000 4 0
#define MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x01a0 0x042c 0x0000 5 0
#define MX6UL_PAD_NAND_ALE__ECSPI3_SS1 0x01a0 0x042c 0x0000 8 0
#define MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x01a4 0x0430 0x0000 0 0
#define MX6UL_PAD_NAND_WP_B__USDHC1_RESET_B 0x01a4 0x0430 0x0000 1 0
#define MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x01a4 0x0430 0x0000 2 0
#define MX6UL_PAD_NAND_WP_B__PWM4_OUT 0x01a4 0x0430 0x0000 3 0
#define MX6UL_PAD_NAND_WP_B__EIM_BCLK 0x01a4 0x0430 0x0000 4 0
#define MX6UL_PAD_NAND_WP_B__GPIO4_IO11 0x01a4 0x0430 0x0000 5 0
#define MX6UL_PAD_NAND_WP_B__ECSPI3_RDY 0x01a4 0x0430 0x0000 8 0
#define MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x01a8 0x0434 0x0000 0 0
#define MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x01a8 0x0434 0x0000 1 0
#define MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x01a8 0x0434 0x0000 2 0
#define MX6UL_PAD_NAND_READY_B__ECSPI3_SS0 0x01a8 0x0434 0x0560 3 1
#define MX6UL_PAD_NAND_READY_B__EIM_CS1_B 0x01a8 0x0434 0x0000 4 0
#define MX6UL_PAD_NAND_READY_B__GPIO4_IO12 0x01a8 0x0434 0x0000 5 0
#define MX6UL_PAD_NAND_READY_B__UART3_DCE_TX 0x01a8 0x0434 0x0000 8 0
#define MX6UL_PAD_NAND_READY_B__UART3_DTE_RX 0x01a8 0x0434 0x0634 8 2
#define MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x01ac 0x0438 0x0000 0 0
#define MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x01ac 0x0438 0x0000 1 0
#define MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x01ac 0x0438 0x0000 2 0
#define MX6UL_PAD_NAND_CE0_B__ECSPI3_SCLK 0x01ac 0x0438 0x0554 3 1
#define MX6UL_PAD_NAND_CE0_B__EIM_DTACK_B 0x01ac 0x0438 0x0000 4 0
#define MX6UL_PAD_NAND_CE0_B__GPIO4_IO13 0x01ac 0x0438 0x0000 5 0
#define MX6UL_PAD_NAND_CE0_B__UART3_DCE_RX 0x01ac 0x0438 0x0634 8 3
#define MX6UL_PAD_NAND_CE0_B__UART3_DTE_TX 0x01ac 0x0438 0x0000 8 0
#define MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0x01b0 0x043c 0x0000 0 0
#define MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x01b0 0x043c 0x0000 1 0
#define MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x01b0 0x043c 0x0000 2 0
#define MX6UL_PAD_NAND_CE1_B__ECSPI3_MOSI 0x01b0 0x043c 0x055c 3 1
#define MX6UL_PAD_NAND_CE1_B__EIM_ADDR18 0x01b0 0x043c 0x0000 4 0
#define MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x01b0 0x043c 0x0000 5 0
#define MX6UL_PAD_NAND_CE1_B__UART3_DCE_CTS 0x01b0 0x043c 0x0000 8 0
#define MX6UL_PAD_NAND_CE1_B__UART3_DTE_RTS 0x01b0 0x043c 0x0630 8 2
#define MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x01b4 0x0440 0x0000 0 0
#define MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x01b4 0x0440 0x0000 1 0
#define MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x01b4 0x0440 0x0000 2 0
#define MX6UL_PAD_NAND_CLE__ECSPI3_MISO 0x01b4 0x0440 0x0558 3 1
#define MX6UL_PAD_NAND_CLE__EIM_ADDR16 0x01b4 0x0440 0x0000 4 0
#define MX6UL_PAD_NAND_CLE__GPIO4_IO15 0x01b4 0x0440 0x0000 5 0
#define MX6UL_PAD_NAND_CLE__UART3_DCE_RTS 0x01b4 0x0440 0x0630 8 3
#define MX6UL_PAD_NAND_CLE__UART3_DTE_CTS 0x01b4 0x0440 0x0000 8 0
#define MX6UL_PAD_NAND_DQS__RAWNAND_DQS 0x01b8 0x0444 0x0000 0 0
#define MX6UL_PAD_NAND_DQS__CSI_FIELD 0x01b8 0x0444 0x0530 1 1
#define MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x01b8 0x0444 0x0000 2 0
#define MX6UL_PAD_NAND_DQS__PWM5_OUT 0x01b8 0x0444 0x0000 3 0
#define MX6UL_PAD_NAND_DQS__EIM_WAIT 0x01b8 0x0444 0x0000 4 0
#define MX6UL_PAD_NAND_DQS__GPIO4_IO16 0x01b8 0x0444 0x0000 5 0
#define MX6UL_PAD_NAND_DQS__SDMA_EXT_EVENT01 0x01b8 0x0444 0x0614 6 1
#define MX6UL_PAD_NAND_DQS__SPDIF_EXT_CLK 0x01b8 0x0444 0x061c 8 1
#define MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x01bc 0x0448 0x0000 0 0
#define MX6UL_PAD_SD1_CMD__GPT2_COMPARE1 0x01bc 0x0448 0x0000 1 0
#define MX6UL_PAD_SD1_CMD__SAI2_RX_SYNC 0x01bc 0x0448 0x0000 2 0
#define MX6UL_PAD_SD1_CMD__SPDIF_OUT 0x01bc 0x0448 0x0000 3 0
#define MX6UL_PAD_SD1_CMD__EIM_ADDR19 0x01bc 0x0448 0x0000 4 0
#define MX6UL_PAD_SD1_CMD__GPIO2_IO16 0x01bc 0x0448 0x0000 5 0
#define MX6UL_PAD_SD1_CMD__SDMA_EXT_EVENT00 0x01bc 0x0448 0x0610 6 2
#define MX6UL_PAD_SD1_CMD__USB_OTG1_PWR 0x01bc 0x0448 0x0000 8 0
#define MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x01c0 0x044c 0x0000 0 0
#define MX6UL_PAD_SD1_CLK__GPT2_COMPARE2 0x01c0 0x044c 0x0000 1 0
#define MX6UL_PAD_SD1_CLK__SAI2_MCLK 0x01c0 0x044c 0x05f0 2 1
#define MX6UL_PAD_SD1_CLK__SPDIF_IN 0x01c0 0x044c 0x0618 3 3
#define MX6UL_PAD_SD1_CLK__EIM_ADDR20 0x01c0 0x044c 0x0000 4 0
#define MX6UL_PAD_SD1_CLK__GPIO2_IO17 0x01c0 0x044c 0x0000 5 0
#define MX6UL_PAD_SD1_CLK__USB_OTG1_OC 0x01c0 0x044c 0x0664 8 2
#define MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x01c4 0x0450 0x0000 0 0
#define MX6UL_PAD_SD1_DATA0__GPT2_COMPARE3 0x01c4 0x0450 0x0000 1 0
#define MX6UL_PAD_SD1_DATA0__SAI2_TX_SYNC 0x01c4 0x0450 0x05fc 2 1
#define MX6UL_PAD_SD1_DATA0__FLEXCAN1_TX 0x01c4 0x0450 0x0000 3 0
#define MX6UL_PAD_SD1_DATA0__EIM_ADDR21 0x01c4 0x0450 0x0000 4 0
#define MX6UL_PAD_SD1_DATA0__GPIO2_IO18 0x01c4 0x0450 0x0000 5 0
#define MX6UL_PAD_SD1_DATA0__ANATOP_OTG1_ID 0x01c4 0x0450 0x04b8 8 2
#define MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x01c8 0x0454 0x0000 0 0
#define MX6UL_PAD_SD1_DATA1__GPT2_CLK 0x01c8 0x0454 0x05a0 1 1
#define MX6UL_PAD_SD1_DATA1__SAI2_TX_BCLK 0x01c8 0x0454 0x05f8 2 1
#define MX6UL_PAD_SD1_DATA1__FLEXCAN1_RX 0x01c8 0x0454 0x0584 3 3
#define MX6UL_PAD_SD1_DATA1__EIM_ADDR22 0x01c8 0x0454 0x0000 4 0
#define MX6UL_PAD_SD1_DATA1__GPIO2_IO19 0x01c8 0x0454 0x0000 5 0
#define MX6UL_PAD_SD1_DATA1__USB_OTG2_PWR 0x01c8 0x0454 0x0000 8 0
#define MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x01cc 0x0458 0x0000 0 0
#define MX6UL_PAD_SD1_DATA2__GPT2_CAPTURE1 0x01cc 0x0458 0x0598 1 1
#define MX6UL_PAD_SD1_DATA2__SAI2_RX_DATA 0x01cc 0x0458 0x05f4 2 1
#define MX6UL_PAD_SD1_DATA2__FLEXCAN2_TX 0x01cc 0x0458 0x0000 3 0
#define MX6UL_PAD_SD1_DATA2__EIM_ADDR23 0x01cc 0x0458 0x0000 4 0
#define MX6UL_PAD_SD1_DATA2__GPIO2_IO20 0x01cc 0x0458 0x0000 5 0
#define MX6UL_PAD_SD1_DATA2__CCM_CLKO1 0x01cc 0x0458 0x0000 6 0
#define MX6UL_PAD_SD1_DATA2__USB_OTG2_OC 0x01cc 0x0458 0x0660 8 2
#define MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x01d0 0x045c 0x0000 0 0
#define MX6UL_PAD_SD1_DATA3__GPT2_CAPTURE2 0x01d0 0x045c 0x059c 1 1
#define MX6UL_PAD_SD1_DATA3__SAI2_TX_DATA 0x01d0 0x045c 0x0000 2 0
#define MX6UL_PAD_SD1_DATA3__FLEXCAN2_RX 0x01d0 0x045c 0x0588 3 3
#define MX6UL_PAD_SD1_DATA3__EIM_ADDR24 0x01d0 0x045c 0x0000 4 0
#define MX6UL_PAD_SD1_DATA3__GPIO2_IO21 0x01d0 0x045c 0x0000 5 0
#define MX6UL_PAD_SD1_DATA3__CCM_CLKO2 0x01d0 0x045c 0x0000 6 0
#define MX6UL_PAD_SD1_DATA3__ANATOP_OTG2_ID 0x01d0 0x045c 0x04bc 8 2
#define MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x01d4 0x0460 0x0000 0 0
#define MX6UL_PAD_CSI_MCLK__USDHC2_CD_B 0x01d4 0x0460 0x0674 1 0
#define MX6UL_PAD_CSI_MCLK__RAWNAND_CE2_B 0x01d4 0x0460 0x0000 2 0
#define MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x01d4 0x0460 0x05a8 3 0
#define MX6UL_PAD_CSI_MCLK__EIM_CS0_B 0x01d4 0x0460 0x0000 4 0
#define MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x01d4 0x0460 0x0000 5 0
#define MX6UL_PAD_CSI_MCLK__SNVS_HP_VIO_5_CTL 0x01d4 0x0460 0x0000 6 0
#define MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x01d4 0x0460 0x0000 8 0
#define MX6UL_PAD_CSI_MCLK__UART6_DTE_RX 0x01d4 0x0460 0x064c 8 0
#define MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x01d8 0x0464 0x0528 0 1
#define MX6UL_PAD_CSI_PIXCLK__USDHC2_WP 0x01d8 0x0464 0x069c 1 2
#define MX6UL_PAD_CSI_PIXCLK__RAWNAND_CE3_B 0x01d8 0x0464 0x0000 2 0
#define MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x01d8 0x0464 0x05a4 3 2
#define MX6UL_PAD_CSI_PIXCLK__EIM_OE 0x01d8 0x0464 0x0000 4 0
#define MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0x01d8 0x0464 0x0000 5 0
#define MX6UL_PAD_CSI_PIXCLK__SNVS_HP_VIO_5 0x01d8 0x0464 0x0000 6 0
#define MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x01d8 0x0464 0x064c 8 3
#define MX6UL_PAD_CSI_PIXCLK__UART6_DTE_TX 0x01d8 0x0464 0x0000 8 0
#define MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x01dc 0x0468 0x052c 0 0
#define MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x01dc 0x0468 0x0670 1 0
#define MX6UL_PAD_CSI_VSYNC__SIM1_PORT1_CLK 0x01dc 0x0468 0x0000 2 0
#define MX6UL_PAD_CSI_VSYNC__I2C2_SDA 0x01dc 0x0468 0x05b0 3 0
#define MX6UL_PAD_CSI_VSYNC__EIM_RW 0x01dc 0x0468 0x0000 4 0
#define MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x01dc 0x0468 0x0000 5 0
#define MX6UL_PAD_CSI_VSYNC__PWM7_OUT 0x01dc 0x0468 0x0000 6 0
#define MX6UL_PAD_CSI_VSYNC__UART6_DCE_RTS 0x01dc 0x0468 0x0648 8 0
#define MX6UL_PAD_CSI_VSYNC__UART6_DTE_CTS 0x01dc 0x0468 0x0000 8 0
#define MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x01e0 0x046c 0x0524 0 0
#define MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x01e0 0x046c 0x0678 1 0
#define MX6UL_PAD_CSI_HSYNC__SIM1_PORT1_PD 0x01e0 0x046c 0x0000 2 0
#define MX6UL_PAD_CSI_HSYNC__I2C2_SCL 0x01e0 0x046c 0x05ac 3 0
#define MX6UL_PAD_CSI_HSYNC__EIM_LBA_B 0x01e0 0x046c 0x0000 4 0
#define MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x01e0 0x046c 0x0000 5 0
#define MX6UL_PAD_CSI_HSYNC__PWM8_OUT 0x01e0 0x046c 0x0000 6 0
#define MX6UL_PAD_CSI_HSYNC__UART6_DCE_CTS 0x01e0 0x046c 0x0000 8 0
#define MX6UL_PAD_CSI_HSYNC__UART6_DTE_RTS 0x01e0 0x046c 0x0648 8 1
#define MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x01e4 0x0470 0x04c4 0 0
#define MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x01e4 0x0470 0x067c 1 0
#define MX6UL_PAD_CSI_DATA00__SIM1_PORT1_RST_B 0x01e4 0x0470 0x0000 2 0
#define MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x01e4 0x0470 0x0544 3 0
#define MX6UL_PAD_CSI_DATA00__EIM_AD00 0x01e4 0x0470 0x0000 4 0
#define MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x01e4 0x0470 0x0000 5 0
#define MX6UL_PAD_CSI_DATA00__SRC_INT_BOOT 0x01e4 0x0470 0x0000 6 0
#define MX6UL_PAD_CSI_DATA00__UART5_DCE_TX 0x01e4 0x0470 0x0000 8 0
#define MX6UL_PAD_CSI_DATA00__UART5_DTE_RX 0x01e4 0x0470 0x0644 8 0
#define MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x01e8 0x0474 0x04c8 0 0
#define MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x01e8 0x0474 0x0680 1 0
#define MX6UL_PAD_CSI_DATA01__SIM1_PORT1_SVEN 0x01e8 0x0474 0x0000 2 0
#define MX6UL_PAD_CSI_DATA01__ECSPI2_SS0 0x01e8 0x0474 0x0550 3 0
#define MX6UL_PAD_CSI_DATA01__EIM_AD01 0x01e8 0x0474 0x0000 4 0
#define MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x01e8 0x0474 0x0000 5 0
#define MX6UL_PAD_CSI_DATA01__SAI1_MCLK 0x01e8 0x0474 0x05e0 6 0
#define MX6UL_PAD_CSI_DATA01__UART5_DCE_RX 0x01e8 0x0474 0x0644 8 1
#define MX6UL_PAD_CSI_DATA01__UART5_DTE_TX 0x01e8 0x0474 0x0000 8 0
#define MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x01ec 0x0478 0x04d8 0 1
#define MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x01ec 0x0478 0x0684 1 2
#define MX6UL_PAD_CSI_DATA02__SIM1_PORT1_TRXD 0x01ec 0x0478 0x0000 2 0
#define MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x01ec 0x0478 0x054c 3 1
#define MX6UL_PAD_CSI_DATA02__EIM_AD02 0x01ec 0x0478 0x0000 4 0
#define MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x01ec 0x0478 0x0000 5 0
#define MX6UL_PAD_CSI_DATA02__SAI1_RX_SYNC 0x01ec 0x0478 0x0000 6 0
#define MX6UL_PAD_CSI_DATA02__UART5_DCE_RTS 0x01ec 0x0478 0x0640 8 5
#define MX6UL_PAD_CSI_DATA02__UART5_DTE_CTS 0x01ec 0x0478 0x0000 8 0
#define MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x01f0 0x047c 0x04cc 0 0
#define MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x01f0 0x047c 0x0688 1 0
#define MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD 0x01f0 0x047c 0x0000 2 0
#define MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x01f0 0x047c 0x0548 3 0
#define MX6UL_PAD_CSI_DATA03__EIM_AD03 0x01f0 0x047c 0x0000 4 0
#define MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x01f0 0x047c 0x0000 5 0
#define MX6UL_PAD_CSI_DATA03__SAI1_RX_BCLK 0x01f0 0x047c 0x0000 6 0
#define MX6UL_PAD_CSI_DATA03__UART5_DCE_CTS 0x01f0 0x047c 0x0000 8 0
#define MX6UL_PAD_CSI_DATA03__UART5_DTE_RTS 0x01f0 0x047c 0x0640 8 0
#define MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x01f4 0x0480 0x04dc 0 1
#define MX6UL_PAD_CSI_DATA04__USDHC2_DATA4 0x01f4 0x0480 0x068c 1 2
#define MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK 0x01f4 0x0480 0x0000 2 0
#define MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x01f4 0x0480 0x0534 3 1
#define MX6UL_PAD_CSI_DATA04__EIM_AD04 0x01f4 0x0480 0x0000 4 0
#define MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x01f4 0x0480 0x0000 5 0
#define MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC 0x01f4 0x0480 0x05ec 6 1
#define MX6UL_PAD_CSI_DATA04__USDHC1_WP 0x01f4 0x0480 0x066c 8 2
#define MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x01f8 0x0484 0x04e0 0 1
#define MX6UL_PAD_CSI_DATA05__USDHC2_DATA5 0x01f8 0x0484 0x0690 1 2
#define MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0x01f8 0x0484 0x0000 2 0
#define MX6UL_PAD_CSI_DATA05__ECSPI1_SS0 0x01f8 0x0484 0x0540 3 1
#define MX6UL_PAD_CSI_DATA05__EIM_AD05 0x01f8 0x0484 0x0000 4 0
#define MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x01f8 0x0484 0x0000 5 0
#define MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK 0x01f8 0x0484 0x05e8 6 1
#define MX6UL_PAD_CSI_DATA05__USDHC1_CD_B 0x01f8 0x0484 0x0668 8 2
#define MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x01fc 0x0488 0x04e4 0 1
#define MX6UL_PAD_CSI_DATA06__USDHC2_DATA6 0x01fc 0x0488 0x0694 1 2
#define MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN 0x01fc 0x0488 0x0000 2 0
#define MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x01fc 0x0488 0x053c 3 1
#define MX6UL_PAD_CSI_DATA06__EIM_AD06 0x01fc 0x0488 0x0000 4 0
#define MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x01fc 0x0488 0x0000 5 0
#define MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x01fc 0x0488 0x05e4 6 1
#define MX6UL_PAD_CSI_DATA06__USDHC1_RESET_B 0x01fc 0x0488 0x0000 8 0
#define MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x0200 0x048c 0x04e8 0 1
#define MX6UL_PAD_CSI_DATA07__USDHC2_DATA7 0x0200 0x048c 0x0698 1 2
#define MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD 0x0200 0x048c 0x0000 2 0
#define MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x0200 0x048c 0x0538 3 1
#define MX6UL_PAD_CSI_DATA07__EIM_AD07 0x0200 0x048c 0x0000 4 0
#define MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x0200 0x048c 0x0000 5 0
#define MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA 0x0200 0x048c 0x0000 6 0
#define MX6UL_PAD_CSI_DATA07__USDHC1_VSELECT 0x0200 0x048c 0x0000 8 0
#endif /* __DTS_IMX6UL_PINFUNC_H */

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@@ -1,26 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
* Copyright (C) 2017 NXP
*/
#ifndef __DTS_IMX6ULL_PINFUNC_SNVS_H
#define __DTS_IMX6ULL_PINFUNC_SNVS_H
/*
* The pin function ID is a tuple of
* <mux_reg conf_reg input_reg mux_mode input_val>
*/
#define MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x0000 0x0044 0x0000 0x5 0x0
#define MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x0004 0x0048 0x0000 0x5 0x0
#define MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0008 0x004C 0x0000 0x5 0x0
#define MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x000C 0x0050 0x0000 0x5 0x0
#define MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0010 0x0054 0x0000 0x5 0x0
#define MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0014 0x0058 0x0000 0x5 0x0
#define MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0018 0x005C 0x0000 0x5 0x0
#define MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x001C 0x0060 0x0000 0x5 0x0
#define MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0020 0x0064 0x0000 0x5 0x0
#define MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0024 0x0068 0x0000 0x5 0x0
#define MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x0028 0x006C 0x0000 0x5 0x0
#define MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x002C 0x0070 0x0000 0x5 0x0
#endif /* __DTS_IMX6ULL_PINFUNC_SNVS_H */

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@@ -1,87 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
*/
#ifndef __DTS_IMX6ULL_PINFUNC_H
#define __DTS_IMX6ULL_PINFUNC_H
#include "imx6ul-pinfunc.h"
/*
* The pin function ID is a tuple of
* <mux_reg conf_reg input_reg mux_mode input_val>
*/
/* signals common for i.MX6UL and i.MX6ULL */
#undef MX6UL_PAD_UART5_TX_DATA__UART5_DTE_RX
#define MX6UL_PAD_UART5_TX_DATA__UART5_DTE_RX 0x00BC 0x0348 0x0644 0x0 0x6
#undef MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX
#define MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x00C0 0x034C 0x0644 0x0 0x7
#undef MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS
#define MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS 0x00CC 0x0358 0x0640 0x1 0x5
#undef MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS
#define MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS 0x00D0 0x035C 0x0640 0x1 0x6
#undef MX6UL_PAD_CSI_DATA02__UART5_DCE_RTS
#define MX6UL_PAD_CSI_DATA02__UART5_DCE_RTS 0x01EC 0x0478 0x0640 0x8 0x7
/* signals for i.MX6ULL only */
#define MX6ULL_PAD_UART1_TX_DATA__UART5_DCE_TX 0x0084 0x0310 0x0000 0x9 0x0
#define MX6ULL_PAD_UART1_TX_DATA__UART5_DTE_RX 0x0084 0x0310 0x0644 0x9 0x4
#define MX6ULL_PAD_UART1_RX_DATA__UART5_DCE_RX 0x0088 0x0314 0x0644 0x9 0x5
#define MX6ULL_PAD_UART1_RX_DATA__UART5_DTE_TX 0x0088 0x0314 0x0000 0x9 0x0
#define MX6ULL_PAD_UART1_CTS_B__UART5_DCE_CTS 0x008C 0x0318 0x0000 0x9 0x0
#define MX6ULL_PAD_UART1_CTS_B__UART5_DTE_RTS 0x008C 0x0318 0x0640 0x9 0x3
#define MX6ULL_PAD_UART1_RTS_B__UART5_DCE_RTS 0x0090 0x031C 0x0640 0x9 0x4
#define MX6ULL_PAD_UART1_RTS_B__UART5_DTE_CTS 0x0090 0x031C 0x0000 0x9 0x0
#define MX6ULL_PAD_UART4_RX_DATA__EPDC_PWRCTRL01 0x00B8 0x0344 0x0000 0x9 0x0
#define MX6ULL_PAD_UART5_TX_DATA__EPDC_PWRCTRL02 0x00BC 0x0348 0x0000 0x9 0x0
#define MX6ULL_PAD_UART5_RX_DATA__EPDC_PWRCTRL03 0x00C0 0x034C 0x0000 0x9 0x0
#define MX6ULL_PAD_ENET1_RX_DATA0__EPDC_SDCE04 0x00C4 0x0350 0x0000 0x9 0x0
#define MX6ULL_PAD_ENET1_RX_DATA1__EPDC_SDCE05 0x00C8 0x0354 0x0000 0x9 0x0
#define MX6ULL_PAD_ENET1_RX_EN__EPDC_SDCE06 0x00CC 0x0358 0x0000 0x9 0x0
#define MX6ULL_PAD_ENET1_TX_DATA0__EPDC_SDCE07 0x00D0 0x035C 0x0000 0x9 0x0
#define MX6ULL_PAD_ENET1_TX_DATA1__EPDC_SDCE08 0x00D4 0x0360 0x0000 0x9 0x0
#define MX6ULL_PAD_ENET1_TX_EN__EPDC_SDCE09 0x00D8 0x0364 0x0000 0x9 0x0
#define MX6ULL_PAD_ENET1_TX_CLK__EPDC_SDOED 0x00DC 0x0368 0x0000 0x9 0x0
#define MX6ULL_PAD_ENET1_RX_ER__EPDC_SDOEZ 0x00E0 0x036C 0x0000 0x9 0x0
#define MX6ULL_PAD_ENET2_RX_DATA0__EPDC_SDDO08 0x00E4 0x0370 0x0000 0x9 0x0
#define MX6ULL_PAD_ENET2_RX_DATA1__EPDC_SDDO09 0x00E8 0x0374 0x0000 0x9 0x0
#define MX6ULL_PAD_ENET2_RX_EN__EPDC_SDDO10 0x00EC 0x0378 0x0000 0x9 0x0
#define MX6ULL_PAD_ENET2_TX_DATA0__EPDC_SDDO11 0x00F0 0x037C 0x0000 0x9 0x0
#define MX6ULL_PAD_ENET2_TX_DATA1__EPDC_SDDO12 0x00F4 0x0380 0x0000 0x9 0x0
#define MX6ULL_PAD_ENET2_TX_EN__EPDC_SDDO13 0x00F8 0x0384 0x0000 0x9 0x0
#define MX6ULL_PAD_ENET2_TX_CLK__EPDC_SDDO14 0x00FC 0x0388 0x0000 0x9 0x0
#define MX6ULL_PAD_ENET2_RX_ER__EPDC_SDDO15 0x0100 0x038C 0x0000 0x9 0x0
#define MX6ULL_PAD_LCD_CLK__EPDC_SDCLK 0x0104 0x0390 0x0000 0x9 0x0
#define MX6ULL_PAD_LCD_ENABLE__EPDC_SDLE 0x0108 0x0394 0x0000 0x9 0x0
#define MX6ULL_PAD_LCD_HSYNC__EPDC_SDOE 0x010C 0x0398 0x0000 0x9 0x0
#define MX6ULL_PAD_LCD_VSYNC__EPDC_SDCE0 0x0110 0x039C 0x0000 0x9 0x0
#define MX6ULL_PAD_LCD_RESET__EPDC_GDOE 0x0114 0x03A0 0x0000 0x9 0x0
#define MX6ULL_PAD_LCD_DATA00__EPDC_SDDO00 0x0118 0x03A4 0x0000 0x9 0x0
#define MX6ULL_PAD_LCD_DATA01__EPDC_SDDO01 0x011C 0x03A8 0x0000 0x9 0x0
#define MX6ULL_PAD_LCD_DATA02__EPDC_SDDO02 0x0120 0x03AC 0x0000 0x9 0x0
#define MX6ULL_PAD_LCD_DATA03__EPDC_SDDO03 0x0124 0x03B0 0x0000 0x9 0x0
#define MX6ULL_PAD_LCD_DATA04__EPDC_SDDO04 0x0128 0x03B4 0x0000 0x9 0x0
#define MX6ULL_PAD_LCD_DATA05__EPDC_SDDO05 0x012C 0x03B8 0x0000 0x9 0x0
#define MX6ULL_PAD_LCD_DATA06__EPDC_SDDO06 0x0130 0x03BC 0x0000 0x9 0x0
#define MX6ULL_PAD_LCD_DATA07__EPDC_SDDO07 0x0134 0x03C0 0x0000 0x9 0x0
#define MX6ULL_PAD_LCD_DATA14__EPDC_SDSHR 0x0150 0x03DC 0x0000 0x9 0x0
#define MX6ULL_PAD_LCD_DATA15__EPDC_GDRL 0x0154 0x03E0 0x0000 0x9 0x0
#define MX6ULL_PAD_LCD_DATA16__EPDC_GDCLK 0x0158 0x03E4 0x0000 0x9 0x0
#define MX6ULL_PAD_LCD_DATA17__EPDC_GDSP 0x015C 0x03E8 0x0000 0x9 0x0
#define MX6ULL_PAD_LCD_DATA21__EPDC_SDCE1 0x016C 0x03F8 0x0000 0x9 0x0
#define MX6ULL_PAD_LCD_DATA22__EPDC_SDCE02 0x0170 0x03FC 0x0000 0x9 0x0
#define MX6ULL_PAD_LCD_DATA23__EPDC_SDCE03 0x0174 0x0400 0x0000 0x9 0x0
#define MX6ULL_PAD_CSI_MCLK__ESAI_TX3_RX2 0x01D4 0x0460 0x0000 0x9 0x0
#define MX6ULL_PAD_CSI_PIXCLK__ESAI_TX2_RX3 0x01D8 0x0464 0x0000 0x9 0x0
#define MX6ULL_PAD_CSI_VSYNC__ESAI_TX4_RX1 0x01DC 0x0468 0x0000 0x9 0x0
#define MX6ULL_PAD_CSI_HSYNC__ESAI_TX1 0x01E0 0x046C 0x0000 0x9 0x0
#define MX6ULL_PAD_CSI_DATA00__ESAI_TX_HF_CLK 0x01E4 0x0470 0x0000 0x9 0x0
#define MX6ULL_PAD_CSI_DATA01__ESAI_RX_HF_CLK 0x01E8 0x0474 0x0000 0x9 0x0
#define MX6ULL_PAD_CSI_DATA02__ESAI_RX_FS 0x01EC 0x0478 0x0000 0x9 0x0
#define MX6ULL_PAD_CSI_DATA03__ESAI_RX_CLK 0x01F0 0x047C 0x0000 0x9 0x0
#define MX6ULL_PAD_CSI_DATA04__ESAI_TX_FS 0x01F4 0x0480 0x0000 0x9 0x0
#define MX6ULL_PAD_CSI_DATA05__ESAI_TX_CLK 0x01F8 0x0484 0x0000 0x9 0x0
#define MX6ULL_PAD_CSI_DATA06__ESAI_TX5_RX0 0x01FC 0x0488 0x0000 0x9 0x0
#define MX6ULL_PAD_CSI_DATA07__ESAI_TX0 0x0200 0x048C 0x0000 0x9 0x0
#endif /* __DTS_IMX6ULL_PINFUNC_H */

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@@ -669,7 +669,7 @@
pinctrl_can_int: canintgrp {
fsl,pins = <
MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0X14 /* SODIMM 73 */
MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x14 /* SODIMM 73 */
>;
};

File diff suppressed because it is too large Load Diff

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@@ -1,478 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright 2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
*/
#ifndef __DTS_IMX7ULP_PINFUNC_H
#define __DTS_IMX7ULP_PINFUNC_H
/*
* The pin function ID is a tuple of
* <mux_conf_reg input_reg mux_mode input_val>
*/
#define IMX7ULP_PAD_PTC0__PTC0 0x0000 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTC0__TRACE_D15 0x0000 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTC0__LPUART4_CTS_B 0x0000 0x0244 0x4 0x1
#define IMX7ULP_PAD_PTC0__LPI2C4_SCL 0x0000 0x0278 0x5 0x1
#define IMX7ULP_PAD_PTC0__TPM4_CLKIN 0x0000 0x0298 0x6 0x1
#define IMX7ULP_PAD_PTC0__FB_AD0 0x0000 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTC1__PTC1 0x0004 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTC1__TRACE_D14 0x0004 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTC1__LPUART4_RTS_B 0x0004 0x0000 0x4 0x0
#define IMX7ULP_PAD_PTC1__LPI2C4_SDA 0x0004 0x027c 0x5 0x1
#define IMX7ULP_PAD_PTC1__TPM4_CH0 0x0004 0x0280 0x6 0x1
#define IMX7ULP_PAD_PTC1__FB_AD1 0x0004 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTC2__PTC2 0x0008 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTC2__TRACE_D13 0x0008 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTC2__LPUART4_TX 0x0008 0x024c 0x4 0x1
#define IMX7ULP_PAD_PTC2__LPI2C4_HREQ 0x0008 0x0274 0x5 0x1
#define IMX7ULP_PAD_PTC2__TPM4_CH1 0x0008 0x0284 0x6 0x1
#define IMX7ULP_PAD_PTC2__FB_AD2 0x0008 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTC3__PTC3 0x000c 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTC3__TRACE_D12 0x000c 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTC3__LPUART4_RX 0x000c 0x0248 0x4 0x1
#define IMX7ULP_PAD_PTC3__TPM4_CH2 0x000c 0x0288 0x6 0x1
#define IMX7ULP_PAD_PTC3__FB_AD3 0x000c 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTC4__PTC4 0x0010 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTC4__TRACE_D11 0x0010 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTC4__FXIO1_D0 0x0010 0x0204 0x2 0x1
#define IMX7ULP_PAD_PTC4__LPSPI2_PCS1 0x0010 0x02a0 0x3 0x1
#define IMX7ULP_PAD_PTC4__LPUART5_CTS_B 0x0010 0x0250 0x4 0x1
#define IMX7ULP_PAD_PTC4__LPI2C5_SCL 0x0010 0x02bc 0x5 0x1
#define IMX7ULP_PAD_PTC4__TPM4_CH3 0x0010 0x028c 0x6 0x1
#define IMX7ULP_PAD_PTC4__FB_AD4 0x0010 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTC5__PTC5 0x0014 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTC5__TRACE_D10 0x0014 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTC5__FXIO1_D1 0x0014 0x0208 0x2 0x1
#define IMX7ULP_PAD_PTC5__LPSPI2_PCS2 0x0014 0x02a4 0x3 0x1
#define IMX7ULP_PAD_PTC5__LPUART5_RTS_B 0x0014 0x0000 0x4 0x0
#define IMX7ULP_PAD_PTC5__LPI2C5_SDA 0x0014 0x02c0 0x5 0x1
#define IMX7ULP_PAD_PTC5__TPM4_CH4 0x0014 0x0290 0x6 0x1
#define IMX7ULP_PAD_PTC5__FB_AD5 0x0014 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTC6__PTC6 0x0018 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTC6__TRACE_D9 0x0018 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTC6__FXIO1_D2 0x0018 0x020c 0x2 0x1
#define IMX7ULP_PAD_PTC6__LPSPI2_PCS3 0x0018 0x02a8 0x3 0x1
#define IMX7ULP_PAD_PTC6__LPUART5_TX 0x0018 0x0258 0x4 0x1
#define IMX7ULP_PAD_PTC6__LPI2C5_HREQ 0x0018 0x02b8 0x5 0x1
#define IMX7ULP_PAD_PTC6__TPM4_CH5 0x0018 0x0294 0x6 0x1
#define IMX7ULP_PAD_PTC6__FB_AD6 0x0018 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTC7__PTC7 0x001c 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTC7__TRACE_D8 0x001c 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTC7__FXIO1_D3 0x001c 0x0210 0x2 0x1
#define IMX7ULP_PAD_PTC7__LPUART5_RX 0x001c 0x0254 0x4 0x1
#define IMX7ULP_PAD_PTC7__TPM5_CH1 0x001c 0x02c8 0x6 0x1
#define IMX7ULP_PAD_PTC7__FB_AD7 0x001c 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTC8__PTC8 0x0020 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTC8__TRACE_D7 0x0020 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTC8__FXIO1_D4 0x0020 0x0214 0x2 0x1
#define IMX7ULP_PAD_PTC8__LPSPI2_SIN 0x0020 0x02b0 0x3 0x1
#define IMX7ULP_PAD_PTC8__LPUART6_CTS_B 0x0020 0x025c 0x4 0x1
#define IMX7ULP_PAD_PTC8__LPI2C6_SCL 0x0020 0x02fc 0x5 0x1
#define IMX7ULP_PAD_PTC8__TPM5_CLKIN 0x0020 0x02cc 0x6 0x1
#define IMX7ULP_PAD_PTC8__FB_AD8 0x0020 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTC9__PTC9 0x0024 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTC9__TRACE_D6 0x0024 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTC9__FXIO1_D5 0x0024 0x0218 0x2 0x1
#define IMX7ULP_PAD_PTC9__LPSPI2_SOUT 0x0024 0x02b4 0x3 0x1
#define IMX7ULP_PAD_PTC9__LPUART6_RTS_B 0x0024 0x0000 0x4 0x0
#define IMX7ULP_PAD_PTC9__LPI2C6_SDA 0x0024 0x0300 0x5 0x1
#define IMX7ULP_PAD_PTC9__TPM5_CH0 0x0024 0x02c4 0x6 0x1
#define IMX7ULP_PAD_PTC9__FB_AD9 0x0024 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTC10__PTC10 0x0028 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTC10__TRACE_D5 0x0028 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTC10__FXIO1_D6 0x0028 0x021c 0x2 0x1
#define IMX7ULP_PAD_PTC10__LPSPI2_SCK 0x0028 0x02ac 0x3 0x1
#define IMX7ULP_PAD_PTC10__LPUART6_TX 0x0028 0x0264 0x4 0x1
#define IMX7ULP_PAD_PTC10__LPI2C6_HREQ 0x0028 0x02f8 0x5 0x1
#define IMX7ULP_PAD_PTC10__TPM7_CH3 0x0028 0x02e8 0x6 0x1
#define IMX7ULP_PAD_PTC10__FB_AD10 0x0028 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTC11__PTC11 0x002c 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTC11__TRACE_D4 0x002c 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTC11__FXIO1_D7 0x002c 0x0220 0x2 0x1
#define IMX7ULP_PAD_PTC11__LPSPI2_PCS0 0x002c 0x029c 0x3 0x1
#define IMX7ULP_PAD_PTC11__LPUART6_RX 0x002c 0x0260 0x4 0x1
#define IMX7ULP_PAD_PTC11__TPM7_CH4 0x002c 0x02ec 0x6 0x1
#define IMX7ULP_PAD_PTC11__FB_AD11 0x002c 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTC12__PTC12 0x0030 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTC12__TRACE_D3 0x0030 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTC12__FXIO1_D8 0x0030 0x0224 0x2 0x1
#define IMX7ULP_PAD_PTC12__LPSPI3_PCS1 0x0030 0x0314 0x3 0x1
#define IMX7ULP_PAD_PTC12__LPUART7_CTS_B 0x0030 0x0268 0x4 0x1
#define IMX7ULP_PAD_PTC12__LPI2C7_SCL 0x0030 0x0308 0x5 0x1
#define IMX7ULP_PAD_PTC12__TPM7_CH5 0x0030 0x02f0 0x6 0x1
#define IMX7ULP_PAD_PTC12__FB_AD12 0x0030 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTC13__PTC13 0x0034 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTC13__TRACE_D2 0x0034 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTC13__FXIO1_D9 0x0034 0x0228 0x2 0x1
#define IMX7ULP_PAD_PTC13__LPSPI3_PCS2 0x0034 0x0318 0x3 0x1
#define IMX7ULP_PAD_PTC13__LPUART7_RTS_B 0x0034 0x0000 0x4 0x0
#define IMX7ULP_PAD_PTC13__LPI2C7_SDA 0x0034 0x030c 0x5 0x1
#define IMX7ULP_PAD_PTC13__TPM7_CLKIN 0x0034 0x02f4 0x6 0x1
#define IMX7ULP_PAD_PTC13__FB_AD13 0x0034 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTC13__USB0_ID 0x0034 0x0338 0xb 0x1
#define IMX7ULP_PAD_PTC14__PTC14 0x0038 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTC14__TRACE_D1 0x0038 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTC14__FXIO1_D10 0x0038 0x022c 0x2 0x1
#define IMX7ULP_PAD_PTC14__LPSPI3_PCS3 0x0038 0x031c 0x3 0x1
#define IMX7ULP_PAD_PTC14__LPUART7_TX 0x0038 0x0270 0x4 0x1
#define IMX7ULP_PAD_PTC14__LPI2C7_HREQ 0x0038 0x0304 0x5 0x1
#define IMX7ULP_PAD_PTC14__TPM7_CH0 0x0038 0x02dc 0x6 0x1
#define IMX7ULP_PAD_PTC14__FB_AD14 0x0038 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTC15__PTC15 0x003c 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTC15__TRACE_D0 0x003c 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTC15__FXIO1_D11 0x003c 0x0230 0x2 0x1
#define IMX7ULP_PAD_PTC15__LPUART7_RX 0x003c 0x026c 0x4 0x1
#define IMX7ULP_PAD_PTC15__TPM7_CH1 0x003c 0x02e0 0x6 0x1
#define IMX7ULP_PAD_PTC15__FB_AD15 0x003c 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTC16__PTC16 0x0040 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTC16__TRACE_CLKOUT 0x0040 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTC16__FXIO1_D12 0x0040 0x0234 0x2 0x1
#define IMX7ULP_PAD_PTC16__LPSPI3_SIN 0x0040 0x0324 0x3 0x1
#define IMX7ULP_PAD_PTC16__TPM7_CH2 0x0040 0x02e4 0x6 0x1
#define IMX7ULP_PAD_PTC16__FB_ALE_FB_CS1_B_FB_TS_B 0x0040 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTC16__USB1_OC2 0x0040 0x0334 0xb 0x1
#define IMX7ULP_PAD_PTC17__PTC17 0x0044 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTC17__FXIO1_D13 0x0044 0x0238 0x2 0x1
#define IMX7ULP_PAD_PTC17__LPSPI3_SOUT 0x0044 0x0328 0x3 0x1
#define IMX7ULP_PAD_PTC17__TPM6_CLKIN 0x0044 0x02d8 0x6 0x1
#define IMX7ULP_PAD_PTC17__FB_CS0_B 0x0044 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTC18__PTC18 0x0048 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTC18__FXIO1_D14 0x0048 0x023c 0x2 0x1
#define IMX7ULP_PAD_PTC18__LPSPI3_SCK 0x0048 0x0320 0x3 0x1
#define IMX7ULP_PAD_PTC18__TPM6_CH0 0x0048 0x02d0 0x6 0x1
#define IMX7ULP_PAD_PTC18__FB_OE_B 0x0048 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTC18__USB0_ID 0x0048 0x0338 0xb 0x2
#define IMX7ULP_PAD_PTC18__VIU_DE 0x0048 0x033c 0xc 0x1
#define IMX7ULP_PAD_PTC19__PTC19 0x004c 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTC19__FXIO1_D15 0x004c 0x0240 0x2 0x1
#define IMX7ULP_PAD_PTC19__LPSPI3_PCS0 0x004c 0x0310 0x3 0x1
#define IMX7ULP_PAD_PTC19__TPM6_CH1 0x004c 0x02d4 0x6 0x1
#define IMX7ULP_PAD_PTC19__FB_A16 0x004c 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTC19__USB0_ID 0x004c 0x0338 0xa 0x3
#define IMX7ULP_PAD_PTC19__USB1_PWR2 0x004c 0x0000 0xb 0x0
#define IMX7ULP_PAD_PTC19__VIU_DE 0x004c 0x033c 0xc 0x3
#define IMX7ULP_PAD_PTD0__PTD0 0x0080 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTD0__SDHC0_RESET_B 0x0080 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTD1__PTD1 0x0084 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTD1__SDHC0_CMD 0x0084 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTD2__PTD2 0x0088 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTD2__SDHC0_CLK 0x0088 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTD3__PTD3 0x008c 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTD3__SDHC0_D7 0x008c 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTD4__PTD4 0x0090 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTD4__SDHC0_D6 0x0090 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTD5__PTD5 0x0094 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTD5__SDHC0_D5 0x0094 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTD6__PTD6 0x0098 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTD6__SDHC0_D4 0x0098 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTD7__PTD7 0x009c 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTD7__SDHC0_D3 0x009c 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTD8__PTD8 0x00a0 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTD8__TPM4_CLKIN 0x00a0 0x0298 0x6 0x2
#define IMX7ULP_PAD_PTD8__SDHC0_D2 0x00a0 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTD9__PTD9 0x00a4 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTD9__TPM4_CH0 0x00a4 0x0280 0x6 0x2
#define IMX7ULP_PAD_PTD9__SDHC0_D1 0x00a4 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTD10__PTD10 0x00a8 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTD10__TPM4_CH1 0x00a8 0x0284 0x6 0x2
#define IMX7ULP_PAD_PTD10__SDHC0_D0 0x00a8 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTD11__PTD11 0x00ac 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTD11__TPM4_CH2 0x00ac 0x0288 0x6 0x2
#define IMX7ULP_PAD_PTD11__SDHC0_DQS 0x00ac 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTE0__PTE0 0x0100 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTE0__FXIO1_D31 0x0100 0x0000 0x2 0x0
#define IMX7ULP_PAD_PTE0__LPSPI2_PCS1 0x0100 0x02a0 0x3 0x2
#define IMX7ULP_PAD_PTE0__LPUART4_CTS_B 0x0100 0x0244 0x4 0x2
#define IMX7ULP_PAD_PTE0__LPI2C4_SCL 0x0100 0x0278 0x5 0x2
#define IMX7ULP_PAD_PTE0__SDHC1_D1 0x0100 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTE0__FB_A25 0x0100 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTE1__PTE1 0x0104 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTE1__FXIO1_D30 0x0104 0x0000 0x2 0x0
#define IMX7ULP_PAD_PTE1__LPSPI2_PCS2 0x0104 0x02a4 0x3 0x2
#define IMX7ULP_PAD_PTE1__LPUART4_RTS_B 0x0104 0x0000 0x4 0x0
#define IMX7ULP_PAD_PTE1__LPI2C4_SDA 0x0104 0x027c 0x5 0x2
#define IMX7ULP_PAD_PTE1__SDHC1_D0 0x0104 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTE1__FB_A26 0x0104 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTE2__PTE2 0x0108 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTE2__FXIO1_D29 0x0108 0x0000 0x2 0x0
#define IMX7ULP_PAD_PTE2__LPSPI2_PCS3 0x0108 0x02a8 0x3 0x2
#define IMX7ULP_PAD_PTE2__LPUART4_TX 0x0108 0x024c 0x4 0x2
#define IMX7ULP_PAD_PTE2__LPI2C4_HREQ 0x0108 0x0274 0x5 0x2
#define IMX7ULP_PAD_PTE2__SDHC1_CLK 0x0108 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTE3__PTE3 0x010c 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTE3__FXIO1_D28 0x010c 0x0000 0x2 0x0
#define IMX7ULP_PAD_PTE3__LPUART4_RX 0x010c 0x0248 0x4 0x2
#define IMX7ULP_PAD_PTE3__TPM5_CH1 0x010c 0x02c8 0x6 0x2
#define IMX7ULP_PAD_PTE3__SDHC1_CMD 0x010c 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTE4__PTE4 0x0110 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTE4__FXIO1_D27 0x0110 0x0000 0x2 0x0
#define IMX7ULP_PAD_PTE4__LPSPI2_SIN 0x0110 0x02b0 0x3 0x2
#define IMX7ULP_PAD_PTE4__LPUART5_CTS_B 0x0110 0x0250 0x4 0x2
#define IMX7ULP_PAD_PTE4__LPI2C5_SCL 0x0110 0x02bc 0x5 0x2
#define IMX7ULP_PAD_PTE4__TPM5_CLKIN 0x0110 0x02cc 0x6 0x2
#define IMX7ULP_PAD_PTE4__SDHC1_D3 0x0110 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTE5__PTE5 0x0114 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTE5__FXIO1_D26 0x0114 0x0000 0x2 0x0
#define IMX7ULP_PAD_PTE5__LPSPI2_SOUT 0x0114 0x02b4 0x3 0x2
#define IMX7ULP_PAD_PTE5__LPUART5_RTS_B 0x0114 0x0000 0x4 0x0
#define IMX7ULP_PAD_PTE5__LPI2C5_SDA 0x0114 0x02c0 0x5 0x2
#define IMX7ULP_PAD_PTE5__TPM5_CH0 0x0114 0x02c4 0x6 0x2
#define IMX7ULP_PAD_PTE5__SDHC1_D2 0x0114 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTE5__VIU_DE 0x0114 0x033c 0xc 0x2
#define IMX7ULP_PAD_PTE6__PTE6 0x0118 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTE6__FXIO1_D25 0x0118 0x0000 0x2 0x0
#define IMX7ULP_PAD_PTE6__LPSPI2_SCK 0x0118 0x02ac 0x3 0x2
#define IMX7ULP_PAD_PTE6__LPUART5_TX 0x0118 0x0258 0x4 0x2
#define IMX7ULP_PAD_PTE6__LPI2C5_HREQ 0x0118 0x02b8 0x5 0x2
#define IMX7ULP_PAD_PTE6__TPM7_CH3 0x0118 0x02e8 0x6 0x2
#define IMX7ULP_PAD_PTE6__SDHC1_D4 0x0118 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTE6__FB_A17 0x0118 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTE6__USB0_OC 0x0118 0x0330 0xb 0x1
#define IMX7ULP_PAD_PTE7__PTE7 0x011c 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTE7__TRACE_D7 0x011c 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTE7__USB0_PWR 0x011c 0x0000 0xb 0x0
#define IMX7ULP_PAD_PTE7__VIU_FID 0x011c 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTE7__FXIO1_D24 0x011c 0x0000 0x2 0x0
#define IMX7ULP_PAD_PTE7__LPSPI2_PCS0 0x011c 0x029c 0x3 0x2
#define IMX7ULP_PAD_PTE7__LPUART5_RX 0x011c 0x0254 0x4 0x2
#define IMX7ULP_PAD_PTE7__TPM7_CH4 0x011c 0x02ec 0x6 0x2
#define IMX7ULP_PAD_PTE7__SDHC1_D5 0x011c 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTE7__FB_A18 0x011c 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTE8__PTE8 0x0120 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTE8__TRACE_D6 0x0120 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTE8__VIU_D16 0x0120 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTE8__FXIO1_D23 0x0120 0x0000 0x2 0x0
#define IMX7ULP_PAD_PTE8__LPSPI3_PCS1 0x0120 0x0314 0x3 0x2
#define IMX7ULP_PAD_PTE8__LPUART6_CTS_B 0x0120 0x025c 0x4 0x2
#define IMX7ULP_PAD_PTE8__LPI2C6_SCL 0x0120 0x02fc 0x5 0x2
#define IMX7ULP_PAD_PTE8__TPM7_CH5 0x0120 0x02f0 0x6 0x2
#define IMX7ULP_PAD_PTE8__SDHC1_WP 0x0120 0x0200 0x7 0x1
#define IMX7ULP_PAD_PTE8__SDHC1_D6 0x0120 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTE8__FB_CS3_B_FB_BE7_0_BLS31_24_B 0x0120 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTE9__PTE9 0x0124 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTE9__TRACE_D5 0x0124 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTE9__VIU_D17 0x0124 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTE9__FXIO1_D22 0x0124 0x0000 0x2 0x0
#define IMX7ULP_PAD_PTE9__LPSPI3_PCS2 0x0124 0x0318 0x3 0x2
#define IMX7ULP_PAD_PTE9__LPUART6_RTS_B 0x0124 0x0000 0x4 0x0
#define IMX7ULP_PAD_PTE9__LPI2C6_SDA 0x0124 0x0300 0x5 0x2
#define IMX7ULP_PAD_PTE9__TPM7_CLKIN 0x0124 0x02f4 0x6 0x2
#define IMX7ULP_PAD_PTE9__SDHC1_CD 0x0124 0x032c 0x7 0x1
#define IMX7ULP_PAD_PTE9__SDHC1_D7 0x0124 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTE9__FB_TBST_B_FB_CS2_B_FB_BE15_8_BLS23_16_B 0x0124 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTE10__PTE10 0x0128 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTE10__TRACE_D4 0x0128 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTE10__VIU_D18 0x0128 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTE10__FXIO1_D21 0x0128 0x0000 0x2 0x0
#define IMX7ULP_PAD_PTE10__LPSPI3_PCS3 0x0128 0x031c 0x3 0x2
#define IMX7ULP_PAD_PTE10__LPUART6_TX 0x0128 0x0264 0x4 0x2
#define IMX7ULP_PAD_PTE10__LPI2C6_HREQ 0x0128 0x02f8 0x5 0x2
#define IMX7ULP_PAD_PTE10__TPM7_CH0 0x0128 0x02dc 0x6 0x2
#define IMX7ULP_PAD_PTE10__SDHC1_VS 0x0128 0x0000 0x7 0x0
#define IMX7ULP_PAD_PTE10__SDHC1_DQS 0x0128 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTE10__FB_A19 0x0128 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTE11__PTE11 0x012c 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTE11__TRACE_D3 0x012c 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTE11__VIU_D19 0x012c 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTE11__FXIO1_D20 0x012c 0x0000 0x2 0x0
#define IMX7ULP_PAD_PTE11__LPUART6_RX 0x012c 0x0260 0x4 0x2
#define IMX7ULP_PAD_PTE11__TPM7_CH1 0x012c 0x02e0 0x6 0x2
#define IMX7ULP_PAD_PTE11__SDHC1_RESET_B 0x012c 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTE11__FB_A20 0x012c 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTE12__PTE12 0x0130 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTE12__TRACE_D2 0x0130 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTE12__USB1_OC2 0x0130 0x0334 0xb 0x2
#define IMX7ULP_PAD_PTE12__VIU_D20 0x0130 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTE12__FXIO1_D19 0x0130 0x0000 0x2 0x0
#define IMX7ULP_PAD_PTE12__LPSPI3_SIN 0x0130 0x0324 0x3 0x2
#define IMX7ULP_PAD_PTE12__LPUART7_CTS_B 0x0130 0x0268 0x4 0x2
#define IMX7ULP_PAD_PTE12__LPI2C7_SCL 0x0130 0x0308 0x5 0x2
#define IMX7ULP_PAD_PTE12__TPM7_CH2 0x0130 0x02e4 0x6 0x2
#define IMX7ULP_PAD_PTE12__SDHC1_WP 0x0130 0x0200 0x8 0x2
#define IMX7ULP_PAD_PTE12__FB_A21 0x0130 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTE13__PTE13 0x0134 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTE13__TRACE_D1 0x0134 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTE13__USB1_PWR2 0x0134 0x0000 0xb 0x0
#define IMX7ULP_PAD_PTE13__VIU_D21 0x0134 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTE13__FXIO1_D18 0x0134 0x0000 0x2 0x0
#define IMX7ULP_PAD_PTE13__LPSPI3_SOUT 0x0134 0x0328 0x3 0x2
#define IMX7ULP_PAD_PTE13__LPUART7_RTS_B 0x0134 0x0000 0x4 0x0
#define IMX7ULP_PAD_PTE13__LPI2C7_SDA 0x0134 0x030c 0x5 0x2
#define IMX7ULP_PAD_PTE13__TPM6_CLKIN 0x0134 0x02d8 0x6 0x2
#define IMX7ULP_PAD_PTE13__SDHC1_CD 0x0134 0x032c 0x8 0x2
#define IMX7ULP_PAD_PTE13__FB_A22 0x0134 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTE14__PTE14 0x0138 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTE14__TRACE_D0 0x0138 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTE14__USB0_OC 0x0138 0x0330 0xb 0x2
#define IMX7ULP_PAD_PTE14__VIU_D22 0x0138 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTE14__FXIO1_D17 0x0138 0x0000 0x2 0x0
#define IMX7ULP_PAD_PTE14__LPSPI3_SCK 0x0138 0x0320 0x3 0x2
#define IMX7ULP_PAD_PTE14__LPUART7_TX 0x0138 0x0270 0x4 0x2
#define IMX7ULP_PAD_PTE14__LPI2C7_HREQ 0x0138 0x0304 0x5 0x2
#define IMX7ULP_PAD_PTE14__TPM6_CH0 0x0138 0x02d0 0x6 0x2
#define IMX7ULP_PAD_PTE14__SDHC1_VS 0x0138 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTE14__FB_A23 0x0138 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTE15__PTE15 0x013c 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTE15__TRACE_CLKOUT 0x013c 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTE15__USB0_PWR 0x013c 0x0000 0xb 0x0
#define IMX7ULP_PAD_PTE15__VIU_D23 0x013c 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTE15__FXIO1_D16 0x013c 0x0000 0x2 0x0
#define IMX7ULP_PAD_PTE15__LPSPI3_PCS0 0x013c 0x0310 0x3 0x2
#define IMX7ULP_PAD_PTE15__LPUART7_RX 0x013c 0x026c 0x4 0x2
#define IMX7ULP_PAD_PTE15__TPM6_CH1 0x013c 0x02d4 0x6 0x2
#define IMX7ULP_PAD_PTE15__FB_A24 0x013c 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTF0__PTF0 0x0180 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTF0__VIU_DE 0x0180 0x033c 0xc 0x0
#define IMX7ULP_PAD_PTF0__LPUART4_CTS_B 0x0180 0x0244 0x4 0x3
#define IMX7ULP_PAD_PTF0__LPI2C4_SCL 0x0180 0x0278 0x5 0x3
#define IMX7ULP_PAD_PTF0__TPM4_CLKIN 0x0180 0x0298 0x6 0x3
#define IMX7ULP_PAD_PTF0__FB_RW_B 0x0180 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTF1__PTF1 0x0184 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTF1__VIU_HSYNC 0x0184 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTF1__LPUART4_RTS_B 0x0184 0x0000 0x4 0x0
#define IMX7ULP_PAD_PTF1__LPI2C4_SDA 0x0184 0x027c 0x5 0x3
#define IMX7ULP_PAD_PTF1__TPM4_CH0 0x0184 0x0280 0x6 0x3
#define IMX7ULP_PAD_PTF1__CLKOUT 0x0184 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTF2__PTF2 0x0188 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTF2__VIU_VSYNC 0x0188 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTF2__LPUART4_TX 0x0188 0x024c 0x4 0x3
#define IMX7ULP_PAD_PTF2__LPI2C4_HREQ 0x0188 0x0274 0x5 0x3
#define IMX7ULP_PAD_PTF2__TPM4_CH1 0x0188 0x0284 0x6 0x3
#define IMX7ULP_PAD_PTF2__FB_TSIZ1_FB_CS5_B_FB_BE23_16_BLS15_8_B 0x0188 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTF3__PTF3 0x018c 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTF3__VIU_PCLK 0x018c 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTF3__LPUART4_RX 0x018c 0x0248 0x4 0x3
#define IMX7ULP_PAD_PTF3__TPM4_CH2 0x018c 0x0288 0x6 0x3
#define IMX7ULP_PAD_PTF3__FB_AD16 0x018c 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTF4__PTF4 0x0190 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTF4__VIU_D0 0x0190 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTF4__FXIO1_D0 0x0190 0x0204 0x2 0x2
#define IMX7ULP_PAD_PTF4__LPSPI2_PCS1 0x0190 0x02a0 0x3 0x3
#define IMX7ULP_PAD_PTF4__LPUART5_CTS_B 0x0190 0x0250 0x4 0x3
#define IMX7ULP_PAD_PTF4__LPI2C5_SCL 0x0190 0x02bc 0x5 0x3
#define IMX7ULP_PAD_PTF4__TPM4_CH3 0x0190 0x028c 0x6 0x2
#define IMX7ULP_PAD_PTF4__FB_AD17 0x0190 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTF5__PTF5 0x0194 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTF5__VIU_D1 0x0194 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTF5__FXIO1_D1 0x0194 0x0208 0x2 0x2
#define IMX7ULP_PAD_PTF5__LPSPI2_PCS2 0x0194 0x02a4 0x3 0x3
#define IMX7ULP_PAD_PTF5__LPUART5_RTS_B 0x0194 0x0000 0x4 0x0
#define IMX7ULP_PAD_PTF5__LPI2C5_SDA 0x0194 0x02c0 0x5 0x3
#define IMX7ULP_PAD_PTF5__TPM4_CH4 0x0194 0x0290 0x6 0x2
#define IMX7ULP_PAD_PTF5__FB_AD18 0x0194 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTF6__PTF6 0x0198 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTF6__VIU_D2 0x0198 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTF6__FXIO1_D2 0x0198 0x020c 0x2 0x2
#define IMX7ULP_PAD_PTF6__LPSPI2_PCS3 0x0198 0x02a8 0x3 0x3
#define IMX7ULP_PAD_PTF6__LPUART5_TX 0x0198 0x0258 0x4 0x3
#define IMX7ULP_PAD_PTF6__LPI2C5_HREQ 0x0198 0x02b8 0x5 0x3
#define IMX7ULP_PAD_PTF6__TPM4_CH5 0x0198 0x0294 0x6 0x2
#define IMX7ULP_PAD_PTF6__FB_AD19 0x0198 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTF7__PTF7 0x019c 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTF7__VIU_D3 0x019c 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTF7__FXIO1_D3 0x019c 0x0210 0x2 0x2
#define IMX7ULP_PAD_PTF7__LPUART5_RX 0x019c 0x0254 0x4 0x3
#define IMX7ULP_PAD_PTF7__TPM5_CH1 0x019c 0x02c8 0x6 0x3
#define IMX7ULP_PAD_PTF7__FB_AD20 0x019c 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTF8__PTF8 0x01a0 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTF8__USB1_ULPI_CLK 0x01a0 0x0000 0xb 0x0
#define IMX7ULP_PAD_PTF8__VIU_D4 0x01a0 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTF8__FXIO1_D4 0x01a0 0x0214 0x2 0x2
#define IMX7ULP_PAD_PTF8__LPSPI2_SIN 0x01a0 0x02b0 0x3 0x3
#define IMX7ULP_PAD_PTF8__LPUART6_CTS_B 0x01a0 0x025c 0x4 0x3
#define IMX7ULP_PAD_PTF8__LPI2C6_SCL 0x01a0 0x02fc 0x5 0x3
#define IMX7ULP_PAD_PTF8__TPM5_CLKIN 0x01a0 0x02cc 0x6 0x3
#define IMX7ULP_PAD_PTF8__FB_AD21 0x01a0 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTF9__PTF9 0x01a4 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTF9__USB1_ULPI_NXT 0x01a4 0x0000 0xb 0x0
#define IMX7ULP_PAD_PTF9__VIU_D5 0x01a4 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTF9__FXIO1_D5 0x01a4 0x0218 0x2 0x2
#define IMX7ULP_PAD_PTF9__LPSPI2_SOUT 0x01a4 0x02b4 0x3 0x3
#define IMX7ULP_PAD_PTF9__LPUART6_RTS_B 0x01a4 0x0000 0x4 0x0
#define IMX7ULP_PAD_PTF9__LPI2C6_SDA 0x01a4 0x0300 0x5 0x3
#define IMX7ULP_PAD_PTF9__TPM5_CH0 0x01a4 0x02c4 0x6 0x3
#define IMX7ULP_PAD_PTF9__FB_AD22 0x01a4 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTF10__PTF10 0x01a8 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTF10__USB1_ULPI_STP 0x01a8 0x0000 0xb 0x0
#define IMX7ULP_PAD_PTF10__VIU_D6 0x01a8 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTF10__FXIO1_D6 0x01a8 0x021c 0x2 0x2
#define IMX7ULP_PAD_PTF10__LPSPI2_SCK 0x01a8 0x02ac 0x3 0x3
#define IMX7ULP_PAD_PTF10__LPUART6_TX 0x01a8 0x0264 0x4 0x3
#define IMX7ULP_PAD_PTF10__LPI2C6_HREQ 0x01a8 0x02f8 0x5 0x3
#define IMX7ULP_PAD_PTF10__TPM7_CH3 0x01a8 0x02e8 0x6 0x3
#define IMX7ULP_PAD_PTF10__FB_AD23 0x01a8 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTF11__PTF11 0x01ac 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTF11__USB1_ULPI_DIR 0x01ac 0x0000 0xb 0x0
#define IMX7ULP_PAD_PTF11__VIU_D7 0x01ac 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTF11__FXIO1_D7 0x01ac 0x0220 0x2 0x2
#define IMX7ULP_PAD_PTF11__LPSPI2_PCS0 0x01ac 0x029c 0x3 0x3
#define IMX7ULP_PAD_PTF11__LPUART6_RX 0x01ac 0x0260 0x4 0x3
#define IMX7ULP_PAD_PTF11__TPM7_CH4 0x01ac 0x02ec 0x6 0x3
#define IMX7ULP_PAD_PTF11__FB_CS4_B_FB_TSIZ0_FB_BE31_24_BLS7_0_B 0x01ac 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTF12__PTF12 0x01b0 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTF12__USB1_ULPI_DATA0 0x01b0 0x0000 0xb 0x0
#define IMX7ULP_PAD_PTF12__VIU_D8 0x01b0 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTF12__FXIO1_D8 0x01b0 0x0224 0x2 0x2
#define IMX7ULP_PAD_PTF12__LPSPI3_PCS1 0x01b0 0x0314 0x3 0x3
#define IMX7ULP_PAD_PTF12__LPUART7_CTS_B 0x01b0 0x0268 0x4 0x3
#define IMX7ULP_PAD_PTF12__LPI2C7_SCL 0x01b0 0x0308 0x5 0x3
#define IMX7ULP_PAD_PTF12__TPM7_CH5 0x01b0 0x02f0 0x6 0x3
#define IMX7ULP_PAD_PTF12__FB_AD24 0x01b0 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTF13__PTF13 0x01b4 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTF13__USB1_ULPI_DATA1 0x01b4 0x0000 0xb 0x0
#define IMX7ULP_PAD_PTF13__VIU_D9 0x01b4 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTF13__FXIO1_D9 0x01b4 0x0228 0x2 0x2
#define IMX7ULP_PAD_PTF13__LPSPI3_PCS2 0x01b4 0x0318 0x3 0x3
#define IMX7ULP_PAD_PTF13__LPUART7_RTS_B 0x01b4 0x0000 0x4 0x0
#define IMX7ULP_PAD_PTF13__LPI2C7_SDA 0x01b4 0x030c 0x5 0x3
#define IMX7ULP_PAD_PTF13__TPM7_CLKIN 0x01b4 0x02f4 0x6 0x3
#define IMX7ULP_PAD_PTF13__FB_AD25 0x01b4 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTF14__PTF14 0x01b8 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTF14__USB1_ULPI_DATA2 0x01b8 0x0000 0xb 0x0
#define IMX7ULP_PAD_PTF14__VIU_D10 0x01b8 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTF14__FXIO1_D10 0x01b8 0x022c 0x2 0x2
#define IMX7ULP_PAD_PTF14__LPSPI3_PCS3 0x01b8 0x031c 0x3 0x3
#define IMX7ULP_PAD_PTF14__LPUART7_TX 0x01b8 0x0270 0x4 0x3
#define IMX7ULP_PAD_PTF14__LPI2C7_HREQ 0x01b8 0x0304 0x5 0x3
#define IMX7ULP_PAD_PTF14__TPM7_CH0 0x01b8 0x02dc 0x6 0x3
#define IMX7ULP_PAD_PTF14__FB_AD26 0x01b8 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTF15__PTF15 0x01bc 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTF15__USB1_ULPI_DATA3 0x01bc 0x0000 0xb 0x0
#define IMX7ULP_PAD_PTF15__VIU_D11 0x01bc 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTF15__FXIO1_D11 0x01bc 0x0230 0x2 0x2
#define IMX7ULP_PAD_PTF15__LPUART7_RX 0x01bc 0x026c 0x4 0x3
#define IMX7ULP_PAD_PTF15__TPM7_CH1 0x01bc 0x02e0 0x6 0x3
#define IMX7ULP_PAD_PTF15__FB_AD27 0x01bc 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTF16__PTF16 0x01c0 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTF16__USB1_ULPI_DATA4 0x01c0 0x0000 0xb 0x0
#define IMX7ULP_PAD_PTF16__VIU_D12 0x01c0 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTF16__FXIO1_D12 0x01c0 0x0234 0x2 0x2
#define IMX7ULP_PAD_PTF16__LPSPI3_SIN 0x01c0 0x0324 0x3 0x3
#define IMX7ULP_PAD_PTF16__TPM7_CH2 0x01c0 0x02e4 0x6 0x3
#define IMX7ULP_PAD_PTF16__FB_AD28 0x01c0 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTF17__PTF17 0x01c4 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTF17__USB1_ULPI_DATA5 0x01c4 0x0000 0xb 0x0
#define IMX7ULP_PAD_PTF17__VIU_D13 0x01c4 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTF17__FXIO1_D13 0x01c4 0x0238 0x2 0x2
#define IMX7ULP_PAD_PTF17__LPSPI3_SOUT 0x01c4 0x0328 0x3 0x3
#define IMX7ULP_PAD_PTF17__TPM6_CLKIN 0x01c4 0x02d8 0x6 0x3
#define IMX7ULP_PAD_PTF17__FB_AD29 0x01c4 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTF18__PTF18 0x01c8 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTF18__USB1_ULPI_DATA6 0x01c8 0x0000 0xb 0x0
#define IMX7ULP_PAD_PTF18__VIU_D14 0x01c8 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTF18__FXIO1_D14 0x01c8 0x023c 0x2 0x2
#define IMX7ULP_PAD_PTF18__LPSPI3_SCK 0x01c8 0x0320 0x3 0x3
#define IMX7ULP_PAD_PTF18__TPM6_CH0 0x01c8 0x02d0 0x6 0x3
#define IMX7ULP_PAD_PTF18__FB_AD30 0x01c8 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTF19__PTF19 0x01cc 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTF19__USB1_ULPI_DATA7 0x01cc 0x0000 0xb 0x0
#define IMX7ULP_PAD_PTF19__VIU_D15 0x01cc 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTF19__FXIO1_D15 0x01cc 0x0240 0x2 0x2
#define IMX7ULP_PAD_PTF19__LPSPI3_PCS0 0x01cc 0x0310 0x3 0x3
#define IMX7ULP_PAD_PTF19__TPM6_CH1 0x01cc 0x02d4 0x6 0x3
#define IMX7ULP_PAD_PTF19__FB_AD31 0x01cc 0x0000 0x9 0x0
#endif /* __DTS_IMX7ULP_PINFUNC_H */

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@@ -1,646 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2017-2018 NXP
*/
#ifndef __DTS_IMX8MM_PINFUNC_H
#define __DTS_IMX8MM_PINFUNC_H
/*
* The pin function ID is a tuple of
* <mux_reg conf_reg input_reg mux_mode input_val>
*/
#define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
#define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0x0
#define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
#define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
#define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0x0
#define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
#define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
#define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0x0
#define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0x0
#define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0x0
#define MX8MM_IOMUXC_GPIO1_IO02_GPIO1_IO2 0x030 0x298 0x000 0x0 0x0
#define MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x030 0x298 0x000 0x1 0x0
#define MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x030 0x298 0x000 0x5 0x0
#define MX8MM_IOMUXC_GPIO1_IO02_SJC_DE_B 0x030 0x298 0x000 0x7 0x0
#define MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x034 0x29C 0x000 0x0 0x0
#define MX8MM_IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x034 0x29C 0x000 0x1 0x0
#define MX8MM_IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x034 0x29C 0x000 0x5 0x0
#define MX8MM_IOMUXC_GPIO1_IO03_ANAMIX_XTAL_OK 0x034 0x29C 0x000 0x6 0x0
#define MX8MM_IOMUXC_GPIO1_IO03_SJC_DONE 0x034 0x29C 0x000 0x7 0x0
#define MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x038 0x2A0 0x000 0x0 0x0
#define MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x038 0x2A0 0x000 0x1 0x0
#define MX8MM_IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x038 0x2A0 0x000 0x5 0x0
#define MX8MM_IOMUXC_GPIO1_IO04_ANAMIX_XTAL_OK_LV 0x038 0x2A0 0x000 0x6 0x0
#define MX8MM_IOMUXC_GPIO1_IO04_USDHC1_TEST_TRIG 0x038 0x2A0 0x000 0x7 0x0
#define MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x03C 0x2A4 0x000 0x0 0x0
#define MX8MM_IOMUXC_GPIO1_IO05_M4_NMI 0x03C 0x2A4 0x000 0x1 0x0
#define MX8MM_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_PMIC_READY 0x03C 0x2A4 0x000 0x5 0x0
#define MX8MM_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_INT_BOOT 0x03C 0x2A4 0x000 0x6 0x0
#define MX8MM_IOMUXC_GPIO1_IO05_USDHC2_TEST_TRIG 0x03C 0x2A4 0x000 0x7 0x0
#define MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x040 0x2A8 0x000 0x0 0x0
#define MX8MM_IOMUXC_GPIO1_IO06_ENET1_MDC 0x040 0x2A8 0x000 0x1 0x0
#define MX8MM_IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x040 0x2A8 0x000 0x5 0x0
#define MX8MM_IOMUXC_GPIO1_IO06_CCMSRCGPCMIX_EXT_CLK3 0x040 0x2A8 0x000 0x6 0x0
#define MX8MM_IOMUXC_GPIO1_IO06_ECSPI1_TEST_TRIG 0x040 0x2A8 0x000 0x7 0x0
#define MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x044 0x2AC 0x000 0x0 0x0
#define MX8MM_IOMUXC_GPIO1_IO07_ENET1_MDIO 0x044 0x2AC 0x000 0x1 0x0
#define MX8MM_IOMUXC_GPIO1_IO07_USDHC1_WP 0x044 0x2AC 0x000 0x5 0x0
#define MX8MM_IOMUXC_GPIO1_IO07_CCMSRCGPCMIX_EXT_CLK4 0x044 0x2AC 0x000 0x6 0x0
#define MX8MM_IOMUXC_GPIO1_IO07_ECSPI2_TEST_TRIG 0x044 0x2AC 0x000 0x7 0x0
#define MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x048 0x2B0 0x000 0x0 0x0
#define MX8MM_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x048 0x2B0 0x000 0x1 0x0
#define MX8MM_IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x048 0x2B0 0x000 0x5 0x0
#define MX8MM_IOMUXC_GPIO1_IO08_CCMSRCGPCMIX_WAIT 0x048 0x2B0 0x000 0x6 0x0
#define MX8MM_IOMUXC_GPIO1_IO08_QSPI_TEST_TRIG 0x048 0x2B0 0x000 0x7 0x0
#define MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x04C 0x2B4 0x000 0x0 0x0
#define MX8MM_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x04C 0x2B4 0x000 0x1 0x0
#define MX8MM_IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x04C 0x2B4 0x000 0x5 0x0
#define MX8MM_IOMUXC_GPIO1_IO09_CCMSRCGPCMIX_STOP 0x04C 0x2B4 0x000 0x6 0x0
#define MX8MM_IOMUXC_GPIO1_IO09_RAWNAND_TEST_TRIG 0x04C 0x2B4 0x000 0x7 0x0
#define MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x050 0x2B8 0x000 0x0 0x0
#define MX8MM_IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x050 0x2B8 0x000 0x1 0x0
#define MX8MM_IOMUXC_GPIO1_IO10_OCOTP_CTRL_WRAPPER_FUSE_LATCHED 0x050 0x2B8 0x000 0x7 0x0
#define MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x054 0x2BC 0x000 0x0 0x0
#define MX8MM_IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x054 0x2BC 0x000 0x1 0x0
#define MX8MM_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_PMIC_READY 0x054 0x2BC 0x4BC 0x5 0x1
#define MX8MM_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_OUT0 0x054 0x2BC 0x000 0x6 0x0
#define MX8MM_IOMUXC_GPIO1_IO11_CAAM_WRAPPER_RNG_OSC_OBS 0x054 0x2BC 0x000 0x7 0x0
#define MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x058 0x2C0 0x000 0x0 0x0
#define MX8MM_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x058 0x2C0 0x000 0x1 0x0
#define MX8MM_IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x058 0x2C0 0x000 0x5 0x0
#define MX8MM_IOMUXC_GPIO1_IO12_CCMSRCGPCMIX_OUT1 0x058 0x2C0 0x000 0x6 0x0
#define MX8MM_IOMUXC_GPIO1_IO12_CSU_CSU_ALARM_AUT0 0x058 0x2C0 0x000 0x7 0x0
#define MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x05C 0x2C4 0x000 0x0 0x0
#define MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x05C 0x2C4 0x000 0x1 0x0
#define MX8MM_IOMUXC_GPIO1_IO13_PWM2_OUT 0x05C 0x2C4 0x000 0x5 0x0
#define MX8MM_IOMUXC_GPIO1_IO13_CCMSRCGPCMIX_OUT2 0x05C 0x2C4 0x000 0x6 0x0
#define MX8MM_IOMUXC_GPIO1_IO13_CSU_CSU_ALARM_AUT1 0x05C 0x2C4 0x000 0x7 0x0
#define MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x060 0x2C8 0x000 0x0 0x0
#define MX8MM_IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x060 0x2C8 0x000 0x1 0x0
#define MX8MM_IOMUXC_GPIO1_IO14_PWM3_OUT 0x060 0x2C8 0x000 0x5 0x0
#define MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x060 0x2C8 0x000 0x6 0x0
#define MX8MM_IOMUXC_GPIO1_IO14_CSU_CSU_ALARM_AUT2 0x060 0x2C8 0x000 0x7 0x0
#define MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x064 0x2CC 0x000 0x0 0x0
#define MX8MM_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x064 0x2CC 0x000 0x1 0x0
#define MX8MM_IOMUXC_GPIO1_IO15_PWM4_OUT 0x064 0x2CC 0x000 0x5 0x0
#define MX8MM_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x064 0x2CC 0x000 0x6 0x0
#define MX8MM_IOMUXC_GPIO1_IO15_CSU_CSU_INT_DEB 0x064 0x2CC 0x000 0x7 0x0
#define MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x068 0x2D0 0x000 0x0 0x0
#define MX8MM_IOMUXC_ENET_MDC_GPIO1_IO16 0x068 0x2D0 0x000 0x5 0x0
#define MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x06C 0x2D4 0x4C0 0x0 0x1
#define MX8MM_IOMUXC_ENET_MDIO_GPIO1_IO17 0x06C 0x2D4 0x000 0x5 0x0
#define MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x070 0x2D8 0x000 0x0 0x0
#define MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18 0x070 0x2D8 0x000 0x5 0x0
#define MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x074 0x2DC 0x000 0x0 0x0
#define MX8MM_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x074 0x2DC 0x000 0x1 0x0
#define MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19 0x074 0x2DC 0x000 0x5 0x0
#define MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x078 0x2E0 0x000 0x0 0x0
#define MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20 0x078 0x2E0 0x000 0x5 0x0
#define MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x07C 0x2E4 0x000 0x0 0x0
#define MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21 0x07C 0x2E4 0x000 0x5 0x0
#define MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x080 0x2E8 0x000 0x0 0x0
#define MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x080 0x2E8 0x000 0x5 0x0
#define MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x084 0x2EC 0x000 0x0 0x0
#define MX8MM_IOMUXC_ENET_TXC_ENET1_TX_ER 0x084 0x2EC 0x000 0x1 0x0
#define MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23 0x084 0x2EC 0x000 0x5 0x0
#define MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x088 0x2F0 0x000 0x0 0x0
#define MX8MM_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x088 0x2F0 0x000 0x5 0x0
#define MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x08C 0x2F4 0x000 0x0 0x0
#define MX8MM_IOMUXC_ENET_RXC_ENET1_RX_ER 0x08C 0x2F4 0x000 0x1 0x0
#define MX8MM_IOMUXC_ENET_RXC_GPIO1_IO25 0x08C 0x2F4 0x000 0x5 0x0
#define MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x090 0x2F8 0x000 0x0 0x0
#define MX8MM_IOMUXC_ENET_RD0_GPIO1_IO26 0x090 0x2F8 0x000 0x5 0x0
#define MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x094 0x2FC 0x000 0x0 0x0
#define MX8MM_IOMUXC_ENET_RD1_GPIO1_IO27 0x094 0x2FC 0x000 0x5 0x0
#define MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x098 0x300 0x000 0x0 0x0
#define MX8MM_IOMUXC_ENET_RD2_GPIO1_IO28 0x098 0x300 0x000 0x5 0x0
#define MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x09C 0x304 0x000 0x0 0x0
#define MX8MM_IOMUXC_ENET_RD3_GPIO1_IO29 0x09C 0x304 0x000 0x5 0x0
#define MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x0A0 0x308 0x000 0x0 0x0
#define MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0 0x0A0 0x308 0x000 0x5 0x0
#define MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x0A4 0x30C 0x000 0x0 0x0
#define MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1 0x0A4 0x30C 0x000 0x5 0x0
#define MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0A8 0x310 0x000 0x0 0x0
#define MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x310 0x000 0x5 0x0
#define MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0AC 0x314 0x000 0x0 0x0
#define MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3 0x0AC 0x314 0x000 0x5 0x0
#define MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0B0 0x318 0x000 0x0 0x0
#define MX8MM_IOMUXC_SD1_DATA2_GPIO2_IO4 0x0B0 0x318 0x000 0x5 0x0
#define MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0B4 0x31C 0x000 0x0 0x0
#define MX8MM_IOMUXC_SD1_DATA3_GPIO2_IO5 0x0B4 0x31C 0x000 0x5 0x0
#define MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0B8 0x320 0x000 0x0 0x0
#define MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x0B8 0x320 0x000 0x5 0x0
#define MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0BC 0x324 0x000 0x0 0x0
#define MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x0BC 0x324 0x000 0x5 0x0
#define MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0C0 0x328 0x000 0x0 0x0
#define MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x0C0 0x328 0x000 0x5 0x0
#define MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0C4 0x32C 0x000 0x0 0x0
#define MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x0C4 0x32C 0x000 0x5 0x0
#define MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x0C8 0x330 0x000 0x0 0x0
#define MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x0C8 0x330 0x000 0x5 0x0
#define MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x0CC 0x334 0x000 0x0 0x0
#define MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x0CC 0x334 0x000 0x5 0x0
#define MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0D0 0x338 0x000 0x0 0x0
#define MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0D0 0x338 0x000 0x5 0x0
#define MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x0D4 0x33C 0x000 0x0 0x0
#define MX8MM_IOMUXC_SD2_CLK_GPIO2_IO13 0x0D4 0x33C 0x000 0x5 0x0
#define MX8MM_IOMUXC_SD2_CLK_CCMSRCGPCMIX_OBSERVE0 0x0D4 0x33C 0x000 0x6 0x0
#define MX8MM_IOMUXC_SD2_CLK_OBSERVE_MUX_OUT0 0x0D4 0x33C 0x000 0x7 0x0
#define MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x0D8 0x340 0x000 0x0 0x0
#define MX8MM_IOMUXC_SD2_CMD_GPIO2_IO14 0x0D8 0x340 0x000 0x5 0x0
#define MX8MM_IOMUXC_SD2_CMD_CCMSRCGPCMIX_OBSERVE1 0x0D8 0x340 0x000 0x6 0x0
#define MX8MM_IOMUXC_SD2_CMD_OBSERVE_MUX_OUT1 0x0D8 0x340 0x000 0x7 0x0
#define MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0DC 0x344 0x000 0x0 0x0
#define MX8MM_IOMUXC_SD2_DATA0_GPIO2_IO15 0x0DC 0x344 0x000 0x5 0x0
#define MX8MM_IOMUXC_SD2_DATA0_CCMSRCGPCMIX_OBSERVE2 0x0DC 0x344 0x000 0x6 0x0
#define MX8MM_IOMUXC_SD2_DATA0_OBSERVE_MUX_OUT2 0x0DC 0x344 0x000 0x7 0x0
#define MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0E0 0x348 0x000 0x0 0x0
#define MX8MM_IOMUXC_SD2_DATA1_GPIO2_IO16 0x0E0 0x348 0x000 0x5 0x0
#define MX8MM_IOMUXC_SD2_DATA1_CCMSRCGPCMIX_WAIT 0x0E0 0x348 0x000 0x6 0x0
#define MX8MM_IOMUXC_SD2_DATA1_OBSERVE_MUX_OUT3 0x0E0 0x348 0x000 0x7 0x0
#define MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0E4 0x34C 0x000 0x0 0x0
#define MX8MM_IOMUXC_SD2_DATA2_GPIO2_IO17 0x0E4 0x34C 0x000 0x5 0x0
#define MX8MM_IOMUXC_SD2_DATA2_CCMSRCGPCMIX_STOP 0x0E4 0x34C 0x000 0x6 0x0
#define MX8MM_IOMUXC_SD2_DATA2_OBSERVE_MUX_OUT4 0x0E4 0x34C 0x000 0x7 0x0
#define MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0E8 0x350 0x000 0x0 0x0
#define MX8MM_IOMUXC_SD2_DATA3_GPIO2_IO18 0x0E8 0x350 0x000 0x5 0x0
#define MX8MM_IOMUXC_SD2_DATA3_CCMSRCGPCMIX_EARLY_RESET 0x0E8 0x350 0x000 0x6 0x0
#define MX8MM_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x0EC 0x354 0x000 0x0 0x0
#define MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x0EC 0x354 0x000 0x5 0x0
#define MX8MM_IOMUXC_SD2_RESET_B_CCMSRCGPCMIX_SYSTEM_RESET 0x0EC 0x354 0x000 0x6 0x0
#define MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x0F0 0x358 0x000 0x0 0x0
#define MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x0F0 0x358 0x000 0x5 0x0
#define MX8MM_IOMUXC_SD2_WP_SIM_M_HMASTLOCK 0x0F0 0x358 0x000 0x7 0x0
#define MX8MM_IOMUXC_NAND_ALE_RAWNAND_ALE 0x0F4 0x35C 0x000 0x0 0x0
#define MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x0F4 0x35C 0x000 0x1 0x0
#define MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0 0x0F4 0x35C 0x000 0x5 0x0
#define MX8MM_IOMUXC_NAND_ALE_SIM_M_HPROT0 0x0F4 0x35C 0x000 0x7 0x0
#define MX8MM_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x0F8 0x360 0x000 0x0 0x0
#define MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x0F8 0x360 0x000 0x1 0x0
#define MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x0F8 0x360 0x000 0x5 0x0
#define MX8MM_IOMUXC_NAND_CE0_B_SIM_M_HPROT1 0x0F8 0x360 0x000 0x7 0x0
#define MX8MM_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x0FC 0x364 0x000 0x0 0x0
#define MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x0FC 0x364 0x000 0x1 0x0
#define MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x0FC 0x364 0x000 0x2 0x0
#define MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x0FC 0x364 0x000 0x5 0x0
#define MX8MM_IOMUXC_NAND_CE1_B_SIM_M_HPROT2 0x0FC 0x364 0x000 0x7 0x0
#define MX8MM_IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x100 0x368 0x000 0x0 0x0
#define MX8MM_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x100 0x368 0x000 0x1 0x0
#define MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x100 0x368 0x000 0x2 0x0
#define MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x100 0x368 0x000 0x5 0x0
#define MX8MM_IOMUXC_NAND_CE2_B_SIM_M_HPROT3 0x100 0x368 0x000 0x7 0x0
#define MX8MM_IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x104 0x36C 0x000 0x0 0x0
#define MX8MM_IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x104 0x36C 0x000 0x1 0x0
#define MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x104 0x36C 0x000 0x2 0x0
#define MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x104 0x36C 0x000 0x5 0x0
#define MX8MM_IOMUXC_NAND_CE3_B_SIM_M_HADDR0 0x104 0x36C 0x000 0x7 0x0
#define MX8MM_IOMUXC_NAND_CLE_RAWNAND_CLE 0x108 0x370 0x000 0x0 0x0
#define MX8MM_IOMUXC_NAND_CLE_QSPI_B_SCLK 0x108 0x370 0x000 0x1 0x0
#define MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x108 0x370 0x000 0x2 0x0
#define MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x108 0x370 0x000 0x5 0x0
#define MX8MM_IOMUXC_NAND_CLE_SIM_M_HADDR1 0x108 0x370 0x000 0x7 0x0
#define MX8MM_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x10C 0x374 0x000 0x0 0x0
#define MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x10C 0x374 0x000 0x1 0x0
#define MX8MM_IOMUXC_NAND_DATA00_GPIO3_IO6 0x10C 0x374 0x000 0x5 0x0
#define MX8MM_IOMUXC_NAND_DATA00_SIM_M_HADDR2 0x10C 0x374 0x000 0x7 0x0
#define MX8MM_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x110 0x378 0x000 0x0 0x0
#define MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x110 0x378 0x000 0x1 0x0
#define MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x110 0x378 0x000 0x5 0x0
#define MX8MM_IOMUXC_NAND_DATA01_SIM_M_HADDR3 0x110 0x378 0x000 0x7 0x0
#define MX8MM_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x114 0x37C 0x000 0x0 0x0
#define MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x114 0x37C 0x000 0x1 0x0
#define MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x114 0x37C 0x000 0x5 0x0
#define MX8MM_IOMUXC_NAND_DATA02_SIM_M_HADDR4 0x114 0x37C 0x000 0x7 0x0
#define MX8MM_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x118 0x380 0x000 0x0 0x0
#define MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x118 0x380 0x000 0x1 0x0
#define MX8MM_IOMUXC_NAND_DATA03_GPIO3_IO9 0x118 0x380 0x000 0x5 0x0
#define MX8MM_IOMUXC_NAND_DATA03_SIM_M_HADDR5 0x118 0x380 0x000 0x7 0x0
#define MX8MM_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x11C 0x384 0x000 0x0 0x0
#define MX8MM_IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x11C 0x384 0x000 0x1 0x0
#define MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x11C 0x384 0x000 0x2 0x0
#define MX8MM_IOMUXC_NAND_DATA04_GPIO3_IO10 0x11C 0x384 0x000 0x5 0x0
#define MX8MM_IOMUXC_NAND_DATA04_SIM_M_HADDR6 0x11C 0x384 0x000 0x7 0x0
#define MX8MM_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x120 0x388 0x000 0x0 0x0
#define MX8MM_IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x120 0x388 0x000 0x1 0x0
#define MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x120 0x388 0x000 0x2 0x0
#define MX8MM_IOMUXC_NAND_DATA05_GPIO3_IO11 0x120 0x388 0x000 0x5 0x0
#define MX8MM_IOMUXC_NAND_DATA05_SIM_M_HADDR7 0x120 0x388 0x000 0x7 0x0
#define MX8MM_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x124 0x38C 0x000 0x0 0x0
#define MX8MM_IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x124 0x38C 0x000 0x1 0x0
#define MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x124 0x38C 0x000 0x2 0x0
#define MX8MM_IOMUXC_NAND_DATA06_GPIO3_IO12 0x124 0x38C 0x000 0x5 0x0
#define MX8MM_IOMUXC_NAND_DATA06_SIM_M_HADDR8 0x124 0x38C 0x000 0x7 0x0
#define MX8MM_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x128 0x390 0x000 0x0 0x0
#define MX8MM_IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x128 0x390 0x000 0x1 0x0
#define MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x128 0x390 0x000 0x2 0x0
#define MX8MM_IOMUXC_NAND_DATA07_GPIO3_IO13 0x128 0x390 0x000 0x5 0x0
#define MX8MM_IOMUXC_NAND_DATA07_SIM_M_HADDR9 0x128 0x390 0x000 0x7 0x0
#define MX8MM_IOMUXC_NAND_DQS_RAWNAND_DQS 0x12C 0x394 0x000 0x0 0x0
#define MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS 0x12C 0x394 0x000 0x1 0x0
#define MX8MM_IOMUXC_NAND_DQS_GPIO3_IO14 0x12C 0x394 0x000 0x5 0x0
#define MX8MM_IOMUXC_NAND_DQS_SIM_M_HADDR10 0x12C 0x394 0x000 0x7 0x0
#define MX8MM_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x130 0x398 0x000 0x0 0x0
#define MX8MM_IOMUXC_NAND_RE_B_QSPI_B_DQS 0x130 0x398 0x000 0x1 0x0
#define MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x130 0x398 0x000 0x2 0x0
#define MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x130 0x398 0x000 0x5 0x0
#define MX8MM_IOMUXC_NAND_RE_B_SIM_M_HADDR11 0x130 0x398 0x000 0x7 0x0
#define MX8MM_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x134 0x39C 0x000 0x0 0x0
#define MX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B 0x134 0x39C 0x000 0x2 0x0
#define MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x134 0x39C 0x000 0x5 0x0
#define MX8MM_IOMUXC_NAND_READY_B_SIM_M_HADDR12 0x134 0x39C 0x000 0x7 0x0
#define MX8MM_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x138 0x3A0 0x000 0x0 0x0
#define MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x138 0x3A0 0x000 0x12 0x0
#define MX8MM_IOMUXC_NAND_WE_B_GPIO3_IO17 0x138 0x3A0 0x000 0x5 0x0
#define MX8MM_IOMUXC_NAND_WE_B_SIM_M_HADDR13 0x138 0x3A0 0x000 0x7 0x0
#define MX8MM_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x13C 0x3A4 0x000 0x0 0x0
#define MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x13C 0x3A4 0x000 0x2 0x0
#define MX8MM_IOMUXC_NAND_WP_B_GPIO3_IO18 0x13C 0x3A4 0x000 0x5 0x0
#define MX8MM_IOMUXC_NAND_WP_B_SIM_M_HADDR14 0x13C 0x3A4 0x000 0x7 0x0
#define MX8MM_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x140 0x3A8 0x4E4 0x0 0x0
#define MX8MM_IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x140 0x3A8 0x000 0x1 0x0
#define MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x140 0x3A8 0x000 0x5 0x0
#define MX8MM_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x144 0x3AC 0x4D0 0x0 0x0
#define MX8MM_IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x144 0x3AC 0x000 0x1 0x0
#define MX8MM_IOMUXC_SAI5_RXC_PDM_CLK 0x144 0x3AC 0x000 0x4 0x0
#define MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x144 0x3AC 0x000 0x5 0x0
#define MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x148 0x3B0 0x4D4 0x0 0x0
#define MX8MM_IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x148 0x3B0 0x000 0x1 0x0
#define MX8MM_IOMUXC_SAI5_RXD0_PDM_DATA0 0x148 0x3B0 0x534 0x4 0x0
#define MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x148 0x3B0 0x000 0x5 0x0
#define MX8MM_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x14C 0x3B4 0x4D8 0x0 0x0
#define MX8MM_IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x14C 0x3B4 0x000 0x1 0x0
#define MX8MM_IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x14C 0x3B4 0x4CC 0x2 0x0
#define MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x14C 0x3B4 0x4EC 0x3 0x0
#define MX8MM_IOMUXC_SAI5_RXD1_PDM_DATA1 0x14C 0x3B4 0x538 0x4 0x0
#define MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x14C 0x3B4 0x000 0x5 0x0
#define MX8MM_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x150 0x3B8 0x4DC 0x0 0x0
#define MX8MM_IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x150 0x3B8 0x000 0x1 0x0
#define MX8MM_IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x150 0x3B8 0x4CC 0x2 0x1
#define MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x150 0x3B8 0x4E8 0x3 0x0
#define MX8MM_IOMUXC_SAI5_RXD2_PDM_DATA2 0x150 0x3B8 0x53C 0x4 0x0
#define MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x150 0x3B8 0x000 0x5 0x0
#define MX8MM_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x154 0x3BC 0x4E0 0x0 0x0
#define MX8MM_IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x154 0x3BC 0x000 0x1 0x0
#define MX8MM_IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x154 0x3BC 0x4CC 0x2 0x2
#define MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x154 0x3BC 0x000 0x3 0x0
#define MX8MM_IOMUXC_SAI5_RXD3_PDM_DATA3 0x154 0x3BC 0x540 0x4 0x0
#define MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x154 0x3BC 0x000 0x5 0x0
#define MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0x158 0x3C0 0x52C 0x0 0x0
#define MX8MM_IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x158 0x3C0 0x4C8 0x1 0x0
#define MX8MM_IOMUXC_SAI5_MCLK_SAI4_MCLK 0x158 0x3C0 0x000 0x2 0x0
#define MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x158 0x3C0 0x000 0x5 0x0
#define MX8MM_IOMUXC_SAI5_MCLK_CCMSRCGPCMIX_TESTER_ACK 0x158 0x3C0 0x000 0x6 0x0
#define MX8MM_IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x15C 0x3C4 0x4C4 0x0 0x0
#define MX8MM_IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x15C 0x3C4 0x4E4 0x1 0x1
#define MX8MM_IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x15C 0x3C4 0x000 0x4 0x0
#define MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x15C 0x3C4 0x000 0x5 0x0
#define MX8MM_IOMUXC_SAI1_RXFS_SIM_M_HADDR15 0x15C 0x3C4 0x000 0x7 0x0
#define MX8MM_IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x160 0x3C8 0x000 0x0 0x0
#define MX8MM_IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x160 0x3C8 0x4D0 0x1 0x1
#define MX8MM_IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x160 0x3C8 0x000 0x4 0x0
#define MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x160 0x3C8 0x000 0x5 0x0
#define MX8MM_IOMUXC_SAI1_RXC_SIM_M_HADDR16 0x160 0x3C8 0x000 0x7 0x0
#define MX8MM_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x164 0x3CC 0x000 0x0 0x0
#define MX8MM_IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x164 0x3CC 0x4D4 0x1 0x1
#define MX8MM_IOMUXC_SAI1_RXD0_PDM_DATA0 0x164 0x3CC 0x534 0x3 0x1
#define MX8MM_IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x164 0x3CC 0x000 0x4 0x0
#define MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x164 0x3CC 0x000 0x5 0x0
#define MX8MM_IOMUXC_SAI1_RXD0_CCMSRCGPCMIX_BOOT_CFG0 0x164 0x3CC 0x000 0x6 0x0
#define MX8MM_IOMUXC_SAI1_RXD0_SIM_M_HADDR17 0x164 0x3CC 0x000 0x7 0x0
#define MX8MM_IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x168 0x3D0 0x000 0x0 0x0
#define MX8MM_IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x168 0x3D0 0x4D8 0x1 0x1
#define MX8MM_IOMUXC_SAI1_RXD1_PDM_DATA1 0x168 0x3D0 0x538 0x3 0x1
#define MX8MM_IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x168 0x3D0 0x000 0x4 0x0
#define MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x168 0x3D0 0x000 0x5 0x0
#define MX8MM_IOMUXC_SAI1_RXD1_CCMSRCGPCMIX_BOOT_CFG1 0x168 0x3D0 0x000 0x6 0x0
#define MX8MM_IOMUXC_SAI1_RXD1_SIM_M_HADDR18 0x168 0x3D0 0x000 0x7 0x0
#define MX8MM_IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x16C 0x3D4 0x000 0x0 0x0
#define MX8MM_IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x16C 0x3D4 0x4DC 0x1 0x1
#define MX8MM_IOMUXC_SAI1_RXD2_PDM_DATA2 0x16C 0x3D4 0x53C 0x3 0x1
#define MX8MM_IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x16C 0x3D4 0x000 0x4 0x0
#define MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x16C 0x3D4 0x000 0x5 0x0
#define MX8MM_IOMUXC_SAI1_RXD2_CCMSRCGPCMIX_BOOT_CFG2 0x16C 0x3D4 0x000 0x6 0x0
#define MX8MM_IOMUXC_SAI1_RXD2_SIM_M_HADDR19 0x16C 0x3D4 0x000 0x7 0x0
#define MX8MM_IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x170 0x3D8 0x4E0 0x0 0x1
#define MX8MM_IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x170 0x3D8 0x000 0x1 0x0
#define MX8MM_IOMUXC_SAI1_RXD3_PDM_DATA3 0x170 0x3D8 0x540 0x3 0x1
#define MX8MM_IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x170 0x3D8 0x000 0x4 0x0
#define MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x170 0x3D8 0x000 0x5 0x0
#define MX8MM_IOMUXC_SAI1_RXD3_CCMSRCGPCMIX_BOOT_CFG3 0x170 0x3D8 0x000 0x6 0x0
#define MX8MM_IOMUXC_SAI1_RXD3_SIM_M_HADDR20 0x170 0x3D8 0x000 0x7 0x0
#define MX8MM_IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x174 0x3DC 0x000 0x0 0x0
#define MX8MM_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x174 0x3DC 0x51C 0x1 0x0
#define MX8MM_IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x174 0x3DC 0x510 0x2 0x0
#define MX8MM_IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x174 0x3DC 0x000 0x4 0x0
#define MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x174 0x3DC 0x000 0x5 0x0
#define MX8MM_IOMUXC_SAI1_RXD4_CCMSRCGPCMIX_BOOT_CFG4 0x174 0x3DC 0x000 0x6 0x0
#define MX8MM_IOMUXC_SAI1_RXD4_SIM_M_HADDR21 0x174 0x3DC 0x000 0x7 0x0
#define MX8MM_IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x178 0x3E0 0x000 0x0 0x0
#define MX8MM_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x178 0x3E0 0x000 0x1 0x0
#define MX8MM_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x178 0x3E0 0x514 0x2 0x0
#define MX8MM_IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x178 0x3E0 0x4C4 0x3 0x1
#define MX8MM_IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x178 0x3E0 0x000 0x4 0x0
#define MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x178 0x3E0 0x000 0x5 0x0
#define MX8MM_IOMUXC_SAI1_RXD5_CCMSRCGPCMIX_BOOT_CFG5 0x178 0x3E0 0x000 0x6 0x0
#define MX8MM_IOMUXC_SAI1_RXD5_SIM_M_HADDR22 0x178 0x3E0 0x000 0x7 0x0
#define MX8MM_IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x17C 0x3E4 0x520 0x0 0x0
#define MX8MM_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x17C 0x3E4 0x000 0x1 0x0
#define MX8MM_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x17C 0x3E4 0x518 0x2 0x0
#define MX8MM_IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x17C 0x3E4 0x000 0x4 0x0
#define MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x17C 0x3E4 0x000 0x5 0x0
#define MX8MM_IOMUXC_SAI1_RXD6_CCMSRCGPCMIX_BOOT_CFG6 0x17C 0x3E4 0x000 0x6 0x0
#define MX8MM_IOMUXC_SAI1_RXD6_SIM_M_HADDR23 0x17C 0x3E4 0x000 0x7 0x0
#define MX8MM_IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x180 0x3E8 0x000 0x0 0x0
#define MX8MM_IOMUXC_SAI1_RXD7_SAI6_MCLK 0x180 0x3E8 0x530 0x1 0x0
#define MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x180 0x3E8 0x4CC 0x2 0x4
#define MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x180 0x3E8 0x000 0x3 0x0
#define MX8MM_IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x180 0x3E8 0x000 0x4 0x0
#define MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x180 0x3E8 0x000 0x5 0x0
#define MX8MM_IOMUXC_SAI1_RXD7_CCMSRCGPCMIX_BOOT_CFG7 0x180 0x3E8 0x000 0x6 0x0
#define MX8MM_IOMUXC_SAI1_RXD7_SIM_M_HADDR24 0x180 0x3E8 0x000 0x7 0x0
#define MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x184 0x3EC 0x4CC 0x0 0x3
#define MX8MM_IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x184 0x3EC 0x4EC 0x1 0x1
#define MX8MM_IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x184 0x3EC 0x000 0x4 0x0
#define MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x184 0x3EC 0x000 0x5 0x0
#define MX8MM_IOMUXC_SAI1_TXFS_SIM_M_HADDR25 0x184 0x3EC 0x000 0x7 0x0
#define MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x188 0x3F0 0x4C8 0x0 0x1
#define MX8MM_IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x188 0x3F0 0x4E8 0x1 0x1
#define MX8MM_IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x188 0x3F0 0x000 0x4 0x0
#define MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x188 0x3F0 0x000 0x5 0x0
#define MX8MM_IOMUXC_SAI1_TXC_SIM_M_HADDR26 0x188 0x3F0 0x000 0x7 0x0
#define MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x18C 0x3F4 0x000 0x0 0x0
#define MX8MM_IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x18C 0x3F4 0x000 0x1 0x0
#define MX8MM_IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x18C 0x3F4 0x000 0x4 0x0
#define MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x18C 0x3F4 0x000 0x5 0x0
#define MX8MM_IOMUXC_SAI1_TXD0_CCMSRCGPCMIX_BOOT_CFG8 0x18C 0x3F4 0x000 0x6 0x0
#define MX8MM_IOMUXC_SAI1_TXD0_SIM_M_HADDR27 0x18C 0x3F4 0x000 0x7 0x0
#define MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x190 0x3F8 0x000 0x0 0x0
#define MX8MM_IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x190 0x3F8 0x000 0x1 0x0
#define MX8MM_IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x190 0x3F8 0x000 0x4 0x0
#define MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x190 0x3F8 0x000 0x5 0x0
#define MX8MM_IOMUXC_SAI1_TXD1_CCMSRCGPCMIX_BOOT_CFG9 0x190 0x3F8 0x000 0x6 0x0
#define MX8MM_IOMUXC_SAI1_TXD1_SIM_M_HADDR28 0x190 0x3F8 0x000 0x7 0x0
#define MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x194 0x3FC 0x000 0x0 0x0
#define MX8MM_IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x194 0x3FC 0x000 0x1 0x0
#define MX8MM_IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x194 0x3FC 0x000 0x4 0x0
#define MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x194 0x3FC 0x000 0x5 0x0
#define MX8MM_IOMUXC_SAI1_TXD2_CCMSRCGPCMIX_BOOT_CFG10 0x194 0x3FC 0x000 0x6 0x0
#define MX8MM_IOMUXC_SAI1_TXD2_SIM_M_HADDR29 0x194 0x3FC 0x000 0x7 0x0
#define MX8MM_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x198 0x400 0x000 0x0 0x0
#define MX8MM_IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x198 0x400 0x000 0x1 0x0
#define MX8MM_IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x198 0x400 0x000 0x4 0x0
#define MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x198 0x400 0x000 0x5 0x0
#define MX8MM_IOMUXC_SAI1_TXD3_CCMSRCGPCMIX_BOOT_CFG11 0x198 0x400 0x000 0x6 0x0
#define MX8MM_IOMUXC_SAI1_TXD3_SIM_M_HADDR30 0x198 0x400 0x000 0x7 0x0
#define MX8MM_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x19C 0x404 0x000 0x0 0x0
#define MX8MM_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x19C 0x404 0x510 0x1 0x1
#define MX8MM_IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x19C 0x404 0x51C 0x2 0x1
#define MX8MM_IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x19C 0x404 0x000 0x4 0x0
#define MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x19C 0x404 0x000 0x5 0x0
#define MX8MM_IOMUXC_SAI1_TXD4_CCMSRCGPCMIX_BOOT_CFG12 0x19C 0x404 0x000 0x6 0x0
#define MX8MM_IOMUXC_SAI1_TXD4_SIM_M_HADDR31 0x19C 0x404 0x000 0x7 0x0
#define MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x1A0 0x408 0x000 0x0 0x0
#define MX8MM_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x1A0 0x408 0x514 0x1 0x1
#define MX8MM_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x1A0 0x408 0x000 0x2 0x0
#define MX8MM_IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x1A0 0x408 0x000 0x4 0x0
#define MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x1A0 0x408 0x000 0x5 0x0
#define MX8MM_IOMUXC_SAI1_TXD5_CCMSRCGPCMIX_BOOT_CFG13 0x1A0 0x408 0x000 0x6 0x0
#define MX8MM_IOMUXC_SAI1_TXD5_SIM_M_HBURST0 0x1A0 0x408 0x000 0x7 0x0
#define MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x1A4 0x40C 0x000 0x0 0x0
#define MX8MM_IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x1A4 0x40C 0x518 0x1 0x1
#define MX8MM_IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x1A4 0x40C 0x520 0x2 0x1
#define MX8MM_IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x1A4 0x40C 0x000 0x4 0x0
#define MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x1A4 0x40C 0x000 0x5 0x0
#define MX8MM_IOMUXC_SAI1_TXD6_CCMSRCGPCMIX_BOOT_CFG14 0x1A4 0x40C 0x000 0x6 0x0
#define MX8MM_IOMUXC_SAI1_TXD6_SIM_M_HBURST1 0x1A4 0x40C 0x000 0x7 0x0
#define MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x1A8 0x410 0x000 0x0 0x0
#define MX8MM_IOMUXC_SAI1_TXD7_SAI6_MCLK 0x1A8 0x410 0x530 0x1 0x1
#define MX8MM_IOMUXC_SAI1_TXD7_PDM_CLK 0x1A8 0x410 0x000 0x3 0x0
#define MX8MM_IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x1A8 0x410 0x000 0x4 0x0
#define MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x1A8 0x410 0x000 0x5 0x0
#define MX8MM_IOMUXC_SAI1_TXD7_CCMSRCGPCMIX_BOOT_CFG15 0x1A8 0x410 0x000 0x6 0x0
#define MX8MM_IOMUXC_SAI1_TXD7_SIM_M_HBURST2 0x1A8 0x410 0x000 0x7 0x0
#define MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0x1AC 0x414 0x000 0x0 0x0
#define MX8MM_IOMUXC_SAI1_MCLK_SAI5_MCLK 0x1AC 0x414 0x52C 0x1 0x1
#define MX8MM_IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x1AC 0x414 0x4C8 0x2 0x2
#define MX8MM_IOMUXC_SAI1_MCLK_PDM_CLK 0x1AC 0x414 0x000 0x3 0x0
#define MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x1AC 0x414 0x000 0x5 0x0
#define MX8MM_IOMUXC_SAI1_MCLK_SIM_M_HRESP 0x1AC 0x414 0x000 0x7 0x0
#define MX8MM_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x1B0 0x418 0x000 0x0 0x0
#define MX8MM_IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x1B0 0x418 0x4EC 0x1 0x2
#define MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x1B0 0x418 0x000 0x4 0x0
#define MX8MM_IOMUXC_SAI2_RXFS_UART1_DTE_RX 0x1B0 0x418 0x4F4 0x4 0x2
#define MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x1B0 0x418 0x000 0x5 0x0
#define MX8MM_IOMUXC_SAI2_RXFS_SIM_M_HSIZE0 0x1B0 0x418 0x000 0x7 0x0
#define MX8MM_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x1B4 0x41C 0x000 0x0 0x0
#define MX8MM_IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x1B4 0x41C 0x4E8 0x1 0x2
#define MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x1B4 0x41C 0x4F4 0x4 0x3
#define MX8MM_IOMUXC_SAI2_RXC_UART1_DTE_TX 0x1B4 0x41C 0x000 0x4 0x0
#define MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x1B4 0x41C 0x000 0x5 0x0
#define MX8MM_IOMUXC_SAI2_RXC_SIM_M_HSIZE1 0x1B4 0x41C 0x000 0x7 0x0
#define MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x1B8 0x420 0x000 0x0 0x0
#define MX8MM_IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x1B8 0x420 0x000 0x1 0x0
#define MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x1B8 0x420 0x4F0 0x4 0x2
#define MX8MM_IOMUXC_SAI2_RXD0_UART1_DTE_CTS_B 0x1B8 0x420 0x000 0x4 0x0
#define MX8MM_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x1B8 0x420 0x000 0x5 0x0
#define MX8MM_IOMUXC_SAI2_RXD0_SIM_M_HSIZE2 0x1B8 0x420 0x000 0x7 0x0
#define MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x1BC 0x424 0x000 0x0 0x0
#define MX8MM_IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x1BC 0x424 0x000 0x1 0x0
#define MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x1BC 0x424 0x000 0x4 0x0
#define MX8MM_IOMUXC_SAI2_TXFS_UART1_DTE_RTS_B 0x1BC 0x424 0x4F0 0x4 0x3
#define MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x1BC 0x424 0x000 0x5 0x0
#define MX8MM_IOMUXC_SAI2_TXFS_SIM_M_HWRITE 0x1BC 0x424 0x000 0x7 0x0
#define MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x1C0 0x428 0x000 0x0 0x0
#define MX8MM_IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x1C0 0x428 0x000 0x1 0x0
#define MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x1C0 0x428 0x000 0x5 0x0
#define MX8MM_IOMUXC_SAI2_TXC_SIM_M_HREADYOUT 0x1C0 0x428 0x000 0x7 0x0
#define MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x1C4 0x42C 0x000 0x0 0x0
#define MX8MM_IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x1C4 0x42C 0x000 0x1 0x0
#define MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x1C4 0x42C 0x000 0x5 0x0
#define MX8MM_IOMUXC_SAI2_TXD0_TPSMP_CLK 0x1C4 0x42C 0x000 0x7 0x0
#define MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x1C8 0x430 0x000 0x0 0x0
#define MX8MM_IOMUXC_SAI2_MCLK_SAI5_MCLK 0x1C8 0x430 0x52C 0x1 0x2
#define MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x1C8 0x430 0x000 0x5 0x0
#define MX8MM_IOMUXC_SAI2_MCLK_TPSMP_HDATA_DIR 0x1C8 0x430 0x000 0x7 0x0
#define MX8MM_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x1CC 0x434 0x000 0x0 0x0
#define MX8MM_IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x1CC 0x434 0x000 0x1 0x0
#define MX8MM_IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x1CC 0x434 0x4E4 0x2 0x2
#define MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x1CC 0x434 0x000 0x5 0x0
#define MX8MM_IOMUXC_SAI3_RXFS_TPSMP_HTRANS0 0x1CC 0x434 0x000 0x7 0x0
#define MX8MM_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x1D0 0x438 0x000 0x0 0x0
#define MX8MM_IOMUXC_SAI3_RXC_GPT1_CLK 0x1D0 0x438 0x000 0x1 0x0
#define MX8MM_IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x1D0 0x438 0x4D0 0x2 0x2
#define MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x1D0 0x438 0x000 0x4 0x0
#define MX8MM_IOMUXC_SAI3_RXC_UART2_DTE_RTS_B 0x1D0 0x438 0x4F8 0x4 0x2
#define MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x1D0 0x438 0x000 0x5 0x0
#define MX8MM_IOMUXC_SAI3_RXC_TPSMP_HTRANS1 0x1D0 0x438 0x000 0x7 0x0
#define MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x1D4 0x43C 0x000 0x0 0x0
#define MX8MM_IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x1D4 0x43C 0x000 0x1 0x0
#define MX8MM_IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x1D4 0x43C 0x4D4 0x2 0x2
#define MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x1D4 0x43C 0x4F8 0x4 0x3
#define MX8MM_IOMUXC_SAI3_RXD_UART2_DTE_CTS_B 0x1D4 0x43C 0x000 0x4 0x0
#define MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x1D4 0x43C 0x000 0x5 0x0
#define MX8MM_IOMUXC_SAI3_RXD_TPSMP_HDATA0 0x1D4 0x43C 0x000 0x7 0x0
#define MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x1D8 0x440 0x000 0x0 0x0
#define MX8MM_IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x1D8 0x440 0x000 0x1 0x0
#define MX8MM_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x1D8 0x440 0x4D8 0x2 0x2
#define MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x1D8 0x440 0x4FC 0x4 0x2
#define MX8MM_IOMUXC_SAI3_TXFS_UART2_DTE_TX 0x1D8 0x440 0x000 0x4 0x0
#define MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x1D8 0x440 0x000 0x5 0x0
#define MX8MM_IOMUXC_SAI3_TXFS_TPSMP_HDATA1 0x1D8 0x440 0x000 0x7 0x0
#define MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x1DC 0x444 0x000 0x0 0x0
#define MX8MM_IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x1DC 0x444 0x000 0x1 0x0
#define MX8MM_IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x1DC 0x444 0x4DC 0x2 0x2
#define MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x1DC 0x444 0x000 0x4 0x0
#define MX8MM_IOMUXC_SAI3_TXC_UART2_DTE_RX 0x1DC 0x444 0x4FC 0x4 0x3
#define MX8MM_IOMUXC_SAI3_TXC_GPIO5_IO0 0x1DC 0x444 0x000 0x5 0x0
#define MX8MM_IOMUXC_SAI3_TXC_TPSMP_HDATA2 0x1DC 0x444 0x000 0x7 0x0
#define MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x1E0 0x448 0x000 0x0 0x0
#define MX8MM_IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x1E0 0x448 0x000 0x1 0x0
#define MX8MM_IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x1E0 0x448 0x4E0 0x2 0x2
#define MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x1E0 0x448 0x000 0x5 0x0
#define MX8MM_IOMUXC_SAI3_TXD_TPSMP_HDATA3 0x1E0 0x448 0x000 0x7 0x0
#define MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0x1E4 0x44C 0x000 0x0 0x0
#define MX8MM_IOMUXC_SAI3_MCLK_PWM4_OUT 0x1E4 0x44C 0x000 0x1 0x0
#define MX8MM_IOMUXC_SAI3_MCLK_SAI5_MCLK 0x1E4 0x44C 0x52C 0x2 0x3
#define MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x1E4 0x44C 0x000 0x5 0x0
#define MX8MM_IOMUXC_SAI3_MCLK_TPSMP_HDATA4 0x1E4 0x44C 0x000 0x7 0x0
#define MX8MM_IOMUXC_SPDIF_TX_SPDIF1_OUT 0x1E8 0x450 0x000 0x0 0x0
#define MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x1E8 0x450 0x000 0x1 0x0
#define MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x1E8 0x450 0x000 0x5 0x0
#define MX8MM_IOMUXC_SPDIF_TX_TPSMP_HDATA5 0x1E8 0x450 0x000 0x7 0x0
#define MX8MM_IOMUXC_SPDIF_RX_SPDIF1_IN 0x1EC 0x454 0x000 0x0 0x0
#define MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x1EC 0x454 0x000 0x1 0x0
#define MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x1EC 0x454 0x000 0x5 0x0
#define MX8MM_IOMUXC_SPDIF_RX_TPSMP_HDATA6 0x1EC 0x454 0x000 0x7 0x0
#define MX8MM_IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x1F0 0x458 0x000 0x0 0x0
#define MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x1F0 0x458 0x000 0x1 0x0
#define MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x1F0 0x458 0x000 0x5 0x0
#define MX8MM_IOMUXC_SPDIF_EXT_CLK_TPSMP_HDATA7 0x1F0 0x458 0x000 0x7 0x0
#define MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x1F4 0x45C 0x000 0x0 0x0
#define MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x1F4 0x45C 0x504 0x1 0x0
#define MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DTE_TX 0x1F4 0x45C 0x000 0x1 0x0
#define MX8MM_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x1F4 0x45C 0x000 0x5 0x0
#define MX8MM_IOMUXC_ECSPI1_SCLK_TPSMP_HDATA8 0x1F4 0x45C 0x000 0x7 0x0
#define MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x1F8 0x460 0x000 0x0 0x0
#define MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x1F8 0x460 0x000 0x1 0x0
#define MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DTE_RX 0x1F8 0x460 0x504 0x1 0x1
#define MX8MM_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x1F8 0x460 0x000 0x5 0x0
#define MX8MM_IOMUXC_ECSPI1_MOSI_TPSMP_HDATA9 0x1F8 0x460 0x000 0x7 0x0
#define MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x1FC 0x464 0x000 0x0 0x0
#define MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x1FC 0x464 0x000 0x1 0x0
#define MX8MM_IOMUXC_ECSPI1_MISO_UART3_DTE_RTS_B 0x1FC 0x464 0x500 0x1 0x0
#define MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x1FC 0x464 0x000 0x5 0x0
#define MX8MM_IOMUXC_ECSPI1_MISO_TPSMP_HDATA10 0x1FC 0x464 0x000 0x7 0x0
#define MX8MM_IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x200 0x468 0x000 0x0 0x0
#define MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x200 0x468 0x500 0x1 0x1
#define MX8MM_IOMUXC_ECSPI1_SS0_UART3_DTE_CTS_B 0x200 0x468 0x000 0x1 0x0
#define MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x200 0x468 0x000 0x5 0x0
#define MX8MM_IOMUXC_ECSPI1_SS0_TPSMP_HDATA11 0x200 0x468 0x000 0x7 0x0
#define MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x204 0x46C 0x000 0x0 0x0
#define MX8MM_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x204 0x46C 0x50C 0x1 0x0
#define MX8MM_IOMUXC_ECSPI2_SCLK_UART4_DTE_TX 0x204 0x46C 0x000 0x1 0x0
#define MX8MM_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x204 0x46C 0x000 0x5 0x0
#define MX8MM_IOMUXC_ECSPI2_SCLK_TPSMP_HDATA12 0x204 0x46C 0x000 0x7 0x0
#define MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x208 0x470 0x000 0x0 0x0
#define MX8MM_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x208 0x470 0x000 0x1 0x0
#define MX8MM_IOMUXC_ECSPI2_MOSI_UART4_DTE_RX 0x208 0x470 0x50C 0x1 0x1
#define MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x208 0x470 0x000 0x5 0x0
#define MX8MM_IOMUXC_ECSPI2_MOSI_TPSMP_HDATA13 0x208 0x470 0x000 0x7 0x0
#define MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x20C 0x474 0x000 0x0 0x0
#define MX8MM_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x20C 0x474 0x000 0x1 0x0
#define MX8MM_IOMUXC_ECSPI2_MISO_UART4_DTE_RTS_B 0x20C 0x474 0x508 0x1 0x0
#define MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x20C 0x474 0x000 0x5 0x0
#define MX8MM_IOMUXC_ECSPI2_MISO_TPSMP_HDATA14 0x20C 0x474 0x000 0x7 0x0
#define MX8MM_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x210 0x478 0x000 0x0 0x0
#define MX8MM_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x210 0x478 0x508 0x1 0x1
#define MX8MM_IOMUXC_ECSPI2_SS0_UART4_DTE_CTS_B 0x210 0x478 0x000 0x1 0x0
#define MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x210 0x478 0x000 0x5 0x0
#define MX8MM_IOMUXC_ECSPI2_SS0_TPSMP_HDATA15 0x210 0x478 0x000 0x7 0x0
#define MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x214 0x47C 0x000 0x0 0x0
#define MX8MM_IOMUXC_I2C1_SCL_ENET1_MDC 0x214 0x47C 0x000 0x1 0x0
#define MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x214 0x47C 0x000 0x5 0x0
#define MX8MM_IOMUXC_I2C1_SCL_TPSMP_HDATA16 0x214 0x47C 0x000 0x7 0x0
#define MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x218 0x480 0x000 0x0 0x0
#define MX8MM_IOMUXC_I2C1_SDA_ENET1_MDIO 0x218 0x480 0x4C0 0x1 0x2
#define MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x218 0x480 0x000 0x5 0x0
#define MX8MM_IOMUXC_I2C1_SDA_TPSMP_HDATA17 0x218 0x480 0x000 0x7 0x0
#define MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x21C 0x484 0x000 0x0 0x0
#define MX8MM_IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x21C 0x484 0x000 0x1 0x0
#define MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x21C 0x484 0x000 0x5 0x0
#define MX8MM_IOMUXC_I2C2_SCL_TPSMP_HDATA18 0x21C 0x484 0x000 0x7 0x0
#define MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x220 0x488 0x000 0x0 0x0
#define MX8MM_IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x220 0x488 0x000 0x1 0x0
#define MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x220 0x488 0x000 0x5 0x0
#define MX8MM_IOMUXC_I2C2_SDA_TPSMP_HDATA19 0x220 0x488 0x000 0x7 0x0
#define MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x224 0x48C 0x000 0x0 0x0
#define MX8MM_IOMUXC_I2C3_SCL_PWM4_OUT 0x224 0x48C 0x000 0x1 0x0
#define MX8MM_IOMUXC_I2C3_SCL_GPT2_CLK 0x224 0x48C 0x000 0x2 0x0
#define MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x224 0x48C 0x000 0x5 0x0
#define MX8MM_IOMUXC_I2C3_SCL_TPSMP_HDATA20 0x224 0x48C 0x000 0x7 0x0
#define MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x228 0x490 0x000 0x0 0x0
#define MX8MM_IOMUXC_I2C3_SDA_PWM3_OUT 0x228 0x490 0x000 0x1 0x0
#define MX8MM_IOMUXC_I2C3_SDA_GPT3_CLK 0x228 0x490 0x000 0x2 0x0
#define MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x228 0x490 0x000 0x5 0x0
#define MX8MM_IOMUXC_I2C3_SDA_TPSMP_HDATA21 0x228 0x490 0x000 0x7 0x0
#define MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x22C 0x494 0x000 0x0 0x0
#define MX8MM_IOMUXC_I2C4_SCL_PWM2_OUT 0x22C 0x494 0x000 0x1 0x0
#define MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x22C 0x494 0x524 0x12 0x0
#define MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x22C 0x494 0x000 0x5 0x0
#define MX8MM_IOMUXC_I2C4_SCL_TPSMP_HDATA22 0x22C 0x494 0x000 0x7 0x0
#define MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x230 0x498 0x000 0x0 0x0
#define MX8MM_IOMUXC_I2C4_SDA_PWM1_OUT 0x230 0x498 0x000 0x1 0x0
#define MX8MM_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x230 0x498 0x528 0x2 0x0
#define MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x230 0x498 0x000 0x5 0x0
#define MX8MM_IOMUXC_I2C4_SDA_TPSMP_HDATA23 0x230 0x498 0x000 0x7 0x0
#define MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x234 0x49C 0x4F4 0x0 0x0
#define MX8MM_IOMUXC_UART1_RXD_UART1_DTE_TX 0x234 0x49C 0x000 0x0 0x0
#define MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x234 0x49C 0x000 0x1 0x0
#define MX8MM_IOMUXC_UART1_RXD_GPIO5_IO22 0x234 0x49C 0x000 0x5 0x0
#define MX8MM_IOMUXC_UART1_RXD_TPSMP_HDATA24 0x234 0x49C 0x000 0x7 0x0
#define MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x238 0x4A0 0x000 0x0 0x0
#define MX8MM_IOMUXC_UART1_TXD_UART1_DTE_RX 0x238 0x4A0 0x4F4 0x0 0x0
#define MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x238 0x4A0 0x000 0x1 0x0
#define MX8MM_IOMUXC_UART1_TXD_GPIO5_IO23 0x238 0x4A0 0x000 0x5 0x0
#define MX8MM_IOMUXC_UART1_TXD_TPSMP_HDATA25 0x238 0x4A0 0x000 0x7 0x0
#define MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x23C 0x4A4 0x4FC 0x0 0x0
#define MX8MM_IOMUXC_UART2_RXD_UART2_DTE_TX 0x23C 0x4A4 0x000 0x0 0x0
#define MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x23C 0x4A4 0x000 0x1 0x0
#define MX8MM_IOMUXC_UART2_RXD_GPIO5_IO24 0x23C 0x4A4 0x000 0x5 0x0
#define MX8MM_IOMUXC_UART2_RXD_TPSMP_HDATA26 0x23C 0x4A4 0x000 0x7 0x0
#define MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x240 0x4A8 0x000 0x0 0x0
#define MX8MM_IOMUXC_UART2_TXD_UART2_DTE_RX 0x240 0x4A8 0x4FC 0x0 0x1
#define MX8MM_IOMUXC_UART2_TXD_ECSPI3_SS0 0x240 0x4A8 0x000 0x1 0x0
#define MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x240 0x4A8 0x000 0x5 0x0
#define MX8MM_IOMUXC_UART2_TXD_TPSMP_HDATA27 0x240 0x4A8 0x000 0x7 0x0
#define MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x244 0x4AC 0x504 0x0 0x2
#define MX8MM_IOMUXC_UART3_RXD_UART3_DTE_TX 0x244 0x4AC 0x000 0x0 0x0
#define MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x244 0x4AC 0x000 0x1 0x0
#define MX8MM_IOMUXC_UART3_RXD_UART1_DTE_RTS_B 0x244 0x4AC 0x4F0 0x1 0x0
#define MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26 0x244 0x4AC 0x000 0x5 0x0
#define MX8MM_IOMUXC_UART3_RXD_TPSMP_HDATA28 0x244 0x4AC 0x000 0x7 0x0
#define MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x248 0x4B0 0x000 0x0 0x0
#define MX8MM_IOMUXC_UART3_TXD_UART3_DTE_RX 0x248 0x4B0 0x504 0x0 0x3
#define MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x248 0x4B0 0x4F0 0x1 0x1
#define MX8MM_IOMUXC_UART3_TXD_UART1_DTE_CTS_B 0x248 0x4B0 0x000 0x1 0x0
#define MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27 0x248 0x4B0 0x000 0x5 0x0
#define MX8MM_IOMUXC_UART3_TXD_TPSMP_HDATA29 0x248 0x4B0 0x000 0x7 0x0
#define MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x24C 0x4B4 0x50C 0x0 0x2
#define MX8MM_IOMUXC_UART4_RXD_UART4_DTE_TX 0x24C 0x4B4 0x000 0x0 0x0
#define MX8MM_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x24C 0x4B4 0x000 0x1 0x0
#define MX8MM_IOMUXC_UART4_RXD_UART2_DTE_RTS_B 0x24C 0x4B4 0x4F8 0x1 0x0
#define MX8MM_IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x24C 0x4B4 0x524 0x2 0x1
#define MX8MM_IOMUXC_UART4_RXD_GPIO5_IO28 0x24C 0x4B4 0x000 0x5 0x0
#define MX8MM_IOMUXC_UART4_RXD_TPSMP_HDATA30 0x24C 0x4B4 0x000 0x7 0x0
#define MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x250 0x4B8 0x000 0x0 0x0
#define MX8MM_IOMUXC_UART4_TXD_UART4_DTE_RX 0x250 0x4B8 0x50C 0x0 0x3
#define MX8MM_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x250 0x4B8 0x4F8 0x1 0x1
#define MX8MM_IOMUXC_UART4_TXD_UART2_DTE_CTS_B 0x250 0x4B8 0x000 0x1 0x0
#define MX8MM_IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x250 0x4B8 0x528 0x2 0x1
#define MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x250 0x4B8 0x000 0x5 0x0
#define MX8MM_IOMUXC_UART4_TXD_TPSMP_HDATA31 0x250 0x4B8 0x000 0x7 0x0
#endif /* __DTS_IMX8MM_PINFUNC_H */

View File

@@ -164,7 +164,6 @@
};
#endif
#ifdef CONFIG_OPTEE
tee: tee {
description = "OP-TEE";
type = "tee";
@@ -176,9 +175,9 @@
tee-os {
filename = "tee.bin";
optional;
};
};
#endif
binman_fip: fip {
arch = "arm64";
@@ -208,11 +207,7 @@
fdt = "fdt-SEQ";
firmware = "uboot";
#ifndef CONFIG_ARMV8_PSCI
#ifdef CONFIG_OPTEE
loadables = "atf", "tee";
#else
loadables = "atf";
#endif
#endif
};
};

View File

@@ -1,646 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2018-2019 NXP
*/
#ifndef __DTS_IMX8MN_PINFUNC_H
#define __DTS_IMX8MN_PINFUNC_H
/*
* The pin function ID is a tuple of
* <mux_reg conf_reg input_reg mux_mode input_val>
*/
#define MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0
#define MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3
#define MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0
#define MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3
#define MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
#define MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0
#define MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
#define MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
#define MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
#define MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
#define MX8MN_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x000 0x5 0x0
#define MX8MN_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0x0
#define MX8MN_IOMUXC_GPIO1_IO02_GPIO1_IO2 0x030 0x298 0x000 0x0 0x0
#define MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x030 0x298 0x000 0x1 0x0
#define MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x030 0x298 0x000 0x5 0x0
#define MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x034 0x29C 0x000 0x0 0x0
#define MX8MN_IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x034 0x29C 0x000 0x1 0x0
#define MX8MN_IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x034 0x29C 0x000 0x5 0x0
#define MX8MN_IOMUXC_GPIO1_IO03_ANAMIX_XTAL_OK 0x034 0x29C 0x000 0x6 0x0
#define MX8MN_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x038 0x2A0 0x000 0x0 0x0
#define MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x038 0x2A0 0x000 0x1 0x0
#define MX8MN_IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x038 0x2A0 0x000 0x5 0x0
#define MX8MN_IOMUXC_GPIO1_IO04_ANAMIX_XTAL_OK_LV 0x038 0x2A0 0x000 0x6 0x0
#define MX8MN_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x03C 0x2A4 0x000 0x0 0x0
#define MX8MN_IOMUXC_GPIO1_IO05_M4_NMI 0x03C 0x2A4 0x000 0x1 0x0
#define MX8MN_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_PMIC_READY 0x03C 0x2A4 0x4BC 0x5 0x0
#define MX8MN_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_INT_BOOT 0x03C 0x2A4 0x000 0x6 0x0
#define MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x040 0x2A8 0x000 0x0 0x0
#define MX8MN_IOMUXC_GPIO1_IO06_ENET1_MDC 0x040 0x2A8 0x000 0x1 0x0
#define MX8MN_IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x040 0x2A8 0x000 0x5 0x0
#define MX8MN_IOMUXC_GPIO1_IO06_CCMSRCGPCMIX_EXT_CLK3 0x040 0x2A8 0x000 0x6 0x0
#define MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x044 0x2AC 0x000 0x0 0x0
#define MX8MN_IOMUXC_GPIO1_IO07_ENET1_MDIO 0x044 0x2AC 0x4C0 0x1 0x0
#define MX8MN_IOMUXC_GPIO1_IO07_USDHC1_WP 0x044 0x2AC 0x000 0x5 0x0
#define MX8MN_IOMUXC_GPIO1_IO07_CCMSRCGPCMIX_EXT_CLK4 0x044 0x2AC 0x000 0x6 0x0
#define MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x048 0x2B0 0x000 0x0 0x0
#define MX8MN_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x048 0x2B0 0x000 0x1 0x0
#define MX8MN_IOMUXC_GPIO1_IO08_PWM1_OUT 0x048 0x2B0 0x000 0x2 0x0
#define MX8MN_IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x048 0x2B0 0x000 0x5 0x0
#define MX8MN_IOMUXC_GPIO1_IO08_CCMSRCGPCMIX_WAIT 0x048 0x2B0 0x000 0x6 0x0
#define MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x04C 0x2B4 0x000 0x0 0x0
#define MX8MN_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x04C 0x2B4 0x000 0x1 0x0
#define MX8MN_IOMUXC_GPIO1_IO09_PWM2_OUT 0x04C 0x2B4 0x000 0x2 0x0
#define MX8MN_IOMUXC_GPIO1_IO09_USDHC3_RESET_B 0x04C 0x2B4 0x000 0x4 0x0
#define MX8MN_IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x04C 0x2B4 0x000 0x5 0x0
#define MX8MN_IOMUXC_GPIO1_IO09_CCMSRCGPCMIX_STOP 0x04C 0x2B4 0x000 0x6 0x0
#define MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x050 0x2B8 0x000 0x0 0x0
#define MX8MN_IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x050 0x2B8 0x000 0x1 0x0
#define MX8MN_IOMUXC_GPIO1_IO10_PWM3_OUT 0x050 0x2B8 0x000 0x2 0x0
#define MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x054 0x2BC 0x000 0x0 0x0
#define MX8MN_IOMUXC_GPIO1_IO11_PWM2_OUT 0x054 0x2BC 0x000 0x1 0x0
#define MX8MN_IOMUXC_GPIO1_IO11_USDHC3_VSELECT 0x054 0x2BC 0x000 0x4 0x0
#define MX8MN_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_PMIC_READY 0x054 0x2BC 0x4BC 0x5 0x1
#define MX8MN_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_OUT0 0x054 0x2BC 0x000 0x6 0x0
#define MX8MN_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x058 0x2C0 0x000 0x0 0x0
#define MX8MN_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x058 0x2C0 0x000 0x1 0x0
#define MX8MN_IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x058 0x2C0 0x000 0x5 0x0
#define MX8MN_IOMUXC_GPIO1_IO12_CCMSRCGPCMIX_OUT1 0x058 0x2C0 0x000 0x6 0x0
#define MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x05C 0x2C4 0x000 0x0 0x0
#define MX8MN_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x05C 0x2C4 0x000 0x1 0x0
#define MX8MN_IOMUXC_GPIO1_IO13_PWM2_OUT 0x05C 0x2C4 0x000 0x5 0x0
#define MX8MN_IOMUXC_GPIO1_IO13_CCMSRCGPCMIX_OUT2 0x05C 0x2C4 0x000 0x6 0x0
#define MX8MN_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x060 0x2C8 0x000 0x0 0x0
#define MX8MN_IOMUXC_GPIO1_IO14_USDHC3_CD_B 0x060 0x2C8 0x598 0x4 0x2
#define MX8MN_IOMUXC_GPIO1_IO14_PWM3_OUT 0x060 0x2C8 0x000 0x5 0x0
#define MX8MN_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x060 0x2C8 0x000 0x6 0x0
#define MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x064 0x2CC 0x000 0x0 0x0
#define MX8MN_IOMUXC_GPIO1_IO15_USDHC3_WP 0x064 0x2CC 0x5B8 0x4 0x2
#define MX8MN_IOMUXC_GPIO1_IO15_PWM4_OUT 0x064 0x2CC 0x000 0x5 0x0
#define MX8MN_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x064 0x2CC 0x000 0x6 0x0
#define MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x068 0x2D0 0x000 0x0 0x0
#define MX8MN_IOMUXC_ENET_MDC_SAI6_TX_DATA0 0x068 0x2D0 0x000 0x2 0x0
#define MX8MN_IOMUXC_ENET_MDC_PDM_BIT_STREAM3 0x068 0x2D0 0x540 0x3 0x1
#define MX8MN_IOMUXC_ENET_MDC_SPDIF1_OUT 0x068 0x2D0 0x000 0x4 0x0
#define MX8MN_IOMUXC_ENET_MDC_GPIO1_IO16 0x068 0x2D0 0x000 0x5 0x0
#define MX8MN_IOMUXC_ENET_MDC_USDHC3_STROBE 0x068 0x2D0 0x59C 0x6 0x1
#define MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x06C 0x2D4 0x4C0 0x0 0x1
#define MX8MN_IOMUXC_ENET_MDIO_SAI6_TX_SYNC 0x06C 0x2D4 0x000 0x2 0x0
#define MX8MN_IOMUXC_ENET_MDIO_PDM_BIT_STREAM2 0x06C 0x2D4 0x53C 0x3 0x1
#define MX8MN_IOMUXC_ENET_MDIO_SPDIF1_IN 0x06C 0x2D4 0x5CC 0x4 0x1
#define MX8MN_IOMUXC_ENET_MDIO_GPIO1_IO17 0x06C 0x2D4 0x000 0x5 0x0
#define MX8MN_IOMUXC_ENET_MDIO_USDHC3_DATA5 0x06C 0x2D4 0x550 0x6 0x1
#define MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x070 0x2D8 0x000 0x0 0x0
#define MX8MN_IOMUXC_ENET_TD3_SAI6_TX_BCLK 0x070 0x2D8 0x000 0x2 0x0
#define MX8MN_IOMUXC_ENET_TD3_PDM_BIT_STREAM1 0x070 0x2D8 0x538 0x3 0x1
#define MX8MN_IOMUXC_ENET_TD3_SPDIF1_EXT_CLK 0x070 0x2D8 0x568 0x4 0x1
#define MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18 0x070 0x2D8 0x000 0x5 0x0
#define MX8MN_IOMUXC_ENET_TD3_USDHC3_DATA6 0x070 0x2D8 0x584 0x6 0x1
#define MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x074 0x2DC 0x000 0x0 0x0
#define MX8MN_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x074 0x2DC 0x5A4 0x1 0x0
#define MX8MN_IOMUXC_ENET_TD2_CCMSRCGPCMIX_ENET_REF_CLK_ROOT 0x074 0x2DC 0x5A4 0x1 0x0
#define MX8MN_IOMUXC_ENET_TD2_SAI6_RX_DATA0 0x074 0x2DC 0x000 0x2 0x0
#define MX8MN_IOMUXC_ENET_TD2_PDM_BIT_STREAM3 0x074 0x2DC 0x540 0x3 0x2
#define MX8MN_IOMUXC_ENET_TD2_GPIO1_IO19 0x074 0x2DC 0x000 0x5 0x0
#define MX8MN_IOMUXC_ENET_TD2_USDHC3_DATA7 0x074 0x2DC 0x54C 0x6 0x1
#define MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x078 0x2E0 0x000 0x0 0x0
#define MX8MN_IOMUXC_ENET_TD1_SAI6_RX_SYNC 0x078 0x2E0 0x000 0x2 0x0
#define MX8MN_IOMUXC_ENET_TD1_PDM_BIT_STREAM2 0x078 0x2E0 0x53C 0x3 0x2
#define MX8MN_IOMUXC_ENET_TD1_GPIO1_IO20 0x078 0x2E0 0x000 0x5 0x0
#define MX8MN_IOMUXC_ENET_TD1_USDHC3_CD_B 0x078 0x2E0 0x598 0x6 0x3
#define MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x07C 0x2E4 0x000 0x0 0x0
#define MX8MN_IOMUXC_ENET_TD0_SAI6_RX_BCLK 0x07C 0x2E4 0x000 0x2 0x0
#define MX8MN_IOMUXC_ENET_TD0_PDM_BIT_STREAM1 0x07C 0x2E4 0x538 0x3 0x2
#define MX8MN_IOMUXC_ENET_TD0_GPIO1_IO21 0x07C 0x2E4 0x000 0x5 0x0
#define MX8MN_IOMUXC_ENET_TD0_USDHC3_WP 0x07C 0x2E4 0x5B8 0x6 0x3
#define MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x080 0x2E8 0x000 0x0 0x0
#define MX8MN_IOMUXC_ENET_TX_CTL_SAI6_MCLK 0x080 0x2E8 0x000 0x2 0x0
#define MX8MN_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x080 0x2E8 0x000 0x5 0x0
#define MX8MN_IOMUXC_ENET_TX_CTL_USDHC3_DATA0 0x080 0x2E8 0x5B4 0x6 0x1
#define MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x084 0x2EC 0x000 0x0 0x0
#define MX8MN_IOMUXC_ENET_TXC_ENET1_TX_ER 0x084 0x2EC 0x000 0x1 0x0
#define MX8MN_IOMUXC_ENET_TXC_SAI7_TX_DATA0 0x084 0x2EC 0x000 0x2 0x0
#define MX8MN_IOMUXC_ENET_TXC_GPIO1_IO23 0x084 0x2EC 0x000 0x5 0x0
#define MX8MN_IOMUXC_ENET_TXC_USDHC3_DATA1 0x084 0x2EC 0x5B0 0x6 0x1
#define MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x088 0x2F0 0x574 0x0 0x0
#define MX8MN_IOMUXC_ENET_RX_CTL_SAI7_TX_SYNC 0x088 0x2F0 0x000 0x2 0x0
#define MX8MN_IOMUXC_ENET_RX_CTL_PDM_BIT_STREAM3 0x088 0x2F0 0x540 0x3 0x3
#define MX8MN_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x088 0x2F0 0x000 0x5 0x0
#define MX8MN_IOMUXC_ENET_RX_CTL_USDHC3_DATA2 0x088 0x2F0 0x5E4 0x6 0x1
#define MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x08C 0x2F4 0x000 0x0 0x0
#define MX8MN_IOMUXC_ENET_RXC_ENET1_RX_ER 0x08C 0x2F4 0x5C8 0x1 0x0
#define MX8MN_IOMUXC_ENET_RXC_SAI7_TX_BCLK 0x08C 0x2F4 0x000 0x2 0x0
#define MX8MN_IOMUXC_ENET_RXC_PDM_BIT_STREAM2 0x08C 0x2F4 0x53C 0x3 0x3
#define MX8MN_IOMUXC_ENET_RXC_GPIO1_IO25 0x08C 0x2F4 0x000 0x5 0x0
#define MX8MN_IOMUXC_ENET_RXC_USDHC3_DATA3 0x08C 0x2F4 0x5E0 0x6 0x1
#define MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x090 0x2F8 0x57C 0x0 0x0
#define MX8MN_IOMUXC_ENET_RD0_SAI7_RX_DATA0 0x090 0x2F8 0x000 0x2 0x0
#define MX8MN_IOMUXC_ENET_RD0_PDM_BIT_STREAM1 0x090 0x2F8 0x538 0x3 0x3
#define MX8MN_IOMUXC_ENET_RD0_GPIO1_IO26 0x090 0x2F8 0x000 0x5 0x0
#define MX8MN_IOMUXC_ENET_RD0_USDHC3_DATA4 0x090 0x2F8 0x558 0x6 0x1
#define MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x094 0x2FC 0x554 0x0 0x0
#define MX8MN_IOMUXC_ENET_RD1_SAI7_RX_SYNC 0x094 0x2FC 0x000 0x2 0x0
#define MX8MN_IOMUXC_ENET_RD1_PDM_BIT_STREAM0 0x094 0x2FC 0x534 0x3 0x1
#define MX8MN_IOMUXC_ENET_RD1_GPIO1_IO27 0x094 0x2FC 0x000 0x5 0x0
#define MX8MN_IOMUXC_ENET_RD1_USDHC3_RESET_B 0x094 0x2FC 0x000 0x6 0x0
#define MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x098 0x300 0x000 0x0 0x0
#define MX8MN_IOMUXC_ENET_RD2_SAI7_RX_BCLK 0x098 0x300 0x000 0x2 0x0
#define MX8MN_IOMUXC_ENET_RD2_PDM_CLK 0x098 0x300 0x000 0x3 0x0
#define MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28 0x098 0x300 0x000 0x5 0x0
#define MX8MN_IOMUXC_ENET_RD2_USDHC3_CLK 0x098 0x300 0x5A0 0x6 0x1
#define MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x09C 0x304 0x000 0x0 0x0
#define MX8MN_IOMUXC_ENET_RD3_SAI7_MCLK 0x09C 0x304 0x000 0x2 0x0
#define MX8MN_IOMUXC_ENET_RD3_SPDIF1_IN 0x09C 0x304 0x5CC 0x3 0x5
#define MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29 0x09C 0x304 0x000 0x5 0x0
#define MX8MN_IOMUXC_ENET_RD3_USDHC3_CMD 0x09C 0x304 0x5DC 0x6 0x1
#define MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x0A0 0x308 0x000 0x0 0x0
#define MX8MN_IOMUXC_SD1_CLK_ENET1_MDC 0x0A0 0x308 0x000 0x1 0x0
#define MX8MN_IOMUXC_SD1_CLK_UART1_DCE_TX 0x0A0 0x308 0x000 0x4 0x0
#define MX8MN_IOMUXC_SD1_CLK_UART1_DTE_RX 0x0A0 0x308 0x4F4 0x4 0x4
#define MX8MN_IOMUXC_SD1_CLK_GPIO2_IO0 0x0A0 0x308 0x000 0x5 0x0
#define MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x0A4 0x30C 0x000 0x0 0x0
#define MX8MN_IOMUXC_SD1_CMD_ENET1_MDIO 0x0A4 0x30C 0x4C0 0x1 0x3
#define MX8MN_IOMUXC_SD1_CMD_UART1_DCE_RX 0x0A4 0x30C 0x4F4 0x4 0x5
#define MX8MN_IOMUXC_SD1_CMD_UART1_DTE_TX 0x0A4 0x30C 0x000 0x4 0x0
#define MX8MN_IOMUXC_SD1_CMD_GPIO2_IO1 0x0A4 0x30C 0x000 0x5 0x0
#define MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0A8 0x310 0x000 0x0 0x0
#define MX8MN_IOMUXC_SD1_DATA0_ENET1_RGMII_TD1 0x0A8 0x310 0x000 0x1 0x0
#define MX8MN_IOMUXC_SD1_DATA0_UART1_DCE_RTS_B 0x0A8 0x310 0x4F0 0x4 0x4
#define MX8MN_IOMUXC_SD1_DATA0_UART1_DTE_CTS_B 0x0A8 0x310 0x000 0x4 0x0
#define MX8MN_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x310 0x000 0x5 0x0
#define MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0AC 0x314 0x000 0x0 0x0
#define MX8MN_IOMUXC_SD1_DATA1_ENET1_RGMII_TD0 0x0AC 0x314 0x000 0x1 0x0
#define MX8MN_IOMUXC_SD1_DATA1_UART1_DCE_CTS_B 0x0AC 0x314 0x000 0x4 0x0
#define MX8MN_IOMUXC_SD1_DATA1_UART1_DTE_RTS_B 0x0AC 0x314 0x4F0 0x4 0x5
#define MX8MN_IOMUXC_SD1_DATA1_GPIO2_IO3 0x0AC 0x314 0x000 0x5 0x0
#define MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0B0 0x318 0x000 0x0 0x0
#define MX8MN_IOMUXC_SD1_DATA2_ENET1_RGMII_RD0 0x0B0 0x318 0x57C 0x1 0x1
#define MX8MN_IOMUXC_SD1_DATA2_UART2_DCE_TX 0x0B0 0x318 0x000 0x4 0x0
#define MX8MN_IOMUXC_SD1_DATA2_UART2_DTE_RX 0x0B0 0x318 0x4FC 0x4 0x4
#define MX8MN_IOMUXC_SD1_DATA2_GPIO2_IO4 0x0B0 0x318 0x000 0x5 0x0
#define MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0B4 0x31C 0x000 0x0 0x0
#define MX8MN_IOMUXC_SD1_DATA3_ENET1_RGMII_RD1 0x0B4 0x31C 0x554 0x1 0x1
#define MX8MN_IOMUXC_SD1_DATA3_UART2_DCE_RX 0x0B4 0x31C 0x4FC 0x4 0x5
#define MX8MN_IOMUXC_SD1_DATA3_UART2_DTE_TX 0x0B4 0x31C 0x000 0x4 0x0
#define MX8MN_IOMUXC_SD1_DATA3_GPIO2_IO5 0x0B4 0x31C 0x000 0x5 0x0
#define MX8MN_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0B8 0x320 0x000 0x0 0x0
#define MX8MN_IOMUXC_SD1_DATA4_ENET1_RGMII_TX_CTL 0x0B8 0x320 0x000 0x1 0x0
#define MX8MN_IOMUXC_SD1_DATA4_I2C1_SCL 0x0B8 0x320 0x55C 0x3 0x1
#define MX8MN_IOMUXC_SD1_DATA4_UART2_DCE_RTS_B 0x0B8 0x320 0x4F8 0x4 0x4
#define MX8MN_IOMUXC_SD1_DATA4_UART2_DTE_CTS_B 0x0B8 0x320 0x000 0x4 0x0
#define MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6 0x0B8 0x320 0x000 0x5 0x0
#define MX8MN_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0BC 0x324 0x000 0x0 0x0
#define MX8MN_IOMUXC_SD1_DATA5_ENET1_TX_ER 0x0BC 0x324 0x000 0x1 0x0
#define MX8MN_IOMUXC_SD1_DATA5_I2C1_SDA 0x0BC 0x324 0x56C 0x3 0x1
#define MX8MN_IOMUXC_SD1_DATA5_UART2_DCE_CTS_B 0x0BC 0x324 0x000 0x4 0x0
#define MX8MN_IOMUXC_SD1_DATA5_UART2_DTE_RTS_B 0x0BC 0x324 0x4F8 0x4 0x5
#define MX8MN_IOMUXC_SD1_DATA5_GPIO2_IO7 0x0BC 0x324 0x000 0x5 0x0
#define MX8MN_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0C0 0x328 0x000 0x0 0x0
#define MX8MN_IOMUXC_SD1_DATA6_ENET1_RGMII_RX_CTL 0x0C0 0x328 0x574 0x1 0x1
#define MX8MN_IOMUXC_SD1_DATA6_I2C2_SCL 0x0C0 0x328 0x5D0 0x3 0x1
#define MX8MN_IOMUXC_SD1_DATA6_UART3_DCE_TX 0x0C0 0x328 0x000 0x4 0x0
#define MX8MN_IOMUXC_SD1_DATA6_UART3_DTE_RX 0x0C0 0x328 0x504 0x4 0x4
#define MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x0C0 0x328 0x000 0x5 0x0
#define MX8MN_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0C4 0x32C 0x000 0x0 0x0
#define MX8MN_IOMUXC_SD1_DATA7_ENET1_RX_ER 0x0C4 0x32C 0x5C8 0x1 0x1
#define MX8MN_IOMUXC_SD1_DATA7_I2C2_SDA 0x0C4 0x32C 0x560 0x3 0x1
#define MX8MN_IOMUXC_SD1_DATA7_UART3_DCE_RX 0x0C4 0x32C 0x504 0x4 0x5
#define MX8MN_IOMUXC_SD1_DATA7_UART3_DTE_TX 0x0C4 0x32C 0x000 0x4 0x0
#define MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x0C4 0x32C 0x000 0x5 0x0
#define MX8MN_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x0C8 0x330 0x000 0x0 0x0
#define MX8MN_IOMUXC_SD1_RESET_B_ENET1_TX_CLK 0x0C8 0x330 0x5A4 0x1 0x1
#define MX8MN_IOMUXC_SD1_RESET_B_CCMSRCGPCMIX_ENET_REF_CLK_ROOT 0x0C8 0x330 0x5A4 0x1 0x0
#define MX8MN_IOMUXC_SD1_RESET_B_I2C3_SCL 0x0C8 0x330 0x588 0x3 0x1
#define MX8MN_IOMUXC_SD1_RESET_B_UART3_DCE_RTS_B 0x0C8 0x330 0x500 0x4 0x2
#define MX8MN_IOMUXC_SD1_RESET_B_UART3_DTE_CTS_B 0x0C8 0x330 0x000 0x4 0x0
#define MX8MN_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x0C8 0x330 0x000 0x5 0x0
#define MX8MN_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x0CC 0x334 0x000 0x0 0x0
#define MX8MN_IOMUXC_SD1_STROBE_I2C3_SDA 0x0CC 0x334 0x5BC 0x3 0x1
#define MX8MN_IOMUXC_SD1_STROBE_UART3_DCE_CTS_B 0x0CC 0x334 0x000 0x4 0x0
#define MX8MN_IOMUXC_SD1_STROBE_UART3_DTE_RTS_B 0x0CC 0x334 0x500 0x4 0x3
#define MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 0x0CC 0x334 0x000 0x5 0x0
#define MX8MN_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0D0 0x338 0x000 0x0 0x0
#define MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0D0 0x338 0x000 0x5 0x0
#define MX8MN_IOMUXC_SD2_CD_B_CCMSRCGPCMIX_TESTER_ACK 0x0D0 0x338 0x000 0x6 0x0
#define MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x0D4 0x33C 0x000 0x0 0x0
#define MX8MN_IOMUXC_SD2_CLK_SAI5_RX_SYNC 0x0D4 0x33C 0x4E4 0x1 0x1
#define MX8MN_IOMUXC_SD2_CLK_ECSPI2_SCLK 0x0D4 0x33C 0x580 0x2 0x1
#define MX8MN_IOMUXC_SD2_CLK_UART4_DCE_RX 0x0D4 0x33C 0x50C 0x3 0x4
#define MX8MN_IOMUXC_SD2_CLK_UART4_DTE_TX 0x0D4 0x33C 0x000 0x3 0x0
#define MX8MN_IOMUXC_SD2_CLK_SAI5_MCLK 0x0D4 0x33C 0x594 0x4 0x1
#define MX8MN_IOMUXC_SD2_CLK_GPIO2_IO13 0x0D4 0x33C 0x000 0x5 0x0
#define MX8MN_IOMUXC_SD2_CLK_CCMSRCGPCMIX_OBSERVE0 0x0D4 0x33C 0x000 0x6 0x0
#define MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x0D8 0x340 0x000 0x0 0x0
#define MX8MN_IOMUXC_SD2_CMD_SAI5_RX_BCLK 0x0D8 0x340 0x4D0 0x1 0x1
#define MX8MN_IOMUXC_SD2_CMD_ECSPI2_MOSI 0x0D8 0x340 0x590 0x2 0x1
#define MX8MN_IOMUXC_SD2_CMD_UART4_DCE_TX 0x0D8 0x340 0x000 0x3 0x0
#define MX8MN_IOMUXC_SD2_CMD_UART4_DTE_RX 0x0D8 0x340 0x50C 0x3 0x5
#define MX8MN_IOMUXC_SD2_CMD_PDM_CLK 0x0D8 0x340 0x000 0x4 0x0
#define MX8MN_IOMUXC_SD2_CMD_GPIO2_IO14 0x0D8 0x340 0x000 0x5 0x0
#define MX8MN_IOMUXC_SD2_CMD_CCMSRCGPCMIX_OBSERVE1 0x0D8 0x340 0x000 0x6 0x0
#define MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0DC 0x344 0x000 0x0 0x0
#define MX8MN_IOMUXC_SD2_DATA0_SAI5_RX_DATA0 0x0DC 0x344 0x4D4 0x1 0x1
#define MX8MN_IOMUXC_SD2_DATA0_I2C4_SDA 0x0DC 0x344 0x58C 0x2 0x1
#define MX8MN_IOMUXC_SD2_DATA0_UART2_DCE_RX 0x0DC 0x344 0x4FC 0x3 0x6
#define MX8MN_IOMUXC_SD2_DATA0_UART2_DTE_TX 0x0DC 0x344 0x000 0x3 0x0
#define MX8MN_IOMUXC_SD2_DATA0_PDM_BIT_STREAM0 0x0DC 0x344 0x534 0x4 0x2
#define MX8MN_IOMUXC_SD2_DATA0_GPIO2_IO15 0x0DC 0x344 0x000 0x5 0x0
#define MX8MN_IOMUXC_SD2_DATA0_CCMSRCGPCMIX_OBSERVE2 0x0DC 0x344 0x000 0x6 0x0
#define MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0E0 0x348 0x000 0x0 0x0
#define MX8MN_IOMUXC_SD2_DATA1_SAI5_TX_SYNC 0x0E0 0x348 0x4EC 0x1 0x1
#define MX8MN_IOMUXC_SD2_DATA1_I2C4_SCL 0x0E0 0x348 0x5D4 0x2 0x1
#define MX8MN_IOMUXC_SD2_DATA1_UART2_DCE_TX 0x0E0 0x348 0x000 0x3 0x0
#define MX8MN_IOMUXC_SD2_DATA1_UART2_DTE_RX 0x0E0 0x348 0x4FC 0x3 0x7
#define MX8MN_IOMUXC_SD2_DATA1_PDM_BIT_STREAM1 0x0E0 0x348 0x538 0x4 0x4
#define MX8MN_IOMUXC_SD2_DATA1_GPIO2_IO16 0x0E0 0x348 0x000 0x5 0x0
#define MX8MN_IOMUXC_SD2_DATA1_CCMSRCGPCMIX_WAIT 0x0E0 0x348 0x000 0x6 0x0
#define MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0E4 0x34C 0x000 0x0 0x0
#define MX8MN_IOMUXC_SD2_DATA2_SAI5_TX_BCLK 0x0E4 0x34C 0x4E8 0x1 0x1
#define MX8MN_IOMUXC_SD2_DATA2_ECSPI2_SS0 0x0E4 0x34C 0x570 0x2 0x2
#define MX8MN_IOMUXC_SD2_DATA2_SPDIF1_OUT 0x0E4 0x34C 0x000 0x3 0x0
#define MX8MN_IOMUXC_SD2_DATA2_PDM_BIT_STREAM2 0x0E4 0x34C 0x53C 0x4 0x4
#define MX8MN_IOMUXC_SD2_DATA2_GPIO2_IO17 0x0E4 0x34C 0x000 0x5 0x0
#define MX8MN_IOMUXC_SD2_DATA2_CCMSRCGPCMIX_STOP 0x0E4 0x34C 0x000 0x6 0x0
#define MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0E8 0x350 0x000 0x0 0x0
#define MX8MN_IOMUXC_SD2_DATA3_SAI5_TX_DATA0 0x0E8 0x350 0x000 0x1 0x0
#define MX8MN_IOMUXC_SD2_DATA3_ECSPI2_MISO 0x0E8 0x350 0x578 0x2 0x1
#define MX8MN_IOMUXC_SD2_DATA3_SPDIF1_IN 0x0E8 0x350 0x5CC 0x3 0x2
#define MX8MN_IOMUXC_SD2_DATA3_PDM_BIT_STREAM3 0x0E8 0x350 0x540 0x4 0x4
#define MX8MN_IOMUXC_SD2_DATA3_GPIO2_IO18 0x0E8 0x350 0x000 0x5 0x0
#define MX8MN_IOMUXC_SD2_DATA3_CCMSRCGPCMIX_EARLY_RESET 0x0E8 0x350 0x000 0x6 0x0
#define MX8MN_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x0EC 0x354 0x000 0x0 0x0
#define MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x0EC 0x354 0x000 0x5 0x0
#define MX8MN_IOMUXC_SD2_RESET_B_CCMSRCGPCMIX_SYSTEM_RESET 0x0EC 0x354 0x000 0x6 0x0
#define MX8MN_IOMUXC_SD2_WP_USDHC2_WP 0x0F0 0x358 0x000 0x0 0x0
#define MX8MN_IOMUXC_SD2_WP_GPIO2_IO20 0x0F0 0x358 0x000 0x5 0x0
#define MX8MN_IOMUXC_SD2_WP_CORESIGHT_EVENTI 0x0F0 0x358 0x000 0x6 0x0
#define MX8MN_IOMUXC_NAND_ALE_RAWNAND_ALE 0x0F4 0x35C 0x000 0x0 0x0
#define MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x0F4 0x35C 0x000 0x1 0x0
#define MX8MN_IOMUXC_NAND_ALE_PDM_BIT_STREAM0 0x0F4 0x35C 0x534 0x3 0x3
#define MX8MN_IOMUXC_NAND_ALE_UART3_DCE_RX 0x0F4 0x35C 0x504 0x4 0x6
#define MX8MN_IOMUXC_NAND_ALE_UART3_DTE_TX 0x0F4 0x35C 0x000 0x4 0x0
#define MX8MN_IOMUXC_NAND_ALE_GPIO3_IO0 0x0F4 0x35C 0x000 0x5 0x0
#define MX8MN_IOMUXC_NAND_ALE_CORESIGHT_TRACE_CLK 0x0F4 0x35C 0x000 0x6 0x0
#define MX8MN_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x0F8 0x360 0x000 0x0 0x0
#define MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x0F8 0x360 0x000 0x1 0x0
#define MX8MN_IOMUXC_NAND_CE0_B_PDM_BIT_STREAM1 0x0F8 0x360 0x538 0x3 0x5
#define MX8MN_IOMUXC_NAND_CE0_B_UART3_DCE_TX 0x0F8 0x360 0x000 0x4 0x0
#define MX8MN_IOMUXC_NAND_CE0_B_UART3_DTE_RX 0x0F8 0x360 0x504 0x4 0x7
#define MX8MN_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x0F8 0x360 0x000 0x5 0x0
#define MX8MN_IOMUXC_NAND_CE0_B_CORESIGHT_TRACE_CTL 0x0F8 0x360 0x000 0x6 0x0
#define MX8MN_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x0FC 0x364 0x000 0x0 0x0
#define MX8MN_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x0FC 0x364 0x000 0x1 0x0
#define MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x0FC 0x364 0x59C 0x2 0x0
#define MX8MN_IOMUXC_NAND_CE1_B_PDM_BIT_STREAM0 0x0FC 0x364 0x534 0x3 0x4
#define MX8MN_IOMUXC_NAND_CE1_B_I2C4_SCL 0x0FC 0x364 0x5D4 0x4 0x2
#define MX8MN_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x0FC 0x364 0x000 0x5 0x0
#define MX8MN_IOMUXC_NAND_CE1_B_CORESIGHT_TRACE0 0x0FC 0x364 0x000 0x6 0x0
#define MX8MN_IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x100 0x368 0x000 0x0 0x0
#define MX8MN_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x100 0x368 0x000 0x1 0x0
#define MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x100 0x368 0x550 0x2 0x0
#define MX8MN_IOMUXC_NAND_CE2_B_PDM_BIT_STREAM1 0x100 0x368 0x538 0x3 0x6
#define MX8MN_IOMUXC_NAND_CE2_B_I2C4_SDA 0x100 0x368 0x58C 0x4 0x2
#define MX8MN_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x100 0x368 0x000 0x5 0x0
#define MX8MN_IOMUXC_NAND_CE2_B_CORESIGHT_TRACE1 0x100 0x368 0x000 0x6 0x0
#define MX8MN_IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x104 0x36C 0x000 0x0 0x0
#define MX8MN_IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x104 0x36C 0x000 0x1 0x0
#define MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x104 0x36C 0x584 0x2 0x0
#define MX8MN_IOMUXC_NAND_CE3_B_PDM_BIT_STREAM2 0x104 0x36C 0x53C 0x3 0x5
#define MX8MN_IOMUXC_NAND_CE3_B_I2C3_SDA 0x104 0x36C 0x5BC 0x4 0x2
#define MX8MN_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x104 0x36C 0x000 0x5 0x0
#define MX8MN_IOMUXC_NAND_CE3_B_CORESIGHT_TRACE2 0x104 0x36C 0x000 0x6 0x0
#define MX8MN_IOMUXC_NAND_CLE_RAWNAND_CLE 0x108 0x370 0x000 0x0 0x0
#define MX8MN_IOMUXC_NAND_CLE_QSPI_B_SCLK 0x108 0x370 0x000 0x1 0x0
#define MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x108 0x370 0x54C 0x2 0x0
#define MX8MN_IOMUXC_NAND_CLE_GPIO3_IO5 0x108 0x370 0x000 0x5 0x0
#define MX8MN_IOMUXC_NAND_CLE_CORESIGHT_TRACE3 0x108 0x370 0x000 0x6 0x0
#define MX8MN_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x10C 0x374 0x000 0x0 0x0
#define MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x10C 0x374 0x000 0x1 0x0
#define MX8MN_IOMUXC_NAND_DATA00_PDM_BIT_STREAM2 0x10C 0x374 0x53C 0x3 0x6
#define MX8MN_IOMUXC_NAND_DATA00_UART4_DCE_RX 0x10C 0x374 0x50C 0x4 0x6
#define MX8MN_IOMUXC_NAND_DATA00_UART4_DTE_TX 0x10C 0x374 0x000 0x4 0x0
#define MX8MN_IOMUXC_NAND_DATA00_GPIO3_IO6 0x10C 0x374 0x000 0x5 0x0
#define MX8MN_IOMUXC_NAND_DATA00_CORESIGHT_TRACE4 0x10C 0x374 0x000 0x6 0x0
#define MX8MN_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x110 0x378 0x000 0x0 0x0
#define MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x110 0x378 0x000 0x1 0x0
#define MX8MN_IOMUXC_NAND_DATA01_PDM_BIT_STREAM3 0x110 0x378 0x540 0x3 0x5
#define MX8MN_IOMUXC_NAND_DATA01_UART4_DCE_TX 0x110 0x378 0x000 0x4 0x0
#define MX8MN_IOMUXC_NAND_DATA01_UART4_DTE_RX 0x110 0x378 0x50C 0x4 0x7
#define MX8MN_IOMUXC_NAND_DATA01_GPIO3_IO7 0x110 0x378 0x000 0x5 0x0
#define MX8MN_IOMUXC_NAND_DATA01_CORESIGHT_TRACE5 0x110 0x378 0x000 0x6 0x0
#define MX8MN_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x114 0x37C 0x000 0x0 0x0
#define MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x114 0x37C 0x000 0x1 0x0
#define MX8MN_IOMUXC_NAND_DATA02_USDHC3_CD_B 0x114 0x37C 0x598 0x2 0x0
#define MX8MN_IOMUXC_NAND_DATA02_I2C4_SDA 0x114 0x37C 0x58C 0x4 0x3
#define MX8MN_IOMUXC_NAND_DATA02_GPIO3_IO8 0x114 0x37C 0x000 0x5 0x0
#define MX8MN_IOMUXC_NAND_DATA02_CORESIGHT_TRACE6 0x114 0x37C 0x000 0x6 0x0
#define MX8MN_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x118 0x380 0x000 0x0 0x0
#define MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x118 0x380 0x000 0x1 0x0
#define MX8MN_IOMUXC_NAND_DATA03_USDHC3_WP 0x118 0x380 0x5B8 0x2 0x0
#define MX8MN_IOMUXC_NAND_DATA03_GPIO3_IO9 0x118 0x380 0x000 0x5 0x0
#define MX8MN_IOMUXC_NAND_DATA03_CORESIGHT_TRACE7 0x118 0x380 0x000 0x6 0x0
#define MX8MN_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x11C 0x384 0x000 0x0 0x0
#define MX8MN_IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x11C 0x384 0x000 0x1 0x0
#define MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x11C 0x384 0x5B4 0x2 0x0
#define MX8MN_IOMUXC_NAND_DATA04_GPIO3_IO10 0x11C 0x384 0x000 0x5 0x0
#define MX8MN_IOMUXC_NAND_DATA04_CORESIGHT_TRACE8 0x11C 0x384 0x000 0x6 0x0
#define MX8MN_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x120 0x388 0x000 0x0 0x0
#define MX8MN_IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x120 0x388 0x000 0x1 0x0
#define MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x120 0x388 0x5B0 0x2 0x0
#define MX8MN_IOMUXC_NAND_DATA05_GPIO3_IO11 0x120 0x388 0x000 0x5 0x0
#define MX8MN_IOMUXC_NAND_DATA05_CORESIGHT_TRACE9 0x120 0x388 0x000 0x6 0x0
#define MX8MN_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x124 0x38C 0x000 0x0 0x0
#define MX8MN_IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x124 0x38C 0x000 0x1 0x0
#define MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x124 0x38C 0x5E4 0x2 0x0
#define MX8MN_IOMUXC_NAND_DATA06_GPIO3_IO12 0x124 0x38C 0x000 0x5 0x0
#define MX8MN_IOMUXC_NAND_DATA06_CORESIGHT_TRACE10 0x124 0x38C 0x000 0x6 0x0
#define MX8MN_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x128 0x390 0x000 0x0 0x0
#define MX8MN_IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x128 0x390 0x000 0x1 0x0
#define MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x128 0x390 0x5E0 0x2 0x0
#define MX8MN_IOMUXC_NAND_DATA07_GPIO3_IO13 0x128 0x390 0x000 0x5 0x0
#define MX8MN_IOMUXC_NAND_DATA07_CORESIGHT_TRACE11 0x128 0x390 0x000 0x6 0x0
#define MX8MN_IOMUXC_NAND_DQS_RAWNAND_DQS 0x12C 0x394 0x000 0x0 0x0
#define MX8MN_IOMUXC_NAND_DQS_QSPI_A_DQS 0x12C 0x394 0x000 0x1 0x0
#define MX8MN_IOMUXC_NAND_DQS_PDM_CLK 0x12C 0x394 0x000 0x3 0x0
#define MX8MN_IOMUXC_NAND_DQS_I2C3_SCL 0x12C 0x394 0x588 0x4 0x2
#define MX8MN_IOMUXC_NAND_DQS_GPIO3_IO14 0x12C 0x394 0x000 0x5 0x0
#define MX8MN_IOMUXC_NAND_DQS_CORESIGHT_TRACE12 0x12C 0x394 0x000 0x6 0x0
#define MX8MN_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x130 0x398 0x000 0x0 0x0
#define MX8MN_IOMUXC_NAND_RE_B_QSPI_B_DQS 0x130 0x398 0x000 0x1 0x0
#define MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x130 0x398 0x558 0x2 0x0
#define MX8MN_IOMUXC_NAND_RE_B_PDM_BIT_STREAM1 0x130 0x398 0x538 0x3 0x7
#define MX8MN_IOMUXC_NAND_RE_B_GPIO3_IO15 0x130 0x398 0x000 0x5 0x0
#define MX8MN_IOMUXC_NAND_RE_B_CORESIGHT_TRACE13 0x130 0x398 0x000 0x6 0x0
#define MX8MN_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x134 0x39C 0x000 0x0 0x0
#define MX8MN_IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x134 0x39C 0x000 0x2 0x0
#define MX8MN_IOMUXC_NAND_READY_B_PDM_BIT_STREAM3 0x134 0x39C 0x540 0x3 0x6
#define MX8MN_IOMUXC_NAND_READY_B_I2C3_SCL 0x134 0x39C 0x588 0x4 0x3
#define MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16 0x134 0x39C 0x000 0x5 0x0
#define MX8MN_IOMUXC_NAND_READY_B_CORESIGHT_TRACE14 0x134 0x39C 0x000 0x6 0x0
#define MX8MN_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x138 0x3A0 0x000 0x0 0x0
#define MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x138 0x3A0 0x5A0 0x2 0x0
#define MX8MN_IOMUXC_NAND_WE_B_I2C3_SDA 0x138 0x3A0 0x5BC 0x4 0x3
#define MX8MN_IOMUXC_NAND_WE_B_GPIO3_IO17 0x138 0x3A0 0x000 0x5 0x0
#define MX8MN_IOMUXC_NAND_WE_B_CORESIGHT_TRACE15 0x138 0x3A0 0x000 0x6 0x0
#define MX8MN_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x13C 0x3A4 0x000 0x0 0x0
#define MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x13C 0x3A4 0x5DC 0x2 0x0
#define MX8MN_IOMUXC_NAND_WP_B_I2C4_SDA 0x13C 0x3A4 0x58C 0x4 0x4
#define MX8MN_IOMUXC_NAND_WP_B_GPIO3_IO18 0x13C 0x3A4 0x000 0x5 0x0
#define MX8MN_IOMUXC_NAND_WP_B_CORESIGHT_EVENTO 0x13C 0x3A4 0x000 0x6 0x0
#define MX8MN_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x140 0x3A8 0x4E4 0x0 0x0
#define MX8MN_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x140 0x3A8 0x000 0x5 0x0
#define MX8MN_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x144 0x3AC 0x4D0 0x0 0x0
#define MX8MN_IOMUXC_SAI5_RXC_PDM_CLK 0x144 0x3AC 0x000 0x4 0x0
#define MX8MN_IOMUXC_SAI5_RXC_GPIO3_IO20 0x144 0x3AC 0x000 0x5 0x0
#define MX8MN_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x148 0x3B0 0x4D4 0x0 0x0
#define MX8MN_IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0x148 0x3B0 0x534 0x4 0x0
#define MX8MN_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x148 0x3B0 0x000 0x5 0x0
#define MX8MN_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x14C 0x3B4 0x4D8 0x0 0x0
#define MX8MN_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x14C 0x3B4 0x4EC 0x3 0x0
#define MX8MN_IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0x14C 0x3B4 0x538 0x4 0x0
#define MX8MN_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x14C 0x3B4 0x000 0x5 0x0
#define MX8MN_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x150 0x3B8 0x4DC 0x0 0x0
#define MX8MN_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x150 0x3B8 0x4E8 0x3 0x0
#define MX8MN_IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0x150 0x3B8 0x53C 0x4 0x0
#define MX8MN_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x150 0x3B8 0x000 0x5 0x0
#define MX8MN_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x154 0x3BC 0x4E0 0x0 0x0
#define MX8MN_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x154 0x3BC 0x000 0x3 0x0
#define MX8MN_IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0x154 0x3BC 0x540 0x4 0x0
#define MX8MN_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x154 0x3BC 0x000 0x5 0x0
#define MX8MN_IOMUXC_SAI5_MCLK_SAI5_MCLK 0x158 0x3C0 0x594 0x0 0x0
#define MX8MN_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x158 0x3C0 0x000 0x5 0x0
#define MX8MN_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x1B0 0x418 0x000 0x0 0x0
#define MX8MN_IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x1B0 0x418 0x4EC 0x1 0x2
#define MX8MN_IOMUXC_SAI2_RXFS_SAI5_TX_DATA1 0x1B0 0x418 0x000 0x2 0x0
#define MX8MN_IOMUXC_SAI2_RXFS_SAI2_RX_DATA1 0x1B0 0x418 0x5AC 0x3 0x0
#define MX8MN_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x1B0 0x418 0x000 0x4 0x0
#define MX8MN_IOMUXC_SAI2_RXFS_UART1_DTE_RX 0x1B0 0x418 0x4F4 0x4 0x2
#define MX8MN_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x1B0 0x418 0x000 0x5 0x0
#define MX8MN_IOMUXC_SAI2_RXFS_PDM_BIT_STREAM2 0x1B0 0x418 0x53C 0x6 0x7
#define MX8MN_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x1B4 0x41C 0x000 0x0 0x0
#define MX8MN_IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x1B4 0x41C 0x4E8 0x1 0x2
#define MX8MN_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x1B4 0x41C 0x4F4 0x4 0x3
#define MX8MN_IOMUXC_SAI2_RXC_UART1_DTE_TX 0x1B4 0x41C 0x000 0x4 0x0
#define MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x1B4 0x41C 0x000 0x5 0x0
#define MX8MN_IOMUXC_SAI2_RXC_PDM_BIT_STREAM1 0x1B4 0x41C 0x538 0x6 0x8
#define MX8MN_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x1B8 0x420 0x000 0x0 0x0
#define MX8MN_IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x1B8 0x420 0x000 0x1 0x0
#define MX8MN_IOMUXC_SAI2_RXD0_SAI2_TX_DATA1 0x1B8 0x420 0x000 0x3 0x0
#define MX8MN_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x1B8 0x420 0x4F0 0x4 0x2
#define MX8MN_IOMUXC_SAI2_RXD0_UART1_DTE_CTS_B 0x1B8 0x420 0x000 0x4 0x0
#define MX8MN_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x1B8 0x420 0x000 0x5 0x0
#define MX8MN_IOMUXC_SAI2_RXD0_PDM_BIT_STREAM3 0x1B8 0x420 0x540 0x6 0x7
#define MX8MN_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x1BC 0x424 0x000 0x0 0x0
#define MX8MN_IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x1BC 0x424 0x000 0x1 0x0
#define MX8MN_IOMUXC_SAI2_TXFS_SAI2_TX_DATA1 0x1BC 0x424 0x000 0x3 0x0
#define MX8MN_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x1BC 0x424 0x000 0x4 0x0
#define MX8MN_IOMUXC_SAI2_TXFS_UART1_DTE_RTS_B 0x1BC 0x424 0x4F0 0x4 0x3
#define MX8MN_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x1BC 0x424 0x000 0x5 0x0
#define MX8MN_IOMUXC_SAI2_TXFS_PDM_BIT_STREAM2 0x1BC 0x424 0x53C 0x6 0x8
#define MX8MN_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x1C0 0x428 0x000 0x0 0x0
#define MX8MN_IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x1C0 0x428 0x000 0x1 0x0
#define MX8MN_IOMUXC_SAI2_TXC_GPIO4_IO25 0x1C0 0x428 0x000 0x5 0x0
#define MX8MN_IOMUXC_SAI2_TXC_PDM_BIT_STREAM1 0x1C0 0x428 0x538 0x6 0x9
#define MX8MN_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x1C4 0x42C 0x000 0x0 0x0
#define MX8MN_IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x1C4 0x42C 0x000 0x1 0x0
#define MX8MN_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x1C4 0x42C 0x000 0x5 0x0
#define MX8MN_IOMUXC_SAI2_TXD0_CCMSRCGPCMIX_BOOT_MODE4 0x1C4 0x42C 0x540 0x6 0x8
#define MX8MN_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x1C8 0x430 0x000 0x0 0x0
#define MX8MN_IOMUXC_SAI2_MCLK_SAI5_MCLK 0x1C8 0x430 0x594 0x1 0x2
#define MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x1C8 0x430 0x000 0x5 0x0
#define MX8MN_IOMUXC_SAI2_MCLK_SAI3_MCLK 0x1C8 0x430 0x5C0 0x6 0x1
#define MX8MN_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x1CC 0x434 0x000 0x0 0x0
#define MX8MN_IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x1CC 0x434 0x5F0 0x1 0x0
#define MX8MN_IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x1CC 0x434 0x4E4 0x2 0x2
#define MX8MN_IOMUXC_SAI3_RXFS_SAI3_RX_DATA1 0x1CC 0x434 0x000 0x3 0x0
#define MX8MN_IOMUXC_SAI3_RXFS_SPDIF1_IN 0x1CC 0x434 0x5CC 0x4 0x3
#define MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x1CC 0x434 0x000 0x5 0x0
#define MX8MN_IOMUXC_SAI3_RXFS_PDM_BIT_STREAM0 0x1CC 0x434 0x534 0x6 0x5
#define MX8MN_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x1D0 0x438 0x000 0x0 0x0
#define MX8MN_IOMUXC_SAI3_RXC_GPT1_CLK 0x1D0 0x438 0x5E8 0x1 0x0
#define MX8MN_IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x1D0 0x438 0x4D0 0x2 0x2
#define MX8MN_IOMUXC_SAI3_RXC_SAI2_RX_DATA1 0x1D0 0x438 0x5AC 0x3 0x2
#define MX8MN_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x1D0 0x438 0x000 0x4 0x0
#define MX8MN_IOMUXC_SAI3_RXC_UART2_DTE_RTS_B 0x1D0 0x438 0x4F8 0x4 0x2
#define MX8MN_IOMUXC_SAI3_RXC_GPIO4_IO29 0x1D0 0x438 0x000 0x5 0x0
#define MX8MN_IOMUXC_SAI3_RXC_PDM_CLK 0x1D0 0x438 0x000 0x6 0x0
#define MX8MN_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x1D4 0x43C 0x000 0x0 0x0
#define MX8MN_IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x1D4 0x43C 0x000 0x1 0x0
#define MX8MN_IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x1D4 0x43C 0x4D4 0x2 0x2
#define MX8MN_IOMUXC_SAI3_RXD_SAI3_TX_DATA1 0x1D4 0x43C 0x000 0x3 0x0
#define MX8MN_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x1D4 0x43C 0x4F8 0x4 0x3
#define MX8MN_IOMUXC_SAI3_RXD_UART2_DTE_CTS_B 0x1D4 0x43C 0x000 0x4 0x0
#define MX8MN_IOMUXC_SAI3_RXD_GPIO4_IO30 0x1D4 0x43C 0x000 0x5 0x0
#define MX8MN_IOMUXC_SAI3_RXD_PDM_BIT_STREAM1 0x1D4 0x43C 0x538 0x6 0x10
#define MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x1D8 0x440 0x000 0x0 0x0
#define MX8MN_IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x1D8 0x440 0x5EC 0x1 0x0
#define MX8MN_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x1D8 0x440 0x4D8 0x2 0x1
#define MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_DATA1 0x1D8 0x440 0x000 0x3 0x0
#define MX8MN_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x1D8 0x440 0x4FC 0x4 0x2
#define MX8MN_IOMUXC_SAI3_TXFS_UART2_DTE_TX 0x1D8 0x440 0x000 0x4 0x0
#define MX8MN_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x1D8 0x440 0x000 0x5 0x0
#define MX8MN_IOMUXC_SAI3_TXFS_PDM_BIT_STREAM3 0x1D8 0x440 0x540 0x6 0x9
#define MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x1DC 0x444 0x000 0x0 0x0
#define MX8MN_IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x1DC 0x444 0x000 0x1 0x0
#define MX8MN_IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x1DC 0x444 0x4DC 0x2 0x1
#define MX8MN_IOMUXC_SAI3_TXC_SAI2_TX_DATA1 0x1DC 0x444 0x000 0x3 0x0
#define MX8MN_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x1DC 0x444 0x000 0x4 0x0
#define MX8MN_IOMUXC_SAI3_TXC_UART2_DTE_RX 0x1DC 0x444 0x4FC 0x4 0x3
#define MX8MN_IOMUXC_SAI3_TXC_GPIO5_IO0 0x1DC 0x444 0x000 0x5 0x0
#define MX8MN_IOMUXC_SAI3_TXC_PDM_BIT_STREAM2 0x1DC 0x444 0x53C 0x6 0x9
#define MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x1E0 0x448 0x000 0x0 0x0
#define MX8MN_IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x1E0 0x448 0x000 0x1 0x0
#define MX8MN_IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x1E0 0x448 0x4E0 0x2 0x1
#define MX8MN_IOMUXC_SAI3_TXD_SPDIF1_EXT_CLK 0x1E0 0x448 0x568 0x4 0x2
#define MX8MN_IOMUXC_SAI3_TXD_GPIO5_IO1 0x1E0 0x448 0x000 0x5 0x0
#define MX8MN_IOMUXC_SAI3_TXD_CCMSRCGPCMIX_BOOT_MODE5 0x1E0 0x448 0x000 0x6 0x0
#define MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0x1E4 0x44C 0x5C0 0x0 0x0
#define MX8MN_IOMUXC_SAI3_MCLK_PWM4_OUT 0x1E4 0x44C 0x000 0x1 0x0
#define MX8MN_IOMUXC_SAI3_MCLK_SAI5_MCLK 0x1E4 0x44C 0x594 0x2 0x3
#define MX8MN_IOMUXC_SAI3_MCLK_SPDIF1_OUT 0x1E4 0x44C 0x000 0x4 0x0
#define MX8MN_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x1E4 0x44C 0x000 0x5 0x0
#define MX8MN_IOMUXC_SAI3_MCLK_SPDIF1_IN 0x1E4 0x44C 0x5CC 0x6 0x4
#define MX8MN_IOMUXC_SPDIF_TX_SPDIF1_OUT 0x1E8 0x450 0x000 0x0 0x0
#define MX8MN_IOMUXC_SPDIF_TX_PWM3_OUT 0x1E8 0x450 0x000 0x1 0x0
#define MX8MN_IOMUXC_SPDIF_TX_GPIO5_IO3 0x1E8 0x450 0x000 0x5 0x0
#define MX8MN_IOMUXC_SPDIF_RX_SPDIF1_IN 0x1EC 0x454 0x5CC 0x0 0x0
#define MX8MN_IOMUXC_SPDIF_RX_PWM2_OUT 0x1EC 0x454 0x000 0x1 0x0
#define MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4 0x1EC 0x454 0x000 0x5 0x0
#define MX8MN_IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x1F0 0x458 0x568 0x0 0x0
#define MX8MN_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x1F0 0x458 0x000 0x1 0x0
#define MX8MN_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x1F0 0x458 0x000 0x5 0x0
#define MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x1F4 0x45C 0x5D8 0x0 0x0
#define MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x1F4 0x45C 0x504 0x1 0x0
#define MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DTE_TX 0x1F4 0x45C 0x000 0x1 0x0
#define MX8MN_IOMUXC_ECSPI1_SCLK_I2C1_SCL 0x1F4 0x45C 0x55C 0x2 0x2
#define MX8MN_IOMUXC_ECSPI1_SCLK_SAI5_RX_SYNC 0x1F4 0x45C 0x4DC 0x3 0x2
#define MX8MN_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x1F4 0x45C 0x000 0x5 0x0
#define MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x1F8 0x460 0x5A8 0x0 0x0
#define MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x1F8 0x460 0x000 0x1 0x0
#define MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DTE_RX 0x1F8 0x460 0x504 0x1 0x1
#define MX8MN_IOMUXC_ECSPI1_MOSI_I2C1_SDA 0x1F8 0x460 0x56C 0x2 0x2
#define MX8MN_IOMUXC_ECSPI1_MOSI_SAI5_RX_BCLK 0x1F8 0x460 0x4D0 0x3 0x3
#define MX8MN_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x1F8 0x460 0x000 0x5 0x0
#define MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x1FC 0x464 0x5C4 0x0 0x0
#define MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x1FC 0x464 0x000 0x1 0x0
#define MX8MN_IOMUXC_ECSPI1_MISO_UART3_DTE_RTS_B 0x1FC 0x464 0x500 0x1 0x0
#define MX8MN_IOMUXC_ECSPI1_MISO_I2C2_SCL 0x1FC 0x464 0x5D0 0x2 0x2
#define MX8MN_IOMUXC_ECSPI1_MISO_SAI5_RX_DATA0 0x1FC 0x464 0x4D4 0x3 0x3
#define MX8MN_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x1FC 0x464 0x000 0x5 0x0
#define MX8MN_IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x200 0x468 0x564 0x0 0x0
#define MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x200 0x468 0x500 0x1 0x1
#define MX8MN_IOMUXC_ECSPI1_SS0_UART3_DTE_CTS_B 0x200 0x468 0x000 0x1 0x0
#define MX8MN_IOMUXC_ECSPI1_SS0_I2C2_SDA 0x200 0x468 0x560 0x2 0x2
#define MX8MN_IOMUXC_ECSPI1_SS0_SAI5_RX_DATA1 0x200 0x468 0x4D8 0x3 0x2
#define MX8MN_IOMUXC_ECSPI1_SS0_SAI5_TX_SYNC 0x200 0x468 0x4EC 0x4 0x3
#define MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x200 0x468 0x000 0x5 0x0
#define MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x204 0x46C 0x580 0x0 0x0
#define MX8MN_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x204 0x46C 0x50C 0x1 0x0
#define MX8MN_IOMUXC_ECSPI2_SCLK_UART4_DTE_TX 0x204 0x46C 0x000 0x1 0x0
#define MX8MN_IOMUXC_ECSPI2_SCLK_I2C3_SCL 0x204 0x46C 0x588 0x2 0x4
#define MX8MN_IOMUXC_ECSPI2_SCLK_SAI5_RX_DATA2 0x204 0x46C 0x000 0x3 0x0
#define MX8MN_IOMUXC_ECSPI2_SCLK_SAI5_TX_BCLK 0x204 0x46C 0x4E8 0x4 0x3
#define MX8MN_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x204 0x46C 0x000 0x5 0x0
#define MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x208 0x470 0x590 0x0 0x0
#define MX8MN_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x208 0x470 0x000 0x1 0x0
#define MX8MN_IOMUXC_ECSPI2_MOSI_UART4_DTE_RX 0x208 0x470 0x50C 0x1 0x1
#define MX8MN_IOMUXC_ECSPI2_MOSI_I2C3_SDA 0x208 0x470 0x5BC 0x2 0x4
#define MX8MN_IOMUXC_ECSPI2_MOSI_SAI5_RX_DATA3 0x208 0x470 0x4E0 0x3 0x2
#define MX8MN_IOMUXC_ECSPI2_MOSI_SAI5_TX_DATA0 0x208 0x470 0x000 0x4 0x0
#define MX8MN_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x208 0x470 0x000 0x5 0x0
#define MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x20C 0x474 0x578 0x0 0x0
#define MX8MN_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x20C 0x474 0x000 0x1 0x0
#define MX8MN_IOMUXC_ECSPI2_MISO_UART4_DTE_RTS_B 0x20C 0x474 0x508 0x1 0x0
#define MX8MN_IOMUXC_ECSPI2_MISO_I2C4_SCL 0x20C 0x474 0x5D4 0x2 0x3
#define MX8MN_IOMUXC_ECSPI2_MISO_SAI5_MCLK 0x20C 0x474 0x594 0x3 0x4
#define MX8MN_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x20C 0x474 0x000 0x5 0x0
#define MX8MN_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x210 0x478 0x570 0x0 0x0
#define MX8MN_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x210 0x478 0x508 0x1 0x1
#define MX8MN_IOMUXC_ECSPI2_SS0_UART4_DTE_CTS_B 0x210 0x478 0x000 0x1 0x0
#define MX8MN_IOMUXC_ECSPI2_SS0_I2C4_SDA 0x210 0x478 0x58C 0x2 0x5
#define MX8MN_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x210 0x478 0x000 0x5 0x0
#define MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x214 0x47C 0x55C 0x0 0x0
#define MX8MN_IOMUXC_I2C1_SCL_ENET1_MDC 0x214 0x47C 0x000 0x1 0x0
#define MX8MN_IOMUXC_I2C1_SCL_ECSPI1_SCLK 0x214 0x47C 0x5D8 0x3 0x1
#define MX8MN_IOMUXC_I2C1_SCL_GPIO5_IO14 0x214 0x47C 0x000 0x5 0x0
#define MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x218 0x480 0x56C 0x0 0x0
#define MX8MN_IOMUXC_I2C1_SDA_ENET1_MDIO 0x218 0x480 0x4C0 0x1 0x2
#define MX8MN_IOMUXC_I2C1_SDA_ECSPI1_MOSI 0x218 0x480 0x5A8 0x3 0x1
#define MX8MN_IOMUXC_I2C1_SDA_GPIO5_IO15 0x218 0x480 0x000 0x5 0x0
#define MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x21C 0x484 0x5D0 0x0 0x0
#define MX8MN_IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x21C 0x484 0x000 0x1 0x0
#define MX8MN_IOMUXC_I2C2_SCL_USDHC3_CD_B 0x21C 0x484 0x598 0x2 0x1
#define MX8MN_IOMUXC_I2C2_SCL_ECSPI1_MISO 0x21C 0x484 0x5C4 0x3 0x1
#define MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x21C 0x484 0x000 0x5 0x0
#define MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x220 0x488 0x560 0x0 0x0
#define MX8MN_IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x220 0x488 0x000 0x1 0x0
#define MX8MN_IOMUXC_I2C2_SDA_USDHC3_WP 0x220 0x488 0x5B8 0x2 0x1
#define MX8MN_IOMUXC_I2C2_SDA_ECSPI1_SS0 0x220 0x488 0x564 0x3 0x1
#define MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x220 0x488 0x000 0x5 0x0
#define MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x224 0x48C 0x588 0x0 0x0
#define MX8MN_IOMUXC_I2C3_SCL_PWM4_OUT 0x224 0x48C 0x000 0x1 0x0
#define MX8MN_IOMUXC_I2C3_SCL_GPT2_CLK 0x224 0x48C 0x000 0x2 0x0
#define MX8MN_IOMUXC_I2C3_SCL_ECSPI2_SCLK 0x224 0x48C 0x580 0x3 0x2
#define MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x224 0x48C 0x000 0x5 0x0
#define MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x228 0x490 0x5BC 0x0 0x0
#define MX8MN_IOMUXC_I2C3_SDA_PWM3_OUT 0x228 0x490 0x000 0x1 0x0
#define MX8MN_IOMUXC_I2C3_SDA_GPT3_CLK 0x228 0x490 0x000 0x2 0x0
#define MX8MN_IOMUXC_I2C3_SDA_ECSPI2_MOSI 0x228 0x490 0x590 0x3 0x2
#define MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x228 0x490 0x000 0x5 0x0
#define MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x22C 0x494 0x5D4 0x0 0x0
#define MX8MN_IOMUXC_I2C4_SCL_PWM2_OUT 0x22C 0x494 0x000 0x1 0x0
#define MX8MN_IOMUXC_I2C4_SCL_ECSPI2_MISO 0x22C 0x494 0x578 0x3 0x2
#define MX8MN_IOMUXC_I2C4_SCL_GPIO5_IO20 0x22C 0x494 0x000 0x5 0x0
#define MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 0x230 0x498 0x58C 0x0 0x0
#define MX8MN_IOMUXC_I2C4_SDA_PWM1_OUT 0x230 0x498 0x000 0x1 0x0
#define MX8MN_IOMUXC_I2C4_SDA_ECSPI2_SS0 0x230 0x498 0x570 0x3 0x1
#define MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21 0x230 0x498 0x000 0x5 0x0
#define MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x234 0x49C 0x4F4 0x0 0x0
#define MX8MN_IOMUXC_UART1_RXD_UART1_DTE_TX 0x234 0x49C 0x000 0x0 0x0
#define MX8MN_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x234 0x49C 0x000 0x1 0x0
#define MX8MN_IOMUXC_UART1_RXD_GPIO5_IO22 0x234 0x49C 0x000 0x5 0x0
#define MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x238 0x4A0 0x000 0x0 0x0
#define MX8MN_IOMUXC_UART1_TXD_UART1_DTE_RX 0x238 0x4A0 0x4F4 0x0 0x1
#define MX8MN_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x238 0x4A0 0x000 0x1 0x0
#define MX8MN_IOMUXC_UART1_TXD_GPIO5_IO23 0x238 0x4A0 0x000 0x5 0x0
#define MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x23C 0x4A4 0x4FC 0x0 0x0
#define MX8MN_IOMUXC_UART2_RXD_UART2_DTE_TX 0x23C 0x4A4 0x000 0x0 0x0
#define MX8MN_IOMUXC_UART2_RXD_ECSPI3_MISO 0x23C 0x4A4 0x000 0x1 0x0
#define MX8MN_IOMUXC_UART2_RXD_GPT1_COMPARE3 0x23C 0x4A4 0x000 0x3 0x0
#define MX8MN_IOMUXC_UART2_RXD_GPIO5_IO24 0x23C 0x4A4 0x000 0x5 0x0
#define MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x240 0x4A8 0x000 0x0 0x0
#define MX8MN_IOMUXC_UART2_TXD_UART2_DTE_RX 0x240 0x4A8 0x4FC 0x0 0x1
#define MX8MN_IOMUXC_UART2_TXD_ECSPI3_SS0 0x240 0x4A8 0x000 0x1 0x0
#define MX8MN_IOMUXC_UART2_TXD_GPT1_COMPARE2 0x240 0x4A8 0x000 0x3 0x0
#define MX8MN_IOMUXC_UART2_TXD_GPIO5_IO25 0x240 0x4A8 0x000 0x5 0x0
#define MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX 0x244 0x4AC 0x504 0x0 0x2
#define MX8MN_IOMUXC_UART3_RXD_UART3_DTE_TX 0x244 0x4AC 0x000 0x0 0x0
#define MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x244 0x4AC 0x000 0x1 0x0
#define MX8MN_IOMUXC_UART3_RXD_UART1_DTE_RTS_B 0x244 0x4AC 0x4F0 0x1 0x0
#define MX8MN_IOMUXC_UART3_RXD_USDHC3_RESET_B 0x244 0x4AC 0x000 0x2 0x0
#define MX8MN_IOMUXC_UART3_RXD_GPT1_CAPTURE2 0x244 0x4AC 0x5EC 0x3 0x1
#define MX8MN_IOMUXC_UART3_RXD_GPIO5_IO26 0x244 0x4AC 0x000 0x5 0x0
#define MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX 0x248 0x4B0 0x000 0x0 0x0
#define MX8MN_IOMUXC_UART3_TXD_UART3_DTE_RX 0x248 0x4B0 0x504 0x0 0x3
#define MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x248 0x4B0 0x4F0 0x1 0x1
#define MX8MN_IOMUXC_UART3_TXD_UART1_DTE_CTS_B 0x248 0x4B0 0x000 0x1 0x0
#define MX8MN_IOMUXC_UART3_TXD_USDHC3_VSELECT 0x248 0x4B0 0x000 0x2 0x0
#define MX8MN_IOMUXC_UART3_TXD_GPT1_CLK 0x248 0x4B0 0x5E8 0x3 0x1
#define MX8MN_IOMUXC_UART3_TXD_GPIO5_IO27 0x248 0x4B0 0x000 0x5 0x0
#define MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x24C 0x4B4 0x50C 0x0 0x2
#define MX8MN_IOMUXC_UART4_RXD_UART4_DTE_TX 0x24C 0x4B4 0x000 0x0 0x0
#define MX8MN_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x24C 0x4B4 0x000 0x1 0x0
#define MX8MN_IOMUXC_UART4_RXD_UART2_DTE_RTS_B 0x24C 0x4B4 0x4F8 0x1 0x0
#define MX8MN_IOMUXC_UART4_RXD_GPT1_COMPARE1 0x24C 0x4B4 0x000 0x3 0x0
#define MX8MN_IOMUXC_UART4_RXD_GPIO5_IO28 0x24C 0x4B4 0x000 0x5 0x0
#define MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x250 0x4B8 0x000 0x0 0x0
#define MX8MN_IOMUXC_UART4_TXD_UART4_DTE_RX 0x250 0x4B8 0x50C 0x0 0x3
#define MX8MN_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x250 0x4B8 0x4F8 0x1 0x1
#define MX8MN_IOMUXC_UART4_TXD_UART2_DTE_CTS_B 0x250 0x4B8 0x000 0x1 0x0
#define MX8MN_IOMUXC_UART4_TXD_GPT1_CAPTURE1 0x250 0x4B8 0x5F0 0x3 0x1
#define MX8MN_IOMUXC_UART4_TXD_GPIO5_IO29 0x250 0x4B8 0x000 0x5 0x0
#endif /* __DTS_IMX8MN_PINFUNC_H */

View File

@@ -240,7 +240,6 @@
};
#endif
#ifdef CONFIG_OPTEE
tee: tee {
description = "OP-TEE";
type = "tee";
@@ -252,9 +251,9 @@
tee-os {
filename = "tee.bin";
optional;
};
};
#endif
binman_fip: fip {
arch = "arm64";
@@ -284,11 +283,7 @@
fdt = "fdt-SEQ";
firmware = "uboot";
#ifndef CONFIG_ARMV8_PSCI
#ifdef CONFIG_OPTEE
loadables = "atf", "tee";
#else
loadables = "atf";
#endif
#endif
};
};

View File

@@ -1,799 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2019 NXP
*/
#ifndef __DTS_IMX8MP_PINFUNC_H
#define __DTS_IMX8MP_PINFUNC_H
/*
* The pin function ID is a tuple of
* <mux_reg conf_reg input_reg mux_mode input_val>
*/
#define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0
#define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0
#define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0
#define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0
#define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0
#define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0
#define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0
#define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0
#define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0
#define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0
#define MX8MP_IOMUXC_GPIO1_IO02__ISP_FLASH_TRIG_0 0x01C 0x27C 0x000 0x3 0x0
#define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_ANY 0x01C 0x27C 0x000 0x5 0x0
#define MX8MP_IOMUXC_GPIO1_IO02__SJC_DE_B 0x01C 0x27C 0x000 0x7 0x0
#define MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x020 0x280 0x000 0x0 0x0
#define MX8MP_IOMUXC_GPIO1_IO03__USDHC1_VSELECT 0x020 0x280 0x000 0x1 0x0
#define MX8MP_IOMUXC_GPIO1_IO03__ISP_PRELIGHT_TRIG_0 0x020 0x280 0x000 0x3 0x0
#define MX8MP_IOMUXC_GPIO1_IO03__SDMA1_EXT_EVENT00 0x020 0x280 0x000 0x5 0x0
#define MX8MP_IOMUXC_GPIO1_IO04__GPIO1_IO04 0x024 0x284 0x000 0x0 0x0
#define MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x024 0x284 0x000 0x1 0x0
#define MX8MP_IOMUXC_GPIO1_IO04__ISP_SHUTTER_OPEN_0 0x024 0x284 0x000 0x3 0x0
#define MX8MP_IOMUXC_GPIO1_IO04__SDMA1_EXT_EVENT01 0x024 0x284 0x000 0x5 0x0
#define MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x028 0x288 0x000 0x0 0x0
#define MX8MP_IOMUXC_GPIO1_IO05__M7_NMI 0x028 0x288 0x000 0x1 0x0
#define MX8MP_IOMUXC_GPIO1_IO05__ISP_FL_TRIG_1 0x028 0x288 0x5D8 0x3 0x0
#define MX8MP_IOMUXC_GPIO1_IO05__CCM_PMIC_READY 0x028 0x288 0x554 0x5 0x0
#define MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x02C 0x28C 0x000 0x0 0x0
#define MX8MP_IOMUXC_GPIO1_IO06__ENET_QOS_MDC 0x02C 0x28C 0x000 0x1 0x0
#define MX8MP_IOMUXC_GPIO1_IO06__ISP_SHUTTER_TRIG_1 0x02C 0x28C 0x5E0 0x3 0x0
#define MX8MP_IOMUXC_GPIO1_IO06__USDHC1_CD_B 0x02C 0x28C 0x000 0x5 0x0
#define MX8MP_IOMUXC_GPIO1_IO06__CCM_EXT_CLK3 0x02C 0x28C 0x000 0x6 0x0
#define MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x030 0x290 0x000 0x0 0x0
#define MX8MP_IOMUXC_GPIO1_IO07__ENET_QOS_MDIO 0x030 0x290 0x590 0x1 0x0
#define MX8MP_IOMUXC_GPIO1_IO07__ISP_FLASH_TRIG_1 0x030 0x290 0x000 0x3 0x0
#define MX8MP_IOMUXC_GPIO1_IO07__USDHC1_WP 0x030 0x290 0x000 0x5 0x0
#define MX8MP_IOMUXC_GPIO1_IO07__CCM_EXT_CLK4 0x030 0x290 0x000 0x6 0x0
#define MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x034 0x294 0x000 0x0 0x0
#define MX8MP_IOMUXC_GPIO1_IO08__ENET_QOS_1588_EVENT0_IN 0x034 0x294 0x000 0x1 0x0
#define MX8MP_IOMUXC_GPIO1_IO08__PWM1_OUT 0x034 0x294 0x000 0x2 0x0
#define MX8MP_IOMUXC_GPIO1_IO08__ISP_PRELIGHT_TRIG_1 0x034 0x294 0x000 0x3 0x0
#define MX8MP_IOMUXC_GPIO1_IO08__ENET_QOS_1588_EVENT0_AUX_IN 0x034 0x294 0x000 0x4 0x0
#define MX8MP_IOMUXC_GPIO1_IO08__USDHC2_RESET_B 0x034 0x294 0x000 0x5 0x0
#define MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x038 0x298 0x000 0x0 0x0
#define MX8MP_IOMUXC_GPIO1_IO09__ENET_QOS_1588_EVENT0_OUT 0x038 0x298 0x000 0x1 0x0
#define MX8MP_IOMUXC_GPIO1_IO09__PWM2_OUT 0x038 0x298 0x000 0x2 0x0
#define MX8MP_IOMUXC_GPIO1_IO09__ISP_SHUTTER_OPEN_1 0x038 0x298 0x000 0x3 0x0
#define MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B 0x038 0x298 0x000 0x4 0x0
#define MX8MP_IOMUXC_GPIO1_IO09__SDMA2_EXT_EVENT00 0x038 0x298 0x000 0x5 0x0
#define MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x03C 0x29C 0x000 0x0 0x0
#define MX8MP_IOMUXC_GPIO1_IO10__USB1_OTG_ID 0x03C 0x29C 0x000 0x1 0x0
#define MX8MP_IOMUXC_GPIO1_IO10__PWM3_OUT 0x03C 0x29C 0x000 0x2 0x0
#define MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x040 0x2A0 0x000 0x0 0x0
#define MX8MP_IOMUXC_GPIO1_IO11__USB2_OTG_ID 0x040 0x2A0 0x000 0x1 0x0
#define MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x040 0x2A0 0x000 0x2 0x0
#define MX8MP_IOMUXC_GPIO1_IO11__USDHC3_VSELECT 0x040 0x2A0 0x000 0x4 0x0
#define MX8MP_IOMUXC_GPIO1_IO11__CCM_PMIC_READY 0x040 0x2A0 0x554 0x5 0x1
#define MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x044 0x2A4 0x000 0x0 0x0
#define MX8MP_IOMUXC_GPIO1_IO12__USB1_OTG_PWR 0x044 0x2A4 0x000 0x1 0x0
#define MX8MP_IOMUXC_GPIO1_IO12__SDMA2_EXT_EVENT01 0x044 0x2A4 0x000 0x5 0x0
#define MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x048 0x2A8 0x000 0x0 0x0
#define MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x048 0x2A8 0x000 0x1 0x0
#define MX8MP_IOMUXC_GPIO1_IO13__PWM2_OUT 0x048 0x2A8 0x000 0x5 0x0
#define MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x04C 0x2AC 0x000 0x0 0x0
#define MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x04C 0x2AC 0x000 0x1 0x0
#define MX8MP_IOMUXC_GPIO1_IO14__USDHC3_CD_B 0x04C 0x2AC 0x608 0x4 0x0
#define MX8MP_IOMUXC_GPIO1_IO14__PWM3_OUT 0x04C 0x2AC 0x000 0x5 0x0
#define MX8MP_IOMUXC_GPIO1_IO14__CCM_CLKO1 0x04C 0x2AC 0x000 0x6 0x0
#define MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x050 0x2B0 0x000 0x0 0x0
#define MX8MP_IOMUXC_GPIO1_IO15__USB2_OTG_OC 0x050 0x2B0 0x000 0x1 0x0
#define MX8MP_IOMUXC_GPIO1_IO15__USDHC3_WP 0x050 0x2B0 0x634 0x4 0x0
#define MX8MP_IOMUXC_GPIO1_IO15__PWM4_OUT 0x050 0x2B0 0x000 0x5 0x0
#define MX8MP_IOMUXC_GPIO1_IO15__CCM_CLKO2 0x050 0x2B0 0x000 0x6 0x0
#define MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x054 0x2B4 0x000 0x0 0x0
#define MX8MP_IOMUXC_ENET_MDC__AUDIOMIX_SAI6_TX_DATA00 0x054 0x2B4 0x000 0x2 0x0
#define MX8MP_IOMUXC_ENET_MDC__GPIO1_IO16 0x054 0x2B4 0x000 0x5 0x0
#define MX8MP_IOMUXC_ENET_MDC__USDHC3_STROBE 0x054 0x2B4 0x630 0x6 0x0
#define MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x058 0x2B8 0x590 0x0 0x1
#define MX8MP_IOMUXC_ENET_MDIO__AUDIOMIX_SAI6_TX_SYNC 0x058 0x2B8 0x528 0x2 0x0
#define MX8MP_IOMUXC_ENET_MDIO__AUDIOMIX_PDM_BIT_STREAM03 0x058 0x2B8 0x4CC 0x3 0x0
#define MX8MP_IOMUXC_ENET_MDIO__GPIO1_IO17 0x058 0x2B8 0x000 0x5 0x0
#define MX8MP_IOMUXC_ENET_MDIO__USDHC3_DATA5 0x058 0x2B8 0x624 0x6 0x0
#define MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x05C 0x2BC 0x000 0x0 0x0
#define MX8MP_IOMUXC_ENET_TD3__AUDIOMIX_SAI6_TX_BCLK 0x05C 0x2BC 0x524 0x2 0x0
#define MX8MP_IOMUXC_ENET_TD3__AUDIOMIX_PDM_BIT_STREAM02 0x05C 0x2BC 0x4C8 0x3 0x0
#define MX8MP_IOMUXC_ENET_TD3__GPIO1_IO18 0x05C 0x2BC 0x000 0x5 0x0
#define MX8MP_IOMUXC_ENET_TD3__USDHC3_DATA6 0x05C 0x2BC 0x628 0x6 0x0
#define MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x060 0x2C0 0x000 0x0 0x0
#define MX8MP_IOMUXC_ENET_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK 0x060 0x2C0 0x000 0x1 0x0
#define MX8MP_IOMUXC_ENET_TD2__AUDIOMIX_SAI6_RX_DATA00 0x060 0x2C0 0x51C 0x2 0x0
#define MX8MP_IOMUXC_ENET_TD2__AUDIOMIX_PDM_BIT_STREAM01 0x060 0x2C0 0x4C4 0x3 0x0
#define MX8MP_IOMUXC_ENET_TD2__GPIO1_IO19 0x060 0x2C0 0x000 0x5 0x0
#define MX8MP_IOMUXC_ENET_TD2__USDHC3_DATA7 0x060 0x2C0 0x62C 0x6 0x0
#define MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x064 0x2C4 0x000 0x0 0x0
#define MX8MP_IOMUXC_ENET_TD1__AUDIOMIX_SAI6_RX_SYNC 0x064 0x2C4 0x520 0x2 0x0
#define MX8MP_IOMUXC_ENET_TD1__AUDIOMIX_PDM_BIT_STREAM00 0x064 0x2C4 0x4C0 0x3 0x0
#define MX8MP_IOMUXC_ENET_TD1__GPIO1_IO20 0x064 0x2C4 0x000 0x5 0x0
#define MX8MP_IOMUXC_ENET_TD1__USDHC3_CD_B 0x064 0x2C4 0x608 0x6 0x1
#define MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x068 0x2C8 0x000 0x0 0x0
#define MX8MP_IOMUXC_ENET_TD0__AUDIOMIX_SAI6_RX_BCLK 0x068 0x2C8 0x518 0x2 0x0
#define MX8MP_IOMUXC_ENET_TD0__AUDIOMIX_PDM_CLK 0x068 0x2C8 0x000 0x3 0x0
#define MX8MP_IOMUXC_ENET_TD0__GPIO1_IO21 0x068 0x2C8 0x000 0x5 0x0
#define MX8MP_IOMUXC_ENET_TD0__USDHC3_WP 0x068 0x2C8 0x634 0x6 0x1
#define MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x06C 0x2CC 0x000 0x0 0x0
#define MX8MP_IOMUXC_ENET_TX_CTL__AUDIOMIX_SAI6_MCLK 0x06C 0x2CC 0x514 0x2 0x0
#define MX8MP_IOMUXC_ENET_TX_CTL__AUDIOMIX_SPDIF1_OUT 0x06C 0x2CC 0x000 0x3 0x0
#define MX8MP_IOMUXC_ENET_TX_CTL__GPIO1_IO22 0x06C 0x2CC 0x000 0x5 0x0
#define MX8MP_IOMUXC_ENET_TX_CTL__USDHC3_DATA0 0x06C 0x2CC 0x610 0x6 0x0
#define MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x070 0x2D0 0x000 0x0 0x0
#define MX8MP_IOMUXC_ENET_TXC__ENET_QOS_TX_ER 0x070 0x2D0 0x000 0x1 0x0
#define MX8MP_IOMUXC_ENET_TXC__AUDIOMIX_SAI7_TX_DATA00 0x070 0x2D0 0x000 0x2 0x0
#define MX8MP_IOMUXC_ENET_TXC__GPIO1_IO23 0x070 0x2D0 0x000 0x5 0x0
#define MX8MP_IOMUXC_ENET_TXC__USDHC3_DATA1 0x070 0x2D0 0x614 0x6 0x0
#define MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x074 0x2D4 0x000 0x0 0x0
#define MX8MP_IOMUXC_ENET_RX_CTL__AUDIOMIX_SAI7_TX_SYNC 0x074 0x2D4 0x540 0x2 0x0
#define MX8MP_IOMUXC_ENET_RX_CTL__AUDIOMIX_PDM_BIT_STREAM03 0x074 0x2D4 0x4CC 0x3 0x1
#define MX8MP_IOMUXC_ENET_RX_CTL__GPIO1_IO24 0x074 0x2D4 0x000 0x5 0x0
#define MX8MP_IOMUXC_ENET_RX_CTL__USDHC3_DATA2 0x074 0x2D4 0x618 0x6 0x0
#define MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x078 0x2D8 0x000 0x0 0x0
#define MX8MP_IOMUXC_ENET_RXC__ENET_QOS_RX_ER 0x078 0x2D8 0x000 0x1 0x0
#define MX8MP_IOMUXC_ENET_RXC__AUDIOMIX_SAI7_TX_BCLK 0x078 0x2D8 0x53C 0x2 0x0
#define MX8MP_IOMUXC_ENET_RXC__AUDIOMIX_PDM_BIT_STREAM02 0x078 0x2D8 0x4C8 0x3 0x1
#define MX8MP_IOMUXC_ENET_RXC__GPIO1_IO25 0x078 0x2D8 0x000 0x5 0x0
#define MX8MP_IOMUXC_ENET_RXC__USDHC3_DATA3 0x078 0x2D8 0x61C 0x6 0x0
#define MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x07C 0x2DC 0x000 0x0 0x0
#define MX8MP_IOMUXC_ENET_RD0__AUDIOMIX_SAI7_RX_DATA00 0x07C 0x2DC 0x534 0x2 0x0
#define MX8MP_IOMUXC_ENET_RD0__AUDIOMIX_PDM_BIT_STREAM01 0x07C 0x2DC 0x4C4 0x3 0x1
#define MX8MP_IOMUXC_ENET_RD0__GPIO1_IO26 0x07C 0x2DC 0x000 0x5 0x0
#define MX8MP_IOMUXC_ENET_RD0__USDHC3_DATA4 0x07C 0x2DC 0x620 0x6 0x0
#define MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x080 0x2E0 0x000 0x0 0x0
#define MX8MP_IOMUXC_ENET_RD1__AUDIOMIX_SAI7_RX_SYNC 0x080 0x2E0 0x538 0x2 0x0
#define MX8MP_IOMUXC_ENET_RD1__AUDIOMIX_PDM_BIT_STREAM00 0x080 0x2E0 0x4C0 0x3 0x1
#define MX8MP_IOMUXC_ENET_RD1__GPIO1_IO27 0x080 0x2E0 0x000 0x5 0x0
#define MX8MP_IOMUXC_ENET_RD1__USDHC3_RESET_B 0x080 0x2E0 0x000 0x6 0x0
#define MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x084 0x2E4 0x000 0x0 0x0
#define MX8MP_IOMUXC_ENET_RD2__AUDIOMIX_SAI7_RX_BCLK 0x084 0x2E4 0x530 0x2 0x0
#define MX8MP_IOMUXC_ENET_RD2__AUDIOMIX_PDM_CLK 0x084 0x2E4 0x000 0x3 0x0
#define MX8MP_IOMUXC_ENET_RD2__GPIO1_IO28 0x084 0x2E4 0x000 0x5 0x0
#define MX8MP_IOMUXC_ENET_RD2__USDHC3_CLK 0x084 0x2E4 0x604 0x6 0x0
#define MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x088 0x2E8 0x000 0x0 0x0
#define MX8MP_IOMUXC_ENET_RD3__AUDIOMIX_SAI7_MCLK 0x088 0x2E8 0x52C 0x2 0x0
#define MX8MP_IOMUXC_ENET_RD3__AUDIOMIX_SPDIF1_IN 0x088 0x2E8 0x544 0x3 0x0
#define MX8MP_IOMUXC_ENET_RD3__GPIO1_IO29 0x088 0x2E8 0x000 0x5 0x0
#define MX8MP_IOMUXC_ENET_RD3__USDHC3_CMD 0x088 0x2E8 0x60C 0x6 0x0
#define MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x08C 0x2EC 0x000 0x0 0x0
#define MX8MP_IOMUXC_SD1_CLK__ENET1_MDC 0x08C 0x2EC 0x000 0x1 0x0
#define MX8MP_IOMUXC_SD1_CLK__I2C5_SCL 0x08C 0x2EC 0x5C4 0x3 0x0
#define MX8MP_IOMUXC_SD1_CLK__UART1_DCE_TX 0x08C 0x2EC 0x000 0x4 0x0
#define MX8MP_IOMUXC_SD1_CLK__UART1_DTE_RX 0x08C 0x2EC 0x5E8 0x4 0x0
#define MX8MP_IOMUXC_SD1_CLK__GPIO2_IO00 0x08C 0x2EC 0x000 0x5 0x0
#define MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x090 0x2F0 0x000 0x0 0x0
#define MX8MP_IOMUXC_SD1_CMD__ENET1_MDIO 0x090 0x2F0 0x57C 0x1 0x0
#define MX8MP_IOMUXC_SD1_CMD__I2C5_SDA 0x090 0x2F0 0x5C8 0x3 0x0
#define MX8MP_IOMUXC_SD1_CMD__UART1_DCE_RX 0x090 0x2F0 0x5E8 0x4 0x1
#define MX8MP_IOMUXC_SD1_CMD__UART1_DTE_TX 0x090 0x2F0 0x000 0x4 0x0
#define MX8MP_IOMUXC_SD1_CMD__GPIO2_IO01 0x090 0x2F0 0x000 0x5 0x0
#define MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x094 0x2F4 0x000 0x0 0x0
#define MX8MP_IOMUXC_SD1_DATA0__ENET1_RGMII_TD1 0x094 0x2F4 0x000 0x1 0x0
#define MX8MP_IOMUXC_SD1_DATA0__I2C6_SCL 0x094 0x2F4 0x5CC 0x3 0x0
#define MX8MP_IOMUXC_SD1_DATA0__UART1_DCE_RTS 0x094 0x2F4 0x5E4 0x4 0x0
#define MX8MP_IOMUXC_SD1_DATA0__UART1_DTE_CTS 0x094 0x2F4 0x000 0x4 0x0
#define MX8MP_IOMUXC_SD1_DATA0__GPIO2_IO02 0x094 0x2F4 0x000 0x5 0x0
#define MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x098 0x2F8 0x000 0x0 0x0
#define MX8MP_IOMUXC_SD1_DATA1__ENET1_RGMII_TD0 0x098 0x2F8 0x000 0x1 0x0
#define MX8MP_IOMUXC_SD1_DATA1__I2C6_SDA 0x098 0x2F8 0x5D0 0x3 0x0
#define MX8MP_IOMUXC_SD1_DATA1__UART1_DCE_CTS 0x098 0x2F8 0x000 0x4 0x0
#define MX8MP_IOMUXC_SD1_DATA1__UART1_DTE_RTS 0x098 0x2F8 0x5E4 0x4 0x1
#define MX8MP_IOMUXC_SD1_DATA1__GPIO2_IO03 0x098 0x2F8 0x000 0x5 0x0
#define MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x09C 0x2FC 0x000 0x0 0x0
#define MX8MP_IOMUXC_SD1_DATA2__ENET1_RGMII_RD0 0x09C 0x2FC 0x580 0x1 0x0
#define MX8MP_IOMUXC_SD1_DATA2__I2C4_SCL 0x09C 0x2FC 0x5BC 0x3 0x0
#define MX8MP_IOMUXC_SD1_DATA2__UART2_DCE_TX 0x09C 0x2FC 0x000 0x4 0x0
#define MX8MP_IOMUXC_SD1_DATA2__UART2_DTE_RX 0x09C 0x2FC 0x5F0 0x4 0x0
#define MX8MP_IOMUXC_SD1_DATA2__GPIO2_IO04 0x09C 0x2FC 0x000 0x5 0x0
#define MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x0A0 0x300 0x000 0x0 0x0
#define MX8MP_IOMUXC_SD1_DATA3__ENET1_RGMII_RD1 0x0A0 0x300 0x584 0x1 0x0
#define MX8MP_IOMUXC_SD1_DATA3__I2C4_SDA 0x0A0 0x300 0x5C0 0x3 0x0
#define MX8MP_IOMUXC_SD1_DATA3__UART2_DCE_RX 0x0A0 0x300 0x5F0 0x4 0x1
#define MX8MP_IOMUXC_SD1_DATA3__UART2_DTE_TX 0x0A0 0x300 0x000 0x4 0x0
#define MX8MP_IOMUXC_SD1_DATA3__GPIO2_IO05 0x0A0 0x300 0x000 0x5 0x0
#define MX8MP_IOMUXC_SD1_DATA4__USDHC1_DATA4 0x0A4 0x304 0x000 0x0 0x0
#define MX8MP_IOMUXC_SD1_DATA4__ENET1_RGMII_TX_CTL 0x0A4 0x304 0x000 0x1 0x0
#define MX8MP_IOMUXC_SD1_DATA4__I2C1_SCL 0x0A4 0x304 0x5A4 0x3 0x0
#define MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS 0x0A4 0x304 0x5EC 0x4 0x0
#define MX8MP_IOMUXC_SD1_DATA4__UART2_DTE_CTS 0x0A4 0x304 0x000 0x4 0x0
#define MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x0A4 0x304 0x000 0x5 0x0
#define MX8MP_IOMUXC_SD1_DATA5__USDHC1_DATA5 0x0A8 0x308 0x000 0x0 0x0
#define MX8MP_IOMUXC_SD1_DATA5__ENET1_TX_ER 0x0A8 0x308 0x000 0x1 0x0
#define MX8MP_IOMUXC_SD1_DATA5__I2C1_SDA 0x0A8 0x308 0x5A8 0x3 0x0
#define MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS 0x0A8 0x308 0x000 0x4 0x0
#define MX8MP_IOMUXC_SD1_DATA5__UART2_DTE_RTS 0x0A8 0x308 0x5EC 0x4 0x1
#define MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x0A8 0x308 0x000 0x5 0x0
#define MX8MP_IOMUXC_SD1_DATA6__USDHC1_DATA6 0x0AC 0x30C 0x000 0x0 0x0
#define MX8MP_IOMUXC_SD1_DATA6__ENET1_RGMII_RX_CTL 0x0AC 0x30C 0x588 0x1 0x0
#define MX8MP_IOMUXC_SD1_DATA6__I2C2_SCL 0x0AC 0x30C 0x5AC 0x3 0x0
#define MX8MP_IOMUXC_SD1_DATA6__UART3_DCE_TX 0x0AC 0x30C 0x000 0x4 0x0
#define MX8MP_IOMUXC_SD1_DATA6__UART3_DTE_RX 0x0AC 0x30C 0x5F8 0x4 0x0
#define MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0x0AC 0x30C 0x000 0x5 0x0
#define MX8MP_IOMUXC_SD1_DATA7__USDHC1_DATA7 0x0B0 0x310 0x000 0x0 0x0
#define MX8MP_IOMUXC_SD1_DATA7__ENET1_RX_ER 0x0B0 0x310 0x58C 0x1 0x0
#define MX8MP_IOMUXC_SD1_DATA7__I2C2_SDA 0x0B0 0x310 0x5B0 0x3 0x0
#define MX8MP_IOMUXC_SD1_DATA7__UART3_DCE_RX 0x0B0 0x310 0x5F8 0x4 0x1
#define MX8MP_IOMUXC_SD1_DATA7__UART3_DTE_TX 0x0B0 0x310 0x000 0x4 0x0
#define MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x0B0 0x310 0x000 0x5 0x0
#define MX8MP_IOMUXC_SD1_RESET_B__USDHC1_RESET_B 0x0B4 0x314 0x000 0x0 0x0
#define MX8MP_IOMUXC_SD1_RESET_B__ENET1_TX_CLK 0x0B4 0x314 0x578 0x1 0x0
#define MX8MP_IOMUXC_SD1_RESET_B__I2C3_SCL 0x0B4 0x314 0x5B4 0x3 0x0
#define MX8MP_IOMUXC_SD1_RESET_B__UART3_DCE_RTS 0x0B4 0x314 0x5F4 0x4 0x0
#define MX8MP_IOMUXC_SD1_RESET_B__UART3_DTE_CTS 0x0B4 0x314 0x000 0x4 0x0
#define MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x0B4 0x314 0x000 0x5 0x0
#define MX8MP_IOMUXC_SD1_STROBE__USDHC1_STROBE 0x0B8 0x318 0x000 0x0 0x0
#define MX8MP_IOMUXC_SD1_STROBE__I2C3_SDA 0x0B8 0x318 0x5B8 0x3 0x0
#define MX8MP_IOMUXC_SD1_STROBE__UART3_DCE_CTS 0x0B8 0x318 0x000 0x4 0x0
#define MX8MP_IOMUXC_SD1_STROBE__UART3_DTE_RTS 0x0B8 0x318 0x5F4 0x4 0x1
#define MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x0B8 0x318 0x000 0x5 0x0
#define MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B 0x0BC 0x31C 0x000 0x0 0x0
#define MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x0BC 0x31C 0x000 0x5 0x0
#define MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x0C0 0x320 0x000 0x0 0x0
#define MX8MP_IOMUXC_SD2_CLK__ECSPI2_SCLK 0x0C0 0x320 0x568 0x2 0x0
#define MX8MP_IOMUXC_SD2_CLK__UART4_DCE_RX 0x0C0 0x320 0x600 0x3 0x0
#define MX8MP_IOMUXC_SD2_CLK__UART4_DTE_TX 0x0C0 0x320 0x000 0x3 0x0
#define MX8MP_IOMUXC_SD2_CLK__GPIO2_IO13 0x0C0 0x320 0x000 0x5 0x0
#define MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x0C4 0x324 0x000 0x0 0x0
#define MX8MP_IOMUXC_SD2_CMD__ECSPI2_MOSI 0x0C4 0x324 0x570 0x2 0x0
#define MX8MP_IOMUXC_SD2_CMD__UART4_DCE_TX 0x0C4 0x324 0x000 0x3 0x0
#define MX8MP_IOMUXC_SD2_CMD__UART4_DTE_RX 0x0C4 0x324 0x600 0x3 0x1
#define MX8MP_IOMUXC_SD2_CMD__AUDIOMIX_PDM_CLK 0x0C4 0x324 0x000 0x4 0x0
#define MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14 0x0C4 0x324 0x000 0x5 0x0
#define MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x0C8 0x328 0x000 0x0 0x0
#define MX8MP_IOMUXC_SD2_DATA0__I2C4_SDA 0x0C8 0x328 0x5C0 0x2 0x1
#define MX8MP_IOMUXC_SD2_DATA0__UART2_DCE_RX 0x0C8 0x328 0x5F0 0x3 0x2
#define MX8MP_IOMUXC_SD2_DATA0__UART2_DTE_TX 0x0C8 0x328 0x000 0x3 0x0
#define MX8MP_IOMUXC_SD2_DATA0__AUDIOMIX_PDM_BIT_STREAM00 0x0C8 0x328 0x4C0 0x4 0x2
#define MX8MP_IOMUXC_SD2_DATA0__GPIO2_IO15 0x0C8 0x328 0x000 0x5 0x0
#define MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x0CC 0x32C 0x000 0x0 0x0
#define MX8MP_IOMUXC_SD2_DATA1__I2C4_SCL 0x0CC 0x32C 0x5BC 0x2 0x1
#define MX8MP_IOMUXC_SD2_DATA1__UART2_DCE_TX 0x0CC 0x32C 0x000 0x3 0x0
#define MX8MP_IOMUXC_SD2_DATA1__UART2_DTE_RX 0x0CC 0x32C 0x5F0 0x3 0x3
#define MX8MP_IOMUXC_SD2_DATA1__AUDIOMIX_PDM_BIT_STREAM01 0x0CC 0x32C 0x4C4 0x4 0x2
#define MX8MP_IOMUXC_SD2_DATA1__GPIO2_IO16 0x0CC 0x32C 0x000 0x5 0x0
#define MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x0D0 0x330 0x000 0x0 0x0
#define MX8MP_IOMUXC_SD2_DATA2__ECSPI2_SS0 0x0D0 0x330 0x574 0x2 0x0
#define MX8MP_IOMUXC_SD2_DATA2__AUDIOMIX_SPDIF1_OUT 0x0D0 0x330 0x000 0x3 0x0
#define MX8MP_IOMUXC_SD2_DATA2__AUDIOMIX_PDM_BIT_STREAM02 0x0D0 0x330 0x4C8 0x4 0x2
#define MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17 0x0D0 0x330 0x000 0x5 0x0
#define MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x0D4 0x334 0x000 0x0 0x0
#define MX8MP_IOMUXC_SD2_DATA3__ECSPI2_MISO 0x0D4 0x334 0x56C 0x2 0x0
#define MX8MP_IOMUXC_SD2_DATA3__AUDIOMIX_SPDIF1_IN 0x0D4 0x334 0x544 0x3 0x1
#define MX8MP_IOMUXC_SD2_DATA3__AUDIOMIX_PDM_BIT_STREAM03 0x0D4 0x334 0x4CC 0x4 0x2
#define MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 0x0D4 0x334 0x000 0x5 0x0
#define MX8MP_IOMUXC_SD2_DATA3__SRC_EARLY_RESET 0x0D4 0x334 0x000 0x6 0x0
#define MX8MP_IOMUXC_SD2_RESET_B__USDHC2_RESET_B 0x0D8 0x338 0x000 0x0 0x0
#define MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x0D8 0x338 0x000 0x5 0x0
#define MX8MP_IOMUXC_SD2_RESET_B__SRC_SYSTEM_RESET 0x0D8 0x338 0x000 0x6 0x0
#define MX8MP_IOMUXC_SD2_WP__USDHC2_WP 0x0DC 0x33C 0x000 0x0 0x0
#define MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x0DC 0x33C 0x000 0x5 0x0
#define MX8MP_IOMUXC_SD2_WP__CORESIGHT_EVENTI 0x0DC 0x33C 0x000 0x6 0x0
#define MX8MP_IOMUXC_NAND_ALE__NAND_ALE 0x0E0 0x340 0x000 0x0 0x0
#define MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x0E0 0x340 0x000 0x1 0x0
#define MX8MP_IOMUXC_NAND_ALE__AUDIOMIX_SAI3_TX_BCLK 0x0E0 0x340 0x4E8 0x2 0x0
#define MX8MP_IOMUXC_NAND_ALE__ISP_FL_TRIG_0 0x0E0 0x340 0x5D4 0x3 0x1
#define MX8MP_IOMUXC_NAND_ALE__UART3_DCE_RX 0x0E0 0x340 0x5F8 0x4 0x2
#define MX8MP_IOMUXC_NAND_ALE__UART3_DTE_TX 0x0E0 0x340 0x000 0x4 0x0
#define MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x0E0 0x340 0x000 0x5 0x0
#define MX8MP_IOMUXC_NAND_ALE__CORESIGHT_TRACE_CLK 0x0E0 0x340 0x000 0x6 0x0
#define MX8MP_IOMUXC_NAND_CE0_B__NAND_CE0_B 0x0E4 0x344 0x000 0x0 0x0
#define MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x0E4 0x344 0x000 0x1 0x0
#define MX8MP_IOMUXC_NAND_CE0_B__AUDIOMIX_SAI3_TX_DATA00 0x0E4 0x344 0x000 0x2 0x0
#define MX8MP_IOMUXC_NAND_CE0_B__ISP_SHUTTER_TRIG_0 0x0E4 0x344 0x5DC 0x3 0x1
#define MX8MP_IOMUXC_NAND_CE0_B__UART3_DCE_TX 0x0E4 0x344 0x000 0x4 0x0
#define MX8MP_IOMUXC_NAND_CE0_B__UART3_DTE_RX 0x0E4 0x344 0x5F8 0x4 0x3
#define MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x0E4 0x344 0x000 0x5 0x0
#define MX8MP_IOMUXC_NAND_CE0_B__CORESIGHT_TRACE_CTL 0x0E4 0x344 0x000 0x6 0x0
#define MX8MP_IOMUXC_NAND_CE1_B__NAND_CE1_B 0x0E8 0x348 0x000 0x0 0x0
#define MX8MP_IOMUXC_NAND_CE1_B__FLEXSPI_A_SS1_B 0x0E8 0x348 0x000 0x1 0x0
#define MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x0E8 0x348 0x630 0x2 0x1
#define MX8MP_IOMUXC_NAND_CE1_B__I2C4_SCL 0x0E8 0x348 0x5BC 0x4 0x2
#define MX8MP_IOMUXC_NAND_CE1_B__GPIO3_IO02 0x0E8 0x348 0x000 0x5 0x0
#define MX8MP_IOMUXC_NAND_CE1_B__CORESIGHT_TRACE00 0x0E8 0x348 0x000 0x6 0x0
#define MX8MP_IOMUXC_NAND_CE2_B__NAND_CE2_B 0x0EC 0x34C 0x000 0x0 0x0
#define MX8MP_IOMUXC_NAND_CE2_B__FLEXSPI_B_SS0_B 0x0EC 0x34C 0x000 0x1 0x0
#define MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x0EC 0x34C 0x624 0x2 0x1
#define MX8MP_IOMUXC_NAND_CE2_B__I2C4_SDA 0x0EC 0x34C 0x5C0 0x4 0x2
#define MX8MP_IOMUXC_NAND_CE2_B__GPIO3_IO03 0x0EC 0x34C 0x000 0x5 0x0
#define MX8MP_IOMUXC_NAND_CE2_B__CORESIGHT_TRACE01 0x0EC 0x34C 0x000 0x6 0x0
#define MX8MP_IOMUXC_NAND_CE3_B__NAND_CE3_B 0x0F0 0x350 0x000 0x0 0x0
#define MX8MP_IOMUXC_NAND_CE3_B__FLEXSPI_B_SS1_B 0x0F0 0x350 0x000 0x1 0x0
#define MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x0F0 0x350 0x628 0x2 0x1
#define MX8MP_IOMUXC_NAND_CE3_B__I2C3_SDA 0x0F0 0x350 0x5B8 0x4 0x1
#define MX8MP_IOMUXC_NAND_CE3_B__GPIO3_IO04 0x0F0 0x350 0x000 0x5 0x0
#define MX8MP_IOMUXC_NAND_CE3_B__CORESIGHT_TRACE02 0x0F0 0x350 0x000 0x6 0x0
#define MX8MP_IOMUXC_NAND_CLE__NAND_CLE 0x0F4 0x354 0x000 0x0 0x0
#define MX8MP_IOMUXC_NAND_CLE__FLEXSPI_B_SCLK 0x0F4 0x354 0x000 0x1 0x0
#define MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x0F4 0x354 0x62C 0x2 0x1
#define MX8MP_IOMUXC_NAND_CLE__UART4_DCE_RX 0x0F4 0x354 0x600 0x4 0x2
#define MX8MP_IOMUXC_NAND_CLE__UART4_DTE_TX 0x0F4 0x354 0x000 0x4 0x0
#define MX8MP_IOMUXC_NAND_CLE__GPIO3_IO05 0x0F4 0x354 0x000 0x5 0x0
#define MX8MP_IOMUXC_NAND_CLE__CORESIGHT_TRACE03 0x0F4 0x354 0x000 0x6 0x0
#define MX8MP_IOMUXC_NAND_DATA00__NAND_DATA00 0x0F8 0x358 0x000 0x0 0x0
#define MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x0F8 0x358 0x000 0x1 0x0
#define MX8MP_IOMUXC_NAND_DATA00__AUDIOMIX_SAI3_RX_DATA00 0x0F8 0x358 0x4E4 0x2 0x0
#define MX8MP_IOMUXC_NAND_DATA00__ISP_FLASH_TRIG_0 0x0F8 0x358 0x000 0x3 0x0
#define MX8MP_IOMUXC_NAND_DATA00__UART4_DCE_RX 0x0F8 0x358 0x600 0x4 0x3
#define MX8MP_IOMUXC_NAND_DATA00__UART4_DTE_TX 0x0F8 0x358 0x000 0x4 0x0
#define MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x0F8 0x358 0x000 0x5 0x0
#define MX8MP_IOMUXC_NAND_DATA00__CORESIGHT_TRACE04 0x0F8 0x358 0x000 0x6 0x0
#define MX8MP_IOMUXC_NAND_DATA01__NAND_DATA01 0x0FC 0x35C 0x000 0x0 0x0
#define MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x0FC 0x35C 0x000 0x1 0x0
#define MX8MP_IOMUXC_NAND_DATA01__AUDIOMIX_SAI3_TX_SYNC 0x0FC 0x35C 0x4EC 0x2 0x0
#define MX8MP_IOMUXC_NAND_DATA01__ISP_PRELIGHT_TRIG_0 0x0FC 0x35C 0x000 0x3 0x0
#define MX8MP_IOMUXC_NAND_DATA01__UART4_DCE_TX 0x0FC 0x35C 0x000 0x4 0x0
#define MX8MP_IOMUXC_NAND_DATA01__UART4_DTE_RX 0x0FC 0x35C 0x600 0x4 0x4
#define MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x0FC 0x35C 0x000 0x5 0x0
#define MX8MP_IOMUXC_NAND_DATA01__CORESIGHT_TRACE05 0x0FC 0x35C 0x000 0x6 0x0
#define MX8MP_IOMUXC_NAND_DATA02__NAND_DATA02 0x100 0x360 0x000 0x0 0x0
#define MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x100 0x360 0x000 0x1 0x0
#define MX8MP_IOMUXC_NAND_DATA02__USDHC3_CD_B 0x100 0x360 0x608 0x2 0x2
#define MX8MP_IOMUXC_NAND_DATA02__UART4_DCE_CTS 0x100 0x360 0x000 0x3 0x0
#define MX8MP_IOMUXC_NAND_DATA02__UART4_DTE_RTS 0x100 0x360 0x5FC 0x3 0x0
#define MX8MP_IOMUXC_NAND_DATA02__I2C4_SDA 0x100 0x360 0x5C0 0x4 0x3
#define MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x100 0x360 0x000 0x5 0x0
#define MX8MP_IOMUXC_NAND_DATA02__CORESIGHT_TRACE06 0x100 0x360 0x000 0x6 0x0
#define MX8MP_IOMUXC_NAND_DATA03__NAND_DATA03 0x104 0x364 0x000 0x0 0x0
#define MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x104 0x364 0x000 0x1 0x0
#define MX8MP_IOMUXC_NAND_DATA03__USDHC3_WP 0x104 0x364 0x634 0x2 0x2
#define MX8MP_IOMUXC_NAND_DATA03__UART4_DCE_RTS 0x104 0x364 0x5FC 0x3 0x1
#define MX8MP_IOMUXC_NAND_DATA03__UART4_DTE_CTS 0x104 0x364 0x000 0x3 0x0
#define MX8MP_IOMUXC_NAND_DATA03__ISP_FL_TRIG_1 0x104 0x364 0x5D8 0x4 0x1
#define MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x104 0x364 0x000 0x5 0x0
#define MX8MP_IOMUXC_NAND_DATA03__CORESIGHT_TRACE07 0x104 0x364 0x000 0x6 0x0
#define MX8MP_IOMUXC_NAND_DATA04__NAND_DATA04 0x108 0x368 0x000 0x0 0x0
#define MX8MP_IOMUXC_NAND_DATA04__FLEXSPI_B_DATA00 0x108 0x368 0x000 0x1 0x0
#define MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x108 0x368 0x610 0x2 0x1
#define MX8MP_IOMUXC_NAND_DATA04__FLEXSPI_A_DATA04 0x108 0x368 0x000 0x3 0x0
#define MX8MP_IOMUXC_NAND_DATA04__ISP_SHUTTER_TRIG_1 0x108 0x368 0x5E0 0x4 0x1
#define MX8MP_IOMUXC_NAND_DATA04__GPIO3_IO10 0x108 0x368 0x000 0x5 0x0
#define MX8MP_IOMUXC_NAND_DATA04__CORESIGHT_TRACE08 0x108 0x368 0x000 0x6 0x0
#define MX8MP_IOMUXC_NAND_DATA05__NAND_DATA05 0x10C 0x36C 0x000 0x0 0x0
#define MX8MP_IOMUXC_NAND_DATA05__FLEXSPI_B_DATA01 0x10C 0x36C 0x000 0x1 0x0
#define MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x10C 0x36C 0x614 0x2 0x1
#define MX8MP_IOMUXC_NAND_DATA05__FLEXSPI_A_DATA05 0x10C 0x36C 0x000 0x3 0x0
#define MX8MP_IOMUXC_NAND_DATA05__ISP_FLASH_TRIG_1 0x10C 0x36C 0x000 0x4 0x0
#define MX8MP_IOMUXC_NAND_DATA05__GPIO3_IO11 0x10C 0x36C 0x000 0x5 0x0
#define MX8MP_IOMUXC_NAND_DATA05__CORESIGHT_TRACE09 0x10C 0x36C 0x000 0x6 0x0
#define MX8MP_IOMUXC_NAND_DATA06__NAND_DATA06 0x110 0x370 0x000 0x0 0x0
#define MX8MP_IOMUXC_NAND_DATA06__FLEXSPI_B_DATA02 0x110 0x370 0x000 0x1 0x0
#define MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x110 0x370 0x618 0x2 0x1
#define MX8MP_IOMUXC_NAND_DATA06__FLEXSPI_A_DATA06 0x110 0x370 0x000 0x3 0x0
#define MX8MP_IOMUXC_NAND_DATA06__ISP_PRELIGHT_TRIG_1 0x110 0x370 0x000 0x4 0x0
#define MX8MP_IOMUXC_NAND_DATA06__GPIO3_IO12 0x110 0x370 0x000 0x5 0x0
#define MX8MP_IOMUXC_NAND_DATA06__CORESIGHT_TRACE10 0x110 0x370 0x000 0x6 0x0
#define MX8MP_IOMUXC_NAND_DATA07__NAND_DATA07 0x114 0x374 0x000 0x0 0x0
#define MX8MP_IOMUXC_NAND_DATA07__FLEXSPI_B_DATA03 0x114 0x374 0x000 0x1 0x0
#define MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x114 0x374 0x61C 0x2 0x1
#define MX8MP_IOMUXC_NAND_DATA07__FLEXSPI_A_DATA07 0x114 0x374 0x000 0x3 0x0
#define MX8MP_IOMUXC_NAND_DATA07__ISP_SHUTTER_OPEN_1 0x114 0x374 0x000 0x4 0x0
#define MX8MP_IOMUXC_NAND_DATA07__GPIO3_IO13 0x114 0x374 0x000 0x5 0x0
#define MX8MP_IOMUXC_NAND_DATA07__CORESIGHT_TRACE11 0x114 0x374 0x000 0x6 0x0
#define MX8MP_IOMUXC_NAND_DQS__NAND_DQS 0x118 0x378 0x000 0x0 0x0
#define MX8MP_IOMUXC_NAND_DQS__FLEXSPI_A_DQS 0x118 0x378 0x000 0x1 0x0
#define MX8MP_IOMUXC_NAND_DQS__AUDIOMIX_SAI3_MCLK 0x118 0x378 0x4E0 0x2 0x0
#define MX8MP_IOMUXC_NAND_DQS__ISP_SHUTTER_OPEN_0 0x118 0x378 0x000 0x3 0x0
#define MX8MP_IOMUXC_NAND_DQS__I2C3_SCL 0x118 0x378 0x5B4 0x4 0x1
#define MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x118 0x378 0x000 0x5 0x0
#define MX8MP_IOMUXC_NAND_DQS__CORESIGHT_TRACE12 0x118 0x378 0x000 0x6 0x0
#define MX8MP_IOMUXC_NAND_RE_B__NAND_RE_B 0x11C 0x37C 0x000 0x0 0x0
#define MX8MP_IOMUXC_NAND_RE_B__FLEXSPI_B_DQS 0x11C 0x37C 0x000 0x1 0x0
#define MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x11C 0x37C 0x620 0x2 0x1
#define MX8MP_IOMUXC_NAND_RE_B__UART4_DCE_TX 0x11C 0x37C 0x000 0x4 0x0
#define MX8MP_IOMUXC_NAND_RE_B__UART4_DTE_RX 0x11C 0x37C 0x600 0x4 0x5
#define MX8MP_IOMUXC_NAND_RE_B__GPIO3_IO15 0x11C 0x37C 0x000 0x5 0x0
#define MX8MP_IOMUXC_NAND_RE_B__CORESIGHT_TRACE13 0x11C 0x37C 0x000 0x6 0x0
#define MX8MP_IOMUXC_NAND_READY_B__NAND_READY_B 0x120 0x380 0x000 0x0 0x0
#define MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x120 0x380 0x000 0x2 0x0
#define MX8MP_IOMUXC_NAND_READY_B__I2C3_SCL 0x120 0x380 0x5B4 0x4 0x2
#define MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x120 0x380 0x000 0x5 0x0
#define MX8MP_IOMUXC_NAND_READY_B__CORESIGHT_TRACE14 0x120 0x380 0x000 0x6 0x0
#define MX8MP_IOMUXC_NAND_WE_B__NAND_WE_B 0x124 0x384 0x000 0x0 0x0
#define MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x124 0x384 0x604 0x2 0x1
#define MX8MP_IOMUXC_NAND_WE_B__I2C3_SDA 0x124 0x384 0x5B8 0x4 0x2
#define MX8MP_IOMUXC_NAND_WE_B__GPIO3_IO17 0x124 0x384 0x000 0x5 0x0
#define MX8MP_IOMUXC_NAND_WE_B__CORESIGHT_TRACE15 0x124 0x384 0x000 0x6 0x0
#define MX8MP_IOMUXC_NAND_WP_B__NAND_WP_B 0x128 0x388 0x000 0x0 0x0
#define MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x128 0x388 0x60C 0x2 0x1
#define MX8MP_IOMUXC_NAND_WP_B__I2C4_SCL 0x128 0x388 0x5BC 0x4 0x3
#define MX8MP_IOMUXC_NAND_WP_B__GPIO3_IO18 0x128 0x388 0x000 0x5 0x0
#define MX8MP_IOMUXC_NAND_WP_B__CORESIGHT_EVENTO 0x128 0x388 0x000 0x6 0x0
#define MX8MP_IOMUXC_SAI5_RXFS__AUDIOMIX_SAI5_RX_SYNC 0x12C 0x38C 0x508 0x0 0x0
#define MX8MP_IOMUXC_SAI5_RXFS__AUDIOMIX_SAI1_TX_DATA00 0x12C 0x38C 0x000 0x1 0x0
#define MX8MP_IOMUXC_SAI5_RXFS__PWM4_OUT 0x12C 0x38C 0x000 0x2 0x0
#define MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL 0x12C 0x38C 0x5CC 0x3 0x1
#define MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x12C 0x38C 0x000 0x5 0x0
#define MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_SAI5_RX_BCLK 0x130 0x390 0x4F4 0x0 0x0
#define MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_SAI1_TX_DATA01 0x130 0x390 0x000 0x1 0x0
#define MX8MP_IOMUXC_SAI5_RXC__PWM3_OUT 0x130 0x390 0x000 0x2 0x0
#define MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA 0x130 0x390 0x5D0 0x3 0x1
#define MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_PDM_CLK 0x130 0x390 0x000 0x4 0x0
#define MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x130 0x390 0x000 0x5 0x0
#define MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_SAI5_RX_DATA00 0x134 0x394 0x4F8 0x0 0x0
#define MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_SAI1_TX_DATA02 0x134 0x394 0x000 0x1 0x0
#define MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT 0x134 0x394 0x000 0x2 0x0
#define MX8MP_IOMUXC_SAI5_RXD0__I2C5_SCL 0x134 0x394 0x5C4 0x3 0x1
#define MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_PDM_BIT_STREAM00 0x134 0x394 0x4C0 0x4 0x3
#define MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x134 0x394 0x000 0x5 0x0
#define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI5_RX_DATA01 0x138 0x398 0x4FC 0x0 0x0
#define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_DATA03 0x138 0x398 0x000 0x1 0x0
#define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_SYNC 0x138 0x398 0x4D8 0x2 0x0
#define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI5_TX_SYNC 0x138 0x398 0x510 0x3 0x0
#define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_PDM_BIT_STREAM01 0x138 0x398 0x4C4 0x4 0x3
#define MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22 0x138 0x398 0x000 0x5 0x0
#define MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x138 0x398 0x000 0x6 0x0
#define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI5_RX_DATA02 0x13C 0x39C 0x500 0x0 0x0
#define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI1_TX_DATA04 0x13C 0x39C 0x000 0x1 0x0
#define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI1_TX_SYNC 0x13C 0x39C 0x4D8 0x2 0x1
#define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI5_TX_BCLK 0x13C 0x39C 0x50C 0x3 0x0
#define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_PDM_BIT_STREAM02 0x13C 0x39C 0x4C8 0x4 0x3
#define MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 0x13C 0x39C 0x000 0x5 0x0
#define MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x13C 0x39C 0x54C 0x6 0x0
#define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI5_RX_DATA03 0x140 0x3A0 0x504 0x0 0x0
#define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI1_TX_DATA05 0x140 0x3A0 0x000 0x1 0x0
#define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI1_TX_SYNC 0x140 0x3A0 0x4D8 0x2 0x2
#define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI5_TX_DATA00 0x140 0x3A0 0x000 0x3 0x0
#define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_PDM_BIT_STREAM03 0x140 0x3A0 0x4CC 0x4 0x3
#define MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 0x140 0x3A0 0x000 0x5 0x0
#define MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x140 0x3A0 0x000 0x6 0x0
#define MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI5_MCLK 0x144 0x3A4 0x4F0 0x0 0x0
#define MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI1_TX_BCLK 0x144 0x3A4 0x4D4 0x1 0x0
#define MX8MP_IOMUXC_SAI5_MCLK__PWM1_OUT 0x144 0x3A4 0x000 0x2 0x0
#define MX8MP_IOMUXC_SAI5_MCLK__I2C5_SDA 0x144 0x3A4 0x5C8 0x3 0x1
#define MX8MP_IOMUXC_SAI5_MCLK__GPIO3_IO25 0x144 0x3A4 0x000 0x5 0x0
#define MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x144 0x3A4 0x550 0x6 0x0
#define MX8MP_IOMUXC_SAI1_RXFS__AUDIOMIX_SAI1_RX_SYNC 0x148 0x3A8 0x4D0 0x0 0x0
#define MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x148 0x3A8 0x000 0x4 0x0
#define MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x148 0x3A8 0x000 0x5 0x0
#define MX8MP_IOMUXC_SAI1_RXC__AUDIOMIX_SAI1_RX_BCLK 0x14C 0x3AC 0x000 0x0 0x0
#define MX8MP_IOMUXC_SAI1_RXC__AUDIOMIX_PDM_CLK 0x14C 0x3AC 0x000 0x3 0x0
#define MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x14C 0x3AC 0x000 0x4 0x0
#define MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x14C 0x3AC 0x000 0x5 0x0
#define MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_RX_DATA00 0x150 0x3B0 0x000 0x0 0x0
#define MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_TX_DATA01 0x150 0x3B0 0x000 0x2 0x0
#define MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_PDM_BIT_STREAM00 0x150 0x3B0 0x4C0 0x3 0x4
#define MX8MP_IOMUXC_SAI1_RXD0__ENET1_1588_EVENT1_IN 0x150 0x3B0 0x000 0x4 0x0
#define MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x150 0x3B0 0x000 0x5 0x0
#define MX8MP_IOMUXC_SAI1_RXD1__AUDIOMIX_SAI1_RX_DATA01 0x154 0x3B4 0x000 0x0 0x0
#define MX8MP_IOMUXC_SAI1_RXD1__AUDIOMIX_PDM_BIT_STREAM01 0x154 0x3B4 0x4C4 0x3 0x4
#define MX8MP_IOMUXC_SAI1_RXD1__ENET1_1588_EVENT1_OUT 0x154 0x3B4 0x000 0x4 0x0
#define MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x154 0x3B4 0x000 0x5 0x0
#define MX8MP_IOMUXC_SAI1_RXD2__AUDIOMIX_SAI1_RX_DATA02 0x158 0x3B8 0x000 0x0 0x0
#define MX8MP_IOMUXC_SAI1_RXD2__AUDIOMIX_PDM_BIT_STREAM02 0x158 0x3B8 0x4C8 0x3 0x4
#define MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x158 0x3B8 0x000 0x4 0x0
#define MX8MP_IOMUXC_SAI1_RXD2__GPIO4_IO04 0x158 0x3B8 0x000 0x5 0x0
#define MX8MP_IOMUXC_SAI1_RXD3__AUDIOMIX_SAI1_RX_DATA03 0x15C 0x3BC 0x000 0x0 0x0
#define MX8MP_IOMUXC_SAI1_RXD3__AUDIOMIX_PDM_BIT_STREAM03 0x15C 0x3BC 0x4CC 0x3 0x4
#define MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x15C 0x3BC 0x57C 0x4 0x1
#define MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x15C 0x3BC 0x000 0x5 0x0
#define MX8MP_IOMUXC_SAI1_RXD4__AUDIOMIX_SAI1_RX_DATA04 0x160 0x3C0 0x000 0x0 0x0
#define MX8MP_IOMUXC_SAI1_RXD4__AUDIOMIX_SAI6_TX_BCLK 0x160 0x3C0 0x524 0x1 0x1
#define MX8MP_IOMUXC_SAI1_RXD4__AUDIOMIX_SAI6_RX_BCLK 0x160 0x3C0 0x518 0x2 0x1
#define MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x160 0x3C0 0x580 0x4 0x1
#define MX8MP_IOMUXC_SAI1_RXD4__GPIO4_IO06 0x160 0x3C0 0x000 0x5 0x0
#define MX8MP_IOMUXC_SAI1_RXD5__AUDIOMIX_SAI1_RX_DATA05 0x164 0x3C4 0x000 0x0 0x0
#define MX8MP_IOMUXC_SAI1_RXD5__AUDIOMIX_SAI6_TX_DATA00 0x164 0x3C4 0x000 0x1 0x0
#define MX8MP_IOMUXC_SAI1_RXD5__AUDIOMIX_SAI6_RX_DATA00 0x164 0x3C4 0x51C 0x2 0x1
#define MX8MP_IOMUXC_SAI1_RXD5__AUDIOMIX_SAI1_RX_SYNC 0x164 0x3C4 0x4D0 0x3 0x1
#define MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x164 0x3C4 0x584 0x4 0x1
#define MX8MP_IOMUXC_SAI1_RXD5__GPIO4_IO07 0x164 0x3C4 0x000 0x5 0x0
#define MX8MP_IOMUXC_SAI1_RXD6__AUDIOMIX_SAI1_RX_DATA06 0x168 0x3C8 0x000 0x0 0x0
#define MX8MP_IOMUXC_SAI1_RXD6__AUDIOMIX_SAI6_TX_SYNC 0x168 0x3C8 0x528 0x1 0x1
#define MX8MP_IOMUXC_SAI1_RXD6__AUDIOMIX_SAI6_RX_SYNC 0x168 0x3C8 0x520 0x2 0x1
#define MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x168 0x3C8 0x000 0x4 0x0
#define MX8MP_IOMUXC_SAI1_RXD6__GPIO4_IO08 0x168 0x3C8 0x000 0x5 0x0
#define MX8MP_IOMUXC_SAI1_RXD7__AUDIOMIX_SAI1_RX_DATA07 0x16C 0x3CC 0x000 0x0 0x0
#define MX8MP_IOMUXC_SAI1_RXD7__AUDIOMIX_SAI6_MCLK 0x16C 0x3CC 0x514 0x1 0x1
#define MX8MP_IOMUXC_SAI1_RXD7__AUDIOMIX_SAI1_TX_SYNC 0x16C 0x3CC 0x4D8 0x2 0x3
#define MX8MP_IOMUXC_SAI1_RXD7__AUDIOMIX_SAI1_TX_DATA04 0x16C 0x3CC 0x000 0x3 0x0
#define MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x16C 0x3CC 0x000 0x4 0x0
#define MX8MP_IOMUXC_SAI1_RXD7__GPIO4_IO09 0x16C 0x3CC 0x000 0x5 0x0
#define MX8MP_IOMUXC_SAI1_TXFS__AUDIOMIX_SAI1_TX_SYNC 0x170 0x3D0 0x4D8 0x0 0x4
#define MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x170 0x3D0 0x588 0x4 0x1
#define MX8MP_IOMUXC_SAI1_TXFS__GPIO4_IO10 0x170 0x3D0 0x000 0x5 0x0
#define MX8MP_IOMUXC_SAI1_TXC__AUDIOMIX_SAI1_TX_BCLK 0x174 0x3D4 0x4D4 0x0 0x1
#define MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x174 0x3D4 0x000 0x4 0x0
#define MX8MP_IOMUXC_SAI1_TXC__GPIO4_IO11 0x174 0x3D4 0x000 0x5 0x0
#define MX8MP_IOMUXC_SAI1_TXD0__AUDIOMIX_SAI1_TX_DATA00 0x178 0x3D8 0x000 0x0 0x0
#define MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x178 0x3D8 0x000 0x4 0x0
#define MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x178 0x3D8 0x000 0x5 0x0
#define MX8MP_IOMUXC_SAI1_TXD1__AUDIOMIX_SAI1_TX_DATA01 0x17C 0x3DC 0x000 0x0 0x0
#define MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x17C 0x3DC 0x000 0x4 0x0
#define MX8MP_IOMUXC_SAI1_TXD1__GPIO4_IO13 0x17C 0x3DC 0x000 0x5 0x0
#define MX8MP_IOMUXC_SAI1_TXD2__AUDIOMIX_SAI1_TX_DATA02 0x180 0x3E0 0x000 0x0 0x0
#define MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x180 0x3E0 0x000 0x4 0x0
#define MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14 0x180 0x3E0 0x000 0x5 0x0
#define MX8MP_IOMUXC_SAI1_TXD3__AUDIOMIX_SAI1_TX_DATA03 0x184 0x3E4 0x000 0x0 0x0
#define MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x184 0x3E4 0x000 0x4 0x0
#define MX8MP_IOMUXC_SAI1_TXD3__GPIO4_IO15 0x184 0x3E4 0x000 0x5 0x0
#define MX8MP_IOMUXC_SAI1_TXD4__AUDIOMIX_SAI1_TX_DATA04 0x188 0x3E8 0x000 0x0 0x0
#define MX8MP_IOMUXC_SAI1_TXD4__AUDIOMIX_SAI6_RX_BCLK 0x188 0x3E8 0x518 0x1 0x2
#define MX8MP_IOMUXC_SAI1_TXD4__AUDIOMIX_SAI6_TX_BCLK 0x188 0x3E8 0x524 0x2 0x2
#define MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x188 0x3E8 0x000 0x4 0x0
#define MX8MP_IOMUXC_SAI1_TXD4__GPIO4_IO16 0x188 0x3E8 0x000 0x5 0x0
#define MX8MP_IOMUXC_SAI1_TXD5__AUDIOMIX_SAI1_TX_DATA05 0x18C 0x3EC 0x000 0x0 0x0
#define MX8MP_IOMUXC_SAI1_TXD5__AUDIOMIX_SAI6_RX_DATA00 0x18C 0x3EC 0x51C 0x1 0x2
#define MX8MP_IOMUXC_SAI1_TXD5__AUDIOMIX_SAI6_TX_DATA00 0x18C 0x3EC 0x000 0x2 0x0
#define MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x18C 0x3EC 0x000 0x4 0x0
#define MX8MP_IOMUXC_SAI1_TXD5__GPIO4_IO17 0x18C 0x3EC 0x000 0x5 0x0
#define MX8MP_IOMUXC_SAI1_TXD6__AUDIOMIX_SAI1_TX_DATA06 0x190 0x3F0 0x000 0x0 0x0
#define MX8MP_IOMUXC_SAI1_TXD6__AUDIOMIX_SAI6_RX_SYNC 0x190 0x3F0 0x520 0x1 0x2
#define MX8MP_IOMUXC_SAI1_TXD6__AUDIOMIX_SAI6_TX_SYNC 0x190 0x3F0 0x528 0x2 0x2
#define MX8MP_IOMUXC_SAI1_TXD6__ENET1_RX_ER 0x190 0x3F0 0x58C 0x4 0x1
#define MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x190 0x3F0 0x000 0x5 0x0
#define MX8MP_IOMUXC_SAI1_TXD7__AUDIOMIX_SAI1_TX_DATA07 0x194 0x3F4 0x000 0x0 0x0
#define MX8MP_IOMUXC_SAI1_TXD7__AUDIOMIX_SAI6_MCLK 0x194 0x3F4 0x514 0x1 0x2
#define MX8MP_IOMUXC_SAI1_TXD7__AUDIOMIX_PDM_CLK 0x194 0x3F4 0x000 0x3 0x0
#define MX8MP_IOMUXC_SAI1_TXD7__ENET1_TX_ER 0x194 0x3F4 0x000 0x4 0x0
#define MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x194 0x3F4 0x000 0x5 0x0
#define MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_MCLK 0x198 0x3F8 0x000 0x0 0x0
#define MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_TX_BCLK 0x198 0x3F8 0x4D4 0x2 0x2
#define MX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK 0x198 0x3F8 0x578 0x4 0x1
#define MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x198 0x3F8 0x000 0x5 0x0
#define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_SAI2_RX_SYNC 0x19C 0x3FC 0x000 0x0 0x0
#define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_SAI5_TX_SYNC 0x19C 0x3FC 0x510 0x1 0x2
#define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_SAI5_TX_DATA01 0x19C 0x3FC 0x000 0x2 0x0
#define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_SAI2_RX_DATA01 0x19C 0x3FC 0x4DC 0x3 0x0
#define MX8MP_IOMUXC_SAI2_RXFS__UART1_DCE_TX 0x19C 0x3FC 0x000 0x4 0x0
#define MX8MP_IOMUXC_SAI2_RXFS__UART1_DTE_RX 0x19C 0x3FC 0x5E8 0x4 0x2
#define MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x19C 0x3FC 0x000 0x5 0x0
#define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_PDM_BIT_STREAM02 0x19C 0x3FC 0x4C8 0x6 0x5
#define MX8MP_IOMUXC_SAI2_RXC__AUDIOMIX_SAI2_RX_BCLK 0x1A0 0x400 0x000 0x0 0x0
#define MX8MP_IOMUXC_SAI2_RXC__AUDIOMIX_SAI5_TX_BCLK 0x1A0 0x400 0x50C 0x1 0x2
#define MX8MP_IOMUXC_SAI2_RXC__CAN1_TX 0x1A0 0x400 0x000 0x3 0x0
#define MX8MP_IOMUXC_SAI2_RXC__UART1_DCE_RX 0x1A0 0x400 0x5E8 0x4 0x3
#define MX8MP_IOMUXC_SAI2_RXC__UART1_DTE_TX 0x1A0 0x400 0x000 0x4 0x0
#define MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x1A0 0x400 0x000 0x5 0x0
#define MX8MP_IOMUXC_SAI2_RXC__AUDIOMIX_PDM_BIT_STREAM01 0x1A0 0x400 0x4C4 0x6 0x5
#define MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_RX_DATA00 0x1A4 0x404 0x000 0x0 0x0
#define MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI5_TX_DATA00 0x1A4 0x404 0x000 0x1 0x0
#define MX8MP_IOMUXC_SAI2_RXD0__ENET_QOS_1588_EVENT2_OUT 0x1A4 0x404 0x000 0x2 0x0
#define MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_TX_DATA01 0x1A4 0x404 0x000 0x3 0x0
#define MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS 0x1A4 0x404 0x5E4 0x4 0x2
#define MX8MP_IOMUXC_SAI2_RXD0__UART1_DTE_CTS 0x1A4 0x404 0x000 0x4 0x0
#define MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23 0x1A4 0x404 0x000 0x5 0x0
#define MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_PDM_BIT_STREAM03 0x1A4 0x404 0x4CC 0x6 0x5
#define MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 0x1A8 0x408 0x000 0x0 0x0
#define MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI5_TX_DATA01 0x1A8 0x408 0x000 0x1 0x0
#define MX8MP_IOMUXC_SAI2_TXFS__ENET_QOS_1588_EVENT3_OUT 0x1A8 0x408 0x000 0x2 0x0
#define MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_DATA01 0x1A8 0x408 0x000 0x3 0x0
#define MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS 0x1A8 0x408 0x000 0x4 0x0
#define MX8MP_IOMUXC_SAI2_TXFS__UART1_DTE_RTS 0x1A8 0x408 0x5E4 0x4 0x3
#define MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x1A8 0x408 0x000 0x5 0x0
#define MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_PDM_BIT_STREAM02 0x1A8 0x408 0x4C8 0x6 0x6
#define MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 0x1AC 0x40C 0x000 0x0 0x0
#define MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI5_TX_DATA02 0x1AC 0x40C 0x000 0x1 0x0
#define MX8MP_IOMUXC_SAI2_TXC__CAN1_RX 0x1AC 0x40C 0x54C 0x3 0x1
#define MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x1AC 0x40C 0x000 0x5 0x0
#define MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_PDM_BIT_STREAM01 0x1AC 0x40C 0x4C4 0x6 0x6
#define MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0x1B0 0x410 0x000 0x0 0x0
#define MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI5_TX_DATA03 0x1B0 0x410 0x000 0x1 0x0
#define MX8MP_IOMUXC_SAI2_TXD0__ENET_QOS_1588_EVENT2_IN 0x1B0 0x410 0x000 0x2 0x0
#define MX8MP_IOMUXC_SAI2_TXD0__CAN2_TX 0x1B0 0x410 0x000 0x3 0x0
#define MX8MP_IOMUXC_SAI2_TXD0__ENET_QOS_1588_EVENT2_AUX_IN 0x1B0 0x410 0x000 0x4 0x0
#define MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x1B0 0x410 0x000 0x5 0x0
#define MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI2_MCLK 0x1B4 0x414 0x000 0x0 0x0
#define MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI5_MCLK 0x1B4 0x414 0x4F0 0x1 0x2
#define MX8MP_IOMUXC_SAI2_MCLK__ENET_QOS_1588_EVENT3_IN 0x1B4 0x414 0x000 0x2 0x0
#define MX8MP_IOMUXC_SAI2_MCLK__CAN2_RX 0x1B4 0x414 0x550 0x3 0x1
#define MX8MP_IOMUXC_SAI2_MCLK__ENET_QOS_1588_EVENT3_AUX_IN 0x1B4 0x414 0x000 0x4 0x0
#define MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x1B4 0x414 0x000 0x5 0x0
#define MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI3_MCLK 0x1B4 0x414 0x4E0 0x6 0x1
#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI3_RX_SYNC 0x1B8 0x418 0x000 0x0 0x0
#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI2_RX_DATA01 0x1B8 0x418 0x4DC 0x1 0x1
#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI5_RX_SYNC 0x1B8 0x418 0x508 0x2 0x2
#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI3_RX_DATA01 0x1B8 0x418 0x000 0x3 0x0
#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SPDIF1_IN 0x1B8 0x418 0x544 0x4 0x2
#define MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x1B8 0x418 0x000 0x5 0x0
#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_PDM_BIT_STREAM00 0x1B8 0x418 0x4C0 0x6 0x5
#define MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI3_RX_BCLK 0x1BC 0x41C 0x000 0x0 0x0
#define MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI2_RX_DATA02 0x1BC 0x41C 0x000 0x1 0x0
#define MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI5_RX_BCLK 0x1BC 0x41C 0x4F4 0x2 0x2
#define MX8MP_IOMUXC_SAI3_RXC__GPT1_CLK 0x1BC 0x41C 0x59C 0x3 0x0
#define MX8MP_IOMUXC_SAI3_RXC__UART2_DCE_CTS 0x1BC 0x41C 0x000 0x4 0x0
#define MX8MP_IOMUXC_SAI3_RXC__UART2_DTE_RTS 0x1BC 0x41C 0x5EC 0x4 0x2
#define MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x1BC 0x41C 0x000 0x5 0x0
#define MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_PDM_CLK 0x1BC 0x41C 0x000 0x6 0x0
#define MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0x1C0 0x420 0x4E4 0x0 0x1
#define MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI2_RX_DATA03 0x1C0 0x420 0x000 0x1 0x0
#define MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI5_RX_DATA00 0x1C0 0x420 0x4F8 0x2 0x2
#define MX8MP_IOMUXC_SAI3_RXD__UART2_DCE_RTS 0x1C0 0x420 0x5EC 0x4 0x3
#define MX8MP_IOMUXC_SAI3_RXD__UART2_DTE_CTS 0x1C0 0x420 0x000 0x4 0x0
#define MX8MP_IOMUXC_SAI3_RXD__GPIO4_IO30 0x1C0 0x420 0x000 0x5 0x0
#define MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_PDM_BIT_STREAM01 0x1C0 0x420 0x4C4 0x6 0x7
#define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0x1C4 0x424 0x4EC 0x0 0x1
#define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI2_TX_DATA01 0x1C4 0x424 0x000 0x1 0x0
#define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI5_RX_DATA01 0x1C4 0x424 0x4FC 0x2 0x2
#define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_DATA01 0x1C4 0x424 0x000 0x3 0x0
#define MX8MP_IOMUXC_SAI3_TXFS__UART2_DCE_RX 0x1C4 0x424 0x5F0 0x4 0x4
#define MX8MP_IOMUXC_SAI3_TXFS__UART2_DTE_TX 0x1C4 0x424 0x000 0x4 0x0
#define MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31 0x1C4 0x424 0x000 0x5 0x0
#define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_PDM_BIT_STREAM03 0x1C4 0x424 0x4CC 0x6 0x6
#define MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0x1C8 0x428 0x4E8 0x0 0x1
#define MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI2_TX_DATA02 0x1C8 0x428 0x000 0x1 0x0
#define MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI5_RX_DATA02 0x1C8 0x428 0x500 0x2 0x2
#define MX8MP_IOMUXC_SAI3_TXC__GPT1_CAPTURE1 0x1C8 0x428 0x594 0x3 0x0
#define MX8MP_IOMUXC_SAI3_TXC__UART2_DCE_TX 0x1C8 0x428 0x000 0x4 0x0
#define MX8MP_IOMUXC_SAI3_TXC__UART2_DTE_RX 0x1C8 0x428 0x5F0 0x4 0x5
#define MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x1C8 0x428 0x000 0x5 0x0
#define MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_PDM_BIT_STREAM02 0x1C8 0x428 0x4C8 0x6 0x7
#define MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0x1CC 0x42C 0x000 0x0 0x0
#define MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI2_TX_DATA03 0x1CC 0x42C 0x000 0x1 0x0
#define MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI5_RX_DATA03 0x1CC 0x42C 0x504 0x2 0x2
#define MX8MP_IOMUXC_SAI3_TXD__GPT1_CAPTURE2 0x1CC 0x42C 0x598 0x3 0x0
#define MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SPDIF1_EXT_CLK 0x1CC 0x42C 0x548 0x4 0x0
#define MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x1CC 0x42C 0x000 0x5 0x0
#define MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0x1D0 0x430 0x4E0 0x0 0x2
#define MX8MP_IOMUXC_SAI3_MCLK__PWM4_OUT 0x1D0 0x430 0x000 0x1 0x0
#define MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI5_MCLK 0x1D0 0x430 0x4F0 0x2 0x3
#define MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SPDIF1_OUT 0x1D0 0x430 0x000 0x4 0x0
#define MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x1D0 0x430 0x000 0x5 0x0
#define MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SPDIF1_IN 0x1D0 0x430 0x544 0x6 0x3
#define MX8MP_IOMUXC_SPDIF_TX__AUDIOMIX_SPDIF1_OUT 0x1D4 0x434 0x000 0x0 0x0
#define MX8MP_IOMUXC_SPDIF_TX__PWM3_OUT 0x1D4 0x434 0x000 0x1 0x0
#define MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x1D4 0x434 0x5C4 0x2 0x2
#define MX8MP_IOMUXC_SPDIF_TX__GPT1_COMPARE1 0x1D4 0x434 0x000 0x3 0x0
#define MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x1D4 0x434 0x000 0x4 0x0
#define MX8MP_IOMUXC_SPDIF_TX__GPIO5_IO03 0x1D4 0x434 0x000 0x5 0x0
#define MX8MP_IOMUXC_SPDIF_RX__AUDIOMIX_SPDIF1_IN 0x1D8 0x438 0x544 0x0 0x4
#define MX8MP_IOMUXC_SPDIF_RX__PWM2_OUT 0x1D8 0x438 0x000 0x1 0x0
#define MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x1D8 0x438 0x5C8 0x2 0x2
#define MX8MP_IOMUXC_SPDIF_RX__GPT1_COMPARE2 0x1D8 0x438 0x000 0x3 0x0
#define MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x1D8 0x438 0x54C 0x4 0x2
#define MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x1D8 0x438 0x000 0x5 0x0
#define MX8MP_IOMUXC_SPDIF_EXT_CLK__GPT1_COMPARE3 0x1DC 0x43C 0x000 0x3 0x0
#define MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x1DC 0x43C 0x000 0x5 0x0
#define MX8MP_IOMUXC_SPDIF_EXT_CLK__AUDIOMIX_SPDIF1_EXT_CLK 0x1DC 0x43C 0x548 0x0 0x1
#define MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT 0x1DC 0x43C 0x000 0x1 0x0
#define MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x1E0 0x440 0x558 0x0 0x0
#define MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x1E0 0x440 0x5F8 0x1 0x4
#define MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DTE_TX 0x1E0 0x440 0x000 0x1 0x0
#define MX8MP_IOMUXC_ECSPI1_SCLK__I2C1_SCL 0x1E0 0x440 0x5A4 0x2 0x1
#define MX8MP_IOMUXC_ECSPI1_SCLK__AUDIOMIX_SAI7_RX_SYNC 0x1E0 0x440 0x538 0x3 0x1
#define MX8MP_IOMUXC_ECSPI1_SCLK__GPIO5_IO06 0x1E0 0x440 0x000 0x5 0x0
#define MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x1E4 0x444 0x560 0x0 0x0
#define MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x1E4 0x444 0x000 0x1 0x0
#define MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DTE_RX 0x1E4 0x444 0x5F8 0x1 0x5
#define MX8MP_IOMUXC_ECSPI1_MOSI__I2C1_SDA 0x1E4 0x444 0x5A8 0x2 0x1
#define MX8MP_IOMUXC_ECSPI1_MOSI__AUDIOMIX_SAI7_RX_BCLK 0x1E4 0x444 0x530 0x3 0x1
#define MX8MP_IOMUXC_ECSPI1_MOSI__GPIO5_IO07 0x1E4 0x444 0x000 0x5 0x0
#define MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x1E8 0x448 0x55C 0x0 0x0
#define MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x1E8 0x448 0x000 0x1 0x0
#define MX8MP_IOMUXC_ECSPI1_MISO__UART3_DTE_RTS 0x1E8 0x448 0x5F4 0x1 0x2
#define MX8MP_IOMUXC_ECSPI1_MISO__I2C2_SCL 0x1E8 0x448 0x5AC 0x2 0x1
#define MX8MP_IOMUXC_ECSPI1_MISO__AUDIOMIX_SAI7_RX_DATA00 0x1E8 0x448 0x534 0x3 0x1
#define MX8MP_IOMUXC_ECSPI1_MISO__GPIO5_IO08 0x1E8 0x448 0x000 0x5 0x0
#define MX8MP_IOMUXC_ECSPI1_SS0__ECSPI1_SS0 0x1EC 0x44C 0x564 0x0 0x0
#define MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x1EC 0x44C 0x5F4 0x1 0x3
#define MX8MP_IOMUXC_ECSPI1_SS0__UART3_DTE_CTS 0x1EC 0x44C 0x000 0x1 0x0
#define MX8MP_IOMUXC_ECSPI1_SS0__I2C2_SDA 0x1EC 0x44C 0x5B0 0x2 0x1
#define MX8MP_IOMUXC_ECSPI1_SS0__AUDIOMIX_SAI7_TX_SYNC 0x1EC 0x44C 0x540 0x3 0x1
#define MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x1EC 0x44C 0x000 0x5 0x0
#define MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x1F0 0x450 0x568 0x0 0x1
#define MX8MP_IOMUXC_ECSPI2_SCLK__UART4_DCE_RX 0x1F0 0x450 0x600 0x1 0x6
#define MX8MP_IOMUXC_ECSPI2_SCLK__UART4_DTE_TX 0x1F0 0x450 0x000 0x1 0x0
#define MX8MP_IOMUXC_ECSPI2_SCLK__I2C3_SCL 0x1F0 0x450 0x5B4 0x2 0x3
#define MX8MP_IOMUXC_ECSPI2_SCLK__AUDIOMIX_SAI7_TX_BCLK 0x1F0 0x450 0x53C 0x3 0x1
#define MX8MP_IOMUXC_ECSPI2_SCLK__GPIO5_IO10 0x1F0 0x450 0x000 0x5 0x0
#define MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x1F4 0x454 0x570 0x0 0x1
#define MX8MP_IOMUXC_ECSPI2_MOSI__UART4_DCE_TX 0x1F4 0x454 0x000 0x1 0x0
#define MX8MP_IOMUXC_ECSPI2_MOSI__UART4_DTE_RX 0x1F4 0x454 0x600 0x1 0x7
#define MX8MP_IOMUXC_ECSPI2_MOSI__I2C3_SDA 0x1F4 0x454 0x5B8 0x2 0x3
#define MX8MP_IOMUXC_ECSPI2_MOSI__AUDIOMIX_SAI7_TX_DATA00 0x1F4 0x454 0x000 0x3 0x0
#define MX8MP_IOMUXC_ECSPI2_MOSI__GPIO5_IO11 0x1F4 0x454 0x000 0x5 0x0
#define MX8MP_IOMUXC_ECSPI2_MISO__GPIO5_IO12 0x1F8 0x458 0x000 0x5 0x0
#define MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x1F8 0x458 0x56C 0x0 0x1
#define MX8MP_IOMUXC_ECSPI2_MISO__UART4_DCE_CTS 0x1F8 0x458 0x000 0x1 0x0
#define MX8MP_IOMUXC_ECSPI2_MISO__UART4_DTE_RTS 0x1F8 0x458 0x5FC 0x1 0x2
#define MX8MP_IOMUXC_ECSPI2_MISO__I2C4_SCL 0x1F8 0x458 0x5BC 0x2 0x4
#define MX8MP_IOMUXC_ECSPI2_MISO__AUDIOMIX_SAI7_MCLK 0x1F8 0x458 0x52C 0x3 0x1
#define MX8MP_IOMUXC_ECSPI2_MISO__CCM_CLKO1 0x1F8 0x458 0x000 0x4 0x0
#define MX8MP_IOMUXC_ECSPI2_SS0__ECSPI2_SS0 0x1FC 0x45C 0x574 0x0 0x1
#define MX8MP_IOMUXC_ECSPI2_SS0__UART4_DCE_RTS 0x1FC 0x45C 0x5FC 0x1 0x3
#define MX8MP_IOMUXC_ECSPI2_SS0__UART4_DTE_CTS 0x1FC 0x45C 0x000 0x1 0x0
#define MX8MP_IOMUXC_ECSPI2_SS0__I2C4_SDA 0x1FC 0x45C 0x5C0 0x2 0x4
#define MX8MP_IOMUXC_ECSPI2_SS0__CCM_CLKO2 0x1FC 0x45C 0x000 0x4 0x0
#define MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x1FC 0x45C 0x000 0x5 0x0
#define MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x200 0x460 0x5A4 0x0 0x2
#define MX8MP_IOMUXC_I2C1_SCL__ENET_QOS_MDC 0x200 0x460 0x000 0x1 0x0
#define MX8MP_IOMUXC_I2C1_SCL__ECSPI1_SCLK 0x200 0x460 0x558 0x3 0x1
#define MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x200 0x460 0x000 0x5 0x0
#define MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x204 0x464 0x5A8 0x0 0x2
#define MX8MP_IOMUXC_I2C1_SDA__ENET_QOS_MDIO 0x204 0x464 0x590 0x1 0x2
#define MX8MP_IOMUXC_I2C1_SDA__ECSPI1_MOSI 0x204 0x464 0x560 0x3 0x1
#define MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x204 0x464 0x000 0x5 0x0
#define MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x208 0x468 0x5AC 0x0 0x2
#define MX8MP_IOMUXC_I2C2_SCL__ENET_QOS_1588_EVENT1_IN 0x208 0x468 0x000 0x1 0x0
#define MX8MP_IOMUXC_I2C2_SCL__USDHC3_CD_B 0x208 0x468 0x608 0x2 0x3
#define MX8MP_IOMUXC_I2C2_SCL__ECSPI1_MISO 0x208 0x468 0x55C 0x3 0x1
#define MX8MP_IOMUXC_I2C2_SCL__ENET_QOS_1588_EVENT1_AUX_IN 0x208 0x468 0x000 0x4 0x0
#define MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x208 0x468 0x000 0x5 0x0
#define MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x20C 0x46C 0x5B0 0x0 0x2
#define MX8MP_IOMUXC_I2C2_SDA__ENET_QOS_1588_EVENT1_OUT 0x20C 0x46C 0x000 0x1 0x0
#define MX8MP_IOMUXC_I2C2_SDA__USDHC3_WP 0x20C 0x46C 0x634 0x2 0x3
#define MX8MP_IOMUXC_I2C2_SDA__ECSPI1_SS0 0x20C 0x46C 0x564 0x3 0x1
#define MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x20C 0x46C 0x000 0x5 0x0
#define MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x210 0x470 0x5B4 0x0 0x4
#define MX8MP_IOMUXC_I2C3_SCL__PWM4_OUT 0x210 0x470 0x000 0x1 0x0
#define MX8MP_IOMUXC_I2C3_SCL__GPT2_CLK 0x210 0x470 0x000 0x2 0x0
#define MX8MP_IOMUXC_I2C3_SCL__ECSPI2_SCLK 0x210 0x470 0x568 0x3 0x2
#define MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x210 0x470 0x000 0x5 0x0
#define MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x214 0x474 0x5B8 0x0 0x4
#define MX8MP_IOMUXC_I2C3_SDA__PWM3_OUT 0x214 0x474 0x000 0x1 0x0
#define MX8MP_IOMUXC_I2C3_SDA__GPT3_CLK 0x214 0x474 0x000 0x2 0x0
#define MX8MP_IOMUXC_I2C3_SDA__ECSPI2_MOSI 0x214 0x474 0x570 0x3 0x2
#define MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x214 0x474 0x000 0x5 0x0
#define MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x218 0x478 0x5BC 0x0 0x5
#define MX8MP_IOMUXC_I2C4_SCL__PWM2_OUT 0x218 0x478 0x000 0x1 0x0
#define MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x218 0x478 0x5A0 0x2 0x0
#define MX8MP_IOMUXC_I2C4_SCL__ECSPI2_MISO 0x218 0x478 0x56C 0x3 0x2
#define MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x218 0x478 0x000 0x5 0x0
#define MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x21C 0x47C 0x5C0 0x0 0x5
#define MX8MP_IOMUXC_I2C4_SDA__PWM1_OUT 0x21C 0x47C 0x000 0x1 0x0
#define MX8MP_IOMUXC_I2C4_SDA__ECSPI2_SS0 0x21C 0x47C 0x574 0x3 0x2
#define MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x21C 0x47C 0x000 0x5 0x0
#define MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x220 0x480 0x5E8 0x0 0x4
#define MX8MP_IOMUXC_UART1_RXD__UART1_DTE_TX 0x220 0x480 0x000 0x0 0x0
#define MX8MP_IOMUXC_UART1_RXD__ECSPI3_SCLK 0x220 0x480 0x000 0x1 0x0
#define MX8MP_IOMUXC_UART1_RXD__GPIO5_IO22 0x220 0x480 0x000 0x5 0x0
#define MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x224 0x484 0x000 0x0 0x0
#define MX8MP_IOMUXC_UART1_TXD__UART1_DTE_RX 0x224 0x484 0x5E8 0x0 0x5
#define MX8MP_IOMUXC_UART1_TXD__ECSPI3_MOSI 0x224 0x484 0x000 0x1 0x0
#define MX8MP_IOMUXC_UART1_TXD__GPIO5_IO23 0x224 0x484 0x000 0x5 0x0
#define MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x228 0x488 0x5F0 0x0 0x6
#define MX8MP_IOMUXC_UART2_RXD__UART2_DTE_TX 0x228 0x488 0x000 0x0 0x0
#define MX8MP_IOMUXC_UART2_RXD__ECSPI3_MISO 0x228 0x488 0x000 0x1 0x0
#define MX8MP_IOMUXC_UART2_RXD__GPT1_COMPARE3 0x228 0x488 0x000 0x3 0x0
#define MX8MP_IOMUXC_UART2_RXD__GPIO5_IO24 0x228 0x488 0x000 0x5 0x0
#define MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x22C 0x48C 0x000 0x0 0x0
#define MX8MP_IOMUXC_UART2_TXD__UART2_DTE_RX 0x22C 0x48C 0x5F0 0x0 0x7
#define MX8MP_IOMUXC_UART2_TXD__ECSPI3_SS0 0x22C 0x48C 0x000 0x1 0x0
#define MX8MP_IOMUXC_UART2_TXD__GPT1_COMPARE2 0x22C 0x48C 0x000 0x3 0x0
#define MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25 0x22C 0x48C 0x000 0x5 0x0
#define MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x230 0x490 0x5F8 0x0 0x6
#define MX8MP_IOMUXC_UART3_RXD__UART3_DTE_TX 0x230 0x490 0x000 0x0 0x0
#define MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x230 0x490 0x000 0x1 0x0
#define MX8MP_IOMUXC_UART3_RXD__UART1_DTE_RTS 0x230 0x490 0x5E4 0x1 0x4
#define MX8MP_IOMUXC_UART3_RXD__USDHC3_RESET_B 0x230 0x490 0x000 0x2 0x0
#define MX8MP_IOMUXC_UART3_RXD__GPT1_CAPTURE2 0x230 0x490 0x598 0x3 0x1
#define MX8MP_IOMUXC_UART3_RXD__CAN2_TX 0x230 0x490 0x000 0x4 0x0
#define MX8MP_IOMUXC_UART3_RXD__GPIO5_IO26 0x230 0x490 0x000 0x5 0x0
#define MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x234 0x494 0x000 0x0 0x0
#define MX8MP_IOMUXC_UART3_TXD__UART3_DTE_RX 0x234 0x494 0x5F8 0x0 0x7
#define MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x234 0x494 0x5E4 0x1 0x5
#define MX8MP_IOMUXC_UART3_TXD__UART1_DTE_CTS 0x234 0x494 0x000 0x1 0x0
#define MX8MP_IOMUXC_UART3_TXD__USDHC3_VSELECT 0x234 0x494 0x000 0x2 0x0
#define MX8MP_IOMUXC_UART3_TXD__GPT1_CLK 0x234 0x494 0x59C 0x3 0x1
#define MX8MP_IOMUXC_UART3_TXD__CAN2_RX 0x234 0x494 0x550 0x4 0x2
#define MX8MP_IOMUXC_UART3_TXD__GPIO5_IO27 0x234 0x494 0x000 0x5 0x0
#define MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x238 0x498 0x600 0x0 0x8
#define MX8MP_IOMUXC_UART4_RXD__UART4_DTE_TX 0x238 0x498 0x000 0x0 0x0
#define MX8MP_IOMUXC_UART4_RXD__UART2_DCE_CTS 0x238 0x498 0x000 0x1 0x0
#define MX8MP_IOMUXC_UART4_RXD__UART2_DTE_RTS 0x238 0x498 0x5EC 0x1 0x4
#define MX8MP_IOMUXC_UART4_RXD__PCIE_CLKREQ_B 0x238 0x498 0x5A0 0x2 0x1
#define MX8MP_IOMUXC_UART4_RXD__GPT1_COMPARE1 0x238 0x498 0x000 0x3 0x0
#define MX8MP_IOMUXC_UART4_RXD__I2C6_SCL 0x238 0x498 0x5CC 0x4 0x2
#define MX8MP_IOMUXC_UART4_RXD__GPIO5_IO28 0x238 0x498 0x000 0x5 0x0
#define MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x23C 0x49C 0x000 0x0 0x0
#define MX8MP_IOMUXC_UART4_TXD__UART4_DTE_RX 0x23C 0x49C 0x600 0x0 0x9
#define MX8MP_IOMUXC_UART4_TXD__UART2_DCE_RTS 0x23C 0x49C 0x5EC 0x1 0x5
#define MX8MP_IOMUXC_UART4_TXD__UART2_DTE_CTS 0x23C 0x49C 0x000 0x1 0x0
#define MX8MP_IOMUXC_UART4_TXD__GPT1_CAPTURE1 0x23C 0x49C 0x594 0x3 0x1
#define MX8MP_IOMUXC_UART4_TXD__I2C6_SDA 0x23C 0x49C 0x5D0 0x4 0x2
#define MX8MP_IOMUXC_UART4_TXD__GPIO5_IO29 0x23C 0x49C 0x000 0x5 0x0
#define MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x240 0x4A0 0x000 0x0 0x0
#define MX8MP_IOMUXC_HDMI_DDC_SCL__I2C5_SCL 0x240 0x4A0 0x5C4 0x3 0x3
#define MX8MP_IOMUXC_HDMI_DDC_SCL__CAN1_TX 0x240 0x4A0 0x000 0x4 0x0
#define MX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26 0x240 0x4A0 0x000 0x5 0x0
#define MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x244 0x4A4 0x000 0x0 0x0
#define MX8MP_IOMUXC_HDMI_DDC_SDA__I2C5_SDA 0x244 0x4A4 0x5C8 0x3 0x3
#define MX8MP_IOMUXC_HDMI_DDC_SDA__CAN1_RX 0x244 0x4A4 0x54C 0x4 0x3
#define MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27 0x244 0x4A4 0x000 0x5 0x0
#define MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x248 0x4A8 0x000 0x0 0x0
#define MX8MP_IOMUXC_HDMI_CEC__I2C6_SCL 0x248 0x4A8 0x5CC 0x3 0x3
#define MX8MP_IOMUXC_HDMI_CEC__CAN2_TX 0x248 0x4A8 0x000 0x4 0x0
#define MX8MP_IOMUXC_HDMI_CEC__GPIO3_IO28 0x248 0x4A8 0x000 0x5 0x0
#define MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x24C 0x4AC 0x000 0x0 0x0
#define MX8MP_IOMUXC_HDMI_HPD__AUDIOMIX_HDMI_HPD_O 0x24C 0x4AC 0x000 0x1 0x0
#define MX8MP_IOMUXC_HDMI_HPD__I2C6_SDA 0x24C 0x4AC 0x5D0 0x3 0x3
#define MX8MP_IOMUXC_HDMI_HPD__CAN2_RX 0x24C 0x4AC 0x550 0x4 0x3
#define MX8MP_IOMUXC_HDMI_HPD__GPIO3_IO29 0x24C 0x4AC 0x000 0x5 0x0
#endif /* __DTS_IMX8MP_PINFUNC_H */

View File

@@ -185,7 +185,6 @@
};
#endif
#ifdef CONFIG_OPTEE
tee: tee {
description = "OP-TEE";
type = "tee";
@@ -197,9 +196,9 @@
tee-os {
filename = "tee.bin";
optional;
};
};
#endif
@fdt-SEQ {
description = "NAME";
@@ -220,11 +219,7 @@
fdt = "fdt-SEQ";
firmware = "uboot";
#ifndef CONFIG_ARMV8_PSCI
#ifdef CONFIG_OPTEE
loadables = "atf", "tee";
#else
loadables = "atf";
#endif
#endif
};
};

View File

@@ -98,6 +98,13 @@
gpios = <6 GPIO_ACTIVE_HIGH>;
line-name = "m2_rst";
};
m2_wdis2 {
gpio-hog;
output-high;
gpios = <14 GPIO_ACTIVE_HIGH>;
line-name = "m2_wdis2#";
};
};
&gpio4 {
@@ -110,11 +117,11 @@
line-name = "m2_off#";
};
m2_wdis {
m2_wdis1 {
gpio-hog;
output-high;
gpios = <18 GPIO_ACTIVE_HIGH>;
line-name = "m2_wdis#";
line-name = "m2_wdis1#";
};
rs485_en {

View File

@@ -0,0 +1,49 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2025 Gateworks Corporation
*/
#include "imx8mp-venice-gw702x-u-boot.dtsi"
&gpio4 {
dio_1 {
gpio-hog;
input;
gpios = <8 GPIO_ACTIVE_HIGH>;
line-name = "dio1";
};
dio_0 {
gpio-hog;
input;
gpios = <11 GPIO_ACTIVE_HIGH>;
line-name = "dio0#";
};
usb1mux {
gpio-hog;
output-high;
gpios = <17 GPIO_ACTIVE_HIGH>;
line-name = "usb1_mux";
};
rs485_en {
gpio-hog;
output-low;
gpios = <22 GPIO_ACTIVE_HIGH>;
line-name = "rs485_en";
};
rs485_term {
gpio-hog;
output-low;
gpios = <23 GPIO_ACTIVE_HIGH>;
line-name = "rs485_term";
};
rs485_half {
gpio-hog;
output-low;
gpios = <27 GPIO_ACTIVE_HIGH>;
line-name = "rs485_hd";
};
};

View File

@@ -1,623 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
*/
#ifndef __DTS_IMX8MQ_PINFUNC_H
#define __DTS_IMX8MQ_PINFUNC_H
/*
* The pin function ID is a tuple of
* <mux_reg conf_reg input_reg mux_mode input_val>
*/
#define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0x0
#define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0x0
#define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0x0
#define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0x0
#define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0x0
#define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
#define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0x0
#define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
#define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
#define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0x0
#define MX8MQ_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
#define MX8MQ_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
#define MX8MQ_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0x0
#define MX8MQ_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0x0
#define MX8MQ_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0x0
#define MX8MQ_IOMUXC_GPIO1_IO02_GPIO1_IO2 0x030 0x298 0x000 0x0 0x0
#define MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x030 0x298 0x000 0x1 0x0
#define MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x030 0x298 0x000 0x5 0x0
#define MX8MQ_IOMUXC_GPIO1_IO02_SJC_DE_B 0x030 0x298 0x000 0x7 0x0
#define MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x034 0x29C 0x000 0x0 0x0
#define MX8MQ_IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x034 0x29C 0x000 0x1 0x0
#define MX8MQ_IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x034 0x29C 0x000 0x5 0x0
#define MX8MQ_IOMUXC_GPIO1_IO03_ANAMIX_XTAL_OK 0x034 0x29C 0x000 0x6 0x0
#define MX8MQ_IOMUXC_GPIO1_IO03_SJC_DONE 0x034 0x29C 0x000 0x7 0x0
#define MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x038 0x2A0 0x000 0x0 0x0
#define MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x038 0x2A0 0x000 0x1 0x0
#define MX8MQ_IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x038 0x2A0 0x000 0x5 0x0
#define MX8MQ_IOMUXC_GPIO1_IO04_ANAMIX_XTAL_OK_LV 0x038 0x2A0 0x000 0x6 0x0
#define MX8MQ_IOMUXC_GPIO1_IO04_USDHC1_TEST_TRIG 0x038 0x2A0 0x000 0x7 0x0
#define MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x03C 0x2A4 0x000 0x0 0x0
#define MX8MQ_IOMUXC_GPIO1_IO05_M4_NMI 0x03C 0x2A4 0x000 0x1 0x0
#define MX8MQ_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_PMIC_READY 0x03C 0x2A4 0x000 0x5 0x0
#define MX8MQ_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_INT_BOOT 0x03C 0x2A4 0x000 0x6 0x0
#define MX8MQ_IOMUXC_GPIO1_IO05_USDHC2_TEST_TRIG 0x03C 0x2A4 0x000 0x7 0x0
#define MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x040 0x2A8 0x000 0x0 0x0
#define MX8MQ_IOMUXC_GPIO1_IO06_ENET1_MDC 0x040 0x2A8 0x000 0x1 0x0
#define MX8MQ_IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x040 0x2A8 0x000 0x5 0x0
#define MX8MQ_IOMUXC_GPIO1_IO06_CCMSRCGPCMIX_EXT_CLK3 0x040 0x2A8 0x000 0x6 0x0
#define MX8MQ_IOMUXC_GPIO1_IO06_ECSPI1_TEST_TRIG 0x040 0x2A8 0x000 0x7 0x0
#define MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x044 0x2AC 0x000 0x0 0x0
#define MX8MQ_IOMUXC_GPIO1_IO07_ENET1_MDIO 0x044 0x2AC 0x000 0x1 0x0
#define MX8MQ_IOMUXC_GPIO1_IO07_USDHC1_WP 0x044 0x2AC 0x000 0x5 0x0
#define MX8MQ_IOMUXC_GPIO1_IO07_CCMSRCGPCMIX_EXT_CLK4 0x044 0x2AC 0x000 0x6 0x0
#define MX8MQ_IOMUXC_GPIO1_IO07_ECSPI2_TEST_TRIG 0x044 0x2AC 0x000 0x7 0x0
#define MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x048 0x2B0 0x000 0x0 0x0
#define MX8MQ_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x048 0x2B0 0x000 0x1 0x0
#define MX8MQ_IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x048 0x2B0 0x000 0x5 0x0
#define MX8MQ_IOMUXC_GPIO1_IO08_CCMSRCGPCMIX_WAIT 0x048 0x2B0 0x000 0x6 0x0
#define MX8MQ_IOMUXC_GPIO1_IO08_QSPI_TEST_TRIG 0x048 0x2B0 0x000 0x7 0x0
#define MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x04C 0x2B4 0x000 0x0 0x0
#define MX8MQ_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x04C 0x2B4 0x000 0x1 0x0
#define MX8MQ_IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x04C 0x2B4 0x000 0x5 0x0
#define MX8MQ_IOMUXC_GPIO1_IO09_CCMSRCGPCMIX_STOP 0x04C 0x2B4 0x000 0x6 0x0
#define MX8MQ_IOMUXC_GPIO1_IO09_RAWNAND_TEST_TRIG 0x04C 0x2B4 0x000 0x7 0x0
#define MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x050 0x2B8 0x000 0x0 0x0
#define MX8MQ_IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x050 0x2B8 0x000 0x1 0x0
#define MX8MQ_IOMUXC_GPIO1_IO10_OCOTP_CTRL_WRAPPER_FUSE_LATCHED 0x050 0x2B8 0x000 0x7 0x0
#define MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x054 0x2BC 0x000 0x0 0x0
#define MX8MQ_IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x054 0x2BC 0x000 0x1 0x0
#define MX8MQ_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_PMIC_READY 0x054 0x2BC 0x4BC 0x5 0x1
#define MX8MQ_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_OUT0 0x054 0x2BC 0x000 0x6 0x0
#define MX8MQ_IOMUXC_GPIO1_IO11_CAAM_WRAPPER_RNG_OSC_OBS 0x054 0x2BC 0x000 0x7 0x0
#define MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x058 0x2C0 0x000 0x0 0x0
#define MX8MQ_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x058 0x2C0 0x000 0x1 0x0
#define MX8MQ_IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x058 0x2C0 0x000 0x5 0x0
#define MX8MQ_IOMUXC_GPIO1_IO12_CCMSRCGPCMIX_OUT1 0x058 0x2C0 0x000 0x6 0x0
#define MX8MQ_IOMUXC_GPIO1_IO12_CSU_CSU_ALARM_AUT0 0x058 0x2C0 0x000 0x7 0x0
#define MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x05C 0x2C4 0x000 0x0 0x0
#define MX8MQ_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x05C 0x2C4 0x000 0x1 0x0
#define MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT 0x05C 0x2C4 0x000 0x5 0x0
#define MX8MQ_IOMUXC_GPIO1_IO13_CCMSRCGPCMIX_OUT2 0x05C 0x2C4 0x000 0x6 0x0
#define MX8MQ_IOMUXC_GPIO1_IO13_CSU_CSU_ALARM_AUT1 0x05C 0x2C4 0x000 0x7 0x0
#define MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x060 0x2C8 0x000 0x0 0x0
#define MX8MQ_IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x060 0x2C8 0x000 0x1 0x0
#define MX8MQ_IOMUXC_GPIO1_IO14_PWM3_OUT 0x060 0x2C8 0x000 0x5 0x0
#define MX8MQ_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x060 0x2C8 0x000 0x6 0x0
#define MX8MQ_IOMUXC_GPIO1_IO14_CSU_CSU_ALARM_AUT2 0x060 0x2C8 0x000 0x7 0x0
#define MX8MQ_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x064 0x2CC 0x000 0x0 0x0
#define MX8MQ_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x064 0x2CC 0x000 0x1 0x0
#define MX8MQ_IOMUXC_GPIO1_IO15_PWM4_OUT 0x064 0x2CC 0x000 0x5 0x0
#define MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x064 0x2CC 0x000 0x6 0x0
#define MX8MQ_IOMUXC_GPIO1_IO15_CSU_CSU_INT_DEB 0x064 0x2CC 0x000 0x7 0x0
#define MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x068 0x2D0 0x000 0x0 0x0
#define MX8MQ_IOMUXC_ENET_MDC_GPIO1_IO16 0x068 0x2D0 0x000 0x5 0x0
#define MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x06C 0x2D4 0x4C0 0x0 0x1
#define MX8MQ_IOMUXC_ENET_MDIO_GPIO1_IO17 0x06C 0x2D4 0x000 0x5 0x0
#define MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x070 0x2D8 0x000 0x0 0x0
#define MX8MQ_IOMUXC_ENET_TD3_GPIO1_IO18 0x070 0x2D8 0x000 0x5 0x0
#define MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x074 0x2DC 0x000 0x0 0x0
#define MX8MQ_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x074 0x2DC 0x000 0x1 0x0
#define MX8MQ_IOMUXC_ENET_TD2_GPIO1_IO19 0x074 0x2DC 0x000 0x5 0x0
#define MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x078 0x2E0 0x000 0x0 0x0
#define MX8MQ_IOMUXC_ENET_TD1_GPIO1_IO20 0x078 0x2E0 0x000 0x5 0x0
#define MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x07C 0x2E4 0x000 0x0 0x0
#define MX8MQ_IOMUXC_ENET_TD0_GPIO1_IO21 0x07C 0x2E4 0x000 0x5 0x0
#define MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x080 0x2E8 0x000 0x0 0x0
#define MX8MQ_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x080 0x2E8 0x000 0x5 0x0
#define MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x084 0x2EC 0x000 0x0 0x0
#define MX8MQ_IOMUXC_ENET_TXC_ENET1_TX_ER 0x084 0x2EC 0x000 0x1 0x0
#define MX8MQ_IOMUXC_ENET_TXC_GPIO1_IO23 0x084 0x2EC 0x000 0x5 0x0
#define MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x088 0x2F0 0x000 0x0 0x0
#define MX8MQ_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x088 0x2F0 0x000 0x5 0x0
#define MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x08C 0x2F4 0x000 0x0 0x0
#define MX8MQ_IOMUXC_ENET_RXC_ENET1_RX_ER 0x08C 0x2F4 0x000 0x1 0x0
#define MX8MQ_IOMUXC_ENET_RXC_GPIO1_IO25 0x08C 0x2F4 0x000 0x5 0x0
#define MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x090 0x2F8 0x000 0x0 0x0
#define MX8MQ_IOMUXC_ENET_RD0_GPIO1_IO26 0x090 0x2F8 0x000 0x5 0x0
#define MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x094 0x2FC 0x000 0x0 0x0
#define MX8MQ_IOMUXC_ENET_RD1_GPIO1_IO27 0x094 0x2FC 0x000 0x5 0x0
#define MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x098 0x300 0x000 0x0 0x0
#define MX8MQ_IOMUXC_ENET_RD2_GPIO1_IO28 0x098 0x300 0x000 0x5 0x0
#define MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x09C 0x304 0x000 0x0 0x0
#define MX8MQ_IOMUXC_ENET_RD3_GPIO1_IO29 0x09C 0x304 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x0A0 0x308 0x000 0x0 0x0
#define MX8MQ_IOMUXC_SD1_CLK_GPIO2_IO0 0x0A0 0x308 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0x0A4 0x30C 0x000 0x0 0x0
#define MX8MQ_IOMUXC_SD1_CMD_GPIO2_IO1 0x0A4 0x30C 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0A8 0x310 0x000 0x0 0x0
#define MX8MQ_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x310 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0AC 0x314 0x000 0x0 0x0
#define MX8MQ_IOMUXC_SD1_DATA1_GPIO2_IO3 0x0AC 0x314 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0B0 0x318 0x000 0x0 0x0
#define MX8MQ_IOMUXC_SD1_DATA2_GPIO2_IO4 0x0B0 0x318 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0B4 0x31C 0x000 0x0 0x0
#define MX8MQ_IOMUXC_SD1_DATA3_GPIO2_IO5 0x0B4 0x31C 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0B8 0x320 0x000 0x0 0x0
#define MX8MQ_IOMUXC_SD1_DATA4_GPIO2_IO6 0x0B8 0x320 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0BC 0x324 0x000 0x0 0x0
#define MX8MQ_IOMUXC_SD1_DATA5_GPIO2_IO7 0x0BC 0x324 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0C0 0x328 0x000 0x0 0x0
#define MX8MQ_IOMUXC_SD1_DATA6_GPIO2_IO8 0x0C0 0x328 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0C4 0x32C 0x000 0x0 0x0
#define MX8MQ_IOMUXC_SD1_DATA7_GPIO2_IO9 0x0C4 0x32C 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x0C8 0x330 0x000 0x0 0x0
#define MX8MQ_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x0C8 0x330 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x0CC 0x334 0x000 0x0 0x0
#define MX8MQ_IOMUXC_SD1_STROBE_GPIO2_IO11 0x0CC 0x334 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0D0 0x338 0x000 0x0 0x0
#define MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0D0 0x338 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x0D4 0x33C 0x000 0x0 0x0
#define MX8MQ_IOMUXC_SD2_CLK_GPIO2_IO13 0x0D4 0x33C 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SD2_CLK_CCMSRCGPCMIX_OBSERVE0 0x0D4 0x33C 0x000 0x6 0x0
#define MX8MQ_IOMUXC_SD2_CLK_OBSERVE_MUX_OUT0 0x0D4 0x33C 0x000 0x7 0x0
#define MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0x0D8 0x340 0x000 0x0 0x0
#define MX8MQ_IOMUXC_SD2_CMD_GPIO2_IO14 0x0D8 0x340 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SD2_CMD_CCMSRCGPCMIX_OBSERVE1 0x0D8 0x340 0x000 0x6 0x0
#define MX8MQ_IOMUXC_SD2_CMD_OBSERVE_MUX_OUT1 0x0D8 0x340 0x000 0x7 0x0
#define MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0DC 0x344 0x000 0x0 0x0
#define MX8MQ_IOMUXC_SD2_DATA0_GPIO2_IO15 0x0DC 0x344 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SD2_DATA0_CCMSRCGPCMIX_OBSERVE2 0x0DC 0x344 0x000 0x6 0x0
#define MX8MQ_IOMUXC_SD2_DATA0_OBSERVE_MUX_OUT2 0x0DC 0x344 0x000 0x7 0x0
#define MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0E0 0x348 0x000 0x0 0x0
#define MX8MQ_IOMUXC_SD2_DATA1_GPIO2_IO16 0x0E0 0x348 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SD2_DATA1_CCMSRCGPCMIX_WAIT 0x0E0 0x348 0x000 0x6 0x0
#define MX8MQ_IOMUXC_SD2_DATA1_OBSERVE_MUX_OUT3 0x0E0 0x348 0x000 0x7 0x0
#define MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0E4 0x34C 0x000 0x0 0x0
#define MX8MQ_IOMUXC_SD2_DATA2_GPIO2_IO17 0x0E4 0x34C 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SD2_DATA2_CCMSRCGPCMIX_STOP 0x0E4 0x34C 0x000 0x6 0x0
#define MX8MQ_IOMUXC_SD2_DATA2_OBSERVE_MUX_OUT4 0x0E4 0x34C 0x000 0x7 0x0
#define MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0E8 0x350 0x000 0x0 0x0
#define MX8MQ_IOMUXC_SD2_DATA3_GPIO2_IO18 0x0E8 0x350 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SD2_DATA3_CCMSRCGPCMIX_EARLY_RESET 0x0E8 0x350 0x000 0x6 0x0
#define MX8MQ_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x0EC 0x354 0x000 0x0 0x0
#define MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x0EC 0x354 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SD2_RESET_B_CCMSRCGPCMIX_SYSTEM_RESET 0x0EC 0x354 0x000 0x6 0x0
#define MX8MQ_IOMUXC_SD2_WP_USDHC2_WP 0x0F0 0x358 0x000 0x0 0x0
#define MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x0F0 0x358 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SD2_WP_SIM_M_HMASTLOCK 0x0F0 0x358 0x000 0x7 0x0
#define MX8MQ_IOMUXC_NAND_ALE_RAWNAND_ALE 0x0F4 0x35C 0x000 0x0 0x0
#define MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x0F4 0x35C 0x000 0x1 0x0
#define MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x0F4 0x35C 0x000 0x5 0x0
#define MX8MQ_IOMUXC_NAND_ALE_SIM_M_HPROT0 0x0F4 0x35C 0x000 0x7 0x0
#define MX8MQ_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x0F8 0x360 0x000 0x0 0x0
#define MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x0F8 0x360 0x000 0x1 0x0
#define MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x0F8 0x360 0x000 0x5 0x0
#define MX8MQ_IOMUXC_NAND_CE0_B_SIM_M_HPROT1 0x0F8 0x360 0x000 0x7 0x0
#define MX8MQ_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x0FC 0x364 0x000 0x0 0x0
#define MX8MQ_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x0FC 0x364 0x000 0x1 0x0
#define MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x0FC 0x364 0x000 0x5 0x0
#define MX8MQ_IOMUXC_NAND_CE1_B_SIM_M_HPROT2 0x0FC 0x364 0x000 0x7 0x0
#define MX8MQ_IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x100 0x368 0x000 0x0 0x0
#define MX8MQ_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x100 0x368 0x000 0x1 0x0
#define MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x100 0x368 0x000 0x5 0x0
#define MX8MQ_IOMUXC_NAND_CE2_B_SIM_M_HPROT3 0x100 0x368 0x000 0x7 0x0
#define MX8MQ_IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x104 0x36C 0x000 0x0 0x0
#define MX8MQ_IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x104 0x36C 0x000 0x1 0x0
#define MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x104 0x36C 0x000 0x5 0x0
#define MX8MQ_IOMUXC_NAND_CE3_B_SIM_M_HADDR0 0x104 0x36C 0x000 0x7 0x0
#define MX8MQ_IOMUXC_NAND_CLE_RAWNAND_CLE 0x108 0x370 0x000 0x0 0x0
#define MX8MQ_IOMUXC_NAND_CLE_QSPI_B_SCLK 0x108 0x370 0x000 0x1 0x0
#define MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x108 0x370 0x000 0x5 0x0
#define MX8MQ_IOMUXC_NAND_CLE_SIM_M_HADDR1 0x108 0x370 0x000 0x7 0x0
#define MX8MQ_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x10C 0x374 0x000 0x0 0x0
#define MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x10C 0x374 0x000 0x1 0x0
#define MX8MQ_IOMUXC_NAND_DATA00_GPIO3_IO6 0x10C 0x374 0x000 0x5 0x0
#define MX8MQ_IOMUXC_NAND_DATA00_SIM_M_HADDR2 0x10C 0x374 0x000 0x7 0x0
#define MX8MQ_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x110 0x378 0x000 0x0 0x0
#define MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x110 0x378 0x000 0x1 0x0
#define MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x110 0x378 0x000 0x5 0x0
#define MX8MQ_IOMUXC_NAND_DATA01_SIM_M_HADDR3 0x110 0x378 0x000 0x7 0x0
#define MX8MQ_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x114 0x37C 0x000 0x0 0x0
#define MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x114 0x37C 0x000 0x1 0x0
#define MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x114 0x37C 0x000 0x5 0x0
#define MX8MQ_IOMUXC_NAND_DATA02_SIM_M_HADDR4 0x114 0x37C 0x000 0x7 0x0
#define MX8MQ_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x118 0x380 0x000 0x0 0x0
#define MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x118 0x380 0x000 0x1 0x0
#define MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x118 0x380 0x000 0x5 0x0
#define MX8MQ_IOMUXC_NAND_DATA03_SIM_M_HADDR5 0x118 0x380 0x000 0x7 0x0
#define MX8MQ_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x11C 0x384 0x000 0x0 0x0
#define MX8MQ_IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x11C 0x384 0x000 0x1 0x0
#define MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x11C 0x384 0x000 0x5 0x0
#define MX8MQ_IOMUXC_NAND_DATA04_SIM_M_HADDR6 0x11C 0x384 0x000 0x7 0x0
#define MX8MQ_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x120 0x388 0x000 0x0 0x0
#define MX8MQ_IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x120 0x388 0x000 0x1 0x0
#define MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x120 0x388 0x000 0x5 0x0
#define MX8MQ_IOMUXC_NAND_DATA05_SIM_M_HADDR7 0x120 0x388 0x000 0x7 0x0
#define MX8MQ_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x124 0x38C 0x000 0x0 0x0
#define MX8MQ_IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x124 0x38C 0x000 0x1 0x0
#define MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x124 0x38C 0x000 0x5 0x0
#define MX8MQ_IOMUXC_NAND_DATA06_SIM_M_HADDR8 0x124 0x38C 0x000 0x7 0x0
#define MX8MQ_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x128 0x390 0x000 0x0 0x0
#define MX8MQ_IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x128 0x390 0x000 0x1 0x0
#define MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13 0x128 0x390 0x000 0x5 0x0
#define MX8MQ_IOMUXC_NAND_DATA07_SIM_M_HADDR9 0x128 0x390 0x000 0x7 0x0
#define MX8MQ_IOMUXC_NAND_DQS_RAWNAND_DQS 0x12C 0x394 0x000 0x0 0x0
#define MX8MQ_IOMUXC_NAND_DQS_QSPI_A_DQS 0x12C 0x394 0x000 0x1 0x0
#define MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x12C 0x394 0x000 0x5 0x0
#define MX8MQ_IOMUXC_NAND_DQS_SIM_M_HADDR10 0x12C 0x394 0x000 0x7 0x0
#define MX8MQ_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x130 0x398 0x000 0x0 0x0
#define MX8MQ_IOMUXC_NAND_RE_B_QSPI_B_DQS 0x130 0x398 0x000 0x1 0x0
#define MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x130 0x398 0x000 0x5 0x0
#define MX8MQ_IOMUXC_NAND_RE_B_SIM_M_HADDR11 0x130 0x398 0x000 0x7 0x0
#define MX8MQ_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x134 0x39C 0x000 0x0 0x0
#define MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x134 0x39C 0x000 0x5 0x0
#define MX8MQ_IOMUXC_NAND_READY_B_SIM_M_HADDR12 0x134 0x39C 0x000 0x7 0x0
#define MX8MQ_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x138 0x3A0 0x000 0x0 0x0
#define MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x138 0x3A0 0x000 0x5 0x0
#define MX8MQ_IOMUXC_NAND_WE_B_SIM_M_HADDR13 0x138 0x3A0 0x000 0x7 0x0
#define MX8MQ_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x13C 0x3A4 0x000 0x0 0x0
#define MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x13C 0x3A4 0x000 0x5 0x0
#define MX8MQ_IOMUXC_NAND_WP_B_SIM_M_HADDR14 0x13C 0x3A4 0x000 0x7 0x0
#define MX8MQ_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x140 0x3A8 0x4E4 0x0 0x0
#define MX8MQ_IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x140 0x3A8 0x000 0x1 0x0
#define MX8MQ_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x140 0x3A8 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x144 0x3AC 0x4D0 0x0 0x0
#define MX8MQ_IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x144 0x3AC 0x000 0x1 0x0
#define MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x144 0x3AC 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x148 0x3B0 0x4D4 0x0 0x0
#define MX8MQ_IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x148 0x3B0 0x000 0x1 0x0
#define MX8MQ_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x148 0x3B0 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x14C 0x3B4 0x4D8 0x0 0x0
#define MX8MQ_IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x14C 0x3B4 0x000 0x1 0x0
#define MX8MQ_IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x14C 0x3B4 0x4CC 0x2 0x0
#define MX8MQ_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x14C 0x3B4 0x4EC 0x3 0x0
#define MX8MQ_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x14C 0x3B4 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x150 0x3B8 0x4DC 0x0 0x0
#define MX8MQ_IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x150 0x3B8 0x000 0x1 0x0
#define MX8MQ_IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x150 0x3B8 0x4CC 0x2 0x1
#define MX8MQ_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x150 0x3B8 0x4E8 0x3 0x0
#define MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x150 0x3B8 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x154 0x3BC 0x4E0 0x0 0x0
#define MX8MQ_IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x154 0x3BC 0x000 0x1 0x0
#define MX8MQ_IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x154 0x3BC 0x4CC 0x2 0x2
#define MX8MQ_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x154 0x3BC 0x000 0x3 0x0
#define MX8MQ_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x154 0x3BC 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SAI5_MCLK_SAI5_MCLK 0x158 0x3C0 0x52C 0x0 0x0
#define MX8MQ_IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x158 0x3C0 0x4C8 0x1 0x0
#define MX8MQ_IOMUXC_SAI5_MCLK_SAI4_MCLK 0x158 0x3C0 0x000 0x2 0x0
#define MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x158 0x3C0 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SAI5_MCLK_CCMSRCGPCMIX_TESTER_ACK 0x158 0x3C0 0x000 0x6 0x0
#define MX8MQ_IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x15C 0x3C4 0x4C4 0x0 0x0
#define MX8MQ_IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x15C 0x3C4 0x4E4 0x1 0x1
#define MX8MQ_IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x15C 0x3C4 0x000 0x4 0x0
#define MX8MQ_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x15C 0x3C4 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SAI1_RXFS_SIM_M_HADDR15 0x15C 0x3C4 0x000 0x7 0x0
#define MX8MQ_IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x160 0x3C8 0x000 0x0 0x0
#define MX8MQ_IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x160 0x3C8 0x4D0 0x1 0x1
#define MX8MQ_IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x160 0x3C8 0x000 0x4 0x0
#define MX8MQ_IOMUXC_SAI1_RXC_GPIO4_IO1 0x160 0x3C8 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SAI1_RXC_SIM_M_HADDR16 0x160 0x3C8 0x000 0x7 0x0
#define MX8MQ_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x164 0x3CC 0x000 0x0 0x0
#define MX8MQ_IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x164 0x3CC 0x4D4 0x1 0x1
#define MX8MQ_IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x164 0x3CC 0x000 0x4 0x0
#define MX8MQ_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x164 0x3CC 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SAI1_RXD0_CCMSRCGPCMIX_BOOT_CFG0 0x164 0x3CC 0x000 0x6 0x0
#define MX8MQ_IOMUXC_SAI1_RXD0_SIM_M_HADDR17 0x164 0x3CC 0x000 0x7 0x0
#define MX8MQ_IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x168 0x3D0 0x000 0x0 0x0
#define MX8MQ_IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x168 0x3D0 0x4D8 0x1 0x1
#define MX8MQ_IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x168 0x3D0 0x000 0x4 0x0
#define MX8MQ_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x168 0x3D0 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SAI1_RXD1_CCMSRCGPCMIX_BOOT_CFG1 0x168 0x3D0 0x000 0x6 0x0
#define MX8MQ_IOMUXC_SAI1_RXD1_SIM_M_HADDR18 0x168 0x3D0 0x000 0x7 0x0
#define MX8MQ_IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x16C 0x3D4 0x000 0x0 0x0
#define MX8MQ_IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x16C 0x3D4 0x4DC 0x1 0x1
#define MX8MQ_IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x16C 0x3D4 0x000 0x4 0x0
#define MX8MQ_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x16C 0x3D4 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SAI1_RXD2_CCMSRCGPCMIX_BOOT_CFG2 0x16C 0x3D4 0x000 0x6 0x0
#define MX8MQ_IOMUXC_SAI1_RXD2_SIM_M_HADDR19 0x16C 0x3D4 0x000 0x7 0x0
#define MX8MQ_IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x170 0x3D8 0x4E0 0x0 0x1
#define MX8MQ_IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x170 0x3D8 0x000 0x1 0x0
#define MX8MQ_IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x170 0x3D8 0x000 0x4 0x0
#define MX8MQ_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x170 0x3D8 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SAI1_RXD3_CCMSRCGPCMIX_BOOT_CFG3 0x170 0x3D8 0x000 0x6 0x0
#define MX8MQ_IOMUXC_SAI1_RXD3_SIM_M_HADDR20 0x170 0x3D8 0x000 0x7 0x0
#define MX8MQ_IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x174 0x3DC 0x000 0x0 0x0
#define MX8MQ_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x174 0x3DC 0x51C 0x1 0x0
#define MX8MQ_IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x174 0x3DC 0x510 0x2 0x0
#define MX8MQ_IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x174 0x3DC 0x000 0x4 0x0
#define MX8MQ_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x174 0x3DC 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SAI1_RXD4_CCMSRCGPCMIX_BOOT_CFG4 0x174 0x3DC 0x000 0x6 0x0
#define MX8MQ_IOMUXC_SAI1_RXD4_SIM_M_HADDR21 0x174 0x3DC 0x000 0x7 0x0
#define MX8MQ_IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x178 0x3E0 0x000 0x0 0x0
#define MX8MQ_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x178 0x3E0 0x000 0x1 0x0
#define MX8MQ_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x178 0x3E0 0x514 0x2 0x0
#define MX8MQ_IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x178 0x3E0 0x4C4 0x3 0x1
#define MX8MQ_IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x178 0x3E0 0x000 0x4 0x0
#define MX8MQ_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x178 0x3E0 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SAI1_RXD5_CCMSRCGPCMIX_BOOT_CFG5 0x178 0x3E0 0x000 0x6 0x0
#define MX8MQ_IOMUXC_SAI1_RXD5_SIM_M_HADDR22 0x178 0x3E0 0x000 0x7 0x0
#define MX8MQ_IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x17C 0x3E4 0x520 0x0 0x0
#define MX8MQ_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x17C 0x3E4 0x000 0x1 0x0
#define MX8MQ_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x17C 0x3E4 0x518 0x2 0x0
#define MX8MQ_IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x17C 0x3E4 0x000 0x4 0x0
#define MX8MQ_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x17C 0x3E4 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SAI1_RXD6_CCMSRCGPCMIX_BOOT_CFG6 0x17C 0x3E4 0x000 0x6 0x0
#define MX8MQ_IOMUXC_SAI1_RXD6_SIM_M_HADDR23 0x17C 0x3E4 0x000 0x7 0x0
#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x180 0x3E8 0x000 0x0 0x0
#define MX8MQ_IOMUXC_SAI1_RXD7_SAI6_MCLK 0x180 0x3E8 0x530 0x1 0x0
#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x180 0x3E8 0x4CC 0x2 0x4
#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x180 0x3E8 0x000 0x3 0x0
#define MX8MQ_IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x180 0x3E8 0x000 0x4 0x0
#define MX8MQ_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x180 0x3E8 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SAI1_RXD7_CCMSRCGPCMIX_BOOT_CFG7 0x180 0x3E8 0x000 0x6 0x0
#define MX8MQ_IOMUXC_SAI1_RXD7_SIM_M_HADDR24 0x180 0x3E8 0x000 0x7 0x0
#define MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x184 0x3EC 0x4CC 0x0 0x3
#define MX8MQ_IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x184 0x3EC 0x4EC 0x1 0x1
#define MX8MQ_IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x184 0x3EC 0x000 0x4 0x0
#define MX8MQ_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x184 0x3EC 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SAI1_TXFS_SIM_M_HADDR25 0x184 0x3EC 0x000 0x7 0x0
#define MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x188 0x3F0 0x4C8 0x0 0x1
#define MX8MQ_IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x188 0x3F0 0x4E8 0x1 0x1
#define MX8MQ_IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x188 0x3F0 0x000 0x4 0x0
#define MX8MQ_IOMUXC_SAI1_TXC_GPIO4_IO11 0x188 0x3F0 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SAI1_TXC_SIM_M_HADDR26 0x188 0x3F0 0x000 0x7 0x0
#define MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x18C 0x3F4 0x000 0x0 0x0
#define MX8MQ_IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x18C 0x3F4 0x000 0x1 0x0
#define MX8MQ_IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x18C 0x3F4 0x000 0x4 0x0
#define MX8MQ_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x18C 0x3F4 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SAI1_TXD0_CCMSRCGPCMIX_BOOT_CFG8 0x18C 0x3F4 0x000 0x6 0x0
#define MX8MQ_IOMUXC_SAI1_TXD0_SIM_M_HADDR27 0x18C 0x3F4 0x000 0x7 0x0
#define MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x190 0x3F8 0x000 0x0 0x0
#define MX8MQ_IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x190 0x3F8 0x000 0x1 0x0
#define MX8MQ_IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x190 0x3F8 0x000 0x4 0x0
#define MX8MQ_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x190 0x3F8 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SAI1_TXD1_CCMSRCGPCMIX_BOOT_CFG9 0x190 0x3F8 0x000 0x6 0x0
#define MX8MQ_IOMUXC_SAI1_TXD1_SIM_M_HADDR28 0x190 0x3F8 0x000 0x7 0x0
#define MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x194 0x3FC 0x000 0x0 0x0
#define MX8MQ_IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x194 0x3FC 0x000 0x1 0x0
#define MX8MQ_IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x194 0x3FC 0x000 0x4 0x0
#define MX8MQ_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x194 0x3FC 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SAI1_TXD2_CCMSRCGPCMIX_BOOT_CFG10 0x194 0x3FC 0x000 0x6 0x0
#define MX8MQ_IOMUXC_SAI1_TXD2_SIM_M_HADDR29 0x194 0x3FC 0x000 0x7 0x0
#define MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x198 0x400 0x000 0x0 0x0
#define MX8MQ_IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x198 0x400 0x000 0x1 0x0
#define MX8MQ_IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x198 0x400 0x000 0x4 0x0
#define MX8MQ_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x198 0x400 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SAI1_TXD3_CCMSRCGPCMIX_BOOT_CFG11 0x198 0x400 0x000 0x6 0x0
#define MX8MQ_IOMUXC_SAI1_TXD3_SIM_M_HADDR30 0x198 0x400 0x000 0x7 0x0
#define MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x19C 0x404 0x000 0x0 0x0
#define MX8MQ_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x19C 0x404 0x510 0x1 0x1
#define MX8MQ_IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x19C 0x404 0x51C 0x2 0x1
#define MX8MQ_IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x19C 0x404 0x000 0x4 0x0
#define MX8MQ_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x19C 0x404 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SAI1_TXD4_CCMSRCGPCMIX_BOOT_CFG12 0x19C 0x404 0x000 0x6 0x0
#define MX8MQ_IOMUXC_SAI1_TXD4_SIM_M_HADDR31 0x19C 0x404 0x000 0x7 0x0
#define MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x1A0 0x408 0x000 0x0 0x0
#define MX8MQ_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x1A0 0x408 0x514 0x1 0x1
#define MX8MQ_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x1A0 0x408 0x000 0x2 0x0
#define MX8MQ_IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x1A0 0x408 0x000 0x4 0x0
#define MX8MQ_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x1A0 0x408 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SAI1_TXD5_CCMSRCGPCMIX_BOOT_CFG13 0x1A0 0x408 0x000 0x6 0x0
#define MX8MQ_IOMUXC_SAI1_TXD5_SIM_M_HBURST0 0x1A0 0x408 0x000 0x7 0x0
#define MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x1A4 0x40C 0x000 0x0 0x0
#define MX8MQ_IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x1A4 0x40C 0x518 0x1 0x1
#define MX8MQ_IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x1A4 0x40C 0x520 0x2 0x1
#define MX8MQ_IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x1A4 0x40C 0x000 0x4 0x0
#define MX8MQ_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x1A4 0x40C 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SAI1_TXD6_CCMSRCGPCMIX_BOOT_CFG14 0x1A4 0x40C 0x000 0x6 0x0
#define MX8MQ_IOMUXC_SAI1_TXD6_SIM_M_HBURST1 0x1A4 0x40C 0x000 0x7 0x0
#define MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x1A8 0x410 0x000 0x0 0x0
#define MX8MQ_IOMUXC_SAI1_TXD7_SAI6_MCLK 0x1A8 0x410 0x530 0x1 0x1
#define MX8MQ_IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x1A8 0x410 0x000 0x4 0x0
#define MX8MQ_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x1A8 0x410 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SAI1_TXD7_CCMSRCGPCMIX_BOOT_CFG15 0x1A8 0x410 0x000 0x6 0x0
#define MX8MQ_IOMUXC_SAI1_TXD7_SIM_M_HBURST2 0x1A8 0x410 0x000 0x7 0x0
#define MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0x1AC 0x414 0x000 0x0 0x0
#define MX8MQ_IOMUXC_SAI1_MCLK_SAI5_MCLK 0x1AC 0x414 0x52C 0x1 0x1
#define MX8MQ_IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x1AC 0x414 0x4C8 0x2 0x2
#define MX8MQ_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x1AC 0x414 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SAI1_MCLK_SIM_M_HRESP 0x1AC 0x414 0x000 0x7 0x0
#define MX8MQ_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x1B0 0x418 0x000 0x0 0x0
#define MX8MQ_IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x1B0 0x418 0x4EC 0x1 0x2
#define MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x1B0 0x418 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SAI2_RXFS_SIM_M_HSIZE0 0x1B0 0x418 0x000 0x7 0x0
#define MX8MQ_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x1B4 0x41C 0x000 0x0 0x0
#define MX8MQ_IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x1B4 0x41C 0x4E8 0x1 0x2
#define MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22 0x1B4 0x41C 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SAI2_RXC_SIM_M_HSIZE1 0x1B4 0x41C 0x000 0x7 0x0
#define MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x1B8 0x420 0x000 0x0 0x0
#define MX8MQ_IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x1B8 0x420 0x000 0x1 0x0
#define MX8MQ_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x1B8 0x420 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SAI2_RXD0_SIM_M_HSIZE2 0x1B8 0x420 0x000 0x7 0x0
#define MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x1BC 0x424 0x000 0x0 0x0
#define MX8MQ_IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x1BC 0x424 0x000 0x1 0x0
#define MX8MQ_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x1BC 0x424 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SAI2_TXFS_SIM_M_HWRITE 0x1BC 0x424 0x000 0x7 0x0
#define MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x1C0 0x428 0x000 0x0 0x0
#define MX8MQ_IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x1C0 0x428 0x000 0x1 0x0
#define MX8MQ_IOMUXC_SAI2_TXC_GPIO4_IO25 0x1C0 0x428 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SAI2_TXC_SIM_M_HREADYOUT 0x1C0 0x428 0x000 0x7 0x0
#define MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x1C4 0x42C 0x000 0x0 0x0
#define MX8MQ_IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x1C4 0x42C 0x000 0x1 0x0
#define MX8MQ_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x1C4 0x42C 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SAI2_TXD0_TPSMP_CLK 0x1C4 0x42C 0x000 0x7 0x0
#define MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x1C8 0x430 0x000 0x0 0x0
#define MX8MQ_IOMUXC_SAI2_MCLK_SAI5_MCLK 0x1C8 0x430 0x52C 0x1 0x2
#define MX8MQ_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x1C8 0x430 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SAI2_MCLK_TPSMP_HDATA_DIR 0x1C8 0x430 0x000 0x7 0x0
#define MX8MQ_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x1CC 0x434 0x000 0x0 0x0
#define MX8MQ_IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x1CC 0x434 0x000 0x1 0x0
#define MX8MQ_IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x1CC 0x434 0x4E4 0x2 0x2
#define MX8MQ_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x1CC 0x434 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SAI3_RXFS_TPSMP_HTRANS0 0x1CC 0x434 0x000 0x7 0x0
#define MX8MQ_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x1D0 0x438 0x000 0x0 0x0
#define MX8MQ_IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x1D0 0x438 0x000 0x1 0x0
#define MX8MQ_IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x1D0 0x438 0x4D0 0x2 0x2
#define MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x1D0 0x438 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SAI3_RXC_TPSMP_HTRANS1 0x1D0 0x438 0x000 0x7 0x0
#define MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x1D4 0x43C 0x000 0x0 0x0
#define MX8MQ_IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x1D4 0x43C 0x000 0x1 0x0
#define MX8MQ_IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x1D4 0x43C 0x4D4 0x2 0x2
#define MX8MQ_IOMUXC_SAI3_RXD_GPIO4_IO30 0x1D4 0x43C 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SAI3_RXD_TPSMP_HDATA0 0x1D4 0x43C 0x000 0x7 0x0
#define MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x1D8 0x440 0x000 0x0 0x0
#define MX8MQ_IOMUXC_SAI3_TXFS_GPT1_CLK 0x1D8 0x440 0x000 0x1 0x0
#define MX8MQ_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x1D8 0x440 0x4D8 0x2 0x2
#define MX8MQ_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x1D8 0x440 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SAI3_TXFS_TPSMP_HDATA1 0x1D8 0x440 0x000 0x7 0x0
#define MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x1DC 0x444 0x000 0x0 0x0
#define MX8MQ_IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x1DC 0x444 0x000 0x1 0x0
#define MX8MQ_IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x1DC 0x444 0x4DC 0x2 0x2
#define MX8MQ_IOMUXC_SAI3_TXC_GPIO5_IO0 0x1DC 0x444 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SAI3_TXC_TPSMP_HDATA2 0x1DC 0x444 0x000 0x7 0x0
#define MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x1E0 0x448 0x000 0x0 0x0
#define MX8MQ_IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x1E0 0x448 0x000 0x1 0x0
#define MX8MQ_IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x1E0 0x448 0x4E0 0x2 0x2
#define MX8MQ_IOMUXC_SAI3_TXD_GPIO5_IO1 0x1E0 0x448 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SAI3_TXD_TPSMP_HDATA3 0x1E0 0x448 0x000 0x7 0x0
#define MX8MQ_IOMUXC_SAI3_MCLK_SAI3_MCLK 0x1E4 0x44C 0x000 0x0 0x0
#define MX8MQ_IOMUXC_SAI3_MCLK_PWM4_OUT 0x1E4 0x44C 0x000 0x1 0x0
#define MX8MQ_IOMUXC_SAI3_MCLK_SAI5_MCLK 0x1E4 0x44C 0x52C 0x2 0x3
#define MX8MQ_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x1E4 0x44C 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SAI3_MCLK_TPSMP_HDATA4 0x1E4 0x44C 0x000 0x7 0x0
#define MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT 0x1E8 0x450 0x000 0x0 0x0
#define MX8MQ_IOMUXC_SPDIF_TX_PWM3_OUT 0x1E8 0x450 0x000 0x1 0x0
#define MX8MQ_IOMUXC_SPDIF_TX_GPIO5_IO3 0x1E8 0x450 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SPDIF_TX_TPSMP_HDATA5 0x1E8 0x450 0x000 0x7 0x0
#define MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN 0x1EC 0x454 0x000 0x0 0x0
#define MX8MQ_IOMUXC_SPDIF_RX_PWM2_OUT 0x1EC 0x454 0x000 0x1 0x0
#define MX8MQ_IOMUXC_SPDIF_RX_GPIO5_IO4 0x1EC 0x454 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SPDIF_RX_TPSMP_HDATA6 0x1EC 0x454 0x000 0x7 0x0
#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x1F0 0x458 0x000 0x0 0x0
#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x1F0 0x458 0x000 0x1 0x0
#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x1F0 0x458 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_TPSMP_HDATA7 0x1F0 0x458 0x000 0x7 0x0
#define MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x1F4 0x45C 0x000 0x0 0x0
#define MX8MQ_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x1F4 0x45C 0x504 0x1 0x0
#define MX8MQ_IOMUXC_ECSPI1_SCLK_UART3_DTE_TX 0x1F4 0x45C 0x000 0x1 0x0
#define MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x1F4 0x45C 0x000 0x5 0x0
#define MX8MQ_IOMUXC_ECSPI1_SCLK_TPSMP_HDATA8 0x1F4 0x45C 0x000 0x7 0x0
#define MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x1F8 0x460 0x000 0x0 0x0
#define MX8MQ_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x1F8 0x460 0x000 0x1 0x0
#define MX8MQ_IOMUXC_ECSPI1_MOSI_UART3_DTE_RX 0x1F8 0x460 0x504 0x1 0x1
#define MX8MQ_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x1F8 0x460 0x000 0x5 0x0
#define MX8MQ_IOMUXC_ECSPI1_MOSI_TPSMP_HDATA9 0x1F8 0x460 0x000 0x7 0x0
#define MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x1FC 0x464 0x000 0x0 0x0
#define MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x1FC 0x464 0x000 0x1 0x0
#define MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DTE_RTS_B 0x1FC 0x464 0x500 0x1 0x0
#define MX8MQ_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x1FC 0x464 0x000 0x5 0x0
#define MX8MQ_IOMUXC_ECSPI1_MISO_TPSMP_HDATA10 0x1FC 0x464 0x000 0x7 0x0
#define MX8MQ_IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x200 0x468 0x000 0x0 0x0
#define MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x200 0x468 0x500 0x1 0x1
#define MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DTE_CTS_B 0x200 0x468 0x000 0x1 0x0
#define MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x200 0x468 0x000 0x5 0x0
#define MX8MQ_IOMUXC_ECSPI1_SS0_TPSMP_HDATA11 0x200 0x468 0x000 0x7 0x0
#define MX8MQ_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x204 0x46C 0x000 0x0 0x0
#define MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x204 0x46C 0x50C 0x1 0x0
#define MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DTE_TX 0x204 0x46C 0x000 0x1 0x0
#define MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x204 0x46C 0x000 0x5 0x0
#define MX8MQ_IOMUXC_ECSPI2_SCLK_TPSMP_HDATA12 0x204 0x46C 0x000 0x7 0x0
#define MX8MQ_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x208 0x470 0x000 0x0 0x0
#define MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x208 0x470 0x000 0x1 0x0
#define MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DTE_RX 0x208 0x470 0x50C 0x1 0x1
#define MX8MQ_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x208 0x470 0x000 0x5 0x0
#define MX8MQ_IOMUXC_ECSPI2_MOSI_TPSMP_HDATA13 0x208 0x470 0x000 0x7 0x0
#define MX8MQ_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x20C 0x474 0x000 0x0 0x0
#define MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x20C 0x474 0x000 0x1 0x0
#define MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DTE_RTS_B 0x20C 0x474 0x508 0x1 0x0
#define MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x20C 0x474 0x000 0x5 0x0
#define MX8MQ_IOMUXC_ECSPI2_MISO_TPSMP_HDATA14 0x20C 0x474 0x000 0x7 0x0
#define MX8MQ_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x210 0x478 0x000 0x0 0x0
#define MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x210 0x478 0x508 0x1 0x1
#define MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DTE_CTS_B 0x210 0x478 0x000 0x1 0x0
#define MX8MQ_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x210 0x478 0x000 0x5 0x0
#define MX8MQ_IOMUXC_ECSPI2_SS0_TPSMP_HDATA15 0x210 0x478 0x000 0x7 0x0
#define MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x214 0x47C 0x000 0x0 0x0
#define MX8MQ_IOMUXC_I2C1_SCL_ENET1_MDC 0x214 0x47C 0x000 0x1 0x0
#define MX8MQ_IOMUXC_I2C1_SCL_GPIO5_IO14 0x214 0x47C 0x000 0x5 0x0
#define MX8MQ_IOMUXC_I2C1_SCL_TPSMP_HDATA16 0x214 0x47C 0x000 0x7 0x0
#define MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x218 0x480 0x000 0x0 0x0
#define MX8MQ_IOMUXC_I2C1_SDA_ENET1_MDIO 0x218 0x480 0x4C0 0x1 0x2
#define MX8MQ_IOMUXC_I2C1_SDA_GPIO5_IO15 0x218 0x480 0x000 0x5 0x0
#define MX8MQ_IOMUXC_I2C1_SDA_TPSMP_HDATA17 0x218 0x480 0x000 0x7 0x0
#define MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x21C 0x484 0x000 0x0 0x0
#define MX8MQ_IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x21C 0x484 0x000 0x1 0x0
#define MX8MQ_IOMUXC_I2C2_SCL_GPIO5_IO16 0x21C 0x484 0x000 0x5 0x0
#define MX8MQ_IOMUXC_I2C2_SCL_TPSMP_HDATA18 0x21C 0x484 0x000 0x7 0x0
#define MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x220 0x488 0x000 0x0 0x0
#define MX8MQ_IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x220 0x488 0x000 0x1 0x0
#define MX8MQ_IOMUXC_I2C2_SDA_GPIO5_IO17 0x220 0x488 0x000 0x5 0x0
#define MX8MQ_IOMUXC_I2C2_SDA_TPSMP_HDATA19 0x220 0x488 0x000 0x7 0x0
#define MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x224 0x48C 0x000 0x0 0x0
#define MX8MQ_IOMUXC_I2C3_SCL_PWM4_OUT 0x224 0x48C 0x000 0x1 0x0
#define MX8MQ_IOMUXC_I2C3_SCL_GPT2_CLK 0x224 0x48C 0x000 0x2 0x0
#define MX8MQ_IOMUXC_I2C3_SCL_GPIO5_IO18 0x224 0x48C 0x000 0x5 0x0
#define MX8MQ_IOMUXC_I2C3_SCL_TPSMP_HDATA20 0x224 0x48C 0x000 0x7 0x0
#define MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x228 0x490 0x000 0x0 0x0
#define MX8MQ_IOMUXC_I2C3_SDA_PWM3_OUT 0x228 0x490 0x000 0x1 0x0
#define MX8MQ_IOMUXC_I2C3_SDA_GPT3_CLK 0x228 0x490 0x000 0x2 0x0
#define MX8MQ_IOMUXC_I2C3_SDA_GPIO5_IO19 0x228 0x490 0x000 0x5 0x0
#define MX8MQ_IOMUXC_I2C3_SDA_TPSMP_HDATA21 0x228 0x490 0x000 0x7 0x0
#define MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x22C 0x494 0x000 0x0 0x0
#define MX8MQ_IOMUXC_I2C4_SCL_PWM2_OUT 0x22C 0x494 0x000 0x1 0x0
#define MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x22C 0x494 0x524 0x2 0x0
#define MX8MQ_IOMUXC_I2C4_SCL_GPIO5_IO20 0x22C 0x494 0x000 0x5 0x0
#define MX8MQ_IOMUXC_I2C4_SCL_TPSMP_HDATA22 0x22C 0x494 0x000 0x7 0x0
#define MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x230 0x498 0x000 0x0 0x0
#define MX8MQ_IOMUXC_I2C4_SDA_PWM1_OUT 0x230 0x498 0x000 0x1 0x0
#define MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x230 0x498 0x528 0x2 0x0
#define MX8MQ_IOMUXC_I2C4_SDA_GPIO5_IO21 0x230 0x498 0x000 0x5 0x0
#define MX8MQ_IOMUXC_I2C4_SDA_TPSMP_HDATA23 0x230 0x498 0x000 0x7 0x0
#define MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x234 0x49C 0x4F4 0x0 0x0
#define MX8MQ_IOMUXC_UART1_RXD_UART1_DTE_TX 0x234 0x49C 0x000 0x0 0x0
#define MX8MQ_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x234 0x49C 0x000 0x1 0x0
#define MX8MQ_IOMUXC_UART1_RXD_GPIO5_IO22 0x234 0x49C 0x000 0x5 0x0
#define MX8MQ_IOMUXC_UART1_RXD_TPSMP_HDATA24 0x234 0x49C 0x000 0x7 0x0
#define MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x238 0x4A0 0x000 0x0 0x0
#define MX8MQ_IOMUXC_UART1_TXD_UART1_DTE_RX 0x238 0x4A0 0x4F4 0x0 0x0
#define MX8MQ_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x238 0x4A0 0x000 0x1 0x0
#define MX8MQ_IOMUXC_UART1_TXD_GPIO5_IO23 0x238 0x4A0 0x000 0x5 0x0
#define MX8MQ_IOMUXC_UART1_TXD_TPSMP_HDATA25 0x238 0x4A0 0x000 0x7 0x0
#define MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x23C 0x4A4 0x4FC 0x0 0x0
#define MX8MQ_IOMUXC_UART2_RXD_UART2_DTE_TX 0x23C 0x4A4 0x000 0x0 0x0
#define MX8MQ_IOMUXC_UART2_RXD_ECSPI3_MISO 0x23C 0x4A4 0x000 0x1 0x0
#define MX8MQ_IOMUXC_UART2_RXD_GPIO5_IO24 0x23C 0x4A4 0x000 0x5 0x0
#define MX8MQ_IOMUXC_UART2_RXD_TPSMP_HDATA26 0x23C 0x4A4 0x000 0x7 0x0
#define MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x240 0x4A8 0x000 0x0 0x0
#define MX8MQ_IOMUXC_UART2_TXD_UART2_DTE_RX 0x240 0x4A8 0x4FC 0x0 0x1
#define MX8MQ_IOMUXC_UART2_TXD_ECSPI3_SS0 0x240 0x4A8 0x000 0x1 0x0
#define MX8MQ_IOMUXC_UART2_TXD_GPIO5_IO25 0x240 0x4A8 0x000 0x5 0x0
#define MX8MQ_IOMUXC_UART2_TXD_TPSMP_HDATA27 0x240 0x4A8 0x000 0x7 0x0
#define MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x244 0x4AC 0x504 0x0 0x2
#define MX8MQ_IOMUXC_UART3_RXD_UART3_DTE_TX 0x244 0x4AC 0x000 0x0 0x0
#define MX8MQ_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x244 0x4AC 0x000 0x1 0x0
#define MX8MQ_IOMUXC_UART3_RXD_UART1_DTE_RTS_B 0x244 0x4AC 0x4F0 0x1 0x0
#define MX8MQ_IOMUXC_UART3_RXD_GPIO5_IO26 0x244 0x4AC 0x000 0x5 0x0
#define MX8MQ_IOMUXC_UART3_RXD_TPSMP_HDATA28 0x244 0x4AC 0x000 0x7 0x0
#define MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x248 0x4B0 0x000 0x0 0x0
#define MX8MQ_IOMUXC_UART3_TXD_UART3_DTE_RX 0x248 0x4B0 0x504 0x0 0x3
#define MX8MQ_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x248 0x4B0 0x4F0 0x1 0x1
#define MX8MQ_IOMUXC_UART3_TXD_UART1_DTE_CTS_B 0x248 0x4B0 0x000 0x1 0x0
#define MX8MQ_IOMUXC_UART3_TXD_GPIO5_IO27 0x248 0x4B0 0x000 0x5 0x0
#define MX8MQ_IOMUXC_UART3_TXD_TPSMP_HDATA29 0x248 0x4B0 0x000 0x7 0x0
#define MX8MQ_IOMUXC_UART4_RXD_UART4_DCE_RX 0x24C 0x4B4 0x50C 0x0 0x2
#define MX8MQ_IOMUXC_UART4_RXD_UART4_DTE_TX 0x24C 0x4B4 0x000 0x0 0x0
#define MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x24C 0x4B4 0x000 0x1 0x0
#define MX8MQ_IOMUXC_UART4_RXD_UART2_DTE_RTS_B 0x24C 0x4B4 0x4F8 0x1 0x0
#define MX8MQ_IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x24C 0x4B4 0x524 0x2 0x1
#define MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x24C 0x4B4 0x000 0x5 0x0
#define MX8MQ_IOMUXC_UART4_RXD_TPSMP_HDATA30 0x24C 0x4B4 0x000 0x7 0x0
#define MX8MQ_IOMUXC_UART4_TXD_UART4_DCE_TX 0x250 0x4B8 0x000 0x0 0x0
#define MX8MQ_IOMUXC_UART4_TXD_UART4_DTE_RX 0x250 0x4B8 0x50C 0x0 0x3
#define MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x250 0x4B8 0x4F8 0x1 0x1
#define MX8MQ_IOMUXC_UART4_TXD_UART2_DTE_CTS_B 0x250 0x4B8 0x000 0x1 0x0
#define MX8MQ_IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x250 0x4B8 0x528 0x2 0x1
#define MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x250 0x4B8 0x000 0x5 0x0
#define MX8MQ_IOMUXC_UART4_TXD_TPSMP_HDATA31 0x250 0x4B8 0x000 0x7 0x0
#define MX8MQ_IOMUXC_TEST_MODE 0x000 0x254 0x000 0x0 0x0
#define MX8MQ_IOMUXC_BOOT_MODE0 0x000 0x258 0x000 0x0 0x0
#define MX8MQ_IOMUXC_BOOT_MODE1 0x000 0x25C 0x000 0x0 0x0
#define MX8MQ_IOMUXC_JTAG_MOD 0x000 0x260 0x000 0x0 0x0
#define MX8MQ_IOMUXC_JTAG_TRST_B 0x000 0x264 0x000 0x0 0x0
#define MX8MQ_IOMUXC_JTAG_TDI 0x000 0x268 0x000 0x0 0x0
#define MX8MQ_IOMUXC_JTAG_TMS 0x000 0x26C 0x000 0x0 0x0
#define MX8MQ_IOMUXC_JTAG_TCK 0x000 0x270 0x000 0x0 0x0
#define MX8MQ_IOMUXC_JTAG_TDO 0x000 0x274 0x000 0x0 0x0
#define MX8MQ_IOMUXC_RTC 0x000 0x278 0x000 0x0 0x0
#endif /* __DTS_IMX8MQ_PINFUNC_H */

View File

@@ -144,7 +144,6 @@
};
#endif
#ifdef CONFIG_OPTEE
tee: tee {
description = "OP-TEE";
type = "tee";
@@ -156,9 +155,9 @@
tee-os {
filename = "tee.bin";
optional;
};
};
#endif
fdt {
compression = "none";
@@ -180,11 +179,7 @@
fdt = "fdt";
firmware = "uboot";
#ifndef CONFIG_ARMV8_PSCI
#ifdef CONFIG_OPTEE
loadables = "atf", "tee";
#else
loadables = "atf";
#endif
#endif
};
};

View File

@@ -28,7 +28,6 @@
&iomuxc1 {
bootph-pre-ram;
fsl,mux_mask = <0xf00>;
};
&pinctrl_lpuart5 {

View File

@@ -1,978 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ OR MIT */
/*
* Copyright 2021 NXP
*/
#ifndef __DTS_IMX8ULP_PINFUNC_H
#define __DTS_IMX8ULP_PINFUNC_H
/*
* The pin function ID is a tuple of
* <mux_reg input_reg mux_mode input_val>
*/
#define MX8ULP_PAD_PTD0__PTD0 0x0000 0x0000 0x1 0x0
#define MX8ULP_PAD_PTD0__I2S6_RX_BCLK 0x0000 0x0B44 0x7 0x1
#define MX8ULP_PAD_PTD0__SDHC0_RESET_B 0x0000 0x0000 0x8 0x0
#define MX8ULP_PAD_PTD0__FLEXSPI2_B_DQS 0x0000 0x0974 0x9 0x1
#define MX8ULP_PAD_PTD0__CLKOUT2 0x0000 0x0000 0xa 0x0
#define MX8ULP_PAD_PTD0__EPDC0_SDCLK_B 0x0000 0x0000 0xb 0x0
#define MX8ULP_PAD_PTD0__LP_APD_DBG_MUX_0 0x0000 0x0000 0xc 0x0
#define MX8ULP_PAD_PTD0__CLKOUT1 0x0000 0x0000 0xd 0x0
#define MX8ULP_PAD_PTD0__DEBUG_MUX0_0 0x0000 0x0000 0xe 0x0
#define MX8ULP_PAD_PTD0__DEBUG_MUX1_0 0x0000 0x0000 0xf 0x0
#define MX8ULP_PAD_PTD1__PTD1 0x0004 0x0000 0x1 0x0
#define MX8ULP_PAD_PTD1__I2S6_RX_FS 0x0004 0x0B48 0x7 0x1
#define MX8ULP_PAD_PTD1__SDHC0_CMD 0x0004 0x0000 0x8 0x0
#define MX8ULP_PAD_PTD1__FLEXSPI2_B_DATA7 0x0004 0x0970 0x9 0x1
#define MX8ULP_PAD_PTD1__EPDC0_SDCLK 0x0004 0x0000 0xb 0x0
#define MX8ULP_PAD_PTD1__DPI0_PCLK 0x0004 0x0000 0xc 0x0
#define MX8ULP_PAD_PTD1__LP_APD_DBG_MUX_1 0x0004 0x0000 0xd 0x0
#define MX8ULP_PAD_PTD1__DEBUG_MUX0_1 0x0004 0x0000 0xe 0x0
#define MX8ULP_PAD_PTD1__DEBUG_MUX1_1 0x0004 0x0000 0xf 0x0
#define MX8ULP_PAD_PTD2__PTD2 0x0008 0x0000 0x1 0x0
#define MX8ULP_PAD_PTD2__I2S6_RXD0 0x0008 0x0B34 0x7 0x1
#define MX8ULP_PAD_PTD2__SDHC0_CLK 0x0008 0x0000 0x8 0x0
#define MX8ULP_PAD_PTD2__FLEXSPI2_B_DATA6 0x0008 0x096C 0x9 0x1
#define MX8ULP_PAD_PTD2__EPDC0_SDLE 0x0008 0x0000 0xb 0x0
#define MX8ULP_PAD_PTD2__DPI0_HSYNC 0x0008 0x0000 0xc 0x0
#define MX8ULP_PAD_PTD2__LP_APD_DBG_MUX_2 0x0008 0x0000 0xd 0x0
#define MX8ULP_PAD_PTD2__DEBUG_MUX0_2 0x0008 0x0000 0xe 0x0
#define MX8ULP_PAD_PTD2__DEBUG_MUX1_2 0x0008 0x0000 0xf 0x0
#define MX8ULP_PAD_PTD3__PTD3 0x000C 0x0000 0x1 0x0
#define MX8ULP_PAD_PTD3__I2S6_RXD1 0x000C 0x0B38 0x7 0x1
#define MX8ULP_PAD_PTD3__SDHC0_D7 0x000C 0x0000 0x8 0x0
#define MX8ULP_PAD_PTD3__FLEXSPI2_B_DATA5 0x000C 0x0968 0x9 0x1
#define MX8ULP_PAD_PTD3__EPDC0_GDSP 0x000C 0x0000 0xb 0x0
#define MX8ULP_PAD_PTD3__DPI0_VSYNC 0x000C 0x0000 0xc 0x0
#define MX8ULP_PAD_PTD3__LP_APD_DBG_MUX_3 0x000C 0x0000 0xd 0x0
#define MX8ULP_PAD_PTD3__DEBUG_MUX0_3 0x000C 0x0000 0xe 0x0
#define MX8ULP_PAD_PTD3__DEBUG_MUX1_3 0x000C 0x0000 0xf 0x0
#define MX8ULP_PAD_PTD4__PTD4 0x0010 0x0000 0x1 0x0
#define MX8ULP_PAD_PTD4__EXT_AUD_MCLK3 0x0010 0x0B14 0x4 0x1
#define MX8ULP_PAD_PTD4__SDHC0_VS 0x0010 0x0000 0x5 0x0
#define MX8ULP_PAD_PTD4__TPM8_CH5 0x0010 0x0B2C 0x6 0x1
#define MX8ULP_PAD_PTD4__I2S6_MCLK 0x0010 0x0000 0x7 0x0
#define MX8ULP_PAD_PTD4__SDHC0_D6 0x0010 0x0000 0x8 0x0
#define MX8ULP_PAD_PTD4__FLEXSPI2_B_DATA4 0x0010 0x0964 0x9 0x1
#define MX8ULP_PAD_PTD4__EPDC0_SDCE0 0x0010 0x0000 0xb 0x0
#define MX8ULP_PAD_PTD4__DPI0_DE 0x0010 0x0000 0xc 0x0
#define MX8ULP_PAD_PTD4__LP_APD_DBG_MUX_4 0x0010 0x0000 0xd 0x0
#define MX8ULP_PAD_PTD4__DEBUG_MUX0_4 0x0010 0x0000 0xe 0x0
#define MX8ULP_PAD_PTD4__DEBUG_MUX1_4 0x0010 0x0000 0xf 0x0
#define MX8ULP_PAD_PTD5__PTD5 0x0014 0x0000 0x1 0x0
#define MX8ULP_PAD_PTD5__SDHC0_CD 0x0014 0x0000 0x5 0x0
#define MX8ULP_PAD_PTD5__TPM8_CH4 0x0014 0x0B28 0x6 0x1
#define MX8ULP_PAD_PTD5__I2S6_TX_BCLK 0x0014 0x0B4C 0x7 0x1
#define MX8ULP_PAD_PTD5__SDHC0_D5 0x0014 0x0000 0x8 0x0
#define MX8ULP_PAD_PTD5__FLEXSPI2_B_SS0_B 0x0014 0x0000 0x9 0x0
#define MX8ULP_PAD_PTD5__FLEXSPI2_B_SCLK_B 0x0014 0x0000 0xa 0x0
#define MX8ULP_PAD_PTD5__EPDC0_D0 0x0014 0x0000 0xb 0x0
#define MX8ULP_PAD_PTD5__DPI0_D0 0x0014 0x0000 0xc 0x0
#define MX8ULP_PAD_PTD5__LP_APD_DBG_MUX_5 0x0014 0x0000 0xd 0x0
#define MX8ULP_PAD_PTD5__DEBUG_MUX0_5 0x0014 0x0000 0xe 0x0
#define MX8ULP_PAD_PTD5__DEBUG_MUX1_5 0x0014 0x0000 0xf 0x0
#define MX8ULP_PAD_PTD6__PTD6 0x0018 0x0000 0x1 0x0
#define MX8ULP_PAD_PTD6__SDHC0_WP 0x0018 0x0000 0x5 0x0
#define MX8ULP_PAD_PTD6__TPM8_CH3 0x0018 0x0B24 0x6 0x1
#define MX8ULP_PAD_PTD6__I2S6_TX_FS 0x0018 0x0B50 0x7 0x1
#define MX8ULP_PAD_PTD6__SDHC0_D4 0x0018 0x0000 0x8 0x0
#define MX8ULP_PAD_PTD6__FLEXSPI2_B_SCLK 0x0018 0x0978 0x9 0x1
#define MX8ULP_PAD_PTD6__EPDC0_D1 0x0018 0x0000 0xb 0x0
#define MX8ULP_PAD_PTD6__DPI0_D1 0x0018 0x0000 0xc 0x0
#define MX8ULP_PAD_PTD6__LP_APD_DBG_MUX_6 0x0018 0x0000 0xd 0x0
#define MX8ULP_PAD_PTD6__DEBUG_MUX0_6 0x0018 0x0000 0xe 0x0
#define MX8ULP_PAD_PTD6__DEBUG_MUX1_6 0x0018 0x0000 0xf 0x0
#define MX8ULP_PAD_PTD7__PTD7 0x001C 0x0000 0x1 0x0
#define MX8ULP_PAD_PTD7__TPM8_CH2 0x001C 0x0B20 0x6 0x1
#define MX8ULP_PAD_PTD7__I2S6_TXD0 0x001C 0x0000 0x7 0x0
#define MX8ULP_PAD_PTD7__SDHC0_D3 0x001C 0x0000 0x8 0x0
#define MX8ULP_PAD_PTD7__FLEXSPI2_B_DATA3 0x001C 0x0960 0x9 0x1
#define MX8ULP_PAD_PTD7__EPDC0_D2 0x001C 0x0000 0xb 0x0
#define MX8ULP_PAD_PTD7__DPI0_D2 0x001C 0x0000 0xc 0x0
#define MX8ULP_PAD_PTD7__LP_APD_DBG_MUX_7 0x001C 0x0000 0xd 0x0
#define MX8ULP_PAD_PTD7__DEBUG_MUX0_7 0x001C 0x0000 0xe 0x0
#define MX8ULP_PAD_PTD7__DEBUG_MUX1_7 0x001C 0x0000 0xf 0x0
#define MX8ULP_PAD_PTD8__PTD8 0x0020 0x0000 0x1 0x0
#define MX8ULP_PAD_PTD8__TPM8_CH1 0x0020 0x0B1C 0x6 0x1
#define MX8ULP_PAD_PTD8__I2S6_TXD1 0x0020 0x0000 0x7 0x0
#define MX8ULP_PAD_PTD8__SDHC0_D2 0x0020 0x0000 0x8 0x0
#define MX8ULP_PAD_PTD8__FLEXSPI2_B_DATA2 0x0020 0x095C 0x9 0x1
#define MX8ULP_PAD_PTD8__EPDC0_D3 0x0020 0x0000 0xb 0x0
#define MX8ULP_PAD_PTD8__DPI0_D3 0x0020 0x0000 0xc 0x0
#define MX8ULP_PAD_PTD8__LP_APD_DBG_MUX_8 0x0020 0x0000 0xe 0x0
#define MX8ULP_PAD_PTD8__DEBUG_MUX1_8 0x0020 0x0000 0xf 0x0
#define MX8ULP_PAD_PTD9__PTD9 0x0024 0x0000 0x1 0x0
#define MX8ULP_PAD_PTD9__TPM8_CLKIN 0x0024 0x0B30 0x6 0x1
#define MX8ULP_PAD_PTD9__I2S6_TXD2 0x0024 0x0000 0x7 0x0
#define MX8ULP_PAD_PTD9__SDHC0_D1 0x0024 0x0000 0x8 0x0
#define MX8ULP_PAD_PTD9__FLEXSPI2_B_DATA1 0x0024 0x0958 0x9 0x1
#define MX8ULP_PAD_PTD9__EPDC0_D4 0x0024 0x0000 0xb 0x0
#define MX8ULP_PAD_PTD9__DPI0_D4 0x0024 0x0000 0xc 0x0
#define MX8ULP_PAD_PTD9__LP_APD_DBG_MUX_9 0x0024 0x0000 0xe 0x0
#define MX8ULP_PAD_PTD9__DEBUG_MUX1_9 0x0024 0x0000 0xf 0x0
#define MX8ULP_PAD_PTD10__PTD10 0x0028 0x0000 0x1 0x0
#define MX8ULP_PAD_PTD10__TPM8_CH0 0x0028 0x0B18 0x6 0x1
#define MX8ULP_PAD_PTD10__I2S6_TXD3 0x0028 0x0000 0x7 0x0
#define MX8ULP_PAD_PTD10__SDHC0_D0 0x0028 0x0000 0x8 0x0
#define MX8ULP_PAD_PTD10__FLEXSPI2_B_DATA0 0x0028 0x0954 0x9 0x1
#define MX8ULP_PAD_PTD10__EPDC0_D5 0x0028 0x0000 0xb 0x0
#define MX8ULP_PAD_PTD10__DPI0_D5 0x0028 0x0000 0xc 0x0
#define MX8ULP_PAD_PTD10__LP_APD_DBG_MUX_10 0x0028 0x0000 0xe 0x0
#define MX8ULP_PAD_PTD10__DEBUG_MUX1_10 0x0028 0x0000 0xf 0x0
#define MX8ULP_PAD_PTD11__PTD11 0x002C 0x0000 0x1 0x0
#define MX8ULP_PAD_PTD11__TPM8_CH5 0x002C 0x0B2C 0x6 0x2
#define MX8ULP_PAD_PTD11__I2S6_RXD2 0x002C 0x0B3C 0x7 0x1
#define MX8ULP_PAD_PTD11__SDHC0_DQS 0x002C 0x0000 0x8 0x0
#define MX8ULP_PAD_PTD11__FLEXSPI2_B_SS0_B 0x002C 0x0000 0x9 0x0
#define MX8ULP_PAD_PTD11__FLEXSPI2_A_SS1_B 0x002C 0x0000 0xa 0x0
#define MX8ULP_PAD_PTD11__EPDC0_D6 0x002C 0x0000 0xb 0x0
#define MX8ULP_PAD_PTD11__DPI0_D6 0x002C 0x0000 0xc 0x0
#define MX8ULP_PAD_PTD11__LP_APD_DBG_MUX_11 0x002C 0x0000 0xf 0x0
#define MX8ULP_PAD_PTD12__PTD12 0x0030 0x0000 0x1 0x0
#define MX8ULP_PAD_PTD12__USB0_ID 0x0030 0x0AC8 0x5 0x1
#define MX8ULP_PAD_PTD12__SDHC2_D3 0x0030 0x0AA4 0x6 0x1
#define MX8ULP_PAD_PTD12__I2S7_RX_BCLK 0x0030 0x0B64 0x7 0x1
#define MX8ULP_PAD_PTD12__SDHC1_DQS 0x0030 0x0A84 0x8 0x1
#define MX8ULP_PAD_PTD12__FLEXSPI2_A_SS0_B 0x0030 0x0000 0x9 0x0
#define MX8ULP_PAD_PTD12__FLEXSPI2_B_SS1_B 0x0030 0x0000 0xa 0x0
#define MX8ULP_PAD_PTD12__EPDC0_D7 0x0030 0x0000 0xb 0x0
#define MX8ULP_PAD_PTD12__DPI0_D7 0x0030 0x0000 0xc 0x0
#define MX8ULP_PAD_PTD12__LP_APD_DBG_MUX_12 0x0030 0x0000 0xf 0x0
#define MX8ULP_PAD_PTD13__PTD13 0x0034 0x0000 0x1 0x0
#define MX8ULP_PAD_PTD13__SPDIF_IN3 0x0034 0x0B80 0x4 0x1
#define MX8ULP_PAD_PTD13__USB0_PWR 0x0034 0x0000 0x5 0x0
#define MX8ULP_PAD_PTD13__SDHC2_D2 0x0034 0x0AA0 0x6 0x1
#define MX8ULP_PAD_PTD13__I2S7_RX_FS 0x0034 0x0B68 0x7 0x1
#define MX8ULP_PAD_PTD13__SDHC1_RESET_B 0x0034 0x0000 0x8 0x0
#define MX8ULP_PAD_PTD13__FLEXSPI2_A_SCLK 0x0034 0x0000 0x9 0x0
#define MX8ULP_PAD_PTD13__CLKOUT2 0x0034 0x0000 0xa 0x0
#define MX8ULP_PAD_PTD13__EPDC0_D8 0x0034 0x0000 0xb 0x0
#define MX8ULP_PAD_PTD13__DPI0_D8 0x0034 0x0000 0xc 0x0
#define MX8ULP_PAD_PTD13__CLKOUT1 0x0034 0x0000 0xd 0x0
#define MX8ULP_PAD_PTD13__LP_APD_DBG_MUX_13 0x0034 0x0000 0xf 0x0
#define MX8ULP_PAD_PTD14__PTD14 0x0038 0x0000 0x1 0x0
#define MX8ULP_PAD_PTD14__SPDIF_OUT3 0x0038 0x0000 0x4 0x0
#define MX8ULP_PAD_PTD14__USB0_OC 0x0038 0x0AC0 0x5 0x1
#define MX8ULP_PAD_PTD14__SDHC2_D1 0x0038 0x0A9C 0x6 0x1
#define MX8ULP_PAD_PTD14__I2S7_RXD0 0x0038 0x0B54 0x7 0x1
#define MX8ULP_PAD_PTD14__SDHC1_D7 0x0038 0x0A80 0x8 0x1
#define MX8ULP_PAD_PTD14__FLEXSPI2_A_DATA3 0x0038 0x0000 0x9 0x0
#define MX8ULP_PAD_PTD14__TRACE0_D7 0x0038 0x0000 0xa 0x0
#define MX8ULP_PAD_PTD14__EPDC0_D9 0x0038 0x0000 0xb 0x0
#define MX8ULP_PAD_PTD14__DPI0_D9 0x0038 0x0000 0xc 0x0
#define MX8ULP_PAD_PTD14__LP_APD_DBG_MUX_14 0x0038 0x0000 0xf 0x0
#define MX8ULP_PAD_PTD15__PTD15 0x003C 0x0000 0x1 0x0
#define MX8ULP_PAD_PTD15__SPDIF_IN2 0x003C 0x0B7C 0x4 0x1
#define MX8ULP_PAD_PTD15__SDHC1_VS 0x003C 0x0000 0x5 0x0
#define MX8ULP_PAD_PTD15__SDHC2_D0 0x003C 0x0A98 0x6 0x1
#define MX8ULP_PAD_PTD15__I2S7_TX_BCLK 0x003C 0x0B6C 0x7 0x1
#define MX8ULP_PAD_PTD15__SDHC1_D6 0x003C 0x0A7C 0x8 0x1
#define MX8ULP_PAD_PTD15__FLEXSPI2_A_DATA2 0x003C 0x0000 0x9 0x0
#define MX8ULP_PAD_PTD15__TRACE0_D6 0x003C 0x0000 0xa 0x0
#define MX8ULP_PAD_PTD15__EPDC0_D10 0x003C 0x0000 0xb 0x0
#define MX8ULP_PAD_PTD15__DPI0_D10 0x003C 0x0000 0xc 0x0
#define MX8ULP_PAD_PTD15__LP_APD_DBG_MUX_15 0x003C 0x0000 0xf 0x0
#define MX8ULP_PAD_PTD16__PTD16 0x0040 0x0000 0x1 0x0
#define MX8ULP_PAD_PTD16__FXIO1_D31 0x0040 0x08A0 0x2 0x1
#define MX8ULP_PAD_PTD16__LPSPI4_PCS1 0x0040 0x08F8 0x3 0x1
#define MX8ULP_PAD_PTD16__SPDIF_OUT2 0x0040 0x0000 0x4 0x0
#define MX8ULP_PAD_PTD16__SDHC1_CD 0x0040 0x0A58 0x5 0x1
#define MX8ULP_PAD_PTD16__SDHC2_CLK 0x0040 0x0A90 0x6 0x1
#define MX8ULP_PAD_PTD16__I2S7_TX_FS 0x0040 0x0B70 0x7 0x1
#define MX8ULP_PAD_PTD16__SDHC1_D5 0x0040 0x0A78 0x8 0x1
#define MX8ULP_PAD_PTD16__FLEXSPI2_A_DATA1 0x0040 0x0000 0x9 0x0
#define MX8ULP_PAD_PTD16__TRACE0_D5 0x0040 0x0000 0xa 0x0
#define MX8ULP_PAD_PTD16__EPDC0_D11 0x0040 0x0000 0xb 0x0
#define MX8ULP_PAD_PTD16__DPI0_D11 0x0040 0x0000 0xc 0x0
#define MX8ULP_PAD_PTD16__LP_APD_DBG_MUX_16 0x0040 0x0000 0xf 0x0
#define MX8ULP_PAD_PTD17__PTD17 0x0044 0x0000 0x1 0x0
#define MX8ULP_PAD_PTD17__FXIO1_D30 0x0044 0x089C 0x2 0x1
#define MX8ULP_PAD_PTD17__LPSPI4_PCS2 0x0044 0x08FC 0x3 0x1
#define MX8ULP_PAD_PTD17__EXT_AUD_MCLK3 0x0044 0x0B14 0x4 0x2
#define MX8ULP_PAD_PTD17__SDHC1_WP 0x0044 0x0A88 0x5 0x1
#define MX8ULP_PAD_PTD17__SDHC2_CMD 0x0044 0x0A94 0x6 0x1
#define MX8ULP_PAD_PTD17__I2S7_TXD0 0x0044 0x0000 0x7 0x0
#define MX8ULP_PAD_PTD17__SDHC1_D4 0x0044 0x0A74 0x8 0x1
#define MX8ULP_PAD_PTD17__FLEXSPI2_A_DATA0 0x0044 0x0000 0x9 0x0
#define MX8ULP_PAD_PTD17__TRACE0_D4 0x0044 0x0000 0xa 0x0
#define MX8ULP_PAD_PTD17__EPDC0_D12 0x0044 0x0000 0xb 0x0
#define MX8ULP_PAD_PTD17__DPI0_D12 0x0044 0x0000 0xc 0x0
#define MX8ULP_PAD_PTD17__LP_APD_DBG_MUX_17 0x0044 0x0000 0xf 0x0
#define MX8ULP_PAD_PTD18__PTD18 0x0048 0x0000 0x1 0x0
#define MX8ULP_PAD_PTD18__FXIO1_D29 0x0048 0x0894 0x2 0x1
#define MX8ULP_PAD_PTD18__LPSPI4_PCS3 0x0048 0x0900 0x3 0x1
#define MX8ULP_PAD_PTD18__SPDIF_CLK 0x0048 0x0000 0x4 0x0
#define MX8ULP_PAD_PTD18__EXT_AUD_MCLK3 0x0048 0x0B14 0x5 0x3
#define MX8ULP_PAD_PTD18__TPM8_CH0 0x0048 0x0B18 0x6 0x2
#define MX8ULP_PAD_PTD18__I2S7_MCLK 0x0048 0x0000 0x7 0x0
#define MX8ULP_PAD_PTD18__SDHC1_D3 0x0048 0x0A70 0x8 0x1
#define MX8ULP_PAD_PTD18__FLEXSPI2_A_DQS 0x0048 0x0000 0x9 0x0
#define MX8ULP_PAD_PTD18__TRACE0_D3 0x0048 0x0000 0xa 0x0
#define MX8ULP_PAD_PTD18__EPDC0_D13 0x0048 0x0000 0xb 0x0
#define MX8ULP_PAD_PTD18__DPI0_D13 0x0048 0x0000 0xc 0x0
#define MX8ULP_PAD_PTD18__LP_APD_DBG_MUX_18 0x0048 0x0000 0xf 0x0
#define MX8ULP_PAD_PTD19__PTD19 0x004C 0x0000 0x1 0x0
#define MX8ULP_PAD_PTD19__FXIO1_D28 0x004C 0x0890 0x2 0x1
#define MX8ULP_PAD_PTD19__SPDIF_IN0 0x004C 0x0B74 0x4 0x1
#define MX8ULP_PAD_PTD19__TPM8_CH1 0x004C 0x0B1C 0x6 0x2
#define MX8ULP_PAD_PTD19__I2S6_RXD3 0x004C 0x0B40 0x7 0x1
#define MX8ULP_PAD_PTD19__SDHC1_D2 0x004C 0x0A6C 0x8 0x1
#define MX8ULP_PAD_PTD19__FLEXSPI2_A_DATA7 0x004C 0x0000 0x9 0x0
#define MX8ULP_PAD_PTD19__TRACE0_D2 0x004C 0x0000 0xa 0x0
#define MX8ULP_PAD_PTD19__EPDC0_D14 0x004C 0x0000 0xb 0x0
#define MX8ULP_PAD_PTD19__DPI0_D14 0x004C 0x0000 0xc 0x0
#define MX8ULP_PAD_PTD19__LP_APD_DBG_MUX_19 0x004C 0x0000 0xf 0x0
#define MX8ULP_PAD_PTD20__PTD20 0x0050 0x0000 0x1 0x0
#define MX8ULP_PAD_PTD20__FXIO1_D27 0x0050 0x088C 0x2 0x1
#define MX8ULP_PAD_PTD20__LPSPI4_SIN 0x0050 0x0908 0x3 0x1
#define MX8ULP_PAD_PTD20__SPDIF_OUT0 0x0050 0x0000 0x4 0x0
#define MX8ULP_PAD_PTD20__TPM8_CLKIN 0x0050 0x0B30 0x6 0x2
#define MX8ULP_PAD_PTD20__I2S7_RXD1 0x0050 0x0B58 0x7 0x1
#define MX8ULP_PAD_PTD20__SDHC1_D1 0x0050 0x0A68 0x8 0x1
#define MX8ULP_PAD_PTD20__FLEXSPI2_A_DATA6 0x0050 0x0000 0x9 0x0
#define MX8ULP_PAD_PTD20__TRACE0_D1 0x0050 0x0000 0xa 0x0
#define MX8ULP_PAD_PTD20__EPDC0_D15 0x0050 0x0000 0xb 0x0
#define MX8ULP_PAD_PTD20__DPI0_D15 0x0050 0x0000 0xc 0x0
#define MX8ULP_PAD_PTD20__LP_APD_DBG_MUX_20 0x0050 0x0000 0xf 0x0
#define MX8ULP_PAD_PTD21__PTD21 0x0054 0x0000 0x1 0x0
#define MX8ULP_PAD_PTD21__FXIO1_D26 0x0054 0x0888 0x2 0x1
#define MX8ULP_PAD_PTD21__LPSPI4_SOUT 0x0054 0x090C 0x3 0x1
#define MX8ULP_PAD_PTD21__SPDIF_IN1 0x0054 0x0B78 0x4 0x1
#define MX8ULP_PAD_PTD21__USB1_PWR 0x0054 0x0000 0x5 0x0
#define MX8ULP_PAD_PTD21__TPM8_CH2 0x0054 0x0B20 0x6 0x2
#define MX8ULP_PAD_PTD21__I2S7_TXD1 0x0054 0x0000 0x7 0x0
#define MX8ULP_PAD_PTD21__SDHC1_D0 0x0054 0x0A64 0x8 0x1
#define MX8ULP_PAD_PTD21__FLEXSPI2_A_DATA5 0x0054 0x0000 0x9 0x0
#define MX8ULP_PAD_PTD21__TRACE0_D0 0x0054 0x0000 0xa 0x0
#define MX8ULP_PAD_PTD21__DPI0_D16 0x0054 0x0000 0xc 0x0
#define MX8ULP_PAD_PTD21__WDOG5_RST 0x0054 0x0000 0xd 0x0
#define MX8ULP_PAD_PTD21__LP_APD_DBG_MUX_21 0x0054 0x0000 0xf 0x0
#define MX8ULP_PAD_PTD22__PTD22 0x0058 0x0000 0x1 0x0
#define MX8ULP_PAD_PTD22__FXIO1_D25 0x0058 0x0884 0x2 0x1
#define MX8ULP_PAD_PTD22__LPSPI4_SCK 0x0058 0x0904 0x3 0x1
#define MX8ULP_PAD_PTD22__SPDIF_OUT1 0x0058 0x0000 0x4 0x0
#define MX8ULP_PAD_PTD22__USB1_OC 0x0058 0x0AC4 0x5 0x1
#define MX8ULP_PAD_PTD22__TPM8_CH3 0x0058 0x0B24 0x6 0x2
#define MX8ULP_PAD_PTD22__I2S7_TXD2 0x0058 0x0000 0x7 0x0
#define MX8ULP_PAD_PTD22__SDHC1_CLK 0x0058 0x0A5C 0x8 0x1
#define MX8ULP_PAD_PTD22__FLEXSPI2_A_DATA4 0x0058 0x0000 0x9 0x0
#define MX8ULP_PAD_PTD22__TRACE0_CLKOUT 0x0058 0x0000 0xa 0x0
#define MX8ULP_PAD_PTD22__DPI0_D17 0x0058 0x0000 0xc 0x0
#define MX8ULP_PAD_PTD22__LP_APD_DBG_MUX_22 0x0058 0x0000 0xf 0x0
#define MX8ULP_PAD_PTD23__PTD23 0x005C 0x0000 0x1 0x0
#define MX8ULP_PAD_PTD23__FXIO1_D24 0x005C 0x0880 0x2 0x1
#define MX8ULP_PAD_PTD23__LPSPI4_PCS0 0x005C 0x08F4 0x3 0x1
#define MX8ULP_PAD_PTD23__USB1_ID 0x005C 0x0ACC 0x5 0x1
#define MX8ULP_PAD_PTD23__TPM8_CH4 0x005C 0x0B28 0x6 0x2
#define MX8ULP_PAD_PTD23__I2S7_TXD3 0x005C 0x0000 0x7 0x0
#define MX8ULP_PAD_PTD23__SDHC1_CMD 0x005C 0x0A60 0x8 0x1
#define MX8ULP_PAD_PTD23__FLEXSPI2_A_SS0_B 0x005C 0x0000 0x9 0x0
#define MX8ULP_PAD_PTD23__FLEXSPI2_A_SCLK_B 0x005C 0x0000 0xa 0x0
#define MX8ULP_PAD_PTD23__DPI0_D18 0x005C 0x0000 0xc 0x0
#define MX8ULP_PAD_PTD23__LP_APD_DBG_MUX_23 0x005C 0x0000 0xf 0x0
#define MX8ULP_PAD_PTE0__PTE0 0x0080 0x0000 0x1 0x0
#define MX8ULP_PAD_PTE0__FXIO1_D23 0x0080 0x087C 0x2 0x1
#define MX8ULP_PAD_PTE0__SPDIF_IN3 0x0080 0x0B80 0x3 0x2
#define MX8ULP_PAD_PTE0__LPUART4_CTS_B 0x0080 0x08DC 0x4 0x1
#define MX8ULP_PAD_PTE0__LPI2C4_SCL 0x0080 0x08C8 0x5 0x1
#define MX8ULP_PAD_PTE0__TPM8_CLKIN 0x0080 0x0B30 0x6 0x3
#define MX8ULP_PAD_PTE0__I2S7_RXD2 0x0080 0x0B5C 0x7 0x1
#define MX8ULP_PAD_PTE0__SDHC2_D1 0x0080 0x0A9C 0x8 0x2
#define MX8ULP_PAD_PTE0__FLEXSPI2_B_DQS 0x0080 0x0974 0x9 0x2
#define MX8ULP_PAD_PTE0__ENET0_CRS 0x0080 0x0AE8 0xa 0x1
#define MX8ULP_PAD_PTE0__DBI0_WRX 0x0080 0x0000 0xb 0x0
#define MX8ULP_PAD_PTE0__DPI0_D19 0x0080 0x0000 0xc 0x0
#define MX8ULP_PAD_PTE0__WUU1_P0 0x0080 0x0000 0xd 0x0
#define MX8ULP_PAD_PTE0__DEBUG_MUX0_8 0x0080 0x0000 0xe 0x0
#define MX8ULP_PAD_PTE0__DEBUG_MUX1_11 0x0080 0x0000 0xf 0x0
#define MX8ULP_PAD_PTE1__PTE1 0x0084 0x0000 0x1 0x0
#define MX8ULP_PAD_PTE1__FXIO1_D22 0x0084 0x0878 0x2 0x1
#define MX8ULP_PAD_PTE1__SPDIF_OUT3 0x0084 0x0000 0x3 0x0
#define MX8ULP_PAD_PTE1__LPUART4_RTS_B 0x0084 0x0000 0x4 0x0
#define MX8ULP_PAD_PTE1__LPI2C4_SDA 0x0084 0x08CC 0x5 0x1
#define MX8ULP_PAD_PTE1__TPM8_CH0 0x0084 0x0B18 0x6 0x3
#define MX8ULP_PAD_PTE1__I2S7_RXD3 0x0084 0x0B60 0x7 0x1
#define MX8ULP_PAD_PTE1__SDHC2_D0 0x0084 0x0A98 0x8 0x2
#define MX8ULP_PAD_PTE1__FLEXSPI2_B_DATA7 0x0084 0x0970 0x9 0x2
#define MX8ULP_PAD_PTE1__ENET0_COL 0x0084 0x0AE4 0xa 0x1
#define MX8ULP_PAD_PTE1__DBI0_CSX 0x0084 0x0000 0xb 0x0
#define MX8ULP_PAD_PTE1__DPI0_D20 0x0084 0x0000 0xc 0x0
#define MX8ULP_PAD_PTE1__WUU1_P1 0x0084 0x0000 0xd 0x0
#define MX8ULP_PAD_PTE1__DEBUG_MUX0_9 0x0084 0x0000 0xe 0x0
#define MX8ULP_PAD_PTE1__DEBUG_MUX1_12 0x0084 0x0000 0xf 0x0
#define MX8ULP_PAD_PTE2__PTE2 0x0088 0x0000 0x1 0x0
#define MX8ULP_PAD_PTE2__FXIO1_D21 0x0088 0x0874 0x2 0x1
#define MX8ULP_PAD_PTE2__SPDIF_IN2 0x0088 0x0B7C 0x3 0x2
#define MX8ULP_PAD_PTE2__LPUART4_TX 0x0088 0x08E4 0x4 0x1
#define MX8ULP_PAD_PTE2__LPI2C4_HREQ 0x0088 0x08C4 0x5 0x1
#define MX8ULP_PAD_PTE2__TPM8_CH1 0x0088 0x0B1C 0x6 0x3
#define MX8ULP_PAD_PTE2__EXT_AUD_MCLK3 0x0088 0x0B14 0x7 0x4
#define MX8ULP_PAD_PTE2__SDHC2_CLK 0x0088 0x0A90 0x8 0x2
#define MX8ULP_PAD_PTE2__FLEXSPI2_B_DATA6 0x0088 0x096C 0x9 0x2
#define MX8ULP_PAD_PTE2__ENET0_TXER 0x0088 0x0000 0xa 0x0
#define MX8ULP_PAD_PTE2__DBI0_DCX 0x0088 0x0000 0xb 0x0
#define MX8ULP_PAD_PTE2__DPI0_D21 0x0088 0x0000 0xc 0x0
#define MX8ULP_PAD_PTE2__LP_HV_DBG_MUX_0 0x0088 0x0000 0xd 0x0
#define MX8ULP_PAD_PTE2__DEBUG_MUX0_10 0x0088 0x0000 0xe 0x0
#define MX8ULP_PAD_PTE2__DEBUG_MUX1_13 0x0088 0x0000 0xf 0x0
#define MX8ULP_PAD_PTE3__PTE3 0x008C 0x0000 0x1 0x0
#define MX8ULP_PAD_PTE3__FXIO1_D20 0x008C 0x0870 0x2 0x1
#define MX8ULP_PAD_PTE3__SPDIF_OUT2 0x008C 0x0000 0x3 0x0
#define MX8ULP_PAD_PTE3__LPUART4_RX 0x008C 0x08E0 0x4 0x1
#define MX8ULP_PAD_PTE3__TPM8_CH2 0x008C 0x0B20 0x6 0x3
#define MX8ULP_PAD_PTE3__I2S6_MCLK 0x008C 0x0000 0x7 0x0
#define MX8ULP_PAD_PTE3__SDHC2_CMD 0x008C 0x0A94 0x8 0x2
#define MX8ULP_PAD_PTE3__FLEXSPI2_B_DATA5 0x008C 0x0968 0x9 0x2
#define MX8ULP_PAD_PTE3__ENET0_TXCLK 0x008C 0x0B10 0xa 0x1
#define MX8ULP_PAD_PTE3__DBI0_RWX 0x008C 0x0000 0xb 0x0
#define MX8ULP_PAD_PTE3__DPI0_D22 0x008C 0x0000 0xc 0x0
#define MX8ULP_PAD_PTE3__WUU1_P2 0x008C 0x0000 0xd 0x0
#define MX8ULP_PAD_PTE3__DEBUG_MUX0_11 0x008C 0x0000 0xe 0x0
#define MX8ULP_PAD_PTE3__DEBUG_MUX1_14 0x008C 0x0000 0xf 0x0
#define MX8ULP_PAD_PTE4__PTE4 0x0090 0x0000 0x1 0x0
#define MX8ULP_PAD_PTE4__FXIO1_D19 0x0090 0x0868 0x2 0x1
#define MX8ULP_PAD_PTE4__SPDIF_CLK 0x0090 0x0000 0x3 0x0
#define MX8ULP_PAD_PTE4__LPUART5_CTS_B 0x0090 0x08E8 0x4 0x1
#define MX8ULP_PAD_PTE4__LPI2C5_SCL 0x0090 0x08D4 0x5 0x1
#define MX8ULP_PAD_PTE4__TPM8_CH3 0x0090 0x0B24 0x6 0x3
#define MX8ULP_PAD_PTE4__I2S6_RX_BCLK 0x0090 0x0B44 0x7 0x2
#define MX8ULP_PAD_PTE4__SDHC2_D3 0x0090 0x0AA4 0x8 0x2
#define MX8ULP_PAD_PTE4__FLEXSPI2_B_DATA4 0x0090 0x0964 0x9 0x2
#define MX8ULP_PAD_PTE4__ENET0_TXD3 0x0090 0x0000 0xa 0x0
#define MX8ULP_PAD_PTE4__DBI0_E 0x0090 0x0000 0xb 0x0
#define MX8ULP_PAD_PTE4__DPI0_D23 0x0090 0x0000 0xc 0x0
#define MX8ULP_PAD_PTE4__WUU1_P3 0x0090 0x0000 0xd 0x0
#define MX8ULP_PAD_PTE4__DEBUG_MUX0_12 0x0090 0x0000 0xe 0x0
#define MX8ULP_PAD_PTE4__DEBUG_MUX1_15 0x0090 0x0000 0xf 0x0
#define MX8ULP_PAD_PTE5__PTE5 0x0094 0x0000 0x1 0x0
#define MX8ULP_PAD_PTE5__FXIO1_D18 0x0094 0x0864 0x2 0x1
#define MX8ULP_PAD_PTE5__SPDIF_IN0 0x0094 0x0B74 0x3 0x2
#define MX8ULP_PAD_PTE5__LPUART5_RTS_B 0x0094 0x0000 0x4 0x0
#define MX8ULP_PAD_PTE5__LPI2C5_SDA 0x0094 0x08D8 0x5 0x1
#define MX8ULP_PAD_PTE5__TPM8_CH4 0x0094 0x0B28 0x6 0x3
#define MX8ULP_PAD_PTE5__I2S6_RX_FS 0x0094 0x0B48 0x7 0x2
#define MX8ULP_PAD_PTE5__SDHC2_D2 0x0094 0x0AA0 0x8 0x2
#define MX8ULP_PAD_PTE5__FLEXSPI2_B_SS0_B 0x0094 0x0000 0x9 0x0
#define MX8ULP_PAD_PTE5__ENET0_TXD2 0x0094 0x0000 0xa 0x0
#define MX8ULP_PAD_PTE5__DBI0_D0 0x0094 0x0000 0xb 0x0
#define MX8ULP_PAD_PTE5__LP_HV_DBG_MUX_1 0x0094 0x0000 0xd 0x0
#define MX8ULP_PAD_PTE5__DEBUG_MUX0_13 0x0094 0x0000 0xe 0x0
#define MX8ULP_PAD_PTE5__DEBUG_MUX1_16 0x0094 0x0000 0xf 0x0
#define MX8ULP_PAD_PTE6__PTE6 0x0098 0x0000 0x1 0x0
#define MX8ULP_PAD_PTE6__FXIO1_D17 0x0098 0x0860 0x2 0x1
#define MX8ULP_PAD_PTE6__SPDIF_OUT0 0x0098 0x0000 0x3 0x0
#define MX8ULP_PAD_PTE6__LPUART5_TX 0x0098 0x08F0 0x4 0x1
#define MX8ULP_PAD_PTE6__LPI2C5_HREQ 0x0098 0x08D0 0x5 0x1
#define MX8ULP_PAD_PTE6__TPM8_CH5 0x0098 0x0B2C 0x6 0x3
#define MX8ULP_PAD_PTE6__I2S6_RXD0 0x0098 0x0B34 0x7 0x2
#define MX8ULP_PAD_PTE6__SDHC2_D4 0x0098 0x0AA8 0x8 0x1
#define MX8ULP_PAD_PTE6__FLEXSPI2_B_SCLK 0x0098 0x0978 0x9 0x2
#define MX8ULP_PAD_PTE6__ENET0_RXCLK 0x0098 0x0B0C 0xa 0x1
#define MX8ULP_PAD_PTE6__DBI0_D1 0x0098 0x0000 0xb 0x0
#define MX8ULP_PAD_PTE6__LP_HV_DBG_MUX_2 0x0098 0x0000 0xc 0x0
#define MX8ULP_PAD_PTE6__WDOG5_RST 0x0098 0x0000 0xd 0x0
#define MX8ULP_PAD_PTE6__DEBUG_MUX0_14 0x0098 0x0000 0xe 0x0
#define MX8ULP_PAD_PTE6__DEBUG_MUX1_17 0x0098 0x0000 0xf 0x0
#define MX8ULP_PAD_PTE7__PTE7 0x009C 0x0000 0x1 0x0
#define MX8ULP_PAD_PTE7__FXIO1_D16 0x009C 0x085C 0x2 0x1
#define MX8ULP_PAD_PTE7__SPDIF_IN1 0x009C 0x0B78 0x3 0x2
#define MX8ULP_PAD_PTE7__LPUART5_RX 0x009C 0x08EC 0x4 0x1
#define MX8ULP_PAD_PTE7__LPI2C6_HREQ 0x009C 0x09B4 0x5 0x1
#define MX8ULP_PAD_PTE7__TPM4_CLKIN 0x009C 0x081C 0x6 0x1
#define MX8ULP_PAD_PTE7__I2S6_RXD1 0x009C 0x0B38 0x7 0x2
#define MX8ULP_PAD_PTE7__SDHC2_D5 0x009C 0x0AAC 0x8 0x1
#define MX8ULP_PAD_PTE7__FLEXSPI2_B_DATA3 0x009C 0x0960 0x9 0x2
#define MX8ULP_PAD_PTE7__ENET0_RXD3 0x009C 0x0B04 0xa 0x1
#define MX8ULP_PAD_PTE7__DBI0_D2 0x009C 0x0000 0xb 0x0
#define MX8ULP_PAD_PTE7__EPDC0_BDR1 0x009C 0x0000 0xc 0x0
#define MX8ULP_PAD_PTE7__WUU1_P4 0x009C 0x0000 0xd 0x0
#define MX8ULP_PAD_PTE7__DEBUG_MUX0_15 0x009C 0x0000 0xe 0x0
#define MX8ULP_PAD_PTE7__DEBUG_MUX1_18 0x009C 0x0000 0xf 0x0
#define MX8ULP_PAD_PTE8__PTE8 0x00A0 0x0000 0x1 0x0
#define MX8ULP_PAD_PTE8__FXIO1_D15 0x00A0 0x0858 0x2 0x1
#define MX8ULP_PAD_PTE8__LPSPI4_PCS1 0x00A0 0x08F8 0x3 0x2
#define MX8ULP_PAD_PTE8__LPUART6_CTS_B 0x00A0 0x09CC 0x4 0x1
#define MX8ULP_PAD_PTE8__LPI2C6_SCL 0x00A0 0x09B8 0x5 0x1
#define MX8ULP_PAD_PTE8__TPM4_CH0 0x00A0 0x0804 0x6 0x1
#define MX8ULP_PAD_PTE8__I2S6_RXD2 0x00A0 0x0B3C 0x7 0x2
#define MX8ULP_PAD_PTE8__SDHC2_D6 0x00A0 0x0AB0 0x8 0x1
#define MX8ULP_PAD_PTE8__FLEXSPI2_B_DATA2 0x00A0 0x095C 0x9 0x2
#define MX8ULP_PAD_PTE8__ENET0_RXD2 0x00A0 0x0B00 0xa 0x1
#define MX8ULP_PAD_PTE8__DBI0_D3 0x00A0 0x0000 0xb 0x0
#define MX8ULP_PAD_PTE8__EPDC0_BDR0 0x00A0 0x0000 0xc 0x0
#define MX8ULP_PAD_PTE8__LP_HV_DBG_MUX_3 0x00A0 0x0000 0xe 0x0
#define MX8ULP_PAD_PTE8__DEBUG_MUX1_19 0x00A0 0x0000 0xf 0x0
#define MX8ULP_PAD_PTE9__PTE9 0x00A4 0x0000 0x1 0x0
#define MX8ULP_PAD_PTE9__FXIO1_D14 0x00A4 0x0854 0x2 0x1
#define MX8ULP_PAD_PTE9__LPSPI4_PCS2 0x00A4 0x08FC 0x3 0x2
#define MX8ULP_PAD_PTE9__LPUART6_RTS_B 0x00A4 0x0000 0x4 0x0
#define MX8ULP_PAD_PTE9__LPI2C6_SDA 0x00A4 0x09BC 0x5 0x1
#define MX8ULP_PAD_PTE9__TPM4_CH1 0x00A4 0x0808 0x6 0x1
#define MX8ULP_PAD_PTE9__I2S6_RXD3 0x00A4 0x0B40 0x7 0x2
#define MX8ULP_PAD_PTE9__SDHC2_D7 0x00A4 0x0AB4 0x8 0x1
#define MX8ULP_PAD_PTE9__FLEXSPI2_B_DATA1 0x00A4 0x0958 0x9 0x2
#define MX8ULP_PAD_PTE9__ENET0_1588_TMR3 0x00A4 0x0AE0 0xa 0x1
#define MX8ULP_PAD_PTE9__DBI0_D4 0x00A4 0x0000 0xb 0x0
#define MX8ULP_PAD_PTE9__EPDC0_VCOM1 0x00A4 0x0000 0xc 0x0
#define MX8ULP_PAD_PTE9__LP_HV_DBG_MUX_4 0x00A4 0x0000 0xe 0x0
#define MX8ULP_PAD_PTE9__DEBUG_MUX1_20 0x00A4 0x0000 0xf 0x0
#define MX8ULP_PAD_PTE10__PTE10 0x00A8 0x0000 0x1 0x0
#define MX8ULP_PAD_PTE10__FXIO1_D13 0x00A8 0x0850 0x2 0x1
#define MX8ULP_PAD_PTE10__LPSPI4_PCS3 0x00A8 0x0900 0x3 0x2
#define MX8ULP_PAD_PTE10__LPUART6_TX 0x00A8 0x09D4 0x4 0x1
#define MX8ULP_PAD_PTE10__I3C2_SCL 0x00A8 0x08BC 0x5 0x1
#define MX8ULP_PAD_PTE10__TPM4_CH2 0x00A8 0x080C 0x6 0x1
#define MX8ULP_PAD_PTE10__I2S6_TX_BCLK 0x00A8 0x0B4C 0x7 0x2
#define MX8ULP_PAD_PTE10__SDHC2_DQS 0x00A8 0x0AB8 0x8 0x1
#define MX8ULP_PAD_PTE10__FLEXSPI2_B_DATA0 0x00A8 0x0954 0x9 0x2
#define MX8ULP_PAD_PTE10__ENET0_1588_TMR2 0x00A8 0x0ADC 0xa 0x1
#define MX8ULP_PAD_PTE10__DBI0_D5 0x00A8 0x0000 0xb 0x0
#define MX8ULP_PAD_PTE10__EPDC0_VCOM0 0x00A8 0x0000 0xc 0x0
#define MX8ULP_PAD_PTE10__LP_HV_DBG_MUX_5 0x00A8 0x0000 0xe 0x0
#define MX8ULP_PAD_PTE10__DEBUG_MUX1_21 0x00A8 0x0000 0xf 0x0
#define MX8ULP_PAD_PTE11__PTE11 0x00AC 0x0000 0x1 0x0
#define MX8ULP_PAD_PTE11__FXIO1_D12 0x00AC 0x084C 0x2 0x1
#define MX8ULP_PAD_PTE11__SPDIF_OUT1 0x00AC 0x0000 0x3 0x0
#define MX8ULP_PAD_PTE11__LPUART6_RX 0x00AC 0x09D0 0x4 0x1
#define MX8ULP_PAD_PTE11__I3C2_SDA 0x00AC 0x08C0 0x5 0x1
#define MX8ULP_PAD_PTE11__TPM4_CH3 0x00AC 0x0810 0x6 0x1
#define MX8ULP_PAD_PTE11__I2S6_TX_FS 0x00AC 0x0B50 0x7 0x2
#define MX8ULP_PAD_PTE11__FLEXSPI2_B_SCLK_B 0x00AC 0x0000 0x8 0x0
#define MX8ULP_PAD_PTE11__FLEXSPI2_B_SS0_B 0x00AC 0x0000 0x9 0x0
#define MX8ULP_PAD_PTE11__ENET0_1588_TMR1 0x00AC 0x0AD8 0xa 0x1
#define MX8ULP_PAD_PTE11__DBI0_D6 0x00AC 0x0000 0xb 0x0
#define MX8ULP_PAD_PTE11__EPDC0_PWRCTRL0 0x00AC 0x0000 0xc 0x0
#define MX8ULP_PAD_PTE11__LP_HV_DBG_MUX_6 0x00AC 0x0000 0xf 0x0
#define MX8ULP_PAD_PTE12__PTE12 0x00B0 0x0000 0x1 0x0
#define MX8ULP_PAD_PTE12__FXIO1_D11 0x00B0 0x0848 0x2 0x1
#define MX8ULP_PAD_PTE12__LPSPI4_SIN 0x00B0 0x0908 0x3 0x2
#define MX8ULP_PAD_PTE12__LPUART7_CTS_B 0x00B0 0x09D8 0x4 0x1
#define MX8ULP_PAD_PTE12__LPI2C7_SCL 0x00B0 0x09C4 0x5 0x1
#define MX8ULP_PAD_PTE12__TPM4_CH4 0x00B0 0x0814 0x6 0x1
#define MX8ULP_PAD_PTE12__I2S6_TXD0 0x00B0 0x0000 0x7 0x0
#define MX8ULP_PAD_PTE12__SDHC2_RESET_B 0x00B0 0x0000 0x8 0x0
#define MX8ULP_PAD_PTE12__FLEXSPI2_B_SS1_B 0x00B0 0x0000 0x9 0x0
#define MX8ULP_PAD_PTE12__ENET0_1588_TMR0 0x00B0 0x0AD4 0xa 0x1
#define MX8ULP_PAD_PTE12__DBI0_D7 0x00B0 0x0000 0xb 0x0
#define MX8ULP_PAD_PTE12__EPDC0_PWRCTRL1 0x00B0 0x0000 0xc 0x0
#define MX8ULP_PAD_PTE12__WUU1_P5 0x00B0 0x0000 0xd 0x0
#define MX8ULP_PAD_PTE13__PTE13 0x00B4 0x0000 0x1 0x0
#define MX8ULP_PAD_PTE13__FXIO1_D10 0x00B4 0x0844 0x2 0x1
#define MX8ULP_PAD_PTE13__LPSPI4_SOUT 0x00B4 0x090C 0x3 0x2
#define MX8ULP_PAD_PTE13__LPUART7_RTS_B 0x00B4 0x0000 0x4 0x0
#define MX8ULP_PAD_PTE13__LPI2C7_SDA 0x00B4 0x09C8 0x5 0x1
#define MX8ULP_PAD_PTE13__TPM4_CH5 0x00B4 0x0818 0x6 0x1
#define MX8ULP_PAD_PTE13__I2S6_TXD1 0x00B4 0x0000 0x7 0x0
#define MX8ULP_PAD_PTE13__SDHC1_WP 0x00B4 0x0A88 0x8 0x2
#define MX8ULP_PAD_PTE13__ENET0_1588_CLKIN 0x00B4 0x0AD0 0xa 0x1
#define MX8ULP_PAD_PTE13__DBI0_D8 0x00B4 0x0000 0xb 0x0
#define MX8ULP_PAD_PTE13__EPDC0_PWRCTRL2 0x00B4 0x0000 0xc 0x0
#define MX8ULP_PAD_PTE13__LP_HV_DBG_MUX_7 0x00B4 0x0000 0xf 0x0
#define MX8ULP_PAD_PTE14__PTE14 0x00B8 0x0000 0x1 0x0
#define MX8ULP_PAD_PTE14__FXIO1_D9 0x00B8 0x08B8 0x2 0x1
#define MX8ULP_PAD_PTE14__LPSPI4_SCK 0x00B8 0x0904 0x3 0x2
#define MX8ULP_PAD_PTE14__LPUART7_TX 0x00B8 0x09E0 0x4 0x1
#define MX8ULP_PAD_PTE14__LPI2C7_HREQ 0x00B8 0x09C0 0x5 0x1
#define MX8ULP_PAD_PTE14__TPM5_CLKIN 0x00B8 0x0838 0x6 0x1
#define MX8ULP_PAD_PTE14__I2S6_TXD2 0x00B8 0x0000 0x7 0x0
#define MX8ULP_PAD_PTE14__SDHC1_CD 0x00B8 0x0A58 0x8 0x2
#define MX8ULP_PAD_PTE14__ENET0_MDIO 0x00B8 0x0AF0 0xa 0x1
#define MX8ULP_PAD_PTE14__DBI0_D9 0x00B8 0x0000 0xb 0x0
#define MX8ULP_PAD_PTE14__EPDC0_PWRCTRL3 0x00B8 0x0000 0xc 0x0
#define MX8ULP_PAD_PTE14__LP_HV_DBG_MUX_8 0x00B8 0x0000 0xf 0x0
#define MX8ULP_PAD_PTE15__PTE15 0x00BC 0x0000 0x1 0x0
#define MX8ULP_PAD_PTE15__FXIO1_D8 0x00BC 0x08B4 0x2 0x1
#define MX8ULP_PAD_PTE15__LPSPI4_PCS0 0x00BC 0x08F4 0x3 0x2
#define MX8ULP_PAD_PTE15__LPUART7_RX 0x00BC 0x09DC 0x4 0x1
#define MX8ULP_PAD_PTE15__I3C2_PUR 0x00BC 0x0000 0x5 0x0
#define MX8ULP_PAD_PTE15__TPM5_CH0 0x00BC 0x0820 0x6 0x1
#define MX8ULP_PAD_PTE15__I2S6_TXD3 0x00BC 0x0000 0x7 0x0
#define MX8ULP_PAD_PTE15__MQS1_LEFT 0x00BC 0x0000 0x8 0x0
#define MX8ULP_PAD_PTE15__ENET0_MDC 0x00BC 0x0000 0xa 0x0
#define MX8ULP_PAD_PTE15__DBI0_D10 0x00BC 0x0000 0xb 0x0
#define MX8ULP_PAD_PTE15__EPDC0_PWRCOM 0x00BC 0x0000 0xc 0x0
#define MX8ULP_PAD_PTE15__WUU1_P6 0x00BC 0x0000 0xd 0x0
#define MX8ULP_PAD_PTE16__PTE16 0x00C0 0x0000 0x1 0x0
#define MX8ULP_PAD_PTE16__FXIO1_D7 0x00C0 0x08B0 0x2 0x1
#define MX8ULP_PAD_PTE16__LPSPI5_PCS1 0x00C0 0x0914 0x3 0x1
#define MX8ULP_PAD_PTE16__LPUART4_CTS_B 0x00C0 0x08DC 0x4 0x2
#define MX8ULP_PAD_PTE16__LPI2C4_SCL 0x00C0 0x08C8 0x5 0x2
#define MX8ULP_PAD_PTE16__TPM5_CH1 0x00C0 0x0824 0x6 0x1
#define MX8ULP_PAD_PTE16__MQS1_LEFT 0x00C0 0x0000 0x7 0x0
#define MX8ULP_PAD_PTE16__MQS1_RIGHT 0x00C0 0x0000 0x8 0x0
#define MX8ULP_PAD_PTE16__USB0_ID 0x00C0 0x0AC8 0x9 0x2
#define MX8ULP_PAD_PTE16__ENET0_TXEN 0x00C0 0x0000 0xa 0x0
#define MX8ULP_PAD_PTE16__DBI0_D11 0x00C0 0x0000 0xb 0x0
#define MX8ULP_PAD_PTE16__EPDC0_PWRIRQ 0x00C0 0x0000 0xc 0x0
#define MX8ULP_PAD_PTE16__WDOG3_RST 0x00C0 0x0000 0xd 0x0
#define MX8ULP_PAD_PTE16__LP_HV_DBG_MUX_9 0x00C0 0x0000 0xf 0x0
#define MX8ULP_PAD_PTE17__PTE17 0x00C4 0x0000 0x1 0x0
#define MX8ULP_PAD_PTE17__FXIO1_D6 0x00C4 0x08AC 0x2 0x1
#define MX8ULP_PAD_PTE17__LPSPI5_PCS2 0x00C4 0x0918 0x3 0x1
#define MX8ULP_PAD_PTE17__LPUART4_RTS_B 0x00C4 0x0000 0x4 0x0
#define MX8ULP_PAD_PTE17__LPI2C4_SDA 0x00C4 0x08CC 0x5 0x2
#define MX8ULP_PAD_PTE17__MQS1_RIGHT 0x00C4 0x0000 0x7 0x0
#define MX8ULP_PAD_PTE17__SDHC1_VS 0x00C4 0x0000 0x8 0x0
#define MX8ULP_PAD_PTE17__USB0_PWR 0x00C4 0x0000 0x9 0x0
#define MX8ULP_PAD_PTE17__ENET0_RXER 0x00C4 0x0B08 0xa 0x1
#define MX8ULP_PAD_PTE17__DBI0_D12 0x00C4 0x0000 0xb 0x0
#define MX8ULP_PAD_PTE17__EPDC0_PWRSTAT 0x00C4 0x0000 0xc 0x0
#define MX8ULP_PAD_PTE17__LP_HV_DBG_MUX_10 0x00C4 0x0000 0xf 0x0
#define MX8ULP_PAD_PTE18__PTE18 0x00C8 0x0000 0x1 0x0
#define MX8ULP_PAD_PTE18__FXIO1_D5 0x00C8 0x08A8 0x2 0x1
#define MX8ULP_PAD_PTE18__LPSPI5_PCS3 0x00C8 0x091C 0x3 0x1
#define MX8ULP_PAD_PTE18__LPUART4_TX 0x00C8 0x08E4 0x4 0x2
#define MX8ULP_PAD_PTE18__LPI2C4_HREQ 0x00C8 0x08C4 0x5 0x2
#define MX8ULP_PAD_PTE18__I2S7_TX_BCLK 0x00C8 0x0B6C 0x7 0x2
#define MX8ULP_PAD_PTE18__USB0_OC 0x00C8 0x0AC0 0x9 0x2
#define MX8ULP_PAD_PTE18__ENET0_CRS_DV 0x00C8 0x0AEC 0xa 0x1
#define MX8ULP_PAD_PTE18__DBI0_D13 0x00C8 0x0000 0xb 0x0
#define MX8ULP_PAD_PTE18__EPDC0_PWRWAKE 0x00C8 0x0000 0xc 0x0
#define MX8ULP_PAD_PTE18__LP_HV_DBG_MUX_11 0x00C8 0x0000 0xf 0x0
#define MX8ULP_PAD_PTE19__PTE19 0x00CC 0x0000 0x1 0x0
#define MX8ULP_PAD_PTE19__FXIO1_D4 0x00CC 0x08A4 0x2 0x1
#define MX8ULP_PAD_PTE19__LPUART4_RX 0x00CC 0x08E0 0x4 0x2
#define MX8ULP_PAD_PTE19__LPI2C5_HREQ 0x00CC 0x08D0 0x5 0x2
#define MX8ULP_PAD_PTE19__I3C2_PUR 0x00CC 0x0000 0x6 0x0
#define MX8ULP_PAD_PTE19__I2S7_TX_FS 0x00CC 0x0B70 0x7 0x2
#define MX8ULP_PAD_PTE19__USB1_PWR 0x00CC 0x0000 0x9 0x0
#define MX8ULP_PAD_PTE19__ENET0_REFCLK 0x00CC 0x0AF4 0xa 0x1
#define MX8ULP_PAD_PTE19__DBI0_D14 0x00CC 0x0000 0xb 0x0
#define MX8ULP_PAD_PTE19__EPDC0_GDCLK 0x00CC 0x0000 0xc 0x0
#define MX8ULP_PAD_PTE19__WUU1_P7 0x00CC 0x0000 0xd 0x0
#define MX8ULP_PAD_PTE20__PTE20 0x00D0 0x0000 0x1 0x0
#define MX8ULP_PAD_PTE20__FXIO1_D3 0x00D0 0x0898 0x2 0x1
#define MX8ULP_PAD_PTE20__LPSPI5_SIN 0x00D0 0x0924 0x3 0x1
#define MX8ULP_PAD_PTE20__LPUART5_CTS_B 0x00D0 0x08E8 0x4 0x2
#define MX8ULP_PAD_PTE20__LPI2C5_SCL 0x00D0 0x08D4 0x5 0x2
#define MX8ULP_PAD_PTE20__I2S7_TXD0 0x00D0 0x0000 0x7 0x0
#define MX8ULP_PAD_PTE20__USB1_OC 0x00D0 0x0AC4 0x9 0x2
#define MX8ULP_PAD_PTE20__ENET0_RXD1 0x00D0 0x0AFC 0xa 0x1
#define MX8ULP_PAD_PTE20__DBI0_D15 0x00D0 0x0000 0xb 0x0
#define MX8ULP_PAD_PTE20__EPDC0_GDOE 0x00D0 0x0000 0xc 0x0
#define MX8ULP_PAD_PTE20__LP_HV_DBG_MUX_12 0x00D0 0x0000 0xf 0x0
#define MX8ULP_PAD_PTE21__PTE21 0x00D4 0x0000 0x1 0x0
#define MX8ULP_PAD_PTE21__FXIO1_D2 0x00D4 0x086C 0x2 0x1
#define MX8ULP_PAD_PTE21__LPSPI5_SOUT 0x00D4 0x0928 0x3 0x1
#define MX8ULP_PAD_PTE21__LPUART5_RTS_B 0x00D4 0x0000 0x4 0x0
#define MX8ULP_PAD_PTE21__LPI2C5_SDA 0x00D4 0x08D8 0x5 0x2
#define MX8ULP_PAD_PTE21__TPM6_CLKIN 0x00D4 0x0994 0x6 0x1
#define MX8ULP_PAD_PTE21__I2S7_TXD1 0x00D4 0x0000 0x7 0x0
#define MX8ULP_PAD_PTE21__USB1_ID 0x00D4 0x0ACC 0x9 0x2
#define MX8ULP_PAD_PTE21__ENET0_RXD0 0x00D4 0x0AF8 0xa 0x1
#define MX8ULP_PAD_PTE21__EPDC0_GDRL 0x00D4 0x0000 0xc 0x0
#define MX8ULP_PAD_PTE21__WDOG4_RST 0x00D4 0x0000 0xd 0x0
#define MX8ULP_PAD_PTE21__LP_HV_DBG_MUX_13 0x00D4 0x0000 0xf 0x0
#define MX8ULP_PAD_PTE22__PTE22 0x00D8 0x0000 0x1 0x0
#define MX8ULP_PAD_PTE22__FXIO1_D1 0x00D8 0x0840 0x2 0x1
#define MX8ULP_PAD_PTE22__LPSPI5_SCK 0x00D8 0x0920 0x3 0x1
#define MX8ULP_PAD_PTE22__LPUART5_TX 0x00D8 0x08F0 0x4 0x2
#define MX8ULP_PAD_PTE22__I3C2_SCL 0x00D8 0x08BC 0x5 0x2
#define MX8ULP_PAD_PTE22__TPM6_CH0 0x00D8 0x097C 0x6 0x1
#define MX8ULP_PAD_PTE22__I2S7_TXD2 0x00D8 0x0000 0x7 0x0
#define MX8ULP_PAD_PTE22__EXT_AUD_MCLK3 0x00D8 0x0B14 0x9 0x5
#define MX8ULP_PAD_PTE22__ENET0_TXD1 0x00D8 0x0000 0xa 0x0
#define MX8ULP_PAD_PTE22__EPDC0_SDOED 0x00D8 0x0000 0xc 0x0
#define MX8ULP_PAD_PTE22__CLKOUT2 0x00D8 0x0000 0xd 0x0
#define MX8ULP_PAD_PTE22__LP_HV_DBG_MUX_14 0x00D8 0x0000 0xf 0x0
#define MX8ULP_PAD_PTE23__PTE23 0x00DC 0x0000 0x1 0x0
#define MX8ULP_PAD_PTE23__FXIO1_D0 0x00DC 0x083C 0x2 0x1
#define MX8ULP_PAD_PTE23__LPSPI5_PCS0 0x00DC 0x0910 0x3 0x1
#define MX8ULP_PAD_PTE23__LPUART5_RX 0x00DC 0x08EC 0x4 0x2
#define MX8ULP_PAD_PTE23__I3C2_SDA 0x00DC 0x08C0 0x5 0x2
#define MX8ULP_PAD_PTE23__TPM6_CH1 0x00DC 0x0980 0x6 0x1
#define MX8ULP_PAD_PTE23__I2S7_TXD3 0x00DC 0x0000 0x7 0x0
#define MX8ULP_PAD_PTE23__EXT_AUD_MCLK2 0x00DC 0x0800 0x9 0x1
#define MX8ULP_PAD_PTE23__ENET0_TXD0 0x00DC 0x0000 0xa 0x0
#define MX8ULP_PAD_PTE23__EPDC0_SDOEZ 0x00DC 0x0000 0xc 0x0
#define MX8ULP_PAD_PTE23__CLKOUT1 0x00DC 0x0000 0xd 0x0
#define MX8ULP_PAD_PTE23__LP_HV_DBG_MUX_15 0x00DC 0x0000 0xf 0x0
#define MX8ULP_PAD_PTF0__PTF0 0x0100 0x0000 0x1 0x0
#define MX8ULP_PAD_PTF0__FXIO1_D0 0x0100 0x083C 0x2 0x2
#define MX8ULP_PAD_PTF0__LPUART6_CTS_B 0x0100 0x09CC 0x4 0x2
#define MX8ULP_PAD_PTF0__LPI2C6_SCL 0x0100 0x09B8 0x5 0x2
#define MX8ULP_PAD_PTF0__I2S7_RX_BCLK 0x0100 0x0B64 0x7 0x2
#define MX8ULP_PAD_PTF0__SDHC1_D1 0x0100 0x0A68 0x8 0x2
#define MX8ULP_PAD_PTF0__ENET0_RXD1 0x0100 0x0AFC 0x9 0x2
#define MX8ULP_PAD_PTF0__USB1_ID 0x0100 0x0ACC 0xa 0x3
#define MX8ULP_PAD_PTF0__EPDC0_SDOE 0x0100 0x0000 0xb 0x0
#define MX8ULP_PAD_PTF0__DPI0_D23 0x0100 0x0000 0xc 0x0
#define MX8ULP_PAD_PTF0__WUU1_P8 0x0100 0x0000 0xd 0x0
#define MX8ULP_PAD_PTF1__PTF1 0x0104 0x0000 0x1 0x0
#define MX8ULP_PAD_PTF1__FXIO1_D1 0x0104 0x0840 0x2 0x2
#define MX8ULP_PAD_PTF1__LPUART6_RTS_B 0x0104 0x0000 0x4 0x0
#define MX8ULP_PAD_PTF1__LPI2C6_SDA 0x0104 0x09BC 0x5 0x2
#define MX8ULP_PAD_PTF1__I2S7_RX_FS 0x0104 0x0B68 0x7 0x2
#define MX8ULP_PAD_PTF1__SDHC1_D0 0x0104 0x0A64 0x8 0x2
#define MX8ULP_PAD_PTF1__ENET0_RXD0 0x0104 0x0AF8 0x9 0x2
#define MX8ULP_PAD_PTF1__LP_HV_DBG_MUX_16 0x0104 0x0000 0xa 0x0
#define MX8ULP_PAD_PTF1__EPDC0_SDSHR 0x0104 0x0000 0xb 0x0
#define MX8ULP_PAD_PTF1__DPI0_D22 0x0104 0x0000 0xc 0x0
#define MX8ULP_PAD_PTF1__WDOG3_RST 0x0104 0x0000 0xd 0x0
#define MX8ULP_PAD_PTF1__DEBUG_MUX0_16 0x0104 0x0000 0xe 0x0
#define MX8ULP_PAD_PTF1__DEBUG_MUX1_22 0x0104 0x0000 0xf 0x0
#define MX8ULP_PAD_PTF2__PTF2 0x0108 0x0000 0x1 0x0
#define MX8ULP_PAD_PTF2__FXIO1_D2 0x0108 0x086C 0x2 0x2
#define MX8ULP_PAD_PTF2__LPUART6_TX 0x0108 0x09D4 0x4 0x2
#define MX8ULP_PAD_PTF2__LPI2C6_HREQ 0x0108 0x09B4 0x5 0x2
#define MX8ULP_PAD_PTF2__I2S7_RXD0 0x0108 0x0B54 0x7 0x2
#define MX8ULP_PAD_PTF2__SDHC1_CLK 0x0108 0x0A5C 0x8 0x2
#define MX8ULP_PAD_PTF2__ENET0_TXD1 0x0108 0x0000 0x9 0x0
#define MX8ULP_PAD_PTF2__USB0_ID 0x0108 0x0AC8 0xa 0x3
#define MX8ULP_PAD_PTF2__EPDC0_SDCE9 0x0108 0x0000 0xb 0x0
#define MX8ULP_PAD_PTF2__DPI0_D21 0x0108 0x0000 0xc 0x0
#define MX8ULP_PAD_PTF2__LP_HV_DBG_MUX_17 0x0108 0x0000 0xd 0x0
#define MX8ULP_PAD_PTF2__DEBUG_MUX0_17 0x0108 0x0000 0xe 0x0
#define MX8ULP_PAD_PTF2__DEBUG_MUX1_23 0x0108 0x0000 0xf 0x0
#define MX8ULP_PAD_PTF3__PTF3 0x010C 0x0000 0x1 0x0
#define MX8ULP_PAD_PTF3__FXIO1_D3 0x010C 0x0898 0x2 0x2
#define MX8ULP_PAD_PTF3__LPUART6_RX 0x010C 0x09D0 0x4 0x2
#define MX8ULP_PAD_PTF3__LPI2C7_HREQ 0x010C 0x09C0 0x5 0x2
#define MX8ULP_PAD_PTF3__I2S7_RXD1 0x010C 0x0B58 0x7 0x2
#define MX8ULP_PAD_PTF3__SDHC1_CMD 0x010C 0x0A60 0x8 0x2
#define MX8ULP_PAD_PTF3__ENET0_TXD0 0x010C 0x0000 0x9 0x0
#define MX8ULP_PAD_PTF3__USB0_PWR 0x010C 0x0000 0xa 0x0
#define MX8ULP_PAD_PTF3__EPDC0_SDCE8 0x010C 0x0000 0xb 0x0
#define MX8ULP_PAD_PTF3__DPI0_D20 0x010C 0x0000 0xc 0x0
#define MX8ULP_PAD_PTF3__WUU1_P9 0x010C 0x0000 0xd 0x0
#define MX8ULP_PAD_PTF3__DEBUG_MUX1_24 0x010C 0x0000 0xf 0x0
#define MX8ULP_PAD_PTF4__PTF4 0x0110 0x0000 0x1 0x0
#define MX8ULP_PAD_PTF4__FXIO1_D4 0x0110 0x08A4 0x2 0x2
#define MX8ULP_PAD_PTF4__LPSPI4_PCS1 0x0110 0x08F8 0x3 0x3
#define MX8ULP_PAD_PTF4__LPUART7_CTS_B 0x0110 0x09D8 0x4 0x2
#define MX8ULP_PAD_PTF4__LPI2C7_SCL 0x0110 0x09C4 0x5 0x2
#define MX8ULP_PAD_PTF4__TPM7_CLKIN 0x0110 0x09B0 0x6 0x1
#define MX8ULP_PAD_PTF4__I2S7_RXD2 0x0110 0x0B5C 0x7 0x2
#define MX8ULP_PAD_PTF4__SDHC1_D3 0x0110 0x0A70 0x8 0x2
#define MX8ULP_PAD_PTF4__ENET0_TXEN 0x0110 0x0000 0x9 0x0
#define MX8ULP_PAD_PTF4__USB0_OC 0x0110 0x0AC0 0xa 0x3
#define MX8ULP_PAD_PTF4__EPDC0_SDCE7 0x0110 0x0000 0xb 0x0
#define MX8ULP_PAD_PTF4__DPI0_D19 0x0110 0x0000 0xc 0x0
#define MX8ULP_PAD_PTF4__WUU1_P10 0x0110 0x0000 0xd 0x0
#define MX8ULP_PAD_PTF4__DEBUG_MUX1_25 0x0110 0x0000 0xf 0x0
#define MX8ULP_PAD_PTF5__PTF5 0x0114 0x0000 0x1 0x0
#define MX8ULP_PAD_PTF5__FXIO1_D5 0x0114 0x08A8 0x2 0x2
#define MX8ULP_PAD_PTF5__LPSPI4_PCS2 0x0114 0x08FC 0x3 0x3
#define MX8ULP_PAD_PTF5__LPUART7_RTS_B 0x0114 0x0000 0x4 0x0
#define MX8ULP_PAD_PTF5__LPI2C7_SDA 0x0114 0x09C8 0x5 0x2
#define MX8ULP_PAD_PTF5__TPM7_CH0 0x0114 0x0998 0x6 0x1
#define MX8ULP_PAD_PTF5__I2S7_RXD3 0x0114 0x0B60 0x7 0x2
#define MX8ULP_PAD_PTF5__SDHC1_D2 0x0114 0x0A6C 0x8 0x2
#define MX8ULP_PAD_PTF5__ENET0_RXER 0x0114 0x0B08 0x9 0x2
#define MX8ULP_PAD_PTF5__USB1_PWR 0x0114 0x0000 0xa 0x0
#define MX8ULP_PAD_PTF5__EPDC0_SDCE6 0x0114 0x0000 0xb 0x0
#define MX8ULP_PAD_PTF5__DPI0_D18 0x0114 0x0000 0xc 0x0
#define MX8ULP_PAD_PTF5__LP_HV_DBG_MUX_18 0x0114 0x0000 0xd 0x0
#define MX8ULP_PAD_PTF5__DEBUG_MUX0_18 0x0114 0x0000 0xe 0x0
#define MX8ULP_PAD_PTF5__DEBUG_MUX1_26 0x0114 0x0000 0xf 0x0
#define MX8ULP_PAD_PTF6__LP_HV_DBG_MUX_19 0x0118 0x0000 0x0 0x0
#define MX8ULP_PAD_PTF6__PTF6 0x0118 0x0000 0x1 0x0
#define MX8ULP_PAD_PTF6__FXIO1_D6 0x0118 0x08AC 0x2 0x2
#define MX8ULP_PAD_PTF6__LPSPI4_PCS3 0x0118 0x0900 0x3 0x3
#define MX8ULP_PAD_PTF6__LPUART7_TX 0x0118 0x09E0 0x4 0x2
#define MX8ULP_PAD_PTF6__I3C2_SCL 0x0118 0x08BC 0x5 0x3
#define MX8ULP_PAD_PTF6__TPM7_CH1 0x0118 0x099C 0x6 0x1
#define MX8ULP_PAD_PTF6__I2S7_MCLK 0x0118 0x0000 0x7 0x0
#define MX8ULP_PAD_PTF6__SDHC1_D4 0x0118 0x0A74 0x8 0x2
#define MX8ULP_PAD_PTF6__ENET0_CRS_DV 0x0118 0x0AEC 0x9 0x2
#define MX8ULP_PAD_PTF6__USB1_OC 0x0118 0x0AC4 0xa 0x3
#define MX8ULP_PAD_PTF6__EPDC0_SDCE5 0x0118 0x0000 0xb 0x0
#define MX8ULP_PAD_PTF6__DPI0_D17 0x0118 0x0000 0xc 0x0
#define MX8ULP_PAD_PTF6__WDOG4_RST 0x0118 0x0000 0xd 0x0
#define MX8ULP_PAD_PTF6__DEBUG_MUX0_19 0x0118 0x0000 0xe 0x0
#define MX8ULP_PAD_PTF6__DEBUG_MUX1_27 0x0118 0x0000 0xf 0x0
#define MX8ULP_PAD_PTF7__PTF7 0x011C 0x0000 0x1 0x0
#define MX8ULP_PAD_PTF7__FXIO1_D7 0x011C 0x08B0 0x2 0x2
#define MX8ULP_PAD_PTF7__LPUART7_RX 0x011C 0x09DC 0x4 0x2
#define MX8ULP_PAD_PTF7__I3C2_SDA 0x011C 0x08C0 0x5 0x3
#define MX8ULP_PAD_PTF7__TPM7_CH2 0x011C 0x09A0 0x6 0x1
#define MX8ULP_PAD_PTF7__MQS1_LEFT 0x011C 0x0000 0x7 0x0
#define MX8ULP_PAD_PTF7__SDHC1_D5 0x011C 0x0A78 0x8 0x2
#define MX8ULP_PAD_PTF7__ENET0_REFCLK 0x011C 0x0AF4 0x9 0x2
#define MX8ULP_PAD_PTF7__TRACE0_D15 0x011C 0x0000 0xa 0x0
#define MX8ULP_PAD_PTF7__EPDC0_SDCE4 0x011C 0x0000 0xb 0x0
#define MX8ULP_PAD_PTF7__DPI0_D16 0x011C 0x0000 0xc 0x0
#define MX8ULP_PAD_PTF7__WUU1_P11 0x011C 0x0000 0xd 0x0
#define MX8ULP_PAD_PTF7__DEBUG_MUX1_28 0x011C 0x0000 0xf 0x0
#define MX8ULP_PAD_PTF8__PTF8 0x0120 0x0000 0x1 0x0
#define MX8ULP_PAD_PTF8__FXIO1_D8 0x0120 0x08B4 0x2 0x2
#define MX8ULP_PAD_PTF8__LPSPI4_SIN 0x0120 0x0908 0x3 0x3
#define MX8ULP_PAD_PTF8__LPUART4_CTS_B 0x0120 0x08DC 0x4 0x3
#define MX8ULP_PAD_PTF8__LPI2C4_SCL 0x0120 0x08C8 0x5 0x3
#define MX8ULP_PAD_PTF8__TPM7_CH3 0x0120 0x09A4 0x6 0x1
#define MX8ULP_PAD_PTF8__MQS1_RIGHT 0x0120 0x0000 0x7 0x0
#define MX8ULP_PAD_PTF8__SDHC1_D6 0x0120 0x0A7C 0x8 0x2
#define MX8ULP_PAD_PTF8__ENET0_MDIO 0x0120 0x0AF0 0x9 0x2
#define MX8ULP_PAD_PTF8__TRACE0_D14 0x0120 0x0000 0xa 0x0
#define MX8ULP_PAD_PTF8__EPDC0_D15 0x0120 0x0000 0xb 0x0
#define MX8ULP_PAD_PTF8__DPI0_D15 0x0120 0x0000 0xc 0x0
#define MX8ULP_PAD_PTF8__LP_HV_DBG_MUX_24 0x0120 0x0000 0xe 0x0
#define MX8ULP_PAD_PTF8__DEBUG_MUX1_29 0x0120 0x0000 0xf 0x0
#define MX8ULP_PAD_PTF9__PTF9 0x0124 0x0000 0x1 0x0
#define MX8ULP_PAD_PTF9__FXIO1_D9 0x0124 0x08B8 0x2 0x2
#define MX8ULP_PAD_PTF9__LPSPI4_SOUT 0x0124 0x090C 0x3 0x3
#define MX8ULP_PAD_PTF9__LPUART4_RTS_B 0x0124 0x0000 0x4 0x0
#define MX8ULP_PAD_PTF9__LPI2C4_SDA 0x0124 0x08CC 0x5 0x3
#define MX8ULP_PAD_PTF9__TPM7_CH4 0x0124 0x09A8 0x6 0x1
#define MX8ULP_PAD_PTF9__EXT_AUD_MCLK2 0x0124 0x0800 0x7 0x2
#define MX8ULP_PAD_PTF9__SDHC1_D7 0x0124 0x0A80 0x8 0x2
#define MX8ULP_PAD_PTF9__ENET0_MDC 0x0124 0x0000 0x9 0x0
#define MX8ULP_PAD_PTF9__TRACE0_D13 0x0124 0x0000 0xa 0x0
#define MX8ULP_PAD_PTF9__EPDC0_D14 0x0124 0x0000 0xb 0x0
#define MX8ULP_PAD_PTF9__DPI0_D14 0x0124 0x0000 0xc 0x0
#define MX8ULP_PAD_PTF9__LP_HV_DBG_MUX_25 0x0124 0x0000 0xe 0x0
#define MX8ULP_PAD_PTF9__DEBUG_MUX1_30 0x0124 0x0000 0xf 0x0
#define MX8ULP_PAD_PTF10__LP_HV_DBG_MUX_26 0x0128 0x0000 0x0 0x0
#define MX8ULP_PAD_PTF10__PTF10 0x0128 0x0000 0x1 0x0
#define MX8ULP_PAD_PTF10__FXIO1_D10 0x0128 0x0844 0x2 0x2
#define MX8ULP_PAD_PTF10__LPSPI4_SCK 0x0128 0x0904 0x3 0x3
#define MX8ULP_PAD_PTF10__LPUART4_TX 0x0128 0x08E4 0x4 0x3
#define MX8ULP_PAD_PTF10__LPI2C4_HREQ 0x0128 0x08C4 0x5 0x3
#define MX8ULP_PAD_PTF10__TPM7_CH5 0x0128 0x09AC 0x6 0x1
#define MX8ULP_PAD_PTF10__I2S4_RX_BCLK 0x0128 0x0000 0x7 0x0
#define MX8ULP_PAD_PTF10__SDHC1_DQS 0x0128 0x0A84 0x8 0x2
#define MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x0128 0x0AD0 0x9 0x2
#define MX8ULP_PAD_PTF10__TRACE0_D12 0x0128 0x0000 0xa 0x0
#define MX8ULP_PAD_PTF10__EPDC0_D13 0x0128 0x0000 0xb 0x0
#define MX8ULP_PAD_PTF10__DPI0_D13 0x0128 0x0000 0xc 0x0
#define MX8ULP_PAD_PTF10__DEBUG_MUX0_20 0x0128 0x0000 0xe 0x0
#define MX8ULP_PAD_PTF10__DEBUG_MUX1_31 0x0128 0x0000 0xf 0x0
#define MX8ULP_PAD_PTF11__PTF11 0x012C 0x0000 0x1 0x0
#define MX8ULP_PAD_PTF11__FXIO1_D11 0x012C 0x0848 0x2 0x2
#define MX8ULP_PAD_PTF11__LPSPI4_PCS0 0x012C 0x08F4 0x3 0x3
#define MX8ULP_PAD_PTF11__LPUART4_RX 0x012C 0x08E0 0x4 0x3
#define MX8ULP_PAD_PTF11__TPM4_CLKIN 0x012C 0x081C 0x6 0x2
#define MX8ULP_PAD_PTF11__I2S4_RX_FS 0x012C 0x0000 0x7 0x0
#define MX8ULP_PAD_PTF11__SDHC1_RESET_B 0x012C 0x0000 0x8 0x0
#define MX8ULP_PAD_PTF11__ENET0_1588_TMR0 0x012C 0x0AD4 0x9 0x2
#define MX8ULP_PAD_PTF11__TRACE0_D11 0x012C 0x0000 0xa 0x0
#define MX8ULP_PAD_PTF11__EPDC0_D12 0x012C 0x0000 0xb 0x0
#define MX8ULP_PAD_PTF11__DPI0_D12 0x012C 0x0000 0xc 0x0
#define MX8ULP_PAD_PTF11__LP_HV_DBG_MUX_27 0x012C 0x0000 0xe 0x0
#define MX8ULP_PAD_PTF11__DEBUG_MUX1_32 0x012C 0x0000 0xf 0x0
#define MX8ULP_PAD_PTF12__PTF12 0x0130 0x0000 0x1 0x0
#define MX8ULP_PAD_PTF12__FXIO1_D12 0x0130 0x084C 0x2 0x2
#define MX8ULP_PAD_PTF12__LPSPI5_PCS1 0x0130 0x0914 0x3 0x2
#define MX8ULP_PAD_PTF12__LPUART5_CTS_B 0x0130 0x08E8 0x4 0x3
#define MX8ULP_PAD_PTF12__LPI2C5_SCL 0x0130 0x08D4 0x5 0x3
#define MX8ULP_PAD_PTF12__TPM4_CH0 0x0130 0x0804 0x6 0x2
#define MX8ULP_PAD_PTF12__I2S4_RXD0 0x0130 0x0000 0x7 0x0
#define MX8ULP_PAD_PTF12__SDHC2_WP 0x0130 0x0ABC 0x8 0x1
#define MX8ULP_PAD_PTF12__ENET0_1588_TMR1 0x0130 0x0AD8 0x9 0x2
#define MX8ULP_PAD_PTF12__TRACE0_D10 0x0130 0x0000 0xa 0x0
#define MX8ULP_PAD_PTF12__EPDC0_D11 0x0130 0x0000 0xb 0x0
#define MX8ULP_PAD_PTF12__DPI0_D11 0x0130 0x0000 0xc 0x0
#define MX8ULP_PAD_PTF12__LP_HV_DBG_MUX_28 0x0130 0x0000 0xe 0x0
#define MX8ULP_PAD_PTF12__DEBUG_MUX1_33 0x0130 0x0000 0xf 0x0
#define MX8ULP_PAD_PTF13__PTF13 0x0134 0x0000 0x1 0x0
#define MX8ULP_PAD_PTF13__FXIO1_D13 0x0134 0x0850 0x2 0x2
#define MX8ULP_PAD_PTF13__LPSPI5_PCS2 0x0134 0x0918 0x3 0x2
#define MX8ULP_PAD_PTF13__LPUART5_RTS_B 0x0134 0x0000 0x4 0x0
#define MX8ULP_PAD_PTF13__LPI2C5_SDA 0x0134 0x08D8 0x5 0x3
#define MX8ULP_PAD_PTF13__TPM4_CH1 0x0134 0x0808 0x6 0x2
#define MX8ULP_PAD_PTF13__I2S4_RXD1 0x0134 0x0000 0x7 0x0
#define MX8ULP_PAD_PTF13__SDHC2_CD 0x0134 0x0A8C 0x8 0x1
#define MX8ULP_PAD_PTF13__ENET0_1588_TMR2 0x0134 0x0ADC 0x9 0x2
#define MX8ULP_PAD_PTF13__TRACE0_D9 0x0134 0x0000 0xa 0x0
#define MX8ULP_PAD_PTF13__EPDC0_D10 0x0134 0x0000 0xb 0x0
#define MX8ULP_PAD_PTF13__DPI0_D10 0x0134 0x0000 0xc 0x0
#define MX8ULP_PAD_PTF13__DEBUG_MUX0_21 0x0134 0x0000 0xe 0x0
#define MX8ULP_PAD_PTF13__LP_HV_DBG_MUX_29 0x0134 0x0000 0xf 0x0
#define MX8ULP_PAD_PTF14__PTF14 0x0138 0x0000 0x1 0x0
#define MX8ULP_PAD_PTF14__FXIO1_D14 0x0138 0x0854 0x2 0x2
#define MX8ULP_PAD_PTF14__LPSPI5_PCS3 0x0138 0x091C 0x3 0x2
#define MX8ULP_PAD_PTF14__LPUART5_TX 0x0138 0x08F0 0x4 0x3
#define MX8ULP_PAD_PTF14__LPI2C5_HREQ 0x0138 0x08D0 0x5 0x3
#define MX8ULP_PAD_PTF14__TPM4_CH2 0x0138 0x080C 0x6 0x2
#define MX8ULP_PAD_PTF14__I2S4_MCLK 0x0138 0x0000 0x7 0x0
#define MX8ULP_PAD_PTF14__SDHC2_VS 0x0138 0x0000 0x8 0x0
#define MX8ULP_PAD_PTF14__ENET0_1588_TMR3 0x0138 0x0AE0 0x9 0x2
#define MX8ULP_PAD_PTF14__TRACE0_D8 0x0138 0x0000 0xa 0x0
#define MX8ULP_PAD_PTF14__EPDC0_D9 0x0138 0x0000 0xb 0x0
#define MX8ULP_PAD_PTF14__DPI0_D9 0x0138 0x0000 0xc 0x0
#define MX8ULP_PAD_PTF14__DEBUG_MUX0_22 0x0138 0x0000 0xe 0x0
#define MX8ULP_PAD_PTF14__LP_HV_DBG_MUX_30 0x0138 0x0000 0xf 0x0
#define MX8ULP_PAD_PTF15__PTF15 0x013C 0x0000 0x1 0x0
#define MX8ULP_PAD_PTF15__FXIO1_D15 0x013C 0x0858 0x2 0x2
#define MX8ULP_PAD_PTF15__LPUART5_RX 0x013C 0x08EC 0x4 0x3
#define MX8ULP_PAD_PTF15__TPM4_CH3 0x013C 0x0810 0x6 0x2
#define MX8ULP_PAD_PTF15__I2S4_TX_BCLK 0x013C 0x0000 0x7 0x0
#define MX8ULP_PAD_PTF15__SDHC2_D1 0x013C 0x0A9C 0x8 0x3
#define MX8ULP_PAD_PTF15__ENET0_RXD2 0x013C 0x0B00 0x9 0x2
#define MX8ULP_PAD_PTF15__TRACE0_D7 0x013C 0x0000 0xa 0x0
#define MX8ULP_PAD_PTF15__EPDC0_D8 0x013C 0x0000 0xb 0x0
#define MX8ULP_PAD_PTF15__DPI0_D8 0x013C 0x0000 0xc 0x0
#define MX8ULP_PAD_PTF15__LP_HV_DBG_MUX_31 0x013C 0x0000 0xf 0x0
#define MX8ULP_PAD_PTF16__PTF16 0x0140 0x0000 0x1 0x0
#define MX8ULP_PAD_PTF16__FXIO1_D16 0x0140 0x085C 0x2 0x2
#define MX8ULP_PAD_PTF16__LPSPI5_SIN 0x0140 0x0924 0x3 0x2
#define MX8ULP_PAD_PTF16__LPUART6_CTS_B 0x0140 0x09CC 0x4 0x3
#define MX8ULP_PAD_PTF16__LPI2C6_SCL 0x0140 0x09B8 0x5 0x3
#define MX8ULP_PAD_PTF16__TPM4_CH4 0x0140 0x0814 0x6 0x2
#define MX8ULP_PAD_PTF16__I2S4_TX_FS 0x0140 0x0000 0x7 0x0
#define MX8ULP_PAD_PTF16__SDHC2_D0 0x0140 0x0A98 0x8 0x3
#define MX8ULP_PAD_PTF16__ENET0_RXD3 0x0140 0x0B04 0x9 0x2
#define MX8ULP_PAD_PTF16__TRACE0_D6 0x0140 0x0000 0xa 0x0
#define MX8ULP_PAD_PTF16__EPDC0_D7 0x0140 0x0000 0xb 0x0
#define MX8ULP_PAD_PTF16__DPI0_D7 0x0140 0x0000 0xc 0x0
#define MX8ULP_PAD_PTF16__LP_HV_DBG_MUX_32 0x0140 0x0000 0xf 0x0
#define MX8ULP_PAD_PTF17__PTF17 0x0144 0x0000 0x1 0x0
#define MX8ULP_PAD_PTF17__FXIO1_D17 0x0144 0x0860 0x2 0x2
#define MX8ULP_PAD_PTF17__LPSPI5_SOUT 0x0144 0x0928 0x3 0x2
#define MX8ULP_PAD_PTF17__LPUART6_RTS_B 0x0144 0x0000 0x4 0x0
#define MX8ULP_PAD_PTF17__LPI2C6_SDA 0x0144 0x09BC 0x5 0x3
#define MX8ULP_PAD_PTF17__TPM4_CH5 0x0144 0x0818 0x6 0x2
#define MX8ULP_PAD_PTF17__I2S4_TXD0 0x0144 0x0000 0x7 0x0
#define MX8ULP_PAD_PTF17__SDHC2_CLK 0x0144 0x0A90 0x8 0x3
#define MX8ULP_PAD_PTF17__ENET0_RXCLK 0x0144 0x0B0C 0x9 0x2
#define MX8ULP_PAD_PTF17__TRACE0_D5 0x0144 0x0000 0xa 0x0
#define MX8ULP_PAD_PTF17__EPDC0_D6 0x0144 0x0000 0xb 0x0
#define MX8ULP_PAD_PTF17__DPI0_D6 0x0144 0x0000 0xc 0x0
#define MX8ULP_PAD_PTF17__DEBUG_MUX0_23 0x0144 0x0000 0xe 0x0
#define MX8ULP_PAD_PTF17__LP_HV_DBG_MUX_33 0x0144 0x0000 0xf 0x0
#define MX8ULP_PAD_PTF18__PTF18 0x0148 0x0000 0x1 0x0
#define MX8ULP_PAD_PTF18__FXIO1_D18 0x0148 0x0864 0x2 0x2
#define MX8ULP_PAD_PTF18__LPSPI5_SCK 0x0148 0x0920 0x3 0x2
#define MX8ULP_PAD_PTF18__LPUART6_TX 0x0148 0x09D4 0x4 0x3
#define MX8ULP_PAD_PTF18__LPI2C6_HREQ 0x0148 0x09B4 0x5 0x3
#define MX8ULP_PAD_PTF18__TPM5_CLKIN 0x0148 0x0838 0x6 0x2
#define MX8ULP_PAD_PTF18__I2S4_TXD1 0x0148 0x0000 0x7 0x0
#define MX8ULP_PAD_PTF18__SDHC2_CMD 0x0148 0x0A94 0x8 0x3
#define MX8ULP_PAD_PTF18__ENET0_TXD2 0x0148 0x0000 0x9 0x0
#define MX8ULP_PAD_PTF18__TRACE0_D4 0x0148 0x0000 0xa 0x0
#define MX8ULP_PAD_PTF18__EPDC0_D5 0x0148 0x0000 0xb 0x0
#define MX8ULP_PAD_PTF18__DPI0_D5 0x0148 0x0000 0xc 0x0
#define MX8ULP_PAD_PTF19__PTF19 0x014C 0x0000 0x1 0x0
#define MX8ULP_PAD_PTF19__FXIO1_D19 0x014C 0x0868 0x2 0x2
#define MX8ULP_PAD_PTF19__LPSPI5_PCS0 0x014C 0x0910 0x3 0x2
#define MX8ULP_PAD_PTF19__LPUART6_RX 0x014C 0x09D0 0x4 0x3
#define MX8ULP_PAD_PTF19__TPM5_CH0 0x014C 0x0820 0x6 0x2
#define MX8ULP_PAD_PTF19__I2S5_RX_BCLK 0x014C 0x0000 0x7 0x0
#define MX8ULP_PAD_PTF19__SDHC2_D3 0x014C 0x0AA4 0x8 0x3
#define MX8ULP_PAD_PTF19__ENET0_TXD3 0x014C 0x0000 0x9 0x0
#define MX8ULP_PAD_PTF19__TRACE0_D3 0x014C 0x0000 0xa 0x0
#define MX8ULP_PAD_PTF19__EPDC0_D4 0x014C 0x0000 0xb 0x0
#define MX8ULP_PAD_PTF19__DPI0_D4 0x014C 0x0000 0xc 0x0
#define MX8ULP_PAD_PTF20__PTF20 0x0150 0x0000 0x1 0x0
#define MX8ULP_PAD_PTF20__FXIO1_D20 0x0150 0x0870 0x2 0x2
#define MX8ULP_PAD_PTF20__LPUART7_CTS_B 0x0150 0x09D8 0x4 0x3
#define MX8ULP_PAD_PTF20__LPI2C7_SCL 0x0150 0x09C4 0x5 0x3
#define MX8ULP_PAD_PTF20__TPM5_CH1 0x0150 0x0824 0x6 0x2
#define MX8ULP_PAD_PTF20__I2S5_RX_FS 0x0150 0x0000 0x7 0x0
#define MX8ULP_PAD_PTF20__SDHC2_D2 0x0150 0x0AA0 0x8 0x3
#define MX8ULP_PAD_PTF20__ENET0_TXCLK 0x0150 0x0B10 0x9 0x2
#define MX8ULP_PAD_PTF20__TRACE0_D2 0x0150 0x0000 0xa 0x0
#define MX8ULP_PAD_PTF20__EPDC0_D3 0x0150 0x0000 0xb 0x0
#define MX8ULP_PAD_PTF20__DPI0_D3 0x0150 0x0000 0xc 0x0
#define MX8ULP_PAD_PTF21__PTF21 0x0154 0x0000 0x1 0x0
#define MX8ULP_PAD_PTF21__FXIO1_D21 0x0154 0x0874 0x2 0x2
#define MX8ULP_PAD_PTF21__SPDIF_CLK 0x0154 0x0000 0x3 0x0
#define MX8ULP_PAD_PTF21__LPUART7_RTS_B 0x0154 0x0000 0x4 0x0
#define MX8ULP_PAD_PTF21__LPI2C7_SDA 0x0154 0x09C8 0x5 0x3
#define MX8ULP_PAD_PTF21__TPM6_CLKIN 0x0154 0x0994 0x6 0x2
#define MX8ULP_PAD_PTF21__I2S5_RXD0 0x0154 0x0000 0x7 0x0
#define MX8ULP_PAD_PTF21__SDHC2_D4 0x0154 0x0AA8 0x8 0x2
#define MX8ULP_PAD_PTF21__ENET0_CRS 0x0154 0x0AE8 0x9 0x2
#define MX8ULP_PAD_PTF21__TRACE0_D1 0x0154 0x0000 0xa 0x0
#define MX8ULP_PAD_PTF21__EPDC0_D2 0x0154 0x0000 0xb 0x0
#define MX8ULP_PAD_PTF21__DPI0_D2 0x0154 0x0000 0xc 0x0
#define MX8ULP_PAD_PTF22__PTF22 0x0158 0x0000 0x1 0x0
#define MX8ULP_PAD_PTF22__FXIO1_D22 0x0158 0x0878 0x2 0x2
#define MX8ULP_PAD_PTF22__SPDIF_IN0 0x0158 0x0B74 0x3 0x3
#define MX8ULP_PAD_PTF22__LPUART7_TX 0x0158 0x09E0 0x4 0x3
#define MX8ULP_PAD_PTF22__LPI2C7_HREQ 0x0158 0x09C0 0x5 0x3
#define MX8ULP_PAD_PTF22__TPM6_CH0 0x0158 0x097C 0x6 0x2
#define MX8ULP_PAD_PTF22__I2S5_RXD1 0x0158 0x0000 0x7 0x0
#define MX8ULP_PAD_PTF22__SDHC2_D5 0x0158 0x0AAC 0x8 0x2
#define MX8ULP_PAD_PTF22__ENET0_COL 0x0158 0x0AE4 0x9 0x2
#define MX8ULP_PAD_PTF22__TRACE0_D0 0x0158 0x0000 0xa 0x0
#define MX8ULP_PAD_PTF22__EPDC0_D1 0x0158 0x0000 0xb 0x0
#define MX8ULP_PAD_PTF22__DPI0_D1 0x0158 0x0000 0xc 0x0
#define MX8ULP_PAD_PTF23__PTF23 0x015C 0x0000 0x1 0x0
#define MX8ULP_PAD_PTF23__FXIO1_D23 0x015C 0x087C 0x2 0x2
#define MX8ULP_PAD_PTF23__SPDIF_OUT0 0x015C 0x0000 0x3 0x0
#define MX8ULP_PAD_PTF23__LPUART7_RX 0x015C 0x09DC 0x4 0x3
#define MX8ULP_PAD_PTF23__I3C2_PUR 0x015C 0x0000 0x5 0x0
#define MX8ULP_PAD_PTF23__TPM6_CH1 0x015C 0x0980 0x6 0x2
#define MX8ULP_PAD_PTF23__I2S5_RXD2 0x015C 0x0000 0x7 0x0
#define MX8ULP_PAD_PTF23__SDHC2_D6 0x015C 0x0AB0 0x8 0x2
#define MX8ULP_PAD_PTF23__ENET0_TXER 0x015C 0x0000 0x9 0x0
#define MX8ULP_PAD_PTF23__TRACE0_CLKOUT 0x015C 0x0000 0xa 0x0
#define MX8ULP_PAD_PTF23__EPDC0_D0 0x015C 0x0000 0xb 0x0
#define MX8ULP_PAD_PTF23__DPI0_D0 0x015C 0x0000 0xc 0x0
#define MX8ULP_PAD_PTF24__PTF24 0x0160 0x0000 0x1 0x0
#define MX8ULP_PAD_PTF24__FXIO1_D24 0x0160 0x0880 0x2 0x2
#define MX8ULP_PAD_PTF24__SPDIF_IN1 0x0160 0x0B78 0x3 0x3
#define MX8ULP_PAD_PTF24__I3C2_SCL 0x0160 0x08BC 0x5 0x4
#define MX8ULP_PAD_PTF24__I2S5_RXD3 0x0160 0x0000 0x7 0x0
#define MX8ULP_PAD_PTF24__SDHC2_D7 0x0160 0x0AB4 0x8 0x2
#define MX8ULP_PAD_PTF24__DBI0_WRX 0x0160 0x0000 0xa 0x0
#define MX8ULP_PAD_PTF24__EPDC0_SDCLK 0x0160 0x0000 0xb 0x0
#define MX8ULP_PAD_PTF24__DPI0_PCLK 0x0160 0x0000 0xc 0x0
#define MX8ULP_PAD_PTF24__WUU1_P12 0x0160 0x0000 0xd 0x0
#define MX8ULP_PAD_PTF25__PTF25 0x0164 0x0000 0x1 0x0
#define MX8ULP_PAD_PTF25__FXIO1_D25 0x0164 0x0884 0x2 0x2
#define MX8ULP_PAD_PTF25__SPDIF_OUT1 0x0164 0x0000 0x3 0x0
#define MX8ULP_PAD_PTF25__I3C2_SDA 0x0164 0x08C0 0x5 0x4
#define MX8ULP_PAD_PTF25__TPM7_CH5 0x0164 0x09AC 0x6 0x2
#define MX8ULP_PAD_PTF25__I2S5_MCLK 0x0164 0x0000 0x7 0x0
#define MX8ULP_PAD_PTF25__SDHC2_DQS 0x0164 0x0AB8 0x8 0x2
#define MX8ULP_PAD_PTF25__EXT_AUD_MCLK2 0x0164 0x0800 0x9 0x3
#define MX8ULP_PAD_PTF25__EPDC0_GDSP 0x0164 0x0000 0xb 0x0
#define MX8ULP_PAD_PTF25__DPI0_VSYNC 0x0164 0x0000 0xc 0x0
#define MX8ULP_PAD_PTF25__WUU1_P13 0x0164 0x0000 0xd 0x0
#define MX8ULP_PAD_PTF26__PTF26 0x0168 0x0000 0x1 0x0
#define MX8ULP_PAD_PTF26__FXIO1_D26 0x0168 0x0888 0x2 0x2
#define MX8ULP_PAD_PTF26__SPDIF_IN2 0x0168 0x0B7C 0x3 0x3
#define MX8ULP_PAD_PTF26__TPM7_CLKIN 0x0168 0x09B0 0x6 0x2
#define MX8ULP_PAD_PTF26__I2S5_TX_BCLK 0x0168 0x0000 0x7 0x0
#define MX8ULP_PAD_PTF26__SDHC2_RESET_B 0x0168 0x0000 0x8 0x0
#define MX8ULP_PAD_PTF26__EPDC0_SDLE 0x0168 0x0000 0xb 0x0
#define MX8ULP_PAD_PTF26__DPI0_HSYNC 0x0168 0x0000 0xc 0x0
#define MX8ULP_PAD_PTF26__WUU1_P14 0x0168 0x0000 0xd 0x0
#define MX8ULP_PAD_PTF27__PTF27 0x016C 0x0000 0x1 0x0
#define MX8ULP_PAD_PTF27__FXIO1_D27 0x016C 0x088C 0x2 0x2
#define MX8ULP_PAD_PTF27__SPDIF_OUT2 0x016C 0x0000 0x3 0x0
#define MX8ULP_PAD_PTF27__TPM7_CH0 0x016C 0x0998 0x6 0x2
#define MX8ULP_PAD_PTF27__I2S5_TX_FS 0x016C 0x0000 0x7 0x0
#define MX8ULP_PAD_PTF27__SDHC2_WP 0x016C 0x0ABC 0x8 0x2
#define MX8ULP_PAD_PTF27__EPDC0_SDCE0 0x016C 0x0000 0xb 0x0
#define MX8ULP_PAD_PTF27__DPI0_DE 0x016C 0x0000 0xc 0x0
#define MX8ULP_PAD_PTF27__WUU1_P15 0x016C 0x0000 0xd 0x0
#define MX8ULP_PAD_PTF28__PTF28 0x0170 0x0000 0x1 0x0
#define MX8ULP_PAD_PTF28__FXIO1_D28 0x0170 0x0890 0x2 0x2
#define MX8ULP_PAD_PTF28__SPDIF_IN3 0x0170 0x0B80 0x3 0x3
#define MX8ULP_PAD_PTF28__TPM7_CH1 0x0170 0x099C 0x6 0x2
#define MX8ULP_PAD_PTF28__I2S5_TXD0 0x0170 0x0000 0x7 0x0
#define MX8ULP_PAD_PTF28__SDHC2_CD 0x0170 0x0A8C 0x8 0x2
#define MX8ULP_PAD_PTF28__EPDC0_SDCLK_B 0x0170 0x0000 0xb 0x0
#define MX8ULP_PAD_PTF28__LP_HV_DBG_MUX_20 0x0170 0x0000 0xf 0x0
#define MX8ULP_PAD_PTF29__PTF29 0x0174 0x0000 0x1 0x0
#define MX8ULP_PAD_PTF29__FXIO1_D29 0x0174 0x0894 0x2 0x2
#define MX8ULP_PAD_PTF29__SPDIF_OUT3 0x0174 0x0000 0x3 0x0
#define MX8ULP_PAD_PTF29__TPM7_CH2 0x0174 0x09A0 0x6 0x2
#define MX8ULP_PAD_PTF29__I2S5_TXD1 0x0174 0x0000 0x7 0x0
#define MX8ULP_PAD_PTF29__SDHC2_VS 0x0174 0x0000 0x8 0x0
#define MX8ULP_PAD_PTF29__EPDC0_SDCE1 0x0174 0x0000 0xb 0x0
#define MX8ULP_PAD_PTF29__WDOG3_RST 0x0174 0x0000 0xd 0x0
#define MX8ULP_PAD_PTF29__LP_HV_DBG_MUX_21 0x0174 0x0000 0xf 0x0
#define MX8ULP_PAD_PTF30__PTF30 0x0178 0x0000 0x1 0x0
#define MX8ULP_PAD_PTF30__FXIO1_D30 0x0178 0x089C 0x2 0x2
#define MX8ULP_PAD_PTF30__TPM7_CH3 0x0178 0x09A4 0x6 0x2
#define MX8ULP_PAD_PTF30__I2S5_TXD2 0x0178 0x0000 0x7 0x0
#define MX8ULP_PAD_PTF30__MQS1_LEFT 0x0178 0x0000 0x8 0x0
#define MX8ULP_PAD_PTF30__EPDC0_SDCE2 0x0178 0x0000 0xb 0x0
#define MX8ULP_PAD_PTF30__WDOG4_RST 0x0178 0x0000 0xd 0x0
#define MX8ULP_PAD_PTF30__LP_HV_DBG_MUX_22 0x0178 0x0000 0xf 0x0
#define MX8ULP_PAD_PTF31__PTF31 0x017C 0x0000 0x1 0x0
#define MX8ULP_PAD_PTF31__FXIO1_D31 0x017C 0x08A0 0x2 0x2
#define MX8ULP_PAD_PTF31__TPM7_CH4 0x017C 0x09A8 0x6 0x2
#define MX8ULP_PAD_PTF31__I2S5_TXD3 0x017C 0x0000 0x7 0x0
#define MX8ULP_PAD_PTF31__MQS1_RIGHT 0x017C 0x0000 0x8 0x0
#define MX8ULP_PAD_PTF31__EPDC0_SDCE3 0x017C 0x0000 0xb 0x0
#define MX8ULP_PAD_PTF31__WDOG5_RST 0x017C 0x0000 0xd 0x0
#define MX8ULP_PAD_PTF31__LP_HV_DBG_MUX_23 0x017C 0x0000 0xf 0x0
#define MX8ULP_PAD_BOOT_MODE0__BOOT_MODE0 0x0400 0x0000 0x0 0x0
#define MX8ULP_PAD_BOOT_MODE1__BOOT_MODE1 0x0404 0x0000 0x0 0x0
#endif /* __DTS_IMX8ULP_PINFUNC_H */

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@@ -0,0 +1,186 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2025 NXP
*/
#include "imx93-u-boot.dtsi"
/ {
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog3>;
bootph-pre-ram;
bootph-some-ram;
};
};
&A55_0 {
clocks = <&clk IMX93_CLK_A55_SEL>;
};
&A55_1 {
clocks = <&clk IMX93_CLK_A55_SEL>;
};
&{/soc@0} {
bootph-all;
bootph-pre-ram;
};
&aips1 {
bootph-pre-ram;
bootph-all;
};
&aips2 {
bootph-pre-ram;
bootph-some-ram;
};
&aips3 {
bootph-pre-ram;
bootph-some-ram;
};
&iomuxc {
bootph-pre-ram;
bootph-some-ram;
};
&reg_usdhc2_vmmc {
u-boot,off-on-delay-us = <20000>;
bootph-pre-ram;
};
&pinctrl_reg_usdhc2_vmmc {
bootph-pre-ram;
};
&pinctrl_uart1 {
bootph-pre-ram;
bootph-some-ram;
};
&pinctrl_usdhc1 {
bootph-pre-ram;
};
&pinctrl_usdhc2_gpio {
bootph-pre-ram;
};
&pinctrl_usdhc2 {
bootph-pre-ram;
};
&gpio1 {
bootph-pre-ram;
bootph-some-ram;
};
&gpio2 {
bootph-pre-ram;
bootph-some-ram;
};
&gpio3 {
bootph-pre-ram;
bootph-some-ram;
};
&gpio4 {
bootph-pre-ram;
bootph-some-ram;
};
&lpuart1 {
bootph-pre-ram;
bootph-some-ram;
};
&usdhc1 {
bootph-pre-ram;
};
&usdhc2 {
bootph-pre-ram;
fsl,signal-voltage-switch-extra-delay-ms = <8>;
};
&lpi2c1 {
bootph-pre-ram;
};
&lpi2c2 {
bootph-pre-ram;
};
&lpi2c3 {
bootph-pre-ram;
};
&{/soc@0/bus@44000000/i2c@44350000/pmic@25} {
bootph-pre-ram;
};
&{/soc@0/bus@44000000/i2c@44350000/pmic@25/regulators} {
bootph-pre-ram;
};
&pinctrl_lpi2c2 {
bootph-pre-ram;
};
&pinctrl_lpi2c3 {
bootph-pre-ram;
};
&fec {
phy-reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>;
phy-reset-duration = <15>;
phy-reset-post-delay = <100>;
};
&ethphy1 {
reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>;
reset-assert-us = <15000>;
reset-deassert-us = <100000>;
};
&usbotg1 {
status = "okay";
extcon = <&ptn5110>;
};
&usbotg2 {
status = "okay";
};
&s4muap {
bootph-pre-ram;
bootph-some-ram;
status = "okay";
};
&clk {
bootph-all;
bootph-pre-ram;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-rates;
/delete-property/ assigned-clock-parents;
};
&osc_32k {
bootph-all;
bootph-pre-ram;
};
&osc_24m {
bootph-all;
bootph-pre-ram;
};
&clk_ext1 {
bootph-all;
bootph-pre-ram;
};

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@@ -0,0 +1,603 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/dts-v1/;
#include <dt-bindings/usb/pd.h>
#include "imx93.dtsi"
/ {
compatible = "fsl,imx93-11x11-frdm", "fsl,imx93";
model = "NXP i.MX93 11X11 FRDM board";
aliases {
mmc0 = &usdhc1; /* EMMC */
mmc1 = &usdhc2; /* uSD */
rtc0 = &pcf2131;
serial0 = &lpuart1;
};
chosen {
stdout-path = &lpuart1;
};
reg_vref_1v8: regulator-adc-vref {
compatible = "regulator-fixed";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vref_1v8";
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
off-on-delay-us = <12000>;
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
pinctrl-names = "default";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "VSD_3V3";
gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usdhc3_vmmc: regulator-usdhc3 {
compatible = "regulator-fixed";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "WLAN_EN";
gpio = <&pcal6524 20 GPIO_ACTIVE_HIGH>;
enable-active-high;
/*
* IW612 wifi chip needs more delay than other wifi chips to complete
* the host interface initialization after power up, otherwise the
* internal state of IW612 may be unstable, resulting in the failure of
* the SDIO3.0 switch voltage.
*/
startup-delay-us = <20000>;
};
reserved-memory {
ranges;
#address-cells = <2>;
#size-cells = <2>;
linux,cma {
compatible = "shared-dma-pool";
alloc-ranges = <0 0x80000000 0 0x30000000>;
reusable;
size = <0 0x10000000>;
linux,cma-default;
};
rsc_table: rsc-table@2021e000 {
reg = <0 0x2021e000 0 0x1000>;
no-map;
};
vdev0vring0: vdev0vring0@a4000000 {
reg = <0 0xa4000000 0 0x8000>;
no-map;
};
vdev0vring1: vdev0vring1@a4008000 {
reg = <0 0xa4008000 0 0x8000>;
no-map;
};
vdev1vring0: vdev1vring0@a4010000 {
reg = <0 0xa4010000 0 0x8000>;
no-map;
};
vdev1vring1: vdev1vring1@a4018000 {
reg = <0 0xa4018000 0 0x8000>;
no-map;
};
vdevbuffer: vdevbuffer@a4020000 {
compatible = "shared-dma-pool";
reg = <0 0xa4020000 0 0x100000>;
no-map;
};
};
usdhc3_pwrseq: usdhc3_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&pcal6524 12 GPIO_ACTIVE_LOW>;
};
};
&adc1 {
vref-supply = <&reg_vref_1v8>;
status = "okay";
};
&eqos {
phy-handle = <&ethphy1>;
phy-mode = "rgmii-id";
pinctrl-0 = <&pinctrl_eqos>;
pinctrl-1 = <&pinctrl_eqos_sleep>;
pinctrl-names = "default", "sleep";
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <5000000>;
ethphy1: ethernet-phy@1 {
reg = <1>;
reset-assert-us = <10000>;
reset-deassert-us = <80000>;
reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>;
};
};
};
&fec {
phy-handle = <&ethphy2>;
phy-mode = "rgmii-id";
pinctrl-0 = <&pinctrl_fec>;
pinctrl-1 = <&pinctrl_fec_sleep>;
pinctrl-names = "default", "sleep";
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <5000000>;
ethphy2: ethernet-phy@2 {
reg = <2>;
eee-broken-1000t;
reset-assert-us = <10000>;
reset-deassert-us = <80000>;
reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>;
};
};
};
&lpi2c2 {
clock-frequency = <400000>;
pinctrl-0 = <&pinctrl_lpi2c2>;
pinctrl-names = "default";
status = "okay";
pcal6524: gpio@22 {
compatible = "nxp,pcal6524";
reg = <0x22>;
#interrupt-cells = <2>;
interrupt-controller;
interrupt-parent = <&gpio3>;
interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
#gpio-cells = <2>;
gpio-controller;
pinctrl-0 = <&pinctrl_pcal6524>;
pinctrl-names = "default";
};
pmic@25 {
compatible = "nxp,pca9451a";
reg = <0x25>;
interrupt-parent = <&pcal6524>;
interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
regulators {
buck1: BUCK1 {
regulator-name = "BUCK1";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <650000>;
regulator-max-microvolt = <2237500>;
regulator-ramp-delay = <3125>;
};
buck2: BUCK2 {
regulator-name = "BUCK2";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <2187500>;
regulator-ramp-delay = <3125>;
};
buck4: BUCK4 {
regulator-name = "BUCK4";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
};
buck5: BUCK5 {
regulator-name = "BUCK5";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
};
buck6: BUCK6 {
regulator-name = "BUCK6";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
};
ldo1: LDO1 {
regulator-name = "LDO1";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1600000>;
regulator-max-microvolt = <3300000>;
};
ldo4: LDO4 {
regulator-name = "LDO4";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
};
ldo5: LDO5 {
regulator-name = "LDO5";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
};
};
eeprom: eeprom@50 {
compatible = "atmel,24c256";
reg = <0x50>;
pagesize = <64>;
};
};
&lpi2c3 {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <400000>;
pinctrl-0 = <&pinctrl_lpi2c3>;
pinctrl-names = "default";
status = "okay";
ptn5110: tcpc@50 {
compatible = "nxp,ptn5110", "tcpci";
reg = <0x50>;
interrupt-parent = <&gpio3>;
interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
typec1_con: connector {
compatible = "usb-c-connector";
data-role = "dual";
label = "USB-C";
op-sink-microwatt = <15000000>;
power-role = "dual";
self-powered;
sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
PDO_VAR(5000, 20000, 3000)>;
source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
try-power-role = "sink";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
typec1_dr_sw: endpoint {
remote-endpoint = <&usb1_drd_sw>;
};
};
};
};
};
pcf2131: rtc@53 {
compatible = "nxp,pcf2131";
reg = <0x53>;
interrupt-parent = <&pcal6524>;
interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
};
};
&lpuart1 { /* console */
pinctrl-0 = <&pinctrl_uart1>;
pinctrl-names = "default";
status = "okay";
};
&usbotg1 {
adp-disable;
disable-over-current;
dr_mode = "otg";
hnp-disable;
srp-disable;
usb-role-switch;
samsung,picophy-dc-vol-level-adjust = <7>;
samsung,picophy-pre-emp-curr-control = <3>;
status = "okay";
port {
usb1_drd_sw: endpoint {
remote-endpoint = <&typec1_dr_sw>;
};
};
};
&usbotg2 {
disable-over-current;
dr_mode = "host";
samsung,picophy-dc-vol-level-adjust = <7>;
samsung,picophy-pre-emp-curr-control = <3>;
status = "okay";
};
&usdhc1 {
bus-width = <8>;
non-removable;
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
status = "okay";
};
&usdhc2 {
bus-width = <4>;
cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
no-mmc;
no-sdio;
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>;
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
vmmc-supply = <&reg_usdhc2_vmmc>;
status = "okay";
};
&wdog3 {
status = "okay";
};
&iomuxc {
pinctrl_eqos: eqosgrp {
fsl,pins = <
MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e
MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e
MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e
MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e
MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e
MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e
MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x58e
MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e
MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e
MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e
MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e
MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e
MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e
MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e
>;
};
pinctrl_eqos_sleep: eqossleepgrp {
fsl,pins = <
MX93_PAD_ENET1_MDC__GPIO4_IO00 0x31e
MX93_PAD_ENET1_MDIO__GPIO4_IO01 0x31e
MX93_PAD_ENET1_RD0__GPIO4_IO10 0x31e
MX93_PAD_ENET1_RD1__GPIO4_IO11 0x31e
MX93_PAD_ENET1_RD2__GPIO4_IO12 0x31e
MX93_PAD_ENET1_RD3__GPIO4_IO13 0x31e
MX93_PAD_ENET1_RXC__GPIO4_IO09 0x31e
MX93_PAD_ENET1_RX_CTL__GPIO4_IO08 0x31e
MX93_PAD_ENET1_TD0__GPIO4_IO05 0x31e
MX93_PAD_ENET1_TD1__GPIO4_IO04 0x31e
MX93_PAD_ENET1_TD2__GPIO4_IO03 0x31e
MX93_PAD_ENET1_TD3__GPIO4_IO02 0x31e
MX93_PAD_ENET1_TXC__GPIO4_IO07 0x31e
MX93_PAD_ENET1_TX_CTL__GPIO4_IO06 0x31e
>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
MX93_PAD_ENET2_MDC__ENET1_MDC 0x57e
MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x57e
MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e
MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e
MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e
MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e
MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x58e
MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e
MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e
MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e
MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e
MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e
MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x58e
MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e
>;
};
pinctrl_fec_sleep: fecsleepgrp {
fsl,pins = <
MX93_PAD_ENET2_MDC__GPIO4_IO14 0x51e
MX93_PAD_ENET2_MDIO__GPIO4_IO15 0x51e
MX93_PAD_ENET2_RD0__GPIO4_IO24 0x51e
MX93_PAD_ENET2_RD1__GPIO4_IO25 0x51e
MX93_PAD_ENET2_RD2__GPIO4_IO26 0x51e
MX93_PAD_ENET2_RD3__GPIO4_IO27 0x51e
MX93_PAD_ENET2_RXC__GPIO4_IO23 0x51e
MX93_PAD_ENET2_RX_CTL__GPIO4_IO22 0x51e
MX93_PAD_ENET2_TD0__GPIO4_IO19 0x51e
MX93_PAD_ENET2_TD1__GPIO4_IO18 0x51e
MX93_PAD_ENET2_TD2__GPIO4_IO17 0x51e
MX93_PAD_ENET2_TD3__GPIO4_IO16 0x51e
MX93_PAD_ENET2_TXC__GPIO4_IO21 0x51e
MX93_PAD_ENET2_TX_CTL__GPIO4_IO20 0x51e
>;
};
pinctrl_flexcan2: flexcan2grp {
fsl,pins = <
MX93_PAD_GPIO_IO25__CAN2_TX 0x139e
MX93_PAD_GPIO_IO27__CAN2_RX 0x139e
>;
};
pinctrl_lpi2c2: lpi2c2grp {
fsl,pins = <
MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e
MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e
>;
};
pinctrl_lpi2c3: lpi2c3grp {
fsl,pins = <
MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e
MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e
>;
};
pinctrl_pcal6524: pcal6524grp {
fsl,pins = <
MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e
>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX93_PAD_UART1_RXD__LPUART1_RX 0x31e
MX93_PAD_UART1_TXD__LPUART1_TX 0x31e
>;
};
/* need to config the SION for data and cmd pad, refer to ERR052021 */
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX93_PAD_SD1_CLK__USDHC1_CLK 0x1582
MX93_PAD_SD1_CMD__USDHC1_CMD 0x40001382
MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x40001382
MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x40001382
MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x40001382
MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x40001382
MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x40001382
MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x40001382
MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x40001382
MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x40001382
MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x1582
>;
};
/* need to config the SION for data and cmd pad, refer to ERR052021 */
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
MX93_PAD_SD1_CLK__USDHC1_CLK 0x158e
MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000138e
MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e
MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000138e
MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000138e
MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000138e
MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000138e
MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000138e
MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000138e
MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000138e
MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x158e
>;
};
/* need to config the SION for data and cmd pad, refer to ERR052021 */
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe
MX93_PAD_SD1_CMD__USDHC1_CMD 0x400013fe
MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x400013fe
MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013fe
MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013fe
MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013fe
MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013fe
MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013fe
MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013fe
MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013fe
MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e
>;
};
pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleepgrp {
fsl,pins = <
MX93_PAD_SD2_CD_B__GPIO3_IO00 0x51e
>;
};
/* need to config the SION for data and cmd pad, refer to ERR052021 */
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX93_PAD_SD2_CLK__USDHC2_CLK 0x1582
MX93_PAD_SD2_CMD__USDHC2_CMD 0x40001382
MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x40001382
MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x40001382
MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x40001382
MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x40001382
MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
/* need to config the SION for data and cmd pad, refer to ERR052021 */
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX93_PAD_SD2_CLK__USDHC2_CLK 0x158e
MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000138e
MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e
MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e
MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e
MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e
MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
/* need to config the SION for data and cmd pad, refer to ERR052021 */
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe
MX93_PAD_SD2_CMD__USDHC2_CMD 0x400013fe
MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x400013fe
MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x400013fe
MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x400013fe
MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x400013fe
MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
pinctrl_usdhc2_sleep: usdhc2-sleepgrp {
fsl,pins = <
MX93_PAD_SD2_CLK__GPIO3_IO01 0x51e
MX93_PAD_SD2_CMD__GPIO3_IO02 0x51e
MX93_PAD_SD2_DATA0__GPIO3_IO03 0x51e
MX93_PAD_SD2_DATA1__GPIO3_IO04 0x51e
MX93_PAD_SD2_DATA2__GPIO3_IO05 0x51e
MX93_PAD_SD2_DATA3__GPIO3_IO06 0x51e
MX93_PAD_SD2_VSELECT__GPIO3_IO19 0x51e
>;
};
};

View File

@@ -1,623 +0,0 @@
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
* Copyright 2022 NXP
*/
#ifndef __DTS_IMX93_PINFUNC_H
#define __DTS_IMX93_PINFUNC_H
/*
* The pin function ID is a tuple of
* <mux_reg conf_reg input_reg mux_mode input_val>
*/
#define MX93_PAD_DAP_TDI__JTAG_MUX_TDI 0x0000 0x01B0 0x03D8 0x0 0x0
#define MX93_PAD_DAP_TDI__MQS2_LEFT 0x0000 0x01B0 0x0000 0x1 0x0
#define MX93_PAD_DAP_TDI__CAN2_TX 0x0000 0x01B0 0x0000 0x3 0x0
#define MX93_PAD_DAP_TDI__FLEXIO2_FLEXIO30 0x0000 0x01B0 0x0000 0x4 0x0
#define MX93_PAD_DAP_TDI__GPIO3_IO28 0x0000 0x01B0 0x0000 0x5 0x0
#define MX93_PAD_DAP_TDI__LPUART5_RX 0x0000 0x01B0 0x0430 0x6 0x0
#define MX93_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x01B4 0x03DC 0x0 0x0
#define MX93_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31 0x0004 0x01B4 0x0000 0x4 0x0
#define MX93_PAD_DAP_TMS_SWDIO__GPIO3_IO29 0x0004 0x01B4 0x0000 0x5 0x0
#define MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x0004 0x01B4 0x0000 0x6 0x0
#define MX93_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK 0x0008 0x01B8 0x03D4 0x0 0x0
#define MX93_PAD_DAP_TCLK_SWCLK__FLEXIO1_FLEXIO30 0x0008 0x01B8 0x0000 0x4 0x0
#define MX93_PAD_DAP_TCLK_SWCLK__GPIO3_IO30 0x0008 0x01B8 0x0000 0x5 0x0
#define MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x0008 0x01B8 0x042C 0x6 0x0
#define MX93_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO 0x000C 0x01BC 0x0000 0x0 0x0
#define MX93_PAD_DAP_TDO_TRACESWO__MQS2_RIGHT 0x000C 0x01BC 0x0000 0x1 0x0
#define MX93_PAD_DAP_TDO_TRACESWO__CAN2_RX 0x000C 0x01BC 0x0364 0x3 0x0
#define MX93_PAD_DAP_TDO_TRACESWO__FLEXIO1_FLEXIO31 0x000C 0x01BC 0x0000 0x4 0x0
#define MX93_PAD_DAP_TDO_TRACESWO__GPIO3_IO31 0x000C 0x01BC 0x0000 0x5 0x0
#define MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x000C 0x01BC 0x0434 0x6 0x0
#define MX93_PAD_GPIO_IO00__GPIO2_IO00 0x0010 0x01C0 0x0000 0x0 0x0
#define MX93_PAD_GPIO_IO00__LPI2C3_SDA 0x0010 0x01C0 0x03E4 0x11 0x0
#define MX93_PAD_GPIO_IO00__MEDIAMIX_CAM_CLK 0x0010 0x01C0 0x0000 0x2 0x0
#define MX93_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x0010 0x01C0 0x0000 0x3 0x0
#define MX93_PAD_GPIO_IO00__LPSPI6_PCS0 0x0010 0x01C0 0x0000 0x4 0x0
#define MX93_PAD_GPIO_IO00__LPUART5_TX 0x0010 0x01C0 0x0434 0x5 0x1
#define MX93_PAD_GPIO_IO00__LPI2C5_SDA 0x0010 0x01C0 0x03EC 0x16 0x0
#define MX93_PAD_GPIO_IO00__FLEXIO1_FLEXIO00 0x0010 0x01C0 0x036C 0x7 0x0
#define MX93_PAD_GPIO_IO01__GPIO2_IO01 0x0014 0x01C4 0x0000 0x0 0x0
#define MX93_PAD_GPIO_IO01__LPI2C3_SCL 0x0014 0x01C4 0x03E0 0x11 0x0
#define MX93_PAD_GPIO_IO01__MEDIAMIX_CAM_DATA00 0x0014 0x01C4 0x0000 0x2 0x0
#define MX93_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x0014 0x01C4 0x0000 0x3 0x0
#define MX93_PAD_GPIO_IO01__LPSPI6_SIN 0x0014 0x01C4 0x0000 0x4 0x0
#define MX93_PAD_GPIO_IO01__LPUART5_RX 0x0014 0x01C4 0x0430 0x5 0x1
#define MX93_PAD_GPIO_IO01__LPI2C5_SCL 0x0014 0x01C4 0x03E8 0x16 0x0
#define MX93_PAD_GPIO_IO01__FLEXIO1_FLEXIO01 0x0014 0x01C4 0x0370 0x7 0x0
#define MX93_PAD_GPIO_IO02__GPIO2_IO02 0x0018 0x01C8 0x0000 0x0 0x0
#define MX93_PAD_GPIO_IO02__LPI2C4_SDA 0x0018 0x01C8 0x0000 0x11 0x0
#define MX93_PAD_GPIO_IO02__MEDIAMIX_CAM_VSYNC 0x0018 0x01C8 0x0000 0x2 0x0
#define MX93_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x0018 0x01C8 0x0000 0x3 0x0
#define MX93_PAD_GPIO_IO02__LPSPI6_SOUT 0x0018 0x01C8 0x0000 0x4 0x0
#define MX93_PAD_GPIO_IO02__LPUART5_CTS_B 0x0018 0x01C8 0x042C 0x5 0x1
#define MX93_PAD_GPIO_IO02__LPI2C6_SDA 0x0018 0x01C8 0x03F4 0x16 0x0
#define MX93_PAD_GPIO_IO02__FLEXIO1_FLEXIO02 0x0018 0x01C8 0x0374 0x7 0x0
#define MX93_PAD_GPIO_IO03__GPIO2_IO03 0x001C 0x01CC 0x0000 0x0 0x0
#define MX93_PAD_GPIO_IO03__LPI2C4_SCL 0x001C 0x01CC 0x0000 0x11 0x0
#define MX93_PAD_GPIO_IO03__MEDIAMIX_CAM_HSYNC 0x001C 0x01CC 0x0000 0x2 0x0
#define MX93_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC 0x001C 0x01CC 0x0000 0x3 0x0
#define MX93_PAD_GPIO_IO03__LPSPI6_SCK 0x001C 0x01CC 0x0000 0x4 0x0
#define MX93_PAD_GPIO_IO03__LPUART5_RTS_B 0x001C 0x01CC 0x0000 0x5 0x0
#define MX93_PAD_GPIO_IO03__LPI2C6_SCL 0x001C 0x01CC 0x03F0 0x16 0x0
#define MX93_PAD_GPIO_IO03__FLEXIO1_FLEXIO03 0x001C 0x01CC 0x0378 0x7 0x0
#define MX93_PAD_GPIO_IO04__GPIO2_IO04 0x0020 0x01D0 0x0000 0x0 0x0
#define MX93_PAD_GPIO_IO04__TPM3_CH0 0x0020 0x01D0 0x0000 0x1 0x0
#define MX93_PAD_GPIO_IO04__PDM_CLK 0x0020 0x01D0 0x0000 0x2 0x0
#define MX93_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA00 0x0020 0x01D0 0x0000 0x3 0x0
#define MX93_PAD_GPIO_IO04__LPSPI7_PCS0 0x0020 0x01D0 0x0000 0x4 0x0
#define MX93_PAD_GPIO_IO04__LPUART6_TX 0x0020 0x01D0 0x0000 0x5 0x0
#define MX93_PAD_GPIO_IO04__LPI2C6_SDA 0x0020 0x01D0 0x03F4 0x16 0x1
#define MX93_PAD_GPIO_IO04__FLEXIO1_FLEXIO04 0x0020 0x01D0 0x037C 0x7 0x0
#define MX93_PAD_GPIO_IO05__GPIO2_IO05 0x0024 0x01D4 0x0000 0x0 0x0
#define MX93_PAD_GPIO_IO05__TPM4_CH0 0x0024 0x01D4 0x0000 0x1 0x0
#define MX93_PAD_GPIO_IO05__PDM_BIT_STREAM00 0x0024 0x01D4 0x0438 0x2 0x0
#define MX93_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA01 0x0024 0x01D4 0x0000 0x3 0x0
#define MX93_PAD_GPIO_IO05__LPSPI7_SIN 0x0024 0x01D4 0x0000 0x4 0x0
#define MX93_PAD_GPIO_IO05__LPUART6_RX 0x0024 0x01D4 0x0000 0x5 0x0
#define MX93_PAD_GPIO_IO05__LPI2C6_SCL 0x0024 0x01D4 0x03F0 0x16 0x1
#define MX93_PAD_GPIO_IO05__FLEXIO1_FLEXIO05 0x0024 0x01D4 0x0380 0x7 0x0
#define MX93_PAD_GPIO_IO06__GPIO2_IO06 0x0028 0x01D8 0x0000 0x0 0x0
#define MX93_PAD_GPIO_IO06__TPM5_CH0 0x0028 0x01D8 0x0000 0x1 0x0
#define MX93_PAD_GPIO_IO06__PDM_BIT_STREAM01 0x0028 0x01D8 0x043C 0x2 0x0
#define MX93_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA02 0x0028 0x01D8 0x0000 0x3 0x0
#define MX93_PAD_GPIO_IO06__LPSPI7_SOUT 0x0028 0x01D8 0x0000 0x4 0x0
#define MX93_PAD_GPIO_IO06__LPUART6_CTS_B 0x0028 0x01D8 0x0000 0x5 0x0
#define MX93_PAD_GPIO_IO06__LPI2C7_SDA 0x0028 0x01D8 0x03FC 0x16 0x0
#define MX93_PAD_GPIO_IO06__FLEXIO1_FLEXIO06 0x0028 0x01D8 0x0384 0x7 0x0
#define MX93_PAD_GPIO_IO07__GPIO2_IO07 0x002C 0x01DC 0x0000 0x0 0x0
#define MX93_PAD_GPIO_IO07__LPSPI3_PCS1 0x002C 0x01DC 0x0000 0x1 0x0
#define MX93_PAD_GPIO_IO07__MEDIAMIX_CAM_DATA01 0x002C 0x01DC 0x0000 0x2 0x0
#define MX93_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA03 0x002C 0x01DC 0x0000 0x3 0x0
#define MX93_PAD_GPIO_IO07__LPSPI7_SCK 0x002C 0x01DC 0x0000 0x4 0x0
#define MX93_PAD_GPIO_IO07__LPUART6_RTS_B 0x002C 0x01DC 0x0000 0x5 0x0
#define MX93_PAD_GPIO_IO07__LPI2C7_SCL 0x002C 0x01DC 0x03F8 0x16 0x0
#define MX93_PAD_GPIO_IO07__FLEXIO1_FLEXIO07 0x002C 0x01DC 0x0388 0x7 0x0
#define MX93_PAD_GPIO_IO08__GPIO2_IO08 0x0030 0x01E0 0x0000 0x0 0x0
#define MX93_PAD_GPIO_IO08__LPSPI3_PCS0 0x0030 0x01E0 0x0000 0x1 0x0
#define MX93_PAD_GPIO_IO08__MEDIAMIX_CAM_DATA02 0x0030 0x01E0 0x0000 0x2 0x0
#define MX93_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA04 0x0030 0x01E0 0x0000 0x3 0x0
#define MX93_PAD_GPIO_IO08__TPM6_CH0 0x0030 0x01E0 0x0000 0x4 0x0
#define MX93_PAD_GPIO_IO08__LPUART7_TX 0x0030 0x01E0 0x0000 0x5 0x0
#define MX93_PAD_GPIO_IO08__LPI2C7_SDA 0x0030 0x01E0 0x03FC 0x16 0x1
#define MX93_PAD_GPIO_IO08__FLEXIO1_FLEXIO08 0x0030 0x01E0 0x038C 0x7 0x0
#define MX93_PAD_GPIO_IO09__GPIO2_IO09 0x0034 0x01E4 0x0000 0x0 0x0
#define MX93_PAD_GPIO_IO09__LPSPI3_SIN 0x0034 0x01E4 0x0000 0x1 0x0
#define MX93_PAD_GPIO_IO09__MEDIAMIX_CAM_DATA03 0x0034 0x01E4 0x0000 0x2 0x0
#define MX93_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA05 0x0034 0x01E4 0x0000 0x3 0x0
#define MX93_PAD_GPIO_IO09__TPM3_EXTCLK 0x0034 0x01E4 0x0000 0x4 0x0
#define MX93_PAD_GPIO_IO09__LPUART7_RX 0x0034 0x01E4 0x0000 0x5 0x0
#define MX93_PAD_GPIO_IO09__LPI2C7_SCL 0x0034 0x01E4 0x03F8 0x16 0x1
#define MX93_PAD_GPIO_IO09__FLEXIO1_FLEXIO09 0x0034 0x01E4 0x0390 0x7 0x0
#define MX93_PAD_GPIO_IO10__GPIO2_IO10 0x0038 0x01E8 0x0000 0x0 0x0
#define MX93_PAD_GPIO_IO10__LPSPI3_SOUT 0x0038 0x01E8 0x0000 0x1 0x0
#define MX93_PAD_GPIO_IO10__MEDIAMIX_CAM_DATA04 0x0038 0x01E8 0x0000 0x2 0x0
#define MX93_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA06 0x0038 0x01E8 0x0000 0x3 0x0
#define MX93_PAD_GPIO_IO10__TPM4_EXTCLK 0x0038 0x01E8 0x0000 0x4 0x0
#define MX93_PAD_GPIO_IO10__LPUART7_CTS_B 0x0038 0x01E8 0x0000 0x5 0x0
#define MX93_PAD_GPIO_IO10__LPI2C8_SDA 0x0038 0x01E8 0x0404 0x16 0x0
#define MX93_PAD_GPIO_IO10__FLEXIO1_FLEXIO10 0x0038 0x01E8 0x0394 0x7 0x0
#define MX93_PAD_GPIO_IO11__GPIO2_IO11 0x003C 0x01EC 0x0000 0x0 0x0
#define MX93_PAD_GPIO_IO11__LPSPI3_SCK 0x003C 0x01EC 0x0000 0x1 0x0
#define MX93_PAD_GPIO_IO11__MEDIAMIX_CAM_DATA05 0x003C 0x01EC 0x0000 0x2 0x0
#define MX93_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA07 0x003C 0x01EC 0x0000 0x3 0x0
#define MX93_PAD_GPIO_IO11__TPM5_EXTCLK 0x003C 0x01EC 0x0000 0x4 0x0
#define MX93_PAD_GPIO_IO11__LPUART7_RTS_B 0x003C 0x01EC 0x0000 0x5 0x0
#define MX93_PAD_GPIO_IO11__LPI2C8_SCL 0x003C 0x01EC 0x0400 0x16 0x0
#define MX93_PAD_GPIO_IO11__FLEXIO1_FLEXIO11 0x003C 0x01EC 0x0398 0x7 0x0
#define MX93_PAD_GPIO_IO12__GPIO2_IO12 0x0040 0x01F0 0x0000 0x0 0x0
#define MX93_PAD_GPIO_IO12__TPM3_CH2 0x0040 0x01F0 0x0000 0x1 0x0
#define MX93_PAD_GPIO_IO12__PDM_BIT_STREAM02 0x0040 0x01F0 0x0440 0x2 0x0
#define MX93_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA08 0x0040 0x01F0 0x0000 0x3 0x0
#define MX93_PAD_GPIO_IO12__LPSPI8_PCS0 0x0040 0x01F0 0x0000 0x4 0x0
#define MX93_PAD_GPIO_IO12__LPUART8_TX 0x0040 0x01F0 0x0000 0x5 0x0
#define MX93_PAD_GPIO_IO12__LPI2C8_SDA 0x0040 0x01F0 0x0404 0x16 0x1
#define MX93_PAD_GPIO_IO12__SAI3_RX_SYNC 0x0040 0x01F0 0x0450 0x7 0x0
#define MX93_PAD_GPIO_IO13__GPIO2_IO13 0x0044 0x01F4 0x0000 0x0 0x0
#define MX93_PAD_GPIO_IO13__TPM4_CH2 0x0044 0x01F4 0x0000 0x1 0x0
#define MX93_PAD_GPIO_IO13__PDM_BIT_STREAM03 0x0044 0x01F4 0x0444 0x2 0x0
#define MX93_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA09 0x0044 0x01F4 0x0000 0x3 0x0
#define MX93_PAD_GPIO_IO13__LPSPI8_SIN 0x0044 0x01F4 0x0000 0x4 0x0
#define MX93_PAD_GPIO_IO13__LPUART8_RX 0x0044 0x01F4 0x0000 0x5 0x0
#define MX93_PAD_GPIO_IO13__LPI2C8_SCL 0x0044 0x01F4 0x0400 0x16 0x1
#define MX93_PAD_GPIO_IO13__FLEXIO1_FLEXIO13 0x0044 0x01F4 0x039C 0x7 0x0
#define MX93_PAD_GPIO_IO14__GPIO2_IO14 0x0048 0x01F8 0x0000 0x0 0x0
#define MX93_PAD_GPIO_IO14__LPUART3_TX 0x0048 0x01F8 0x041C 0x1 0x0
#define MX93_PAD_GPIO_IO14__MEDIAMIX_CAM_DATA06 0x0048 0x01F8 0x0000 0x2 0x0
#define MX93_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 0x0048 0x01F8 0x0000 0x3 0x0
#define MX93_PAD_GPIO_IO14__LPSPI8_SOUT 0x0048 0x01F8 0x0000 0x4 0x0
#define MX93_PAD_GPIO_IO14__LPUART8_CTS_B 0x0048 0x01F8 0x0000 0x5 0x0
#define MX93_PAD_GPIO_IO14__LPUART4_TX 0x0048 0x01F8 0x0428 0x6 0x0
#define MX93_PAD_GPIO_IO14__FLEXIO1_FLEXIO14 0x0048 0x01F8 0x03A0 0x7 0x0
#define MX93_PAD_GPIO_IO15__GPIO2_IO15 0x004C 0x01FC 0x0000 0x0 0x0
#define MX93_PAD_GPIO_IO15__LPUART3_RX 0x004C 0x01FC 0x0418 0x1 0x0
#define MX93_PAD_GPIO_IO15__MEDIAMIX_CAM_DATA07 0x004C 0x01FC 0x0000 0x2 0x0
#define MX93_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 0x004C 0x01FC 0x0000 0x3 0x0
#define MX93_PAD_GPIO_IO15__LPSPI8_SCK 0x004C 0x01FC 0x0000 0x4 0x0
#define MX93_PAD_GPIO_IO15__LPUART8_RTS_B 0x004C 0x01FC 0x0000 0x5 0x0
#define MX93_PAD_GPIO_IO15__LPUART4_RX 0x004C 0x01FC 0x0424 0x6 0x0
#define MX93_PAD_GPIO_IO15__FLEXIO1_FLEXIO15 0x004C 0x01FC 0x03A4 0x7 0x0
#define MX93_PAD_GPIO_IO16__GPIO2_IO16 0x0050 0x0200 0x0000 0x0 0x0
#define MX93_PAD_GPIO_IO16__SAI3_TX_BCLK 0x0050 0x0200 0x0000 0x1 0x0
#define MX93_PAD_GPIO_IO16__PDM_BIT_STREAM02 0x0050 0x0200 0x0440 0x2 0x1
#define MX93_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 0x0050 0x0200 0x0000 0x3 0x0
#define MX93_PAD_GPIO_IO16__LPUART3_CTS_B 0x0050 0x0200 0x0414 0x4 0x0
#define MX93_PAD_GPIO_IO16__LPSPI4_PCS2 0x0050 0x0200 0x0000 0x5 0x0
#define MX93_PAD_GPIO_IO16__LPUART4_CTS_B 0x0050 0x0200 0x0420 0x6 0x0
#define MX93_PAD_GPIO_IO16__FLEXIO1_FLEXIO16 0x0050 0x0200 0x03A8 0x7 0x0
#define MX93_PAD_GPIO_IO17__GPIO2_IO17 0x0054 0x0204 0x0000 0x0 0x0
#define MX93_PAD_GPIO_IO17__SAI3_MCLK 0x0054 0x0204 0x0000 0x1 0x0
#define MX93_PAD_GPIO_IO17__MEDIAMIX_CAM_DATA08 0x0054 0x0204 0x0000 0x2 0x0
#define MX93_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 0x0054 0x0204 0x0000 0x3 0x0
#define MX93_PAD_GPIO_IO17__LPUART3_RTS_B 0x0054 0x0204 0x0000 0x4 0x0
#define MX93_PAD_GPIO_IO17__LPSPI4_PCS1 0x0054 0x0204 0x0000 0x5 0x0
#define MX93_PAD_GPIO_IO17__LPUART4_RTS_B 0x0054 0x0204 0x0000 0x6 0x0
#define MX93_PAD_GPIO_IO17__FLEXIO1_FLEXIO17 0x0054 0x0204 0x03AC 0x7 0x0
#define MX93_PAD_GPIO_IO18__GPIO2_IO18 0x0058 0x0208 0x0000 0x0 0x0
#define MX93_PAD_GPIO_IO18__SAI3_RX_BCLK 0x0058 0x0208 0x044C 0x1 0x0
#define MX93_PAD_GPIO_IO18__MEDIAMIX_CAM_DATA09 0x0058 0x0208 0x0000 0x2 0x0
#define MX93_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 0x0058 0x0208 0x0000 0x3 0x0
#define MX93_PAD_GPIO_IO18__LPSPI5_PCS0 0x0058 0x0208 0x0000 0x4 0x0
#define MX93_PAD_GPIO_IO18__LPSPI4_PCS0 0x0058 0x0208 0x0000 0x5 0x0
#define MX93_PAD_GPIO_IO18__TPM5_CH2 0x0058 0x0208 0x0000 0x6 0x0
#define MX93_PAD_GPIO_IO18__FLEXIO1_FLEXIO18 0x0058 0x0208 0x03B0 0x7 0x0
#define MX93_PAD_GPIO_IO19__GPIO2_IO19 0x005C 0x020C 0x0000 0x0 0x0
#define MX93_PAD_GPIO_IO19__SAI3_RX_SYNC 0x005C 0x020C 0x0450 0x1 0x1
#define MX93_PAD_GPIO_IO19__PDM_BIT_STREAM03 0x005C 0x020C 0x0444 0x2 0x1
#define MX93_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 0x005C 0x020C 0x0000 0x3 0x0
#define MX93_PAD_GPIO_IO19__LPSPI5_SIN 0x005C 0x020C 0x0000 0x4 0x0
#define MX93_PAD_GPIO_IO19__LPSPI4_SIN 0x005C 0x020C 0x0000 0x5 0x0
#define MX93_PAD_GPIO_IO19__TPM6_CH2 0x005C 0x020C 0x0000 0x6 0x0
#define MX93_PAD_GPIO_IO19__SAI3_TX_DATA00 0x005C 0x020C 0x0000 0x7 0x0
#define MX93_PAD_GPIO_IO20__GPIO2_IO20 0x0060 0x0210 0x0000 0x0 0x0
#define MX93_PAD_GPIO_IO20__SAI3_RX_DATA00 0x0060 0x0210 0x0000 0x1 0x0
#define MX93_PAD_GPIO_IO20__PDM_BIT_STREAM00 0x0060 0x0210 0x0438 0x2 0x1
#define MX93_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 0x0060 0x0210 0x0000 0x3 0x0
#define MX93_PAD_GPIO_IO20__LPSPI5_SOUT 0x0060 0x0210 0x0000 0x4 0x0
#define MX93_PAD_GPIO_IO20__LPSPI4_SOUT 0x0060 0x0210 0x0000 0x5 0x0
#define MX93_PAD_GPIO_IO20__TPM3_CH1 0x0060 0x0210 0x0000 0x6 0x0
#define MX93_PAD_GPIO_IO20__FLEXIO1_FLEXIO20 0x0060 0x0210 0x03B4 0x7 0x0
#define MX93_PAD_GPIO_IO21__GPIO2_IO21 0x0064 0x0214 0x0000 0x0 0x0
#define MX93_PAD_GPIO_IO21__SAI3_TX_DATA00 0x0064 0x0214 0x0000 0x1 0x0
#define MX93_PAD_GPIO_IO21__PDM_CLK 0x0064 0x0214 0x0000 0x2 0x0
#define MX93_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 0x0064 0x0214 0x0000 0x3 0x0
#define MX93_PAD_GPIO_IO21__LPSPI5_SCK 0x0064 0x0214 0x0000 0x4 0x0
#define MX93_PAD_GPIO_IO21__LPSPI4_SCK 0x0064 0x0214 0x0000 0x5 0x0
#define MX93_PAD_GPIO_IO21__TPM4_CH1 0x0064 0x0214 0x0000 0x6 0x0
#define MX93_PAD_GPIO_IO21__SAI3_RX_BCLK 0x0064 0x0214 0x044C 0x7 0x1
#define MX93_PAD_GPIO_IO22__GPIO2_IO22 0x0068 0x0218 0x0000 0x0 0x0
#define MX93_PAD_GPIO_IO22__USDHC3_CLK 0x0068 0x0218 0x0458 0x1 0x0
#define MX93_PAD_GPIO_IO22__SPDIF_IN 0x0068 0x0218 0x0454 0x2 0x0
#define MX93_PAD_GPIO_IO22__MEDIAMIX_DISP_DATA18 0x0068 0x0218 0x0000 0x3 0x0
#define MX93_PAD_GPIO_IO22__TPM5_CH1 0x0068 0x0218 0x0000 0x4 0x0
#define MX93_PAD_GPIO_IO22__TPM6_EXTCLK 0x0068 0x0218 0x0000 0x5 0x0
#define MX93_PAD_GPIO_IO22__LPI2C5_SDA 0x0068 0x0218 0x03EC 0x16 0x1
#define MX93_PAD_GPIO_IO22__FLEXIO1_FLEXIO22 0x0068 0x0218 0x03B8 0x7 0x0
#define MX93_PAD_GPIO_IO23__GPIO2_IO23 0x006C 0x021C 0x0000 0x0 0x0
#define MX93_PAD_GPIO_IO23__USDHC3_CMD 0x006C 0x021C 0x045C 0x1 0x0
#define MX93_PAD_GPIO_IO23__SPDIF_OUT 0x006C 0x021C 0x0000 0x2 0x0
#define MX93_PAD_GPIO_IO23__MEDIAMIX_DISP_DATA19 0x006C 0x021C 0x0000 0x3 0x0
#define MX93_PAD_GPIO_IO23__TPM6_CH1 0x006C 0x021C 0x0000 0x4 0x0
#define MX93_PAD_GPIO_IO23__LPI2C5_SCL 0x006C 0x021C 0x03E8 0x16 0x1
#define MX93_PAD_GPIO_IO23__FLEXIO1_FLEXIO23 0x006C 0x021C 0x03BC 0x7 0x0
#define MX93_PAD_GPIO_IO24__GPIO2_IO24 0x0070 0x0220 0x0000 0x0 0x0
#define MX93_PAD_GPIO_IO24__USDHC3_DATA0 0x0070 0x0220 0x0460 0x1 0x0
#define MX93_PAD_GPIO_IO24__MEDIAMIX_DISP_DATA20 0x0070 0x0220 0x0000 0x3 0x0
#define MX93_PAD_GPIO_IO24__TPM3_CH3 0x0070 0x0220 0x0000 0x4 0x0
#define MX93_PAD_GPIO_IO24__JTAG_MUX_TDO 0x0070 0x0220 0x0000 0x5 0x0
#define MX93_PAD_GPIO_IO24__LPSPI6_PCS1 0x0070 0x0220 0x0000 0x6 0x0
#define MX93_PAD_GPIO_IO24__FLEXIO1_FLEXIO24 0x0070 0x0220 0x03C0 0x7 0x0
#define MX93_PAD_GPIO_IO25__GPIO2_IO25 0x0074 0x0224 0x0000 0x0 0x0
#define MX93_PAD_GPIO_IO25__USDHC3_DATA1 0x0074 0x0224 0x0464 0x1 0x0
#define MX93_PAD_GPIO_IO25__CAN2_TX 0x0074 0x0224 0x0000 0x2 0x0
#define MX93_PAD_GPIO_IO25__MEDIAMIX_DISP_DATA21 0x0074 0x0224 0x0000 0x3 0x0
#define MX93_PAD_GPIO_IO25__TPM4_CH3 0x0074 0x0224 0x0000 0x4 0x0
#define MX93_PAD_GPIO_IO25__JTAG_MUX_TCK 0x0074 0x0224 0x03D4 0x5 0x1
#define MX93_PAD_GPIO_IO25__LPSPI7_PCS1 0x0074 0x0224 0x0000 0x6 0x0
#define MX93_PAD_GPIO_IO25__FLEXIO1_FLEXIO25 0x0074 0x0224 0x03C4 0x7 0x0
#define MX93_PAD_GPIO_IO26__GPIO2_IO26 0x0078 0x0228 0x0000 0x0 0x0
#define MX93_PAD_GPIO_IO26__USDHC3_DATA2 0x0078 0x0228 0x0468 0x1 0x0
#define MX93_PAD_GPIO_IO26__PDM_BIT_STREAM01 0x0078 0x0228 0x043C 0x2 0x1
#define MX93_PAD_GPIO_IO26__MEDIAMIX_DISP_DATA22 0x0078 0x0228 0x0000 0x3 0x0
#define MX93_PAD_GPIO_IO26__TPM5_CH3 0x0078 0x0228 0x0000 0x4 0x0
#define MX93_PAD_GPIO_IO26__JTAG_MUX_TDI 0x0078 0x0228 0x03D8 0x5 0x1
#define MX93_PAD_GPIO_IO26__LPSPI8_PCS1 0x0078 0x0228 0x0000 0x6 0x0
#define MX93_PAD_GPIO_IO26__SAI3_TX_SYNC 0x0078 0x0228 0x0000 0x7 0x0
#define MX93_PAD_GPIO_IO27__GPIO2_IO27 0x007C 0x022C 0x0000 0x0 0x0
#define MX93_PAD_GPIO_IO27__USDHC3_DATA3 0x007C 0x022C 0x046C 0x1 0x0
#define MX93_PAD_GPIO_IO27__CAN2_RX 0x007C 0x022C 0x0364 0x2 0x1
#define MX93_PAD_GPIO_IO27__MEDIAMIX_DISP_DATA23 0x007C 0x022C 0x0000 0x3 0x0
#define MX93_PAD_GPIO_IO27__TPM6_CH3 0x007C 0x022C 0x0000 0x4 0x0
#define MX93_PAD_GPIO_IO27__JTAG_MUX_TMS 0x007C 0x022C 0x03DC 0x5 0x1
#define MX93_PAD_GPIO_IO27__LPSPI5_PCS1 0x007C 0x022C 0x0000 0x6 0x0
#define MX93_PAD_GPIO_IO27__FLEXIO1_FLEXIO27 0x007C 0x022C 0x03C8 0x7 0x0
#define MX93_PAD_GPIO_IO28__GPIO2_IO28 0x0080 0x0230 0x0000 0x0 0x0
#define MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x0080 0x0230 0x03E4 0x11 0x1
#define MX93_PAD_GPIO_IO28__FLEXIO1_FLEXIO28 0x0080 0x0230 0x0000 0x7 0x0
#define MX93_PAD_GPIO_IO29__GPIO2_IO29 0x0084 0x0234 0x0000 0x0 0x0
#define MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x0084 0x0234 0x03E0 0x11 0x1
#define MX93_PAD_GPIO_IO29__FLEXIO1_FLEXIO29 0x0084 0x0234 0x0000 0x7 0x0
#define MX93_PAD_CCM_CLKO1__CCMSRCGPCMIX_CLKO1 0x0088 0x0238 0x0000 0x0 0x0
#define MX93_PAD_CCM_CLKO1__FLEXIO1_FLEXIO26 0x0088 0x0238 0x0000 0x4 0x0
#define MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x0088 0x0238 0x0000 0x5 0x0
#define MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x008C 0x023C 0x0000 0x5 0x0
#define MX93_PAD_CCM_CLKO2__CCMSRCGPCMIX_CLKO2 0x008C 0x023C 0x0000 0x0 0x0
#define MX93_PAD_CCM_CLKO2__FLEXIO1_FLEXIO27 0x008C 0x023C 0x03C8 0x4 0x1
#define MX93_PAD_CCM_CLKO3__CCMSRCGPCMIX_CLKO3 0x0090 0x0240 0x0000 0x0 0x0
#define MX93_PAD_CCM_CLKO3__FLEXIO2_FLEXIO28 0x0090 0x0240 0x0000 0x4 0x0
#define MX93_PAD_CCM_CLKO3__GPIO4_IO28 0x0090 0x0240 0x0000 0x5 0x0
#define MX93_PAD_CCM_CLKO4__CCMSRCGPCMIX_CLKO4 0x0094 0x0244 0x0000 0x0 0x0
#define MX93_PAD_CCM_CLKO4__FLEXIO2_FLEXIO29 0x0094 0x0244 0x0000 0x4 0x0
#define MX93_PAD_CCM_CLKO4__GPIO4_IO29 0x0094 0x0244 0x0000 0x5 0x0
#define MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x0098 0x0248 0x0000 0x0 0x0
#define MX93_PAD_ENET1_MDC__LPUART3_DCB_B 0x0098 0x0248 0x0000 0x1 0x0
#define MX93_PAD_ENET1_MDC__I3C2_SCL 0x0098 0x0248 0x03CC 0x2 0x0
#define MX93_PAD_ENET1_MDC__HSIOMIX_OTG_ID1 0x0098 0x0248 0x0000 0x3 0x0
#define MX93_PAD_ENET1_MDC__FLEXIO2_FLEXIO00 0x0098 0x0248 0x0000 0x4 0x0
#define MX93_PAD_ENET1_MDC__GPIO4_IO00 0x0098 0x0248 0x0000 0x5 0x0
#define MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x009C 0x024C 0x0000 0x0 0x0
#define MX93_PAD_ENET1_MDIO__LPUART3_RIN_B 0x009C 0x024C 0x0000 0x1 0x0
#define MX93_PAD_ENET1_MDIO__I3C2_SDA 0x009C 0x024C 0x03D0 0x2 0x0
#define MX93_PAD_ENET1_MDIO__HSIOMIX_OTG_PWR1 0x009C 0x024C 0x0000 0x3 0x0
#define MX93_PAD_ENET1_MDIO__FLEXIO2_FLEXIO01 0x009C 0x024C 0x0000 0x4 0x0
#define MX93_PAD_ENET1_MDIO__GPIO4_IO01 0x009C 0x024C 0x0000 0x5 0x0
#define MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x00A0 0x0250 0x0000 0x0 0x0
#define MX93_PAD_ENET1_TD3__CAN2_TX 0x00A0 0x0250 0x0000 0x2 0x0
#define MX93_PAD_ENET1_TD3__HSIOMIX_OTG_ID2 0x00A0 0x0250 0x0000 0x3 0x0
#define MX93_PAD_ENET1_TD3__FLEXIO2_FLEXIO02 0x00A0 0x0250 0x0000 0x4 0x0
#define MX93_PAD_ENET1_TD3__GPIO4_IO02 0x00A0 0x0250 0x0000 0x5 0x0
#define MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x00A4 0x0254 0x0000 0x0 0x0
#define MX93_PAD_ENET1_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK 0x00A4 0x0254 0x0000 0x1 0x0
#define MX93_PAD_ENET1_TD2__CAN2_RX 0x00A4 0x0254 0x0364 0x2 0x2
#define MX93_PAD_ENET1_TD2__HSIOMIX_OTG_OC2 0x00A4 0x0254 0x0000 0x3 0x0
#define MX93_PAD_ENET1_TD2__FLEXIO2_FLEXIO03 0x00A4 0x0254 0x0000 0x4 0x0
#define MX93_PAD_ENET1_TD2__GPIO4_IO03 0x00A4 0x0254 0x0000 0x5 0x0
#define MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x00A8 0x0258 0x0000 0x0 0x0
#define MX93_PAD_ENET1_TD1__LPUART3_RTS_B 0x00A8 0x0258 0x0000 0x1 0x0
#define MX93_PAD_ENET1_TD1__I3C2_PUR 0x00A8 0x0258 0x0000 0x2 0x0
#define MX93_PAD_ENET1_TD1__HSIOMIX_OTG_OC1 0x00A8 0x0258 0x0000 0x3 0x0
#define MX93_PAD_ENET1_TD1__FLEXIO2_FLEXIO04 0x00A8 0x0258 0x0000 0x4 0x0
#define MX93_PAD_ENET1_TD1__GPIO4_IO04 0x00A8 0x0258 0x0000 0x5 0x0
#define MX93_PAD_ENET1_TD1__I3C2_PUR_B 0x00A8 0x0258 0x0000 0x6 0x0
#define MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x00AC 0x025C 0x0000 0x0 0x0
#define MX93_PAD_ENET1_TD0__LPUART3_TX 0x00AC 0x025C 0x041C 0x1 0x1
#define MX93_PAD_ENET1_TD0__FLEXIO2_FLEXIO05 0x00AC 0x025C 0x0000 0x4 0x0
#define MX93_PAD_ENET1_TD0__GPIO4_IO05 0x00AC 0x025C 0x0000 0x5 0x0
#define MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x00B0 0x0260 0x0000 0x0 0x0
#define MX93_PAD_ENET1_TX_CTL__LPUART3_DTR_B 0x00B0 0x0260 0x0000 0x1 0x0
#define MX93_PAD_ENET1_TX_CTL__FLEXIO2_FLEXIO06 0x00B0 0x0260 0x0000 0x4 0x0
#define MX93_PAD_ENET1_TX_CTL__GPIO4_IO06 0x00B0 0x0260 0x0000 0x5 0x0
#define MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x00B4 0x0264 0x0000 0x0 0x0
#define MX93_PAD_ENET1_TXC__ENET_QOS_TX_ER 0x00B4 0x0264 0x0000 0x1 0x0
#define MX93_PAD_ENET1_TXC__FLEXIO2_FLEXIO07 0x00B4 0x0264 0x0000 0x4 0x0
#define MX93_PAD_ENET1_TXC__GPIO4_IO07 0x00B4 0x0264 0x0000 0x5 0x0
#define MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x00B8 0x0268 0x0000 0x0 0x0
#define MX93_PAD_ENET1_RX_CTL__LPUART3_DSR_B 0x00B8 0x0268 0x0000 0x1 0x0
#define MX93_PAD_ENET1_RX_CTL__HSIOMIX_OTG_PWR2 0x00B8 0x0268 0x0000 0x3 0x0
#define MX93_PAD_ENET1_RX_CTL__FLEXIO2_FLEXIO08 0x00B8 0x0268 0x0000 0x4 0x0
#define MX93_PAD_ENET1_RX_CTL__GPIO4_IO08 0x00B8 0x0268 0x0000 0x5 0x0
#define MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x00BC 0x026C 0x0000 0x0 0x0
#define MX93_PAD_ENET1_RXC__ENET_QOS_RX_ER 0x00BC 0x026C 0x0000 0x1 0x0
#define MX93_PAD_ENET1_RXC__FLEXIO2_FLEXIO09 0x00BC 0x026C 0x0000 0x4 0x0
#define MX93_PAD_ENET1_RXC__GPIO4_IO09 0x00BC 0x026C 0x0000 0x5 0x0
#define MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x00C0 0x0270 0x0000 0x0 0x0
#define MX93_PAD_ENET1_RD0__LPUART3_RX 0x00C0 0x0270 0x0418 0x1 0x1
#define MX93_PAD_ENET1_RD0__FLEXIO2_FLEXIO10 0x00C0 0x0270 0x0000 0x4 0x0
#define MX93_PAD_ENET1_RD0__GPIO4_IO10 0x00C0 0x0270 0x0000 0x5 0x0
#define MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x00C4 0x0274 0x0000 0x0 0x0
#define MX93_PAD_ENET1_RD1__LPUART3_CTS_B 0x00C4 0x0274 0x0414 0x1 0x1
#define MX93_PAD_ENET1_RD1__LPTMR2_ALT1 0x00C4 0x0274 0x0408 0x3 0x0
#define MX93_PAD_ENET1_RD1__FLEXIO2_FLEXIO11 0x00C4 0x0274 0x0000 0x4 0x0
#define MX93_PAD_ENET1_RD1__GPIO4_IO11 0x00C4 0x0274 0x0000 0x5 0x0
#define MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x00C8 0x0278 0x0000 0x0 0x0
#define MX93_PAD_ENET1_RD2__LPTMR2_ALT2 0x00C8 0x0278 0x040C 0x3 0x0
#define MX93_PAD_ENET1_RD2__FLEXIO2_FLEXIO12 0x00C8 0x0278 0x0000 0x4 0x0
#define MX93_PAD_ENET1_RD2__GPIO4_IO12 0x00C8 0x0278 0x0000 0x5 0x0
#define MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x00CC 0x027C 0x0000 0x0 0x0
#define MX93_PAD_ENET1_RD3__FLEXSPI1_TESTER_TRIGGER 0x00CC 0x027C 0x0000 0x2 0x0
#define MX93_PAD_ENET1_RD3__LPTMR2_ALT3 0x00CC 0x027C 0x0410 0x3 0x0
#define MX93_PAD_ENET1_RD3__FLEXIO2_FLEXIO13 0x00CC 0x027C 0x0000 0x4 0x0
#define MX93_PAD_ENET1_RD3__GPIO4_IO13 0x00CC 0x027C 0x0000 0x5 0x0
#define MX93_PAD_ENET2_MDC__ENET1_MDC 0x00D0 0x0280 0x0000 0x0 0x0
#define MX93_PAD_ENET2_MDC__LPUART4_DCB_B 0x00D0 0x0280 0x0000 0x1 0x0
#define MX93_PAD_ENET2_MDC__SAI2_RX_SYNC 0x00D0 0x0280 0x0000 0x2 0x0
#define MX93_PAD_ENET2_MDC__FLEXIO2_FLEXIO14 0x00D0 0x0280 0x0000 0x4 0x0
#define MX93_PAD_ENET2_MDC__GPIO4_IO14 0x00D0 0x0280 0x0000 0x5 0x0
#define MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x00D4 0x0284 0x0000 0x0 0x0
#define MX93_PAD_ENET2_MDIO__LPUART4_RIN_B 0x00D4 0x0284 0x0000 0x1 0x0
#define MX93_PAD_ENET2_MDIO__SAI2_RX_BCLK 0x00D4 0x0284 0x0000 0x2 0x0
#define MX93_PAD_ENET2_MDIO__FLEXIO2_FLEXIO15 0x00D4 0x0284 0x0000 0x4 0x0
#define MX93_PAD_ENET2_MDIO__GPIO4_IO15 0x00D4 0x0284 0x0000 0x5 0x0
#define MX93_PAD_ENET2_TD3__SAI2_RX_DATA00 0x00D8 0x0288 0x0000 0x2 0x0
#define MX93_PAD_ENET2_TD3__FLEXIO2_FLEXIO16 0x00D8 0x0288 0x0000 0x4 0x0
#define MX93_PAD_ENET2_TD3__GPIO4_IO16 0x00D8 0x0288 0x0000 0x5 0x0
#define MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x00D8 0x0288 0x0000 0x0 0x0
#define MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x00DC 0x028C 0x0000 0x0 0x0
#define MX93_PAD_ENET2_TD2__ENET1_TX_CLK 0x00DC 0x028C 0x0000 0x1 0x0
#define MX93_PAD_ENET2_TD2__SAI2_RX_DATA01 0x00DC 0x028C 0x0000 0x2 0x0
#define MX93_PAD_ENET2_TD2__FLEXIO2_FLEXIO17 0x00DC 0x028C 0x0000 0x4 0x0
#define MX93_PAD_ENET2_TD2__GPIO4_IO17 0x00DC 0x028C 0x0000 0x5 0x0
#define MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x00E0 0x0290 0x0000 0x0 0x0
#define MX93_PAD_ENET2_TD1__LPUART4_RTS_B 0x00E0 0x0290 0x0000 0x1 0x0
#define MX93_PAD_ENET2_TD1__SAI2_RX_DATA02 0x00E0 0x0290 0x0000 0x2 0x0
#define MX93_PAD_ENET2_TD1__FLEXIO2_FLEXIO18 0x00E0 0x0290 0x0000 0x4 0x0
#define MX93_PAD_ENET2_TD1__GPIO4_IO18 0x00E0 0x0290 0x0000 0x5 0x0
#define MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x00E4 0x0294 0x0000 0x0 0x0
#define MX93_PAD_ENET2_TD0__LPUART4_TX 0x00E4 0x0294 0x0428 0x1 0x1
#define MX93_PAD_ENET2_TD0__SAI2_RX_DATA03 0x00E4 0x0294 0x0000 0x2 0x0
#define MX93_PAD_ENET2_TD0__FLEXIO2_FLEXIO19 0x00E4 0x0294 0x0000 0x4 0x0
#define MX93_PAD_ENET2_TD0__GPIO4_IO19 0x00E4 0x0294 0x0000 0x5 0x0
#define MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x00E8 0x0298 0x0000 0x0 0x0
#define MX93_PAD_ENET2_TX_CTL__LPUART4_DTR_B 0x00E8 0x0298 0x0000 0x1 0x0
#define MX93_PAD_ENET2_TX_CTL__SAI2_TX_SYNC 0x00E8 0x0298 0x0000 0x2 0x0
#define MX93_PAD_ENET2_TX_CTL__FLEXIO2_FLEXIO20 0x00E8 0x0298 0x0000 0x4 0x0
#define MX93_PAD_ENET2_TX_CTL__GPIO4_IO20 0x00E8 0x0298 0x0000 0x5 0x0
#define MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x00EC 0x029C 0x0000 0x0 0x0
#define MX93_PAD_ENET2_TXC__ENET1_TX_ER 0x00EC 0x029C 0x0000 0x1 0x0
#define MX93_PAD_ENET2_TXC__SAI2_TX_BCLK 0x00EC 0x029C 0x0000 0x2 0x0
#define MX93_PAD_ENET2_TXC__FLEXIO2_FLEXIO21 0x00EC 0x029C 0x0000 0x4 0x0
#define MX93_PAD_ENET2_TXC__GPIO4_IO21 0x00EC 0x029C 0x0000 0x5 0x0
#define MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x00F0 0x02A0 0x0000 0x0 0x0
#define MX93_PAD_ENET2_RX_CTL__LPUART4_DSR_B 0x00F0 0x02A0 0x0000 0x1 0x0
#define MX93_PAD_ENET2_RX_CTL__SAI2_TX_DATA00 0x00F0 0x02A0 0x0000 0x2 0x0
#define MX93_PAD_ENET2_RX_CTL__FLEXIO2_FLEXIO22 0x00F0 0x02A0 0x0000 0x4 0x0
#define MX93_PAD_ENET2_RX_CTL__GPIO4_IO22 0x00F0 0x02A0 0x0000 0x5 0x0
#define MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x00F4 0x02A4 0x0000 0x0 0x0
#define MX93_PAD_ENET2_RXC__ENET1_RX_ER 0x00F4 0x02A4 0x0000 0x1 0x0
#define MX93_PAD_ENET2_RXC__SAI2_TX_DATA01 0x00F4 0x02A4 0x0000 0x2 0x0
#define MX93_PAD_ENET2_RXC__FLEXIO2_FLEXIO23 0x00F4 0x02A4 0x0000 0x4 0x0
#define MX93_PAD_ENET2_RXC__GPIO4_IO23 0x00F4 0x02A4 0x0000 0x5 0x0
#define MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x00F8 0x02A8 0x0000 0x0 0x0
#define MX93_PAD_ENET2_RD0__LPUART4_RX 0x00F8 0x02A8 0x0424 0x1 0x1
#define MX93_PAD_ENET2_RD0__SAI2_TX_DATA02 0x00F8 0x02A8 0x0000 0x2 0x0
#define MX93_PAD_ENET2_RD0__FLEXIO2_FLEXIO24 0x00F8 0x02A8 0x0000 0x4 0x0
#define MX93_PAD_ENET2_RD0__GPIO4_IO24 0x00F8 0x02A8 0x0000 0x5 0x0
#define MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x00FC 0x02AC 0x0000 0x0 0x0
#define MX93_PAD_ENET2_RD1__SPDIF_IN 0x00FC 0x02AC 0x0454 0x1 0x1
#define MX93_PAD_ENET2_RD1__SAI2_TX_DATA03 0x00FC 0x02AC 0x0000 0x2 0x0
#define MX93_PAD_ENET2_RD1__FLEXIO2_FLEXIO25 0x00FC 0x02AC 0x0000 0x4 0x0
#define MX93_PAD_ENET2_RD1__GPIO4_IO25 0x00FC 0x02AC 0x0000 0x5 0x0
#define MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x0100 0x02B0 0x0000 0x0 0x0
#define MX93_PAD_ENET2_RD2__LPUART4_CTS_B 0x0100 0x02B0 0x0420 0x1 0x1
#define MX93_PAD_ENET2_RD2__SAI2_MCLK 0x0100 0x02B0 0x0000 0x2 0x0
#define MX93_PAD_ENET2_RD2__MQS2_RIGHT 0x0100 0x02B0 0x0000 0x3 0x0
#define MX93_PAD_ENET2_RD2__FLEXIO2_FLEXIO26 0x0100 0x02B0 0x0000 0x4 0x0
#define MX93_PAD_ENET2_RD2__GPIO4_IO26 0x0100 0x02B0 0x0000 0x5 0x0
#define MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x0104 0x02B4 0x0000 0x0 0x0
#define MX93_PAD_ENET2_RD3__SPDIF_OUT 0x0104 0x02B4 0x0000 0x1 0x0
#define MX93_PAD_ENET2_RD3__SPDIF_IN 0x0104 0x02B4 0x0454 0x2 0x2
#define MX93_PAD_ENET2_RD3__MQS2_LEFT 0x0104 0x02B4 0x0000 0x3 0x0
#define MX93_PAD_ENET2_RD3__FLEXIO2_FLEXIO27 0x0104 0x02B4 0x0000 0x4 0x0
#define MX93_PAD_ENET2_RD3__GPIO4_IO27 0x0104 0x02B4 0x0000 0x5 0x0
#define MX93_PAD_SD1_CLK__FLEXIO1_FLEXIO08 0x0108 0x02B8 0x038C 0x4 0x1
#define MX93_PAD_SD1_CLK__GPIO3_IO08 0x0108 0x02B8 0x0000 0x5 0x0
#define MX93_PAD_SD1_CLK__USDHC1_CLK 0x0108 0x02B8 0x0000 0x0 0x0
#define MX93_PAD_SD1_CMD__USDHC1_CMD 0x010C 0x02BC 0x0000 0x0 0x0
#define MX93_PAD_SD1_CMD__FLEXIO1_FLEXIO09 0x010C 0x02BC 0x0390 0x4 0x1
#define MX93_PAD_SD1_CMD__GPIO3_IO09 0x010C 0x02BC 0x0000 0x5 0x0
#define MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x0110 0x02C0 0x0000 0x0 0x0
#define MX93_PAD_SD1_DATA0__FLEXIO1_FLEXIO10 0x0110 0x02C0 0x0394 0x4 0x1
#define MX93_PAD_SD1_DATA0__GPIO3_IO10 0x0110 0x02C0 0x0000 0x5 0x0
#define MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x0114 0x02C4 0x0000 0x0 0x0
#define MX93_PAD_SD1_DATA1__FLEXIO1_FLEXIO11 0x0114 0x02C4 0x0398 0x4 0x1
#define MX93_PAD_SD1_DATA1__GPIO3_IO11 0x0114 0x02C4 0x0000 0x5 0x0
#define MX93_PAD_SD1_DATA1__CCMSRCGPCMIX_INT_BOOT 0x0114 0x02C4 0x0000 0x6 0x0
#define MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x0118 0x02C8 0x0000 0x0 0x0
#define MX93_PAD_SD1_DATA2__FLEXIO1_FLEXIO12 0x0118 0x02C8 0x0000 0x4 0x0
#define MX93_PAD_SD1_DATA2__GPIO3_IO12 0x0118 0x02C8 0x0000 0x5 0x0
#define MX93_PAD_SD1_DATA2__CCMSRCGPCMIX_PMIC_READY 0x0118 0x02C8 0x0000 0x6 0x0
#define MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x011C 0x02CC 0x0000 0x0 0x0
#define MX93_PAD_SD1_DATA3__FLEXSPI1_A_SS1_B 0x011C 0x02CC 0x0000 0x1 0x0
#define MX93_PAD_SD1_DATA3__FLEXIO1_FLEXIO13 0x011C 0x02CC 0x039C 0x4 0x1
#define MX93_PAD_SD1_DATA3__GPIO3_IO13 0x011C 0x02CC 0x0000 0x5 0x0
#define MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x0120 0x02D0 0x0000 0x0 0x0
#define MX93_PAD_SD1_DATA4__FLEXSPI1_A_DATA04 0x0120 0x02D0 0x0000 0x1 0x0
#define MX93_PAD_SD1_DATA4__FLEXIO1_FLEXIO14 0x0120 0x02D0 0x03A0 0x4 0x1
#define MX93_PAD_SD1_DATA4__GPIO3_IO14 0x0120 0x02D0 0x0000 0x5 0x0
#define MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x0124 0x02D4 0x0000 0x0 0x0
#define MX93_PAD_SD1_DATA5__FLEXSPI1_A_DATA05 0x0124 0x02D4 0x0000 0x1 0x0
#define MX93_PAD_SD1_DATA5__USDHC1_RESET_B 0x0124 0x02D4 0x0000 0x2 0x0
#define MX93_PAD_SD1_DATA5__FLEXIO1_FLEXIO15 0x0124 0x02D4 0x03A4 0x4 0x1
#define MX93_PAD_SD1_DATA5__GPIO3_IO15 0x0124 0x02D4 0x0000 0x5 0x0
#define MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x0128 0x02D8 0x0000 0x0 0x0
#define MX93_PAD_SD1_DATA6__FLEXSPI1_A_DATA06 0x0128 0x02D8 0x0000 0x1 0x0
#define MX93_PAD_SD1_DATA6__USDHC1_CD_B 0x0128 0x02D8 0x0000 0x2 0x0
#define MX93_PAD_SD1_DATA6__FLEXIO1_FLEXIO16 0x0128 0x02D8 0x03A8 0x4 0x1
#define MX93_PAD_SD1_DATA6__GPIO3_IO16 0x0128 0x02D8 0x0000 0x5 0x0
#define MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x012C 0x02DC 0x0000 0x0 0x0
#define MX93_PAD_SD1_DATA7__FLEXSPI1_A_DATA07 0x012C 0x02DC 0x0000 0x1 0x0
#define MX93_PAD_SD1_DATA7__USDHC1_WP 0x012C 0x02DC 0x0000 0x2 0x0
#define MX93_PAD_SD1_DATA7__FLEXIO1_FLEXIO17 0x012C 0x02DC 0x03AC 0x4 0x1
#define MX93_PAD_SD1_DATA7__GPIO3_IO17 0x012C 0x02DC 0x0000 0x5 0x0
#define MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x0130 0x02E0 0x0000 0x0 0x0
#define MX93_PAD_SD1_STROBE__FLEXSPI1_A_DQS 0x0130 0x02E0 0x0000 0x1 0x0
#define MX93_PAD_SD1_STROBE__FLEXIO1_FLEXIO18 0x0130 0x02E0 0x03B0 0x4 0x1
#define MX93_PAD_SD1_STROBE__GPIO3_IO18 0x0130 0x02E0 0x0000 0x5 0x0
#define MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x0134 0x02E4 0x0000 0x0 0x0
#define MX93_PAD_SD2_VSELECT__USDHC2_WP 0x0134 0x02E4 0x0000 0x1 0x0
#define MX93_PAD_SD2_VSELECT__LPTMR2_ALT3 0x0134 0x02E4 0x0410 0x2 0x1
#define MX93_PAD_SD2_VSELECT__FLEXIO1_FLEXIO19 0x0134 0x02E4 0x0000 0x4 0x0
#define MX93_PAD_SD2_VSELECT__GPIO3_IO19 0x0134 0x02E4 0x0000 0x5 0x0
#define MX93_PAD_SD2_VSELECT__CCMSRCGPCMIX_EXT_CLK1 0x0134 0x02E4 0x0368 0x6 0x0
#define MX93_PAD_SD3_CLK__USDHC3_CLK 0x0138 0x02E8 0x0458 0x0 0x1
#define MX93_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x0138 0x02E8 0x0000 0x1 0x0
#define MX93_PAD_SD3_CLK__FLEXIO1_FLEXIO20 0x0138 0x02E8 0x03B4 0x4 0x1
#define MX93_PAD_SD3_CLK__GPIO3_IO20 0x0138 0x02E8 0x0000 0x5 0x0
#define MX93_PAD_SD3_CMD__USDHC3_CMD 0x013C 0x02EC 0x045C 0x0 0x1
#define MX93_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x013C 0x02EC 0x0000 0x1 0x0
#define MX93_PAD_SD3_CMD__FLEXIO1_FLEXIO21 0x013C 0x02EC 0x0000 0x4 0x0
#define MX93_PAD_SD3_CMD__GPIO3_IO21 0x013C 0x02EC 0x0000 0x5 0x0
#define MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x0140 0x02F0 0x0460 0x0 0x1
#define MX93_PAD_SD3_DATA0__FLEXSPI1_A_DATA00 0x0140 0x02F0 0x0000 0x1 0x0
#define MX93_PAD_SD3_DATA0__FLEXIO1_FLEXIO22 0x0140 0x02F0 0x03B8 0x4 0x1
#define MX93_PAD_SD3_DATA0__GPIO3_IO22 0x0140 0x02F0 0x0000 0x5 0x0
#define MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x0144 0x02F4 0x0464 0x0 0x1
#define MX93_PAD_SD3_DATA1__FLEXSPI1_A_DATA01 0x0144 0x02F4 0x0000 0x1 0x0
#define MX93_PAD_SD3_DATA1__FLEXIO1_FLEXIO23 0x0144 0x02F4 0x03BC 0x4 0x1
#define MX93_PAD_SD3_DATA1__GPIO3_IO23 0x0144 0x02F4 0x0000 0x5 0x0
#define MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x0148 0x02F8 0x0468 0x0 0x1
#define MX93_PAD_SD3_DATA2__FLEXSPI1_A_DATA02 0x0148 0x02F8 0x0000 0x1 0x0
#define MX93_PAD_SD3_DATA2__FLEXIO1_FLEXIO24 0x0148 0x02F8 0x03C0 0x4 0x1
#define MX93_PAD_SD3_DATA2__GPIO3_IO24 0x0148 0x02F8 0x0000 0x5 0x0
#define MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x014C 0x02FC 0x046C 0x0 0x1
#define MX93_PAD_SD3_DATA3__FLEXSPI1_A_DATA03 0x014C 0x02FC 0x0000 0x1 0x0
#define MX93_PAD_SD3_DATA3__FLEXIO1_FLEXIO25 0x014C 0x02FC 0x03C4 0x4 0x1
#define MX93_PAD_SD3_DATA3__GPIO3_IO25 0x014C 0x02FC 0x0000 0x5 0x0
#define MX93_PAD_SD2_CD_B__USDHC2_CD_B 0x0150 0x0300 0x0000 0x0 0x0
#define MX93_PAD_SD2_CD_B__ENET_QOS_1588_EVENT0_IN 0x0150 0x0300 0x0000 0x1 0x0
#define MX93_PAD_SD2_CD_B__I3C2_SCL 0x0150 0x0300 0x03CC 0x2 0x1
#define MX93_PAD_SD2_CD_B__FLEXIO1_FLEXIO00 0x0150 0x0300 0x036C 0x4 0x1
#define MX93_PAD_SD2_CD_B__GPIO3_IO00 0x0150 0x0300 0x0000 0x5 0x0
#define MX93_PAD_SD2_CLK__USDHC2_CLK 0x0154 0x0304 0x0000 0x0 0x0
#define MX93_PAD_SD2_CLK__ENET_QOS_1588_EVENT0_OUT 0x0154 0x0304 0x0000 0x1 0x0
#define MX93_PAD_SD2_CLK__I3C2_SDA 0x0154 0x0304 0x03D0 0x2 0x1
#define MX93_PAD_SD2_CLK__FLEXIO1_FLEXIO01 0x0154 0x0304 0x0370 0x4 0x1
#define MX93_PAD_SD2_CLK__GPIO3_IO01 0x0154 0x0304 0x0000 0x5 0x0
#define MX93_PAD_SD2_CLK__CCMSRCGPCMIX_OBSERVE0 0x0154 0x0304 0x0000 0x6 0x0
#define MX93_PAD_SD2_CMD__USDHC2_CMD 0x0158 0x0308 0x0000 0x0 0x0
#define MX93_PAD_SD2_CMD__ENET1_1588_EVENT0_IN 0x0158 0x0308 0x0000 0x1 0x0
#define MX93_PAD_SD2_CMD__I3C2_PUR 0x0158 0x0308 0x0000 0x2 0x0
#define MX93_PAD_SD2_CMD__I3C2_PUR_B 0x0158 0x0308 0x0000 0x3 0x0
#define MX93_PAD_SD2_CMD__FLEXIO1_FLEXIO02 0x0158 0x0308 0x0374 0x4 0x1
#define MX93_PAD_SD2_CMD__GPIO3_IO02 0x0158 0x0308 0x0000 0x5 0x0
#define MX93_PAD_SD2_CMD__CCMSRCGPCMIX_OBSERVE1 0x0158 0x0308 0x0000 0x6 0x0
#define MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x015C 0x030C 0x0000 0x0 0x0
#define MX93_PAD_SD2_DATA0__ENET1_1588_EVENT0_OUT 0x015C 0x030C 0x0000 0x1 0x0
#define MX93_PAD_SD2_DATA0__CAN2_TX 0x015C 0x030C 0x0000 0x2 0x0
#define MX93_PAD_SD2_DATA0__FLEXIO1_FLEXIO03 0x015C 0x030C 0x0378 0x4 0x1
#define MX93_PAD_SD2_DATA0__GPIO3_IO03 0x015C 0x030C 0x0000 0x5 0x0
#define MX93_PAD_SD2_DATA0__CCMSRCGPCMIX_OBSERVE2 0x015C 0x030C 0x0000 0x6 0x0
#define MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x0160 0x0310 0x0000 0x0 0x0
#define MX93_PAD_SD2_DATA1__ENET1_1588_EVENT1_IN 0x0160 0x0310 0x0000 0x1 0x0
#define MX93_PAD_SD2_DATA1__CAN2_RX 0x0160 0x0310 0x0364 0x2 0x3
#define MX93_PAD_SD2_DATA1__FLEXIO1_FLEXIO04 0x0160 0x0310 0x037C 0x4 0x1
#define MX93_PAD_SD2_DATA1__GPIO3_IO04 0x0160 0x0310 0x0000 0x5 0x0
#define MX93_PAD_SD2_DATA1__CCMSRCGPCMIX_WAIT 0x0160 0x0310 0x0000 0x6 0x0
#define MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x0164 0x0314 0x0000 0x0 0x0
#define MX93_PAD_SD2_DATA2__ENET1_1588_EVENT1_OUT 0x0164 0x0314 0x0000 0x1 0x0
#define MX93_PAD_SD2_DATA2__MQS2_RIGHT 0x0164 0x0314 0x0000 0x2 0x0
#define MX93_PAD_SD2_DATA2__FLEXIO1_FLEXIO05 0x0164 0x0314 0x0380 0x4 0x1
#define MX93_PAD_SD2_DATA2__GPIO3_IO05 0x0164 0x0314 0x0000 0x5 0x0
#define MX93_PAD_SD2_DATA2__CCMSRCGPCMIX_STOP 0x0164 0x0314 0x0000 0x6 0x0
#define MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x0168 0x0318 0x0000 0x0 0x0
#define MX93_PAD_SD2_DATA3__LPTMR2_ALT1 0x0168 0x0318 0x0408 0x1 0x1
#define MX93_PAD_SD2_DATA3__MQS2_LEFT 0x0168 0x0318 0x0000 0x2 0x0
#define MX93_PAD_SD2_DATA3__FLEXIO1_FLEXIO06 0x0168 0x0318 0x0384 0x4 0x1
#define MX93_PAD_SD2_DATA3__GPIO3_IO06 0x0168 0x0318 0x0000 0x5 0x0
#define MX93_PAD_SD2_DATA3__CCMSRCGPCMIX_EARLY_RESET 0x0168 0x0318 0x0000 0x6 0x0
#define MX93_PAD_SD2_RESET_B__USDHC2_RESET_B 0x016C 0x031C 0x0000 0x0 0x0
#define MX93_PAD_SD2_RESET_B__LPTMR2_ALT2 0x016C 0x031C 0x040C 0x1 0x1
#define MX93_PAD_SD2_RESET_B__FLEXIO1_FLEXIO07 0x016C 0x031C 0x0388 0x4 0x1
#define MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x016C 0x031C 0x0000 0x5 0x0
#define MX93_PAD_SD2_RESET_B__CCMSRCGPCMIX_SYSTEM_RESET 0x016C 0x031C 0x0000 0x6 0x0
#define MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x0170 0x0320 0x0000 0x10 0x0
#define MX93_PAD_I2C1_SCL__I3C1_SCL 0x0170 0x0320 0x0000 0x1 0x0
#define MX93_PAD_I2C1_SCL__LPUART1_DCB_B 0x0170 0x0320 0x0000 0x2 0x0
#define MX93_PAD_I2C1_SCL__TPM2_CH0 0x0170 0x0320 0x0000 0x3 0x0
#define MX93_PAD_I2C1_SCL__GPIO1_IO00 0x0170 0x0320 0x0000 0x5 0x0
#define MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x0174 0x0324 0x0000 0x10 0x0
#define MX93_PAD_I2C1_SDA__I3C1_SDA 0x0174 0x0324 0x0000 0x1 0x0
#define MX93_PAD_I2C1_SDA__LPUART1_RIN_B 0x0174 0x0324 0x0000 0x2 0x0
#define MX93_PAD_I2C1_SDA__TPM2_CH1 0x0174 0x0324 0x0000 0x3 0x0
#define MX93_PAD_I2C1_SDA__GPIO1_IO01 0x0174 0x0324 0x0000 0x5 0x0
#define MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x0178 0x0328 0x0000 0x10 0x0
#define MX93_PAD_I2C2_SCL__I3C1_PUR 0x0178 0x0328 0x0000 0x1 0x0
#define MX93_PAD_I2C2_SCL__LPUART2_DCB_B 0x0178 0x0328 0x0000 0x2 0x0
#define MX93_PAD_I2C2_SCL__TPM2_CH2 0x0178 0x0328 0x0000 0x3 0x0
#define MX93_PAD_I2C2_SCL__SAI1_RX_SYNC 0x0178 0x0328 0x0000 0x4 0x0
#define MX93_PAD_I2C2_SCL__GPIO1_IO02 0x0178 0x0328 0x0000 0x5 0x0
#define MX93_PAD_I2C2_SCL__I3C1_PUR_B 0x0178 0x0328 0x0000 0x6 0x0
#define MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x017C 0x032C 0x0000 0x10 0x0
#define MX93_PAD_I2C2_SDA__LPUART2_RIN_B 0x017C 0x032C 0x0000 0x2 0x0
#define MX93_PAD_I2C2_SDA__TPM2_CH3 0x017C 0x032C 0x0000 0x3 0x0
#define MX93_PAD_I2C2_SDA__SAI1_RX_BCLK 0x017C 0x032C 0x0000 0x4 0x0
#define MX93_PAD_I2C2_SDA__GPIO1_IO03 0x017C 0x032C 0x0000 0x5 0x0
#define MX93_PAD_UART1_RXD__LPUART1_RX 0x0180 0x0330 0x0000 0x0 0x0
#define MX93_PAD_UART1_RXD__S400_UART_RX 0x0180 0x0330 0x0000 0x1 0x0
#define MX93_PAD_UART1_RXD__LPSPI2_SIN 0x0180 0x0330 0x0000 0x2 0x0
#define MX93_PAD_UART1_RXD__TPM1_CH0 0x0180 0x0330 0x0000 0x3 0x0
#define MX93_PAD_UART1_RXD__GPIO1_IO04 0x0180 0x0330 0x0000 0x5 0x0
#define MX93_PAD_UART1_TXD__LPUART1_TX 0x0184 0x0334 0x0000 0x0 0x0
#define MX93_PAD_UART1_TXD__S400_UART_TX 0x0184 0x0334 0x0000 0x1 0x0
#define MX93_PAD_UART1_TXD__LPSPI2_PCS0 0x0184 0x0334 0x0000 0x2 0x0
#define MX93_PAD_UART1_TXD__TPM1_CH1 0x0184 0x0334 0x0000 0x3 0x0
#define MX93_PAD_UART1_TXD__GPIO1_IO05 0x0184 0x0334 0x0000 0x5 0x0
#define MX93_PAD_UART2_RXD__LPUART2_RX 0x0188 0x0338 0x0000 0x0 0x0
#define MX93_PAD_UART2_RXD__LPUART1_CTS_B 0x0188 0x0338 0x0000 0x1 0x0
#define MX93_PAD_UART2_RXD__LPSPI2_SOUT 0x0188 0x0338 0x0000 0x2 0x0
#define MX93_PAD_UART2_RXD__TPM1_CH2 0x0188 0x0338 0x0000 0x3 0x0
#define MX93_PAD_UART2_RXD__SAI1_MCLK 0x0188 0x0338 0x0448 0x4 0x0
#define MX93_PAD_UART2_RXD__GPIO1_IO06 0x0188 0x0338 0x0000 0x5 0x0
#define MX93_PAD_UART2_TXD__LPUART2_TX 0x018C 0x033C 0x0000 0x0 0x0
#define MX93_PAD_UART2_TXD__LPUART1_RTS_B 0x018C 0x033C 0x0000 0x1 0x0
#define MX93_PAD_UART2_TXD__LPSPI2_SCK 0x018C 0x033C 0x0000 0x2 0x0
#define MX93_PAD_UART2_TXD__TPM1_CH3 0x018C 0x033C 0x0000 0x3 0x0
#define MX93_PAD_UART2_TXD__GPIO1_IO07 0x018C 0x033C 0x0000 0x5 0x0
#define MX93_PAD_PDM_CLK__PDM_CLK 0x0190 0x0340 0x0000 0x0 0x0
#define MX93_PAD_PDM_CLK__MQS1_LEFT 0x0190 0x0340 0x0000 0x1 0x0
#define MX93_PAD_PDM_CLK__LPTMR1_ALT1 0x0190 0x0340 0x0000 0x4 0x0
#define MX93_PAD_PDM_CLK__GPIO1_IO08 0x0190 0x0340 0x0000 0x5 0x0
#define MX93_PAD_PDM_CLK__CAN1_TX 0x0190 0x0340 0x0000 0x6 0x0
#define MX93_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM00 0x0194 0x0344 0x0438 0x0 0x2
#define MX93_PAD_PDM_BIT_STREAM0__MQS1_RIGHT 0x0194 0x0344 0x0000 0x1 0x0
#define MX93_PAD_PDM_BIT_STREAM0__LPSPI1_PCS1 0x0194 0x0344 0x0000 0x2 0x0
#define MX93_PAD_PDM_BIT_STREAM0__TPM1_EXTCLK 0x0194 0x0344 0x0000 0x3 0x0
#define MX93_PAD_PDM_BIT_STREAM0__LPTMR1_ALT2 0x0194 0x0344 0x0000 0x4 0x0
#define MX93_PAD_PDM_BIT_STREAM0__GPIO1_IO09 0x0194 0x0344 0x0000 0x5 0x0
#define MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x0194 0x0344 0x0360 0x6 0x0
#define MX93_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM01 0x0198 0x0348 0x043C 0x0 0x2
#define MX93_PAD_PDM_BIT_STREAM1__NMI_GLUE_NMI 0x0198 0x0348 0x0000 0x1 0x0
#define MX93_PAD_PDM_BIT_STREAM1__LPSPI2_PCS1 0x0198 0x0348 0x0000 0x2 0x0
#define MX93_PAD_PDM_BIT_STREAM1__TPM2_EXTCLK 0x0198 0x0348 0x0000 0x3 0x0
#define MX93_PAD_PDM_BIT_STREAM1__LPTMR1_ALT3 0x0198 0x0348 0x0000 0x4 0x0
#define MX93_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x0198 0x0348 0x0000 0x5 0x0
#define MX93_PAD_PDM_BIT_STREAM1__CCMSRCGPCMIX_EXT_CLK1 0x0198 0x0348 0x0368 0x6 0x1
#define MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x019C 0x034C 0x0000 0x0 0x0
#define MX93_PAD_SAI1_TXFS__SAI1_TX_DATA01 0x019C 0x034C 0x0000 0x1 0x0
#define MX93_PAD_SAI1_TXFS__LPSPI1_PCS0 0x019C 0x034C 0x0000 0x2 0x0
#define MX93_PAD_SAI1_TXFS__LPUART2_DTR_B 0x019C 0x034C 0x0000 0x3 0x0
#define MX93_PAD_SAI1_TXFS__MQS1_LEFT 0x019C 0x034C 0x0000 0x4 0x0
#define MX93_PAD_SAI1_TXFS__GPIO1_IO11 0x019C 0x034C 0x0000 0x5 0x0
#define MX93_PAD_SAI1_TXC__SAI1_TX_BCLK 0x01A0 0x0350 0x0000 0x0 0x0
#define MX93_PAD_SAI1_TXC__LPUART2_CTS_B 0x01A0 0x0350 0x0000 0x1 0x0
#define MX93_PAD_SAI1_TXC__LPSPI1_SIN 0x01A0 0x0350 0x0000 0x2 0x0
#define MX93_PAD_SAI1_TXC__LPUART1_DSR_B 0x01A0 0x0350 0x0000 0x3 0x0
#define MX93_PAD_SAI1_TXC__CAN1_RX 0x01A0 0x0350 0x0360 0x4 0x1
#define MX93_PAD_SAI1_TXC__GPIO1_IO12 0x01A0 0x0350 0x0000 0x5 0x0
#define MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00 0x01A4 0x0354 0x0000 0x0 0x0
#define MX93_PAD_SAI1_TXD0__LPUART2_RTS_B 0x01A4 0x0354 0x0000 0x1 0x0
#define MX93_PAD_SAI1_TXD0__LPSPI1_SCK 0x01A4 0x0354 0x0000 0x2 0x0
#define MX93_PAD_SAI1_TXD0__LPUART1_DTR_B 0x01A4 0x0354 0x0000 0x3 0x0
#define MX93_PAD_SAI1_TXD0__CAN1_TX 0x01A4 0x0354 0x0000 0x4 0x0
#define MX93_PAD_SAI1_TXD0__GPIO1_IO13 0x01A4 0x0354 0x0000 0x5 0x0
#define MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 0x01A8 0x0358 0x0000 0x0 0x0
#define MX93_PAD_SAI1_RXD0__SAI1_MCLK 0x01A8 0x0358 0x0448 0x1 0x1
#define MX93_PAD_SAI1_RXD0__LPSPI1_SOUT 0x01A8 0x0358 0x0000 0x2 0x0
#define MX93_PAD_SAI1_RXD0__LPUART2_DSR_B 0x01A8 0x0358 0x0000 0x3 0x0
#define MX93_PAD_SAI1_RXD0__MQS1_RIGHT 0x01A8 0x0358 0x0000 0x4 0x0
#define MX93_PAD_SAI1_RXD0__GPIO1_IO14 0x01A8 0x0358 0x0000 0x5 0x0
#define MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x01AC 0x035C 0x0000 0x0 0x0
#define MX93_PAD_WDOG_ANY__GPIO1_IO15 0x01AC 0x035C 0x0000 0x5 0x0
#endif /* __DTS_IMX93_PINFUNC_H */

View File

@@ -22,12 +22,12 @@
type = "nxp-header-ddrfw";
imx-lpddr-imem {
filename = "lpddr5_imem_v202311.bin";
filename = "lpddr5_imem_v202409.bin";
type = "blob-ext";
};
imx-lpddr-dmem {
filename = "lpddr5_dmem_v202311.bin";
filename = "lpddr5_dmem_v202409.bin";
type = "blob-ext";
};
};
@@ -36,12 +36,12 @@
type = "nxp-header-ddrfw";
imx-lpddr-imem-qb {
filename = "lpddr5_imem_qb_v202311.bin";
filename = "lpddr5_imem_qb_v202409.bin";
type = "blob-ext";
};
imx-lpddr-dmem-qb {
filename = "lpddr5_dmem_qb_v202311.bin";
filename = "lpddr5_dmem_qb_v202409.bin";
type = "blob-ext";
};
};
@@ -52,15 +52,47 @@
pad-byte = <0x00>;
spl {
align = <0x400>;
align-size = <0x400>;
type = "mkimage";
args = "-n spl/u-boot-spl.cfgout -T imx8image";
type = "nxp-imx9image";
cfg-path = "spl/u-boot-spl.cfgout";
args;
#ifndef CONFIG_IMX95_A0
cntr-version = <2>;
#endif
boot-from = "sd";
soc-type = "IMX9";
#ifdef CONFIG_IMX95_A0
append = "mx95a0-ahab-container.img";
#else
append = "mx95b0-ahab-container.img";
#endif
container;
#ifndef CONFIG_IMX95_A0
dummy-ddr;
#endif
image0 = "oei", "m33-oei-ddrfw.bin", "0x1ffc0000";
hold = <0x10000>;
#ifdef CONFIG_IMX95_A0
image1 = "oei", "oei-m33-tcm.bin", "0x1ffc0000";
#endif
image2 = "m33", "m33_image.bin", "0x1ffc0000";
image3 = "a55", "spl/u-boot-spl.bin", "0x20480000";
dummy-v2x = <0x8b000000>;
};
u-boot {
type = "mkimage";
args = "-n u-boot-container.cfgout -T imx8image";
type = "nxp-imx9image";
cfg-path = "u-boot-container.cfgout";
args;
#ifndef CONFIG_IMX95_A0
cntr-version = <2>;
#endif
boot-from = "sd";
soc-type = "IMX9";
container;
image0 = "a55", "bl31.bin", "0x8a200000";
image1 = "a55", "u-boot.bin", "0x90200000";
};
};
};

View File

@@ -64,7 +64,6 @@
iomuxc: iomuxc@401f8000 {
compatible = "fsl,imxrt-iomuxc";
reg = <0x401f8000 0x4000>;
fsl,mux_mask = <0x7>;
};
anatop: anatop@400d8000 {

File diff suppressed because it is too large Load Diff

View File

@@ -77,7 +77,6 @@
iomuxc: iomuxc@400e8000 {
compatible = "fsl,imxrt-iomuxc";
reg = <0x400e8000 0x4000>;
fsl,mux_mask = <0x7>;
};
anatop: anatop@40c84000 {

View File

@@ -0,0 +1,37 @@
// SPDX-License-Identifier: GPL-2.0
/*
* IPQ5424 RDP466 board device tree source
*
* Copyright (c) 2025 The Linux Foundation. All rights reserved.
*/
/ {
/* Will be removed when SMEM parsing is updated */
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x20000000>;
};
};
&sdhc {
sdhci-caps-mask = <0x0 0x04000000>;
sdhci-caps = <0x0 0x04000000>; /* SDHCI_CAN_VDD_180 */
mmc-ddr-1_8v;
mmc-hs200-1_8v;
max-frequency = <192000000>;
bus-width = <4>;
pinctrl-0 = <&sdc_default_state>;
pinctrl-names = "default";
non-removable;
/*
* This reset is needed to clear out the settings done by
* previous boot loader. Without this the SDHCI_RESET_ALL
* reset done sdhci_init() times out.
*/
resets = <&gcc GCC_SDCC_BCR>;
status = "okay";
};

View File

@@ -64,7 +64,7 @@
&cbass_main {
sysctrler: sysctrler {
compatible = "ti,am654-system-controller";
compatible = "ti,am654-tisci-rproc-r5";
mboxes= <&secure_proxy_main 1>,
<&secure_proxy_main 0>,
<&secure_proxy_sa3 0>;

View File

@@ -9,10 +9,6 @@
#include "k3-binman.dtsi"
/ {
chosen {
tick-timer = &main_timer0;
};
/* Keep the LEDs on by default to indicate life */
leds {
led-0 {
@@ -37,10 +33,6 @@
};
};
&main_timer0 {
clock-frequency = <25000000>;
};
&sd_pins_default {
/* Force to use SDCD card detect pin */
pinctrl-single,pins = <

View File

@@ -13,7 +13,6 @@
/ {
chosen {
stdout-path = "serial2:115200n8";
tick-timer = &main_timer0;
};
aliases {
@@ -96,10 +95,6 @@
bootph-all;
};
&main_timer0 {
clock-frequency = <25000000>;
};
&main_uart0 {
bootph-all;
};

View File

@@ -25,7 +25,7 @@
content-sysfw-data = <&combined_tifs_cfg>;
content-sysfw-inner-cert = <&sysfw_inner_cert>;
content-dm-data = <&combined_dm_cfg>;
load = <0x43c00000>;
load = <CONFIG_SPL_TEXT_BASE>;
load-sysfw = <0x40000>;
load-sysfw-data = <0x67000>;
load-dm-data = <0x43c3a800>;
@@ -36,7 +36,6 @@
ti_fs_enc: ti-fs-enc.bin {
filename = "ti-sysfw/ti-fs-firmware-am62x-hs-enc.bin";
type = "blob-ext";
optional;
};
combined_tifs_cfg: combined-tifs-cfg.bin {
filename = "combined-tifs-cfg.bin";
@@ -45,7 +44,6 @@
sysfw_inner_cert: sysfw-inner-cert {
filename = "ti-sysfw/ti-fs-firmware-am62x-hs-cert.bin";
type = "blob-ext";
optional;
};
combined_dm_cfg: combined-dm-cfg.bin {
filename = "combined-dm-cfg.bin";
@@ -71,7 +69,7 @@
content-sysfw-data = <&combined_tifs_cfg_fs>;
content-sysfw-inner-cert = <&sysfw_inner_cert_fs>;
content-dm-data = <&combined_dm_cfg_fs>;
load = <0x43c00000>;
load = <CONFIG_SPL_TEXT_BASE>;
load-sysfw = <0x40000>;
load-sysfw-data = <0x67000>;
load-dm-data = <0x43c3a800>;
@@ -82,7 +80,6 @@
ti_fs_enc_fs: ti-fs-enc.bin {
filename = "ti-sysfw/ti-fs-firmware-am62x-hs-fs-enc.bin";
type = "blob-ext";
optional;
};
combined_tifs_cfg_fs: combined-tifs-cfg.bin {
filename = "combined-tifs-cfg.bin";
@@ -91,7 +88,6 @@
sysfw_inner_cert_fs: sysfw-inner-cert {
filename = "ti-sysfw/ti-fs-firmware-am62x-hs-fs-cert.bin";
type = "blob-ext";
optional;
};
combined_dm_cfg_fs: combined-dm-cfg.bin {
filename = "combined-dm-cfg.bin";
@@ -109,7 +105,7 @@
combined;
dm-data;
content-sbl = <&u_boot_spl_unsigned>;
load = <0x43c00000>;
load = <CONFIG_SPL_TEXT_BASE>;
content-sysfw = <&ti_fs_gp>;
load-sysfw = <0x40000>;
content-sysfw-data = <&combined_tifs_cfg_gp>;
@@ -125,7 +121,6 @@
ti_fs_gp: ti-fs-gp.bin {
filename = "ti-sysfw/ti-fs-firmware-am62x-gp.bin";
type = "blob-ext";
optional;
};
combined_tifs_cfg_gp: combined-tifs-cfg-gp.bin {
filename = "combined-tifs-cfg.bin";
@@ -405,11 +400,105 @@
};
&binman {
tifsstub-hs {
filename = "tifsstub.bin_hs";
ti-secure-rom {
content = <&tifsstub_hs_cert>;
core = "secure";
load = <0x40000>;
sw-rev = <CONFIG_K3_X509_SWRV>;
keyfile = "custMpk.pem";
countersign;
tifsstub;
};
tifsstub_hs_cert: tifsstub-hs-cert.bin {
filename = "ti-sysfw/ti-fs-stub-firmware-am62x-hs-cert.bin";
type = "blob-ext";
optional;
};
tifsstub_hs_enc: tifsstub-hs-enc.bin {
filename = "ti-sysfw/ti-fs-stub-firmware-am62x-hs-enc.bin";
type = "blob-ext";
optional;
};
};
tifsstub-fs {
filename = "tifsstub.bin_fs";
tifsstub_fs_cert: tifsstub-fs-cert.bin {
filename = "ti-sysfw/ti-fs-stub-firmware-am62x-hs-cert.bin";
type = "blob-ext";
optional;
};
tifsstub_fs_enc: tifsstub-fs-enc.bin {
filename = "ti-sysfw/ti-fs-stub-firmware-am62x-hs-enc.bin";
type = "blob-ext";
optional;
};
};
tifsstub-gp {
filename = "tifsstub.bin_gp";
ti-secure-rom {
content = <&tifsstub_gp>;
core = "secure";
load = <0x60000>;
sw-rev = <CONFIG_K3_X509_SWRV>;
keyfile = "ti-degenerate-key.pem";
tifsstub;
};
tifsstub_gp: tifsstub-gp.bin {
filename = "ti-sysfw/ti-fs-stub-firmware-am62x-gp.bin";
type = "blob-ext";
optional;
};
};
ti-spl_unsigned {
insert-template = <&ti_spl_unsigned_template>;
fit {
images {
tifsstub-hs {
description = "TIFSSTUB";
type = "firmware";
arch = "arm32";
compression = "none";
os = "tifsstub-hs";
load = <0x9dc00000>;
entry = <0x9dc00000>;
blob-ext {
filename = "tifsstub.bin_hs";
};
};
tifsstub-fs {
description = "TIFSSTUB";
type = "firmware";
arch = "arm32";
compression = "none";
os = "tifsstub-fs";
load = <0x9dc00000>;
entry = <0x9dc00000>;
blob-ext {
filename = "tifsstub.bin_fs";
};
};
tifsstub-gp {
description = "TIFSSTUB";
type = "firmware";
arch = "arm32";
compression = "none";
os = "tifsstub-gp";
load = <0x9dc00000>;
entry = <0x9dc00000>;
blob-ext {
filename = "tifsstub.bin_gp";
};
};
dm {
ti-dm {
filename = "ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f";

View File

@@ -46,6 +46,14 @@
};
};
&main_timer0 {
/delete-property/ clocks;
/delete-property/ clocks-names;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
clock-frequency = <25000000>;
};
&dmsc {
mboxes= <&secure_proxy_main 0>,
<&secure_proxy_main 1>,
@@ -62,7 +70,7 @@
&cbass_main {
sysctrler: sysctrler {
compatible = "ti,am654-system-controller";
compatible = "ti,am654-tisci-rproc-r5";
mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&secure_proxy_sa3 0>;
mbox-names = "tx", "rx", "boot_notify";
bootph-pre-ram;
@@ -103,7 +111,6 @@
ti_fs_gp: ti-fs-gp.bin {
filename = "ti-sysfw/ti-fs-firmware-am62x-gp.bin";
type = "blob-ext";
optional;
};
combined_tifs_cfg_gp: combined-tifs-cfg-gp.bin {
filename = "combined-tifs-cfg.bin";

View File

@@ -54,6 +54,14 @@
};
};
&main_timer0 {
/delete-property/ clocks;
/delete-property/ clocks-names;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
clock-frequency = <25000000>;
};
&secure_proxy_sa3 {
/* We require this for boot handshake */
status = "okay";
@@ -61,7 +69,7 @@
&cbass_main {
sysctrler: sysctrler {
compatible = "ti,am654-system-controller";
compatible = "ti,am654-tisci-rproc-r5";
mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&secure_proxy_sa3 0>;
mbox-names = "tx", "rx", "boot_notify";
bootph-pre-ram;

View File

@@ -64,7 +64,7 @@
&cbass_main {
sysctrler: sysctrler {
compatible = "ti,am654-system-controller";
compatible = "ti,am654-tisci-rproc-r5";
mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&secure_proxy_sa3 0>;
mbox-names = "tx", "rx", "boot_notify";
bootph-pre-ram;

View File

@@ -23,7 +23,7 @@
content-sysfw-data = <&combined_tifs_cfg>;
content-sysfw-inner-cert = <&sysfw_inner_cert>;
content-dm-data = <&combined_dm_cfg>;
load = <0x43c00000>;
load = <CONFIG_SPL_TEXT_BASE>;
load-sysfw = <0x40000>;
load-sysfw-data = <0x67000>;
load-dm-data = <0x43c3a800>;
@@ -34,7 +34,6 @@
ti_fs_enc: ti-fs-enc.bin {
filename = "ti-sysfw/ti-fs-firmware-am62x-hs-enc.bin";
type = "blob-ext";
optional;
};
combined_tifs_cfg: combined-tifs-cfg.bin {
filename = "combined-tifs-cfg.bin";
@@ -43,7 +42,6 @@
sysfw_inner_cert: sysfw-inner-cert {
filename = "ti-sysfw/ti-fs-firmware-am62x-hs-cert.bin";
type = "blob-ext";
optional;
};
combined_dm_cfg: combined-dm-cfg.bin {
filename = "combined-dm-cfg.bin";
@@ -69,7 +67,7 @@
content-sysfw-data = <&combined_tifs_cfg_fs>;
content-sysfw-inner-cert = <&sysfw_inner_cert_fs>;
content-dm-data = <&combined_dm_cfg_fs>;
load = <0x43c00000>;
load = <CONFIG_SPL_TEXT_BASE>;
load-sysfw = <0x40000>;
load-sysfw-data = <0x67000>;
load-dm-data = <0x43c3a800>;
@@ -80,7 +78,6 @@
ti_fs_enc_fs: ti-fs-enc.bin {
filename = "ti-sysfw/ti-fs-firmware-am62x-hs-fs-enc.bin";
type = "blob-ext";
optional;
};
combined_tifs_cfg_fs: combined-tifs-cfg.bin {
filename = "combined-tifs-cfg.bin";
@@ -89,7 +86,6 @@
sysfw_inner_cert_fs: sysfw-inner-cert {
filename = "ti-sysfw/ti-fs-firmware-am62x-hs-fs-cert.bin";
type = "blob-ext";
optional;
};
combined_dm_cfg_fs: combined-dm-cfg.bin {
filename = "combined-dm-cfg.bin";
@@ -107,7 +103,7 @@
combined;
dm-data;
content-sbl = <&u_boot_spl_unsigned>;
load = <0x43c00000>;
load = <CONFIG_SPL_TEXT_BASE>;
content-sysfw = <&ti_fs_gp>;
load-sysfw = <0x40000>;
content-sysfw-data = <&combined_tifs_cfg_gp>;
@@ -123,7 +119,6 @@
ti_fs_gp: ti-fs-gp.bin {
filename = "ti-sysfw/ti-fs-firmware-am62x-gp.bin";
type = "blob-ext";
optional;
};
combined_tifs_cfg_gp: combined-tifs-cfg-gp.bin {
filename = "combined-tifs-cfg.bin";
@@ -263,7 +258,6 @@
};
dm: ti-dm {
filename = "ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f";
optional;
};
};
@@ -391,7 +385,6 @@
dm {
ti-dm {
filename = "ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f";
optional;
};
};

View File

@@ -53,7 +53,7 @@
&cbass_main {
sysctrler: sysctrler {
compatible = "ti,am654-system-controller";
compatible = "ti,am654-tisci-rproc-r5";
mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&secure_proxy_sa3 0>;
mbox-names = "tx", "rx", "boot_notify";
bootph-pre-ram;
@@ -69,6 +69,14 @@
ti,secure-host;
};
&main_timer0 {
/delete-property/ clocks;
/delete-property/ clocks-names;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
clock-frequency = <25000000>;
};
&secure_proxy_sa3 {
/* We require this for boot handshake */
status = "okay";

View File

@@ -23,7 +23,7 @@
content-sysfw-data = <&combined_tifs_cfg>;
content-sysfw-inner-cert = <&sysfw_inner_cert>;
content-dm-data = <&combined_dm_cfg>;
load = <0x43c00000>;
load = <CONFIG_SPL_TEXT_BASE>;
load-sysfw = <0x40000>;
load-sysfw-data = <0x67000>;
load-dm-data = <0x43c3a800>;
@@ -34,7 +34,6 @@
ti_fs_enc: ti-fs-enc.bin {
filename = "ti-sysfw/ti-fs-firmware-am62x-hs-enc.bin";
type = "blob-ext";
optional;
};
combined_tifs_cfg: combined-tifs-cfg.bin {
filename = "combined-tifs-cfg.bin";
@@ -43,7 +42,6 @@
sysfw_inner_cert: sysfw-inner-cert {
filename = "ti-sysfw/ti-fs-firmware-am62x-hs-cert.bin";
type = "blob-ext";
optional;
};
combined_dm_cfg: combined-dm-cfg.bin {
filename = "combined-dm-cfg.bin";
@@ -69,7 +67,7 @@
content-sysfw-data = <&combined_tifs_cfg_fs>;
content-sysfw-inner-cert = <&sysfw_inner_cert_fs>;
content-dm-data = <&combined_dm_cfg_fs>;
load = <0x43c00000>;
load = <CONFIG_SPL_TEXT_BASE>;
load-sysfw = <0x40000>;
load-sysfw-data = <0x67000>;
load-dm-data = <0x43c3a800>;
@@ -80,7 +78,6 @@
ti_fs_enc_fs: ti-fs-enc.bin {
filename = "ti-sysfw/ti-fs-firmware-am62x-hs-fs-enc.bin";
type = "blob-ext";
optional;
};
combined_tifs_cfg_fs: combined-tifs-cfg.bin {
filename = "combined-tifs-cfg.bin";
@@ -89,7 +86,6 @@
sysfw_inner_cert_fs: sysfw-inner-cert {
filename = "ti-sysfw/ti-fs-firmware-am62x-hs-fs-cert.bin";
type = "blob-ext";
optional;
};
combined_dm_cfg_fs: combined-dm-cfg.bin {
filename = "combined-dm-cfg.bin";
@@ -107,7 +103,7 @@
combined;
dm-data;
content-sbl = <&u_boot_spl_unsigned>;
load = <0x43c00000>;
load = <CONFIG_SPL_TEXT_BASE>;
content-sysfw = <&ti_fs_gp>;
load-sysfw = <0x40000>;
content-sysfw-data = <&combined_tifs_cfg_gp>;
@@ -123,7 +119,6 @@
ti_fs_gp: ti-fs-gp.bin {
filename = "ti-sysfw/ti-fs-firmware-am62x-gp.bin";
type = "blob-ext";
optional;
};
combined_tifs_cfg_gp: combined-tifs-cfg-gp.bin {
filename = "combined-tifs-cfg.bin";

View File

@@ -12,10 +12,6 @@
eeprom2 = &eeprom_display_adapter;
};
chosen {
tick-timer = &main_timer0;
};
memory@80000000 {
bootph-all;
};
@@ -25,10 +21,6 @@
};
};
&main_timer0 {
clock-frequency = <25000000>;
};
&main_bcdma {
reg = <0x00 0x485c0100 0x00 0x100>,
<0x00 0x4c000000 0x00 0x20000>,

View File

@@ -30,7 +30,7 @@
content-sysfw-data = <&combined_tifs_cfg>;
content-sysfw-inner-cert = <&sysfw_inner_cert>;
content-dm-data = <&combined_dm_cfg>;
load = <0x43c00000>;
load = <CONFIG_SPL_TEXT_BASE>;
load-sysfw = <0x40000>;
load-sysfw-data = <0x67000>;
load-dm-data = <0x43c3a800>;
@@ -41,7 +41,6 @@
ti_fs_enc: ti-fs-enc.bin {
filename = "ti-sysfw/ti-fs-firmware-am62ax-hs-enc.bin";
type = "blob-ext";
optional;
};
combined_tifs_cfg: combined-tifs-cfg.bin {
filename = "combined-tifs-cfg.bin";
@@ -50,7 +49,6 @@
sysfw_inner_cert: sysfw-inner-cert {
filename = "ti-sysfw/ti-fs-firmware-am62ax-hs-cert.bin";
type = "blob-ext";
optional;
};
combined_dm_cfg: combined-dm-cfg.bin {
filename = "combined-dm-cfg.bin";
@@ -76,7 +74,7 @@
content-sysfw-data = <&combined_tifs_cfg_fs>;
content-sysfw-inner-cert = <&sysfw_inner_cert_fs>;
content-dm-data = <&combined_dm_cfg_fs>;
load = <0x43c00000>;
load = <CONFIG_SPL_TEXT_BASE>;
load-sysfw = <0x40000>;
load-sysfw-data = <0x67000>;
load-dm-data = <0x43c3a800>;
@@ -87,7 +85,6 @@
ti_fs_enc_fs: ti-fs-enc.bin {
filename = "ti-sysfw/ti-fs-firmware-am62ax-hs-fs-enc.bin";
type = "blob-ext";
optional;
};
combined_tifs_cfg_fs: combined-tifs-cfg.bin {
filename = "combined-tifs-cfg.bin";
@@ -96,7 +93,6 @@
sysfw_inner_cert_fs: sysfw-inner-cert {
filename = "ti-sysfw/ti-fs-firmware-am62ax-hs-fs-cert.bin";
type = "blob-ext";
optional;
};
combined_dm_cfg_fs: combined-dm-cfg.bin {
filename = "combined-dm-cfg.bin";
@@ -105,44 +101,6 @@
};
};
&binman {
tiboot3-am62ax-gp-phycore-som.bin {
filename = "tiboot3-am62ax-gp-phycore-som.bin";
ti-secure-rom {
content = <&u_boot_spl_unsigned>, <&ti_fs_gp>,
<&combined_tifs_cfg_gp>, <&combined_dm_cfg_gp>;
combined;
dm-data;
content-sbl = <&u_boot_spl_unsigned>;
load = <0x43c00000>;
content-sysfw = <&ti_fs_gp>;
load-sysfw = <0x40000>;
content-sysfw-data = <&combined_tifs_cfg_gp>;
load-sysfw-data = <0x67000>;
content-dm-data = <&combined_dm_cfg_gp>;
load-dm-data = <0x43c3a800>;
sw-rev = <1>;
keyfile = "ti-degenerate-key.pem";
};
u_boot_spl_unsigned: u-boot-spl {
no-expanded;
};
ti_fs_gp: ti-fs-gp.bin {
filename = "ti-sysfw/ti-fs-firmware-am62ax-gp.bin";
type = "blob-ext";
optional;
};
combined_tifs_cfg_gp: combined-tifs-cfg-gp.bin {
filename = "combined-tifs-cfg.bin";
type = "blob-ext";
};
combined_dm_cfg_gp: combined-dm-cfg-gp.bin {
filename = "combined-dm-cfg.bin";
type = "blob-ext";
};
};
};
#include "k3-binman-capsule-r5.dtsi"
&capsule_tiboot3 {
@@ -202,23 +160,6 @@
};
tifsstub-gp {
filename = "tifsstub.bin_gp";
ti-secure-rom {
content = <&tifsstub_gp>;
core = "secure";
load = <0x60000>;
sw-rev = <CONFIG_K3_X509_SWRV>;
keyfile = "ti-degenerate-key.pem";
tifsstub;
};
tifsstub_gp: tifsstub-gp.bin {
filename = "ti-sysfw/ti-fs-stub-firmware-am62ax-gp.bin";
type = "blob-ext";
optional;
};
};
ti-spl {
insert-template = <&ti_spl_template>;
@@ -250,18 +191,6 @@
};
};
tifsstub-gp {
description = "TIFSSTUB";
type = "firmware";
arch = "arm32";
compression = "none";
os = "tifsstub-gp";
load = <0x9ca00000>;
entry = <0x9ca00000>;
blob-ext {
filename = "tifsstub.bin_gp";
};
};
dm {
ti-secure {
content = <&dm>;
@@ -269,7 +198,6 @@
};
dm: ti-dm {
filename = "ti-dm/am62axx/ipc_echo_testb_mcu1_0_release_strip.xer5f";
optional;
};
};
@@ -295,7 +223,7 @@
description = "k3-am62a7-phyboard-lyra-rdk";
firmware = "atf";
loadables = "tee", "dm", "spl",
"tifsstub-hs", "tifsstub-fs", "tifsstub-gp";
"tifsstub-hs", "tifsstub-fs";
fdt = "fdt-0";
};
};
@@ -409,121 +337,6 @@
};
};
&binman {
ti-spl_unsigned {
insert-template = <&ti_spl_unsigned_template>;
fit {
images {
tifsstub-hs {
description = "tifsstub";
type = "firmware";
arch = "arm32";
compression = "none";
os = "tifsstub-hs";
load = <0x9ca00000>;
entry = <0x9ca00000>;
blob-ext {
filename = "tifsstub.bin_hs";
};
};
tifsstub-fs {
description = "tifsstub";
type = "firmware";
arch = "arm32";
compression = "none";
os = "tifsstub-fs";
load = <0x9ca00000>;
entry = <0x9ca00000>;
blob-ext {
filename = "tifsstub.bin_fs";
};
};
tifsstub-gp {
description = "tifsstub";
type = "firmware";
arch = "arm32";
compression = "none";
os = "tifsstub-gp";
load = <0x9ca00000>;
entry = <0x9ca00000>;
blob-ext {
filename = "tifsstub.bin_gp";
};
};
dm {
ti-dm {
filename = "ti-dm/am62axx/ipc_echo_testb_mcu1_0_release_strip.xer5f";
optional;
};
};
fdt-0 {
description = "k3-am62a7-phyboard-lyra-rdk";
type = "flat_dt";
arch = "arm";
compression = "none";
spl_am62a7_phyboard_lyra_dtb_unsigned: blob {
filename = SPL_AM62A7_PHYBOARD_LYRA_DTB;
};
};
};
configurations {
default = "conf-0";
conf-0 {
description = "k3-am62a7-phyboard-lyra-rdk";
firmware = "atf";
loadables = "tee", "dm", "spl",
"tifsstub-hs", "tifsstub-fs", "tifsstub-gp";
fdt = "fdt-0";
};
};
};
};
};
&binman {
u-boot_unsigned {
insert-template = <&u_boot_unsigned_template>;
fit {
images {
uboot {
description = "U-Boot for AM62Ax board";
};
fdt-0 {
description = "k3-am62a7-phyboard-lyra-rdk";
type = "flat_dt";
arch = "arm";
compression = "none";
blob {
filename = AM62A7_PHYBOARD_LYRA_DTB;
};
hash {
algo = "crc32";
};
};
};
configurations {
default = "conf-0";
conf-0 {
description = "k3-am62a7-phyboard-lyra-rdk";
firmware = "uboot";
loadables = "uboot";
fdt = "fdt-0";
};
};
};
};
};
#include "k3-binman-capsule.dtsi"
&capsule_tispl {

View File

@@ -27,7 +27,7 @@
content-sysfw-data = <&combined_tifs_cfg>;
content-sysfw-inner-cert = <&sysfw_inner_cert>;
content-dm-data = <&combined_dm_cfg>;
load = <0x43c00000>;
load = <CONFIG_SPL_TEXT_BASE>;
load-sysfw = <0x40000>;
load-sysfw-data = <0x67000>;
load-dm-data = <0x43c3a800>;
@@ -38,7 +38,6 @@
ti_fs_enc: ti-fs-enc.bin {
filename = "ti-sysfw/ti-fs-firmware-am62ax-hs-enc.bin";
type = "blob-ext";
optional;
};
combined_tifs_cfg: combined-tifs-cfg.bin {
filename = "combined-tifs-cfg.bin";
@@ -47,7 +46,6 @@
sysfw_inner_cert: sysfw-inner-cert {
filename = "ti-sysfw/ti-fs-firmware-am62ax-hs-cert.bin";
type = "blob-ext";
optional;
};
combined_dm_cfg: combined-dm-cfg.bin {
filename = "combined-dm-cfg.bin";
@@ -73,7 +71,7 @@
content-sysfw-data = <&combined_tifs_cfg_fs>;
content-sysfw-inner-cert = <&sysfw_inner_cert_fs>;
content-dm-data = <&combined_dm_cfg_fs>;
load = <0x43c00000>;
load = <CONFIG_SPL_TEXT_BASE>;
load-sysfw = <0x40000>;
load-sysfw-data = <0x67000>;
load-dm-data = <0x43c3a800>;
@@ -84,7 +82,6 @@
ti_fs_enc_fs: ti-fs-enc.bin {
filename = "ti-sysfw/ti-fs-firmware-am62ax-hs-fs-enc.bin";
type = "blob-ext";
optional;
};
combined_tifs_cfg_fs: combined-tifs-cfg.bin {
filename = "combined-tifs-cfg.bin";
@@ -93,7 +90,6 @@
sysfw_inner_cert_fs: sysfw-inner-cert {
filename = "ti-sysfw/ti-fs-firmware-am62ax-hs-fs-cert.bin";
type = "blob-ext";
optional;
};
combined_dm_cfg_fs: combined-dm-cfg.bin {
filename = "combined-dm-cfg.bin";
@@ -102,44 +98,6 @@
};
};
&binman {
tiboot3-am62ax-gp-evm.bin {
filename = "tiboot3-am62ax-gp-evm.bin";
ti-secure-rom {
content = <&u_boot_spl_unsigned>, <&ti_fs_gp>,
<&combined_tifs_cfg_gp>, <&combined_dm_cfg_gp>;
combined;
dm-data;
content-sbl = <&u_boot_spl_unsigned>;
load = <0x43c00000>;
content-sysfw = <&ti_fs_gp>;
load-sysfw = <0x40000>;
content-sysfw-data = <&combined_tifs_cfg_gp>;
load-sysfw-data = <0x67000>;
content-dm-data = <&combined_dm_cfg_gp>;
load-dm-data = <0x43c3a800>;
sw-rev = <1>;
keyfile = "ti-degenerate-key.pem";
};
u_boot_spl_unsigned: u-boot-spl {
no-expanded;
};
ti_fs_gp: ti-fs-gp.bin {
filename = "ti-sysfw/ti-fs-firmware-am62ax-gp.bin";
type = "blob-ext";
optional;
};
combined_tifs_cfg_gp: combined-tifs-cfg-gp.bin {
filename = "combined-tifs-cfg.bin";
type = "blob-ext";
};
combined_dm_cfg_gp: combined-dm-cfg-gp.bin {
filename = "combined-dm-cfg.bin";
type = "blob-ext";
};
};
};
#endif
#ifdef CONFIG_TARGET_AM62A7_A53_EVM
@@ -186,23 +144,6 @@
};
tifsstub-gp {
filename = "tifsstub.bin_gp";
ti-secure-rom {
content = <&tifsstub_gp>;
core = "secure";
load = <0x60000>;
sw-rev = <CONFIG_K3_X509_SWRV>;
keyfile = "ti-degenerate-key.pem";
tifsstub;
};
tifsstub_gp: tifsstub-gp.bin {
filename = "ti-sysfw/ti-fs-stub-firmware-am62ax-gp.bin";
type = "blob-ext";
optional;
};
};
ti-spl {
insert-template = <&ti_spl_template>;
@@ -234,18 +175,6 @@
};
};
tifsstub-gp {
description = "TIFSSTUB";
type = "firmware";
arch = "arm32";
compression = "none";
os = "tifsstub-gp";
load = <0x9ca00000>;
entry = <0x9ca00000>;
blob-ext {
filename = "tifsstub.bin_gp";
};
};
dm {
ti-secure {
content = <&dm>;
@@ -253,7 +182,6 @@
};
dm: ti-dm {
filename = "ti-dm/am62axx/ipc_echo_testb_mcu1_0_release_strip.xer5f";
optional;
};
};
@@ -281,7 +209,7 @@
description = "k3-am62a7-sk";
firmware = "atf";
loadables = "tee", "dm", "spl",
"tifsstub-hs", "tifsstub-fs", "tifsstub-gp";
"tifsstub-hs", "tifsstub-fs";
fdt = "fdt-0";
};
};
@@ -332,118 +260,4 @@
};
};
&binman {
ti-spl_unsigned {
insert-template = <&ti_spl_unsigned_template>;
fit {
images {
tifsstub-hs {
description = "tifsstub";
type = "firmware";
arch = "arm32";
compression = "none";
os = "tifsstub-hs";
load = <0x9ca00000>;
entry = <0x9ca00000>;
blob-ext {
filename = "tifsstub.bin_hs";
};
};
tifsstub-fs {
description = "tifsstub";
type = "firmware";
arch = "arm32";
compression = "none";
os = "tifsstub-fs";
load = <0x9ca00000>;
entry = <0x9ca00000>;
blob-ext {
filename = "tifsstub.bin_fs";
};
};
tifsstub-gp {
description = "tifsstub";
type = "firmware";
arch = "arm32";
compression = "none";
os = "tifsstub-gp";
load = <0x9ca00000>;
entry = <0x9ca00000>;
blob-ext {
filename = "tifsstub.bin_gp";
};
};
dm {
ti-dm {
filename = "ti-dm/am62axx/ipc_echo_testb_mcu1_0_release_strip.xer5f";
optional;
};
};
fdt-0 {
description = "k3-am62a7-sk";
type = "flat_dt";
arch = "arm";
compression = "none";
blob {
filename = SPL_AM62A7_SK_DTB;
};
};
};
configurations {
default = "conf-0";
conf-0 {
description = "k3-am62a7-sk";
firmware = "atf";
loadables = "tee", "dm", "spl",
"tifsstub-hs", "tifsstub-fs", "tifsstub-gp";
fdt = "fdt-0";
};
};
};
};
};
&binman {
u-boot_unsigned {
insert-template = <&u_boot_unsigned_template>;
fit {
images {
uboot {
description = "U-Boot for AM62Ax Board";
};
fdt-0 {
description = "k3-am62a7-sk";
type = "flat_dt";
arch = "arm";
compression = "none";
blob {
filename = AM62A7_SK_DTB;
};
hash {
algo = "crc32";
};
};
};
configurations {
default = "conf-0";
conf-0 {
description = "k3-am62a7-sk";
firmware = "uboot";
loadables = "uboot";
fdt = "fdt-0";
};
};
};
};
};
#endif

View File

@@ -13,7 +13,6 @@
/ {
chosen {
stdout-path = "serial2:115200n8";
tick-timer = &main_timer0;
};
aliases {
@@ -157,10 +156,6 @@
bootph-all;
};
&main_timer0 {
bootph-all;
};
&main_uart0 {
bootph-all;
};

View File

@@ -70,7 +70,7 @@
};
sysctrler: sysctrler {
compatible = "ti,am654-system-controller";
compatible = "ti,am654-tisci-rproc-r5";
mboxes= <&secure_proxy_main 1>,
<&secure_proxy_main 0>,
<&sa3_secproxy 0>;
@@ -88,6 +88,15 @@
ti,secure-host;
};
&main_timer0 {
/delete-property/ clocks;
/delete-property/ clocks-names;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
clock-frequency = <25000000>;
bootph-pre-ram;
};
&main_bcdma {
ti,sci = <&dm_tifs>;
};

View File

@@ -63,7 +63,7 @@
&cbass_main {
sysctrler: sysctrler {
compatible = "ti,am654-system-controller";
compatible = "ti,am654-tisci-rproc-r5";
mboxes= <&secure_proxy_main 1>,
<&secure_proxy_main 0>,
<&secure_proxy_sa3 0>;

View File

@@ -25,7 +25,7 @@
content-sysfw-data = <&combined_tifs_cfg_fs>;
content-sysfw-inner-cert = <&sysfw_inner_cert_fs>;
content-dm-data = <&combined_dm_cfg_fs>;
load = <0x43c00000>;
load = <CONFIG_SPL_TEXT_BASE>;
load-sysfw = <0x40000>;
load-sysfw-data = <0x67000>;
load-dm-data = <0x43c4a800>;
@@ -38,7 +38,6 @@
ti_fs_enc_fs: ti-fs-enc.bin {
filename = "ti-sysfw/ti-fs-firmware-am62px-hs-fs-enc.bin";
type = "blob-ext";
optional;
};
combined_tifs_cfg_fs: combined-tifs-cfg.bin {
@@ -49,7 +48,6 @@
sysfw_inner_cert_fs: sysfw-inner-cert {
filename = "ti-sysfw/ti-fs-firmware-am62px-hs-fs-cert.bin";
type = "blob-ext";
optional;
};
combined_dm_cfg_fs: combined-dm-cfg.bin {
@@ -74,7 +72,7 @@
content-sysfw-data = <&combined_tifs_cfg_hs>;
content-sysfw-inner-cert = <&sysfw_inner_cert_hs>;
content-dm-data = <&combined_dm_cfg_hs>;
load = <0x43c00000>;
load = <CONFIG_SPL_TEXT_BASE>;
load-sysfw = <0x40000>;
load-sysfw-data = <0x67000>;
load-dm-data = <0x43c4a800>;
@@ -87,7 +85,6 @@
ti_fs_enc_hs: ti-fs-enc.bin {
filename = "ti-sysfw/ti-fs-firmware-am62px-hs-enc.bin";
type = "blob-ext";
optional;
};
combined_tifs_cfg_hs: combined-tifs-cfg.bin {
@@ -98,7 +95,6 @@
sysfw_inner_cert_hs: sysfw-inner-cert {
filename = "ti-sysfw/ti-fs-firmware-am62px-hs-cert.bin";
type = "blob-ext";
optional;
};
combined_dm_cfg_hs: combined-dm-cfg.bin {
@@ -203,7 +199,6 @@
dm: ti-dm {
filename = "ti-dm/am62pxx/ipc_echo_testb_mcu1_0_release_strip.xer5f";
optional;
};
};

View File

@@ -0,0 +1,243 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2025 Toradex
*
* Common dtsi for Verdin AM62P SoM on Development carrier board
*
* https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62p
* https://www.toradex.com/products/carrier-board/verdin-development-board-kit
*/
/ {
aliases {
eeprom1 = &carrier_eeprom;
};
sound {
compatible = "simple-audio-card";
simple-audio-card,bitclock-master = <&codec_dai>;
simple-audio-card,format = "i2s";
simple-audio-card,frame-master = <&codec_dai>;
simple-audio-card,mclk-fs = <256>;
simple-audio-card,name = "verdin-nau8822";
simple-audio-card,routing =
"Headphones", "LHP",
"Headphones", "RHP",
"Speaker", "LSPK",
"Speaker", "RSPK",
"Line Out", "AUXOUT1",
"Line Out", "AUXOUT2",
"LAUX", "Line In",
"RAUX", "Line In",
"LMICP", "Mic In",
"RMICP", "Mic In";
simple-audio-card,widgets =
"Headphones", "Headphones",
"Line Out", "Line Out",
"Speaker", "Speaker",
"Microphone", "Mic In",
"Line", "Line In";
codec_dai: simple-audio-card,codec {
sound-dai = <&nau8822_1a>;
};
simple-audio-card,cpu {
sound-dai = <&mcasp0>;
};
};
};
/* Verdin ETHs */
&cpsw3g {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rgmii1>, <&pinctrl_rgmii2>;
status = "okay";
};
/* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */
&cpsw3g_mdio {
status = "okay";
carrier_eth_phy: ethernet-phy@7 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eth2_rgmii_int>;
interrupt-parent = <&main_gpio0>;
interrupts = <42 IRQ_TYPE_EDGE_FALLING>;
micrel,led-mode = <0>;
};
};
/* Verdin ETH_1 (On-module PHY) */
&cpsw_port1 {
status = "okay";
};
/* Verdin ETH_2_RGMII */
&cpsw_port2 {
phy-handle = <&carrier_eth_phy>;
phy-mode = "rgmii-rxid";
status = "okay";
};
/* Verdin PWM_3_DSI */
&epwm0 {
status = "okay";
};
/* Verdin PWM_1, PWM_2 */
&epwm2 {
status = "okay";
};
&main_gpio0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie_1_reset>,
<&pinctrl_gpio_5>,
<&pinctrl_gpio_6>,
<&pinctrl_gpio_7>,
<&pinctrl_gpio_8>;
};
/* Verdin I2C_1 */
&main_i2c0 {
status = "okay";
nau8822_1a: audio-codec@1a {
compatible = "nuvoton,nau8822";
reg = <0x1a>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2s1_mclk>;
#sound-dai-cells = <0>;
};
carrier_gpio_expander: gpio@21 {
compatible = "nxp,pcal6416";
reg = <0x21>;
#gpio-cells = <2>;
gpio-controller;
};
/* Current measurement into module VCC */
hwmon@40 {
compatible = "ti,ina219";
reg = <0x40>;
shunt-resistor = <10000>;
};
temperature-sensor@4f {
compatible = "ti,tmp75c";
reg = <0x4f>;
};
carrier_eeprom: eeprom@57 {
compatible = "st,24c02", "atmel,24c02";
reg = <0x57>;
pagesize = <16>;
};
};
/* Verdin I2C_2_DSI */
&main_i2c1 {
status = "okay";
};
/* Verdin I2C_4_CSI */
&main_i2c3 {
status = "okay";
};
/* Verdin CAN_1 */
&main_mcan0 {
status = "okay";
};
/* Verdin SPI_1 */
&main_spi1 {
status = "okay";
};
/* Verdin UART_3, used as the Linux console */
&main_uart0 {
status = "okay";
};
/* Verdin UART_1, connector X50 through RS485 transceiver */
&main_uart1 {
rs485-rx-during-tx;
linux,rs485-enabled-at-boot-time;
status = "okay";
};
/* Verdin I2S_1 */
&mcasp0 {
status = "okay";
};
&mcu_gpio0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_1>,
<&pinctrl_gpio_2>,
<&pinctrl_gpio_3>,
<&pinctrl_gpio_4>;
};
/* Verdin I2C_3_HDMI */
&mcu_i2c0 {
status = "okay";
};
/* Verdin CAN_2 */
&mcu_mcan0 {
status = "okay";
};
/* Verdin UART_4 */
&mcu_uart0 {
status = "okay";
};
/* Verdin QSPI_1 */
&ospi0 {
status = "okay";
};
/* Verdin SD_1 */
&sdhci1 {
status = "okay";
};
/* Verdin USB_1 */
&usbss0 {
status = "okay";
};
&usb0 {
status = "okay";
};
/* Verdin USB_2 */
&usbss1 {
status = "okay";
};
&usb1 {
status = "okay";
};
/* Verdin CTRL_WAKE1_MICO# */
&verdin_gpio_keys {
status = "okay";
};
/* Verdin PCIE_1_RESET# */
&verdin_pcie_1_reset_hog {
status = "okay";
};
/* Verdin UART_2 */
&wkup_uart0 {
status = "okay";
};

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